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-rw-r--r--MAINTAINERS8
-rw-r--r--arch/powerpc/Kconfig2
-rw-r--r--arch/powerpc/boot/dts/fsl/kmcent2.dts303
-rw-r--r--arch/powerpc/boot/dts/fsl/kmcoge4.dts4
-rw-r--r--arch/powerpc/configs/85xx/kmp204x_defconfig220
-rw-r--r--arch/powerpc/configs/pseries_defconfig1
-rw-r--r--arch/powerpc/include/asm/bitops.h28
-rw-r--r--arch/powerpc/include/asm/pnv-pci.h2
-rw-r--r--arch/powerpc/include/asm/ppc_asm.h1
-rw-r--r--arch/powerpc/include/asm/processor.h2
-rw-r--r--arch/powerpc/include/asm/prom.h1
-rw-r--r--arch/powerpc/include/asm/reg.h2
-rw-r--r--arch/powerpc/include/asm/reg_8xx.h11
-rw-r--r--arch/powerpc/include/asm/rtas.h2
-rw-r--r--arch/powerpc/kernel/asm-offsets.c772
-rw-r--r--arch/powerpc/kernel/cpu_setup_power.S4
-rw-r--r--arch/powerpc/kernel/cputable.c17
-rw-r--r--arch/powerpc/kernel/entry_32.S19
-rw-r--r--arch/powerpc/kernel/head_32.S3
-rw-r--r--arch/powerpc/kernel/head_8xx.S72
-rw-r--r--arch/powerpc/kernel/hw_breakpoint.c6
-rw-r--r--arch/powerpc/kernel/optprobes_head.S7
-rw-r--r--arch/powerpc/kernel/pci-common.c10
-rw-r--r--arch/powerpc/kernel/process.c22
-rw-r--r--arch/powerpc/kernel/prom_init.c2
-rw-r--r--arch/powerpc/kernel/setup_64.c12
-rw-r--r--arch/powerpc/kernel/time.c2
-rw-r--r--arch/powerpc/mm/pgtable.c4
-rw-r--r--arch/powerpc/mm/slb_low.S24
-rw-r--r--arch/powerpc/perf/8xx-pmu.c173
-rw-r--r--arch/powerpc/perf/Makefile2
-rw-r--r--arch/powerpc/perf/core-book3s.c38
-rw-r--r--arch/powerpc/perf/isa207-common.c94
-rw-r--r--arch/powerpc/perf/isa207-common.h7
-rw-r--r--arch/powerpc/perf/power8-pmu.c35
-rw-r--r--arch/powerpc/perf/power9-events-list.h3
-rw-r--r--arch/powerpc/perf/power9-pmu.c47
-rw-r--r--arch/powerpc/platforms/85xx/Makefile1
-rw-r--r--arch/powerpc/platforms/85xx/corenet_generic.c1
-rw-r--r--arch/powerpc/platforms/85xx/t1042rdb_diu.c152
-rw-r--r--arch/powerpc/platforms/Kconfig.cputype7
-rw-r--r--arch/powerpc/platforms/cell/spufs/file.c65
-rw-r--r--arch/powerpc/platforms/cell/spufs/spufs.h3
-rw-r--r--arch/powerpc/platforms/powernv/Kconfig3
-rw-r--r--arch/powerpc/platforms/powernv/pci-ioda.c2
-rw-r--r--arch/powerpc/platforms/pseries/dlpar.c38
-rw-r--r--arch/powerpc/platforms/pseries/hotplug-memory.c272
-rw-r--r--arch/powerpc/xmon/ppc-dis.c260
-rw-r--r--arch/powerpc/xmon/ppc-opc.c8999
-rw-r--r--arch/powerpc/xmon/ppc.h268
-rw-r--r--arch/powerpc/xmon/xmon.c58
-rw-r--r--drivers/misc/cxl/cxl.h5
-rw-r--r--drivers/misc/cxl/main.c3
-rw-r--r--drivers/misc/cxl/pci.c11
-rw-r--r--drivers/misc/cxl/vphb.c18
-rw-r--r--drivers/pci/hotplug/pnv_php.c81
56 files changed, 7867 insertions, 4342 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index 846f97aa3508..00018356f4a5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7483,18 +7483,24 @@ L: linuxppc-dev@lists.ozlabs.org
7483Q: http://patchwork.ozlabs.org/project/linuxppc-dev/list/ 7483Q: http://patchwork.ozlabs.org/project/linuxppc-dev/list/
7484T: git git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git 7484T: git git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git
7485S: Supported 7485S: Supported
7486F: Documentation/ABI/stable/sysfs-firmware-opal-*
7487F: Documentation/devicetree/bindings/powerpc/opal/
7488F: Documentation/devicetree/bindings/rtc/rtc-opal.txt
7489F: Documentation/devicetree/bindings/i2c/i2c-opal.txt
7486F: Documentation/powerpc/ 7490F: Documentation/powerpc/
7487F: arch/powerpc/ 7491F: arch/powerpc/
7488F: drivers/char/tpm/tpm_ibmvtpm* 7492F: drivers/char/tpm/tpm_ibmvtpm*
7489F: drivers/crypto/nx/ 7493F: drivers/crypto/nx/
7490F: drivers/crypto/vmx/ 7494F: drivers/crypto/vmx/
7495F: drivers/i2c/busses/i2c-opal.c
7491F: drivers/net/ethernet/ibm/ibmveth.* 7496F: drivers/net/ethernet/ibm/ibmveth.*
7492F: drivers/net/ethernet/ibm/ibmvnic.* 7497F: drivers/net/ethernet/ibm/ibmvnic.*
7493F: drivers/pci/hotplug/pnv_php.c 7498F: drivers/pci/hotplug/pnv_php.c
7494F: drivers/pci/hotplug/rpa* 7499F: drivers/pci/hotplug/rpa*
7500F: drivers/rtc/rtc-opal.c
7495F: drivers/scsi/ibmvscsi/ 7501F: drivers/scsi/ibmvscsi/
7502F: drivers/tty/hvc/hvc_opal.c
7496F: tools/testing/selftests/powerpc 7503F: tools/testing/selftests/powerpc
7497N: opal
7498N: /pmac 7504N: /pmac
7499N: powermac 7505N: powermac
7500N: powernv 7506N: powernv
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 8582121d7a45..494091762bd7 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -115,7 +115,7 @@ config PPC
115 select HAVE_PERF_REGS 115 select HAVE_PERF_REGS
116 select HAVE_PERF_USER_STACK_DUMP 116 select HAVE_PERF_USER_STACK_DUMP
117 select HAVE_REGS_AND_STACK_ACCESS_API 117 select HAVE_REGS_AND_STACK_ACCESS_API
118 select HAVE_HW_BREAKPOINT if PERF_EVENTS && PPC_BOOK3S_64 118 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (PPC_BOOK3S || PPC_8xx)
119 select ARCH_WANT_IPC_PARSE_VERSION 119 select ARCH_WANT_IPC_PARSE_VERSION
120 select SPARSE_IRQ 120 select SPARSE_IRQ
121 select IRQ_DOMAIN 121 select IRQ_DOMAIN
diff --git a/arch/powerpc/boot/dts/fsl/kmcent2.dts b/arch/powerpc/boot/dts/fsl/kmcent2.dts
new file mode 100644
index 000000000000..47afa438602e
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/kmcent2.dts
@@ -0,0 +1,303 @@
1/*
2 * Keymile kmcent2 Device Tree Source, based on T1040RDB DTS
3 *
4 * (C) Copyright 2016
5 * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
6 *
7 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15/include/ "t104xsi-pre.dtsi"
16
17/ {
18 model = "keymile,kmcent2";
19 compatible = "keymile,kmcent2";
20
21 aliases {
22 front_phy = &front_phy;
23 };
24
25 reserved-memory {
26 #address-cells = <2>;
27 #size-cells = <2>;
28 ranges;
29
30 bman_fbpr: bman-fbpr {
31 size = <0 0x1000000>;
32 alignment = <0 0x1000000>;
33 };
34 qman_fqd: qman-fqd {
35 size = <0 0x400000>;
36 alignment = <0 0x400000>;
37 };
38 qman_pfdr: qman-pfdr {
39 size = <0 0x2000000>;
40 alignment = <0 0x2000000>;
41 };
42 };
43
44 ifc: localbus@ffe124000 {
45 reg = <0xf 0xfe124000 0 0x2000>;
46 ranges = <0 0 0xf 0xe8000000 0x04000000
47 1 0 0xf 0xfa000000 0x00010000
48 2 0 0xf 0xfb000000 0x00010000
49 4 0 0xf 0xc0000000 0x08000000
50 6 0 0xf 0xd0000000 0x08000000
51 7 0 0xf 0xd8000000 0x08000000>;
52
53 nor@0,0 {
54 #address-cells = <1>;
55 #size-cells = <1>;
56 compatible = "cfi-flash";
57 reg = <0x0 0x0 0x04000000>;
58 bank-width = <2>;
59 device-width = <2>;
60 };
61
62 nand@1,0 {
63 #address-cells = <1>;
64 #size-cells = <1>;
65 compatible = "fsl,ifc-nand";
66 reg = <0x1 0x0 0x10000>;
67 };
68
69 board-control@2,0 {
70 compatible = "keymile,qriox";
71 reg = <0x2 0x0 0x80>;
72 };
73
74 chassis-mgmt@6,0 {
75 compatible = "keymile,bfticu";
76 reg = <6 0 0x100>;
77 interrupt-controller;
78 interrupt-parent = <&mpic>;
79 interrupts = <11 1 0 0>;
80 #interrupt-cells = <1>;
81 };
82
83 };
84
85 memory {
86 device_type = "memory";
87 };
88
89 dcsr: dcsr@f00000000 {
90 ranges = <0x00000000 0xf 0x00000000 0x01072000>;
91 };
92
93 bportals: bman-portals@ff4000000 {
94 ranges = <0x0 0xf 0xf4000000 0x2000000>;
95 };
96
97 qportals: qman-portals@ff6000000 {
98 ranges = <0x0 0xf 0xf6000000 0x2000000>;
99 };
100
101 soc: soc@ffe000000 {
102 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
103 reg = <0xf 0xfe000000 0 0x00001000>;
104
105 spi@110000 {
106 network-clock@1 {
107 compatible = "zarlink,zl30364";
108 reg = <1>;
109 spi-max-frequency = <1000000>;
110 };
111 };
112
113 sdhc@114000 {
114 status = "disabled";
115 };
116
117 i2c@118000 {
118 clock-frequency = <100000>;
119
120 mux@70 {
121 compatible = "nxp,pca9547";
122 reg = <0x70>;
123 #address-cells = <1>;
124 #size-cells = <0>;
125 i2c-mux-idle-disconnect;
126
127 i2c@0 {
128 reg = <0>;
129 #address-cells = <1>;
130 #size-cells = <0>;
131
132 eeprom@54 {
133 compatible = "24c02";
134 reg = <0x54>;
135 pagesize = <2>;
136 read-only;
137 label = "ddr3-spd";
138 };
139 };
140
141 i2c@7 {
142 reg = <7>;
143 #address-cells = <1>;
144 #size-cells = <0>;
145
146 temp-sensor@48 {
147 compatible = "national,lm75";
148 reg = <0x48>;
149 label = "SENSOR_0";
150 };
151 temp-sensor@4a {
152 compatible = "national,lm75";
153 reg = <0x4a>;
154 label = "SENSOR_2";
155 };
156 temp-sensor@4b {
157 compatible = "national,lm75";
158 reg = <0x4b>;
159 label = "SENSOR_3";
160 };
161 };
162 };
163 };
164
165 i2c@118100 {
166 clock-frequency = <100000>;
167
168 eeprom@50 {
169 compatible = "atmel,24c08";
170 reg = <0x50>;
171 pagesize = <16>;
172 };
173
174 eeprom@54 {
175 compatible = "atmel,24c08";
176 reg = <0x54>;
177 pagesize = <16>;
178 };
179 };
180
181 i2c@119000 {
182 status = "disabled";
183 };
184
185 i2c@119100 {
186 status = "disabled";
187 };
188
189 serial2: serial@11d500 {
190 status = "disabled";
191 };
192
193 serial3: serial@11d600 {
194 status = "disabled";
195 };
196
197 usb0: usb@210000 {
198 status = "disabled";
199 };
200 usb1: usb@211000 {
201 status = "disabled";
202 };
203
204 display@180000 {
205 status = "disabled";
206 };
207
208 sata@220000 {
209 status = "disabled";
210 };
211 sata@221000 {
212 status = "disabled";
213 };
214
215 fman@400000 {
216 ethernet@e0000 {
217 fixed-link = <0 1 1000 0 0>;
218 phy-connection-type = "sgmii";
219 };
220
221 ethernet@e2000 {
222 fixed-link = <1 1 1000 0 0>;
223 phy-connection-type = "sgmii";
224 };
225
226 ethernet@e4000 {
227 status = "disabled";
228 };
229
230 ethernet@e6000 {
231 status = "disabled";
232 };
233
234 ethernet@e8000 {
235 phy-handle = <&front_phy>;
236 phy-connection-type = "rgmii";
237 };
238
239 mdio0: mdio@fc000 {
240 front_phy: ethernet-phy@11 {
241 reg = <0x11>;
242 };
243 };
244 };
245 };
246
247
248 pci0: pcie@ffe240000 {
249 reg = <0xf 0xfe240000 0 0x10000>;
250 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
251 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
252 pcie@0 {
253 ranges = <0x02000000 0 0xe0000000
254 0x02000000 0 0xe0000000
255 0 0x20000000
256
257 0x01000000 0 0x00000000
258 0x01000000 0 0x00000000
259 0 0x00010000>;
260 };
261 };
262
263 pci1: pcie@ffe250000 {
264 status = "disabled";
265 };
266
267 pci2: pcie@ffe260000 {
268 status = "disabled";
269 };
270
271 pci3: pcie@ffe270000 {
272 status = "disabled";
273 };
274
275 qe: qe@ffe140000 {
276 ranges = <0x0 0xf 0xfe140000 0x40000>;
277 reg = <0xf 0xfe140000 0 0x480>;
278 brg-frequency = <0>;
279 bus-frequency = <0>;
280
281 si1: si@700 {
282 compatible = "fsl,t1040-qe-si";
283 reg = <0x700 0x80>;
284 };
285
286 siram1: siram@1000 {
287 compatible = "fsl,t1040-qe-siram";
288 reg = <0x1000 0x800>;
289 };
290
291 ucc_hdlc: ucc@2000 {
292 device_type = "hdlc";
293 compatible = "fsl,ucc-hdlc";
294 rx-clock-name = "clk9";
295 tx-clock-name = "clk9";
296 fsl,tx-timeslot-mask = <0xfffffffe>;
297 fsl,rx-timeslot-mask = <0xfffffffe>;
298 fsl,siram-entry-id = <0>;
299 };
300 };
301};
302
303#include "t1040si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/fsl/kmcoge4.dts b/arch/powerpc/boot/dts/fsl/kmcoge4.dts
index ae70a24094b0..e103c0f3f650 100644
--- a/arch/powerpc/boot/dts/fsl/kmcoge4.dts
+++ b/arch/powerpc/boot/dts/fsl/kmcoge4.dts
@@ -83,6 +83,10 @@
83 }; 83 };
84 }; 84 };
85 85
86 sdhc@114000 {
87 status = "disabled";
88 };
89
86 i2c@119000 { 90 i2c@119000 {
87 status = "disabled"; 91 status = "disabled";
88 }; 92 };
diff --git a/arch/powerpc/configs/85xx/kmp204x_defconfig b/arch/powerpc/configs/85xx/kmp204x_defconfig
deleted file mode 100644
index aaaaa609cd24..000000000000
--- a/arch/powerpc/configs/85xx/kmp204x_defconfig
+++ /dev/null
@@ -1,220 +0,0 @@
1CONFIG_PPC_85xx=y
2CONFIG_SMP=y
3CONFIG_NR_CPUS=8
4CONFIG_SYSVIPC=y
5CONFIG_POSIX_MQUEUE=y
6CONFIG_AUDIT=y
7CONFIG_NO_HZ=y
8CONFIG_HIGH_RES_TIMERS=y
9CONFIG_BSD_PROCESS_ACCT=y
10CONFIG_IKCONFIG=y
11CONFIG_IKCONFIG_PROC=y
12CONFIG_LOG_BUF_SHIFT=14
13CONFIG_CGROUPS=y
14CONFIG_CGROUP_SCHED=y
15CONFIG_RELAY=y
16CONFIG_BLK_DEV_INITRD=y
17CONFIG_KALLSYMS_ALL=y
18CONFIG_EMBEDDED=y
19CONFIG_PERF_EVENTS=y
20CONFIG_SLAB=y
21CONFIG_MODULES=y
22CONFIG_MODULE_UNLOAD=y
23CONFIG_MODULE_FORCE_UNLOAD=y
24CONFIG_MODVERSIONS=y
25# CONFIG_BLK_DEV_BSG is not set
26CONFIG_PARTITION_ADVANCED=y
27CONFIG_MAC_PARTITION=y
28CONFIG_CORENET_GENERIC=y
29CONFIG_MPIC_MSGR=y
30CONFIG_HIGHMEM=y
31# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
32CONFIG_BINFMT_MISC=m
33CONFIG_KEXEC=y
34CONFIG_FORCE_MAX_ZONEORDER=13
35CONFIG_PCI=y
36CONFIG_PCIEPORTBUS=y
37# CONFIG_PCIEASPM is not set
38CONFIG_PCI_MSI=y
39CONFIG_ADVANCED_OPTIONS=y
40CONFIG_LOWMEM_SIZE_BOOL=y
41CONFIG_LOWMEM_SIZE=0x20000000
42CONFIG_NET=y
43CONFIG_PACKET=y
44CONFIG_UNIX=y
45CONFIG_XFRM_USER=y
46CONFIG_XFRM_SUB_POLICY=y
47CONFIG_XFRM_STATISTICS=y
48CONFIG_NET_KEY=y
49CONFIG_NET_KEY_MIGRATE=y
50CONFIG_INET=y
51CONFIG_IP_MULTICAST=y
52CONFIG_IP_ADVANCED_ROUTER=y
53CONFIG_IP_MULTIPLE_TABLES=y
54CONFIG_IP_ROUTE_MULTIPATH=y
55CONFIG_IP_ROUTE_VERBOSE=y
56CONFIG_IP_PNP=y
57CONFIG_IP_PNP_DHCP=y
58CONFIG_IP_PNP_BOOTP=y
59CONFIG_IP_PNP_RARP=y
60CONFIG_NET_IPIP=y
61CONFIG_IP_MROUTE=y
62CONFIG_IP_PIMSM_V1=y
63CONFIG_IP_PIMSM_V2=y
64CONFIG_INET_AH=y
65CONFIG_INET_ESP=y
66CONFIG_INET_IPCOMP=y
67CONFIG_IPV6=y
68CONFIG_IP_SCTP=m
69CONFIG_TIPC=y
70CONFIG_NET_SCHED=y
71CONFIG_NET_SCH_CBQ=y
72CONFIG_NET_SCH_HTB=y
73CONFIG_NET_SCH_HFSC=y
74CONFIG_NET_SCH_PRIO=y
75CONFIG_NET_SCH_MULTIQ=y
76CONFIG_NET_SCH_RED=y
77CONFIG_NET_SCH_SFQ=y
78CONFIG_NET_SCH_TEQL=y
79CONFIG_NET_SCH_TBF=y
80CONFIG_NET_SCH_GRED=y
81CONFIG_NET_CLS_BASIC=y
82CONFIG_NET_CLS_TCINDEX=y
83CONFIG_NET_CLS_U32=y
84CONFIG_CLS_U32_PERF=y
85CONFIG_CLS_U32_MARK=y
86CONFIG_NET_CLS_FLOW=y
87CONFIG_NET_CLS_CGROUP=y
88CONFIG_UEVENT_HELPER_PATH="/sbin/mdev"
89CONFIG_DEVTMPFS=y
90CONFIG_MTD=y
91CONFIG_MTD_CMDLINE_PARTS=y
92CONFIG_MTD_BLOCK=y
93CONFIG_MTD_CFI=y
94CONFIG_MTD_CFI_AMDSTD=y
95CONFIG_MTD_PHYSMAP_OF=y
96CONFIG_MTD_PHRAM=y
97CONFIG_MTD_NAND=y
98CONFIG_MTD_NAND_ECC_BCH=y
99CONFIG_MTD_NAND_FSL_ELBC=y
100CONFIG_MTD_UBI=y
101CONFIG_MTD_UBI_GLUEBI=y
102CONFIG_BLK_DEV_LOOP=y
103CONFIG_BLK_DEV_RAM=y
104CONFIG_BLK_DEV_RAM_COUNT=2
105CONFIG_BLK_DEV_RAM_SIZE=2048
106CONFIG_EEPROM_AT24=y
107CONFIG_SCSI=y
108CONFIG_BLK_DEV_SD=y
109CONFIG_CHR_DEV_ST=y
110CONFIG_BLK_DEV_SR=y
111CONFIG_CHR_DEV_SG=y
112CONFIG_SCSI_LOGGING=y
113CONFIG_SCSI_SYM53C8XX_2=y
114CONFIG_NETDEVICES=y
115# CONFIG_NET_VENDOR_3COM is not set
116# CONFIG_NET_VENDOR_ADAPTEC is not set
117# CONFIG_NET_VENDOR_ALTEON is not set
118# CONFIG_NET_VENDOR_AMD is not set
119# CONFIG_NET_VENDOR_ATHEROS is not set
120# CONFIG_NET_VENDOR_BROADCOM is not set
121# CONFIG_NET_VENDOR_BROCADE is not set
122# CONFIG_NET_VENDOR_CHELSIO is not set
123# CONFIG_NET_VENDOR_CISCO is not set
124# CONFIG_NET_VENDOR_DEC is not set
125# CONFIG_NET_VENDOR_DLINK is not set
126# CONFIG_NET_VENDOR_EMULEX is not set
127# CONFIG_NET_VENDOR_EXAR is not set
128CONFIG_FSL_PQ_MDIO=y
129CONFIG_FSL_XGMAC_MDIO=y
130# CONFIG_NET_VENDOR_HP is not set
131# CONFIG_NET_VENDOR_INTEL is not set
132# CONFIG_NET_VENDOR_MARVELL is not set
133# CONFIG_NET_VENDOR_MELLANOX is not set
134# CONFIG_NET_VENDOR_MICREL is not set
135# CONFIG_NET_VENDOR_MICROCHIP is not set
136# CONFIG_NET_VENDOR_MYRI is not set
137# CONFIG_NET_VENDOR_NATSEMI is not set
138# CONFIG_NET_VENDOR_NVIDIA is not set
139# CONFIG_NET_VENDOR_OKI is not set
140# CONFIG_NET_PACKET_ENGINE is not set
141# CONFIG_NET_VENDOR_QLOGIC is not set
142# CONFIG_NET_VENDOR_REALTEK is not set
143# CONFIG_NET_VENDOR_RDC is not set
144# CONFIG_NET_VENDOR_SEEQ is not set
145# CONFIG_NET_VENDOR_SILAN is not set
146# CONFIG_NET_VENDOR_SIS is not set
147# CONFIG_NET_VENDOR_SMSC is not set
148# CONFIG_NET_VENDOR_STMICRO is not set
149# CONFIG_NET_VENDOR_SUN is not set
150# CONFIG_NET_VENDOR_TEHUTI is not set
151# CONFIG_NET_VENDOR_TI is not set
152# CONFIG_NET_VENDOR_VIA is not set
153# CONFIG_NET_VENDOR_WIZNET is not set
154# CONFIG_NET_VENDOR_XILINX is not set
155CONFIG_MARVELL_PHY=y
156CONFIG_VITESSE_PHY=y
157CONFIG_FIXED_PHY=y
158# CONFIG_WLAN is not set
159# CONFIG_INPUT_MOUSEDEV is not set
160# CONFIG_INPUT_KEYBOARD is not set
161# CONFIG_INPUT_MOUSE is not set
162CONFIG_SERIO_LIBPS2=y
163# CONFIG_LEGACY_PTYS is not set
164CONFIG_PPC_EPAPR_HV_BYTECHAN=y
165CONFIG_SERIAL_8250=y
166CONFIG_SERIAL_8250_CONSOLE=y
167CONFIG_SERIAL_8250_MANY_PORTS=y
168CONFIG_SERIAL_8250_DETECT_IRQ=y
169CONFIG_SERIAL_8250_RSA=y
170CONFIG_NVRAM=y
171CONFIG_I2C=y
172CONFIG_I2C_CHARDEV=y
173CONFIG_I2C_MUX=y
174CONFIG_I2C_MUX_PCA954x=y
175CONFIG_I2C_MPC=y
176CONFIG_SPI=y
177CONFIG_SPI_FSL_SPI=y
178CONFIG_SPI_FSL_ESPI=y
179CONFIG_SPI_SPIDEV=m
180CONFIG_PTP_1588_CLOCK=y
181# CONFIG_HWMON is not set
182# CONFIG_USB_SUPPORT is not set
183CONFIG_EDAC=y
184CONFIG_EDAC_MM_EDAC=y
185CONFIG_EDAC_MPC85XX=y
186CONFIG_RTC_CLASS=y
187CONFIG_RTC_DRV_DS3232=y
188CONFIG_RTC_DRV_CMOS=y
189CONFIG_UIO=y
190CONFIG_STAGING=y
191CONFIG_CLK_QORIQ=y
192CONFIG_EXT2_FS=y
193CONFIG_NTFS_FS=y
194CONFIG_PROC_KCORE=y
195CONFIG_TMPFS=y
196CONFIG_JFFS2_FS=y
197CONFIG_UBIFS_FS=y
198CONFIG_CRAMFS=y
199CONFIG_SQUASHFS=y
200CONFIG_SQUASHFS_XZ=y
201CONFIG_NFS_FS=y
202CONFIG_NFS_V4=y
203CONFIG_ROOT_NFS=y
204CONFIG_NLS_ISO8859_1=y
205CONFIG_NLS_UTF8=m
206CONFIG_CRC_ITU_T=m
207CONFIG_DEBUG_INFO=y
208CONFIG_MAGIC_SYSRQ=y
209CONFIG_DEBUG_SHIRQ=y
210CONFIG_DETECT_HUNG_TASK=y
211CONFIG_SCHEDSTATS=y
212CONFIG_RCU_TRACE=y
213CONFIG_UPROBE_EVENT=y
214CONFIG_CRYPTO_NULL=y
215CONFIG_CRYPTO_PCBC=m
216CONFIG_CRYPTO_MD4=y
217CONFIG_CRYPTO_SHA256=y
218CONFIG_CRYPTO_SHA512=y
219# CONFIG_CRYPTO_ANSI_CPRNG is not set
220CONFIG_CRYPTO_DEV_FSL_CAAM=y
diff --git a/arch/powerpc/configs/pseries_defconfig b/arch/powerpc/configs/pseries_defconfig
index 6d0eb02fefa4..4ff68b752618 100644
--- a/arch/powerpc/configs/pseries_defconfig
+++ b/arch/powerpc/configs/pseries_defconfig
@@ -58,7 +58,6 @@ CONFIG_KEXEC_FILE=y
58CONFIG_IRQ_ALL_CPUS=y 58CONFIG_IRQ_ALL_CPUS=y
59CONFIG_MEMORY_HOTPLUG=y 59CONFIG_MEMORY_HOTPLUG=y
60CONFIG_MEMORY_HOTREMOVE=y 60CONFIG_MEMORY_HOTREMOVE=y
61CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE=y
62CONFIG_KSM=y 61CONFIG_KSM=y
63CONFIG_TRANSPARENT_HUGEPAGE=y 62CONFIG_TRANSPARENT_HUGEPAGE=y
64CONFIG_PPC_64K_PAGES=y 63CONFIG_PPC_64K_PAGES=y
diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h
index 59abc620f8e8..73eb794d6163 100644
--- a/arch/powerpc/include/asm/bitops.h
+++ b/arch/powerpc/include/asm/bitops.h
@@ -154,6 +154,34 @@ static __inline__ int test_and_change_bit(unsigned long nr,
154 return test_and_change_bits(BIT_MASK(nr), addr + BIT_WORD(nr)) != 0; 154 return test_and_change_bits(BIT_MASK(nr), addr + BIT_WORD(nr)) != 0;
155} 155}
156 156
157#ifdef CONFIG_PPC64
158static __inline__ unsigned long clear_bit_unlock_return_word(int nr,
159 volatile unsigned long *addr)
160{
161 unsigned long old, t;
162 unsigned long *p = (unsigned long *)addr + BIT_WORD(nr);
163 unsigned long mask = BIT_MASK(nr);
164
165 __asm__ __volatile__ (
166 PPC_RELEASE_BARRIER
167"1:" PPC_LLARX(%0,0,%3,0) "\n"
168 "andc %1,%0,%2\n"
169 PPC405_ERR77(0,%3)
170 PPC_STLCX "%1,0,%3\n"
171 "bne- 1b\n"
172 : "=&r" (old), "=&r" (t)
173 : "r" (mask), "r" (p)
174 : "cc", "memory");
175
176 return old;
177}
178
179/* This is a special function for mm/filemap.c */
180#define clear_bit_unlock_is_negative_byte(nr, addr) \
181 (clear_bit_unlock_return_word(nr, addr) & BIT_MASK(PG_waiters))
182
183#endif /* CONFIG_PPC64 */
184
157#include <asm-generic/bitops/non-atomic.h> 185#include <asm-generic/bitops/non-atomic.h>
158 186
159static __inline__ void __clear_bit_unlock(int nr, volatile unsigned long *addr) 187static __inline__ void __clear_bit_unlock(int nr, volatile unsigned long *addr)
diff --git a/arch/powerpc/include/asm/pnv-pci.h b/arch/powerpc/include/asm/pnv-pci.h
index 696438f09aea..de9681034353 100644
--- a/arch/powerpc/include/asm/pnv-pci.h
+++ b/arch/powerpc/include/asm/pnv-pci.h
@@ -57,6 +57,8 @@ struct pnv_php_slot {
57 uint64_t id; 57 uint64_t id;
58 char *name; 58 char *name;
59 int slot_no; 59 int slot_no;
60 unsigned int flags;
61#define PNV_PHP_FLAG_BROKEN_PDC 0x1
60 struct kref kref; 62 struct kref kref;
61#define PNV_PHP_STATE_INITIALIZED 0 63#define PNV_PHP_STATE_INITIALIZED 0
62#define PNV_PHP_STATE_REGISTERED 1 64#define PNV_PHP_STATE_REGISTERED 1
diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h
index 025833b8df9f..359c44341761 100644
--- a/arch/powerpc/include/asm/ppc_asm.h
+++ b/arch/powerpc/include/asm/ppc_asm.h
@@ -505,7 +505,6 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
505#define MTMSRD(r) mtmsrd r 505#define MTMSRD(r) mtmsrd r
506#define MTMSR_EERI(reg) mtmsrd reg,1 506#define MTMSR_EERI(reg) mtmsrd reg,1
507#else 507#else
508#define FIX_SRR1(ra, rb)
509#ifndef CONFIG_40x 508#ifndef CONFIG_40x
510#define RFI rfi 509#define RFI rfi
511#else 510#else
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 21e0b52685b5..e0fecbcea2a2 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -225,6 +225,7 @@ struct thread_struct {
225#ifdef CONFIG_PPC64 225#ifdef CONFIG_PPC64
226 unsigned long start_tb; /* Start purr when proc switched in */ 226 unsigned long start_tb; /* Start purr when proc switched in */
227 unsigned long accum_tb; /* Total accumulated purr for process */ 227 unsigned long accum_tb; /* Total accumulated purr for process */
228#endif
228#ifdef CONFIG_HAVE_HW_BREAKPOINT 229#ifdef CONFIG_HAVE_HW_BREAKPOINT
229 struct perf_event *ptrace_bps[HBP_NUM]; 230 struct perf_event *ptrace_bps[HBP_NUM];
230 /* 231 /*
@@ -233,7 +234,6 @@ struct thread_struct {
233 */ 234 */
234 struct perf_event *last_hit_ubp; 235 struct perf_event *last_hit_ubp;
235#endif /* CONFIG_HAVE_HW_BREAKPOINT */ 236#endif /* CONFIG_HAVE_HW_BREAKPOINT */
236#endif
237 struct arch_hw_breakpoint hw_brk; /* info on the hardware breakpoint */ 237 struct arch_hw_breakpoint hw_brk; /* info on the hardware breakpoint */
238 unsigned long trap_nr; /* last trap # on this thread */ 238 unsigned long trap_nr; /* last trap # on this thread */
239 u8 load_fp; 239 u8 load_fp;
diff --git a/arch/powerpc/include/asm/prom.h b/arch/powerpc/include/asm/prom.h
index 2c8001cc93b6..4a90634e8322 100644
--- a/arch/powerpc/include/asm/prom.h
+++ b/arch/powerpc/include/asm/prom.h
@@ -153,6 +153,7 @@ struct of_drconf_cell {
153#define OV5_XCMO 0x0440 /* Page Coalescing */ 153#define OV5_XCMO 0x0440 /* Page Coalescing */
154#define OV5_TYPE1_AFFINITY 0x0580 /* Type 1 NUMA affinity */ 154#define OV5_TYPE1_AFFINITY 0x0580 /* Type 1 NUMA affinity */
155#define OV5_PRRN 0x0540 /* Platform Resource Reassignment */ 155#define OV5_PRRN 0x0540 /* Platform Resource Reassignment */
156#define OV5_HP_EVT 0x0604 /* Hot Plug Event support */
156#define OV5_RESIZE_HPT 0x0601 /* Hash Page Table resizing */ 157#define OV5_RESIZE_HPT 0x0601 /* Hash Page Table resizing */
157#define OV5_PFO_HW_RNG 0x1180 /* PFO Random Number Generator */ 158#define OV5_PFO_HW_RNG 0x1180 /* PFO Random Number Generator */
158#define OV5_PFO_HW_842 0x1140 /* PFO Compression Accelerator */ 159#define OV5_PFO_HW_842 0x1140 /* PFO Compression Accelerator */
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index cb02d32db147..fc879fd6bdae 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -552,7 +552,9 @@
552#define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */ 552#define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */
553#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */ 553#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
554#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ 554#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
555#ifndef SPRN_ICTRL
555#define SPRN_ICTRL 0x3F3 /* 1011 7450 icache and interrupt ctrl */ 556#define SPRN_ICTRL 0x3F3 /* 1011 7450 icache and interrupt ctrl */
557#endif
556#define ICTRL_EICE 0x08000000 /* enable icache parity errs */ 558#define ICTRL_EICE 0x08000000 /* enable icache parity errs */
557#define ICTRL_EDC 0x04000000 /* enable dcache parity errs */ 559#define ICTRL_EDC 0x04000000 /* enable dcache parity errs */
558#define ICTRL_EICP 0x00000100 /* enable icache par. check */ 560#define ICTRL_EICP 0x00000100 /* enable icache par. check */
diff --git a/arch/powerpc/include/asm/reg_8xx.h b/arch/powerpc/include/asm/reg_8xx.h
index 1f1636124a04..ae16fef7a4d6 100644
--- a/arch/powerpc/include/asm/reg_8xx.h
+++ b/arch/powerpc/include/asm/reg_8xx.h
@@ -28,6 +28,17 @@
28/* Special MSR manipulation registers */ 28/* Special MSR manipulation registers */
29#define SPRN_EIE 80 /* External interrupt enable (EE=1, RI=1) */ 29#define SPRN_EIE 80 /* External interrupt enable (EE=1, RI=1) */
30#define SPRN_EID 81 /* External interrupt disable (EE=0, RI=1) */ 30#define SPRN_EID 81 /* External interrupt disable (EE=0, RI=1) */
31#define SPRN_NRI 82 /* Non recoverable interrupt (EE=0, RI=0) */
32
33/* Debug registers */
34#define SPRN_CMPA 144
35#define SPRN_COUNTA 150
36#define SPRN_CMPE 152
37#define SPRN_CMPF 153
38#define SPRN_LCTRL1 156
39#define SPRN_LCTRL2 157
40#define SPRN_ICTRL 158
41#define SPRN_BAR 159
31 42
32/* Commands. Only the first few are available to the instruction cache. 43/* Commands. Only the first few are available to the instruction cache.
33*/ 44*/
diff --git a/arch/powerpc/include/asm/rtas.h b/arch/powerpc/include/asm/rtas.h
index 076b89247ab5..ec9dd79398ee 100644
--- a/arch/powerpc/include/asm/rtas.h
+++ b/arch/powerpc/include/asm/rtas.h
@@ -307,6 +307,7 @@ struct pseries_hp_errorlog {
307 union { 307 union {
308 __be32 drc_index; 308 __be32 drc_index;
309 __be32 drc_count; 309 __be32 drc_count;
310 struct { __be32 count, index; } ic;
310 char drc_name[1]; 311 char drc_name[1];
311 } _drc_u; 312 } _drc_u;
312}; 313};
@@ -323,6 +324,7 @@ struct pseries_hp_errorlog {
323#define PSERIES_HP_ELOG_ID_DRC_NAME 1 324#define PSERIES_HP_ELOG_ID_DRC_NAME 1
324#define PSERIES_HP_ELOG_ID_DRC_INDEX 2 325#define PSERIES_HP_ELOG_ID_DRC_INDEX 2
325#define PSERIES_HP_ELOG_ID_DRC_COUNT 3 326#define PSERIES_HP_ELOG_ID_DRC_COUNT 3
327#define PSERIES_HP_ELOG_ID_DRC_IC 4
326 328
327struct pseries_errorlog *get_pseries_errorlog(struct rtas_error_log *log, 329struct pseries_errorlog *get_pseries_errorlog(struct rtas_error_log *log,
328 uint16_t section_id); 330 uint16_t section_id);
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index f25239b3a06f..4367e7df51a1 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -72,205 +72,190 @@
72#include <asm/fixmap.h> 72#include <asm/fixmap.h>
73#endif 73#endif
74 74
75#define STACK_PT_REGS_OFFSET(sym, val) \
76 DEFINE(sym, STACK_FRAME_OVERHEAD + offsetof(struct pt_regs, val))
77
75int main(void) 78int main(void)
76{ 79{
77 DEFINE(THREAD, offsetof(struct task_struct, thread)); 80 OFFSET(THREAD, task_struct, thread);
78 DEFINE(MM, offsetof(struct task_struct, mm)); 81 OFFSET(MM, task_struct, mm);
79 DEFINE(MMCONTEXTID, offsetof(struct mm_struct, context.id)); 82 OFFSET(MMCONTEXTID, mm_struct, context.id);
80#ifdef CONFIG_PPC64 83#ifdef CONFIG_PPC64
81 DEFINE(SIGSEGV, SIGSEGV); 84 DEFINE(SIGSEGV, SIGSEGV);
82 DEFINE(NMI_MASK, NMI_MASK); 85 DEFINE(NMI_MASK, NMI_MASK);
83 DEFINE(TASKTHREADPPR, offsetof(struct task_struct, thread.ppr)); 86 OFFSET(TASKTHREADPPR, task_struct, thread.ppr);
84#else 87#else
85 DEFINE(THREAD_INFO, offsetof(struct task_struct, stack)); 88 OFFSET(THREAD_INFO, task_struct, stack);
86 DEFINE(THREAD_INFO_GAP, _ALIGN_UP(sizeof(struct thread_info), 16)); 89 DEFINE(THREAD_INFO_GAP, _ALIGN_UP(sizeof(struct thread_info), 16));
87 DEFINE(KSP_LIMIT, offsetof(struct thread_struct, ksp_limit)); 90 OFFSET(KSP_LIMIT, thread_struct, ksp_limit);
88#endif /* CONFIG_PPC64 */ 91#endif /* CONFIG_PPC64 */
89 92
90#ifdef CONFIG_LIVEPATCH 93#ifdef CONFIG_LIVEPATCH
91 DEFINE(TI_livepatch_sp, offsetof(struct thread_info, livepatch_sp)); 94 OFFSET(TI_livepatch_sp, thread_info, livepatch_sp);
92#endif 95#endif
93 96
94 DEFINE(KSP, offsetof(struct thread_struct, ksp)); 97 OFFSET(KSP, thread_struct, ksp);
95 DEFINE(PT_REGS, offsetof(struct thread_struct, regs)); 98 OFFSET(PT_REGS, thread_struct, regs);
96#ifdef CONFIG_BOOKE 99#ifdef CONFIG_BOOKE
97 DEFINE(THREAD_NORMSAVES, offsetof(struct thread_struct, normsave[0])); 100 OFFSET(THREAD_NORMSAVES, thread_struct, normsave[0]);
98#endif 101#endif
99 DEFINE(THREAD_FPEXC_MODE, offsetof(struct thread_struct, fpexc_mode)); 102 OFFSET(THREAD_FPEXC_MODE, thread_struct, fpexc_mode);
100 DEFINE(THREAD_FPSTATE, offsetof(struct thread_struct, fp_state)); 103 OFFSET(THREAD_FPSTATE, thread_struct, fp_state);
101 DEFINE(THREAD_FPSAVEAREA, offsetof(struct thread_struct, fp_save_area)); 104 OFFSET(THREAD_FPSAVEAREA, thread_struct, fp_save_area);
102 DEFINE(FPSTATE_FPSCR, offsetof(struct thread_fp_state, fpscr)); 105 OFFSET(FPSTATE_FPSCR, thread_fp_state, fpscr);
103 DEFINE(THREAD_LOAD_FP, offsetof(struct thread_struct, load_fp)); 106 OFFSET(THREAD_LOAD_FP, thread_struct, load_fp);
104#ifdef CONFIG_ALTIVEC 107#ifdef CONFIG_ALTIVEC
105 DEFINE(THREAD_VRSTATE, offsetof(struct thread_struct, vr_state)); 108 OFFSET(THREAD_VRSTATE, thread_struct, vr_state);
106 DEFINE(THREAD_VRSAVEAREA, offsetof(struct thread_struct, vr_save_area)); 109 OFFSET(THREAD_VRSAVEAREA, thread_struct, vr_save_area);
107 DEFINE(THREAD_VRSAVE, offsetof(struct thread_struct, vrsave)); 110 OFFSET(THREAD_VRSAVE, thread_struct, vrsave);
108 DEFINE(THREAD_USED_VR, offsetof(struct thread_struct, used_vr)); 111 OFFSET(THREAD_USED_VR, thread_struct, used_vr);
109 DEFINE(VRSTATE_VSCR, offsetof(struct thread_vr_state, vscr)); 112 OFFSET(VRSTATE_VSCR, thread_vr_state, vscr);
110 DEFINE(THREAD_LOAD_VEC, offsetof(struct thread_struct, load_vec)); 113 OFFSET(THREAD_LOAD_VEC, thread_struct, load_vec);
111#endif /* CONFIG_ALTIVEC */ 114#endif /* CONFIG_ALTIVEC */
112#ifdef CONFIG_VSX 115#ifdef CONFIG_VSX
113 DEFINE(THREAD_USED_VSR, offsetof(struct thread_struct, used_vsr)); 116 OFFSET(THREAD_USED_VSR, thread_struct, used_vsr);
114#endif /* CONFIG_VSX */ 117#endif /* CONFIG_VSX */
115#ifdef CONFIG_PPC64 118#ifdef CONFIG_PPC64
116 DEFINE(KSP_VSID, offsetof(struct thread_struct, ksp_vsid)); 119 OFFSET(KSP_VSID, thread_struct, ksp_vsid);
117#else /* CONFIG_PPC64 */ 120#else /* CONFIG_PPC64 */
118 DEFINE(PGDIR, offsetof(struct thread_struct, pgdir)); 121 OFFSET(PGDIR, thread_struct, pgdir);
119#ifdef CONFIG_SPE 122#ifdef CONFIG_SPE
120 DEFINE(THREAD_EVR0, offsetof(struct thread_struct, evr[0])); 123 OFFSET(THREAD_EVR0, thread_struct, evr[0]);
121 DEFINE(THREAD_ACC, offsetof(struct thread_struct, acc)); 124 OFFSET(THREAD_ACC, thread_struct, acc);
122 DEFINE(THREAD_SPEFSCR, offsetof(struct thread_struct, spefscr)); 125 OFFSET(THREAD_SPEFSCR, thread_struct, spefscr);
123 DEFINE(THREAD_USED_SPE, offsetof(struct thread_struct, used_spe)); 126 OFFSET(THREAD_USED_SPE, thread_struct, used_spe);
124#endif /* CONFIG_SPE */ 127#endif /* CONFIG_SPE */
125#endif /* CONFIG_PPC64 */ 128#endif /* CONFIG_PPC64 */
126#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) 129#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
127 DEFINE(THREAD_DBCR0, offsetof(struct thread_struct, debug.dbcr0)); 130 OFFSET(THREAD_DBCR0, thread_struct, debug.dbcr0);
128#endif 131#endif
129#ifdef CONFIG_KVM_BOOK3S_32_HANDLER 132#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
130 DEFINE(THREAD_KVM_SVCPU, offsetof(struct thread_struct, kvm_shadow_vcpu)); 133 OFFSET(THREAD_KVM_SVCPU, thread_struct, kvm_shadow_vcpu);
131#endif 134#endif
132#if defined(CONFIG_KVM) && defined(CONFIG_BOOKE) 135#if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
133 DEFINE(THREAD_KVM_VCPU, offsetof(struct thread_struct, kvm_vcpu)); 136 OFFSET(THREAD_KVM_VCPU, thread_struct, kvm_vcpu);
134#endif 137#endif
135 138
136#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 139#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
137 DEFINE(PACATMSCRATCH, offsetof(struct paca_struct, tm_scratch)); 140 OFFSET(PACATMSCRATCH, paca_struct, tm_scratch);
138 DEFINE(THREAD_TM_TFHAR, offsetof(struct thread_struct, tm_tfhar)); 141 OFFSET(THREAD_TM_TFHAR, thread_struct, tm_tfhar);
139 DEFINE(THREAD_TM_TEXASR, offsetof(struct thread_struct, tm_texasr)); 142 OFFSET(THREAD_TM_TEXASR, thread_struct, tm_texasr);
140 DEFINE(THREAD_TM_TFIAR, offsetof(struct thread_struct, tm_tfiar)); 143 OFFSET(THREAD_TM_TFIAR, thread_struct, tm_tfiar);
141 DEFINE(THREAD_TM_TAR, offsetof(struct thread_struct, tm_tar)); 144 OFFSET(THREAD_TM_TAR, thread_struct, tm_tar);
142 DEFINE(THREAD_TM_PPR, offsetof(struct thread_struct, tm_ppr)); 145 OFFSET(THREAD_TM_PPR, thread_struct, tm_ppr);
143 DEFINE(THREAD_TM_DSCR, offsetof(struct thread_struct, tm_dscr)); 146 OFFSET(THREAD_TM_DSCR, thread_struct, tm_dscr);
144 DEFINE(PT_CKPT_REGS, offsetof(struct thread_struct, ckpt_regs)); 147 OFFSET(PT_CKPT_REGS, thread_struct, ckpt_regs);
145 DEFINE(THREAD_CKVRSTATE, offsetof(struct thread_struct, 148 OFFSET(THREAD_CKVRSTATE, thread_struct, ckvr_state);
146 ckvr_state)); 149 OFFSET(THREAD_CKVRSAVE, thread_struct, ckvrsave);
147 DEFINE(THREAD_CKVRSAVE, offsetof(struct thread_struct, 150 OFFSET(THREAD_CKFPSTATE, thread_struct, ckfp_state);
148 ckvrsave));
149 DEFINE(THREAD_CKFPSTATE, offsetof(struct thread_struct,
150 ckfp_state));
151 /* Local pt_regs on stack for Transactional Memory funcs. */ 151 /* Local pt_regs on stack for Transactional Memory funcs. */
152 DEFINE(TM_FRAME_SIZE, STACK_FRAME_OVERHEAD + 152 DEFINE(TM_FRAME_SIZE, STACK_FRAME_OVERHEAD +
153 sizeof(struct pt_regs) + 16); 153 sizeof(struct pt_regs) + 16);
154#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 154#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
155 155
156 DEFINE(TI_FLAGS, offsetof(struct thread_info, flags)); 156 OFFSET(TI_FLAGS, thread_info, flags);
157 DEFINE(TI_LOCAL_FLAGS, offsetof(struct thread_info, local_flags)); 157 OFFSET(TI_LOCAL_FLAGS, thread_info, local_flags);
158 DEFINE(TI_PREEMPT, offsetof(struct thread_info, preempt_count)); 158 OFFSET(TI_PREEMPT, thread_info, preempt_count);
159 DEFINE(TI_TASK, offsetof(struct thread_info, task)); 159 OFFSET(TI_TASK, thread_info, task);
160 DEFINE(TI_CPU, offsetof(struct thread_info, cpu)); 160 OFFSET(TI_CPU, thread_info, cpu);
161 161
162#ifdef CONFIG_PPC64 162#ifdef CONFIG_PPC64
163 DEFINE(DCACHEL1BLOCKSIZE, offsetof(struct ppc64_caches, l1d.block_size)); 163 OFFSET(DCACHEL1BLOCKSIZE, ppc64_caches, l1d.block_size);
164 DEFINE(DCACHEL1LOGBLOCKSIZE, offsetof(struct ppc64_caches, l1d.log_block_size)); 164 OFFSET(DCACHEL1LOGBLOCKSIZE, ppc64_caches, l1d.log_block_size);
165 DEFINE(DCACHEL1BLOCKSPERPAGE, offsetof(struct ppc64_caches, l1d.blocks_per_page)); 165 OFFSET(DCACHEL1BLOCKSPERPAGE, ppc64_caches, l1d.blocks_per_page);
166 DEFINE(ICACHEL1BLOCKSIZE, offsetof(struct ppc64_caches, l1i.block_size)); 166 OFFSET(ICACHEL1BLOCKSIZE, ppc64_caches, l1i.block_size);
167 DEFINE(ICACHEL1LOGBLOCKSIZE, offsetof(struct ppc64_caches, l1i.log_block_size)); 167 OFFSET(ICACHEL1LOGBLOCKSIZE, ppc64_caches, l1i.log_block_size);
168 DEFINE(ICACHEL1BLOCKSPERPAGE, offsetof(struct ppc64_caches, l1i.blocks_per_page)); 168 OFFSET(ICACHEL1BLOCKSPERPAGE, ppc64_caches, l1i.blocks_per_page);
169 /* paca */ 169 /* paca */
170 DEFINE(PACA_SIZE, sizeof(struct paca_struct)); 170 DEFINE(PACA_SIZE, sizeof(struct paca_struct));
171 DEFINE(PACAPACAINDEX, offsetof(struct paca_struct, paca_index)); 171 OFFSET(PACAPACAINDEX, paca_struct, paca_index);
172 DEFINE(PACAPROCSTART, offsetof(struct paca_struct, cpu_start)); 172 OFFSET(PACAPROCSTART, paca_struct, cpu_start);
173 DEFINE(PACAKSAVE, offsetof(struct paca_struct, kstack)); 173 OFFSET(PACAKSAVE, paca_struct, kstack);
174 DEFINE(PACACURRENT, offsetof(struct paca_struct, __current)); 174 OFFSET(PACACURRENT, paca_struct, __current);
175 DEFINE(PACASAVEDMSR, offsetof(struct paca_struct, saved_msr)); 175 OFFSET(PACASAVEDMSR, paca_struct, saved_msr);
176 DEFINE(PACASTABRR, offsetof(struct paca_struct, stab_rr)); 176 OFFSET(PACASTABRR, paca_struct, stab_rr);
177 DEFINE(PACAR1, offsetof(struct paca_struct, saved_r1)); 177 OFFSET(PACAR1, paca_struct, saved_r1);
178 DEFINE(PACATOC, offsetof(struct paca_struct, kernel_toc)); 178 OFFSET(PACATOC, paca_struct, kernel_toc);
179 DEFINE(PACAKBASE, offsetof(struct paca_struct, kernelbase)); 179 OFFSET(PACAKBASE, paca_struct, kernelbase);
180 DEFINE(PACAKMSR, offsetof(struct paca_struct, kernel_msr)); 180 OFFSET(PACAKMSR, paca_struct, kernel_msr);
181 DEFINE(PACASOFTIRQEN, offsetof(struct paca_struct, soft_enabled)); 181 OFFSET(PACASOFTIRQEN, paca_struct, soft_enabled);
182 DEFINE(PACAIRQHAPPENED, offsetof(struct paca_struct, irq_happened)); 182 OFFSET(PACAIRQHAPPENED, paca_struct, irq_happened);
183#ifdef CONFIG_PPC_BOOK3S 183#ifdef CONFIG_PPC_BOOK3S
184 DEFINE(PACACONTEXTID, offsetof(struct paca_struct, mm_ctx_id)); 184 OFFSET(PACACONTEXTID, paca_struct, mm_ctx_id);
185#ifdef CONFIG_PPC_MM_SLICES 185#ifdef CONFIG_PPC_MM_SLICES
186 DEFINE(PACALOWSLICESPSIZE, offsetof(struct paca_struct, 186 OFFSET(PACALOWSLICESPSIZE, paca_struct, mm_ctx_low_slices_psize);
187 mm_ctx_low_slices_psize)); 187 OFFSET(PACAHIGHSLICEPSIZE, paca_struct, mm_ctx_high_slices_psize);
188 DEFINE(PACAHIGHSLICEPSIZE, offsetof(struct paca_struct,
189 mm_ctx_high_slices_psize));
190 DEFINE(MMUPSIZEDEFSIZE, sizeof(struct mmu_psize_def)); 188 DEFINE(MMUPSIZEDEFSIZE, sizeof(struct mmu_psize_def));
191#endif /* CONFIG_PPC_MM_SLICES */ 189#endif /* CONFIG_PPC_MM_SLICES */
192#endif 190#endif
193 191
194#ifdef CONFIG_PPC_BOOK3E 192#ifdef CONFIG_PPC_BOOK3E
195 DEFINE(PACAPGD, offsetof(struct paca_struct, pgd)); 193 OFFSET(PACAPGD, paca_struct, pgd);
196 DEFINE(PACA_KERNELPGD, offsetof(struct paca_struct, kernel_pgd)); 194 OFFSET(PACA_KERNELPGD, paca_struct, kernel_pgd);
197 DEFINE(PACA_EXGEN, offsetof(struct paca_struct, exgen)); 195 OFFSET(PACA_EXGEN, paca_struct, exgen);
198 DEFINE(PACA_EXTLB, offsetof(struct paca_struct, extlb)); 196 OFFSET(PACA_EXTLB, paca_struct, extlb);
199 DEFINE(PACA_EXMC, offsetof(struct paca_struct, exmc)); 197 OFFSET(PACA_EXMC, paca_struct, exmc);
200 DEFINE(PACA_EXCRIT, offsetof(struct paca_struct, excrit)); 198 OFFSET(PACA_EXCRIT, paca_struct, excrit);
201 DEFINE(PACA_EXDBG, offsetof(struct paca_struct, exdbg)); 199 OFFSET(PACA_EXDBG, paca_struct, exdbg);
202 DEFINE(PACA_MC_STACK, offsetof(struct paca_struct, mc_kstack)); 200 OFFSET(PACA_MC_STACK, paca_struct, mc_kstack);
203 DEFINE(PACA_CRIT_STACK, offsetof(struct paca_struct, crit_kstack)); 201 OFFSET(PACA_CRIT_STACK, paca_struct, crit_kstack);
204 DEFINE(PACA_DBG_STACK, offsetof(struct paca_struct, dbg_kstack)); 202 OFFSET(PACA_DBG_STACK, paca_struct, dbg_kstack);
205 DEFINE(PACA_TCD_PTR, offsetof(struct paca_struct, tcd_ptr)); 203 OFFSET(PACA_TCD_PTR, paca_struct, tcd_ptr);
206 204
207 DEFINE(TCD_ESEL_NEXT, 205 OFFSET(TCD_ESEL_NEXT, tlb_core_data, esel_next);
208 offsetof(struct tlb_core_data, esel_next)); 206 OFFSET(TCD_ESEL_MAX, tlb_core_data, esel_max);
209 DEFINE(TCD_ESEL_MAX, 207 OFFSET(TCD_ESEL_FIRST, tlb_core_data, esel_first);
210 offsetof(struct tlb_core_data, esel_max));
211 DEFINE(TCD_ESEL_FIRST,
212 offsetof(struct tlb_core_data, esel_first));
213#endif /* CONFIG_PPC_BOOK3E */ 208#endif /* CONFIG_PPC_BOOK3E */
214 209
215#ifdef CONFIG_PPC_STD_MMU_64 210#ifdef CONFIG_PPC_STD_MMU_64
216 DEFINE(PACASLBCACHE, offsetof(struct paca_struct, slb_cache)); 211 OFFSET(PACASLBCACHE, paca_struct, slb_cache);
217 DEFINE(PACASLBCACHEPTR, offsetof(struct paca_struct, slb_cache_ptr)); 212 OFFSET(PACASLBCACHEPTR, paca_struct, slb_cache_ptr);
218 DEFINE(PACAVMALLOCSLLP, offsetof(struct paca_struct, vmalloc_sllp)); 213 OFFSET(PACAVMALLOCSLLP, paca_struct, vmalloc_sllp);
219#ifdef CONFIG_PPC_MM_SLICES 214#ifdef CONFIG_PPC_MM_SLICES
220 DEFINE(MMUPSIZESLLP, offsetof(struct mmu_psize_def, sllp)); 215 OFFSET(MMUPSIZESLLP, mmu_psize_def, sllp);
221#else 216#else
222 DEFINE(PACACONTEXTSLLP, offsetof(struct paca_struct, mm_ctx_sllp)); 217 OFFSET(PACACONTEXTSLLP, paca_struct, mm_ctx_sllp);
223#endif /* CONFIG_PPC_MM_SLICES */ 218#endif /* CONFIG_PPC_MM_SLICES */
224 DEFINE(PACA_EXGEN, offsetof(struct paca_struct, exgen)); 219 OFFSET(PACA_EXGEN, paca_struct, exgen);
225 DEFINE(PACA_EXMC, offsetof(struct paca_struct, exmc)); 220 OFFSET(PACA_EXMC, paca_struct, exmc);
226 DEFINE(PACA_EXSLB, offsetof(struct paca_struct, exslb)); 221 OFFSET(PACA_EXSLB, paca_struct, exslb);
227 DEFINE(PACALPPACAPTR, offsetof(struct paca_struct, lppaca_ptr)); 222 OFFSET(PACALPPACAPTR, paca_struct, lppaca_ptr);
228 DEFINE(PACA_SLBSHADOWPTR, offsetof(struct paca_struct, slb_shadow_ptr)); 223 OFFSET(PACA_SLBSHADOWPTR, paca_struct, slb_shadow_ptr);
229 DEFINE(SLBSHADOW_STACKVSID, 224 OFFSET(SLBSHADOW_STACKVSID, slb_shadow, save_area[SLB_NUM_BOLTED - 1].vsid);
230 offsetof(struct slb_shadow, save_area[SLB_NUM_BOLTED - 1].vsid)); 225 OFFSET(SLBSHADOW_STACKESID, slb_shadow, save_area[SLB_NUM_BOLTED - 1].esid);
231 DEFINE(SLBSHADOW_STACKESID, 226 OFFSET(SLBSHADOW_SAVEAREA, slb_shadow, save_area);
232 offsetof(struct slb_shadow, save_area[SLB_NUM_BOLTED - 1].esid)); 227 OFFSET(LPPACA_PMCINUSE, lppaca, pmcregs_in_use);
233 DEFINE(SLBSHADOW_SAVEAREA, offsetof(struct slb_shadow, save_area)); 228 OFFSET(LPPACA_DTLIDX, lppaca, dtl_idx);
234 DEFINE(LPPACA_PMCINUSE, offsetof(struct lppaca, pmcregs_in_use)); 229 OFFSET(LPPACA_YIELDCOUNT, lppaca, yield_count);
235 DEFINE(LPPACA_DTLIDX, offsetof(struct lppaca, dtl_idx)); 230 OFFSET(PACA_DTL_RIDX, paca_struct, dtl_ridx);
236 DEFINE(LPPACA_YIELDCOUNT, offsetof(struct lppaca, yield_count));
237 DEFINE(PACA_DTL_RIDX, offsetof(struct paca_struct, dtl_ridx));
238#endif /* CONFIG_PPC_STD_MMU_64 */ 231#endif /* CONFIG_PPC_STD_MMU_64 */
239 DEFINE(PACAEMERGSP, offsetof(struct paca_struct, emergency_sp)); 232 OFFSET(PACAEMERGSP, paca_struct, emergency_sp);
240#ifdef CONFIG_PPC_BOOK3S_64 233#ifdef CONFIG_PPC_BOOK3S_64
241 DEFINE(PACAMCEMERGSP, offsetof(struct paca_struct, mc_emergency_sp)); 234 OFFSET(PACAMCEMERGSP, paca_struct, mc_emergency_sp);
242 DEFINE(PACA_IN_MCE, offsetof(struct paca_struct, in_mce)); 235 OFFSET(PACA_IN_MCE, paca_struct, in_mce);
243#endif 236#endif
244 DEFINE(PACAHWCPUID, offsetof(struct paca_struct, hw_cpu_id)); 237 OFFSET(PACAHWCPUID, paca_struct, hw_cpu_id);
245 DEFINE(PACAKEXECSTATE, offsetof(struct paca_struct, kexec_state)); 238 OFFSET(PACAKEXECSTATE, paca_struct, kexec_state);
246 DEFINE(PACA_DSCR_DEFAULT, offsetof(struct paca_struct, dscr_default)); 239 OFFSET(PACA_DSCR_DEFAULT, paca_struct, dscr_default);
247 DEFINE(ACCOUNT_STARTTIME, 240 OFFSET(ACCOUNT_STARTTIME, paca_struct, accounting.starttime);
248 offsetof(struct paca_struct, accounting.starttime)); 241 OFFSET(ACCOUNT_STARTTIME_USER, paca_struct, accounting.starttime_user);
249 DEFINE(ACCOUNT_STARTTIME_USER, 242 OFFSET(ACCOUNT_USER_TIME, paca_struct, accounting.utime);
250 offsetof(struct paca_struct, accounting.starttime_user)); 243 OFFSET(ACCOUNT_SYSTEM_TIME, paca_struct, accounting.stime);
251 DEFINE(ACCOUNT_USER_TIME, 244 OFFSET(PACA_TRAP_SAVE, paca_struct, trap_save);
252 offsetof(struct paca_struct, accounting.utime)); 245 OFFSET(PACA_NAPSTATELOST, paca_struct, nap_state_lost);
253 DEFINE(ACCOUNT_SYSTEM_TIME, 246 OFFSET(PACA_SPRG_VDSO, paca_struct, sprg_vdso);
254 offsetof(struct paca_struct, accounting.stime));
255 DEFINE(PACA_TRAP_SAVE, offsetof(struct paca_struct, trap_save));
256 DEFINE(PACA_NAPSTATELOST, offsetof(struct paca_struct, nap_state_lost));
257 DEFINE(PACA_SPRG_VDSO, offsetof(struct paca_struct, sprg_vdso));
258#else /* CONFIG_PPC64 */ 247#else /* CONFIG_PPC64 */
259#ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE 248#ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
260 DEFINE(ACCOUNT_STARTTIME, 249 OFFSET(ACCOUNT_STARTTIME, thread_info, accounting.starttime);
261 offsetof(struct thread_info, accounting.starttime)); 250 OFFSET(ACCOUNT_STARTTIME_USER, thread_info, accounting.starttime_user);
262 DEFINE(ACCOUNT_STARTTIME_USER, 251 OFFSET(ACCOUNT_USER_TIME, thread_info, accounting.utime);
263 offsetof(struct thread_info, accounting.starttime_user)); 252 OFFSET(ACCOUNT_SYSTEM_TIME, thread_info, accounting.stime);
264 DEFINE(ACCOUNT_USER_TIME,
265 offsetof(struct thread_info, accounting.utime));
266 DEFINE(ACCOUNT_SYSTEM_TIME,
267 offsetof(struct thread_info, accounting.stime));
268#endif 253#endif
269#endif /* CONFIG_PPC64 */ 254#endif /* CONFIG_PPC64 */
270 255
271 /* RTAS */ 256 /* RTAS */
272 DEFINE(RTASBASE, offsetof(struct rtas_t, base)); 257 OFFSET(RTASBASE, rtas_t, base);
273 DEFINE(RTASENTRY, offsetof(struct rtas_t, entry)); 258 OFFSET(RTASENTRY, rtas_t, entry);
274 259
275 /* Interrupt register frame */ 260 /* Interrupt register frame */
276 DEFINE(INT_FRAME_SIZE, STACK_INT_FRAME_SIZE); 261 DEFINE(INT_FRAME_SIZE, STACK_INT_FRAME_SIZE);
@@ -280,38 +265,38 @@ int main(void)
280 DEFINE(PROM_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs) + 16); 265 DEFINE(PROM_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs) + 16);
281 DEFINE(RTAS_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs) + 16); 266 DEFINE(RTAS_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs) + 16);
282#endif /* CONFIG_PPC64 */ 267#endif /* CONFIG_PPC64 */
283 DEFINE(GPR0, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[0])); 268 STACK_PT_REGS_OFFSET(GPR0, gpr[0]);
284 DEFINE(GPR1, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[1])); 269 STACK_PT_REGS_OFFSET(GPR1, gpr[1]);
285 DEFINE(GPR2, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[2])); 270 STACK_PT_REGS_OFFSET(GPR2, gpr[2]);
286 DEFINE(GPR3, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[3])); 271 STACK_PT_REGS_OFFSET(GPR3, gpr[3]);
287 DEFINE(GPR4, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[4])); 272 STACK_PT_REGS_OFFSET(GPR4, gpr[4]);
288 DEFINE(GPR5, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[5])); 273 STACK_PT_REGS_OFFSET(GPR5, gpr[5]);
289 DEFINE(GPR6, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[6])); 274 STACK_PT_REGS_OFFSET(GPR6, gpr[6]);
290 DEFINE(GPR7, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[7])); 275 STACK_PT_REGS_OFFSET(GPR7, gpr[7]);
291 DEFINE(GPR8, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[8])); 276 STACK_PT_REGS_OFFSET(GPR8, gpr[8]);
292 DEFINE(GPR9, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[9])); 277 STACK_PT_REGS_OFFSET(GPR9, gpr[9]);
293 DEFINE(GPR10, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[10])); 278 STACK_PT_REGS_OFFSET(GPR10, gpr[10]);
294 DEFINE(GPR11, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[11])); 279 STACK_PT_REGS_OFFSET(GPR11, gpr[11]);
295 DEFINE(GPR12, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[12])); 280 STACK_PT_REGS_OFFSET(GPR12, gpr[12]);
296 DEFINE(GPR13, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[13])); 281 STACK_PT_REGS_OFFSET(GPR13, gpr[13]);
297#ifndef CONFIG_PPC64 282#ifndef CONFIG_PPC64
298 DEFINE(GPR14, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[14])); 283 STACK_PT_REGS_OFFSET(GPR14, gpr[14]);
299#endif /* CONFIG_PPC64 */ 284#endif /* CONFIG_PPC64 */
300 /* 285 /*
301 * Note: these symbols include _ because they overlap with special 286 * Note: these symbols include _ because they overlap with special
302 * register names 287 * register names
303 */ 288 */
304 DEFINE(_NIP, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, nip)); 289 STACK_PT_REGS_OFFSET(_NIP, nip);
305 DEFINE(_MSR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, msr)); 290 STACK_PT_REGS_OFFSET(_MSR, msr);
306 DEFINE(_CTR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, ctr)); 291 STACK_PT_REGS_OFFSET(_CTR, ctr);
307 DEFINE(_LINK, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, link)); 292 STACK_PT_REGS_OFFSET(_LINK, link);
308 DEFINE(_CCR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, ccr)); 293 STACK_PT_REGS_OFFSET(_CCR, ccr);
309 DEFINE(_XER, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, xer)); 294 STACK_PT_REGS_OFFSET(_XER, xer);
310 DEFINE(_DAR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dar)); 295 STACK_PT_REGS_OFFSET(_DAR, dar);
311 DEFINE(_DSISR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dsisr)); 296 STACK_PT_REGS_OFFSET(_DSISR, dsisr);
312 DEFINE(ORIG_GPR3, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, orig_gpr3)); 297 STACK_PT_REGS_OFFSET(ORIG_GPR3, orig_gpr3);
313 DEFINE(RESULT, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, result)); 298 STACK_PT_REGS_OFFSET(RESULT, result);
314 DEFINE(_TRAP, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, trap)); 299 STACK_PT_REGS_OFFSET(_TRAP, trap);
315#ifndef CONFIG_PPC64 300#ifndef CONFIG_PPC64
316 /* 301 /*
317 * The PowerPC 400-class & Book-E processors have neither the DAR 302 * The PowerPC 400-class & Book-E processors have neither the DAR
@@ -319,10 +304,10 @@ int main(void)
319 * DEAR and ESR SPRs for such processors. For critical interrupts 304 * DEAR and ESR SPRs for such processors. For critical interrupts
320 * we use them to hold SRR0 and SRR1. 305 * we use them to hold SRR0 and SRR1.
321 */ 306 */
322 DEFINE(_DEAR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dar)); 307 STACK_PT_REGS_OFFSET(_DEAR, dar);
323 DEFINE(_ESR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dsisr)); 308 STACK_PT_REGS_OFFSET(_ESR, dsisr);
324#else /* CONFIG_PPC64 */ 309#else /* CONFIG_PPC64 */
325 DEFINE(SOFTE, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, softe)); 310 STACK_PT_REGS_OFFSET(SOFTE, softe);
326 311
327 /* These _only_ to be used with {PROM,RTAS}_FRAME_SIZE!!! */ 312 /* These _only_ to be used with {PROM,RTAS}_FRAME_SIZE!!! */
328 DEFINE(_SRR0, STACK_FRAME_OVERHEAD+sizeof(struct pt_regs)); 313 DEFINE(_SRR0, STACK_FRAME_OVERHEAD+sizeof(struct pt_regs));
@@ -351,17 +336,17 @@ int main(void)
351#endif 336#endif
352 337
353#ifndef CONFIG_PPC64 338#ifndef CONFIG_PPC64
354 DEFINE(MM_PGD, offsetof(struct mm_struct, pgd)); 339 OFFSET(MM_PGD, mm_struct, pgd);
355#endif /* ! CONFIG_PPC64 */ 340#endif /* ! CONFIG_PPC64 */
356 341
357 /* About the CPU features table */ 342 /* About the CPU features table */
358 DEFINE(CPU_SPEC_FEATURES, offsetof(struct cpu_spec, cpu_features)); 343 OFFSET(CPU_SPEC_FEATURES, cpu_spec, cpu_features);
359 DEFINE(CPU_SPEC_SETUP, offsetof(struct cpu_spec, cpu_setup)); 344 OFFSET(CPU_SPEC_SETUP, cpu_spec, cpu_setup);
360 DEFINE(CPU_SPEC_RESTORE, offsetof(struct cpu_spec, cpu_restore)); 345 OFFSET(CPU_SPEC_RESTORE, cpu_spec, cpu_restore);
361 346
362 DEFINE(pbe_address, offsetof(struct pbe, address)); 347 OFFSET(pbe_address, pbe, address);
363 DEFINE(pbe_orig_address, offsetof(struct pbe, orig_address)); 348 OFFSET(pbe_orig_address, pbe, orig_address);
364 DEFINE(pbe_next, offsetof(struct pbe, next)); 349 OFFSET(pbe_next, pbe, next);
365 350
366#ifndef CONFIG_PPC64 351#ifndef CONFIG_PPC64
367 DEFINE(TASK_SIZE, TASK_SIZE); 352 DEFINE(TASK_SIZE, TASK_SIZE);
@@ -369,40 +354,40 @@ int main(void)
369#endif /* ! CONFIG_PPC64 */ 354#endif /* ! CONFIG_PPC64 */
370 355
371 /* datapage offsets for use by vdso */ 356 /* datapage offsets for use by vdso */
372 DEFINE(CFG_TB_ORIG_STAMP, offsetof(struct vdso_data, tb_orig_stamp)); 357 OFFSET(CFG_TB_ORIG_STAMP, vdso_data, tb_orig_stamp);
373 DEFINE(CFG_TB_TICKS_PER_SEC, offsetof(struct vdso_data, tb_ticks_per_sec)); 358 OFFSET(CFG_TB_TICKS_PER_SEC, vdso_data, tb_ticks_per_sec);
374 DEFINE(CFG_TB_TO_XS, offsetof(struct vdso_data, tb_to_xs)); 359 OFFSET(CFG_TB_TO_XS, vdso_data, tb_to_xs);
375 DEFINE(CFG_TB_UPDATE_COUNT, offsetof(struct vdso_data, tb_update_count)); 360 OFFSET(CFG_TB_UPDATE_COUNT, vdso_data, tb_update_count);
376 DEFINE(CFG_TZ_MINUTEWEST, offsetof(struct vdso_data, tz_minuteswest)); 361 OFFSET(CFG_TZ_MINUTEWEST, vdso_data, tz_minuteswest);
377 DEFINE(CFG_TZ_DSTTIME, offsetof(struct vdso_data, tz_dsttime)); 362 OFFSET(CFG_TZ_DSTTIME, vdso_data, tz_dsttime);
378 DEFINE(CFG_SYSCALL_MAP32, offsetof(struct vdso_data, syscall_map_32)); 363 OFFSET(CFG_SYSCALL_MAP32, vdso_data, syscall_map_32);
379 DEFINE(WTOM_CLOCK_SEC, offsetof(struct vdso_data, wtom_clock_sec)); 364 OFFSET(WTOM_CLOCK_SEC, vdso_data, wtom_clock_sec);
380 DEFINE(WTOM_CLOCK_NSEC, offsetof(struct vdso_data, wtom_clock_nsec)); 365 OFFSET(WTOM_CLOCK_NSEC, vdso_data, wtom_clock_nsec);
381 DEFINE(STAMP_XTIME, offsetof(struct vdso_data, stamp_xtime)); 366 OFFSET(STAMP_XTIME, vdso_data, stamp_xtime);
382 DEFINE(STAMP_SEC_FRAC, offsetof(struct vdso_data, stamp_sec_fraction)); 367 OFFSET(STAMP_SEC_FRAC, vdso_data, stamp_sec_fraction);
383 DEFINE(CFG_ICACHE_BLOCKSZ, offsetof(struct vdso_data, icache_block_size)); 368 OFFSET(CFG_ICACHE_BLOCKSZ, vdso_data, icache_block_size);
384 DEFINE(CFG_DCACHE_BLOCKSZ, offsetof(struct vdso_data, dcache_block_size)); 369 OFFSET(CFG_DCACHE_BLOCKSZ, vdso_data, dcache_block_size);
385 DEFINE(CFG_ICACHE_LOGBLOCKSZ, offsetof(struct vdso_data, icache_log_block_size)); 370 OFFSET(CFG_ICACHE_LOGBLOCKSZ, vdso_data, icache_log_block_size);
386 DEFINE(CFG_DCACHE_LOGBLOCKSZ, offsetof(struct vdso_data, dcache_log_block_size)); 371 OFFSET(CFG_DCACHE_LOGBLOCKSZ, vdso_data, dcache_log_block_size);
387#ifdef CONFIG_PPC64 372#ifdef CONFIG_PPC64
388 DEFINE(CFG_SYSCALL_MAP64, offsetof(struct vdso_data, syscall_map_64)); 373 OFFSET(CFG_SYSCALL_MAP64, vdso_data, syscall_map_64);
389 DEFINE(TVAL64_TV_SEC, offsetof(struct timeval, tv_sec)); 374 OFFSET(TVAL64_TV_SEC, timeval, tv_sec);
390 DEFINE(TVAL64_TV_USEC, offsetof(struct timeval, tv_usec)); 375 OFFSET(TVAL64_TV_USEC, timeval, tv_usec);
391 DEFINE(TVAL32_TV_SEC, offsetof(struct compat_timeval, tv_sec)); 376 OFFSET(TVAL32_TV_SEC, compat_timeval, tv_sec);
392 DEFINE(TVAL32_TV_USEC, offsetof(struct compat_timeval, tv_usec)); 377 OFFSET(TVAL32_TV_USEC, compat_timeval, tv_usec);
393 DEFINE(TSPC64_TV_SEC, offsetof(struct timespec, tv_sec)); 378 OFFSET(TSPC64_TV_SEC, timespec, tv_sec);
394 DEFINE(TSPC64_TV_NSEC, offsetof(struct timespec, tv_nsec)); 379 OFFSET(TSPC64_TV_NSEC, timespec, tv_nsec);
395 DEFINE(TSPC32_TV_SEC, offsetof(struct compat_timespec, tv_sec)); 380 OFFSET(TSPC32_TV_SEC, compat_timespec, tv_sec);
396 DEFINE(TSPC32_TV_NSEC, offsetof(struct compat_timespec, tv_nsec)); 381 OFFSET(TSPC32_TV_NSEC, compat_timespec, tv_nsec);
397#else 382#else
398 DEFINE(TVAL32_TV_SEC, offsetof(struct timeval, tv_sec)); 383 OFFSET(TVAL32_TV_SEC, timeval, tv_sec);
399 DEFINE(TVAL32_TV_USEC, offsetof(struct timeval, tv_usec)); 384 OFFSET(TVAL32_TV_USEC, timeval, tv_usec);
400 DEFINE(TSPC32_TV_SEC, offsetof(struct timespec, tv_sec)); 385 OFFSET(TSPC32_TV_SEC, timespec, tv_sec);
401 DEFINE(TSPC32_TV_NSEC, offsetof(struct timespec, tv_nsec)); 386 OFFSET(TSPC32_TV_NSEC, timespec, tv_nsec);
402#endif 387#endif
403 /* timeval/timezone offsets for use by vdso */ 388 /* timeval/timezone offsets for use by vdso */
404 DEFINE(TZONE_TZ_MINWEST, offsetof(struct timezone, tz_minuteswest)); 389 OFFSET(TZONE_TZ_MINWEST, timezone, tz_minuteswest);
405 DEFINE(TZONE_TZ_DSTTIME, offsetof(struct timezone, tz_dsttime)); 390 OFFSET(TZONE_TZ_DSTTIME, timezone, tz_dsttime);
406 391
407 /* Other bits used by the vdso */ 392 /* Other bits used by the vdso */
408 DEFINE(CLOCK_REALTIME, CLOCK_REALTIME); 393 DEFINE(CLOCK_REALTIME, CLOCK_REALTIME);
@@ -422,170 +407,170 @@ int main(void)
422 DEFINE(PTE_SIZE, sizeof(pte_t)); 407 DEFINE(PTE_SIZE, sizeof(pte_t));
423 408
424#ifdef CONFIG_KVM 409#ifdef CONFIG_KVM
425 DEFINE(VCPU_HOST_STACK, offsetof(struct kvm_vcpu, arch.host_stack)); 410 OFFSET(VCPU_HOST_STACK, kvm_vcpu, arch.host_stack);
426 DEFINE(VCPU_HOST_PID, offsetof(struct kvm_vcpu, arch.host_pid)); 411 OFFSET(VCPU_HOST_PID, kvm_vcpu, arch.host_pid);
427 DEFINE(VCPU_GUEST_PID, offsetof(struct kvm_vcpu, arch.pid)); 412 OFFSET(VCPU_GUEST_PID, kvm_vcpu, arch.pid);
428 DEFINE(VCPU_GPRS, offsetof(struct kvm_vcpu, arch.gpr)); 413 OFFSET(VCPU_GPRS, kvm_vcpu, arch.gpr);
429 DEFINE(VCPU_VRSAVE, offsetof(struct kvm_vcpu, arch.vrsave)); 414 OFFSET(VCPU_VRSAVE, kvm_vcpu, arch.vrsave);
430 DEFINE(VCPU_FPRS, offsetof(struct kvm_vcpu, arch.fp.fpr)); 415 OFFSET(VCPU_FPRS, kvm_vcpu, arch.fp.fpr);
431#ifdef CONFIG_ALTIVEC 416#ifdef CONFIG_ALTIVEC
432 DEFINE(VCPU_VRS, offsetof(struct kvm_vcpu, arch.vr.vr)); 417 OFFSET(VCPU_VRS, kvm_vcpu, arch.vr.vr);
433#endif 418#endif
434 DEFINE(VCPU_XER, offsetof(struct kvm_vcpu, arch.xer)); 419 OFFSET(VCPU_XER, kvm_vcpu, arch.xer);
435 DEFINE(VCPU_CTR, offsetof(struct kvm_vcpu, arch.ctr)); 420 OFFSET(VCPU_CTR, kvm_vcpu, arch.ctr);
436 DEFINE(VCPU_LR, offsetof(struct kvm_vcpu, arch.lr)); 421 OFFSET(VCPU_LR, kvm_vcpu, arch.lr);
437#ifdef CONFIG_PPC_BOOK3S 422#ifdef CONFIG_PPC_BOOK3S
438 DEFINE(VCPU_TAR, offsetof(struct kvm_vcpu, arch.tar)); 423 OFFSET(VCPU_TAR, kvm_vcpu, arch.tar);
439#endif 424#endif
440 DEFINE(VCPU_CR, offsetof(struct kvm_vcpu, arch.cr)); 425 OFFSET(VCPU_CR, kvm_vcpu, arch.cr);
441 DEFINE(VCPU_PC, offsetof(struct kvm_vcpu, arch.pc)); 426 OFFSET(VCPU_PC, kvm_vcpu, arch.pc);
442#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 427#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
443 DEFINE(VCPU_MSR, offsetof(struct kvm_vcpu, arch.shregs.msr)); 428 OFFSET(VCPU_MSR, kvm_vcpu, arch.shregs.msr);
444 DEFINE(VCPU_SRR0, offsetof(struct kvm_vcpu, arch.shregs.srr0)); 429 OFFSET(VCPU_SRR0, kvm_vcpu, arch.shregs.srr0);
445 DEFINE(VCPU_SRR1, offsetof(struct kvm_vcpu, arch.shregs.srr1)); 430 OFFSET(VCPU_SRR1, kvm_vcpu, arch.shregs.srr1);
446 DEFINE(VCPU_SPRG0, offsetof(struct kvm_vcpu, arch.shregs.sprg0)); 431 OFFSET(VCPU_SPRG0, kvm_vcpu, arch.shregs.sprg0);
447 DEFINE(VCPU_SPRG1, offsetof(struct kvm_vcpu, arch.shregs.sprg1)); 432 OFFSET(VCPU_SPRG1, kvm_vcpu, arch.shregs.sprg1);
448 DEFINE(VCPU_SPRG2, offsetof(struct kvm_vcpu, arch.shregs.sprg2)); 433 OFFSET(VCPU_SPRG2, kvm_vcpu, arch.shregs.sprg2);
449 DEFINE(VCPU_SPRG3, offsetof(struct kvm_vcpu, arch.shregs.sprg3)); 434 OFFSET(VCPU_SPRG3, kvm_vcpu, arch.shregs.sprg3);
450#endif 435#endif
451#ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING 436#ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
452 DEFINE(VCPU_TB_RMENTRY, offsetof(struct kvm_vcpu, arch.rm_entry)); 437 OFFSET(VCPU_TB_RMENTRY, kvm_vcpu, arch.rm_entry);
453 DEFINE(VCPU_TB_RMINTR, offsetof(struct kvm_vcpu, arch.rm_intr)); 438 OFFSET(VCPU_TB_RMINTR, kvm_vcpu, arch.rm_intr);
454 DEFINE(VCPU_TB_RMEXIT, offsetof(struct kvm_vcpu, arch.rm_exit)); 439 OFFSET(VCPU_TB_RMEXIT, kvm_vcpu, arch.rm_exit);
455 DEFINE(VCPU_TB_GUEST, offsetof(struct kvm_vcpu, arch.guest_time)); 440 OFFSET(VCPU_TB_GUEST, kvm_vcpu, arch.guest_time);
456 DEFINE(VCPU_TB_CEDE, offsetof(struct kvm_vcpu, arch.cede_time)); 441 OFFSET(VCPU_TB_CEDE, kvm_vcpu, arch.cede_time);
457 DEFINE(VCPU_CUR_ACTIVITY, offsetof(struct kvm_vcpu, arch.cur_activity)); 442 OFFSET(VCPU_CUR_ACTIVITY, kvm_vcpu, arch.cur_activity);
458 DEFINE(VCPU_ACTIVITY_START, offsetof(struct kvm_vcpu, arch.cur_tb_start)); 443 OFFSET(VCPU_ACTIVITY_START, kvm_vcpu, arch.cur_tb_start);
459 DEFINE(TAS_SEQCOUNT, offsetof(struct kvmhv_tb_accumulator, seqcount)); 444 OFFSET(TAS_SEQCOUNT, kvmhv_tb_accumulator, seqcount);
460 DEFINE(TAS_TOTAL, offsetof(struct kvmhv_tb_accumulator, tb_total)); 445 OFFSET(TAS_TOTAL, kvmhv_tb_accumulator, tb_total);
461 DEFINE(TAS_MIN, offsetof(struct kvmhv_tb_accumulator, tb_min)); 446 OFFSET(TAS_MIN, kvmhv_tb_accumulator, tb_min);
462 DEFINE(TAS_MAX, offsetof(struct kvmhv_tb_accumulator, tb_max)); 447 OFFSET(TAS_MAX, kvmhv_tb_accumulator, tb_max);
463#endif 448#endif
464 DEFINE(VCPU_SHARED_SPRG3, offsetof(struct kvm_vcpu_arch_shared, sprg3)); 449 OFFSET(VCPU_SHARED_SPRG3, kvm_vcpu_arch_shared, sprg3);
465 DEFINE(VCPU_SHARED_SPRG4, offsetof(struct kvm_vcpu_arch_shared, sprg4)); 450 OFFSET(VCPU_SHARED_SPRG4, kvm_vcpu_arch_shared, sprg4);
466 DEFINE(VCPU_SHARED_SPRG5, offsetof(struct kvm_vcpu_arch_shared, sprg5)); 451 OFFSET(VCPU_SHARED_SPRG5, kvm_vcpu_arch_shared, sprg5);
467 DEFINE(VCPU_SHARED_SPRG6, offsetof(struct kvm_vcpu_arch_shared, sprg6)); 452 OFFSET(VCPU_SHARED_SPRG6, kvm_vcpu_arch_shared, sprg6);
468 DEFINE(VCPU_SHARED_SPRG7, offsetof(struct kvm_vcpu_arch_shared, sprg7)); 453 OFFSET(VCPU_SHARED_SPRG7, kvm_vcpu_arch_shared, sprg7);
469 DEFINE(VCPU_SHADOW_PID, offsetof(struct kvm_vcpu, arch.shadow_pid)); 454 OFFSET(VCPU_SHADOW_PID, kvm_vcpu, arch.shadow_pid);
470 DEFINE(VCPU_SHADOW_PID1, offsetof(struct kvm_vcpu, arch.shadow_pid1)); 455 OFFSET(VCPU_SHADOW_PID1, kvm_vcpu, arch.shadow_pid1);
471 DEFINE(VCPU_SHARED, offsetof(struct kvm_vcpu, arch.shared)); 456 OFFSET(VCPU_SHARED, kvm_vcpu, arch.shared);
472 DEFINE(VCPU_SHARED_MSR, offsetof(struct kvm_vcpu_arch_shared, msr)); 457 OFFSET(VCPU_SHARED_MSR, kvm_vcpu_arch_shared, msr);
473 DEFINE(VCPU_SHADOW_MSR, offsetof(struct kvm_vcpu, arch.shadow_msr)); 458 OFFSET(VCPU_SHADOW_MSR, kvm_vcpu, arch.shadow_msr);
474#if defined(CONFIG_PPC_BOOK3S_64) && defined(CONFIG_KVM_BOOK3S_PR_POSSIBLE) 459#if defined(CONFIG_PPC_BOOK3S_64) && defined(CONFIG_KVM_BOOK3S_PR_POSSIBLE)
475 DEFINE(VCPU_SHAREDBE, offsetof(struct kvm_vcpu, arch.shared_big_endian)); 460 OFFSET(VCPU_SHAREDBE, kvm_vcpu, arch.shared_big_endian);
476#endif 461#endif
477 462
478 DEFINE(VCPU_SHARED_MAS0, offsetof(struct kvm_vcpu_arch_shared, mas0)); 463 OFFSET(VCPU_SHARED_MAS0, kvm_vcpu_arch_shared, mas0);
479 DEFINE(VCPU_SHARED_MAS1, offsetof(struct kvm_vcpu_arch_shared, mas1)); 464 OFFSET(VCPU_SHARED_MAS1, kvm_vcpu_arch_shared, mas1);
480 DEFINE(VCPU_SHARED_MAS2, offsetof(struct kvm_vcpu_arch_shared, mas2)); 465 OFFSET(VCPU_SHARED_MAS2, kvm_vcpu_arch_shared, mas2);
481 DEFINE(VCPU_SHARED_MAS7_3, offsetof(struct kvm_vcpu_arch_shared, mas7_3)); 466 OFFSET(VCPU_SHARED_MAS7_3, kvm_vcpu_arch_shared, mas7_3);
482 DEFINE(VCPU_SHARED_MAS4, offsetof(struct kvm_vcpu_arch_shared, mas4)); 467 OFFSET(VCPU_SHARED_MAS4, kvm_vcpu_arch_shared, mas4);
483 DEFINE(VCPU_SHARED_MAS6, offsetof(struct kvm_vcpu_arch_shared, mas6)); 468 OFFSET(VCPU_SHARED_MAS6, kvm_vcpu_arch_shared, mas6);
484 469
485 DEFINE(VCPU_KVM, offsetof(struct kvm_vcpu, kvm)); 470 OFFSET(VCPU_KVM, kvm_vcpu, kvm);
486 DEFINE(KVM_LPID, offsetof(struct kvm, arch.lpid)); 471 OFFSET(KVM_LPID, kvm, arch.lpid);
487 472
488 /* book3s */ 473 /* book3s */
489#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 474#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
490 DEFINE(KVM_TLB_SETS, offsetof(struct kvm, arch.tlb_sets)); 475 OFFSET(KVM_TLB_SETS, kvm, arch.tlb_sets);
491 DEFINE(KVM_SDR1, offsetof(struct kvm, arch.sdr1)); 476 OFFSET(KVM_SDR1, kvm, arch.sdr1);
492 DEFINE(KVM_HOST_LPID, offsetof(struct kvm, arch.host_lpid)); 477 OFFSET(KVM_HOST_LPID, kvm, arch.host_lpid);
493 DEFINE(KVM_HOST_LPCR, offsetof(struct kvm, arch.host_lpcr)); 478 OFFSET(KVM_HOST_LPCR, kvm, arch.host_lpcr);
494 DEFINE(KVM_HOST_SDR1, offsetof(struct kvm, arch.host_sdr1)); 479 OFFSET(KVM_HOST_SDR1, kvm, arch.host_sdr1);
495 DEFINE(KVM_NEED_FLUSH, offsetof(struct kvm, arch.need_tlb_flush.bits)); 480 OFFSET(KVM_NEED_FLUSH, kvm, arch.need_tlb_flush.bits);
496 DEFINE(KVM_ENABLED_HCALLS, offsetof(struct kvm, arch.enabled_hcalls)); 481 OFFSET(KVM_ENABLED_HCALLS, kvm, arch.enabled_hcalls);
497 DEFINE(KVM_VRMA_SLB_V, offsetof(struct kvm, arch.vrma_slb_v)); 482 OFFSET(KVM_VRMA_SLB_V, kvm, arch.vrma_slb_v);
498 DEFINE(KVM_RADIX, offsetof(struct kvm, arch.radix)); 483 OFFSET(KVM_RADIX, kvm, arch.radix);
499 DEFINE(VCPU_DSISR, offsetof(struct kvm_vcpu, arch.shregs.dsisr)); 484 OFFSET(VCPU_DSISR, kvm_vcpu, arch.shregs.dsisr);
500 DEFINE(VCPU_DAR, offsetof(struct kvm_vcpu, arch.shregs.dar)); 485 OFFSET(VCPU_DAR, kvm_vcpu, arch.shregs.dar);
501 DEFINE(VCPU_VPA, offsetof(struct kvm_vcpu, arch.vpa.pinned_addr)); 486 OFFSET(VCPU_VPA, kvm_vcpu, arch.vpa.pinned_addr);
502 DEFINE(VCPU_VPA_DIRTY, offsetof(struct kvm_vcpu, arch.vpa.dirty)); 487 OFFSET(VCPU_VPA_DIRTY, kvm_vcpu, arch.vpa.dirty);
503 DEFINE(VCPU_HEIR, offsetof(struct kvm_vcpu, arch.emul_inst)); 488 OFFSET(VCPU_HEIR, kvm_vcpu, arch.emul_inst);
504 DEFINE(VCPU_CPU, offsetof(struct kvm_vcpu, cpu)); 489 OFFSET(VCPU_CPU, kvm_vcpu, cpu);
505 DEFINE(VCPU_THREAD_CPU, offsetof(struct kvm_vcpu, arch.thread_cpu)); 490 OFFSET(VCPU_THREAD_CPU, kvm_vcpu, arch.thread_cpu);
506#endif 491#endif
507#ifdef CONFIG_PPC_BOOK3S 492#ifdef CONFIG_PPC_BOOK3S
508 DEFINE(VCPU_PURR, offsetof(struct kvm_vcpu, arch.purr)); 493 OFFSET(VCPU_PURR, kvm_vcpu, arch.purr);
509 DEFINE(VCPU_SPURR, offsetof(struct kvm_vcpu, arch.spurr)); 494 OFFSET(VCPU_SPURR, kvm_vcpu, arch.spurr);
510 DEFINE(VCPU_IC, offsetof(struct kvm_vcpu, arch.ic)); 495 OFFSET(VCPU_IC, kvm_vcpu, arch.ic);
511 DEFINE(VCPU_DSCR, offsetof(struct kvm_vcpu, arch.dscr)); 496 OFFSET(VCPU_DSCR, kvm_vcpu, arch.dscr);
512 DEFINE(VCPU_AMR, offsetof(struct kvm_vcpu, arch.amr)); 497 OFFSET(VCPU_AMR, kvm_vcpu, arch.amr);
513 DEFINE(VCPU_UAMOR, offsetof(struct kvm_vcpu, arch.uamor)); 498 OFFSET(VCPU_UAMOR, kvm_vcpu, arch.uamor);
514 DEFINE(VCPU_IAMR, offsetof(struct kvm_vcpu, arch.iamr)); 499 OFFSET(VCPU_IAMR, kvm_vcpu, arch.iamr);
515 DEFINE(VCPU_CTRL, offsetof(struct kvm_vcpu, arch.ctrl)); 500 OFFSET(VCPU_CTRL, kvm_vcpu, arch.ctrl);
516 DEFINE(VCPU_DABR, offsetof(struct kvm_vcpu, arch.dabr)); 501 OFFSET(VCPU_DABR, kvm_vcpu, arch.dabr);
517 DEFINE(VCPU_DABRX, offsetof(struct kvm_vcpu, arch.dabrx)); 502 OFFSET(VCPU_DABRX, kvm_vcpu, arch.dabrx);
518 DEFINE(VCPU_DAWR, offsetof(struct kvm_vcpu, arch.dawr)); 503 OFFSET(VCPU_DAWR, kvm_vcpu, arch.dawr);
519 DEFINE(VCPU_DAWRX, offsetof(struct kvm_vcpu, arch.dawrx)); 504 OFFSET(VCPU_DAWRX, kvm_vcpu, arch.dawrx);
520 DEFINE(VCPU_CIABR, offsetof(struct kvm_vcpu, arch.ciabr)); 505 OFFSET(VCPU_CIABR, kvm_vcpu, arch.ciabr);
521 DEFINE(VCPU_HFLAGS, offsetof(struct kvm_vcpu, arch.hflags)); 506 OFFSET(VCPU_HFLAGS, kvm_vcpu, arch.hflags);
522 DEFINE(VCPU_DEC, offsetof(struct kvm_vcpu, arch.dec)); 507 OFFSET(VCPU_DEC, kvm_vcpu, arch.dec);
523 DEFINE(VCPU_DEC_EXPIRES, offsetof(struct kvm_vcpu, arch.dec_expires)); 508 OFFSET(VCPU_DEC_EXPIRES, kvm_vcpu, arch.dec_expires);
524 DEFINE(VCPU_PENDING_EXC, offsetof(struct kvm_vcpu, arch.pending_exceptions)); 509 OFFSET(VCPU_PENDING_EXC, kvm_vcpu, arch.pending_exceptions);
525 DEFINE(VCPU_CEDED, offsetof(struct kvm_vcpu, arch.ceded)); 510 OFFSET(VCPU_CEDED, kvm_vcpu, arch.ceded);
526 DEFINE(VCPU_PRODDED, offsetof(struct kvm_vcpu, arch.prodded)); 511 OFFSET(VCPU_PRODDED, kvm_vcpu, arch.prodded);
527 DEFINE(VCPU_MMCR, offsetof(struct kvm_vcpu, arch.mmcr)); 512 OFFSET(VCPU_MMCR, kvm_vcpu, arch.mmcr);
528 DEFINE(VCPU_PMC, offsetof(struct kvm_vcpu, arch.pmc)); 513 OFFSET(VCPU_PMC, kvm_vcpu, arch.pmc);
529 DEFINE(VCPU_SPMC, offsetof(struct kvm_vcpu, arch.spmc)); 514 OFFSET(VCPU_SPMC, kvm_vcpu, arch.spmc);
530 DEFINE(VCPU_SIAR, offsetof(struct kvm_vcpu, arch.siar)); 515 OFFSET(VCPU_SIAR, kvm_vcpu, arch.siar);
531 DEFINE(VCPU_SDAR, offsetof(struct kvm_vcpu, arch.sdar)); 516 OFFSET(VCPU_SDAR, kvm_vcpu, arch.sdar);
532 DEFINE(VCPU_SIER, offsetof(struct kvm_vcpu, arch.sier)); 517 OFFSET(VCPU_SIER, kvm_vcpu, arch.sier);
533 DEFINE(VCPU_SLB, offsetof(struct kvm_vcpu, arch.slb)); 518 OFFSET(VCPU_SLB, kvm_vcpu, arch.slb);
534 DEFINE(VCPU_SLB_MAX, offsetof(struct kvm_vcpu, arch.slb_max)); 519 OFFSET(VCPU_SLB_MAX, kvm_vcpu, arch.slb_max);
535 DEFINE(VCPU_SLB_NR, offsetof(struct kvm_vcpu, arch.slb_nr)); 520 OFFSET(VCPU_SLB_NR, kvm_vcpu, arch.slb_nr);
536 DEFINE(VCPU_FAULT_DSISR, offsetof(struct kvm_vcpu, arch.fault_dsisr)); 521 OFFSET(VCPU_FAULT_DSISR, kvm_vcpu, arch.fault_dsisr);
537 DEFINE(VCPU_FAULT_DAR, offsetof(struct kvm_vcpu, arch.fault_dar)); 522 OFFSET(VCPU_FAULT_DAR, kvm_vcpu, arch.fault_dar);
538 DEFINE(VCPU_FAULT_GPA, offsetof(struct kvm_vcpu, arch.fault_gpa)); 523 OFFSET(VCPU_FAULT_GPA, kvm_vcpu, arch.fault_gpa);
539 DEFINE(VCPU_INTR_MSR, offsetof(struct kvm_vcpu, arch.intr_msr)); 524 OFFSET(VCPU_INTR_MSR, kvm_vcpu, arch.intr_msr);
540 DEFINE(VCPU_LAST_INST, offsetof(struct kvm_vcpu, arch.last_inst)); 525 OFFSET(VCPU_LAST_INST, kvm_vcpu, arch.last_inst);
541 DEFINE(VCPU_TRAP, offsetof(struct kvm_vcpu, arch.trap)); 526 OFFSET(VCPU_TRAP, kvm_vcpu, arch.trap);
542 DEFINE(VCPU_CFAR, offsetof(struct kvm_vcpu, arch.cfar)); 527 OFFSET(VCPU_CFAR, kvm_vcpu, arch.cfar);
543 DEFINE(VCPU_PPR, offsetof(struct kvm_vcpu, arch.ppr)); 528 OFFSET(VCPU_PPR, kvm_vcpu, arch.ppr);
544 DEFINE(VCPU_FSCR, offsetof(struct kvm_vcpu, arch.fscr)); 529 OFFSET(VCPU_FSCR, kvm_vcpu, arch.fscr);
545 DEFINE(VCPU_PSPB, offsetof(struct kvm_vcpu, arch.pspb)); 530 OFFSET(VCPU_PSPB, kvm_vcpu, arch.pspb);
546 DEFINE(VCPU_EBBHR, offsetof(struct kvm_vcpu, arch.ebbhr)); 531 OFFSET(VCPU_EBBHR, kvm_vcpu, arch.ebbhr);
547 DEFINE(VCPU_EBBRR, offsetof(struct kvm_vcpu, arch.ebbrr)); 532 OFFSET(VCPU_EBBRR, kvm_vcpu, arch.ebbrr);
548 DEFINE(VCPU_BESCR, offsetof(struct kvm_vcpu, arch.bescr)); 533 OFFSET(VCPU_BESCR, kvm_vcpu, arch.bescr);
549 DEFINE(VCPU_CSIGR, offsetof(struct kvm_vcpu, arch.csigr)); 534 OFFSET(VCPU_CSIGR, kvm_vcpu, arch.csigr);
550 DEFINE(VCPU_TACR, offsetof(struct kvm_vcpu, arch.tacr)); 535 OFFSET(VCPU_TACR, kvm_vcpu, arch.tacr);
551 DEFINE(VCPU_TCSCR, offsetof(struct kvm_vcpu, arch.tcscr)); 536 OFFSET(VCPU_TCSCR, kvm_vcpu, arch.tcscr);
552 DEFINE(VCPU_ACOP, offsetof(struct kvm_vcpu, arch.acop)); 537 OFFSET(VCPU_ACOP, kvm_vcpu, arch.acop);
553 DEFINE(VCPU_WORT, offsetof(struct kvm_vcpu, arch.wort)); 538 OFFSET(VCPU_WORT, kvm_vcpu, arch.wort);
554 DEFINE(VCPU_TID, offsetof(struct kvm_vcpu, arch.tid)); 539 OFFSET(VCPU_TID, kvm_vcpu, arch.tid);
555 DEFINE(VCPU_PSSCR, offsetof(struct kvm_vcpu, arch.psscr)); 540 OFFSET(VCPU_PSSCR, kvm_vcpu, arch.psscr);
556 DEFINE(VCORE_ENTRY_EXIT, offsetof(struct kvmppc_vcore, entry_exit_map)); 541 OFFSET(VCORE_ENTRY_EXIT, kvmppc_vcore, entry_exit_map);
557 DEFINE(VCORE_IN_GUEST, offsetof(struct kvmppc_vcore, in_guest)); 542 OFFSET(VCORE_IN_GUEST, kvmppc_vcore, in_guest);
558 DEFINE(VCORE_NAPPING_THREADS, offsetof(struct kvmppc_vcore, napping_threads)); 543 OFFSET(VCORE_NAPPING_THREADS, kvmppc_vcore, napping_threads);
559 DEFINE(VCORE_KVM, offsetof(struct kvmppc_vcore, kvm)); 544 OFFSET(VCORE_KVM, kvmppc_vcore, kvm);
560 DEFINE(VCORE_TB_OFFSET, offsetof(struct kvmppc_vcore, tb_offset)); 545 OFFSET(VCORE_TB_OFFSET, kvmppc_vcore, tb_offset);
561 DEFINE(VCORE_LPCR, offsetof(struct kvmppc_vcore, lpcr)); 546 OFFSET(VCORE_LPCR, kvmppc_vcore, lpcr);
562 DEFINE(VCORE_PCR, offsetof(struct kvmppc_vcore, pcr)); 547 OFFSET(VCORE_PCR, kvmppc_vcore, pcr);
563 DEFINE(VCORE_DPDES, offsetof(struct kvmppc_vcore, dpdes)); 548 OFFSET(VCORE_DPDES, kvmppc_vcore, dpdes);
564 DEFINE(VCORE_VTB, offsetof(struct kvmppc_vcore, vtb)); 549 OFFSET(VCORE_VTB, kvmppc_vcore, vtb);
565 DEFINE(VCPU_SLB_E, offsetof(struct kvmppc_slb, orige)); 550 OFFSET(VCPU_SLB_E, kvmppc_slb, orige);
566 DEFINE(VCPU_SLB_V, offsetof(struct kvmppc_slb, origv)); 551 OFFSET(VCPU_SLB_V, kvmppc_slb, origv);
567 DEFINE(VCPU_SLB_SIZE, sizeof(struct kvmppc_slb)); 552 DEFINE(VCPU_SLB_SIZE, sizeof(struct kvmppc_slb));
568#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 553#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
569 DEFINE(VCPU_TFHAR, offsetof(struct kvm_vcpu, arch.tfhar)); 554 OFFSET(VCPU_TFHAR, kvm_vcpu, arch.tfhar);
570 DEFINE(VCPU_TFIAR, offsetof(struct kvm_vcpu, arch.tfiar)); 555 OFFSET(VCPU_TFIAR, kvm_vcpu, arch.tfiar);
571 DEFINE(VCPU_TEXASR, offsetof(struct kvm_vcpu, arch.texasr)); 556 OFFSET(VCPU_TEXASR, kvm_vcpu, arch.texasr);
572 DEFINE(VCPU_GPR_TM, offsetof(struct kvm_vcpu, arch.gpr_tm)); 557 OFFSET(VCPU_GPR_TM, kvm_vcpu, arch.gpr_tm);
573 DEFINE(VCPU_FPRS_TM, offsetof(struct kvm_vcpu, arch.fp_tm.fpr)); 558 OFFSET(VCPU_FPRS_TM, kvm_vcpu, arch.fp_tm.fpr);
574 DEFINE(VCPU_VRS_TM, offsetof(struct kvm_vcpu, arch.vr_tm.vr)); 559 OFFSET(VCPU_VRS_TM, kvm_vcpu, arch.vr_tm.vr);
575 DEFINE(VCPU_VRSAVE_TM, offsetof(struct kvm_vcpu, arch.vrsave_tm)); 560 OFFSET(VCPU_VRSAVE_TM, kvm_vcpu, arch.vrsave_tm);
576 DEFINE(VCPU_CR_TM, offsetof(struct kvm_vcpu, arch.cr_tm)); 561 OFFSET(VCPU_CR_TM, kvm_vcpu, arch.cr_tm);
577 DEFINE(VCPU_XER_TM, offsetof(struct kvm_vcpu, arch.xer_tm)); 562 OFFSET(VCPU_XER_TM, kvm_vcpu, arch.xer_tm);
578 DEFINE(VCPU_LR_TM, offsetof(struct kvm_vcpu, arch.lr_tm)); 563 OFFSET(VCPU_LR_TM, kvm_vcpu, arch.lr_tm);
579 DEFINE(VCPU_CTR_TM, offsetof(struct kvm_vcpu, arch.ctr_tm)); 564 OFFSET(VCPU_CTR_TM, kvm_vcpu, arch.ctr_tm);
580 DEFINE(VCPU_AMR_TM, offsetof(struct kvm_vcpu, arch.amr_tm)); 565 OFFSET(VCPU_AMR_TM, kvm_vcpu, arch.amr_tm);
581 DEFINE(VCPU_PPR_TM, offsetof(struct kvm_vcpu, arch.ppr_tm)); 566 OFFSET(VCPU_PPR_TM, kvm_vcpu, arch.ppr_tm);
582 DEFINE(VCPU_DSCR_TM, offsetof(struct kvm_vcpu, arch.dscr_tm)); 567 OFFSET(VCPU_DSCR_TM, kvm_vcpu, arch.dscr_tm);
583 DEFINE(VCPU_TAR_TM, offsetof(struct kvm_vcpu, arch.tar_tm)); 568 OFFSET(VCPU_TAR_TM, kvm_vcpu, arch.tar_tm);
584#endif 569#endif
585 570
586#ifdef CONFIG_PPC_BOOK3S_64 571#ifdef CONFIG_PPC_BOOK3S_64
587#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE 572#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
588 DEFINE(PACA_SVCPU, offsetof(struct paca_struct, shadow_vcpu)); 573 OFFSET(PACA_SVCPU, paca_struct, shadow_vcpu);
589# define SVCPU_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, shadow_vcpu.f)) 574# define SVCPU_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, shadow_vcpu.f))
590#else 575#else
591# define SVCPU_FIELD(x, f) 576# define SVCPU_FIELD(x, f)
@@ -668,11 +653,11 @@ int main(void)
668 HSTATE_FIELD(HSTATE_DECEXP, dec_expires); 653 HSTATE_FIELD(HSTATE_DECEXP, dec_expires);
669 HSTATE_FIELD(HSTATE_SPLIT_MODE, kvm_split_mode); 654 HSTATE_FIELD(HSTATE_SPLIT_MODE, kvm_split_mode);
670 DEFINE(IPI_PRIORITY, IPI_PRIORITY); 655 DEFINE(IPI_PRIORITY, IPI_PRIORITY);
671 DEFINE(KVM_SPLIT_RPR, offsetof(struct kvm_split_mode, rpr)); 656 OFFSET(KVM_SPLIT_RPR, kvm_split_mode, rpr);
672 DEFINE(KVM_SPLIT_PMMAR, offsetof(struct kvm_split_mode, pmmar)); 657 OFFSET(KVM_SPLIT_PMMAR, kvm_split_mode, pmmar);
673 DEFINE(KVM_SPLIT_LDBAR, offsetof(struct kvm_split_mode, ldbar)); 658 OFFSET(KVM_SPLIT_LDBAR, kvm_split_mode, ldbar);
674 DEFINE(KVM_SPLIT_DO_NAP, offsetof(struct kvm_split_mode, do_nap)); 659 OFFSET(KVM_SPLIT_DO_NAP, kvm_split_mode, do_nap);
675 DEFINE(KVM_SPLIT_NAPPED, offsetof(struct kvm_split_mode, napped)); 660 OFFSET(KVM_SPLIT_NAPPED, kvm_split_mode, napped);
676#endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */ 661#endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */
677 662
678#ifdef CONFIG_PPC_BOOK3S_64 663#ifdef CONFIG_PPC_BOOK3S_64
@@ -682,32 +667,27 @@ int main(void)
682#endif /* CONFIG_PPC_BOOK3S_64 */ 667#endif /* CONFIG_PPC_BOOK3S_64 */
683 668
684#else /* CONFIG_PPC_BOOK3S */ 669#else /* CONFIG_PPC_BOOK3S */
685 DEFINE(VCPU_CR, offsetof(struct kvm_vcpu, arch.cr)); 670 OFFSET(VCPU_CR, kvm_vcpu, arch.cr);
686 DEFINE(VCPU_XER, offsetof(struct kvm_vcpu, arch.xer)); 671 OFFSET(VCPU_XER, kvm_vcpu, arch.xer);
687 DEFINE(VCPU_LR, offsetof(struct kvm_vcpu, arch.lr)); 672 OFFSET(VCPU_LR, kvm_vcpu, arch.lr);
688 DEFINE(VCPU_CTR, offsetof(struct kvm_vcpu, arch.ctr)); 673 OFFSET(VCPU_CTR, kvm_vcpu, arch.ctr);
689 DEFINE(VCPU_PC, offsetof(struct kvm_vcpu, arch.pc)); 674 OFFSET(VCPU_PC, kvm_vcpu, arch.pc);
690 DEFINE(VCPU_SPRG9, offsetof(struct kvm_vcpu, arch.sprg9)); 675 OFFSET(VCPU_SPRG9, kvm_vcpu, arch.sprg9);
691 DEFINE(VCPU_LAST_INST, offsetof(struct kvm_vcpu, arch.last_inst)); 676 OFFSET(VCPU_LAST_INST, kvm_vcpu, arch.last_inst);
692 DEFINE(VCPU_FAULT_DEAR, offsetof(struct kvm_vcpu, arch.fault_dear)); 677 OFFSET(VCPU_FAULT_DEAR, kvm_vcpu, arch.fault_dear);
693 DEFINE(VCPU_FAULT_ESR, offsetof(struct kvm_vcpu, arch.fault_esr)); 678 OFFSET(VCPU_FAULT_ESR, kvm_vcpu, arch.fault_esr);
694 DEFINE(VCPU_CRIT_SAVE, offsetof(struct kvm_vcpu, arch.crit_save)); 679 OFFSET(VCPU_CRIT_SAVE, kvm_vcpu, arch.crit_save);
695#endif /* CONFIG_PPC_BOOK3S */ 680#endif /* CONFIG_PPC_BOOK3S */
696#endif /* CONFIG_KVM */ 681#endif /* CONFIG_KVM */
697 682
698#ifdef CONFIG_KVM_GUEST 683#ifdef CONFIG_KVM_GUEST
699 DEFINE(KVM_MAGIC_SCRATCH1, offsetof(struct kvm_vcpu_arch_shared, 684 OFFSET(KVM_MAGIC_SCRATCH1, kvm_vcpu_arch_shared, scratch1);
700 scratch1)); 685 OFFSET(KVM_MAGIC_SCRATCH2, kvm_vcpu_arch_shared, scratch2);
701 DEFINE(KVM_MAGIC_SCRATCH2, offsetof(struct kvm_vcpu_arch_shared, 686 OFFSET(KVM_MAGIC_SCRATCH3, kvm_vcpu_arch_shared, scratch3);
702 scratch2)); 687 OFFSET(KVM_MAGIC_INT, kvm_vcpu_arch_shared, int_pending);
703 DEFINE(KVM_MAGIC_SCRATCH3, offsetof(struct kvm_vcpu_arch_shared, 688 OFFSET(KVM_MAGIC_MSR, kvm_vcpu_arch_shared, msr);
704 scratch3)); 689 OFFSET(KVM_MAGIC_CRITICAL, kvm_vcpu_arch_shared, critical);
705 DEFINE(KVM_MAGIC_INT, offsetof(struct kvm_vcpu_arch_shared, 690 OFFSET(KVM_MAGIC_SR, kvm_vcpu_arch_shared, sr);
706 int_pending));
707 DEFINE(KVM_MAGIC_MSR, offsetof(struct kvm_vcpu_arch_shared, msr));
708 DEFINE(KVM_MAGIC_CRITICAL, offsetof(struct kvm_vcpu_arch_shared,
709 critical));
710 DEFINE(KVM_MAGIC_SR, offsetof(struct kvm_vcpu_arch_shared, sr));
711#endif 691#endif
712 692
713#ifdef CONFIG_44x 693#ifdef CONFIG_44x
@@ -716,45 +696,37 @@ int main(void)
716#endif 696#endif
717#ifdef CONFIG_PPC_FSL_BOOK3E 697#ifdef CONFIG_PPC_FSL_BOOK3E
718 DEFINE(TLBCAM_SIZE, sizeof(struct tlbcam)); 698 DEFINE(TLBCAM_SIZE, sizeof(struct tlbcam));
719 DEFINE(TLBCAM_MAS0, offsetof(struct tlbcam, MAS0)); 699 OFFSET(TLBCAM_MAS0, tlbcam, MAS0);
720 DEFINE(TLBCAM_MAS1, offsetof(struct tlbcam, MAS1)); 700 OFFSET(TLBCAM_MAS1, tlbcam, MAS1);
721 DEFINE(TLBCAM_MAS2, offsetof(struct tlbcam, MAS2)); 701 OFFSET(TLBCAM_MAS2, tlbcam, MAS2);
722 DEFINE(TLBCAM_MAS3, offsetof(struct tlbcam, MAS3)); 702 OFFSET(TLBCAM_MAS3, tlbcam, MAS3);
723 DEFINE(TLBCAM_MAS7, offsetof(struct tlbcam, MAS7)); 703 OFFSET(TLBCAM_MAS7, tlbcam, MAS7);
724#endif 704#endif
725 705
726#if defined(CONFIG_KVM) && defined(CONFIG_SPE) 706#if defined(CONFIG_KVM) && defined(CONFIG_SPE)
727 DEFINE(VCPU_EVR, offsetof(struct kvm_vcpu, arch.evr[0])); 707 OFFSET(VCPU_EVR, kvm_vcpu, arch.evr[0]);
728 DEFINE(VCPU_ACC, offsetof(struct kvm_vcpu, arch.acc)); 708 OFFSET(VCPU_ACC, kvm_vcpu, arch.acc);
729 DEFINE(VCPU_SPEFSCR, offsetof(struct kvm_vcpu, arch.spefscr)); 709 OFFSET(VCPU_SPEFSCR, kvm_vcpu, arch.spefscr);
730 DEFINE(VCPU_HOST_SPEFSCR, offsetof(struct kvm_vcpu, arch.host_spefscr)); 710 OFFSET(VCPU_HOST_SPEFSCR, kvm_vcpu, arch.host_spefscr);
731#endif 711#endif
732 712
733#ifdef CONFIG_KVM_BOOKE_HV 713#ifdef CONFIG_KVM_BOOKE_HV
734 DEFINE(VCPU_HOST_MAS4, offsetof(struct kvm_vcpu, arch.host_mas4)); 714 OFFSET(VCPU_HOST_MAS4, kvm_vcpu, arch.host_mas4);
735 DEFINE(VCPU_HOST_MAS6, offsetof(struct kvm_vcpu, arch.host_mas6)); 715 OFFSET(VCPU_HOST_MAS6, kvm_vcpu, arch.host_mas6);
736#endif 716#endif
737 717
738#ifdef CONFIG_KVM_EXIT_TIMING 718#ifdef CONFIG_KVM_EXIT_TIMING
739 DEFINE(VCPU_TIMING_EXIT_TBU, offsetof(struct kvm_vcpu, 719 OFFSET(VCPU_TIMING_EXIT_TBU, kvm_vcpu, arch.timing_exit.tv32.tbu);
740 arch.timing_exit.tv32.tbu)); 720 OFFSET(VCPU_TIMING_EXIT_TBL, kvm_vcpu, arch.timing_exit.tv32.tbl);
741 DEFINE(VCPU_TIMING_EXIT_TBL, offsetof(struct kvm_vcpu, 721 OFFSET(VCPU_TIMING_LAST_ENTER_TBU, kvm_vcpu, arch.timing_last_enter.tv32.tbu);
742 arch.timing_exit.tv32.tbl)); 722 OFFSET(VCPU_TIMING_LAST_ENTER_TBL, kvm_vcpu, arch.timing_last_enter.tv32.tbl);
743 DEFINE(VCPU_TIMING_LAST_ENTER_TBU, offsetof(struct kvm_vcpu,
744 arch.timing_last_enter.tv32.tbu));
745 DEFINE(VCPU_TIMING_LAST_ENTER_TBL, offsetof(struct kvm_vcpu,
746 arch.timing_last_enter.tv32.tbl));
747#endif 723#endif
748 724
749#ifdef CONFIG_PPC_POWERNV 725#ifdef CONFIG_PPC_POWERNV
750 DEFINE(PACA_CORE_IDLE_STATE_PTR, 726 OFFSET(PACA_CORE_IDLE_STATE_PTR, paca_struct, core_idle_state_ptr);
751 offsetof(struct paca_struct, core_idle_state_ptr)); 727 OFFSET(PACA_THREAD_IDLE_STATE, paca_struct, thread_idle_state);
752 DEFINE(PACA_THREAD_IDLE_STATE, 728 OFFSET(PACA_THREAD_MASK, paca_struct, thread_mask);
753 offsetof(struct paca_struct, thread_idle_state)); 729 OFFSET(PACA_SUBCORE_SIBLING_MASK, paca_struct, subcore_sibling_mask);
754 DEFINE(PACA_THREAD_MASK,
755 offsetof(struct paca_struct, thread_mask));
756 DEFINE(PACA_SUBCORE_SIBLING_MASK,
757 offsetof(struct paca_struct, subcore_sibling_mask));
758#endif 730#endif
759 731
760 DEFINE(PPC_DBELL_SERVER, PPC_DBELL_SERVER); 732 DEFINE(PPC_DBELL_SERVER, PPC_DBELL_SERVER);
diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S
index 917188615bf5..7fe8c79e6937 100644
--- a/arch/powerpc/kernel/cpu_setup_power.S
+++ b/arch/powerpc/kernel/cpu_setup_power.S
@@ -101,6 +101,8 @@ _GLOBAL(__setup_cpu_power9)
101 mfspr r3,SPRN_LPCR 101 mfspr r3,SPRN_LPCR
102 LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE) 102 LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE)
103 or r3, r3, r4 103 or r3, r3, r4
104 LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
105 andc r3, r3, r4
104 bl __init_LPCR 106 bl __init_LPCR
105 bl __init_HFSCR 107 bl __init_HFSCR
106 bl __init_tlb_power9 108 bl __init_tlb_power9
@@ -122,6 +124,8 @@ _GLOBAL(__restore_cpu_power9)
122 mfspr r3,SPRN_LPCR 124 mfspr r3,SPRN_LPCR
123 LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE) 125 LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE)
124 or r3, r3, r4 126 or r3, r3, r4
127 LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
128 andc r3, r3, r4
125 bl __init_LPCR 129 bl __init_LPCR
126 bl __init_HFSCR 130 bl __init_HFSCR
127 bl __init_tlb_power9 131 bl __init_tlb_power9
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 6a82ef039c50..bb7a1890aeb7 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -386,6 +386,23 @@ static struct cpu_spec __initdata cpu_specs[] = {
386 .machine_check_early = __machine_check_early_realmode_p8, 386 .machine_check_early = __machine_check_early_realmode_p8,
387 .platform = "power8", 387 .platform = "power8",
388 }, 388 },
389 { /* 3.00-compliant processor, i.e. Power9 "architected" mode */
390 .pvr_mask = 0xffffffff,
391 .pvr_value = 0x0f000005,
392 .cpu_name = "POWER9 (architected)",
393 .cpu_features = CPU_FTRS_POWER9,
394 .cpu_user_features = COMMON_USER_POWER9,
395 .cpu_user_features2 = COMMON_USER2_POWER9,
396 .mmu_features = MMU_FTRS_POWER9,
397 .icache_bsize = 128,
398 .dcache_bsize = 128,
399 .oprofile_type = PPC_OPROFILE_INVALID,
400 .oprofile_cpu_type = "ppc64/ibm-compat-v1",
401 .cpu_setup = __setup_cpu_power9,
402 .cpu_restore = __restore_cpu_power9,
403 .flush_tlb = __flush_tlb_power9,
404 .platform = "power9",
405 },
389 { /* Power7 */ 406 { /* Power7 */
390 .pvr_mask = 0xffff0000, 407 .pvr_mask = 0xffff0000,
391 .pvr_value = 0x003f0000, 408 .pvr_value = 0x003f0000,
diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
index 3841d749a430..a38600949f3a 100644
--- a/arch/powerpc/kernel/entry_32.S
+++ b/arch/powerpc/kernel/entry_32.S
@@ -205,6 +205,9 @@ transfer_to_handler_cont:
205 mflr r9 205 mflr r9
206 lwz r11,0(r9) /* virtual address of handler */ 206 lwz r11,0(r9) /* virtual address of handler */
207 lwz r9,4(r9) /* where to go when done */ 207 lwz r9,4(r9) /* where to go when done */
208#ifdef CONFIG_PPC_8xx_PERF_EVENT
209 mtspr SPRN_NRI, r0
210#endif
208#ifdef CONFIG_TRACE_IRQFLAGS 211#ifdef CONFIG_TRACE_IRQFLAGS
209 lis r12,reenable_mmu@h 212 lis r12,reenable_mmu@h
210 ori r12,r12,reenable_mmu@l 213 ori r12,r12,reenable_mmu@l
@@ -292,7 +295,9 @@ stack_ovf:
292 lis r9,StackOverflow@ha 295 lis r9,StackOverflow@ha
293 addi r9,r9,StackOverflow@l 296 addi r9,r9,StackOverflow@l
294 LOAD_MSR_KERNEL(r10,MSR_KERNEL) 297 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
295 FIX_SRR1(r10,r12) 298#ifdef CONFIG_PPC_8xx_PERF_EVENT
299 mtspr SPRN_NRI, r0
300#endif
296 mtspr SPRN_SRR0,r9 301 mtspr SPRN_SRR0,r9
297 mtspr SPRN_SRR1,r10 302 mtspr SPRN_SRR1,r10
298 SYNC 303 SYNC
@@ -417,9 +422,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
417 mtlr r4 422 mtlr r4
418 mtcr r5 423 mtcr r5
419 lwz r7,_NIP(r1) 424 lwz r7,_NIP(r1)
420 FIX_SRR1(r8, r0)
421 lwz r2,GPR2(r1) 425 lwz r2,GPR2(r1)
422 lwz r1,GPR1(r1) 426 lwz r1,GPR1(r1)
427#ifdef CONFIG_PPC_8xx_PERF_EVENT
428 mtspr SPRN_NRI, r0
429#endif
423 mtspr SPRN_SRR0,r7 430 mtspr SPRN_SRR0,r7
424 mtspr SPRN_SRR1,r8 431 mtspr SPRN_SRR1,r8
425 SYNC 432 SYNC
@@ -699,6 +706,9 @@ fast_exception_return:
699 lwz r10,_LINK(r11) 706 lwz r10,_LINK(r11)
700 mtlr r10 707 mtlr r10
701 REST_GPR(10, r11) 708 REST_GPR(10, r11)
709#ifdef CONFIG_PPC_8xx_PERF_EVENT
710 mtspr SPRN_NRI, r0
711#endif
702 mtspr SPRN_SRR1,r9 712 mtspr SPRN_SRR1,r9
703 mtspr SPRN_SRR0,r12 713 mtspr SPRN_SRR0,r12
704 REST_GPR(9, r11) 714 REST_GPR(9, r11)
@@ -947,7 +957,9 @@ END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
947 .globl exc_exit_restart 957 .globl exc_exit_restart
948exc_exit_restart: 958exc_exit_restart:
949 lwz r12,_NIP(r1) 959 lwz r12,_NIP(r1)
950 FIX_SRR1(r9,r10) 960#ifdef CONFIG_PPC_8xx_PERF_EVENT
961 mtspr SPRN_NRI, r0
962#endif
951 mtspr SPRN_SRR0,r12 963 mtspr SPRN_SRR0,r12
952 mtspr SPRN_SRR1,r9 964 mtspr SPRN_SRR1,r9
953 REST_4GPRS(9, r1) 965 REST_4GPRS(9, r1)
@@ -1290,7 +1302,6 @@ _GLOBAL(enter_rtas)
12901: tophys(r9,r1) 13021: tophys(r9,r1)
1291 lwz r8,INT_FRAME_SIZE+4(r9) /* get return address */ 1303 lwz r8,INT_FRAME_SIZE+4(r9) /* get return address */
1292 lwz r9,8(r9) /* original msr value */ 1304 lwz r9,8(r9) /* original msr value */
1293 FIX_SRR1(r9,r0)
1294 addi r1,r1,INT_FRAME_SIZE 1305 addi r1,r1,INT_FRAME_SIZE
1295 li r0,0 1306 li r0,0
1296 mtspr SPRN_SPRG_RTAS,r0 1307 mtspr SPRN_SPRG_RTAS,r0
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index 9d963547d243..1607be7c0ef2 100644
--- a/arch/powerpc/kernel/head_32.S
+++ b/arch/powerpc/kernel/head_32.S
@@ -869,7 +869,6 @@ __secondary_start:
869 869
870 /* enable MMU and jump to start_secondary */ 870 /* enable MMU and jump to start_secondary */
871 li r4,MSR_KERNEL 871 li r4,MSR_KERNEL
872 FIX_SRR1(r4,r5)
873 lis r3,start_secondary@h 872 lis r3,start_secondary@h
874 ori r3,r3,start_secondary@l 873 ori r3,r3,start_secondary@l
875 mtspr SPRN_SRR0,r3 874 mtspr SPRN_SRR0,r3
@@ -977,7 +976,6 @@ start_here:
977 ori r4,r4,2f@l 976 ori r4,r4,2f@l
978 tophys(r4,r4) 977 tophys(r4,r4)
979 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR) 978 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
980 FIX_SRR1(r3,r5)
981 mtspr SPRN_SRR0,r4 979 mtspr SPRN_SRR0,r4
982 mtspr SPRN_SRR1,r3 980 mtspr SPRN_SRR1,r3
983 SYNC 981 SYNC
@@ -1001,7 +999,6 @@ start_here:
1001 999
1002/* Now turn on the MMU for real! */ 1000/* Now turn on the MMU for real! */
1003 li r4,MSR_KERNEL 1001 li r4,MSR_KERNEL
1004 FIX_SRR1(r4,r5)
1005 lis r3,start_kernel@h 1002 lis r3,start_kernel@h
1006 ori r3,r3,start_kernel@l 1003 ori r3,r3,start_kernel@l
1007 mtspr SPRN_SRR0,r3 1004 mtspr SPRN_SRR0,r3
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 1a9c99d3e5d8..c032fe8c2d26 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -329,6 +329,12 @@ InstructionTLBMiss:
329 mtspr SPRN_SPRG_SCRATCH2, r3 329 mtspr SPRN_SPRG_SCRATCH2, r3
330#endif 330#endif
331 EXCEPTION_PROLOG_0 331 EXCEPTION_PROLOG_0
332#ifdef CONFIG_PPC_8xx_PERF_EVENT
333 lis r10, (itlb_miss_counter - PAGE_OFFSET)@ha
334 lwz r11, (itlb_miss_counter - PAGE_OFFSET)@l(r10)
335 addi r11, r11, 1
336 stw r11, (itlb_miss_counter - PAGE_OFFSET)@l(r10)
337#endif
332 338
333 /* If we are faulting a kernel address, we have to use the 339 /* If we are faulting a kernel address, we have to use the
334 * kernel page tables. 340 * kernel page tables.
@@ -429,6 +435,12 @@ InstructionTLBMiss:
429DataStoreTLBMiss: 435DataStoreTLBMiss:
430 mtspr SPRN_SPRG_SCRATCH2, r3 436 mtspr SPRN_SPRG_SCRATCH2, r3
431 EXCEPTION_PROLOG_0 437 EXCEPTION_PROLOG_0
438#ifdef CONFIG_PPC_8xx_PERF_EVENT
439 lis r10, (dtlb_miss_counter - PAGE_OFFSET)@ha
440 lwz r11, (dtlb_miss_counter - PAGE_OFFSET)@l(r10)
441 addi r11, r11, 1
442 stw r11, (dtlb_miss_counter - PAGE_OFFSET)@l(r10)
443#endif
432 mfcr r3 444 mfcr r3
433 445
434 /* If we are faulting a kernel address, we have to use the 446 /* If we are faulting a kernel address, we have to use the
@@ -561,6 +573,7 @@ InstructionTLBError:
561 andis. r10,r5,0x4000 573 andis. r10,r5,0x4000
562 beq+ 1f 574 beq+ 1f
563 tlbie r4 575 tlbie r4
576itlbie:
564 /* 0x400 is InstructionAccess exception, needed by bad_page_fault() */ 577 /* 0x400 is InstructionAccess exception, needed by bad_page_fault() */
5651: EXC_XFER_LITE(0x400, handle_page_fault) 5781: EXC_XFER_LITE(0x400, handle_page_fault)
566 579
@@ -585,6 +598,7 @@ DARFixed:/* Return from dcbx instruction bug workaround */
585 andis. r10,r5,0x4000 598 andis. r10,r5,0x4000
586 beq+ 1f 599 beq+ 1f
587 tlbie r4 600 tlbie r4
601dtlbie:
5881: li r10,RPN_PATTERN 6021: li r10,RPN_PATTERN
589 mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */ 603 mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */
590 /* 0x300 is DataAccess exception, needed by bad_page_fault() */ 604 /* 0x300 is DataAccess exception, needed by bad_page_fault() */
@@ -602,8 +616,43 @@ DARFixed:/* Return from dcbx instruction bug workaround */
602 * support of breakpoints and such. Someday I will get around to 616 * support of breakpoints and such. Someday I will get around to
603 * using them. 617 * using them.
604 */ 618 */
605 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE) 619 . = 0x1c00
620DataBreakpoint:
621 EXCEPTION_PROLOG_0
622 mfcr r10
623 mfspr r11, SPRN_SRR0
624 cmplwi cr0, r11, (dtlbie - PAGE_OFFSET)@l
625 cmplwi cr7, r11, (itlbie - PAGE_OFFSET)@l
626 beq- cr0, 11f
627 beq- cr7, 11f
628 EXCEPTION_PROLOG_1
629 EXCEPTION_PROLOG_2
630 addi r3,r1,STACK_FRAME_OVERHEAD
631 mfspr r4,SPRN_BAR
632 stw r4,_DAR(r11)
633 mfspr r5,SPRN_DSISR
634 EXC_XFER_EE(0x1c00, do_break)
63511:
636 mtcr r10
637 EXCEPTION_EPILOG_0
638 rfi
639
640#ifdef CONFIG_PPC_8xx_PERF_EVENT
641 . = 0x1d00
642InstructionBreakpoint:
643 EXCEPTION_PROLOG_0
644 lis r10, (instruction_counter - PAGE_OFFSET)@ha
645 lwz r11, (instruction_counter - PAGE_OFFSET)@l(r10)
646 addi r11, r11, -1
647 stw r11, (instruction_counter - PAGE_OFFSET)@l(r10)
648 lis r10, 0xffff
649 ori r10, r10, 0x01
650 mtspr SPRN_COUNTA, r10
651 EXCEPTION_EPILOG_0
652 rfi
653#else
606 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE) 654 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
655#endif
607 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE) 656 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
608 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE) 657 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
609 658
@@ -977,6 +1026,14 @@ initial_mmu:
977 lis r8, IDC_ENABLE@h 1026 lis r8, IDC_ENABLE@h
978 mtspr SPRN_DC_CST, r8 1027 mtspr SPRN_DC_CST, r8
979#endif 1028#endif
1029 /* Disable debug mode entry on breakpoints */
1030 mfspr r8, SPRN_DER
1031#ifdef CONFIG_PPC_8xx_PERF_EVENT
1032 rlwinm r8, r8, 0, ~0xc
1033#else
1034 rlwinm r8, r8, 0, ~0x8
1035#endif
1036 mtspr SPRN_DER, r8
980 blr 1037 blr
981 1038
982 1039
@@ -1010,3 +1067,16 @@ cpu6_errata_word:
1010 .space 16 1067 .space 16
1011#endif 1068#endif
1012 1069
1070#ifdef CONFIG_PPC_8xx_PERF_EVENT
1071 .globl itlb_miss_counter
1072itlb_miss_counter:
1073 .space 4
1074
1075 .globl dtlb_miss_counter
1076dtlb_miss_counter:
1077 .space 4
1078
1079 .globl instruction_counter
1080instruction_counter:
1081 .space 4
1082#endif
diff --git a/arch/powerpc/kernel/hw_breakpoint.c b/arch/powerpc/kernel/hw_breakpoint.c
index 53cc9270aac8..53b9c1dfd7d9 100644
--- a/arch/powerpc/kernel/hw_breakpoint.c
+++ b/arch/powerpc/kernel/hw_breakpoint.c
@@ -211,9 +211,11 @@ int hw_breakpoint_handler(struct die_args *args)
211 int rc = NOTIFY_STOP; 211 int rc = NOTIFY_STOP;
212 struct perf_event *bp; 212 struct perf_event *bp;
213 struct pt_regs *regs = args->regs; 213 struct pt_regs *regs = args->regs;
214#ifndef CONFIG_PPC_8xx
214 int stepped = 1; 215 int stepped = 1;
215 struct arch_hw_breakpoint *info;
216 unsigned int instr; 216 unsigned int instr;
217#endif
218 struct arch_hw_breakpoint *info;
217 unsigned long dar = regs->dar; 219 unsigned long dar = regs->dar;
218 220
219 /* Disable breakpoints during exception handling */ 221 /* Disable breakpoints during exception handling */
@@ -257,6 +259,7 @@ int hw_breakpoint_handler(struct die_args *args)
257 (dar - bp->attr.bp_addr < bp->attr.bp_len))) 259 (dar - bp->attr.bp_addr < bp->attr.bp_len)))
258 info->type |= HW_BRK_TYPE_EXTRANEOUS_IRQ; 260 info->type |= HW_BRK_TYPE_EXTRANEOUS_IRQ;
259 261
262#ifndef CONFIG_PPC_8xx
260 /* Do not emulate user-space instructions, instead single-step them */ 263 /* Do not emulate user-space instructions, instead single-step them */
261 if (user_mode(regs)) { 264 if (user_mode(regs)) {
262 current->thread.last_hit_ubp = bp; 265 current->thread.last_hit_ubp = bp;
@@ -280,6 +283,7 @@ int hw_breakpoint_handler(struct die_args *args)
280 perf_event_disable_inatomic(bp); 283 perf_event_disable_inatomic(bp);
281 goto out; 284 goto out;
282 } 285 }
286#endif
283 /* 287 /*
284 * As a policy, the callback is invoked in a 'trigger-after-execute' 288 * As a policy, the callback is invoked in a 'trigger-after-execute'
285 * fashion 289 * fashion
diff --git a/arch/powerpc/kernel/optprobes_head.S b/arch/powerpc/kernel/optprobes_head.S
index 53e429b5a29d..4937bef7652f 100644
--- a/arch/powerpc/kernel/optprobes_head.S
+++ b/arch/powerpc/kernel/optprobes_head.S
@@ -65,6 +65,13 @@ optprobe_template_entry:
65 mfdsisr r5 65 mfdsisr r5
66 std r5,_DSISR(r1) 66 std r5,_DSISR(r1)
67 67
68 /*
69 * We may get here from a module, so load the kernel TOC in r2.
70 * The original TOC gets restored when pt_regs is restored
71 * further below.
72 */
73 ld r2,PACATOC(r13)
74
68 .global optprobe_template_op_address 75 .global optprobe_template_op_address
69optprobe_template_op_address: 76optprobe_template_op_address:
70 /* 77 /*
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index 8e6fde8d28f3..ffda24a38dda 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -1560,16 +1560,10 @@ static void pcibios_setup_phb_resources(struct pci_controller *hose,
1560 /* Hookup PHB Memory resources */ 1560 /* Hookup PHB Memory resources */
1561 for (i = 0; i < 3; ++i) { 1561 for (i = 0; i < 3; ++i) {
1562 res = &hose->mem_resources[i]; 1562 res = &hose->mem_resources[i];
1563 if (!res->flags) { 1563 if (!res->flags)
1564 if (i == 0)
1565 printk(KERN_ERR "PCI: Memory resource 0 not set for "
1566 "host bridge %s (domain %d)\n",
1567 hose->dn->full_name, hose->global_number);
1568 continue; 1564 continue;
1569 }
1570 offset = hose->mem_offset[i];
1571
1572 1565
1566 offset = hose->mem_offset[i];
1573 pr_debug("PCI: PHB MEM resource %d = %pR off 0x%08llx\n", i, 1567 pr_debug("PCI: PHB MEM resource %d = %pR off 0x%08llx\n", i,
1574 res, (unsigned long long)offset); 1568 res, (unsigned long long)offset);
1575 1569
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 5dd056df0baa..4379a079b3c2 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -730,6 +730,28 @@ static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
730 mtspr(SPRN_DABRX, dabrx); 730 mtspr(SPRN_DABRX, dabrx);
731 return 0; 731 return 0;
732} 732}
733#elif defined(CONFIG_PPC_8xx)
734static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
735{
736 unsigned long addr = dabr & ~HW_BRK_TYPE_DABR;
737 unsigned long lctrl1 = 0x90000000; /* compare type: equal on E & F */
738 unsigned long lctrl2 = 0x8e000002; /* watchpoint 1 on cmp E | F */
739
740 if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_READ)
741 lctrl1 |= 0xa0000;
742 else if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_WRITE)
743 lctrl1 |= 0xf0000;
744 else if ((dabr & HW_BRK_TYPE_RDWR) == 0)
745 lctrl2 = 0;
746
747 mtspr(SPRN_LCTRL2, 0);
748 mtspr(SPRN_CMPE, addr);
749 mtspr(SPRN_CMPF, addr + 4);
750 mtspr(SPRN_LCTRL1, lctrl1);
751 mtspr(SPRN_LCTRL2, lctrl2);
752
753 return 0;
754}
733#else 755#else
734static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 756static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
735{ 757{
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index 616de028f7f8..a3944540fe0d 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -839,7 +839,7 @@ struct ibm_arch_vec __cacheline_aligned ibm_architecture_vec = {
839 0, 839 0,
840#endif 840#endif
841 .associativity = OV5_FEAT(OV5_TYPE1_AFFINITY) | OV5_FEAT(OV5_PRRN), 841 .associativity = OV5_FEAT(OV5_TYPE1_AFFINITY) | OV5_FEAT(OV5_PRRN),
842 .bin_opts = OV5_FEAT(OV5_RESIZE_HPT), 842 .bin_opts = OV5_FEAT(OV5_RESIZE_HPT) | OV5_FEAT(OV5_HP_EVT),
843 .micro_checkpoint = 0, 843 .micro_checkpoint = 0,
844 .reserved0 = 0, 844 .reserved0 = 0,
845 .max_cpus = cpu_to_be32(NR_CPUS), /* number of cores supported */ 845 .max_cpus = cpu_to_be32(NR_CPUS), /* number of cores supported */
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index b9855f1b290a..adf2084f214b 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -113,14 +113,12 @@ void __init setup_tlb_core_data(void)
113 * If we have threads, we need either tlbsrx. 113 * If we have threads, we need either tlbsrx.
114 * or e6500 tablewalk mode, or else TLB handlers 114 * or e6500 tablewalk mode, or else TLB handlers
115 * will be racy and could produce duplicate entries. 115 * will be racy and could produce duplicate entries.
116 * Should we panic instead?
116 */ 117 */
117 if (smt_enabled_at_boot >= 2 && 118 WARN_ONCE(smt_enabled_at_boot >= 2 &&
118 !mmu_has_feature(MMU_FTR_USE_TLBRSRV) && 119 !mmu_has_feature(MMU_FTR_USE_TLBRSRV) &&
119 book3e_htw_mode != PPC_HTW_E6500) { 120 book3e_htw_mode != PPC_HTW_E6500,
120 /* Should we panic instead? */ 121 "%s: unsupported MMU configuration\n", __func__);
121 WARN_ONCE("%s: unsupported MMU configuration -- expect problems\n",
122 __func__);
123 }
124 } 122 }
125} 123}
126#endif 124#endif
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
index 14e485525e31..bc84a8d47b9e 100644
--- a/arch/powerpc/kernel/time.c
+++ b/arch/powerpc/kernel/time.c
@@ -709,7 +709,7 @@ unsigned long long running_clock(void)
709 * time and on a host which doesn't do any virtualisation TB *should* equal 709 * time and on a host which doesn't do any virtualisation TB *should* equal
710 * VTB so it makes no difference anyway. 710 * VTB so it makes no difference anyway.
711 */ 711 */
712 return local_clock() - cputime_to_nsecs(kcpustat_this_cpu->cpustat[CPUTIME_STEAL]); 712 return local_clock() - kcpustat_this_cpu->cpustat[CPUTIME_STEAL];
713} 713}
714#endif 714#endif
715 715
diff --git a/arch/powerpc/mm/pgtable.c b/arch/powerpc/mm/pgtable.c
index cb39c8bd2436..a03ff3d99e0c 100644
--- a/arch/powerpc/mm/pgtable.c
+++ b/arch/powerpc/mm/pgtable.c
@@ -193,9 +193,7 @@ void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
193 */ 193 */
194 VM_WARN_ON(pte_present(*ptep) && !pte_protnone(*ptep)); 194 VM_WARN_ON(pte_present(*ptep) && !pte_protnone(*ptep));
195 195
196 /* 196 /* Add the pte bit when trying to set a pte */
197 * Add the pte bit when tryint set a pte
198 */
199 pte = __pte(pte_val(pte) | _PAGE_PTE); 197 pte = __pte(pte_val(pte) | _PAGE_PTE);
200 198
201 /* Note: mm->context.id might not yet have been assigned as 199 /* Note: mm->context.id might not yet have been assigned as
diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S
index e2974fcd20f1..a85e06ea6c20 100644
--- a/arch/powerpc/mm/slb_low.S
+++ b/arch/powerpc/mm/slb_low.S
@@ -71,9 +71,9 @@ slb_miss_kernel_load_linear:
71 71
72 72
73BEGIN_FTR_SECTION 73BEGIN_FTR_SECTION
74 b slb_finish_load 74 b .Lslb_finish_load
75END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT) 75END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
76 b slb_finish_load_1T 76 b .Lslb_finish_load_1T
77 77
781: 781:
79#ifdef CONFIG_SPARSEMEM_VMEMMAP 79#ifdef CONFIG_SPARSEMEM_VMEMMAP
@@ -109,9 +109,9 @@ slb_miss_kernel_load_io:
109 addi r9,r9,(MAX_USER_CONTEXT - 0xc + 1)@l 109 addi r9,r9,(MAX_USER_CONTEXT - 0xc + 1)@l
110 110
111BEGIN_FTR_SECTION 111BEGIN_FTR_SECTION
112 b slb_finish_load 112 b .Lslb_finish_load
113END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT) 113END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
114 b slb_finish_load_1T 114 b .Lslb_finish_load_1T
115 115
1160: /* 1160: /*
117 * For userspace addresses, make sure this is region 0. 117 * For userspace addresses, make sure this is region 0.
@@ -174,9 +174,9 @@ END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
174 ld r9,PACACONTEXTID(r13) 174 ld r9,PACACONTEXTID(r13)
175BEGIN_FTR_SECTION 175BEGIN_FTR_SECTION
176 cmpldi r10,0x1000 176 cmpldi r10,0x1000
177 bge slb_finish_load_1T 177 bge .Lslb_finish_load_1T
178END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT) 178END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
179 b slb_finish_load 179 b .Lslb_finish_load
180 180
1818: /* invalid EA - return an error indication */ 1818: /* invalid EA - return an error indication */
182 crset 4*cr0+eq /* indicate failure */ 182 crset 4*cr0+eq /* indicate failure */
@@ -187,7 +187,7 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
187 * 187 *
188 * r3 = EA, r9 = context, r10 = ESID, r11 = flags, clobbers r9, cr7 = <> PAGE_OFFSET 188 * r3 = EA, r9 = context, r10 = ESID, r11 = flags, clobbers r9, cr7 = <> PAGE_OFFSET
189 */ 189 */
190slb_finish_load: 190.Lslb_finish_load:
191 rldimi r10,r9,ESID_BITS,0 191 rldimi r10,r9,ESID_BITS,0
192 ASM_VSID_SCRAMBLE(r10,r9,256M) 192 ASM_VSID_SCRAMBLE(r10,r9,256M)
193 /* 193 /*
@@ -256,7 +256,7 @@ slb_compare_rr_to_size:
256 * 256 *
257 * r3 = EA, r9 = context, r10 = ESID(256MB), r11 = flags, clobbers r9 257 * r3 = EA, r9 = context, r10 = ESID(256MB), r11 = flags, clobbers r9
258 */ 258 */
259slb_finish_load_1T: 259.Lslb_finish_load_1T:
260 srdi r10,r10,(SID_SHIFT_1T - SID_SHIFT) /* get 1T ESID */ 260 srdi r10,r10,(SID_SHIFT_1T - SID_SHIFT) /* get 1T ESID */
261 rldimi r10,r9,ESID_BITS_1T,0 261 rldimi r10,r9,ESID_BITS_1T,0
262 ASM_VSID_SCRAMBLE(r10,r9,1T) 262 ASM_VSID_SCRAMBLE(r10,r9,1T)
@@ -272,3 +272,11 @@ slb_finish_load_1T:
272 clrrdi r3,r3,SID_SHIFT_1T /* clear out non-ESID bits */ 272 clrrdi r3,r3,SID_SHIFT_1T /* clear out non-ESID bits */
273 b 7b 273 b 7b
274 274
275
276_ASM_NOKPROBE_SYMBOL(slb_allocate_realmode)
277_ASM_NOKPROBE_SYMBOL(slb_miss_kernel_load_linear)
278_ASM_NOKPROBE_SYMBOL(slb_miss_kernel_load_io)
279_ASM_NOKPROBE_SYMBOL(slb_compare_rr_to_size)
280#ifdef CONFIG_SPARSEMEM_VMEMMAP
281_ASM_NOKPROBE_SYMBOL(slb_miss_kernel_load_vmemmap)
282#endif
diff --git a/arch/powerpc/perf/8xx-pmu.c b/arch/powerpc/perf/8xx-pmu.c
new file mode 100644
index 000000000000..3c39f05f0af3
--- /dev/null
+++ b/arch/powerpc/perf/8xx-pmu.c
@@ -0,0 +1,173 @@
1/*
2 * Performance event support - PPC 8xx
3 *
4 * Copyright 2016 Christophe Leroy, CS Systemes d'Information
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#include <linux/kernel.h>
13#include <linux/sched.h>
14#include <linux/perf_event.h>
15#include <linux/percpu.h>
16#include <linux/hardirq.h>
17#include <asm/pmc.h>
18#include <asm/machdep.h>
19#include <asm/firmware.h>
20#include <asm/ptrace.h>
21
22#define PERF_8xx_ID_CPU_CYCLES 1
23#define PERF_8xx_ID_HW_INSTRUCTIONS 2
24#define PERF_8xx_ID_ITLB_LOAD_MISS 3
25#define PERF_8xx_ID_DTLB_LOAD_MISS 4
26
27#define C(x) PERF_COUNT_HW_CACHE_##x
28#define DTLB_LOAD_MISS (C(DTLB) | (C(OP_READ) << 8) | (C(RESULT_MISS) << 16))
29#define ITLB_LOAD_MISS (C(ITLB) | (C(OP_READ) << 8) | (C(RESULT_MISS) << 16))
30
31extern unsigned long itlb_miss_counter, dtlb_miss_counter;
32extern atomic_t instruction_counter;
33
34static atomic_t insn_ctr_ref;
35
36static s64 get_insn_ctr(void)
37{
38 int ctr;
39 unsigned long counta;
40
41 do {
42 ctr = atomic_read(&instruction_counter);
43 counta = mfspr(SPRN_COUNTA);
44 } while (ctr != atomic_read(&instruction_counter));
45
46 return ((s64)ctr << 16) | (counta >> 16);
47}
48
49static int event_type(struct perf_event *event)
50{
51 switch (event->attr.type) {
52 case PERF_TYPE_HARDWARE:
53 if (event->attr.config == PERF_COUNT_HW_CPU_CYCLES)
54 return PERF_8xx_ID_CPU_CYCLES;
55 if (event->attr.config == PERF_COUNT_HW_INSTRUCTIONS)
56 return PERF_8xx_ID_HW_INSTRUCTIONS;
57 break;
58 case PERF_TYPE_HW_CACHE:
59 if (event->attr.config == ITLB_LOAD_MISS)
60 return PERF_8xx_ID_ITLB_LOAD_MISS;
61 if (event->attr.config == DTLB_LOAD_MISS)
62 return PERF_8xx_ID_DTLB_LOAD_MISS;
63 break;
64 case PERF_TYPE_RAW:
65 break;
66 default:
67 return -ENOENT;
68 }
69 return -EOPNOTSUPP;
70}
71
72static int mpc8xx_pmu_event_init(struct perf_event *event)
73{
74 int type = event_type(event);
75
76 if (type < 0)
77 return type;
78 return 0;
79}
80
81static int mpc8xx_pmu_add(struct perf_event *event, int flags)
82{
83 int type = event_type(event);
84 s64 val = 0;
85
86 if (type < 0)
87 return type;
88
89 switch (type) {
90 case PERF_8xx_ID_CPU_CYCLES:
91 val = get_tb();
92 break;
93 case PERF_8xx_ID_HW_INSTRUCTIONS:
94 if (atomic_inc_return(&insn_ctr_ref) == 1)
95 mtspr(SPRN_ICTRL, 0xc0080007);
96 val = get_insn_ctr();
97 break;
98 case PERF_8xx_ID_ITLB_LOAD_MISS:
99 val = itlb_miss_counter;
100 break;
101 case PERF_8xx_ID_DTLB_LOAD_MISS:
102 val = dtlb_miss_counter;
103 break;
104 }
105 local64_set(&event->hw.prev_count, val);
106 return 0;
107}
108
109static void mpc8xx_pmu_read(struct perf_event *event)
110{
111 int type = event_type(event);
112 s64 prev, val = 0, delta = 0;
113
114 if (type < 0)
115 return;
116
117 do {
118 prev = local64_read(&event->hw.prev_count);
119 switch (type) {
120 case PERF_8xx_ID_CPU_CYCLES:
121 val = get_tb();
122 delta = 16 * (val - prev);
123 break;
124 case PERF_8xx_ID_HW_INSTRUCTIONS:
125 val = get_insn_ctr();
126 delta = prev - val;
127 if (delta < 0)
128 delta += 0x1000000000000LL;
129 break;
130 case PERF_8xx_ID_ITLB_LOAD_MISS:
131 val = itlb_miss_counter;
132 delta = (s64)((s32)val - (s32)prev);
133 break;
134 case PERF_8xx_ID_DTLB_LOAD_MISS:
135 val = dtlb_miss_counter;
136 delta = (s64)((s32)val - (s32)prev);
137 break;
138 }
139 } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev);
140
141 local64_add(delta, &event->count);
142}
143
144static void mpc8xx_pmu_del(struct perf_event *event, int flags)
145{
146 mpc8xx_pmu_read(event);
147 if (event_type(event) != PERF_8xx_ID_HW_INSTRUCTIONS)
148 return;
149
150 /* If it was the last user, stop counting to avoid useles overhead */
151 if (atomic_dec_return(&insn_ctr_ref) == 0)
152 mtspr(SPRN_ICTRL, 7);
153}
154
155static struct pmu mpc8xx_pmu = {
156 .event_init = mpc8xx_pmu_event_init,
157 .add = mpc8xx_pmu_add,
158 .del = mpc8xx_pmu_del,
159 .read = mpc8xx_pmu_read,
160 .capabilities = PERF_PMU_CAP_NO_INTERRUPT |
161 PERF_PMU_CAP_NO_NMI,
162};
163
164static int init_mpc8xx_pmu(void)
165{
166 mtspr(SPRN_ICTRL, 7);
167 mtspr(SPRN_CMPA, 0);
168 mtspr(SPRN_COUNTA, 0xffff);
169
170 return perf_pmu_register(&mpc8xx_pmu, "cpu", PERF_TYPE_RAW);
171}
172
173early_initcall(init_mpc8xx_pmu);
diff --git a/arch/powerpc/perf/Makefile b/arch/powerpc/perf/Makefile
index f102d5370101..4d606b99a5cb 100644
--- a/arch/powerpc/perf/Makefile
+++ b/arch/powerpc/perf/Makefile
@@ -13,5 +13,7 @@ obj-$(CONFIG_FSL_EMB_PERF_EVENT_E500) += e500-pmu.o e6500-pmu.o
13 13
14obj-$(CONFIG_HV_PERF_CTRS) += hv-24x7.o hv-gpci.o hv-common.o 14obj-$(CONFIG_HV_PERF_CTRS) += hv-24x7.o hv-gpci.o hv-common.o
15 15
16obj-$(CONFIG_PPC_8xx_PERF_EVENT) += 8xx-pmu.o
17
16obj-$(CONFIG_PPC64) += $(obj64-y) 18obj-$(CONFIG_PPC64) += $(obj64-y)
17obj-$(CONFIG_PPC32) += $(obj32-y) 19obj-$(CONFIG_PPC32) += $(obj32-y)
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index 270eb9b74e2e..595dd718ea87 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -57,6 +57,7 @@ struct cpu_hw_events {
57 void *bhrb_context; 57 void *bhrb_context;
58 struct perf_branch_stack bhrb_stack; 58 struct perf_branch_stack bhrb_stack;
59 struct perf_branch_entry bhrb_entries[BHRB_MAX_ENTRIES]; 59 struct perf_branch_entry bhrb_entries[BHRB_MAX_ENTRIES];
60 u64 ic_init;
60}; 61};
61 62
62static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); 63static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
@@ -127,6 +128,10 @@ static inline void power_pmu_bhrb_disable(struct perf_event *event) {}
127static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) {} 128static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) {}
128static inline void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) {} 129static inline void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) {}
129static void pmao_restore_workaround(bool ebb) { } 130static void pmao_restore_workaround(bool ebb) { }
131static bool use_ic(u64 event)
132{
133 return false;
134}
130#endif /* CONFIG_PPC32 */ 135#endif /* CONFIG_PPC32 */
131 136
132static bool regs_use_siar(struct pt_regs *regs) 137static bool regs_use_siar(struct pt_regs *regs)
@@ -243,7 +248,7 @@ static inline u32 perf_get_misc_flags(struct pt_regs *regs)
243 */ 248 */
244 if (ppmu->flags & PPMU_NO_SIPR) { 249 if (ppmu->flags & PPMU_NO_SIPR) {
245 unsigned long siar = mfspr(SPRN_SIAR); 250 unsigned long siar = mfspr(SPRN_SIAR);
246 if (siar >= PAGE_OFFSET) 251 if (is_kernel_addr(siar))
247 return PERF_RECORD_MISC_KERNEL; 252 return PERF_RECORD_MISC_KERNEL;
248 return PERF_RECORD_MISC_USER; 253 return PERF_RECORD_MISC_USER;
249 } 254 }
@@ -688,6 +693,15 @@ static void pmao_restore_workaround(bool ebb)
688 mtspr(SPRN_PMC5, pmcs[4]); 693 mtspr(SPRN_PMC5, pmcs[4]);
689 mtspr(SPRN_PMC6, pmcs[5]); 694 mtspr(SPRN_PMC6, pmcs[5]);
690} 695}
696
697static bool use_ic(u64 event)
698{
699 if (cpu_has_feature(CPU_FTR_POWER9_DD1) &&
700 (event == 0x200f2 || event == 0x300f2))
701 return true;
702
703 return false;
704}
691#endif /* CONFIG_PPC64 */ 705#endif /* CONFIG_PPC64 */
692 706
693static void perf_event_interrupt(struct pt_regs *regs); 707static void perf_event_interrupt(struct pt_regs *regs);
@@ -1007,6 +1021,7 @@ static u64 check_and_compute_delta(u64 prev, u64 val)
1007static void power_pmu_read(struct perf_event *event) 1021static void power_pmu_read(struct perf_event *event)
1008{ 1022{
1009 s64 val, delta, prev; 1023 s64 val, delta, prev;
1024 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
1010 1025
1011 if (event->hw.state & PERF_HES_STOPPED) 1026 if (event->hw.state & PERF_HES_STOPPED)
1012 return; 1027 return;
@@ -1016,6 +1031,13 @@ static void power_pmu_read(struct perf_event *event)
1016 1031
1017 if (is_ebb_event(event)) { 1032 if (is_ebb_event(event)) {
1018 val = read_pmc(event->hw.idx); 1033 val = read_pmc(event->hw.idx);
1034 if (use_ic(event->attr.config)) {
1035 val = mfspr(SPRN_IC);
1036 if (val > cpuhw->ic_init)
1037 val = val - cpuhw->ic_init;
1038 else
1039 val = val + (0 - cpuhw->ic_init);
1040 }
1019 local64_set(&event->hw.prev_count, val); 1041 local64_set(&event->hw.prev_count, val);
1020 return; 1042 return;
1021 } 1043 }
@@ -1029,6 +1051,13 @@ static void power_pmu_read(struct perf_event *event)
1029 prev = local64_read(&event->hw.prev_count); 1051 prev = local64_read(&event->hw.prev_count);
1030 barrier(); 1052 barrier();
1031 val = read_pmc(event->hw.idx); 1053 val = read_pmc(event->hw.idx);
1054 if (use_ic(event->attr.config)) {
1055 val = mfspr(SPRN_IC);
1056 if (val > cpuhw->ic_init)
1057 val = val - cpuhw->ic_init;
1058 else
1059 val = val + (0 - cpuhw->ic_init);
1060 }
1032 delta = check_and_compute_delta(prev, val); 1061 delta = check_and_compute_delta(prev, val);
1033 if (!delta) 1062 if (!delta)
1034 return; 1063 return;
@@ -1466,6 +1495,13 @@ nocheck:
1466 event->attr.branch_sample_type); 1495 event->attr.branch_sample_type);
1467 } 1496 }
1468 1497
1498 /*
1499 * Workaround for POWER9 DD1 to use the Instruction Counter
1500 * register value for instruction counting
1501 */
1502 if (use_ic(event->attr.config))
1503 cpuhw->ic_init = mfspr(SPRN_IC);
1504
1469 perf_pmu_enable(event->pmu); 1505 perf_pmu_enable(event->pmu);
1470 local_irq_restore(flags); 1506 local_irq_restore(flags);
1471 return ret; 1507 return ret;
diff --git a/arch/powerpc/perf/isa207-common.c b/arch/powerpc/perf/isa207-common.c
index 50e598cf644b..e79fb5fb817d 100644
--- a/arch/powerpc/perf/isa207-common.c
+++ b/arch/powerpc/perf/isa207-common.c
@@ -97,6 +97,28 @@ static unsigned long combine_shift(unsigned long pmc)
97 return MMCR1_COMBINE_SHIFT(pmc); 97 return MMCR1_COMBINE_SHIFT(pmc);
98} 98}
99 99
100static inline bool event_is_threshold(u64 event)
101{
102 return (event >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK;
103}
104
105static bool is_thresh_cmp_valid(u64 event)
106{
107 unsigned int cmp, exp;
108
109 /*
110 * Check the mantissa upper two bits are not zero, unless the
111 * exponent is also zero. See the THRESH_CMP_MANTISSA doc.
112 */
113 cmp = (event >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK;
114 exp = cmp >> 7;
115
116 if (exp && (cmp & 0x60) == 0)
117 return false;
118
119 return true;
120}
121
100int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp) 122int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp)
101{ 123{
102 unsigned int unit, pmc, cache, ebb; 124 unsigned int unit, pmc, cache, ebb;
@@ -163,28 +185,26 @@ int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp)
163 value |= CNST_SAMPLE_VAL(event >> EVENT_SAMPLE_SHIFT); 185 value |= CNST_SAMPLE_VAL(event >> EVENT_SAMPLE_SHIFT);
164 } 186 }
165 187
166 /* 188 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
167 * Special case for PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC, 189 if (event_is_threshold(event) && is_thresh_cmp_valid(event)) {
168 * the threshold control bits are used for the match value. 190 mask |= CNST_THRESH_MASK;
169 */ 191 value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT);
170 if (event_is_fab_match(event)) { 192 }
171 mask |= CNST_FAB_MATCH_MASK;
172 value |= CNST_FAB_MATCH_VAL(event >> EVENT_THR_CTL_SHIFT);
173 } else { 193 } else {
174 /* 194 /*
175 * Check the mantissa upper two bits are not zero, unless the 195 * Special case for PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC,
176 * exponent is also zero. See the THRESH_CMP_MANTISSA doc. 196 * the threshold control bits are used for the match value.
177 */ 197 */
178 unsigned int cmp, exp; 198 if (event_is_fab_match(event)) {
179 199 mask |= CNST_FAB_MATCH_MASK;
180 cmp = (event >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK; 200 value |= CNST_FAB_MATCH_VAL(event >> EVENT_THR_CTL_SHIFT);
181 exp = cmp >> 7; 201 } else {
182 202 if (!is_thresh_cmp_valid(event))
183 if (exp && (cmp & 0x60) == 0) 203 return -1;
184 return -1;
185 204
186 mask |= CNST_THRESH_MASK; 205 mask |= CNST_THRESH_MASK;
187 value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT); 206 value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT);
207 }
188 } 208 }
189 209
190 if (!pmc && ebb) 210 if (!pmc && ebb)
@@ -279,7 +299,7 @@ int isa207_compute_mmcr(u64 event[], int n_ev,
279 * PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC, 299 * PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC,
280 * the threshold bits are used for the match value. 300 * the threshold bits are used for the match value.
281 */ 301 */
282 if (event_is_fab_match(event[i])) { 302 if (!cpu_has_feature(CPU_FTR_ARCH_300) && event_is_fab_match(event[i])) {
283 mmcr1 |= ((event[i] >> EVENT_THR_CTL_SHIFT) & 303 mmcr1 |= ((event[i] >> EVENT_THR_CTL_SHIFT) &
284 EVENT_THR_CTL_MASK) << MMCR1_FAB_SHIFT; 304 EVENT_THR_CTL_MASK) << MMCR1_FAB_SHIFT;
285 } else { 305 } else {
@@ -338,3 +358,39 @@ void isa207_disable_pmc(unsigned int pmc, unsigned long mmcr[])
338 if (pmc <= 3) 358 if (pmc <= 3)
339 mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SHIFT(pmc + 1)); 359 mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SHIFT(pmc + 1));
340} 360}
361
362static int find_alternative(u64 event, const unsigned int ev_alt[][MAX_ALT], int size)
363{
364 int i, j;
365
366 for (i = 0; i < size; ++i) {
367 if (event < ev_alt[i][0])
368 break;
369
370 for (j = 0; j < MAX_ALT && ev_alt[i][j]; ++j)
371 if (event == ev_alt[i][j])
372 return i;
373 }
374
375 return -1;
376}
377
378int isa207_get_alternatives(u64 event, u64 alt[],
379 const unsigned int ev_alt[][MAX_ALT], int size)
380{
381 int i, j, num_alt = 0;
382 u64 alt_event;
383
384 alt[num_alt++] = event;
385 i = find_alternative(event, ev_alt, size);
386 if (i >= 0) {
387 /* Filter out the original event, it's already in alt[0] */
388 for (j = 0; j < MAX_ALT; ++j) {
389 alt_event = ev_alt[i][j];
390 if (alt_event && alt_event != event)
391 alt[num_alt++] = alt_event;
392 }
393 }
394
395 return num_alt;
396}
diff --git a/arch/powerpc/perf/isa207-common.h b/arch/powerpc/perf/isa207-common.h
index 90495f1580c7..cf9bd8990159 100644
--- a/arch/powerpc/perf/isa207-common.h
+++ b/arch/powerpc/perf/isa207-common.h
@@ -222,6 +222,10 @@
222 CNST_PMC_VAL(1) | CNST_PMC_VAL(2) | CNST_PMC_VAL(3) | \ 222 CNST_PMC_VAL(1) | CNST_PMC_VAL(2) | CNST_PMC_VAL(3) | \
223 CNST_PMC_VAL(4) | CNST_PMC_VAL(5) | CNST_PMC_VAL(6) | CNST_NC_VAL 223 CNST_PMC_VAL(4) | CNST_PMC_VAL(5) | CNST_PMC_VAL(6) | CNST_NC_VAL
224 224
225/*
226 * Lets restrict use of PMC5 for instruction counting.
227 */
228#define P9_DD1_TEST_ADDER (ISA207_TEST_ADDER | CNST_PMC_VAL(5))
225 229
226/* Bits in MMCR1 for PowerISA v2.07 */ 230/* Bits in MMCR1 for PowerISA v2.07 */
227#define MMCR1_UNIT_SHIFT(pmc) (60 - (4 * ((pmc) - 1))) 231#define MMCR1_UNIT_SHIFT(pmc) (60 - (4 * ((pmc) - 1)))
@@ -260,5 +264,8 @@ int isa207_compute_mmcr(u64 event[], int n_ev,
260 unsigned int hwc[], unsigned long mmcr[], 264 unsigned int hwc[], unsigned long mmcr[],
261 struct perf_event *pevents[]); 265 struct perf_event *pevents[]);
262void isa207_disable_pmc(unsigned int pmc, unsigned long mmcr[]); 266void isa207_disable_pmc(unsigned int pmc, unsigned long mmcr[]);
267int isa207_get_alternatives(u64 event, u64 alt[],
268 const unsigned int ev_alt[][MAX_ALT], int size);
269
263 270
264#endif 271#endif
diff --git a/arch/powerpc/perf/power8-pmu.c b/arch/powerpc/perf/power8-pmu.c
index d07186382f3a..ce15b19a7962 100644
--- a/arch/powerpc/perf/power8-pmu.c
+++ b/arch/powerpc/perf/power8-pmu.c
@@ -48,43 +48,12 @@ static const unsigned int event_alternatives[][MAX_ALT] = {
48 { PM_RUN_INST_CMPL_ALT, PM_RUN_INST_CMPL }, 48 { PM_RUN_INST_CMPL_ALT, PM_RUN_INST_CMPL },
49}; 49};
50 50
51/*
52 * Scan the alternatives table for a match and return the
53 * index into the alternatives table if found, else -1.
54 */
55static int find_alternative(u64 event)
56{
57 int i, j;
58
59 for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
60 if (event < event_alternatives[i][0])
61 break;
62
63 for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j)
64 if (event == event_alternatives[i][j])
65 return i;
66 }
67
68 return -1;
69}
70
71static int power8_get_alternatives(u64 event, unsigned int flags, u64 alt[]) 51static int power8_get_alternatives(u64 event, unsigned int flags, u64 alt[])
72{ 52{
73 int i, j, num_alt = 0; 53 int i, j, num_alt = 0;
74 u64 alt_event;
75
76 alt[num_alt++] = event;
77
78 i = find_alternative(event);
79 if (i >= 0) {
80 /* Filter out the original event, it's already in alt[0] */
81 for (j = 0; j < MAX_ALT; ++j) {
82 alt_event = event_alternatives[i][j];
83 if (alt_event && alt_event != event)
84 alt[num_alt++] = alt_event;
85 }
86 }
87 54
55 num_alt = isa207_get_alternatives(event, alt, event_alternatives,
56 (int)ARRAY_SIZE(event_alternatives));
88 if (flags & PPMU_ONLY_COUNT_RUN) { 57 if (flags & PPMU_ONLY_COUNT_RUN) {
89 /* 58 /*
90 * We're only counting in RUN state, so PM_CYC is equivalent to 59 * We're only counting in RUN state, so PM_CYC is equivalent to
diff --git a/arch/powerpc/perf/power9-events-list.h b/arch/powerpc/perf/power9-events-list.h
index 929b56d47ad9..71a6bfee5c02 100644
--- a/arch/powerpc/perf/power9-events-list.h
+++ b/arch/powerpc/perf/power9-events-list.h
@@ -53,3 +53,6 @@ EVENT(PM_ITLB_MISS, 0x400fc)
53EVENT(PM_RUN_INST_CMPL, 0x500fa) 53EVENT(PM_RUN_INST_CMPL, 0x500fa)
54/* Run_cycles */ 54/* Run_cycles */
55EVENT(PM_RUN_CYC, 0x600f4) 55EVENT(PM_RUN_CYC, 0x600f4)
56/* Instruction Dispatched */
57EVENT(PM_INST_DISP, 0x200f2)
58EVENT(PM_INST_DISP_ALT, 0x300f2)
diff --git a/arch/powerpc/perf/power9-pmu.c b/arch/powerpc/perf/power9-pmu.c
index 7332634e18c9..7f6582708e06 100644
--- a/arch/powerpc/perf/power9-pmu.c
+++ b/arch/powerpc/perf/power9-pmu.c
@@ -22,7 +22,7 @@
22 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | 22 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
23 * | | [ ] [ ] [ thresh_cmp ] [ thresh_ctl ] 23 * | | [ ] [ ] [ thresh_cmp ] [ thresh_ctl ]
24 * | | | | | 24 * | | | | |
25 * | | *- IFM (Linux) | thresh start/stop OR FAB match -* 25 * | | *- IFM (Linux) | thresh start/stop -*
26 * | *- BHRB (Linux) *sm 26 * | *- BHRB (Linux) *sm
27 * *- EBB (Linux) 27 * *- EBB (Linux)
28 * 28 *
@@ -50,11 +50,9 @@
50 * MMCR1[31] = pmc4combine[1] 50 * MMCR1[31] = pmc4combine[1]
51 * 51 *
52 * if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011 52 * if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011
53 * # PM_MRK_FAB_RSP_MATCH 53 * MMCR1[20:27] = thresh_ctl
54 * MMCR1[20:27] = thresh_ctl (FAB_CRESP_MATCH / FAB_TYPE_MATCH)
55 * else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001 54 * else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001
56 * # PM_MRK_FAB_RSP_MATCH_CYC 55 * MMCR1[20:27] = thresh_ctl
57 * MMCR1[20:27] = thresh_ctl (FAB_CRESP_MATCH / FAB_TYPE_MATCH)
58 * else 56 * else
59 * MMCRA[48:55] = thresh_ctl (THRESH START/END) 57 * MMCRA[48:55] = thresh_ctl (THRESH START/END)
60 * 58 *
@@ -106,6 +104,21 @@ enum {
106/* PowerISA v2.07 format attribute structure*/ 104/* PowerISA v2.07 format attribute structure*/
107extern struct attribute_group isa207_pmu_format_group; 105extern struct attribute_group isa207_pmu_format_group;
108 106
107/* Table of alternatives, sorted by column 0 */
108static const unsigned int power9_event_alternatives[][MAX_ALT] = {
109 { PM_INST_DISP, PM_INST_DISP_ALT },
110};
111
112static int power9_get_alternatives(u64 event, unsigned int flags, u64 alt[])
113{
114 int num_alt = 0;
115
116 num_alt = isa207_get_alternatives(event, alt, power9_event_alternatives,
117 (int)ARRAY_SIZE(power9_event_alternatives));
118
119 return num_alt;
120}
121
109GENERIC_EVENT_ATTR(cpu-cycles, PM_CYC); 122GENERIC_EVENT_ATTR(cpu-cycles, PM_CYC);
110GENERIC_EVENT_ATTR(stalled-cycles-frontend, PM_ICT_NOSLOT_CYC); 123GENERIC_EVENT_ATTR(stalled-cycles-frontend, PM_ICT_NOSLOT_CYC);
111GENERIC_EVENT_ATTR(stalled-cycles-backend, PM_CMPLU_STALL); 124GENERIC_EVENT_ATTR(stalled-cycles-backend, PM_CMPLU_STALL);
@@ -213,6 +226,17 @@ static const struct attribute_group *power9_pmu_attr_groups[] = {
213 NULL, 226 NULL,
214}; 227};
215 228
229static int power9_generic_events_dd1[] = {
230 [PERF_COUNT_HW_CPU_CYCLES] = PM_CYC,
231 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PM_ICT_NOSLOT_CYC,
232 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = PM_CMPLU_STALL,
233 [PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_DISP,
234 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BRU_CMPL,
235 [PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED_CMPL,
236 [PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1,
237 [PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1_FIN,
238};
239
216static int power9_generic_events[] = { 240static int power9_generic_events[] = {
217 [PERF_COUNT_HW_CPU_CYCLES] = PM_CYC, 241 [PERF_COUNT_HW_CPU_CYCLES] = PM_CYC,
218 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PM_ICT_NOSLOT_CYC, 242 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PM_ICT_NOSLOT_CYC,
@@ -383,10 +407,11 @@ static struct power_pmu power9_isa207_pmu = {
383 .config_bhrb = power9_config_bhrb, 407 .config_bhrb = power9_config_bhrb,
384 .bhrb_filter_map = power9_bhrb_filter_map, 408 .bhrb_filter_map = power9_bhrb_filter_map,
385 .get_constraint = isa207_get_constraint, 409 .get_constraint = isa207_get_constraint,
410 .get_alternatives = power9_get_alternatives,
386 .disable_pmc = isa207_disable_pmc, 411 .disable_pmc = isa207_disable_pmc,
387 .flags = PPMU_NO_SIAR | PPMU_ARCH_207S, 412 .flags = PPMU_NO_SIAR | PPMU_ARCH_207S,
388 .n_generic = ARRAY_SIZE(power9_generic_events), 413 .n_generic = ARRAY_SIZE(power9_generic_events_dd1),
389 .generic_events = power9_generic_events, 414 .generic_events = power9_generic_events_dd1,
390 .cache_events = &power9_cache_events, 415 .cache_events = &power9_cache_events,
391 .attr_groups = power9_isa207_pmu_attr_groups, 416 .attr_groups = power9_isa207_pmu_attr_groups,
392 .bhrb_nr = 32, 417 .bhrb_nr = 32,
@@ -396,11 +421,12 @@ static struct power_pmu power9_pmu = {
396 .name = "POWER9", 421 .name = "POWER9",
397 .n_counter = MAX_PMU_COUNTERS, 422 .n_counter = MAX_PMU_COUNTERS,
398 .add_fields = ISA207_ADD_FIELDS, 423 .add_fields = ISA207_ADD_FIELDS,
399 .test_adder = ISA207_TEST_ADDER, 424 .test_adder = P9_DD1_TEST_ADDER,
400 .compute_mmcr = isa207_compute_mmcr, 425 .compute_mmcr = isa207_compute_mmcr,
401 .config_bhrb = power9_config_bhrb, 426 .config_bhrb = power9_config_bhrb,
402 .bhrb_filter_map = power9_bhrb_filter_map, 427 .bhrb_filter_map = power9_bhrb_filter_map,
403 .get_constraint = isa207_get_constraint, 428 .get_constraint = isa207_get_constraint,
429 .get_alternatives = power9_get_alternatives,
404 .disable_pmc = isa207_disable_pmc, 430 .disable_pmc = isa207_disable_pmc,
405 .flags = PPMU_HAS_SIER | PPMU_ARCH_207S, 431 .flags = PPMU_HAS_SIER | PPMU_ARCH_207S,
406 .n_generic = ARRAY_SIZE(power9_generic_events), 432 .n_generic = ARRAY_SIZE(power9_generic_events),
@@ -420,6 +446,11 @@ static int __init init_power9_pmu(void)
420 return -ENODEV; 446 return -ENODEV;
421 447
422 if (cpu_has_feature(CPU_FTR_POWER9_DD1)) { 448 if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {
449 /*
450 * Since PM_INST_CMPL may not provide right counts in all
451 * sampling scenarios in power9 DD1, instead use PM_INST_DISP.
452 */
453 EVENT_VAR(PM_INST_CMPL, _g).id = PM_INST_DISP;
423 rc = register_power_pmu(&power9_isa207_pmu); 454 rc = register_power_pmu(&power9_isa207_pmu);
424 } else { 455 } else {
425 rc = register_power_pmu(&power9_pmu); 456 rc = register_power_pmu(&power9_pmu);
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 7bc86dae9517..fe19dad568e2 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_P1022_RDK) += p1022_rdk.o
22obj-$(CONFIG_P1023_RDB) += p1023_rdb.o 22obj-$(CONFIG_P1023_RDB) += p1023_rdb.o
23obj-$(CONFIG_TWR_P102x) += twr_p102x.o 23obj-$(CONFIG_TWR_P102x) += twr_p102x.o
24obj-$(CONFIG_CORENET_GENERIC) += corenet_generic.o 24obj-$(CONFIG_CORENET_GENERIC) += corenet_generic.o
25obj-$(CONFIG_FB_FSL_DIU) += t1042rdb_diu.o
25obj-$(CONFIG_STX_GP3) += stx_gp3.o 26obj-$(CONFIG_STX_GP3) += stx_gp3.o
26obj-$(CONFIG_TQM85xx) += tqm85xx.o 27obj-$(CONFIG_TQM85xx) += tqm85xx.o
27obj-$(CONFIG_SBC8548) += sbc8548.o 28obj-$(CONFIG_SBC8548) += sbc8548.o
diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c b/arch/powerpc/platforms/85xx/corenet_generic.c
index 6c0ba75fb256..ac191a7a1337 100644
--- a/arch/powerpc/platforms/85xx/corenet_generic.c
+++ b/arch/powerpc/platforms/85xx/corenet_generic.c
@@ -157,6 +157,7 @@ static const char * const boards[] __initconst = {
157 "fsl,T1040RDB", 157 "fsl,T1040RDB",
158 "fsl,T1042RDB", 158 "fsl,T1042RDB",
159 "fsl,T1042RDB_PI", 159 "fsl,T1042RDB_PI",
160 "keymile,kmcent2",
160 "keymile,kmcoge4", 161 "keymile,kmcoge4",
161 "varisys,CYRUS", 162 "varisys,CYRUS",
162 NULL 163 NULL
diff --git a/arch/powerpc/platforms/85xx/t1042rdb_diu.c b/arch/powerpc/platforms/85xx/t1042rdb_diu.c
new file mode 100644
index 000000000000..58fa3d319f1c
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/t1042rdb_diu.c
@@ -0,0 +1,152 @@
1/*
2 * T1042 platform DIU operation
3 *
4 * Copyright 2014 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#include <linux/io.h>
13#include <linux/kernel.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16
17#include <sysdev/fsl_soc.h>
18
19/*DIU Pixel ClockCR offset in scfg*/
20#define CCSR_SCFG_PIXCLKCR 0x28
21
22/* DIU Pixel Clock bits of the PIXCLKCR */
23#define PIXCLKCR_PXCKEN 0x80000000
24#define PIXCLKCR_PXCKINV 0x40000000
25#define PIXCLKCR_PXCKDLY 0x0000FF00
26#define PIXCLKCR_PXCLK_MASK 0x00FF0000
27
28/* Some CPLD register definitions */
29#define CPLD_DIUCSR 0x16
30#define CPLD_DIUCSR_DVIEN 0x80
31#define CPLD_DIUCSR_BACKLIGHT 0x0f
32
33struct device_node *cpld_node;
34
35/**
36 * t1042rdb_set_monitor_port: switch the output to a different monitor port
37 */
38static void t1042rdb_set_monitor_port(enum fsl_diu_monitor_port port)
39{
40 static void __iomem *cpld_base;
41
42 cpld_base = of_iomap(cpld_node, 0);
43 if (!cpld_base) {
44 pr_err("%s: Could not map cpld registers\n", __func__);
45 goto exit;
46 }
47
48 switch (port) {
49 case FSL_DIU_PORT_DVI:
50 /* Enable the DVI(HDMI) port, disable the DFP and
51 * the backlight
52 */
53 clrbits8(cpld_base + CPLD_DIUCSR, CPLD_DIUCSR_DVIEN);
54 break;
55 case FSL_DIU_PORT_LVDS:
56 /*
57 * LVDS also needs backlight enabled, otherwise the display
58 * will be blank.
59 */
60 /* Enable the DFP port, disable the DVI*/
61 setbits8(cpld_base + CPLD_DIUCSR, 0x01 << 8);
62 setbits8(cpld_base + CPLD_DIUCSR, 0x01 << 4);
63 setbits8(cpld_base + CPLD_DIUCSR, CPLD_DIUCSR_BACKLIGHT);
64 break;
65 default:
66 pr_err("%s: Unsupported monitor port %i\n", __func__, port);
67 }
68
69 iounmap(cpld_base);
70exit:
71 of_node_put(cpld_node);
72}
73
74/**
75 * t1042rdb_set_pixel_clock: program the DIU's clock
76 * @pixclock: pixel clock in ps (pico seconds)
77 */
78static void t1042rdb_set_pixel_clock(unsigned int pixclock)
79{
80 struct device_node *scfg_np;
81 void __iomem *scfg;
82 unsigned long freq;
83 u64 temp;
84 u32 pxclk;
85
86 scfg_np = of_find_compatible_node(NULL, NULL, "fsl,t1040-scfg");
87 if (!scfg_np) {
88 pr_err("%s: Missing scfg node. Can not display video.\n",
89 __func__);
90 return;
91 }
92
93 scfg = of_iomap(scfg_np, 0);
94 of_node_put(scfg_np);
95 if (!scfg) {
96 pr_err("%s: Could not map device. Can not display video.\n",
97 __func__);
98 return;
99 }
100
101 /* Convert pixclock into frequency */
102 temp = 1000000000000ULL;
103 do_div(temp, pixclock);
104 freq = temp;
105
106 /*
107 * 'pxclk' is the ratio of the platform clock to the pixel clock.
108 * This number is programmed into the PIXCLKCR register, and the valid
109 * range of values is 2-255.
110 */
111 pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq);
112 pxclk = clamp_t(u32, pxclk, 2, 255);
113
114 /* Disable the pixel clock, and set it to non-inverted and no delay */
115 clrbits32(scfg + CCSR_SCFG_PIXCLKCR,
116 PIXCLKCR_PXCKEN | PIXCLKCR_PXCKDLY | PIXCLKCR_PXCLK_MASK);
117
118 /* Enable the clock and set the pxclk */
119 setbits32(scfg + CCSR_SCFG_PIXCLKCR, PIXCLKCR_PXCKEN | (pxclk << 16));
120
121 iounmap(scfg);
122}
123
124/**
125 * t1042rdb_valid_monitor_port: set the monitor port for sysfs
126 */
127static enum fsl_diu_monitor_port
128t1042rdb_valid_monitor_port(enum fsl_diu_monitor_port port)
129{
130 switch (port) {
131 case FSL_DIU_PORT_DVI:
132 case FSL_DIU_PORT_LVDS:
133 return port;
134 default:
135 return FSL_DIU_PORT_DVI; /* Dual-link LVDS is not supported */
136 }
137}
138
139static int __init t1042rdb_diu_init(void)
140{
141 cpld_node = of_find_compatible_node(NULL, NULL, "fsl,t1042rdb-cpld");
142 if (!cpld_node)
143 return 0;
144
145 diu_ops.set_monitor_port = t1042rdb_set_monitor_port;
146 diu_ops.set_pixel_clock = t1042rdb_set_pixel_clock;
147 diu_ops.valid_monitor_port = t1042rdb_valid_monitor_port;
148
149 return 0;
150}
151
152early_initcall(t1042rdb_diu_init);
diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
index 6e89e5a8d4fb..99b0ae8acb78 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -172,6 +172,13 @@ config PPC_FPU
172 bool 172 bool
173 default y if PPC64 173 default y if PPC64
174 174
175config PPC_8xx_PERF_EVENT
176 bool "PPC 8xx perf events"
177 depends on PPC_8xx && PERF_EVENTS
178 help
179 This is Performance Events support for PPC 8xx. The 8xx doesn't
180 have a PMU but some events are emulated using 8xx features.
181
175config FSL_EMB_PERFMON 182config FSL_EMB_PERFMON
176 bool "Freescale Embedded Perfmon" 183 bool "Freescale Embedded Perfmon"
177 depends on E500 || PPC_83xx 184 depends on E500 || PPC_83xx
diff --git a/arch/powerpc/platforms/cell/spufs/file.c b/arch/powerpc/platforms/cell/spufs/file.c
index e5ec1368f0cd..ae2f740a82f1 100644
--- a/arch/powerpc/platforms/cell/spufs/file.c
+++ b/arch/powerpc/platforms/cell/spufs/file.c
@@ -683,23 +683,13 @@ size_t spu_ibox_read(struct spu_context *ctx, u32 *data)
683 return ctx->ops->ibox_read(ctx, data); 683 return ctx->ops->ibox_read(ctx, data);
684} 684}
685 685
686static int spufs_ibox_fasync(int fd, struct file *file, int on)
687{
688 struct spu_context *ctx = file->private_data;
689
690 return fasync_helper(fd, file, on, &ctx->ibox_fasync);
691}
692
693/* interrupt-level ibox callback function. */ 686/* interrupt-level ibox callback function. */
694void spufs_ibox_callback(struct spu *spu) 687void spufs_ibox_callback(struct spu *spu)
695{ 688{
696 struct spu_context *ctx = spu->ctx; 689 struct spu_context *ctx = spu->ctx;
697 690
698 if (!ctx) 691 if (ctx)
699 return; 692 wake_up_all(&ctx->ibox_wq);
700
701 wake_up_all(&ctx->ibox_wq);
702 kill_fasync(&ctx->ibox_fasync, SIGIO, POLLIN);
703} 693}
704 694
705/* 695/*
@@ -794,7 +784,6 @@ static const struct file_operations spufs_ibox_fops = {
794 .open = spufs_pipe_open, 784 .open = spufs_pipe_open,
795 .read = spufs_ibox_read, 785 .read = spufs_ibox_read,
796 .poll = spufs_ibox_poll, 786 .poll = spufs_ibox_poll,
797 .fasync = spufs_ibox_fasync,
798 .llseek = no_llseek, 787 .llseek = no_llseek,
799}; 788};
800 789
@@ -832,26 +821,13 @@ size_t spu_wbox_write(struct spu_context *ctx, u32 data)
832 return ctx->ops->wbox_write(ctx, data); 821 return ctx->ops->wbox_write(ctx, data);
833} 822}
834 823
835static int spufs_wbox_fasync(int fd, struct file *file, int on)
836{
837 struct spu_context *ctx = file->private_data;
838 int ret;
839
840 ret = fasync_helper(fd, file, on, &ctx->wbox_fasync);
841
842 return ret;
843}
844
845/* interrupt-level wbox callback function. */ 824/* interrupt-level wbox callback function. */
846void spufs_wbox_callback(struct spu *spu) 825void spufs_wbox_callback(struct spu *spu)
847{ 826{
848 struct spu_context *ctx = spu->ctx; 827 struct spu_context *ctx = spu->ctx;
849 828
850 if (!ctx) 829 if (ctx)
851 return; 830 wake_up_all(&ctx->wbox_wq);
852
853 wake_up_all(&ctx->wbox_wq);
854 kill_fasync(&ctx->wbox_fasync, SIGIO, POLLOUT);
855} 831}
856 832
857/* 833/*
@@ -944,7 +920,6 @@ static const struct file_operations spufs_wbox_fops = {
944 .open = spufs_pipe_open, 920 .open = spufs_pipe_open,
945 .write = spufs_wbox_write, 921 .write = spufs_wbox_write,
946 .poll = spufs_wbox_poll, 922 .poll = spufs_wbox_poll,
947 .fasync = spufs_wbox_fasync,
948 .llseek = no_llseek, 923 .llseek = no_llseek,
949}; 924};
950 925
@@ -1520,28 +1495,8 @@ void spufs_mfc_callback(struct spu *spu)
1520{ 1495{
1521 struct spu_context *ctx = spu->ctx; 1496 struct spu_context *ctx = spu->ctx;
1522 1497
1523 if (!ctx) 1498 if (ctx)
1524 return; 1499 wake_up_all(&ctx->mfc_wq);
1525
1526 wake_up_all(&ctx->mfc_wq);
1527
1528 pr_debug("%s %s\n", __func__, spu->name);
1529 if (ctx->mfc_fasync) {
1530 u32 free_elements, tagstatus;
1531 unsigned int mask;
1532
1533 /* no need for spu_acquire in interrupt context */
1534 free_elements = ctx->ops->get_mfc_free_elements(ctx);
1535 tagstatus = ctx->ops->read_mfc_tagstatus(ctx);
1536
1537 mask = 0;
1538 if (free_elements & 0xffff)
1539 mask |= POLLOUT;
1540 if (tagstatus & ctx->tagwait)
1541 mask |= POLLIN;
1542
1543 kill_fasync(&ctx->mfc_fasync, SIGIO, mask);
1544 }
1545} 1500}
1546 1501
1547static int spufs_read_mfc_tagstatus(struct spu_context *ctx, u32 *status) 1502static int spufs_read_mfc_tagstatus(struct spu_context *ctx, u32 *status)
@@ -1803,13 +1758,6 @@ static int spufs_mfc_fsync(struct file *file, loff_t start, loff_t end, int data
1803 return err; 1758 return err;
1804} 1759}
1805 1760
1806static int spufs_mfc_fasync(int fd, struct file *file, int on)
1807{
1808 struct spu_context *ctx = file->private_data;
1809
1810 return fasync_helper(fd, file, on, &ctx->mfc_fasync);
1811}
1812
1813static const struct file_operations spufs_mfc_fops = { 1761static const struct file_operations spufs_mfc_fops = {
1814 .open = spufs_mfc_open, 1762 .open = spufs_mfc_open,
1815 .release = spufs_mfc_release, 1763 .release = spufs_mfc_release,
@@ -1818,7 +1766,6 @@ static const struct file_operations spufs_mfc_fops = {
1818 .poll = spufs_mfc_poll, 1766 .poll = spufs_mfc_poll,
1819 .flush = spufs_mfc_flush, 1767 .flush = spufs_mfc_flush,
1820 .fsync = spufs_mfc_fsync, 1768 .fsync = spufs_mfc_fsync,
1821 .fasync = spufs_mfc_fasync,
1822 .mmap = spufs_mfc_mmap, 1769 .mmap = spufs_mfc_mmap,
1823 .llseek = no_llseek, 1770 .llseek = no_llseek,
1824}; 1771};
diff --git a/arch/powerpc/platforms/cell/spufs/spufs.h b/arch/powerpc/platforms/cell/spufs/spufs.h
index bcfd6f063efa..aac733966092 100644
--- a/arch/powerpc/platforms/cell/spufs/spufs.h
+++ b/arch/powerpc/platforms/cell/spufs/spufs.h
@@ -102,9 +102,6 @@ struct spu_context {
102 wait_queue_head_t stop_wq; 102 wait_queue_head_t stop_wq;
103 wait_queue_head_t mfc_wq; 103 wait_queue_head_t mfc_wq;
104 wait_queue_head_t run_wq; 104 wait_queue_head_t run_wq;
105 struct fasync_struct *ibox_fasync;
106 struct fasync_struct *wbox_fasync;
107 struct fasync_struct *mfc_fasync;
108 u32 tagwait; 105 u32 tagwait;
109 struct spu_context_ops *ops; 106 struct spu_context_ops *ops;
110 struct work_struct reap_work; 107 struct work_struct reap_work;
diff --git a/arch/powerpc/platforms/powernv/Kconfig b/arch/powerpc/platforms/powernv/Kconfig
index 604190cab522..3a07e4dcf97c 100644
--- a/arch/powerpc/platforms/powernv/Kconfig
+++ b/arch/powerpc/platforms/powernv/Kconfig
@@ -5,7 +5,8 @@ config PPC_POWERNV
5 select PPC_XICS 5 select PPC_XICS
6 select PPC_ICP_NATIVE 6 select PPC_ICP_NATIVE
7 select PPC_P7_NAP 7 select PPC_P7_NAP
8 select PPC_PCI_CHOICE if EMBEDDED 8 select PCI
9 select PCI_MSI
9 select EPAPR_BOOT 10 select EPAPR_BOOT
10 select PPC_INDIRECT_PIO 11 select PPC_INDIRECT_PIO
11 select PPC_UDBG_16550 12 select PPC_UDBG_16550
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
index e0f83c204ccc..6901a06da2f9 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -1468,14 +1468,12 @@ void pnv_pci_sriov_disable(struct pci_dev *pdev)
1468 struct pnv_phb *phb; 1468 struct pnv_phb *phb;
1469 struct pnv_ioda_pe *pe; 1469 struct pnv_ioda_pe *pe;
1470 struct pci_dn *pdn; 1470 struct pci_dn *pdn;
1471 struct pci_sriov *iov;
1472 u16 num_vfs, i; 1471 u16 num_vfs, i;
1473 1472
1474 bus = pdev->bus; 1473 bus = pdev->bus;
1475 hose = pci_bus_to_host(bus); 1474 hose = pci_bus_to_host(bus);
1476 phb = hose->private_data; 1475 phb = hose->private_data;
1477 pdn = pci_get_pdn(pdev); 1476 pdn = pci_get_pdn(pdev);
1478 iov = pdev->sriov;
1479 num_vfs = pdn->num_vfs; 1477 num_vfs = pdn->num_vfs;
1480 1478
1481 /* Release VF PEs */ 1479 /* Release VF PEs */
diff --git a/arch/powerpc/platforms/pseries/dlpar.c b/arch/powerpc/platforms/pseries/dlpar.c
index d3a81e746fc4..193e052fa0dd 100644
--- a/arch/powerpc/platforms/pseries/dlpar.c
+++ b/arch/powerpc/platforms/pseries/dlpar.c
@@ -354,11 +354,17 @@ static int handle_dlpar_errorlog(struct pseries_hp_errorlog *hp_elog)
354 switch (hp_elog->id_type) { 354 switch (hp_elog->id_type) {
355 case PSERIES_HP_ELOG_ID_DRC_COUNT: 355 case PSERIES_HP_ELOG_ID_DRC_COUNT:
356 hp_elog->_drc_u.drc_count = 356 hp_elog->_drc_u.drc_count =
357 be32_to_cpu(hp_elog->_drc_u.drc_count); 357 be32_to_cpu(hp_elog->_drc_u.drc_count);
358 break; 358 break;
359 case PSERIES_HP_ELOG_ID_DRC_INDEX: 359 case PSERIES_HP_ELOG_ID_DRC_INDEX:
360 hp_elog->_drc_u.drc_index = 360 hp_elog->_drc_u.drc_index =
361 be32_to_cpu(hp_elog->_drc_u.drc_index); 361 be32_to_cpu(hp_elog->_drc_u.drc_index);
362 break;
363 case PSERIES_HP_ELOG_ID_DRC_IC:
364 hp_elog->_drc_u.ic.count =
365 be32_to_cpu(hp_elog->_drc_u.ic.count);
366 hp_elog->_drc_u.ic.index =
367 be32_to_cpu(hp_elog->_drc_u.ic.index);
362 } 368 }
363 369
364 switch (hp_elog->resource) { 370 switch (hp_elog->resource) {
@@ -467,7 +473,33 @@ static int dlpar_parse_id_type(char **cmd, struct pseries_hp_errorlog *hp_elog)
467 if (!arg) 473 if (!arg)
468 return -EINVAL; 474 return -EINVAL;
469 475
470 if (sysfs_streq(arg, "index")) { 476 if (sysfs_streq(arg, "indexed-count")) {
477 hp_elog->id_type = PSERIES_HP_ELOG_ID_DRC_IC;
478 arg = strsep(cmd, " ");
479 if (!arg) {
480 pr_err("No DRC count specified.\n");
481 return -EINVAL;
482 }
483
484 if (kstrtou32(arg, 0, &count)) {
485 pr_err("Invalid DRC count specified.\n");
486 return -EINVAL;
487 }
488
489 arg = strsep(cmd, " ");
490 if (!arg) {
491 pr_err("No DRC Index specified.\n");
492 return -EINVAL;
493 }
494
495 if (kstrtou32(arg, 0, &index)) {
496 pr_err("Invalid DRC Index specified.\n");
497 return -EINVAL;
498 }
499
500 hp_elog->_drc_u.ic.count = cpu_to_be32(count);
501 hp_elog->_drc_u.ic.index = cpu_to_be32(index);
502 } else if (sysfs_streq(arg, "index")) {
471 hp_elog->id_type = PSERIES_HP_ELOG_ID_DRC_INDEX; 503 hp_elog->id_type = PSERIES_HP_ELOG_ID_DRC_INDEX;
472 arg = strsep(cmd, " "); 504 arg = strsep(cmd, " ");
473 if (!arg) { 505 if (!arg) {
diff --git a/arch/powerpc/platforms/pseries/hotplug-memory.c b/arch/powerpc/platforms/pseries/hotplug-memory.c
index 3381c20edbc0..e104c71ea44a 100644
--- a/arch/powerpc/platforms/pseries/hotplug-memory.c
+++ b/arch/powerpc/platforms/pseries/hotplug-memory.c
@@ -320,6 +320,19 @@ static int dlpar_remove_device_tree_lmb(struct of_drconf_cell *lmb)
320 return dlpar_update_device_tree_lmb(lmb); 320 return dlpar_update_device_tree_lmb(lmb);
321} 321}
322 322
323static struct memory_block *lmb_to_memblock(struct of_drconf_cell *lmb)
324{
325 unsigned long section_nr;
326 struct mem_section *mem_sect;
327 struct memory_block *mem_block;
328
329 section_nr = pfn_to_section_nr(PFN_DOWN(lmb->base_addr));
330 mem_sect = __nr_to_section(section_nr);
331
332 mem_block = find_memory_block(mem_sect);
333 return mem_block;
334}
335
323#ifdef CONFIG_MEMORY_HOTREMOVE 336#ifdef CONFIG_MEMORY_HOTREMOVE
324static int pseries_remove_memblock(unsigned long base, unsigned int memblock_size) 337static int pseries_remove_memblock(unsigned long base, unsigned int memblock_size)
325{ 338{
@@ -407,19 +420,6 @@ static bool lmb_is_removable(struct of_drconf_cell *lmb)
407 420
408static int dlpar_add_lmb(struct of_drconf_cell *); 421static int dlpar_add_lmb(struct of_drconf_cell *);
409 422
410static struct memory_block *lmb_to_memblock(struct of_drconf_cell *lmb)
411{
412 unsigned long section_nr;
413 struct mem_section *mem_sect;
414 struct memory_block *mem_block;
415
416 section_nr = pfn_to_section_nr(PFN_DOWN(lmb->base_addr));
417 mem_sect = __nr_to_section(section_nr);
418
419 mem_block = find_memory_block(mem_sect);
420 return mem_block;
421}
422
423static int dlpar_remove_lmb(struct of_drconf_cell *lmb) 423static int dlpar_remove_lmb(struct of_drconf_cell *lmb)
424{ 424{
425 struct memory_block *mem_block; 425 struct memory_block *mem_block;
@@ -601,6 +601,94 @@ static int dlpar_memory_readd_by_index(u32 drc_index, struct property *prop)
601 601
602 return rc; 602 return rc;
603} 603}
604
605static int dlpar_memory_remove_by_ic(u32 lmbs_to_remove, u32 drc_index,
606 struct property *prop)
607{
608 struct of_drconf_cell *lmbs;
609 u32 num_lmbs, *p;
610 int i, rc, start_lmb_found;
611 int lmbs_available = 0, start_index = 0, end_index;
612
613 pr_info("Attempting to hot-remove %u LMB(s) at %x\n",
614 lmbs_to_remove, drc_index);
615
616 if (lmbs_to_remove == 0)
617 return -EINVAL;
618
619 p = prop->value;
620 num_lmbs = *p++;
621 lmbs = (struct of_drconf_cell *)p;
622 start_lmb_found = 0;
623
624 /* Navigate to drc_index */
625 while (start_index < num_lmbs) {
626 if (lmbs[start_index].drc_index == drc_index) {
627 start_lmb_found = 1;
628 break;
629 }
630
631 start_index++;
632 }
633
634 if (!start_lmb_found)
635 return -EINVAL;
636
637 end_index = start_index + lmbs_to_remove;
638
639 /* Validate that there are enough LMBs to satisfy the request */
640 for (i = start_index; i < end_index; i++) {
641 if (lmbs[i].flags & DRCONF_MEM_RESERVED)
642 break;
643
644 lmbs_available++;
645 }
646
647 if (lmbs_available < lmbs_to_remove)
648 return -EINVAL;
649
650 for (i = start_index; i < end_index; i++) {
651 if (!(lmbs[i].flags & DRCONF_MEM_ASSIGNED))
652 continue;
653
654 rc = dlpar_remove_lmb(&lmbs[i]);
655 if (rc)
656 break;
657
658 lmbs[i].reserved = 1;
659 }
660
661 if (rc) {
662 pr_err("Memory indexed-count-remove failed, adding any removed LMBs\n");
663
664 for (i = start_index; i < end_index; i++) {
665 if (!lmbs[i].reserved)
666 continue;
667
668 rc = dlpar_add_lmb(&lmbs[i]);
669 if (rc)
670 pr_err("Failed to add LMB, drc index %x\n",
671 be32_to_cpu(lmbs[i].drc_index));
672
673 lmbs[i].reserved = 0;
674 }
675 rc = -EINVAL;
676 } else {
677 for (i = start_index; i < end_index; i++) {
678 if (!lmbs[i].reserved)
679 continue;
680
681 dlpar_release_drc(lmbs[i].drc_index);
682 pr_info("Memory at %llx (drc index %x) was hot-removed\n",
683 lmbs[i].base_addr, lmbs[i].drc_index);
684
685 lmbs[i].reserved = 0;
686 }
687 }
688
689 return rc;
690}
691
604#else 692#else
605static inline int pseries_remove_memblock(unsigned long base, 693static inline int pseries_remove_memblock(unsigned long base,
606 unsigned int memblock_size) 694 unsigned int memblock_size)
@@ -628,9 +716,32 @@ static int dlpar_memory_remove_by_index(u32 drc_index, struct property *prop)
628{ 716{
629 return -EOPNOTSUPP; 717 return -EOPNOTSUPP;
630} 718}
719static int dlpar_memory_readd_by_index(u32 drc_index, struct property *prop)
720{
721 return -EOPNOTSUPP;
722}
631 723
724static int dlpar_memory_remove_by_ic(u32 lmbs_to_remove, u32 drc_index,
725 struct property *prop)
726{
727 return -EOPNOTSUPP;
728}
632#endif /* CONFIG_MEMORY_HOTREMOVE */ 729#endif /* CONFIG_MEMORY_HOTREMOVE */
633 730
731static int dlpar_online_lmb(struct of_drconf_cell *lmb)
732{
733 struct memory_block *mem_block;
734 int rc;
735
736 mem_block = lmb_to_memblock(lmb);
737 if (!mem_block)
738 return -EINVAL;
739
740 rc = device_online(&mem_block->dev);
741 put_device(&mem_block->dev);
742 return rc;
743}
744
634static int dlpar_add_lmb(struct of_drconf_cell *lmb) 745static int dlpar_add_lmb(struct of_drconf_cell *lmb)
635{ 746{
636 unsigned long block_sz; 747 unsigned long block_sz;
@@ -654,10 +765,18 @@ static int dlpar_add_lmb(struct of_drconf_cell *lmb)
654 765
655 /* Add the memory */ 766 /* Add the memory */
656 rc = add_memory(nid, lmb->base_addr, block_sz); 767 rc = add_memory(nid, lmb->base_addr, block_sz);
657 if (rc) 768 if (rc) {
658 dlpar_remove_device_tree_lmb(lmb); 769 dlpar_remove_device_tree_lmb(lmb);
659 else 770 return rc;
771 }
772
773 rc = dlpar_online_lmb(lmb);
774 if (rc) {
775 remove_memory(nid, lmb->base_addr, block_sz);
776 dlpar_remove_device_tree_lmb(lmb);
777 } else {
660 lmb->flags |= DRCONF_MEM_ASSIGNED; 778 lmb->flags |= DRCONF_MEM_ASSIGNED;
779 }
661 780
662 return rc; 781 return rc;
663} 782}
@@ -776,6 +895,97 @@ static int dlpar_memory_add_by_index(u32 drc_index, struct property *prop)
776 return rc; 895 return rc;
777} 896}
778 897
898static int dlpar_memory_add_by_ic(u32 lmbs_to_add, u32 drc_index,
899 struct property *prop)
900{
901 struct of_drconf_cell *lmbs;
902 u32 num_lmbs, *p;
903 int i, rc, start_lmb_found;
904 int lmbs_available = 0, start_index = 0, end_index;
905
906 pr_info("Attempting to hot-add %u LMB(s) at index %x\n",
907 lmbs_to_add, drc_index);
908
909 if (lmbs_to_add == 0)
910 return -EINVAL;
911
912 p = prop->value;
913 num_lmbs = *p++;
914 lmbs = (struct of_drconf_cell *)p;
915 start_lmb_found = 0;
916
917 /* Navigate to drc_index */
918 while (start_index < num_lmbs) {
919 if (lmbs[start_index].drc_index == drc_index) {
920 start_lmb_found = 1;
921 break;
922 }
923
924 start_index++;
925 }
926
927 if (!start_lmb_found)
928 return -EINVAL;
929
930 end_index = start_index + lmbs_to_add;
931
932 /* Validate that the LMBs in this range are not reserved */
933 for (i = start_index; i < end_index; i++) {
934 if (lmbs[i].flags & DRCONF_MEM_RESERVED)
935 break;
936
937 lmbs_available++;
938 }
939
940 if (lmbs_available < lmbs_to_add)
941 return -EINVAL;
942
943 for (i = start_index; i < end_index; i++) {
944 if (lmbs[i].flags & DRCONF_MEM_ASSIGNED)
945 continue;
946
947 rc = dlpar_acquire_drc(lmbs[i].drc_index);
948 if (rc)
949 break;
950
951 rc = dlpar_add_lmb(&lmbs[i]);
952 if (rc) {
953 dlpar_release_drc(lmbs[i].drc_index);
954 break;
955 }
956
957 lmbs[i].reserved = 1;
958 }
959
960 if (rc) {
961 pr_err("Memory indexed-count-add failed, removing any added LMBs\n");
962
963 for (i = start_index; i < end_index; i++) {
964 if (!lmbs[i].reserved)
965 continue;
966
967 rc = dlpar_remove_lmb(&lmbs[i]);
968 if (rc)
969 pr_err("Failed to remove LMB, drc index %x\n",
970 be32_to_cpu(lmbs[i].drc_index));
971 else
972 dlpar_release_drc(lmbs[i].drc_index);
973 }
974 rc = -EINVAL;
975 } else {
976 for (i = start_index; i < end_index; i++) {
977 if (!lmbs[i].reserved)
978 continue;
979
980 pr_info("Memory at %llx (drc index %x) was hot-added\n",
981 lmbs[i].base_addr, lmbs[i].drc_index);
982 lmbs[i].reserved = 0;
983 }
984 }
985
986 return rc;
987}
988
779int dlpar_memory(struct pseries_hp_errorlog *hp_elog) 989int dlpar_memory(struct pseries_hp_errorlog *hp_elog)
780{ 990{
781 struct device_node *dn; 991 struct device_node *dn;
@@ -783,9 +993,6 @@ int dlpar_memory(struct pseries_hp_errorlog *hp_elog)
783 u32 count, drc_index; 993 u32 count, drc_index;
784 int rc; 994 int rc;
785 995
786 count = hp_elog->_drc_u.drc_count;
787 drc_index = hp_elog->_drc_u.drc_index;
788
789 lock_device_hotplug(); 996 lock_device_hotplug();
790 997
791 dn = of_find_node_by_path("/ibm,dynamic-reconfiguration-memory"); 998 dn = of_find_node_by_path("/ibm,dynamic-reconfiguration-memory");
@@ -802,22 +1009,39 @@ int dlpar_memory(struct pseries_hp_errorlog *hp_elog)
802 1009
803 switch (hp_elog->action) { 1010 switch (hp_elog->action) {
804 case PSERIES_HP_ELOG_ACTION_ADD: 1011 case PSERIES_HP_ELOG_ACTION_ADD:
805 if (hp_elog->id_type == PSERIES_HP_ELOG_ID_DRC_COUNT) 1012 if (hp_elog->id_type == PSERIES_HP_ELOG_ID_DRC_COUNT) {
1013 count = hp_elog->_drc_u.drc_count;
806 rc = dlpar_memory_add_by_count(count, prop); 1014 rc = dlpar_memory_add_by_count(count, prop);
807 else if (hp_elog->id_type == PSERIES_HP_ELOG_ID_DRC_INDEX) 1015 } else if (hp_elog->id_type == PSERIES_HP_ELOG_ID_DRC_INDEX) {
1016 drc_index = hp_elog->_drc_u.drc_index;
808 rc = dlpar_memory_add_by_index(drc_index, prop); 1017 rc = dlpar_memory_add_by_index(drc_index, prop);
809 else 1018 } else if (hp_elog->id_type == PSERIES_HP_ELOG_ID_DRC_IC) {
1019 count = hp_elog->_drc_u.ic.count;
1020 drc_index = hp_elog->_drc_u.ic.index;
1021 rc = dlpar_memory_add_by_ic(count, drc_index, prop);
1022 } else {
810 rc = -EINVAL; 1023 rc = -EINVAL;
1024 }
1025
811 break; 1026 break;
812 case PSERIES_HP_ELOG_ACTION_REMOVE: 1027 case PSERIES_HP_ELOG_ACTION_REMOVE:
813 if (hp_elog->id_type == PSERIES_HP_ELOG_ID_DRC_COUNT) 1028 if (hp_elog->id_type == PSERIES_HP_ELOG_ID_DRC_COUNT) {
1029 count = hp_elog->_drc_u.drc_count;
814 rc = dlpar_memory_remove_by_count(count, prop); 1030 rc = dlpar_memory_remove_by_count(count, prop);
815 else if (hp_elog->id_type == PSERIES_HP_ELOG_ID_DRC_INDEX) 1031 } else if (hp_elog->id_type == PSERIES_HP_ELOG_ID_DRC_INDEX) {
1032 drc_index = hp_elog->_drc_u.drc_index;
816 rc = dlpar_memory_remove_by_index(drc_index, prop); 1033 rc = dlpar_memory_remove_by_index(drc_index, prop);
817 else 1034 } else if (hp_elog->id_type == PSERIES_HP_ELOG_ID_DRC_IC) {
1035 count = hp_elog->_drc_u.ic.count;
1036 drc_index = hp_elog->_drc_u.ic.index;
1037 rc = dlpar_memory_remove_by_ic(count, drc_index, prop);
1038 } else {
818 rc = -EINVAL; 1039 rc = -EINVAL;
1040 }
1041
819 break; 1042 break;
820 case PSERIES_HP_ELOG_ACTION_READD: 1043 case PSERIES_HP_ELOG_ACTION_READD:
1044 drc_index = hp_elog->_drc_u.drc_index;
821 rc = dlpar_memory_readd_by_index(drc_index, prop); 1045 rc = dlpar_memory_readd_by_index(drc_index, prop);
822 break; 1046 break;
823 default: 1047 default:
diff --git a/arch/powerpc/xmon/ppc-dis.c b/arch/powerpc/xmon/ppc-dis.c
index ee9891734149..31db8c072acd 100644
--- a/arch/powerpc/xmon/ppc-dis.c
+++ b/arch/powerpc/xmon/ppc-dis.c
@@ -1,6 +1,5 @@
1/* ppc-dis.c -- Disassemble PowerPC instructions 1/* ppc-dis.c -- Disassemble PowerPC instructions
2 Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006 2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
3 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support 3 Written by Ian Lance Taylor, Cygnus Support
5 4
6This file is part of GDB, GAS, and the GNU binutils. 5This file is part of GDB, GAS, and the GNU binutils.
@@ -26,57 +25,94 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, US
26#include "ppc.h" 25#include "ppc.h"
27#include "dis-asm.h" 26#include "dis-asm.h"
28 27
29/* Print a PowerPC or POWER instruction. */ 28/* This file provides several disassembler functions, all of which use
29 the disassembler interface defined in dis-asm.h. Several functions
30 are provided because this file handles disassembly for the PowerPC
31 in both big and little endian mode and also for the POWER (RS/6000)
32 chip. */
33
34/* Extract the operand value from the PowerPC or POWER instruction. */
30 35
31int 36static long
32print_insn_powerpc (unsigned long insn, unsigned long memaddr) 37operand_value_powerpc (const struct powerpc_operand *operand,
38 unsigned long insn, ppc_cpu_t dialect)
33{ 39{
34 const struct powerpc_opcode *opcode; 40 long value;
35 const struct powerpc_opcode *opcode_end; 41 int invalid;
36 unsigned long op; 42 /* Extract the value from the instruction. */
37 int dialect; 43 if (operand->extract)
44 value = (*operand->extract) (insn, dialect, &invalid);
45 else
46 {
47 if (operand->shift >= 0)
48 value = (insn >> operand->shift) & operand->bitm;
49 else
50 value = (insn << -operand->shift) & operand->bitm;
51 if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
52 {
53 /* BITM is always some number of zeros followed by some
54 number of ones, followed by some number of zeros. */
55 unsigned long top = operand->bitm;
56 /* top & -top gives the rightmost 1 bit, so this
57 fills in any trailing zeros. */
58 top |= (top & -top) - 1;
59 top &= ~(top >> 1);
60 value = (value ^ top) - top;
61 }
62 }
38 63
39 dialect = PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_COMMON 64 return value;
40 | PPC_OPCODE_64 | PPC_OPCODE_POWER4 | PPC_OPCODE_ALTIVEC; 65}
41 66
42 if (cpu_has_feature(CPU_FTRS_POWER5)) 67/* Determine whether the optional operand(s) should be printed. */
43 dialect |= PPC_OPCODE_POWER5;
44 68
45 if (cpu_has_feature(CPU_FTRS_CELL)) 69static int
46 dialect |= PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC; 70skip_optional_operands (const unsigned char *opindex,
71 unsigned long insn, ppc_cpu_t dialect)
72{
73 const struct powerpc_operand *operand;
47 74
48 if (cpu_has_feature(CPU_FTRS_POWER6)) 75 for (; *opindex != 0; opindex++)
49 dialect |= PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC; 76 {
77 operand = &powerpc_operands[*opindex];
78 if ((operand->flags & PPC_OPERAND_NEXT) != 0
79 || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
80 && operand_value_powerpc (operand, insn, dialect) !=
81 ppc_optional_operand_value (operand)))
82 return 0;
83 }
84
85 return 1;
86}
87
88/* Find a match for INSN in the opcode table, given machine DIALECT.
89 A DIALECT of -1 is special, matching all machine opcode variations. */
90
91static const struct powerpc_opcode *
92lookup_powerpc (unsigned long insn, ppc_cpu_t dialect)
93{
94 const struct powerpc_opcode *opcode;
95 const struct powerpc_opcode *opcode_end;
96 unsigned long op;
50 97
51 /* Get the major opcode of the instruction. */ 98 /* Get the major opcode of the instruction. */
52 op = PPC_OP (insn); 99 op = PPC_OP (insn);
53 100
54 /* Find the first match in the opcode table. We could speed this up
55 a bit by doing a binary search on the major opcode. */
56 opcode_end = powerpc_opcodes + powerpc_num_opcodes; 101 opcode_end = powerpc_opcodes + powerpc_num_opcodes;
57 again: 102 /* Find the first match in the opcode table for this major opcode. */
58 for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++) 103 for (opcode = powerpc_opcodes; opcode < opcode_end; ++opcode)
59 { 104 {
60 unsigned long table_op;
61 const unsigned char *opindex; 105 const unsigned char *opindex;
62 const struct powerpc_operand *operand; 106 const struct powerpc_operand *operand;
63 int invalid; 107 int invalid;
64 int need_comma;
65 int need_paren;
66
67 table_op = PPC_OP (opcode->opcode);
68 if (op < table_op)
69 break;
70 if (op > table_op)
71 continue;
72 108
73 if ((insn & opcode->mask) != opcode->opcode 109 if ((insn & opcode->mask) != opcode->opcode
74 || (opcode->flags & dialect) == 0) 110 || (dialect != (ppc_cpu_t) -1
111 && ((opcode->flags & dialect) == 0
112 || (opcode->deprecated & dialect) != 0)))
75 continue; 113 continue;
76 114
77 /* Make two passes over the operands. First see if any of them 115 /* Check validity of operands. */
78 have extraction functions, and, if they do, make sure the
79 instruction is valid. */
80 invalid = 0; 116 invalid = 0;
81 for (opindex = opcode->operands; *opindex != 0; opindex++) 117 for (opindex = opcode->operands; *opindex != 0; opindex++)
82 { 118 {
@@ -87,14 +123,77 @@ print_insn_powerpc (unsigned long insn, unsigned long memaddr)
87 if (invalid) 123 if (invalid)
88 continue; 124 continue;
89 125
90 /* The instruction is valid. */ 126 return opcode;
91 printf("%s", opcode->name); 127 }
128
129 return NULL;
130}
131
132/* Print a PowerPC or POWER instruction. */
133
134int print_insn_powerpc (unsigned long insn, unsigned long memaddr)
135{
136 const struct powerpc_opcode *opcode;
137 bool insn_is_short;
138 ppc_cpu_t dialect;
139
140 dialect = PPC_OPCODE_PPC | PPC_OPCODE_COMMON
141 | PPC_OPCODE_64 | PPC_OPCODE_POWER4 | PPC_OPCODE_ALTIVEC;
142
143 if (cpu_has_feature(CPU_FTRS_POWER5))
144 dialect |= PPC_OPCODE_POWER5;
145
146 if (cpu_has_feature(CPU_FTRS_CELL))
147 dialect |= (PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC);
148
149 if (cpu_has_feature(CPU_FTRS_POWER6))
150 dialect |= (PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC);
151
152 if (cpu_has_feature(CPU_FTRS_POWER7))
153 dialect |= (PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7
154 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX);
155
156 if (cpu_has_feature(CPU_FTRS_POWER8))
157 dialect |= (PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7
158 | PPC_OPCODE_POWER8 | PPC_OPCODE_HTM
159 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_VSX);
160
161 if (cpu_has_feature(CPU_FTRS_POWER9))
162 dialect |= (PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7
163 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9 | PPC_OPCODE_HTM
164 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2
165 | PPC_OPCODE_VSX | PPC_OPCODE_VSX3),
166
167 /* Get the major opcode of the insn. */
168 opcode = NULL;
169 insn_is_short = false;
170
171 if (opcode == NULL)
172 opcode = lookup_powerpc (insn, dialect);
173 if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
174 opcode = lookup_powerpc (insn, (ppc_cpu_t) -1);
175
176 if (opcode != NULL)
177 {
178 const unsigned char *opindex;
179 const struct powerpc_operand *operand;
180 int need_comma;
181 int need_paren;
182 int skip_optional;
183
92 if (opcode->operands[0] != 0) 184 if (opcode->operands[0] != 0)
93 printf("\t"); 185 printf("%-7s ", opcode->name);
186 else
187 printf("%s", opcode->name);
188
189 if (insn_is_short)
190 /* The operands will be fetched out of the 16-bit instruction. */
191 insn >>= 16;
94 192
95 /* Now extract and print the operands. */ 193 /* Now extract and print the operands. */
96 need_comma = 0; 194 need_comma = 0;
97 need_paren = 0; 195 need_paren = 0;
196 skip_optional = -1;
98 for (opindex = opcode->operands; *opindex != 0; opindex++) 197 for (opindex = opcode->operands; *opindex != 0; opindex++)
99 { 198 {
100 long value; 199 long value;
@@ -107,23 +206,18 @@ print_insn_powerpc (unsigned long insn, unsigned long memaddr)
107 if ((operand->flags & PPC_OPERAND_FAKE) != 0) 206 if ((operand->flags & PPC_OPERAND_FAKE) != 0)
108 continue; 207 continue;
109 208
110 /* Extract the value from the instruction. */ 209 /* If all of the optional operands have the value zero,
111 if (operand->extract) 210 then don't print any of them. */
112 value = (*operand->extract) (insn, dialect, &invalid); 211 if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
113 else
114 { 212 {
115 value = (insn >> operand->shift) & ((1 << operand->bits) - 1); 213 if (skip_optional < 0)
116 if ((operand->flags & PPC_OPERAND_SIGNED) != 0 214 skip_optional = skip_optional_operands (opindex, insn,
117 && (value & (1 << (operand->bits - 1))) != 0) 215 dialect);
118 value -= 1 << operand->bits; 216 if (skip_optional)
217 continue;
119 } 218 }
120 219
121 /* If the operand is optional, and the value is zero, don't 220 value = operand_value_powerpc (operand, insn, dialect);
122 print anything. */
123 if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
124 && (operand->flags & PPC_OPERAND_NEXT) == 0
125 && value == 0)
126 continue;
127 221
128 if (need_comma) 222 if (need_comma)
129 { 223 {
@@ -139,30 +233,38 @@ print_insn_powerpc (unsigned long insn, unsigned long memaddr)
139 printf("f%ld", value); 233 printf("f%ld", value);
140 else if ((operand->flags & PPC_OPERAND_VR) != 0) 234 else if ((operand->flags & PPC_OPERAND_VR) != 0)
141 printf("v%ld", value); 235 printf("v%ld", value);
236 else if ((operand->flags & PPC_OPERAND_VSR) != 0)
237 printf("vs%ld", value);
142 else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0) 238 else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
143 print_address (memaddr + value); 239 print_address(memaddr + value);
144 else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0) 240 else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
145 print_address (value & 0xffffffff); 241 print_address(value & 0xffffffff);
146 else if ((operand->flags & PPC_OPERAND_CR) == 0 242 else if ((operand->flags & PPC_OPERAND_FSL) != 0)
147 || (dialect & PPC_OPCODE_PPC) == 0) 243 printf("fsl%ld", value);
244 else if ((operand->flags & PPC_OPERAND_FCR) != 0)
245 printf("fcr%ld", value);
246 else if ((operand->flags & PPC_OPERAND_UDI) != 0)
148 printf("%ld", value); 247 printf("%ld", value);
149 else 248 else if ((operand->flags & PPC_OPERAND_CR_REG) != 0
249 && (((dialect & PPC_OPCODE_PPC) != 0)
250 || ((dialect & PPC_OPCODE_VLE) != 0)))
251 printf("cr%ld", value);
252 else if (((operand->flags & PPC_OPERAND_CR_BIT) != 0)
253 && (((dialect & PPC_OPCODE_PPC) != 0)
254 || ((dialect & PPC_OPCODE_VLE) != 0)))
150 { 255 {
151 if (operand->bits == 3) 256 static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
152 printf("cr%ld", value); 257 int cr;
153 else 258 int cc;
154 { 259
155 static const char *cbnames[4] = { "lt", "gt", "eq", "so" }; 260 cr = value >> 2;
156 int cr; 261 if (cr != 0)
157 int cc; 262 printf("4*cr%d+", cr);
158 263 cc = value & 3;
159 cr = value >> 2; 264 printf("%s", cbnames[cc]);
160 if (cr != 0)
161 printf("4*cr%d+", cr);
162 cc = value & 3;
163 printf("%s", cbnames[cc]);
164 }
165 } 265 }
266 else
267 printf("%d", (int) value);
166 268
167 if (need_paren) 269 if (need_paren)
168 { 270 {
@@ -179,14 +281,16 @@ print_insn_powerpc (unsigned long insn, unsigned long memaddr)
179 } 281 }
180 } 282 }
181 283
182 /* We have found and printed an instruction; return. */ 284 /* We have found and printed an instruction.
183 return 4; 285 If it was a short VLE instruction we have more to do. */
184 } 286 if (insn_is_short)
185 287 {
186 if ((dialect & PPC_OPCODE_ANY) != 0) 288 memaddr += 2;
187 { 289 return 2;
188 dialect = ~PPC_OPCODE_ANY; 290 }
189 goto again; 291 else
292 /* Otherwise, return. */
293 return 4;
190 } 294 }
191 295
192 /* We could not find a match. */ 296 /* We could not find a match. */
diff --git a/arch/powerpc/xmon/ppc-opc.c b/arch/powerpc/xmon/ppc-opc.c
index 954dbf8222d7..ac2b55b1332e 100644
--- a/arch/powerpc/xmon/ppc-opc.c
+++ b/arch/powerpc/xmon/ppc-opc.c
@@ -1,6 +1,5 @@
1/* ppc-opc.c -- PowerPC opcode list 1/* ppc-opc.c -- PowerPC opcode list
2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004, 2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
3 2005 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support 3 Written by Ian Lance Taylor, Cygnus Support
5 4
6 This file is part of GDB, GAS, and the GNU binutils. 5 This file is part of GDB, GAS, and the GNU binutils.
@@ -42,66 +41,97 @@
42 41
43/* Local insertion and extraction functions. */ 42/* Local insertion and extraction functions. */
44 43
45static unsigned long insert_bat (unsigned long, long, int, const char **); 44static unsigned long insert_arx (unsigned long, long, ppc_cpu_t, const char **);
46static long extract_bat (unsigned long, int, int *); 45static long extract_arx (unsigned long, ppc_cpu_t, int *);
47static unsigned long insert_bba (unsigned long, long, int, const char **); 46static unsigned long insert_ary (unsigned long, long, ppc_cpu_t, const char **);
48static long extract_bba (unsigned long, int, int *); 47static long extract_ary (unsigned long, ppc_cpu_t, int *);
49static unsigned long insert_bd (unsigned long, long, int, const char **); 48static unsigned long insert_bat (unsigned long, long, ppc_cpu_t, const char **);
50static long extract_bd (unsigned long, int, int *); 49static long extract_bat (unsigned long, ppc_cpu_t, int *);
51static unsigned long insert_bdm (unsigned long, long, int, const char **); 50static unsigned long insert_bba (unsigned long, long, ppc_cpu_t, const char **);
52static long extract_bdm (unsigned long, int, int *); 51static long extract_bba (unsigned long, ppc_cpu_t, int *);
53static unsigned long insert_bdp (unsigned long, long, int, const char **); 52static unsigned long insert_bdm (unsigned long, long, ppc_cpu_t, const char **);
54static long extract_bdp (unsigned long, int, int *); 53static long extract_bdm (unsigned long, ppc_cpu_t, int *);
55static unsigned long insert_bo (unsigned long, long, int, const char **); 54static unsigned long insert_bdp (unsigned long, long, ppc_cpu_t, const char **);
56static long extract_bo (unsigned long, int, int *); 55static long extract_bdp (unsigned long, ppc_cpu_t, int *);
57static unsigned long insert_boe (unsigned long, long, int, const char **); 56static unsigned long insert_bo (unsigned long, long, ppc_cpu_t, const char **);
58static long extract_boe (unsigned long, int, int *); 57static long extract_bo (unsigned long, ppc_cpu_t, int *);
59static unsigned long insert_dq (unsigned long, long, int, const char **); 58static unsigned long insert_boe (unsigned long, long, ppc_cpu_t, const char **);
60static long extract_dq (unsigned long, int, int *); 59static long extract_boe (unsigned long, ppc_cpu_t, int *);
61static unsigned long insert_ds (unsigned long, long, int, const char **); 60static unsigned long insert_esync (unsigned long, long, ppc_cpu_t, const char **);
62static long extract_ds (unsigned long, int, int *); 61static unsigned long insert_dcmxs (unsigned long, long, ppc_cpu_t, const char **);
63static unsigned long insert_de (unsigned long, long, int, const char **); 62static long extract_dcmxs (unsigned long, ppc_cpu_t, int *);
64static long extract_de (unsigned long, int, int *); 63static unsigned long insert_dxd (unsigned long, long, ppc_cpu_t, const char **);
65static unsigned long insert_des (unsigned long, long, int, const char **); 64static long extract_dxd (unsigned long, ppc_cpu_t, int *);
66static long extract_des (unsigned long, int, int *); 65static unsigned long insert_dxdn (unsigned long, long, ppc_cpu_t, const char **);
67static unsigned long insert_fxm (unsigned long, long, int, const char **); 66static long extract_dxdn (unsigned long, ppc_cpu_t, int *);
68static long extract_fxm (unsigned long, int, int *); 67static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **);
69static unsigned long insert_li (unsigned long, long, int, const char **); 68static long extract_fxm (unsigned long, ppc_cpu_t, int *);
70static long extract_li (unsigned long, int, int *); 69static unsigned long insert_li20 (unsigned long, long, ppc_cpu_t, const char **);
71static unsigned long insert_mbe (unsigned long, long, int, const char **); 70static long extract_li20 (unsigned long, ppc_cpu_t, int *);
72static long extract_mbe (unsigned long, int, int *); 71static unsigned long insert_ls (unsigned long, long, ppc_cpu_t, const char **);
73static unsigned long insert_mb6 (unsigned long, long, int, const char **); 72static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t, const char **);
74static long extract_mb6 (unsigned long, int, int *); 73static long extract_mbe (unsigned long, ppc_cpu_t, int *);
75static unsigned long insert_nb (unsigned long, long, int, const char **); 74static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t, const char **);
76static long extract_nb (unsigned long, int, int *); 75static long extract_mb6 (unsigned long, ppc_cpu_t, int *);
77static unsigned long insert_nsi (unsigned long, long, int, const char **); 76static long extract_nb (unsigned long, ppc_cpu_t, int *);
78static long extract_nsi (unsigned long, int, int *); 77static unsigned long insert_nbi (unsigned long, long, ppc_cpu_t, const char **);
79static unsigned long insert_ral (unsigned long, long, int, const char **); 78static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t, const char **);
80static unsigned long insert_ram (unsigned long, long, int, const char **); 79static long extract_nsi (unsigned long, ppc_cpu_t, int *);
81static unsigned long insert_raq (unsigned long, long, int, const char **); 80static unsigned long insert_oimm (unsigned long, long, ppc_cpu_t, const char **);
82static unsigned long insert_ras (unsigned long, long, int, const char **); 81static long extract_oimm (unsigned long, ppc_cpu_t, int *);
83static unsigned long insert_rbs (unsigned long, long, int, const char **); 82static unsigned long insert_ral (unsigned long, long, ppc_cpu_t, const char **);
84static long extract_rbs (unsigned long, int, int *); 83static unsigned long insert_ram (unsigned long, long, ppc_cpu_t, const char **);
85static unsigned long insert_rsq (unsigned long, long, int, const char **); 84static unsigned long insert_raq (unsigned long, long, ppc_cpu_t, const char **);
86static unsigned long insert_rtq (unsigned long, long, int, const char **); 85static unsigned long insert_ras (unsigned long, long, ppc_cpu_t, const char **);
87static unsigned long insert_sh6 (unsigned long, long, int, const char **); 86static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t, const char **);
88static long extract_sh6 (unsigned long, int, int *); 87static long extract_rbs (unsigned long, ppc_cpu_t, int *);
89static unsigned long insert_spr (unsigned long, long, int, const char **); 88static unsigned long insert_rbx (unsigned long, long, ppc_cpu_t, const char **);
90static long extract_spr (unsigned long, int, int *); 89static unsigned long insert_rx (unsigned long, long, ppc_cpu_t, const char **);
91static unsigned long insert_sprg (unsigned long, long, int, const char **); 90static long extract_rx (unsigned long, ppc_cpu_t, int *);
92static long extract_sprg (unsigned long, int, int *); 91static unsigned long insert_ry (unsigned long, long, ppc_cpu_t, const char **);
93static unsigned long insert_tbr (unsigned long, long, int, const char **); 92static long extract_ry (unsigned long, ppc_cpu_t, int *);
94static long extract_tbr (unsigned long, int, int *); 93static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t, const char **);
95static unsigned long insert_ev2 (unsigned long, long, int, const char **); 94static long extract_sh6 (unsigned long, ppc_cpu_t, int *);
96static long extract_ev2 (unsigned long, int, int *); 95static unsigned long insert_sci8 (unsigned long, long, ppc_cpu_t, const char **);
97static unsigned long insert_ev4 (unsigned long, long, int, const char **); 96static long extract_sci8 (unsigned long, ppc_cpu_t, int *);
98static long extract_ev4 (unsigned long, int, int *); 97static unsigned long insert_sci8n (unsigned long, long, ppc_cpu_t, const char **);
99static unsigned long insert_ev8 (unsigned long, long, int, const char **); 98static long extract_sci8n (unsigned long, ppc_cpu_t, int *);
100static long extract_ev8 (unsigned long, int, int *); 99static unsigned long insert_sd4h (unsigned long, long, ppc_cpu_t, const char **);
100static long extract_sd4h (unsigned long, ppc_cpu_t, int *);
101static unsigned long insert_sd4w (unsigned long, long, ppc_cpu_t, const char **);
102static long extract_sd4w (unsigned long, ppc_cpu_t, int *);
103static unsigned long insert_spr (unsigned long, long, ppc_cpu_t, const char **);
104static long extract_spr (unsigned long, ppc_cpu_t, int *);
105static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t, const char **);
106static long extract_sprg (unsigned long, ppc_cpu_t, int *);
107static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t, const char **);
108static long extract_tbr (unsigned long, ppc_cpu_t, int *);
109static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t, const char **);
110static long extract_xt6 (unsigned long, ppc_cpu_t, int *);
111static unsigned long insert_xtq6 (unsigned long, long, ppc_cpu_t, const char **);
112static long extract_xtq6 (unsigned long, ppc_cpu_t, int *);
113static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t, const char **);
114static long extract_xa6 (unsigned long, ppc_cpu_t, int *);
115static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t, const char **);
116static long extract_xb6 (unsigned long, ppc_cpu_t, int *);
117static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t, const char **);
118static long extract_xb6s (unsigned long, ppc_cpu_t, int *);
119static unsigned long insert_xc6 (unsigned long, long, ppc_cpu_t, const char **);
120static long extract_xc6 (unsigned long, ppc_cpu_t, int *);
121static unsigned long insert_dm (unsigned long, long, ppc_cpu_t, const char **);
122static long extract_dm (unsigned long, ppc_cpu_t, int *);
123static unsigned long insert_vlesi (unsigned long, long, ppc_cpu_t, const char **);
124static long extract_vlesi (unsigned long, ppc_cpu_t, int *);
125static unsigned long insert_vlensi (unsigned long, long, ppc_cpu_t, const char **);
126static long extract_vlensi (unsigned long, ppc_cpu_t, int *);
127static unsigned long insert_vleui (unsigned long, long, ppc_cpu_t, const char **);
128static long extract_vleui (unsigned long, ppc_cpu_t, int *);
129static unsigned long insert_vleil (unsigned long, long, ppc_cpu_t, const char **);
130static long extract_vleil (unsigned long, ppc_cpu_t, int *);
101 131
102/* The operands table. 132/* The operands table.
103 133
104 The fields are bits, shift, insert, extract, flags. 134 The fields are bitm, shift, insert, extract, flags.
105 135
106 We used to put parens around the various additions, like the one 136 We used to put parens around the various additions, like the one
107 for BA just below. However, that caused trouble with feeble 137 for BA just below. However, that caused trouble with feeble
@@ -119,493 +149,934 @@ const struct powerpc_operand powerpc_operands[] =
119 149
120 /* The BA field in an XL form instruction. */ 150 /* The BA field in an XL form instruction. */
121#define BA UNUSED + 1 151#define BA UNUSED + 1
122#define BA_MASK (0x1f << 16) 152 /* The BI field in a B form or XL form instruction. */
123 { 5, 16, NULL, NULL, PPC_OPERAND_CR }, 153#define BI BA
154#define BI_MASK (0x1f << 16)
155 { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
124 156
125 /* The BA field in an XL form instruction when it must be the same 157 /* The BA field in an XL form instruction when it must be the same
126 as the BT field in the same instruction. */ 158 as the BT field in the same instruction. */
127#define BAT BA + 1 159#define BAT BA + 1
128 { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE }, 160 { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
129 161
130 /* The BB field in an XL form instruction. */ 162 /* The BB field in an XL form instruction. */
131#define BB BAT + 1 163#define BB BAT + 1
132#define BB_MASK (0x1f << 11) 164#define BB_MASK (0x1f << 11)
133 { 5, 11, NULL, NULL, PPC_OPERAND_CR }, 165 { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR_BIT },
134 166
135 /* The BB field in an XL form instruction when it must be the same 167 /* The BB field in an XL form instruction when it must be the same
136 as the BA field in the same instruction. */ 168 as the BA field in the same instruction. */
137#define BBA BB + 1 169#define BBA BB + 1
138 { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE }, 170 /* The VB field in a VX form instruction when it must be the same
171 as the VA field in the same instruction. */
172#define VBA BBA
173 { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
139 174
140 /* The BD field in a B form instruction. The lower two bits are 175 /* The BD field in a B form instruction. The lower two bits are
141 forced to zero. */ 176 forced to zero. */
142#define BD BBA + 1 177#define BD BBA + 1
143 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 178 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
144 179
145 /* The BD field in a B form instruction when absolute addressing is 180 /* The BD field in a B form instruction when absolute addressing is
146 used. */ 181 used. */
147#define BDA BD + 1 182#define BDA BD + 1
148 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 183 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
149 184
150 /* The BD field in a B form instruction when the - modifier is used. 185 /* The BD field in a B form instruction when the - modifier is used.
151 This sets the y bit of the BO field appropriately. */ 186 This sets the y bit of the BO field appropriately. */
152#define BDM BDA + 1 187#define BDM BDA + 1
153 { 16, 0, insert_bdm, extract_bdm, 188 { 0xfffc, 0, insert_bdm, extract_bdm,
154 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 189 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
155 190
156 /* The BD field in a B form instruction when the - modifier is used 191 /* The BD field in a B form instruction when the - modifier is used
157 and absolute address is used. */ 192 and absolute address is used. */
158#define BDMA BDM + 1 193#define BDMA BDM + 1
159 { 16, 0, insert_bdm, extract_bdm, 194 { 0xfffc, 0, insert_bdm, extract_bdm,
160 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 195 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
161 196
162 /* The BD field in a B form instruction when the + modifier is used. 197 /* The BD field in a B form instruction when the + modifier is used.
163 This sets the y bit of the BO field appropriately. */ 198 This sets the y bit of the BO field appropriately. */
164#define BDP BDMA + 1 199#define BDP BDMA + 1
165 { 16, 0, insert_bdp, extract_bdp, 200 { 0xfffc, 0, insert_bdp, extract_bdp,
166 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 201 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
167 202
168 /* The BD field in a B form instruction when the + modifier is used 203 /* The BD field in a B form instruction when the + modifier is used
169 and absolute addressing is used. */ 204 and absolute addressing is used. */
170#define BDPA BDP + 1 205#define BDPA BDP + 1
171 { 16, 0, insert_bdp, extract_bdp, 206 { 0xfffc, 0, insert_bdp, extract_bdp,
172 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 207 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
173 208
174 /* The BF field in an X or XL form instruction. */ 209 /* The BF field in an X or XL form instruction. */
175#define BF BDPA + 1 210#define BF BDPA + 1
176 { 3, 23, NULL, NULL, PPC_OPERAND_CR }, 211 /* The CRFD field in an X form instruction. */
212#define CRFD BF
213 /* The CRD field in an XL form instruction. */
214#define CRD BF
215 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG },
216
217 /* The BF field in an X or XL form instruction. */
218#define BFF BF + 1
219 { 0x7, 23, NULL, NULL, 0 },
177 220
178 /* An optional BF field. This is used for comparison instructions, 221 /* An optional BF field. This is used for comparison instructions,
179 in which an omitted BF field is taken as zero. */ 222 in which an omitted BF field is taken as zero. */
180#define OBF BF + 1 223#define OBF BFF + 1
181 { 3, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, 224 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
182 225
183 /* The BFA field in an X or XL form instruction. */ 226 /* The BFA field in an X or XL form instruction. */
184#define BFA OBF + 1 227#define BFA OBF + 1
185 { 3, 18, NULL, NULL, PPC_OPERAND_CR }, 228 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG },
186
187 /* The BI field in a B form or XL form instruction. */
188#define BI BFA + 1
189#define BI_MASK (0x1f << 16)
190 { 5, 16, NULL, NULL, PPC_OPERAND_CR },
191 229
192 /* The BO field in a B form instruction. Certain values are 230 /* The BO field in a B form instruction. Certain values are
193 illegal. */ 231 illegal. */
194#define BO BI + 1 232#define BO BFA + 1
195#define BO_MASK (0x1f << 21) 233#define BO_MASK (0x1f << 21)
196 { 5, 21, insert_bo, extract_bo, 0 }, 234 { 0x1f, 21, insert_bo, extract_bo, 0 },
197 235
198 /* The BO field in a B form instruction when the + or - modifier is 236 /* The BO field in a B form instruction when the + or - modifier is
199 used. This is like the BO field, but it must be even. */ 237 used. This is like the BO field, but it must be even. */
200#define BOE BO + 1 238#define BOE BO + 1
201 { 5, 21, insert_boe, extract_boe, 0 }, 239 { 0x1e, 21, insert_boe, extract_boe, 0 },
240
241 /* The RM field in an X form instruction. */
242#define RM BOE + 1
243 { 0x3, 11, NULL, NULL, 0 },
202 244
203#define BH BOE + 1 245#define BH RM + 1
204 { 2, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, 246 { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
205 247
206 /* The BT field in an X or XL form instruction. */ 248 /* The BT field in an X or XL form instruction. */
207#define BT BH + 1 249#define BT BH + 1
208 { 5, 21, NULL, NULL, PPC_OPERAND_CR }, 250 { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR_BIT },
251
252 /* The BI16 field in a BD8 form instruction. */
253#define BI16 BT + 1
254 { 0x3, 8, NULL, NULL, PPC_OPERAND_CR_BIT },
255
256 /* The BI32 field in a BD15 form instruction. */
257#define BI32 BI16 + 1
258 { 0xf, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
259
260 /* The BO32 field in a BD15 form instruction. */
261#define BO32 BI32 + 1
262 { 0x3, 20, NULL, NULL, 0 },
263
264 /* The B8 field in a BD8 form instruction. */
265#define B8 BO32 + 1
266 { 0x1fe, -1, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
267
268 /* The B15 field in a BD15 form instruction. The lowest bit is
269 forced to zero. */
270#define B15 B8 + 1
271 { 0xfffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
272
273 /* The B24 field in a BD24 form instruction. The lowest bit is
274 forced to zero. */
275#define B24 B15 + 1
276 { 0x1fffffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
209 277
210 /* The condition register number portion of the BI field in a B form 278 /* The condition register number portion of the BI field in a B form
211 or XL form instruction. This is used for the extended 279 or XL form instruction. This is used for the extended
212 conditional branch mnemonics, which set the lower two bits of the 280 conditional branch mnemonics, which set the lower two bits of the
213 BI field. This field is optional. */ 281 BI field. This field is optional. */
214#define CR BT + 1 282#define CR B24 + 1
215 { 3, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, 283 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
216 284
217 /* The CRB field in an X form instruction. */ 285 /* The CRB field in an X form instruction. */
218#define CRB CR + 1 286#define CRB CR + 1
219 { 5, 6, NULL, NULL, 0 }, 287 /* The MB field in an M form instruction. */
288#define MB CRB
289#define MB_MASK (0x1f << 6)
290 { 0x1f, 6, NULL, NULL, 0 },
220 291
221 /* The CRFD field in an X form instruction. */ 292 /* The CRD32 field in an XL form instruction. */
222#define CRFD CRB + 1 293#define CRD32 CRB + 1
223 { 3, 23, NULL, NULL, PPC_OPERAND_CR }, 294 { 0x3, 21, NULL, NULL, PPC_OPERAND_CR_REG },
224 295
225 /* The CRFS field in an X form instruction. */ 296 /* The CRFS field in an X form instruction. */
226#define CRFS CRFD + 1 297#define CRFS CRD32 + 1
227 { 3, 0, NULL, NULL, PPC_OPERAND_CR }, 298 { 0x7, 0, NULL, NULL, PPC_OPERAND_CR_REG },
299
300#define CRS CRFS + 1
301 { 0x3, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
228 302
229 /* The CT field in an X form instruction. */ 303 /* The CT field in an X form instruction. */
230#define CT CRFS + 1 304#define CT CRS + 1
231 { 5, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, 305 /* The MO field in an mbar instruction. */
306#define MO CT
307 { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
232 308
233 /* The D field in a D form instruction. This is a displacement off 309 /* The D field in a D form instruction. This is a displacement off
234 a register, and implies that the next operand is a register in 310 a register, and implies that the next operand is a register in
235 parentheses. */ 311 parentheses. */
236#define D CT + 1 312#define D CT + 1
237 { 16, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, 313 { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
238 314
239 /* The DE field in a DE form instruction. This is like D, but is 12 315 /* The D8 field in a D form instruction. This is a displacement off
240 bits only. */ 316 a register, and implies that the next operand is a register in
241#define DE D + 1 317 parentheses. */
242 { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS }, 318#define D8 D + 1
319 { 0xff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
320
321 /* The DCMX field in an X form instruction. */
322#define DCMX D8 + 1
323 { 0x7f, 16, NULL, NULL, 0 },
243 324
244 /* The DES field in a DES form instruction. This is like DS, but is 14 325 /* The split DCMX field in an X form instruction. */
245 bits only (12 stored.) */ 326#define DCMXS DCMX + 1
246#define DES DE + 1 327 { 0x7f, PPC_OPSHIFT_INV, insert_dcmxs, extract_dcmxs, 0 },
247 { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
248 328
249 /* The DQ field in a DQ form instruction. This is like D, but the 329 /* The DQ field in a DQ form instruction. This is like D, but the
250 lower four bits are forced to zero. */ 330 lower four bits are forced to zero. */
251#define DQ DES + 1 331#define DQ DCMXS + 1
252 { 16, 0, insert_dq, extract_dq, 332 { 0xfff0, 0, NULL, NULL,
253 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ }, 333 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
254 334
255 /* The DS field in a DS form instruction. This is like D, but the 335 /* The DS field in a DS form instruction. This is like D, but the
256 lower two bits are forced to zero. */ 336 lower two bits are forced to zero. */
257#define DS DQ + 1 337#define DS DQ + 1
258 { 16, 0, insert_ds, extract_ds, 338 { 0xfffc, 0, NULL, NULL,
259 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS }, 339 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
340
341 /* The DUIS or BHRBE fields in a XFX form instruction, 10 bits
342 unsigned imediate */
343#define DUIS DS + 1
344#define BHRBE DUIS
345 { 0x3ff, 11, NULL, NULL, 0 },
346
347 /* The split D field in a DX form instruction. */
348#define DXD DUIS + 1
349 { 0xffff, PPC_OPSHIFT_INV, insert_dxd, extract_dxd,
350 PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT},
351
352 /* The split ND field in a DX form instruction.
353 This is the same as the DX field, only negated. */
354#define NDXD DXD + 1
355 { 0xffff, PPC_OPSHIFT_INV, insert_dxdn, extract_dxdn,
356 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT},
260 357
261 /* The E field in a wrteei instruction. */ 358 /* The E field in a wrteei instruction. */
262#define E DS + 1 359 /* And the W bit in the pair singles instructions. */
263 { 1, 15, NULL, NULL, 0 }, 360 /* And the ST field in a VX form instruction. */
361#define E NDXD + 1
362#define PSW E
363#define ST E
364 { 0x1, 15, NULL, NULL, 0 },
264 365
265 /* The FL1 field in a POWER SC form instruction. */ 366 /* The FL1 field in a POWER SC form instruction. */
266#define FL1 E + 1 367#define FL1 E + 1
267 { 4, 12, NULL, NULL, 0 }, 368 /* The U field in an X form instruction. */
369#define U FL1
370 { 0xf, 12, NULL, NULL, 0 },
268 371
269 /* The FL2 field in a POWER SC form instruction. */ 372 /* The FL2 field in a POWER SC form instruction. */
270#define FL2 FL1 + 1 373#define FL2 FL1 + 1
271 { 3, 2, NULL, NULL, 0 }, 374 { 0x7, 2, NULL, NULL, 0 },
272 375
273 /* The FLM field in an XFL form instruction. */ 376 /* The FLM field in an XFL form instruction. */
274#define FLM FL2 + 1 377#define FLM FL2 + 1
275 { 8, 17, NULL, NULL, 0 }, 378 { 0xff, 17, NULL, NULL, 0 },
276 379
277 /* The FRA field in an X or A form instruction. */ 380 /* The FRA field in an X or A form instruction. */
278#define FRA FLM + 1 381#define FRA FLM + 1
279#define FRA_MASK (0x1f << 16) 382#define FRA_MASK (0x1f << 16)
280 { 5, 16, NULL, NULL, PPC_OPERAND_FPR }, 383 { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
384
385 /* The FRAp field of DFP instructions. */
386#define FRAp FRA + 1
387 { 0x1e, 16, NULL, NULL, PPC_OPERAND_FPR },
281 388
282 /* The FRB field in an X or A form instruction. */ 389 /* The FRB field in an X or A form instruction. */
283#define FRB FRA + 1 390#define FRB FRAp + 1
284#define FRB_MASK (0x1f << 11) 391#define FRB_MASK (0x1f << 11)
285 { 5, 11, NULL, NULL, PPC_OPERAND_FPR }, 392 { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
393
394 /* The FRBp field of DFP instructions. */
395#define FRBp FRB + 1
396 { 0x1e, 11, NULL, NULL, PPC_OPERAND_FPR },
286 397
287 /* The FRC field in an A form instruction. */ 398 /* The FRC field in an A form instruction. */
288#define FRC FRB + 1 399#define FRC FRBp + 1
289#define FRC_MASK (0x1f << 6) 400#define FRC_MASK (0x1f << 6)
290 { 5, 6, NULL, NULL, PPC_OPERAND_FPR }, 401 { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
291 402
292 /* The FRS field in an X form instruction or the FRT field in a D, X 403 /* The FRS field in an X form instruction or the FRT field in a D, X
293 or A form instruction. */ 404 or A form instruction. */
294#define FRS FRC + 1 405#define FRS FRC + 1
295#define FRT FRS 406#define FRT FRS
296 { 5, 21, NULL, NULL, PPC_OPERAND_FPR }, 407 { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
408
409 /* The FRSp field of stfdp or the FRTp field of lfdp and DFP
410 instructions. */
411#define FRSp FRS + 1
412#define FRTp FRSp
413 { 0x1e, 21, NULL, NULL, PPC_OPERAND_FPR },
297 414
298 /* The FXM field in an XFX instruction. */ 415 /* The FXM field in an XFX instruction. */
299#define FXM FRS + 1 416#define FXM FRSp + 1
300#define FXM_MASK (0xff << 12) 417 { 0xff, 12, insert_fxm, extract_fxm, 0 },
301 { 8, 12, insert_fxm, extract_fxm, 0 },
302 418
303 /* Power4 version for mfcr. */ 419 /* Power4 version for mfcr. */
304#define FXM4 FXM + 1 420#define FXM4 FXM + 1
305 { 8, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL }, 421 { 0xff, 12, insert_fxm, extract_fxm,
422 PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
423 /* If the FXM4 operand is ommitted, use the sentinel value -1. */
424 { -1, -1, NULL, NULL, 0},
425
426 /* The IMM20 field in an LI instruction. */
427#define IMM20 FXM4 + 2
428 { 0xfffff, PPC_OPSHIFT_INV, insert_li20, extract_li20, PPC_OPERAND_SIGNED},
306 429
307 /* The L field in a D or X form instruction. */ 430 /* The L field in a D or X form instruction. */
308#define L FXM4 + 1 431#define L IMM20 + 1
309 { 1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, 432 { 0x1, 21, NULL, NULL, 0 },
433
434 /* The optional L field in tlbie and tlbiel instructions. */
435#define LOPT L + 1
436 /* The R field in a HTM X form instruction. */
437#define HTM_R LOPT
438 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
439
440 /* The optional (for 32-bit) L field in cmp[l][i] instructions. */
441#define L32OPT LOPT + 1
442 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL32 },
443
444 /* The L field in dcbf instruction. */
445#define L2OPT L32OPT + 1
446 { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
310 447
311 /* The LEV field in a POWER SVC form instruction. */ 448 /* The LEV field in a POWER SVC form instruction. */
312#define SVC_LEV L + 1 449#define SVC_LEV L2OPT + 1
313 { 7, 5, NULL, NULL, 0 }, 450 { 0x7f, 5, NULL, NULL, 0 },
314 451
315 /* The LEV field in an SC form instruction. */ 452 /* The LEV field in an SC form instruction. */
316#define LEV SVC_LEV + 1 453#define LEV SVC_LEV + 1
317 { 7, 5, NULL, NULL, PPC_OPERAND_OPTIONAL }, 454 { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
318 455
319 /* The LI field in an I form instruction. The lower two bits are 456 /* The LI field in an I form instruction. The lower two bits are
320 forced to zero. */ 457 forced to zero. */
321#define LI LEV + 1 458#define LI LEV + 1
322 { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 459 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
323 460
324 /* The LI field in an I form instruction when used as an absolute 461 /* The LI field in an I form instruction when used as an absolute
325 address. */ 462 address. */
326#define LIA LI + 1 463#define LIA LI + 1
327 { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 464 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
328 465
329 /* The LS field in an X (sync) form instruction. */ 466 /* The LS or WC field in an X (sync or wait) form instruction. */
330#define LS LIA + 1 467#define LS LIA + 1
331 { 2, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, 468#define WC LS
332 469 { 0x3, 21, insert_ls, NULL, PPC_OPERAND_OPTIONAL },
333 /* The MB field in an M form instruction. */
334#define MB LS + 1
335#define MB_MASK (0x1f << 6)
336 { 5, 6, NULL, NULL, 0 },
337 470
338 /* The ME field in an M form instruction. */ 471 /* The ME field in an M form instruction. */
339#define ME MB + 1 472#define ME LS + 1
340#define ME_MASK (0x1f << 1) 473#define ME_MASK (0x1f << 1)
341 { 5, 1, NULL, NULL, 0 }, 474 { 0x1f, 1, NULL, NULL, 0 },
342 475
343 /* The MB and ME fields in an M form instruction expressed a single 476 /* The MB and ME fields in an M form instruction expressed a single
344 operand which is a bitmask indicating which bits to select. This 477 operand which is a bitmask indicating which bits to select. This
345 is a two operand form using PPC_OPERAND_NEXT. See the 478 is a two operand form using PPC_OPERAND_NEXT. See the
346 description in opcode/ppc.h for what this means. */ 479 description in opcode/ppc.h for what this means. */
347#define MBE ME + 1 480#define MBE ME + 1
348 { 5, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT }, 481 { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
349 { 32, 0, insert_mbe, extract_mbe, 0 }, 482 { -1, 0, insert_mbe, extract_mbe, 0 },
350 483
351 /* The MB or ME field in an MD or MDS form instruction. The high 484 /* The MB or ME field in an MD or MDS form instruction. The high
352 bit is wrapped to the low end. */ 485 bit is wrapped to the low end. */
353#define MB6 MBE + 2 486#define MB6 MBE + 2
354#define ME6 MB6 487#define ME6 MB6
355#define MB6_MASK (0x3f << 5) 488#define MB6_MASK (0x3f << 5)
356 { 6, 5, insert_mb6, extract_mb6, 0 }, 489 { 0x3f, 5, insert_mb6, extract_mb6, 0 },
357
358 /* The MO field in an mbar instruction. */
359#define MO MB6 + 1
360 { 5, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
361 490
362 /* The NB field in an X form instruction. The value 32 is stored as 491 /* The NB field in an X form instruction. The value 32 is stored as
363 0. */ 492 0. */
364#define NB MO + 1 493#define NB MB6 + 1
365 { 6, 11, insert_nb, extract_nb, 0 }, 494 { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
495
496 /* The NBI field in an lswi instruction, which has special value
497 restrictions. The value 32 is stored as 0. */
498#define NBI NB + 1
499 { 0x1f, 11, insert_nbi, extract_nb, PPC_OPERAND_PLUS1 },
366 500
367 /* The NSI field in a D form instruction. This is the same as the 501 /* The NSI field in a D form instruction. This is the same as the
368 SI field, only negated. */ 502 SI field, only negated. */
369#define NSI NB + 1 503#define NSI NBI + 1
370 { 16, 0, insert_nsi, extract_nsi, 504 { 0xffff, 0, insert_nsi, extract_nsi,
371 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, 505 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
506
507 /* The NSI field in a D form instruction when we accept a wide range
508 of positive values. */
509#define NSISIGNOPT NSI + 1
510 { 0xffff, 0, insert_nsi, extract_nsi,
511 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
372 512
373 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */ 513 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
374#define RA NSI + 1 514#define RA NSISIGNOPT + 1
375#define RA_MASK (0x1f << 16) 515#define RA_MASK (0x1f << 16)
376 { 5, 16, NULL, NULL, PPC_OPERAND_GPR }, 516 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
377 517
378 /* As above, but 0 in the RA field means zero, not r0. */ 518 /* As above, but 0 in the RA field means zero, not r0. */
379#define RA0 RA + 1 519#define RA0 RA + 1
380 { 5, 16, NULL, NULL, PPC_OPERAND_GPR_0 }, 520 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
381 521
382 /* The RA field in the DQ form lq instruction, which has special 522 /* The RA field in the DQ form lq or an lswx instruction, which have special
383 value restrictions. */ 523 value restrictions. */
384#define RAQ RA0 + 1 524#define RAQ RA0 + 1
385 { 5, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 }, 525#define RAX RAQ
526 { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
386 527
387 /* The RA field in a D or X form instruction which is an updating 528 /* The RA field in a D or X form instruction which is an updating
388 load, which means that the RA field may not be zero and may not 529 load, which means that the RA field may not be zero and may not
389 equal the RT field. */ 530 equal the RT field. */
390#define RAL RAQ + 1 531#define RAL RAQ + 1
391 { 5, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 }, 532 { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
392 533
393 /* The RA field in an lmw instruction, which has special value 534 /* The RA field in an lmw instruction, which has special value
394 restrictions. */ 535 restrictions. */
395#define RAM RAL + 1 536#define RAM RAL + 1
396 { 5, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 }, 537 { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
397 538
398 /* The RA field in a D or X form instruction which is an updating 539 /* The RA field in a D or X form instruction which is an updating
399 store or an updating floating point load, which means that the RA 540 store or an updating floating point load, which means that the RA
400 field may not be zero. */ 541 field may not be zero. */
401#define RAS RAM + 1 542#define RAS RAM + 1
402 { 5, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 }, 543 { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
403 544
404 /* The RA field of the tlbwe instruction, which is optional. */ 545 /* The RA field of the tlbwe, dccci and iccci instructions,
546 which are optional. */
405#define RAOPT RAS + 1 547#define RAOPT RAS + 1
406 { 5, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, 548 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
407 549
408 /* The RB field in an X, XO, M, or MDS form instruction. */ 550 /* The RB field in an X, XO, M, or MDS form instruction. */
409#define RB RAOPT + 1 551#define RB RAOPT + 1
410#define RB_MASK (0x1f << 11) 552#define RB_MASK (0x1f << 11)
411 { 5, 11, NULL, NULL, PPC_OPERAND_GPR }, 553 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },
412 554
413 /* The RB field in an X form instruction when it must be the same as 555 /* The RB field in an X form instruction when it must be the same as
414 the RS field in the instruction. This is used for extended 556 the RS field in the instruction. This is used for extended
415 mnemonics like mr. */ 557 mnemonics like mr. */
416#define RBS RB + 1 558#define RBS RB + 1
417 { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE }, 559 { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
560
561 /* The RB field in an lswx instruction, which has special value
562 restrictions. */
563#define RBX RBS + 1
564 { 0x1f, 11, insert_rbx, NULL, PPC_OPERAND_GPR },
565
566 /* The RB field of the dccci and iccci instructions, which are optional. */
567#define RBOPT RBX + 1
568 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
569
570 /* The RC register field in an maddld, maddhd or maddhdu instruction. */
571#define RC RBOPT + 1
572 { 0x1f, 6, NULL, NULL, PPC_OPERAND_GPR },
418 573
419 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form 574 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
420 instruction or the RT field in a D, DS, X, XFX or XO form 575 instruction or the RT field in a D, DS, X, XFX or XO form
421 instruction. */ 576 instruction. */
422#define RS RBS + 1 577#define RS RC + 1
423#define RT RS 578#define RT RS
424#define RT_MASK (0x1f << 21) 579#define RT_MASK (0x1f << 21)
425 { 5, 21, NULL, NULL, PPC_OPERAND_GPR }, 580#define RD RS
581 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
426 582
427 /* The RS field of the DS form stq instruction, which has special 583 /* The RS and RT fields of the DS form stq and DQ form lq instructions,
428 value restrictions. */ 584 which have special value restrictions. */
429#define RSQ RS + 1 585#define RSQ RS + 1
430 { 5, 21, insert_rsq, NULL, PPC_OPERAND_GPR_0 }, 586#define RTQ RSQ
431 587 { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR },
432 /* The RT field of the DQ form lq instruction, which has special
433 value restrictions. */
434#define RTQ RSQ + 1
435 { 5, 21, insert_rtq, NULL, PPC_OPERAND_GPR_0 },
436 588
437 /* The RS field of the tlbwe instruction, which is optional. */ 589 /* The RS field of the tlbwe instruction, which is optional. */
438#define RSO RTQ + 1 590#define RSO RSQ + 1
439#define RTO RSO 591#define RTO RSO
440 { 5, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, 592 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
593
594 /* The RX field of the SE_RR form instruction. */
595#define RX RSO + 1
596 { 0x1f, PPC_OPSHIFT_INV, insert_rx, extract_rx, PPC_OPERAND_GPR },
597
598 /* The ARX field of the SE_RR form instruction. */
599#define ARX RX + 1
600 { 0x1f, PPC_OPSHIFT_INV, insert_arx, extract_arx, PPC_OPERAND_GPR },
601
602 /* The RY field of the SE_RR form instruction. */
603#define RY ARX + 1
604#define RZ RY
605 { 0x1f, PPC_OPSHIFT_INV, insert_ry, extract_ry, PPC_OPERAND_GPR },
606
607 /* The ARY field of the SE_RR form instruction. */
608#define ARY RY + 1
609 { 0x1f, PPC_OPSHIFT_INV, insert_ary, extract_ary, PPC_OPERAND_GPR },
610
611 /* The SCLSCI8 field in a D form instruction. */
612#define SCLSCI8 ARY + 1
613 { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8, extract_sci8, 0 },
614
615 /* The SCLSCI8N field in a D form instruction. This is the same as the
616 SCLSCI8 field, only negated. */
617#define SCLSCI8N SCLSCI8 + 1
618 { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8n, extract_sci8n,
619 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
620
621 /* The SD field of the SD4 form instruction. */
622#define SE_SD SCLSCI8N + 1
623 { 0xf, 8, NULL, NULL, PPC_OPERAND_PARENS },
624
625 /* The SD field of the SD4 form instruction, for halfword. */
626#define SE_SDH SE_SD + 1
627 { 0x1e, PPC_OPSHIFT_INV, insert_sd4h, extract_sd4h, PPC_OPERAND_PARENS },
628
629 /* The SD field of the SD4 form instruction, for word. */
630#define SE_SDW SE_SDH + 1
631 { 0x3c, PPC_OPSHIFT_INV, insert_sd4w, extract_sd4w, PPC_OPERAND_PARENS },
441 632
442 /* The SH field in an X or M form instruction. */ 633 /* The SH field in an X or M form instruction. */
443#define SH RSO + 1 634#define SH SE_SDW + 1
444#define SH_MASK (0x1f << 11) 635#define SH_MASK (0x1f << 11)
445 { 5, 11, NULL, NULL, 0 }, 636 /* The other UIMM field in a EVX form instruction. */
637#define EVUIMM SH
638 /* The FC field in an atomic X form instruction. */
639#define FC SH
640 { 0x1f, 11, NULL, NULL, 0 },
641
642 /* The SI field in a HTM X form instruction. */
643#define HTM_SI SH + 1
644 { 0x1f, 11, NULL, NULL, PPC_OPERAND_SIGNED },
446 645
447 /* The SH field in an MD form instruction. This is split. */ 646 /* The SH field in an MD form instruction. This is split. */
448#define SH6 SH + 1 647#define SH6 HTM_SI + 1
449#define SH6_MASK ((0x1f << 11) | (1 << 1)) 648#define SH6_MASK ((0x1f << 11) | (1 << 1))
450 { 6, 1, insert_sh6, extract_sh6, 0 }, 649 { 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_sh6, 0 },
451 650
452 /* The SH field of the tlbwe instruction, which is optional. */ 651 /* The SH field of the tlbwe instruction, which is optional. */
453#define SHO SH6 + 1 652#define SHO SH6 + 1
454 { 5, 11,NULL, NULL, PPC_OPERAND_OPTIONAL }, 653 { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
455 654
456 /* The SI field in a D form instruction. */ 655 /* The SI field in a D form instruction. */
457#define SI SHO + 1 656#define SI SHO + 1
458 { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED }, 657 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
459 658
460 /* The SI field in a D form instruction when we accept a wide range 659 /* The SI field in a D form instruction when we accept a wide range
461 of positive values. */ 660 of positive values. */
462#define SISIGNOPT SI + 1 661#define SISIGNOPT SI + 1
463 { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, 662 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
663
664 /* The SI8 field in a D form instruction. */
665#define SI8 SISIGNOPT + 1
666 { 0xff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
464 667
465 /* The SPR field in an XFX form instruction. This is flipped--the 668 /* The SPR field in an XFX form instruction. This is flipped--the
466 lower 5 bits are stored in the upper 5 and vice- versa. */ 669 lower 5 bits are stored in the upper 5 and vice- versa. */
467#define SPR SISIGNOPT + 1 670#define SPR SI8 + 1
468#define PMR SPR 671#define PMR SPR
672#define TMR SPR
469#define SPR_MASK (0x3ff << 11) 673#define SPR_MASK (0x3ff << 11)
470 { 10, 11, insert_spr, extract_spr, 0 }, 674 { 0x3ff, 11, insert_spr, extract_spr, 0 },
471 675
472 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */ 676 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
473#define SPRBAT SPR + 1 677#define SPRBAT SPR + 1
474#define SPRBAT_MASK (0x3 << 17) 678#define SPRBAT_MASK (0x3 << 17)
475 { 2, 17, NULL, NULL, 0 }, 679 { 0x3, 17, NULL, NULL, 0 },
476 680
477 /* The SPRG register number in an XFX form m[ft]sprg instruction. */ 681 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
478#define SPRG SPRBAT + 1 682#define SPRG SPRBAT + 1
479 { 5, 16, insert_sprg, extract_sprg, 0 }, 683 { 0x1f, 16, insert_sprg, extract_sprg, 0 },
480 684
481 /* The SR field in an X form instruction. */ 685 /* The SR field in an X form instruction. */
482#define SR SPRG + 1 686#define SR SPRG + 1
483 { 4, 16, NULL, NULL, 0 }, 687 /* The 4-bit UIMM field in a VX form instruction. */
688#define UIMM4 SR
689 { 0xf, 16, NULL, NULL, 0 },
484 690
485 /* The STRM field in an X AltiVec form instruction. */ 691 /* The STRM field in an X AltiVec form instruction. */
486#define STRM SR + 1 692#define STRM SR + 1
487#define STRM_MASK (0x3 << 21) 693 /* The T field in a tlbilx form instruction. */
488 { 2, 21, NULL, NULL, 0 }, 694#define T STRM
695 /* The L field in wclr instructions. */
696#define L2 STRM
697 { 0x3, 21, NULL, NULL, 0 },
698
699 /* The ESYNC field in an X (sync) form instruction. */
700#define ESYNC STRM + 1
701 { 0xf, 16, insert_esync, NULL, PPC_OPERAND_OPTIONAL },
489 702
490 /* The SV field in a POWER SC form instruction. */ 703 /* The SV field in a POWER SC form instruction. */
491#define SV STRM + 1 704#define SV ESYNC + 1
492 { 14, 2, NULL, NULL, 0 }, 705 { 0x3fff, 2, NULL, NULL, 0 },
493 706
494 /* The TBR field in an XFX form instruction. This is like the SPR 707 /* The TBR field in an XFX form instruction. This is like the SPR
495 field, but it is optional. */ 708 field, but it is optional. */
496#define TBR SV + 1 709#define TBR SV + 1
497 { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL }, 710 { 0x3ff, 11, insert_tbr, extract_tbr,
711 PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
712 /* If the TBR operand is ommitted, use the value 268. */
713 { -1, 268, NULL, NULL, 0},
498 714
499 /* The TO field in a D or X form instruction. */ 715 /* The TO field in a D or X form instruction. */
500#define TO TBR + 1 716#define TO TBR + 2
717#define DUI TO
501#define TO_MASK (0x1f << 21) 718#define TO_MASK (0x1f << 21)
502 { 5, 21, NULL, NULL, 0 }, 719 { 0x1f, 21, NULL, NULL, 0 },
503
504 /* The U field in an X form instruction. */
505#define U TO + 1
506 { 4, 12, NULL, NULL, 0 },
507 720
508 /* The UI field in a D form instruction. */ 721 /* The UI field in a D form instruction. */
509#define UI U + 1 722#define UI TO + 1
510 { 16, 0, NULL, NULL, 0 }, 723 { 0xffff, 0, NULL, NULL, 0 },
724
725#define UISIGNOPT UI + 1
726 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNOPT },
727
728 /* The IMM field in an SE_IM5 instruction. */
729#define UI5 UISIGNOPT + 1
730 { 0x1f, 4, NULL, NULL, 0 },
731
732 /* The OIMM field in an SE_OIM5 instruction. */
733#define OIMM5 UI5 + 1
734 { 0x1f, PPC_OPSHIFT_INV, insert_oimm, extract_oimm, PPC_OPERAND_PLUS1 },
735
736 /* The UI7 field in an SE_LI instruction. */
737#define UI7 OIMM5 + 1
738 { 0x7f, 4, NULL, NULL, 0 },
511 739
512 /* The VA field in a VA, VX or VXR form instruction. */ 740 /* The VA field in a VA, VX or VXR form instruction. */
513#define VA UI + 1 741#define VA UI7 + 1
514#define VA_MASK (0x1f << 16) 742 { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
515 { 5, 16, NULL, NULL, PPC_OPERAND_VR },
516 743
517 /* The VB field in a VA, VX or VXR form instruction. */ 744 /* The VB field in a VA, VX or VXR form instruction. */
518#define VB VA + 1 745#define VB VA + 1
519#define VB_MASK (0x1f << 11) 746 { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
520 { 5, 11, NULL, NULL, PPC_OPERAND_VR },
521 747
522 /* The VC field in a VA form instruction. */ 748 /* The VC field in a VA form instruction. */
523#define VC VB + 1 749#define VC VB + 1
524#define VC_MASK (0x1f << 6) 750 { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
525 { 5, 6, NULL, NULL, PPC_OPERAND_VR },
526 751
527 /* The VD or VS field in a VA, VX, VXR or X form instruction. */ 752 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
528#define VD VC + 1 753#define VD VC + 1
529#define VS VD 754#define VS VD
530#define VD_MASK (0x1f << 21) 755 { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
531 { 5, 21, NULL, NULL, PPC_OPERAND_VR },
532 756
533 /* The SIMM field in a VX form instruction. */ 757 /* The SIMM field in a VX form instruction, and TE in Z form. */
534#define SIMM VD + 1 758#define SIMM VD + 1
535 { 5, 16, NULL, NULL, PPC_OPERAND_SIGNED}, 759#define TE SIMM
760 { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
536 761
537 /* The UIMM field in a VX form instruction. */ 762 /* The UIMM field in a VX form instruction. */
538#define UIMM SIMM + 1 763#define UIMM SIMM + 1
539 { 5, 16, NULL, NULL, 0 }, 764#define DCTL UIMM
765 { 0x1f, 16, NULL, NULL, 0 },
540 766
541 /* The SHB field in a VA form instruction. */ 767 /* The 3-bit UIMM field in a VX form instruction. */
542#define SHB UIMM + 1 768#define UIMM3 UIMM + 1
543 { 4, 6, NULL, NULL, 0 }, 769 { 0x7, 16, NULL, NULL, 0 },
544 770
545 /* The other UIMM field in a EVX form instruction. */ 771 /* The 6-bit UIM field in a X form instruction. */
546#define EVUIMM SHB + 1 772#define UIM6 UIMM3 + 1
547 { 5, 11, NULL, NULL, 0 }, 773 { 0x3f, 16, NULL, NULL, 0 },
774
775 /* The SIX field in a VX form instruction. */
776#define SIX UIM6 + 1
777 { 0xf, 11, NULL, NULL, 0 },
778
779 /* The PS field in a VX form instruction. */
780#define PS SIX + 1
781 { 0x1, 9, NULL, NULL, 0 },
782
783 /* The SHB field in a VA form instruction. */
784#define SHB PS + 1
785 { 0xf, 6, NULL, NULL, 0 },
548 786
549 /* The other UIMM field in a half word EVX form instruction. */ 787 /* The other UIMM field in a half word EVX form instruction. */
550#define EVUIMM_2 EVUIMM + 1 788#define EVUIMM_2 SHB + 1
551 { 32, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS }, 789 { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
552 790
553 /* The other UIMM field in a word EVX form instruction. */ 791 /* The other UIMM field in a word EVX form instruction. */
554#define EVUIMM_4 EVUIMM_2 + 1 792#define EVUIMM_4 EVUIMM_2 + 1
555 { 32, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS }, 793 { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
556 794
557 /* The other UIMM field in a double EVX form instruction. */ 795 /* The other UIMM field in a double EVX form instruction. */
558#define EVUIMM_8 EVUIMM_4 + 1 796#define EVUIMM_8 EVUIMM_4 + 1
559 { 32, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS }, 797 { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
560 798
561 /* The WS field. */ 799 /* The WS or DRM field in an X form instruction. */
562#define WS EVUIMM_8 + 1 800#define WS EVUIMM_8 + 1
563#define WS_MASK (0x7 << 11) 801#define DRM WS
564 { 3, 11, NULL, NULL, 0 }, 802 { 0x7, 11, NULL, NULL, 0 },
565 803
566 /* The L field in an mtmsrd or A form instruction. */ 804 /* PowerPC paired singles extensions. */
567#define MTMSRD_L WS + 1 805 /* W bit in the pair singles instructions for x type instructions. */
568#define A_L MTMSRD_L 806#define PSWM WS + 1
569 { 1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL }, 807 /* The BO16 field in a BD8 form instruction. */
808#define BO16 PSWM
809 { 0x1, 10, 0, 0, 0 },
810
811 /* IDX bits for quantization in the pair singles instructions. */
812#define PSQ PSWM + 1
813 { 0x7, 12, 0, 0, 0 },
814
815 /* IDX bits for quantization in the pair singles x-type instructions. */
816#define PSQM PSQ + 1
817 { 0x7, 7, 0, 0, 0 },
818
819 /* Smaller D field for quantization in the pair singles instructions. */
820#define PSD PSQM + 1
821 { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
822
823 /* The L field in an mtmsrd or A form instruction or R or W in an X form. */
824#define A_L PSD + 1
825#define W A_L
826#define X_R A_L
827 { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
828
829 /* The RMC or CY field in a Z23 form instruction. */
830#define RMC A_L + 1
831#define CY RMC
832 { 0x3, 9, NULL, NULL, 0 },
570 833
571 /* The DCM field in a Z form instruction. */ 834#define R RMC + 1
572#define DCM MTMSRD_L + 1 835 { 0x1, 16, NULL, NULL, 0 },
573 { 6, 16, NULL, NULL, 0 },
574
575 /* Likewise, the DGM field in a Z form instruction. */
576#define DGM DCM + 1
577 { 6, 16, NULL, NULL, 0 },
578 836
579#define TE DGM + 1 837#define RIC R + 1
580 { 5, 11, NULL, NULL, 0 }, 838 { 0x3, 18, NULL, NULL, PPC_OPERAND_OPTIONAL },
581 839
582#define RMC TE + 1 840#define PRS RIC + 1
583 { 2, 21, NULL, NULL, 0 }, 841 { 0x1, 17, NULL, NULL, PPC_OPERAND_OPTIONAL },
584 842
585#define R RMC + 1 843#define SP PRS + 1
586 { 1, 15, NULL, NULL, 0 }, 844 { 0x3, 19, NULL, NULL, 0 },
587
588#define SP R + 1
589 { 2, 11, NULL, NULL, 0 },
590 845
591#define S SP + 1 846#define S SP + 1
592 { 1, 11, NULL, NULL, 0 }, 847 { 0x1, 20, NULL, NULL, 0 },
593 848
594 /* SH field starting at bit position 16. */ 849 /* The S field in a XL form instruction. */
595#define SH16 S + 1 850#define SXL S + 1
596 { 6, 10, NULL, NULL, 0 }, 851 { 0x1, 11, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
852 /* If the SXL operand is ommitted, use the value 1. */
853 { -1, 1, NULL, NULL, 0},
597 854
598 /* The L field in an X form with the RT field fixed instruction. */ 855 /* SH field starting at bit position 16. */
599#define XRT_L SH16 + 1 856#define SH16 SXL + 2
600 { 2, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, 857 /* The DCM and DGM fields in a Z form instruction. */
858#define DCM SH16
859#define DGM DCM
860 { 0x3f, 10, NULL, NULL, 0 },
601 861
602 /* The EH field in larx instruction. */ 862 /* The EH field in larx instruction. */
603#define EH XRT_L + 1 863#define EH SH16 + 1
604 { 1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL }, 864 { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
865
866 /* The L field in an mtfsf or XFL form instruction. */
867 /* The A field in a HTM X form instruction. */
868#define XFL_L EH + 1
869#define HTM_A XFL_L
870 { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
871
872 /* Xilinx APU related masks and macros */
873#define FCRT XFL_L + 1
874#define FCRT_MASK (0x1f << 21)
875 { 0x1f, 21, 0, 0, PPC_OPERAND_FCR },
876
877 /* Xilinx FSL related masks and macros */
878#define FSL FCRT + 1
879#define FSL_MASK (0x1f << 11)
880 { 0x1f, 11, 0, 0, PPC_OPERAND_FSL },
881
882 /* Xilinx UDI related masks and macros */
883#define URT FSL + 1
884 { 0x1f, 21, 0, 0, PPC_OPERAND_UDI },
885
886#define URA URT + 1
887 { 0x1f, 16, 0, 0, PPC_OPERAND_UDI },
888
889#define URB URA + 1
890 { 0x1f, 11, 0, 0, PPC_OPERAND_UDI },
891
892#define URC URB + 1
893 { 0x1f, 6, 0, 0, PPC_OPERAND_UDI },
894
895 /* The VLESIMM field in a D form instruction. */
896#define VLESIMM URC + 1
897 { 0xffff, PPC_OPSHIFT_INV, insert_vlesi, extract_vlesi,
898 PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
899
900 /* The VLENSIMM field in a D form instruction. */
901#define VLENSIMM VLESIMM + 1
902 { 0xffff, PPC_OPSHIFT_INV, insert_vlensi, extract_vlensi,
903 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
904
905 /* The VLEUIMM field in a D form instruction. */
906#define VLEUIMM VLENSIMM + 1
907 { 0xffff, PPC_OPSHIFT_INV, insert_vleui, extract_vleui, 0 },
908
909 /* The VLEUIMML field in a D form instruction. */
910#define VLEUIMML VLEUIMM + 1
911 { 0xffff, PPC_OPSHIFT_INV, insert_vleil, extract_vleil, 0 },
912
913 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
914#define XS6 VLEUIMML + 1
915#define XT6 XS6
916 { 0x3f, PPC_OPSHIFT_INV, insert_xt6, extract_xt6, PPC_OPERAND_VSR },
917
918 /* The XT and XS fields in an DQ form VSX instruction. This is split. */
919#define XSQ6 XT6 + 1
920#define XTQ6 XSQ6
921 { 0x3f, PPC_OPSHIFT_INV, insert_xtq6, extract_xtq6, PPC_OPERAND_VSR },
922
923 /* The XA field in an XX3 form instruction. This is split. */
924#define XA6 XTQ6 + 1
925 { 0x3f, PPC_OPSHIFT_INV, insert_xa6, extract_xa6, PPC_OPERAND_VSR },
926
927 /* The XB field in an XX2 or XX3 form instruction. This is split. */
928#define XB6 XA6 + 1
929 { 0x3f, PPC_OPSHIFT_INV, insert_xb6, extract_xb6, PPC_OPERAND_VSR },
930
931 /* The XB field in an XX3 form instruction when it must be the same as
932 the XA field in the instruction. This is used in extended mnemonics
933 like xvmovdp. This is split. */
934#define XB6S XB6 + 1
935 { 0x3f, PPC_OPSHIFT_INV, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE },
936
937 /* The XC field in an XX4 form instruction. This is split. */
938#define XC6 XB6S + 1
939 { 0x3f, PPC_OPSHIFT_INV, insert_xc6, extract_xc6, PPC_OPERAND_VSR },
940
941 /* The DM or SHW field in an XX3 form instruction. */
942#define DM XC6 + 1
943#define SHW DM
944 { 0x3, 8, NULL, NULL, 0 },
945
946 /* The DM field in an extended mnemonic XX3 form instruction. */
947#define DMEX DM + 1
948 { 0x3, 8, insert_dm, extract_dm, 0 },
949
950 /* The UIM field in an XX2 form instruction. */
951#define UIM DMEX + 1
952 /* The 2-bit UIMM field in a VX form instruction. */
953#define UIMM2 UIM
954 /* The 2-bit L field in a darn instruction. */
955#define LRAND UIM
956 { 0x3, 16, NULL, NULL, 0 },
957
958#define ERAT_T UIM + 1
959 { 0x7, 21, NULL, NULL, 0 },
960
961#define IH ERAT_T + 1
962 { 0x7, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
963
964 /* The 8-bit IMM8 field in a XX1 form instruction. */
965#define IMM8 IH + 1
966 { 0xff, 11, NULL, NULL, PPC_OPERAND_SIGNOPT },
605}; 967};
606 968
969const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
970 / sizeof (powerpc_operands[0]));
971
607/* The functions used to insert and extract complicated operands. */ 972/* The functions used to insert and extract complicated operands. */
608 973
974/* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */
975
976static unsigned long
977insert_arx (unsigned long insn,
978 long value,
979 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
980 const char **errmsg ATTRIBUTE_UNUSED)
981{
982 if (value >= 8 && value < 24)
983 return insn | ((value - 8) & 0xf);
984 else
985 {
986 *errmsg = _("invalid register");
987 return 0;
988 }
989}
990
991static long
992extract_arx (unsigned long insn,
993 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
994 int *invalid ATTRIBUTE_UNUSED)
995{
996 return (insn & 0xf) + 8;
997}
998
999static unsigned long
1000insert_ary (unsigned long insn,
1001 long value,
1002 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1003 const char **errmsg ATTRIBUTE_UNUSED)
1004{
1005 if (value >= 8 && value < 24)
1006 return insn | (((value - 8) & 0xf) << 4);
1007 else
1008 {
1009 *errmsg = _("invalid register");
1010 return 0;
1011 }
1012}
1013
1014static long
1015extract_ary (unsigned long insn,
1016 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1017 int *invalid ATTRIBUTE_UNUSED)
1018{
1019 return ((insn >> 4) & 0xf) + 8;
1020}
1021
1022static unsigned long
1023insert_rx (unsigned long insn,
1024 long value,
1025 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1026 const char **errmsg)
1027{
1028 if (value >= 0 && value < 8)
1029 return insn | value;
1030 else if (value >= 24 && value <= 31)
1031 return insn | (value - 16);
1032 else
1033 {
1034 *errmsg = _("invalid register");
1035 return 0;
1036 }
1037}
1038
1039static long
1040extract_rx (unsigned long insn,
1041 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1042 int *invalid ATTRIBUTE_UNUSED)
1043{
1044 int value = insn & 0xf;
1045 if (value >= 0 && value < 8)
1046 return value;
1047 else
1048 return value + 16;
1049}
1050
1051static unsigned long
1052insert_ry (unsigned long insn,
1053 long value,
1054 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1055 const char **errmsg)
1056{
1057 if (value >= 0 && value < 8)
1058 return insn | (value << 4);
1059 else if (value >= 24 && value <= 31)
1060 return insn | ((value - 16) << 4);
1061 else
1062 {
1063 *errmsg = _("invalid register");
1064 return 0;
1065 }
1066}
1067
1068static long
1069extract_ry (unsigned long insn,
1070 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1071 int *invalid ATTRIBUTE_UNUSED)
1072{
1073 int value = (insn >> 4) & 0xf;
1074 if (value >= 0 && value < 8)
1075 return value;
1076 else
1077 return value + 16;
1078}
1079
609/* The BA field in an XL form instruction when it must be the same as 1080/* The BA field in an XL form instruction when it must be the same as
610 the BT field in the same instruction. This operand is marked FAKE. 1081 the BT field in the same instruction. This operand is marked FAKE.
611 The insertion function just copies the BT field into the BA field, 1082 The insertion function just copies the BT field into the BA field,
@@ -615,7 +1086,7 @@ const struct powerpc_operand powerpc_operands[] =
615static unsigned long 1086static unsigned long
616insert_bat (unsigned long insn, 1087insert_bat (unsigned long insn,
617 long value ATTRIBUTE_UNUSED, 1088 long value ATTRIBUTE_UNUSED,
618 int dialect ATTRIBUTE_UNUSED, 1089 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
619 const char **errmsg ATTRIBUTE_UNUSED) 1090 const char **errmsg ATTRIBUTE_UNUSED)
620{ 1091{
621 return insn | (((insn >> 21) & 0x1f) << 16); 1092 return insn | (((insn >> 21) & 0x1f) << 16);
@@ -623,7 +1094,7 @@ insert_bat (unsigned long insn,
623 1094
624static long 1095static long
625extract_bat (unsigned long insn, 1096extract_bat (unsigned long insn,
626 int dialect ATTRIBUTE_UNUSED, 1097 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
627 int *invalid) 1098 int *invalid)
628{ 1099{
629 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) 1100 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
@@ -640,7 +1111,7 @@ extract_bat (unsigned long insn,
640static unsigned long 1111static unsigned long
641insert_bba (unsigned long insn, 1112insert_bba (unsigned long insn,
642 long value ATTRIBUTE_UNUSED, 1113 long value ATTRIBUTE_UNUSED,
643 int dialect ATTRIBUTE_UNUSED, 1114 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
644 const char **errmsg ATTRIBUTE_UNUSED) 1115 const char **errmsg ATTRIBUTE_UNUSED)
645{ 1116{
646 return insn | (((insn >> 16) & 0x1f) << 11); 1117 return insn | (((insn >> 16) & 0x1f) << 11);
@@ -648,7 +1119,7 @@ insert_bba (unsigned long insn,
648 1119
649static long 1120static long
650extract_bba (unsigned long insn, 1121extract_bba (unsigned long insn,
651 int dialect ATTRIBUTE_UNUSED, 1122 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
652 int *invalid) 1123 int *invalid)
653{ 1124{
654 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) 1125 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
@@ -656,26 +1127,6 @@ extract_bba (unsigned long insn,
656 return 0; 1127 return 0;
657} 1128}
658 1129
659/* The BD field in a B form instruction. The lower two bits are
660 forced to zero. */
661
662static unsigned long
663insert_bd (unsigned long insn,
664 long value,
665 int dialect ATTRIBUTE_UNUSED,
666 const char **errmsg ATTRIBUTE_UNUSED)
667{
668 return insn | (value & 0xfffc);
669}
670
671static long
672extract_bd (unsigned long insn,
673 int dialect ATTRIBUTE_UNUSED,
674 int *invalid ATTRIBUTE_UNUSED)
675{
676 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
677}
678
679/* The BD field in a B form instruction when the - modifier is used. 1130/* The BD field in a B form instruction when the - modifier is used.
680 This modifier means that the branch is not expected to be taken. 1131 This modifier means that the branch is not expected to be taken.
681 For chips built to versions of the architecture prior to version 2 1132 For chips built to versions of the architecture prior to version 2
@@ -687,15 +1138,21 @@ extract_bd (unsigned long insn,
687 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable, 1138 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
688 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001 1139 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
689 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000 1140 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
690 for branch on CTR. We only handle the taken/not-taken hint here. */ 1141 for branch on CTR. We only handle the taken/not-taken hint here.
1142 Note that we don't relax the conditions tested here when
1143 disassembling with -Many because insns using extract_bdm and
1144 extract_bdp always occur in pairs. One or the other will always
1145 be valid. */
1146
1147#define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
691 1148
692static unsigned long 1149static unsigned long
693insert_bdm (unsigned long insn, 1150insert_bdm (unsigned long insn,
694 long value, 1151 long value,
695 int dialect, 1152 ppc_cpu_t dialect,
696 const char **errmsg ATTRIBUTE_UNUSED) 1153 const char **errmsg ATTRIBUTE_UNUSED)
697{ 1154{
698 if ((dialect & PPC_OPCODE_POWER4) == 0) 1155 if ((dialect & ISA_V2) == 0)
699 { 1156 {
700 if ((value & 0x8000) != 0) 1157 if ((value & 0x8000) != 0)
701 insn |= 1 << 21; 1158 insn |= 1 << 21;
@@ -712,10 +1169,10 @@ insert_bdm (unsigned long insn,
712 1169
713static long 1170static long
714extract_bdm (unsigned long insn, 1171extract_bdm (unsigned long insn,
715 int dialect, 1172 ppc_cpu_t dialect,
716 int *invalid) 1173 int *invalid)
717{ 1174{
718 if ((dialect & PPC_OPCODE_POWER4) == 0) 1175 if ((dialect & ISA_V2) == 0)
719 { 1176 {
720 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0)) 1177 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
721 *invalid = 1; 1178 *invalid = 1;
@@ -737,10 +1194,10 @@ extract_bdm (unsigned long insn,
737static unsigned long 1194static unsigned long
738insert_bdp (unsigned long insn, 1195insert_bdp (unsigned long insn,
739 long value, 1196 long value,
740 int dialect, 1197 ppc_cpu_t dialect,
741 const char **errmsg ATTRIBUTE_UNUSED) 1198 const char **errmsg ATTRIBUTE_UNUSED)
742{ 1199{
743 if ((dialect & PPC_OPCODE_POWER4) == 0) 1200 if ((dialect & ISA_V2) == 0)
744 { 1201 {
745 if ((value & 0x8000) == 0) 1202 if ((value & 0x8000) == 0)
746 insn |= 1 << 21; 1203 insn |= 1 << 21;
@@ -757,10 +1214,10 @@ insert_bdp (unsigned long insn,
757 1214
758static long 1215static long
759extract_bdp (unsigned long insn, 1216extract_bdp (unsigned long insn,
760 int dialect, 1217 ppc_cpu_t dialect,
761 int *invalid) 1218 int *invalid)
762{ 1219{
763 if ((dialect & PPC_OPCODE_POWER4) == 0) 1220 if ((dialect & ISA_V2) == 0)
764 { 1221 {
765 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0)) 1222 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
766 *invalid = 1; 1223 *invalid = 1;
@@ -775,55 +1232,70 @@ extract_bdp (unsigned long insn,
775 return ((insn & 0xfffc) ^ 0x8000) - 0x8000; 1232 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
776} 1233}
777 1234
1235static inline int
1236valid_bo_pre_v2 (long value)
1237{
1238 /* Certain encodings have bits that are required to be zero.
1239 These are (z must be zero, y may be anything):
1240 0000y
1241 0001y
1242 001zy
1243 0100y
1244 0101y
1245 011zy
1246 1z00y
1247 1z01y
1248 1z1zz
1249 */
1250 if ((value & 0x14) == 0)
1251 return 1;
1252 else if ((value & 0x14) == 0x4)
1253 return (value & 0x2) == 0;
1254 else if ((value & 0x14) == 0x10)
1255 return (value & 0x8) == 0;
1256 else
1257 return value == 0x14;
1258}
1259
1260static inline int
1261valid_bo_post_v2 (long value)
1262{
1263 /* Certain encodings have bits that are required to be zero.
1264 These are (z must be zero, a & t may be anything):
1265 0000z
1266 0001z
1267 001at
1268 0100z
1269 0101z
1270 011at
1271 1a00t
1272 1a01t
1273 1z1zz
1274 */
1275 if ((value & 0x14) == 0)
1276 return (value & 0x1) == 0;
1277 else if ((value & 0x14) == 0x14)
1278 return value == 0x14;
1279 else
1280 return 1;
1281}
1282
778/* Check for legal values of a BO field. */ 1283/* Check for legal values of a BO field. */
779 1284
780static int 1285static int
781valid_bo (long value, int dialect) 1286valid_bo (long value, ppc_cpu_t dialect, int extract)
782{ 1287{
783 if ((dialect & PPC_OPCODE_POWER4) == 0) 1288 int valid_y = valid_bo_pre_v2 (value);
784 { 1289 int valid_at = valid_bo_post_v2 (value);
785 /* Certain encodings have bits that are required to be zero. 1290
786 These are (z must be zero, y may be anything): 1291 /* When disassembling with -Many, accept either encoding on the
787 001zy 1292 second pass through opcodes. */
788 011zy 1293 if (extract && dialect == ~(ppc_cpu_t) PPC_OPCODE_ANY)
789 1z00y 1294 return valid_y || valid_at;
790 1z01y 1295 if ((dialect & ISA_V2) == 0)
791 1z1zz 1296 return valid_y;
792 */
793 switch (value & 0x14)
794 {
795 default:
796 case 0:
797 return 1;
798 case 0x4:
799 return (value & 0x2) == 0;
800 case 0x10:
801 return (value & 0x8) == 0;
802 case 0x14:
803 return value == 0x14;
804 }
805 }
806 else 1297 else
807 { 1298 return valid_at;
808 /* Certain encodings have bits that are required to be zero.
809 These are (z must be zero, a & t may be anything):
810 0000z
811 0001z
812 0100z
813 0101z
814 001at
815 011at
816 1a00t
817 1a01t
818 1z1zz
819 */
820 if ((value & 0x14) == 0)
821 return (value & 0x1) == 0;
822 else if ((value & 0x14) == 0x14)
823 return value == 0x14;
824 else
825 return 1;
826 }
827} 1299}
828 1300
829/* The BO field in a B form instruction. Warn about attempts to set 1301/* The BO field in a B form instruction. Warn about attempts to set
@@ -832,23 +1304,25 @@ valid_bo (long value, int dialect)
832static unsigned long 1304static unsigned long
833insert_bo (unsigned long insn, 1305insert_bo (unsigned long insn,
834 long value, 1306 long value,
835 int dialect, 1307 ppc_cpu_t dialect,
836 const char **errmsg) 1308 const char **errmsg)
837{ 1309{
838 if (!valid_bo (value, dialect)) 1310 if (!valid_bo (value, dialect, 0))
839 *errmsg = _("invalid conditional option"); 1311 *errmsg = _("invalid conditional option");
1312 else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
1313 *errmsg = _("invalid counter access");
840 return insn | ((value & 0x1f) << 21); 1314 return insn | ((value & 0x1f) << 21);
841} 1315}
842 1316
843static long 1317static long
844extract_bo (unsigned long insn, 1318extract_bo (unsigned long insn,
845 int dialect, 1319 ppc_cpu_t dialect,
846 int *invalid) 1320 int *invalid)
847{ 1321{
848 long value; 1322 long value;
849 1323
850 value = (insn >> 21) & 0x1f; 1324 value = (insn >> 21) & 0x1f;
851 if (!valid_bo (value, dialect)) 1325 if (!valid_bo (value, dialect, 1))
852 *invalid = 1; 1326 *invalid = 1;
853 return value; 1327 return value;
854} 1328}
@@ -860,11 +1334,13 @@ extract_bo (unsigned long insn,
860static unsigned long 1334static unsigned long
861insert_boe (unsigned long insn, 1335insert_boe (unsigned long insn,
862 long value, 1336 long value,
863 int dialect, 1337 ppc_cpu_t dialect,
864 const char **errmsg) 1338 const char **errmsg)
865{ 1339{
866 if (!valid_bo (value, dialect)) 1340 if (!valid_bo (value, dialect, 0))
867 *errmsg = _("invalid conditional option"); 1341 *errmsg = _("invalid conditional option");
1342 else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
1343 *errmsg = _("invalid counter access");
868 else if ((value & 1) != 0) 1344 else if ((value & 1) != 0)
869 *errmsg = _("attempt to set y bit when using + or - modifier"); 1345 *errmsg = _("attempt to set y bit when using + or - modifier");
870 1346
@@ -873,166 +1349,73 @@ insert_boe (unsigned long insn,
873 1349
874static long 1350static long
875extract_boe (unsigned long insn, 1351extract_boe (unsigned long insn,
876 int dialect, 1352 ppc_cpu_t dialect,
877 int *invalid) 1353 int *invalid)
878{ 1354{
879 long value; 1355 long value;
880 1356
881 value = (insn >> 21) & 0x1f; 1357 value = (insn >> 21) & 0x1f;
882 if (!valid_bo (value, dialect)) 1358 if (!valid_bo (value, dialect, 1))
883 *invalid = 1; 1359 *invalid = 1;
884 return value & 0x1e; 1360 return value & 0x1e;
885} 1361}
886 1362
887/* The DQ field in a DQ form instruction. This is like D, but the 1363/* The DCMX field in a X form instruction when the field is split
888 lower four bits are forced to zero. */ 1364 into separate DC, DM and DX fields. */
889
890static unsigned long
891insert_dq (unsigned long insn,
892 long value,
893 int dialect ATTRIBUTE_UNUSED,
894 const char **errmsg)
895{
896 if ((value & 0xf) != 0)
897 *errmsg = _("offset not a multiple of 16");
898 return insn | (value & 0xfff0);
899}
900
901static long
902extract_dq (unsigned long insn,
903 int dialect ATTRIBUTE_UNUSED,
904 int *invalid ATTRIBUTE_UNUSED)
905{
906 return ((insn & 0xfff0) ^ 0x8000) - 0x8000;
907}
908 1365
909static unsigned long 1366static unsigned long
910insert_ev2 (unsigned long insn, 1367insert_dcmxs (unsigned long insn,
911 long value, 1368 long value,
912 int dialect ATTRIBUTE_UNUSED, 1369 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
913 const char **errmsg) 1370 const char **errmsg ATTRIBUTE_UNUSED)
914{ 1371{
915 if ((value & 1) != 0) 1372 return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3) | (value & 0x40);
916 *errmsg = _("offset not a multiple of 2");
917 if ((value > 62) != 0)
918 *errmsg = _("offset greater than 62");
919 return insn | ((value & 0x3e) << 10);
920} 1373}
921 1374
922static long 1375static long
923extract_ev2 (unsigned long insn, 1376extract_dcmxs (unsigned long insn,
924 int dialect ATTRIBUTE_UNUSED, 1377 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
925 int *invalid ATTRIBUTE_UNUSED) 1378 int *invalid ATTRIBUTE_UNUSED)
926{ 1379{
927 return (insn >> 10) & 0x3e; 1380 return (insn & 0x40) | ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
928} 1381}
929 1382
930static unsigned long 1383/* The D field in a DX form instruction when the field is split
931insert_ev4 (unsigned long insn, 1384 into separate D0, D1 and D2 fields. */
932 long value,
933 int dialect ATTRIBUTE_UNUSED,
934 const char **errmsg)
935{
936 if ((value & 3) != 0)
937 *errmsg = _("offset not a multiple of 4");
938 if ((value > 124) != 0)
939 *errmsg = _("offset greater than 124");
940 return insn | ((value & 0x7c) << 9);
941}
942
943static long
944extract_ev4 (unsigned long insn,
945 int dialect ATTRIBUTE_UNUSED,
946 int *invalid ATTRIBUTE_UNUSED)
947{
948 return (insn >> 9) & 0x7c;
949}
950 1385
951static unsigned long 1386static unsigned long
952insert_ev8 (unsigned long insn, 1387insert_dxd (unsigned long insn,
953 long value, 1388 long value,
954 int dialect ATTRIBUTE_UNUSED, 1389 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
955 const char **errmsg) 1390 const char **errmsg ATTRIBUTE_UNUSED)
956{ 1391{
957 if ((value & 7) != 0) 1392 return insn | (value & 0xffc1) | ((value & 0x3e) << 15);
958 *errmsg = _("offset not a multiple of 8");
959 if ((value > 248) != 0)
960 *errmsg = _("offset greater than 248");
961 return insn | ((value & 0xf8) << 8);
962} 1393}
963 1394
964static long 1395static long
965extract_ev8 (unsigned long insn, 1396extract_dxd (unsigned long insn,
966 int dialect ATTRIBUTE_UNUSED, 1397 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
967 int *invalid ATTRIBUTE_UNUSED) 1398 int *invalid ATTRIBUTE_UNUSED)
968{ 1399{
969 return (insn >> 8) & 0xf8; 1400 unsigned long dxd = (insn & 0xffc1) | ((insn >> 15) & 0x3e);
1401 return (dxd ^ 0x8000) - 0x8000;
970} 1402}
971 1403
972/* The DS field in a DS form instruction. This is like D, but the
973 lower two bits are forced to zero. */
974
975static unsigned long 1404static unsigned long
976insert_ds (unsigned long insn, 1405insert_dxdn (unsigned long insn,
977 long value,
978 int dialect ATTRIBUTE_UNUSED,
979 const char **errmsg)
980{
981 if ((value & 3) != 0)
982 *errmsg = _("offset not a multiple of 4");
983 return insn | (value & 0xfffc);
984}
985
986static long
987extract_ds (unsigned long insn,
988 int dialect ATTRIBUTE_UNUSED,
989 int *invalid ATTRIBUTE_UNUSED)
990{
991 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
992}
993
994/* The DE field in a DE form instruction. */
995
996static unsigned long
997insert_de (unsigned long insn,
998 long value,
999 int dialect ATTRIBUTE_UNUSED,
1000 const char **errmsg)
1001{
1002 if (value > 2047 || value < -2048)
1003 *errmsg = _("offset not between -2048 and 2047");
1004 return insn | ((value << 4) & 0xfff0);
1005}
1006
1007static long
1008extract_de (unsigned long insn,
1009 int dialect ATTRIBUTE_UNUSED,
1010 int *invalid ATTRIBUTE_UNUSED)
1011{
1012 return (insn & 0xfff0) >> 4;
1013}
1014
1015/* The DES field in a DES form instruction. */
1016
1017static unsigned long
1018insert_des (unsigned long insn,
1019 long value, 1406 long value,
1020 int dialect ATTRIBUTE_UNUSED, 1407 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1021 const char **errmsg) 1408 const char **errmsg ATTRIBUTE_UNUSED)
1022{ 1409{
1023 if (value > 8191 || value < -8192) 1410 return insert_dxd (insn, -value, dialect, errmsg);
1024 *errmsg = _("offset not between -8192 and 8191");
1025 else if ((value & 3) != 0)
1026 *errmsg = _("offset not a multiple of 4");
1027 return insn | ((value << 2) & 0xfff0);
1028} 1411}
1029 1412
1030static long 1413static long
1031extract_des (unsigned long insn, 1414extract_dxdn (unsigned long insn,
1032 int dialect ATTRIBUTE_UNUSED, 1415 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1033 int *invalid ATTRIBUTE_UNUSED) 1416 int *invalid ATTRIBUTE_UNUSED)
1034{ 1417{
1035 return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000; 1418 return -extract_dxd (insn, dialect, invalid);
1036} 1419}
1037 1420
1038/* FXM mask in mfcr and mtcrf instructions. */ 1421/* FXM mask in mfcr and mtcrf instructions. */
@@ -1040,7 +1423,7 @@ extract_des (unsigned long insn,
1040static unsigned long 1423static unsigned long
1041insert_fxm (unsigned long insn, 1424insert_fxm (unsigned long insn,
1042 long value, 1425 long value,
1043 int dialect, 1426 ppc_cpu_t dialect,
1044 const char **errmsg) 1427 const char **errmsg)
1045{ 1428{
1046 /* If we're handling the mfocrf and mtocrf insns ensure that exactly 1429 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
@@ -1054,19 +1437,13 @@ insert_fxm (unsigned long insn,
1054 } 1437 }
1055 } 1438 }
1056 1439
1057 /* If the optional field on mfcr is missing that means we want to use
1058 the old form of the instruction that moves the whole cr. In that
1059 case we'll have VALUE zero. There doesn't seem to be a way to
1060 distinguish this from the case where someone writes mfcr %r3,0. */
1061 else if (value == 0)
1062 ;
1063
1064 /* If only one bit of the FXM field is set, we can use the new form 1440 /* If only one bit of the FXM field is set, we can use the new form
1065 of the instruction, which is faster. Unlike the Power4 branch hint 1441 of the instruction, which is faster. Unlike the Power4 branch hint
1066 encoding, this is not backward compatible. Do not generate the 1442 encoding, this is not backward compatible. Do not generate the
1067 new form unless -mpower4 has been given, or -many and the two 1443 new form unless -mpower4 has been given, or -many and the two
1068 operand form of mfcr was used. */ 1444 operand form of mfcr was used. */
1069 else if ((value & -value) == value 1445 else if (value > 0
1446 && (value & -value) == value
1070 && ((dialect & PPC_OPCODE_POWER4) != 0 1447 && ((dialect & PPC_OPCODE_POWER4) != 0
1071 || ((dialect & PPC_OPCODE_ANY) != 0 1448 || ((dialect & PPC_OPCODE_ANY) != 0
1072 && (insn & (0x3ff << 1)) == 19 << 1))) 1449 && (insn & (0x3ff << 1)) == 19 << 1)))
@@ -1075,7 +1452,10 @@ insert_fxm (unsigned long insn,
1075 /* Any other value on mfcr is an error. */ 1452 /* Any other value on mfcr is an error. */
1076 else if ((insn & (0x3ff << 1)) == 19 << 1) 1453 else if ((insn & (0x3ff << 1)) == 19 << 1)
1077 { 1454 {
1078 *errmsg = _("ignoring invalid mfcr mask"); 1455 /* A value of -1 means we used the one operand form of
1456 mfcr which is valid. */
1457 if (value != -1)
1458 *errmsg = _("invalid mfcr mask");
1079 value = 0; 1459 value = 0;
1080 } 1460 }
1081 1461
@@ -1084,7 +1464,7 @@ insert_fxm (unsigned long insn,
1084 1464
1085static long 1465static long
1086extract_fxm (unsigned long insn, 1466extract_fxm (unsigned long insn,
1087 int dialect ATTRIBUTE_UNUSED, 1467 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1088 int *invalid) 1468 int *invalid)
1089{ 1469{
1090 long mask = (insn >> 12) & 0xff; 1470 long mask = (insn >> 12) & 0xff;
@@ -1102,31 +1482,86 @@ extract_fxm (unsigned long insn,
1102 { 1482 {
1103 if (mask != 0) 1483 if (mask != 0)
1104 *invalid = 1; 1484 *invalid = 1;
1485 else
1486 mask = -1;
1105 } 1487 }
1106 1488
1107 return mask; 1489 return mask;
1108} 1490}
1109 1491
1110/* The LI field in an I form instruction. The lower two bits are 1492static unsigned long
1111 forced to zero. */ 1493insert_li20 (unsigned long insn,
1494 long value,
1495 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1496 const char **errmsg ATTRIBUTE_UNUSED)
1497{
1498 return insn | ((value & 0xf0000) >> 5) | ((value & 0x0f800) << 5) | (value & 0x7ff);
1499}
1500
1501static long
1502extract_li20 (unsigned long insn,
1503 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1504 int *invalid ATTRIBUTE_UNUSED)
1505{
1506 long ext = ((insn & 0x4000) == 0x4000) ? 0xfff00000 : 0x00000000;
1507
1508 return ext
1509 | (((insn >> 11) & 0xf) << 16)
1510 | (((insn >> 17) & 0xf) << 12)
1511 | (((insn >> 16) & 0x1) << 11)
1512 | (insn & 0x7ff);
1513}
1514
1515/* The 2-bit L field in a SYNC or WC field in a WAIT instruction.
1516 For SYNC, some L values are reserved:
1517 * Value 3 is reserved on newer server cpus.
1518 * Values 2 and 3 are reserved on all other cpus. */
1112 1519
1113static unsigned long 1520static unsigned long
1114insert_li (unsigned long insn, 1521insert_ls (unsigned long insn,
1115 long value, 1522 long value,
1116 int dialect ATTRIBUTE_UNUSED, 1523 ppc_cpu_t dialect,
1117 const char **errmsg) 1524 const char **errmsg)
1118{ 1525{
1119 if ((value & 3) != 0) 1526 /* For SYNC, some L values are illegal. */
1120 *errmsg = _("ignoring least significant bits in branch offset"); 1527 if (((insn >> 1) & 0x3ff) == 598)
1121 return insn | (value & 0x3fffffc); 1528 {
1529 long max_lvalue = (dialect & PPC_OPCODE_POWER4) ? 2 : 1;
1530 if (value > max_lvalue)
1531 {
1532 *errmsg = _("illegal L operand value");
1533 return insn;
1534 }
1535 }
1536
1537 return insn | ((value & 0x3) << 21);
1122} 1538}
1123 1539
1124static long 1540/* The 4-bit E field in a sync instruction that accepts 2 operands.
1125extract_li (unsigned long insn, 1541 If ESYNC is non-zero, then the L field must be either 0 or 1 and
1126 int dialect ATTRIBUTE_UNUSED, 1542 the complement of ESYNC-bit2. */
1127 int *invalid ATTRIBUTE_UNUSED) 1543
1544static unsigned long
1545insert_esync (unsigned long insn,
1546 long value,
1547 ppc_cpu_t dialect,
1548 const char **errmsg)
1128{ 1549{
1129 return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000; 1550 unsigned long ls = (insn >> 21) & 0x03;
1551
1552 if (value == 0)
1553 {
1554 if (((dialect & PPC_OPCODE_E6500) != 0 && ls > 1)
1555 || ((dialect & PPC_OPCODE_POWER9) != 0 && ls > 2))
1556 *errmsg = _("illegal L operand value");
1557 return insn;
1558 }
1559
1560 if ((ls & ~0x1)
1561 || (((value >> 1) & 0x1) ^ ls) == 0)
1562 *errmsg = _("incompatible L operand value");
1563
1564 return insn | ((value & 0xf) << 16);
1130} 1565}
1131 1566
1132/* The MB and ME fields in an M form instruction expressed as a single 1567/* The MB and ME fields in an M form instruction expressed as a single
@@ -1137,7 +1572,7 @@ extract_li (unsigned long insn,
1137static unsigned long 1572static unsigned long
1138insert_mbe (unsigned long insn, 1573insert_mbe (unsigned long insn,
1139 long value, 1574 long value,
1140 int dialect ATTRIBUTE_UNUSED, 1575 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1141 const char **errmsg) 1576 const char **errmsg)
1142{ 1577{
1143 unsigned long uval, mask; 1578 unsigned long uval, mask;
@@ -1189,7 +1624,7 @@ insert_mbe (unsigned long insn,
1189 1624
1190static long 1625static long
1191extract_mbe (unsigned long insn, 1626extract_mbe (unsigned long insn,
1192 int dialect ATTRIBUTE_UNUSED, 1627 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1193 int *invalid) 1628 int *invalid)
1194{ 1629{
1195 long ret; 1630 long ret;
@@ -1223,7 +1658,7 @@ extract_mbe (unsigned long insn,
1223static unsigned long 1658static unsigned long
1224insert_mb6 (unsigned long insn, 1659insert_mb6 (unsigned long insn,
1225 long value, 1660 long value,
1226 int dialect ATTRIBUTE_UNUSED, 1661 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1227 const char **errmsg ATTRIBUTE_UNUSED) 1662 const char **errmsg ATTRIBUTE_UNUSED)
1228{ 1663{
1229 return insn | ((value & 0x1f) << 6) | (value & 0x20); 1664 return insn | ((value & 0x1f) << 6) | (value & 0x20);
@@ -1231,7 +1666,7 @@ insert_mb6 (unsigned long insn,
1231 1666
1232static long 1667static long
1233extract_mb6 (unsigned long insn, 1668extract_mb6 (unsigned long insn,
1234 int dialect ATTRIBUTE_UNUSED, 1669 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1235 int *invalid ATTRIBUTE_UNUSED) 1670 int *invalid ATTRIBUTE_UNUSED)
1236{ 1671{
1237 return ((insn >> 6) & 0x1f) | (insn & 0x20); 1672 return ((insn >> 6) & 0x1f) | (insn & 0x20);
@@ -1240,22 +1675,9 @@ extract_mb6 (unsigned long insn,
1240/* The NB field in an X form instruction. The value 32 is stored as 1675/* The NB field in an X form instruction. The value 32 is stored as
1241 0. */ 1676 0. */
1242 1677
1243static unsigned long
1244insert_nb (unsigned long insn,
1245 long value,
1246 int dialect ATTRIBUTE_UNUSED,
1247 const char **errmsg)
1248{
1249 if (value < 0 || value > 32)
1250 *errmsg = _("value out of range");
1251 if (value == 32)
1252 value = 0;
1253 return insn | ((value & 0x1f) << 11);
1254}
1255
1256static long 1678static long
1257extract_nb (unsigned long insn, 1679extract_nb (unsigned long insn,
1258 int dialect ATTRIBUTE_UNUSED, 1680 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1259 int *invalid ATTRIBUTE_UNUSED) 1681 int *invalid ATTRIBUTE_UNUSED)
1260{ 1682{
1261 long ret; 1683 long ret;
@@ -1266,6 +1688,26 @@ extract_nb (unsigned long insn,
1266 return ret; 1688 return ret;
1267} 1689}
1268 1690
1691/* The NB field in an lswi instruction, which has special value
1692 restrictions. The value 32 is stored as 0. */
1693
1694static unsigned long
1695insert_nbi (unsigned long insn,
1696 long value,
1697 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1698 const char **errmsg ATTRIBUTE_UNUSED)
1699{
1700 long rtvalue = (insn & RT_MASK) >> 21;
1701 long ravalue = (insn & RA_MASK) >> 16;
1702
1703 if (value == 0)
1704 value = 32;
1705 if (rtvalue + (value + 3) / 4 > (rtvalue > ravalue ? ravalue + 32
1706 : ravalue))
1707 *errmsg = _("address register in load range");
1708 return insn | ((value & 0x1f) << 11);
1709}
1710
1269/* The NSI field in a D form instruction. This is the same as the SI 1711/* The NSI field in a D form instruction. This is the same as the SI
1270 field, only negated. The extraction function always marks it as 1712 field, only negated. The extraction function always marks it as
1271 invalid, since we never want to recognize an instruction which uses 1713 invalid, since we never want to recognize an instruction which uses
@@ -1274,7 +1716,7 @@ extract_nb (unsigned long insn,
1274static unsigned long 1716static unsigned long
1275insert_nsi (unsigned long insn, 1717insert_nsi (unsigned long insn,
1276 long value, 1718 long value,
1277 int dialect ATTRIBUTE_UNUSED, 1719 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1278 const char **errmsg ATTRIBUTE_UNUSED) 1720 const char **errmsg ATTRIBUTE_UNUSED)
1279{ 1721{
1280 return insn | (-value & 0xffff); 1722 return insn | (-value & 0xffff);
@@ -1282,7 +1724,7 @@ insert_nsi (unsigned long insn,
1282 1724
1283static long 1725static long
1284extract_nsi (unsigned long insn, 1726extract_nsi (unsigned long insn,
1285 int dialect ATTRIBUTE_UNUSED, 1727 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1286 int *invalid) 1728 int *invalid)
1287{ 1729{
1288 *invalid = 1; 1730 *invalid = 1;
@@ -1296,7 +1738,7 @@ extract_nsi (unsigned long insn,
1296static unsigned long 1738static unsigned long
1297insert_ral (unsigned long insn, 1739insert_ral (unsigned long insn,
1298 long value, 1740 long value,
1299 int dialect ATTRIBUTE_UNUSED, 1741 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1300 const char **errmsg) 1742 const char **errmsg)
1301{ 1743{
1302 if (value == 0 1744 if (value == 0
@@ -1311,7 +1753,7 @@ insert_ral (unsigned long insn,
1311static unsigned long 1753static unsigned long
1312insert_ram (unsigned long insn, 1754insert_ram (unsigned long insn,
1313 long value, 1755 long value,
1314 int dialect ATTRIBUTE_UNUSED, 1756 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1315 const char **errmsg) 1757 const char **errmsg)
1316{ 1758{
1317 if ((unsigned long) value >= ((insn >> 21) & 0x1f)) 1759 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
@@ -1319,13 +1761,13 @@ insert_ram (unsigned long insn,
1319 return insn | ((value & 0x1f) << 16); 1761 return insn | ((value & 0x1f) << 16);
1320} 1762}
1321 1763
1322/* The RA field in the DQ form lq instruction, which has special 1764/* The RA field in the DQ form lq or an lswx instruction, which have special
1323 value restrictions. */ 1765 value restrictions. */
1324 1766
1325static unsigned long 1767static unsigned long
1326insert_raq (unsigned long insn, 1768insert_raq (unsigned long insn,
1327 long value, 1769 long value,
1328 int dialect ATTRIBUTE_UNUSED, 1770 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1329 const char **errmsg) 1771 const char **errmsg)
1330{ 1772{
1331 long rtvalue = (insn & RT_MASK) >> 21; 1773 long rtvalue = (insn & RT_MASK) >> 21;
@@ -1342,7 +1784,7 @@ insert_raq (unsigned long insn,
1342static unsigned long 1784static unsigned long
1343insert_ras (unsigned long insn, 1785insert_ras (unsigned long insn,
1344 long value, 1786 long value,
1345 int dialect ATTRIBUTE_UNUSED, 1787 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1346 const char **errmsg) 1788 const char **errmsg)
1347{ 1789{
1348 if (value == 0) 1790 if (value == 0)
@@ -1359,7 +1801,7 @@ insert_ras (unsigned long insn,
1359static unsigned long 1801static unsigned long
1360insert_rbs (unsigned long insn, 1802insert_rbs (unsigned long insn,
1361 long value ATTRIBUTE_UNUSED, 1803 long value ATTRIBUTE_UNUSED,
1362 int dialect ATTRIBUTE_UNUSED, 1804 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1363 const char **errmsg ATTRIBUTE_UNUSED) 1805 const char **errmsg ATTRIBUTE_UNUSED)
1364{ 1806{
1365 return insn | (((insn >> 21) & 0x1f) << 11); 1807 return insn | (((insn >> 21) & 0x1f) << 11);
@@ -1367,7 +1809,7 @@ insert_rbs (unsigned long insn,
1367 1809
1368static long 1810static long
1369extract_rbs (unsigned long insn, 1811extract_rbs (unsigned long insn,
1370 int dialect ATTRIBUTE_UNUSED, 1812 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1371 int *invalid) 1813 int *invalid)
1372{ 1814{
1373 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f)) 1815 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
@@ -1375,32 +1817,155 @@ extract_rbs (unsigned long insn,
1375 return 0; 1817 return 0;
1376} 1818}
1377 1819
1378/* The RT field of the DQ form lq instruction, which has special 1820/* The RB field in an lswx instruction, which has special value
1379 value restrictions. */ 1821 restrictions. */
1380 1822
1381static unsigned long 1823static unsigned long
1382insert_rtq (unsigned long insn, 1824insert_rbx (unsigned long insn,
1383 long value, 1825 long value,
1384 int dialect ATTRIBUTE_UNUSED, 1826 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1385 const char **errmsg) 1827 const char **errmsg)
1386{ 1828{
1387 if ((value & 1) != 0) 1829 long rtvalue = (insn & RT_MASK) >> 21;
1388 *errmsg = _("target register operand must be even"); 1830
1389 return insn | ((value & 0x1f) << 21); 1831 if (value == rtvalue)
1832 *errmsg = _("source and target register operands must be different");
1833 return insn | ((value & 0x1f) << 11);
1390} 1834}
1391 1835
1392/* The RS field of the DS form stq instruction, which has special 1836/* The SCI8 field is made up of SCL and {U,N}I8 fields. */
1393 value restrictions. */ 1837static unsigned long
1838insert_sci8 (unsigned long insn,
1839 long value,
1840 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1841 const char **errmsg)
1842{
1843 unsigned int fill_scale = 0;
1844 unsigned long ui8 = value;
1845
1846 if ((ui8 & 0xffffff00) == 0)
1847 ;
1848 else if ((ui8 & 0xffffff00) == 0xffffff00)
1849 fill_scale = 0x400;
1850 else if ((ui8 & 0xffff00ff) == 0)
1851 {
1852 fill_scale = 1 << 8;
1853 ui8 >>= 8;
1854 }
1855 else if ((ui8 & 0xffff00ff) == 0xffff00ff)
1856 {
1857 fill_scale = 0x400 | (1 << 8);
1858 ui8 >>= 8;
1859 }
1860 else if ((ui8 & 0xff00ffff) == 0)
1861 {
1862 fill_scale = 2 << 8;
1863 ui8 >>= 16;
1864 }
1865 else if ((ui8 & 0xff00ffff) == 0xff00ffff)
1866 {
1867 fill_scale = 0x400 | (2 << 8);
1868 ui8 >>= 16;
1869 }
1870 else if ((ui8 & 0x00ffffff) == 0)
1871 {
1872 fill_scale = 3 << 8;
1873 ui8 >>= 24;
1874 }
1875 else if ((ui8 & 0x00ffffff) == 0x00ffffff)
1876 {
1877 fill_scale = 0x400 | (3 << 8);
1878 ui8 >>= 24;
1879 }
1880 else
1881 {
1882 *errmsg = _("illegal immediate value");
1883 ui8 = 0;
1884 }
1885
1886 return insn | fill_scale | (ui8 & 0xff);
1887}
1888
1889static long
1890extract_sci8 (unsigned long insn,
1891 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1892 int *invalid ATTRIBUTE_UNUSED)
1893{
1894 int fill = insn & 0x400;
1895 int scale_factor = (insn & 0x300) >> 5;
1896 long value = (insn & 0xff) << scale_factor;
1897
1898 if (fill != 0)
1899 value |= ~((long) 0xff << scale_factor);
1900 return value;
1901}
1394 1902
1395static unsigned long 1903static unsigned long
1396insert_rsq (unsigned long insn, 1904insert_sci8n (unsigned long insn,
1397 long value ATTRIBUTE_UNUSED, 1905 long value,
1398 int dialect ATTRIBUTE_UNUSED, 1906 ppc_cpu_t dialect,
1399 const char **errmsg) 1907 const char **errmsg)
1400{ 1908{
1401 if ((value & 1) != 0) 1909 return insert_sci8 (insn, -value, dialect, errmsg);
1402 *errmsg = _("source register operand must be even"); 1910}
1403 return insn | ((value & 0x1f) << 21); 1911
1912static long
1913extract_sci8n (unsigned long insn,
1914 ppc_cpu_t dialect,
1915 int *invalid)
1916{
1917 return -extract_sci8 (insn, dialect, invalid);
1918}
1919
1920static unsigned long
1921insert_sd4h (unsigned long insn,
1922 long value,
1923 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1924 const char **errmsg ATTRIBUTE_UNUSED)
1925{
1926 return insn | ((value & 0x1e) << 7);
1927}
1928
1929static long
1930extract_sd4h (unsigned long insn,
1931 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1932 int *invalid ATTRIBUTE_UNUSED)
1933{
1934 return ((insn >> 8) & 0xf) << 1;
1935}
1936
1937static unsigned long
1938insert_sd4w (unsigned long insn,
1939 long value,
1940 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1941 const char **errmsg ATTRIBUTE_UNUSED)
1942{
1943 return insn | ((value & 0x3c) << 6);
1944}
1945
1946static long
1947extract_sd4w (unsigned long insn,
1948 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1949 int *invalid ATTRIBUTE_UNUSED)
1950{
1951 return ((insn >> 8) & 0xf) << 2;
1952}
1953
1954static unsigned long
1955insert_oimm (unsigned long insn,
1956 long value,
1957 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1958 const char **errmsg ATTRIBUTE_UNUSED)
1959{
1960 return insn | (((value - 1) & 0x1f) << 4);
1961}
1962
1963static long
1964extract_oimm (unsigned long insn,
1965 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1966 int *invalid ATTRIBUTE_UNUSED)
1967{
1968 return ((insn >> 4) & 0x1f) + 1;
1404} 1969}
1405 1970
1406/* The SH field in an MD form instruction. This is split. */ 1971/* The SH field in an MD form instruction. This is split. */
@@ -1408,18 +1973,26 @@ insert_rsq (unsigned long insn,
1408static unsigned long 1973static unsigned long
1409insert_sh6 (unsigned long insn, 1974insert_sh6 (unsigned long insn,
1410 long value, 1975 long value,
1411 int dialect ATTRIBUTE_UNUSED, 1976 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1412 const char **errmsg ATTRIBUTE_UNUSED) 1977 const char **errmsg ATTRIBUTE_UNUSED)
1413{ 1978{
1414 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); 1979 /* SH6 operand in the rldixor instructions. */
1980 if (PPC_OP (insn) == 4)
1981 return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 5);
1982 else
1983 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1415} 1984}
1416 1985
1417static long 1986static long
1418extract_sh6 (unsigned long insn, 1987extract_sh6 (unsigned long insn,
1419 int dialect ATTRIBUTE_UNUSED, 1988 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1420 int *invalid ATTRIBUTE_UNUSED) 1989 int *invalid ATTRIBUTE_UNUSED)
1421{ 1990{
1422 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20); 1991 /* SH6 operand in the rldixor instructions. */
1992 if (PPC_OP (insn) == 4)
1993 return ((insn >> 6) & 0x1f) | ((insn << 5) & 0x20);
1994 else
1995 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1423} 1996}
1424 1997
1425/* The SPR field in an XFX form instruction. This is flipped--the 1998/* The SPR field in an XFX form instruction. This is flipped--the
@@ -1428,7 +2001,7 @@ extract_sh6 (unsigned long insn,
1428static unsigned long 2001static unsigned long
1429insert_spr (unsigned long insn, 2002insert_spr (unsigned long insn,
1430 long value, 2003 long value,
1431 int dialect ATTRIBUTE_UNUSED, 2004 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1432 const char **errmsg ATTRIBUTE_UNUSED) 2005 const char **errmsg ATTRIBUTE_UNUSED)
1433{ 2006{
1434 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); 2007 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
@@ -1436,26 +2009,23 @@ insert_spr (unsigned long insn,
1436 2009
1437static long 2010static long
1438extract_spr (unsigned long insn, 2011extract_spr (unsigned long insn,
1439 int dialect ATTRIBUTE_UNUSED, 2012 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1440 int *invalid ATTRIBUTE_UNUSED) 2013 int *invalid ATTRIBUTE_UNUSED)
1441{ 2014{
1442 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); 2015 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1443} 2016}
1444 2017
1445/* Some dialects have 8 SPRG registers instead of the standard 4. */ 2018/* Some dialects have 8 SPRG registers instead of the standard 4. */
2019#define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405)
1446 2020
1447static unsigned long 2021static unsigned long
1448insert_sprg (unsigned long insn, 2022insert_sprg (unsigned long insn,
1449 long value, 2023 long value,
1450 int dialect, 2024 ppc_cpu_t dialect,
1451 const char **errmsg) 2025 const char **errmsg)
1452{ 2026{
1453 /* This check uses PPC_OPCODE_403 because PPC405 is later defined
1454 as a synonym. If ever a 405 specific dialect is added this
1455 check should use that instead. */
1456 if (value > 7 2027 if (value > 7
1457 || (value > 3 2028 || (value > 3 && (dialect & ALLOW8_SPRG) == 0))
1458 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1459 *errmsg = _("invalid sprg number"); 2029 *errmsg = _("invalid sprg number");
1460 2030
1461 /* If this is mfsprg4..7 then use spr 260..263 which can be read in 2031 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
@@ -1468,54 +2038,272 @@ insert_sprg (unsigned long insn,
1468 2038
1469static long 2039static long
1470extract_sprg (unsigned long insn, 2040extract_sprg (unsigned long insn,
1471 int dialect, 2041 ppc_cpu_t dialect,
1472 int *invalid) 2042 int *invalid)
1473{ 2043{
1474 unsigned long val = (insn >> 16) & 0x1f; 2044 unsigned long val = (insn >> 16) & 0x1f;
1475 2045
1476 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279 2046 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
1477 If not BOOKE or 405, then both use only 272..275. */ 2047 If not BOOKE, 405 or VLE, then both use only 272..275. */
1478 if (val <= 3 2048 if ((val - 0x10 > 3 && (dialect & ALLOW8_SPRG) == 0)
1479 || (val < 0x10 && (insn & 0x100) != 0) 2049 || (val - 0x10 > 7 && (insn & 0x100) != 0)
1480 || (val - 0x10 > 3 2050 || val <= 3
1481 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0)) 2051 || (val & 8) != 0)
1482 *invalid = 1; 2052 *invalid = 1;
1483 return val & 7; 2053 return val & 7;
1484} 2054}
1485 2055
1486/* The TBR field in an XFX instruction. This is just like SPR, but it 2056/* The TBR field in an XFX instruction. This is just like SPR, but it
1487 is optional. When TBR is omitted, it must be inserted as 268 (the 2057 is optional. */
1488 magic number of the TB register). These functions treat 0
1489 (indicating an omitted optional operand) as 268. This means that
1490 ``mftb 4,0'' is not handled correctly. This does not matter very
1491 much, since the architecture manual does not define mftb as
1492 accepting any values other than 268 or 269. */
1493
1494#define TB (268)
1495 2058
1496static unsigned long 2059static unsigned long
1497insert_tbr (unsigned long insn, 2060insert_tbr (unsigned long insn,
1498 long value, 2061 long value,
1499 int dialect ATTRIBUTE_UNUSED, 2062 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1500 const char **errmsg ATTRIBUTE_UNUSED) 2063 const char **errmsg)
1501{ 2064{
1502 if (value == 0) 2065 if (value != 268 && value != 269)
1503 value = TB; 2066 *errmsg = _("invalid tbr number");
1504 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); 2067 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1505} 2068}
1506 2069
1507static long 2070static long
1508extract_tbr (unsigned long insn, 2071extract_tbr (unsigned long insn,
1509 int dialect ATTRIBUTE_UNUSED, 2072 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1510 int *invalid ATTRIBUTE_UNUSED) 2073 int *invalid)
1511{ 2074{
1512 long ret; 2075 long ret;
1513 2076
1514 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); 2077 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1515 if (ret == TB) 2078 if (ret != 268 && ret != 269)
1516 ret = 0; 2079 *invalid = 1;
1517 return ret; 2080 return ret;
1518} 2081}
2082
2083/* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
2084
2085static unsigned long
2086insert_xt6 (unsigned long insn,
2087 long value,
2088 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2089 const char **errmsg ATTRIBUTE_UNUSED)
2090{
2091 return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5);
2092}
2093
2094static long
2095extract_xt6 (unsigned long insn,
2096 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2097 int *invalid ATTRIBUTE_UNUSED)
2098{
2099 return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f);
2100}
2101
2102/* The XT and XS fields in an DQ form VSX instruction. This is split. */
2103static unsigned long
2104insert_xtq6 (unsigned long insn,
2105 long value,
2106 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2107 const char **errmsg ATTRIBUTE_UNUSED)
2108{
2109 return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 2);
2110}
2111
2112static long
2113extract_xtq6 (unsigned long insn,
2114 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2115 int *invalid ATTRIBUTE_UNUSED)
2116{
2117 return ((insn << 2) & 0x20) | ((insn >> 21) & 0x1f);
2118}
2119
2120/* The XA field in an XX3 form instruction. This is split. */
2121
2122static unsigned long
2123insert_xa6 (unsigned long insn,
2124 long value,
2125 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2126 const char **errmsg ATTRIBUTE_UNUSED)
2127{
2128 return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3);
2129}
2130
2131static long
2132extract_xa6 (unsigned long insn,
2133 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2134 int *invalid ATTRIBUTE_UNUSED)
2135{
2136 return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
2137}
2138
2139/* The XB field in an XX3 form instruction. This is split. */
2140
2141static unsigned long
2142insert_xb6 (unsigned long insn,
2143 long value,
2144 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2145 const char **errmsg ATTRIBUTE_UNUSED)
2146{
2147 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
2148}
2149
2150static long
2151extract_xb6 (unsigned long insn,
2152 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2153 int *invalid ATTRIBUTE_UNUSED)
2154{
2155 return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f);
2156}
2157
2158/* The XB field in an XX3 form instruction when it must be the same as
2159 the XA field in the instruction. This is used for extended
2160 mnemonics like xvmovdp. This operand is marked FAKE. The insertion
2161 function just copies the XA field into the XB field, and the
2162 extraction function just checks that the fields are the same. */
2163
2164static unsigned long
2165insert_xb6s (unsigned long insn,
2166 long value ATTRIBUTE_UNUSED,
2167 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2168 const char **errmsg ATTRIBUTE_UNUSED)
2169{
2170 return insn | (((insn >> 16) & 0x1f) << 11) | (((insn >> 2) & 0x1) << 1);
2171}
2172
2173static long
2174extract_xb6s (unsigned long insn,
2175 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2176 int *invalid)
2177{
2178 if ((((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
2179 || (((insn >> 2) & 0x1) != ((insn >> 1) & 0x1)))
2180 *invalid = 1;
2181 return 0;
2182}
2183
2184/* The XC field in an XX4 form instruction. This is split. */
2185
2186static unsigned long
2187insert_xc6 (unsigned long insn,
2188 long value,
2189 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2190 const char **errmsg ATTRIBUTE_UNUSED)
2191{
2192 return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2);
2193}
2194
2195static long
2196extract_xc6 (unsigned long insn,
2197 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2198 int *invalid ATTRIBUTE_UNUSED)
2199{
2200 return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f);
2201}
2202
2203static unsigned long
2204insert_dm (unsigned long insn,
2205 long value,
2206 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2207 const char **errmsg)
2208{
2209 if (value != 0 && value != 1)
2210 *errmsg = _("invalid constant");
2211 return insn | (((value) ? 3 : 0) << 8);
2212}
2213
2214static long
2215extract_dm (unsigned long insn,
2216 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2217 int *invalid)
2218{
2219 long value;
2220
2221 value = (insn >> 8) & 3;
2222 if (value != 0 && value != 3)
2223 *invalid = 1;
2224 return (value) ? 1 : 0;
2225}
2226
2227/* The VLESIMM field in an I16A form instruction. This is split. */
2228
2229static unsigned long
2230insert_vlesi (unsigned long insn,
2231 long value,
2232 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2233 const char **errmsg ATTRIBUTE_UNUSED)
2234{
2235 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2236}
2237
2238static long
2239extract_vlesi (unsigned long insn,
2240 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2241 int *invalid ATTRIBUTE_UNUSED)
2242{
2243 long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2244 value = (value ^ 0x8000) - 0x8000;
2245 return value;
2246}
2247
2248static unsigned long
2249insert_vlensi (unsigned long insn,
2250 long value,
2251 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2252 const char **errmsg ATTRIBUTE_UNUSED)
2253{
2254 value = -value;
2255 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2256}
2257static long
2258extract_vlensi (unsigned long insn,
2259 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2260 int *invalid ATTRIBUTE_UNUSED)
2261{
2262 long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2263 value = (value ^ 0x8000) - 0x8000;
2264 /* Don't use for disassembly. */
2265 *invalid = 1;
2266 return -value;
2267}
2268
2269/* The VLEUIMM field in an I16A form instruction. This is split. */
2270
2271static unsigned long
2272insert_vleui (unsigned long insn,
2273 long value,
2274 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2275 const char **errmsg ATTRIBUTE_UNUSED)
2276{
2277 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2278}
2279
2280static long
2281extract_vleui (unsigned long insn,
2282 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2283 int *invalid ATTRIBUTE_UNUSED)
2284{
2285 return ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2286}
2287
2288/* The VLEUIMML field in an I16L form instruction. This is split. */
2289
2290static unsigned long
2291insert_vleil (unsigned long insn,
2292 long value,
2293 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2294 const char **errmsg ATTRIBUTE_UNUSED)
2295{
2296 return insn | ((value & 0xf800) << 5) | (value & 0x7ff);
2297}
2298
2299static long
2300extract_vleil (unsigned long insn,
2301 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2302 int *invalid ATTRIBUTE_UNUSED)
2303{
2304 return ((insn >> 5) & 0xf800) | (insn & 0x7ff);
2305}
2306
1519 2307
1520/* Macros used to form opcodes. */ 2308/* Macros used to form opcodes. */
1521 2309
@@ -1535,6 +2323,17 @@ extract_tbr (unsigned long insn,
1535#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21)) 2323#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1536#define OPL_MASK OPL (0x3f,1) 2324#define OPL_MASK OPL (0x3f,1)
1537 2325
2326/* The main opcode combined with an update code in D form instruction.
2327 Used for extended mnemonics for VLE memory instructions. */
2328#define OPVUP(x,vup) (OP (x) | ((((unsigned long)(vup)) & 0xff) << 8))
2329#define OPVUP_MASK OPVUP (0x3f, 0xff)
2330
2331/* The main opcode combined with an update code and the RT fields specified in
2332 D form instruction. Used for VLE volatile context save/restore
2333 instructions. */
2334#define OPVUPRT(x,vup,rt) (OPVUP (x, vup) | ((((unsigned long)(rt)) & 0x1f) << 21))
2335#define OPVUPRT_MASK OPVUPRT (0x3f, 0xff, 0x1f)
2336
1538/* An A form instruction. */ 2337/* An A form instruction. */
1539#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1)) 2338#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1540#define A_MASK A (0x3f, 0x1f, 1) 2339#define A_MASK A (0x3f, 0x1f, 1)
@@ -1555,6 +2354,43 @@ extract_tbr (unsigned long insn,
1555#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1)) 2354#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1556#define B_MASK B (0x3f, 1, 1) 2355#define B_MASK B (0x3f, 1, 1)
1557 2356
2357/* A BD8 form instruction. This is a 16-bit instruction. */
2358#define BD8(op, aa, lk) (((((unsigned long)(op)) & 0x3f) << 10) | (((aa) & 1) << 9) | (((lk) & 1) << 8))
2359#define BD8_MASK BD8 (0x3f, 1, 1)
2360
2361/* Another BD8 form instruction. This is a 16-bit instruction. */
2362#define BD8IO(op) ((((unsigned long)(op)) & 0x1f) << 11)
2363#define BD8IO_MASK BD8IO (0x1f)
2364
2365/* A BD8 form instruction for simplified mnemonics. */
2366#define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8))
2367/* A mask that excludes BO32 and BI32. */
2368#define EBD8IO1_MASK 0xf800
2369/* A mask that includes BO32 and excludes BI32. */
2370#define EBD8IO2_MASK 0xfc00
2371/* A mask that include BO32 AND BI32. */
2372#define EBD8IO3_MASK 0xff00
2373
2374/* A BD15 form instruction. */
2375#define BD15(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 0xf) << 22) | ((lk) & 1))
2376#define BD15_MASK BD15 (0x3f, 0xf, 1)
2377
2378/* A BD15 form instruction for extended conditional branch mnemonics. */
2379#define EBD15(op, aa, bo, lk) (((op) & 0x3f) << 26) | (((aa) & 0xf) << 22) | (((bo) & 0x3) << 20) | ((lk) & 1)
2380#define EBD15_MASK 0xfff00001
2381
2382/* A BD15 form instruction for extended conditional branch mnemonics with BI. */
2383#define EBD15BI(op, aa, bo, bi, lk) (((op) & 0x3f) << 26) \
2384 | (((aa) & 0xf) << 22) \
2385 | (((bo) & 0x3) << 20) \
2386 | (((bi) & 0x3) << 16) \
2387 | ((lk) & 1)
2388#define EBD15BI_MASK 0xfff30001
2389
2390/* A BD24 form instruction. */
2391#define BD24(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 25) | ((lk) & 1))
2392#define BD24_MASK BD24 (0x3f, 1, 1)
2393
1558/* A B form instruction setting the BO field. */ 2394/* A B form instruction setting the BO field. */
1559#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21)) 2395#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1560#define BBO_MASK BBO (0x3f, 0x1f, 1, 1) 2396#define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
@@ -1562,7 +2398,7 @@ extract_tbr (unsigned long insn,
1562/* A BBO_MASK with the y bit of the BO field removed. This permits 2398/* A BBO_MASK with the y bit of the BO field removed. This permits
1563 matching a conditional branch regardless of the setting of the y 2399 matching a conditional branch regardless of the setting of the y
1564 bit. Similarly for the 'at' bits used for power4 branch hints. */ 2400 bit. Similarly for the 'at' bits used for power4 branch hints. */
1565#define Y_MASK (((unsigned long) 1) << 21) 2401#define Y_MASK (((unsigned long) 1) << 21)
1566#define AT1_MASK (((unsigned long) 3) << 21) 2402#define AT1_MASK (((unsigned long) 3) << 21)
1567#define AT2_MASK (((unsigned long) 9) << 21) 2403#define AT2_MASK (((unsigned long) 9) << 21)
1568#define BBOY_MASK (BBO_MASK &~ Y_MASK) 2404#define BBOY_MASK (BBO_MASK &~ Y_MASK)
@@ -1583,6 +2419,12 @@ extract_tbr (unsigned long insn,
1583#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK) 2419#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1584#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK) 2420#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1585 2421
2422/* A VLE C form instruction. */
2423#define C_LK(x, lk) (((((unsigned long)(x)) & 0x7fff) << 1) | ((lk) & 1))
2424#define C_LK_MASK C_LK(0x7fff, 1)
2425#define C(x) ((((unsigned long)(x)) & 0xffff))
2426#define C_MASK C(0xffff)
2427
1586/* An Context form instruction. */ 2428/* An Context form instruction. */
1587#define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7)) 2429#define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
1588#define CTX_MASK CTX(0x3f, 0x7) 2430#define CTX_MASK CTX(0x3f, 0x7)
@@ -1594,22 +2436,46 @@ extract_tbr (unsigned long insn,
1594/* The main opcode mask with the RA field clear. */ 2436/* The main opcode mask with the RA field clear. */
1595#define DRA_MASK (OP_MASK | RA_MASK) 2437#define DRA_MASK (OP_MASK | RA_MASK)
1596 2438
2439/* A DQ form VSX instruction. */
2440#define DQX(op, xop) (OP (op) | ((xop) & 0x7))
2441#define DQX_MASK DQX (0x3f, 7)
2442
1597/* A DS form instruction. */ 2443/* A DS form instruction. */
1598#define DSO(op, xop) (OP (op) | ((xop) & 0x3)) 2444#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1599#define DS_MASK DSO (0x3f, 3) 2445#define DS_MASK DSO (0x3f, 3)
1600 2446
1601/* A DE form instruction. */ 2447/* An DX form instruction. */
1602#define DEO(op, xop) (OP (op) | ((xop) & 0xf)) 2448#define DX(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1603#define DE_MASK DEO (0x3e, 0xf) 2449#define DX_MASK DX (0x3f, 0x1f)
1604 2450
1605/* An EVSEL form instruction. */ 2451/* An EVSEL form instruction. */
1606#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3) 2452#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1607#define EVSEL_MASK EVSEL(0x3f, 0xff) 2453#define EVSEL_MASK EVSEL(0x3f, 0xff)
1608 2454
2455/* An IA16 form instruction. */
2456#define IA16(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2457#define IA16_MASK IA16(0x3f, 0x1f)
2458
2459/* An I16A form instruction. */
2460#define I16A(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2461#define I16A_MASK I16A(0x3f, 0x1f)
2462
2463/* An I16L form instruction. */
2464#define I16L(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2465#define I16L_MASK I16L(0x3f, 0x1f)
2466
2467/* An IM7 form instruction. */
2468#define IM7(op) ((((unsigned long)(op)) & 0x1f) << 11)
2469#define IM7_MASK IM7(0x1f)
2470
1609/* An M form instruction. */ 2471/* An M form instruction. */
1610#define M(op, rc) (OP (op) | ((rc) & 1)) 2472#define M(op, rc) (OP (op) | ((rc) & 1))
1611#define M_MASK M (0x3f, 1) 2473#define M_MASK M (0x3f, 1)
1612 2474
2475/* An LI20 form instruction. */
2476#define LI20(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1) << 15)
2477#define LI20_MASK LI20(0x3f, 0x1)
2478
1613/* An M form instruction with the ME field specified. */ 2479/* An M form instruction with the ME field specified. */
1614#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1)) 2480#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1615 2481
@@ -1640,44 +2506,189 @@ extract_tbr (unsigned long insn,
1640#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1)) 2506#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1641#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1) 2507#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1642 2508
1643/* An VX form instruction. */ 2509/* An SCI8 form instruction. */
2510#define SCI8(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11))
2511#define SCI8_MASK SCI8(0x3f, 0x1f)
2512
2513/* An SCI8 form instruction. */
2514#define SCI8BF(op, fop, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11) | (((fop) & 7) << 23))
2515#define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f)
2516
2517/* An SD4 form instruction. This is a 16-bit instruction. */
2518#define SD4(op) ((((unsigned long)(op)) & 0xf) << 12)
2519#define SD4_MASK SD4(0xf)
2520
2521/* An SE_IM5 form instruction. This is a 16-bit instruction. */
2522#define SE_IM5(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x1) << 9))
2523#define SE_IM5_MASK SE_IM5(0x3f, 1)
2524
2525/* An SE_R form instruction. This is a 16-bit instruction. */
2526#define SE_R(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3f) << 4))
2527#define SE_R_MASK SE_R(0x3f, 0x3f)
2528
2529/* An SE_RR form instruction. This is a 16-bit instruction. */
2530#define SE_RR(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3) << 8))
2531#define SE_RR_MASK SE_RR(0x3f, 3)
2532
2533/* A VX form instruction. */
1644#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff)) 2534#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1645 2535
1646/* The mask for an VX form instruction. */ 2536/* The mask for an VX form instruction. */
1647#define VX_MASK VX(0x3f, 0x7ff) 2537#define VX_MASK VX(0x3f, 0x7ff)
1648 2538
1649/* An VA form instruction. */ 2539/* A VX_MASK with the VA field fixed. */
2540#define VXVA_MASK (VX_MASK | (0x1f << 16))
2541
2542/* A VX_MASK with the VB field fixed. */
2543#define VXVB_MASK (VX_MASK | (0x1f << 11))
2544
2545/* A VX_MASK with the VA and VB fields fixed. */
2546#define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11))
2547
2548/* A VX_MASK with the VD and VA fields fixed. */
2549#define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16))
2550
2551/* A VX_MASK with a UIMM4 field. */
2552#define VXUIMM4_MASK (VX_MASK | (0x1 << 20))
2553
2554/* A VX_MASK with a UIMM3 field. */
2555#define VXUIMM3_MASK (VX_MASK | (0x3 << 19))
2556
2557/* A VX_MASK with a UIMM2 field. */
2558#define VXUIMM2_MASK (VX_MASK | (0x7 << 18))
2559
2560/* A VX_MASK with a PS field. */
2561#define VXPS_MASK (VX_MASK & ~(0x1 << 9))
2562
2563/* A VX_MASK with the VA field fixed with a PS field. */
2564#define VXVAPS_MASK ((VX_MASK | (0x1f << 16)) & ~(0x1 << 9))
2565
2566/* A VA form instruction. */
1650#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f)) 2567#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1651 2568
1652/* The mask for an VA form instruction. */ 2569/* The mask for an VA form instruction. */
1653#define VXA_MASK VXA(0x3f, 0x3f) 2570#define VXA_MASK VXA(0x3f, 0x3f)
1654 2571
1655/* An VXR form instruction. */ 2572/* A VXA_MASK with a SHB field. */
2573#define VXASHB_MASK (VXA_MASK | (1 << 10))
2574
2575/* A VXR form instruction. */
1656#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff)) 2576#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1657 2577
1658/* The mask for a VXR form instruction. */ 2578/* The mask for a VXR form instruction. */
1659#define VXR_MASK VXR(0x3f, 0x3ff, 1) 2579#define VXR_MASK VXR(0x3f, 0x3ff, 1)
1660 2580
2581/* A VX form instruction with a VA tertiary opcode. */
2582#define VXVA(op, xop, vaop) (VX(op,xop) | (((vaop) & 0x1f) << 16))
2583
2584#define VXASH(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2585#define VXASH_MASK VXASH (0x3f, 0x1f)
2586
1661/* An X form instruction. */ 2587/* An X form instruction. */
1662#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) 2588#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1663 2589
2590/* A X form instruction for Quad-Precision FP Instructions. */
2591#define XVA(op, xop, vaop) (X(op,xop) | (((vaop) & 0x1f) << 16))
2592
2593/* An EX form instruction. */
2594#define EX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2595
2596/* The mask for an EX form instruction. */
2597#define EX_MASK EX (0x3f, 0x7ff)
2598
2599/* An XX2 form instruction. */
2600#define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2))
2601
2602/* A XX2 form instruction with the VA bits specified. */
2603#define XX2VA(op, xop, vaop) (XX2(op,xop) | (((vaop) & 0x1f) << 16))
2604
2605/* An XX3 form instruction. */
2606#define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3))
2607
2608/* An XX3 form instruction with the RC bit specified. */
2609#define XX3RC(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | ((((unsigned long)(xop)) & 0x7f) << 3))
2610
2611/* An XX4 form instruction. */
2612#define XX4(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3) << 4))
2613
1664/* A Z form instruction. */ 2614/* A Z form instruction. */
1665#define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1)) 2615#define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
1666 2616
1667/* An X form instruction with the RC bit specified. */ 2617/* An X form instruction with the RC bit specified. */
1668#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1)) 2618#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1669 2619
2620/* A X form instruction for Quad-Precision FP Instructions with RC bit. */
2621#define XVARC(op, xop, vaop, rc) (XVA ((op), (xop), (vaop)) | ((rc) & 1))
2622
2623/* An X form instruction with the RA bits specified as two ops. */
2624#define XMMF(op, xop, mop0, mop1) (X ((op), (xop)) | ((mop0) & 3) << 19 | ((mop1) & 7) << 16)
2625
1670/* A Z form instruction with the RC bit specified. */ 2626/* A Z form instruction with the RC bit specified. */
1671#define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) 2627#define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
1672 2628
1673/* The mask for an X form instruction. */ 2629/* The mask for an X form instruction. */
1674#define X_MASK XRC (0x3f, 0x3ff, 1) 2630#define X_MASK XRC (0x3f, 0x3ff, 1)
1675 2631
2632/* The mask for an X form instruction with the BF bits specified. */
2633#define XBF_MASK (X_MASK | (3 << 21))
2634
2635/* An X form wait instruction with everything filled in except the WC field. */
2636#define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
2637
2638/* The mask for an XX1 form instruction. */
2639#define XX1_MASK X (0x3f, 0x3ff)
2640
2641/* An XX1_MASK with the RB field fixed. */
2642#define XX1RB_MASK (XX1_MASK | RB_MASK)
2643
2644/* The mask for an XX2 form instruction. */
2645#define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16))
2646
2647/* The mask for an XX2 form instruction with the UIM bits specified. */
2648#define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18))
2649
2650/* The mask for an XX2 form instruction with the 4 UIM bits specified. */
2651#define XX2UIM4_MASK (XX2 (0x3f, 0x1ff) | (1 << 20))
2652
2653/* The mask for an XX2 form instruction with the BF bits specified. */
2654#define XX2BF_MASK (XX2_MASK | (3 << 21) | (1))
2655
2656/* The mask for an XX2 form instruction with the BF and DCMX bits specified. */
2657#define XX2BFD_MASK (XX2 (0x3f, 0x1ff) | 1)
2658
2659/* The mask for an XX2 form instruction with a split DCMX bits specified. */
2660#define XX2DCMXS_MASK XX2 (0x3f, 0x1ee)
2661
2662/* The mask for an XX3 form instruction. */
2663#define XX3_MASK XX3 (0x3f, 0xff)
2664
2665/* The mask for an XX3 form instruction with the BF bits specified. */
2666#define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1))
2667
2668/* The mask for an XX3 form instruction with the DM or SHW bits specified. */
2669#define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
2670#define XX3SHW_MASK XX3DM_MASK
2671
2672/* The mask for an XX4 form instruction. */
2673#define XX4_MASK XX4 (0x3f, 0x3)
2674
2675/* An X form wait instruction with everything filled in except the WC field. */
2676#define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
2677
2678/* The mask for an XMMF form instruction. */
2679#define XMMF_MASK (XMMF (0x3f, 0x3ff, 3, 7) | (1))
2680
1676/* The mask for a Z form instruction. */ 2681/* The mask for a Z form instruction. */
1677#define Z_MASK ZRC (0x3f, 0x1ff, 1) 2682#define Z_MASK ZRC (0x3f, 0x1ff, 1)
2683#define Z2_MASK ZRC (0x3f, 0xff, 1)
1678 2684
1679/* An X_MASK with the RA field fixed. */ 2685/* An X_MASK with the RA/VA field fixed. */
1680#define XRA_MASK (X_MASK | RA_MASK) 2686#define XRA_MASK (X_MASK | RA_MASK)
2687#define XVA_MASK XRA_MASK
2688
2689/* An XRA_MASK with the A_L/W field clear. */
2690#define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
2691#define XRLA_MASK XWRA_MASK
1681 2692
1682/* An X_MASK with the RB field fixed. */ 2693/* An X_MASK with the RB field fixed. */
1683#define XRB_MASK (X_MASK | RB_MASK) 2694#define XRB_MASK (X_MASK | RB_MASK)
@@ -1691,18 +2702,54 @@ extract_tbr (unsigned long insn,
1691/* An X_MASK with the RA and RB fields fixed. */ 2702/* An X_MASK with the RA and RB fields fixed. */
1692#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK) 2703#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1693 2704
2705/* An XBF_MASK with the RA and RB fields fixed. */
2706#define XBFRARB_MASK (XBF_MASK | RA_MASK | RB_MASK)
2707
1694/* An XRARB_MASK, but with the L bit clear. */ 2708/* An XRARB_MASK, but with the L bit clear. */
1695#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16)) 2709#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1696 2710
2711/* An XRARB_MASK, but with the L bits in a darn instruction clear. */
2712#define XLRAND_MASK (XRARB_MASK & ~((unsigned long) 3 << 16))
2713
1697/* An X_MASK with the RT and RA fields fixed. */ 2714/* An X_MASK with the RT and RA fields fixed. */
1698#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK) 2715#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1699 2716
2717/* An X_MASK with the RT and RB fields fixed. */
2718#define XRTRB_MASK (X_MASK | RT_MASK | RB_MASK)
2719
1700/* An XRTRA_MASK, but with L bit clear. */ 2720/* An XRTRA_MASK, but with L bit clear. */
1701#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21)) 2721#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1702 2722
2723/* An X_MASK with the RT, RA and RB fields fixed. */
2724#define XRTRARB_MASK (X_MASK | RT_MASK | RA_MASK | RB_MASK)
2725
2726/* An XRTRARB_MASK, but with L bit clear. */
2727#define XRTLRARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 21))
2728
2729/* An XRTRARB_MASK, but with A bit clear. */
2730#define XRTARARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 25))
2731
2732/* An XRTRARB_MASK, but with BF bits clear. */
2733#define XRTBFRARB_MASK (XRTRARB_MASK & ~((unsigned long) 7 << 23))
2734
1703/* An X form instruction with the L bit specified. */ 2735/* An X form instruction with the L bit specified. */
1704#define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21)) 2736#define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1705 2737
2738/* An X form instruction with the L bits specified. */
2739#define XOPL2(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
2740
2741/* An X form instruction with the L bit and RC bit specified. */
2742#define XRCL(op, xop, l, rc) (XRC ((op), (xop), (rc)) | ((((unsigned long)(l)) & 1) << 21))
2743
2744/* An X form instruction with RT fields specified */
2745#define XRT(op, xop, rt) (X ((op), (xop)) \
2746 | ((((unsigned long)(rt)) & 0x1f) << 21))
2747
2748/* An X form instruction with RT and RA fields specified */
2749#define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \
2750 | ((((unsigned long)(rt)) & 0x1f) << 21) \
2751 | ((((unsigned long)(ra)) & 0x1f) << 16))
2752
1706/* The mask for an X form comparison instruction. */ 2753/* The mask for an X form comparison instruction. */
1707#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22)) 2754#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1708 2755
@@ -1724,6 +2771,9 @@ extract_tbr (unsigned long insn,
1724/* An X form sync instruction with everything filled in except the LS field. */ 2771/* An X form sync instruction with everything filled in except the LS field. */
1725#define XSYNC_MASK (0xff9fffff) 2772#define XSYNC_MASK (0xff9fffff)
1726 2773
2774/* An X form sync instruction with everything filled in except the L and E fields. */
2775#define XSYNCLE_MASK (0xff90ffff)
2776
1727/* An X_MASK, but with the EH bit clear. */ 2777/* An X_MASK, but with the EH bit clear. */
1728#define XEH_MASK (X_MASK & ~((unsigned long )1)) 2778#define XEH_MASK (X_MASK & ~((unsigned long )1))
1729 2779
@@ -1733,11 +2783,11 @@ extract_tbr (unsigned long insn,
1733 2783
1734/* An XFL form instruction. */ 2784/* An XFL form instruction. */
1735#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1)) 2785#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1736#define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16)) 2786#define XFL_MASK XFL (0x3f, 0x3ff, 1)
1737 2787
1738/* An X form isel instruction. */ 2788/* An X form isel instruction. */
1739#define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1)) 2789#define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1740#define XISEL_MASK XISEL(0x3f, 0x1f) 2790#define XISEL_MASK XISEL(0x3f, 0x1f)
1741 2791
1742/* An XL form instruction with the LK field set to 0. */ 2792/* An XL form instruction with the LK field set to 0. */
1743#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) 2793#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
@@ -1748,6 +2798,9 @@ extract_tbr (unsigned long insn,
1748/* The mask for an XL form instruction. */ 2798/* The mask for an XL form instruction. */
1749#define XL_MASK XLLK (0x3f, 0x3ff, 1) 2799#define XL_MASK XLLK (0x3f, 0x3ff, 1)
1750 2800
2801/* An XL_MASK with the RT, RA and RB fields fixed, but S bit clear. */
2802#define XLS_MASK ((XL_MASK | RT_MASK | RA_MASK | RB_MASK) & ~(1 << 11))
2803
1751/* An XL form instruction which explicitly sets the BO field. */ 2804/* An XL form instruction which explicitly sets the BO field. */
1752#define XLO(op, bo, xop, lk) \ 2805#define XLO(op, bo, xop, lk) \
1753 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21)) 2806 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
@@ -1778,6 +2831,9 @@ extract_tbr (unsigned long insn,
1778/* An XL_MASK with the BO, BI and BB fields fixed. */ 2831/* An XL_MASK with the BO, BI and BB fields fixed. */
1779#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK) 2832#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1780 2833
2834/* An X form mbar instruction with MO field. */
2835#define XMBAR(op, xop, mo) (X ((op), (xop)) | ((((unsigned long)(mo)) & 1) << 21))
2836
1781/* An XO form instruction. */ 2837/* An XO form instruction. */
1782#define XO(op, xop, oe, rc) \ 2838#define XO(op, xop, oe, rc) \
1783 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1)) 2839 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
@@ -1786,6 +2842,12 @@ extract_tbr (unsigned long insn,
1786/* An XO_MASK with the RB field fixed. */ 2842/* An XO_MASK with the RB field fixed. */
1787#define XORB_MASK (XO_MASK | RB_MASK) 2843#define XORB_MASK (XO_MASK | RB_MASK)
1788 2844
2845/* An XOPS form instruction for paired singles. */
2846#define XOPS(op, xop, rc) \
2847 (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
2848#define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
2849
2850
1789/* An XS form instruction. */ 2851/* An XS form instruction. */
1790#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1)) 2852#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1791#define XS_MASK XS (0x3f, 0x1ff, 1) 2853#define XS_MASK XS (0x3f, 0x1ff, 1)
@@ -1809,7 +2871,7 @@ extract_tbr (unsigned long insn,
1809 2871
1810/* An XFX form instruction with the SPR field filled in except for the 2872/* An XFX form instruction with the SPR field filled in except for the
1811 SPRG field. */ 2873 SPRG field. */
1812#define XSPRG_MASK (XSPR_MASK & ~(0x17 << 16)) 2874#define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
1813 2875
1814/* An X form instruction with everything filled in except the E field. */ 2876/* An X form instruction with everything filled in except the E field. */
1815#define XE_MASK (0xffff7fff) 2877#define XE_MASK (0xffff7fff)
@@ -1818,6 +2880,19 @@ extract_tbr (unsigned long insn,
1818#define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f)) 2880#define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1819#define XUC_MASK XUC(0x3f, 0x1f) 2881#define XUC_MASK XUC(0x3f, 0x1f)
1820 2882
2883/* An XW form instruction. */
2884#define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1))
2885/* The mask for a G form instruction. rc not supported at present. */
2886#define XW_MASK XW (0x3f, 0x3f, 0)
2887
2888/* An APU form instruction. */
2889#define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1))
2890
2891/* The mask for an APU form instruction. */
2892#define APU_MASK APU (0x3f, 0x3ff, 1)
2893#define APU_RT_MASK (APU_MASK | RT_MASK)
2894#define APU_RA_MASK (APU_MASK | RA_MASK)
2895
1821/* The BO encodings used in extended conditional branch mnemonics. */ 2896/* The BO encodings used in extended conditional branch mnemonics. */
1822#define BODNZF (0x0) 2897#define BODNZF (0x0)
1823#define BODNZFP (0x1) 2898#define BODNZFP (0x1)
@@ -1848,6 +2923,16 @@ extract_tbr (unsigned long insn,
1848 2923
1849#define BOU (0x14) 2924#define BOU (0x14)
1850 2925
2926/* The BO16 encodings used in extended VLE conditional branch mnemonics. */
2927#define BO16F (0x0)
2928#define BO16T (0x1)
2929
2930/* The BO32 encodings used in extended VLE conditional branch mnemonics. */
2931#define BO32F (0x0)
2932#define BO32T (0x1)
2933#define BO32DNZ (0x2)
2934#define BO32DZ (0x3)
2935
1851/* The BI condition bit encodings used in extended conditional branch 2936/* The BI condition bit encodings used in extended conditional branch
1852 mnemonics. */ 2937 mnemonics. */
1853#define CBLT (0) 2938#define CBLT (0)
@@ -1875,3066 +2960,4267 @@ extract_tbr (unsigned long insn,
1875/* Smaller names for the flags so each entry in the opcodes table will 2960/* Smaller names for the flags so each entry in the opcodes table will
1876 fit on a single line. */ 2961 fit on a single line. */
1877#undef PPC 2962#undef PPC
1878#define PPC PPC_OPCODE_PPC 2963#define PPC PPC_OPCODE_PPC
1879#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON 2964#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1880#define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1881#define POWER4 PPC_OPCODE_POWER4 2965#define POWER4 PPC_OPCODE_POWER4
1882#define POWER5 PPC_OPCODE_POWER5 2966#define POWER5 PPC_OPCODE_POWER5
1883#define POWER6 PPC_OPCODE_POWER6 2967#define POWER6 PPC_OPCODE_POWER6
2968#define POWER7 PPC_OPCODE_POWER7
2969#define POWER8 PPC_OPCODE_POWER8
2970#define POWER9 PPC_OPCODE_POWER9
1884#define CELL PPC_OPCODE_CELL 2971#define CELL PPC_OPCODE_CELL
1885#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC 2972#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE
1886#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC 2973#define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \
2974 | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
1887#define PPC403 PPC_OPCODE_403 2975#define PPC403 PPC_OPCODE_403
1888#define PPC405 PPC403 2976#define PPC405 PPC_OPCODE_405
1889#define PPC440 PPC_OPCODE_440 2977#define PPC440 PPC_OPCODE_440
1890#define PPC750 PPC 2978#define PPC464 PPC440
1891#define PPC860 PPC 2979#define PPC476 PPC_OPCODE_476
2980#define PPC750 PPC_OPCODE_750
2981#define PPC7450 PPC_OPCODE_7450
2982#define PPC860 PPC_OPCODE_860
2983#define PPCPS PPC_OPCODE_PPCPS
1892#define PPCVEC PPC_OPCODE_ALTIVEC 2984#define PPCVEC PPC_OPCODE_ALTIVEC
1893#define POWER PPC_OPCODE_POWER 2985#define PPCVEC2 PPC_OPCODE_ALTIVEC2
1894#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 2986#define PPCVEC3 PPC_OPCODE_ALTIVEC2
1895#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 2987#define PPCVSX PPC_OPCODE_VSX
1896#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32 2988#define PPCVSX2 PPC_OPCODE_VSX
1897#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON 2989#define PPCVSX3 PPC_OPCODE_VSX3
1898#define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32 2990#define POWER PPC_OPCODE_POWER
1899#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 2991#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
2992#define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
2993#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
2994#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
2995#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
1900#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON 2996#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
1901#define MFDEC1 PPC_OPCODE_POWER 2997#define MFDEC1 PPC_OPCODE_POWER
1902#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE 2998#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE | PPC_OPCODE_TITAN
1903#define BOOKE PPC_OPCODE_BOOKE 2999#define BOOKE PPC_OPCODE_BOOKE
1904#define BOOKE64 PPC_OPCODE_BOOKE64 3000#define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS
1905#define CLASSIC PPC_OPCODE_CLASSIC
1906#define PPCE300 PPC_OPCODE_E300 3001#define PPCE300 PPC_OPCODE_E300
1907#define PPCSPE PPC_OPCODE_SPE 3002#define PPCSPE PPC_OPCODE_SPE
1908#define PPCISEL PPC_OPCODE_ISEL 3003#define PPCISEL PPC_OPCODE_ISEL
1909#define PPCEFS PPC_OPCODE_EFS 3004#define PPCEFS PPC_OPCODE_EFS
1910#define PPCBRLK PPC_OPCODE_BRLOCK 3005#define PPCBRLK PPC_OPCODE_BRLOCK
1911#define PPCPMR PPC_OPCODE_PMR 3006#define PPCPMR PPC_OPCODE_PMR
1912#define PPCCHLK PPC_OPCODE_CACHELCK 3007#define PPCTMR PPC_OPCODE_TMR
1913#define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64 3008#define PPCCHLK PPC_OPCODE_CACHELCK
1914#define PPCRFMCI PPC_OPCODE_RFMCI 3009#define PPCRFMCI PPC_OPCODE_RFMCI
3010#define E500MC PPC_OPCODE_E500MC
3011#define PPCA2 PPC_OPCODE_A2
3012#define TITAN PPC_OPCODE_TITAN
3013#define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN
3014#define E500 PPC_OPCODE_E500
3015#define E6500 PPC_OPCODE_E6500
3016#define PPCVLE PPC_OPCODE_VLE
3017#define PPCHTM PPC_OPCODE_HTM
3018#define E200Z4 PPC_OPCODE_E200Z4
3019/* The list of embedded processors that use the embedded operand ordering
3020 for the 3 operand dcbt and dcbtst instructions. */
3021#define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \
3022 | PPC_OPCODE_A2)
3023
3024
1915 3025
1916/* The opcode table. 3026/* The opcode table.
1917 3027
1918 The format of the opcode table is: 3028 The format of the opcode table is:
1919 3029
1920 NAME OPCODE MASK FLAGS { OPERANDS } 3030 NAME OPCODE MASK FLAGS ANTI {OPERANDS}
1921 3031
1922 NAME is the name of the instruction. 3032 NAME is the name of the instruction.
1923 OPCODE is the instruction opcode. 3033 OPCODE is the instruction opcode.
1924 MASK is the opcode mask; this is used to tell the disassembler 3034 MASK is the opcode mask; this is used to tell the disassembler
1925 which bits in the actual opcode must match OPCODE. 3035 which bits in the actual opcode must match OPCODE.
1926 FLAGS are flags indicated what processors support the instruction. 3036 FLAGS are flags indicating which processors support the instruction.
3037 ANTI indicates which processors don't support the instruction.
1927 OPERANDS is the list of operands. 3038 OPERANDS is the list of operands.
1928 3039
1929 The disassembler reads the table in order and prints the first 3040 The disassembler reads the table in order and prints the first
1930 instruction which matches, so this table is sorted to put more 3041 instruction which matches, so this table is sorted to put more
1931 specific instructions before more general instructions. It is also 3042 specific instructions before more general instructions.
1932 sorted by major opcode. */ 3043
3044 This table must be sorted by major opcode. Please try to keep it
3045 vaguely sorted within major opcode too, except of course where
3046 constrained otherwise by disassembler operation. */
1933 3047
1934const struct powerpc_opcode powerpc_opcodes[] = { 3048const struct powerpc_opcode powerpc_opcodes[] = {
1935{ "attn", X(0,256), X_MASK, POWER4, { 0 } }, 3049{"attn", X(0,256), X_MASK, POWER4|PPCA2, PPC476|PPCVLE, {0}},
1936{ "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } }, 3050{"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
1937{ "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } }, 3051{"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
1938{ "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } }, 3052{"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
1939{ "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } }, 3053{"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
1940{ "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } }, 3054{"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
1941{ "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } }, 3055{"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
1942{ "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } }, 3056{"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
1943{ "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } }, 3057{"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
1944{ "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } }, 3058{"tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
1945{ "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } }, 3059{"tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
1946{ "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } }, 3060{"tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
1947{ "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } }, 3061{"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
1948{ "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } }, 3062{"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
1949{ "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } }, 3063{"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
1950{ "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } }, 3064{"tdui", OPTO(2,TOU), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
1951 3065{"tdi", OP(2), OP_MASK, PPC64, PPCVLE, {TO, RA, SI}},
1952{ "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } }, 3066
1953{ "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } }, 3067{"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
1954{ "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } }, 3068{"tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
1955{ "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } }, 3069{"twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
1956{ "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } }, 3070{"tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
1957{ "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } }, 3071{"tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
1958{ "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } }, 3072{"teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
1959{ "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } }, 3073{"twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
1960{ "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } }, 3074{"tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
1961{ "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } }, 3075{"twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
1962{ "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } }, 3076{"tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
1963{ "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } }, 3077{"twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
1964{ "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } }, 3078{"tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
1965{ "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } }, 3079{"twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
1966{ "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } }, 3080{"tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
1967{ "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } }, 3081{"twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
1968{ "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } }, 3082{"tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
1969{ "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } }, 3083{"twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
1970{ "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } }, 3084{"tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
1971{ "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } }, 3085{"twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
1972{ "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } }, 3086{"tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
1973{ "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } }, 3087{"twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
1974{ "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } }, 3088{"tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
1975{ "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } }, 3089{"twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
1976{ "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } }, 3090{"tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
1977{ "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } }, 3091{"twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
1978{ "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } }, 3092{"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
1979{ "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } }, 3093{"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
1980{ "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } }, 3094{"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
1981{ "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } }, 3095{"twui", OPTO(3,TOU), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
1982 3096{"tui", OPTO(3,TOU), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
1983{ "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3097{"twi", OP(3), OP_MASK, PPCCOM, PPCVLE, {TO, RA, SI}},
1984{ "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3098{"ti", OP(3), OP_MASK, PWRCOM, PPCVLE, {TO, RA, SI}},
1985{ "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3099
1986{ "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3100{"ps_cmpu0", X (4, 0), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
1987{ "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3101{"vaddubm", VX (4, 0), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1988{ "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3102{"vmul10cuq", VX (4, 1), VXVB_MASK, PPCVEC3, 0, {VD, VA}},
1989{ "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3103{"vmaxub", VX (4, 2), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1990{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3104{"vrlb", VX (4, 4), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1991{ "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3105{"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
1992{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3106{"vcmpneb", VXR(4, 7,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
1993{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3107{"vmuloub", VX (4, 8), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1994{ "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3108{"vaddfp", VX (4, 10), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1995{ "macchwu", XO(4,140,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3109{"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
1996{ "macchwu.", XO(4,140,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3110{"vmrghb", VX (4, 12), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1997{ "macchwuo", XO(4,140,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3111{"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
1998{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3112{"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
1999{ "machhw", XO(4,44,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3113{"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, 0, {RT, RA, RB}},
2000{ "machhw.", XO(4,44,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3114{"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, 0, {RT, RA, RB}},
2001{ "machhwo", XO(4,44,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3115{"ps_sum0", A (4, 10,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
2002{ "machhwo.", XO(4,44,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3116{"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
2003{ "machhws", XO(4,108,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3117{"ps_sum1", A (4, 11,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
2004{ "machhws.", XO(4,108,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3118{"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
2005{ "machhwso", XO(4,108,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3119{"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
2006{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3120{"machhwu", XO (4, 12,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2007{ "machhwsu", XO(4,76,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3121{"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
2008{ "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3122{"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2009{ "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3123{"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
2010{ "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3124{"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
2011{ "machhwu", XO(4,12,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3125{"ps_madds0", A (4, 14,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
2012{ "machhwu.", XO(4,12,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3126{"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
2013{ "machhwuo", XO(4,12,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3127{"ps_madds1", A (4, 15,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
2014{ "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3128{"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
2015{ "maclhw", XO(4,428,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3129{"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
2016{ "maclhw.", XO(4,428,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3130{"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
2017{ "maclhwo", XO(4,428,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3131{"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
2018{ "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3132{"vmsumudm", VXA(4, 35), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
2019{ "maclhws", XO(4,492,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3133{"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
2020{ "maclhws.", XO(4,492,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3134{"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
2021{ "maclhwso", XO(4,492,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3135{"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
2022{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3136{"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
2023{ "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3137{"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
2024{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3138{"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
2025{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3139{"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
2026{ "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3140{"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
2027{ "maclhwu", XO(4,396,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3141{"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
2028{ "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3142{"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
2029{ "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3143{"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
2030{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3144{"vsel", VXA(4, 42), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
2031{ "mulchw", XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 3145{"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
2032{ "mulchw.", XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 3146{"vperm", VXA(4, 43), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
2033{ "mulchwu", XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 3147{"vsldoi", VXA(4, 44), VXASHB_MASK, PPCVEC, 0, {VD, VA, VB, SHB}},
2034{ "mulchwu.", XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 3148{"vpermxor", VXA(4, 45), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
2035{ "mulhhw", XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 3149{"ps_sel", A (4, 23,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
2036{ "mulhhw.", XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 3150{"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}},
2037{ "mulhhwu", XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 3151{"ps_sel.", A (4, 23,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
2038{ "mulhhwu.", XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 3152{"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}},
2039{ "mullhw", XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 3153{"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
2040{ "mullhw.", XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 3154{"maddhd", VXA(4, 48), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
2041{ "mullhwu", XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 3155{"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
2042{ "mullhwu.", XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 3156{"maddhdu", VXA(4, 49), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
2043{ "nmacchw", XO(4,174,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3157{"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
2044{ "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3158{"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
2045{ "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3159{"maddld", VXA(4, 51), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
2046{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3160{"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
2047{ "nmacchws", XO(4,238,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3161{"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
2048{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3162{"ps_msub", A (4, 28,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
2049{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3163{"ps_msub.", A (4, 28,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
2050{ "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3164{"ps_madd", A (4, 29,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
2051{ "nmachhw", XO(4,46,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3165{"ps_madd.", A (4, 29,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
2052{ "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3166{"vpermr", VXA(4, 59), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
2053{ "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3167{"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
2054{ "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3168{"vaddeuqm", VXA(4, 60), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
2055{ "nmachhws", XO(4,110,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3169{"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
2056{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3170{"vaddecuq", VXA(4, 61), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
2057{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3171{"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
2058{ "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3172{"vsubeuqm", VXA(4, 62), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
2059{ "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3173{"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
2060{ "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3174{"vsubecuq", VXA(4, 63), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
2061{ "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3175{"ps_cmpo0", X (4, 32), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
2062{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3176{"vadduhm", VX (4, 64), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2063{ "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3177{"vmul10ecuq", VX (4, 65), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
2064{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3178{"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2065{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3179{"vrlh", VX (4, 68), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2066{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 3180{"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2067{ "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } }, 3181{"vcmpneh", VXR(4, 71,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
2068{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } }, 3182{"vmulouh", VX (4, 72), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2069 3183{"vsubfp", VX (4, 74), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2070 /* Double-precision opcodes. */ 3184{"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
2071 /* Some of these conflict with AltiVec, so move them before, since 3185{"vmrghh", VX (4, 76), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2072 PPCVEC includes the PPC_OPCODE_PPC set. */ 3186{"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
2073{ "efscfd", VX(4, 719), VX_MASK, PPCEFS, { RS, RB } }, 3187{"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2074{ "efdabs", VX(4, 740), VX_MASK, PPCEFS, { RS, RA } }, 3188{"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
2075{ "efdnabs", VX(4, 741), VX_MASK, PPCEFS, { RS, RA } }, 3189{"mulhhw", XRC(4, 40,0), X_MASK, MULHW, 0, {RT, RA, RB}},
2076{ "efdneg", VX(4, 742), VX_MASK, PPCEFS, { RS, RA } }, 3190{"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
2077{ "efdadd", VX(4, 736), VX_MASK, PPCEFS, { RS, RA, RB } }, 3191{"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, 0, {RT, RA, RB}},
2078{ "efdsub", VX(4, 737), VX_MASK, PPCEFS, { RS, RA, RB } }, 3192{"machhw", XO (4, 44,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2079{ "efdmul", VX(4, 744), VX_MASK, PPCEFS, { RS, RA, RB } }, 3193{"machhw.", XO (4, 44,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2080{ "efddiv", VX(4, 745), VX_MASK, PPCEFS, { RS, RA, RB } }, 3194{"nmachhw", XO (4, 46,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2081{ "efdcmpgt", VX(4, 748), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 3195{"nmachhw.", XO (4, 46,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2082{ "efdcmplt", VX(4, 749), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 3196{"ps_cmpu1", X (4, 64), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
2083{ "efdcmpeq", VX(4, 750), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 3197{"vadduwm", VX (4, 128), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2084{ "efdtstgt", VX(4, 764), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 3198{"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2085{ "efdtstlt", VX(4, 765), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 3199{"vrlw", VX (4, 132), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2086{ "efdtsteq", VX(4, 766), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 3200{"vrlwmi", VX (4, 133), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
2087{ "efdcfsi", VX(4, 753), VX_MASK, PPCEFS, { RS, RB } }, 3201{"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2088{ "efdcfsid", VX(4, 739), VX_MASK, PPCEFS, { RS, RB } }, 3202{"vcmpnew", VXR(4, 135,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
2089{ "efdcfui", VX(4, 752), VX_MASK, PPCEFS, { RS, RB } }, 3203{"vmulouw", VX (4, 136), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2090{ "efdcfuid", VX(4, 738), VX_MASK, PPCEFS, { RS, RB } }, 3204{"vmuluwm", VX (4, 137), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2091{ "efdcfsf", VX(4, 755), VX_MASK, PPCEFS, { RS, RB } }, 3205{"vmrghw", VX (4, 140), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2092{ "efdcfuf", VX(4, 754), VX_MASK, PPCEFS, { RS, RB } }, 3206{"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2093{ "efdctsi", VX(4, 757), VX_MASK, PPCEFS, { RS, RB } }, 3207{"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
2094{ "efdctsidz",VX(4, 747), VX_MASK, PPCEFS, { RS, RB } }, 3208{"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
2095{ "efdctsiz", VX(4, 762), VX_MASK, PPCEFS, { RS, RB } }, 3209{"machhwsu", XO (4, 76,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2096{ "efdctui", VX(4, 756), VX_MASK, PPCEFS, { RS, RB } }, 3210{"machhwsu.", XO (4, 76,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2097{ "efdctuidz",VX(4, 746), VX_MASK, PPCEFS, { RS, RB } }, 3211{"ps_cmpo1", X (4, 96), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
2098{ "efdctuiz", VX(4, 760), VX_MASK, PPCEFS, { RS, RB } }, 3212{"vaddudm", VX (4, 192), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2099{ "efdctsf", VX(4, 759), VX_MASK, PPCEFS, { RS, RB } }, 3213{"vmaxud", VX (4, 194), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2100{ "efdctuf", VX(4, 758), VX_MASK, PPCEFS, { RS, RB } }, 3214{"vrld", VX (4, 196), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2101{ "efdcfs", VX(4, 751), VX_MASK, PPCEFS, { RS, RB } }, 3215{"vrldmi", VX (4, 197), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
2102 /* End of double-precision opcodes. */ 3216{"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2103 3217{"vcmpequd", VXR(4, 199,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
2104{ "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } }, 3218{"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2105{ "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } }, 3219{"machhws", XO (4, 108,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2106{ "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } }, 3220{"machhws.", XO (4, 108,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2107{ "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } }, 3221{"nmachhws", XO (4, 110,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2108{ "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } }, 3222{"nmachhws.", XO (4, 110,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2109{ "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } }, 3223{"vadduqm", VX (4, 256), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2110{ "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } }, 3224{"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2111{ "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } }, 3225{"vslb", VX (4, 260), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2112{ "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } }, 3226{"vcmpnezb", VXR(4, 263,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
2113{ "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } }, 3227{"vmulosb", VX (4, 264), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2114{ "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } }, 3228{"vrefp", VX (4, 266), VXVA_MASK, PPCVEC, 0, {VD, VB}},
2115{ "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } }, 3229{"vmrglb", VX (4, 268), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2116{ "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } }, 3230{"vpkshus", VX (4, 270), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2117{ "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } }, 3231{"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
2118{ "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } }, 3232{"mulchwu", XRC(4, 136,0), X_MASK, MULHW, 0, {RT, RA, RB}},
2119{ "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } }, 3233{"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
2120{ "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } }, 3234{"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, 0, {RT, RA, RB}},
2121{ "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } }, 3235{"macchwu", XO (4, 140,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2122{ "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } }, 3236{"macchwu.", XO (4, 140,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2123{ "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } }, 3237{"vaddcuq", VX (4, 320), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2124{ "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } }, 3238{"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2125{ "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3239{"vslh", VX (4, 324), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2126{ "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3240{"vcmpnezh", VXR(4, 327,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
2127{ "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3241{"vmulosh", VX (4, 328), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2128{ "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3242{"vrsqrtefp", VX (4, 330), VXVA_MASK, PPCVEC, 0, {VD, VB}},
2129{ "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3243{"vmrglh", VX (4, 332), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2130{ "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3244{"vpkswus", VX (4, 334), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2131{ "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3245{"mulchw", XRC(4, 168,0), X_MASK, MULHW, 0, {RT, RA, RB}},
2132{ "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3246{"mulchw.", XRC(4, 168,1), X_MASK, MULHW, 0, {RT, RA, RB}},
2133{ "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3247{"macchw", XO (4, 172,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2134{ "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3248{"macchw.", XO (4, 172,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2135{ "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3249{"nmacchw", XO (4, 174,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2136{ "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3250{"nmacchw.", XO (4, 174,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2137{ "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3251{"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2138{ "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3252{"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2139{ "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3253{"vslw", VX (4, 388), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2140{ "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3254{"vrlwnm", VX (4, 389), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
2141{ "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3255{"vcmpnezw", VXR(4, 391,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
2142{ "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3256{"vmulosw", VX (4, 392), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2143{ "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3257{"vexptefp", VX (4, 394), VXVA_MASK, PPCVEC, 0, {VD, VB}},
2144{ "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3258{"vmrglw", VX (4, 396), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2145{ "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3259{"vpkshss", VX (4, 398), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2146{ "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3260{"macchwsu", XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2147{ "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3261{"macchwsu.", XO (4, 204,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2148{ "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3262{"vmaxsd", VX (4, 450), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2149{ "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3263{"vsl", VX (4, 452), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2150{ "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 3264{"vrldnm", VX (4, 453), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
2151{ "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } }, 3265{"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2152{ "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } }, 3266{"vlogefp", VX (4, 458), VXVA_MASK, PPCVEC, 0, {VD, VB}},
2153{ "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } }, 3267{"vpkswss", VX (4, 462), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2154{ "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } }, 3268{"macchws", XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2155{ "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } }, 3269{"macchws.", XO (4, 236,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2156{ "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } }, 3270{"nmacchws", XO (4, 238,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2157{ "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } }, 3271{"nmacchws.", XO (4, 238,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2158{ "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } }, 3272{"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2159{ "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } }, 3273{"vaddubs", VX (4, 512), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2160{ "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } }, 3274{"vmul10uq", VX (4, 513), VXVB_MASK, PPCVEC3, 0, {VD, VA}},
2161{ "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } }, 3275{"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
2162{ "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } }, 3276{"vminub", VX (4, 514), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2163{ "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 3277{"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2164{ "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 3278{"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}},
2165{ "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } }, 3279{"vsrb", VX (4, 516), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2166{ "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } }, 3280{"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}},
2167{ "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } }, 3281{"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
2168{ "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } }, 3282{"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2169{ "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } }, 3283{"evabs", VX (4, 520), VX_MASK, PPCSPE, 0, {RS, RA}},
2170{ "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } }, 3284{"vmuleub", VX (4, 520), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2171{ "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } }, 3285{"evneg", VX (4, 521), VX_MASK, PPCSPE, 0, {RS, RA}},
2172{ "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 3286{"evextsb", VX (4, 522), VX_MASK, PPCSPE, 0, {RS, RA}},
2173{ "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } }, 3287{"vrfin", VX (4, 522), VXVA_MASK, PPCVEC, 0, {VD, VB}},
2174{ "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } }, 3288{"evextsh", VX (4, 523), VX_MASK, PPCSPE, 0, {RS, RA}},
2175{ "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } }, 3289{"evrndw", VX (4, 524), VX_MASK, PPCSPE, 0, {RS, RA}},
2176{ "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } }, 3290{"vspltb", VX (4, 524), VXUIMM4_MASK, PPCVEC, 0, {VD, VB, UIMM4}},
2177{ "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } }, 3291{"vextractub", VX (4, 525), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
2178{ "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } }, 3292{"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, 0, {RS, RA}},
2179{ "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 3293{"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, 0, {RS, RA}},
2180{ "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 3294{"vupkhsb", VX (4, 526), VXVA_MASK, PPCVEC, 0, {VD, VB}},
2181{ "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 3295{"brinc", VX (4, 527), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2182{ "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 3296{"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
2183{ "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 3297{"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
2184{ "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 3298{"evand", VX (4, 529), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2185{ "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } }, 3299{"evandc", VX (4, 530), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2186{ "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } }, 3300{"evxor", VX (4, 534), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2187{ "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } }, 3301{"evmr", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},
2188{ "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } }, 3302{"evor", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2189{ "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } }, 3303{"evnor", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2190{ "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } }, 3304{"evnot", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},
2191{ "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } }, 3305{"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
2192{ "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } }, 3306{"eveqv", VX (4, 537), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2193{ "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } }, 3307{"evorc", VX (4, 539), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2194{ "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } }, 3308{"evnand", VX (4, 542), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2195{ "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } }, 3309{"evsrwu", VX (4, 544), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2196{ "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 3310{"evsrws", VX (4, 545), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2197{ "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } }, 3311{"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
2198{ "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } }, 3312{"evsrwis", VX (4, 547), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
2199{ "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } }, 3313{"evslw", VX (4, 548), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2200{ "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } }, 3314{"evslwi", VX (4, 550), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
2201{ "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } }, 3315{"evrlw", VX (4, 552), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2202{ "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } }, 3316{"evsplati", VX (4, 553), VX_MASK, PPCSPE, 0, {RS, SIMM}},
2203{ "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } }, 3317{"evrlwi", VX (4, 554), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
2204{ "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } }, 3318{"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, 0, {RS, SIMM}},
2205{ "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } }, 3319{"evmergehi", VX (4, 556), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2206{ "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } }, 3320{"evmergelo", VX (4, 557), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2207{ "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } }, 3321{"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2208{ "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } }, 3322{"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2209{ "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } }, 3323{"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
2210{ "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } }, 3324{"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
2211{ "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } }, 3325{"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
2212{ "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } }, 3326{"evcmplts", VX (4, 563), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
2213{ "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } }, 3327{"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
2214{ "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } }, 3328{"cget", APU(4, 284,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
2215{ "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 3329{"vadduhs", VX (4, 576), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2216{ "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } }, 3330{"vmul10euq", VX (4, 577), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
2217{ "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } }, 3331{"vminuh", VX (4, 578), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2218{ "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } }, 3332{"vsrh", VX (4, 580), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2219{ "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } }, 3333{"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2220{ "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } }, 3334{"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2221{ "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } }, 3335{"vrfiz", VX (4, 586), VXVA_MASK, PPCVEC, 0, {VD, VB}},
2222{ "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } }, 3336{"vsplth", VX (4, 588), VXUIMM3_MASK, PPCVEC, 0, {VD, VB, UIMM3}},
2223{ "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } }, 3337{"vextractuh", VX (4, 589), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
2224{ "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } }, 3338{"vupkhsh", VX (4, 590), VXVA_MASK, PPCVEC, 0, {VD, VB}},
2225{ "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } }, 3339{"nget", APU(4, 300,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
2226{ "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } }, 3340{"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, 0, {RS, RA, RB, CRFS}},
2227{ "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } }, 3341{"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
2228{ "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } }, 3342{"evfsadd", VX (4, 640), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2229{ "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } }, 3343{"vadduws", VX (4, 640), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2230{ "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } }, 3344{"evfssub", VX (4, 641), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2231{ "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } }, 3345{"vminuw", VX (4, 642), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2232{ "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } }, 3346{"evfsabs", VX (4, 644), VX_MASK, PPCSPE, 0, {RS, RA}},
2233{ "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } }, 3347{"vsrw", VX (4, 644), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2234{ "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } }, 3348{"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, 0, {RS, RA}},
2235{ "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } }, 3349{"evfsneg", VX (4, 646), VX_MASK, PPCSPE, 0, {RS, RA}},
2236{ "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } }, 3350{"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2237{ "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } }, 3351{"vmuleuw", VX (4, 648), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2238{ "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } }, 3352{"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2239{ "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } }, 3353{"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2240{ "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } }, 3354{"vrfip", VX (4, 650), VXVA_MASK, PPCVEC, 0, {VD, VB}},
2241{ "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } }, 3355{"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
2242{ "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } }, 3356{"vspltw", VX (4, 652), VXUIMM2_MASK, PPCVEC, 0, {VD, VB, UIMM2}},
2243{ "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } }, 3357{"vextractuw", VX (4, 653), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
2244{ "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } }, 3358{"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
2245{ "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } }, 3359{"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
2246{ "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } }, 3360{"vupklsb", VX (4, 654), VXVA_MASK, PPCVEC, 0, {VD, VB}},
2247{ "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } }, 3361{"evfscfui", VX (4, 656), VX_MASK, PPCSPE, 0, {RS, RB}},
2248{ "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } }, 3362{"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, 0, {RS, RB}},
2249{ "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } }, 3363{"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, 0, {RS, RB}},
2250{ "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } }, 3364{"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, 0, {RS, RB}},
2251{ "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } }, 3365{"evfsctui", VX (4, 660), VX_MASK, PPCSPE, 0, {RS, RB}},
2252{ "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } }, 3366{"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, 0, {RS, RB}},
2253{ "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } }, 3367{"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, 0, {RS, RB}},
2254{ "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } }, 3368{"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, 0, {RS, RB}},
2255{ "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } }, 3369{"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, 0, {RS, RB}},
2256{ "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } }, 3370{"put", APU(4, 332,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
2257{ "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } }, 3371{"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, 0, {RS, RB}},
2258{ "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } }, 3372{"evfststgt", VX (4, 668), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
2259 3373{"evfststlt", VX (4, 669), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
2260{ "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } }, 3374{"evfststeq", VX (4, 670), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
2261{ "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } }, 3375{"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
2262{ "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } }, 3376{"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
2263{ "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } }, 3377{"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
2264{ "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } }, 3378{"vminud", VX (4, 706), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2265{ "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } }, 3379{"efsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}},
2266{ "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } }, 3380{"vsr", VX (4, 708), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2267{ "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } }, 3381{"efsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}},
2268{ "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } }, 3382{"efsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}},
2269{ "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } }, 3383{"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2270{ "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } }, 3384{"vcmpgtud", VXR(4, 711,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
2271{ "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } }, 3385{"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
2272{ "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } }, 3386{"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
2273 3387{"vrfim", VX (4, 714), VXVA_MASK, PPCVEC, 0, {VD, VB}},
2274{ "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } }, 3388{"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
2275 3389{"vextractd", VX (4, 717), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
2276{ "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } }, 3390{"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
2277{ "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } }, 3391{"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
2278{ "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } }, 3392{"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC, 0, {VD, VB}},
2279{ "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } }, 3393{"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}},
2280{ "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } }, 3394{"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}},
2281{ "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } }, 3395{"efscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}},
2282{ "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } }, 3396{"efscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}},
2283{ "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } }, 3397{"efscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}},
2284{ "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } }, 3398{"efsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}},
2285{ "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } }, 3399{"efsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}},
2286 3400{"efsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}},
2287{ "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } }, 3401{"efsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}},
2288{ "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } }, 3402{"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}},
2289{ "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } }, 3403{"nput", APU(4, 364,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
2290{ "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } }, 3404{"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}},
2291{ "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } }, 3405{"efststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
2292{ "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } }, 3406{"efststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
2293{ "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } }, 3407{"efststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
2294{ "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } }, 3408{"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
2295{ "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } }, 3409{"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
2296{ "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } }, 3410{"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, 0, {RS, RB}},
2297{ "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } }, 3411{"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, 0, {RS, RB}},
2298{ "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } }, 3412{"efdabs", VX (4, 740), VX_MASK, PPCEFS, 0, {RS, RA}},
2299{ "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } }, 3413{"efdnabs", VX (4, 741), VX_MASK, PPCEFS, 0, {RS, RA}},
2300{ "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } }, 3414{"efdneg", VX (4, 742), VX_MASK, PPCEFS, 0, {RS, RA}},
2301 3415{"efdmul", VX (4, 744), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
2302{ "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 3416{"efddiv", VX (4, 745), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
2303{ "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 3417{"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, 0, {RS, RB}},
2304{ "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 3418{"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, 0, {RS, RB}},
2305{ "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 3419{"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
2306{ "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 3420{"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
2307{ "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } }, 3421{"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
2308 3422{"efdcfs", VX (4, 751), VX_MASK, PPCEFS, 0, {RS, RB}},
2309{ "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, 3423{"efdcfui", VX (4, 752), VX_MASK, PPCEFS, 0, {RS, RB}},
2310{ "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } }, 3424{"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, 0, {RS, RB}},
2311{ "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, 3425{"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, 0, {RS, RB}},
2312{ "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } }, 3426{"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, 0, {RS, RB}},
2313{ "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, 3427{"efdctui", VX (4, 756), VX_MASK, PPCEFS, 0, {RS, RB}},
2314{ "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } }, 3428{"efdctsi", VX (4, 757), VX_MASK, PPCEFS, 0, {RS, RB}},
2315{ "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 3429{"efdctuf", VX (4, 758), VX_MASK, PPCEFS, 0, {RS, RB}},
2316{ "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } }, 3430{"efdctsf", VX (4, 759), VX_MASK, PPCEFS, 0, {RS, RB}},
2317{ "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 3431{"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, 0, {RS, RB}},
2318{ "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } }, 3432{"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
2319{ "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 3433{"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, 0, {RS, RB}},
2320{ "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } }, 3434{"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
2321{ "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 3435{"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
2322{ "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } }, 3436{"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
2323{ "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 3437{"evlddx", VX (4, 768), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2324{ "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } }, 3438{"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2325{ "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } }, 3439{"evldd", VX (4, 769), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
2326{ "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } }, 3440{"evldwx", VX (4, 770), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2327{ "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } }, 3441{"vminsb", VX (4, 770), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2328{ "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } }, 3442{"evldw", VX (4, 771), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
2329{ "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } }, 3443{"evldhx", VX (4, 772), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2330{ "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } }, 3444{"vsrab", VX (4, 772), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2331 3445{"evldh", VX (4, 773), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
2332{ "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, 3446{"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2333{ "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } }, 3447{"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2334{ "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, 3448{"vmulesb", VX (4, 776), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2335{ "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } }, 3449{"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
2336{ "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, 3450{"vcfux", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
2337{ "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } }, 3451{"vcuxwfp", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
2338{ "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 3452{"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2339{ "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } }, 3453{"vspltisb", VX (4, 780), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
2340{ "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 3454{"vinsertb", VX (4, 781), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
2341{ "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } }, 3455{"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
2342{ "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 3456{"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2343{ "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } }, 3457{"vpkpx", VX (4, 782), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2344{ "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 3458{"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
2345{ "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } }, 3459{"mullhwu", XRC(4, 392,0), X_MASK, MULHW, 0, {RT, RA, RB}},
2346 3460{"evlwhex", VX (4, 784), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2347{ "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } }, 3461{"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, 0, {RT, RA, RB}},
2348{ "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } }, 3462{"evlwhe", VX (4, 785), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
2349{ "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } }, 3463{"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2350{ "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } }, 3464{"evlwhou", VX (4, 789), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
2351{ "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } }, 3465{"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2352{ "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } }, 3466{"evlwhos", VX (4, 791), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
2353{ "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } }, 3467{"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
2354{ "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 3468{"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2355{ "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 3469{"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
2356{ "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 3470{"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
2357{ "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 3471{"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2358{ "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 3472{"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
2359{ "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 3473{"evstddx", VX (4, 800), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2360{ "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } }, 3474{"evstdd", VX (4, 801), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
2361{ "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } }, 3475{"evstdwx", VX (4, 802), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2362{ "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } }, 3476{"evstdw", VX (4, 803), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
2363{ "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } }, 3477{"evstdhx", VX (4, 804), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2364{ "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } }, 3478{"evstdh", VX (4, 805), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
2365{ "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } }, 3479{"evstwhex", VX (4, 816), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2366{ "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } }, 3480{"evstwhe", VX (4, 817), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
2367{ "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } }, 3481{"evstwhox", VX (4, 820), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2368{ "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } }, 3482{"evstwho", VX (4, 821), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
2369{ "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } }, 3483{"evstwwex", VX (4, 824), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2370 3484{"evstwwe", VX (4, 825), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
2371{ "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } }, 3485{"evstwwox", VX (4, 828), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2372{ "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } }, 3486{"evstwwo", VX (4, 829), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
2373{ "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } }, 3487{"vaddshs", VX (4, 832), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2374{ "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } }, 3488{"bcdcpsgn.", VX (4, 833), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
2375{ "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } }, 3489{"vminsh", VX (4, 834), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2376{ "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } }, 3490{"vsrah", VX (4, 836), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2377{ "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } }, 3491{"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2378{ "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 3492{"vmulesh", VX (4, 840), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2379{ "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 3493{"vcfsx", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
2380{ "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 3494{"vcsxwfp", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
2381{ "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 3495{"vspltish", VX (4, 844), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
2382{ "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 3496{"vinserth", VX (4, 845), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
2383{ "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 3497{"vupkhpx", VX (4, 846), VXVA_MASK, PPCVEC, 0, {VD, VB}},
2384{ "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } }, 3498{"mullhw", XRC(4, 424,0), X_MASK, MULHW, 0, {RT, RA, RB}},
2385{ "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } }, 3499{"mullhw.", XRC(4, 424,1), X_MASK, MULHW, 0, {RT, RA, RB}},
2386{ "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } }, 3500{"maclhw", XO (4, 428,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
2387{ "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } }, 3501{"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
2388{ "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } }, 3502{"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
2389{ "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } }, 3503{"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
2390{ "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } }, 3504{"vaddsws", VX (4, 896), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2391{ "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } }, 3505{"vminsw", VX (4, 898), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2392{ "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } }, 3506{"vsraw", VX (4, 900), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2393{ "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } }, 3507{"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2394 3508{"vmulesw", VX (4, 904), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2395{ "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } }, 3509{"vctuxs", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
2396{ "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } }, 3510{"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
2397{ "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } }, 3511{"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
2398{ "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } }, 3512{"vinsertw", VX (4, 909), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
2399{ "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } }, 3513{"maclhwsu", XO (4, 460,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2400{ "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } }, 3514{"maclhwsu.", XO (4, 460,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2401{ "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } }, 3515{"vminsd", VX (4, 962), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2402{ "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } }, 3516{"vsrad", VX (4, 964), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2403{ "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } }, 3517{"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2404{ "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } }, 3518{"vcmpgtsd", VXR(4, 967,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
2405{ "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } }, 3519{"vctsxs", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
2406{ "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } }, 3520{"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
2407{ "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } }, 3521{"vinsertd", VX (4, 973), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
2408{ "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } }, 3522{"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC, 0, {VD, VB}},
2409{ "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } }, 3523{"maclhws", XO (4, 492,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2410{ "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } }, 3524{"maclhws.", XO (4, 492,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2411 3525{"nmaclhws", XO (4, 494,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2412{ "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } }, 3526{"nmaclhws.", XO (4, 494,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2413{ "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } }, 3527{"vsububm", VX (4,1024), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2414{ "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } }, 3528{"bcdadd.", VX (4,1025), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
2415{ "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } }, 3529{"vavgub", VX (4,1026), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2416{ "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } }, 3530{"vabsdub", VX (4,1027), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2417{ "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } }, 3531{"evmhessf", VX (4,1027), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2418{ "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } }, 3532{"vand", VX (4,1028), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2419{ "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } }, 3533{"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2420{ "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } }, 3534{"vcmpneb.", VXR(4, 7,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
2421{ "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } }, 3535{"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2422{ "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } }, 3536{"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2423{ "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } }, 3537{"evmhossf", VX (4,1031), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2424 3538{"vpmsumb", VX (4,1032), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2425{ "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } }, 3539{"evmheumi", VX (4,1032), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2426{ "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } }, 3540{"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2427{ "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } }, 3541{"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2428{ "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } }, 3542{"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2429{ "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } }, 3543{"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2430{ "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } }, 3544{"vslo", VX (4,1036), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2431{ "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } }, 3545{"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2432{ "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } }, 3546{"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2433{ "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } }, 3547{"machhwuo", XO (4, 12,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2434{ "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } }, 3548{"machhwuo.", XO (4, 12,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2435{ "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } }, 3549{"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
2436{ "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } }, 3550{"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
2437 3551{"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2438{ "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } }, 3552{"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2439{ "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } }, 3553{"evmheumia", VX (4,1064), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2440{ "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } }, 3554{"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2441{ "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } }, 3555{"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2442{ "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } }, 3556{"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2443{ "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } }, 3557{"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2444 3558{"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2445{ "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } }, 3559{"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2446{ "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } }, 3560{"bcdsub.", VX (4,1089), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
2447{ "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } }, 3561{"vavguh", VX (4,1090), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2448{ "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } }, 3562{"vabsduh", VX (4,1091), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2449{ "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } }, 3563{"vandc", VX (4,1092), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2450{ "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } }, 3564{"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2451 3565{"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2452{ "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } }, 3566{"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2453{ "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } }, 3567{"vcmpneh.", VXR(4, 71,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
2454{ "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } }, 3568{"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2455{ "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } }, 3569{"vpmsumh", VX (4,1096), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2456{ "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } }, 3570{"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2457{ "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } }, 3571{"vminfp", VX (4,1098), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2458{ "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } }, 3572{"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2459{ "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } }, 3573{"vsro", VX (4,1100), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2460 3574{"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2461{ "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } }, 3575{"vpkudum", VX (4,1102), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2462{ "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } }, 3576{"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2463 3577{"evmwssf", VX (4,1107), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2464{ "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } }, 3578{"machhwo", XO (4, 44,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2465{ "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } }, 3579{"evmwumi", VX (4,1112), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2466{ "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } }, 3580{"machhwo.", XO (4, 44,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2467{ "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } }, 3581{"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2468 3582{"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2469{ "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } }, 3583{"nmachhwo", XO (4, 46,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2470{ "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } }, 3584{"nmachhwo.", XO (4, 46,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2471{ "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } }, 3585{"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
2472{ "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } }, 3586{"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
2473 3587{"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2474{ "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } }, 3588{"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2475{ "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } }, 3589{"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2476{ "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } }, 3590{"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2477{ "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } }, 3591{"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2478{ "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } }, 3592{"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2479{ "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } }, 3593{"evmwumia", VX (4,1144), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2480{ "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } }, 3594{"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2481{ "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } }, 3595{"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2482 3596{"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2483{ "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } }, 3597{"bcdus.", VX (4,1153), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
2484{ "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } }, 3598{"vavguw", VX (4,1154), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2485{ "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } }, 3599{"vabsduw", VX (4,1155), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2486{ "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } }, 3600{"vmr", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VBA}},
2487 3601{"vor", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2488{ "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } }, 3602{"vcmpnew.", VXR(4, 135,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
2489{ "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } }, 3603{"vpmsumw", VX (4,1160), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2490{ "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } }, 3604{"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2491{ "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } }, 3605{"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2492 3606{"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2493{ "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } }, 3607{"machhwsuo", XO (4, 76,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2494{ "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } }, 3608{"machhwsuo.", XO (4, 76,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2495{ "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } }, 3609{"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
2496{ "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } }, 3610{"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
2497 3611{"vsubudm", VX (4,1216), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2498{ "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } }, 3612{"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, 0, {RS, RA}},
2499{ "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } }, 3613{"bcds.", VX (4,1217), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
2500{ "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } }, 3614{"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, 0, {RS, RA}},
2501{ "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } }, 3615{"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, 0, {RS, RA}},
2502 3616{"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, 0, {RS, RA}},
2503{ "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } }, 3617{"evmra", VX (4,1220), VX_MASK, PPCSPE, 0, {RS, RA}},
2504 3618{"vxor", VX (4,1220), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2505{ "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } }, 3619{"evdivws", VX (4,1222), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2506{ "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } }, 3620{"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2507 3621{"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2508{ "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } }, 3622{"vcmpequd.", VXR(4, 199,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
2509{ "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } }, 3623{"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2510 3624{"evdivwu", VX (4,1223), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2511{ "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } }, 3625{"vpmsumd", VX (4,1224), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2512{ "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } }, 3626{"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, 0, {RS, RA}},
2513 3627{"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, 0, {RS, RA}},
2514{ "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } }, 3628{"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, 0, {RS, RA}},
2515 3629{"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, 0, {RS, RA}},
2516{ "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } }, 3630{"vpkudus", VX (4,1230), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2517{ "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } }, 3631{"machhwso", XO (4, 108,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2518{ "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } }, 3632{"machhwso.", XO (4, 108,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2519{ "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } }, 3633{"nmachhwso", XO (4, 110,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2520 3634{"nmachhwso.", XO (4, 110,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2521{ "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } }, 3635{"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
2522{ "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } }, 3636{"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
2523{ "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } }, 3637{"vsubuqm", VX (4,1280), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2524{ "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } }, 3638{"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2525 3639{"bcdtrunc.", VX (4,1281), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
2526{ "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } }, 3640{"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2527{ "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } }, 3641{"vavgsb", VX (4,1282), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2528{ "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } }, 3642{"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2529{ "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } }, 3643{"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2530 3644{"vnot", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VBA}},
2531{ "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } }, 3645{"vnor", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2532{ "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } }, 3646{"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2533{ "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } }, 3647{"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2534 3648{"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2535{ "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } }, 3649{"vcmpnezb.", VXR(4, 263,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
2536{ "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } }, 3650{"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2537{ "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } }, 3651{"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2538 3652{"vcipher", VX (4,1288), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2539{ "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } }, 3653{"vcipherlast", VX (4,1289), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2540{ "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } }, 3654{"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2541{ "addi", OP(14), OP_MASK, PPCCOM, { RT, RA0, SI } }, 3655{"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2542{ "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA0 } }, 3656{"vgbbd", VX (4,1292), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
2543{ "subi", OP(14), OP_MASK, PPCCOM, { RT, RA0, NSI } }, 3657{"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2544{ "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA0 } }, 3658{"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2545 3659{"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2546{ "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } }, 3660{"macchwuo", XO (4, 140,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2547{ "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } }, 3661{"macchwuo.", XO (4, 140,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2548{ "addis", OP(15), OP_MASK, PPCCOM, { RT,RA0,SISIGNOPT } }, 3662{"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2549{ "cau", OP(15), OP_MASK, PWRCOM, { RT,RA0,SISIGNOPT } }, 3663{"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2550{ "subis", OP(15), OP_MASK, PPCCOM, { RT, RA0, NSI } }, 3664{"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2551 3665{"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2552{ "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } }, 3666{"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2553{ "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } }, 3667{"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2554{ "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } }, 3668{"vsubcuq", VX (4,1344), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2555{ "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } }, 3669{"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2556{ "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } }, 3670{"bcdutrunc.", VX (4,1345), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
2557{ "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } }, 3671{"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2558{ "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } }, 3672{"vavgsh", VX (4,1346), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2559{ "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } }, 3673{"vorc", VX (4,1348), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2560{ "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } }, 3674{"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2561{ "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } }, 3675{"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2562{ "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } }, 3676{"vcmpnezh.", VXR(4, 327,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
2563{ "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } }, 3677{"vncipher", VX (4,1352), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2564{ "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } }, 3678{"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2565{ "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } }, 3679{"vncipherlast",VX (4,1353), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2566{ "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } }, 3680{"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2567{ "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } }, 3681{"vbpermq", VX (4,1356), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2568{ "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } }, 3682{"vpksdus", VX (4,1358), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2569{ "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } }, 3683{"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2570{ "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } }, 3684{"macchwo", XO (4, 172,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2571{ "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } }, 3685{"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2572{ "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } }, 3686{"macchwo.", XO (4, 172,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2573{ "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } }, 3687{"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2574{ "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } }, 3688{"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2575{ "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } }, 3689{"nmacchwo", XO (4, 174,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2576{ "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } }, 3690{"nmacchwo.", XO (4, 174,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2577{ "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } }, 3691{"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2578{ "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } }, 3692{"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2579{ "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } }, 3693{"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2580{ "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3694{"bcdctsq.", VXVA(4,1409,0), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
2581{ "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3695{"bcdcfsq.", VXVA(4,1409,2), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
2582{ "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } }, 3696{"bcdctz.", VXVA(4,1409,4), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
2583{ "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3697{"bcdctn.", VXVA(4,1409,5), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
2584{ "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3698{"bcdcfz.", VXVA(4,1409,6), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
2585{ "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } }, 3699{"bcdcfn.", VXVA(4,1409,7), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
2586{ "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3700{"bcdsetsgn.", VXVA(4,1409,31), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
2587{ "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3701{"vavgsw", VX (4,1410), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2588{ "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 3702{"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2589{ "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3703{"vnand", VX (4,1412), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2590{ "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3704{"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2591{ "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 3705{"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2592{ "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3706{"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2593{ "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3707{"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2594{ "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } }, 3708{"vcmpnezw.", VXR(4, 391,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
2595{ "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3709{"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2596{ "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3710{"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2597{ "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } }, 3711{"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2598{ "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3712{"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2599{ "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3713{"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2600{ "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 3714{"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2601{ "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3715{"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2602{ "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3716{"macchwsuo", XO (4, 204,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2603{ "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 3717{"macchwsuo.", XO (4, 204,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2604{ "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3718{"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2605{ "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3719{"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2606{ "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } }, 3720{"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2607{ "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3721{"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2608{ "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3722{"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2609{ "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } }, 3723{"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2610{ "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3724{"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2611{ "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3725{"bcdsr.", VX (4,1473), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
2612{ "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 3726{"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2613{ "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3727{"vsld", VX (4,1476), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2614{ "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3728{"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2615{ "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 3729{"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2616{ "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3730{"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
2617{ "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3731{"vsbox", VX (4,1480), VXVB_MASK, PPCVEC2, 0, {VD, VA}},
2618{ "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } }, 3732{"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2619{ "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3733{"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2620{ "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3734{"vbpermd", VX (4,1484), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
2621{ "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } }, 3735{"vpksdss", VX (4,1486), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2622{ "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3736{"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2623{ "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3737{"macchwso", XO (4, 236,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2624{ "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 3738{"evmwumian", VX (4,1496), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2625{ "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3739{"macchwso.", XO (4, 236,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2626{ "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3740{"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2627{ "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 3741{"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
2628{ "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3742{"nmacchwso", XO (4, 238,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2629{ "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3743{"nmacchwso.", XO (4, 238,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2630{ "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } }, 3744{"vsububs", VX (4,1536), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2631{ "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3745{"vclzlsbb", VXVA(4,1538,0), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
2632{ "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3746{"vctzlsbb", VXVA(4,1538,1), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
2633{ "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } }, 3747{"vnegw", VXVA(4,1538,6), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
2634{ "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3748{"vnegd", VXVA(4,1538,7), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
2635{ "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3749{"vprtybw", VXVA(4,1538,8), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
2636{ "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } }, 3750{"vprtybd", VXVA(4,1538,9), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
2637{ "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3751{"vprtybq", VXVA(4,1538,10), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
2638{ "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3752{"vextsb2w", VXVA(4,1538,16), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
2639{ "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } }, 3753{"vextsh2w", VXVA(4,1538,17), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
2640{ "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3754{"vextsb2d", VXVA(4,1538,24), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
2641{ "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3755{"vextsh2d", VXVA(4,1538,25), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
2642{ "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } }, 3756{"vextsw2d", VXVA(4,1538,26), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
2643{ "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3757{"vctzb", VXVA(4,1538,28), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
2644{ "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3758{"vctzh", VXVA(4,1538,29), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
2645{ "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } }, 3759{"vctzw", VXVA(4,1538,30), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
2646{ "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3760{"vctzd", VXVA(4,1538,31), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
2647{ "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3761{"mfvscr", VX (4,1540), VXVAVB_MASK, PPCVEC, 0, {VD}},
2648{ "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 3762{"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2649{ "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3763{"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2650{ "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3764{"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2651{ "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 3765{"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2652{ "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3766{"vextublx", VX (4,1549), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
2653{ "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3767{"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2654{ "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } }, 3768{"mtvscr", VX (4,1604), VXVDVA_MASK, PPCVEC, 0, {VB}},
2655{ "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3769{"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2656{ "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3770{"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2657{ "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } }, 3771{"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2658{ "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3772{"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2659{ "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3773{"vextuhlx", VX (4,1613), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
2660{ "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 3774{"vupkhsw", VX (4,1614), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
2661{ "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3775{"vsubuws", VX (4,1664), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2662{ "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3776{"vshasigmaw", VX (4,1666), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
2663{ "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 3777{"veqv", VX (4,1668), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2664{ "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3778{"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2665{ "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3779{"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2666{ "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } }, 3780{"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2667{ "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3781{"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2668{ "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3782{"vmrgow", VX (4,1676), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2669{ "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } }, 3783{"vextuwlx", VX (4,1677), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
2670{ "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3784{"vshasigmad", VX (4,1730), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
2671{ "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3785{"vsrd", VX (4,1732), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2672{ "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 3786{"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2673{ "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3787{"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2674{ "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3788{"vcmpgtud.", VXR(4, 711,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
2675{ "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 3789{"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2676{ "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3790{"vupklsw", VX (4,1742), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
2677{ "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3791{"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2678{ "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } }, 3792{"vclzb", VX (4,1794), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
2679{ "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3793{"vpopcntb", VX (4,1795), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
2680{ "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3794{"vsrv", VX (4,1796), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
2681{ "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } }, 3795{"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2682{ "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3796{"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2683{ "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3797{"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2684{ "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 3798{"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2685{ "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3799{"vextubrx", VX (4,1805), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
2686{ "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3800{"maclhwuo", XO (4, 396,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2687{ "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 3801{"maclhwuo.", XO (4, 396,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2688{ "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3802{"vsubshs", VX (4,1856), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2689{ "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3803{"vclzh", VX (4,1858), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
2690{ "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } }, 3804{"vpopcnth", VX (4,1859), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
2691{ "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3805{"vslv", VX (4,1860), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
2692{ "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3806{"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2693{ "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } }, 3807{"vextuhrx", VX (4,1869), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
2694{ "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3808{"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2695{ "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3809{"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2696{ "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 3810{"maclhwo", XO (4, 428,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2697{ "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3811{"maclhwo.", XO (4, 428,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2698{ "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3812{"nmaclhwo", XO (4, 430,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2699{ "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 3813{"nmaclhwo.", XO (4, 430,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2700{ "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3814{"vsubsws", VX (4,1920), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2701{ "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3815{"vclzw", VX (4,1922), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
2702{ "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } }, 3816{"vpopcntw", VX (4,1923), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
2703{ "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3817{"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2704{ "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3818{"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2705{ "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } }, 3819{"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2706{ "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3820{"vsumsws", VX (4,1928), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
2707{ "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3821{"vmrgew", VX (4,1932), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
2708{ "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 3822{"vextuwrx", VX (4,1933), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
2709{ "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3823{"maclhwsuo", XO (4, 460,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2710{ "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3824{"maclhwsuo.", XO (4, 460,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2711{ "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 3825{"vclzd", VX (4,1986), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
2712{ "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3826{"vpopcntd", VX (4,1987), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
2713{ "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3827{"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
2714{ "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } }, 3828{"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2715{ "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 3829{"vcmpgtsd.", VXR(4, 967,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
2716{ "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 3830{"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
2717{ "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } }, 3831{"maclhwso", XO (4, 492,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2718{ "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3832{"maclhwso.", XO (4, 492,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2719{ "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3833{"nmaclhwso", XO (4, 494,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
2720{ "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } }, 3834{"nmaclhwso.", XO (4, 494,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
2721{ "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 3835{"dcbz_l", X (4,1014), XRT_MASK, PPCPS, 0, {RA, RB}},
2722{ "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 3836
2723{ "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } }, 3837{"mulli", OP(7), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
2724{ "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, 3838{"muli", OP(7), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
2725{ "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, 3839
2726{ "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, 3840{"subfic", OP(8), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
2727{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, 3841{"sfi", OP(8), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
2728{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, 3842
2729{ "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, 3843{"dozi", OP(9), OP_MASK, M601, PPCVLE, {RT, RA, SI}},
2730{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, 3844
2731{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, 3845{"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, UISIGNOPT}},
2732{ "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, 3846{"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, UISIGNOPT}},
2733{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, 3847{"cmpli", OP(10), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, UISIGNOPT}},
2734{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, 3848{"cmpli", OP(10), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, UISIGNOPT}},
2735{ "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, 3849
2736{ "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, 3850{"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, SI}},
2737{ "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, 3851{"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, SI}},
2738{ "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, 3852{"cmpi", OP(11), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, SI}},
2739{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, 3853{"cmpi", OP(11), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, SI}},
2740{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, 3854
2741{ "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, 3855{"addic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
2742{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, 3856{"ai", OP(12), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
2743{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, 3857{"subic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}},
2744{ "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, 3858
2745{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, 3859{"addic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
2746{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, 3860{"ai.", OP(13), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
2747{ "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, 3861{"subic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}},
2748{ "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } }, 3862
2749{ "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } }, 3863{"li", OP(14), DRA_MASK, PPCCOM, PPCVLE, {RT, SI}},
2750{ "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } }, 3864{"lil", OP(14), DRA_MASK, PWRCOM, PPCVLE, {RT, SI}},
2751{ "bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, { BI, BD } }, 3865{"addi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SI}},
2752{ "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } }, 3866{"cal", OP(14), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
2753{ "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } }, 3867{"subi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSI}},
2754{ "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } }, 3868{"la", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}},
2755{ "bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, { BI, BD } }, 3869
2756{ "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } }, 3870{"lis", OP(15), DRA_MASK, PPCCOM, PPCVLE, {RT, SISIGNOPT}},
2757{ "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } }, 3871{"liu", OP(15), DRA_MASK, PWRCOM, PPCVLE, {RT, SISIGNOPT}},
2758{ "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } }, 3872{"addis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SISIGNOPT}},
2759{ "bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } }, 3873{"cau", OP(15), OP_MASK, PWRCOM, PPCVLE, {RT, RA0, SISIGNOPT}},
2760{ "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } }, 3874{"subis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSISIGNOPT}},
2761{ "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } }, 3875
2762{ "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } }, 3876{"bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
2763{ "bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } }, 3877{"bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
2764{ "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } }, 3878{"bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BD}},
2765{ "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } }, 3879{"bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, PPCVLE, {BD}},
2766{ "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } }, 3880{"bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
2767{ "bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, { BI, BD } }, 3881{"bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
2768{ "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } }, 3882{"bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BD}},
2769{ "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } }, 3883{"bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, PPCVLE, {BD}},
2770{ "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD } }, 3884{"bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
2771{ "bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, { BI, BD } }, 3885{"bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
2772{ "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } }, 3886{"bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDA}},
2773{ "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } }, 3887{"bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, PPCVLE, {BDA}},
2774{ "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } }, 3888{"bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
2775{ "bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } }, 3889{"bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
2776{ "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } }, 3890{"bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDA}},
2777{ "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } }, 3891{"bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, PPCVLE, {BDA}},
2778{ "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } }, 3892{"bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
2779{ "bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } }, 3893{"bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
2780{ "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, 3894{"bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, PPCVLE, {BD}},
2781{ "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, 3895{"bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
2782{ "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, 3896{"bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
2783{ "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, 3897{"bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, PPCVLE, {BD}},
2784{ "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, 3898{"bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
2785{ "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, 3899{"bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
2786{ "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, 3900{"bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, PPCVLE, {BDA}},
2787{ "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, 3901{"bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
2788{ "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, 3902{"bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
2789{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, 3903{"bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, PPCVLE, {BDA}},
2790{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, 3904
2791{ "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, 3905{"bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2792{ "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, 3906{"bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2793{ "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, 3907{"bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
2794{ "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, 3908{"bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2795{ "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, 3909{"bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2796{ "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, 3910{"bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
2797{ "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, 3911{"bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2798{ "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, 3912{"bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2799{ "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, 3913{"bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
2800{ "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, 3914{"bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2801{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, 3915{"bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2802{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, 3916{"bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
2803{ "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, 3917{"bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2804{ "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } }, 3918{"bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2805{ "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } }, 3919{"bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
2806{ "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } }, 3920{"bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2807{ "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } }, 3921{"bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2808{ "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } }, 3922{"bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
2809{ "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } }, 3923{"bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2810{ "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } }, 3924{"bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2811{ "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } }, 3925{"bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
2812{ "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } }, 3926{"bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2813{ "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } }, 3927{"bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2814{ "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } }, 3928{"bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
2815{ "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } }, 3929{"ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2816 3930{"ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2817{ "sc", SC(17,1,0), SC_MASK, PPC, { LEV } }, 3931{"ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
2818{ "svc", SC(17,0,0), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } }, 3932{"bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2819{ "svcl", SC(17,0,1), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } }, 3933{"bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2820{ "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } }, 3934{"bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
2821{ "svcla", SC(17,1,1), SC_MASK, POWER, { SV } }, 3935{"blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2822 3936{"blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2823{ "b", B(18,0,0), B_MASK, COM, { LI } }, 3937{"blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
2824{ "bl", B(18,0,1), B_MASK, COM, { LI } }, 3938{"bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2825{ "ba", B(18,1,0), B_MASK, COM, { LIA } }, 3939{"bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2826{ "bla", B(18,1,1), B_MASK, COM, { LIA } }, 3940{"bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
2827 3941{"blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2828{ "mcrf", XL(19,0), XLBB_MASK|(3 << 21)|(3 << 16), COM, { BF, BFA } }, 3942{"blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2829 3943{"blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
2830{ "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, 3944{"bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2831{ "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } }, 3945{"bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2832{ "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, 3946{"bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
2833{ "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } }, 3947{"blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2834{ "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, 3948{"blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2835{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, 3949{"blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
2836{ "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, 3950{"bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2837{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, 3951{"bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2838{ "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, 3952{"bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
2839{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, 3953{"bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2840{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, 3954{"bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2841{ "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, 3955{"bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
2842{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, 3956{"bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2843{ "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, 3957{"bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2844{ "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, 3958{"bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
2845{ "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, 3959{"bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2846{ "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, 3960{"bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2847{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, 3961{"bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
2848{ "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, 3962{"bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2849{ "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, 3963{"bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2850{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, 3964{"bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
2851{ "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, 3965{"bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2852{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, 3966{"bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2853{ "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, 3967{"bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
2854{ "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3968{"bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2855{ "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3969{"bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2856{ "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 3970{"bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
2857{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3971{"bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2858{ "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 3972{"bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2859{ "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 3973{"bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
2860{ "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3974{"bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2861{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3975{"bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2862{ "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 3976{"bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
2863{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3977{"bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2864{ "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 3978{"bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2865{ "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 3979{"bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
2866{ "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3980{"bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2867{ "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3981{"bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2868{ "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 3982{"bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
2869{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3983{"bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2870{ "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 3984{"bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2871{ "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 3985{"bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
2872{ "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3986{"bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2873{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3987{"bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2874{ "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 3988{"bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
2875{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3989
2876{ "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 3990{"blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2877{ "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 3991{"blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2878{ "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3992{"blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
2879{ "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3993{"bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2880{ "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 3994{"bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2881{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3995{"bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
2882{ "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 3996{"blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2883{ "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 3997{"blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2884{ "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3998{"blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
2885{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3999{"bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2886{ "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 4000{"bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2887{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4001{"bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
2888{ "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 4002{"bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2889{ "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 4003{"bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2890{ "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4004{"bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
2891{ "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4005{"bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2892{ "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 4006{"bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2893{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4007{"bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
2894{ "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 4008{"bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2895{ "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 4009{"bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2896{ "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4010{"bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
2897{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4011{"bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2898{ "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 4012{"bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2899{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4013{"bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
2900{ "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 4014{"beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2901{ "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 4015{"beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2902{ "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4016{"beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
2903{ "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4017{"beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2904{ "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 4018{"beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2905{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4019{"beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
2906{ "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 4020{"beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2907{ "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4021{"beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2908{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4022{"beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
2909{ "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 4023{"beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2910{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4024{"beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2911{ "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 4025{"beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
2912{ "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4026{"bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2913{ "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4027{"bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2914{ "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 4028{"bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
2915{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4029{"bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2916{ "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 4030{"bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2917{ "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 4031{"bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
2918{ "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4032{"bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2919{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4033{"bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2920{ "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 4034{"bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
2921{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4035{"bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
2922{ "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 4036{"bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
2923{ "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 4037{"bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
2924{ "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4038{"bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2925{ "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4039{"bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2926{ "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 4040{"bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
2927{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4041{"buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2928{ "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 4042{"buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2929{ "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 4043{"buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
2930{ "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4044{"bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2931{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4045{"bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2932{ "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 4046{"bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
2933{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4047{"bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
2934{ "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 4048{"bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
2935{ "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 4049{"bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
2936{ "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4050
2937{ "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4051{"bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
2938{ "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 4052{"bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
2939{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4053{"bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
2940{ "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 4054{"bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
2941{ "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 4055{"bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
2942{ "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4056{"bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
2943{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4057{"bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
2944{ "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 4058{"bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
2945{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4059{"bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
2946{ "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 4060{"bdnzfla-", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
2947{ "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 4061{"bdnzfla+", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
2948{ "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4062{"bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
2949{ "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4063{"bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
2950{ "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 4064{"bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
2951{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4065{"bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
2952{ "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 4066{"bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
2953{ "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 4067{"bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
2954{ "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4068{"bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
2955{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4069{"bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
2956{ "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 4070{"bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
2957{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4071{"bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
2958{ "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 4072{"bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
2959{ "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 4073{"bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
2960{ "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4074{"bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
2961{ "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4075
2962{ "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 4076{"bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
2963{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4077{"bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
2964{ "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 4078{"bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
2965{ "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 4079{"bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
2966{ "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4080{"bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
2967{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4081{"bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
2968{ "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 4082{"bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
2969{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4083{"bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
2970{ "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 4084{"bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
2971{ "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 4085{"bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
2972{ "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4086{"bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
2973{ "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4087{"bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
2974{ "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 4088{"bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
2975{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4089{"bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
2976{ "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 4090{"bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
2977{ "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 4091{"bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
2978{ "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4092
2979{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4093{"bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
2980{ "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 4094{"bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
2981{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4095{"bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
2982{ "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 4096{"bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
2983{ "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 4097{"bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
2984{ "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4098{"bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
2985{ "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4099{"bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
2986{ "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 4100{"bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
2987{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4101{"bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
2988{ "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 4102{"bdnztla-", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
2989{ "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4103{"bdnztla+", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
2990{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4104{"bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
2991{ "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 4105{"bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
2992{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4106{"bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
2993{ "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 4107{"bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
2994{ "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, 4108{"bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
2995{ "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 4109{"bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
2996{ "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } }, 4110{"bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
2997{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 4111{"bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
2998{ "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } }, 4112{"bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
2999{ "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } }, 4113{"bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
3000{ "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, 4114{"bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
3001{ "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 4115{"bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
3002{ "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } }, 4116{"bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
3003{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 4117
3004{ "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } }, 4118{"bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
3005{ "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } }, 4119{"bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
3006{ "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, 4120{"bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
3007{ "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 4121{"bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
3008{ "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } }, 4122{"btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
3009{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 4123{"btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
3010{ "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } }, 4124{"btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
3011{ "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } }, 4125{"bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
3012{ "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, 4126{"bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
3013{ "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 4127{"bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
3014{ "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } }, 4128{"bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
3015{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 4129{"bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
3016{ "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } }, 4130{"btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
3017{ "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } }, 4131{"btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
3018{ "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, 4132{"btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
3019{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 4133{"bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
3020{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 4134
3021{ "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, 4135{"bc-", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDM}},
3022{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 4136{"bc+", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDP}},
3023{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 4137{"bc", B(16,0,0), B_MASK, COM, PPCVLE, {BO, BI, BD}},
3024{ "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, 4138{"bcl-", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDM}},
3025{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 4139{"bcl+", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDP}},
3026{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 4140{"bcl", B(16,0,1), B_MASK, COM, PPCVLE, {BO, BI, BD}},
3027{ "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, 4141{"bca-", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDMA}},
3028{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 4142{"bca+", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDPA}},
3029{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 4143{"bca", B(16,1,0), B_MASK, COM, PPCVLE, {BO, BI, BDA}},
3030{ "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, 4144{"bcla-", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDMA}},
3031{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 4145{"bcla+", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDPA}},
3032{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 4146{"bcla", B(16,1,1), B_MASK, COM, PPCVLE, {BO, BI, BDA}},
3033{ "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, 4147
3034{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 4148{"svc", SC(17,0,0), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
3035{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 4149{"svcl", SC(17,0,1), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
3036{ "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, 4150{"sc", SC(17,1,0), SC_MASK, PPC, PPCVLE, {LEV}},
3037{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 4151{"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCVLE, {SV}},
3038{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 4152{"svcla", SC(17,1,1), SC_MASK, POWER, PPCVLE, {SV}},
3039{ "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, 4153
3040{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 4154{"b", B(18,0,0), B_MASK, COM, PPCVLE, {LI}},
3041{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 4155{"bl", B(18,0,1), B_MASK, COM, PPCVLE, {LI}},
3042{ "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, 4156{"ba", B(18,1,0), B_MASK, COM, PPCVLE, {LIA}},
3043{ "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, 4157{"bla", B(18,1,1), B_MASK, COM, PPCVLE, {LIA}},
3044{ "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, 4158
3045{ "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, 4159{"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}},
3046{ "bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, { BO, BI, BH } }, 4160
3047{ "bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, { BO, BI, BH } }, 4161{"addpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, DXD}},
3048{ "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } }, 4162{"subpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, NDXD}},
3049{ "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } }, 4163
3050{ "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } }, 4164{"bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
3051{ "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI } }, 4165{"bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
3052 4166{"bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
3053{ "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } }, 4167{"bdnzlrl-", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
3054 4168{"bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
3055{ "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } }, 4169{"bdnzlrl+", XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
3056{ "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } }, 4170{"bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
3057{ "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } }, 4171{"bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
3058 4172{"bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
3059{ "rfi", XL(19,50), 0xffffffff, COM, { 0 } }, 4173{"bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
3060{ "rfci", XL(19,51), 0xffffffff, PPC403 | BOOKE, { 0 } }, 4174{"bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
3061 4175{"bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
3062{ "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } }, 4176{"blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
3063 4177{"br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, PPCVLE, {0}},
3064{ "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } }, 4178{"blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
3065 4179{"brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, PPCVLE, {0}},
3066{ "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } }, 4180{"bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
3067{ "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } }, 4181{"bdnzlrl-", XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
3068 4182{"bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
3069{ "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } }, 4183{"bdnzlrl+", XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
3070{ "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } }, 4184{"bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
3071 4185{"bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
3072{ "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } }, 4186{"bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
3073 4187{"bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
3074{ "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } }, 4188
3075 4189{"bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3076{ "hrfid", XL(19,274), 0xffffffff, POWER5 | CELL, { 0 } }, 4190{"bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3077 4191{"bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
3078{ "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } }, 4192{"bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3079{ "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } }, 4193{"bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3080 4194{"bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
3081{ "doze", XL(19,402), 0xffffffff, POWER6, { 0 } }, 4195{"bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3082 4196{"bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3083{ "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } }, 4197{"bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
3084 4198{"bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3085{ "nap", XL(19,434), 0xffffffff, POWER6, { 0 } }, 4199{"bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3086 4200{"bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
3087{ "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } }, 4201{"blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3088{ "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } }, 4202{"blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3089 4203{"bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
3090{ "sleep", XL(19,466), 0xffffffff, POWER6, { 0 } }, 4204{"bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3091{ "rvwinkle", XL(19,498), 0xffffffff, POWER6, { 0 } }, 4205{"bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3092 4206{"bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
3093{ "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } }, 4207{"blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3094{ "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } }, 4208{"blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3095{ "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4209{"blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
3096{ "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4210{"bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3097{ "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4211{"bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3098{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4212{"bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
3099{ "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4213{"bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3100{ "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4214{"bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3101{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4215{"bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
3102{ "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4216{"bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3103{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4217{"bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3104{ "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4218{"bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
3105{ "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4219{"bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3106{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4220{"bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3107{ "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4221{"bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
3108{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4222{"bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3109{ "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4223{"bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3110{ "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4224{"bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3111{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4225{"bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3112{ "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4226{"bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
3113{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4227{"bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3114{ "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4228{"bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3115{ "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4229{"bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3116{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4230{"bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3117{ "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4231{"bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3118{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4232{"bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3119{ "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4233{"blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3120{ "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4234{"bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3121{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4235{"blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3122{ "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4236{"bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3123{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4237{"bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3124{ "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4238{"bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3125{ "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4239{"bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3126{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4240{"bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3127{ "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4241{"bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3128{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4242{"bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3129{ "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4243{"bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3130{ "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4244{"bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3131{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4245{"bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3132{ "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4246{"bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3133{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4247{"blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3134{ "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4248{"bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3135{ "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4249{"blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3136{ "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4250{"bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3137{ "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4251{"bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3138{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4252{"bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3139{ "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4253{"bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3140{ "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4254{"bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3141{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4255{"bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3142{ "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4256{"bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3143{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4257{"bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3144{ "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4258{"bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3145{ "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4259{"bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3146{ "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4260{"bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3147{ "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4261{"blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3148{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4262{"bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3149{ "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4263{"blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3150{ "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4264{"bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3151{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4265{"bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3152{ "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4266{"bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3153{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4267{"bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3154{ "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4268{"bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3155{ "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4269{"bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3156{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4270{"bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3157{ "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4271{"bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3158{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4272{"bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3159{ "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4273{"bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
3160{ "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4274{"bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3161{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4275{"bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3162{ "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4276{"bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
3163{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4277{"bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3164{ "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4278{"bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3165{ "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4279{"bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
3166{ "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4280{"bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3167{ "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4281{"bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3168{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4282{"bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
3169{ "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4283{"beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3170{ "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4284{"beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3171{ "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4285{"beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
3172{ "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4286{"beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3173{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4287{"beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3174{ "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4288{"beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
3175{ "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4289{"bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3176{ "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4290{"bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3177{ "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4291{"bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
3178{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4292{"bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3179{ "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4293{"bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3180{ "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4294{"bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3181{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4295{"bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3182{ "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4296{"bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
3183{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4297{"bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3184{ "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4298{"bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3185{ "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4299{"bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3186{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4300{"bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3187{ "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4301{"bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3188{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4302{"bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3189{ "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4303{"beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3190{ "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4304{"beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3191{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4305{"bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3192{ "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4306{"bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3193{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4307{"bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3194{ "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4308{"bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3195{ "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4309{"bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3196{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4310{"bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3197{ "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4311{"bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3198{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4312{"bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3199{ "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4313{"beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3200{ "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4314{"beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3201{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4315{"bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3202{ "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4316{"bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3203{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4317{"bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3204{ "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4318{"bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3205{ "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 4319{"bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3206{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4320{"bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3207{ "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4321{"bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3208{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4322{"bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3209{ "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 4323{"beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3210{ "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 4324{"beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3211{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4325{"bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3212{ "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4326{"bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3213{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 4327{"bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3214{ "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 4328{"bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3215{ "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } }, 4329
3216{ "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, 4330{"bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
3217{ "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } }, 4331{"bdnzflr-", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
3218{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, 4332{"bdnzflrl", XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
3219{ "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } }, 4333{"bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
3220{ "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } }, 4334{"bdnzflr+", XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
3221{ "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, 4335{"bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
3222{ "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } }, 4336{"bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
3223{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, 4337{"bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
3224{ "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } }, 4338{"bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
3225{ "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } }, 4339{"bdzflrl-", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
3226{ "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, 4340{"bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
3227{ "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } }, 4341{"bdzflrl+", XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
3228{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, 4342{"bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
3229{ "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } }, 4343{"bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
3230{ "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } }, 4344{"bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
3231{ "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, 4345{"bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
3232{ "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } }, 4346{"bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
3233{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, 4347{"bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
3234{ "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } }, 4348{"bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
3235{ "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, 4349{"bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
3236{ "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, 4350{"bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
3237{ "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, 4351{"bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
3238{ "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, 4352{"bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
3239{ "bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, { BO, BI, BH } }, 4353{"bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
3240{ "bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, { BO, BI, BH } }, 4354{"bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
3241{ "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } }, 4355{"bdnztlr-", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
3242{ "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } }, 4356{"bdnztlrl", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
3243{ "bcctre", XLLK(19,529,0), XLYBB_MASK, BOOKE64, { BO, BI } }, 4357{"bdnztlrl-", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
3244{ "bcctrel", XLLK(19,529,1), XLYBB_MASK, BOOKE64, { BO, BI } }, 4358{"bdnztlr+", XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
3245 4359{"bdnztlrl+", XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
3246{ "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, 4360{"bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
3247{ "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, 4361{"bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
3248 4362{"bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
3249{ "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, 4363{"bdztlrl-", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
3250{ "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, 4364{"bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
3251 4365{"bdztlrl+", XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
3252{ "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } }, 4366{"btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
3253{ "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } }, 4367{"btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
3254{ "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, 4368{"bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
3255{ "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, 4369{"btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
3256{ "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } }, 4370{"btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
3257{ "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } }, 4371{"bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
3258{ "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, 4372{"btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
3259{ "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, 4373{"btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
3260 4374{"btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
3261{ "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } }, 4375{"btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
3262{ "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } }, 4376{"btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
3263 4377{"btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
3264{ "be", B(22,0,0), B_MASK, BOOKE64, { LI } }, 4378
3265{ "bel", B(22,0,1), B_MASK, BOOKE64, { LI } }, 4379{"bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
3266{ "bea", B(22,1,0), B_MASK, BOOKE64, { LIA } }, 4380{"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
3267{ "bela", B(22,1,1), B_MASK, BOOKE64, { LIA } }, 4381{"bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
3268 4382{"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
3269{ "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } }, 4383{"bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
3270{ "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } }, 4384{"bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
3271{ "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } }, 4385{"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
3272{ "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } }, 4386{"bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
3273{ "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } }, 4387
3274{ "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } }, 4388{"rfid", XL(19,18), 0xffffffff, PPC64, PPCVLE, {0}},
3275 4389
3276{ "nop", OP(24), 0xffffffff, PPCCOM, { 0 } }, 4390{"crnot", XL(19,33), XL_MASK, PPCCOM, PPCVLE, {BT, BA, BBA}},
3277{ "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } }, 4391{"crnor", XL(19,33), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
3278{ "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } }, 4392{"rfmci", X(19,38), 0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCVLE, {0}},
3279 4393
3280{ "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } }, 4394{"rfdi", XL(19,39), 0xffffffff, E500MC, PPCVLE, {0}},
3281{ "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } }, 4395{"rfi", XL(19,50), 0xffffffff, COM, PPCVLE, {0}},
3282 4396{"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCVLE, {0}},
3283{ "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } }, 4397
3284{ "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } }, 4398{"rfsvc", XL(19,82), 0xffffffff, POWER, PPCVLE, {0}},
3285 4399
3286{ "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } }, 4400{"rfgi", XL(19,102), 0xffffffff, E500MC|PPCA2, PPCVLE, {0}},
3287{ "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } }, 4401
3288 4402{"crandc", XL(19,129), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
3289{ "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } }, 4403
3290{ "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } }, 4404{"rfebb", XL(19,146), XLS_MASK, POWER8, PPCVLE, {SXL}},
3291 4405
3292{ "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } }, 4406{"isync", XL(19,150), 0xffffffff, PPCCOM, PPCVLE, {0}},
3293{ "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } }, 4407{"ics", XL(19,150), 0xffffffff, PWRCOM, PPCVLE, {0}},
3294 4408
3295{ "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } }, 4409{"crclr", XL(19,193), XL_MASK, PPCCOM, PPCVLE, {BT, BAT, BBA}},
3296{ "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } }, 4410{"crxor", XL(19,193), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
3297{ "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, 4411
3298{ "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } }, 4412{"dnh", X(19,198), X_MASK, E500MC, PPCVLE, {DUI, DUIS}},
3299{ "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } }, 4413
3300{ "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, 4414{"crnand", XL(19,225), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
3301 4415
3302{ "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } }, 4416{"crand", XL(19,257), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
3303{ "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } }, 4417
3304 4418{"hrfid", XL(19,274), 0xffffffff, POWER5|CELL, PPC476|PPCVLE, {0}},
3305{ "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, 4419
3306{ "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, 4420{"crset", XL(19,289), XL_MASK, PPCCOM, PPCVLE, {BT, BAT, BBA}},
3307 4421{"creqv", XL(19,289), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
3308{ "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, 4422
3309{ "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, 4423{"urfid", XL(19,306), 0xffffffff, POWER9, PPCVLE, {0}},
3310 4424{"stop", XL(19,370), 0xffffffff, POWER9, PPCVLE, {0}},
3311{ "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } }, 4425
3312{ "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } }, 4426{"doze", XL(19,402), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
3313{ "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } }, 4427
3314{ "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } }, 4428{"crorc", XL(19,417), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
3315 4429
3316{ "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } }, 4430{"nap", XL(19,434), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
3317{ "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } }, 4431
3318 4432{"crmove", XL(19,449), XL_MASK, PPCCOM, PPCVLE, {BT, BA, BBA}},
3319{ "cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } }, 4433{"cror", XL(19,449), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
3320{ "cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } }, 4434
3321{ "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } }, 4435{"sleep", XL(19,466), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
3322{ "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } }, 4436{"rvwinkle", XL(19,498), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
3323 4437
3324{ "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } }, 4438{"bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, PPCVLE, {0}},
3325{ "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } }, 4439{"bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, PPCVLE, {0}},
3326{ "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } }, 4440
3327{ "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } }, 4441{"bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3328{ "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } }, 4442{"bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3329{ "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } }, 4443{"bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3330{ "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } }, 4444{"bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3331{ "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } }, 4445{"bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3332{ "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } }, 4446{"bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3333{ "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } }, 4447{"bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3334{ "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } }, 4448{"bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3335{ "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } }, 4449{"blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3336{ "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } }, 4450{"blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3337{ "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } }, 4451{"bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3338{ "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } }, 4452{"bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3339{ "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } }, 4453{"blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3340{ "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } }, 4454{"blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3341{ "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } }, 4455{"bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3342{ "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } }, 4456{"bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3343{ "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } }, 4457{"bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3344{ "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } }, 4458{"bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3345{ "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } }, 4459{"bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3346{ "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } }, 4460{"bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3347{ "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } }, 4461{"bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3348{ "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } }, 4462{"bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3349{ "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } }, 4463{"bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3350{ "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } }, 4464{"bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3351{ "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } }, 4465{"bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3352{ "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } }, 4466{"bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3353{ "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } }, 4467{"bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3354{ "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } }, 4468{"bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3355 4469{"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3356{ "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 4470{"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3357{ "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 4471{"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3358{ "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } }, 4472{"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3359{ "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 4473{"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3360{ "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 4474{"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3361{ "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } }, 4475{"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3362{ "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 4476{"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3363{ "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 4477{"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3364{ "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } }, 4478{"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3365{ "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 4479{"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3366{ "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 4480{"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3367{ "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } }, 4481{"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3368 4482{"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3369{ "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } }, 4483{"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3370{ "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } }, 4484{"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3371 4485{"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3372{ "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 4486{"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3373{ "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 4487{"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3374{ "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 4488{"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3375{ "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 4489{"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3376{ "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 4490{"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3377{ "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 4491{"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3378{ "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 4492{"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3379{ "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 4493{"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3380 4494{"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3381{ "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } }, 4495{"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3382{ "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } }, 4496{"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3383 4497{"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3384{ "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } }, 4498{"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3385{ "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } }, 4499{"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3386{ "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } }, 4500{"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3387{ "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } }, 4501{"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3388 4502{"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3389{ "mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, { RT, FXM } }, 4503{"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3390{ "mfcr", X(31,19), XRARB_MASK, NOPOWER4 | COM, { RT } }, 4504{"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3391{ "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } }, 4505{"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3392 4506{"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3393{ "lwarx", X(31,20), XEH_MASK, PPC, { RT, RA0, RB, EH } }, 4507{"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3394 4508{"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3395{ "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } }, 4509{"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3396 4510{"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3397{ "icbt", X(31,22), X_MASK, BOOKE|PPCE300, { CT, RA, RB } }, 4511{"bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3398{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } }, 4512{"bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3399 4513{"bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3400{ "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA0, RB } }, 4514{"bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3401{ "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } }, 4515{"bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3402 4516{"bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3403{ "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } }, 4517{"bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3404{ "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } }, 4518{"bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3405{ "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } }, 4519{"beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3406{ "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } }, 4520{"beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3407 4521{"beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3408{ "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } }, 4522{"beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3409{ "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } }, 4523{"bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3410{ "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } }, 4524{"bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3411{ "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } }, 4525{"bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3412 4526{"bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3413{ "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } }, 4527{"bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3414{ "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } }, 4528{"bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3415 4529{"bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
3416{ "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } }, 4530{"bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3417{ "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } }, 4531{"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3418 4532{"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3419{ "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } }, 4533{"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3420{ "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } }, 4534{"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3421 4535{"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3422{ "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } }, 4536{"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3423 4537{"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3424{ "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA0, RB } }, 4538{"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3425 4539{"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3426{ "cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } }, 4540{"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
3427{ "cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } }, 4541{"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3428{ "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } }, 4542{"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3429{ "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } }, 4543{"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3430 4544{"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3431{ "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } }, 4545{"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3432{ "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } }, 4546{"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3433{ "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } }, 4547{"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3434{ "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } }, 4548{"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3435{ "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } }, 4549{"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3436{ "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } }, 4550{"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3437{ "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } }, 4551{"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
3438{ "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } }, 4552{"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4553{"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4554{"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4555{"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4556{"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4557{"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4558{"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4559{"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4560{"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4561
4562{"bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4563{"bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4564{"bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4565{"bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4566{"bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4567{"bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4568{"bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4569{"bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4570{"bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4571{"bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4572{"btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4573{"btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4574{"btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4575{"btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4576{"btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4577{"btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4578{"btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4579{"btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4580{"btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4581{"btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4582
4583{"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4584{"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4585{"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4586{"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4587{"bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4588{"bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4589{"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4590{"bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4591
4592{"bctar-", XLYLK(19,560,0,0), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4593{"bctarl-", XLYLK(19,560,0,1), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4594{"bctar+", XLYLK(19,560,1,0), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4595{"bctarl+", XLYLK(19,560,1,1), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4596{"bctar", XLLK(19,560,0), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}},
4597{"bctarl", XLLK(19,560,1), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}},
4598
4599{"rlwimi", M(20,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4600{"rlimi", M(20,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4601
4602{"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4603{"rlimi.", M(20,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4604
4605{"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}},
4606{"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}},
4607{"rlwinm", M(21,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4608{"rlinm", M(21,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4609{"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}},
4610{"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}},
4611{"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4612{"rlinm.", M(21,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4613
4614{"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
4615{"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
4616
4617{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}},
4618{"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4619{"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4620{"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}},
4621{"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4622{"rlnm.", M(23,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4623
4624{"nop", OP(24), 0xffffffff, PPCCOM, PPCVLE, {0}},
4625{"ori", OP(24), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4626{"oril", OP(24), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4627
4628{"oris", OP(25), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4629{"oriu", OP(25), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4630
4631{"xnop", OP(26), 0xffffffff, PPCCOM, PPCVLE, {0}},
4632{"xori", OP(26), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4633{"xoril", OP(26), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4634
4635{"xoris", OP(27), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4636{"xoriu", OP(27), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4637
4638{"andi.", OP(28), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4639{"andil.", OP(28), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4640
4641{"andis.", OP(29), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4642{"andiu.", OP(29), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4643
4644{"rotldi", MD(30,0,0), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}},
4645{"clrldi", MD(30,0,0), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}},
4646{"rldicl", MD(30,0,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4647{"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}},
4648{"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}},
4649{"rldicl.", MD(30,0,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4650
4651{"rldicr", MD(30,1,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}},
4652{"rldicr.", MD(30,1,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}},
4653
4654{"rldic", MD(30,2,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4655{"rldic.", MD(30,2,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4656
4657{"rldimi", MD(30,3,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4658{"rldimi.", MD(30,3,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4659
4660{"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}},
4661{"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}},
4662{"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}},
4663{"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}},
4664
4665{"rldcr", MDS(30,9,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}},
4666{"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}},
4667
4668{"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
4669{"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
4670{"cmp", X(31,0), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}},
4671{"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
4672
4673{"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4674{"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4675{"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4676{"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4677{"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, 0, {RA, RB}},
4678{"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, 0, {RA, RB}},
4679{"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4680{"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4681{"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, 0, {RA, RB}},
4682{"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, 0, {RA, RB}},
4683{"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4684{"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4685{"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, 0, {RA, RB}},
4686{"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, 0, {RA, RB}},
4687{"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4688{"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4689{"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4690{"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4691{"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, 0, {RA, RB}},
4692{"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, 0, {RA, RB}},
4693{"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4694{"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4695{"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4696{"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4697{"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, 0, {RA, RB}},
4698{"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, 0, {RA, RB}},
4699{"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4700{"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4701{"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, 0, {0}},
4702{"twu", XTO(31,4,TOU), XTO_MASK, PPCCOM, 0, {RA, RB}},
4703{"tu", XTO(31,4,TOU), XTO_MASK, PWRCOM, 0, {RA, RB}},
4704{"tw", X(31,4), X_MASK, PPCCOM, 0, {TO, RA, RB}},
4705{"t", X(31,4), X_MASK, PWRCOM, 0, {TO, RA, RB}},
4706
4707{"lvsl", X(31,6), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4708{"lvebx", X(31,7), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4709{"lbfcmx", APU(31,7,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4710
4711{"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4712{"sf", XO(31,8,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4713{"subc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
4714{"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4715{"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4716{"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
4717
4718{"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
4719{"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
4720
4721{"addc", XO(31,10,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4722{"a", XO(31,10,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4723{"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4724{"a.", XO(31,10,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4725
4726{"mulhwu", XO(31,11,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4727{"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
4728
4729{"lxsiwzx", X(31,12), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
4730
4731{"isellt", X(31,15), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
4732
4733{"tlbilxlpid", XTO(31,18,0), XTO_MASK, E500MC|PPCA2, 0, {0}},
4734{"tlbilxpid", XTO(31,18,1), XTO_MASK, E500MC|PPCA2, 0, {0}},
4735{"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|PPCA2, 0, {RA0, RB}},
4736{"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, 0, {T, RA0, RB}},
4737
4738{"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, COM, 0, {RT, FXM4}},
4739{"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, 0, {RT, FXM}},
4740
4741{"lwarx", X(31,20), XEH_MASK, PPC, 0, {RT, RA0, RB, EH}},
4742
4743{"ldx", X(31,21), X_MASK, PPC64, 0, {RT, RA0, RB}},
4744
4745{"icbt", X(31,22), X_MASK, BOOKE|PPCE300|PPCA2|PPC476, 0, {CT, RA0, RB}},
4746
4747{"lwzx", X(31,23), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
4748{"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}},
4749
4750{"slw", XRC(31,24,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
4751{"sl", XRC(31,24,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
4752{"slw.", XRC(31,24,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
4753{"sl.", XRC(31,24,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
4754
4755{"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, 0, {RA, RS}},
4756{"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, 0, {RA, RS}},
4757{"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, 0, {RA, RS}},
4758{"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, 0, {RA, RS}},
4759
4760{"sld", XRC(31,27,0), X_MASK, PPC64, 0, {RA, RS, RB}},
4761{"sld.", XRC(31,27,1), X_MASK, PPC64, 0, {RA, RS, RB}},
4762
4763{"and", XRC(31,28,0), X_MASK, COM, 0, {RA, RS, RB}},
4764{"and.", XRC(31,28,1), X_MASK, COM, 0, {RA, RS, RB}},
4765
4766{"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}},
4767{"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}},
4768
4769{"ldepx", X(31,29), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
4770
4771{"waitasec", X(31,30), XRTRARB_MASK, POWER8, POWER9, {0}},
4772{"wait", X(31,30), XWC_MASK, POWER9, 0, {WC}},
4773
4774{"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
4775
4776{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
4777{"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
4778{"cmpl", X(31,32), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}},
4779{"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
4780
4781{"lvsr", X(31,38), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4782{"lvehx", X(31,39), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4783{"lhfcmx", APU(31,39,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4784
4785{"mviwsplt", X(31,46), X_MASK, PPCVEC2, 0, {VD, RA, RB}},
4786
4787{"iselgt", X(31,47), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
4788
4789{"lvewx", X(31,71), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4790
4791{"addg6s", XO(31,74,0,0), XO_MASK, POWER6, 0, {RT, RA, RB}},
4792
4793{"lxsiwax", X(31,76), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
4794
4795{"iseleq", X(31,79), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
4796
4797{"isel", XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, 0, {RT, RA0, RB, CRB}},
4798
4799{"subf", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4800{"sub", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RB, RA}},
4801{"subf.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
4802{"sub.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RB, RA}},
4803
4804{"mfvsrd", X(31,51), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}},
4805{"mffprd", X(31,51), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}},
4806{"mfvrd", X(31,51)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}},
4807{"eratilx", X(31,51), X_MASK, PPCA2, 0, {ERAT_T, RA, RB}},
4808
4809{"lbarx", X(31,52), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},
4810
4811{"ldux", X(31,53), X_MASK, PPC64, 0, {RT, RAL, RB}},
4812
4813{"dcbst", X(31,54), XRT_MASK, PPC, 0, {RA0, RB}},
4814
4815{"lwzux", X(31,55), X_MASK, PPCCOM, 0, {RT, RAL, RB}},
4816{"lux", X(31,55), X_MASK, PWRCOM, 0, {RT, RA, RB}},
4817
4818{"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, 0, {RA, RS}},
4819{"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, 0, {RA, RS}},
4820
4821{"andc", XRC(31,60,0), X_MASK, COM, 0, {RA, RS, RB}},
4822{"andc.", XRC(31,60,1), X_MASK, COM, 0, {RA, RS, RB}},
4823
4824{"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, 0, {0}},
4825{"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, 0, {0}},
4826{"wait", X(31,62), XWC_MASK, E500MC|PPCA2, 0, {WC}},
4827
4828{"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
4829
4830{"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, 0, {RA, RB}},
4831{"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, 0, {RA, RB}},
4832{"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, 0, {RA, RB}},
4833{"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, 0, {RA, RB}},
4834{"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, 0, {RA, RB}},
4835{"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, 0, {RA, RB}},
4836{"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, 0, {RA, RB}},
4837{"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, 0, {RA, RB}},
4838{"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, 0, {RA, RB}},
4839{"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, 0, {RA, RB}},
4840{"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, 0, {RA, RB}},
4841{"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, 0, {RA, RB}},
4842{"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, 0, {RA, RB}},
4843{"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, 0, {RA, RB}},
4844{"tdu", XTO(31,68,TOU), XTO_MASK, PPC64, 0, {RA, RB}},
4845{"td", X(31,68), X_MASK, PPC64, 0, {TO, RA, RB}},
4846
4847{"lwfcmx", APU(31,71,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4848{"mulhd", XO(31,73,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
4849{"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
4850
4851{"mulhw", XO(31,75,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4852{"mulhw.", XO(31,75,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
4853
4854{"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}},
4855{"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}},
4856
4857{"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, 0, {SR, RS}},
4858
4859{"mfmsr", X(31,83), XRARB_MASK, COM, 0, {RT}},
4860
4861{"ldarx", X(31,84), XEH_MASK, PPC64, 0, {RT, RA0, RB, EH}},
4862
4863{"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476, {RA0, RB}},
4864{"dcbf", X(31,86), XLRT_MASK, PPC, 0, {RA0, RB, L2OPT}},
4865
4866{"lbzx", X(31,87), X_MASK, COM, 0, {RT, RA0, RB}},
4867
4868{"lbepx", X(31,95), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
4869
4870{"dni", XRC(31,97,1), XRB_MASK, E6500, 0, {DUI, DCTL}},
4871
4872{"lvx", X(31,103), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4873{"lqfcmx", APU(31,103,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4874
4875{"neg", XO(31,104,0,0), XORB_MASK, COM, 0, {RT, RA}},
4876{"neg.", XO(31,104,0,1), XORB_MASK, COM, 0, {RT, RA}},
4877
4878{"mul", XO(31,107,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
4879{"mul.", XO(31,107,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
4880
4881{"mvidsplt", X(31,110), X_MASK, PPCVEC2, 0, {VD, RA, RB}},
4882
4883{"mtsrdin", X(31,114), XRA_MASK, PPC64, 0, {RS, RB}},
4884
4885{"mffprwz", X(31,115), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}},
4886{"mfvrwz", X(31,115)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}},
4887{"mfvsrwz", X(31,115), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}},
4888
4889{"lharx", X(31,116), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},
4890
4891{"clf", X(31,118), XTO_MASK, POWER, 0, {RA, RB}},
4892
4893{"lbzux", X(31,119), X_MASK, COM, 0, {RT, RAL, RB}},
4894
4895{"popcntb", X(31,122), XRB_MASK, POWER5, 0, {RA, RS}},
4896
4897{"not", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RBS}},
4898{"nor", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RB}},
4899{"not.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RBS}},
4900{"nor.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RB}},
4901
4902{"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
4903
4904{"setb", X(31,128), XRB_MASK|(3<<16), POWER9, 0, {RT, BFA}},
4905
4906{"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RS}},
4907
4908{"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
4909
4910{"stvebx", X(31,135), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
4911{"stbfcmx", APU(31,135,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4912
4913{"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4914{"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4915{"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4916{"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4917
4918{"adde", XO(31,138,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4919{"ae", XO(31,138,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4920{"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4921{"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4922
4923{"stxsiwx", X(31,140), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}},
4924
4925{"msgsndp", XRTRA(31,142,0,0), XRTRA_MASK, POWER8, 0, {RB}},
4926{"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
4927
4928{"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, 0, {RS}},
4929{"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, 0, {FXM, RS}},
4930{"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, 0, {FXM, RS}},
4931
4932{"mtmsr", X(31,146), XRLARB_MASK, COM, 0, {RS, A_L}},
4933
4934{"mtsle", X(31,147), XRTLRARB_MASK, POWER8, 0, {L}},
3439 4935
3440{ "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } }, 4936{"eratsx", XRC(31,147,0), X_MASK, PPCA2, 0, {RT, RA0, RB}},
4937{"eratsx.", XRC(31,147,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
3441 4938
3442{ "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } }, 4939{"stdx", X(31,149), X_MASK, PPC64, 0, {RS, RA0, RB}},
3443 4940
3444{ "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } }, 4941{"stwcx.", XRC(31,150,1), X_MASK, PPC, 0, {RS, RA0, RB}},
3445{ "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
3446 4942
3447{ "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } }, 4943{"stwx", X(31,151), X_MASK, PPCCOM, 0, {RS, RA0, RB}},
4944{"stx", X(31,151), X_MASK, PWRCOM, 0, {RS, RA, RB}},
3448 4945
3449{ "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } }, 4946{"slq", XRC(31,152,0), X_MASK, M601, 0, {RA, RS, RB}},
4947{"slq.", XRC(31,152,1), X_MASK, M601, 0, {RA, RS, RB}},
3450 4948
3451{ "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } }, 4949{"sle", XRC(31,153,0), X_MASK, M601, 0, {RA, RS, RB}},
3452{ "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } }, 4950{"sle.", XRC(31,153,1), X_MASK, M601, 0, {RA, RS, RB}},
3453 4951
3454{ "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } }, 4952{"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS}},
3455{ "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
3456 4953
3457{ "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } }, 4954{"stdepx", X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
3458{ "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } },
3459{ "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } },
3460{ "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } },
3461{ "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } },
3462{ "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
3463{ "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } },
3464{ "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } },
3465{ "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } },
3466{ "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } },
3467{ "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } },
3468{ "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } },
3469{ "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } },
3470{ "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } },
3471{ "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } },
3472 4955
3473{ "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } }, 4956{"stwepx", X(31,159), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
3474{ "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3475 4957
3476{ "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } }, 4958{"wrteei", X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {E}},
3477{ "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
3478 4959
3479{ "dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, { RA, RS, RB } }, 4960{"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
3480{ "dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3481 4961
3482{ "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } }, 4962{"stvehx", X(31,167), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
4963{"sthfcmx", APU(31,167,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
3483 4964
3484{ "mfmsr", X(31,83), XRARB_MASK, COM, { RT } }, 4965{"addex", ZRC(31,170,0), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}},
3485 4966
3486{ "ldarx", X(31,84), XEH_MASK, PPC64, { RT, RA0, RB, EH } }, 4967{"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK, POWER8, 0, {RB}},
4968{"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
3487 4969
3488{ "dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, { RA, RB } }, 4970{"mtmsrd", X(31,178), XRLARB_MASK, PPC64, 0, {RS, A_L}},
3489{ "dcbf", X(31,86), XLRT_MASK, PPC, { RA, RB, XRT_L } },
3490 4971
3491{ "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } }, 4972{"mtvsrd", X(31,179), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
4973{"mtfprd", X(31,179), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
4974{"mtvrd", X(31,179)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
4975{"eratre", X(31,179), X_MASK, PPCA2, 0, {RT, RA, WS}},
3492 4976
3493{ "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } }, 4977{"stdux", X(31,181), X_MASK, PPC64, 0, {RS, RAS, RB}},
3494 4978
3495{ "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA0, RB } }, 4979{"stqcx.", XRC(31,182,1), X_MASK, POWER8, 0, {RSQ, RA0, RB}},
4980{"wchkall", X(31,182), X_MASK, PPCA2, 0, {OBF}},
3496 4981
3497{ "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } }, 4982{"stwux", X(31,183), X_MASK, PPCCOM, 0, {RS, RAS, RB}},
3498{ "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } }, 4983{"stux", X(31,183), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
3499{ "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } },
3500{ "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } },
3501 4984
3502{ "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } }, 4985{"sliq", XRC(31,184,0), X_MASK, M601, 0, {RA, RS, SH}},
3503{ "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } }, 4986{"sliq.", XRC(31,184,1), X_MASK, M601, 0, {RA, RS, SH}},
3504{ "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } },
3505{ "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } },
3506 4987
3507{ "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } }, 4988{"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, 0, {RA, RS}},
3508 4989
3509{ "clf", X(31,118), XTO_MASK, POWER, { RA, RB } }, 4990{"cmprb", X(31,192), XCMP_MASK, POWER9, 0, {BF, L, RA, RB}},
3510 4991
3511{ "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } }, 4992{"icblq.", XRC(31,198,1), X_MASK, E6500, 0, {CT, RA0, RB}},
3512 4993
3513{ "popcntb", X(31,122), XRB_MASK, POWER5, { RA, RS } }, 4994{"stvewx", X(31,199), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
4995{"stwfcmx", APU(31,199,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
3514 4996
3515{ "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } }, 4997{"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
3516{ "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } }, 4998{"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
3517{ "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } }, 4999{"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
3518{ "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } }, 5000{"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
3519 5001
3520{ "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA0, RB } }, 5002{"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5003{"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5004{"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5005{"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
3521 5006
3522{ "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } }, 5007{"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}},
3523 5008
3524{ "wrtee", X(31,131), XRARB_MASK, PPC403 | BOOKE, { RS } }, 5009{"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}},
3525 5010
3526{ "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }}, 5011{"mtfprwa", X(31,211), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
5012{"mtvrwa", X(31,211)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
5013{"mtvsrwa", X(31,211), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
5014{"eratwe", X(31,211), X_MASK, PPCA2, 0, {RS, RA, WS}},
3527 5015
3528{ "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 5016{"ldawx.", XRC(31,212,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
3529{ "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3530{ "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3531{ "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3532{ "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3533{ "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3534{ "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3535{ "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3536 5017
3537{ "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 5018{"stdcx.", XRC(31,214,1), X_MASK, PPC64, 0, {RS, RA0, RB}},
3538{ "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3539{ "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3540{ "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3541{ "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3542{ "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3543{ "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3544{ "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3545 5019
3546{ "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }}, 5020{"stbx", X(31,215), X_MASK, COM, 0, {RS, RA0, RB}},
3547 5021
3548{ "mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, { FXM, RS } }, 5022{"sllq", XRC(31,216,0), X_MASK, M601, 0, {RA, RS, RB}},
3549{ "mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, { RS }}, 5023{"sllq.", XRC(31,216,1), X_MASK, M601, 0, {RA, RS, RB}},
3550{ "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
3551 5024
3552{ "mtmsr", X(31,146), XRARB_MASK, COM, { RS } }, 5025{"sleq", XRC(31,217,0), X_MASK, M601, 0, {RA, RS, RB}},
5026{"sleq.", XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}},
3553 5027
3554{ "stdx", X(31,149), X_MASK, PPC64, { RS, RA0, RB } }, 5028{"stbepx", X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
3555 5029
3556{ "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA0, RB } }, 5030{"cmpeqb", X(31,224), XCMPL_MASK, POWER9, 0, {BF, RA, RB}},
3557 5031
3558{ "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA0, RB } }, 5032{"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
3559{ "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
3560 5033
3561{ "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA0, RB } }, 5034{"stvx", X(31,231), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5035{"stqfcmx", APU(31,231,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
3562 5036
3563{ "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA0, RB } }, 5037{"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5038{"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5039{"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5040{"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
3564 5041
3565{ "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } }, 5042{"mulld", XO(31,233,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
3566{ "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } }, 5043{"mulld.", XO(31,233,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
3567 5044
3568{ "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } }, 5045{"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
3569{ "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } }, 5046{"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5047{"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5048{"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
3570 5049
3571{ "prtyw", X(31,154), XRB_MASK, POWER6, { RA, RS } }, 5050{"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5051{"muls", XO(31,235,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5052{"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5053{"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
3572 5054
3573{ "wrteei", X(31,163), XE_MASK, PPC403 | BOOKE, { E } }, 5055{"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}},
5056{"msgclr", XRTRA(31,238,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}},
5057{"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}},
5058{"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}},
3574 5059
3575{ "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }}, 5060{"mtfprwz", X(31,243), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
3576{ "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }}, 5061{"mtvrwz", X(31,243)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
5062{"mtvsrwz", X(31,243), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
3577 5063
3578{ "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, MTMSRD_L } }, 5064{"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, 0, {RA0, RB}},
5065{"dcbtst", X(31,246), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
5066{"dcbtst", X(31,246), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},
5067{"dcbtst", X(31,246), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
3579 5068
3580{ "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } }, 5069{"stbux", X(31,247), X_MASK, COM, 0, {RS, RAS, RB}},
3581 5070
3582{ "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } }, 5071{"slliq", XRC(31,248,0), X_MASK, M601, 0, {RA, RS, SH}},
3583{ "stux", X(31,183), X_MASK, PWRCOM, { RS, RA0, RB } }, 5072{"slliq.", XRC(31,248,1), X_MASK, M601, 0, {RA, RS, SH}},
3584 5073
3585{ "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } }, 5074{"bpermd", X(31,252), X_MASK, POWER7|PPCA2, 0, {RA, RS, RB}},
3586{ "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
3587 5075
3588{ "prtyd", X(31,186), XRB_MASK, POWER6, { RA, RS } }, 5076{"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
3589 5077
3590{ "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } }, 5078{"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA}},
5079{"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, 0, {RS, RA}},
3591 5080
3592{ "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } }, 5081{"lvexbx", X(31,261), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
3593{ "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3594{ "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3595{ "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3596{ "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3597{ "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3598{ "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3599{ "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3600 5082
3601{ "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } }, 5083{"icbt", X(31,262), XRT_MASK, PPC403, 0, {RA, RB}},
3602{ "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3603{ "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3604{ "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3605{ "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3606{ "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3607{ "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3608{ "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3609 5084
3610{ "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } }, 5085{"lvepxl", X(31,263), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
3611 5086
3612{ "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA0, RB } }, 5087{"ldfcmx", APU(31,263,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5088{"doz", XO(31,264,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5089{"doz.", XO(31,264,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
3613 5090
3614{ "stbx", X(31,215), X_MASK, COM, { RS, RA0, RB } }, 5091{"modud", X(31,265), X_MASK, POWER9, 0, {RT, RA, RB}},
3615 5092
3616{ "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } }, 5093{"add", XO(31,266,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
3617{ "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } }, 5094{"cax", XO(31,266,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5095{"add.", XO(31,266,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5096{"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
3618 5097
3619{ "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } }, 5098{"moduw", X(31,267), X_MASK, POWER9, 0, {RT, RA, RB}},
3620{ "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
3621 5099
3622{ "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA0, RB } }, 5100{"lxvx", X(31,268), XX1_MASK|1<<6, PPCVSX3, 0, {XT6, RA0, RB}},
5101{"lxvl", X(31,269), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
3623 5102
3624{ "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }}, 5103{"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2, 0, {0}},
3625 5104
3626{ "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } }, 5105{"tlbiel", X(31,274), X_MASK|1<<20,POWER9, PPC476, {RB, RSO, RIC, PRS, X_R}},
3627{ "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } }, 5106{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, POWER9|PPC476, {RB, LOPT}},
3628{ "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3629{ "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3630{ "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3631{ "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3632{ "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3633{ "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3634 5107
3635{ "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } }, 5108{"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}},
3636{ "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3637{ "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3638{ "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3639 5109
3640{ "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } }, 5110{"lqarx", X(31,276), XEH_MASK, POWER8, 0, {RTQ, RAX, RBX, EH}},
3641{ "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3642{ "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3643{ "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3644{ "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3645{ "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3646{ "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3647{ "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3648 5111
3649{ "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 5112{"lscbx", XRC(31,277,0), X_MASK, M601, 0, {RT, RA, RB}},
3650{ "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 5113{"lscbx.", XRC(31,277,1), X_MASK, M601, 0, {RT, RA, RB}},
3651{ "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3652{ "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3653{ "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3654{ "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3655{ "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3656{ "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3657 5114
3658{ "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }}, 5115{"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, 0, {RA0, RB}},
3659{ "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } }, 5116{"dcbt", X(31,278), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
3660{ "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } }, 5117{"dcbt", X(31,278), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},
5118{"dcbt", X(31,278), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
3661 5119
3662{ "dcbtst", X(31,246), X_MASK, PPC, { CT, RA, RB } }, 5120{"lhzx", X(31,279), X_MASK, COM, 0, {RT, RA0, RB}},
3663 5121
3664{ "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } }, 5122{"cdtbcd", X(31,282), XRB_MASK, POWER6, 0, {RA, RS}},
3665
3666{ "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
3667{ "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
3668
3669{ "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } },
3670
3671{ "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } },
3672
3673{ "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } },
3674
3675{ "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
3676{ "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
3677{ "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
3678{ "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } },
3679
3680{ "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3681{ "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3682{ "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3683{ "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3684{ "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3685{ "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3686{ "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3687{ "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3688
3689{ "tlbiel", X(31,274), XRTLRA_MASK, POWER4, { RB, L } },
3690
3691{ "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } },
3692
3693{ "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
3694{ "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
3695
3696{ "dcbt", X(31,278), X_MASK, PPC, { CT, RA, RB } },
3697
3698{ "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } },
3699
3700{ "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
3701{ "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
3702
3703{ "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } },
3704
3705{ "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA0, RB } },
3706
3707{ "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } },
3708{ "tlbi", X(31,306), XRT_MASK, POWER, { RA0, RB } },
3709
3710{ "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
3711
3712{ "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } },
3713
3714{ "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
3715{ "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
3716
3717{ "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } },
3718
3719{ "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } },
3720{ "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } },
3721{ "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } },
3722{ "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } },
3723{ "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } },
3724{ "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } },
3725{ "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } },
3726{ "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } },
3727{ "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } },
3728{ "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } },
3729{ "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } },
3730{ "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } },
3731{ "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } },
3732{ "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } },
3733{ "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } },
3734{ "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } },
3735{ "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } },
3736{ "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } },
3737{ "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } },
3738{ "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } },
3739{ "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } },
3740{ "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } },
3741{ "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } },
3742{ "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } },
3743{ "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } },
3744{ "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } },
3745{ "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } },
3746{ "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } },
3747{ "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } },
3748{ "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } },
3749{ "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } },
3750{ "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } },
3751{ "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } },
3752{ "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } },
3753{ "mfdcr", X(31,323), X_MASK, PPC403 | BOOKE, { RT, SPR } },
3754
3755{ "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
3756{ "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
3757{ "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
3758{ "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
3759
3760{ "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
3761
3762{ "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } },
3763{ "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } },
3764{ "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } },
3765{ "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } },
3766{ "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } },
3767{ "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
3768{ "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
3769{ "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } },
3770{ "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
3771{ "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } },
3772{ "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } },
3773{ "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
3774{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
3775{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
3776{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
3777{ "mfcfar", XSPR(31,339,28), XSPR_MASK, POWER6, { RT } },
3778{ "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } },
3779{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
3780{ "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } },
3781{ "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } },
3782{ "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } },
3783{ "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
3784{ "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } },
3785{ "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
3786{ "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } },
3787{ "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } },
3788{ "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } },
3789{ "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } },
3790{ "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } },
3791{ "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } },
3792{ "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } },
3793{ "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } },
3794{ "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } },
3795{ "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } },
3796{ "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } },
3797{ "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } },
3798{ "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } },
3799{ "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } },
3800{ "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } },
3801{ "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } },
3802{ "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } },
3803{ "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } },
3804{ "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } },
3805{ "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
3806{ "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3807{ "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } },
3808{ "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3809{ "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } },
3810{ "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } },
3811{ "mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, { RT, SPRG } },
3812{ "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
3813{ "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
3814{ "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } },
3815{ "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } },
3816{ "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405 | BOOKE, { RT } },
3817{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405 | BOOKE, { RT } },
3818{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405 | BOOKE, { RT } },
3819{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405 | BOOKE, { RT } },
3820{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } },
3821{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
3822{ "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } },
3823{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
3824{ "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } },
3825{ "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
3826{ "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } },
3827{ "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } },
3828{ "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } },
3829{ "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
3830{ "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } },
3831{ "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } },
3832{ "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
3833{ "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } },
3834{ "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
3835{ "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } },
3836{ "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
3837{ "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } },
3838{ "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
3839{ "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } },
3840{ "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
3841{ "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } },
3842{ "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
3843{ "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } },
3844{ "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
3845{ "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } },
3846{ "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } },
3847{ "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } },
3848{ "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } },
3849{ "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } },
3850{ "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } },
3851{ "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } },
3852{ "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } },
3853{ "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } },
3854{ "mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, { RT } },
3855{ "mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, { RT } },
3856{ "mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, { RT } },
3857{ "mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, { RT } },
3858{ "mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, { RT } },
3859{ "mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, { RT } },
3860{ "mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, { RT } },
3861{ "mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, { RT } },
3862{ "mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, { RT } },
3863{ "mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, { RT } },
3864{ "mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, { RT } },
3865{ "mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, { RT } },
3866{ "mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, { RT } },
3867{ "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } },
3868{ "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } },
3869{ "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } },
3870{ "mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, { RT } },
3871{ "mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, { RT } },
3872{ "mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, { RT } },
3873{ "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } },
3874{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3875{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3876{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3877{ "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3878{ "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } },
3879{ "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } },
3880{ "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } },
3881{ "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } },
3882{ "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } },
3883{ "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } },
3884{ "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } },
3885{ "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } },
3886{ "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } },
3887{ "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } },
3888{ "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } },
3889{ "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } },
3890{ "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } },
3891{ "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } },
3892{ "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } },
3893{ "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } },
3894{ "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } },
3895{ "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } },
3896{ "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } },
3897{ "mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, { RT } },
3898{ "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } },
3899{ "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } },
3900{ "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } },
3901{ "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } },
3902{ "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } },
3903{ "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } },
3904{ "mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, { RT } },
3905{ "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } },
3906{ "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } },
3907{ "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } },
3908{ "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } },
3909{ "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } },
3910{ "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } },
3911{ "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } },
3912{ "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } },
3913{ "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } },
3914{ "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } },
3915{ "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } },
3916{ "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } },
3917{ "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
3918{ "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } },
3919{ "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } },
3920{ "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } },
3921{ "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } },
3922{ "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } },
3923{ "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } },
3924{ "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } },
3925{ "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } },
3926{ "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } },
3927{ "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } },
3928{ "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } },
3929{ "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } },
3930{ "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
3931{ "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } },
3932{ "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } },
3933{ "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } },
3934{ "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } },
3935{ "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } },
3936{ "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } },
3937{ "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } },
3938{ "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } },
3939{ "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } },
3940{ "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } },
3941{ "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } },
3942{ "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } },
3943{ "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } },
3944{ "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } },
3945{ "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } },
3946{ "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } },
3947{ "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } },
3948{ "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } },
3949{ "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
3950
3951{ "lwax", X(31,341), X_MASK, PPC64, { RT, RA0, RB } },
3952
3953{ "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3954{ "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3955
3956{ "lhax", X(31,343), X_MASK, COM, { RT, RA0, RB } },
3957
3958{ "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA0, RB } },
3959
3960{ "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3961{ "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3962
3963{ "dccci", X(31,454), XRT_MASK, PPC403|PPC440, { RA, RB } },
3964
3965{ "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
3966{ "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
3967{ "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } },
3968{ "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } },
3969
3970{ "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } },
3971{ "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } },
3972{ "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } },
3973{ "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } },
3974
3975{ "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
3976
3977{ "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
3978
3979{ "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
3980
3981{ "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } },
3982
3983{ "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } },
3984
3985{ "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }},
3986
3987{ "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3988{ "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3989
3990{ "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3991{ "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3992
3993{ "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }},
3994
3995{ "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
3996
3997{ "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } },
3998
3999{ "cmpb", X(31,508), X_MASK, POWER6, { RA, RS, RB } },
4000
4001{ "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
4002
4003{ "lfdpx", X(31,791), X_MASK, POWER6, { FRT, RA, RB } },
4004
4005{ "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
4006
4007{ "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
4008
4009{ "stfdpx", X(31,919), X_MASK, POWER6, { FRS, RA, RB } },
4010
4011{ "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
4012
4013{ "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
4014{ "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
4015
4016{ "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } },
4017{ "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } },
4018
4019{ "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA0, RB } },
4020
4021{ "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
4022
4023{ "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
4024
4025{ "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
4026
4027{ "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } },
4028
4029{ "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
4030{ "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
4031{ "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
4032{ "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
4033
4034{ "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RS } },
4035{ "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RS } },
4036{ "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RS } },
4037{ "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RS } },
4038{ "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RS } },
4039{ "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RS } },
4040{ "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RS } },
4041{ "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RS } },
4042{ "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RS } },
4043{ "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RS } },
4044{ "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RS } },
4045{ "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RS } },
4046{ "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RS } },
4047{ "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RS } },
4048{ "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RS } },
4049{ "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RS } },
4050{ "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RS } },
4051{ "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RS } },
4052{ "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RS } },
4053{ "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RS } },
4054{ "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RS } },
4055{ "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RS } },
4056{ "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RS } },
4057{ "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RS } },
4058{ "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RS } },
4059{ "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RS } },
4060{ "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RS } },
4061{ "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RS } },
4062{ "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RS } },
4063{ "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RS } },
4064{ "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RS } },
4065{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RS } },
4066{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RS } },
4067{ "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RS } },
4068{ "mtdcr", X(31,451), X_MASK, PPC403 | BOOKE, { SPR, RS } },
4069
4070{ "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4071{ "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4072
4073{ "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4074{ "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4075{ "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4076{ "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4077
4078{ "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4079{ "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4080
4081{ "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
4082{ "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
4083{ "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
4084{ "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
4085
4086{ "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } },
4087{ "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } },
4088{ "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } },
4089{ "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } },
4090{ "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
4091{ "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } },
4092{ "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } },
4093{ "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } },
4094{ "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } },
4095{ "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } },
4096{ "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
4097{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } },
4098{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
4099{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
4100{ "mtcfar", XSPR(31,467,28), XSPR_MASK, POWER6, { RS } },
4101{ "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } },
4102{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS } },
4103{ "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } },
4104{ "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } },
4105{ "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } },
4106{ "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } },
4107{ "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RS } },
4108{ "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } },
4109{ "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RS } },
4110{ "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } },
4111{ "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RS } },
4112{ "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RS } },
4113{ "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RS } },
4114{ "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RS } },
4115{ "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RS } },
4116{ "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RS } },
4117{ "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RS } },
4118{ "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RS } },
4119{ "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RS } },
4120{ "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RS } },
4121{ "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RS } },
4122{ "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RS } },
4123{ "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RS } },
4124{ "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RS } },
4125{ "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RS } },
4126{ "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RS } },
4127{ "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RS } },
4128{ "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } },
4129{ "mtsprg", XSPR(31,467,256), XSPRG_MASK,PPC, { SPRG, RS } },
4130{ "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RS } },
4131{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RS } },
4132{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RS } },
4133{ "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RS } },
4134{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405 | BOOKE, { RS } },
4135{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405 | BOOKE, { RS } },
4136{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405 | BOOKE, { RS } },
4137{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405 | BOOKE, { RS } },
4138{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
4139{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
4140{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
4141{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
4142{ "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } },
4143{ "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RS } },
4144{ "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } },
4145{ "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RS } },
4146{ "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } },
4147{ "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RS } },
4148{ "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } },
4149{ "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } },
4150{ "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RS } },
4151{ "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } },
4152{ "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RS } },
4153{ "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } },
4154{ "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RS } },
4155{ "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } },
4156{ "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RS } },
4157{ "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } },
4158{ "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RS } },
4159{ "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } },
4160{ "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RS } },
4161{ "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } },
4162{ "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RS } },
4163{ "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } },
4164{ "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RS } },
4165{ "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } },
4166{ "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RS } },
4167{ "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } },
4168{ "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RS } },
4169{ "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } },
4170{ "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } },
4171{ "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } },
4172{ "mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, { RS } },
4173{ "mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, { RS } },
4174{ "mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, { RS } },
4175{ "mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, { RS } },
4176{ "mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, { RS } },
4177{ "mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, { RS } },
4178{ "mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, { RS } },
4179{ "mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, { RS } },
4180{ "mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, { RS } },
4181{ "mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, { RS } },
4182{ "mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, { RS } },
4183{ "mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, { RS } },
4184{ "mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, { RS } },
4185{ "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } },
4186{ "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } },
4187{ "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } },
4188{ "mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, { RS } },
4189{ "mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, { RS } },
4190{ "mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, { RS } },
4191{ "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } },
4192{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4193{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4194{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4195{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4196{ "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } },
4197{ "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } },
4198{ "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
4199{ "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RS } },
4200{ "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RS } },
4201{ "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RS } },
4202{ "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RS } },
4203{ "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RS } },
4204{ "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RS } },
4205{ "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RS } },
4206{ "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RS } },
4207{ "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RS } },
4208{ "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RS } },
4209{ "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RS } },
4210{ "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RS } },
4211{ "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RS } },
4212{ "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RS } },
4213{ "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RS } },
4214{ "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RS } },
4215{ "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RS } },
4216{ "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RS } },
4217{ "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RS } },
4218{ "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RS } },
4219{ "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RS } },
4220{ "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RS } },
4221{ "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RS } },
4222{ "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RS } },
4223{ "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RS } },
4224{ "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RS } },
4225{ "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RS } },
4226{ "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RS } },
4227{ "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RS } },
4228{ "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RS } },
4229{ "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RS } },
4230{ "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RS } },
4231{ "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RS } },
4232{ "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RS } },
4233{ "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RS } },
4234{ "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RS } },
4235{ "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RS } },
4236{ "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RS } },
4237{ "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RS } },
4238{ "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
4239
4240{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
4241
4242{ "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
4243{ "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
4244
4245{ "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } },
4246
4247{ "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }},
4248
4249{ "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
4250
4251{ "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }},
4252
4253{ "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } },
4254{ "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4255{ "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } },
4256{ "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } },
4257{ "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4258{ "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } },
4259
4260{ "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4261{ "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4262{ "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4263{ "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4264
4265{ "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4266{ "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4267
4268{ "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
4269{ "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
4270{ "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
4271{ "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
4272 5123
4273{ "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }}, 5124{"eqv", XRC(31,284,0), X_MASK, COM, 0, {RA, RS, RB}},
5125{"eqv.", XRC(31,284,1), X_MASK, COM, 0, {RA, RS, RB}},
4274 5126
4275{ "slbia", X(31,498), 0xffffffff, PPC64, { 0 } }, 5127{"lhepx", X(31,287), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
4276 5128
4277{ "cli", X(31,502), XRB_MASK, POWER, { RT, RA } }, 5129{"mfdcrux", X(31,291), X_MASK, PPC464, 0, {RS, RA}},
4278 5130
4279{ "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } }, 5131{"lvexhx", X(31,293), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5132{"lvepx", X(31,295), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
4280 5133
4281{ "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } }, 5134{"lxvll", X(31,301), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
4282 5135
4283{ "bblels", X(31,518), X_MASK, PPCBRLK, { 0 }}, 5136{"mfbhrbe", X(31,302), X_MASK, POWER8, 0, {RT, BHRBE}},
4284{ "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, { BF } }, 5137
5138{"tlbie", X(31,306), X_MASK|1<<20,POWER9, TITAN, {RB, RS, RIC, PRS, X_R}},
5139{"tlbie", X(31,306), XRA_MASK, POWER7, POWER9|TITAN, {RB, RS}},
5140{"tlbie", X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, LOPT}},
5141{"tlbi", X(31,306), XRT_MASK, POWER, 0, {RA0, RB}},
5142
5143{"mfvsrld", X(31,307), XX1RB_MASK, PPCVSX3, 0, {RA, XS6}},
5144
5145{"ldmx", X(31,309), X_MASK, POWER9, 0, {RT, RA0, RB}},
5146
5147{"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
5148
5149{"lhzux", X(31,311), X_MASK, COM, 0, {RT, RAL, RB}},
5150
5151{"cbcdtd", X(31,314), XRB_MASK, POWER6, 0, {RA, RS}},
5152
5153{"xor", XRC(31,316,0), X_MASK, COM, 0, {RA, RS, RB}},
5154{"xor.", XRC(31,316,1), X_MASK, COM, 0, {RA, RS, RB}},
5155
5156{"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
5157
5158{"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, 0, {RT}},
5159{"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, 0, {RT}},
5160{"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, 0, {RT}},
5161{"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, 0, {RT}},
5162{"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, 0, {RT}},
5163{"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, 0, {RT}},
5164{"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, 0, {RT}},
5165{"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, 0, {RT}},
5166{"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, 0, {RT}},
5167{"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, 0, {RT}},
5168{"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, 0, {RT}},
5169{"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, 0, {RT}},
5170{"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, 0, {RT}},
5171{"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, 0, {RT}},
5172{"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, 0, {RT}},
5173{"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, 0, {RT}},
5174{"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, 0, {RT}},
5175{"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, 0, {RT}},
5176{"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, 0, {RT}},
5177{"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, 0, {RT}},
5178{"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, 0, {RT}},
5179{"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, 0, {RT}},
5180{"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, 0, {RT}},
5181{"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, 0, {RT}},
5182{"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, 0, {RT}},
5183{"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, 0, {RT}},
5184{"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, 0, {RT}},
5185{"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, 0, {RT}},
5186{"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, 0, {RT}},
5187{"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, 0, {RT}},
5188{"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, 0, {RT}},
5189{"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, 0, {RT}},
5190{"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, 0, {RT}},
5191{"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, 0, {RT}},
5192{"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {RT, SPR}},
5193{"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, 0, {RT, SPR}},
5194
5195{"lvexwx", X(31,325), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5196
5197{"dcread", X(31,326), X_MASK, PPC476|TITAN, 0, {RT, RA0, RB}},
5198
5199{"div", XO(31,331,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5200{"div.", XO(31,331,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
5201
5202{"lxvdsx", X(31,332), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
5203
5204{"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, 0, {RT, PMR}},
5205{"mftmr", X(31,366), X_MASK, PPCTMR|E6500, 0, {RT, TMR}},
5206
5207{"slbsync", X(31,338), 0xffffffff, POWER9, 0, {0}},
5208
5209{"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, 0, {RT}},
5210{"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, 0, {RT}},
5211{"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, TITAN, {RT}},
5212{"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, TITAN, {RT}},
5213{"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, 0, {RT}},
5214{"mflr", XSPR(31,339, 8), XSPR_MASK, COM, 0, {RT}},
5215{"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, 0, {RT}},
5216{"mfdscr", XSPR(31,339, 17), XSPR_MASK, POWER6, 0, {RT}},
5217{"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, 0, {RT}},
5218{"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}},
5219{"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN, {RT}},
5220{"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, MFDEC1, {RT}},
5221{"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, 0, {RT}},
5222{"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, TITAN, {RT}},
5223{"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, 0, {RT}},
5224{"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, 0, {RT}},
5225{"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, 0, {RT}},
5226{"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, 0, {RT}},
5227{"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, 0, {RT}},
5228{"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, 0, {RT}},
5229{"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, 0, {RT}},
5230{"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, 0, {RT}},
5231{"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, 0, {RT}},
5232{"mfctrl", XSPR(31,339,136), XSPR_MASK, POWER4, 0, {RT}},
5233{"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, 0, {RT}},
5234{"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, 0, {RT}},
5235{"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, 0, {RT}},
5236{"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, 0, {RT}},
5237{"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, 0, {RT}},
5238{"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, 0, {RT}},
5239{"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, 0, {RT}},
5240{"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, 0, {RT}},
5241{"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, 0, {RT}},
5242{"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, 0, {RT}},
5243{"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, 0, {RT}},
5244{"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, 0, {RT}},
5245{"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, 0, {RT}},
5246{"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, 0, {RT}},
5247{"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, 0, {RT}},
5248{"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, 0, {RT}},
5249{"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, 0, {RT}},
5250{"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, 0, {RT}},
5251{"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, 0, {RT, SPRG}},
5252{"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5253{"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5254{"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5255{"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5256{"mftbu", XSPR(31,339,269), XSPR_MASK, POWER4|BOOKE, 0, {RT}},
5257{"mftb", X(31,339), X_MASK, POWER4|BOOKE, 0, {RT, TBR}},
5258{"mftbl", XSPR(31,339,268), XSPR_MASK, POWER4|BOOKE, 0, {RT}},
5259{"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, 0, {RT}},
5260{"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, 0, {RT}},
5261{"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, 0, {RT}},
5262{"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, 0, {RT}},
5263{"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, 0, {RT}},
5264{"mfear", XSPR(31,339,282), XSPR_MASK, PPC, TITAN, {RT}},
5265{"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, 0, {RT}},
5266{"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, 0, {RT}},
5267{"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, 0, {RT}},
5268{"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, 0, {RT}},
5269{"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, 0, {RT}},
5270{"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, 0, {RT}},
5271{"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, 0, {RT}},
5272{"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, 0, {RT}},
5273{"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, 0, {RT}},
5274{"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, 0, {RT}},
5275{"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, 0, {RT}},
5276{"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, 0, {RT}},
5277{"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, 0, {RT}},
5278{"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, 0, {RT}},
5279{"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, 0, {RT}},
5280{"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, 0, {RT}},
5281{"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, 0, {RT}},
5282{"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, 0, {RT}},
5283{"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, 0, {RT}},
5284{"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, 0, {RT}},
5285{"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, 0, {RT}},
5286{"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, 0, {RT}},
5287{"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, 0, {RT}},
5288{"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, 0, {RT}},
5289{"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, 0, {RT}},
5290{"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, 0, {RT}},
5291{"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, 0, {RT}},
5292{"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, 0, {RT}},
5293{"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, 0, {RT}},
5294{"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, 0, {RT}},
5295{"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, 0, {RT}},
5296{"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, 0, {RT}},
5297{"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, 0, {RT}},
5298{"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, 0, {RT}},
5299{"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, 0, {RT}},
5300{"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, 0, {RT}},
5301{"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5302{"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, 0, {RT}},
5303{"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5304{"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, 0, {RT}},
5305{"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, 0, {RT}},
5306{"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5307{"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5308{"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, 0, {RT}},
5309{"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, 0, {RT}},
5310{"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, 0, {RT}},
5311{"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, 0, {RT}},
5312{"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, 0, {RT}},
5313{"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, 0, {RT}},
5314{"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, 0, {RT}},
5315{"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, 0, {RT}},
5316{"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, 0, {RT}},
5317{"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN, {RT}},
5318{"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, 0, {RT}},
5319{"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, 0, {RT}},
5320{"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, 0, {RT}},
5321{"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, 0, {RT}},
5322{"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, 0, {RT}},
5323{"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, 0, {RT}},
5324{"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, 0, {RT}},
5325{"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, 0, {RT}},
5326{"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, 0, {RT}},
5327{"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, 0, {RT}},
5328{"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, 0, {RT}},
5329{"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, 0, {RT}},
5330{"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, 0, {RT}},
5331{"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, 0, {RT}},
5332{"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, 0, {RT}},
5333{"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, 0, {RT}},
5334{"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, 0, {RT}},
5335{"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, 0, {RT}},
5336{"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, 0, {RT}},
5337{"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, 0, {RT}},
5338{"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, 0, {RT}},
5339{"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, 0, {RT}},
5340{"mfivndx", XSPR(31,339,880), XSPR_MASK, TITAN, 0, {RT}},
5341{"mfdvndx", XSPR(31,339,881), XSPR_MASK, TITAN, 0, {RT}},
5342{"mfivlim", XSPR(31,339,882), XSPR_MASK, TITAN, 0, {RT}},
5343{"mfdvlim", XSPR(31,339,883), XSPR_MASK, TITAN, 0, {RT}},
5344{"mfclcsr", XSPR(31,339,884), XSPR_MASK, TITAN, 0, {RT}},
5345{"mfccr1", XSPR(31,339,888), XSPR_MASK, TITAN, 0, {RT}},
5346{"mfppr", XSPR(31,339,896), XSPR_MASK, POWER7, 0, {RT}},
5347{"mfppr32", XSPR(31,339,898), XSPR_MASK, POWER7, 0, {RT}},
5348{"mfrstcfg", XSPR(31,339,923), XSPR_MASK, TITAN, 0, {RT}},
5349{"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK, TITAN, 0, {RT}},
5350{"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK, TITAN, 0, {RT}},
5351{"mficdbtr", XSPR(31,339,927), XSPR_MASK, TITAN, 0, {RT}},
5352{"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, 0, {RT}},
5353{"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, 0, {RT}},
5354{"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, 0, {RT}},
5355{"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, 0, {RT}},
5356{"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, 0, {RT}},
5357{"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, 0, {RT}},
5358{"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, 0, {RT}},
5359{"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, 0, {RT}},
5360{"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, 0, {RT}},
5361{"mfmmucr", XSPR(31,339,946), XSPR_MASK, TITAN, 0, {RT}},
5362{"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, 0, {RT}},
5363{"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, 0, {RT}},
5364{"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, 0, {RT}},
5365{"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, 0, {RT}},
5366{"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, 0, {RT}},
5367{"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, 0, {RT}},
5368{"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, 0, {RT}},
5369{"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, 0, {RT}},
5370{"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, 0, {RT}},
5371{"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, 0, {RT}},
5372{"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, 0, {RT}},
5373{"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, 0, {RT}},
5374{"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, 0, {RT}},
5375{"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, 0, {RT}},
5376{"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, 0, {RT}},
5377{"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, 0, {RT}},
5378{"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, 0, {RT}},
5379{"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, 0, {RT}},
5380{"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, 0, {RT}},
5381{"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, 0, {RT}},
5382{"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, 0, {RT}},
5383{"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, 0, {RT}},
5384{"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, 0, {RT}},
5385{"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, 0, {RT}},
5386{"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, 0, {RT}},
5387{"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, 0, {RT}},
5388{"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, 0, {RT}},
5389{"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, 0, {RT}},
5390{"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, 0, {RT}},
5391{"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, 0, {RT}},
5392{"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, 0, {RT}},
5393{"mfdbdr", XSPR(31,339,1011), XSPR_MASK, TITAN, 0, {RS}},
5394{"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, 0, {RT}},
5395{"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, 0, {RT}},
5396{"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, 0, {RT}},
5397{"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, 0, {RT}},
5398{"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, 0, {RT}},
5399{"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, 0, {RT}},
5400{"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, 0, {RT}},
5401{"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, 0, {RT}},
5402{"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, 0, {RT}},
5403{"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, 0, {RT}},
5404{"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, 0, {RT}},
5405{"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, 0, {RT}},
5406{"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, 0, {RT}},
5407{"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, 0, {RT}},
5408{"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, 0, {RT}},
5409{"mfspr", X(31,339), X_MASK, COM, 0, {RT, SPR}},
5410
5411{"lwax", X(31,341), X_MASK, PPC64, 0, {RT, RA0, RB}},
5412
5413{"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
5414
5415{"lhax", X(31,343), X_MASK, COM, 0, {RT, RA0, RB}},
5416
5417{"lvxl", X(31,359), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
5418
5419{"abs", XO(31,360,0,0), XORB_MASK, M601, 0, {RT, RA}},
5420{"abs.", XO(31,360,0,1), XORB_MASK, M601, 0, {RT, RA}},
5421
5422{"divs", XO(31,363,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5423{"divs.", XO(31,363,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
5424
5425{"lxvwsx", X(31,364), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
5426
5427{"tlbia", X(31,370), 0xffffffff, PPC, E500|TITAN, {0}},
5428
5429{"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371|POWER4, {RT}},
5430{"mftb", X(31,371), X_MASK, PPC, NO371|POWER4, {RT, TBR}},
5431{"mftbl", XSPR(31,371,268), XSPR_MASK, PPC, NO371|POWER4, {RT}},
5432
5433{"lwaux", X(31,373), X_MASK, PPC64, 0, {RT, RAL, RB}},
5434
5435{"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
5436
5437{"lhaux", X(31,375), X_MASK, COM, 0, {RT, RAL, RB}},
5438
5439{"popcntw", X(31,378), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}},
5440
5441{"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}},
5442{"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, 0, {RA, RS}},
5443
5444{"stvexbx", X(31,389), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5445
5446{"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
5447{"stdfcmx", APU(31,391,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5448
5449{"divdeu", XO(31,393,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5450{"divdeu.", XO(31,393,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5451{"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5452{"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5453
5454{"stxvx", X(31,396), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
5455{"stxvl", X(31,397), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
5456
5457{"dcblce", X(31,398), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
5458
5459{"slbmte", X(31,402), XRA_MASK, PPC64, 0, {RS, RB}},
5460
5461{"mtvsrws", X(31,403), XX1RB_MASK, PPCVSX3, 0, {XT6, RA}},
5462
5463{"pbt.", XRC(31,404,1), X_MASK, POWER8, 0, {RS, RA0, RB}},
5464
5465{"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},
5466{"icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},
5467
5468{"sthx", X(31,407), X_MASK, COM, 0, {RS, RA0, RB}},
5469
5470{"orc", XRC(31,412,0), X_MASK, COM, 0, {RA, RS, RB}},
5471{"orc.", XRC(31,412,1), X_MASK, COM, 0, {RA, RS, RB}},
5472
5473{"sthepx", X(31,415), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
5474
5475{"mtdcrux", X(31,419), X_MASK, PPC464, 0, {RA, RS}},
5476
5477{"stvexhx", X(31,421), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5478
5479{"dcblq.", XRC(31,422,1), X_MASK, E6500, 0, {CT, RA0, RB}},
5480
5481{"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5482{"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5483{"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5484{"divwe.", XO(31,427,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5485
5486{"stxvll", X(31,429), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
5487
5488{"clrbhrb", X(31,430), 0xffffffff, POWER8, 0, {0}},
5489
5490{"slbie", X(31,434), XRTRA_MASK, PPC64, 0, {RB}},
5491
5492{"mtvsrdd", X(31,435), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
5493
5494{"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
5495
5496{"sthux", X(31,439), X_MASK, COM, 0, {RS, RAS, RB}},
5497
5498{"mdors", 0x7f9ce378, 0xffffffff, E500MC, 0, {0}},
5499
5500{"miso", 0x7f5ad378, 0xffffffff, E6500, 0, {0}},
5501
5502/* The "yield", "mdoio" and "mdoom" instructions are extended mnemonics for
5503 "or rX,rX,rX", with rX being r27, r29 and r30 respectively. */
5504{"yield", 0x7f7bdb78, 0xffffffff, POWER7, 0, {0}},
5505{"mdoio", 0x7fbdeb78, 0xffffffff, POWER7, 0, {0}},
5506{"mdoom", 0x7fdef378, 0xffffffff, POWER7, 0, {0}},
5507{"mr", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RBS}},
5508{"or", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RB}},
5509{"mr.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RBS}},
5510{"or.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RB}},
5511
5512{"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, 0, {RS}},
5513{"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, 0, {RS}},
5514{"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, 0, {RS}},
5515{"mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, 0, {RS}},
5516{"mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, 0, {RS}},
5517{"mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, 0, {RS}},
5518{"mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, 0, {RS}},
5519{"mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, 0, {RS}},
5520{"mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, 0, {RS}},
5521{"mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, 0, {RS}},
5522{"mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, 0, {RS}},
5523{"mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, 0, {RS}},
5524{"mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, 0, {RS}},
5525{"mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, 0, {RS}},
5526{"mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, 0, {RS}},
5527{"mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, 0, {RS}},
5528{"mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, 0, {RS}},
5529{"mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, 0, {RS}},
5530{"mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, 0, {RS}},
5531{"mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, 0, {RS}},
5532{"mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, 0, {RS}},
5533{"mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, 0, {RS}},
5534{"mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, 0, {RS}},
5535{"mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, 0, {RS}},
5536{"mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, 0, {RS}},
5537{"mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, 0, {RS}},
5538{"mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, 0, {RS}},
5539{"mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, 0, {RS}},
5540{"mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, 0, {RS}},
5541{"mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, 0, {RS}},
5542{"mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, 0, {RS}},
5543{"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, 0, {RS}},
5544{"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, 0, {RS}},
5545{"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, 0, {RS}},
5546{"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {SPR, RS}},
5547{"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, 0, {SPR, RS}},
5548
5549{"stvexwx", X(31,453), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5550
5551{"dccci", X(31,454), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, 0, {RAOPT, RBOPT}},
5552{"dci", X(31,454), XRARB_MASK, PPCA2|PPC476, 0, {CT}},
5553
5554{"divdu", XO(31,457,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5555{"divdu.", XO(31,457,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
5556
5557{"divwu", XO(31,459,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5558{"divwu.", XO(31,459,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5559
5560{"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, 0, {PMR, RS}},
5561{"mttmr", X(31,494), X_MASK, PPCTMR|E6500, 0, {TMR, RS}},
5562
5563{"slbieg", X(31,466), XRA_MASK, POWER9, 0, {RS, RB}},
5564
5565{"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, 0, {RS}},
5566{"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, 0, {RS}},
5567{"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, 0, {RS}},
5568{"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, 0, {RS}},
5569{"mtdscr", XSPR(31,467, 17), XSPR_MASK, POWER6, 0, {RS}},
5570{"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, 0, {RS}},
5571{"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, TITAN, {RS}},
5572{"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, TITAN, {RS}},
5573{"mtrtcu", XSPR(31,467, 20), XSPR_MASK, COM, TITAN, {RS}},
5574{"mtrtcl", XSPR(31,467, 21), XSPR_MASK, COM, TITAN, {RS}},
5575{"mtdec", XSPR(31,467, 22), XSPR_MASK, COM, 0, {RS}},
5576{"mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, 0, {RS}},
5577{"mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, TITAN, {RS}},
5578{"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, 0, {RS}},
5579{"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, 0, {RS}},
5580{"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, 0, {RS}},
5581{"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, 0, {RS}},
5582{"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, 0, {RS}},
5583{"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, 0, {RS}},
5584{"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, 0, {RS}},
5585{"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, 0, {RS}},
5586{"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, 0, {RS}},
5587{"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, 0, {RS}},
5588{"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, 0, {RS}},
5589{"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, 0, {RS}},
5590{"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, 0, {RS}},
5591{"mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, 0, {RS}},
5592{"mticr", XSPR(31,467,148), XSPR_MASK, PPC860, 0, {RS}},
5593{"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, 0, {RS}},
5594{"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, 0, {RS}},
5595{"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, 0, {RS}},
5596{"mtctrl", XSPR(31,467,152), XSPR_MASK, POWER4, 0, {RS}},
5597{"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, 0, {RS}},
5598{"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, 0, {RS}},
5599{"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, 0, {RS}},
5600{"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, 0, {RS}},
5601{"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, 0, {RS}},
5602{"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, 0, {RS}},
5603{"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, 0, {RS}},
5604{"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, 0, {RS}},
5605{"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, 0, {RS}},
5606{"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, 0, {RS}},
5607{"mtsprg", XSPR(31,467,256), XSPRG_MASK, PPC, 0, {SPRG, RS}},
5608{"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, 0, {RS}},
5609{"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, 0, {RS}},
5610{"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, 0, {RS}},
5611{"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, 0, {RS}},
5612{"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5613{"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5614{"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5615{"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5616{"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, 0, {RS}},
5617{"mtear", XSPR(31,467,282), XSPR_MASK, PPC, TITAN, {RS}},
5618{"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, 0, {RS}},
5619{"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, 0, {RS}},
5620{"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, 0, {RS}},
5621{"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, 0, {RS}},
5622{"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, 0, {RS}},
5623{"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, 0, {RS}},
5624{"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, 0, {RS}},
5625{"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, 0, {RS}},
5626{"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, 0, {RS}},
5627{"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, 0, {RS}},
5628{"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, 0, {RS}},
5629{"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, 0, {RS}},
5630{"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, 0, {RS}},
5631{"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, 0, {RS}},
5632{"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, 0, {RS}},
5633{"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, 0, {RS}},
5634{"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, 0, {RS}},
5635{"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, 0, {RS}},
5636{"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, 0, {RS}},
5637{"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, 0, {RS}},
5638{"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, 0, {RS}},
5639{"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, 0, {RS}},
5640{"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, 0, {RS}},
5641{"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, 0, {RS}},
5642{"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, 0, {RS}},
5643{"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, 0, {RS}},
5644{"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, 0, {RS}},
5645{"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, 0, {RS}},
5646{"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, 0, {RS}},
5647{"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, 0, {RS}},
5648{"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, 0, {RS}},
5649{"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, 0, {RS}},
5650{"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, 0, {RS}},
5651{"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, 0, {RS}},
5652{"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, 0, {RS}},
5653{"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, 0, {RS}},
5654{"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5655{"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, 0, {RS}},
5656{"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5657{"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, 0, {RS}},
5658{"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, 0, {RS}},
5659{"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5660{"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5661{"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, 0, {RS}},
5662{"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, 0, {RS}},
5663{"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, 0, {RS}},
5664{"mtivndx", XSPR(31,467,880), XSPR_MASK, TITAN, 0, {RS}},
5665{"mtdvndx", XSPR(31,467,881), XSPR_MASK, TITAN, 0, {RS}},
5666{"mtivlim", XSPR(31,467,882), XSPR_MASK, TITAN, 0, {RS}},
5667{"mtdvlim", XSPR(31,467,883), XSPR_MASK, TITAN, 0, {RS}},
5668{"mtclcsr", XSPR(31,467,884), XSPR_MASK, TITAN, 0, {RS}},
5669{"mtccr1", XSPR(31,467,888), XSPR_MASK, TITAN, 0, {RS}},
5670{"mtppr", XSPR(31,467,896), XSPR_MASK, POWER7, 0, {RS}},
5671{"mtppr32", XSPR(31,467,898), XSPR_MASK, POWER7, 0, {RS}},
5672{"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, 0, {RS}},
5673{"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, 0, {RS}},
5674{"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, 0, {RS}},
5675{"mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, 0, {RS}},
5676{"mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, 0, {RS}},
5677{"mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, 0, {RS}},
5678{"mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, 0, {RS}},
5679{"mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, 0, {RS}},
5680{"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, 0, {RS}},
5681{"mtrmmucr", XSPR(31,467,946), XSPR_MASK, TITAN, 0, {RS}},
5682{"mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, 0, {RS}},
5683{"mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, 0, {RS}},
5684{"mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, 0, {RS}},
5685{"mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, 0, {RS}},
5686{"mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, 0, {RS}},
5687{"mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, 0, {RS}},
5688{"mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, 0, {RS}},
5689{"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, 0, {RS}},
5690{"mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, 0, {RS}},
5691{"mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, 0, {RS}},
5692{"mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, 0, {RS}},
5693{"mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, 0, {RS}},
5694{"mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, 0, {RS}},
5695{"mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, 0, {RS}},
5696{"mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, 0, {RS}},
5697{"mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, 0, {RS}},
5698{"mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, 0, {RS}},
5699{"mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, 0, {RS}},
5700{"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, 0, {RS}},
5701{"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, 0, {RS}},
5702{"mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, 0, {RS}},
5703{"mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, 0, {RS}},
5704{"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, 0, {RS}},
5705{"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, 0, {RS}},
5706{"mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, 0, {RS}},
5707{"mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, 0, {RS}},
5708{"mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, 0, {RS}},
5709{"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, 0, {RS}},
5710{"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, 0, {RS}},
5711{"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, 0, {RS}},
5712{"mtdbdr", XSPR(31,467,1011), XSPR_MASK, TITAN, 0, {RS}},
5713{"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, 0, {RS}},
5714{"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, 0, {RS}},
5715{"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, 0, {RS}},
5716{"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, 0, {RS}},
5717{"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, 0, {RS}},
5718{"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, 0, {RS}},
5719{"mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, 0, {RS}},
5720{"mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, 0, {RS}},
5721{"mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, 0, {RS}},
5722{"mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, 0, {RS}},
5723{"mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, 0, {RS}},
5724{"mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, 0, {RS}},
5725{"mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, 0, {RS}},
5726{"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, 0, {RS}},
5727{"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, 0, {RS}},
5728{"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, 0, {RS}},
5729{"mtspr", X(31,467), X_MASK, COM, 0, {SPR, RS}},
5730
5731{"dcbi", X(31,470), XRT_MASK, PPC, 0, {RA0, RB}},
5732
5733{"nand", XRC(31,476,0), X_MASK, COM, 0, {RA, RS, RB}},
5734{"nand.", XRC(31,476,1), X_MASK, COM, 0, {RA, RS, RB}},
5735
5736{"dsn", X(31,483), XRT_MASK, E500MC, 0, {RA, RB}},
5737
5738{"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2|PPC476, {RT, RA0, RB}},
5739
5740{"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
5741
5742{"stvxl", X(31,487), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5743
5744{"nabs", XO(31,488,0,0), XORB_MASK, M601, 0, {RT, RA}},
5745{"nabs.", XO(31,488,0,1), XORB_MASK, M601, 0, {RT, RA}},
5746
5747{"divd", XO(31,489,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5748{"divd.", XO(31,489,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
5749
5750{"divw", XO(31,491,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5751{"divw.", XO(31,491,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5752
5753{"icbtlse", X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
5754
5755{"slbia", X(31,498), 0xff1fffff, POWER6, 0, {IH}},
5756{"slbia", X(31,498), 0xffffffff, PPC64, POWER6, {0}},
5757
5758{"cli", X(31,502), XRB_MASK, POWER, 0, {RT, RA}},
5759
5760{"popcntd", X(31,506), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}},
5761
5762{"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS, RB}},
5763
5764{"mcrxr", X(31,512), XBFRARB_MASK, COM, POWER7, {BF}},
5765
5766{"lbdcbx", X(31,514), X_MASK, E200Z4, 0, {RT, RA, RB}},
5767{"lbdx", X(31,515), X_MASK, E500MC, 0, {RT, RA, RB}},
4285 5768
4286{ "clcs", X(31,531), XRB_MASK, M601, { RT, RA } }, 5769{"bblels", X(31,518), X_MASK, PPCBRLK, 0, {0}},
4287 5770
4288{ "ldbrx", X(31,532), X_MASK, CELL, { RT, RA0, RB } }, 5771{"lvlx", X(31,519), X_MASK, CELL, 0, {VD, RA0, RB}},
5772{"lbfcmux", APU(31,519,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4289 5773
4290{ "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA0, RB } }, 5774{"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4291{ "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } }, 5775{"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5776{"subco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
5777{"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5778{"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5779{"subco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
4292 5780
4293{ "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA0, RB } }, 5781{"addco", XO(31,10,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4294{ "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } }, 5782{"ao", XO(31,10,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5783{"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5784{"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4295 5785
4296{ "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } }, 5786{"lxsspx", X(31,524), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
4297 5787
4298{ "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } }, 5788{"clcs", X(31,531), XRB_MASK, M601, 0, {RT, RA}},
4299{ "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } },
4300{ "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } },
4301{ "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } },
4302 5789
4303{ "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } }, 5790{"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, 0, {RT, RA0, RB}},
4304{ "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } },
4305 5791
4306{ "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } }, 5792{"lswx", X(31,533), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, RBX}},
4307{ "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } }, 5793{"lsx", X(31,533), X_MASK, PWRCOM, 0, {RT, RA, RB}},
4308 5794
4309{ "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } }, 5795{"lwbrx", X(31,534), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
4310{ "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } }, 5796{"lbrx", X(31,534), X_MASK, PWRCOM, 0, {RT, RA, RB}},
4311 5797
4312{ "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA0, RB } }, 5798{"lfsx", X(31,535), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
4313 5799
4314{ "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA0, RB } }, 5800{"srw", XRC(31,536,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
5801{"sr", XRC(31,536,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
5802{"srw.", XRC(31,536,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
5803{"sr.", XRC(31,536,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
4315 5804
4316{ "bbelr", X(31,550), X_MASK, PPCBRLK, { 0 }}, 5805{"rrib", XRC(31,537,0), X_MASK, M601, 0, {RA, RS, RB}},
5806{"rrib.", XRC(31,537,1), X_MASK, M601, 0, {RA, RS, RB}},
4317 5807
4318{ "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } }, 5808{"cnttzw", XRC(31,538,0), XRB_MASK, POWER9, 0, {RA, RS}},
5809{"cnttzw.", XRC(31,538,1), XRB_MASK, POWER9, 0, {RA, RS}},
4319 5810
4320{ "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } }, 5811{"srd", XRC(31,539,0), X_MASK, PPC64, 0, {RA, RS, RB}},
5812{"srd.", XRC(31,539,1), X_MASK, PPC64, 0, {RA, RS, RB}},
4321 5813
4322{ "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } }, 5814{"maskir", XRC(31,541,0), X_MASK, M601, 0, {RA, RS, RB}},
5815{"maskir.", XRC(31,541,1), X_MASK, M601, 0, {RA, RS, RB}},
4323 5816
4324{ "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } }, 5817{"lhdcbx", X(31,546), X_MASK, E200Z4, 0, {RT, RA, RB}},
5818{"lhdx", X(31,547), X_MASK, E500MC, 0, {RT, RA, RB}},
4325 5819
4326{ "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA0, NB } }, 5820{"lvtrx", X(31,549), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
4327{ "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA0, NB } },
4328 5821
4329{ "lwsync", XSYNC(31,598,1), 0xffffffff, PPC, { 0 } }, 5822{"bbelr", X(31,550), X_MASK, PPCBRLK, 0, {0}},
4330{ "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } },
4331{ "msync", X(31,598), 0xffffffff, BOOKE, { 0 } },
4332{ "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } },
4333{ "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
4334 5823
4335{ "lfdx", X(31,599), X_MASK, COM, { FRT, RA0, RB } }, 5824{"lvrx", X(31,551), X_MASK, CELL, 0, {VD, RA0, RB}},
5825{"lhfcmux", APU(31,551,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4336 5826
4337{ "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA0, RB } }, 5827{"subfo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5828{"subo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RB, RA}},
5829{"subfo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5830{"subo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RB, RA}},
4338 5831
4339{ "mffgpr", XRC(31,607,0), XRA_MASK, POWER6, { FRT, RB } }, 5832{"tlbsync", X(31,566), 0xffffffff, PPC, 0, {0}},
4340 5833
4341{ "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } }, 5834{"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
4342 5835
4343{ "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } }, 5836{"cnttzd", XRC(31,570,0), XRB_MASK, POWER9, 0, {RA, RS}},
5837{"cnttzd.", XRC(31,570,1), XRB_MASK, POWER9, 0, {RA, RS}},
4344 5838
4345{ "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } }, 5839{"mcrxrx", X(31,576), XBFRARB_MASK, POWER9, 0, {BF}},
4346 5840
4347{ "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } }, 5841{"lwdcbx", X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}},
5842{"lwdx", X(31,579), X_MASK, E500MC, 0, {RT, RA, RB}},
4348 5843
4349{ "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } }, 5844{"lvtlx", X(31,581), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
4350 5845
4351{ "stdbrx", X(31,660), X_MASK, CELL, { RS, RA0, RB } }, 5846{"lwat", X(31,582), X_MASK, POWER9, 0, {RT, RA0, FC}},
4352 5847
4353{ "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA0, RB } }, 5848{"lwfcmux", APU(31,583,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4354{ "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA0, RB } },
4355 5849
4356{ "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA0, RB } }, 5850{"lxsdx", X(31,588), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
4357{ "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA0, RB } },
4358 5851
4359{ "stfsx", X(31,663), X_MASK, COM, { FRS, RA0, RB } }, 5852{"mfsr", X(31,595), XRB_MASK|(1<<20), COM, NON32, {RT, SR}},
4360 5853
4361{ "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } }, 5854{"lswi", X(31,597), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, NBI}},
4362{ "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } }, 5855{"lsi", X(31,597), X_MASK, PWRCOM, 0, {RT, RA0, NB}},
4363 5856
4364{ "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } }, 5857{"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4, BOOKE|PPC476, {0}},
4365{ "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } }, 5858{"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}},
5859{"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, 0, {0}},
5860{"sync", X(31,598), XSYNCLE_MASK, E6500, 0, {LS, ESYNC}},
5861{"sync", X(31,598), XSYNC_MASK, PPCCOM, BOOKE|PPC476, {LS}},
5862{"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, 0, {0}},
5863{"sync", X(31,598), 0xffffffff, BOOKE|PPC476, E6500, {0}},
5864{"lwsync", X(31,598), 0xffffffff, E500, 0, {0}},
5865{"dcs", X(31,598), 0xffffffff, PWRCOM, 0, {0}},
4366 5866
4367{ "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA0, RB } }, 5867{"lfdx", X(31,599), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
4368 5868
4369{ "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA0, RB } }, 5869{"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}},
5870{"lfdepx", X(31,607), X_MASK, E500MC|PPCA2, 0, {FRT, RA0, RB}},
4370 5871
4371{ "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } }, 5872{"lddx", X(31,611), X_MASK, E500MC, 0, {RT, RA, RB}},
4372 5873
4373{ "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } }, 5874{"lvswx", X(31,613), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
4374{ "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } },
4375 5875
4376{ "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } }, 5876{"ldat", X(31,614), X_MASK, POWER9, 0, {RT, RA0, FC}},
4377 5877
4378{ "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA0, NB } }, 5878{"lqfcmux", APU(31,615,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4379{ "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA0, NB } },
4380 5879
4381{ "stfdx", X(31,727), X_MASK, COM, { FRS, RA0, RB } }, 5880{"nego", XO(31,104,1,0), XORB_MASK, COM, 0, {RT, RA}},
5881{"nego.", XO(31,104,1,1), XORB_MASK, COM, 0, {RT, RA}},
4382 5882
4383{ "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } }, 5883{"mulo", XO(31,107,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
4384{ "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } }, 5884{"mulo.", XO(31,107,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
4385 5885
4386{ "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } }, 5886{"mfsri", X(31,627), X_MASK, M601, 0, {RT, RA, RB}},
4387{ "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
4388 5887
4389{ "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA0, RB } }, 5888{"dclst", X(31,630), XRB_MASK, M601, 0, {RS, RA}},
4390 5889
4391{ "mftgpr", XRC(31,735,0), XRA_MASK, POWER6, { RT, FRB } }, 5890{"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
4392 5891
4393{ "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } }, 5892{"stbdcbx", X(31,642), X_MASK, E200Z4, 0, {RS, RA, RB}},
5893{"stbdx", X(31,643), X_MASK, E500MC, 0, {RS, RA, RB}},
4394 5894
4395{ "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } }, 5895{"stvlx", X(31,647), X_MASK, CELL, 0, {VS, RA0, RB}},
5896{"stbfcmux", APU(31,647,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4396 5897
4397{ "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } }, 5898{"stxsspx", X(31,652), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}},
4398{ "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } },
4399 5899
4400{ "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } }, 5900{"tbegin.", XRC(31,654,1), XRTLRARB_MASK, PPCHTM, 0, {HTM_R}},
4401 5901
4402{ "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } }, 5902{"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5903{"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5904{"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5905{"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4403 5906
4404{ "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } }, 5907{"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4405{ "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } }, 5908{"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5909{"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5910{"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4406 5911
4407{ "lwzcix", X(31,789), X_MASK, POWER6, { RT, RA0, RB } }, 5912{"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}},
4408 5913
4409{ "lhbrx", X(31,790), X_MASK, COM, { RT, RA0, RB } }, 5914{"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, 0, {RS, RA0, RB}},
4410 5915
4411{ "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } }, 5916{"stswx", X(31,661), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, RB}},
4412{ "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } }, 5917{"stsx", X(31,661), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
4413{ "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
4414{ "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } },
4415 5918
4416{ "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } }, 5919{"stwbrx", X(31,662), X_MASK, PPCCOM, 0, {RS, RA0, RB}},
4417{ "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } }, 5920{"stbrx", X(31,662), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
4418 5921
4419{ "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA0, RB } }, 5922{"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
4420 5923
4421{ "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA0, RB } }, 5924{"srq", XRC(31,664,0), X_MASK, M601, 0, {RA, RS, RB}},
4422{ "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA0, RB } }, 5925{"srq.", XRC(31,664,1), X_MASK, M601, 0, {RA, RS, RB}},
4423 5926
4424{ "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } }, 5927{"sre", XRC(31,665,0), X_MASK, M601, 0, {RA, RS, RB}},
5928{"sre.", XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}},
4425 5929
4426{ "lhzcix", X(31,821), X_MASK, POWER6, { RT, RA0, RB } }, 5930{"sthdcbx", X(31,674), X_MASK, E200Z4, 0, {RS, RA, RB}},
5931{"sthdx", X(31,675), X_MASK, E500MC, 0, {RS, RA, RB}},
4427 5932
4428{ "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } }, 5933{"stvfrx", X(31,677), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
4429{ "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } },
4430 5934
4431{ "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } }, 5935{"stvrx", X(31,679), X_MASK, CELL, 0, {VS, RA0, RB}},
4432{ "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } }, 5936{"sthfcmux", APU(31,679,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4433{ "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
4434{ "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
4435 5937
4436{ "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } }, 5938{"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, 0, {0}},
5939{"tend.", XRC(31,686,1), XRTARARB_MASK, PPCHTM, 0, {HTM_A}},
4437 5940
4438{ "lbzcix", X(31,853), X_MASK, POWER6, { RT, RA0, RB } }, 5941{"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},
4439 5942
4440{ "mbar", X(31,854), X_MASK, BOOKE, { MO } }, 5943{"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
4441{ "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
4442 5944
4443{ "lfiwax", X(31,855), X_MASK, POWER6, { FRT, RA0, RB } }, 5945{"sriq", XRC(31,696,0), X_MASK, M601, 0, {RA, RS, SH}},
5946{"sriq.", XRC(31,696,1), X_MASK, M601, 0, {RA, RS, SH}},
4444 5947
4445{ "ldcix", X(31,885), X_MASK, POWER6, { RT, RA0, RB } }, 5948{"stwdcbx", X(31,706), X_MASK, E200Z4, 0, {RS, RA, RB}},
5949{"stwdx", X(31,707), X_MASK, E500MC, 0, {RS, RA, RB}},
4446 5950
4447{ "tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, { RTO, RA, RB } }, 5951{"stvflx", X(31,709), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
4448{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
4449{ "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RA, RB } },
4450{ "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RA, RB } },
4451 5952
4452{ "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } }, 5953{"stwat", X(31,710), X_MASK, POWER9, 0, {RS, RA0, FC}},
4453 5954
4454{ "stwcix", X(31,917), X_MASK, POWER6, { RS, RA0, RB } }, 5955{"stwfcmux", APU(31,711,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4455 5956
4456{ "sthbrx", X(31,918), X_MASK, COM, { RS, RA0, RB } }, 5957{"stxsdx", X(31,716), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
4457 5958
4458{ "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } }, 5959{"tcheck", X(31,718), XRTBFRARB_MASK, PPCHTM, 0, {BF}},
4459{ "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
4460 5960
4461{ "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } }, 5961{"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
4462{ "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } }, 5962{"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5963{"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5964{"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
4463 5965
4464{ "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } }, 5966{"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
4465{ "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } }, 5967{"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
4466{ "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } }, 5968{"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
4467{ "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } }, 5969{"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
4468 5970
4469{ "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA0, RB } }, 5971{"stswi", X(31,725), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, NB}},
5972{"stsi", X(31,725), X_MASK, PWRCOM, 0, {RS, RA0, NB}},
4470 5973
4471{ "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA0, RB } }, 5974{"sthcx.", XRC(31,726,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},
4472 5975
4473{ "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } }, 5976{"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
4474{ "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
4475{ "tlbre", X(31,946), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
4476 5977
4477{ "sthcix", X(31,949), X_MASK, POWER6, { RS, RA0, RB } }, 5978{"srlq", XRC(31,728,0), X_MASK, M601, 0, {RA, RS, RB}},
5979{"srlq.", XRC(31,728,1), X_MASK, M601, 0, {RA, RS, RB}},
4478 5980
4479{ "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } }, 5981{"sreq", XRC(31,729,0), X_MASK, M601, 0, {RA, RS, RB}},
4480{ "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } }, 5982{"sreq.", XRC(31,729,1), X_MASK, M601, 0, {RA, RS, RB}},
4481 5983
4482{ "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} }, 5984{"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, POWER7, {RT, FRB}},
4483{ "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} }, 5985{"stfdepx", X(31,735), X_MASK, E500MC|PPCA2, 0, {FRS, RA0, RB}},
4484 5986
4485{ "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } }, 5987{"stddx", X(31,739), X_MASK, E500MC, 0, {RS, RA, RB}},
4486 5988
4487{ "iccci", X(31,966), XRT_MASK, PPC403|PPC440, { RA, RB } }, 5989{"stvswx", X(31,741), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
4488 5990
4489{ "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } }, 5991{"stdat", X(31,742), X_MASK, POWER9, 0, {RS, RA0, FC}},
4490{ "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
4491{ "tlbwe", X(31,978), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
4492{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
4493 5992
4494{ "stbcix", X(31,981), X_MASK, POWER6, { RS, RA0, RB } }, 5993{"stqfcmux", APU(31,743,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4495 5994
4496{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } }, 5995{"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5996{"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5997{"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5998{"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
4497 5999
4498{ "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA0, RB } }, 6000{"mulldo", XO(31,233,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
6001{"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
4499 6002
4500{ "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } }, 6003{"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
4501{ "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } }, 6004{"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
6005{"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
6006{"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
4502 6007
4503{ "icread", X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } }, 6008{"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6009{"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6010{"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6011{"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4504 6012
4505{ "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } }, 6013{"tsuspend.", XRCL(31,750,0,1), XRTRARB_MASK,PPCHTM, 0, {0}},
4506{ "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA0, RB } }, 6014{"tresume.", XRCL(31,750,1,1), XRTRARB_MASK,PPCHTM, 0, {0}},
6015{"tsr.", XRC(31,750,1), XRTLRARB_MASK,PPCHTM, 0, {L}},
4507 6016
4508{ "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } }, 6017{"darn", X(31,755), XLRAND_MASK, POWER9, 0, {RT, LRAND}},
4509 6018
4510{ "stdcix", X(31,1013), X_MASK, POWER6, { RS, RA0, RB } }, 6019{"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, 0, {RA0, RB}},
6020{"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, 0, {RA0, RB}},
4511 6021
4512{ "dcbzl", XOPL(31,1014,1), XRT_MASK,POWER4, { RA, RB } }, 6022{"stfdux", X(31,759), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
4513{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4514{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4515 6023
4516{ "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } }, 6024{"srliq", XRC(31,760,0), X_MASK, M601, 0, {RA, RS, SH}},
6025{"srliq.", XRC(31,760,1), X_MASK, M601, 0, {RA, RS, SH}},
4517 6026
4518{ "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } }, 6027{"lvsm", X(31,773), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
4519{ "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },
4520{ "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
4521{ "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } },
4522{ "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } },
4523{ "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } },
4524{ "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } },
4525{ "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
4526{ "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
4527{ "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
4528{ "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
4529{ "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
4530 6028
4531/* New load/store left/right index vector instructions that are in the Cell only. */ 6029{"copy", XOPL(31,774,1), XRT_MASK, POWER9, 0, {RA0, RB}},
4532{ "lvlx", X(31, 519), X_MASK, CELL, { VD, RA0, RB } },
4533{ "lvlxl", X(31, 775), X_MASK, CELL, { VD, RA0, RB } },
4534{ "lvrx", X(31, 551), X_MASK, CELL, { VD, RA0, RB } },
4535{ "lvrxl", X(31, 807), X_MASK, CELL, { VD, RA0, RB } },
4536{ "stvlx", X(31, 647), X_MASK, CELL, { VS, RA0, RB } },
4537{ "stvlxl", X(31, 903), X_MASK, CELL, { VS, RA0, RB } },
4538{ "stvrx", X(31, 679), X_MASK, CELL, { VS, RA0, RB } },
4539{ "stvrxl", X(31, 935), X_MASK, CELL, { VS, RA0, RB } },
4540 6030
4541{ "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } }, 6031{"stvepxl", X(31,775), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
4542{ "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } }, 6032{"lvlxl", X(31,775), X_MASK, CELL, 0, {VD, RA0, RB}},
6033{"ldfcmux", APU(31,775,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4543 6034
4544{ "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } }, 6035{"dozo", XO(31,264,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
4545{ "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA0 } }, 6036{"dozo.", XO(31,264,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
4546 6037
4547{ "lbz", OP(34), OP_MASK, COM, { RT, D, RA0 } }, 6038{"addo", XO(31,266,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6039{"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6040{"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6041{"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4548 6042
4549{ "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } }, 6043{"modsd", X(31,777), X_MASK, POWER9, 0, {RT, RA, RB}},
6044{"modsw", X(31,779), X_MASK, POWER9, 0, {RT, RA, RB}},
4550 6045
4551{ "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA0 } }, 6046{"lxvw4x", X(31,780), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
4552{ "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA0 } }, 6047{"lxsibzx", X(31,781), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
4553 6048
4554{ "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } }, 6049{"tabortwc.", XRC(31,782,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},
4555{ "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA0 } },
4556 6050
4557{ "stb", OP(38), OP_MASK, COM, { RS, D, RA0 } }, 6051{"tlbivax", X(31,786), XRT_MASK, BOOKE|PPCA2|PPC476, 0, {RA0, RB}},
4558 6052
4559{ "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } }, 6053{"lwzcix", X(31,789), X_MASK, POWER6, 0, {RT, RA0, RB}},
4560 6054
4561{ "lhz", OP(40), OP_MASK, COM, { RT, D, RA0 } }, 6055{"lhbrx", X(31,790), X_MASK, COM, 0, {RT, RA0, RB}},
4562 6056
4563{ "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } }, 6057{"lfdpx", X(31,791), X_MASK, POWER6, POWER7, {FRTp, RA0, RB}},
6058{"lfqx", X(31,791), X_MASK, POWER2, 0, {FRT, RA, RB}},
4564 6059
4565{ "lha", OP(42), OP_MASK, COM, { RT, D, RA0 } }, 6060{"sraw", XRC(31,792,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
6061{"sra", XRC(31,792,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
6062{"sraw.", XRC(31,792,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
6063{"sra.", XRC(31,792,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
4566 6064
4567{ "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } }, 6065{"srad", XRC(31,794,0), X_MASK, PPC64, 0, {RA, RS, RB}},
6066{"srad.", XRC(31,794,1), X_MASK, PPC64, 0, {RA, RS, RB}},
4568 6067
4569{ "sth", OP(44), OP_MASK, COM, { RS, D, RA0 } }, 6068{"lfddx", X(31,803), X_MASK, E500MC, 0, {FRT, RA, RB}},
4570 6069
4571{ "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } }, 6070{"lvtrxl", X(31,805), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
6071{"stvepx", X(31,807), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6072{"lvrxl", X(31,807), X_MASK, CELL, 0, {VD, RA0, RB}},
4572 6073
4573{ "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } }, 6074{"lxvh8x", X(31,812), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
4574{ "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA0 } }, 6075{"lxsihzx", X(31,813), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
4575 6076
4576{ "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA0 } }, 6077{"tabortdc.", XRC(31,814,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},
4577{ "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA0 } },
4578 6078
4579{ "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } }, 6079{"rac", X(31,818), X_MASK, M601, 0, {RT, RA, RB}},
4580 6080
4581{ "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } }, 6081{"erativax", X(31,819), X_MASK, PPCA2, 0, {RS, RA0, RB}},
4582 6082
4583{ "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } }, 6083{"lhzcix", X(31,821), X_MASK, POWER6, 0, {RT, RA0, RB}},
4584 6084
4585{ "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } }, 6085{"dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, 0, {STRM}},
4586 6086
4587{ "stfs", OP(52), OP_MASK, COM, { FRS, D, RA0 } }, 6087{"lfqux", X(31,823), X_MASK, POWER2, 0, {FRT, RA, RB}},
4588 6088
4589{ "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } }, 6089{"srawi", XRC(31,824,0), X_MASK, PPCCOM, 0, {RA, RS, SH}},
6090{"srai", XRC(31,824,0), X_MASK, PWRCOM, 0, {RA, RS, SH}},
6091{"srawi.", XRC(31,824,1), X_MASK, PPCCOM, 0, {RA, RS, SH}},
6092{"srai.", XRC(31,824,1), X_MASK, PWRCOM, 0, {RA, RS, SH}},
4590 6093
4591{ "stfd", OP(54), OP_MASK, COM, { FRS, D, RA0 } }, 6094{"sradi", XS(31,413,0), XS_MASK, PPC64, 0, {RA, RS, SH6}},
6095{"sradi.", XS(31,413,1), XS_MASK, PPC64, 0, {RA, RS, SH6}},
4592 6096
4593{ "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } }, 6097{"lvtlxl", X(31,837), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
4594 6098
4595{ "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } }, 6099{"cpabort", X(31,838), XRTRARB_MASK,POWER9, 0, {0}},
4596 6100
4597{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA0 } }, 6101{"divo", XO(31,331,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6102{"divo.", XO(31,331,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
4598 6103
4599{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA0 } }, 6104{"lxvd2x", X(31,844), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
6105{"lxvx", X(31,844), XX1_MASK, POWER8, POWER9|PPCVSX3, {XT6, RA0, RB}},
4600 6106
4601{ "lfdp", OP(57), OP_MASK, POWER6, { FRT, D, RA0 } }, 6107{"tabortwci.", XRC(31,846,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}},
4602 6108
4603{ "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA0 } }, 6109{"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, 0, {RA0, RB}},
4604{ "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } },
4605{ "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4606{ "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } },
4607{ "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4608{ "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } },
4609{ "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4610{ "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } },
4611{ "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4612{ "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } },
4613{ "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4614{ "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } },
4615{ "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4616{ "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } },
4617 6110
4618{ "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA0 } }, 6111{"slbiag", X(31,850), XRARB_MASK, POWER9, 0, {RS}},
6112{"slbmfev", X(31,851), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},
6113{"slbmfev", X(31,851), XRA_MASK, PPC64, POWER9, {RT, RB}},
4619 6114
4620{ "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } }, 6115{"lbzcix", X(31,853), X_MASK, POWER6, 0, {RT, RA0, RB}},
4621 6116
4622{ "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA0 } }, 6117{"eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0}},
6118{"mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476, 0, {MO}},
6119{"eieio", XMBAR(31,854,1),0xffffffff, E500, 0, {0}},
6120{"eieio", X(31,854), 0xffffffff, PPCA2|PPC476, 0, {0}},
4623 6121
4624{ "dadd", XRC(59,2,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 6122{"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, 0, {FRT, RA0, RB}},
4625{ "dadd.", XRC(59,2,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4626 6123
4627{ "dqua", ZRC(59,3,0), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } }, 6124{"lvswxl", X(31,869), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
4628{ "dqua.", ZRC(59,3,1), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4629 6125
4630{ "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 6126{"abso", XO(31,360,1,0), XORB_MASK, M601, 0, {RT, RA}},
4631{ "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 6127{"abso.", XO(31,360,1,1), XORB_MASK, M601, 0, {RT, RA}},
4632 6128
4633{ "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 6129{"divso", XO(31,363,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
4634{ "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 6130{"divso.", XO(31,363,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
4635 6131
4636{ "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 6132{"lxvb16x", X(31,876), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
4637{ "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4638 6133
4639{ "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, 6134{"tabortdci.", XRC(31,878,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}},
4640{ "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4641 6135
4642{ "fres", A(59,24,0), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } }, 6136{"rmieg", X(31,882), XRTRA_MASK, POWER9, 0, {RB}},
4643{ "fres.", A(59,24,1), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
4644 6137
4645{ "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } }, 6138{"ldcix", X(31,885), X_MASK, POWER6, 0, {RT, RA0, RB}},
4646{ "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4647 6139
4648{ "frsqrtes", A(59,26,0), AFRALFRC_MASK,POWER5, { FRT, FRB, A_L } }, 6140{"msgsync", X(31,886), 0xffffffff, POWER9, 0, {0}},
4649{ "frsqrtes.",A(59,26,1), AFRALFRC_MASK,POWER5, { FRT, FRB, A_L } },
4650 6141
4651{ "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 6142{"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, 0, {FRT, RA0, RB}},
4652{ "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4653 6143
4654{ "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 6144{"extswsli", XS(31,445,0), XS_MASK, POWER9, 0, {RA, RS, SH6}},
4655{ "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 6145{"extswsli.", XS(31,445,1), XS_MASK, POWER9, 0, {RA, RS, SH6}},
4656 6146
4657{ "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 6147{"paste.", XRCL(31,902,1,1),XRT_MASK, POWER9, 0, {RA0, RB}},
4658{ "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4659 6148
4660{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 6149{"stvlxl", X(31,903), X_MASK, CELL, 0, {VS, RA0, RB}},
4661{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 6150{"stdfcmux", APU(31,903,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4662 6151
4663{ "dmul", XRC(59,34,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 6152{"divdeuo", XO(31,393,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
4664{ "dmul.", XRC(59,34,1), X_MASK, POWER6, { FRT, FRA, FRB } }, 6153{"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6154{"divweuo", XO(31,395,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6155{"divweuo.", XO(31,395,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
4665 6156
4666{ "drrnd", ZRC(59,35,0), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } }, 6157{"stxvw4x", X(31,908), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
4667{ "drrnd.", ZRC(59,35,1), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } }, 6158{"stxsibx", X(31,909), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
4668 6159
4669{ "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 6160{"tabort.", XRC(31,910,1), XRTRB_MASK, PPCHTM, 0, {RA}},
4670{ "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4671 6161
4672{ "dquai", ZRC(59,67,0), Z_MASK, POWER6, { TE, FRT, FRB, RMC } }, 6162{"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},
4673{ "dquai.", ZRC(59,67,1), Z_MASK, POWER6, { TE, FRT, FRB, RMC } }, 6163{"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},
4674 6164
4675{ "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 6165{"slbmfee", X(31,915), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},
4676{ "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 6166{"slbmfee", X(31,915), XRA_MASK, PPC64, POWER9, {RT, RB}},
4677 6167
4678{ "drintx", ZRC(59,99,0), Z_MASK, POWER6, { R, FRT, FRB, RMC } }, 6168{"stwcix", X(31,917), X_MASK, POWER6, 0, {RS, RA0, RB}},
4679{ "drintx.", ZRC(59,99,1), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
4680 6169
4681{ "dcmpo", X(59,130), X_MASK, POWER6, { BF, FRA, FRB } }, 6170{"sthbrx", X(31,918), X_MASK, COM, 0, {RS, RA0, RB}},
4682 6171
4683{ "dtstex", X(59,162), X_MASK, POWER6, { BF, FRA, FRB } }, 6172{"stfdpx", X(31,919), X_MASK, POWER6, POWER7, {FRSp, RA0, RB}},
4684{ "dtstdc", Z(59,194), Z_MASK, POWER6, { BF, FRA, DCM } }, 6173{"stfqx", X(31,919), X_MASK, POWER2, 0, {FRS, RA0, RB}},
4685{ "dtstdg", Z(59,226), Z_MASK, POWER6, { BF, FRA, DGM } },
4686 6174
4687{ "drintn", ZRC(59,227,0), Z_MASK, POWER6, { R, FRT, FRB, RMC } }, 6175{"sraq", XRC(31,920,0), X_MASK, M601, 0, {RA, RS, RB}},
4688{ "drintn.", ZRC(59,227,1), Z_MASK, POWER6, { R, FRT, FRB, RMC } }, 6176{"sraq.", XRC(31,920,1), X_MASK, M601, 0, {RA, RS, RB}},
4689 6177
4690{ "dctdp", XRC(59,258,0), X_MASK, POWER6, { FRT, FRB } }, 6178{"srea", XRC(31,921,0), X_MASK, M601, 0, {RA, RS, RB}},
4691{ "dctdp.", XRC(59,258,1), X_MASK, POWER6, { FRT, FRB } }, 6179{"srea.", XRC(31,921,1), X_MASK, M601, 0, {RA, RS, RB}},
4692 6180
4693{ "dctfix", XRC(59,290,0), X_MASK, POWER6, { FRT, FRB } }, 6181{"extsh", XRC(31,922,0), XRB_MASK, PPCCOM, 0, {RA, RS}},
4694{ "dctfix.", XRC(59,290,1), X_MASK, POWER6, { FRT, FRB } }, 6182{"exts", XRC(31,922,0), XRB_MASK, PWRCOM, 0, {RA, RS}},
6183{"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, 0, {RA, RS}},
6184{"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, 0, {RA, RS}},
4695 6185
4696{ "ddedpd", XRC(59,322,0), X_MASK, POWER6, { SP, FRT, FRB } }, 6186{"stfddx", X(31,931), X_MASK, E500MC, 0, {FRS, RA, RB}},
4697{ "ddedpd.", XRC(59,322,1), X_MASK, POWER6, { SP, FRT, FRB } },
4698 6187
4699{ "dxex", XRC(59,354,0), X_MASK, POWER6, { FRT, FRB } }, 6188{"stvfrxl", X(31,933), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
4700{ "dxex.", XRC(59,354,1), X_MASK, POWER6, { FRT, FRB } },
4701 6189
4702{ "dsub", XRC(59,514,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 6190{"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, 0, {RA0, RB}},
4703{ "dsub.", XRC(59,514,1), X_MASK, POWER6, { FRT, FRA, FRB } }, 6191{"wclrall", X(31,934), XRARB_MASK, PPCA2, 0, {L2}},
6192{"wclr", X(31,934), X_MASK, PPCA2, 0, {L2, RA0, RB}},
4704 6193
4705{ "ddiv", XRC(59,546,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 6194{"stvrxl", X(31,935), X_MASK, CELL, 0, {VS, RA0, RB}},
4706{ "ddiv.", XRC(59,546,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4707 6195
4708{ "dcmpu", X(59,642), X_MASK, POWER6, { BF, FRA, FRB } }, 6196{"divdeo", XO(31,425,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6197{"divdeo.", XO(31,425,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6198{"divweo", XO(31,427,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6199{"divweo.", XO(31,427,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
4709 6200
4710{ "dtstsf", X(59,674), X_MASK, POWER6, { BF, FRA, FRB } }, 6201{"stxvh8x", X(31,940), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
6202{"stxsihx", X(31,941), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
4711 6203
4712{ "drsp", XRC(59,770,0), X_MASK, POWER6, { FRT, FRB } }, 6204{"treclaim.", XRC(31,942,1), XRTRB_MASK, PPCHTM, 0, {RA}},
4713{ "drsp.", XRC(59,770,1), X_MASK, POWER6, { FRT, FRB } },
4714 6205
4715{ "dcffix", XRC(59,802,0), X_MASK, POWER6, { FRT, FRB } }, 6206{"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
4716{ "dcffix.", XRC(59,802,1), X_MASK, POWER6, { FRT, FRB } }, 6207{"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
6208{"tlbre", X(31,946), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}},
4717 6209
4718{ "denbcd", XRC(59,834,0), X_MASK, POWER6, { S, FRT, FRB } }, 6210{"sthcix", X(31,949), X_MASK, POWER6, 0, {RS, RA0, RB}},
4719{ "denbcd.", XRC(59,834,1), X_MASK, POWER6, { S, FRT, FRB } },
4720 6211
4721{ "diex", XRC(59,866,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 6212{"icswepx", XRC(31,950,0), X_MASK, PPCA2, 0, {RS, RA, RB}},
4722{ "diex.", XRC(59,866,1), X_MASK, POWER6, { FRT, FRA, FRB } }, 6213{"icswepx.", XRC(31,950,1), X_MASK, PPCA2, 0, {RS, RA, RB}},
4723 6214
4724{ "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } }, 6215{"stfqux", X(31,951), X_MASK, POWER2, 0, {FRS, RA, RB}},
4725 6216
4726{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } }, 6217{"sraiq", XRC(31,952,0), X_MASK, M601, 0, {RA, RS, SH}},
6218{"sraiq.", XRC(31,952,1), X_MASK, M601, 0, {RA, RS, SH}},
4727 6219
4728{ "stfdp", OP(61), OP_MASK, POWER6, { FRT, D, RA0 } }, 6220{"extsb", XRC(31,954,0), XRB_MASK, PPC, 0, {RA, RS}},
6221{"extsb.", XRC(31,954,1), XRB_MASK, PPC, 0, {RA, RS}},
4729 6222
4730{ "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA0 } }, 6223{"stvflxl", X(31,965), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
4731{ "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA0 } },
4732{ "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA0 } },
4733{ "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4734{ "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA0 } },
4735{ "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4736{ "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA0 } },
4737{ "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } },
4738{ "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA0 } },
4739{ "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4740{ "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA0 } },
4741{ "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4742 6224
4743{ "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA0 } }, 6225{"iccci", X(31,966), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, 0, {RAOPT, RBOPT}},
6226{"ici", X(31,966), XRARB_MASK, PPCA2|PPC476, 0, {CT}},
4744 6227
4745{ "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } }, 6228{"divduo", XO(31,457,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
6229{"divduo.", XO(31,457,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
4746 6230
4747{ "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA0 } }, 6231{"divwuo", XO(31,459,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
6232{"divwuo.", XO(31,459,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
4748 6233
4749{ "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } }, 6234{"stxvd2x", X(31,972), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
6235{"stxvx", X(31,972), XX1_MASK, POWER8, POWER9|PPCVSX3, {XS6, RA0, RB}},
4750 6236
4751{ "daddq", XRC(63,2,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 6237{"tlbld", X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}},
4752{ "daddq.", XRC(63,2,1), X_MASK, POWER6, { FRT, FRA, FRB } }, 6238{"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, 0, {RT, RA}},
6239{"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, 0, {RT, RA}},
6240{"tlbwe", X(31,978), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}},
4753 6241
4754{ "dquaq", ZRC(63,3,0), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } }, 6242{"slbfee.", XRC(31,979,1), XRA_MASK, POWER6, 0, {RT, RB}},
4755{ "dquaq.", ZRC(63,3,1), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4756 6243
4757{ "fcpsgn", XRC(63,8,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 6244{"stbcix", X(31,981), X_MASK, POWER6, 0, {RS, RA0, RB}},
4758{ "fcpsgn.", XRC(63,8,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4759 6245
4760{ "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } }, 6246{"icbi", X(31,982), XRT_MASK, PPC, 0, {RA0, RB}},
4761{ "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } },
4762 6247
4763{ "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } }, 6248{"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}},
4764{ "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } },
4765{ "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4766{ "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } },
4767 6249
4768{ "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } }, 6250{"extsw", XRC(31,986,0), XRB_MASK, PPC64, 0, {RA, RS}},
4769{ "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } }, 6251{"extsw.", XRC(31,986,1), XRB_MASK, PPC64, 0, {RA, RS}},
4770{ "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4771{ "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } },
4772 6252
4773{ "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, 6253{"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
4774{ "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4775{ "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4776{ "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4777 6254
4778{ "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, 6255{"stvswxl", X(31,997), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
4779{ "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4780{ "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4781{ "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4782 6256
4783{ "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, 6257{"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA0, RB}},
4784{ "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4785{ "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4786{ "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4787 6258
4788{ "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } }, 6259{"nabso", XO(31,488,1,0), XORB_MASK, M601, 0, {RT, RA}},
4789{ "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } }, 6260{"nabso.", XO(31,488,1,1), XORB_MASK, M601, 0, {RT, RA}},
4790 6261
4791{ "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 6262{"divdo", XO(31,489,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
4792{ "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 6263{"divdo.", XO(31,489,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
4793 6264
4794{ "fre", A(63,24,0), AFRALFRC_MASK, POWER5, { FRT, FRB, A_L } }, 6265{"divwo", XO(31,491,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4795{ "fre.", A(63,24,1), AFRALFRC_MASK, POWER5, { FRT, FRB, A_L } }, 6266{"divwo.", XO(31,491,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
4796 6267
4797{ "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } }, 6268{"stxvb16x", X(31,1004), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
4798{ "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4799{ "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4800{ "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4801 6269
4802{ "frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } }, 6270{"trechkpt.", XRC(31,1006,1), XRTRARB_MASK,PPCHTM, 0, {0}},
4803{ "frsqrte.",A(63,26,1), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
4804 6271
4805{ "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, 6272{"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}},
4806{ "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4807{ "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4808{ "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4809 6273
4810{ "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, 6274{"stdcix", X(31,1013), X_MASK, POWER6, 0, {RS, RA0, RB}},
4811{ "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4812{ "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4813{ "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4814 6275
4815{ "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, 6276{"dcbz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}},
4816{ "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, 6277{"dclz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}},
4817{ "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4818{ "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4819 6278
4820{ "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, 6279{"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
4821{ "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4822{ "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4823{ "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4824 6280
4825{ "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } }, 6281{"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476, {RA0, RB}},
4826 6282
4827{ "dmulq", XRC(63,34,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 6283{"cctpl", 0x7c210b78, 0xffffffff, CELL, 0, {0}},
4828{ "dmulq.", XRC(63,34,1), X_MASK, POWER6, { FRT, FRA, FRB } }, 6284{"cctpm", 0x7c421378, 0xffffffff, CELL, 0, {0}},
6285{"cctph", 0x7c631b78, 0xffffffff, CELL, 0, {0}},
4829 6286
4830{ "drrndq", ZRC(63,35,0), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } }, 6287{"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
4831{ "drrndq.", ZRC(63,35,1), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } }, 6288{"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
6289{"dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, 0, {0}},
4832 6290
4833{ "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } }, 6291{"db8cyc", 0x7f9ce378, 0xffffffff, CELL, 0, {0}},
4834{ "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } }, 6292{"db10cyc", 0x7fbdeb78, 0xffffffff, CELL, 0, {0}},
6293{"db12cyc", 0x7fdef378, 0xffffffff, CELL, 0, {0}},
6294{"db16cyc", 0x7ffffb78, 0xffffffff, CELL, 0, {0}},
4835 6295
4836{ "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } }, 6296{"lwz", OP(32), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}},
4837{ "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } }, 6297{"l", OP(32), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
4838 6298
4839{ "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } }, 6299{"lwzu", OP(33), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAL}},
6300{"lu", OP(33), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
4840 6301
4841{ "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 6302{"lbz", OP(34), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
4842{ "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4843 6303
4844{ "dquaiq", ZRC(63,67,0), Z_MASK, POWER6, { TE, FRT, FRB, RMC } }, 6304{"lbzu", OP(35), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
4845{ "dquaiq.", ZRC(63,67,1), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4846 6305
4847{ "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } }, 6306{"stw", OP(36), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}},
4848{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } }, 6307{"st", OP(36), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
4849 6308
4850{ "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } }, 6309{"stwu", OP(37), OP_MASK, PPCCOM, PPCVLE, {RS, D, RAS}},
4851{ "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } }, 6310{"stu", OP(37), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
4852 6311
4853{ "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 6312{"stb", OP(38), OP_MASK, COM, PPCVLE, {RS, D, RA0}},
4854{ "dscriq.", ZRC(63,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4855 6313
4856{ "drintxq", ZRC(63,99,0), Z_MASK, POWER6, { R, FRT, FRB, RMC } }, 6314{"stbu", OP(39), OP_MASK, COM, PPCVLE, {RS, D, RAS}},
4857{ "drintxq.",ZRC(63,99,1), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
4858 6315
4859{ "dcmpoq", X(63,130), X_MASK, POWER6, { BF, FRA, FRB } }, 6316{"lhz", OP(40), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
4860 6317
4861{ "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } }, 6318{"lhzu", OP(41), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
4862{ "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4863 6319
4864{ "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } }, 6320{"lha", OP(42), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
4865{ "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } },
4866 6321
4867{ "dtstexq", X(63,162), X_MASK, POWER6, { BF, FRA, FRB } }, 6322{"lhau", OP(43), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
4868{ "dtstdcq", Z(63,194), Z_MASK, POWER6, { BF, FRA, DCM } },
4869{ "dtstdgq", Z(63,226), Z_MASK, POWER6, { BF, FRA, DGM } },
4870 6323
4871{ "drintnq", ZRC(63,227,0), Z_MASK, POWER6, { R, FRT, FRB, RMC } }, 6324{"sth", OP(44), OP_MASK, COM, PPCVLE, {RS, D, RA0}},
4872{ "drintnq.",ZRC(63,227,1), Z_MASK, POWER6, { R, FRT, FRB, RMC } },
4873 6325
4874{ "dctqpq", XRC(63,258,0), X_MASK, POWER6, { FRT, FRB } }, 6326{"sthu", OP(45), OP_MASK, COM, PPCVLE, {RS, D, RAS}},
4875{ "dctqpq.", XRC(63,258,1), X_MASK, POWER6, { FRT, FRB } },
4876 6327
4877{ "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } }, 6328{"lmw", OP(46), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAM}},
4878{ "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } }, 6329{"lm", OP(46), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
4879 6330
4880{ "dctfixq", XRC(63,290,0), X_MASK, POWER6, { FRT, FRB } }, 6331{"stmw", OP(47), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}},
4881{ "dctfixq.",XRC(63,290,1), X_MASK, POWER6, { FRT, FRB } }, 6332{"stm", OP(47), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
4882 6333
4883{ "ddedpdq", XRC(63,322,0), X_MASK, POWER6, { SP, FRT, FRB } }, 6334{"lfs", OP(48), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}},
4884{ "ddedpdq.",XRC(63,322,1), X_MASK, POWER6, { SP, FRT, FRB } },
4885 6335
4886{ "dxexq", XRC(63,354,0), X_MASK, POWER6, { FRT, FRB } }, 6336{"lfsu", OP(49), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}},
4887{ "dxexq.", XRC(63,354,1), X_MASK, POWER6, { FRT, FRB } },
4888 6337
4889{ "frin", XRC(63,392,0), XRA_MASK, POWER5, { FRT, FRB } }, 6338{"lfd", OP(50), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}},
4890{ "frin.", XRC(63,392,1), XRA_MASK, POWER5, { FRT, FRB } },
4891{ "friz", XRC(63,424,0), XRA_MASK, POWER5, { FRT, FRB } },
4892{ "friz.", XRC(63,424,1), XRA_MASK, POWER5, { FRT, FRB } },
4893{ "frip", XRC(63,456,0), XRA_MASK, POWER5, { FRT, FRB } },
4894{ "frip.", XRC(63,456,1), XRA_MASK, POWER5, { FRT, FRB } },
4895{ "frim", XRC(63,488,0), XRA_MASK, POWER5, { FRT, FRB } },
4896{ "frim.", XRC(63,488,1), XRA_MASK, POWER5, { FRT, FRB } },
4897 6339
4898{ "dsubq", XRC(63,514,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 6340{"lfdu", OP(51), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}},
4899{ "dsubq.", XRC(63,514,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4900 6341
4901{ "ddivq", XRC(63,546,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 6342{"stfs", OP(52), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}},
4902{ "ddivq.", XRC(63,546,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4903 6343
4904{ "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } }, 6344{"stfsu", OP(53), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}},
4905{ "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } },
4906 6345
4907{ "dcmpuq", X(63,642), X_MASK, POWER6, { BF, FRA, FRB } }, 6346{"stfd", OP(54), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}},
4908 6347
4909{ "dtstsfq", X(63,674), X_MASK, POWER6, { BF, FRA, FRB } }, 6348{"stfdu", OP(55), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}},
4910 6349
4911{ "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } }, 6350{"lq", OP(56), OP_MASK, POWER4, PPC476|PPCVLE, {RTQ, DQ, RAQ}},
4912{ "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } }, 6351{"psq_l", OP(56), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}},
6352{"lfq", OP(56), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}},
4913 6353
4914{ "drdpq", XRC(63,770,0), X_MASK, POWER6, { FRT, FRB } }, 6354{"lxsd", DSO(57,2), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}},
4915{ "drdpq.", XRC(63,770,1), X_MASK, POWER6, { FRT, FRB } }, 6355{"lxssp", DSO(57,3), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}},
6356{"lfdp", OP(57), OP_MASK, POWER6, POWER7|PPCVLE, {FRTp, DS, RA0}},
6357{"psq_lu", OP(57), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}},
6358{"lfqu", OP(57), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}},
4916 6359
4917{ "dcffixq", XRC(63,802,0), X_MASK, POWER6, { FRT, FRB } }, 6360{"ld", DSO(58,0), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}},
4918{ "dcffixq.",XRC(63,802,1), X_MASK, POWER6, { FRT, FRB } }, 6361{"ldu", DSO(58,1), DS_MASK, PPC64, PPCVLE, {RT, DS, RAL}},
6362{"lwa", DSO(58,2), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}},
4919 6363
4920{ "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } }, 6364{"dadd", XRC(59,2,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
4921{ "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } }, 6365{"dadd.", XRC(59,2,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
4922 6366
4923{ "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } }, 6367{"dqua", ZRC(59,3,0), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}},
4924{ "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } }, 6368{"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}},
4925 6369
4926{ "denbcdq", XRC(63,834,0), X_MASK, POWER6, { S, FRT, FRB } }, 6370{"fdivs", A(59,18,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
4927{ "denbcdq.",XRC(63,834,1), X_MASK, POWER6, { S, FRT, FRB } }, 6371{"fdivs.", A(59,18,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
4928 6372
4929{ "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } }, 6373{"fsubs", A(59,20,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
4930{ "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } }, 6374{"fsubs.", A(59,20,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
4931 6375
4932{ "diexq", XRC(63,866,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 6376{"fadds", A(59,21,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
4933{ "diexq.", XRC(63,866,1), X_MASK, POWER6, { FRT, FRA, FRB } }, 6377{"fadds.", A(59,21,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
4934 6378
6379{"fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}},
6380{"fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}},
6381
6382{"fres", A(59,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6383{"fres", A(59,24,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
6384{"fres.", A(59,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6385{"fres.", A(59,24,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
6386
6387{"fmuls", A(59,25,0), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
6388{"fmuls.", A(59,25,1), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
6389
6390{"frsqrtes", A(59,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6391{"frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
6392{"frsqrtes.", A(59,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6393{"frsqrtes.", A(59,26,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
6394
6395{"fmsubs", A(59,28,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6396{"fmsubs.", A(59,28,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6397
6398{"fmadds", A(59,29,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6399{"fmadds.", A(59,29,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6400
6401{"fnmsubs", A(59,30,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6402{"fnmsubs.", A(59,30,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6403
6404{"fnmadds", A(59,31,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6405{"fnmadds.", A(59,31,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6406
6407{"dmul", XRC(59,34,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6408{"dmul.", XRC(59,34,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6409
6410{"drrnd", ZRC(59,35,0), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}},
6411{"drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}},
6412
6413{"dscli", ZRC(59,66,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6414{"dscli.", ZRC(59,66,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6415
6416{"dquai", ZRC(59,67,0), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}},
6417{"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}},
6418
6419{"dscri", ZRC(59,98,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6420{"dscri.", ZRC(59,98,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6421
6422{"drintx", ZRC(59,99,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6423{"drintx.", ZRC(59,99,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6424
6425{"dcmpo", X(59,130), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6426
6427{"dtstex", X(59,162), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6428{"dtstdc", Z(59,194), Z_MASK, POWER6, PPCVLE, {BF, FRA, DCM}},
6429{"dtstdg", Z(59,226), Z_MASK, POWER6, PPCVLE, {BF, FRA, DGM}},
6430
6431{"drintn", ZRC(59,227,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6432{"drintn.", ZRC(59,227,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6433
6434{"dctdp", XRC(59,258,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6435{"dctdp.", XRC(59,258,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6436
6437{"dctfix", XRC(59,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6438{"dctfix.", XRC(59,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6439
6440{"ddedpd", XRC(59,322,0), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}},
6441{"ddedpd.", XRC(59,322,1), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}},
6442
6443{"dxex", XRC(59,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6444{"dxex.", XRC(59,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6445
6446{"dsub", XRC(59,514,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6447{"dsub.", XRC(59,514,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6448
6449{"ddiv", XRC(59,546,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6450{"ddiv.", XRC(59,546,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6451
6452{"dcmpu", X(59,642), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6453
6454{"dtstsf", X(59,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6455{"dtstsfi", X(59,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRB}},
6456
6457{"drsp", XRC(59,770,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6458{"drsp.", XRC(59,770,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6459
6460{"dcffix", XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6461{"dcffix.", XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6462
6463{"denbcd", XRC(59,834,0), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}},
6464{"denbcd.", XRC(59,834,1), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}},
6465
6466{"fcfids", XRC(59,846,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6467{"fcfids.", XRC(59,846,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6468
6469{"diex", XRC(59,866,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6470{"diex.", XRC(59,866,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6471
6472{"fcfidus", XRC(59,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6473{"fcfidus.", XRC(59,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6474
6475{"xsaddsp", XX3(60,0), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6476{"xsmaddasp", XX3(60,1), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6477{"xxsldwi", XX3(60,2), XX3SHW_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, SHW}},
6478{"xscmpeqdp", XX3(60,3), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6479{"xsrsqrtesp", XX2(60,10), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6480{"xssqrtsp", XX2(60,11), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6481{"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, XC6}},
6482{"xssubsp", XX3(60,8), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6483{"xsmaddmsp", XX3(60,9), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6484{"xxspltd", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S, DMEX}},
6485{"xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6486{"xxswapd", XX3(60,10)|(2<<8), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}},
6487{"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6488{"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, DM}},
6489{"xscmpgtdp", XX3(60,11), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6490{"xsresp", XX2(60,26), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6491{"xsmulsp", XX3(60,16), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6492{"xsmsubasp", XX3(60,17), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6493{"xxmrghw", XX3(60,18), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6494{"xscmpgedp", XX3(60,19), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6495{"xsdivsp", XX3(60,24), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6496{"xsmsubmsp", XX3(60,25), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6497{"xxperm", XX3(60,26), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6498{"xsadddp", XX3(60,32), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6499{"xsmaddadp", XX3(60,33), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6500{"xscmpudp", XX3(60,35), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6501{"xscvdpuxws", XX2(60,72), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6502{"xsrdpi", XX2(60,73), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6503{"xsrsqrtedp", XX2(60,74), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6504{"xssqrtdp", XX2(60,75), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6505{"xssubdp", XX3(60,40), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6506{"xsmaddmdp", XX3(60,41), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6507{"xscmpodp", XX3(60,43), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6508{"xscvdpsxws", XX2(60,88), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6509{"xsrdpiz", XX2(60,89), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6510{"xsredp", XX2(60,90), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6511{"xsmuldp", XX3(60,48), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6512{"xsmsubadp", XX3(60,49), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6513{"xxmrglw", XX3(60,50), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6514{"xsrdpip", XX2(60,105), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6515{"xstsqrtdp", XX2(60,106), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
6516{"xsrdpic", XX2(60,107), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6517{"xsdivdp", XX3(60,56), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6518{"xsmsubmdp", XX3(60,57), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6519{"xxpermr", XX3(60,58), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6520{"xscmpexpdp", XX3(60,59), XX3BF_MASK, PPCVSX3, PPCVLE, {BF, XA6, XB6}},
6521{"xsrdpim", XX2(60,121), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6522{"xstdivdp", XX3(60,61), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6523{"xvaddsp", XX3(60,64), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6524{"xvmaddasp", XX3(60,65), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6525{"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6526{"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6527{"xvcvspuxws", XX2(60,136), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6528{"xvrspi", XX2(60,137), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6529{"xvrsqrtesp", XX2(60,138), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6530{"xvsqrtsp", XX2(60,139), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6531{"xvsubsp", XX3(60,72), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6532{"xvmaddmsp", XX3(60,73), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6533{"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6534{"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6535{"xvcvspsxws", XX2(60,152), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6536{"xvrspiz", XX2(60,153), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6537{"xvresp", XX2(60,154), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6538{"xvmulsp", XX3(60,80), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6539{"xvmsubasp", XX3(60,81), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6540{"xxspltw", XX2(60,164), XX2UIM_MASK, PPCVSX, PPCVLE, {XT6, XB6, UIM}},
6541{"xxextractuw", XX2(60,165), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}},
6542{"xvcmpgesp", XX3RC(60,83,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6543{"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6544{"xvcvuxwsp", XX2(60,168), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6545{"xvrspip", XX2(60,169), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6546{"xvtsqrtsp", XX2(60,170), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
6547{"xvrspic", XX2(60,171), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6548{"xvdivsp", XX3(60,88), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6549{"xvmsubmsp", XX3(60,89), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6550{"xxspltib", X(60,360), XX1_MASK|3<<19, PPCVSX3, PPCVLE, {XT6, IMM8}},
6551{"xxinsertw", XX2(60,181), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}},
6552{"xvcvsxwsp", XX2(60,184), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6553{"xvrspim", XX2(60,185), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6554{"xvtdivsp", XX3(60,93), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6555{"xvadddp", XX3(60,96), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6556{"xvmaddadp", XX3(60,97), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6557{"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6558{"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6559{"xvcvdpuxws", XX2(60,200), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6560{"xvrdpi", XX2(60,201), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6561{"xvrsqrtedp", XX2(60,202), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6562{"xvsqrtdp", XX2(60,203), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6563{"xvsubdp", XX3(60,104), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6564{"xvmaddmdp", XX3(60,105), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6565{"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6566{"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6567{"xvcvdpsxws", XX2(60,216), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6568{"xvrdpiz", XX2(60,217), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6569{"xvredp", XX2(60,218), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6570{"xvmuldp", XX3(60,112), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6571{"xvmsubadp", XX3(60,113), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6572{"xvcmpgedp", XX3RC(60,115,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6573{"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6574{"xvcvuxwdp", XX2(60,232), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6575{"xvrdpip", XX2(60,233), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6576{"xvtsqrtdp", XX2(60,234), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
6577{"xvrdpic", XX2(60,235), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6578{"xvdivdp", XX3(60,120), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6579{"xvmsubmdp", XX3(60,121), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6580{"xvcvsxwdp", XX2(60,248), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6581{"xvrdpim", XX2(60,249), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6582{"xvtdivdp", XX3(60,125), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6583{"xsmaxcdp", XX3(60,128), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6584{"xsnmaddasp", XX3(60,129), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6585{"xxland", XX3(60,130), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6586{"xscvdpsp", XX2(60,265), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6587{"xscvdpspn", XX2(60,267), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6588{"xsmincdp", XX3(60,136), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6589{"xsnmaddmsp", XX3(60,137), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6590{"xxlandc", XX3(60,138), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6591{"xsrsp", XX2(60,281), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6592{"xsmaxjdp", XX3(60,144), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6593{"xsnmsubasp", XX3(60,145), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6594{"xxlor", XX3(60,146), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6595{"xscvuxdsp", XX2(60,296), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6596{"xststdcsp", XX2(60,298), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}},
6597{"xsminjdp", XX3(60,152), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6598{"xsnmsubmsp", XX3(60,153), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6599{"xxlxor", XX3(60,154), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6600{"xscvsxdsp", XX2(60,312), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6601{"xsmaxdp", XX3(60,160), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6602{"xsnmaddadp", XX3(60,161), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6603{"xxlnor", XX3(60,162), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6604{"xscvdpuxds", XX2(60,328), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6605{"xscvspdp", XX2(60,329), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6606{"xscvspdpn", XX2(60,331), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6607{"xsmindp", XX3(60,168), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6608{"xsnmaddmdp", XX3(60,169), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6609{"xxlorc", XX3(60,170), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6610{"xscvdpsxds", XX2(60,344), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6611{"xsabsdp", XX2(60,345), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6612{"xsxexpdp", XX2VA(60,347,0),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}},
6613{"xsxsigdp", XX2VA(60,347,1),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}},
6614{"xscvhpdp", XX2VA(60,347,16),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6615{"xscvdphp", XX2VA(60,347,17),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6616{"xscpsgndp", XX3(60,176), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6617{"xsnmsubadp", XX3(60,177), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6618{"xxlnand", XX3(60,178), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6619{"xscvuxddp", XX2(60,360), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6620{"xsnabsdp", XX2(60,361), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6621{"xststdcdp", XX2(60,362), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}},
6622{"xsnmsubmdp", XX3(60,185), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6623{"xxleqv", XX3(60,186), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6624{"xscvsxddp", XX2(60,376), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6625{"xsnegdp", XX2(60,377), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6626{"xvmaxsp", XX3(60,192), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6627{"xvnmaddasp", XX3(60,193), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6628{"xvcvspuxds", XX2(60,392), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6629{"xvcvdpsp", XX2(60,393), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6630{"xvminsp", XX3(60,200), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6631{"xvnmaddmsp", XX3(60,201), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6632{"xvcvspsxds", XX2(60,408), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6633{"xvabssp", XX2(60,409), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6634{"xvmovsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}},
6635{"xvcpsgnsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6636{"xvnmsubasp", XX3(60,209), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6637{"xvcvuxdsp", XX2(60,424), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6638{"xvnabssp", XX2(60,425), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6639{"xvtstdcsp", XX2(60,426), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}},
6640{"xviexpsp", XX3(60,216), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6641{"xvnmsubmsp", XX3(60,217), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6642{"xvcvsxdsp", XX2(60,440), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6643{"xvnegsp", XX2(60,441), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6644{"xvmaxdp", XX3(60,224), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6645{"xvnmaddadp", XX3(60,225), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6646{"xvcvdpuxds", XX2(60,456), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6647{"xvcvspdp", XX2(60,457), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6648{"xsiexpdp", X(60,918), XX1_MASK, PPCVSX3, PPCVLE, {XT6, RA, RB}},
6649{"xvmindp", XX3(60,232), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6650{"xvnmaddmdp", XX3(60,233), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6651{"xvcvdpsxds", XX2(60,472), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6652{"xvabsdp", XX2(60,473), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6653{"xvxexpdp", XX2VA(60,475,0),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6654{"xvxsigdp", XX2VA(60,475,1),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6655{"xxbrh", XX2VA(60,475,7),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6656{"xvxexpsp", XX2VA(60,475,8),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6657{"xvxsigsp", XX2VA(60,475,9),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6658{"xxbrw", XX2VA(60,475,15),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6659{"xxbrd", XX2VA(60,475,23),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6660{"xvcvhpsp", XX2VA(60,475,24),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6661{"xvcvsphp", XX2VA(60,475,25),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6662{"xxbrq", XX2VA(60,475,31),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6663{"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}},
6664{"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6665{"xvnmsubadp", XX3(60,241), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6666{"xvcvuxddp", XX2(60,488), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6667{"xvnabsdp", XX2(60,489), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6668{"xvtstdcdp", XX2(60,490), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}},
6669{"xviexpdp", XX3(60,248), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6670{"xvnmsubmdp", XX3(60,249), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6671{"xvcvsxddp", XX2(60,504), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6672{"xvnegdp", XX2(60,505), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6673
6674{"psq_st", OP(60), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}},
6675{"stfq", OP(60), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}},
6676
6677{"lxv", DQX(61,1), DQX_MASK, PPCVSX3, PPCVLE, {XTQ6, DQ, RA0}},
6678{"stxv", DQX(61,5), DQX_MASK, PPCVSX3, PPCVLE, {XSQ6, DQ, RA0}},
6679{"stxsd", DSO(61,2), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}},
6680{"stxssp", DSO(61,3), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}},
6681{"stfdp", OP(61), OP_MASK, POWER6, POWER7|PPCVLE, {FRSp, DS, RA0}},
6682{"psq_stu", OP(61), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}},
6683{"stfqu", OP(61), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}},
6684
6685{"std", DSO(62,0), DS_MASK, PPC64, PPCVLE, {RS, DS, RA0}},
6686{"stdu", DSO(62,1), DS_MASK, PPC64, PPCVLE, {RS, DS, RAS}},
6687{"stq", DSO(62,2), DS_MASK, POWER4, PPC476|PPCVLE, {RSQ, DS, RA0}},
6688
6689{"fcmpu", X(63,0), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}},
6690
6691{"daddq", XRC(63,2,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6692{"daddq.", XRC(63,2,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6693
6694{"dquaq", ZRC(63,3,0), Z2_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}},
6695{"dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}},
6696
6697{"xsaddqp", XRC(63,4,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6698{"xsaddqpo", XRC(63,4,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6699
6700{"xsrqpi", ZRC(63,5,0), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
6701{"xsrqpix", ZRC(63,5,1), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
6702
6703{"fcpsgn", XRC(63,8,0), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}},
6704{"fcpsgn.", XRC(63,8,1), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}},
6705
6706{"frsp", XRC(63,12,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6707{"frsp.", XRC(63,12,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6708
6709{"fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
6710{"fcir", XRC(63,14,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
6711{"fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
6712{"fcir.", XRC(63,14,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
6713
6714{"fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
6715{"fcirz", XRC(63,15,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
6716{"fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
6717{"fcirz.", XRC(63,15,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
6718
6719{"fdiv", A(63,18,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6720{"fd", A(63,18,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6721{"fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6722{"fd.", A(63,18,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6723
6724{"fsub", A(63,20,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6725{"fs", A(63,20,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6726{"fsub.", A(63,20,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6727{"fs.", A(63,20,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6728
6729{"fadd", A(63,21,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6730{"fa", A(63,21,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6731{"fadd.", A(63,21,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6732{"fa.", A(63,21,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6733
6734{"fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}},
6735{"fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}},
6736
6737{"fsel", A(63,23,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6738{"fsel.", A(63,23,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6739
6740{"fre", A(63,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6741{"fre", A(63,24,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
6742{"fre.", A(63,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6743{"fre.", A(63,24,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
6744
6745{"fmul", A(63,25,0), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
6746{"fm", A(63,25,0), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}},
6747{"fmul.", A(63,25,1), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
6748{"fm.", A(63,25,1), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}},
6749
6750{"frsqrte", A(63,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6751{"frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
6752{"frsqrte.", A(63,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6753{"frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
6754
6755{"fmsub", A(63,28,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6756{"fms", A(63,28,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6757{"fmsub.", A(63,28,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6758{"fms.", A(63,28,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6759
6760{"fmadd", A(63,29,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6761{"fma", A(63,29,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6762{"fmadd.", A(63,29,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6763{"fma.", A(63,29,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6764
6765{"fnmsub", A(63,30,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6766{"fnms", A(63,30,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6767{"fnmsub.", A(63,30,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6768{"fnms.", A(63,30,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6769
6770{"fnmadd", A(63,31,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6771{"fnma", A(63,31,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6772{"fnmadd.", A(63,31,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6773{"fnma.", A(63,31,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6774
6775{"fcmpo", X(63,32), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}},
6776
6777{"dmulq", XRC(63,34,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6778{"dmulq.", XRC(63,34,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6779
6780{"drrndq", ZRC(63,35,0), Z2_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}},
6781{"drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}},
6782
6783{"xsmulqp", XRC(63,36,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6784{"xsmulqpo", XRC(63,36,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6785
6786{"xsrqpxp", Z(63,37), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
6787
6788{"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, PPCVLE, {BT}},
6789{"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, PPCVLE, {BT}},
6790
6791{"fneg", XRC(63,40,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6792{"fneg.", XRC(63,40,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6793
6794{"mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}},
6795
6796{"dscliq", ZRC(63,66,0), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
6797{"dscliq.", ZRC(63,66,1), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
6798
6799{"dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}},
6800{"dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}},
6801
6802{"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, PPCVLE, {BT}},
6803{"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, PPCVLE, {BT}},
6804
6805{"fmr", XRC(63,72,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6806{"fmr.", XRC(63,72,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6807
6808{"dscriq", ZRC(63,98,0), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
6809{"dscriq.", ZRC(63,98,1), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
6810
6811{"drintxq", ZRC(63,99,0), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
6812{"drintxq.", ZRC(63,99,1), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
6813
6814{"xscpsgnqp", X(63,100), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6815
6816{"ftdiv", X(63,128), XBF_MASK, POWER7, PPCVLE, {BF, FRA, FRB}},
6817
6818{"dcmpoq", X(63,130), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
6819
6820{"xscmpoqp", X(63,132), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
6821
6822{"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}},
6823{"mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}},
6824{"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}},
6825{"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}},
6826
6827{"fnabs", XRC(63,136,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6828{"fnabs.", XRC(63,136,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6829
6830{"fctiwu", XRC(63,142,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6831{"fctiwu.", XRC(63,142,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6832{"fctiwuz", XRC(63,143,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6833{"fctiwuz.", XRC(63,143,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6834
6835{"ftsqrt", X(63,160), XBF_MASK|FRA_MASK, POWER7, PPCVLE, {BF, FRB}},
6836
6837{"dtstexq", X(63,162), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
6838
6839{"xscmpexpqp", X(63,164), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
6840
6841{"dtstdcq", Z(63,194), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DCM}},
6842{"dtstdgq", Z(63,226), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DGM}},
6843
6844{"drintnq", ZRC(63,227,0), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
6845{"drintnq.", ZRC(63,227,1), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
6846
6847{"dctqpq", XRC(63,258,0), X_MASK, POWER6, PPCVLE, {FRTp, FRB}},
6848{"dctqpq.", XRC(63,258,1), X_MASK, POWER6, PPCVLE, {FRTp, FRB}},
6849
6850{"fabs", XRC(63,264,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6851{"fabs.", XRC(63,264,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6852
6853{"dctfixq", XRC(63,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
6854{"dctfixq.", XRC(63,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
6855
6856{"ddedpdq", XRC(63,322,0), X_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}},
6857{"ddedpdq.", XRC(63,322,1), X_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}},
6858
6859{"dxexq", XRC(63,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
6860{"dxexq.", XRC(63,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
6861
6862{"xsmaddqp", XRC(63,388,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6863{"xsmaddqpo", XRC(63,388,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6864
6865{"frin", XRC(63,392,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6866{"frin.", XRC(63,392,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6867
6868{"xsmsubqp", XRC(63,420,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6869{"xsmsubqpo", XRC(63,420,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6870
6871{"friz", XRC(63,424,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6872{"friz.", XRC(63,424,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6873
6874{"xsnmaddqp", XRC(63,452,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6875{"xsnmaddqpo", XRC(63,452,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6876
6877{"frip", XRC(63,456,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6878{"frip.", XRC(63,456,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6879
6880{"xsnmsubqp", XRC(63,484,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6881{"xsnmsubqpo", XRC(63,484,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6882
6883{"frim", XRC(63,488,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6884{"frim.", XRC(63,488,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6885
6886{"dsubq", XRC(63,514,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6887{"dsubq.", XRC(63,514,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6888
6889{"xssubqp", XRC(63,516,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6890{"xssubqpo", XRC(63,516,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6891
6892{"ddivq", XRC(63,546,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6893{"ddivq.", XRC(63,546,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6894
6895{"xsdivqp", XRC(63,548,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6896{"xsdivqpo", XRC(63,548,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6897
6898{"mffs", XRC(63,583,0), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}},
6899{"mffs.", XRC(63,583,1), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}},
6900
6901{"mffsce", XMMF(63,583,0,1), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}},
6902{"mffscdrn", XMMF(63,583,2,4), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}},
6903{"mffscdrni", XMMF(63,583,2,5), XMMF_MASK|(3<<14), POWER9, PPCVLE, {FRT, DRM}},
6904{"mffscrn", XMMF(63,583,2,6), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}},
6905{"mffscrni", XMMF(63,583,2,7), XMMF_MASK|(7<<13), POWER9, PPCVLE, {FRT, RM}},
6906{"mffsl", XMMF(63,583,3,0), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}},
6907
6908{"dcmpuq", X(63,642), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
6909
6910{"xscmpuqp", X(63,644), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
6911
6912{"dtstsfq", X(63,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRBp}},
6913{"dtstsfiq", X(63,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRBp}},
6914
6915{"xststdcqp", X(63,708), X_MASK, PPCVSX3, PPCVLE, {BF, VB, DCMX}},
6916
6917{"mtfsf", XFL(63,711,0), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}},
6918{"mtfsf", XFL(63,711,0), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}},
6919{"mtfsf.", XFL(63,711,1), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}},
6920{"mtfsf.", XFL(63,711,1), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}},
6921
6922{"drdpq", XRC(63,770,0), X_MASK, POWER6, PPCVLE, {FRTp, FRBp}},
6923{"drdpq.", XRC(63,770,1), X_MASK, POWER6, PPCVLE, {FRTp, FRBp}},
6924
6925{"dcffixq", XRC(63,802,0), X_MASK, POWER6, PPCVLE, {FRTp, FRB}},
6926{"dcffixq.", XRC(63,802,1), X_MASK, POWER6, PPCVLE, {FRTp, FRB}},
6927
6928{"xsabsqp", XVA(63,804,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6929{"xsxexpqp", XVA(63,804,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6930{"xsnabsqp", XVA(63,804,8), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6931{"xsnegqp", XVA(63,804,16), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6932{"xsxsigqp", XVA(63,804,18), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6933{"xssqrtqp", XVARC(63,804,27,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6934{"xssqrtqpo", XVARC(63,804,27,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6935
6936{"fctid", XRC(63,814,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6937{"fctid", XRC(63,814,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
6938{"fctid.", XRC(63,814,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6939{"fctid.", XRC(63,814,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
6940
6941{"fctidz", XRC(63,815,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6942{"fctidz", XRC(63,815,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
6943{"fctidz.", XRC(63,815,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6944{"fctidz.", XRC(63,815,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
6945
6946{"denbcdq", XRC(63,834,0), X_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}},
6947{"denbcdq.", XRC(63,834,1), X_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}},
6948
6949{"xscvqpuwz", XVA(63,836,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6950{"xscvudqp", XVA(63,836,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6951{"xscvqpswz", XVA(63,836,9), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6952{"xscvsdqp", XVA(63,836,10), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6953{"xscvqpudz", XVA(63,836,17), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6954{"xscvqpdp", XVARC(63,836,20,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6955{"xscvqpdpo", XVARC(63,836,20,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6956{"xscvdpqp", XVA(63,836,22), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6957{"xscvqpsdz", XVA(63,836,25), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6958
6959{"fmrgow", X(63,838), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}},
6960
6961{"fcfid", XRC(63,846,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6962{"fcfid", XRC(63,846,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
6963{"fcfid.", XRC(63,846,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6964{"fcfid.", XRC(63,846,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
6965
6966{"diexq", XRC(63,866,0), X_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}},
6967{"diexq.", XRC(63,866,1), X_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}},
6968
6969{"xsiexpqp", X(63,868), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6970
6971{"fctidu", XRC(63,942,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6972{"fctidu.", XRC(63,942,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6973
6974{"fctiduz", XRC(63,943,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6975{"fctiduz.", XRC(63,943,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6976
6977{"fmrgew", X(63,966), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}},
6978
6979{"fcfidu", XRC(63,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6980{"fcfidu.", XRC(63,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6981};
6982
6983const int powerpc_num_opcodes =
6984 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
6985
6986/* The VLE opcode table.
6987
6988 The format of this opcode table is the same as the main opcode table. */
6989
6990const struct powerpc_opcode vle_opcodes[] = {
6991{"se_illegal", C(0), C_MASK, PPCVLE, 0, {}},
6992{"se_isync", C(1), C_MASK, PPCVLE, 0, {}},
6993{"se_sc", C(2), C_MASK, PPCVLE, 0, {}},
6994{"se_blr", C_LK(2,0), C_LK_MASK, PPCVLE, 0, {}},
6995{"se_blrl", C_LK(2,1), C_LK_MASK, PPCVLE, 0, {}},
6996{"se_bctr", C_LK(3,0), C_LK_MASK, PPCVLE, 0, {}},
6997{"se_bctrl", C_LK(3,1), C_LK_MASK, PPCVLE, 0, {}},
6998{"se_rfi", C(8), C_MASK, PPCVLE, 0, {}},
6999{"se_rfci", C(9), C_MASK, PPCVLE, 0, {}},
7000{"se_rfdi", C(10), C_MASK, PPCVLE, 0, {}},
7001{"se_rfmci", C(11), C_MASK, PPCRFMCI|PPCVLE, 0, {}},
7002{"se_not", SE_R(0,2), SE_R_MASK, PPCVLE, 0, {RX}},
7003{"se_neg", SE_R(0,3), SE_R_MASK, PPCVLE, 0, {RX}},
7004{"se_mflr", SE_R(0,8), SE_R_MASK, PPCVLE, 0, {RX}},
7005{"se_mtlr", SE_R(0,9), SE_R_MASK, PPCVLE, 0, {RX}},
7006{"se_mfctr", SE_R(0,10), SE_R_MASK, PPCVLE, 0, {RX}},
7007{"se_mtctr", SE_R(0,11), SE_R_MASK, PPCVLE, 0, {RX}},
7008{"se_extzb", SE_R(0,12), SE_R_MASK, PPCVLE, 0, {RX}},
7009{"se_extsb", SE_R(0,13), SE_R_MASK, PPCVLE, 0, {RX}},
7010{"se_extzh", SE_R(0,14), SE_R_MASK, PPCVLE, 0, {RX}},
7011{"se_extsh", SE_R(0,15), SE_R_MASK, PPCVLE, 0, {RX}},
7012{"se_mr", SE_RR(0,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7013{"se_mtar", SE_RR(0,2), SE_RR_MASK, PPCVLE, 0, {ARX, RY}},
7014{"se_mfar", SE_RR(0,3), SE_RR_MASK, PPCVLE, 0, {RX, ARY}},
7015{"se_add", SE_RR(1,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7016{"se_mullw", SE_RR(1,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7017{"se_sub", SE_RR(1,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7018{"se_subf", SE_RR(1,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7019{"se_cmp", SE_RR(3,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7020{"se_cmpl", SE_RR(3,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7021{"se_cmph", SE_RR(3,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7022{"se_cmphl", SE_RR(3,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7023
7024{"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
7025{"e_cmpwi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
7026{"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
7027{"e_cmplwi", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
7028{"e_addi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7029{"e_subi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
7030{"e_addi.", SCI8(6,17), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7031{"e_addic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7032{"e_subic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
7033{"e_addic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7034{"e_subic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
7035{"e_mulli", SCI8(6,20), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7036{"e_subfic", SCI8(6,22), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7037{"e_subfic.", SCI8(6,23), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7038{"e_andi", SCI8(6,24), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7039{"e_andi.", SCI8(6,25), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7040{"e_nop", SCI8(6,26), 0xffffffff, PPCVLE, 0, {0}},
7041{"e_ori", SCI8(6,26), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7042{"e_ori.", SCI8(6,27), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7043{"e_xori", SCI8(6,28), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7044{"e_xori.", SCI8(6,29), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7045{"e_lbzu", OPVUP(6,0), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7046{"e_lhau", OPVUP(6,3), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7047{"e_lhzu", OPVUP(6,1), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7048{"e_lmw", OPVUP(6,8), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7049{"e_lwzu", OPVUP(6,2), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7050{"e_stbu", OPVUP(6,4), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7051{"e_sthu", OPVUP(6,5), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7052{"e_stwu", OPVUP(6,6), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7053{"e_stmw", OPVUP(6,9), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7054{"e_ldmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7055{"e_stmvgprw", OPVUPRT(6,17,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7056{"e_ldmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7057{"e_stmvsprw", OPVUPRT(6,17,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7058{"e_ldmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7059{"e_stmvsrrw", OPVUPRT(6,17,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7060{"e_ldmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7061{"e_stmvcsrrw", OPVUPRT(6,17,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7062{"e_ldmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7063{"e_stmvdsrrw", OPVUPRT(6,17,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7064{"e_add16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, SI}},
7065{"e_la", OP(7), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7066{"e_sub16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, NSI}},
7067
7068{"se_addi", SE_IM5(8,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
7069{"se_cmpli", SE_IM5(8,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
7070{"se_subi", SE_IM5(9,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
7071{"se_subi.", SE_IM5(9,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
7072{"se_cmpi", SE_IM5(10,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7073{"se_bmaski", SE_IM5(11,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7074{"se_andi", SE_IM5(11,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7075
7076{"e_lbz", OP(12), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7077{"e_stb", OP(13), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7078{"e_lha", OP(14), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7079
7080{"se_srw", SE_RR(16,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7081{"se_sraw", SE_RR(16,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7082{"se_slw", SE_RR(16,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7083{"se_nop", SE_RR(17,0), 0xffff, PPCVLE, 0, {0}},
7084{"se_or", SE_RR(17,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7085{"se_andc", SE_RR(17,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7086{"se_and", SE_RR(17,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7087{"se_and.", SE_RR(17,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7088{"se_li", IM7(9), IM7_MASK, PPCVLE, 0, {RX, UI7}},
7089
7090{"e_lwz", OP(20), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7091{"e_stw", OP(21), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7092{"e_lhz", OP(22), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7093{"e_sth", OP(23), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7094
7095{"se_bclri", SE_IM5(24,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7096{"se_bgeni", SE_IM5(24,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7097{"se_bseti", SE_IM5(25,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7098{"se_btsti", SE_IM5(25,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7099{"se_srwi", SE_IM5(26,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7100{"se_srawi", SE_IM5(26,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7101{"se_slwi", SE_IM5(27,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7102
7103{"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7104{"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7105{"e_or2is", I16L(28,26), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7106{"e_and2i.", I16L(28,25), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7107{"e_or2i", I16L(28,24), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7108{"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}},
7109{"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
7110{"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}},
7111{"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
7112{"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
7113{"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
7114{"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
7115{"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
7116{"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
7117{"e_li", LI20(28,0), LI20_MASK, PPCVLE, 0, {RT, IMM20}},
7118{"e_rlwimi", M(29,0), M_MASK, PPCVLE, 0, {RA, RS, SH, MB, ME}},
7119{"e_rlwinm", M(29,1), M_MASK, PPCVLE, 0, {RA, RT, SH, MBE, ME}},
7120{"e_b", BD24(30,0,0), BD24_MASK, PPCVLE, 0, {B24}},
7121{"e_bl", BD24(30,0,1), BD24_MASK, PPCVLE, 0, {B24}},
7122{"e_bdnz", EBD15(30,8,BO32DNZ,0), EBD15_MASK, PPCVLE, 0, {B15}},
7123{"e_bdnzl", EBD15(30,8,BO32DNZ,1), EBD15_MASK, PPCVLE, 0, {B15}},
7124{"e_bdz", EBD15(30,8,BO32DZ,0), EBD15_MASK, PPCVLE, 0, {B15}},
7125{"e_bdzl", EBD15(30,8,BO32DZ,1), EBD15_MASK, PPCVLE, 0, {B15}},
7126{"e_bge", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7127{"e_bgel", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7128{"e_bnl", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7129{"e_bnll", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7130{"e_blt", EBD15BI(30,8,BO32T,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7131{"e_bltl", EBD15BI(30,8,BO32T,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7132{"e_bgt", EBD15BI(30,8,BO32T,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7133{"e_bgtl", EBD15BI(30,8,BO32T,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7134{"e_ble", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7135{"e_blel", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7136{"e_bng", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7137{"e_bngl", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7138{"e_bne", EBD15BI(30,8,BO32F,CBEQ,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7139{"e_bnel", EBD15BI(30,8,BO32F,CBEQ,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7140{"e_beq", EBD15BI(30,8,BO32T,CBEQ,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7141{"e_beql", EBD15BI(30,8,BO32T,CBEQ,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7142{"e_bso", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7143{"e_bsol", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7144{"e_bun", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7145{"e_bunl", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7146{"e_bns", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7147{"e_bnsl", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7148{"e_bnu", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7149{"e_bnul", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7150{"e_bc", BD15(30,8,0), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}},
7151{"e_bcl", BD15(30,8,1), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}},
7152
7153{"e_bf", EBD15(30,8,BO32F,0), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
7154{"e_bfl", EBD15(30,8,BO32F,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
7155{"e_bt", EBD15(30,8,BO32T,0), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
7156{"e_btl", EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
7157
7158{"e_cmph", X(31,14), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
7159{"e_cmphl", X(31,46), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
7160{"e_crandc", XL(31,129), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7161{"e_crnand", XL(31,225), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7162{"e_crnot", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BBA}},
7163{"e_crnor", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7164{"e_crclr", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BAT, BBA}},
7165{"e_crxor", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7166{"e_mcrf", XL(31,16), XL_MASK, PPCVLE, 0, {CRD, CR}},
7167{"e_slwi", EX(31,112), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7168{"e_slwi.", EX(31,113), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7169
7170{"e_crand", XL(31,257), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7171
7172{"e_rlw", EX(31,560), EX_MASK, PPCVLE, 0, {RA, RS, RB}},
7173{"e_rlw.", EX(31,561), EX_MASK, PPCVLE, 0, {RA, RS, RB}},
7174
7175{"e_crset", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BAT, BBA}},
7176{"e_creqv", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7177
7178{"e_rlwi", EX(31,624), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7179{"e_rlwi.", EX(31,625), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7180
7181{"e_crorc", XL(31,417), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7182
7183{"e_crmove", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BBA}},
7184{"e_cror", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7185
7186{"mtmas1", XSPR(31,467,625), XSPR_MASK, PPCVLE, 0, {RS}},
7187
7188{"e_srwi", EX(31,1136), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7189{"e_srwi.", EX(31,1137), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7190
7191{"se_lbz", SD4(8), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}},
7192
7193{"se_stb", SD4(9), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}},
7194
7195{"se_lhz", SD4(10), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}},
7196
7197{"se_sth", SD4(11), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}},
7198
7199{"se_lwz", SD4(12), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}},
7200
7201{"se_stw", SD4(13), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}},
7202
7203{"se_bge", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7204{"se_bnl", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7205{"se_ble", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7206{"se_bng", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7207{"se_bne", EBD8IO(28,0,2), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7208{"se_bns", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7209{"se_bnu", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7210{"se_bf", EBD8IO(28,0,0), EBD8IO2_MASK, PPCVLE, 0, {BI16, B8}},
7211{"se_blt", EBD8IO(28,1,0), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7212{"se_bgt", EBD8IO(28,1,1), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7213{"se_beq", EBD8IO(28,1,2), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7214{"se_bso", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7215{"se_bun", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7216{"se_bt", EBD8IO(28,1,0), EBD8IO2_MASK, PPCVLE, 0, {BI16, B8}},
7217{"se_bc", BD8IO(28), BD8IO_MASK, PPCVLE, 0, {BO16, BI16, B8}},
7218{"se_b", BD8(58,0,0), BD8_MASK, PPCVLE, 0, {B8}},
7219{"se_bl", BD8(58,0,1), BD8_MASK, PPCVLE, 0, {B8}},
4935}; 7220};
4936 7221
4937const int powerpc_num_opcodes = ARRAY_SIZE(powerpc_opcodes); 7222const int vle_num_opcodes =
7223 sizeof (vle_opcodes) / sizeof (vle_opcodes[0]);
4938 7224
4939/* The macro table. This is only used by the assembler. */ 7225/* The macro table. This is only used by the assembler. */
4940 7226
@@ -4949,45 +7235,58 @@ const int powerpc_num_opcodes = ARRAY_SIZE(powerpc_opcodes);
4949 support extracting the whole word (32 bits in this case). */ 7235 support extracting the whole word (32 bits in this case). */
4950 7236
4951const struct powerpc_macro powerpc_macros[] = { 7237const struct powerpc_macro powerpc_macros[] = {
4952{ "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" }, 7238{"extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1"},
4953{ "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" }, 7239{"extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1"},
4954{ "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" }, 7240{"extrdi", 4, PPC64, "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
4955{ "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" }, 7241{"extrdi.", 4, PPC64, "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
4956{ "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" }, 7242{"insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3"},
4957{ "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" }, 7243{"insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3"},
4958{ "rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" }, 7244{"rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"},
4959{ "rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" }, 7245{"rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"},
4960{ "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" }, 7246{"sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)"},
4961{ "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" }, 7247{"sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)"},
4962{ "srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" }, 7248{"srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"},
4963{ "srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" }, 7249{"srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"},
4964{ "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" }, 7250{"clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)"},
4965{ "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" }, 7251{"clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)"},
4966{ "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" }, 7252{"clrlsldi", 4, PPC64, "rldic %0,%1,%3,(%2)-(%3)"},
4967{ "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" }, 7253{"clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)"},
4968 7254
4969{ "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" }, 7255{"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"},
4970{ "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" }, 7256{"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"},
4971{ "extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" }, 7257{"extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
4972{ "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" }, 7258{"extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
4973{ "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" }, 7259{"inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4974{ "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"}, 7260{"inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4975{ "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" }, 7261{"insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4976{ "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, 7262{"insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4977{ "rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" }, 7263{"rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
4978{ "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" }, 7264{"rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"},
4979{ "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" }, 7265{"slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"},
4980{ "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" }, 7266{"sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"},
4981{ "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" }, 7267{"slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"},
4982{ "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" }, 7268{"sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)"},
4983{ "srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, 7269{"srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
4984{ "sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, 7270{"sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
4985{ "srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, 7271{"srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
4986{ "sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, 7272{"sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
4987{ "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" }, 7273{"clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"},
4988{ "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" }, 7274{"clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"},
4989{ "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" }, 7275{"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
4990{ "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" }, 7276{"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
7277
7278{"e_extlwi", 4, PPCVLE, "e_rlwinm %0,%1,%3,0,(%2)-1"},
7279{"e_extrwi", 4, PPCVLE, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
7280{"e_inslwi", 4, PPCVLE, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
7281{"e_insrwi", 4, PPCVLE, "e_rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
7282{"e_rotlwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31"},
7283{"e_rotrwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
7284{"e_slwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31-(%2)"},
7285{"e_srwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7286{"e_clrlwi", 3, PPCVLE, "e_rlwinm %0,%1,0,%2,31"},
7287{"e_clrrwi", 3, PPCVLE, "e_rlwinm %0,%1,0,0,31-(%2)"},
7288{"e_clrlslwi",4, PPCVLE, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
4991}; 7289};
4992 7290
4993const int powerpc_num_macros = ARRAY_SIZE(powerpc_macros); 7291const int powerpc_num_macros =
7292 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
diff --git a/arch/powerpc/xmon/ppc.h b/arch/powerpc/xmon/ppc.h
index 110df96354b4..d00f33dcf192 100644
--- a/arch/powerpc/xmon/ppc.h
+++ b/arch/powerpc/xmon/ppc.h
@@ -1,6 +1,5 @@
1/* ppc.h -- Header file for PowerPC opcode table 1/* ppc.h -- Header file for PowerPC opcode table
2 Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006 2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
3 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support 3 Written by Ian Lance Taylor, Cygnus Support
5 4
6This file is part of GDB, GAS, and the GNU binutils. 5This file is part of GDB, GAS, and the GNU binutils.
@@ -22,6 +21,12 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, US
22#ifndef PPC_H 21#ifndef PPC_H
23#define PPC_H 22#define PPC_H
24 23
24#ifdef __cplusplus
25extern "C" {
26#endif
27
28typedef uint64_t ppc_cpu_t;
29
25/* The opcode table is an array of struct powerpc_opcode. */ 30/* The opcode table is an array of struct powerpc_opcode. */
26 31
27struct powerpc_opcode 32struct powerpc_opcode
@@ -42,7 +47,12 @@ struct powerpc_opcode
42 /* One bit flags for the opcode. These are used to indicate which 47 /* One bit flags for the opcode. These are used to indicate which
43 specific processors support the instructions. The defined values 48 specific processors support the instructions. The defined values
44 are listed below. */ 49 are listed below. */
45 unsigned long flags; 50 ppc_cpu_t flags;
51
52 /* One bit flags for the opcode. These are used to indicate which
53 specific processors no longer support the instructions. The defined
54 values are listed below. */
55 ppc_cpu_t deprecated;
46 56
47 /* An array of operand codes. Each code is an index into the 57 /* An array of operand codes. Each code is an index into the
48 operand table. They appear in the order which the operands must 58 operand table. They appear in the order which the operands must
@@ -55,6 +65,8 @@ struct powerpc_opcode
55 instructions. */ 65 instructions. */
56extern const struct powerpc_opcode powerpc_opcodes[]; 66extern const struct powerpc_opcode powerpc_opcodes[];
57extern const int powerpc_num_opcodes; 67extern const int powerpc_num_opcodes;
68extern const struct powerpc_opcode vle_opcodes[];
69extern const int vle_num_opcodes;
58 70
59/* Values defined for the flags field of a struct powerpc_opcode. */ 71/* Values defined for the flags field of a struct powerpc_opcode. */
60 72
@@ -67,106 +79,178 @@ extern const int powerpc_num_opcodes;
67/* Opcode is defined for the POWER2 (Rios 2) architecture. */ 79/* Opcode is defined for the POWER2 (Rios 2) architecture. */
68#define PPC_OPCODE_POWER2 4 80#define PPC_OPCODE_POWER2 4
69 81
70/* Opcode is only defined on 32 bit architectures. */
71#define PPC_OPCODE_32 8
72
73/* Opcode is only defined on 64 bit architectures. */
74#define PPC_OPCODE_64 0x10
75
76/* Opcode is supported by the Motorola PowerPC 601 processor. The 601 82/* Opcode is supported by the Motorola PowerPC 601 processor. The 601
77 is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions, 83 is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
78 but it also supports many additional POWER instructions. */ 84 but it also supports many additional POWER instructions. */
79#define PPC_OPCODE_601 0x20 85#define PPC_OPCODE_601 8
80 86
81/* Opcode is supported in both the Power and PowerPC architectures 87/* Opcode is supported in both the Power and PowerPC architectures
82 (ie, compiler's -mcpu=common or assembler's -mcom). */ 88 (ie, compiler's -mcpu=common or assembler's -mcom). More than just
83#define PPC_OPCODE_COMMON 0x40 89 the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER
90 and PPC_OPCODE_POWER2 because many instructions changed mnemonics
91 between POWER and POWERPC. */
92#define PPC_OPCODE_COMMON 0x10
84 93
85/* Opcode is supported for any Power or PowerPC platform (this is 94/* Opcode is supported for any Power or PowerPC platform (this is
86 for the assembler's -many option, and it eliminates duplicates). */ 95 for the assembler's -many option, and it eliminates duplicates). */
87#define PPC_OPCODE_ANY 0x80 96#define PPC_OPCODE_ANY 0x20
97
98/* Opcode is only defined on 64 bit architectures. */
99#define PPC_OPCODE_64 0x40
88 100
89/* Opcode is supported as part of the 64-bit bridge. */ 101/* Opcode is supported as part of the 64-bit bridge. */
90#define PPC_OPCODE_64_BRIDGE 0x100 102#define PPC_OPCODE_64_BRIDGE 0x80
91 103
92/* Opcode is supported by Altivec Vector Unit */ 104/* Opcode is supported by Altivec Vector Unit */
93#define PPC_OPCODE_ALTIVEC 0x200 105#define PPC_OPCODE_ALTIVEC 0x100
94 106
95/* Opcode is supported by PowerPC 403 processor. */ 107/* Opcode is supported by PowerPC 403 processor. */
96#define PPC_OPCODE_403 0x400 108#define PPC_OPCODE_403 0x200
97 109
98/* Opcode is supported by PowerPC BookE processor. */ 110/* Opcode is supported by PowerPC BookE processor. */
99#define PPC_OPCODE_BOOKE 0x800 111#define PPC_OPCODE_BOOKE 0x400
100
101/* Opcode is only supported by 64-bit PowerPC BookE processor. */
102#define PPC_OPCODE_BOOKE64 0x1000
103 112
104/* Opcode is supported by PowerPC 440 processor. */ 113/* Opcode is supported by PowerPC 440 processor. */
105#define PPC_OPCODE_440 0x2000 114#define PPC_OPCODE_440 0x800
106 115
107/* Opcode is only supported by Power4 architecture. */ 116/* Opcode is only supported by Power4 architecture. */
108#define PPC_OPCODE_POWER4 0x4000 117#define PPC_OPCODE_POWER4 0x1000
109
110/* Opcode isn't supported by Power4 architecture. */
111#define PPC_OPCODE_NOPOWER4 0x8000
112 118
113/* Opcode is only supported by POWERPC Classic architecture. */ 119/* Opcode is only supported by Power7 architecture. */
114#define PPC_OPCODE_CLASSIC 0x10000 120#define PPC_OPCODE_POWER7 0x2000
115 121
116/* Opcode is only supported by e500x2 Core. */ 122/* Opcode is only supported by e500x2 Core. */
117#define PPC_OPCODE_SPE 0x20000 123#define PPC_OPCODE_SPE 0x4000
118 124
119/* Opcode is supported by e500x2 Integer select APU. */ 125/* Opcode is supported by e500x2 Integer select APU. */
120#define PPC_OPCODE_ISEL 0x40000 126#define PPC_OPCODE_ISEL 0x8000
121 127
122/* Opcode is an e500 SPE floating point instruction. */ 128/* Opcode is an e500 SPE floating point instruction. */
123#define PPC_OPCODE_EFS 0x80000 129#define PPC_OPCODE_EFS 0x10000
124 130
125/* Opcode is supported by branch locking APU. */ 131/* Opcode is supported by branch locking APU. */
126#define PPC_OPCODE_BRLOCK 0x100000 132#define PPC_OPCODE_BRLOCK 0x20000
127 133
128/* Opcode is supported by performance monitor APU. */ 134/* Opcode is supported by performance monitor APU. */
129#define PPC_OPCODE_PMR 0x200000 135#define PPC_OPCODE_PMR 0x40000
130 136
131/* Opcode is supported by cache locking APU. */ 137/* Opcode is supported by cache locking APU. */
132#define PPC_OPCODE_CACHELCK 0x400000 138#define PPC_OPCODE_CACHELCK 0x80000
133 139
134/* Opcode is supported by machine check APU. */ 140/* Opcode is supported by machine check APU. */
135#define PPC_OPCODE_RFMCI 0x800000 141#define PPC_OPCODE_RFMCI 0x100000
136 142
137/* Opcode is only supported by Power5 architecture. */ 143/* Opcode is only supported by Power5 architecture. */
138#define PPC_OPCODE_POWER5 0x1000000 144#define PPC_OPCODE_POWER5 0x200000
139 145
140/* Opcode is supported by PowerPC e300 family. */ 146/* Opcode is supported by PowerPC e300 family. */
141#define PPC_OPCODE_E300 0x2000000 147#define PPC_OPCODE_E300 0x400000
142 148
143/* Opcode is only supported by Power6 architecture. */ 149/* Opcode is only supported by Power6 architecture. */
144#define PPC_OPCODE_POWER6 0x4000000 150#define PPC_OPCODE_POWER6 0x800000
145 151
146/* Opcode is only supported by PowerPC Cell family. */ 152/* Opcode is only supported by PowerPC Cell family. */
147#define PPC_OPCODE_CELL 0x8000000 153#define PPC_OPCODE_CELL 0x1000000
154
155/* Opcode is supported by CPUs with paired singles support. */
156#define PPC_OPCODE_PPCPS 0x2000000
157
158/* Opcode is supported by Power E500MC */
159#define PPC_OPCODE_E500MC 0x4000000
160
161/* Opcode is supported by PowerPC 405 processor. */
162#define PPC_OPCODE_405 0x8000000
163
164/* Opcode is supported by Vector-Scalar (VSX) Unit */
165#define PPC_OPCODE_VSX 0x10000000
166
167/* Opcode is supported by A2. */
168#define PPC_OPCODE_A2 0x20000000
169
170/* Opcode is supported by PowerPC 476 processor. */
171#define PPC_OPCODE_476 0x40000000
172
173/* Opcode is supported by AppliedMicro Titan core */
174#define PPC_OPCODE_TITAN 0x80000000
175
176/* Opcode which is supported by the e500 family */
177#define PPC_OPCODE_E500 0x100000000ull
178
179/* Opcode is supported by Extended Altivec Vector Unit */
180#define PPC_OPCODE_ALTIVEC2 0x200000000ull
181
182/* Opcode is supported by Power E6500 */
183#define PPC_OPCODE_E6500 0x400000000ull
184
185/* Opcode is supported by Thread management APU */
186#define PPC_OPCODE_TMR 0x800000000ull
187
188/* Opcode which is supported by the VLE extension. */
189#define PPC_OPCODE_VLE 0x1000000000ull
190
191/* Opcode is only supported by Power8 architecture. */
192#define PPC_OPCODE_POWER8 0x2000000000ull
193
194/* Opcode which is supported by the Hardware Transactional Memory extension. */
195/* Currently, this is the same as the POWER8 mask. If another cpu comes out
196 that isn't a superset of POWER8, we can define this to its own mask. */
197#define PPC_OPCODE_HTM PPC_OPCODE_POWER8
198
199/* Opcode is supported by ppc750cl. */
200#define PPC_OPCODE_750 0x4000000000ull
201
202/* Opcode is supported by ppc7450. */
203#define PPC_OPCODE_7450 0x8000000000ull
204
205/* Opcode is supported by ppc821/850/860. */
206#define PPC_OPCODE_860 0x10000000000ull
207
208/* Opcode is only supported by Power9 architecture. */
209#define PPC_OPCODE_POWER9 0x20000000000ull
210
211/* Opcode is supported by Vector-Scalar (VSX) Unit from ISA 2.08. */
212#define PPC_OPCODE_VSX3 0x40000000000ull
213
214 /* Opcode is supported by e200z4. */
215#define PPC_OPCODE_E200Z4 0x80000000000ull
148 216
149/* A macro to extract the major opcode from an instruction. */ 217/* A macro to extract the major opcode from an instruction. */
150#define PPC_OP(i) (((i) >> 26) & 0x3f) 218#define PPC_OP(i) (((i) >> 26) & 0x3f)
219
220/* A macro to determine if the instruction is a 2-byte VLE insn. */
221#define PPC_OP_SE_VLE(m) ((m) <= 0xffff)
222
223/* A macro to extract the major opcode from a VLE instruction. */
224#define VLE_OP(i,m) (((i) >> ((m) <= 0xffff ? 10 : 26)) & 0x3f)
225
226/* A macro to convert a VLE opcode to a VLE opcode segment. */
227#define VLE_OP_TO_SEG(i) ((i) >> 1)
151 228
152/* The operands table is an array of struct powerpc_operand. */ 229/* The operands table is an array of struct powerpc_operand. */
153 230
154struct powerpc_operand 231struct powerpc_operand
155{ 232{
156 /* The number of bits in the operand. */ 233 /* A bitmask of bits in the operand. */
157 int bits; 234 unsigned int bitm;
158 235
159 /* How far the operand is left shifted in the instruction. */ 236 /* The shift operation to be applied to the operand. No shift
237 is made if this is zero. For positive values, the operand
238 is shifted left by SHIFT. For negative values, the operand
239 is shifted right by -SHIFT. Use PPC_OPSHIFT_INV to indicate
240 that BITM and SHIFT cannot be used to determine where the
241 operand goes in the insn. */
160 int shift; 242 int shift;
161 243
162 /* Insertion function. This is used by the assembler. To insert an 244 /* Insertion function. This is used by the assembler. To insert an
163 operand value into an instruction, check this field. 245 operand value into an instruction, check this field.
164 246
165 If it is NULL, execute 247 If it is NULL, execute
166 i |= (op & ((1 << o->bits) - 1)) << o->shift; 248 if (o->shift >= 0)
249 i |= (op & o->bitm) << o->shift;
250 else
251 i |= (op & o->bitm) >> -o->shift;
167 (i is the instruction which we are filling in, o is a pointer to 252 (i is the instruction which we are filling in, o is a pointer to
168 this structure, and op is the opcode value; this assumes twos 253 this structure, and op is the operand value).
169 complement arithmetic).
170 254
171 If this field is not NULL, then simply call it with the 255 If this field is not NULL, then simply call it with the
172 instruction and the operand value. It will return the new value 256 instruction and the operand value. It will return the new value
@@ -176,18 +260,20 @@ struct powerpc_operand
176 operand value is legal, *ERRMSG will be unchanged (most operands 260 operand value is legal, *ERRMSG will be unchanged (most operands
177 can accept any value). */ 261 can accept any value). */
178 unsigned long (*insert) 262 unsigned long (*insert)
179 (unsigned long instruction, long op, int dialect, const char **errmsg); 263 (unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg);
180 264
181 /* Extraction function. This is used by the disassembler. To 265 /* Extraction function. This is used by the disassembler. To
182 extract this operand type from an instruction, check this field. 266 extract this operand type from an instruction, check this field.
183 267
184 If it is NULL, compute 268 If it is NULL, compute
185 op = ((i) >> o->shift) & ((1 << o->bits) - 1); 269 if (o->shift >= 0)
186 if ((o->flags & PPC_OPERAND_SIGNED) != 0 270 op = (i >> o->shift) & o->bitm;
187 && (op & (1 << (o->bits - 1))) != 0) 271 else
188 op -= 1 << o->bits; 272 op = (i << -o->shift) & o->bitm;
273 if ((o->flags & PPC_OPERAND_SIGNED) != 0)
274 sign_extend (op);
189 (i is the instruction, o is a pointer to this structure, and op 275 (i is the instruction, o is a pointer to this structure, and op
190 is the result; this assumes twos complement arithmetic). 276 is the result).
191 277
192 If this field is not NULL, then simply call it with the 278 If this field is not NULL, then simply call it with the
193 instruction value. It will return the value of the operand. If 279 instruction value. It will return the value of the operand. If
@@ -195,7 +281,7 @@ struct powerpc_operand
195 non-zero if this operand type can not actually be extracted from 281 non-zero if this operand type can not actually be extracted from
196 this operand (i.e., the instruction does not match). If the 282 this operand (i.e., the instruction does not match). If the
197 operand is valid, *INVALID will not be changed. */ 283 operand is valid, *INVALID will not be changed. */
198 long (*extract) (unsigned long instruction, int dialect, int *invalid); 284 long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid);
199 285
200 /* One bit syntax flags. */ 286 /* One bit syntax flags. */
201 unsigned long flags; 287 unsigned long flags;
@@ -205,17 +291,23 @@ struct powerpc_operand
205 the operands field of the powerpc_opcodes table. */ 291 the operands field of the powerpc_opcodes table. */
206 292
207extern const struct powerpc_operand powerpc_operands[]; 293extern const struct powerpc_operand powerpc_operands[];
294extern const unsigned int num_powerpc_operands;
295
296/* Use with the shift field of a struct powerpc_operand to indicate
297 that BITM and SHIFT cannot be used to determine where the operand
298 goes in the insn. */
299#define PPC_OPSHIFT_INV (-1U << 31)
208 300
209/* Values defined for the flags field of a struct powerpc_operand. */ 301/* Values defined for the flags field of a struct powerpc_operand. */
210 302
211/* This operand takes signed values. */ 303/* This operand takes signed values. */
212#define PPC_OPERAND_SIGNED (01) 304#define PPC_OPERAND_SIGNED (0x1)
213 305
214/* This operand takes signed values, but also accepts a full positive 306/* This operand takes signed values, but also accepts a full positive
215 range of values when running in 32 bit mode. That is, if bits is 307 range of values when running in 32 bit mode. That is, if bits is
216 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode, 308 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
217 this flag is ignored. */ 309 this flag is ignored. */
218#define PPC_OPERAND_SIGNOPT (02) 310#define PPC_OPERAND_SIGNOPT (0x2)
219 311
220/* This operand does not actually exist in the assembler input. This 312/* This operand does not actually exist in the assembler input. This
221 is used to support extended mnemonics such as mr, for which two 313 is used to support extended mnemonics such as mr, for which two
@@ -223,14 +315,14 @@ extern const struct powerpc_operand powerpc_operands[];
223 insert function with any op value. The disassembler should call 315 insert function with any op value. The disassembler should call
224 the extract function, ignore the return value, and check the value 316 the extract function, ignore the return value, and check the value
225 placed in the valid argument. */ 317 placed in the valid argument. */
226#define PPC_OPERAND_FAKE (04) 318#define PPC_OPERAND_FAKE (0x4)
227 319
228/* The next operand should be wrapped in parentheses rather than 320/* The next operand should be wrapped in parentheses rather than
229 separated from this one by a comma. This is used for the load and 321 separated from this one by a comma. This is used for the load and
230 store instructions which want their operands to look like 322 store instructions which want their operands to look like
231 reg,displacement(reg) 323 reg,displacement(reg)
232 */ 324 */
233#define PPC_OPERAND_PARENS (010) 325#define PPC_OPERAND_PARENS (0x8)
234 326
235/* This operand may use the symbolic names for the CR fields, which 327/* This operand may use the symbolic names for the CR fields, which
236 are 328 are
@@ -239,26 +331,26 @@ extern const struct powerpc_operand powerpc_operands[];
239 cr4 4 cr5 5 cr6 6 cr7 7 331 cr4 4 cr5 5 cr6 6 cr7 7
240 These may be combined arithmetically, as in cr2*4+gt. These are 332 These may be combined arithmetically, as in cr2*4+gt. These are
241 only supported on the PowerPC, not the POWER. */ 333 only supported on the PowerPC, not the POWER. */
242#define PPC_OPERAND_CR (020) 334#define PPC_OPERAND_CR_BIT (0x10)
243 335
244/* This operand names a register. The disassembler uses this to print 336/* This operand names a register. The disassembler uses this to print
245 register names with a leading 'r'. */ 337 register names with a leading 'r'. */
246#define PPC_OPERAND_GPR (040) 338#define PPC_OPERAND_GPR (0x20)
247 339
248/* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */ 340/* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */
249#define PPC_OPERAND_GPR_0 (0100) 341#define PPC_OPERAND_GPR_0 (0x40)
250 342
251/* This operand names a floating point register. The disassembler 343/* This operand names a floating point register. The disassembler
252 prints these with a leading 'f'. */ 344 prints these with a leading 'f'. */
253#define PPC_OPERAND_FPR (0200) 345#define PPC_OPERAND_FPR (0x80)
254 346
255/* This operand is a relative branch displacement. The disassembler 347/* This operand is a relative branch displacement. The disassembler
256 prints these symbolically if possible. */ 348 prints these symbolically if possible. */
257#define PPC_OPERAND_RELATIVE (0400) 349#define PPC_OPERAND_RELATIVE (0x100)
258 350
259/* This operand is an absolute branch address. The disassembler 351/* This operand is an absolute branch address. The disassembler
260 prints these symbolically if possible. */ 352 prints these symbolically if possible. */
261#define PPC_OPERAND_ABSOLUTE (01000) 353#define PPC_OPERAND_ABSOLUTE (0x200)
262 354
263/* This operand is optional, and is zero if omitted. This is used for 355/* This operand is optional, and is zero if omitted. This is used for
264 example, in the optional BF field in the comparison instructions. The 356 example, in the optional BF field in the comparison instructions. The
@@ -266,7 +358,7 @@ extern const struct powerpc_operand powerpc_operands[];
266 and the number of operands remaining for the opcode, and decide 358 and the number of operands remaining for the opcode, and decide
267 whether this operand is present or not. The disassembler should 359 whether this operand is present or not. The disassembler should
268 print this operand out only if it is not zero. */ 360 print this operand out only if it is not zero. */
269#define PPC_OPERAND_OPTIONAL (02000) 361#define PPC_OPERAND_OPTIONAL (0x400)
270 362
271/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand 363/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
272 is omitted, then for the next operand use this operand value plus 364 is omitted, then for the next operand use this operand value plus
@@ -274,24 +366,48 @@ extern const struct powerpc_operand powerpc_operands[];
274 hack is needed because the Power rotate instructions can take 366 hack is needed because the Power rotate instructions can take
275 either 4 or 5 operands. The disassembler should print this operand 367 either 4 or 5 operands. The disassembler should print this operand
276 out regardless of the PPC_OPERAND_OPTIONAL field. */ 368 out regardless of the PPC_OPERAND_OPTIONAL field. */
277#define PPC_OPERAND_NEXT (04000) 369#define PPC_OPERAND_NEXT (0x800)
278 370
279/* This operand should be regarded as a negative number for the 371/* This operand should be regarded as a negative number for the
280 purposes of overflow checking (i.e., the normal most negative 372 purposes of overflow checking (i.e., the normal most negative
281 number is disallowed and one more than the normal most positive 373 number is disallowed and one more than the normal most positive
282 number is allowed). This flag will only be set for a signed 374 number is allowed). This flag will only be set for a signed
283 operand. */ 375 operand. */
284#define PPC_OPERAND_NEGATIVE (010000) 376#define PPC_OPERAND_NEGATIVE (0x1000)
285 377
286/* This operand names a vector unit register. The disassembler 378/* This operand names a vector unit register. The disassembler
287 prints these with a leading 'v'. */ 379 prints these with a leading 'v'. */
288#define PPC_OPERAND_VR (020000) 380#define PPC_OPERAND_VR (0x2000)
289 381
290/* This operand is for the DS field in a DS form instruction. */ 382/* This operand is for the DS field in a DS form instruction. */
291#define PPC_OPERAND_DS (040000) 383#define PPC_OPERAND_DS (0x4000)
292 384
293/* This operand is for the DQ field in a DQ form instruction. */ 385/* This operand is for the DQ field in a DQ form instruction. */
294#define PPC_OPERAND_DQ (0100000) 386#define PPC_OPERAND_DQ (0x8000)
387
388/* Valid range of operand is 0..n rather than 0..n-1. */
389#define PPC_OPERAND_PLUS1 (0x10000)
390
391/* Xilinx APU and FSL related operands */
392#define PPC_OPERAND_FSL (0x20000)
393#define PPC_OPERAND_FCR (0x40000)
394#define PPC_OPERAND_UDI (0x80000)
395
396/* This operand names a vector-scalar unit register. The disassembler
397 prints these with a leading 'vs'. */
398#define PPC_OPERAND_VSR (0x100000)
399
400/* This is a CR FIELD that does not use symbolic names. */
401#define PPC_OPERAND_CR_REG (0x200000)
402
403/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
404 is omitted, then the value it should use for the operand is stored
405 in the SHIFT field of the immediatly following operand field. */
406#define PPC_OPERAND_OPTIONAL_VALUE (0x400000)
407
408/* This flag is only used with PPC_OPERAND_OPTIONAL. The operand is
409 only optional when generating 32-bit code. */
410#define PPC_OPERAND_OPTIONAL32 (0x800000)
295 411
296/* The POWER and PowerPC assemblers use a few macros. We keep them 412/* The POWER and PowerPC assemblers use a few macros. We keep them
297 with the operands table for simplicity. The macro table is an 413 with the operands table for simplicity. The macro table is an
@@ -308,7 +424,7 @@ struct powerpc_macro
308 /* One bit flags for the opcode. These are used to indicate which 424 /* One bit flags for the opcode. These are used to indicate which
309 specific processors support the instructions. The values are the 425 specific processors support the instructions. The values are the
310 same as those for the struct powerpc_opcode flags field. */ 426 same as those for the struct powerpc_opcode flags field. */
311 unsigned long flags; 427 ppc_cpu_t flags;
312 428
313 /* A format string to turn the macro into a normal instruction. 429 /* A format string to turn the macro into a normal instruction.
314 Each %N in the string is replaced with operand number N (zero 430 Each %N in the string is replaced with operand number N (zero
@@ -319,4 +435,18 @@ struct powerpc_macro
319extern const struct powerpc_macro powerpc_macros[]; 435extern const struct powerpc_macro powerpc_macros[];
320extern const int powerpc_num_macros; 436extern const int powerpc_num_macros;
321 437
438extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *);
439
440static inline long
441ppc_optional_operand_value (const struct powerpc_operand *operand)
442{
443 if ((operand->flags & PPC_OPERAND_OPTIONAL_VALUE) != 0)
444 return (operand+1)->shift;
445 return 0;
446}
447
448#ifdef __cplusplus
449}
450#endif
451
322#endif /* PPC_H */ 452#endif /* PPC_H */
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index 5720236d0266..26fa03fc9f3c 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -212,6 +212,10 @@ Commands:\n\
212 "\ 212 "\
213 C checksum\n\ 213 C checksum\n\
214 d dump bytes\n\ 214 d dump bytes\n\
215 d1 dump 1 byte values\n\
216 d2 dump 2 byte values\n\
217 d4 dump 4 byte values\n\
218 d8 dump 8 byte values\n\
215 di dump instructions\n\ 219 di dump instructions\n\
216 df dump float values\n\ 220 df dump float values\n\
217 dd dump double values\n\ 221 dd dump double values\n\
@@ -2334,9 +2338,42 @@ static void dump_pacas(void)
2334} 2338}
2335#endif 2339#endif
2336 2340
2341static void dump_by_size(unsigned long addr, long count, int size)
2342{
2343 unsigned char temp[16];
2344 int i, j;
2345 u64 val;
2346
2347 count = ALIGN(count, 16);
2348
2349 for (i = 0; i < count; i += 16, addr += 16) {
2350 printf(REG, addr);
2351
2352 if (mread(addr, temp, 16) != 16) {
2353 printf("\nFaulted reading %d bytes from 0x"REG"\n", 16, addr);
2354 return;
2355 }
2356
2357 for (j = 0; j < 16; j += size) {
2358 putchar(' ');
2359 switch (size) {
2360 case 1: val = temp[j]; break;
2361 case 2: val = *(u16 *)&temp[j]; break;
2362 case 4: val = *(u32 *)&temp[j]; break;
2363 case 8: val = *(u64 *)&temp[j]; break;
2364 default: val = 0;
2365 }
2366
2367 printf("%0*lx", size * 2, val);
2368 }
2369 printf("\n");
2370 }
2371}
2372
2337static void 2373static void
2338dump(void) 2374dump(void)
2339{ 2375{
2376 static char last[] = { "d?\n" };
2340 int c; 2377 int c;
2341 2378
2342 c = inchar(); 2379 c = inchar();
@@ -2350,8 +2387,9 @@ dump(void)
2350 } 2387 }
2351#endif 2388#endif
2352 2389
2353 if ((isxdigit(c) && c != 'f' && c != 'd') || c == '\n') 2390 if (c == '\n')
2354 termch = c; 2391 termch = c;
2392
2355 scanhex((void *)&adrs); 2393 scanhex((void *)&adrs);
2356 if (termch != '\n') 2394 if (termch != '\n')
2357 termch = 0; 2395 termch = 0;
@@ -2383,9 +2421,23 @@ dump(void)
2383 ndump = 64; 2421 ndump = 64;
2384 else if (ndump > MAX_DUMP) 2422 else if (ndump > MAX_DUMP)
2385 ndump = MAX_DUMP; 2423 ndump = MAX_DUMP;
2386 prdump(adrs, ndump); 2424
2425 switch (c) {
2426 case '8':
2427 case '4':
2428 case '2':
2429 case '1':
2430 ndump = ALIGN(ndump, 16);
2431 dump_by_size(adrs, ndump, c - '0');
2432 last[1] = c;
2433 last_cmd = last;
2434 break;
2435 default:
2436 prdump(adrs, ndump);
2437 last_cmd = "d\n";
2438 }
2439
2387 adrs += ndump; 2440 adrs += ndump;
2388 last_cmd = "d\n";
2389 } 2441 }
2390} 2442}
2391 2443
diff --git a/drivers/misc/cxl/cxl.h b/drivers/misc/cxl/cxl.h
index 6c722d96b775..79e60ec70bd3 100644
--- a/drivers/misc/cxl/cxl.h
+++ b/drivers/misc/cxl/cxl.h
@@ -418,8 +418,9 @@ struct cxl_afu {
418 struct dentry *debugfs; 418 struct dentry *debugfs;
419 struct mutex contexts_lock; 419 struct mutex contexts_lock;
420 spinlock_t afu_cntl_lock; 420 spinlock_t afu_cntl_lock;
421 /* Used to block access to AFU config space while deconfigured */ 421
422 struct rw_semaphore configured_rwsem; 422 /* -1: AFU deconfigured/locked, >= 0: number of readers */
423 atomic_t configured_state;
423 424
424 /* AFU error buffer fields and bin attribute for sysfs */ 425 /* AFU error buffer fields and bin attribute for sysfs */
425 u64 eb_len, eb_offset; 426 u64 eb_len, eb_offset;
diff --git a/drivers/misc/cxl/main.c b/drivers/misc/cxl/main.c
index 2a6bf1d0a3a4..cc1706a92ace 100644
--- a/drivers/misc/cxl/main.c
+++ b/drivers/misc/cxl/main.c
@@ -268,8 +268,7 @@ struct cxl_afu *cxl_alloc_afu(struct cxl *adapter, int slice)
268 idr_init(&afu->contexts_idr); 268 idr_init(&afu->contexts_idr);
269 mutex_init(&afu->contexts_lock); 269 mutex_init(&afu->contexts_lock);
270 spin_lock_init(&afu->afu_cntl_lock); 270 spin_lock_init(&afu->afu_cntl_lock);
271 init_rwsem(&afu->configured_rwsem); 271 atomic_set(&afu->configured_state, -1);
272 down_write(&afu->configured_rwsem);
273 afu->prefault_mode = CXL_PREFAULT_NONE; 272 afu->prefault_mode = CXL_PREFAULT_NONE;
274 afu->irqs_max = afu->adapter->user_irqs; 273 afu->irqs_max = afu->adapter->user_irqs;
275 274
diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
index cca938845ffd..91f645992c94 100644
--- a/drivers/misc/cxl/pci.c
+++ b/drivers/misc/cxl/pci.c
@@ -1129,7 +1129,7 @@ static int pci_configure_afu(struct cxl_afu *afu, struct cxl *adapter, struct pc
1129 if ((rc = cxl_native_register_psl_irq(afu))) 1129 if ((rc = cxl_native_register_psl_irq(afu)))
1130 goto err2; 1130 goto err2;
1131 1131
1132 up_write(&afu->configured_rwsem); 1132 atomic_set(&afu->configured_state, 0);
1133 return 0; 1133 return 0;
1134 1134
1135err2: 1135err2:
@@ -1142,7 +1142,14 @@ err1:
1142 1142
1143static void pci_deconfigure_afu(struct cxl_afu *afu) 1143static void pci_deconfigure_afu(struct cxl_afu *afu)
1144{ 1144{
1145 down_write(&afu->configured_rwsem); 1145 /*
1146 * It's okay to deconfigure when AFU is already locked, otherwise wait
1147 * until there are no readers
1148 */
1149 if (atomic_read(&afu->configured_state) != -1) {
1150 while (atomic_cmpxchg(&afu->configured_state, 0, -1) != -1)
1151 schedule();
1152 }
1146 cxl_native_release_psl_irq(afu); 1153 cxl_native_release_psl_irq(afu);
1147 if (afu->adapter->native->sl_ops->release_serr_irq) 1154 if (afu->adapter->native->sl_ops->release_serr_irq)
1148 afu->adapter->native->sl_ops->release_serr_irq(afu); 1155 afu->adapter->native->sl_ops->release_serr_irq(afu);
diff --git a/drivers/misc/cxl/vphb.c b/drivers/misc/cxl/vphb.c
index 639a343b7836..512a4897dbf6 100644
--- a/drivers/misc/cxl/vphb.c
+++ b/drivers/misc/cxl/vphb.c
@@ -83,6 +83,16 @@ static inline struct cxl_afu *pci_bus_to_afu(struct pci_bus *bus)
83 return phb ? phb->private_data : NULL; 83 return phb ? phb->private_data : NULL;
84} 84}
85 85
86static void cxl_afu_configured_put(struct cxl_afu *afu)
87{
88 atomic_dec_if_positive(&afu->configured_state);
89}
90
91static bool cxl_afu_configured_get(struct cxl_afu *afu)
92{
93 return atomic_inc_unless_negative(&afu->configured_state);
94}
95
86static inline int cxl_pcie_config_info(struct pci_bus *bus, unsigned int devfn, 96static inline int cxl_pcie_config_info(struct pci_bus *bus, unsigned int devfn,
87 struct cxl_afu *afu, int *_record) 97 struct cxl_afu *afu, int *_record)
88{ 98{
@@ -107,7 +117,7 @@ static int cxl_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
107 117
108 afu = pci_bus_to_afu(bus); 118 afu = pci_bus_to_afu(bus);
109 /* Grab a reader lock on afu. */ 119 /* Grab a reader lock on afu. */
110 if (afu == NULL || !down_read_trylock(&afu->configured_rwsem)) 120 if (afu == NULL || !cxl_afu_configured_get(afu))
111 return PCIBIOS_DEVICE_NOT_FOUND; 121 return PCIBIOS_DEVICE_NOT_FOUND;
112 122
113 rc = cxl_pcie_config_info(bus, devfn, afu, &record); 123 rc = cxl_pcie_config_info(bus, devfn, afu, &record);
@@ -132,7 +142,7 @@ static int cxl_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
132 } 142 }
133 143
134out: 144out:
135 up_read(&afu->configured_rwsem); 145 cxl_afu_configured_put(afu);
136 return rc ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; 146 return rc ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
137} 147}
138 148
@@ -144,7 +154,7 @@ static int cxl_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
144 154
145 afu = pci_bus_to_afu(bus); 155 afu = pci_bus_to_afu(bus);
146 /* Grab a reader lock on afu. */ 156 /* Grab a reader lock on afu. */
147 if (afu == NULL || !down_read_trylock(&afu->configured_rwsem)) 157 if (afu == NULL || !cxl_afu_configured_get(afu))
148 return PCIBIOS_DEVICE_NOT_FOUND; 158 return PCIBIOS_DEVICE_NOT_FOUND;
149 159
150 rc = cxl_pcie_config_info(bus, devfn, afu, &record); 160 rc = cxl_pcie_config_info(bus, devfn, afu, &record);
@@ -166,7 +176,7 @@ static int cxl_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
166 } 176 }
167 177
168out: 178out:
169 up_read(&afu->configured_rwsem); 179 cxl_afu_configured_put(afu);
170 return rc ? PCIBIOS_SET_FAILED : PCIBIOS_SUCCESSFUL; 180 return rc ? PCIBIOS_SET_FAILED : PCIBIOS_SUCCESSFUL;
171} 181}
172 182
diff --git a/drivers/pci/hotplug/pnv_php.c b/drivers/pci/hotplug/pnv_php.c
index d2961ef39a3a..7c203198b582 100644
--- a/drivers/pci/hotplug/pnv_php.c
+++ b/drivers/pci/hotplug/pnv_php.c
@@ -35,9 +35,11 @@ static void pnv_php_register(struct device_node *dn);
35static void pnv_php_unregister_one(struct device_node *dn); 35static void pnv_php_unregister_one(struct device_node *dn);
36static void pnv_php_unregister(struct device_node *dn); 36static void pnv_php_unregister(struct device_node *dn);
37 37
38static void pnv_php_disable_irq(struct pnv_php_slot *php_slot) 38static void pnv_php_disable_irq(struct pnv_php_slot *php_slot,
39 bool disable_device)
39{ 40{
40 struct pci_dev *pdev = php_slot->pdev; 41 struct pci_dev *pdev = php_slot->pdev;
42 int irq = php_slot->irq;
41 u16 ctrl; 43 u16 ctrl;
42 44
43 if (php_slot->irq > 0) { 45 if (php_slot->irq > 0) {
@@ -56,10 +58,14 @@ static void pnv_php_disable_irq(struct pnv_php_slot *php_slot)
56 php_slot->wq = NULL; 58 php_slot->wq = NULL;
57 } 59 }
58 60
59 if (pdev->msix_enabled) 61 if (disable_device || irq > 0) {
60 pci_disable_msix(pdev); 62 if (pdev->msix_enabled)
61 else if (pdev->msi_enabled) 63 pci_disable_msix(pdev);
62 pci_disable_msi(pdev); 64 else if (pdev->msi_enabled)
65 pci_disable_msi(pdev);
66
67 pci_disable_device(pdev);
68 }
63} 69}
64 70
65static void pnv_php_free_slot(struct kref *kref) 71static void pnv_php_free_slot(struct kref *kref)
@@ -68,7 +74,7 @@ static void pnv_php_free_slot(struct kref *kref)
68 struct pnv_php_slot, kref); 74 struct pnv_php_slot, kref);
69 75
70 WARN_ON(!list_empty(&php_slot->children)); 76 WARN_ON(!list_empty(&php_slot->children));
71 pnv_php_disable_irq(php_slot); 77 pnv_php_disable_irq(php_slot, false);
72 kfree(php_slot->name); 78 kfree(php_slot->name);
73 kfree(php_slot); 79 kfree(php_slot);
74} 80}
@@ -76,7 +82,7 @@ static void pnv_php_free_slot(struct kref *kref)
76static inline void pnv_php_put_slot(struct pnv_php_slot *php_slot) 82static inline void pnv_php_put_slot(struct pnv_php_slot *php_slot)
77{ 83{
78 84
79 if (WARN_ON(!php_slot)) 85 if (!php_slot)
80 return; 86 return;
81 87
82 kref_put(&php_slot->kref, pnv_php_free_slot); 88 kref_put(&php_slot->kref, pnv_php_free_slot);
@@ -430,9 +436,21 @@ static int pnv_php_enable(struct pnv_php_slot *php_slot, bool rescan)
430 if (ret) 436 if (ret)
431 return ret; 437 return ret;
432 438
433 /* Proceed if there have nothing behind the slot */ 439 /*
434 if (presence == OPAL_PCI_SLOT_EMPTY) 440 * Proceed if there have nothing behind the slot. However,
441 * we should leave the slot in registered state at the
442 * beginning. Otherwise, the PCI devices inserted afterwards
443 * won't be probed and populated.
444 */
445 if (presence == OPAL_PCI_SLOT_EMPTY) {
446 if (!php_slot->power_state_check) {
447 php_slot->power_state_check = true;
448
449 return 0;
450 }
451
435 goto scan; 452 goto scan;
453 }
436 454
437 /* 455 /*
438 * If the power supply to the slot is off, we can't detect 456 * If the power supply to the slot is off, we can't detect
@@ -705,10 +723,15 @@ static irqreturn_t pnv_php_interrupt(int irq, void *data)
705 if (sts & PCI_EXP_SLTSTA_DLLSC) { 723 if (sts & PCI_EXP_SLTSTA_DLLSC) {
706 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lsts); 724 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lsts);
707 added = !!(lsts & PCI_EXP_LNKSTA_DLLLA); 725 added = !!(lsts & PCI_EXP_LNKSTA_DLLLA);
708 } else if (sts & PCI_EXP_SLTSTA_PDC) { 726 } else if (!(php_slot->flags & PNV_PHP_FLAG_BROKEN_PDC) &&
727 (sts & PCI_EXP_SLTSTA_PDC)) {
709 ret = pnv_pci_get_presence_state(php_slot->id, &presence); 728 ret = pnv_pci_get_presence_state(php_slot->id, &presence);
710 if (!ret) 729 if (ret) {
730 dev_warn(&pdev->dev, "PCI slot [%s] error %d getting presence (0x%04x), to retry the operation.\n",
731 php_slot->name, ret, sts);
711 return IRQ_HANDLED; 732 return IRQ_HANDLED;
733 }
734
712 added = !!(presence == OPAL_PCI_SLOT_PRESENT); 735 added = !!(presence == OPAL_PCI_SLOT_PRESENT);
713 } else { 736 } else {
714 return IRQ_NONE; 737 return IRQ_NONE;
@@ -752,6 +775,7 @@ static irqreturn_t pnv_php_interrupt(int irq, void *data)
752static void pnv_php_init_irq(struct pnv_php_slot *php_slot, int irq) 775static void pnv_php_init_irq(struct pnv_php_slot *php_slot, int irq)
753{ 776{
754 struct pci_dev *pdev = php_slot->pdev; 777 struct pci_dev *pdev = php_slot->pdev;
778 u32 broken_pdc = 0;
755 u16 sts, ctrl; 779 u16 sts, ctrl;
756 int ret; 780 int ret;
757 781
@@ -759,29 +783,44 @@ static void pnv_php_init_irq(struct pnv_php_slot *php_slot, int irq)
759 php_slot->wq = alloc_workqueue("pciehp-%s", 0, 0, php_slot->name); 783 php_slot->wq = alloc_workqueue("pciehp-%s", 0, 0, php_slot->name);
760 if (!php_slot->wq) { 784 if (!php_slot->wq) {
761 dev_warn(&pdev->dev, "Cannot alloc workqueue\n"); 785 dev_warn(&pdev->dev, "Cannot alloc workqueue\n");
762 pnv_php_disable_irq(php_slot); 786 pnv_php_disable_irq(php_slot, true);
763 return; 787 return;
764 } 788 }
765 789
790 /* Check PDC (Presence Detection Change) is broken or not */
791 ret = of_property_read_u32(php_slot->dn, "ibm,slot-broken-pdc",
792 &broken_pdc);
793 if (!ret && broken_pdc)
794 php_slot->flags |= PNV_PHP_FLAG_BROKEN_PDC;
795
766 /* Clear pending interrupts */ 796 /* Clear pending interrupts */
767 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &sts); 797 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &sts);
768 sts |= (PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC); 798 if (php_slot->flags & PNV_PHP_FLAG_BROKEN_PDC)
799 sts |= PCI_EXP_SLTSTA_DLLSC;
800 else
801 sts |= (PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC);
769 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, sts); 802 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, sts);
770 803
771 /* Request the interrupt */ 804 /* Request the interrupt */
772 ret = request_irq(irq, pnv_php_interrupt, IRQF_SHARED, 805 ret = request_irq(irq, pnv_php_interrupt, IRQF_SHARED,
773 php_slot->name, php_slot); 806 php_slot->name, php_slot);
774 if (ret) { 807 if (ret) {
775 pnv_php_disable_irq(php_slot); 808 pnv_php_disable_irq(php_slot, true);
776 dev_warn(&pdev->dev, "Error %d enabling IRQ %d\n", ret, irq); 809 dev_warn(&pdev->dev, "Error %d enabling IRQ %d\n", ret, irq);
777 return; 810 return;
778 } 811 }
779 812
780 /* Enable the interrupts */ 813 /* Enable the interrupts */
781 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &ctrl); 814 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &ctrl);
782 ctrl |= (PCI_EXP_SLTCTL_HPIE | 815 if (php_slot->flags & PNV_PHP_FLAG_BROKEN_PDC) {
783 PCI_EXP_SLTCTL_PDCE | 816 ctrl &= ~PCI_EXP_SLTCTL_PDCE;
784 PCI_EXP_SLTCTL_DLLSCE); 817 ctrl |= (PCI_EXP_SLTCTL_HPIE |
818 PCI_EXP_SLTCTL_DLLSCE);
819 } else {
820 ctrl |= (PCI_EXP_SLTCTL_HPIE |
821 PCI_EXP_SLTCTL_PDCE |
822 PCI_EXP_SLTCTL_DLLSCE);
823 }
785 pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, ctrl); 824 pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, ctrl);
786 825
787 /* The interrupt is initialized successfully when @irq is valid */ 826 /* The interrupt is initialized successfully when @irq is valid */
@@ -793,6 +832,14 @@ static void pnv_php_enable_irq(struct pnv_php_slot *php_slot)
793 struct pci_dev *pdev = php_slot->pdev; 832 struct pci_dev *pdev = php_slot->pdev;
794 int irq, ret; 833 int irq, ret;
795 834
835 /*
836 * The MSI/MSIx interrupt might have been occupied by other
837 * drivers. Don't populate the surprise hotplug capability
838 * in that case.
839 */
840 if (pci_dev_msi_enabled(pdev))
841 return;
842
796 ret = pci_enable_device(pdev); 843 ret = pci_enable_device(pdev);
797 if (ret) { 844 if (ret) {
798 dev_warn(&pdev->dev, "Error %d enabling device\n", ret); 845 dev_warn(&pdev->dev, "Error %d enabling device\n", ret);
generated by cgit v1.2.2 (git 2.25.0) at 2025-06-01 10:07:40 -0400