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-rw-r--r--drivers/clk/meson/axg-audio.c964
1 files changed, 482 insertions, 482 deletions
diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c
index 7ab200b6c3bf..38fccffc171e 100644
--- a/drivers/clk/meson/axg-audio.c
+++ b/drivers/clk/meson/axg-audio.c
@@ -20,18 +20,18 @@
20#include "clk-phase.h" 20#include "clk-phase.h"
21#include "sclk-div.h" 21#include "sclk-div.h"
22 22
23#define AXG_MST_IN_COUNT 8 23#define AUD_MST_IN_COUNT 8
24#define AXG_SLV_SCLK_COUNT 10 24#define AUD_SLV_SCLK_COUNT 10
25#define AXG_SLV_LRCLK_COUNT 10 25#define AUD_SLV_LRCLK_COUNT 10
26 26
27#define AXG_AUD_GATE(_name, _reg, _bit, _pname, _iflags) \ 27#define AUD_GATE(_name, _reg, _bit, _pname, _iflags) \
28struct clk_regmap axg_##_name = { \ 28struct clk_regmap aud_##_name = { \
29 .data = &(struct clk_regmap_gate_data){ \ 29 .data = &(struct clk_regmap_gate_data){ \
30 .offset = (_reg), \ 30 .offset = (_reg), \
31 .bit_idx = (_bit), \ 31 .bit_idx = (_bit), \
32 }, \ 32 }, \
33 .hw.init = &(struct clk_init_data) { \ 33 .hw.init = &(struct clk_init_data) { \
34 .name = "axg_"#_name, \ 34 .name = "aud_"#_name, \
35 .ops = &clk_regmap_gate_ops, \ 35 .ops = &clk_regmap_gate_ops, \
36 .parent_names = (const char *[]){ _pname }, \ 36 .parent_names = (const char *[]){ _pname }, \
37 .num_parents = 1, \ 37 .num_parents = 1, \
@@ -39,8 +39,8 @@ struct clk_regmap axg_##_name = { \
39 }, \ 39 }, \
40} 40}
41 41
42#define AXG_AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pnames, _iflags) \ 42#define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pnames, _iflags) \
43struct clk_regmap axg_##_name = { \ 43struct clk_regmap aud_##_name = { \
44 .data = &(struct clk_regmap_mux_data){ \ 44 .data = &(struct clk_regmap_mux_data){ \
45 .offset = (_reg), \ 45 .offset = (_reg), \
46 .mask = (_mask), \ 46 .mask = (_mask), \
@@ -48,7 +48,7 @@ struct clk_regmap axg_##_name = { \
48 .flags = (_dflags), \ 48 .flags = (_dflags), \
49 }, \ 49 }, \
50 .hw.init = &(struct clk_init_data){ \ 50 .hw.init = &(struct clk_init_data){ \
51 .name = "axg_"#_name, \ 51 .name = "aud_"#_name, \
52 .ops = &clk_regmap_mux_ops, \ 52 .ops = &clk_regmap_mux_ops, \
53 .parent_names = (_pnames), \ 53 .parent_names = (_pnames), \
54 .num_parents = ARRAY_SIZE(_pnames), \ 54 .num_parents = ARRAY_SIZE(_pnames), \
@@ -56,8 +56,8 @@ struct clk_regmap axg_##_name = { \
56 }, \ 56 }, \
57} 57}
58 58
59#define AXG_AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) \ 59#define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) \
60struct clk_regmap axg_##_name = { \ 60struct clk_regmap aud_##_name = { \
61 .data = &(struct clk_regmap_div_data){ \ 61 .data = &(struct clk_regmap_div_data){ \
62 .offset = (_reg), \ 62 .offset = (_reg), \
63 .shift = (_shift), \ 63 .shift = (_shift), \
@@ -65,7 +65,7 @@ struct clk_regmap axg_##_name = { \
65 .flags = (_dflags), \ 65 .flags = (_dflags), \
66 }, \ 66 }, \
67 .hw.init = &(struct clk_init_data){ \ 67 .hw.init = &(struct clk_init_data){ \
68 .name = "axg_"#_name, \ 68 .name = "aud_"#_name, \
69 .ops = &clk_regmap_divider_ops, \ 69 .ops = &clk_regmap_divider_ops, \
70 .parent_names = (const char *[]) { _pname }, \ 70 .parent_names = (const char *[]) { _pname }, \
71 .num_parents = 1, \ 71 .num_parents = 1, \
@@ -73,109 +73,109 @@ struct clk_regmap axg_##_name = { \
73 }, \ 73 }, \
74} 74}
75 75
76#define AXG_PCLK_GATE(_name, _bit) \ 76#define AUD_PCLK_GATE(_name, _bit) \
77 AXG_AUD_GATE(_name, AUDIO_CLK_GATE_EN, _bit, "axg_audio_pclk", 0) 77 AUD_GATE(_name, AUDIO_CLK_GATE_EN, _bit, "audio_pclk", 0)
78 78
79/* Audio peripheral clocks */ 79/* Audio peripheral clocks */
80static AXG_PCLK_GATE(ddr_arb, 0); 80static AUD_PCLK_GATE(ddr_arb, 0);
81static AXG_PCLK_GATE(pdm, 1); 81static AUD_PCLK_GATE(pdm, 1);
82static AXG_PCLK_GATE(tdmin_a, 2); 82static AUD_PCLK_GATE(tdmin_a, 2);
83static AXG_PCLK_GATE(tdmin_b, 3); 83static AUD_PCLK_GATE(tdmin_b, 3);
84static AXG_PCLK_GATE(tdmin_c, 4); 84static AUD_PCLK_GATE(tdmin_c, 4);
85static AXG_PCLK_GATE(tdmin_lb, 5); 85static AUD_PCLK_GATE(tdmin_lb, 5);
86static AXG_PCLK_GATE(tdmout_a, 6); 86static AUD_PCLK_GATE(tdmout_a, 6);
87static AXG_PCLK_GATE(tdmout_b, 7); 87static AUD_PCLK_GATE(tdmout_b, 7);
88static AXG_PCLK_GATE(tdmout_c, 8); 88static AUD_PCLK_GATE(tdmout_c, 8);
89static AXG_PCLK_GATE(frddr_a, 9); 89static AUD_PCLK_GATE(frddr_a, 9);
90static AXG_PCLK_GATE(frddr_b, 10); 90static AUD_PCLK_GATE(frddr_b, 10);
91static AXG_PCLK_GATE(frddr_c, 11); 91static AUD_PCLK_GATE(frddr_c, 11);
92static AXG_PCLK_GATE(toddr_a, 12); 92static AUD_PCLK_GATE(toddr_a, 12);
93static AXG_PCLK_GATE(toddr_b, 13); 93static AUD_PCLK_GATE(toddr_b, 13);
94static AXG_PCLK_GATE(toddr_c, 14); 94static AUD_PCLK_GATE(toddr_c, 14);
95static AXG_PCLK_GATE(loopback, 15); 95static AUD_PCLK_GATE(loopback, 15);
96static AXG_PCLK_GATE(spdifin, 16); 96static AUD_PCLK_GATE(spdifin, 16);
97static AXG_PCLK_GATE(spdifout, 17); 97static AUD_PCLK_GATE(spdifout, 17);
98static AXG_PCLK_GATE(resample, 18); 98static AUD_PCLK_GATE(resample, 18);
99static AXG_PCLK_GATE(power_detect, 19); 99static AUD_PCLK_GATE(power_detect, 19);
100 100
101/* Audio Master Clocks */ 101/* Audio Master Clocks */
102static const char * const mst_mux_parent_names[] = { 102static const char * const mst_mux_parent_names[] = {
103 "axg_mst_in0", "axg_mst_in1", "axg_mst_in2", "axg_mst_in3", 103 "aud_mst_in0", "aud_mst_in1", "aud_mst_in2", "aud_mst_in3",
104 "axg_mst_in4", "axg_mst_in5", "axg_mst_in6", "axg_mst_in7", 104 "aud_mst_in4", "aud_mst_in5", "aud_mst_in6", "aud_mst_in7",
105}; 105};
106 106
107#define AXG_MST_MUX(_name, _reg, _flag) \ 107#define AUD_MST_MUX(_name, _reg, _flag) \
108 AXG_AUD_MUX(_name##_sel, _reg, 0x7, 24, _flag, \ 108 AUD_MUX(_name##_sel, _reg, 0x7, 24, _flag, \
109 mst_mux_parent_names, CLK_SET_RATE_PARENT) 109 mst_mux_parent_names, CLK_SET_RATE_PARENT)
110 110
111#define AXG_MST_MCLK_MUX(_name, _reg) \ 111#define AUD_MST_MCLK_MUX(_name, _reg) \
112 AXG_MST_MUX(_name, _reg, CLK_MUX_ROUND_CLOSEST) 112 AUD_MST_MUX(_name, _reg, CLK_MUX_ROUND_CLOSEST)
113 113
114#define AXG_MST_SYS_MUX(_name, _reg) \ 114#define AUD_MST_SYS_MUX(_name, _reg) \
115 AXG_MST_MUX(_name, _reg, 0) 115 AUD_MST_MUX(_name, _reg, 0)
116 116
117static AXG_MST_MCLK_MUX(mst_a_mclk, AUDIO_MCLK_A_CTRL); 117static AUD_MST_MCLK_MUX(mst_a_mclk, AUDIO_MCLK_A_CTRL);
118static AXG_MST_MCLK_MUX(mst_b_mclk, AUDIO_MCLK_B_CTRL); 118static AUD_MST_MCLK_MUX(mst_b_mclk, AUDIO_MCLK_B_CTRL);
119static AXG_MST_MCLK_MUX(mst_c_mclk, AUDIO_MCLK_C_CTRL); 119static AUD_MST_MCLK_MUX(mst_c_mclk, AUDIO_MCLK_C_CTRL);
120static AXG_MST_MCLK_MUX(mst_d_mclk, AUDIO_MCLK_D_CTRL); 120static AUD_MST_MCLK_MUX(mst_d_mclk, AUDIO_MCLK_D_CTRL);
121static AXG_MST_MCLK_MUX(mst_e_mclk, AUDIO_MCLK_E_CTRL); 121static AUD_MST_MCLK_MUX(mst_e_mclk, AUDIO_MCLK_E_CTRL);
122static AXG_MST_MCLK_MUX(mst_f_mclk, AUDIO_MCLK_F_CTRL); 122static AUD_MST_MCLK_MUX(mst_f_mclk, AUDIO_MCLK_F_CTRL);
123static AXG_MST_MCLK_MUX(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL); 123static AUD_MST_MCLK_MUX(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
124static AXG_MST_MCLK_MUX(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0); 124static AUD_MST_MCLK_MUX(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
125static AXG_MST_SYS_MUX(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL); 125static AUD_MST_SYS_MUX(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
126static AXG_MST_SYS_MUX(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1); 126static AUD_MST_SYS_MUX(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
127 127
128#define AXG_MST_DIV(_name, _reg, _flag) \ 128#define AUD_MST_DIV(_name, _reg, _flag) \
129 AXG_AUD_DIV(_name##_div, _reg, 0, 16, _flag, \ 129 AUD_DIV(_name##_div, _reg, 0, 16, _flag, \
130 "axg_"#_name"_sel", CLK_SET_RATE_PARENT) \ 130 "aud_"#_name"_sel", CLK_SET_RATE_PARENT) \
131 131
132#define AXG_MST_MCLK_DIV(_name, _reg) \ 132#define AUD_MST_MCLK_DIV(_name, _reg) \
133 AXG_MST_DIV(_name, _reg, CLK_DIVIDER_ROUND_CLOSEST) 133 AUD_MST_DIV(_name, _reg, CLK_DIVIDER_ROUND_CLOSEST)
134 134
135#define AXG_MST_SYS_DIV(_name, _reg) \ 135#define AUD_MST_SYS_DIV(_name, _reg) \
136 AXG_MST_DIV(_name, _reg, 0) 136 AUD_MST_DIV(_name, _reg, 0)
137 137
138static AXG_MST_MCLK_DIV(mst_a_mclk, AUDIO_MCLK_A_CTRL); 138static AUD_MST_MCLK_DIV(mst_a_mclk, AUDIO_MCLK_A_CTRL);
139static AXG_MST_MCLK_DIV(mst_b_mclk, AUDIO_MCLK_B_CTRL); 139static AUD_MST_MCLK_DIV(mst_b_mclk, AUDIO_MCLK_B_CTRL);
140static AXG_MST_MCLK_DIV(mst_c_mclk, AUDIO_MCLK_C_CTRL); 140static AUD_MST_MCLK_DIV(mst_c_mclk, AUDIO_MCLK_C_CTRL);
141static AXG_MST_MCLK_DIV(mst_d_mclk, AUDIO_MCLK_D_CTRL); 141static AUD_MST_MCLK_DIV(mst_d_mclk, AUDIO_MCLK_D_CTRL);
142static AXG_MST_MCLK_DIV(mst_e_mclk, AUDIO_MCLK_E_CTRL); 142static AUD_MST_MCLK_DIV(mst_e_mclk, AUDIO_MCLK_E_CTRL);
143static AXG_MST_MCLK_DIV(mst_f_mclk, AUDIO_MCLK_F_CTRL); 143static AUD_MST_MCLK_DIV(mst_f_mclk, AUDIO_MCLK_F_CTRL);
144static AXG_MST_MCLK_DIV(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL); 144static AUD_MST_MCLK_DIV(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
145static AXG_MST_MCLK_DIV(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0); 145static AUD_MST_MCLK_DIV(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
146static AXG_MST_SYS_DIV(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL); 146static AUD_MST_SYS_DIV(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
147static AXG_MST_SYS_DIV(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1); 147static AUD_MST_SYS_DIV(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
148 148
149#define AXG_MST_MCLK_GATE(_name, _reg) \ 149#define AUD_MST_MCLK_GATE(_name, _reg) \
150 AXG_AUD_GATE(_name, _reg, 31, "axg_"#_name"_div", \ 150 AUD_GATE(_name, _reg, 31, "aud_"#_name"_div", \
151 CLK_SET_RATE_PARENT) 151 CLK_SET_RATE_PARENT)
152 152
153static AXG_MST_MCLK_GATE(mst_a_mclk, AUDIO_MCLK_A_CTRL); 153static AUD_MST_MCLK_GATE(mst_a_mclk, AUDIO_MCLK_A_CTRL);
154static AXG_MST_MCLK_GATE(mst_b_mclk, AUDIO_MCLK_B_CTRL); 154static AUD_MST_MCLK_GATE(mst_b_mclk, AUDIO_MCLK_B_CTRL);
155static AXG_MST_MCLK_GATE(mst_c_mclk, AUDIO_MCLK_C_CTRL); 155static AUD_MST_MCLK_GATE(mst_c_mclk, AUDIO_MCLK_C_CTRL);
156static AXG_MST_MCLK_GATE(mst_d_mclk, AUDIO_MCLK_D_CTRL); 156static AUD_MST_MCLK_GATE(mst_d_mclk, AUDIO_MCLK_D_CTRL);
157static AXG_MST_MCLK_GATE(mst_e_mclk, AUDIO_MCLK_E_CTRL); 157static AUD_MST_MCLK_GATE(mst_e_mclk, AUDIO_MCLK_E_CTRL);
158static AXG_MST_MCLK_GATE(mst_f_mclk, AUDIO_MCLK_F_CTRL); 158static AUD_MST_MCLK_GATE(mst_f_mclk, AUDIO_MCLK_F_CTRL);
159static AXG_MST_MCLK_GATE(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL); 159static AUD_MST_MCLK_GATE(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
160static AXG_MST_MCLK_GATE(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL); 160static AUD_MST_MCLK_GATE(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
161static AXG_MST_MCLK_GATE(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0); 161static AUD_MST_MCLK_GATE(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
162static AXG_MST_MCLK_GATE(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1); 162static AUD_MST_MCLK_GATE(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
163 163
164/* Sample Clocks */ 164/* Sample Clocks */
165#define AXG_MST_SCLK_PRE_EN(_name, _reg) \ 165#define AUD_MST_SCLK_PRE_EN(_name, _reg) \
166 AXG_AUD_GATE(mst_##_name##_sclk_pre_en, _reg, 31, \ 166 AUD_GATE(mst_##_name##_sclk_pre_en, _reg, 31, \
167 "axg_mst_"#_name"_mclk", 0) 167 "aud_mst_"#_name"_mclk", 0)
168 168
169static AXG_MST_SCLK_PRE_EN(a, AUDIO_MST_A_SCLK_CTRL0); 169static AUD_MST_SCLK_PRE_EN(a, AUDIO_MST_A_SCLK_CTRL0);
170static AXG_MST_SCLK_PRE_EN(b, AUDIO_MST_B_SCLK_CTRL0); 170static AUD_MST_SCLK_PRE_EN(b, AUDIO_MST_B_SCLK_CTRL0);
171static AXG_MST_SCLK_PRE_EN(c, AUDIO_MST_C_SCLK_CTRL0); 171static AUD_MST_SCLK_PRE_EN(c, AUDIO_MST_C_SCLK_CTRL0);
172static AXG_MST_SCLK_PRE_EN(d, AUDIO_MST_D_SCLK_CTRL0); 172static AUD_MST_SCLK_PRE_EN(d, AUDIO_MST_D_SCLK_CTRL0);
173static AXG_MST_SCLK_PRE_EN(e, AUDIO_MST_E_SCLK_CTRL0); 173static AUD_MST_SCLK_PRE_EN(e, AUDIO_MST_E_SCLK_CTRL0);
174static AXG_MST_SCLK_PRE_EN(f, AUDIO_MST_F_SCLK_CTRL0); 174static AUD_MST_SCLK_PRE_EN(f, AUDIO_MST_F_SCLK_CTRL0);
175 175
176#define AXG_AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width, \ 176#define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width, \
177 _hi_shift, _hi_width, _pname, _iflags) \ 177 _hi_shift, _hi_width, _pname, _iflags) \
178struct clk_regmap axg_##_name = { \ 178struct clk_regmap aud_##_name = { \
179 .data = &(struct meson_sclk_div_data) { \ 179 .data = &(struct meson_sclk_div_data) { \
180 .div = { \ 180 .div = { \
181 .reg_off = (_reg), \ 181 .reg_off = (_reg), \
@@ -189,7 +189,7 @@ struct clk_regmap axg_##_name = { \
189 }, \ 189 }, \
190 }, \ 190 }, \
191 .hw.init = &(struct clk_init_data) { \ 191 .hw.init = &(struct clk_init_data) { \
192 .name = "axg_"#_name, \ 192 .name = "aud_"#_name, \
193 .ops = &meson_sclk_div_ops, \ 193 .ops = &meson_sclk_div_ops, \
194 .parent_names = (const char *[]) { _pname }, \ 194 .parent_names = (const char *[]) { _pname }, \
195 .num_parents = 1, \ 195 .num_parents = 1, \
@@ -197,32 +197,32 @@ struct clk_regmap axg_##_name = { \
197 }, \ 197 }, \
198} 198}
199 199
200#define AXG_MST_SCLK_DIV(_name, _reg) \ 200#define AUD_MST_SCLK_DIV(_name, _reg) \
201 AXG_AUD_SCLK_DIV(mst_##_name##_sclk_div, _reg, 20, 10, 0, 0, \ 201 AUD_SCLK_DIV(mst_##_name##_sclk_div, _reg, 20, 10, 0, 0, \
202 "axg_mst_"#_name"_sclk_pre_en", \ 202 "aud_mst_"#_name"_sclk_pre_en", \
203 CLK_SET_RATE_PARENT) 203 CLK_SET_RATE_PARENT)
204 204
205static AXG_MST_SCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0); 205static AUD_MST_SCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
206static AXG_MST_SCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0); 206static AUD_MST_SCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
207static AXG_MST_SCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0); 207static AUD_MST_SCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);
208static AXG_MST_SCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0); 208static AUD_MST_SCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);
209static AXG_MST_SCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0); 209static AUD_MST_SCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
210static AXG_MST_SCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0); 210static AUD_MST_SCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
211 211
212#define AXG_MST_SCLK_POST_EN(_name, _reg) \ 212#define AUD_MST_SCLK_POST_EN(_name, _reg) \
213 AXG_AUD_GATE(mst_##_name##_sclk_post_en, _reg, 30, \ 213 AUD_GATE(mst_##_name##_sclk_post_en, _reg, 30, \
214 "axg_mst_"#_name"_sclk_div", CLK_SET_RATE_PARENT) 214 "aud_mst_"#_name"_sclk_div", CLK_SET_RATE_PARENT)
215 215
216static AXG_MST_SCLK_POST_EN(a, AUDIO_MST_A_SCLK_CTRL0); 216static AUD_MST_SCLK_POST_EN(a, AUDIO_MST_A_SCLK_CTRL0);
217static AXG_MST_SCLK_POST_EN(b, AUDIO_MST_B_SCLK_CTRL0); 217static AUD_MST_SCLK_POST_EN(b, AUDIO_MST_B_SCLK_CTRL0);
218static AXG_MST_SCLK_POST_EN(c, AUDIO_MST_C_SCLK_CTRL0); 218static AUD_MST_SCLK_POST_EN(c, AUDIO_MST_C_SCLK_CTRL0);
219static AXG_MST_SCLK_POST_EN(d, AUDIO_MST_D_SCLK_CTRL0); 219static AUD_MST_SCLK_POST_EN(d, AUDIO_MST_D_SCLK_CTRL0);
220static AXG_MST_SCLK_POST_EN(e, AUDIO_MST_E_SCLK_CTRL0); 220static AUD_MST_SCLK_POST_EN(e, AUDIO_MST_E_SCLK_CTRL0);
221static AXG_MST_SCLK_POST_EN(f, AUDIO_MST_F_SCLK_CTRL0); 221static AUD_MST_SCLK_POST_EN(f, AUDIO_MST_F_SCLK_CTRL0);
222 222
223#define AXG_AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \ 223#define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \
224 _pname, _iflags) \ 224 _pname, _iflags) \
225struct clk_regmap axg_##_name = { \ 225struct clk_regmap aud_##_name = { \
226 .data = &(struct meson_clk_triphase_data) { \ 226 .data = &(struct meson_clk_triphase_data) { \
227 .ph0 = { \ 227 .ph0 = { \
228 .reg_off = (_reg), \ 228 .reg_off = (_reg), \
@@ -241,7 +241,7 @@ struct clk_regmap axg_##_name = { \
241 }, \ 241 }, \
242 }, \ 242 }, \
243 .hw.init = &(struct clk_init_data) { \ 243 .hw.init = &(struct clk_init_data) { \
244 .name = "axg_"#_name, \ 244 .name = "aud_"#_name, \
245 .ops = &meson_clk_triphase_ops, \ 245 .ops = &meson_clk_triphase_ops, \
246 .parent_names = (const char *[]) { _pname }, \ 246 .parent_names = (const char *[]) { _pname }, \
247 .num_parents = 1, \ 247 .num_parents = 1, \
@@ -249,87 +249,87 @@ struct clk_regmap axg_##_name = { \
249 }, \ 249 }, \
250} 250}
251 251
252#define AXG_MST_SCLK(_name, _reg) \ 252#define AUD_MST_SCLK(_name, _reg) \
253 AXG_AUD_TRIPHASE(mst_##_name##_sclk, _reg, 1, 0, 2, 4, \ 253 AUD_TRIPHASE(mst_##_name##_sclk, _reg, 1, 0, 2, 4, \
254 "axg_mst_"#_name"_sclk_post_en", CLK_SET_RATE_PARENT) 254 "aud_mst_"#_name"_sclk_post_en", CLK_SET_RATE_PARENT)
255 255
256static AXG_MST_SCLK(a, AUDIO_MST_A_SCLK_CTRL1); 256static AUD_MST_SCLK(a, AUDIO_MST_A_SCLK_CTRL1);
257static AXG_MST_SCLK(b, AUDIO_MST_B_SCLK_CTRL1); 257static AUD_MST_SCLK(b, AUDIO_MST_B_SCLK_CTRL1);
258static AXG_MST_SCLK(c, AUDIO_MST_C_SCLK_CTRL1); 258static AUD_MST_SCLK(c, AUDIO_MST_C_SCLK_CTRL1);
259static AXG_MST_SCLK(d, AUDIO_MST_D_SCLK_CTRL1); 259static AUD_MST_SCLK(d, AUDIO_MST_D_SCLK_CTRL1);
260static AXG_MST_SCLK(e, AUDIO_MST_E_SCLK_CTRL1); 260static AUD_MST_SCLK(e, AUDIO_MST_E_SCLK_CTRL1);
261static AXG_MST_SCLK(f, AUDIO_MST_F_SCLK_CTRL1); 261static AUD_MST_SCLK(f, AUDIO_MST_F_SCLK_CTRL1);
262 262
263#define AXG_MST_LRCLK_DIV(_name, _reg) \ 263#define AUD_MST_LRCLK_DIV(_name, _reg) \
264 AXG_AUD_SCLK_DIV(mst_##_name##_lrclk_div, _reg, 0, 10, 10, 10, \ 264 AUD_SCLK_DIV(mst_##_name##_lrclk_div, _reg, 0, 10, 10, 10, \
265 "axg_mst_"#_name"_sclk_post_en", 0) \ 265 "aud_mst_"#_name"_sclk_post_en", 0) \
266 266
267static AXG_MST_LRCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0); 267static AUD_MST_LRCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
268static AXG_MST_LRCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0); 268static AUD_MST_LRCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
269static AXG_MST_LRCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0); 269static AUD_MST_LRCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);
270static AXG_MST_LRCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0); 270static AUD_MST_LRCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);
271static AXG_MST_LRCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0); 271static AUD_MST_LRCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
272static AXG_MST_LRCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0); 272static AUD_MST_LRCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
273 273
274#define AXG_MST_LRCLK(_name, _reg) \ 274#define AUD_MST_LRCLK(_name, _reg) \
275 AXG_AUD_TRIPHASE(mst_##_name##_lrclk, _reg, 1, 1, 3, 5, \ 275 AUD_TRIPHASE(mst_##_name##_lrclk, _reg, 1, 1, 3, 5, \
276 "axg_mst_"#_name"_lrclk_div", CLK_SET_RATE_PARENT) 276 "aud_mst_"#_name"_lrclk_div", CLK_SET_RATE_PARENT)
277 277
278static AXG_MST_LRCLK(a, AUDIO_MST_A_SCLK_CTRL1); 278static AUD_MST_LRCLK(a, AUDIO_MST_A_SCLK_CTRL1);
279static AXG_MST_LRCLK(b, AUDIO_MST_B_SCLK_CTRL1); 279static AUD_MST_LRCLK(b, AUDIO_MST_B_SCLK_CTRL1);
280static AXG_MST_LRCLK(c, AUDIO_MST_C_SCLK_CTRL1); 280static AUD_MST_LRCLK(c, AUDIO_MST_C_SCLK_CTRL1);
281static AXG_MST_LRCLK(d, AUDIO_MST_D_SCLK_CTRL1); 281static AUD_MST_LRCLK(d, AUDIO_MST_D_SCLK_CTRL1);
282static AXG_MST_LRCLK(e, AUDIO_MST_E_SCLK_CTRL1); 282static AUD_MST_LRCLK(e, AUDIO_MST_E_SCLK_CTRL1);
283static AXG_MST_LRCLK(f, AUDIO_MST_F_SCLK_CTRL1); 283static AUD_MST_LRCLK(f, AUDIO_MST_F_SCLK_CTRL1);
284 284
285static const char * const tdm_sclk_parent_names[] = { 285static const char * const tdm_sclk_parent_names[] = {
286 "axg_mst_a_sclk", "axg_mst_b_sclk", "axg_mst_c_sclk", 286 "aud_mst_a_sclk", "aud_mst_b_sclk", "aud_mst_c_sclk",
287 "axg_mst_d_sclk", "axg_mst_e_sclk", "axg_mst_f_sclk", 287 "aud_mst_d_sclk", "aud_mst_e_sclk", "aud_mst_f_sclk",
288 "axg_slv_sclk0", "axg_slv_sclk1", "axg_slv_sclk2", 288 "aud_slv_sclk0", "aud_slv_sclk1", "aud_slv_sclk2",
289 "axg_slv_sclk3", "axg_slv_sclk4", "axg_slv_sclk5", 289 "aud_slv_sclk3", "aud_slv_sclk4", "aud_slv_sclk5",
290 "axg_slv_sclk6", "axg_slv_sclk7", "axg_slv_sclk8", 290 "aud_slv_sclk6", "aud_slv_sclk7", "aud_slv_sclk8",
291 "axg_slv_sclk9" 291 "aud_slv_sclk9"
292}; 292};
293 293
294#define AXG_TDM_SCLK_MUX(_name, _reg) \ 294#define AUD_TDM_SCLK_MUX(_name, _reg) \
295 AXG_AUD_MUX(tdm##_name##_sclk_sel, _reg, 0xf, 24, \ 295 AUD_MUX(tdm##_name##_sclk_sel, _reg, 0xf, 24, \
296 CLK_MUX_ROUND_CLOSEST, \ 296 CLK_MUX_ROUND_CLOSEST, \
297 tdm_sclk_parent_names, 0) 297 tdm_sclk_parent_names, 0)
298 298
299static AXG_TDM_SCLK_MUX(in_a, AUDIO_CLK_TDMIN_A_CTRL); 299static AUD_TDM_SCLK_MUX(in_a, AUDIO_CLK_TDMIN_A_CTRL);
300static AXG_TDM_SCLK_MUX(in_b, AUDIO_CLK_TDMIN_B_CTRL); 300static AUD_TDM_SCLK_MUX(in_b, AUDIO_CLK_TDMIN_B_CTRL);
301static AXG_TDM_SCLK_MUX(in_c, AUDIO_CLK_TDMIN_C_CTRL); 301static AUD_TDM_SCLK_MUX(in_c, AUDIO_CLK_TDMIN_C_CTRL);
302static AXG_TDM_SCLK_MUX(in_lb, AUDIO_CLK_TDMIN_LB_CTRL); 302static AUD_TDM_SCLK_MUX(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
303static AXG_TDM_SCLK_MUX(out_a, AUDIO_CLK_TDMOUT_A_CTRL); 303static AUD_TDM_SCLK_MUX(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
304static AXG_TDM_SCLK_MUX(out_b, AUDIO_CLK_TDMOUT_B_CTRL); 304static AUD_TDM_SCLK_MUX(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
305static AXG_TDM_SCLK_MUX(out_c, AUDIO_CLK_TDMOUT_C_CTRL); 305static AUD_TDM_SCLK_MUX(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
306 306
307#define AXG_TDM_SCLK_PRE_EN(_name, _reg) \ 307#define AUD_TDM_SCLK_PRE_EN(_name, _reg) \
308 AXG_AUD_GATE(tdm##_name##_sclk_pre_en, _reg, 31, \ 308 AUD_GATE(tdm##_name##_sclk_pre_en, _reg, 31, \
309 "axg_tdm"#_name"_sclk_sel", CLK_SET_RATE_PARENT) 309 "aud_tdm"#_name"_sclk_sel", CLK_SET_RATE_PARENT)
310 310
311static AXG_TDM_SCLK_PRE_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL); 311static AUD_TDM_SCLK_PRE_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL);
312static AXG_TDM_SCLK_PRE_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL); 312static AUD_TDM_SCLK_PRE_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL);
313static AXG_TDM_SCLK_PRE_EN(in_c, AUDIO_CLK_TDMIN_C_CTRL); 313static AUD_TDM_SCLK_PRE_EN(in_c, AUDIO_CLK_TDMIN_C_CTRL);
314static AXG_TDM_SCLK_PRE_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL); 314static AUD_TDM_SCLK_PRE_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
315static AXG_TDM_SCLK_PRE_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL); 315static AUD_TDM_SCLK_PRE_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
316static AXG_TDM_SCLK_PRE_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL); 316static AUD_TDM_SCLK_PRE_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
317static AXG_TDM_SCLK_PRE_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL); 317static AUD_TDM_SCLK_PRE_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
318 318
319#define AXG_TDM_SCLK_POST_EN(_name, _reg) \ 319#define AUD_TDM_SCLK_POST_EN(_name, _reg) \
320 AXG_AUD_GATE(tdm##_name##_sclk_post_en, _reg, 30, \ 320 AUD_GATE(tdm##_name##_sclk_post_en, _reg, 30, \
321 "axg_tdm"#_name"_sclk_pre_en", CLK_SET_RATE_PARENT) 321 "aud_tdm"#_name"_sclk_pre_en", CLK_SET_RATE_PARENT)
322 322
323static AXG_TDM_SCLK_POST_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL); 323static AUD_TDM_SCLK_POST_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL);
324static AXG_TDM_SCLK_POST_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL); 324static AUD_TDM_SCLK_POST_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL);
325static AXG_TDM_SCLK_POST_EN(in_c, AUDIO_CLK_TDMIN_C_CTRL); 325static AUD_TDM_SCLK_POST_EN(in_c, AUDIO_CLK_TDMIN_C_CTRL);
326static AXG_TDM_SCLK_POST_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL); 326static AUD_TDM_SCLK_POST_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
327static AXG_TDM_SCLK_POST_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL); 327static AUD_TDM_SCLK_POST_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
328static AXG_TDM_SCLK_POST_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL); 328static AUD_TDM_SCLK_POST_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
329static AXG_TDM_SCLK_POST_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL); 329static AUD_TDM_SCLK_POST_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
330 330
331#define AXG_TDM_SCLK(_name, _reg) \ 331#define AUD_TDM_SCLK(_name, _reg) \
332 struct clk_regmap axg_tdm##_name##_sclk = { \ 332 struct clk_regmap aud_tdm##_name##_sclk = { \
333 .data = &(struct meson_clk_phase_data) { \ 333 .data = &(struct meson_clk_phase_data) { \
334 .ph = { \ 334 .ph = { \
335 .reg_off = (_reg), \ 335 .reg_off = (_reg), \
@@ -338,44 +338,44 @@ static AXG_TDM_SCLK_POST_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
338 }, \ 338 }, \
339 }, \ 339 }, \
340 .hw.init = &(struct clk_init_data) { \ 340 .hw.init = &(struct clk_init_data) { \
341 .name = "axg_tdm"#_name"_sclk", \ 341 .name = "aud_tdm"#_name"_sclk", \
342 .ops = &meson_clk_phase_ops, \ 342 .ops = &meson_clk_phase_ops, \
343 .parent_names = (const char *[]) \ 343 .parent_names = (const char *[]) \
344 { "axg_tdm"#_name"_sclk_post_en" }, \ 344 { "aud_tdm"#_name"_sclk_post_en" }, \
345 .num_parents = 1, \ 345 .num_parents = 1, \
346 .flags = CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT, \ 346 .flags = CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT, \
347 }, \ 347 }, \
348} 348}
349 349
350static AXG_TDM_SCLK(in_a, AUDIO_CLK_TDMIN_A_CTRL); 350static AUD_TDM_SCLK(in_a, AUDIO_CLK_TDMIN_A_CTRL);
351static AXG_TDM_SCLK(in_b, AUDIO_CLK_TDMIN_B_CTRL); 351static AUD_TDM_SCLK(in_b, AUDIO_CLK_TDMIN_B_CTRL);
352static AXG_TDM_SCLK(in_c, AUDIO_CLK_TDMIN_C_CTRL); 352static AUD_TDM_SCLK(in_c, AUDIO_CLK_TDMIN_C_CTRL);
353static AXG_TDM_SCLK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL); 353static AUD_TDM_SCLK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
354static AXG_TDM_SCLK(out_a, AUDIO_CLK_TDMOUT_A_CTRL); 354static AUD_TDM_SCLK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
355static AXG_TDM_SCLK(out_b, AUDIO_CLK_TDMOUT_B_CTRL); 355static AUD_TDM_SCLK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
356static AXG_TDM_SCLK(out_c, AUDIO_CLK_TDMOUT_C_CTRL); 356static AUD_TDM_SCLK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
357 357
358static const char * const tdm_lrclk_parent_names[] = { 358static const char * const tdm_lrclk_parent_names[] = {
359 "axg_mst_a_lrclk", "axg_mst_b_lrclk", "axg_mst_c_lrclk", 359 "aud_mst_a_lrclk", "aud_mst_b_lrclk", "aud_mst_c_lrclk",
360 "axg_mst_d_lrclk", "axg_mst_e_lrclk", "axg_mst_f_lrclk", 360 "aud_mst_d_lrclk", "aud_mst_e_lrclk", "aud_mst_f_lrclk",
361 "axg_slv_lrclk0", "axg_slv_lrclk1", "axg_slv_lrclk2", 361 "aud_slv_lrclk0", "aud_slv_lrclk1", "aud_slv_lrclk2",
362 "axg_slv_lrclk3", "axg_slv_lrclk4", "axg_slv_lrclk5", 362 "aud_slv_lrclk3", "aud_slv_lrclk4", "aud_slv_lrclk5",
363 "axg_slv_lrclk6", "axg_slv_lrclk7", "axg_slv_lrclk8", 363 "aud_slv_lrclk6", "aud_slv_lrclk7", "aud_slv_lrclk8",
364 "axg_slv_lrclk9" 364 "aud_slv_lrclk9"
365}; 365};
366 366
367#define AXG_TDM_LRLCK(_name, _reg) \ 367#define AUD_TDM_LRLCK(_name, _reg) \
368 AXG_AUD_MUX(tdm##_name##_lrclk, _reg, 0xf, 20, \ 368 AUD_MUX(tdm##_name##_lrclk, _reg, 0xf, 20, \
369 CLK_MUX_ROUND_CLOSEST, \ 369 CLK_MUX_ROUND_CLOSEST, \
370 tdm_lrclk_parent_names, 0) 370 tdm_lrclk_parent_names, 0)
371 371
372static AXG_TDM_LRLCK(in_a, AUDIO_CLK_TDMIN_A_CTRL); 372static AUD_TDM_LRLCK(in_a, AUDIO_CLK_TDMIN_A_CTRL);
373static AXG_TDM_LRLCK(in_b, AUDIO_CLK_TDMIN_B_CTRL); 373static AUD_TDM_LRLCK(in_b, AUDIO_CLK_TDMIN_B_CTRL);
374static AXG_TDM_LRLCK(in_c, AUDIO_CLK_TDMIN_C_CTRL); 374static AUD_TDM_LRLCK(in_c, AUDIO_CLK_TDMIN_C_CTRL);
375static AXG_TDM_LRLCK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL); 375static AUD_TDM_LRLCK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
376static AXG_TDM_LRLCK(out_a, AUDIO_CLK_TDMOUT_A_CTRL); 376static AUD_TDM_LRLCK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
377static AXG_TDM_LRLCK(out_b, AUDIO_CLK_TDMOUT_B_CTRL); 377static AUD_TDM_LRLCK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
378static AXG_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL); 378static AUD_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
379 379
380/* 380/*
381 * Array of all clocks provided by this provider 381 * Array of all clocks provided by this provider
@@ -383,255 +383,255 @@ static AXG_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
383 */ 383 */
384static struct clk_hw_onecell_data axg_audio_hw_onecell_data = { 384static struct clk_hw_onecell_data axg_audio_hw_onecell_data = {
385 .hws = { 385 .hws = {
386 [AUD_CLKID_DDR_ARB] = &axg_ddr_arb.hw, 386 [AUD_CLKID_DDR_ARB] = &aud_ddr_arb.hw,
387 [AUD_CLKID_PDM] = &axg_pdm.hw, 387 [AUD_CLKID_PDM] = &aud_pdm.hw,
388 [AUD_CLKID_TDMIN_A] = &axg_tdmin_a.hw, 388 [AUD_CLKID_TDMIN_A] = &aud_tdmin_a.hw,
389 [AUD_CLKID_TDMIN_B] = &axg_tdmin_b.hw, 389 [AUD_CLKID_TDMIN_B] = &aud_tdmin_b.hw,
390 [AUD_CLKID_TDMIN_C] = &axg_tdmin_c.hw, 390 [AUD_CLKID_TDMIN_C] = &aud_tdmin_c.hw,
391 [AUD_CLKID_TDMIN_LB] = &axg_tdmin_lb.hw, 391 [AUD_CLKID_TDMIN_LB] = &aud_tdmin_lb.hw,
392 [AUD_CLKID_TDMOUT_A] = &axg_tdmout_a.hw, 392 [AUD_CLKID_TDMOUT_A] = &aud_tdmout_a.hw,
393 [AUD_CLKID_TDMOUT_B] = &axg_tdmout_b.hw, 393 [AUD_CLKID_TDMOUT_B] = &aud_tdmout_b.hw,
394 [AUD_CLKID_TDMOUT_C] = &axg_tdmout_c.hw, 394 [AUD_CLKID_TDMOUT_C] = &aud_tdmout_c.hw,
395 [AUD_CLKID_FRDDR_A] = &axg_frddr_a.hw, 395 [AUD_CLKID_FRDDR_A] = &aud_frddr_a.hw,
396 [AUD_CLKID_FRDDR_B] = &axg_frddr_b.hw, 396 [AUD_CLKID_FRDDR_B] = &aud_frddr_b.hw,
397 [AUD_CLKID_FRDDR_C] = &axg_frddr_c.hw, 397 [AUD_CLKID_FRDDR_C] = &aud_frddr_c.hw,
398 [AUD_CLKID_TODDR_A] = &axg_toddr_a.hw, 398 [AUD_CLKID_TODDR_A] = &aud_toddr_a.hw,
399 [AUD_CLKID_TODDR_B] = &axg_toddr_b.hw, 399 [AUD_CLKID_TODDR_B] = &aud_toddr_b.hw,
400 [AUD_CLKID_TODDR_C] = &axg_toddr_c.hw, 400 [AUD_CLKID_TODDR_C] = &aud_toddr_c.hw,
401 [AUD_CLKID_LOOPBACK] = &axg_loopback.hw, 401 [AUD_CLKID_LOOPBACK] = &aud_loopback.hw,
402 [AUD_CLKID_SPDIFIN] = &axg_spdifin.hw, 402 [AUD_CLKID_SPDIFIN] = &aud_spdifin.hw,
403 [AUD_CLKID_SPDIFOUT] = &axg_spdifout.hw, 403 [AUD_CLKID_SPDIFOUT] = &aud_spdifout.hw,
404 [AUD_CLKID_RESAMPLE] = &axg_resample.hw, 404 [AUD_CLKID_RESAMPLE] = &aud_resample.hw,
405 [AUD_CLKID_POWER_DETECT] = &axg_power_detect.hw, 405 [AUD_CLKID_POWER_DETECT] = &aud_power_detect.hw,
406 [AUD_CLKID_MST_A_MCLK_SEL] = &axg_mst_a_mclk_sel.hw, 406 [AUD_CLKID_MST_A_MCLK_SEL] = &aud_mst_a_mclk_sel.hw,
407 [AUD_CLKID_MST_B_MCLK_SEL] = &axg_mst_b_mclk_sel.hw, 407 [AUD_CLKID_MST_B_MCLK_SEL] = &aud_mst_b_mclk_sel.hw,
408 [AUD_CLKID_MST_C_MCLK_SEL] = &axg_mst_c_mclk_sel.hw, 408 [AUD_CLKID_MST_C_MCLK_SEL] = &aud_mst_c_mclk_sel.hw,
409 [AUD_CLKID_MST_D_MCLK_SEL] = &axg_mst_d_mclk_sel.hw, 409 [AUD_CLKID_MST_D_MCLK_SEL] = &aud_mst_d_mclk_sel.hw,
410 [AUD_CLKID_MST_E_MCLK_SEL] = &axg_mst_e_mclk_sel.hw, 410 [AUD_CLKID_MST_E_MCLK_SEL] = &aud_mst_e_mclk_sel.hw,
411 [AUD_CLKID_MST_F_MCLK_SEL] = &axg_mst_f_mclk_sel.hw, 411 [AUD_CLKID_MST_F_MCLK_SEL] = &aud_mst_f_mclk_sel.hw,
412 [AUD_CLKID_MST_A_MCLK_DIV] = &axg_mst_a_mclk_div.hw, 412 [AUD_CLKID_MST_A_MCLK_DIV] = &aud_mst_a_mclk_div.hw,
413 [AUD_CLKID_MST_B_MCLK_DIV] = &axg_mst_b_mclk_div.hw, 413 [AUD_CLKID_MST_B_MCLK_DIV] = &aud_mst_b_mclk_div.hw,
414 [AUD_CLKID_MST_C_MCLK_DIV] = &axg_mst_c_mclk_div.hw, 414 [AUD_CLKID_MST_C_MCLK_DIV] = &aud_mst_c_mclk_div.hw,
415 [AUD_CLKID_MST_D_MCLK_DIV] = &axg_mst_d_mclk_div.hw, 415 [AUD_CLKID_MST_D_MCLK_DIV] = &aud_mst_d_mclk_div.hw,
416 [AUD_CLKID_MST_E_MCLK_DIV] = &axg_mst_e_mclk_div.hw, 416 [AUD_CLKID_MST_E_MCLK_DIV] = &aud_mst_e_mclk_div.hw,
417 [AUD_CLKID_MST_F_MCLK_DIV] = &axg_mst_f_mclk_div.hw, 417 [AUD_CLKID_MST_F_MCLK_DIV] = &aud_mst_f_mclk_div.hw,
418 [AUD_CLKID_MST_A_MCLK] = &axg_mst_a_mclk.hw, 418 [AUD_CLKID_MST_A_MCLK] = &aud_mst_a_mclk.hw,
419 [AUD_CLKID_MST_B_MCLK] = &axg_mst_b_mclk.hw, 419 [AUD_CLKID_MST_B_MCLK] = &aud_mst_b_mclk.hw,
420 [AUD_CLKID_MST_C_MCLK] = &axg_mst_c_mclk.hw, 420 [AUD_CLKID_MST_C_MCLK] = &aud_mst_c_mclk.hw,
421 [AUD_CLKID_MST_D_MCLK] = &axg_mst_d_mclk.hw, 421 [AUD_CLKID_MST_D_MCLK] = &aud_mst_d_mclk.hw,
422 [AUD_CLKID_MST_E_MCLK] = &axg_mst_e_mclk.hw, 422 [AUD_CLKID_MST_E_MCLK] = &aud_mst_e_mclk.hw,
423 [AUD_CLKID_MST_F_MCLK] = &axg_mst_f_mclk.hw, 423 [AUD_CLKID_MST_F_MCLK] = &aud_mst_f_mclk.hw,
424 [AUD_CLKID_SPDIFOUT_CLK_SEL] = &axg_spdifout_clk_sel.hw, 424 [AUD_CLKID_SPDIFOUT_CLK_SEL] = &aud_spdifout_clk_sel.hw,
425 [AUD_CLKID_SPDIFOUT_CLK_DIV] = &axg_spdifout_clk_div.hw, 425 [AUD_CLKID_SPDIFOUT_CLK_DIV] = &aud_spdifout_clk_div.hw,
426 [AUD_CLKID_SPDIFOUT_CLK] = &axg_spdifout_clk.hw, 426 [AUD_CLKID_SPDIFOUT_CLK] = &aud_spdifout_clk.hw,
427 [AUD_CLKID_SPDIFIN_CLK_SEL] = &axg_spdifin_clk_sel.hw, 427 [AUD_CLKID_SPDIFIN_CLK_SEL] = &aud_spdifin_clk_sel.hw,
428 [AUD_CLKID_SPDIFIN_CLK_DIV] = &axg_spdifin_clk_div.hw, 428 [AUD_CLKID_SPDIFIN_CLK_DIV] = &aud_spdifin_clk_div.hw,
429 [AUD_CLKID_SPDIFIN_CLK] = &axg_spdifin_clk.hw, 429 [AUD_CLKID_SPDIFIN_CLK] = &aud_spdifin_clk.hw,
430 [AUD_CLKID_PDM_DCLK_SEL] = &axg_pdm_dclk_sel.hw, 430 [AUD_CLKID_PDM_DCLK_SEL] = &aud_pdm_dclk_sel.hw,
431 [AUD_CLKID_PDM_DCLK_DIV] = &axg_pdm_dclk_div.hw, 431 [AUD_CLKID_PDM_DCLK_DIV] = &aud_pdm_dclk_div.hw,
432 [AUD_CLKID_PDM_DCLK] = &axg_pdm_dclk.hw, 432 [AUD_CLKID_PDM_DCLK] = &aud_pdm_dclk.hw,
433 [AUD_CLKID_PDM_SYSCLK_SEL] = &axg_pdm_sysclk_sel.hw, 433 [AUD_CLKID_PDM_SYSCLK_SEL] = &aud_pdm_sysclk_sel.hw,
434 [AUD_CLKID_PDM_SYSCLK_DIV] = &axg_pdm_sysclk_div.hw, 434 [AUD_CLKID_PDM_SYSCLK_DIV] = &aud_pdm_sysclk_div.hw,
435 [AUD_CLKID_PDM_SYSCLK] = &axg_pdm_sysclk.hw, 435 [AUD_CLKID_PDM_SYSCLK] = &aud_pdm_sysclk.hw,
436 [AUD_CLKID_MST_A_SCLK_PRE_EN] = &axg_mst_a_sclk_pre_en.hw, 436 [AUD_CLKID_MST_A_SCLK_PRE_EN] = &aud_mst_a_sclk_pre_en.hw,
437 [AUD_CLKID_MST_B_SCLK_PRE_EN] = &axg_mst_b_sclk_pre_en.hw, 437 [AUD_CLKID_MST_B_SCLK_PRE_EN] = &aud_mst_b_sclk_pre_en.hw,
438 [AUD_CLKID_MST_C_SCLK_PRE_EN] = &axg_mst_c_sclk_pre_en.hw, 438 [AUD_CLKID_MST_C_SCLK_PRE_EN] = &aud_mst_c_sclk_pre_en.hw,
439 [AUD_CLKID_MST_D_SCLK_PRE_EN] = &axg_mst_d_sclk_pre_en.hw, 439 [AUD_CLKID_MST_D_SCLK_PRE_EN] = &aud_mst_d_sclk_pre_en.hw,
440 [AUD_CLKID_MST_E_SCLK_PRE_EN] = &axg_mst_e_sclk_pre_en.hw, 440 [AUD_CLKID_MST_E_SCLK_PRE_EN] = &aud_mst_e_sclk_pre_en.hw,
441 [AUD_CLKID_MST_F_SCLK_PRE_EN] = &axg_mst_f_sclk_pre_en.hw, 441 [AUD_CLKID_MST_F_SCLK_PRE_EN] = &aud_mst_f_sclk_pre_en.hw,
442 [AUD_CLKID_MST_A_SCLK_DIV] = &axg_mst_a_sclk_div.hw, 442 [AUD_CLKID_MST_A_SCLK_DIV] = &aud_mst_a_sclk_div.hw,
443 [AUD_CLKID_MST_B_SCLK_DIV] = &axg_mst_b_sclk_div.hw, 443 [AUD_CLKID_MST_B_SCLK_DIV] = &aud_mst_b_sclk_div.hw,
444 [AUD_CLKID_MST_C_SCLK_DIV] = &axg_mst_c_sclk_div.hw, 444 [AUD_CLKID_MST_C_SCLK_DIV] = &aud_mst_c_sclk_div.hw,
445 [AUD_CLKID_MST_D_SCLK_DIV] = &axg_mst_d_sclk_div.hw, 445 [AUD_CLKID_MST_D_SCLK_DIV] = &aud_mst_d_sclk_div.hw,
446 [AUD_CLKID_MST_E_SCLK_DIV] = &axg_mst_e_sclk_div.hw, 446 [AUD_CLKID_MST_E_SCLK_DIV] = &aud_mst_e_sclk_div.hw,
447 [AUD_CLKID_MST_F_SCLK_DIV] = &axg_mst_f_sclk_div.hw, 447 [AUD_CLKID_MST_F_SCLK_DIV] = &aud_mst_f_sclk_div.hw,
448 [AUD_CLKID_MST_A_SCLK_POST_EN] = &axg_mst_a_sclk_post_en.hw, 448 [AUD_CLKID_MST_A_SCLK_POST_EN] = &aud_mst_a_sclk_post_en.hw,
449 [AUD_CLKID_MST_B_SCLK_POST_EN] = &axg_mst_b_sclk_post_en.hw, 449 [AUD_CLKID_MST_B_SCLK_POST_EN] = &aud_mst_b_sclk_post_en.hw,
450 [AUD_CLKID_MST_C_SCLK_POST_EN] = &axg_mst_c_sclk_post_en.hw, 450 [AUD_CLKID_MST_C_SCLK_POST_EN] = &aud_mst_c_sclk_post_en.hw,
451 [AUD_CLKID_MST_D_SCLK_POST_EN] = &axg_mst_d_sclk_post_en.hw, 451 [AUD_CLKID_MST_D_SCLK_POST_EN] = &aud_mst_d_sclk_post_en.hw,
452 [AUD_CLKID_MST_E_SCLK_POST_EN] = &axg_mst_e_sclk_post_en.hw, 452 [AUD_CLKID_MST_E_SCLK_POST_EN] = &aud_mst_e_sclk_post_en.hw,
453 [AUD_CLKID_MST_F_SCLK_POST_EN] = &axg_mst_f_sclk_post_en.hw, 453 [AUD_CLKID_MST_F_SCLK_POST_EN] = &aud_mst_f_sclk_post_en.hw,
454 [AUD_CLKID_MST_A_SCLK] = &axg_mst_a_sclk.hw, 454 [AUD_CLKID_MST_A_SCLK] = &aud_mst_a_sclk.hw,
455 [AUD_CLKID_MST_B_SCLK] = &axg_mst_b_sclk.hw, 455 [AUD_CLKID_MST_B_SCLK] = &aud_mst_b_sclk.hw,
456 [AUD_CLKID_MST_C_SCLK] = &axg_mst_c_sclk.hw, 456 [AUD_CLKID_MST_C_SCLK] = &aud_mst_c_sclk.hw,
457 [AUD_CLKID_MST_D_SCLK] = &axg_mst_d_sclk.hw, 457 [AUD_CLKID_MST_D_SCLK] = &aud_mst_d_sclk.hw,
458 [AUD_CLKID_MST_E_SCLK] = &axg_mst_e_sclk.hw, 458 [AUD_CLKID_MST_E_SCLK] = &aud_mst_e_sclk.hw,
459 [AUD_CLKID_MST_F_SCLK] = &axg_mst_f_sclk.hw, 459 [AUD_CLKID_MST_F_SCLK] = &aud_mst_f_sclk.hw,
460 [AUD_CLKID_MST_A_LRCLK_DIV] = &axg_mst_a_lrclk_div.hw, 460 [AUD_CLKID_MST_A_LRCLK_DIV] = &aud_mst_a_lrclk_div.hw,
461 [AUD_CLKID_MST_B_LRCLK_DIV] = &axg_mst_b_lrclk_div.hw, 461 [AUD_CLKID_MST_B_LRCLK_DIV] = &aud_mst_b_lrclk_div.hw,
462 [AUD_CLKID_MST_C_LRCLK_DIV] = &axg_mst_c_lrclk_div.hw, 462 [AUD_CLKID_MST_C_LRCLK_DIV] = &aud_mst_c_lrclk_div.hw,
463 [AUD_CLKID_MST_D_LRCLK_DIV] = &axg_mst_d_lrclk_div.hw, 463 [AUD_CLKID_MST_D_LRCLK_DIV] = &aud_mst_d_lrclk_div.hw,
464 [AUD_CLKID_MST_E_LRCLK_DIV] = &axg_mst_e_lrclk_div.hw, 464 [AUD_CLKID_MST_E_LRCLK_DIV] = &aud_mst_e_lrclk_div.hw,
465 [AUD_CLKID_MST_F_LRCLK_DIV] = &axg_mst_f_lrclk_div.hw, 465 [AUD_CLKID_MST_F_LRCLK_DIV] = &aud_mst_f_lrclk_div.hw,
466 [AUD_CLKID_MST_A_LRCLK] = &axg_mst_a_lrclk.hw, 466 [AUD_CLKID_MST_A_LRCLK] = &aud_mst_a_lrclk.hw,
467 [AUD_CLKID_MST_B_LRCLK] = &axg_mst_b_lrclk.hw, 467 [AUD_CLKID_MST_B_LRCLK] = &aud_mst_b_lrclk.hw,
468 [AUD_CLKID_MST_C_LRCLK] = &axg_mst_c_lrclk.hw, 468 [AUD_CLKID_MST_C_LRCLK] = &aud_mst_c_lrclk.hw,
469 [AUD_CLKID_MST_D_LRCLK] = &axg_mst_d_lrclk.hw, 469 [AUD_CLKID_MST_D_LRCLK] = &aud_mst_d_lrclk.hw,
470 [AUD_CLKID_MST_E_LRCLK] = &axg_mst_e_lrclk.hw, 470 [AUD_CLKID_MST_E_LRCLK] = &aud_mst_e_lrclk.hw,
471 [AUD_CLKID_MST_F_LRCLK] = &axg_mst_f_lrclk.hw, 471 [AUD_CLKID_MST_F_LRCLK] = &aud_mst_f_lrclk.hw,
472 [AUD_CLKID_TDMIN_A_SCLK_SEL] = &axg_tdmin_a_sclk_sel.hw, 472 [AUD_CLKID_TDMIN_A_SCLK_SEL] = &aud_tdmin_a_sclk_sel.hw,
473 [AUD_CLKID_TDMIN_B_SCLK_SEL] = &axg_tdmin_b_sclk_sel.hw, 473 [AUD_CLKID_TDMIN_B_SCLK_SEL] = &aud_tdmin_b_sclk_sel.hw,
474 [AUD_CLKID_TDMIN_C_SCLK_SEL] = &axg_tdmin_c_sclk_sel.hw, 474 [AUD_CLKID_TDMIN_C_SCLK_SEL] = &aud_tdmin_c_sclk_sel.hw,
475 [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &axg_tdmin_lb_sclk_sel.hw, 475 [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &aud_tdmin_lb_sclk_sel.hw,
476 [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &axg_tdmout_a_sclk_sel.hw, 476 [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &aud_tdmout_a_sclk_sel.hw,
477 [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &axg_tdmout_b_sclk_sel.hw, 477 [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &aud_tdmout_b_sclk_sel.hw,
478 [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &axg_tdmout_c_sclk_sel.hw, 478 [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &aud_tdmout_c_sclk_sel.hw,
479 [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &axg_tdmin_a_sclk_pre_en.hw, 479 [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &aud_tdmin_a_sclk_pre_en.hw,
480 [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &axg_tdmin_b_sclk_pre_en.hw, 480 [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &aud_tdmin_b_sclk_pre_en.hw,
481 [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &axg_tdmin_c_sclk_pre_en.hw, 481 [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &aud_tdmin_c_sclk_pre_en.hw,
482 [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &axg_tdmin_lb_sclk_pre_en.hw, 482 [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &aud_tdmin_lb_sclk_pre_en.hw,
483 [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &axg_tdmout_a_sclk_pre_en.hw, 483 [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &aud_tdmout_a_sclk_pre_en.hw,
484 [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &axg_tdmout_b_sclk_pre_en.hw, 484 [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &aud_tdmout_b_sclk_pre_en.hw,
485 [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &axg_tdmout_c_sclk_pre_en.hw, 485 [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &aud_tdmout_c_sclk_pre_en.hw,
486 [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &axg_tdmin_a_sclk_post_en.hw, 486 [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &aud_tdmin_a_sclk_post_en.hw,
487 [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &axg_tdmin_b_sclk_post_en.hw, 487 [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &aud_tdmin_b_sclk_post_en.hw,
488 [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &axg_tdmin_c_sclk_post_en.hw, 488 [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &aud_tdmin_c_sclk_post_en.hw,
489 [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &axg_tdmin_lb_sclk_post_en.hw, 489 [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &aud_tdmin_lb_sclk_post_en.hw,
490 [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &axg_tdmout_a_sclk_post_en.hw, 490 [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &aud_tdmout_a_sclk_post_en.hw,
491 [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &axg_tdmout_b_sclk_post_en.hw, 491 [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &aud_tdmout_b_sclk_post_en.hw,
492 [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &axg_tdmout_c_sclk_post_en.hw, 492 [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &aud_tdmout_c_sclk_post_en.hw,
493 [AUD_CLKID_TDMIN_A_SCLK] = &axg_tdmin_a_sclk.hw, 493 [AUD_CLKID_TDMIN_A_SCLK] = &aud_tdmin_a_sclk.hw,
494 [AUD_CLKID_TDMIN_B_SCLK] = &axg_tdmin_b_sclk.hw, 494 [AUD_CLKID_TDMIN_B_SCLK] = &aud_tdmin_b_sclk.hw,
495 [AUD_CLKID_TDMIN_C_SCLK] = &axg_tdmin_c_sclk.hw, 495 [AUD_CLKID_TDMIN_C_SCLK] = &aud_tdmin_c_sclk.hw,
496 [AUD_CLKID_TDMIN_LB_SCLK] = &axg_tdmin_lb_sclk.hw, 496 [AUD_CLKID_TDMIN_LB_SCLK] = &aud_tdmin_lb_sclk.hw,
497 [AUD_CLKID_TDMOUT_A_SCLK] = &axg_tdmout_a_sclk.hw, 497 [AUD_CLKID_TDMOUT_A_SCLK] = &aud_tdmout_a_sclk.hw,
498 [AUD_CLKID_TDMOUT_B_SCLK] = &axg_tdmout_b_sclk.hw, 498 [AUD_CLKID_TDMOUT_B_SCLK] = &aud_tdmout_b_sclk.hw,
499 [AUD_CLKID_TDMOUT_C_SCLK] = &axg_tdmout_c_sclk.hw, 499 [AUD_CLKID_TDMOUT_C_SCLK] = &aud_tdmout_c_sclk.hw,
500 [AUD_CLKID_TDMIN_A_LRCLK] = &axg_tdmin_a_lrclk.hw, 500 [AUD_CLKID_TDMIN_A_LRCLK] = &aud_tdmin_a_lrclk.hw,
501 [AUD_CLKID_TDMIN_B_LRCLK] = &axg_tdmin_b_lrclk.hw, 501 [AUD_CLKID_TDMIN_B_LRCLK] = &aud_tdmin_b_lrclk.hw,
502 [AUD_CLKID_TDMIN_C_LRCLK] = &axg_tdmin_c_lrclk.hw, 502 [AUD_CLKID_TDMIN_C_LRCLK] = &aud_tdmin_c_lrclk.hw,
503 [AUD_CLKID_TDMIN_LB_LRCLK] = &axg_tdmin_lb_lrclk.hw, 503 [AUD_CLKID_TDMIN_LB_LRCLK] = &aud_tdmin_lb_lrclk.hw,
504 [AUD_CLKID_TDMOUT_A_LRCLK] = &axg_tdmout_a_lrclk.hw, 504 [AUD_CLKID_TDMOUT_A_LRCLK] = &aud_tdmout_a_lrclk.hw,
505 [AUD_CLKID_TDMOUT_B_LRCLK] = &axg_tdmout_b_lrclk.hw, 505 [AUD_CLKID_TDMOUT_B_LRCLK] = &aud_tdmout_b_lrclk.hw,
506 [AUD_CLKID_TDMOUT_C_LRCLK] = &axg_tdmout_c_lrclk.hw, 506 [AUD_CLKID_TDMOUT_C_LRCLK] = &aud_tdmout_c_lrclk.hw,
507 [NR_CLKS] = NULL, 507 [NR_CLKS] = NULL,
508 }, 508 },
509 .num = NR_CLKS, 509 .num = NR_CLKS,
510}; 510};
511 511
512/* Convenience table to populate regmap in .probe() */ 512/* Convenience table to populate regmap in .probe() */
513static struct clk_regmap *const axg_audio_clk_regmaps[] = { 513static struct clk_regmap *const aud_clk_regmaps[] = {
514 &axg_ddr_arb, 514 &aud_ddr_arb,
515 &axg_pdm, 515 &aud_pdm,
516 &axg_tdmin_a, 516 &aud_tdmin_a,
517 &axg_tdmin_b, 517 &aud_tdmin_b,
518 &axg_tdmin_c, 518 &aud_tdmin_c,
519 &axg_tdmin_lb, 519 &aud_tdmin_lb,
520 &axg_tdmout_a, 520 &aud_tdmout_a,
521 &axg_tdmout_b, 521 &aud_tdmout_b,
522 &axg_tdmout_c, 522 &aud_tdmout_c,
523 &axg_frddr_a, 523 &aud_frddr_a,
524 &axg_frddr_b, 524 &aud_frddr_b,
525 &axg_frddr_c, 525 &aud_frddr_c,
526 &axg_toddr_a, 526 &aud_toddr_a,
527 &axg_toddr_b, 527 &aud_toddr_b,
528 &axg_toddr_c, 528 &aud_toddr_c,
529 &axg_loopback, 529 &aud_loopback,
530 &axg_spdifin, 530 &aud_spdifin,
531 &axg_spdifout, 531 &aud_spdifout,
532 &axg_resample, 532 &aud_resample,
533 &axg_power_detect, 533 &aud_power_detect,
534 &axg_mst_a_mclk_sel, 534 &aud_mst_a_mclk_sel,
535 &axg_mst_b_mclk_sel, 535 &aud_mst_b_mclk_sel,
536 &axg_mst_c_mclk_sel, 536 &aud_mst_c_mclk_sel,
537 &axg_mst_d_mclk_sel, 537 &aud_mst_d_mclk_sel,
538 &axg_mst_e_mclk_sel, 538 &aud_mst_e_mclk_sel,
539 &axg_mst_f_mclk_sel, 539 &aud_mst_f_mclk_sel,
540 &axg_mst_a_mclk_div, 540 &aud_mst_a_mclk_div,
541 &axg_mst_b_mclk_div, 541 &aud_mst_b_mclk_div,
542 &axg_mst_c_mclk_div, 542 &aud_mst_c_mclk_div,
543 &axg_mst_d_mclk_div, 543 &aud_mst_d_mclk_div,
544 &axg_mst_e_mclk_div, 544 &aud_mst_e_mclk_div,
545 &axg_mst_f_mclk_div, 545 &aud_mst_f_mclk_div,
546 &axg_mst_a_mclk, 546 &aud_mst_a_mclk,
547 &axg_mst_b_mclk, 547 &aud_mst_b_mclk,
548 &axg_mst_c_mclk, 548 &aud_mst_c_mclk,
549 &axg_mst_d_mclk, 549 &aud_mst_d_mclk,
550 &axg_mst_e_mclk, 550 &aud_mst_e_mclk,
551 &axg_mst_f_mclk, 551 &aud_mst_f_mclk,
552 &axg_spdifout_clk_sel, 552 &aud_spdifout_clk_sel,
553 &axg_spdifout_clk_div, 553 &aud_spdifout_clk_div,
554 &axg_spdifout_clk, 554 &aud_spdifout_clk,
555 &axg_spdifin_clk_sel, 555 &aud_spdifin_clk_sel,
556 &axg_spdifin_clk_div, 556 &aud_spdifin_clk_div,
557 &axg_spdifin_clk, 557 &aud_spdifin_clk,
558 &axg_pdm_dclk_sel, 558 &aud_pdm_dclk_sel,
559 &axg_pdm_dclk_div, 559 &aud_pdm_dclk_div,
560 &axg_pdm_dclk, 560 &aud_pdm_dclk,
561 &axg_pdm_sysclk_sel, 561 &aud_pdm_sysclk_sel,
562 &axg_pdm_sysclk_div, 562 &aud_pdm_sysclk_div,
563 &axg_pdm_sysclk, 563 &aud_pdm_sysclk,
564 &axg_mst_a_sclk_pre_en, 564 &aud_mst_a_sclk_pre_en,
565 &axg_mst_b_sclk_pre_en, 565 &aud_mst_b_sclk_pre_en,
566 &axg_mst_c_sclk_pre_en, 566 &aud_mst_c_sclk_pre_en,
567 &axg_mst_d_sclk_pre_en, 567 &aud_mst_d_sclk_pre_en,
568 &axg_mst_e_sclk_pre_en, 568 &aud_mst_e_sclk_pre_en,
569 &axg_mst_f_sclk_pre_en, 569 &aud_mst_f_sclk_pre_en,
570 &axg_mst_a_sclk_div, 570 &aud_mst_a_sclk_div,
571 &axg_mst_b_sclk_div, 571 &aud_mst_b_sclk_div,
572 &axg_mst_c_sclk_div, 572 &aud_mst_c_sclk_div,
573 &axg_mst_d_sclk_div, 573 &aud_mst_d_sclk_div,
574 &axg_mst_e_sclk_div, 574 &aud_mst_e_sclk_div,
575 &axg_mst_f_sclk_div, 575 &aud_mst_f_sclk_div,
576 &axg_mst_a_sclk_post_en, 576 &aud_mst_a_sclk_post_en,
577 &axg_mst_b_sclk_post_en, 577 &aud_mst_b_sclk_post_en,
578 &axg_mst_c_sclk_post_en, 578 &aud_mst_c_sclk_post_en,
579 &axg_mst_d_sclk_post_en, 579 &aud_mst_d_sclk_post_en,
580 &axg_mst_e_sclk_post_en, 580 &aud_mst_e_sclk_post_en,
581 &axg_mst_f_sclk_post_en, 581 &aud_mst_f_sclk_post_en,
582 &axg_mst_a_sclk, 582 &aud_mst_a_sclk,
583 &axg_mst_b_sclk, 583 &aud_mst_b_sclk,
584 &axg_mst_c_sclk, 584 &aud_mst_c_sclk,
585 &axg_mst_d_sclk, 585 &aud_mst_d_sclk,
586 &axg_mst_e_sclk, 586 &aud_mst_e_sclk,
587 &axg_mst_f_sclk, 587 &aud_mst_f_sclk,
588 &axg_mst_a_lrclk_div, 588 &aud_mst_a_lrclk_div,
589 &axg_mst_b_lrclk_div, 589 &aud_mst_b_lrclk_div,
590 &axg_mst_c_lrclk_div, 590 &aud_mst_c_lrclk_div,
591 &axg_mst_d_lrclk_div, 591 &aud_mst_d_lrclk_div,
592 &axg_mst_e_lrclk_div, 592 &aud_mst_e_lrclk_div,
593 &axg_mst_f_lrclk_div, 593 &aud_mst_f_lrclk_div,
594 &axg_mst_a_lrclk, 594 &aud_mst_a_lrclk,
595 &axg_mst_b_lrclk, 595 &aud_mst_b_lrclk,
596 &axg_mst_c_lrclk, 596 &aud_mst_c_lrclk,
597 &axg_mst_d_lrclk, 597 &aud_mst_d_lrclk,
598 &axg_mst_e_lrclk, 598 &aud_mst_e_lrclk,
599 &axg_mst_f_lrclk, 599 &aud_mst_f_lrclk,
600 &axg_tdmin_a_sclk_sel, 600 &aud_tdmin_a_sclk_sel,
601 &axg_tdmin_b_sclk_sel, 601 &aud_tdmin_b_sclk_sel,
602 &axg_tdmin_c_sclk_sel, 602 &aud_tdmin_c_sclk_sel,
603 &axg_tdmin_lb_sclk_sel, 603 &aud_tdmin_lb_sclk_sel,
604 &axg_tdmout_a_sclk_sel, 604 &aud_tdmout_a_sclk_sel,
605 &axg_tdmout_b_sclk_sel, 605 &aud_tdmout_b_sclk_sel,
606 &axg_tdmout_c_sclk_sel, 606 &aud_tdmout_c_sclk_sel,
607 &axg_tdmin_a_sclk_pre_en, 607 &aud_tdmin_a_sclk_pre_en,
608 &axg_tdmin_b_sclk_pre_en, 608 &aud_tdmin_b_sclk_pre_en,
609 &axg_tdmin_c_sclk_pre_en, 609 &aud_tdmin_c_sclk_pre_en,
610 &axg_tdmin_lb_sclk_pre_en, 610 &aud_tdmin_lb_sclk_pre_en,
611 &axg_tdmout_a_sclk_pre_en, 611 &aud_tdmout_a_sclk_pre_en,
612 &axg_tdmout_b_sclk_pre_en, 612 &aud_tdmout_b_sclk_pre_en,
613 &axg_tdmout_c_sclk_pre_en, 613 &aud_tdmout_c_sclk_pre_en,
614 &axg_tdmin_a_sclk_post_en, 614 &aud_tdmin_a_sclk_post_en,
615 &axg_tdmin_b_sclk_post_en, 615 &aud_tdmin_b_sclk_post_en,
616 &axg_tdmin_c_sclk_post_en, 616 &aud_tdmin_c_sclk_post_en,
617 &axg_tdmin_lb_sclk_post_en, 617 &aud_tdmin_lb_sclk_post_en,
618 &axg_tdmout_a_sclk_post_en, 618 &aud_tdmout_a_sclk_post_en,
619 &axg_tdmout_b_sclk_post_en, 619 &aud_tdmout_b_sclk_post_en,
620 &axg_tdmout_c_sclk_post_en, 620 &aud_tdmout_c_sclk_post_en,
621 &axg_tdmin_a_sclk, 621 &aud_tdmin_a_sclk,
622 &axg_tdmin_b_sclk, 622 &aud_tdmin_b_sclk,
623 &axg_tdmin_c_sclk, 623 &aud_tdmin_c_sclk,
624 &axg_tdmin_lb_sclk, 624 &aud_tdmin_lb_sclk,
625 &axg_tdmout_a_sclk, 625 &aud_tdmout_a_sclk,
626 &axg_tdmout_b_sclk, 626 &aud_tdmout_b_sclk,
627 &axg_tdmout_c_sclk, 627 &aud_tdmout_c_sclk,
628 &axg_tdmin_a_lrclk, 628 &aud_tdmin_a_lrclk,
629 &axg_tdmin_b_lrclk, 629 &aud_tdmin_b_lrclk,
630 &axg_tdmin_c_lrclk, 630 &aud_tdmin_c_lrclk,
631 &axg_tdmin_lb_lrclk, 631 &aud_tdmin_lb_lrclk,
632 &axg_tdmout_a_lrclk, 632 &aud_tdmout_a_lrclk,
633 &axg_tdmout_b_lrclk, 633 &aud_tdmout_b_lrclk,
634 &axg_tdmout_c_lrclk, 634 &aud_tdmout_c_lrclk,
635}; 635};
636 636
637static int devm_clk_get_enable(struct device *dev, char *id) 637static int devm_clk_get_enable(struct device *dev, char *id)
@@ -672,7 +672,7 @@ static int axg_register_clk_hw_input(struct device *dev,
672 struct clk_hw *hw; 672 struct clk_hw *hw;
673 int err = 0; 673 int err = 0;
674 674
675 clk_name = kasprintf(GFP_KERNEL, "axg_%s", name); 675 clk_name = kasprintf(GFP_KERNEL, "aud_%s", name);
676 if (!clk_name) 676 if (!clk_name)
677 return -ENOMEM; 677 return -ENOMEM;
678 678
@@ -755,7 +755,7 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
755 } 755 }
756 756
757 /* Register the peripheral input clock */ 757 /* Register the peripheral input clock */
758 hw = meson_clk_hw_register_input(dev, "pclk", "axg_audio_pclk", 0); 758 hw = meson_clk_hw_register_input(dev, "pclk", "audio_pclk", 0);
759 if (IS_ERR(hw)) 759 if (IS_ERR(hw))
760 return PTR_ERR(hw); 760 return PTR_ERR(hw);
761 761
@@ -763,28 +763,28 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
763 763
764 /* Register optional input master clocks */ 764 /* Register optional input master clocks */
765 ret = axg_register_clk_hw_inputs(dev, "mst_in", 765 ret = axg_register_clk_hw_inputs(dev, "mst_in",
766 AXG_MST_IN_COUNT, 766 AUD_MST_IN_COUNT,
767 AUD_CLKID_MST0); 767 AUD_CLKID_MST0);
768 if (ret) 768 if (ret)
769 return ret; 769 return ret;
770 770
771 /* Register optional input slave sclks */ 771 /* Register optional input slave sclks */
772 ret = axg_register_clk_hw_inputs(dev, "slv_sclk", 772 ret = axg_register_clk_hw_inputs(dev, "slv_sclk",
773 AXG_SLV_SCLK_COUNT, 773 AUD_SLV_SCLK_COUNT,
774 AUD_CLKID_SLV_SCLK0); 774 AUD_CLKID_SLV_SCLK0);
775 if (ret) 775 if (ret)
776 return ret; 776 return ret;
777 777
778 /* Register optional input slave lrclks */ 778 /* Register optional input slave lrclks */
779 ret = axg_register_clk_hw_inputs(dev, "slv_lrclk", 779 ret = axg_register_clk_hw_inputs(dev, "slv_lrclk",
780 AXG_SLV_LRCLK_COUNT, 780 AUD_SLV_LRCLK_COUNT,
781 AUD_CLKID_SLV_LRCLK0); 781 AUD_CLKID_SLV_LRCLK0);
782 if (ret) 782 if (ret)
783 return ret; 783 return ret;
784 784
785 /* Populate regmap for the regmap backed clocks */ 785 /* Populate regmap for the regmap backed clocks */
786 for (i = 0; i < ARRAY_SIZE(axg_audio_clk_regmaps); i++) 786 for (i = 0; i < ARRAY_SIZE(aud_clk_regmaps); i++)
787 axg_audio_clk_regmaps[i]->map = map; 787 aud_clk_regmaps[i]->map = map;
788 788
789 /* Take care to skip the registered input clocks */ 789 /* Take care to skip the registered input clocks */
790 for (i = AUD_CLKID_DDR_ARB; i < axg_audio_hw_onecell_data.num; i++) { 790 for (i = AUD_CLKID_DDR_ARB; i < axg_audio_hw_onecell_data.num; i++) {
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-30 19:07:55 -0500