diff options
-rw-r--r-- | drivers/clk/clk-gpio.c | 33 | ||||
-rw-r--r-- | drivers/clk/clk-qoriq.c | 4 | ||||
-rw-r--r-- | drivers/clk/clk-scpi.c | 1 | ||||
-rw-r--r-- | drivers/clk/imx/clk-pllv1.c | 14 | ||||
-rw-r--r-- | drivers/clk/imx/clk-pllv2.c | 9 | ||||
-rw-r--r-- | drivers/clk/mmp/clk-mmp2.c | 1 | ||||
-rw-r--r-- | drivers/clk/mmp/clk-pxa168.c | 1 | ||||
-rw-r--r-- | drivers/clk/mmp/clk-pxa910.c | 1 | ||||
-rw-r--r-- | drivers/clk/sunxi/clk-a10-pll2.c | 23 | ||||
-rw-r--r-- | drivers/clk/ti/clk-816x.c | 2 | ||||
-rw-r--r-- | drivers/clk/ti/clkt_dpll.c | 4 | ||||
-rw-r--r-- | drivers/clk/ti/divider.c | 16 | ||||
-rw-r--r-- | drivers/clk/ti/fapll.c | 4 | ||||
-rw-r--r-- | drivers/clk/ti/mux.c | 15 |
14 files changed, 53 insertions, 75 deletions
diff --git a/drivers/clk/clk-gpio.c b/drivers/clk/clk-gpio.c index 10819e248414..335322dc403f 100644 --- a/drivers/clk/clk-gpio.c +++ b/drivers/clk/clk-gpio.c | |||
@@ -209,6 +209,8 @@ EXPORT_SYMBOL_GPL(clk_register_gpio_mux); | |||
209 | 209 | ||
210 | struct clk_gpio_delayed_register_data { | 210 | struct clk_gpio_delayed_register_data { |
211 | const char *gpio_name; | 211 | const char *gpio_name; |
212 | int num_parents; | ||
213 | const char **parent_names; | ||
212 | struct device_node *node; | 214 | struct device_node *node; |
213 | struct mutex lock; | 215 | struct mutex lock; |
214 | struct clk *clk; | 216 | struct clk *clk; |
@@ -222,8 +224,6 @@ static struct clk *of_clk_gpio_delayed_register_get( | |||
222 | { | 224 | { |
223 | struct clk_gpio_delayed_register_data *data = _data; | 225 | struct clk_gpio_delayed_register_data *data = _data; |
224 | struct clk *clk; | 226 | struct clk *clk; |
225 | const char **parent_names; | ||
226 | int i, num_parents; | ||
227 | int gpio; | 227 | int gpio; |
228 | enum of_gpio_flags of_flags; | 228 | enum of_gpio_flags of_flags; |
229 | 229 | ||
@@ -248,26 +248,14 @@ static struct clk *of_clk_gpio_delayed_register_get( | |||
248 | return ERR_PTR(gpio); | 248 | return ERR_PTR(gpio); |
249 | } | 249 | } |
250 | 250 | ||
251 | num_parents = of_clk_get_parent_count(data->node); | 251 | clk = data->clk_register_get(data->node->name, data->parent_names, |
252 | 252 | data->num_parents, gpio, of_flags & OF_GPIO_ACTIVE_LOW); | |
253 | parent_names = kcalloc(num_parents, sizeof(char *), GFP_KERNEL); | ||
254 | if (!parent_names) { | ||
255 | clk = ERR_PTR(-ENOMEM); | ||
256 | goto out; | ||
257 | } | ||
258 | |||
259 | for (i = 0; i < num_parents; i++) | ||
260 | parent_names[i] = of_clk_get_parent_name(data->node, i); | ||
261 | |||
262 | clk = data->clk_register_get(data->node->name, parent_names, | ||
263 | num_parents, gpio, of_flags & OF_GPIO_ACTIVE_LOW); | ||
264 | if (IS_ERR(clk)) | 253 | if (IS_ERR(clk)) |
265 | goto out; | 254 | goto out; |
266 | 255 | ||
267 | data->clk = clk; | 256 | data->clk = clk; |
268 | out: | 257 | out: |
269 | mutex_unlock(&data->lock); | 258 | mutex_unlock(&data->lock); |
270 | kfree(parent_names); | ||
271 | 259 | ||
272 | return clk; | 260 | return clk; |
273 | } | 261 | } |
@@ -296,11 +284,24 @@ static void __init of_gpio_clk_setup(struct device_node *node, | |||
296 | unsigned gpio, bool active_low)) | 284 | unsigned gpio, bool active_low)) |
297 | { | 285 | { |
298 | struct clk_gpio_delayed_register_data *data; | 286 | struct clk_gpio_delayed_register_data *data; |
287 | const char **parent_names; | ||
288 | int i, num_parents; | ||
299 | 289 | ||
300 | data = kzalloc(sizeof(*data), GFP_KERNEL); | 290 | data = kzalloc(sizeof(*data), GFP_KERNEL); |
301 | if (!data) | 291 | if (!data) |
302 | return; | 292 | return; |
303 | 293 | ||
294 | num_parents = of_clk_get_parent_count(node); | ||
295 | |||
296 | parent_names = kcalloc(num_parents, sizeof(char *), GFP_KERNEL); | ||
297 | if (!parent_names) | ||
298 | return; | ||
299 | |||
300 | for (i = 0; i < num_parents; i++) | ||
301 | parent_names[i] = of_clk_get_parent_name(node, i); | ||
302 | |||
303 | data->num_parents = num_parents; | ||
304 | data->parent_names = parent_names; | ||
304 | data->node = node; | 305 | data->node = node; |
305 | data->gpio_name = gpio_name; | 306 | data->gpio_name = gpio_name; |
306 | data->clk_register_get = clk_register_get; | 307 | data->clk_register_get = clk_register_get; |
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c index 1ab0fb81c6a0..7bc1c4527ae4 100644 --- a/drivers/clk/clk-qoriq.c +++ b/drivers/clk/clk-qoriq.c | |||
@@ -778,8 +778,10 @@ static struct clk * __init create_one_cmux(struct clockgen *cg, int idx) | |||
778 | */ | 778 | */ |
779 | clksel = (cg_in(cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT; | 779 | clksel = (cg_in(cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT; |
780 | div = get_pll_div(cg, hwc, clksel); | 780 | div = get_pll_div(cg, hwc, clksel); |
781 | if (!div) | 781 | if (!div) { |
782 | kfree(hwc); | ||
782 | return NULL; | 783 | return NULL; |
784 | } | ||
783 | 785 | ||
784 | pct80_rate = clk_get_rate(div->clk); | 786 | pct80_rate = clk_get_rate(div->clk); |
785 | pct80_rate *= 8; | 787 | pct80_rate *= 8; |
diff --git a/drivers/clk/clk-scpi.c b/drivers/clk/clk-scpi.c index 0b501a9fef92..cd0f2726f5e0 100644 --- a/drivers/clk/clk-scpi.c +++ b/drivers/clk/clk-scpi.c | |||
@@ -292,6 +292,7 @@ static int scpi_clocks_probe(struct platform_device *pdev) | |||
292 | ret = scpi_clk_add(dev, child, match); | 292 | ret = scpi_clk_add(dev, child, match); |
293 | if (ret) { | 293 | if (ret) { |
294 | scpi_clocks_remove(pdev); | 294 | scpi_clocks_remove(pdev); |
295 | of_node_put(child); | ||
295 | return ret; | 296 | return ret; |
296 | } | 297 | } |
297 | } | 298 | } |
diff --git a/drivers/clk/imx/clk-pllv1.c b/drivers/clk/imx/clk-pllv1.c index 8564e4342c7d..82fe3662b5f6 100644 --- a/drivers/clk/imx/clk-pllv1.c +++ b/drivers/clk/imx/clk-pllv1.c | |||
@@ -52,7 +52,7 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw, | |||
52 | unsigned long parent_rate) | 52 | unsigned long parent_rate) |
53 | { | 53 | { |
54 | struct clk_pllv1 *pll = to_clk_pllv1(hw); | 54 | struct clk_pllv1 *pll = to_clk_pllv1(hw); |
55 | long long ll; | 55 | unsigned long long ull; |
56 | int mfn_abs; | 56 | int mfn_abs; |
57 | unsigned int mfi, mfn, mfd, pd; | 57 | unsigned int mfi, mfn, mfd, pd; |
58 | u32 reg; | 58 | u32 reg; |
@@ -94,16 +94,16 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw, | |||
94 | rate = parent_rate * 2; | 94 | rate = parent_rate * 2; |
95 | rate /= pd + 1; | 95 | rate /= pd + 1; |
96 | 96 | ||
97 | ll = (unsigned long long)rate * mfn_abs; | 97 | ull = (unsigned long long)rate * mfn_abs; |
98 | 98 | ||
99 | do_div(ll, mfd + 1); | 99 | do_div(ull, mfd + 1); |
100 | 100 | ||
101 | if (mfn_is_negative(pll, mfn)) | 101 | if (mfn_is_negative(pll, mfn)) |
102 | ll = -ll; | 102 | ull = (rate * mfi) - ull; |
103 | else | ||
104 | ull = (rate * mfi) + ull; | ||
103 | 105 | ||
104 | ll = (rate * mfi) + ll; | 106 | return ull; |
105 | |||
106 | return ll; | ||
107 | } | 107 | } |
108 | 108 | ||
109 | static struct clk_ops clk_pllv1_ops = { | 109 | static struct clk_ops clk_pllv1_ops = { |
diff --git a/drivers/clk/imx/clk-pllv2.c b/drivers/clk/imx/clk-pllv2.c index b18f875eac6a..4aeda56ce372 100644 --- a/drivers/clk/imx/clk-pllv2.c +++ b/drivers/clk/imx/clk-pllv2.c | |||
@@ -79,7 +79,7 @@ static unsigned long __clk_pllv2_recalc_rate(unsigned long parent_rate, | |||
79 | { | 79 | { |
80 | long mfi, mfn, mfd, pdf, ref_clk; | 80 | long mfi, mfn, mfd, pdf, ref_clk; |
81 | unsigned long dbl; | 81 | unsigned long dbl; |
82 | s64 temp; | 82 | u64 temp; |
83 | 83 | ||
84 | dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN; | 84 | dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN; |
85 | 85 | ||
@@ -98,8 +98,9 @@ static unsigned long __clk_pllv2_recalc_rate(unsigned long parent_rate, | |||
98 | temp = (u64) ref_clk * abs(mfn); | 98 | temp = (u64) ref_clk * abs(mfn); |
99 | do_div(temp, mfd + 1); | 99 | do_div(temp, mfd + 1); |
100 | if (mfn < 0) | 100 | if (mfn < 0) |
101 | temp = -temp; | 101 | temp = (ref_clk * mfi) - temp; |
102 | temp = (ref_clk * mfi) + temp; | 102 | else |
103 | temp = (ref_clk * mfi) + temp; | ||
103 | 104 | ||
104 | return temp; | 105 | return temp; |
105 | } | 106 | } |
@@ -126,7 +127,7 @@ static int __clk_pllv2_set_rate(unsigned long rate, unsigned long parent_rate, | |||
126 | { | 127 | { |
127 | u32 reg; | 128 | u32 reg; |
128 | long mfi, pdf, mfn, mfd = 999999; | 129 | long mfi, pdf, mfn, mfd = 999999; |
129 | s64 temp64; | 130 | u64 temp64; |
130 | unsigned long quad_parent_rate; | 131 | unsigned long quad_parent_rate; |
131 | 132 | ||
132 | quad_parent_rate = 4 * parent_rate; | 133 | quad_parent_rate = 4 * parent_rate; |
diff --git a/drivers/clk/mmp/clk-mmp2.c b/drivers/clk/mmp/clk-mmp2.c index 09d2832fbd78..71fd29348f28 100644 --- a/drivers/clk/mmp/clk-mmp2.c +++ b/drivers/clk/mmp/clk-mmp2.c | |||
@@ -9,6 +9,7 @@ | |||
9 | * warranty of any kind, whether express or implied. | 9 | * warranty of any kind, whether express or implied. |
10 | */ | 10 | */ |
11 | 11 | ||
12 | #include <linux/clk.h> | ||
12 | #include <linux/module.h> | 13 | #include <linux/module.h> |
13 | #include <linux/kernel.h> | 14 | #include <linux/kernel.h> |
14 | #include <linux/spinlock.h> | 15 | #include <linux/spinlock.h> |
diff --git a/drivers/clk/mmp/clk-pxa168.c b/drivers/clk/mmp/clk-pxa168.c index 93e967c0f972..75244915df05 100644 --- a/drivers/clk/mmp/clk-pxa168.c +++ b/drivers/clk/mmp/clk-pxa168.c | |||
@@ -9,6 +9,7 @@ | |||
9 | * warranty of any kind, whether express or implied. | 9 | * warranty of any kind, whether express or implied. |
10 | */ | 10 | */ |
11 | 11 | ||
12 | #include <linux/clk.h> | ||
12 | #include <linux/module.h> | 13 | #include <linux/module.h> |
13 | #include <linux/kernel.h> | 14 | #include <linux/kernel.h> |
14 | #include <linux/spinlock.h> | 15 | #include <linux/spinlock.h> |
diff --git a/drivers/clk/mmp/clk-pxa910.c b/drivers/clk/mmp/clk-pxa910.c index 993abcdb32cc..37ba04ba1368 100644 --- a/drivers/clk/mmp/clk-pxa910.c +++ b/drivers/clk/mmp/clk-pxa910.c | |||
@@ -9,6 +9,7 @@ | |||
9 | * warranty of any kind, whether express or implied. | 9 | * warranty of any kind, whether express or implied. |
10 | */ | 10 | */ |
11 | 11 | ||
12 | #include <linux/clk.h> | ||
12 | #include <linux/module.h> | 13 | #include <linux/module.h> |
13 | #include <linux/kernel.h> | 14 | #include <linux/kernel.h> |
14 | #include <linux/spinlock.h> | 15 | #include <linux/spinlock.h> |
diff --git a/drivers/clk/sunxi/clk-a10-pll2.c b/drivers/clk/sunxi/clk-a10-pll2.c index 5484c31ec568..0ee1f363e4be 100644 --- a/drivers/clk/sunxi/clk-a10-pll2.c +++ b/drivers/clk/sunxi/clk-a10-pll2.c | |||
@@ -41,15 +41,10 @@ | |||
41 | 41 | ||
42 | #define SUN4I_PLL2_OUTPUTS 4 | 42 | #define SUN4I_PLL2_OUTPUTS 4 |
43 | 43 | ||
44 | struct sun4i_pll2_data { | ||
45 | u32 post_div_offset; | ||
46 | u32 pre_div_flags; | ||
47 | }; | ||
48 | |||
49 | static DEFINE_SPINLOCK(sun4i_a10_pll2_lock); | 44 | static DEFINE_SPINLOCK(sun4i_a10_pll2_lock); |
50 | 45 | ||
51 | static void __init sun4i_pll2_setup(struct device_node *node, | 46 | static void __init sun4i_pll2_setup(struct device_node *node, |
52 | struct sun4i_pll2_data *data) | 47 | int post_div_offset) |
53 | { | 48 | { |
54 | const char *clk_name = node->name, *parent; | 49 | const char *clk_name = node->name, *parent; |
55 | struct clk **clks, *base_clk, *prediv_clk; | 50 | struct clk **clks, *base_clk, *prediv_clk; |
@@ -76,7 +71,7 @@ static void __init sun4i_pll2_setup(struct device_node *node, | |||
76 | parent, 0, reg, | 71 | parent, 0, reg, |
77 | SUN4I_PLL2_PRE_DIV_SHIFT, | 72 | SUN4I_PLL2_PRE_DIV_SHIFT, |
78 | SUN4I_PLL2_PRE_DIV_WIDTH, | 73 | SUN4I_PLL2_PRE_DIV_WIDTH, |
79 | data->pre_div_flags, | 74 | CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, |
80 | &sun4i_a10_pll2_lock); | 75 | &sun4i_a10_pll2_lock); |
81 | if (!prediv_clk) { | 76 | if (!prediv_clk) { |
82 | pr_err("Couldn't register the prediv clock\n"); | 77 | pr_err("Couldn't register the prediv clock\n"); |
@@ -127,7 +122,7 @@ static void __init sun4i_pll2_setup(struct device_node *node, | |||
127 | */ | 122 | */ |
128 | val = readl(reg); | 123 | val = readl(reg); |
129 | val &= ~(SUN4I_PLL2_POST_DIV_MASK << SUN4I_PLL2_POST_DIV_SHIFT); | 124 | val &= ~(SUN4I_PLL2_POST_DIV_MASK << SUN4I_PLL2_POST_DIV_SHIFT); |
130 | val |= (SUN4I_PLL2_POST_DIV_VALUE - data->post_div_offset) << SUN4I_PLL2_POST_DIV_SHIFT; | 125 | val |= (SUN4I_PLL2_POST_DIV_VALUE - post_div_offset) << SUN4I_PLL2_POST_DIV_SHIFT; |
131 | writel(val, reg); | 126 | writel(val, reg); |
132 | 127 | ||
133 | of_property_read_string_index(node, "clock-output-names", | 128 | of_property_read_string_index(node, "clock-output-names", |
@@ -191,25 +186,17 @@ err_unmap: | |||
191 | iounmap(reg); | 186 | iounmap(reg); |
192 | } | 187 | } |
193 | 188 | ||
194 | static struct sun4i_pll2_data sun4i_a10_pll2_data = { | ||
195 | .pre_div_flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, | ||
196 | }; | ||
197 | |||
198 | static void __init sun4i_a10_pll2_setup(struct device_node *node) | 189 | static void __init sun4i_a10_pll2_setup(struct device_node *node) |
199 | { | 190 | { |
200 | sun4i_pll2_setup(node, &sun4i_a10_pll2_data); | 191 | sun4i_pll2_setup(node, 0); |
201 | } | 192 | } |
202 | 193 | ||
203 | CLK_OF_DECLARE(sun4i_a10_pll2, "allwinner,sun4i-a10-pll2-clk", | 194 | CLK_OF_DECLARE(sun4i_a10_pll2, "allwinner,sun4i-a10-pll2-clk", |
204 | sun4i_a10_pll2_setup); | 195 | sun4i_a10_pll2_setup); |
205 | 196 | ||
206 | static struct sun4i_pll2_data sun5i_a13_pll2_data = { | ||
207 | .post_div_offset = 1, | ||
208 | }; | ||
209 | |||
210 | static void __init sun5i_a13_pll2_setup(struct device_node *node) | 197 | static void __init sun5i_a13_pll2_setup(struct device_node *node) |
211 | { | 198 | { |
212 | sun4i_pll2_setup(node, &sun5i_a13_pll2_data); | 199 | sun4i_pll2_setup(node, 1); |
213 | } | 200 | } |
214 | 201 | ||
215 | CLK_OF_DECLARE(sun5i_a13_pll2, "allwinner,sun5i-a13-pll2-clk", | 202 | CLK_OF_DECLARE(sun5i_a13_pll2, "allwinner,sun5i-a13-pll2-clk", |
diff --git a/drivers/clk/ti/clk-816x.c b/drivers/clk/ti/clk-816x.c index 1dfad0c712cd..2a5d84fdddc5 100644 --- a/drivers/clk/ti/clk-816x.c +++ b/drivers/clk/ti/clk-816x.c | |||
@@ -20,6 +20,8 @@ static struct ti_dt_clk dm816x_clks[] = { | |||
20 | DT_CLK(NULL, "sys_clkin", "sys_clkin_ck"), | 20 | DT_CLK(NULL, "sys_clkin", "sys_clkin_ck"), |
21 | DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"), | 21 | DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"), |
22 | DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"), | 22 | DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"), |
23 | DT_CLK(NULL, "timer_32k_ck", "sysclk18_ck"), | ||
24 | DT_CLK(NULL, "timer_ext_ck", "tclkin_ck"), | ||
23 | DT_CLK(NULL, "mpu_ck", "mpu_ck"), | 25 | DT_CLK(NULL, "mpu_ck", "mpu_ck"), |
24 | DT_CLK(NULL, "timer1_fck", "timer1_fck"), | 26 | DT_CLK(NULL, "timer1_fck", "timer1_fck"), |
25 | DT_CLK(NULL, "timer2_fck", "timer2_fck"), | 27 | DT_CLK(NULL, "timer2_fck", "timer2_fck"), |
diff --git a/drivers/clk/ti/clkt_dpll.c b/drivers/clk/ti/clkt_dpll.c index 9023ca9caf84..b5cc6f66ae5d 100644 --- a/drivers/clk/ti/clkt_dpll.c +++ b/drivers/clk/ti/clkt_dpll.c | |||
@@ -240,7 +240,7 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw) | |||
240 | */ | 240 | */ |
241 | unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) | 241 | unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) |
242 | { | 242 | { |
243 | long long dpll_clk; | 243 | u64 dpll_clk; |
244 | u32 dpll_mult, dpll_div, v; | 244 | u32 dpll_mult, dpll_div, v; |
245 | struct dpll_data *dd; | 245 | struct dpll_data *dd; |
246 | 246 | ||
@@ -262,7 +262,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) | |||
262 | dpll_div = v & dd->div1_mask; | 262 | dpll_div = v & dd->div1_mask; |
263 | dpll_div >>= __ffs(dd->div1_mask); | 263 | dpll_div >>= __ffs(dd->div1_mask); |
264 | 264 | ||
265 | dpll_clk = (long long)clk_get_rate(dd->clk_ref) * dpll_mult; | 265 | dpll_clk = (u64)clk_get_rate(dd->clk_ref) * dpll_mult; |
266 | do_div(dpll_clk, dpll_div + 1); | 266 | do_div(dpll_clk, dpll_div + 1); |
267 | 267 | ||
268 | return dpll_clk; | 268 | return dpll_clk; |
diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c index 5b1726829e6d..df2558350fc1 100644 --- a/drivers/clk/ti/divider.c +++ b/drivers/clk/ti/divider.c | |||
@@ -214,7 +214,6 @@ static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, | |||
214 | { | 214 | { |
215 | struct clk_divider *divider; | 215 | struct clk_divider *divider; |
216 | unsigned int div, value; | 216 | unsigned int div, value; |
217 | unsigned long flags = 0; | ||
218 | u32 val; | 217 | u32 val; |
219 | 218 | ||
220 | if (!hw || !rate) | 219 | if (!hw || !rate) |
@@ -228,9 +227,6 @@ static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, | |||
228 | if (value > div_mask(divider)) | 227 | if (value > div_mask(divider)) |
229 | value = div_mask(divider); | 228 | value = div_mask(divider); |
230 | 229 | ||
231 | if (divider->lock) | ||
232 | spin_lock_irqsave(divider->lock, flags); | ||
233 | |||
234 | if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { | 230 | if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { |
235 | val = div_mask(divider) << (divider->shift + 16); | 231 | val = div_mask(divider) << (divider->shift + 16); |
236 | } else { | 232 | } else { |
@@ -240,9 +236,6 @@ static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, | |||
240 | val |= value << divider->shift; | 236 | val |= value << divider->shift; |
241 | ti_clk_ll_ops->clk_writel(val, divider->reg); | 237 | ti_clk_ll_ops->clk_writel(val, divider->reg); |
242 | 238 | ||
243 | if (divider->lock) | ||
244 | spin_unlock_irqrestore(divider->lock, flags); | ||
245 | |||
246 | return 0; | 239 | return 0; |
247 | } | 240 | } |
248 | 241 | ||
@@ -256,8 +249,7 @@ static struct clk *_register_divider(struct device *dev, const char *name, | |||
256 | const char *parent_name, | 249 | const char *parent_name, |
257 | unsigned long flags, void __iomem *reg, | 250 | unsigned long flags, void __iomem *reg, |
258 | u8 shift, u8 width, u8 clk_divider_flags, | 251 | u8 shift, u8 width, u8 clk_divider_flags, |
259 | const struct clk_div_table *table, | 252 | const struct clk_div_table *table) |
260 | spinlock_t *lock) | ||
261 | { | 253 | { |
262 | struct clk_divider *div; | 254 | struct clk_divider *div; |
263 | struct clk *clk; | 255 | struct clk *clk; |
@@ -288,7 +280,6 @@ static struct clk *_register_divider(struct device *dev, const char *name, | |||
288 | div->shift = shift; | 280 | div->shift = shift; |
289 | div->width = width; | 281 | div->width = width; |
290 | div->flags = clk_divider_flags; | 282 | div->flags = clk_divider_flags; |
291 | div->lock = lock; | ||
292 | div->hw.init = &init; | 283 | div->hw.init = &init; |
293 | div->table = table; | 284 | div->table = table; |
294 | 285 | ||
@@ -421,7 +412,7 @@ struct clk *ti_clk_register_divider(struct ti_clk *setup) | |||
421 | 412 | ||
422 | clk = _register_divider(NULL, setup->name, div->parent, | 413 | clk = _register_divider(NULL, setup->name, div->parent, |
423 | flags, (void __iomem *)reg, div->bit_shift, | 414 | flags, (void __iomem *)reg, div->bit_shift, |
424 | width, div_flags, table, NULL); | 415 | width, div_flags, table); |
425 | 416 | ||
426 | if (IS_ERR(clk)) | 417 | if (IS_ERR(clk)) |
427 | kfree(table); | 418 | kfree(table); |
@@ -584,8 +575,7 @@ static void __init of_ti_divider_clk_setup(struct device_node *node) | |||
584 | goto cleanup; | 575 | goto cleanup; |
585 | 576 | ||
586 | clk = _register_divider(NULL, node->name, parent_name, flags, reg, | 577 | clk = _register_divider(NULL, node->name, parent_name, flags, reg, |
587 | shift, width, clk_divider_flags, table, | 578 | shift, width, clk_divider_flags, table); |
588 | NULL); | ||
589 | 579 | ||
590 | if (!IS_ERR(clk)) { | 580 | if (!IS_ERR(clk)) { |
591 | of_clk_add_provider(node, of_clk_src_simple_get, clk); | 581 | of_clk_add_provider(node, of_clk_src_simple_get, clk); |
diff --git a/drivers/clk/ti/fapll.c b/drivers/clk/ti/fapll.c index f4b2e9888bdf..66a0d0ed8b55 100644 --- a/drivers/clk/ti/fapll.c +++ b/drivers/clk/ti/fapll.c | |||
@@ -168,7 +168,7 @@ static unsigned long ti_fapll_recalc_rate(struct clk_hw *hw, | |||
168 | { | 168 | { |
169 | struct fapll_data *fd = to_fapll(hw); | 169 | struct fapll_data *fd = to_fapll(hw); |
170 | u32 fapll_n, fapll_p, v; | 170 | u32 fapll_n, fapll_p, v; |
171 | long long rate; | 171 | u64 rate; |
172 | 172 | ||
173 | if (ti_fapll_clock_is_bypass(fd)) | 173 | if (ti_fapll_clock_is_bypass(fd)) |
174 | return parent_rate; | 174 | return parent_rate; |
@@ -314,7 +314,7 @@ static unsigned long ti_fapll_synth_recalc_rate(struct clk_hw *hw, | |||
314 | { | 314 | { |
315 | struct fapll_synth *synth = to_synth(hw); | 315 | struct fapll_synth *synth = to_synth(hw); |
316 | u32 synth_div_m; | 316 | u32 synth_div_m; |
317 | long long rate; | 317 | u64 rate; |
318 | 318 | ||
319 | /* The audio_pll_clk1 is hardwired to produce 32.768KiHz clock */ | 319 | /* The audio_pll_clk1 is hardwired to produce 32.768KiHz clock */ |
320 | if (!synth->div) | 320 | if (!synth->div) |
diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c index 69f08a1d047d..dab9ba88b9d6 100644 --- a/drivers/clk/ti/mux.c +++ b/drivers/clk/ti/mux.c | |||
@@ -69,7 +69,6 @@ static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index) | |||
69 | { | 69 | { |
70 | struct clk_mux *mux = to_clk_mux(hw); | 70 | struct clk_mux *mux = to_clk_mux(hw); |
71 | u32 val; | 71 | u32 val; |
72 | unsigned long flags = 0; | ||
73 | 72 | ||
74 | if (mux->table) { | 73 | if (mux->table) { |
75 | index = mux->table[index]; | 74 | index = mux->table[index]; |
@@ -81,9 +80,6 @@ static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index) | |||
81 | index++; | 80 | index++; |
82 | } | 81 | } |
83 | 82 | ||
84 | if (mux->lock) | ||
85 | spin_lock_irqsave(mux->lock, flags); | ||
86 | |||
87 | if (mux->flags & CLK_MUX_HIWORD_MASK) { | 83 | if (mux->flags & CLK_MUX_HIWORD_MASK) { |
88 | val = mux->mask << (mux->shift + 16); | 84 | val = mux->mask << (mux->shift + 16); |
89 | } else { | 85 | } else { |
@@ -93,9 +89,6 @@ static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index) | |||
93 | val |= index << mux->shift; | 89 | val |= index << mux->shift; |
94 | ti_clk_ll_ops->clk_writel(val, mux->reg); | 90 | ti_clk_ll_ops->clk_writel(val, mux->reg); |
95 | 91 | ||
96 | if (mux->lock) | ||
97 | spin_unlock_irqrestore(mux->lock, flags); | ||
98 | |||
99 | return 0; | 92 | return 0; |
100 | } | 93 | } |
101 | 94 | ||
@@ -109,7 +102,7 @@ static struct clk *_register_mux(struct device *dev, const char *name, | |||
109 | const char **parent_names, u8 num_parents, | 102 | const char **parent_names, u8 num_parents, |
110 | unsigned long flags, void __iomem *reg, | 103 | unsigned long flags, void __iomem *reg, |
111 | u8 shift, u32 mask, u8 clk_mux_flags, | 104 | u8 shift, u32 mask, u8 clk_mux_flags, |
112 | u32 *table, spinlock_t *lock) | 105 | u32 *table) |
113 | { | 106 | { |
114 | struct clk_mux *mux; | 107 | struct clk_mux *mux; |
115 | struct clk *clk; | 108 | struct clk *clk; |
@@ -133,7 +126,6 @@ static struct clk *_register_mux(struct device *dev, const char *name, | |||
133 | mux->shift = shift; | 126 | mux->shift = shift; |
134 | mux->mask = mask; | 127 | mux->mask = mask; |
135 | mux->flags = clk_mux_flags; | 128 | mux->flags = clk_mux_flags; |
136 | mux->lock = lock; | ||
137 | mux->table = table; | 129 | mux->table = table; |
138 | mux->hw.init = &init; | 130 | mux->hw.init = &init; |
139 | 131 | ||
@@ -175,7 +167,7 @@ struct clk *ti_clk_register_mux(struct ti_clk *setup) | |||
175 | 167 | ||
176 | return _register_mux(NULL, setup->name, mux->parents, mux->num_parents, | 168 | return _register_mux(NULL, setup->name, mux->parents, mux->num_parents, |
177 | flags, (void __iomem *)reg, mux->bit_shift, mask, | 169 | flags, (void __iomem *)reg, mux->bit_shift, mask, |
178 | mux_flags, NULL, NULL); | 170 | mux_flags, NULL); |
179 | } | 171 | } |
180 | 172 | ||
181 | /** | 173 | /** |
@@ -227,8 +219,7 @@ static void of_mux_clk_setup(struct device_node *node) | |||
227 | mask = (1 << fls(mask)) - 1; | 219 | mask = (1 << fls(mask)) - 1; |
228 | 220 | ||
229 | clk = _register_mux(NULL, node->name, parent_names, num_parents, | 221 | clk = _register_mux(NULL, node->name, parent_names, num_parents, |
230 | flags, reg, shift, mask, clk_mux_flags, NULL, | 222 | flags, reg, shift, mask, clk_mux_flags, NULL); |
231 | NULL); | ||
232 | 223 | ||
233 | if (!IS_ERR(clk)) | 224 | if (!IS_ERR(clk)) |
234 | of_clk_add_provider(node, of_clk_src_simple_get, clk); | 225 | of_clk_add_provider(node, of_clk_src_simple_get, clk); |