diff options
| -rw-r--r-- | drivers/gpu/drm/radeon/cik.c | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index de77c27d8106..55944163dfef 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c | |||
| @@ -3905,7 +3905,21 @@ void cik_fence_gfx_ring_emit(struct radeon_device *rdev, | |||
| 3905 | struct radeon_ring *ring = &rdev->ring[fence->ring]; | 3905 | struct radeon_ring *ring = &rdev->ring[fence->ring]; |
| 3906 | u64 addr = rdev->fence_drv[fence->ring].gpu_addr; | 3906 | u64 addr = rdev->fence_drv[fence->ring].gpu_addr; |
| 3907 | 3907 | ||
| 3908 | /* EVENT_WRITE_EOP - flush caches, send int */ | 3908 | /* Workaround for cache flush problems. First send a dummy EOP |
| 3909 | * event down the pipe with seq one below. | ||
| 3910 | */ | ||
| 3911 | radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); | ||
| 3912 | radeon_ring_write(ring, (EOP_TCL1_ACTION_EN | | ||
| 3913 | EOP_TC_ACTION_EN | | ||
| 3914 | EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | | ||
| 3915 | EVENT_INDEX(5))); | ||
| 3916 | radeon_ring_write(ring, addr & 0xfffffffc); | ||
| 3917 | radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | | ||
| 3918 | DATA_SEL(1) | INT_SEL(0)); | ||
| 3919 | radeon_ring_write(ring, fence->seq - 1); | ||
| 3920 | radeon_ring_write(ring, 0); | ||
| 3921 | |||
| 3922 | /* Then send the real EOP event down the pipe. */ | ||
| 3909 | radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); | 3923 | radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); |
| 3910 | radeon_ring_write(ring, (EOP_TCL1_ACTION_EN | | 3924 | radeon_ring_write(ring, (EOP_TCL1_ACTION_EN | |
| 3911 | EOP_TC_ACTION_EN | | 3925 | EOP_TC_ACTION_EN | |
