diff options
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 23 |
1 files changed, 9 insertions, 14 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index 920960089f27..e2b0b1646f99 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | |||
| @@ -472,19 +472,11 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev) | |||
| 472 | WREG32(mmVM_CONTEXT1_CNTL, | 472 | WREG32(mmVM_CONTEXT1_CNTL, |
| 473 | VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK | | 473 | VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK | |
| 474 | (1UL << VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT) | | 474 | (1UL << VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT) | |
| 475 | ((amdgpu_vm_block_size - 9) << VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT) | | 475 | ((amdgpu_vm_block_size - 9) << VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT)); |
| 476 | VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | | 476 | if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) |
| 477 | VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK | | 477 | gmc_v6_0_set_fault_enable_default(adev, false); |
| 478 | VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | | 478 | else |
| 479 | VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK | | 479 | gmc_v6_0_set_fault_enable_default(adev, true); |
| 480 | VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | | ||
| 481 | VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK | | ||
| 482 | VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | | ||
| 483 | VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK | | ||
| 484 | VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | | ||
| 485 | VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK | | ||
| 486 | VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | | ||
| 487 | VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK); | ||
| 488 | 480 | ||
| 489 | gmc_v6_0_gart_flush_gpu_tlb(adev, 0); | 481 | gmc_v6_0_gart_flush_gpu_tlb(adev, 0); |
| 490 | dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n", | 482 | dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n", |
| @@ -763,7 +755,10 @@ static int gmc_v6_0_late_init(void *handle) | |||
| 763 | { | 755 | { |
| 764 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | 756 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 765 | 757 | ||
| 766 | return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0); | 758 | if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) |
| 759 | return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0); | ||
| 760 | else | ||
| 761 | return 0; | ||
| 767 | } | 762 | } |
| 768 | 763 | ||
| 769 | static int gmc_v6_0_sw_init(void *handle) | 764 | static int gmc_v6_0_sw_init(void *handle) |
