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-rw-r--r--arch/x86/events/intel/core.c4
-rw-r--r--arch/x86/events/perf_event.h24
2 files changed, 27 insertions, 1 deletions
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 829e89cfcee2..cfd91a03304d 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -2958,6 +2958,10 @@ static unsigned long intel_pmu_free_running_flags(struct perf_event *event)
2958 2958
2959 if (event->attr.use_clockid) 2959 if (event->attr.use_clockid)
2960 flags &= ~PERF_SAMPLE_TIME; 2960 flags &= ~PERF_SAMPLE_TIME;
2961 if (!event->attr.exclude_kernel)
2962 flags &= ~PERF_SAMPLE_REGS_USER;
2963 if (event->attr.sample_regs_user & ~PEBS_REGS)
2964 flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR);
2961 return flags; 2965 return flags;
2962} 2966}
2963 2967
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 4196f81ec0e1..f7aaadf9331f 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -85,13 +85,15 @@ struct amd_nb {
85 * Flags PEBS can handle without an PMI. 85 * Flags PEBS can handle without an PMI.
86 * 86 *
87 * TID can only be handled by flushing at context switch. 87 * TID can only be handled by flushing at context switch.
88 * REGS_USER can be handled for events limited to ring 3.
88 * 89 *
89 */ 90 */
90#define PEBS_FREERUNNING_FLAGS \ 91#define PEBS_FREERUNNING_FLAGS \
91 (PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \ 92 (PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \
92 PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \ 93 PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \
93 PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \ 94 PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \
94 PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR) 95 PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR | \
96 PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER)
95 97
96/* 98/*
97 * A debug store configuration. 99 * A debug store configuration.
@@ -110,6 +112,26 @@ struct debug_store {
110 u64 pebs_event_reset[MAX_PEBS_EVENTS]; 112 u64 pebs_event_reset[MAX_PEBS_EVENTS];
111}; 113};
112 114
115#define PEBS_REGS \
116 (PERF_REG_X86_AX | \
117 PERF_REG_X86_BX | \
118 PERF_REG_X86_CX | \
119 PERF_REG_X86_DX | \
120 PERF_REG_X86_DI | \
121 PERF_REG_X86_SI | \
122 PERF_REG_X86_SP | \
123 PERF_REG_X86_BP | \
124 PERF_REG_X86_IP | \
125 PERF_REG_X86_FLAGS | \
126 PERF_REG_X86_R8 | \
127 PERF_REG_X86_R9 | \
128 PERF_REG_X86_R10 | \
129 PERF_REG_X86_R11 | \
130 PERF_REG_X86_R12 | \
131 PERF_REG_X86_R13 | \
132 PERF_REG_X86_R14 | \
133 PERF_REG_X86_R15)
134
113/* 135/*
114 * Per register state. 136 * Per register state.
115 */ 137 */