diff options
| -rw-r--r-- | drivers/clk/qcom/mmcc-msm8996.c | 32 |
1 files changed, 0 insertions, 32 deletions
diff --git a/drivers/clk/qcom/mmcc-msm8996.c b/drivers/clk/qcom/mmcc-msm8996.c index 6df7ff36b416..847dd9dadeca 100644 --- a/drivers/clk/qcom/mmcc-msm8996.c +++ b/drivers/clk/qcom/mmcc-msm8996.c | |||
| @@ -1279,21 +1279,6 @@ static struct clk_branch mmss_misc_cxo_clk = { | |||
| 1279 | }, | 1279 | }, |
| 1280 | }; | 1280 | }; |
| 1281 | 1281 | ||
| 1282 | static struct clk_branch mmss_mmagic_axi_clk = { | ||
| 1283 | .halt_reg = 0x506c, | ||
| 1284 | .clkr = { | ||
| 1285 | .enable_reg = 0x506c, | ||
| 1286 | .enable_mask = BIT(0), | ||
| 1287 | .hw.init = &(struct clk_init_data){ | ||
| 1288 | .name = "mmss_mmagic_axi_clk", | ||
| 1289 | .parent_names = (const char *[]){ "axi_clk_src" }, | ||
| 1290 | .num_parents = 1, | ||
| 1291 | .flags = CLK_SET_RATE_PARENT, | ||
| 1292 | .ops = &clk_branch2_ops, | ||
| 1293 | }, | ||
| 1294 | }, | ||
| 1295 | }; | ||
| 1296 | |||
| 1297 | static struct clk_branch mmss_mmagic_maxi_clk = { | 1282 | static struct clk_branch mmss_mmagic_maxi_clk = { |
| 1298 | .halt_reg = 0x5074, | 1283 | .halt_reg = 0x5074, |
| 1299 | .clkr = { | 1284 | .clkr = { |
| @@ -1579,21 +1564,6 @@ static struct clk_branch smmu_video_axi_clk = { | |||
| 1579 | }, | 1564 | }, |
| 1580 | }; | 1565 | }; |
| 1581 | 1566 | ||
| 1582 | static struct clk_branch mmagic_bimc_axi_clk = { | ||
| 1583 | .halt_reg = 0x5294, | ||
| 1584 | .clkr = { | ||
| 1585 | .enable_reg = 0x5294, | ||
| 1586 | .enable_mask = BIT(0), | ||
| 1587 | .hw.init = &(struct clk_init_data){ | ||
| 1588 | .name = "mmagic_bimc_axi_clk", | ||
| 1589 | .parent_names = (const char *[]){ "axi_clk_src" }, | ||
| 1590 | .num_parents = 1, | ||
| 1591 | .flags = CLK_SET_RATE_PARENT, | ||
| 1592 | .ops = &clk_branch2_ops, | ||
| 1593 | }, | ||
| 1594 | }, | ||
| 1595 | }; | ||
| 1596 | |||
| 1597 | static struct clk_branch mmagic_bimc_noc_cfg_ahb_clk = { | 1567 | static struct clk_branch mmagic_bimc_noc_cfg_ahb_clk = { |
| 1598 | .halt_reg = 0x5298, | 1568 | .halt_reg = 0x5298, |
| 1599 | .clkr = { | 1569 | .clkr = { |
| @@ -3121,7 +3091,6 @@ static struct clk_regmap *mmcc_msm8996_clocks[] = { | |||
| 3121 | [MMSS_MMAGIC_CFG_AHB_CLK] = &mmss_mmagic_cfg_ahb_clk.clkr, | 3091 | [MMSS_MMAGIC_CFG_AHB_CLK] = &mmss_mmagic_cfg_ahb_clk.clkr, |
| 3122 | [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr, | 3092 | [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr, |
| 3123 | [MMSS_MISC_CXO_CLK] = &mmss_misc_cxo_clk.clkr, | 3093 | [MMSS_MISC_CXO_CLK] = &mmss_misc_cxo_clk.clkr, |
| 3124 | [MMSS_MMAGIC_AXI_CLK] = &mmss_mmagic_axi_clk.clkr, | ||
| 3125 | [MMSS_MMAGIC_MAXI_CLK] = &mmss_mmagic_maxi_clk.clkr, | 3094 | [MMSS_MMAGIC_MAXI_CLK] = &mmss_mmagic_maxi_clk.clkr, |
| 3126 | [MMAGIC_CAMSS_AXI_CLK] = &mmagic_camss_axi_clk.clkr, | 3095 | [MMAGIC_CAMSS_AXI_CLK] = &mmagic_camss_axi_clk.clkr, |
| 3127 | [MMAGIC_CAMSS_NOC_CFG_AHB_CLK] = &mmagic_camss_noc_cfg_ahb_clk.clkr, | 3096 | [MMAGIC_CAMSS_NOC_CFG_AHB_CLK] = &mmagic_camss_noc_cfg_ahb_clk.clkr, |
| @@ -3141,7 +3110,6 @@ static struct clk_regmap *mmcc_msm8996_clocks[] = { | |||
| 3141 | [MMAGIC_VIDEO_NOC_CFG_AHB_CLK] = &mmagic_video_noc_cfg_ahb_clk.clkr, | 3110 | [MMAGIC_VIDEO_NOC_CFG_AHB_CLK] = &mmagic_video_noc_cfg_ahb_clk.clkr, |
| 3142 | [SMMU_VIDEO_AHB_CLK] = &smmu_video_ahb_clk.clkr, | 3111 | [SMMU_VIDEO_AHB_CLK] = &smmu_video_ahb_clk.clkr, |
| 3143 | [SMMU_VIDEO_AXI_CLK] = &smmu_video_axi_clk.clkr, | 3112 | [SMMU_VIDEO_AXI_CLK] = &smmu_video_axi_clk.clkr, |
| 3144 | [MMAGIC_BIMC_AXI_CLK] = &mmagic_bimc_axi_clk.clkr, | ||
| 3145 | [MMAGIC_BIMC_NOC_CFG_AHB_CLK] = &mmagic_bimc_noc_cfg_ahb_clk.clkr, | 3113 | [MMAGIC_BIMC_NOC_CFG_AHB_CLK] = &mmagic_bimc_noc_cfg_ahb_clk.clkr, |
| 3146 | [GPU_GX_GFX3D_CLK] = &gpu_gx_gfx3d_clk.clkr, | 3114 | [GPU_GX_GFX3D_CLK] = &gpu_gx_gfx3d_clk.clkr, |
| 3147 | [GPU_GX_RBBMTIMER_CLK] = &gpu_gx_rbbmtimer_clk.clkr, | 3115 | [GPU_GX_RBBMTIMER_CLK] = &gpu_gx_rbbmtimer_clk.clkr, |
