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-rw-r--r--arch/microblaze/include/asm/page.h3
-rw-r--r--arch/microblaze/kernel/hw_exception_handler.S53
2 files changed, 32 insertions, 24 deletions
diff --git a/arch/microblaze/include/asm/page.h b/arch/microblaze/include/asm/page.h
index 287c5485d286..dd9ea9d6b765 100644
--- a/arch/microblaze/include/asm/page.h
+++ b/arch/microblaze/include/asm/page.h
@@ -37,6 +37,8 @@
37 37
38#define LOAD_OFFSET ASM_CONST((CONFIG_KERNEL_START-CONFIG_KERNEL_BASE_ADDR)) 38#define LOAD_OFFSET ASM_CONST((CONFIG_KERNEL_START-CONFIG_KERNEL_BASE_ADDR))
39 39
40#define PTE_SHIFT (PAGE_SHIFT - 2) /* 1024 ptes per page */
41
40#ifndef __ASSEMBLY__ 42#ifndef __ASSEMBLY__
41 43
42/* MS be sure that SLAB allocates aligned objects */ 44/* MS be sure that SLAB allocates aligned objects */
@@ -71,7 +73,6 @@ extern unsigned int __page_offset;
71 * The basic type of a PTE - 32 bit physical addressing. 73 * The basic type of a PTE - 32 bit physical addressing.
72 */ 74 */
73typedef unsigned long pte_basic_t; 75typedef unsigned long pte_basic_t;
74#define PTE_SHIFT (PAGE_SHIFT - 2) /* 1024 ptes per page */
75#define PTE_FMT "%.8lx" 76#define PTE_FMT "%.8lx"
76 77
77#endif /* CONFIG_MMU */ 78#endif /* CONFIG_MMU */
diff --git a/arch/microblaze/kernel/hw_exception_handler.S b/arch/microblaze/kernel/hw_exception_handler.S
index aa510f450ac6..76a069dc13cb 100644
--- a/arch/microblaze/kernel/hw_exception_handler.S
+++ b/arch/microblaze/kernel/hw_exception_handler.S
@@ -602,18 +602,19 @@ ex_handler_done:
602 lwi r4, r4, TASK_THREAD+PGDIR 602 lwi r4, r4, TASK_THREAD+PGDIR
603 ex4: 603 ex4:
604 tophys(r4,r4) 604 tophys(r4,r4)
605 BSRLI(r5,r3,20) /* Create L1 (pgdir/pmd) address */ 605 /* Create L1 (pgdir/pmd) address */
606 andi r5, r5, 0xffc 606 BSRLI(r5,r3, PGDIR_SHIFT - 2)
607 andi r5, r5, PAGE_SIZE - 4
607/* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */ 608/* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
608 or r4, r4, r5 609 or r4, r4, r5
609 lwi r4, r4, 0 /* Get L1 entry */ 610 lwi r4, r4, 0 /* Get L1 entry */
610 andi r5, r4, 0xfffff000 /* Extract L2 (pte) base address */ 611 andi r5, r4, PAGE_MASK /* Extract L2 (pte) base address */
611 beqi r5, ex2 /* Bail if no table */ 612 beqi r5, ex2 /* Bail if no table */
612 613
613 tophys(r5,r5) 614 tophys(r5,r5)
614 BSRLI(r6,r3,10) /* Compute PTE address */ 615 BSRLI(r6,r3,PTE_SHIFT) /* Compute PTE address */
615 andi r6, r6, 0xffc 616 andi r6, r6, PAGE_SIZE - 4
616 andi r5, r5, 0xfffff003 617 andi r5, r5, PAGE_MASK + 0x3
617 or r5, r5, r6 618 or r5, r5, r6
618 lwi r4, r5, 0 /* Get Linux PTE */ 619 lwi r4, r5, 0 /* Get Linux PTE */
619 620
@@ -632,7 +633,9 @@ ex_handler_done:
632 * Many of these bits are software only. Bits we don't set 633 * Many of these bits are software only. Bits we don't set
633 * here we (properly should) assume have the appropriate value. 634 * here we (properly should) assume have the appropriate value.
634 */ 635 */
635 andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */ 636/* Ignore memory coherent, just LSB on ZSEL is used + EX/WR */
637 andi r4, r4, PAGE_MASK | TLB_EX | TLB_WR | \
638 TLB_ZSEL(1) | TLB_ATTR_MASK
636 ori r4, r4, _PAGE_HWEXEC /* make it executable */ 639 ori r4, r4, _PAGE_HWEXEC /* make it executable */
637 640
638 /* find the TLB index that caused the fault. It has to be here*/ 641 /* find the TLB index that caused the fault. It has to be here*/
@@ -701,18 +704,19 @@ ex_handler_done:
701 lwi r4, r4, TASK_THREAD+PGDIR 704 lwi r4, r4, TASK_THREAD+PGDIR
702 ex6: 705 ex6:
703 tophys(r4,r4) 706 tophys(r4,r4)
704 BSRLI(r5,r3,20) /* Create L1 (pgdir/pmd) address */ 707 /* Create L1 (pgdir/pmd) address */
705 andi r5, r5, 0xffc 708 BSRLI(r5,r3, PGDIR_SHIFT - 2)
709 andi r5, r5, PAGE_SIZE - 4
706/* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */ 710/* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
707 or r4, r4, r5 711 or r4, r4, r5
708 lwi r4, r4, 0 /* Get L1 entry */ 712 lwi r4, r4, 0 /* Get L1 entry */
709 andi r5, r4, 0xfffff000 /* Extract L2 (pte) base address */ 713 andi r5, r4, PAGE_MASK /* Extract L2 (pte) base address */
710 beqi r5, ex7 /* Bail if no table */ 714 beqi r5, ex7 /* Bail if no table */
711 715
712 tophys(r5,r5) 716 tophys(r5,r5)
713 BSRLI(r6,r3,10) /* Compute PTE address */ 717 BSRLI(r6,r3,PTE_SHIFT) /* Compute PTE address */
714 andi r6, r6, 0xffc 718 andi r6, r6, PAGE_SIZE - 4
715 andi r5, r5, 0xfffff003 719 andi r5, r5, PAGE_MASK + 0x3
716 or r5, r5, r6 720 or r5, r5, r6
717 lwi r4, r5, 0 /* Get Linux PTE */ 721 lwi r4, r5, 0 /* Get Linux PTE */
718 722
@@ -731,7 +735,8 @@ ex_handler_done:
731 * here we (properly should) assume have the appropriate value. 735 * here we (properly should) assume have the appropriate value.
732 */ 736 */
733 brid finish_tlb_load 737 brid finish_tlb_load
734 andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */ 738 andi r4, r4, PAGE_MASK | TLB_EX | TLB_WR | \
739 TLB_ZSEL(1) | TLB_ATTR_MASK
735 ex7: 740 ex7:
736 /* The bailout. Restore registers to pre-exception conditions 741 /* The bailout. Restore registers to pre-exception conditions
737 * and call the heavyweights to help us out. 742 * and call the heavyweights to help us out.
@@ -771,18 +776,19 @@ ex_handler_done:
771 lwi r4, r4, TASK_THREAD+PGDIR 776 lwi r4, r4, TASK_THREAD+PGDIR
772 ex9: 777 ex9:
773 tophys(r4,r4) 778 tophys(r4,r4)
774 BSRLI(r5,r3,20) /* Create L1 (pgdir/pmd) address */ 779 /* Create L1 (pgdir/pmd) address */
775 andi r5, r5, 0xffc 780 BSRLI(r5,r3, PGDIR_SHIFT - 2)
781 andi r5, r5, PAGE_SIZE - 4
776/* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */ 782/* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
777 or r4, r4, r5 783 or r4, r4, r5
778 lwi r4, r4, 0 /* Get L1 entry */ 784 lwi r4, r4, 0 /* Get L1 entry */
779 andi r5, r4, 0xfffff000 /* Extract L2 (pte) base address */ 785 andi r5, r4, PAGE_MASK /* Extract L2 (pte) base address */
780 beqi r5, ex10 /* Bail if no table */ 786 beqi r5, ex10 /* Bail if no table */
781 787
782 tophys(r5,r5) 788 tophys(r5,r5)
783 BSRLI(r6,r3,10) /* Compute PTE address */ 789 BSRLI(r6,r3,PTE_SHIFT) /* Compute PTE address */
784 andi r6, r6, 0xffc 790 andi r6, r6, PAGE_SIZE - 4
785 andi r5, r5, 0xfffff003 791 andi r5, r5, PAGE_MASK + 0x3
786 or r5, r5, r6 792 or r5, r5, r6
787 lwi r4, r5, 0 /* Get Linux PTE */ 793 lwi r4, r5, 0 /* Get Linux PTE */
788 794
@@ -801,7 +807,8 @@ ex_handler_done:
801 * here we (properly should) assume have the appropriate value. 807 * here we (properly should) assume have the appropriate value.
802 */ 808 */
803 brid finish_tlb_load 809 brid finish_tlb_load
804 andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */ 810 andi r4, r4, PAGE_MASK | TLB_EX | TLB_WR | \
811 TLB_ZSEL(1) | TLB_ATTR_MASK
805 ex10: 812 ex10:
806 /* The bailout. Restore registers to pre-exception conditions 813 /* The bailout. Restore registers to pre-exception conditions
807 * and call the heavyweights to help us out. 814 * and call the heavyweights to help us out.
@@ -854,8 +861,8 @@ ex_handler_done:
854 * set of bits. These are size, valid, E, U0, and ensure 861 * set of bits. These are size, valid, E, U0, and ensure
855 * bits 20 and 21 are zero. 862 * bits 20 and 21 are zero.
856 */ 863 */
857 andi r3, r3, 0xfffff000 864 andi r3, r3, PAGE_MASK
858 ori r3, r3, 0x0c0 865 ori r3, r3, TLB_VALID | TLB_PAGESZ(PAGESZ_4K)
859 mts rtlbhi, r3 /* Load TLB HI */ 866 mts rtlbhi, r3 /* Load TLB HI */
860 nop 867 nop
861 868
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-28 14:48:04 -0500