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-rw-r--r--arch/arm/boot/dts/imx25.dtsi1
-rw-r--r--arch/arm/boot/dts/imx27-apf27.dts1
-rw-r--r--arch/arm/boot/dts/imx27.dtsi1
-rw-r--r--arch/arm/boot/dts/imx50.dtsi4
-rw-r--r--arch/arm/boot/dts/imx51.dtsi4
-rw-r--r--arch/arm/boot/dts/imx53-m53evk.dts23
-rw-r--r--arch/arm/boot/dts/imx53-qsb-common.dtsi3
-rw-r--r--arch/arm/boot/dts/imx53-tx53-x03x.dts11
-rw-r--r--arch/arm/boot/dts/imx53.dtsi6
-rw-r--r--arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts48
-rw-r--r--arch/arm/boot/dts/imx6q-gw5400-a.dts3
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw52xx.dtsi3
-rw-r--r--arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi22
-rw-r--r--arch/arm/boot/dts/imx6qdl.dtsi13
-rw-r--r--arch/arm/boot/dts/imx6sl-evk.dts1
-rw-r--r--arch/arm/boot/dts/imx6sl.dtsi4
-rw-r--r--arch/arm/boot/dts/vf610-twr.dts2
-rw-r--r--arch/arm/boot/dts/vf610.dtsi4
-rw-r--r--arch/arm/mach-imx/clk-imx6q.c29
19 files changed, 123 insertions, 60 deletions
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index 32f760e24898..ea323f09dc78 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -56,6 +56,7 @@
56 56
57 osc { 57 osc {
58 compatible = "fsl,imx-osc", "fixed-clock"; 58 compatible = "fsl,imx-osc", "fixed-clock";
59 #clock-cells = <0>;
59 clock-frequency = <24000000>; 60 clock-frequency = <24000000>;
60 }; 61 };
61 }; 62 };
diff --git a/arch/arm/boot/dts/imx27-apf27.dts b/arch/arm/boot/dts/imx27-apf27.dts
index 09f57b39e3ef..73aae4f5e539 100644
--- a/arch/arm/boot/dts/imx27-apf27.dts
+++ b/arch/arm/boot/dts/imx27-apf27.dts
@@ -29,6 +29,7 @@
29 29
30 osc26m { 30 osc26m {
31 compatible = "fsl,imx-osc26m", "fixed-clock"; 31 compatible = "fsl,imx-osc26m", "fixed-clock";
32 #clock-cells = <0>;
32 clock-frequency = <0>; 33 clock-frequency = <0>;
33 }; 34 };
34 }; 35 };
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 6279e0b4f768..137e010eab35 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -48,6 +48,7 @@
48 48
49 osc26m { 49 osc26m {
50 compatible = "fsl,imx-osc26m", "fixed-clock"; 50 compatible = "fsl,imx-osc26m", "fixed-clock";
51 #clock-cells = <0>;
51 clock-frequency = <26000000>; 52 clock-frequency = <26000000>;
52 }; 53 };
53 }; 54 };
diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi
index 0c75fe3deb35..9c89d1ca97c2 100644
--- a/arch/arm/boot/dts/imx50.dtsi
+++ b/arch/arm/boot/dts/imx50.dtsi
@@ -53,21 +53,25 @@
53 53
54 ckil { 54 ckil {
55 compatible = "fsl,imx-ckil", "fixed-clock"; 55 compatible = "fsl,imx-ckil", "fixed-clock";
56 #clock-cells = <0>;
56 clock-frequency = <32768>; 57 clock-frequency = <32768>;
57 }; 58 };
58 59
59 ckih1 { 60 ckih1 {
60 compatible = "fsl,imx-ckih1", "fixed-clock"; 61 compatible = "fsl,imx-ckih1", "fixed-clock";
62 #clock-cells = <0>;
61 clock-frequency = <22579200>; 63 clock-frequency = <22579200>;
62 }; 64 };
63 65
64 ckih2 { 66 ckih2 {
65 compatible = "fsl,imx-ckih2", "fixed-clock"; 67 compatible = "fsl,imx-ckih2", "fixed-clock";
68 #clock-cells = <0>;
66 clock-frequency = <0>; 69 clock-frequency = <0>;
67 }; 70 };
68 71
69 osc { 72 osc {
70 compatible = "fsl,imx-osc", "fixed-clock"; 73 compatible = "fsl,imx-osc", "fixed-clock";
74 #clock-cells = <0>;
71 clock-frequency = <24000000>; 75 clock-frequency = <24000000>;
72 }; 76 };
73 }; 77 };
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 5f8216d08f6b..150bb4e2f744 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -50,21 +50,25 @@
50 50
51 ckil { 51 ckil {
52 compatible = "fsl,imx-ckil", "fixed-clock"; 52 compatible = "fsl,imx-ckil", "fixed-clock";
53 #clock-cells = <0>;
53 clock-frequency = <32768>; 54 clock-frequency = <32768>;
54 }; 55 };
55 56
56 ckih1 { 57 ckih1 {
57 compatible = "fsl,imx-ckih1", "fixed-clock"; 58 compatible = "fsl,imx-ckih1", "fixed-clock";
59 #clock-cells = <0>;
58 clock-frequency = <0>; 60 clock-frequency = <0>;
59 }; 61 };
60 62
61 ckih2 { 63 ckih2 {
62 compatible = "fsl,imx-ckih2", "fixed-clock"; 64 compatible = "fsl,imx-ckih2", "fixed-clock";
65 #clock-cells = <0>;
63 clock-frequency = <0>; 66 clock-frequency = <0>;
64 }; 67 };
65 68
66 osc { 69 osc {
67 compatible = "fsl,imx-osc", "fixed-clock"; 70 compatible = "fsl,imx-osc", "fixed-clock";
71 #clock-cells = <0>;
68 clock-frequency = <24000000>; 72 clock-frequency = <24000000>;
69 }; 73 };
70 }; 74 };
diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/imx53-m53evk.dts
index f6d3ac3e5587..d5d146a8b149 100644
--- a/arch/arm/boot/dts/imx53-m53evk.dts
+++ b/arch/arm/boot/dts/imx53-m53evk.dts
@@ -17,7 +17,8 @@
17 compatible = "denx,imx53-m53evk", "fsl,imx53"; 17 compatible = "denx,imx53-m53evk", "fsl,imx53";
18 18
19 memory { 19 memory {
20 reg = <0x70000000 0x20000000>; 20 reg = <0x70000000 0x20000000>,
21 <0xb0000000 0x20000000>;
21 }; 22 };
22 23
23 soc { 24 soc {
@@ -193,17 +194,17 @@
193 irq-trigger = <0x1>; 194 irq-trigger = <0x1>;
194 195
195 stmpe_touchscreen { 196 stmpe_touchscreen {
196 compatible = "stmpe,ts"; 197 compatible = "st,stmpe-ts";
197 reg = <0>; 198 reg = <0>;
198 ts,sample-time = <4>; 199 st,sample-time = <4>;
199 ts,mod-12b = <1>; 200 st,mod-12b = <1>;
200 ts,ref-sel = <0>; 201 st,ref-sel = <0>;
201 ts,adc-freq = <1>; 202 st,adc-freq = <1>;
202 ts,ave-ctrl = <3>; 203 st,ave-ctrl = <3>;
203 ts,touch-det-delay = <3>; 204 st,touch-det-delay = <3>;
204 ts,settling = <4>; 205 st,settling = <4>;
205 ts,fraction-z = <7>; 206 st,fraction-z = <7>;
206 ts,i-drive = <1>; 207 st,i-drive = <1>;
207 }; 208 };
208 }; 209 };
209 210
diff --git a/arch/arm/boot/dts/imx53-qsb-common.dtsi b/arch/arm/boot/dts/imx53-qsb-common.dtsi
index 3f825a6813da..ede04fa4161f 100644
--- a/arch/arm/boot/dts/imx53-qsb-common.dtsi
+++ b/arch/arm/boot/dts/imx53-qsb-common.dtsi
@@ -14,7 +14,8 @@
14 14
15/ { 15/ {
16 memory { 16 memory {
17 reg = <0x70000000 0x40000000>; 17 reg = <0x70000000 0x20000000>,
18 <0xb0000000 0x20000000>;
18 }; 19 };
19 20
20 display0: display@di0 { 21 display0: display@di0 {
diff --git a/arch/arm/boot/dts/imx53-tx53-x03x.dts b/arch/arm/boot/dts/imx53-tx53-x03x.dts
index 0217dde3b36b..3b73e81dc3f0 100644
--- a/arch/arm/boot/dts/imx53-tx53-x03x.dts
+++ b/arch/arm/boot/dts/imx53-tx53-x03x.dts
@@ -25,12 +25,17 @@
25 soc { 25 soc {
26 display: display@di0 { 26 display: display@di0 {
27 compatible = "fsl,imx-parallel-display"; 27 compatible = "fsl,imx-parallel-display";
28 crtcs = <&ipu 0>;
29 interface-pix-fmt = "rgb24"; 28 interface-pix-fmt = "rgb24";
30 pinctrl-names = "default"; 29 pinctrl-names = "default";
31 pinctrl-0 = <&pinctrl_rgb24_vga1>; 30 pinctrl-0 = <&pinctrl_rgb24_vga1>;
32 status = "okay"; 31 status = "okay";
33 32
33 port {
34 display0_in: endpoint {
35 remote-endpoint = <&ipu_di0_disp0>;
36 };
37 };
38
34 display-timings { 39 display-timings {
35 VGA { 40 VGA {
36 clock-frequency = <25200000>; 41 clock-frequency = <25200000>;
@@ -293,6 +298,10 @@
293 }; 298 };
294}; 299};
295 300
301&ipu_di0_disp0 {
302 remote-endpoint = <&display0_in>;
303};
304
296&kpp { 305&kpp {
297 pinctrl-names = "default"; 306 pinctrl-names = "default";
298 pinctrl-0 = <&pinctrl_kpp>; 307 pinctrl-0 = <&pinctrl_kpp>;
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index b57ab57740f6..9c2bff2252d0 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -70,21 +70,25 @@
70 70
71 ckil { 71 ckil {
72 compatible = "fsl,imx-ckil", "fixed-clock"; 72 compatible = "fsl,imx-ckil", "fixed-clock";
73 #clock-cells = <0>;
73 clock-frequency = <32768>; 74 clock-frequency = <32768>;
74 }; 75 };
75 76
76 ckih1 { 77 ckih1 {
77 compatible = "fsl,imx-ckih1", "fixed-clock"; 78 compatible = "fsl,imx-ckih1", "fixed-clock";
79 #clock-cells = <0>;
78 clock-frequency = <22579200>; 80 clock-frequency = <22579200>;
79 }; 81 };
80 82
81 ckih2 { 83 ckih2 {
82 compatible = "fsl,imx-ckih2", "fixed-clock"; 84 compatible = "fsl,imx-ckih2", "fixed-clock";
85 #clock-cells = <0>;
83 clock-frequency = <0>; 86 clock-frequency = <0>;
84 }; 87 };
85 88
86 osc { 89 osc {
87 compatible = "fsl,imx-osc", "fixed-clock"; 90 compatible = "fsl,imx-osc", "fixed-clock";
91 #clock-cells = <0>;
88 clock-frequency = <24000000>; 92 clock-frequency = <24000000>;
89 }; 93 };
90 }; 94 };
@@ -430,7 +434,7 @@
430 434
431 port { 435 port {
432 lvds1_in: endpoint { 436 lvds1_in: endpoint {
433 remote-endpoint = <&ipu_di0_lvds0>; 437 remote-endpoint = <&ipu_di1_lvds1>;
434 }; 438 };
435 }; 439 };
436 }; 440 };
diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
index a63bbb3d46bb..e4ae38fd0269 100644
--- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
+++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
@@ -19,7 +19,10 @@
19 compatible = "dmo,imx6q-edmqmx6", "fsl,imx6q"; 19 compatible = "dmo,imx6q-edmqmx6", "fsl,imx6q";
20 20
21 aliases { 21 aliases {
22 gpio7 = &stmpe_gpio; 22 gpio7 = &stmpe_gpio1;
23 gpio8 = &stmpe_gpio2;
24 stmpe-i2c0 = &stmpe1;
25 stmpe-i2c1 = &stmpe2;
23 }; 26 };
24 27
25 memory { 28 memory {
@@ -40,13 +43,15 @@
40 regulator-always-on; 43 regulator-always-on;
41 }; 44 };
42 45
43 reg_usb_otg_vbus: regulator@1 { 46 reg_usb_otg_switch: regulator@1 {
44 compatible = "regulator-fixed"; 47 compatible = "regulator-fixed";
45 reg = <1>; 48 reg = <1>;
46 regulator-name = "usb_otg_vbus"; 49 regulator-name = "usb_otg_switch";
47 regulator-min-microvolt = <5000000>; 50 regulator-min-microvolt = <5000000>;
48 regulator-max-microvolt = <5000000>; 51 regulator-max-microvolt = <5000000>;
49 gpio = <&gpio7 12 0>; 52 gpio = <&gpio7 12 0>;
53 regulator-boot-on;
54 regulator-always-on;
50 }; 55 };
51 56
52 reg_usb_host1: regulator@2 { 57 reg_usb_host1: regulator@2 {
@@ -65,23 +70,23 @@
65 70
66 led-blue { 71 led-blue {
67 label = "blue"; 72 label = "blue";
68 gpios = <&stmpe_gpio 8 GPIO_ACTIVE_HIGH>; 73 gpios = <&stmpe_gpio1 8 GPIO_ACTIVE_HIGH>;
69 linux,default-trigger = "heartbeat"; 74 linux,default-trigger = "heartbeat";
70 }; 75 };
71 76
72 led-green { 77 led-green {
73 label = "green"; 78 label = "green";
74 gpios = <&stmpe_gpio 9 GPIO_ACTIVE_HIGH>; 79 gpios = <&stmpe_gpio1 9 GPIO_ACTIVE_HIGH>;
75 }; 80 };
76 81
77 led-pink { 82 led-pink {
78 label = "pink"; 83 label = "pink";
79 gpios = <&stmpe_gpio 10 GPIO_ACTIVE_HIGH>; 84 gpios = <&stmpe_gpio1 10 GPIO_ACTIVE_HIGH>;
80 }; 85 };
81 86
82 led-red { 87 led-red {
83 label = "red"; 88 label = "red";
84 gpios = <&stmpe_gpio 11 GPIO_ACTIVE_HIGH>; 89 gpios = <&stmpe_gpio1 11 GPIO_ACTIVE_HIGH>;
85 }; 90 };
86 }; 91 };
87}; 92};
@@ -99,7 +104,8 @@
99 clock-frequency = <100000>; 104 clock-frequency = <100000>;
100 pinctrl-names = "default"; 105 pinctrl-names = "default";
101 pinctrl-0 = <&pinctrl_i2c2 106 pinctrl-0 = <&pinctrl_i2c2
102 &pinctrl_stmpe>; 107 &pinctrl_stmpe1
108 &pinctrl_stmpe2>;
103 status = "okay"; 109 status = "okay";
104 110
105 pmic: pfuze100@08 { 111 pmic: pfuze100@08 {
@@ -205,13 +211,25 @@
205 }; 211 };
206 }; 212 };
207 213
208 stmpe: stmpe1601@40 { 214 stmpe1: stmpe1601@40 {
209 compatible = "st,stmpe1601"; 215 compatible = "st,stmpe1601";
210 reg = <0x40>; 216 reg = <0x40>;
211 interrupts = <30 0>; 217 interrupts = <30 0>;
212 interrupt-parent = <&gpio3>; 218 interrupt-parent = <&gpio3>;
213 219
214 stmpe_gpio: stmpe_gpio { 220 stmpe_gpio1: stmpe_gpio {
221 #gpio-cells = <2>;
222 compatible = "st,stmpe-gpio";
223 };
224 };
225
226 stmpe2: stmpe1601@44 {
227 compatible = "st,stmpe1601";
228 reg = <0x44>;
229 interrupts = <2 0>;
230 interrupt-parent = <&gpio5>;
231
232 stmpe_gpio2: stmpe_gpio {
215 #gpio-cells = <2>; 233 #gpio-cells = <2>;
216 compatible = "st,stmpe-gpio"; 234 compatible = "st,stmpe-gpio";
217 }; 235 };
@@ -273,10 +291,14 @@
273 >; 291 >;
274 }; 292 };
275 293
276 pinctrl_stmpe: stmpegrp { 294 pinctrl_stmpe1: stmpe1grp {
277 fsl,pins = <MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x80000000>; 295 fsl,pins = <MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x80000000>;
278 }; 296 };
279 297
298 pinctrl_stmpe2: stmpe2grp {
299 fsl,pins = <MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000>;
300 };
301
280 pinctrl_uart1: uart1grp { 302 pinctrl_uart1: uart1grp {
281 fsl,pins = < 303 fsl,pins = <
282 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 304 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
@@ -293,7 +315,7 @@
293 315
294 pinctrl_usbotg: usbotggrp { 316 pinctrl_usbotg: usbotggrp {
295 fsl,pins = < 317 fsl,pins = <
296 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 318 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
297 >; 319 >;
298 }; 320 };
299 321
@@ -344,11 +366,11 @@
344&usbh1 { 366&usbh1 {
345 vbus-supply = <&reg_usb_host1>; 367 vbus-supply = <&reg_usb_host1>;
346 disable-over-current; 368 disable-over-current;
369 dr_mode = "host";
347 status = "okay"; 370 status = "okay";
348}; 371};
349 372
350&usbotg { 373&usbotg {
351 vbus-supply = <&reg_usb_otg_vbus>;
352 pinctrl-names = "default"; 374 pinctrl-names = "default";
353 pinctrl-0 = <&pinctrl_usbotg>; 375 pinctrl-0 = <&pinctrl_usbotg>;
354 disable-over-current; 376 disable-over-current;
diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts
index 902f98310481..e51bb3f0fd56 100644
--- a/arch/arm/boot/dts/imx6q-gw5400-a.dts
+++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts
@@ -487,9 +487,6 @@
487 487
488&ldb { 488&ldb {
489 status = "okay"; 489 status = "okay";
490 lvds-channel@0 {
491 crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
492 };
493}; 490};
494 491
495&pcie { 492&pcie {
diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
index 8e99c9a9bc76..035d3a85c318 100644
--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
@@ -436,9 +436,6 @@
436 436
437&ldb { 437&ldb {
438 status = "okay"; 438 status = "okay";
439 lvds-channel@0 {
440 crtcs = <&ipu1 0>, <&ipu1 1>;
441 };
442}; 439};
443 440
444&pcie { 441&pcie {
diff --git a/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi b/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
index a3cb2fff8f61..d16066608e21 100644
--- a/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
@@ -26,25 +26,25 @@
26 /* GPIO16 -> AR8035 25MHz */ 26 /* GPIO16 -> AR8035 25MHz */
27 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0xc0000000 27 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0xc0000000
28 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x80000000 28 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x80000000
29 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 29 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
30 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 30 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
31 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 31 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
32 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 32 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
33 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 33 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
34 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ 34 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
35 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 35 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1
36 /* AR8035 pin strapping: IO voltage: pull up */ 36 /* AR8035 pin strapping: IO voltage: pull up */
37 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 37 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
38 /* AR8035 pin strapping: PHYADDR#0: pull down */ 38 /* AR8035 pin strapping: PHYADDR#0: pull down */
39 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0 39 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030
40 /* AR8035 pin strapping: PHYADDR#1: pull down */ 40 /* AR8035 pin strapping: PHYADDR#1: pull down */
41 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x130b0 41 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
42 /* AR8035 pin strapping: MODE#1: pull up */ 42 /* AR8035 pin strapping: MODE#1: pull up */
43 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 43 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
44 /* AR8035 pin strapping: MODE#3: pull up */ 44 /* AR8035 pin strapping: MODE#3: pull up */
45 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 45 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
46 /* AR8035 pin strapping: MODE#0: pull down */ 46 /* AR8035 pin strapping: MODE#0: pull down */
47 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 47 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
48 48
49 /* 49 /*
50 * As the RMII pins are also connected to RGMII 50 * As the RMII pins are also connected to RGMII
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 55cb926fa3f7..eca0971d4db1 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -10,6 +10,8 @@
10 * http://www.gnu.org/copyleft/gpl.html 10 * http://www.gnu.org/copyleft/gpl.html
11 */ 11 */
12 12
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14
13#include "skeleton.dtsi" 15#include "skeleton.dtsi"
14 16
15/ { 17/ {
@@ -46,8 +48,6 @@
46 intc: interrupt-controller@00a01000 { 48 intc: interrupt-controller@00a01000 {
47 compatible = "arm,cortex-a9-gic"; 49 compatible = "arm,cortex-a9-gic";
48 #interrupt-cells = <3>; 50 #interrupt-cells = <3>;
49 #address-cells = <1>;
50 #size-cells = <1>;
51 interrupt-controller; 51 interrupt-controller;
52 reg = <0x00a01000 0x1000>, 52 reg = <0x00a01000 0x1000>,
53 <0x00a00100 0x100>; 53 <0x00a00100 0x100>;
@@ -59,16 +59,19 @@
59 59
60 ckil { 60 ckil {
61 compatible = "fsl,imx-ckil", "fixed-clock"; 61 compatible = "fsl,imx-ckil", "fixed-clock";
62 #clock-cells = <0>;
62 clock-frequency = <32768>; 63 clock-frequency = <32768>;
63 }; 64 };
64 65
65 ckih1 { 66 ckih1 {
66 compatible = "fsl,imx-ckih1", "fixed-clock"; 67 compatible = "fsl,imx-ckih1", "fixed-clock";
68 #clock-cells = <0>;
67 clock-frequency = <0>; 69 clock-frequency = <0>;
68 }; 70 };
69 71
70 osc { 72 osc {
71 compatible = "fsl,imx-osc", "fixed-clock"; 73 compatible = "fsl,imx-osc", "fixed-clock";
74 #clock-cells = <0>;
72 clock-frequency = <24000000>; 75 clock-frequency = <24000000>;
73 }; 76 };
74 }; 77 };
@@ -138,6 +141,12 @@
138 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ 141 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
139 num-lanes = <1>; 142 num-lanes = <1>;
140 interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>; 143 interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>;
144 #interrupt-cells = <1>;
145 interrupt-map-mask = <0 0 0 0x7>;
146 interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
147 <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
148 <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
149 <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
141 clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>; 150 clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>;
142 clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi"; 151 clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi";
143 status = "disabled"; 152 status = "disabled";
diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts
index 864d8dfb51ca..a8d9a93fab85 100644
--- a/arch/arm/boot/dts/imx6sl-evk.dts
+++ b/arch/arm/boot/dts/imx6sl-evk.dts
@@ -282,6 +282,7 @@
282 MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1 282 MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1
283 MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1 283 MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1
284 MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1 284 MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
285 MX6SL_PAD_ECSPI1_SS0__GPIO4_IO11 0x80000000
285 >; 286 >;
286 }; 287 };
287 288
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 3cb4941afeef..d26b099260a3 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -68,8 +68,6 @@
68 intc: interrupt-controller@00a01000 { 68 intc: interrupt-controller@00a01000 {
69 compatible = "arm,cortex-a9-gic"; 69 compatible = "arm,cortex-a9-gic";
70 #interrupt-cells = <3>; 70 #interrupt-cells = <3>;
71 #address-cells = <1>;
72 #size-cells = <1>;
73 interrupt-controller; 71 interrupt-controller;
74 reg = <0x00a01000 0x1000>, 72 reg = <0x00a01000 0x1000>,
75 <0x00a00100 0x100>; 73 <0x00a00100 0x100>;
@@ -81,11 +79,13 @@
81 79
82 ckil { 80 ckil {
83 compatible = "fixed-clock"; 81 compatible = "fixed-clock";
82 #clock-cells = <0>;
84 clock-frequency = <32768>; 83 clock-frequency = <32768>;
85 }; 84 };
86 85
87 osc { 86 osc {
88 compatible = "fixed-clock"; 87 compatible = "fixed-clock";
88 #clock-cells = <0>;
89 clock-frequency = <24000000>; 89 clock-frequency = <24000000>;
90 }; 90 };
91 }; 91 };
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts
index 7dd1d6ede525..ded361075aab 100644
--- a/arch/arm/boot/dts/vf610-twr.dts
+++ b/arch/arm/boot/dts/vf610-twr.dts
@@ -25,11 +25,13 @@
25 clocks { 25 clocks {
26 audio_ext { 26 audio_ext {
27 compatible = "fixed-clock"; 27 compatible = "fixed-clock";
28 #clock-cells = <0>;
28 clock-frequency = <24576000>; 29 clock-frequency = <24576000>;
29 }; 30 };
30 31
31 enet_ext { 32 enet_ext {
32 compatible = "fixed-clock"; 33 compatible = "fixed-clock";
34 #clock-cells = <0>;
33 clock-frequency = <50000000>; 35 clock-frequency = <50000000>;
34 }; 36 };
35 }; 37 };
diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi
index 804873367669..b8ce0aa7b157 100644
--- a/arch/arm/boot/dts/vf610.dtsi
+++ b/arch/arm/boot/dts/vf610.dtsi
@@ -45,11 +45,13 @@
45 45
46 sxosc { 46 sxosc {
47 compatible = "fixed-clock"; 47 compatible = "fixed-clock";
48 #clock-cells = <0>;
48 clock-frequency = <32768>; 49 clock-frequency = <32768>;
49 }; 50 };
50 51
51 fxosc { 52 fxosc {
52 compatible = "fixed-clock"; 53 compatible = "fixed-clock";
54 #clock-cells = <0>;
53 clock-frequency = <24000000>; 55 clock-frequency = <24000000>;
54 }; 56 };
55 }; 57 };
@@ -72,8 +74,6 @@
72 intc: interrupt-controller@40002000 { 74 intc: interrupt-controller@40002000 {
73 compatible = "arm,cortex-a9-gic"; 75 compatible = "arm,cortex-a9-gic";
74 #interrupt-cells = <3>; 76 #interrupt-cells = <3>;
75 #address-cells = <1>;
76 #size-cells = <1>;
77 interrupt-controller; 77 interrupt-controller;
78 reg = <0x40003000 0x1000>, 78 reg = <0x40003000 0x1000>,
79 <0x40002100 0x100>; 79 <0x40002100 0x100>;
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index b0e7f9d2c245..2b4d6acfa34a 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -208,8 +208,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
208 * the "output_enable" bit as a gate, even though it's really just 208 * the "output_enable" bit as a gate, even though it's really just
209 * enabling clock output. 209 * enabling clock output.
210 */ 210 */
211 clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "dummy", base + 0x160, 10); 211 clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "lvds1_sel", base + 0x160, 10);
212 clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "dummy", base + 0x160, 11); 212 clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "lvds2_sel", base + 0x160, 11);
213 213
214 /* name parent_name reg idx */ 214 /* name parent_name reg idx */
215 clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); 215 clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
@@ -258,14 +258,14 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
258 clk[ipu2_sel] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); 258 clk[ipu2_sel] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
259 clk[ldb_di0_sel] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); 259 clk[ldb_di0_sel] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
260 clk[ldb_di1_sel] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); 260 clk[ldb_di1_sel] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
261 clk[ipu1_di0_pre_sel] = imx_clk_mux("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels)); 261 clk[ipu1_di0_pre_sel] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
262 clk[ipu1_di1_pre_sel] = imx_clk_mux("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels)); 262 clk[ipu1_di1_pre_sel] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
263 clk[ipu2_di0_pre_sel] = imx_clk_mux("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels)); 263 clk[ipu2_di0_pre_sel] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
264 clk[ipu2_di1_pre_sel] = imx_clk_mux("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels)); 264 clk[ipu2_di1_pre_sel] = imx_clk_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
265 clk[ipu1_di0_sel] = imx_clk_mux("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels)); 265 clk[ipu1_di0_sel] = imx_clk_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT);
266 clk[ipu1_di1_sel] = imx_clk_mux("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels)); 266 clk[ipu1_di1_sel] = imx_clk_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT);
267 clk[ipu2_di0_sel] = imx_clk_mux("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels)); 267 clk[ipu2_di0_sel] = imx_clk_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT);
268 clk[ipu2_di1_sel] = imx_clk_mux("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels)); 268 clk[ipu2_di1_sel] = imx_clk_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT);
269 clk[hsi_tx_sel] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels)); 269 clk[hsi_tx_sel] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels));
270 clk[pcie_axi_sel] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels)); 270 clk[pcie_axi_sel] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels));
271 clk[ssi1_sel] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); 271 clk[ssi1_sel] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
@@ -445,6 +445,15 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
445 clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]); 445 clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]);
446 } 446 }
447 447
448 clk_set_parent(clk[ipu1_di0_pre_sel], clk[pll5_video_div]);
449 clk_set_parent(clk[ipu1_di1_pre_sel], clk[pll5_video_div]);
450 clk_set_parent(clk[ipu2_di0_pre_sel], clk[pll5_video_div]);
451 clk_set_parent(clk[ipu2_di1_pre_sel], clk[pll5_video_div]);
452 clk_set_parent(clk[ipu1_di0_sel], clk[ipu1_di0_pre]);
453 clk_set_parent(clk[ipu1_di1_sel], clk[ipu1_di1_pre]);
454 clk_set_parent(clk[ipu2_di0_sel], clk[ipu2_di0_pre]);
455 clk_set_parent(clk[ipu2_di1_sel], clk[ipu2_di1_pre]);
456
448 /* 457 /*
449 * The gpmi needs 100MHz frequency in the EDO/Sync mode, 458 * The gpmi needs 100MHz frequency in the EDO/Sync mode,
450 * We can not get the 100MHz from the pll2_pfd0_352m. 459 * We can not get the 100MHz from the pll2_pfd0_352m.
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-01 04:21:12 -0500