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-rw-r--r--drivers/gpu/drm/vmwgfx/svga3d_reg.h122
-rw-r--r--drivers/gpu/drm/vmwgfx/svga3d_surfacedefs.h11
-rw-r--r--drivers/gpu/drm/vmwgfx/svga_reg.h9
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_context.c9
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_drv.c3
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_drv.h1
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c9
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c3
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_shader.c16
-rw-r--r--include/uapi/drm/vmwgfx_drm.h1
10 files changed, 113 insertions, 71 deletions
diff --git a/drivers/gpu/drm/vmwgfx/svga3d_reg.h b/drivers/gpu/drm/vmwgfx/svga3d_reg.h
index b645647b7776..bb594c11605e 100644
--- a/drivers/gpu/drm/vmwgfx/svga3d_reg.h
+++ b/drivers/gpu/drm/vmwgfx/svga3d_reg.h
@@ -1223,9 +1223,19 @@ typedef enum {
1223#define SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL 1129 1223#define SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL 1129
1224 1224
1225#define SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE 1130 1225#define SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE 1130
1226 1226#define SVGA_3D_CMD_GB_SCREEN_DMA 1131
1227#define SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH 1132
1228#define SVGA_3D_CMD_GB_MOB_FENCE 1133
1229#define SVGA_3D_CMD_DEFINE_GB_SURFACE_V2 1134
1227#define SVGA_3D_CMD_DEFINE_GB_MOB64 1135 1230#define SVGA_3D_CMD_DEFINE_GB_MOB64 1135
1228#define SVGA_3D_CMD_REDEFINE_GB_MOB64 1136 1231#define SVGA_3D_CMD_REDEFINE_GB_MOB64 1136
1232#define SVGA_3D_CMD_NOP_ERROR 1137
1233
1234#define SVGA_3D_CMD_RESERVED1 1138
1235#define SVGA_3D_CMD_RESERVED2 1139
1236#define SVGA_3D_CMD_RESERVED3 1140
1237#define SVGA_3D_CMD_RESERVED4 1141
1238#define SVGA_3D_CMD_RESERVED5 1142
1229 1239
1230#define SVGA_3D_CMD_MAX 1142 1240#define SVGA_3D_CMD_MAX 1142
1231#define SVGA_3D_CMD_FUTURE_MAX 3000 1241#define SVGA_3D_CMD_FUTURE_MAX 3000
@@ -1973,8 +1983,7 @@ struct {
1973 uint32 sizeInBytes; 1983 uint32 sizeInBytes;
1974 uint32 validSizeInBytes; 1984 uint32 validSizeInBytes;
1975 SVGAMobFormat ptDepth; 1985 SVGAMobFormat ptDepth;
1976} 1986} __packed
1977__attribute__((__packed__))
1978SVGA3dCmdSetOTableBase; /* SVGA_3D_CMD_SET_OTABLE_BASE */ 1987SVGA3dCmdSetOTableBase; /* SVGA_3D_CMD_SET_OTABLE_BASE */
1979 1988
1980typedef 1989typedef
@@ -1984,15 +1993,13 @@ struct {
1984 uint32 sizeInBytes; 1993 uint32 sizeInBytes;
1985 uint32 validSizeInBytes; 1994 uint32 validSizeInBytes;
1986 SVGAMobFormat ptDepth; 1995 SVGAMobFormat ptDepth;
1987} 1996} __packed
1988__attribute__((__packed__))
1989SVGA3dCmdSetOTableBase64; /* SVGA_3D_CMD_SET_OTABLE_BASE64 */ 1997SVGA3dCmdSetOTableBase64; /* SVGA_3D_CMD_SET_OTABLE_BASE64 */
1990 1998
1991typedef 1999typedef
1992struct { 2000struct {
1993 SVGAOTableType type; 2001 SVGAOTableType type;
1994} 2002} __packed
1995__attribute__((__packed__))
1996SVGA3dCmdReadbackOTable; /* SVGA_3D_CMD_READBACK_OTABLE */ 2003SVGA3dCmdReadbackOTable; /* SVGA_3D_CMD_READBACK_OTABLE */
1997 2004
1998/* 2005/*
@@ -2005,8 +2012,7 @@ struct SVGA3dCmdDefineGBMob {
2005 SVGAMobFormat ptDepth; 2012 SVGAMobFormat ptDepth;
2006 PPN base; 2013 PPN base;
2007 uint32 sizeInBytes; 2014 uint32 sizeInBytes;
2008} 2015} __packed
2009__attribute__((__packed__))
2010SVGA3dCmdDefineGBMob; /* SVGA_3D_CMD_DEFINE_GB_MOB */ 2016SVGA3dCmdDefineGBMob; /* SVGA_3D_CMD_DEFINE_GB_MOB */
2011 2017
2012 2018
@@ -2017,8 +2023,7 @@ SVGA3dCmdDefineGBMob; /* SVGA_3D_CMD_DEFINE_GB_MOB */
2017typedef 2023typedef
2018struct SVGA3dCmdDestroyGBMob { 2024struct SVGA3dCmdDestroyGBMob {
2019 SVGAMobId mobid; 2025 SVGAMobId mobid;
2020} 2026} __packed
2021__attribute__((__packed__))
2022SVGA3dCmdDestroyGBMob; /* SVGA_3D_CMD_DESTROY_GB_MOB */ 2027SVGA3dCmdDestroyGBMob; /* SVGA_3D_CMD_DESTROY_GB_MOB */
2023 2028
2024/* 2029/*
@@ -2031,8 +2036,7 @@ struct SVGA3dCmdRedefineGBMob {
2031 SVGAMobFormat ptDepth; 2036 SVGAMobFormat ptDepth;
2032 PPN base; 2037 PPN base;
2033 uint32 sizeInBytes; 2038 uint32 sizeInBytes;
2034} 2039} __packed
2035__attribute__((__packed__))
2036SVGA3dCmdRedefineGBMob; /* SVGA_3D_CMD_REDEFINE_GB_MOB */ 2040SVGA3dCmdRedefineGBMob; /* SVGA_3D_CMD_REDEFINE_GB_MOB */
2037 2041
2038/* 2042/*
@@ -2045,8 +2049,7 @@ struct SVGA3dCmdDefineGBMob64 {
2045 SVGAMobFormat ptDepth; 2049 SVGAMobFormat ptDepth;
2046 PPN64 base; 2050 PPN64 base;
2047 uint32 sizeInBytes; 2051 uint32 sizeInBytes;
2048} 2052} __packed
2049__attribute__((__packed__))
2050SVGA3dCmdDefineGBMob64; /* SVGA_3D_CMD_DEFINE_GB_MOB64 */ 2053SVGA3dCmdDefineGBMob64; /* SVGA_3D_CMD_DEFINE_GB_MOB64 */
2051 2054
2052/* 2055/*
@@ -2059,8 +2062,7 @@ struct SVGA3dCmdRedefineGBMob64 {
2059 SVGAMobFormat ptDepth; 2062 SVGAMobFormat ptDepth;
2060 PPN64 base; 2063 PPN64 base;
2061 uint32 sizeInBytes; 2064 uint32 sizeInBytes;
2062} 2065} __packed
2063__attribute__((__packed__))
2064SVGA3dCmdRedefineGBMob64; /* SVGA_3D_CMD_REDEFINE_GB_MOB64 */ 2066SVGA3dCmdRedefineGBMob64; /* SVGA_3D_CMD_REDEFINE_GB_MOB64 */
2065 2067
2066/* 2068/*
@@ -2070,8 +2072,7 @@ SVGA3dCmdRedefineGBMob64; /* SVGA_3D_CMD_REDEFINE_GB_MOB64 */
2070typedef 2072typedef
2071struct SVGA3dCmdUpdateGBMobMapping { 2073struct SVGA3dCmdUpdateGBMobMapping {
2072 SVGAMobId mobid; 2074 SVGAMobId mobid;
2073} 2075} __packed
2074__attribute__((__packed__))
2075SVGA3dCmdUpdateGBMobMapping; /* SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING */ 2076SVGA3dCmdUpdateGBMobMapping; /* SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING */
2076 2077
2077/* 2078/*
@@ -2087,7 +2088,8 @@ struct SVGA3dCmdDefineGBSurface {
2087 uint32 multisampleCount; 2088 uint32 multisampleCount;
2088 SVGA3dTextureFilter autogenFilter; 2089 SVGA3dTextureFilter autogenFilter;
2089 SVGA3dSize size; 2090 SVGA3dSize size;
2090} SVGA3dCmdDefineGBSurface; /* SVGA_3D_CMD_DEFINE_GB_SURFACE */ 2091} __packed
2092SVGA3dCmdDefineGBSurface; /* SVGA_3D_CMD_DEFINE_GB_SURFACE */
2091 2093
2092/* 2094/*
2093 * Destroy a guest-backed surface. 2095 * Destroy a guest-backed surface.
@@ -2096,7 +2098,8 @@ struct SVGA3dCmdDefineGBSurface {
2096typedef 2098typedef
2097struct SVGA3dCmdDestroyGBSurface { 2099struct SVGA3dCmdDestroyGBSurface {
2098 uint32 sid; 2100 uint32 sid;
2099} SVGA3dCmdDestroyGBSurface; /* SVGA_3D_CMD_DESTROY_GB_SURFACE */ 2101} __packed
2102SVGA3dCmdDestroyGBSurface; /* SVGA_3D_CMD_DESTROY_GB_SURFACE */
2100 2103
2101/* 2104/*
2102 * Bind a guest-backed surface to an object. 2105 * Bind a guest-backed surface to an object.
@@ -2106,7 +2109,8 @@ typedef
2106struct SVGA3dCmdBindGBSurface { 2109struct SVGA3dCmdBindGBSurface {
2107 uint32 sid; 2110 uint32 sid;
2108 SVGAMobId mobid; 2111 SVGAMobId mobid;
2109} SVGA3dCmdBindGBSurface; /* SVGA_3D_CMD_BIND_GB_SURFACE */ 2112} __packed
2113SVGA3dCmdBindGBSurface; /* SVGA_3D_CMD_BIND_GB_SURFACE */
2110 2114
2111/* 2115/*
2112 * Conditionally bind a mob to a guest backed surface if testMobid 2116 * Conditionally bind a mob to a guest backed surface if testMobid
@@ -2123,7 +2127,7 @@ struct{
2123 SVGAMobId testMobid; 2127 SVGAMobId testMobid;
2124 SVGAMobId mobid; 2128 SVGAMobId mobid;
2125 uint32 flags; 2129 uint32 flags;
2126} 2130} __packed
2127SVGA3dCmdCondBindGBSurface; /* SVGA_3D_CMD_COND_BIND_GB_SURFACE */ 2131SVGA3dCmdCondBindGBSurface; /* SVGA_3D_CMD_COND_BIND_GB_SURFACE */
2128 2132
2129/* 2133/*
@@ -2135,7 +2139,8 @@ typedef
2135struct SVGA3dCmdUpdateGBImage { 2139struct SVGA3dCmdUpdateGBImage {
2136 SVGA3dSurfaceImageId image; 2140 SVGA3dSurfaceImageId image;
2137 SVGA3dBox box; 2141 SVGA3dBox box;
2138} SVGA3dCmdUpdateGBImage; /* SVGA_3D_CMD_UPDATE_GB_IMAGE */ 2142} __packed
2143SVGA3dCmdUpdateGBImage; /* SVGA_3D_CMD_UPDATE_GB_IMAGE */
2139 2144
2140/* 2145/*
2141 * Update an entire guest-backed surface. 2146 * Update an entire guest-backed surface.
@@ -2145,7 +2150,8 @@ struct SVGA3dCmdUpdateGBImage {
2145typedef 2150typedef
2146struct SVGA3dCmdUpdateGBSurface { 2151struct SVGA3dCmdUpdateGBSurface {
2147 uint32 sid; 2152 uint32 sid;
2148} SVGA3dCmdUpdateGBSurface; /* SVGA_3D_CMD_UPDATE_GB_SURFACE */ 2153} __packed
2154SVGA3dCmdUpdateGBSurface; /* SVGA_3D_CMD_UPDATE_GB_SURFACE */
2149 2155
2150/* 2156/*
2151 * Readback an image in a guest-backed surface. 2157 * Readback an image in a guest-backed surface.
@@ -2155,7 +2161,8 @@ struct SVGA3dCmdUpdateGBSurface {
2155typedef 2161typedef
2156struct SVGA3dCmdReadbackGBImage { 2162struct SVGA3dCmdReadbackGBImage {
2157 SVGA3dSurfaceImageId image; 2163 SVGA3dSurfaceImageId image;
2158} SVGA3dCmdReadbackGBImage; /* SVGA_3D_CMD_READBACK_GB_IMAGE*/ 2164} __packed
2165SVGA3dCmdReadbackGBImage; /* SVGA_3D_CMD_READBACK_GB_IMAGE*/
2159 2166
2160/* 2167/*
2161 * Readback an entire guest-backed surface. 2168 * Readback an entire guest-backed surface.
@@ -2165,7 +2172,8 @@ struct SVGA3dCmdReadbackGBImage {
2165typedef 2172typedef
2166struct SVGA3dCmdReadbackGBSurface { 2173struct SVGA3dCmdReadbackGBSurface {
2167 uint32 sid; 2174 uint32 sid;
2168} SVGA3dCmdReadbackGBSurface; /* SVGA_3D_CMD_READBACK_GB_SURFACE */ 2175} __packed
2176SVGA3dCmdReadbackGBSurface; /* SVGA_3D_CMD_READBACK_GB_SURFACE */
2169 2177
2170/* 2178/*
2171 * Readback a sub rect of an image in a guest-backed surface. After 2179 * Readback a sub rect of an image in a guest-backed surface. After
@@ -2179,7 +2187,7 @@ struct SVGA3dCmdReadbackGBImagePartial {
2179 SVGA3dSurfaceImageId image; 2187 SVGA3dSurfaceImageId image;
2180 SVGA3dBox box; 2188 SVGA3dBox box;
2181 uint32 invertBox; 2189 uint32 invertBox;
2182} 2190} __packed
2183SVGA3dCmdReadbackGBImagePartial; /* SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL */ 2191SVGA3dCmdReadbackGBImagePartial; /* SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL */
2184 2192
2185/* 2193/*
@@ -2190,7 +2198,8 @@ SVGA3dCmdReadbackGBImagePartial; /* SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL */
2190typedef 2198typedef
2191struct SVGA3dCmdInvalidateGBImage { 2199struct SVGA3dCmdInvalidateGBImage {
2192 SVGA3dSurfaceImageId image; 2200 SVGA3dSurfaceImageId image;
2193} SVGA3dCmdInvalidateGBImage; /* SVGA_3D_CMD_INVALIDATE_GB_IMAGE */ 2201} __packed
2202SVGA3dCmdInvalidateGBImage; /* SVGA_3D_CMD_INVALIDATE_GB_IMAGE */
2194 2203
2195/* 2204/*
2196 * Invalidate an entire guest-backed surface. 2205 * Invalidate an entire guest-backed surface.
@@ -2200,7 +2209,8 @@ struct SVGA3dCmdInvalidateGBImage {
2200typedef 2209typedef
2201struct SVGA3dCmdInvalidateGBSurface { 2210struct SVGA3dCmdInvalidateGBSurface {
2202 uint32 sid; 2211 uint32 sid;
2203} SVGA3dCmdInvalidateGBSurface; /* SVGA_3D_CMD_INVALIDATE_GB_SURFACE */ 2212} __packed
2213SVGA3dCmdInvalidateGBSurface; /* SVGA_3D_CMD_INVALIDATE_GB_SURFACE */
2204 2214
2205/* 2215/*
2206 * Invalidate a sub rect of an image in a guest-backed surface. After 2216 * Invalidate a sub rect of an image in a guest-backed surface. After
@@ -2214,7 +2224,7 @@ struct SVGA3dCmdInvalidateGBImagePartial {
2214 SVGA3dSurfaceImageId image; 2224 SVGA3dSurfaceImageId image;
2215 SVGA3dBox box; 2225 SVGA3dBox box;
2216 uint32 invertBox; 2226 uint32 invertBox;
2217} 2227} __packed
2218SVGA3dCmdInvalidateGBImagePartial; /* SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL */ 2228SVGA3dCmdInvalidateGBImagePartial; /* SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL */
2219 2229
2220/* 2230/*
@@ -2224,7 +2234,8 @@ SVGA3dCmdInvalidateGBImagePartial; /* SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL */
2224typedef 2234typedef
2225struct SVGA3dCmdDefineGBContext { 2235struct SVGA3dCmdDefineGBContext {
2226 uint32 cid; 2236 uint32 cid;
2227} SVGA3dCmdDefineGBContext; /* SVGA_3D_CMD_DEFINE_GB_CONTEXT */ 2237} __packed
2238SVGA3dCmdDefineGBContext; /* SVGA_3D_CMD_DEFINE_GB_CONTEXT */
2228 2239
2229/* 2240/*
2230 * Destroy a guest-backed context. 2241 * Destroy a guest-backed context.
@@ -2233,7 +2244,8 @@ struct SVGA3dCmdDefineGBContext {
2233typedef 2244typedef
2234struct SVGA3dCmdDestroyGBContext { 2245struct SVGA3dCmdDestroyGBContext {
2235 uint32 cid; 2246 uint32 cid;
2236} SVGA3dCmdDestroyGBContext; /* SVGA_3D_CMD_DESTROY_GB_CONTEXT */ 2247} __packed
2248SVGA3dCmdDestroyGBContext; /* SVGA_3D_CMD_DESTROY_GB_CONTEXT */
2237 2249
2238/* 2250/*
2239 * Bind a guest-backed context. 2251 * Bind a guest-backed context.
@@ -2252,7 +2264,8 @@ struct SVGA3dCmdBindGBContext {
2252 uint32 cid; 2264 uint32 cid;
2253 SVGAMobId mobid; 2265 SVGAMobId mobid;
2254 uint32 validContents; 2266 uint32 validContents;
2255} SVGA3dCmdBindGBContext; /* SVGA_3D_CMD_BIND_GB_CONTEXT */ 2267} __packed
2268SVGA3dCmdBindGBContext; /* SVGA_3D_CMD_BIND_GB_CONTEXT */
2256 2269
2257/* 2270/*
2258 * Readback a guest-backed context. 2271 * Readback a guest-backed context.
@@ -2262,7 +2275,8 @@ struct SVGA3dCmdBindGBContext {
2262typedef 2275typedef
2263struct SVGA3dCmdReadbackGBContext { 2276struct SVGA3dCmdReadbackGBContext {
2264 uint32 cid; 2277 uint32 cid;
2265} SVGA3dCmdReadbackGBContext; /* SVGA_3D_CMD_READBACK_GB_CONTEXT */ 2278} __packed
2279SVGA3dCmdReadbackGBContext; /* SVGA_3D_CMD_READBACK_GB_CONTEXT */
2266 2280
2267/* 2281/*
2268 * Invalidate a guest-backed context. 2282 * Invalidate a guest-backed context.
@@ -2270,7 +2284,8 @@ struct SVGA3dCmdReadbackGBContext {
2270typedef 2284typedef
2271struct SVGA3dCmdInvalidateGBContext { 2285struct SVGA3dCmdInvalidateGBContext {
2272 uint32 cid; 2286 uint32 cid;
2273} SVGA3dCmdInvalidateGBContext; /* SVGA_3D_CMD_INVALIDATE_GB_CONTEXT */ 2287} __packed
2288SVGA3dCmdInvalidateGBContext; /* SVGA_3D_CMD_INVALIDATE_GB_CONTEXT */
2274 2289
2275/* 2290/*
2276 * Define a guest-backed shader. 2291 * Define a guest-backed shader.
@@ -2281,7 +2296,8 @@ struct SVGA3dCmdDefineGBShader {
2281 uint32 shid; 2296 uint32 shid;
2282 SVGA3dShaderType type; 2297 SVGA3dShaderType type;
2283 uint32 sizeInBytes; 2298 uint32 sizeInBytes;
2284} SVGA3dCmdDefineGBShader; /* SVGA_3D_CMD_DEFINE_GB_SHADER */ 2299} __packed
2300SVGA3dCmdDefineGBShader; /* SVGA_3D_CMD_DEFINE_GB_SHADER */
2285 2301
2286/* 2302/*
2287 * Bind a guest-backed shader. 2303 * Bind a guest-backed shader.
@@ -2291,7 +2307,8 @@ typedef struct SVGA3dCmdBindGBShader {
2291 uint32 shid; 2307 uint32 shid;
2292 SVGAMobId mobid; 2308 SVGAMobId mobid;
2293 uint32 offsetInBytes; 2309 uint32 offsetInBytes;
2294} SVGA3dCmdBindGBShader; /* SVGA_3D_CMD_BIND_GB_SHADER */ 2310} __packed
2311SVGA3dCmdBindGBShader; /* SVGA_3D_CMD_BIND_GB_SHADER */
2295 2312
2296/* 2313/*
2297 * Destroy a guest-backed shader. 2314 * Destroy a guest-backed shader.
@@ -2299,7 +2316,8 @@ typedef struct SVGA3dCmdBindGBShader {
2299 2316
2300typedef struct SVGA3dCmdDestroyGBShader { 2317typedef struct SVGA3dCmdDestroyGBShader {
2301 uint32 shid; 2318 uint32 shid;
2302} SVGA3dCmdDestroyGBShader; /* SVGA_3D_CMD_DESTROY_GB_SHADER */ 2319} __packed
2320SVGA3dCmdDestroyGBShader; /* SVGA_3D_CMD_DESTROY_GB_SHADER */
2303 2321
2304typedef 2322typedef
2305struct { 2323struct {
@@ -2314,14 +2332,16 @@ struct {
2314 * Note that FLOAT and INT constants are 4-dwords in length, while 2332 * Note that FLOAT and INT constants are 4-dwords in length, while
2315 * BOOL constants are 1-dword in length. 2333 * BOOL constants are 1-dword in length.
2316 */ 2334 */
2317} SVGA3dCmdSetGBShaderConstInline; 2335} __packed
2336SVGA3dCmdSetGBShaderConstInline;
2318/* SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE */ 2337/* SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE */
2319 2338
2320typedef 2339typedef
2321struct { 2340struct {
2322 uint32 cid; 2341 uint32 cid;
2323 SVGA3dQueryType type; 2342 SVGA3dQueryType type;
2324} SVGA3dCmdBeginGBQuery; /* SVGA_3D_CMD_BEGIN_GB_QUERY */ 2343} __packed
2344SVGA3dCmdBeginGBQuery; /* SVGA_3D_CMD_BEGIN_GB_QUERY */
2325 2345
2326typedef 2346typedef
2327struct { 2347struct {
@@ -2329,7 +2349,8 @@ struct {
2329 SVGA3dQueryType type; 2349 SVGA3dQueryType type;
2330 SVGAMobId mobid; 2350 SVGAMobId mobid;
2331 uint32 offset; 2351 uint32 offset;
2332} SVGA3dCmdEndGBQuery; /* SVGA_3D_CMD_END_GB_QUERY */ 2352} __packed
2353SVGA3dCmdEndGBQuery; /* SVGA_3D_CMD_END_GB_QUERY */
2333 2354
2334 2355
2335/* 2356/*
@@ -2346,21 +2367,22 @@ struct {
2346 SVGA3dQueryType type; 2367 SVGA3dQueryType type;
2347 SVGAMobId mobid; 2368 SVGAMobId mobid;
2348 uint32 offset; 2369 uint32 offset;
2349} SVGA3dCmdWaitForGBQuery; /* SVGA_3D_CMD_WAIT_FOR_GB_QUERY */ 2370} __packed
2371SVGA3dCmdWaitForGBQuery; /* SVGA_3D_CMD_WAIT_FOR_GB_QUERY */
2350 2372
2351typedef 2373typedef
2352struct { 2374struct {
2353 SVGAMobId mobid; 2375 SVGAMobId mobid;
2354 uint32 fbOffset; 2376 uint32 fbOffset;
2355 uint32 initalized; 2377 uint32 initalized;
2356} 2378} __packed
2357SVGA3dCmdEnableGart; /* SVGA_3D_CMD_ENABLE_GART */ 2379SVGA3dCmdEnableGart; /* SVGA_3D_CMD_ENABLE_GART */
2358 2380
2359typedef 2381typedef
2360struct { 2382struct {
2361 SVGAMobId mobid; 2383 SVGAMobId mobid;
2362 uint32 gartOffset; 2384 uint32 gartOffset;
2363} 2385} __packed
2364SVGA3dCmdMapMobIntoGart; /* SVGA_3D_CMD_MAP_MOB_INTO_GART */ 2386SVGA3dCmdMapMobIntoGart; /* SVGA_3D_CMD_MAP_MOB_INTO_GART */
2365 2387
2366 2388
@@ -2368,7 +2390,7 @@ typedef
2368struct { 2390struct {
2369 uint32 gartOffset; 2391 uint32 gartOffset;
2370 uint32 numPages; 2392 uint32 numPages;
2371} 2393} __packed
2372SVGA3dCmdUnmapGartRange; /* SVGA_3D_CMD_UNMAP_GART_RANGE */ 2394SVGA3dCmdUnmapGartRange; /* SVGA_3D_CMD_UNMAP_GART_RANGE */
2373 2395
2374 2396
@@ -2385,27 +2407,27 @@ struct {
2385 int32 xRoot; 2407 int32 xRoot;
2386 int32 yRoot; 2408 int32 yRoot;
2387 uint32 flags; 2409 uint32 flags;
2388} 2410} __packed
2389SVGA3dCmdDefineGBScreenTarget; /* SVGA_3D_CMD_DEFINE_GB_SCREENTARGET */ 2411SVGA3dCmdDefineGBScreenTarget; /* SVGA_3D_CMD_DEFINE_GB_SCREENTARGET */
2390 2412
2391typedef 2413typedef
2392struct { 2414struct {
2393 uint32 stid; 2415 uint32 stid;
2394} 2416} __packed
2395SVGA3dCmdDestroyGBScreenTarget; /* SVGA_3D_CMD_DESTROY_GB_SCREENTARGET */ 2417SVGA3dCmdDestroyGBScreenTarget; /* SVGA_3D_CMD_DESTROY_GB_SCREENTARGET */
2396 2418
2397typedef 2419typedef
2398struct { 2420struct {
2399 uint32 stid; 2421 uint32 stid;
2400 SVGA3dSurfaceImageId image; 2422 SVGA3dSurfaceImageId image;
2401} 2423} __packed
2402SVGA3dCmdBindGBScreenTarget; /* SVGA_3D_CMD_BIND_GB_SCREENTARGET */ 2424SVGA3dCmdBindGBScreenTarget; /* SVGA_3D_CMD_BIND_GB_SCREENTARGET */
2403 2425
2404typedef 2426typedef
2405struct { 2427struct {
2406 uint32 stid; 2428 uint32 stid;
2407 SVGA3dBox box; 2429 SVGA3dBox box;
2408} 2430} __packed
2409SVGA3dCmdUpdateGBScreenTarget; /* SVGA_3D_CMD_UPDATE_GB_SCREENTARGET */ 2431SVGA3dCmdUpdateGBScreenTarget; /* SVGA_3D_CMD_UPDATE_GB_SCREENTARGET */
2410 2432
2411/* 2433/*
diff --git a/drivers/gpu/drm/vmwgfx/svga3d_surfacedefs.h b/drivers/gpu/drm/vmwgfx/svga3d_surfacedefs.h
index 8369c3ba10fe..ef3385096145 100644
--- a/drivers/gpu/drm/vmwgfx/svga3d_surfacedefs.h
+++ b/drivers/gpu/drm/vmwgfx/svga3d_surfacedefs.h
@@ -38,8 +38,11 @@
38 38
39#define DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y)) 39#define DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y))
40#define max_t(type, x, y) ((x) > (y) ? (x) : (y)) 40#define max_t(type, x, y) ((x) > (y) ? (x) : (y))
41#define min_t(type, x, y) ((x) < (y) ? (x) : (y))
41#define surf_size_struct SVGA3dSize 42#define surf_size_struct SVGA3dSize
42#define u32 uint32 43#define u32 uint32
44#define u64 uint64_t
45#define U32_MAX ((u32)~0U)
43 46
44#endif /* __KERNEL__ */ 47#endif /* __KERNEL__ */
45 48
@@ -704,8 +707,8 @@ static const struct svga3d_surface_desc svga3d_surface_descs[] = {
704 707
705static inline u32 clamped_umul32(u32 a, u32 b) 708static inline u32 clamped_umul32(u32 a, u32 b)
706{ 709{
707 uint64_t tmp = (uint64_t) a*b; 710 u64 tmp = (u64) a*b;
708 return (tmp > (uint64_t) ((u32) -1)) ? (u32) -1 : tmp; 711 return (tmp > (u64) U32_MAX) ? U32_MAX : tmp;
709} 712}
710 713
711static inline const struct svga3d_surface_desc * 714static inline const struct svga3d_surface_desc *
@@ -834,7 +837,7 @@ svga3dsurface_get_serialized_size(SVGA3dSurfaceFormat format,
834 bool cubemap) 837 bool cubemap)
835{ 838{
836 const struct svga3d_surface_desc *desc = svga3dsurface_get_desc(format); 839 const struct svga3d_surface_desc *desc = svga3dsurface_get_desc(format);
837 u32 total_size = 0; 840 u64 total_size = 0;
838 u32 mip; 841 u32 mip;
839 842
840 for (mip = 0; mip < num_mip_levels; mip++) { 843 for (mip = 0; mip < num_mip_levels; mip++) {
@@ -847,7 +850,7 @@ svga3dsurface_get_serialized_size(SVGA3dSurfaceFormat format,
847 if (cubemap) 850 if (cubemap)
848 total_size *= SVGA3D_MAX_SURFACE_FACES; 851 total_size *= SVGA3D_MAX_SURFACE_FACES;
849 852
850 return total_size; 853 return (u32) min_t(u64, total_size, (u64) U32_MAX);
851} 854}
852 855
853 856
diff --git a/drivers/gpu/drm/vmwgfx/svga_reg.h b/drivers/gpu/drm/vmwgfx/svga_reg.h
index 71defa4d2d75..11323dd5196f 100644
--- a/drivers/gpu/drm/vmwgfx/svga_reg.h
+++ b/drivers/gpu/drm/vmwgfx/svga_reg.h
@@ -169,10 +169,17 @@ enum {
169 SVGA_REG_TRACES = 45, /* Enable trace-based updates even when FIFO is on */ 169 SVGA_REG_TRACES = 45, /* Enable trace-based updates even when FIFO is on */
170 SVGA_REG_GMRS_MAX_PAGES = 46, /* Maximum number of 4KB pages for all GMRs */ 170 SVGA_REG_GMRS_MAX_PAGES = 46, /* Maximum number of 4KB pages for all GMRs */
171 SVGA_REG_MEMORY_SIZE = 47, /* Total dedicated device memory excluding FIFO */ 171 SVGA_REG_MEMORY_SIZE = 47, /* Total dedicated device memory excluding FIFO */
172 SVGA_REG_COMMAND_LOW = 48, /* Lower 32 bits and submits commands */
173 SVGA_REG_COMMAND_HIGH = 49, /* Upper 32 bits of command buffer PA */
172 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM = 50, /* Max primary memory */ 174 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM = 50, /* Max primary memory */
173 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB = 51, /* Suggested limit on mob mem */ 175 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB = 51, /* Suggested limit on mob mem */
174 SVGA_REG_DEV_CAP = 52, /* Write dev cap index, read value */ 176 SVGA_REG_DEV_CAP = 52, /* Write dev cap index, read value */
175 SVGA_REG_TOP = 53, /* Must be 1 more than the last register */ 177 SVGA_REG_CMD_PREPEND_LOW = 53,
178 SVGA_REG_CMD_PREPEND_HIGH = 54,
179 SVGA_REG_SCREENTARGET_MAX_WIDTH = 55,
180 SVGA_REG_SCREENTARGET_MAX_HEIGHT = 56,
181 SVGA_REG_MOB_MAX_SIZE = 57,
182 SVGA_REG_TOP = 58, /* Must be 1 more than the last register */
176 183
177 SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */ 184 SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
178 /* Next 768 (== 256*3) registers exist for colormap */ 185 /* Next 768 (== 256*3) registers exist for colormap */
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_context.c b/drivers/gpu/drm/vmwgfx/vmwgfx_context.c
index 9426c53fb483..1e80152674b5 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_context.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_context.c
@@ -551,8 +551,7 @@ static int vmw_context_scrub_shader(struct vmw_ctx_bindinfo *bi, bool rebind)
551 cmd->header.size = sizeof(cmd->body); 551 cmd->header.size = sizeof(cmd->body);
552 cmd->body.cid = bi->ctx->id; 552 cmd->body.cid = bi->ctx->id;
553 cmd->body.type = bi->i1.shader_type; 553 cmd->body.type = bi->i1.shader_type;
554 cmd->body.shid = 554 cmd->body.shid = ((rebind) ? bi->res->id : SVGA3D_INVALID_ID);
555 cpu_to_le32((rebind) ? bi->res->id : SVGA3D_INVALID_ID);
556 vmw_fifo_commit(dev_priv, sizeof(*cmd)); 555 vmw_fifo_commit(dev_priv, sizeof(*cmd));
557 556
558 return 0; 557 return 0;
@@ -585,8 +584,7 @@ static int vmw_context_scrub_render_target(struct vmw_ctx_bindinfo *bi,
585 cmd->header.size = sizeof(cmd->body); 584 cmd->header.size = sizeof(cmd->body);
586 cmd->body.cid = bi->ctx->id; 585 cmd->body.cid = bi->ctx->id;
587 cmd->body.type = bi->i1.rt_type; 586 cmd->body.type = bi->i1.rt_type;
588 cmd->body.target.sid = 587 cmd->body.target.sid = ((rebind) ? bi->res->id : SVGA3D_INVALID_ID);
589 cpu_to_le32((rebind) ? bi->res->id : SVGA3D_INVALID_ID);
590 cmd->body.target.face = 0; 588 cmd->body.target.face = 0;
591 cmd->body.target.mipmap = 0; 589 cmd->body.target.mipmap = 0;
592 vmw_fifo_commit(dev_priv, sizeof(*cmd)); 590 vmw_fifo_commit(dev_priv, sizeof(*cmd));
@@ -628,8 +626,7 @@ static int vmw_context_scrub_texture(struct vmw_ctx_bindinfo *bi,
628 cmd->body.c.cid = bi->ctx->id; 626 cmd->body.c.cid = bi->ctx->id;
629 cmd->body.s1.stage = bi->i1.texture_stage; 627 cmd->body.s1.stage = bi->i1.texture_stage;
630 cmd->body.s1.name = SVGA3D_TS_BIND_TEXTURE; 628 cmd->body.s1.name = SVGA3D_TS_BIND_TEXTURE;
631 cmd->body.s1.value = 629 cmd->body.s1.value = ((rebind) ? bi->res->id : SVGA3D_INVALID_ID);
632 cpu_to_le32((rebind) ? bi->res->id : SVGA3D_INVALID_ID);
633 vmw_fifo_commit(dev_priv, sizeof(*cmd)); 630 vmw_fifo_commit(dev_priv, sizeof(*cmd));
634 631
635 return 0; 632 return 0;
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
index 3bdc0adc656d..0083cbf99edf 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
@@ -667,6 +667,7 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
667 dev_priv->memory_size = 512*1024*1024; 667 dev_priv->memory_size = 512*1024*1024;
668 } 668 }
669 dev_priv->max_mob_pages = 0; 669 dev_priv->max_mob_pages = 0;
670 dev_priv->max_mob_size = 0;
670 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 671 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
671 uint64_t mem_size = 672 uint64_t mem_size =
672 vmw_read(dev_priv, 673 vmw_read(dev_priv,
@@ -676,6 +677,8 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
676 dev_priv->prim_bb_mem = 677 dev_priv->prim_bb_mem =
677 vmw_read(dev_priv, 678 vmw_read(dev_priv,
678 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); 679 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM);
680 dev_priv->max_mob_size =
681 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE);
679 } else 682 } else
680 dev_priv->prim_bb_mem = dev_priv->vram_size; 683 dev_priv->prim_bb_mem = dev_priv->vram_size;
681 684
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
index ecaa302a6154..9e4be1725985 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
@@ -386,6 +386,7 @@ struct vmw_private {
386 uint32_t max_gmr_ids; 386 uint32_t max_gmr_ids;
387 uint32_t max_gmr_pages; 387 uint32_t max_gmr_pages;
388 uint32_t max_mob_pages; 388 uint32_t max_mob_pages;
389 uint32_t max_mob_size;
389 uint32_t memory_size; 390 uint32_t memory_size;
390 bool has_gmr; 391 bool has_gmr;
391 bool has_mob; 392 bool has_mob;
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
index 269b85cc875a..efb575a7996c 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
@@ -602,7 +602,7 @@ static int vmw_cmd_cid_check(struct vmw_private *dev_priv,
602{ 602{
603 struct vmw_cid_cmd { 603 struct vmw_cid_cmd {
604 SVGA3dCmdHeader header; 604 SVGA3dCmdHeader header;
605 __le32 cid; 605 uint32_t cid;
606 } *cmd; 606 } *cmd;
607 607
608 cmd = container_of(header, struct vmw_cid_cmd, header); 608 cmd = container_of(header, struct vmw_cid_cmd, header);
@@ -1835,7 +1835,7 @@ static int vmw_cmd_check_not_3d(struct vmw_private *dev_priv,
1835 return 0; 1835 return 0;
1836} 1836}
1837 1837
1838static const struct vmw_cmd_entry const vmw_cmd_entries[SVGA_3D_CMD_MAX] = { 1838static const struct vmw_cmd_entry vmw_cmd_entries[SVGA_3D_CMD_MAX] = {
1839 VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_DEFINE, &vmw_cmd_invalid, 1839 VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_DEFINE, &vmw_cmd_invalid,
1840 false, false, false), 1840 false, false, false),
1841 VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_DESTROY, &vmw_cmd_invalid, 1841 VMW_CMD_DEF(SVGA_3D_CMD_SURFACE_DESTROY, &vmw_cmd_invalid,
@@ -2032,6 +2032,9 @@ static int vmw_cmd_check(struct vmw_private *dev_priv,
2032 goto out_invalid; 2032 goto out_invalid;
2033 2033
2034 entry = &vmw_cmd_entries[cmd_id]; 2034 entry = &vmw_cmd_entries[cmd_id];
2035 if (unlikely(!entry->func))
2036 goto out_invalid;
2037
2035 if (unlikely(!entry->user_allow && !sw_context->kernel)) 2038 if (unlikely(!entry->user_allow && !sw_context->kernel))
2036 goto out_privileged; 2039 goto out_privileged;
2037 2040
@@ -2469,7 +2472,7 @@ int vmw_execbuf_process(struct drm_file *file_priv,
2469 if (dev_priv->has_mob) { 2472 if (dev_priv->has_mob) {
2470 ret = vmw_rebind_contexts(sw_context); 2473 ret = vmw_rebind_contexts(sw_context);
2471 if (unlikely(ret != 0)) 2474 if (unlikely(ret != 0))
2472 goto out_err; 2475 goto out_unlock_binding;
2473 } 2476 }
2474 2477
2475 cmd = vmw_fifo_reserve(dev_priv, command_size); 2478 cmd = vmw_fifo_reserve(dev_priv, command_size);
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c b/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
index f9881f9e62bd..47b70949bf3a 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
@@ -102,6 +102,9 @@ int vmw_getparam_ioctl(struct drm_device *dev, void *data,
102 vmw_fp->gb_aware = true; 102 vmw_fp->gb_aware = true;
103 param->value = dev_priv->max_mob_pages * PAGE_SIZE; 103 param->value = dev_priv->max_mob_pages * PAGE_SIZE;
104 break; 104 break;
105 case DRM_VMW_PARAM_MAX_MOB_SIZE:
106 param->value = dev_priv->max_mob_size;
107 break;
105 default: 108 default:
106 DRM_ERROR("Illegal vmwgfx get param request: %d\n", 109 DRM_ERROR("Illegal vmwgfx get param request: %d\n",
107 param->param); 110 param->param);
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_shader.c b/drivers/gpu/drm/vmwgfx/vmwgfx_shader.c
index 217d941b8176..ee3856578a12 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_shader.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_shader.c
@@ -371,13 +371,13 @@ int vmw_shader_destroy_ioctl(struct drm_device *dev, void *data,
371 TTM_REF_USAGE); 371 TTM_REF_USAGE);
372} 372}
373 373
374int vmw_shader_alloc(struct vmw_private *dev_priv, 374static int vmw_shader_alloc(struct vmw_private *dev_priv,
375 struct vmw_dma_buffer *buffer, 375 struct vmw_dma_buffer *buffer,
376 size_t shader_size, 376 size_t shader_size,
377 size_t offset, 377 size_t offset,
378 SVGA3dShaderType shader_type, 378 SVGA3dShaderType shader_type,
379 struct ttm_object_file *tfile, 379 struct ttm_object_file *tfile,
380 u32 *handle) 380 u32 *handle)
381{ 381{
382 struct vmw_user_shader *ushader; 382 struct vmw_user_shader *ushader;
383 struct vmw_resource *res, *tmp; 383 struct vmw_resource *res, *tmp;
@@ -779,6 +779,8 @@ vmw_compat_shader_man_create(struct vmw_private *dev_priv)
779 int ret; 779 int ret;
780 780
781 man = kzalloc(sizeof(*man), GFP_KERNEL); 781 man = kzalloc(sizeof(*man), GFP_KERNEL);
782 if (man == NULL)
783 return ERR_PTR(-ENOMEM);
782 784
783 man->dev_priv = dev_priv; 785 man->dev_priv = dev_priv;
784 INIT_LIST_HEAD(&man->list); 786 INIT_LIST_HEAD(&man->list);
diff --git a/include/uapi/drm/vmwgfx_drm.h b/include/uapi/drm/vmwgfx_drm.h
index 9971c560ed9a..87792a5fee3b 100644
--- a/include/uapi/drm/vmwgfx_drm.h
+++ b/include/uapi/drm/vmwgfx_drm.h
@@ -87,6 +87,7 @@
87#define DRM_VMW_PARAM_MAX_SURF_MEMORY 7 87#define DRM_VMW_PARAM_MAX_SURF_MEMORY 7
88#define DRM_VMW_PARAM_3D_CAPS_SIZE 8 88#define DRM_VMW_PARAM_3D_CAPS_SIZE 8
89#define DRM_VMW_PARAM_MAX_MOB_MEMORY 9 89#define DRM_VMW_PARAM_MAX_MOB_MEMORY 9
90#define DRM_VMW_PARAM_MAX_MOB_SIZE 10
90 91
91/** 92/**
92 * struct drm_vmw_getparam_arg 93 * struct drm_vmw_getparam_arg