509 files changed, 29079 insertions, 6220 deletions

diff --git a/Documentation/arm/Samsung/Bootloader-interface.txt b/Documentation/arm/Samsung/Bootloader-interface.txt
index ed494ac0beb2..d17ed518a7ea 100644
--- a/Documentation/arm/Samsung/Bootloader-interface.txt
+++ b/Documentation/arm/Samsung/Bootloader-interface.txt
@@ -26,6 +26,7 @@ Offset        Value                                        Purpose
 0x20          0xfcba0d10 (Magic cookie)                    AFTR
 0x24          exynos_cpu_resume_ns                         AFTR
 0x28 + 4*cpu  0x8 (Magic cookie, Exynos3250)               AFTR
+0x28          0x0 or last value during resume (Exynos542x) System suspend
 
 
 2. Secure mode
diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt
index b5c2b5c35766..4498292b833d 100644
--- a/Documentation/devicetree/bindings/arm/amlogic.txt
+++ b/Documentation/devicetree/bindings/arm/amlogic.txt
@@ -57,12 +57,17 @@ Boards with the Amlogic Meson AXG A113D SoC shall have the following properties:
   Required root node property:
     compatible: "amlogic,a113d", "amlogic,meson-axg";
 
+Boards with the Amlogic Meson G12A S905D2 SoC shall have the following properties:
+  Required root node property:
+    compatible: "amlogic,g12a";
+
 Board compatible values (alphabetically, grouped by SoC):
 
   - "geniatech,atv1200" (Meson6)
 
   - "minix,neo-x8" (Meson8)
 
+  - "endless,ec100" (Meson8b)
   - "hardkernel,odroid-c1" (Meson8b)
   - "tronfy,mxq" (Meson8b)
 
@@ -101,6 +106,8 @@ Board compatible values (alphabetically, grouped by SoC):
 
   - "amlogic,s400" (Meson axg a113d)
 
+  - "amlogic,u200" (Meson g12a s905d2)
+
 Amlogic Meson Firmware registers Interface
 ------------------------------------------
 
diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt
index 1e3e29a545e2..0dcc3ea5adff 100644
--- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt
+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt
@@ -42,6 +42,14 @@ Raspberry Pi Compute Module
 Required root node properties:
 compatible = "raspberrypi,compute-module", "brcm,bcm2835";
 
+Raspberry Pi Compute Module 3
+Required root node properties:
+compatible = "raspberrypi,3-compute-module", "brcm,bcm2837";
+
+Raspberry Pi Compute Module 3 Lite
+Required root node properties:
+compatible = "raspberrypi,3-compute-module-lite", "brcm,bcm2837";
+
 Raspberry Pi Zero
 Required root node properties:
 compatible = "raspberrypi,model-zero", "brcm,bcm2835";
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index 1e775aaa5c5b..5074aeecd327 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -57,6 +57,50 @@ i.MX6SLL EVK board
 Required root node properties:
     - compatible = "fsl,imx6sll-evk", "fsl,imx6sll";
 
+i.MX6 Quad Plus SABRE Smart Device Board
+Required root node properties:
+    - compatible = "fsl,imx6qp-sabresd", "fsl,imx6qp";
+
+i.MX6 Quad Plus SABRE Automotive Board
+Required root node properties:
+    - compatible = "fsl,imx6qp-sabreauto", "fsl,imx6qp";
+
+i.MX6 DualLite SABRE Smart Device Board
+Required root node properties:
+    - compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
+
+i.MX6 DualLite/Solo SABRE Automotive Board
+Required root node properties:
+    - compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl";
+
+i.MX6 SoloLite EVK Board
+Required root node properties:
+    - compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
+
+i.MX6 UltraLite 14x14 EVK Board
+Required root node properties:
+    - compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul";
+
+i.MX6 UltraLiteLite 14x14 EVK Board
+Required root node properties:
+    - compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";
+
+i.MX6 ULZ 14x14 EVK Board
+Required root node properties:
+    - compatible = "fsl,imx6ulz-14x14-evk", "fsl,imx6ull", "fsl,imx6ulz";
+
+i.MX6 SoloX SDB Board
+Required root node properties:
+    - compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
+
+i.MX6 SoloX Sabre Auto Board
+Required root node properties:
+    - compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx";
+
+i.MX7 SabreSD Board
+Required root node properties:
+    - compatible = "fsl,imx7d-sdb", "fsl,imx7d";
+
 Generic i.MX boards
 -------------------
 
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 199cd36fe1ba..a97f643e7d1c 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -8,6 +8,14 @@ HiKey960 Board
 Required root node properties:
         - compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
 
+Hi3670 SoC
+Required root node properties:
+        - compatible = "hisilicon,hi3670";
+
+HiKey970 Board
+Required root node properties:
+        - compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670";
+
 Hi3798cv200 SoC
 Required root node properties:
         - compatible = "hisilicon,hi3798cv200";
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
index b404d592ce58..4e4a3c0ab9ab 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
@@ -10,6 +10,7 @@ Required Properties:
         - "mediatek,mt2712-apmixedsys", "syscon"
         - "mediatek,mt6797-apmixedsys"
         - "mediatek,mt7622-apmixedsys"
+        - "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys"
         - "mediatek,mt8135-apmixedsys"
         - "mediatek,mt8173-apmixedsys"
 - #clock-cells: Must be 1
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
index 34a69ba67f13..d1606b2c3e63 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
@@ -8,6 +8,7 @@ Required Properties:
 - compatible: Should be one of:
         - "mediatek,mt2701-audsys", "syscon"
         - "mediatek,mt7622-audsys", "syscon"
+        - "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
 - #clock-cells: Must be 1
 
 The AUDSYS controller uses the common clk binding from
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt
index 4010e37c53a0..149567a38215 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt
@@ -8,6 +8,7 @@ Required Properties:
 - compatible: Should be:
         - "mediatek,mt2701-bdpsys", "syscon"
         - "mediatek,mt2712-bdpsys", "syscon"
+        - "mediatek,mt7623-bdpsys", "mediatek,mt2701-bdpsys", "syscon"
 - #clock-cells: Must be 1
 
 The bdpsys controller uses the common clk binding from
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
index 8f5335b480ac..f17cfe64255d 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
@@ -8,6 +8,7 @@ Required Properties:
 - compatible: Should be:
         - "mediatek,mt2701-ethsys", "syscon"
         - "mediatek,mt7622-ethsys", "syscon"
+        - "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
 - #clock-cells: Must be 1
 - #reset-cells: Must be 1
 
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt
index f5629d64cef2..323905af82c3 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt
@@ -9,6 +9,7 @@ Required Properties:
 - compatible: Should be:
         - "mediatek,mt2701-hifsys", "syscon"
         - "mediatek,mt7622-hifsys", "syscon"
+        - "mediatek,mt7623-hifsys", "mediatek,mt2701-hifsys", "syscon"
 - #clock-cells: Must be 1
 
 The hifsys controller uses the common clk binding from
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
index 868bd51a98be..3f99672163e3 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
@@ -9,6 +9,7 @@ Required Properties:
         - "mediatek,mt2701-imgsys", "syscon"
         - "mediatek,mt2712-imgsys", "syscon"
         - "mediatek,mt6797-imgsys", "syscon"
+        - "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon"
         - "mediatek,mt8173-imgsys", "syscon"
 - #clock-cells: Must be 1
 
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
index 566f153f9f83..89f4272a1441 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
@@ -11,6 +11,7 @@ Required Properties:
         - "mediatek,mt2712-infracfg", "syscon"
         - "mediatek,mt6797-infracfg", "syscon"
         - "mediatek,mt7622-infracfg", "syscon"
+        - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
         - "mediatek,mt8135-infracfg", "syscon"
         - "mediatek,mt8173-infracfg", "syscon"
 - #clock-cells: Must be 1
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
index 4eb8bbe15c01..15d977afad31 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
@@ -9,6 +9,7 @@ Required Properties:
         - "mediatek,mt2701-mmsys", "syscon"
         - "mediatek,mt2712-mmsys", "syscon"
         - "mediatek,mt6797-mmsys", "syscon"
+        - "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon"
         - "mediatek,mt8173-mmsys", "syscon"
 - #clock-cells: Must be 1
 
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
index fb58ca8c2770..6755514deb80 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
@@ -10,6 +10,7 @@ Required Properties:
         - "mediatek,mt2701-pericfg", "syscon"
         - "mediatek,mt2712-pericfg", "syscon"
         - "mediatek,mt7622-pericfg", "syscon"
+        - "mediatek,mt7623-pericfg", "mediatek,mt2701-pericfg", "syscon"
         - "mediatek,mt8135-pericfg", "syscon"
         - "mediatek,mt8173-pericfg", "syscon"
 - #clock-cells: Must be 1
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
index 24014a7e2332..d849465b8c99 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
@@ -10,6 +10,7 @@ Required Properties:
         - "mediatek,mt2712-topckgen", "syscon"
         - "mediatek,mt6797-topckgen"
         - "mediatek,mt7622-topckgen"
+        - "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen"
         - "mediatek,mt8135-topckgen"
         - "mediatek,mt8173-topckgen"
 - #clock-cells: Must be 1
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
index ea40d05089f8..3212afc753c8 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
@@ -9,6 +9,7 @@ Required Properties:
         - "mediatek,mt2701-vdecsys", "syscon"
         - "mediatek,mt2712-vdecsys", "syscon"
         - "mediatek,mt6797-vdecsys", "syscon"
+        - "mediatek,mt7623-vdecsys", "mediatek,mt2701-vdecsys", "syscon"
         - "mediatek,mt8173-vdecsys", "syscon"
 - #clock-cells: Must be 1
 
diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt
index acfd3c773dd0..0cc71236d639 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.txt
+++ b/Documentation/devicetree/bindings/arm/rockchip.txt
@@ -5,6 +5,10 @@ Rockchip platforms device tree bindings
     Required root node properties:
       - compatible = "vamrs,ficus", "rockchip,rk3399";
 
+- 96boards RK3399 Rock960 (ROCK960 Consumer Edition)
+    Required root node properties:
+      - compatible = "vamrs,rock960", "rockchip,rk3399";
+
 - Amarula Vyasa RK3288 board
     Required root node properties:
       - compatible = "amarula,vyasa-rk3288", "rockchip,rk3288";
@@ -13,6 +17,10 @@ Rockchip platforms device tree bindings
     Required root node properties:
       - compatible = "asus,rk3288-tinker", "rockchip,rk3288";
 
+- Asus Tinker board S
+    Required root node properties:
+      - compatible = "asus,rk3288-tinker-s", "rockchip,rk3288";
+
 - Kylin RK3036 board:
     Required root node properties:
       - compatible = "rockchip,kylin-rk3036", "rockchip,rk3036";
@@ -59,6 +67,10 @@ Rockchip platforms device tree bindings
     Required root node properties:
       - compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328";
 
+- Firefly ROC-RK3399-PC board:
+    Required root node properties:
+      - compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399";
+
 - ChipSPARK PopMetal-RK3288 board:
     Required root node properties:
       - compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288";
@@ -160,6 +172,10 @@ Rockchip platforms device tree bindings
     Required root node properties:
     - compatible = "pine64,rock64", "rockchip,rk3328";
 
+- Pine64 RockPro64 board:
+    Required root node properties:
+    - compatible = "pine64,rockpro64", "rockchip,rk3399";
+
 - Rockchip PX3 Evaluation board:
     Required root node properties:
       - compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188";
@@ -168,6 +184,10 @@ Rockchip platforms device tree bindings
     Required root node properties:
       - compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368";
 
+- Rockchip PX30 Evaluation board:
+    Required root node properties:
+      - compatible = "rockchip,px30-evb", "rockchip,px30";
+
 - Rockchip RV1108 Evaluation board
     Required root node properties:
       - compatible = "rockchip,rv1108-evb", "rockchip,rv1108";
diff --git a/Documentation/devicetree/bindings/arm/scu.txt b/Documentation/devicetree/bindings/arm/scu.txt
index 08a587875996..74d0a780ce51 100644
--- a/Documentation/devicetree/bindings/arm/scu.txt
+++ b/Documentation/devicetree/bindings/arm/scu.txt
@@ -22,7 +22,7 @@ References:
 
 Example:
 
-scu@a04100000 {
+scu@a0410000 {
         compatible = "arm,cortex-a9-scu";
         reg = <0xa0410000 0x100>;
 };
diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index 89b4a389fbc7..f5e0f82fd503 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -7,6 +7,8 @@ SoCs:
     compatible = "renesas,emev2"
   - RZ/A1H (R7S72100)
     compatible = "renesas,r7s72100"
+  - RZ/A2 (R7S9210)
+    compatible = "renesas,r7s9210"
   - SH-Mobile AG5 (R8A73A00/SH73A0)
     compatible = "renesas,sh73a0"
   - R-Mobile APE6 (R8A73A40)
@@ -23,6 +25,10 @@ SoCs:
     compatible = "renesas,r8a7745"
   - RZ/G1C (R8A77470)
     compatible = "renesas,r8a77470"
+  - RZ/G2M (R8A774A1)
+    compatible = "renesas,r8a774a1"
+  - RZ/G2E (RA8774C0)
+    compatible = "renesas,r8a774c0"
   - R-Car M1A (R8A77781)
     compatible = "renesas,r8a7778"
   - R-Car H1 (R8A77790)
@@ -107,6 +113,8 @@ Boards:
     compatible = "renesas,lager", "renesas,r8a7790"
   - M3ULCB (R-Car Starter Kit Pro, RTP0RC7796SKBX0010SA09 (M3 ES1.0))
     compatible = "renesas,m3ulcb", "renesas,r8a7796"
+  - M3NULCB (R-Car Starter Kit Pro, RTP0RC77965SKBX010SA00 (M3-N ES1.1))
+    compatible = "renesas,m3nulcb", "renesas,r8a77965"
   - Marzen (R0P7779A00010S)
     compatible = "renesas,marzen", "renesas,r8a7779"
   - Porter (M2-LCDP)
@@ -143,12 +151,12 @@ Boards:
     compatible = "renesas,wheat", "renesas,r8a7792"
 
 
-Most Renesas ARM SoCs have a Product Register that allows to retrieve SoC
-product and revision information.  If present, a device node for this register
-should be added.
+Most Renesas ARM SoCs have a Product Register or Boundary Scan ID Register that
+allows to retrieve SoC product and revision information.  If present, a device
+node for this register should be added.
 
 Required properties:
-  - compatible: Must be "renesas,prr".
+  - compatible: Must be "renesas,prr" or "renesas,bsid"
   - reg: Base address and length of the register block.
 
 
diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,berlin.txt b/Documentation/devicetree/bindings/arm/syna.txt
index 3bab18409b7a..2face46a5f64 100644
--- a/Documentation/devicetree/bindings/arm/marvell/marvell,berlin.txt
+++ b/Documentation/devicetree/bindings/arm/syna.txt
@@ -1,4 +1,9 @@
-Marvell Berlin SoC Family Device Tree Bindings
+Synaptics SoC Device Tree Bindings
+
+According to https://www.synaptics.com/company/news/conexant-marvell
+Synaptics has acquired the Multimedia Solutions Business of Marvell, so
+berlin SoCs are now Synaptics' SoCs now.
+
 ---------------------------------------------------------------
 
 Work in progress statement:
@@ -13,6 +18,10 @@ stable binding/ABI.
 
 ---------------------------------------------------------------
 
+Boards with the Synaptics AS370 SoC shall have the following properties:
+  Required root node property:
+    compatible: "syna,as370"
+
 Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
 shall have the following properties:
 
diff --git a/Documentation/devicetree/bindings/arm/tegra.txt b/Documentation/devicetree/bindings/arm/tegra.txt
index 32f62bb7006d..c59b15f64346 100644
--- a/Documentation/devicetree/bindings/arm/tegra.txt
+++ b/Documentation/devicetree/bindings/arm/tegra.txt
@@ -47,12 +47,17 @@ board-specific compatible values:
   nvidia,ventana
   toradex,apalis_t30
   toradex,apalis_t30-eval
+  toradex,apalis_t30-v1.1
+  toradex,apalis_t30-v1.1-eval
   toradex,apalis-tk1
   toradex,apalis-tk1-eval
-  toradex,colibri_t20-512
+  toradex,apalis-tk1-v1.2
+  toradex,apalis-tk1-v1.2-eval
+  toradex,colibri_t20
+  toradex,colibri_t20-eval-v3
+  toradex,colibri_t20-iris
   toradex,colibri_t30
   toradex,colibri_t30-eval-v3
-  toradex,iris
 
 Trusted Foundations
 -------------------------------------------
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt
index 5a3bf7c5a7a0..c9fd6d1de57e 100644
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt
@@ -34,3 +34,96 @@ Board DTS:
         pmc@c360000 {
                 nvidia,invert-interrupt;
         };
+
+== Pad Control ==
+
+On Tegra SoCs a pad is a set of pins which are configured as a group.
+The pin grouping is a fixed attribute of the hardware. The PMC can be
+used to set pad power state and signaling voltage. A pad can be either
+in active or power down mode. The support for power state and signaling
+voltage configuration varies depending on the pad in question. 3.3 V and
+1.8 V signaling voltages are supported on pins where software
+controllable signaling voltage switching is available.
+
+Pad configurations are described with pin configuration nodes which
+are placed under the pmc node and they are referred to by the pinctrl
+client properties. For more information see
+Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
+
+The following pads are present on Tegra186:
+csia            csib            dsi             mipi-bias
+pex-clk-bias    pex-clk3        pex-clk2        pex-clk1
+usb0            usb1            usb2            usb-bias
+uart            audio           hsic            dbg
+hdmi-dp0        hdmi-dp1        pex-cntrl       sdmmc2-hv
+sdmmc4          cam             dsib            dsic
+dsid            csic            csid            csie
+dsif            spi             ufs             dmic-hv
+edp             sdmmc1-hv       sdmmc3-hv       conn
+audio-hv        ao-hv
+
+Required pin configuration properties:
+  - pins: A list of strings, each of which contains the name of a pad
+          to be configured.
+
+Optional pin configuration properties:
+  - low-power-enable: Configure the pad into power down mode
+  - low-power-disable: Configure the pad into active mode
+  - power-source: Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
+    TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
+    The values are defined in
+    include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
+
+Note: The power state can be configured on all of the above pads except
+      for ao-hv. Following pads have software configurable signaling
+      voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv, audio-hv,
+      ao-hv.
+
+Pad configuration state example:
+        pmc: pmc@7000e400 {
+                compatible = "nvidia,tegra186-pmc";
+                reg = <0 0x0c360000 0 0x10000>,
+                      <0 0x0c370000 0 0x10000>,
+                      <0 0x0c380000 0 0x10000>,
+                      <0 0x0c390000 0 0x10000>;
+                reg-names = "pmc", "wake", "aotag", "scratch";
+
+                ...
+
+                sdmmc1_3v3: sdmmc1-3v3 {
+                        pins = "sdmmc1-hv";
+                        power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
+                };
+
+                sdmmc1_1v8: sdmmc1-1v8 {
+                        pins = "sdmmc1-hv";
+                        power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
+                };
+
+                hdmi_off: hdmi-off {
+                        pins = "hdmi";
+                        low-power-enable;
+                }
+
+                hdmi_on: hdmi-on {
+                        pins = "hdmi";
+                        low-power-disable;
+                }
+        };
+
+Pinctrl client example:
+        sdmmc1: sdhci@3400000 {
+                ...
+                pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
+                pinctrl-0 = <&sdmmc1_3v3>;
+                pinctrl-1 = <&sdmmc1_1v8>;
+        };
+
+        ...
+
+        sor0: sor@15540000 {
+                ...
+                pinctrl-0 = <&hdmi_off>;
+                pinctrl-1 = <&hdmi_on>;
+                pinctrl-names = "hdmi-on", "hdmi-off";
+        };
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
index a74b37b07e5c..cb12f33a247f 100644
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
@@ -195,3 +195,106 @@ Example:
                 power-domains = <&pd_audio>;
                 ...
         };
+
+== Pad Control ==
+
+On Tegra SoCs a pad is a set of pins which are configured as a group.
+The pin grouping is a fixed attribute of the hardware. The PMC can be
+used to set pad power state and signaling voltage. A pad can be either
+in active or power down mode. The support for power state and signaling
+voltage configuration varies depending on the pad in question. 3.3 V and
+1.8 V signaling voltages are supported on pins where software
+controllable signaling voltage switching is available.
+
+The pad configuration state nodes are placed under the pmc node and they
+are referred to by the pinctrl client properties. For more information
+see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
+The pad name should be used as the value of the pins property in pin
+configuration nodes.
+
+The following pads are present on Tegra124 and Tegra132:
+audio           bb              cam             comp
+csia            csb             cse             dsi
+dsib            dsic            dsid            hdmi
+hsic            hv              lvds            mipi-bias
+nand            pex-bias        pex-clk1        pex-clk2
+pex-cntrl       sdmmc1          sdmmc3          sdmmc4
+sys_ddc         uart            usb0            usb1
+usb2            usb_bias
+
+The following pads are present on Tegra210:
+audio           audio-hv        cam             csia
+csib            csic            csid            csie
+csif            dbg             debug-nonao     dmic
+dp              dsi             dsib            dsic
+dsid            emmc            emmc2           gpio
+hdmi            hsic            lvds            mipi-bias
+pex-bias        pex-clk1        pex-clk2        pex-cntrl
+sdmmc1          sdmmc3          spi             spi-hv
+uart            usb0            usb1            usb2
+usb3            usb-bias
+
+Required pin configuration properties:
+  - pins: Must contain name of the pad(s) to be configured.
+
+Optional pin configuration properties:
+  - low-power-enable: Configure the pad into power down mode
+  - low-power-disable: Configure the pad into active mode
+  - power-source: Must contain either TEGRA_IO_PAD_VOLTAGE_1V8
+    or TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
+    The values are defined in
+    include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
+
+Note: The power state can be configured on all of the Tegra124 and
+      Tegra132 pads. None of the Tegra124 or Tegra132 pads support
+      signaling voltage switching.
+
+Note: All of the listed Tegra210 pads except pex-cntrl support power
+      state configuration. Signaling voltage switching is supported on
+      following Tegra210 pads: audio, audio-hv, cam, dbg, dmic, gpio,
+      pex-cntrl, sdmmc1, sdmmc3, spi, spi-hv, and uart.
+
+Pad configuration state example:
+        pmc: pmc@7000e400 {
+                compatible = "nvidia,tegra210-pmc";
+                reg = <0x0 0x7000e400 0x0 0x400>;
+                clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
+                clock-names = "pclk", "clk32k_in";
+
+                ...
+
+                sdmmc1_3v3: sdmmc1-3v3 {
+                        pins = "sdmmc1";
+                        power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
+                };
+
+                sdmmc1_1v8: sdmmc1-1v8 {
+                        pins = "sdmmc1";
+                        power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
+                };
+
+                hdmi_off: hdmi-off {
+                        pins = "hdmi";
+                        low-power-enable;
+                }
+
+                hdmi_on: hdmi-on {
+                        pins = "hdmi";
+                        low-power-disable;
+                }
+        };
+
+Pinctrl client example:
+        sdmmc1: sdhci@700b0000 {
+                ...
+                pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
+                pinctrl-0 = <&sdmmc1_3v3>;
+                pinctrl-1 = <&sdmmc1_1v8>;
+        };
+        ...
+        sor@54540000 {
+                ...
+                pinctrl-0 = <&hdmi_off>;
+                pinctrl-1 = <&hdmi_on>;
+                pinctrl-names = "hdmi-on", "hdmi-off";
+        };
diff --git a/Documentation/devicetree/bindings/arm/ux500/boards.txt b/Documentation/devicetree/bindings/arm/ux500/boards.txt
index 0fa429534f49..89408de55bfd 100644
--- a/Documentation/devicetree/bindings/arm/ux500/boards.txt
+++ b/Documentation/devicetree/bindings/arm/ux500/boards.txt
@@ -60,7 +60,7 @@ Example:
                               <0xa0410100 0x100>;
                 };
 
-                scu@a04100000 {
+                scu@a0410000 {
                         compatible = "arm,cortex-a9-scu";
                         reg = <0xa0410000 0x100>;
                 };
diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
index a45ca67a9d5f..e1308346e00d 100644
--- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
@@ -6,6 +6,14 @@ Required properties:
 - interrupts: Should contain CCM interrupt
 - #clock-cells: Should be <1>
 
+Optional properties:
+- fsl,pmic-stby-poweroff: Configure CCM to assert PMIC_STBY_REQ signal
+  on power off.
+  Use this property if the SoC should be powered off by external power
+  management IC (PMIC) triggered via PMIC_STBY_REQ signal.
+  Boards that are designed to initiate poweroff on PMIC_ON_REQ signal should
+  be using "syscon-poweroff" driver instead.
+
 The clock consumer should specify the desired clock by having the clock
 ID in its "clocks" phandle cell.  See include/dt-bindings/clock/imx6qdl-clock.h
 for the full list of i.MX6 Quad and DualLite clock IDs.
diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
index df5db732138d..6922db598def 100644
--- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
+++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
@@ -41,6 +41,8 @@ Required properties:
 - compatible : must be one of the following string:
         "mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW.
         "mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW.
+        "mediatek,mt7623-m4u", "mediatek,mt2701-m4u" for mt7623 which uses
+                                                     generation one m4u HW.
         "mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW.
 - reg : m4u register base and size.
 - interrupts : the interrupt of m4u.
@@ -51,7 +53,7 @@ Required properties:
         according to the local arbiter index, like larb0, larb1, larb2...
 - iommu-cells : must be 1. This is the mtk_m4u_id according to the HW.
         Specifies the mtk_m4u_id as defined in
-        dt-binding/memory/mt2701-larb-port.h for mt2701,
+        dt-binding/memory/mt2701-larb-port.h for mt2701, mt7623
         dt-binding/memory/mt2712-larb-port.h for mt2712, and
         dt-binding/memory/mt8173-larb-port.h for mt8173.
 
diff --git a/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.txt b/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.txt
index 3813947b4d4f..044b11913c49 100644
--- a/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.txt
+++ b/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.txt
@@ -5,6 +5,7 @@ Mediatek JPEG Decoder is the JPEG decode hardware present in Mediatek SoCs
 Required properties:
 - compatible : must be one of the following string:
         "mediatek,mt8173-jpgdec"
+        "mediatek,mt7623-jpgdec", "mediatek,mt2701-jpgdec"
         "mediatek,mt2701-jpgdec"
 - reg : physical base address of the jpeg decoder registers and length of
   memory mapped region.
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
index 615abdd0eb0d..e937ddd871a6 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
@@ -17,6 +17,7 @@ Required properties:
 - compatible : must be one of :
         "mediatek,mt2701-smi-common"
         "mediatek,mt2712-smi-common"
+        "mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common"
         "mediatek,mt8173-smi-common"
 - reg : the register and size of the SMI block.
 - power-domains : a phandle to the power domain of this local arbiter.
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
index 083155cdc2a0..94eddcae77ab 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
@@ -6,6 +6,7 @@ Required properties:
 - compatible : must be one of :
                 "mediatek,mt2701-smi-larb"
                 "mediatek,mt2712-smi-larb"
+                "mediatek,mt7623-smi-larb", "mediatek,mt2701-smi-larb"
                 "mediatek,mt8173-smi-larb"
 - reg : the register and size of this local arbiter.
 - mediatek,smi : a phandle to the smi_common node.
@@ -16,7 +17,7 @@ Required properties:
             the register.
   - "smi" : It's the clock for transfer data and command.
 
-Required property for mt2701 and mt2712:
+Required property for mt2701, mt2712 and mt7623:
 - mediatek,larb-id :the hardware id of this larb.
 
 Example:
diff --git a/Documentation/devicetree/bindings/net/dsa/b53.txt b/Documentation/devicetree/bindings/net/dsa/b53.txt
index 1811e1972a7a..5201bc15fdd6 100644
--- a/Documentation/devicetree/bindings/net/dsa/b53.txt
+++ b/Documentation/devicetree/bindings/net/dsa/b53.txt
@@ -46,6 +46,42 @@ Required properties:
       "brcm,bcm6328-switch"
       "brcm,bcm6368-switch" and the mandatory "brcm,bcm63xx-switch"
 
+Required properties for BCM585xx/586xx/88312 SoCs:
+
+ - reg: a total of 3 register base addresses, the first one must be the
+   Switch Register Access block base, the second is the port 5/4 mux
+   configuration register and the third one is the SGMII configuration
+   and status register base address.
+
+ - interrupts: a total of 13 interrupts must be specified, in the following
+   order: port 0-5, 7-8 link status change, then the integrated PHY interrupt,
+   then the timestamping interrupt and the sleep timer interrupts for ports
+   5,7,8.
+
+Optional properties for BCM585xx/586xx/88312 SoCs:
+
+  - reg-names: a total of 3 names matching the 3 base register address, must
+    be in the following order:
+        "srab"
+        "mux_config"
+        "sgmii_config"
+
+  - interrupt-names: a total of 13 names matching the 13 interrupts specified
+    must be in the following order:
+        "link_state_p0"
+        "link_state_p1"
+        "link_state_p2"
+        "link_state_p3"
+        "link_state_p4"
+        "link_state_p5"
+        "link_state_p7"
+        "link_state_p8"
+        "phy"
+        "ts"
+        "imp_sleep_timer_p5"
+        "imp_sleep_timer_p7"
+        "imp_sleep_timer_p8"
+
 See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional
 required and optional properties.
 
diff --git a/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt b/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt
index e319fe5e205a..99c4ba6a3f61 100644
--- a/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt
+++ b/Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt
@@ -7,6 +7,7 @@ Required properties:
   "allwinner,sun8i-a83t-sid"
   "allwinner,sun8i-h3-sid"
   "allwinner,sun50i-a64-sid"
+  "allwinner,sun50i-h5-sid"
 
 - reg: Should contain registers location and length
 
diff --git a/Documentation/devicetree/bindings/power/actions,owl-sps.txt b/Documentation/devicetree/bindings/power/actions,owl-sps.txt
index 78edd63641e8..a3571937b019 100644
--- a/Documentation/devicetree/bindings/power/actions,owl-sps.txt
+++ b/Documentation/devicetree/bindings/power/actions,owl-sps.txt
@@ -3,11 +3,13 @@ Actions Semi Owl Smart Power System (SPS)
 Required properties:
 - compatible          :  "actions,s500-sps" for S500
                          "actions,s700-sps" for S700
+                         "actions,s900-sps" for S900
 - reg                 :  Offset and length of the register set for the device.
 - #power-domain-cells :  Must be 1.
                          See macros in:
                           include/dt-bindings/power/owl-s500-powergate.h for S500
                           include/dt-bindings/power/owl-s700-powergate.h for S700
+                          include/dt-bindings/power/owl-s900-powergate.h for S900
 
 
 Example:
diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.txt b/Documentation/devicetree/bindings/soc/rockchip/grf.txt
index 7dc5ce858a0e..46e27cd69f18 100644
--- a/Documentation/devicetree/bindings/soc/rockchip/grf.txt
+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.txt
@@ -13,6 +13,7 @@ On RK3328 SoCs, the GRF adds a section for USB2PHYGRF,
 Required Properties:
 
 - compatible: GRF should be one of the following:
+   - "rockchip,px30-grf", "syscon": for px30
    - "rockchip,rk3036-grf", "syscon": for rk3036
    - "rockchip,rk3066-grf", "syscon": for rk3066
    - "rockchip,rk3188-grf", "syscon": for rk3188
@@ -23,6 +24,7 @@ Required Properties:
    - "rockchip,rk3399-grf", "syscon": for rk3399
    - "rockchip,rv1108-grf", "syscon": for rv1108
 - compatible: PMUGRF should be one of the following:
+   - "rockchip,px30-pmugrf", "syscon": for px30
    - "rockchip,rk3368-pmugrf", "syscon": for rk3368
    - "rockchip,rk3399-pmugrf", "syscon": for rk3399
 - compatible: SGRF should be one of the following
diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt b/Documentation/devicetree/bindings/usb/dwc2.txt
index 46da5f184460..6dc3c4a34483 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.txt
+++ b/Documentation/devicetree/bindings/usb/dwc2.txt
@@ -6,6 +6,7 @@ Required properties:
   - brcm,bcm2835-usb: The DWC2 USB controller instance in the BCM2835 SoC.
   - hisilicon,hi6220-usb: The DWC2 USB controller instance in the hi6220 SoC.
   - rockchip,rk3066-usb: The DWC2 USB controller instance in the rk3066 Soc;
+  - "rockchip,px30-usb", "rockchip,rk3066-usb", "snps,dwc2": for px30 Soc;
   - "rockchip,rk3188-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3188 Soc;
   - "rockchip,rk3288-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3288 Soc;
   - "lantiq,arx100-usb": The DWC2 USB controller instance in Lantiq ARX SoCs;
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 14818137a029..4b1a2a8fcc16 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -115,6 +115,7 @@ elan	Elan Microelectronic Corp.
 embest  Shenzhen Embest Technology Co., Ltd.
 emmicro EM Microelectronic
 emtrion emtrion GmbH
+endless Endless Mobile, Inc.
 energymicro     Silicon Laboratories (formerly Energy Micro AS)
 engicam Engicam S.r.l.
 epcos   EPCOS AG
@@ -301,6 +302,7 @@ pine64	Pine64
 pixcir  PIXCIR MICROELECTRONICS Co., Ltd
 plathome        Plat'Home Co., Ltd.
 plda    PLDA
+plx     Broadcom Corporation (formerly PLX Technology)
 portwell        Portwell Inc.
 poslab  Poslab Technology Co., Ltd.
 powervr PowerVR (deprecated, use img)
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b5bd3de87c33..b0e966d625b9 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -81,6 +81,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += \
         bcm2836-rpi-2-b.dtb \
         bcm2837-rpi-3-b.dtb \
         bcm2837-rpi-3-b-plus.dtb \
+        bcm2837-rpi-cm3-io3.dtb \
         bcm2835-rpi-zero.dtb \
         bcm2835-rpi-zero-w.dtb
 dtb-$(CONFIG_ARCH_BCM_5301X) += \
@@ -321,6 +322,7 @@ dtb-$(CONFIG_MACH_MESON6) += \
         meson6-atv1200.dtb
 dtb-$(CONFIG_MACH_MESON8) += \
         meson8-minix-neo-x8.dtb \
+        meson8b-ec100.dtb \
         meson8b-mxq.dtb \
         meson8b-odroidc1.dtb \
         meson8m2-mxiii-plus.dtb
@@ -548,6 +550,7 @@ dtb-$(CONFIG_SOC_IMX6SX) += \
 dtb-$(CONFIG_SOC_IMX6UL) += \
         imx6ul-14x14-evk.dtb \
         imx6ul-ccimx6ulsbcexpress.dtb \
+        imx6ul-ccimx6ulsbcpro.dtb \
         imx6ul-geam.dtb \
         imx6ul-isiot-emmc.dtb \
         imx6ul-isiot-nand.dtb \
@@ -559,7 +562,8 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
         imx6ul-tx6ul-mainboard.dtb \
         imx6ull-14x14-evk.dtb \
         imx6ull-colibri-eval-v3.dtb \
-        imx6ull-colibri-wifi-eval-v3.dtb
+        imx6ull-colibri-wifi-eval-v3.dtb \
+        imx6ulz-14x14-evk.dtb
 dtb-$(CONFIG_SOC_IMX7D) += \
         imx7d-cl-som-imx7.dtb \
         imx7d-colibri-emmc-eval-v3.dtb \
@@ -649,6 +653,7 @@ dtb-$(CONFIG_ARCH_OMAP3) += \
         omap3-gta04a3.dtb \
         omap3-gta04a4.dtb \
         omap3-gta04a5.dtb \
+        omap3-gta04a5one.dtb \
         omap3-ha.dtb \
         omap3-ha-lcd.dtb \
         omap3-igep0020.dtb \
@@ -706,6 +711,7 @@ dtb-$(CONFIG_SOC_AM33XX) += \
         am335x-evmsk.dtb \
         am335x-icev2.dtb \
         am335x-lxm.dtb \
+        am335x-moxa-uc-2101.dtb \
         am335x-moxa-uc-8100-me-t.dtb \
         am335x-nano.dtb \
         am335x-pdu001.dtb \
@@ -864,6 +870,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
         rk3288-r89.dtb \
         rk3288-rock2-square.dtb \
         rk3288-tinker.dtb \
+        rk3288-tinker-s.dtb \
         rk3288-veyron-brain.dtb \
         rk3288-veyron-jaq.dtb \
         rk3288-veyron-jerry.dtb \
@@ -892,7 +899,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \
         socfpga_arria10_socdk_sdmmc.dtb \
         socfpga_cyclone5_mcvevk.dtb \
         socfpga_cyclone5_socdk.dtb \
-        socfpga_cyclone5_de0_sockit.dtb \
+        socfpga_cyclone5_de0_nano_soc.dtb \
         socfpga_cyclone5_sockit.dtb \
         socfpga_cyclone5_socrates.dtb \
         socfpga_cyclone5_sodia.dtb \
@@ -1033,6 +1040,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
         sun8i-h2-plus-orangepi-r1.dtb \
         sun8i-h2-plus-orangepi-zero.dtb \
         sun8i-h3-bananapi-m2-plus.dtb \
+        sun8i-h3-bananapi-m2-plus-v1.2.dtb \
         sun8i-h3-beelink-x2.dtb \
         sun8i-h3-libretech-all-h3-cc.dtb \
         sun8i-h3-nanopi-m1.dtb  \
@@ -1046,6 +1054,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
         sun8i-h3-orangepi-pc-plus.dtb \
         sun8i-h3-orangepi-plus.dtb \
         sun8i-h3-orangepi-plus2e.dtb \
+        sun8i-h3-orangepi-zero-plus2.dtb \
         sun8i-r16-bananapi-m2m.dtb \
         sun8i-r16-nintendo-nes-classic.dtb \
         sun8i-r16-nintendo-super-nes-classic.dtb \
@@ -1061,6 +1070,7 @@ dtb-$(CONFIG_ARCH_TANGO) += \
         tango4-vantage-1172.dtb
 dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
         tegra20-harmony.dtb \
+        tegra20-colibri-eval-v3.dtb \
         tegra20-colibri-iris.dtb \
         tegra20-medcom-wide.dtb \
         tegra20-paz00.dtb \
@@ -1071,6 +1081,7 @@ dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
         tegra20-ventana.dtb
 dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \
         tegra30-apalis-eval.dtb \
+        tegra30-apalis-v1.1-eval.dtb \
         tegra30-beaver.dtb \
         tegra30-cardhu-a02.dtb \
         tegra30-cardhu-a04.dtb \
@@ -1149,6 +1160,7 @@ dtb-$(CONFIG_MACH_ARMADA_370) += \
 dtb-$(CONFIG_MACH_ARMADA_375) += \
         armada-375-db.dtb
 dtb-$(CONFIG_MACH_ARMADA_38X) += \
+        armada-385-db-88f6820-amc.dtb \
         armada-385-db-ap.dtb \
         armada-385-linksys-caiman.dtb \
         armada-385-linksys-cobra.dtb \
@@ -1199,6 +1211,8 @@ dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
 dtb-$(CONFIG_ARCH_ASPEED) += \
         aspeed-ast2500-evb.dtb \
         aspeed-bmc-arm-centriq2400-rep.dtb \
+        aspeed-bmc-arm-stardragon4800-rep2.dtb \
+        aspeed-bmc-facebook-tiogapass.dtb \
         aspeed-bmc-intel-s2600wf.dtb \
         aspeed-bmc-opp-lanyang.dtb \
         aspeed-bmc-opp-palmetto.dtb \
diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi
index 73b514dddf65..9e5e75ea87f5 100644
--- a/arch/arm/boot/dts/am335x-bone-common.dtsi
+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
@@ -379,7 +379,7 @@
 };
 
 &cpsw_emac0 {
-        phy_id = <&davinci_mdio>, <0>;
+        phy-handle = <&ethphy0>;
         phy-mode = "mii";
 };
 
@@ -396,6 +396,10 @@
         pinctrl-0 = <&davinci_mdio_default>;
         pinctrl-1 = <&davinci_mdio_sleep>;
         status = "okay";
+
+        ethphy0: ethernet-phy@0 {
+                reg = <0>;
+        };
 };
 
 &mmc1 {
diff --git a/arch/arm/boot/dts/am335x-boneblack-common.dtsi b/arch/arm/boot/dts/am335x-boneblack-common.dtsi
index 325daae40278..e543c2bee8c2 100644
--- a/arch/arm/boot/dts/am335x-boneblack-common.dtsi
+++ b/arch/arm/boot/dts/am335x-boneblack-common.dtsi
@@ -7,6 +7,7 @@
  */
 
 #include <dt-bindings/display/tda998x.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 
 &ldo3_reg {
         regulator-min-microvolt = <1800000>;
@@ -88,9 +89,11 @@
 };
 
 &i2c0 {
-        tda19988: tda19988 {
+        tda19988: tda19988@70 {
                 compatible = "nxp,tda998x";
                 reg = <0x70>;
+                nxp,calib-gpios = <&gpio1 25 0>;
+                interrupts-extended = <&gpio1 25 IRQ_TYPE_LEVEL_LOW>;
 
                 pinctrl-names = "default", "off";
                 pinctrl-0 = <&nxp_hdmi_bonelt_pins>;
diff --git a/arch/arm/boot/dts/am335x-chiliboard.dts b/arch/arm/boot/dts/am335x-chiliboard.dts
index 59431b235944..9c2a947aacf5 100644
--- a/arch/arm/boot/dts/am335x-chiliboard.dts
+++ b/arch/arm/boot/dts/am335x-chiliboard.dts
@@ -140,10 +140,14 @@
         pinctrl-0 = <&davinci_mdio_default>;
         pinctrl-1 = <&davinci_mdio_sleep>;
         status = "okay";
+
+        ethphy0: ethernet-phy@0 {
+                reg = <0>;
+        };
 };
 
 &cpsw_emac0 {
-        phy_id = <&davinci_mdio>, <0>;
+        phy-handle = <&ethphy0>;
         phy-mode = "rmii";
 };
 
diff --git a/arch/arm/boot/dts/am335x-cm-t335.dts b/arch/arm/boot/dts/am335x-cm-t335.dts
index 947c81b7aaaf..c4d3e1f1a95e 100644
--- a/arch/arm/boot/dts/am335x-cm-t335.dts
+++ b/arch/arm/boot/dts/am335x-cm-t335.dts
@@ -486,10 +486,14 @@ status = "okay";
         pinctrl-0 = <&davinci_mdio_default>;
         pinctrl-1 = <&davinci_mdio_sleep>;
         status = "okay";
+
+        ethphy0: ethernet-phy@0 {
+                reg = <0>;
+        };
 };
 
 &cpsw_emac0 {
-        phy_id = <&davinci_mdio>, <0>;
+        phy-handle = <&ethphy0>;
         phy-mode = "rgmii-txid";
 };
 
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index c87d01297a01..98ec9c3e49ba 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -713,6 +713,7 @@
         pinctrl-0 = <&cpsw_default>;
         pinctrl-1 = <&cpsw_sleep>;
         status = "okay";
+        slaves = <1>;
 };
 
 &davinci_mdio {
@@ -720,15 +721,14 @@
         pinctrl-0 = <&davinci_mdio_default>;
         pinctrl-1 = <&davinci_mdio_sleep>;
         status = "okay";
-};
 
-&cpsw_emac0 {
-        phy_id = <&davinci_mdio>, <0>;
-        phy-mode = "rgmii-txid";
+        ethphy0: ethernet-phy@0 {
+                reg = <0>;
+        };
 };
 
-&cpsw_emac1 {
-        phy_id = <&davinci_mdio>, <1>;
+&cpsw_emac0 {
+        phy-handle = <&ethphy0>;
         phy-mode = "rgmii-txid";
 };
 
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index bf1a40e45c97..245868f58fe3 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -639,16 +639,24 @@
         pinctrl-0 = <&davinci_mdio_default>;
         pinctrl-1 = <&davinci_mdio_sleep>;
         status = "okay";
+
+        ethphy0: ethernet-phy@0 {
+                reg = <0>;
+        };
+
+        ethphy1: ethernet-phy@1 {
+                reg = <1>;
+        };
 };
 
 &cpsw_emac0 {
-        phy_id = <&davinci_mdio>, <0>;
+        phy-handle = <&ethphy0>;
         phy-mode = "rgmii-txid";
         dual_emac_res_vlan = <1>;
 };
 
 &cpsw_emac1 {
-        phy_id = <&davinci_mdio>, <1>;
+        phy-handle = <&ethphy1>;
         phy-mode = "rgmii-txid";
         dual_emac_res_vlan = <2>;
 };
diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi
index a5769a8f5fc8..55b4c94cfafb 100644
--- a/arch/arm/boot/dts/am335x-igep0033.dtsi
+++ b/arch/arm/boot/dts/am335x-igep0033.dtsi
@@ -102,15 +102,24 @@
 
 &davinci_mdio {
         status = "okay";
+
+        ethphy0: ethernet-phy@0 {
+                reg = <0>;
+        };
+
+        ethphy1: ethernet-phy@1 {
+                reg = <1>;
+        };
 };
 
 &cpsw_emac0 {
-        phy_id = <&davinci_mdio>, <0>;
+        phy-handle = <&ethphy0>;
         phy-mode = "rmii";
+
 };
 
 &cpsw_emac1 {
-        phy_id = <&davinci_mdio>, <1>;
+        phy-handle = <&ethphy1>;
         phy-mode = "rmii";
 };
 
diff --git a/arch/arm/boot/dts/am335x-lxm.dts b/arch/arm/boot/dts/am335x-lxm.dts
index 1d6c6fa703e4..481edcfaf121 100644
--- a/arch/arm/boot/dts/am335x-lxm.dts
+++ b/arch/arm/boot/dts/am335x-lxm.dts
@@ -317,13 +317,13 @@
 };
 
 &cpsw_emac0 {
-        phy_id = <&davinci_mdio>, <5>;
+        phy-handle = <&ethphy0>;
         phy-mode = "rmii";
         dual_emac_res_vlan = <2>;
 };
 
 &cpsw_emac1 {
-        phy_id = <&davinci_mdio>, <4>;
+        phy-handle = <&ethphy1>;
         phy-mode = "rmii";
         dual_emac_res_vlan = <3>;
 };
@@ -345,6 +345,14 @@
         pinctrl-0 = <&davinci_mdio_default>;
         pinctrl-1 = <&davinci_mdio_sleep>;
         status = "okay";
+
+        ethphy0: ethernet-phy@5 {
+                reg = <5>;
+        };
+
+        ethphy1: ethernet-phy@4 {
+                reg = <4>;
+        };
 };
 
 &mmc1 {
diff --git a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi b/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi
new file mode 100644
index 000000000000..14f781953475
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi
@@ -0,0 +1,249 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MOXA Inc. - https://www.moxa.com/
+ *
+ * Authors: SZ Lin (林上智) <sz.lin@moxa.com>
+ *          Wes Huang (黃淵河) <wes.huang@moxa.com>
+ *          Fero JD Zhou (周俊達) <FeroJD.Zhou@moxa.com>
+ */
+
+#include "am33xx.dtsi"
+
+/ {
+        vbat: vbat-regulator {
+                compatible = "regulator-fixed";
+        };
+
+        /* Power supply provides a fixed 3.3V @3A */
+        vmmcsd_fixed: vmmcsd-regulator {
+              compatible = "regulator-fixed";
+              regulator-name = "vmmcsd_fixed";
+              regulator-min-microvolt = <3300000>;
+              regulator-max-microvolt = <3300000>;
+              regulator-boot-on;
+        };
+
+        buttons: push_button {
+                compatible = "gpio-keys";
+        };
+};
+
+&am33xx_pinmux {
+        pinctrl-names = "default";
+
+        i2c0_pins: pinmux_i2c0_pins {
+                pinctrl-single,pins = <
+                        AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)       /* i2c0_sda.i2c0_sda */
+                        AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)       /* i2c0_scl.i2c0_scl */
+                >;
+        };
+
+        push_button_pins: pinmux_push_button {
+                pinctrl-single,pins = <
+                        AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* lcd_hsync.gpio2_23 */
+                >;
+        };
+
+        uart0_pins: pinmux_uart0_pins {
+                pinctrl-single,pins = <
+                        AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart0_rxd.uart0_rxd */
+                        AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart0_txd.uart0_txd */
+                >;
+        };
+
+        davinci_mdio_default: davinci_mdio_default {
+                pinctrl-single,pins = <
+                        /* MDIO */
+                        AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)       /* mdio_data.mdio_data */
+                        AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)                      /* mdio_clk.mdio_clk */
+                >;
+        };
+
+        mmc1_pins_default: pinmux_mmc1_pins {
+                pinctrl-single,pins = <
+                        /* eMMC */
+                        AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad12.mmc1_dat0 */
+                        AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad13.mmc1_dat1 */
+                        AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad14.mmc1_dat2 */
+                        AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad15.mmc1_dat3 */
+                        AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad8.mmc1_dat4 */
+                        AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad9.mmc1_dat5 */
+                        AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad10.mmc1_dat6 */
+                        AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad11.mmc1_dat7 */
+                        AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2)       /* gpmc_csn2.mmc1_cmd */
+                        AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2)       /* gpmc_csn1.mmc1_clk */
+                >;
+        };
+
+        spi0_pins: pinmux_spi0 {
+                pinctrl-single,pins = <
+                        AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0)        /* spi0_sclk.spi0_sclk */
+                        AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0)        /* spi0_cs0.spi0_cs0 */
+                        AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0)        /* spi0_d0.spi0_d0 */
+                        AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0)        /* spi0_d1.spi0_d1 */
+                >;
+        };
+};
+
+&uart0 {
+        /* Console */
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart0_pins>;
+};
+
+&i2c0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c0_pins>;
+
+        status = "okay";
+        clock-frequency = <400000>;
+
+        eeprom: eeprom@50 {
+                compatible = "atmel,24c16";
+                pagesize = <16>;
+                reg = <0x50>;
+        };
+
+        rtc_wdt: rtc_wdt@68 {
+                compatible = "dallas,ds1374";
+                reg = <0x68>;
+        };
+};
+
+&usb {
+        status = "okay";
+};
+
+&usb_ctrl_mod {
+        status = "okay";
+};
+
+&usb0_phy {
+        status = "okay";
+};
+
+&usb0 {
+        status = "okay";
+        dr_mode = "host";
+};
+
+&cppi41dma  {
+        status = "okay";
+};
+
+/* Power */
+&vbat {
+        regulator-name = "vbat";
+        regulator-min-microvolt = <5000000>;
+        regulator-max-microvolt = <5000000>;
+};
+
+&mac {
+        pinctrl-names = "default";
+        pinctrl-0 = <&cpsw_default>;
+        status = "okay";
+};
+
+&davinci_mdio {
+        pinctrl-names = "default";
+        pinctrl-0 = <&davinci_mdio_default>;
+        status = "okay";
+};
+
+&cpsw_emac0 {
+        status = "okay";
+};
+
+&cpsw_emac1 {
+        status = "okay";
+};
+
+&phy_sel {
+        reg= <0x44e10650 0xf5>;
+        rmii-clock-ext;
+};
+
+&sham {
+        status = "okay";
+};
+
+&aes {
+        status = "okay";
+};
+
+&gpio0 {
+        ti,no-reset-on-init;
+};
+
+&mmc2 {
+        pinctrl-names = "default";
+        vmmc-supply = <&vmmcsd_fixed>;
+        bus-width = <8>;
+        pinctrl-0 = <&mmc1_pins_default>;
+        ti,non-removable;
+        status = "okay";
+};
+
+&buttons {
+        pinctrl-names = "default";
+        pinctrl-0 = <&push_button_pins>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        button@0 {
+                label = "push_button";
+                linux,code = <0x100>;
+                gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
+        };
+};
+
+/* SPI Busses */
+&spi0 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&spi0_pins>;
+
+        m25p80@0 {
+                compatible = "mx25l6405d";
+                spi-max-frequency = <40000000>;
+
+                reg = <0>;
+                spi-cpol;
+                spi-cpha;
+
+                partitions {
+                        compatible = "fixed-partitions";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        /* reg : The partition's offset and size within the mtd bank. */
+                        partitions@0 {
+                                label = "MLO";
+                                reg = <0x0 0x80000>;
+                        };
+
+                        partitions@1 {
+                                label = "U-Boot";
+                                reg = <0x80000 0x100000>;
+                        };
+
+                        partitions@2 {
+                                label = "U-Boot Env";
+                                reg = <0x180000 0x40000>;
+                        };
+                };
+        };
+};
+
+&spi1 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&spi1_pins>;
+
+        tpm_spi_tis@0 {
+                compatible = "tcg,tpm_tis-spi";
+                reg = <0>;
+                spi-max-frequency = <500000>;
+        };
+};
diff --git a/arch/arm/boot/dts/am335x-moxa-uc-2101.dts b/arch/arm/boot/dts/am335x-moxa-uc-2101.dts
new file mode 100644
index 000000000000..48aee6de4cdb
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-moxa-uc-2101.dts
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MOXA Inc. - https://www.moxa.com/
+ *
+ * Authors: SZ Lin (林上智) <sz.lin@moxa.com>
+ *          Wes Huang (黃淵河) <wes.huang@moxa.com>
+ *          Fero JD Zhou (周俊達) <FeroJD.Zhou@moxa.com>
+ */
+
+/dts-v1/;
+
+#include "am335x-moxa-uc-2100-common.dtsi"
+
+/ {
+        model = "Moxa UC-2101";
+        compatible = "moxa,uc-2101", "ti,am33xx";
+
+        leds {
+                compatible = "gpio-leds";
+                led1 {
+                        label = "UC2100:GREEN:USER";
+                        gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+        };
+};
+
+&am33xx_pinmux {
+        pinctrl-names = "default";
+
+        cpsw_default: cpsw_default {
+                pinctrl-single,pins = <
+                        /* Slave 1 */
+                        AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1)     /* mii1_crs.rmii1_crs_dv */
+                        AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE1)       /* mii1_rxerr.rmii1_rxerr */
+                        AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1)    /* mii1_txen.rmii1_txen */
+                        AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1)    /* mii1_txd1.rmii1_txd1 */
+                        AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1)    /* mii1_txd0.rmii1_txd0 */
+                        AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE1)       /* mii1_rxd1.rmii1_rxd1 */
+                        AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE1)       /* mii1_rxd0.rmii1_rxd0 */
+                        AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0)     /* mii1_refclk.rmii1_refclk */
+                >;
+        };
+
+        spi1_pins: pinmux_spi1 {
+                pinctrl-single,pins = <
+                        AM33XX_IOPAD(0x964, PIN_INPUT_PULLUP | MUX_MODE4)        /* ecap0_in_pwm0_out.spi1_sclk */
+                        AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE4)        /* uart1_ctsn.spi1_cs0 */
+                        AM33XX_IOPAD(0x968, PIN_INPUT_PULLUP | MUX_MODE4)        /* uart0_ctsn.spi1_d0 */
+                        AM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE4)        /* uart0_rtsn.spi1_d1 */
+                >;
+        };
+};
+
+&davinci_mdio {
+        phy0: ethernet-phy@4 {
+                reg = <4>;
+        };
+};
+
+&cpsw_emac0 {
+        status = "okay";
+        phy-handle = <&phy0>;
+        phy-mode = "rmii";
+};
+
+&cpsw_emac1 {
+        status = "disabled";
+};
diff --git a/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts b/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts
index f82233cd18e0..5a58efc0c874 100644
--- a/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts
+++ b/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts
@@ -422,18 +422,26 @@
         pinctrl-names = "default";
         pinctrl-0 = <&davinci_mdio_default>;
         status = "okay";
+
+        ethphy0: ethernet-phy@4 {
+                reg = <4>;
+        };
+
+        ethphy1: ethernet-phy@5 {
+                reg = <5>;
+        };
 };
 
 &cpsw_emac0 {
         status = "okay";
-        phy_id = <&davinci_mdio>, <4>;
+        phy-handle = <&ethphy0>;
         phy-mode = "rmii";
         dual_emac_res_vlan = <1>;
 };
 
 &cpsw_emac1 {
         status = "okay";
-        phy_id = <&davinci_mdio>, <5>;
+        phy-handle = <&ethphy1>;
         phy-mode = "rmii";
         dual_emac_res_vlan = <2>;
 };
diff --git a/arch/arm/boot/dts/am335x-nano.dts b/arch/arm/boot/dts/am335x-nano.dts
index 946d7069f417..9c9143ed4003 100644
--- a/arch/arm/boot/dts/am335x-nano.dts
+++ b/arch/arm/boot/dts/am335x-nano.dts
@@ -380,16 +380,24 @@
 
 &davinci_mdio {
         status = "okay";
+
+        ethphy0: ethernet-phy@0 {
+                reg = <0>;
+        };
+
+        ethphy1: ethernet-phy@1 {
+                reg = <1>;
+        };
 };
 
 &cpsw_emac0 {
-        phy_id = <&davinci_mdio>, <0>;
+        phy-handle = <&ethphy0>;
         phy-mode = "mii";
         dual_emac_res_vlan = <1>;
 };
 
 &cpsw_emac1 {
-        phy_id = <&davinci_mdio>, <1>;
+        phy-handle = <&ethphy1>;
         phy-mode = "mii";
         dual_emac_res_vlan = <2>;
 };
diff --git a/arch/arm/boot/dts/am335x-osd3358-sm-red.dts b/arch/arm/boot/dts/am335x-osd3358-sm-red.dts
index 4d969013f99a..85cd1d0a73ca 100644
--- a/arch/arm/boot/dts/am335x-osd3358-sm-red.dts
+++ b/arch/arm/boot/dts/am335x-osd3358-sm-red.dts
@@ -161,7 +161,7 @@
                 invensense,key = [4e cc 7e eb f6 1e 35 22 00 34 0d 65 32 e9 94 89];*/
         };
 
-        bmp280: pressure@78 {
+        bmp280: pressure@76 {
                 compatible = "bosch,bmp280";
                 reg = <0x76>;
         };
@@ -424,7 +424,7 @@
 };
 
 &cpsw_emac0 {
-        phy_id = <&davinci_mdio>, <4>;
+        phy-handle = <&ethphy0>;
         phy-mode = "rgmii-txid";
 };
 
@@ -441,6 +441,10 @@
         pinctrl-0 = <&davinci_mdio_default>;
         pinctrl-1 = <&davinci_mdio_sleep>;
         status = "okay";
+
+        ethphy0: ethernet-phy@4 {
+                reg = <4>;
+        };
 };
 
 &mmc1 {
diff --git a/arch/arm/boot/dts/am335x-pdu001.dts b/arch/arm/boot/dts/am335x-pdu001.dts
index 1ad530a39a95..6dd9d487aaeb 100644
--- a/arch/arm/boot/dts/am335x-pdu001.dts
+++ b/arch/arm/boot/dts/am335x-pdu001.dts
@@ -373,7 +373,7 @@
         ti,pindir-d0-out-d1-in;
         status = "okay";
 
-        cfaf240320a032t {
+        display-controller@0 {
                 compatible = "orisetech,otm3225a";
                 reg = <0>;
                 spi-max-frequency = <1000000>;
@@ -533,16 +533,24 @@
         pinctrl-names = "default";
         pinctrl-0 = <&davinci_mdio_default>;
         status = "okay";
+
+        ethphy0: ethernet-phy@0 {
+                reg = <0>;
+        };
+
+        ethphy1: ethernet-phy@1 {
+                reg = <1>;
+        };
 };
 
 &cpsw_emac0 {
-        phy_id = <&davinci_mdio>, <0>;
+        phy-handle = <&ethphy0>;
         phy-mode = "mii";
         dual_emac_res_vlan = <1>;
 };
 
 &cpsw_emac1 {
-        phy_id = <&davinci_mdio>, <1>;
+        phy-handle = <&ethphy1>;
         phy-mode = "mii";
         dual_emac_res_vlan = <2>;
 };
diff --git a/arch/arm/boot/dts/am335x-pepper.dts b/arch/arm/boot/dts/am335x-pepper.dts
index 9fb7426070ce..6be79b8349ac 100644
--- a/arch/arm/boot/dts/am335x-pepper.dts
+++ b/arch/arm/boot/dts/am335x-pepper.dts
@@ -265,13 +265,13 @@
 /* Ethernet */
 &cpsw_emac0 {
         status = "okay";
-        phy_id = <&davinci_mdio>, <0>;
+        phy-handle = <&ethphy0>;
         phy-mode = "rgmii";
 };
 
 &cpsw_emac1 {
         status = "okay";
-        phy_id = <&davinci_mdio>, <1>;
+        phy-handle = <&ethphy1>;
         phy-mode = "rgmii";
 };
 
@@ -279,6 +279,14 @@
         status = "okay";
         pinctrl-names = "default";
         pinctrl-0 = <&mdio_pins>;
+
+        ethphy0: ethernet-phy@0 {
+                reg = <0>;
+        };
+
+        ethphy1: ethernet-phy@1 {
+                reg = <1>;
+        };
 };
 
 &mac {
diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe.dts b/arch/arm/boot/dts/am335x-sancloud-bbe.dts
index 7b8e7417a11e..35527fdf56cc 100644
--- a/arch/arm/boot/dts/am335x-sancloud-bbe.dts
+++ b/arch/arm/boot/dts/am335x-sancloud-bbe.dts
@@ -103,10 +103,14 @@
         pinctrl-0 = <&davinci_mdio_default>;
         pinctrl-1 = <&davinci_mdio_sleep>;
         status = "okay";
+
+        ethphy0: ethernet-phy@0 {
+                reg = <0>;
+        };
 };
 
 &cpsw_emac0 {
-        phy_id = <&davinci_mdio>, <0>;
+        phy-handle = <&ethphy0>;
         phy-mode = "rgmii-txid";
 };
 
diff --git a/arch/arm/boot/dts/am335x-shc.dts b/arch/arm/boot/dts/am335x-shc.dts
index 4f6a286ea293..1d925ed2b102 100644
--- a/arch/arm/boot/dts/am335x-shc.dts
+++ b/arch/arm/boot/dts/am335x-shc.dts
@@ -206,7 +206,6 @@
         status = "okay";
         slaves = <1>;
         cpsw_emac0: slave@4a100200  {
-                phy_id = <&davinci_mdio>, <0>;
                 phy-mode = "mii";
                 phy-handle = <&ethernetphy0>;
         };
diff --git a/arch/arm/boot/dts/am3517-evm-ui.dtsi b/arch/arm/boot/dts/am3517-evm-ui.dtsi
new file mode 100644
index 000000000000..e841918c1c26
--- /dev/null
+++ b/arch/arm/boot/dts/am3517-evm-ui.dtsi
@@ -0,0 +1,220 @@
+/*
+ * Copyright (C) 2018 Logic PD, Inc - http://www.logicpd.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <dt-bindings/input/input.h>
+
+/ {
+        codec1 {
+                compatible = "simple-audio-card";
+                simple-audio-card,name = "tlv320aic23-hifi";
+
+                simple-audio-card,widgets =
+                        "Microphone", "Mic In",
+                        "Line", "Line In",
+                        "Line", "Line Out";
+
+                simple-audio-card,routing =
+                        "Line Out", "LOUT",
+                        "Line Out", "ROUT",
+                        "LLINEIN", "Line In",
+                        "RLINEIN", "Line In",
+                        "MICIN", "Mic In";
+
+                simple-audio-card,format = "i2s";
+                simple-audio-card,bitclock-master = <&sound_master>;
+                simple-audio-card,frame-master = <&sound_master>;
+
+                simple-audio-card,cpu {
+                        sound-dai = <&mcbsp1>;
+                };
+
+                sound_master: simple-audio-card,codec {
+                        sound-dai = <&tlv320aic23_1>;
+                        system-clock-frequency = <12000000>;
+                };
+        };
+
+        codec2 {
+                compatible = "simple-audio-card";
+                simple-audio-card,name = "tlv320aic23-hifi";
+
+                simple-audio-card,widgets =
+                        "Microphone", "Mic In",
+                        "Line", "Line In",
+                        "Line", "Line Out";
+
+                simple-audio-card,routing =
+                        "Line Out", "LOUT",
+                        "Line Out", "ROUT",
+                        "LLINEIN", "Line In",
+                        "RLINEIN", "Line In",
+                        "MICIN", "Mic In";
+
+                simple-audio-card,format = "i2s";
+                simple-audio-card,bitclock-master = <&sound_master2>;
+                simple-audio-card,frame-master = <&sound_master2>;
+
+                simple-audio-card,cpu {
+                        sound-dai = <&mcbsp2>;
+                };
+
+                sound_master2: simple-audio-card,codec {
+                        sound-dai = <&tlv320aic23_2>;
+                        system-clock-frequency = <12000000>;
+                };
+        };
+
+        expander-keys {
+                compatible = "gpio-keys-polled";
+                poll-interval = <100>;
+
+                record {
+                        label = "Record";
+                        /* linux,code = <BTN_0>; */
+                        gpios = <&tca6416_2 15 GPIO_ACTIVE_LOW>;
+                };
+
+                play {
+                        label = "Play";
+                        linux,code = <KEY_PLAY>;
+                        gpios = <&tca6416_2 14 GPIO_ACTIVE_LOW>;
+                };
+
+                Stop {
+                        label = "Stop";
+                        linux,code = <KEY_STOP>;
+                        gpios = <&tca6416_2 13 GPIO_ACTIVE_LOW>;
+                };
+
+                fwd {
+                        label = "FWD";
+                        linux,code = <KEY_FASTFORWARD>;
+                        gpios = <&tca6416_2 12 GPIO_ACTIVE_LOW>;
+                };
+
+                rwd {
+                        label = "RWD";
+                        linux,code = <KEY_REWIND>;
+                        gpios = <&tca6416_2 11 GPIO_ACTIVE_LOW>;
+                };
+
+                shift {
+                        label = "Shift";
+                        linux,code = <KEY_LEFTSHIFT>;
+                        gpios = <&tca6416_2 10 GPIO_ACTIVE_LOW>;
+                };
+
+                Mode {
+                        label = "Mode";
+                        linux,code = <BTN_MODE>;
+                        gpios = <&tca6416_2 9 GPIO_ACTIVE_LOW>;
+                };
+
+                Menu {
+                        label = "Menu";
+                        linux,code = <KEY_MENU>;
+                        gpios = <&tca6416_2 8 GPIO_ACTIVE_LOW>;
+                };
+
+                Up {
+                        label = "Up";
+                        linux,code = <KEY_UP>;
+                        gpios = <&tca6416_2 7 GPIO_ACTIVE_LOW>;
+                };
+
+                Down {
+                        label = "Down";
+                        linux,code = <KEY_DOWN>;
+                        gpios = <&tca6416_2 6 GPIO_ACTIVE_LOW>;
+                };
+        };
+};
+
+&i2c2 {
+        /* Audio codecs */
+        tlv320aic23_1: codec@1a {
+                compatible = "ti,tlv320aic23";
+                reg = <0x1a>;
+                #sound-dai-cells= <0>;
+                status = "okay";
+        };
+
+        tlv320aic23_2: codec@1b {
+                compatible = "ti,tlv320aic23";
+                reg = <0x1b>;
+                #sound-dai-cells= <0>;
+                status = "okay";
+        };
+};
+
+&i2c3 {
+        /* Audio codecs */
+        tlv320aic23_3: codec@1a {
+                compatible = "ti,tlv320aic23";
+                reg = <0x1a>;
+                #sound-dai-cells= <0>;
+                status = "okay";
+        };
+
+        /* GPIO Expanders */
+        tca6416_2: gpio@20 {
+                compatible = "ti,tca6416";
+                reg = <0x20>;
+                gpio-controller;
+                #gpio-cells = <2>;
+                vcc-supply = <&vdd_io_reg>;
+        };
+
+        tca6416_3: gpio@21 {
+                compatible = "ti,tca6416";
+                reg = <0x21>;
+                gpio-controller;
+                #gpio-cells = <2>;
+                vcc-supply = <&vdd_io_reg>;
+        };
+
+        /* TVP5146 Analog Video decoder input */
+        tvp5146@5c {
+                compatible = "ti,tvp5146m2";
+                reg = <0x5c>;
+        };
+};
+
+&mcbsp1 {
+        status = "ok";
+        #sound-dai-cells = <0>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&mcbsp1_pins>;
+};
+
+&mcbsp2 {
+        status = "ok";
+        #sound-dai-cells = <0>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&mcbsp2_pins>;
+};
+
+&omap3_pmx_core {
+        mcbsp1_pins: pinmux_mcbsp1_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE0)       /* mcbsp1_dx.mcbsp1_dx */
+                        OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT | MUX_MODE0)        /* mcbsp1_dx.mcbsp1_dr */
+                        OMAP3_CORE1_IOPAD(0x2196, PIN_INPUT | MUX_MODE0)        /* mcbsp_clks.mcbsp1_fsx */
+                        OMAP3_CORE1_IOPAD(0x2198, PIN_INPUT | MUX_MODE0)        /* mcbsp1_clkx.mcbsp1_clkx */
+                >;
+        };
+
+        mcbsp2_pins: pinmux_mcbsp2_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0)        /* mcbsp2_fsx.mcbsp2_fsx */
+                        OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0)        /* mcbsp2_clkx.mcbsp2_clkx */
+                        OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0)        /* mcbsp2_dr.mcbsp2.dr */
+                        OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0)       /* mcbsp2_dx.mcbsp2_dx */
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts
index 1d158cfda15f..d4d33cd7adad 100644
--- a/arch/arm/boot/dts/am3517-evm.dts
+++ b/arch/arm/boot/dts/am3517-evm.dts
@@ -9,6 +9,7 @@
 
 #include "am3517.dtsi"
 #include "am3517-som.dtsi"
+#include "am3517-evm-ui.dtsi"
 #include <dt-bindings/input/input.h>
 
 / {
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index d4b7c59eec68..a68e89dae7a1 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -1101,7 +1101,7 @@
                         };
                 };
 
-                qspi: qspi@47900000 {
+                qspi: spi@47900000 {
                         compatible = "ti,am4372-qspi";
                         reg = <0x47900000 0x100>,
                               <0x30000000 0x4000000>;
diff --git a/arch/arm/boot/dts/am437x-cm-t43.dts b/arch/arm/boot/dts/am437x-cm-t43.dts
index bff5abe69bdb..4fcf647815a2 100644
--- a/arch/arm/boot/dts/am437x-cm-t43.dts
+++ b/arch/arm/boot/dts/am437x-cm-t43.dts
@@ -339,16 +339,24 @@
         pinctrl-names = "default";
         pinctrl-0 = <&davinci_mdio_default>;
         status = "okay";
+
+        ethphy0: ethernet-phy@0 {
+                reg = <0>;
+        };
+
+        ethphy1: ethernet-phy@1 {
+                reg = <1>;
+        };
 };
 
 &cpsw_emac0 {
-        phy_id = <&davinci_mdio>, <0>;
+        phy-handle = <&ethphy0>;
         phy-mode = "rgmii-txid";
         dual_emac_res_vlan = <1>;
 };
 
 &cpsw_emac1 {
-        phy_id = <&davinci_mdio>, <1>;
+        phy-handle = <&ethphy1>;
         phy-mode = "rgmii-txid";
         dual_emac_res_vlan = <2>;
 };
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
index 5b97c20c5ed4..601bf4daaeb7 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -831,10 +831,14 @@
         pinctrl-0 = <&davinci_mdio_default>;
         pinctrl-1 = <&davinci_mdio_sleep>;
         status = "okay";
+
+        ethphy0: ethernet-phy@0 {
+                reg = <0>;
+        };
 };
 
 &cpsw_emac0 {
-        phy_id = <&davinci_mdio>, <0>;
+        phy-handle = <&ethphy0>;
         phy-mode = "rgmii";
 };
 
diff --git a/arch/arm/boot/dts/am437x-idk-evm.dts b/arch/arm/boot/dts/am437x-idk-evm.dts
index 20132477a871..bb285409473e 100644
--- a/arch/arm/boot/dts/am437x-idk-evm.dts
+++ b/arch/arm/boot/dts/am437x-idk-evm.dts
@@ -499,10 +499,14 @@
         pinctrl-0 = <&davinci_mdio_default>;
         pinctrl-1 = <&davinci_mdio_sleep>;
         status = "okay";
+
+        ethphy0: ethernet-phy@0 {
+                reg = <0>;
+        };
 };
 
 &cpsw_emac0 {
-        phy_id = <&davinci_mdio>, <0>;
+        phy-handle = <&ethphy0>;
         phy-mode = "rgmii";
 };
 
diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts
index d4be3fd0b6f4..088cba09d34d 100644
--- a/arch/arm/boot/dts/am437x-sk-evm.dts
+++ b/arch/arm/boot/dts/am437x-sk-evm.dts
@@ -799,16 +799,24 @@
         pinctrl-0 = <&davinci_mdio_default>;
         pinctrl-1 = <&davinci_mdio_sleep>;
         status = "okay";
+
+        ethphy0: ethernet-phy@4 {
+                reg = <4>;
+        };
+
+        ethphy1: ethernet-phy@5 {
+                reg = <5>;
+        };
 };
 
 &cpsw_emac0 {
-        phy_id = <&davinci_mdio>, <4>;
+        phy-handle = <&ethphy0>;
         phy-mode = "rgmii";
         dual_emac_res_vlan = <1>;
 };
 
 &cpsw_emac1 {
-        phy_id = <&davinci_mdio>, <5>;
+        phy-handle = <&ethphy1>;
         phy-mode = "rgmii";
         dual_emac_res_vlan = <2>;
 };
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index 6502d3397653..4ea753b3ee43 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -575,10 +575,14 @@
         pinctrl-0 = <&davinci_mdio_default>;
         pinctrl-1 = <&davinci_mdio_sleep>;
         status = "okay";
+
+        ethphy0: ethernet-phy@16 {
+                reg = <16>;
+        };
 };
 
 &cpsw_emac0 {
-        phy_id = <&davinci_mdio>, <16>;
+        phy-handle = <&ethphy0>;
         phy-mode = "rmii";
 };
 
diff --git a/arch/arm/boot/dts/am571x-idk.dts b/arch/arm/boot/dts/am571x-idk.dts
index d9a2049a1ea8..6432309b39e3 100644
--- a/arch/arm/boot/dts/am571x-idk.dts
+++ b/arch/arm/boot/dts/am571x-idk.dts
@@ -64,6 +64,82 @@
                         linux,default-trigger = "mmc0";
                 };
         };
+
+        idk-leds {
+                status = "disabled";
+                compatible = "gpio-leds";
+                red0-led {
+                        label = "idk:red0";
+                        gpios = <&gpio6 19 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                green0-led {
+                        label = "idk:green0";
+                        gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                blue0-led {
+                        label = "idk:blue0";
+                        gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                red1-led {
+                        label = "idk:red1";
+                        gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                green1-led {
+                        label = "idk:green1";
+                        gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                blue1-led {
+                        label = "idk:blue1";
+                        gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                red2-led {
+                        label = "idk:red2";
+                        gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                green2-led {
+                        label = "idk:green2";
+                        gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                blue2-led {
+                        label = "idk:blue2";
+                        gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                red3-led {
+                        label = "idk:red3";
+                        gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                green3-led {
+                        label = "idk:green3";
+                        gpios = <&gpio7 25 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                blue3-led {
+                        label = "idk:blue3";
+                        gpios = <&gpio7 24 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+        };
 };
 
 &extcon_usb2 {
@@ -71,6 +147,10 @@
         vbus-gpio = <&gpio7 22 GPIO_ACTIVE_HIGH>;
 };
 
+&sn65hvs882 {
+        load-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
+};
+
 &mailbox5 {
         status = "okay";
         mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
@@ -114,7 +194,3 @@
         pinctrl-1 = <&mmc2_pins_hs>;
         pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>;
 };
-
-&cpu0 {
-        vdd-supply = <&smps12_reg>;
-};
diff --git a/arch/arm/boot/dts/am572x-idk-common.dtsi b/arch/arm/boot/dts/am572x-idk-common.dtsi
index 784639ddf451..a064f13b3880 100644
--- a/arch/arm/boot/dts/am572x-idk-common.dtsi
+++ b/arch/arm/boot/dts/am572x-idk-common.dtsi
@@ -55,6 +55,82 @@
                         linux,default-trigger = "mmc0";
                 };
         };
+
+        idk-leds {
+                status = "disabled";
+                compatible = "gpio-leds";
+                red0-led {
+                        label = "idk:red0";
+                        gpios = <&gpio6 19 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                green0-led {
+                        label = "idk:green0";
+                        gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                blue0-led {
+                        label = "idk:blue0";
+                        gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                red1-led {
+                        label = "idk:red1";
+                        gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                green1-led {
+                        label = "idk:green1";
+                        gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                blue1-led {
+                        label = "idk:blue1";
+                        gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                red2-led {
+                        label = "idk:red2";
+                        gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                green2-led {
+                        label = "idk:green2";
+                        gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                blue2-led {
+                        label = "idk:blue2";
+                        gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                red3-led {
+                        label = "idk:red3";
+                        gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                green3-led {
+                        label = "idk:green3";
+                        gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                blue3-led {
+                        label = "idk:blue3";
+                        gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+        };
 };
 
 &extcon_usb2 {
diff --git a/arch/arm/boot/dts/am572x-idk.dts b/arch/arm/boot/dts/am572x-idk.dts
index 3ef9111d0e8b..b2fb6e097be7 100644
--- a/arch/arm/boot/dts/am572x-idk.dts
+++ b/arch/arm/boot/dts/am572x-idk.dts
@@ -36,7 +36,3 @@
         pinctrl-1 = <&mmc2_pins_hs>;
         pinctrl-2 = <&mmc2_pins_ddr_rev20>;
 };
-
-&cpu0 {
-        vdd-supply = <&smps12_reg>;
-};
diff --git a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
index 203266f88480..4748ce8747ad 100644
--- a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
+++ b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
@@ -518,7 +518,7 @@
         };
 
         /* touch controller */
-        ads7846@0 {
+        touchscreen@1 {
                 pinctrl-names = "default";
                 pinctrl-0 = <&ads7846_pins>;
 
@@ -558,13 +558,13 @@
 };
 
 &cpsw_emac0 {
-        phy_id = <&davinci_mdio>, <0>;
+        phy-handle = <&ethphy0>;
         phy-mode = "rgmii-txid";
         dual_emac_res_vlan = <0>;
 };
 
 &cpsw_emac1 {
-        phy_id = <&davinci_mdio>, <1>;
+        phy-handle = <&ethphy1>;
         phy-mode = "rgmii-txid";
         dual_emac_res_vlan = <1>;
 };
@@ -573,6 +573,14 @@
         pinctrl-names = "default", "sleep";
         pinctrl-0 = <&davinci_mdio_pins_default>;
         pinctrl-1 = <&davinci_mdio_pins_sleep>;
+
+        ethphy0: ethernet-phy@0 {
+                reg = <0>;
+        };
+
+        ethphy1: ethernet-phy@1 {
+                reg = <1>;
+        };
 };
 
 &usb2_phy1 {
diff --git a/arch/arm/boot/dts/am57xx-idk-common.dtsi b/arch/arm/boot/dts/am57xx-idk-common.dtsi
index c9063ffca524..f7bd26458915 100644
--- a/arch/arm/boot/dts/am57xx-idk-common.dtsi
+++ b/arch/arm/boot/dts/am57xx-idk-common.dtsi
@@ -372,17 +372,27 @@
 };
 
 &cpsw_emac0 {
-        phy_id = <&davinci_mdio>, <0>;
+        phy-handle = <&ethphy0>;
         phy-mode = "rgmii";
         dual_emac_res_vlan = <1>;
 };
 
 &cpsw_emac1 {
-        phy_id = <&davinci_mdio>, <1>;
+        phy-handle = <&ethphy1>;
         phy-mode = "rgmii";
         dual_emac_res_vlan = <2>;
 };
 
+&davinci_mdio {
+        ethphy0: ethernet-phy@0 {
+                reg = <0>;
+        };
+
+        ethphy1: ethernet-phy@1 {
+                reg = <1>;
+        };
+};
+
 &usb2_phy1 {
         phy-supply = <&ldousb_reg>;
 };
@@ -478,3 +488,7 @@
                 };
         };
 };
+
+&cpu0 {
+        vdd-supply = <&smps12_reg>;
+};
diff --git a/arch/arm/boot/dts/arm-realview-eb.dtsi b/arch/arm/boot/dts/arm-realview-eb.dtsi
index a917cf8825ca..0e4c7c4c8c09 100644
--- a/arch/arm/boot/dts/arm-realview-eb.dtsi
+++ b/arch/arm/boot/dts/arm-realview-eb.dtsi
@@ -371,7 +371,7 @@
                         clock-names = "uartclk", "apb_pclk";
                 };
 
-                ssp: ssp@1000d000 {
+                ssp: spi@1000d000 {
                         compatible = "arm,pl022", "arm,primecell";
                         reg = <0x1000d000 0x1000>;
                         clocks = <&sspclk>, <&pclk>;
diff --git a/arch/arm/boot/dts/arm-realview-pb1176.dts b/arch/arm/boot/dts/arm-realview-pb1176.dts
index f935b72d3d96..f2a1d25eb6cf 100644
--- a/arch/arm/boot/dts/arm-realview-pb1176.dts
+++ b/arch/arm/boot/dts/arm-realview-pb1176.dts
@@ -380,7 +380,7 @@
                         clock-names = "apb_pclk";
                 };
 
-                pb1176_ssp: ssp@1010b000 {
+                pb1176_ssp: spi@1010b000 {
                         compatible = "arm,pl022", "arm,primecell";
                         reg = <0x1010b000 0x1000>;
                         interrupt-parent = <&intc_dc1176>;
diff --git a/arch/arm/boot/dts/arm-realview-pb11mp.dts b/arch/arm/boot/dts/arm-realview-pb11mp.dts
index 36203288de42..7f9cbdf33a51 100644
--- a/arch/arm/boot/dts/arm-realview-pb11mp.dts
+++ b/arch/arm/boot/dts/arm-realview-pb11mp.dts
@@ -523,7 +523,7 @@
                         clock-names = "uartclk", "apb_pclk";
                 };
 
-                ssp@1000d000 {
+                spi@1000d000 {
                         compatible = "arm,pl022", "arm,primecell";
                         reg = <0x1000d000 0x1000>;
                         interrupt-parent = <&intc_pb11mp>;
diff --git a/arch/arm/boot/dts/arm-realview-pbx.dtsi b/arch/arm/boot/dts/arm-realview-pbx.dtsi
index 10868ba3277f..a5676697ff3b 100644
--- a/arch/arm/boot/dts/arm-realview-pbx.dtsi
+++ b/arch/arm/boot/dts/arm-realview-pbx.dtsi
@@ -362,7 +362,7 @@
                         clock-names = "uartclk", "apb_pclk";
                 };
 
-                ssp: ssp@1000d000 {
+                ssp: spi@1000d000 {
                         compatible = "arm,pl022", "arm,primecell";
                         reg = <0x1000d000 0x1000>;
                         clocks = <&sspclk>, <&pclk>;
diff --git a/arch/arm/boot/dts/armada-385-db-88f6820-amc.dts b/arch/arm/boot/dts/armada-385-db-88f6820-amc.dts
new file mode 100644
index 000000000000..7881df3b28a0
--- /dev/null
+++ b/arch/arm/boot/dts/armada-385-db-88f6820-amc.dts
@@ -0,0 +1,155 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Device Tree file for Marvell Armada 385 AMC board
+ * (DB-88F6820-AMC)
+ *
+ * Copyright (C) 2017 Allied Telesis Labs
+ */
+
+/dts-v1/;
+#include "armada-385.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+        model = "Marvell Armada 385 AMC";
+        compatible = "marvell,a385-db-amc", "marvell,armada385", "marvell,armada380";
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+
+        aliases {
+                ethernet0 = &eth0;
+                ethernet1 = &eth1;
+                spi1 = &spi1;
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x80000000>; /* 2GB */
+        };
+
+        soc {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+                          MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
+        };
+};
+
+&i2c0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c0_pins>;
+        status = "okay";
+};
+
+&uart0 {
+        /*
+         * Exported on the micro USB connector CON3
+         * through an FTDI
+         */
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart0_pins>;
+        status = "okay";
+};
+
+
+&eth0 {
+        pinctrl-names = "default";
+        /*
+         * The Reference Clock 0 is used to provide a
+         * clock to the PHY
+         */
+        pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
+        status = "okay";
+        phy = <&phy0>;
+        phy-mode = "rgmii-id";
+};
+
+&eth2 {
+        status = "okay";
+        phy = <&phy1>;
+        phy-mode = "sgmii";
+};
+
+&usb0 {
+        status = "okay";
+};
+
+
+
+&mdio {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mdio_pins>;
+
+        phy0: ethernet-phy@1 {
+                reg = <1>;
+        };
+
+        phy1: ethernet-phy@0 {
+                reg = <0>;
+        };
+};
+
+&nand_controller {
+        status = "okay";
+
+        nand@0 {
+                reg = <0>;
+                label = "pxa3xx_nand-0";
+                nand-rb = <0>;
+                nand-on-flash-bbt;
+
+                partitions {
+                        compatible = "fixed-partitions";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        partition@0 {
+                                reg = <0x00000000 0x40000000>;
+                                label = "user";
+                        };
+                };
+        };
+};
+
+&pciec {
+        status = "okay";
+};
+
+&pcie1 {
+        /* Port 0, Lane 0 */
+        status = "okay";
+};
+
+&spi1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&spi1_pins>;
+        status = "okay";
+
+        spi-flash@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "jedec,spi-nor";
+                reg = <0>; /* Chip select 0 */
+                spi-max-frequency = <50000000>;
+                m25p,fast-read;
+
+                partitions {
+                        compatible = "fixed-partitions";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        partition@0 {
+                                reg = <0x00000000 0x00100000>;
+                                label = "u-boot";
+                        };
+                        partition@100000 {
+                                reg = <0x00100000 0x00040000>;
+                                label = "u-boot-env";
+                        };
+                };
+        };
+};
+
+&refclk {
+        clock-frequency = <20000000>;
+};
diff --git a/arch/arm/boot/dts/armada-388-clearfog.dtsi b/arch/arm/boot/dts/armada-388-clearfog.dtsi
index 7c6ad2afb094..1b0d0680c8b6 100644
--- a/arch/arm/boot/dts/armada-388-clearfog.dtsi
+++ b/arch/arm/boot/dts/armada-388-clearfog.dtsi
@@ -48,7 +48,7 @@
                                              &clearfog_sdhci_cd_pins>;
                                 pinctrl-names = "default";
                                 status = "okay";
-                                vmmc = <&reg_3p3v>;
+                                vmmc-supply = <&reg_3p3v>;
                                 wp-inverted;
                         };
 
diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
index 8d708cc22495..59753470cd34 100644
--- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
+++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
@@ -189,7 +189,7 @@
                                 };
                         };
 
-                        nand: nand@d0000 {
+                        nand_controller: nand-controller@d0000 {
                                 clocks = <&dfx_coredivclk 0>;
                         };
 
@@ -243,7 +243,7 @@
                         ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
 
                         pp0: packet-processor@0 {
-                                compatible = "marvell,prestera-98dx3236";
+                                compatible = "marvell,prestera-98dx3236", "marvell,prestera";
                                 reg = <0 0x4000000>;
                                 interrupts = <33>, <34>, <35>;
                                 dfx = <&dfx>;
diff --git a/arch/arm/boot/dts/armada-xp-98dx3336.dtsi b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
index 2f5fc67dd6dc..1d9d8a8ea60c 100644
--- a/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
+++ b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi
@@ -35,5 +35,5 @@
 };
 
 &pp0 {
-        compatible = "marvell,prestera-98dx3336";
+        compatible = "marvell,prestera-98dx3336", "marvell,prestera";
 };
diff --git a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
index 7a9e8839880b..48ffdc72bfc7 100644
--- a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
+++ b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi
@@ -49,6 +49,6 @@
 };
 
 &pp0 {
-        compatible = "marvell,prestera-98dx4251";
+        compatible = "marvell,prestera-98dx4251", "marvell,prestera";
         interrupts = <33>, <34>, <35>, <36>;
 };
diff --git a/arch/arm/boot/dts/armada-xp-db-dxbc2.dts b/arch/arm/boot/dts/armada-xp-db-dxbc2.dts
index f42fc6118b7c..8a3aa616bbd0 100644
--- a/arch/arm/boot/dts/armada-xp-db-dxbc2.dts
+++ b/arch/arm/boot/dts/armada-xp-db-dxbc2.dts
@@ -68,14 +68,18 @@
         status = "okay";
 };
 
-&nand {
+&nand_controller {
         status = "okay";
-        label = "pxa3xx_nand-0";
-        num-cs = <1>;
-        marvell,nand-keep-config;
-        nand-on-flash-bbt;
-        nand-ecc-strength = <4>;
-        nand-ecc-step-size = <512>;
+
+        nand@0 {
+                reg = <0>;
+                label = "pxa3xx_nand-0";
+                nand-rb = <0>;
+                marvell,nand-keep-config;
+                nand-on-flash-bbt;
+                nand-ecc-strength = <4>;
+                nand-ecc-step-size = <512>;
+        };
 };
 
 &sdio {
diff --git a/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts b/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts
index 8432f517e346..df048050615f 100644
--- a/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts
+++ b/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts
@@ -67,14 +67,18 @@
         status = "okay";
 };
 
-&nand {
+&nand_controller {
         status = "okay";
-        label = "pxa3xx_nand-0";
-        num-cs = <1>;
-        marvell,nand-keep-config;
-        nand-on-flash-bbt;
-        nand-ecc-strength = <4>;
-        nand-ecc-step-size = <512>;
+
+        nand@0 {
+                reg = <0>;
+                label = "pxa3xx_nand-0";
+                nand-rb = <0>;
+                marvell,nand-keep-config;
+                nand-on-flash-bbt;
+                nand-ecc-strength = <4>;
+                nand-ecc-step-size = <512>;
+        };
 };
 
 &spi0 {
diff --git a/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts b/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts
new file mode 100644
index 000000000000..bdfd8c9f3a7c
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts
@@ -0,0 +1,207 @@
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+#include "aspeed-g5.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+
+/ {
+        model = "HXT StarDragon 4800 REP2 AST2520";
+        compatible = "hxt,stardragon4800-rep2-bmc", "aspeed,ast2500";
+
+        chosen {
+                stdout-path = &uart5;
+                bootargs = "console=ttyS4,115200 earlyprintk";
+        };
+
+        memory@80000000 {
+                reg = <0x80000000 0x40000000>;
+        };
+
+        iio-hwmon {
+                compatible = "iio-hwmon";
+                io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
+                                                <&adc 4>, <&adc 5>, <&adc 6>, <&adc 8>;
+        };
+
+        iio-hwmon-battery {
+                compatible = "iio-hwmon";
+                io-channels = <&adc 7>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                system_fault1 {
+                        label = "System_fault1";
+                        gpios = <&gpio ASPEED_GPIO(I, 3) GPIO_ACTIVE_LOW>;
+                };
+
+                system_fault2 {
+                        label = "System_fault2";
+                        gpios = <&gpio ASPEED_GPIO(I, 2) GPIO_ACTIVE_LOW>;
+                };
+        };
+};
+
+&fmc {
+        status = "okay";
+        flash@0 {
+                status = "okay";
+                m25p,fast-read;
+                label = "bmc";
+#include "openbmc-flash-layout.dtsi"
+        };
+};
+
+&spi1 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_spi1_default>;
+        flash@0 {
+                status = "okay";
+        };
+};
+
+&spi2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_spi2ck_default
+                        &pinctrl_spi2miso_default
+                        &pinctrl_spi2mosi_default
+                        &pinctrl_spi2cs0_default>;
+};
+
+&uart3 {
+        status = "okay";
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>;
+        current-speed = <115200>;
+};
+
+&uart5 {
+        status = "okay";
+};
+
+&mac0 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>;
+};
+
+&mac1 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_rmii2_default>;
+        use-ncsi;
+};
+
+&i2c0 {
+        status = "okay";
+};
+
+&i2c1 {
+        status = "okay";
+
+        tmp421@1e {
+                compatible = "ti,tmp421";
+                reg = <0x1e>;
+        };
+        tmp421@2a {
+                compatible = "ti,tmp421";
+                reg = <0x2a>;
+        };
+        tmp421@1c {
+                compatible = "ti,tmp421";
+                reg = <0x1c>;
+        };
+};
+
+&i2c2 {
+        status = "okay";
+};
+
+&i2c3 {
+        status = "okay";
+};
+
+&i2c4 {
+        status = "okay";
+};
+
+&i2c5 {
+        status = "okay";
+};
+
+&i2c6 {
+        status = "okay";
+
+        tmp421@1f {
+                compatible = "ti,tmp421";
+                reg = <0x1f>;
+        };
+        nvt210@4c {
+                compatible = "nvt210";
+                reg = <0x4c>;
+        };
+        eeprom@50 {
+                compatible = "atmel,24c128";
+                reg = <0x50>;
+                pagesize = <128>;
+        };
+};
+
+&i2c7 {
+        status = "okay";
+};
+
+&i2c8 {
+        status = "okay";
+
+        pca9641@70 {
+                compatible = "nxp,pca9641";
+                reg = <0x70>;
+                i2c-arb {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        eeprom@50 {
+                                compatible = "atmel,24c02";
+                                reg = <0x50>;
+                        };
+                        dps650ab@58 {
+                                compatible = "dps650ab";
+                                reg = <0x58>;
+                        };
+                };
+        };
+};
+
+&i2c9 {
+        status = "okay";
+};
+
+&vuart {
+        status = "okay";
+};
+
+&gfx {
+        status = "okay";
+};
+
+&pinctrl {
+        aspeed,external-nodes = <&gfx &lhc>;
+};
+
+&gpio {
+        pin_gpio_c7 {
+                gpio-hog;
+                gpios = <ASPEED_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
+                output-low;
+                line-name = "BIOS_SPI_MUX_S";
+        };
+        pin_gpio_d1 {
+                gpio-hog;
+                gpios = <ASPEED_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
+                output-high;
+                line-name = "PHY2_RESET_N";
+        };
+};
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
new file mode 100644
index 000000000000..f8e7b71af7e6
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0+
+// Copyright (c) 2018 Facebook Inc.
+// Author: Vijay Khemka <vijaykhemka@fb.com>
+/dts-v1/;
+
+#include "aspeed-g5.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+
+/ {
+        model = "Facebook TiogaPass BMC";
+        compatible = "facebook,tiogapass-bmc", "aspeed,ast2500";
+        aliases {
+                serial0 = &uart1;
+                serial4 = &uart5;
+        };
+        chosen {
+                stdout-path = &uart5;
+                bootargs = "console=ttyS4,115200 earlyprintk";
+        };
+
+        memory@80000000 {
+                reg = <0x80000000 0x20000000>;
+        };
+};
+
+&fmc {
+        status = "okay";
+        flash@0 {
+                status = "okay";
+                m25p,fast-read;
+#include "openbmc-flash-layout.dtsi"
+        };
+};
+
+&spi1 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_spi1_default>;
+        flash@0 {
+                status = "okay";
+                m25p,fast-read;
+                label = "pnor";
+        };
+};
+
+&uart1 {
+        // Host Console
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_txd1_default
+                     &pinctrl_rxd1_default>;
+};
+
+&uart5 {
+        // BMC Console
+        status = "okay";
+};
+
+&mac0 {
+        status = "okay";
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_rmii1_default>;
+        use-ncsi;
+};
+
+&i2c0 {
+        status = "okay";
+        //Airmax Conn B, CPU0 PIROM, CPU1 PIROM
+};
+
+&i2c1 {
+        status = "okay";
+        //X24 Riser
+};
+
+&i2c2 {
+        status = "okay";
+        // Mezz Management SMBus
+};
+
+&i2c3 {
+        status = "okay";
+        // SMBus to Board ID EEPROM
+};
+
+&i2c4 {
+        status = "okay";
+        // BMC Debug Header
+};
+
+&i2c5 {
+        status = "okay";
+        // CPU Voltage regulators
+};
+
+&i2c6 {
+        status = "okay";
+        tpm@20 {
+                compatible = "infineon,slb9645tt";
+                reg = <0x20>;
+        };
+        tmp421@4e {
+                compatible = "ti,tmp421";
+                reg = <0x4e>;
+        };
+        tmp421@4f {
+                compatible = "ti,tmp421";
+                reg = <0x4f>;
+        };
+        eeprom@54 {
+                compatible = "atmel,24c64";
+                reg = <0x54>;
+                pagesize = <32>;
+        };
+};
+
+&i2c7 {
+        status = "okay";
+        //HSC, AirMax Conn A
+};
+
+&i2c8 {
+        status = "okay";
+        //Mezz Sensor SMBus
+};
+
+&i2c9 {
+        status = "okay";
+        //USB Debug Connector
+};
+
+&pwm_tacho {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>;
+        fan@0 {
+                reg = <0x00>;
+                aspeed,fan-tach-ch = /bits/ 8 <0x00>;
+        };
+
+        fan@1 {
+                reg = <0x00>;
+                aspeed,fan-tach-ch = /bits/ 8 <0x01>;
+        };
+};
diff --git a/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts b/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts
index 76aa6ea1f988..385c0f4b69ee 100644
--- a/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts
@@ -7,6 +7,25 @@
         model = "Quanta Q71L BMC";
         compatible = "quanta,q71l-bmc", "aspeed,ast2400";
 
+        aliases {
+                i2c14 = &i2c_pcie2;
+                i2c15 = &i2c_pcie3;
+                i2c16 = &i2c_pcie6;
+                i2c17 = &i2c_pcie7;
+                i2c18 = &i2c_pcie1;
+                i2c19 = &i2c_pcie4;
+                i2c20 = &i2c_pcie5;
+                i2c21 = &i2c_pcie8;
+                i2c22 = &i2c_pcie9;
+                i2c23 = &i2c_pcie10;
+                i2c24 = &i2c_ssd1;
+                i2c25 = &i2c_ssd2;
+                i2c26 = &i2c_psu4;
+                i2c27 = &i2c_psu1;
+                i2c28 = &i2c_psu3;
+                i2c29 = &i2c_psu2;
+        };
+
         chosen {
                 stdout-path = &uart5;
                 bootargs = "console=ttyS4,115200 earlyprintk";
@@ -93,6 +112,10 @@
                         &pinctrl_ddcclk_default &pinctrl_ddcdat_default>;
 };
 
+&ibt {
+        status = "okay";
+};
+
 &lpc_snoop {
         status = "okay";
         snoop-ports = <0x80>;
@@ -299,24 +322,44 @@
                         #address-cells = <1>;
                         #size-cells = <0>;
                         reg = <0>;
+
+                        psu@59 {
+                                compatible = "pmbus";
+                                reg = <0x59>;
+                        };
                 };
 
                 i2c_psu1: i2c@1 {
                         #address-cells = <1>;
                         #size-cells = <0>;
                         reg = <1>;
+
+                        psu@58 {
+                                compatible = "pmbus";
+                                reg = <0x58>;
+                        };
                 };
 
                 i2c_psu3: i2c@2 {
                         #address-cells = <1>;
                         #size-cells = <0>;
                         reg = <2>;
+
+                        psu@58 {
+                                compatible = "pmbus";
+                                reg = <0x58>;
+                        };
                 };
 
                 i2c_psu2: i2c@3 {
                         #address-cells = <1>;
                         #size-cells = <0>;
                         reg = <3>;
+
+                        psu@59 {
+                                compatible = "pmbus";
+                                reg = <0x59>;
+                        };
                 };
         };
 
@@ -345,6 +388,10 @@
         status = "okay";
 };
 
+&adc {
+        status = "okay";
+};
+
 &pwm_tacho {
         status = "okay";
 
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index b23a983f95a5..69f6b9d2e7e7 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -350,7 +350,7 @@
                                 status = "disabled";
                         };
 
-                        i2c: i2c@1e78a000 {
+                        i2c: bus@1e78a000 {
                                 compatible = "simple-bus";
                                 #address-cells = <1>;
                                 #size-cells = <1>;
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 87fdc146ff52..d107459fc0f8 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -410,7 +410,7 @@
                                 status = "disabled";
                         };
 
-                        i2c: i2c@1e78a000 {
+                        i2c: bus@1e78a000 {
                                 compatible = "simple-bus";
                                 #address-cells = <1>;
                                 #size-cells = <1>;
diff --git a/arch/arm/boot/dts/at91-dvk_su60_somc.dtsi b/arch/arm/boot/dts/at91-dvk_su60_somc.dtsi
index bb86f17ed5ed..21876da7c442 100644
--- a/arch/arm/boot/dts/at91-dvk_su60_somc.dtsi
+++ b/arch/arm/boot/dts/at91-dvk_su60_somc.dtsi
@@ -70,9 +70,9 @@
 &i2c1 {
         status = "okay";
 
-        eeprom@87 {
+        eeprom@57 {
                 compatible = "giantec,gt24c32a", "atmel,24c32";
-                reg = <87>;
+                reg = <0x57>;
                 pagesize = <32>;
         };
 };
diff --git a/arch/arm/boot/dts/at91-dvk_su60_somc_lcm.dtsi b/arch/arm/boot/dts/at91-dvk_su60_somc_lcm.dtsi
index 4b9176dc5d02..df0f0cc575c1 100644
--- a/arch/arm/boot/dts/at91-dvk_su60_somc_lcm.dtsi
+++ b/arch/arm/boot/dts/at91-dvk_su60_somc_lcm.dtsi
@@ -59,9 +59,9 @@
 &i2c1 {
         status = "okay";
 
-        ft5426@56 {
+        ft5426@38 {
                 compatible = "focaltech,ft5426", "edt,edt-ft5406";
-                reg = <56>;
+                reg = <0x38>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&pinctrl_lcd_ctp_int>;
 
diff --git a/arch/arm/boot/dts/at91-nattis-2-natte-2.dts b/arch/arm/boot/dts/at91-nattis-2-natte-2.dts
index af9f38456d04..911d2c7c1500 100644
--- a/arch/arm/boot/dts/at91-nattis-2-natte-2.dts
+++ b/arch/arm/boot/dts/at91-nattis-2-natte-2.dts
@@ -16,46 +16,6 @@
         compatible = "axentia,nattis-2", "axentia,natte-2", "axentia,linea",
                      "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
 
-        ahb {
-                apb {
-                        pinctrl@fffff200 {
-                                nattis {
-                                        pinctrl_usba_vbus: usba_vbus {
-                                                atmel,pins =
-                                                        <AT91_PIOD 28
-                                                         AT91_PERIPH_GPIO
-                                                         AT91_PINCTRL_DEGLITCH>;
-                                        };
-
-                                        pinctrl_mmc0_cd: mmc0_cd {
-                                                atmel,pins =
-                                                        <AT91_PIOD 5
-                                                         AT91_PERIPH_GPIO
-                                                         AT91_PINCTRL_PULL_UP_DEGLITCH>;
-                                        };
-
-                                        pinctrl_lcd_prlud0: lcd_prlud0 {
-                                                atmel,pins =
-                                                        <AT91_PIOA 21
-                                                         AT91_PERIPH_GPIO
-                                                         AT91_PINCTRL_OUTPUT_VAL(0)>;
-                                        };
-
-                                        pinctrl_lcd_hipow0: lcd_hipow0 {
-                                                atmel,pins =
-                                                        <AT91_PIOA 23
-                                                         AT91_PERIPH_GPIO
-                                                         AT91_PINCTRL_OUTPUT_VAL(0)>;
-                                        };
-                                };
-                        };
-
-                        watchdog@fffffe40 {
-                                status = "okay";
-                        };
-                };
-        };
-
         gpio-keys {
                 compatible = "gpio-keys";
 
@@ -103,10 +63,29 @@
         };
 
         panel: panel {
-                compatible = "sharp,lq150x1lg11";
+                compatible = "sharp,lq150x1lg11", "panel-lvds";
+
                 backlight = <&panel_bl>;
                 power-supply = <&panel_reg>;
 
+                width-mm = <304>;
+                height-mm = <228>;
+
+                data-mapping = "jeida-18";
+
+                panel-timing {
+                        // 1024x768 @ 60Hz (typical)
+                        clock-frequency = <50000000 65000000 80000000>;
+                        hactive = <1024>;
+                        vactive = <768>;
+                        hfront-porch = <48 88 88>;
+                        hback-porch = <96 168 168>;
+                        hsync-len = <32 64 64>;
+                        vsync-len = <3 13 74>;
+                        vfront-porch = <3 13 74>;
+                        vback-porch = <3 12 74>;
+                };
+
                 port {
                         panel_input: endpoint {
                                 remote-endpoint = <&lvds_encoder_output>;
@@ -115,7 +94,10 @@
         };
 
         lvds-encoder {
-                compatible = "lvds-encoder";
+                compatible = "ti,ds90c185", "lvds-encoder";
+
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_lvds_prlud0 &pinctrl_lvds_hipow0>;
 
                 ports {
                         #address-cells = <1>;
@@ -159,6 +141,36 @@
         };
 };
 
+&pinctrl {
+        nattis {
+                pinctrl_usba_vbus: usba_vbus {
+                        atmel,pins = <AT91_PIOD 28 AT91_PERIPH_GPIO
+                                      AT91_PINCTRL_DEGLITCH>;
+                };
+
+                pinctrl_mmc0_cd: mmc0_cd {
+                        atmel,pins = <AT91_PIOD  5 AT91_PERIPH_GPIO
+                                      AT91_PINCTRL_PULL_UP_DEGLITCH>;
+                };
+
+                pinctrl_lvds_prlud0: lvds_prlud0 {
+                        atmel,pins = <AT91_PIOA 21 AT91_PERIPH_GPIO
+                                      (AT91_PINCTRL_OUTPUT |
+                                       AT91_PINCTRL_OUTPUT_VAL(0))>;
+                };
+
+                pinctrl_lvds_hipow0: lvds_hipow0 {
+                        atmel,pins = <AT91_PIOA 23 AT91_PERIPH_GPIO
+                                      (AT91_PINCTRL_OUTPUT |
+                                       AT91_PINCTRL_OUTPUT_VAL(0))>;
+                };
+        };
+};
+
+&watchdog {
+        status = "okay";
+};
+
 &i2c0 {
         status = "okay";
 
@@ -195,14 +207,12 @@
 
         hlcdc-display-controller {
                 pinctrl-names = "default";
-                pinctrl-0 = <&pinctrl_lcd_base
-                             &pinctrl_lcd_rgb565
-                             &pinctrl_lcd_prlud0
-                             &pinctrl_lcd_hipow0>;
+                pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb565>;
 
                 port@0 {
                         hlcdc_output: endpoint {
                                 remote-endpoint = <&lvds_encoder_input>;
+                                bus-width = <16>;
                         };
                 };
         };
@@ -219,6 +229,7 @@
                 reg = <0>;
                 bus-width = <4>;
                 cd-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
+                cd-inverted;
         };
 };
 
diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
index e86e0c00eb6b..363a43d77424 100644
--- a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
+++ b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
@@ -283,6 +283,13 @@
                                 status = "okay";
                         };
 
+                        adc: adc@fc030000 {
+                                vddana-supply = <&vddana>;
+                                vref-supply = <&advref>;
+
+                                status = "disabled";
+                        };
+
                         pinctrl@fc038000 {
 
                                 pinctrl_can1_default: can1_default {
@@ -549,4 +556,39 @@
                         linux,default-trigger = "heartbeat";
                 };
         };
+
+        vddin_3v3: fixed-regulator-vddin_3v3 {
+                compatible = "regulator-fixed";
+
+                regulator-name = "VDDIN_3V3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+                regulator-boot-on;
+                status = "okay";
+        };
+
+        vddana: fixed-regulator-vddana {
+                compatible = "regulator-fixed";
+
+                regulator-name = "VDDANA";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+                regulator-boot-on;
+                vin-supply = <&vddin_3v3>;
+                status = "okay";
+        };
+
+        advref: fixed-regulator-advref {
+                compatible = "regulator-fixed";
+
+                regulator-name = "advref";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+                regulator-boot-on;
+                vin-supply = <&vddana>;
+                status = "okay";
+        };
 };
diff --git a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
index 3b1baa8605a7..2214bfe7aa20 100644
--- a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
@@ -92,13 +92,13 @@
                                                         reg = <0x40000 0xc0000>;
                                                 };
 
-                                                bootloaderenv@0x100000 {
-                                                        label = "bootloader env";
+                                                bootloaderenvred@0x100000 {
+                                                        label = "bootloader env redundant";
                                                         reg = <0x100000 0x40000>;
                                                 };
 
-                                                bootloaderenvred@0x140000 {
-                                                        label = "bootloader env redundant";
+                                                bootloaderenv@0x140000 {
+                                                        label = "bootloader env";
                                                         reg = <0x140000 0x40000>;
                                                 };
 
diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
index fcc85d70f36e..518e2b095ccf 100644
--- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
@@ -281,6 +281,12 @@
                                 status = "okay";
                         };
 
+                        i2s0: i2s@f8050000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2s0_default>;
+                                status = "disabled"; /* conflict with can0 */
+                        };
+
                         can0: can@f8054000 {
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_can0_default>;
@@ -424,6 +430,24 @@
                                         bias-disable;
                                 };
 
+                                pinctrl_i2s0_default: i2s0_default {
+                                        pinmux = <PIN_PC1__I2SC0_CK>,
+                                                 <PIN_PC2__I2SC0_MCK>,
+                                                 <PIN_PC3__I2SC0_WS>,
+                                                 <PIN_PC4__I2SC0_DI0>,
+                                                 <PIN_PC5__I2SC0_DO0>;
+                                        bias-disable;
+                                };
+
+                                pinctrl_i2s1_default: i2s1_default {
+                                        pinmux = <PIN_PA15__I2SC1_CK>,
+                                                 <PIN_PA14__I2SC1_MCK>,
+                                                 <PIN_PA16__I2SC1_WS>,
+                                                 <PIN_PA17__I2SC1_DI0>,
+                                                 <PIN_PA18__I2SC1_DO0>;
+                                        bias-disable;
+                                };
+
                                 pinctrl_key_gpio_default: key_gpio_default {
                                         pinmux = <PIN_PB9__GPIO>;
                                         bias-pull-up;
@@ -546,6 +570,12 @@
                                 status = "okay";
                         };
 
+                        i2s1: i2s@fc04c000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2s1_default>;
+                                status = "disabled"; /* conflict with spi0, sdmmc1 */
+                        };
+
                         can1: can@fc050000 {
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_can1_default>;
diff --git a/arch/arm/boot/dts/at91-sama5d3_xplained.dts b/arch/arm/boot/dts/at91-sama5d3_xplained.dts
index 02c1d2958d78..322a744e4363 100644
--- a/arch/arm/boot/dts/at91-sama5d3_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d3_xplained.dts
@@ -297,12 +297,17 @@
 
                                                 bootloader@40000 {
                                                         label = "bootloader";
-                                                        reg = <0x40000 0x80000>;
+                                                        reg = <0x40000 0xc0000>;
                                                 };
 
-                                                bootloaderenv@c0000 {
+                                                bootloaderenvred@100000 {
+                                                        label = "bootloader env redundant";
+                                                        reg = <0x100000 0x40000>;
+                                                };
+
+                                                bootloaderenv@140000 {
                                                         label = "bootloader env";
-                                                        reg = <0xc0000 0xc0000>;
+                                                        reg = <0x140000 0x40000>;
                                                 };
 
                                                 dtb@180000 {
diff --git a/arch/arm/boot/dts/at91-sama5d4_xplained.dts b/arch/arm/boot/dts/at91-sama5d4_xplained.dts
index 4b7c762d5f22..43aef56ac74a 100644
--- a/arch/arm/boot/dts/at91-sama5d4_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d4_xplained.dts
@@ -232,12 +232,17 @@
 
                                                 bootloader@40000 {
                                                         label = "bootloader";
-                                                        reg = <0x40000 0x80000>;
+                                                        reg = <0x40000 0xc0000>;
                                                 };
 
-                                                bootloaderenv@c0000 {
+                                                bootloaderenvred@100000 {
+                                                        label = "bootloader env redundant";
+                                                        reg = <0x100000 0x40000>;
+                                                };
+
+                                                bootloaderenv@140000 {
                                                         label = "bootloader env";
-                                                        reg = <0xc0000 0xc0000>;
+                                                        reg = <0x140000 0x40000>;
                                                 };
 
                                                 dtb@180000 {
@@ -252,7 +257,7 @@
 
                                                 rootfs@800000 {
                                                         label = "rootfs";
-                                                        reg = <0x800000 0x0f800000>;
+                                                        reg = <0x800000 0x1f800000>;
                                                 };
                                         };
                                 };
diff --git a/arch/arm/boot/dts/at91-tse850-3.dts b/arch/arm/boot/dts/at91-tse850-3.dts
index 2fbec69d9cd6..fe8876eaf917 100644
--- a/arch/arm/boot/dts/at91-tse850-3.dts
+++ b/arch/arm/boot/dts/at91-tse850-3.dts
@@ -16,25 +16,6 @@
         compatible = "axentia,tse850v3", "axentia,linea",
                      "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
 
-        ahb {
-                apb {
-                        pinctrl@fffff200 {
-                                tse850 {
-                                        pinctrl_usba_vbus: usba-vbus {
-                                                atmel,pins =
-                                                        <AT91_PIOC 31
-                                                         AT91_PERIPH_GPIO
-                                                         AT91_PINCTRL_DEGLITCH>;
-                                        };
-                                };
-                        };
-
-                        watchdog@fffffe40 {
-                                status = "okay";
-                        };
-                };
-        };
-
         sck: oscillator {
                 compatible = "fixed-clock";
 
@@ -253,6 +234,19 @@
         };
 };
 
+&pinctrl {
+        tse850 {
+                pinctrl_usba_vbus: usba-vbus {
+                        atmel,pins = <AT91_PIOC 31 AT91_PERIPH_GPIO
+                                      AT91_PINCTRL_DEGLITCH>;
+                };
+        };
+};
+
+&watchdog {
+        status = "okay";
+};
+
 &usart0 {
         status = "okay";
 
diff --git a/arch/arm/boot/dts/at91-vinco.dts b/arch/arm/boot/dts/at91-vinco.dts
index 1be9889a2b3a..430277291e02 100644
--- a/arch/arm/boot/dts/at91-vinco.dts
+++ b/arch/arm/boot/dts/at91-vinco.dts
@@ -128,7 +128,7 @@
                         i2c2: i2c@f8024000 {
                                 status = "okay";
 
-                                rtc1: rtc@64 {
+                                rtc1: rtc@32 {
                                         compatible = "epson,rx8900";
                                         reg = <0x32>;
                                 };
diff --git a/arch/arm/boot/dts/at91sam9260ek.dts b/arch/arm/boot/dts/at91sam9260ek.dts
index d2b865f60293..07d1b571e601 100644
--- a/arch/arm/boot/dts/at91sam9260ek.dts
+++ b/arch/arm/boot/dts/at91sam9260ek.dts
@@ -127,7 +127,7 @@
 
                         spi0: spi@fffc8000 {
                                 cs-gpios = <0>, <&pioC 11 0>, <0>, <0>;
-                                mtd_dataflash@0 {
+                                mtd_dataflash@1 {
                                         compatible = "atmel,at45", "atmel,dataflash";
                                         spi-max-frequency = <50000000>;
                                         reg = <1>;
diff --git a/arch/arm/boot/dts/at91sam9261ek.dts b/arch/arm/boot/dts/at91sam9261ek.dts
index a29fc0494076..a57f2d435dca 100644
--- a/arch/arm/boot/dts/at91sam9261ek.dts
+++ b/arch/arm/boot/dts/at91sam9261ek.dts
@@ -160,7 +160,7 @@
                                         spi-max-frequency = <15000000>;
                                 };
 
-                                tsc2046@0 {
+                                tsc2046@2 {
                                         reg = <2>;
                                         compatible = "ti,ads7843";
                                         interrupts-extended = <&pioC 2 IRQ_TYPE_EDGE_BOTH>;
diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
index 71df3adfc7ca..ec1f17ab6753 100644
--- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
@@ -109,7 +109,7 @@
 
                         spi0: spi@fffc8000 {
                                 cs-gpios = <0>, <&pioC 11 0>, <0>, <0>;
-                                mtd_dataflash@0 {
+                                mtd_dataflash@1 {
                                         compatible = "atmel,at45", "atmel,dataflash";
                                         spi-max-frequency = <50000000>;
                                         reg = <1>;
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 1ee25a475be8..d16db1fa7e15 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -570,7 +570,7 @@
                                         };
                                 };
 
-                                uart1 {
+                                usart1 {
                                         pinctrl_usart1: usart1-0 {
                                                 atmel,pins =
                                                         <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE
diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi
index 4908ee07e628..c4cc9cc945fa 100644
--- a/arch/arm/boot/dts/at91sam9x5cm.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5cm.dtsi
@@ -85,12 +85,22 @@
 
                                                 uboot@40000 {
                                                         label = "u-boot";
-                                                        reg = <0x40000 0x80000>;
+                                                        reg = <0x40000 0xc0000>;
                                                 };
 
-                                                ubootenv@c0000 {
+                                                ubootenvred@100000 {
+                                                        label = "U-Boot Env Redundant";
+                                                        reg = <0x100000 0x40000>;
+                                                };
+
+                                                ubootenv@140000 {
                                                         label = "U-Boot Env";
-                                                        reg = <0xc0000 0x140000>;
+                                                        reg = <0x140000 0x40000>;
+                                                };
+
+                                                dtb@180000 {
+                                                        label = "device tree";
+                                                        reg = <0x180000 0x80000>;
                                                 };
 
                                                 kernel@200000 {
@@ -100,7 +110,7 @@
 
                                                 rootfs@800000 {
                                                         label = "rootfs";
-                                                        reg = <0x800000 0x1f800000>;
+                                                        reg = <0x800000 0x0f800000>;
                                                 };
                                         };
                                 };
diff --git a/arch/arm/boot/dts/bcm-hr2.dtsi b/arch/arm/boot/dts/bcm-hr2.dtsi
index 3084a7c95733..e4d49731287f 100644
--- a/arch/arm/boot/dts/bcm-hr2.dtsi
+++ b/arch/arm/boot/dts/bcm-hr2.dtsi
@@ -216,7 +216,7 @@
                         reg = <0x33000 0x14>;
                 };
 
-                qspi: qspi@27200 {
+                qspi: spi@27200 {
                         compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi";
                         reg = <0x027200 0x184>,
                               <0x027000 0x124>,
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 09ba85046322..2fd111d9d59c 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -273,7 +273,7 @@
                         brcm,nand-has-wp;
                 };
 
-                qspi: qspi@27200 {
+                qspi: spi@27200 {
                         compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi";
                         reg = <0x027200 0x184>,
                               <0x027000 0x124>,
@@ -377,7 +377,36 @@
 
                 srab: srab@36000 {
                         compatible = "brcm,nsp-srab";
-                        reg = <0x36000 0x1000>;
+                        reg = <0x36000 0x1000>,
+                              <0x3f308 0x8>,
+                              <0x3f410 0xc>;
+                        reg-names = "srab", "mux_config", "sgmii";
+                        interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "link_state_p0",
+                                          "link_state_p1",
+                                          "link_state_p2",
+                                          "link_state_p3",
+                                          "link_state_p4",
+                                          "link_state_p5",
+                                          "link_state_p7",
+                                          "link_state_p8",
+                                          "phy",
+                                          "ts",
+                                          "imp_sleep_timer_p5",
+                                          "imp_sleep_timer_p7",
+                                          "imp_sleep_timer_p8";
                         #address-cells = <1>;
                         #size-cells = <0>;
 
diff --git a/arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts b/arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts
new file mode 100644
index 000000000000..6c8233a36d86
--- /dev/null
+++ b/arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+#include "bcm2837-rpi-cm3.dtsi"
+#include "bcm283x-rpi-usb-host.dtsi"
+
+/ {
+        compatible = "raspberrypi,3-compute-module", "brcm,bcm2837";
+        model = "Raspberry Pi Compute Module 3 IO board V3.0";
+};
+
+&gpio {
+        /*
+         * This is based on the official GPU firmware DT blob.
+         *
+         * Legend:
+         * "NC" = not connected (no rail from the SoC)
+         * "FOO" = GPIO line named "FOO" on the schematic
+         * "FOO_N" = GPIO line named "FOO" on schematic, active low
+         */
+        gpio-line-names = "GPIO0",
+                          "GPIO1",
+                          "GPIO2",
+                          "GPIO3",
+                          "GPIO4",
+                          "GPIO5",
+                          "GPIO6",
+                          "GPIO7",
+                          "GPIO8",
+                          "GPIO9",
+                          "GPIO10",
+                          "GPIO11",
+                          "GPIO12",
+                          "GPIO13",
+                          "GPIO14",
+                          "GPIO15",
+                          "GPIO16",
+                          "GPIO17",
+                          "GPIO18",
+                          "GPIO19",
+                          "GPIO20",
+                          "GPIO21",
+                          "GPIO22",
+                          "GPIO23",
+                          "GPIO24",
+                          "GPIO25",
+                          "GPIO26",
+                          "GPIO27",
+                          "GPIO28",
+                          "GPIO29",
+                          "GPIO30",
+                          "GPIO31",
+                          "GPIO32",
+                          "GPIO33",
+                          "GPIO34",
+                          "GPIO35",
+                          "GPIO36",
+                          "GPIO37",
+                          "GPIO38",
+                          "GPIO39",
+                          "GPIO40",
+                          "GPIO41",
+                          "GPIO42",
+                          "GPIO43",
+                          "GPIO44",
+                          "GPIO45",
+                          "GPIO46",
+                          "GPIO47",
+                          /* Used by eMMC */
+                          "SD_CLK_R",
+                          "SD_CMD_R",
+                          "SD_DATA0_R",
+                          "SD_DATA1_R",
+                          "SD_DATA2_R",
+                          "SD_DATA3_R";
+
+        pinctrl-0 = <&gpioout &alt0>;
+};
+
+&hdmi {
+        hpd-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
+};
+
+&uart0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart0_gpio14>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi b/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi
new file mode 100644
index 000000000000..7b7ab6aea988
--- /dev/null
+++ b/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+#include "bcm2837.dtsi"
+#include "bcm2835-rpi.dtsi"
+
+/ {
+        memory {
+                reg = <0 0x40000000>;
+        };
+
+        reg_3v3: fixed-regulator {
+                compatible = "regulator-fixed";
+                regulator-name = "3V3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+        };
+
+        reg_1v8: fixed-regulator {
+                compatible = "regulator-fixed";
+                regulator-name = "1V8";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                regulator-always-on;
+        };
+};
+
+&firmware {
+        expgpio: gpio {
+                compatible = "raspberrypi,firmware-gpio";
+                gpio-controller;
+                #gpio-cells = <2>;
+                gpio-line-names = "HDMI_HPD_N",
+                                  "EMMC_EN_N",
+                                  "NC",
+                                  "NC",
+                                  "NC",
+                                  "NC",
+                                  "NC",
+                                  "NC";
+                status = "okay";
+        };
+};
+
+&sdhost {
+        pinctrl-names = "default";
+        pinctrl-0 = <&sdhost_gpio48>;
+        bus-width = <4>;
+        vmmc-supply = <&reg_3v3>;
+        vqmmc-supply = <&reg_1v8>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm283x-rpi-lan7515.dtsi b/arch/arm/boot/dts/bcm283x-rpi-lan7515.dtsi
index 9403da0990d0..70bece63f9a7 100644
--- a/arch/arm/boot/dts/bcm283x-rpi-lan7515.dtsi
+++ b/arch/arm/boot/dts/bcm283x-rpi-lan7515.dtsi
@@ -1,4 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/net/microchip-lan78xx.h>
+
 / {
         aliases {
                 ethernet0 = &ethernet;
@@ -21,6 +23,18 @@
                         ethernet: ethernet@1 {
                                 compatible = "usb424,7800";
                                 reg = <1>;
+
+                                mdio {
+                                        #address-cells = <0x1>;
+                                        #size-cells = <0x0>;
+                                        eth_phy: ethernet-phy@1 {
+                                                reg = <1>;
+                                                microchip,led-modes = <
+                                                        LAN78XX_LINK_1000_ACTIVITY
+                                                        LAN78XX_LINK_10_100_ACTIVITY
+                                                >;
+                                        };
+                                };
                         };
                 };
         };
diff --git a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts
index 5f663f848db1..189cc3dcd6ef 100644
--- a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts
+++ b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts
@@ -94,6 +94,34 @@
 
 &spi_nor {
         status = "okay";
+
+        partitions {
+                compatible = "fixed-partitions";
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                boot@0 {
+                        label = "boot";
+                        reg = <0x000000 0x040000>;
+                        read-only;
+                };
+
+                os-image@100000 {
+                        label = "os-image";
+                        reg = <0x040000 0x200000>;
+                        compatible = "brcm,trx";
+                };
+
+                rootfs@240000 {
+                        label = "rootfs";
+                        reg = <0x240000 0xc00000>;
+                };
+
+                nvram@ff0000 {
+                        label = "nvram";
+                        reg = <0xff0000 0x010000>;
+                };
+        };
 };
 
 &usb2 {
diff --git a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts
index 2033411240c7..4cb10f88a95e 100644
--- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts
+++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts
@@ -66,3 +66,34 @@
 &usb3_phy {
         status = "okay";
 };
+
+&nandcs {
+        partitions {
+                compatible = "fixed-partitions";
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                boot@0 {
+                        label = "boot";
+                        reg = <0x00000000 0x00080000>;
+                        read-only;
+                };
+
+                nvram@80000 {
+                        label = "nvram";
+                        reg = <0x00080000 0x00180000>;
+                };
+
+                firmware@200000 {
+                        label = "firmware";
+                        reg = <0x00200000 0x07cc0000>;
+                        compatible = "brcm,trx";
+                };
+
+                asus@7ec0000 {
+                        label = "asus";
+                        reg = <0x07ec0000 0x00140000>;
+                        read-only;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts
index c7143a9daa1a..b527d2ff987e 100644
--- a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts
+++ b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts
@@ -103,6 +103,34 @@
 
 &spi_nor {
         status = "okay";
+
+        partitions {
+                compatible = "fixed-partitions";
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                boot@0 {
+                        label = "boot";
+                        reg = <0x000000 0x040000>;
+                        read-only;
+                };
+
+                os-image@100000 {
+                        label = "os-image";
+                        reg = <0x040000 0x200000>;
+                        compatible = "brcm,trx";
+                };
+
+                rootfs@240000 {
+                        label = "rootfs";
+                        reg = <0x240000 0xc00000>;
+                };
+
+                nvram@ff0000 {
+                        label = "nvram";
+                        reg = <0xff0000 0x010000>;
+                };
+        };
 };
 
 &usb3_phy {
diff --git a/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi b/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi
index e5a2d62daf92..925a7c9ce5b7 100644
--- a/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi
+++ b/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi
@@ -12,6 +12,10 @@
                         reg = <0>;
                         #address-cells = <1>;
                         #size-cells = <1>;
+
+                        partitions {
+                                compatible = "brcm,bcm947xx-cfe-partitions";
+                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
index bc607d11eef8..7a5c188c2676 100644
--- a/arch/arm/boot/dts/bcm5301x.dtsi
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
@@ -475,8 +475,11 @@
                         compatible = "jedec,spi-nor";
                         reg = <0>;
                         spi-max-frequency = <20000000>;
-                        linux,part-probe = "ofpart", "bcm47xxpart";
                         status = "disabled";
+
+                        partitions {
+                                compatible = "brcm,bcm947xx-cfe-partitions";
+                        };
                 };
         };
 
diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts
index ea3fc194f8f3..a53a2f629d74 100644
--- a/arch/arm/boot/dts/bcm958625hr.dts
+++ b/arch/arm/boot/dts/bcm958625hr.dts
@@ -58,6 +58,24 @@
                 open-source;
                 priority = <200>;
         };
+
+        /* Hardware I2C block cannot do more than 63 bytes per transfer,
+         * which would prevent reading from a SFP's EEPROM (256 byte).
+         */
+        i2c1: i2c {
+                compatible = "i2c-gpio";
+                sda-gpios = <&gpioa 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+                scl-gpios = <&gpioa 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+        };
+
+        sfp: sfp {
+                compatible = "sff,sfp";
+                i2c-bus = <&i2c1>;
+                mod-def0-gpios = <&gpioa 28 GPIO_ACTIVE_LOW>;
+                los-gpios = <&gpioa 24 GPIO_ACTIVE_HIGH>;
+                tx-fault-gpios = <&gpioa 30 GPIO_ACTIVE_HIGH>;
+                tx-disable-gpios = <&gpioa 26 GPIO_ACTIVE_HIGH>;
+        };
 };
 
 &amac0 {
@@ -210,6 +228,14 @@
                         reg = <4>;
                 };
 
+                port@5 {
+                        label = "sfp";
+                        phy-mode = "sgmii";
+                        reg = <5>;
+                        sfp = <&sfp>;
+                        managed = "in-band-status";
+                };
+
                 port@8 {
                         ethernet = <&amac2>;
                         label = "cpu";
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
index f9b757905845..a3c9b346721d 100644
--- a/arch/arm/boot/dts/da850-evm.dts
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -221,6 +221,12 @@
                 gpio-controller;
                 #gpio-cells = <2>;
         };
+        tca6416_bb: gpio@21 {
+                compatible = "ti,tca6416";
+                reg = <0x21>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
 };
 
 &wdt {
diff --git a/arch/arm/boot/dts/da850-lego-ev3.dts b/arch/arm/boot/dts/da850-lego-ev3.dts
index c4729d0e6c19..66fcadf0ba91 100644
--- a/arch/arm/boot/dts/da850-lego-ev3.dts
+++ b/arch/arm/boot/dts/da850-lego-ev3.dts
@@ -352,7 +352,8 @@
                 compatible = "ti,ads7957";
                 reg = <3>;
                 #io-channel-cells = <1>;
-                spi-max-frequency = <10000000>;
+                spi-max-frequency = <1000000>;
+                ti,spi-wdelay = <63>;
                 vref-supply = <&adc_ref>;
         };
 };
diff --git a/arch/arm/boot/dts/dm8148-evm.dts b/arch/arm/boot/dts/dm8148-evm.dts
index 85d7b5148b0a..2d201719ba69 100644
--- a/arch/arm/boot/dts/dm8148-evm.dts
+++ b/arch/arm/boot/dts/dm8148-evm.dts
@@ -27,15 +27,25 @@
 };
 
 &cpsw_emac0 {
-        phy_id = <&davinci_mdio>, <0>;
+        phy-handle = <&ethphy0>;
         phy-mode = "rgmii";
 };
 
 &cpsw_emac1 {
-        phy_id = <&davinci_mdio>, <1>;
+        phy-handle = <&ethphy1>;
         phy-mode = "rgmii";
 };
 
+&davinci_mdio {
+        ethphy0: ethernet-phy@0 {
+                reg = <0>;
+        };
+
+        ethphy1: ethernet-phy@1 {
+                reg = <1>;
+        };
+};
+
 &gpmc {
         ranges = <0 0 0x04000000 0x01000000>;   /* CS0: 16MB for NAND */
 
diff --git a/arch/arm/boot/dts/dm8148-t410.dts b/arch/arm/boot/dts/dm8148-t410.dts
index c46a227b543d..63301bcacf19 100644
--- a/arch/arm/boot/dts/dm8148-t410.dts
+++ b/arch/arm/boot/dts/dm8148-t410.dts
@@ -36,15 +36,25 @@
 };
 
 &cpsw_emac0 {
-        phy_id = <&davinci_mdio>, <0>;
+        phy-handle = <&ethphy0>;
         phy-mode = "rgmii";
 };
 
 &cpsw_emac1 {
-        phy_id = <&davinci_mdio>, <1>;
+        phy-handle = <&ethphy1>;
         phy-mode = "rgmii";
 };
 
+&davinci_mdio {
+        ethphy0: ethernet-phy@0 {
+                reg = <0>;
+        };
+
+        ethphy1: ethernet-phy@1 {
+                reg = <1>;
+        };
+};
+
 &mmc1 {
         status = "disabled";
 };
diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts
index 580e3cbcfbf7..3e1584e787ae 100644
--- a/arch/arm/boot/dts/dove-cubox.dts
+++ b/arch/arm/boot/dts/dove-cubox.dts
@@ -87,7 +87,7 @@
         status = "okay";
         clock-frequency = <100000>;
 
-        si5351: clock-generator {
+        si5351: clock-generator@60 {
                 compatible = "silabs,si5351a-msop";
                 reg = <0x60>;
                 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index 4a0a5115b298..250ad0535e8c 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -155,7 +155,7 @@
                                   0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800   /* CESA SRAM  2k */
                                   0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU  SRAM  2k */
 
-                        spi0: spi-ctrl@10600 {
+                        spi0: spi@10600 {
                                 compatible = "marvell,orion-spi";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
@@ -168,7 +168,7 @@
                                 status = "disabled";
                         };
 
-                        i2c: i2c-ctrl@11000 {
+                        i2c: i2c@11000 {
                                 compatible = "marvell,mv64xxx-i2c";
                                 reg = <0x11000 0x20>;
                                 #address-cells = <1>;
@@ -218,7 +218,7 @@
                                 status = "disabled";
                         };
 
-                        spi1: spi-ctrl@14600 {
+                        spi1: spi@14600 {
                                 compatible = "marvell,orion-spi";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/dra62x-j5eco-evm.dts b/arch/arm/boot/dts/dra62x-j5eco-evm.dts
index 31b824ad5d29..906aedde045d 100644
--- a/arch/arm/boot/dts/dra62x-j5eco-evm.dts
+++ b/arch/arm/boot/dts/dra62x-j5eco-evm.dts
@@ -27,15 +27,25 @@
 };
 
 &cpsw_emac0 {
-        phy_id = <&davinci_mdio>, <0>;
+        phy-handle = <&ethphy0>;
         phy-mode = "rgmii";
 };
 
 &cpsw_emac1 {
-        phy_id = <&davinci_mdio>, <1>;
+        phy-handle = <&ethphy1>;
         phy-mode = "rgmii";
 };
 
+&davinci_mdio {
+        ethphy0: ethernet-phy@0 {
+                reg = <0>;
+        };
+
+        ethphy1: ethernet-phy@1 {
+                reg = <1>;
+        };
+};
+
 &gpmc {
         ranges = <0 0 0x04000000 0x01000000>;   /* CS0: 16MB for NAND */
 
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 6ed5f9156270..cc079064a23b 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -512,17 +512,27 @@
 };
 
 &cpsw_emac0 {
-        phy_id = <&davinci_mdio>, <2>;
+        phy-handle = <&ethphy0>;
         phy-mode = "rgmii";
         dual_emac_res_vlan = <1>;
 };
 
 &cpsw_emac1 {
-        phy_id = <&davinci_mdio>, <3>;
+        phy-handle = <&ethphy1>;
         phy-mode = "rgmii";
         dual_emac_res_vlan = <2>;
 };
 
+&davinci_mdio {
+        ethphy0: ethernet-phy@2 {
+                reg = <2>;
+        };
+
+        ethphy1: ethernet-phy@3 {
+                reg = <3>;
+        };
+};
+
 &dcan1 {
         status = "ok";
         pinctrl-names = "default", "sleep", "active";
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index a0ddf497e8cd..7ce24b282d42 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -336,6 +336,7 @@
                                                 <0 0 0 2 &pcie1_intc 2>,
                                                 <0 0 0 3 &pcie1_intc 3>,
                                                 <0 0 0 4 &pcie1_intc 4>;
+                                ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
                                 status = "disabled";
                                 pcie1_intc: interrupt-controller {
                                         interrupt-controller;
@@ -354,7 +355,7 @@
                                 ti,hwmods = "pcie1";
                                 phys = <&pcie1_phy>;
                                 phy-names = "pcie-phy0";
-                                ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
+                                ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
                                 status = "disabled";
                         };
                 };
@@ -387,6 +388,7 @@
                                                 <0 0 0 2 &pcie2_intc 2>,
                                                 <0 0 0 3 &pcie2_intc 3>,
                                                 <0 0 0 4 &pcie2_intc 4>;
+                                ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
                                 pcie2_intc: interrupt-controller {
                                         interrupt-controller;
                                         #address-cells = <0>;
@@ -1369,7 +1371,7 @@
                         status = "disabled";
                 };
 
-                qspi: qspi@4b300000 {
+                qspi: spi@4b300000 {
                         compatible = "ti,dra7xxx-qspi";
                         reg = <0x4b300000 0x100>,
                               <0x5c000000 0x4000000>;
diff --git a/arch/arm/boot/dts/dra71-evm.dts b/arch/arm/boot/dts/dra71-evm.dts
index c471bf3277b4..82cc7ec37af0 100644
--- a/arch/arm/boot/dts/dra71-evm.dts
+++ b/arch/arm/boot/dts/dra71-evm.dts
@@ -203,13 +203,13 @@
 };
 
 &cpsw_emac0 {
-        phy_id = <&davinci_mdio>, <2>;
+        phy-handle = <&dp83867_0>;
         phy-mode = "rgmii-id";
         dual_emac_res_vlan = <1>;
 };
 
 &cpsw_emac1 {
-        phy_id = <&davinci_mdio>, <3>;
+        phy-handle = <&dp83867_1>;
         phy-mode = "rgmii-id";
         dual_emac_res_vlan = <2>;
 };
diff --git a/arch/arm/boot/dts/dra72-evm-revc.dts b/arch/arm/boot/dts/dra72-evm-revc.dts
index bf588d00728d..fafc2a4d7bb9 100644
--- a/arch/arm/boot/dts/dra72-evm-revc.dts
+++ b/arch/arm/boot/dts/dra72-evm-revc.dts
@@ -61,13 +61,13 @@
 };
 
 &cpsw_emac0 {
-        phy_id = <&davinci_mdio>, <2>;
+        phy-handle = <&dp83867_0>;
         phy-mode = "rgmii-id";
         dual_emac_res_vlan = <1>;
 };
 
 &cpsw_emac1 {
-        phy_id = <&davinci_mdio>, <3>;
+        phy-handle = <&dp83867_1>;
         phy-mode = "rgmii-id";
         dual_emac_res_vlan = <2>;
 };
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index c572693b1665..154b0a0ceb18 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -51,10 +51,16 @@
 };
 
 &cpsw_emac0 {
-        phy_id = <&davinci_mdio>, <3>;
+        phy-handle = <&ethphy0>;
         phy-mode = "rgmii";
 };
 
+&davinci_mdio {
+        ethphy0: ethernet-phy@3 {
+                reg = <3>;
+        };
+};
+
 &mmc1 {
         pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
         pinctrl-0 = <&mmc1_pins_default>;
diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts
index 5a46163d465f..8a57895fd8f3 100644
--- a/arch/arm/boot/dts/dra76-evm.dts
+++ b/arch/arm/boot/dts/dra76-evm.dts
@@ -375,13 +375,13 @@
 };
 
 &cpsw_emac0 {
-        phy_id = <&davinci_mdio>, <2>;
+        phy-handle = <&dp83867_0>;
         phy-mode = "rgmii-id";
         dual_emac_res_vlan = <1>;
 };
 
 &cpsw_emac1 {
-        phy_id = <&davinci_mdio>, <3>;
+        phy-handle = <&dp83867_1>;
         phy-mode = "rgmii-id";
         dual_emac_res_vlan = <2>;
 };
diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi
index 620b50c19ead..7c22cbf6f3d4 100644
--- a/arch/arm/boot/dts/exynos3250-artik5.dtsi
+++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi
@@ -69,6 +69,8 @@
                 compatible = "samsung,s2mps14-pmic";
                 interrupt-parent = <&gpx3>;
                 interrupts = <5 IRQ_TYPE_NONE>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&s2mps14_irq>;
                 reg = <0x66>;
 
                 s2mps14_osc: clocks {
@@ -350,6 +352,11 @@
                 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV3>;
                 samsung,pin-val = <1>;
         };
+
+        s2mps14_irq: s2mps14-irq {
+                samsung,pins = "gpx3-5";
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+        };
 };
 
 &rtc {
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index 2ab99f9f3d0a..dd9ec05eb0f7 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -151,6 +151,8 @@
                 reg = <0x66>;
                 interrupt-parent = <&gpx0>;
                 interrupts = <4 IRQ_TYPE_NONE>, <3 IRQ_TYPE_NONE>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&max8997_irq>;
 
                 max8997,pmic-buck1-dvs-voltage = <1350000>;
                 max8997,pmic-buck2-dvs-voltage = <1100000>;
@@ -288,6 +290,13 @@
         };
 };
 
+&pinctrl_1 {
+        max8997_irq: max8997-irq {
+                samsung,pins = "gpx0-3", "gpx0-4";
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+        };
+};
+
 &sdhci_0 {
         bus-width = <4>;
         pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_cd>;
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index 6f1d76cb7951..f9bbc6315cd9 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -385,6 +385,12 @@
                              regulator-max-microvolt = <1800000>;
                         };
 
+                        tflash_reg: LDO17 {
+                             regulator-name = "VTF_2.8V";
+                             regulator-min-microvolt = <2800000>;
+                             regulator-max-microvolt = <2800000>;
+                        };
+
                         vddq_reg: LDO21 {
                              regulator-name = "VDDQ_M1M2_1.2V";
                              regulator-min-microvolt = <1200000>;
@@ -452,6 +458,15 @@
         status = "okay";
 };
 
+&sdhci_2 {
+        bus-width = <4>;
+        pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>;
+        pinctrl-names = "default";
+        vmmc-supply = <&tflash_reg>;
+        cd-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>;
+        status = "okay";
+};
+
 &serial_0 {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index 4e6ff97e1ec4..5c3d98654f13 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -310,6 +310,9 @@
 
         pmic@66 {
                 compatible = "national,lp3974";
+                interrupts-extended = <&gpx0 7 0>, <&gpx2 7 0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&lp3974_irq>;
                 reg = <0x66>;
 
                 max8998,pmic-buck1-default-dvs-idx = <0>;
@@ -503,6 +506,11 @@
 };
 
 &pinctrl_1 {
+        lp3974_irq: lp3974-irq {
+                samsung,pins = "gpx0-7", "gpx2-7";
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+        };
+
         hdmi_hpd: hdmi-hpd {
                 samsung,pins = "gpx3-7";
                 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
@@ -537,8 +545,7 @@
         pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>;
         pinctrl-names = "default";
         vmmc-supply = <&ldo5_reg>;
-        cd-gpios = <&gpx3 4 GPIO_ACTIVE_HIGH>;
-        cd-inverted;
+        cd-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi
index c0476c290977..aed2f2e2b0d1 100644
--- a/arch/arm/boot/dts/exynos4412-midas.dtsi
+++ b/arch/arm/boot/dts/exynos4412-midas.dtsi
@@ -1269,8 +1269,7 @@
 
 &sdhci_2 {
         bus-width = <4>;
-        cd-gpios = <&gpx3 4 GPIO_ACTIVE_HIGH>;
-        cd-inverted;
+        cd-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>;
         pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sdhci2_cd>;
         pinctrl-names = "default";
         vmmc-supply = <&ldo21_reg>;
diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index a09e46c9dbc0..2caa3132f34e 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -539,8 +539,7 @@
         pinctrl-names = "default";
         vmmc-supply = <&ldo21_reg>;
         vqmmc-supply = <&ldo4_reg>;
-        cd-gpios = <&gpk2 2 GPIO_ACTIVE_HIGH>;
-        cd-inverted;
+        cd-gpios = <&gpk2 2 GPIO_ACTIVE_LOW>;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index 7a8a5c55701a..7d1f2dc59038 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -71,6 +71,17 @@
                 };
         };
 
+        panel: panel {
+                compatible = "boe,hv070wsa-100";
+                power-supply = <&vcc_3v3_reg>;
+                enable-gpios = <&gpd1 3 GPIO_ACTIVE_HIGH>;
+                port {
+                        panel_ep: endpoint {
+                                remote-endpoint = <&bridge_out_ep>;
+                        };
+                };
+        };
+
         regulators {
                 compatible = "simple-bus";
                 #address-cells = <1>;
@@ -97,6 +108,30 @@
                         reg = <2>;
                         regulator-name = "hdmi-en";
                 };
+
+                vcc_1v2_reg: regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "VCC_1V2";
+                        regulator-min-microvolt = <1200000>;
+                        regulator-max-microvolt = <1200000>;
+                };
+
+                vcc_1v8_reg: regulator@4 {
+                        compatible = "regulator-fixed";
+                        reg = <4>;
+                        regulator-name = "VCC_1V8";
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                };
+
+                vcc_3v3_reg: regulator@5 {
+                        compatible = "regulator-fixed";
+                        reg = <5>;
+                        regulator-name = "VCC_3V3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                };
         };
 
         fixed-rate-clocks {
@@ -119,6 +154,32 @@
         cpu0-supply = <&buck2_reg>;
 };
 
+&dsi_0 {
+        vddcore-supply = <&ldo8_reg>;
+        vddio-supply = <&ldo10_reg>;
+        samsung,pll-clock-frequency = <24000000>;
+        samsung,burst-clock-frequency = <320000000>;
+        samsung,esc-clock-frequency = <10000000>;
+        status = "okay";
+
+        bridge@0 {
+                reg = <0>;
+                compatible = "toshiba,tc358764";
+                vddc-supply = <&vcc_1v2_reg>;
+                vddio-supply = <&vcc_1v8_reg>;
+                vddlvds-supply = <&vcc_3v3_reg>;
+                reset-gpios = <&gpd1 6 GPIO_ACTIVE_LOW>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                port@1 {
+                        reg = <1>;
+                        bridge_out_ep: endpoint {
+                                remote-endpoint = <&panel_ep>;
+                        };
+                };
+        };
+};
+
 &dp {
         status = "okay";
         samsung,color-space = <0>;
@@ -149,9 +210,11 @@
 };
 
 &hdmi {
+        pinctrl-names = "default";
+        pinctrl-0 = <&hdmi_hpd>;
         status = "okay";
-        ddc = <&i2c_2>;
-        hpd-gpios = <&gpx3 7 GPIO_ACTIVE_LOW>;
+        ddc = <&i2c_ddc>;
+        hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>;
         vdd_osc-supply = <&ldo10_reg>;
         vdd_pll-supply = <&ldo8_reg>;
         vdd-supply = <&ldo8_reg>;
@@ -168,6 +231,8 @@
                 reg = <0x66>;
                 interrupt-parent = <&gpx3>;
                 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&s5m8767_irq>;
 
                 vinb1-supply = <&main_dc_reg>;
                 vinb2-supply = <&main_dc_reg>;
@@ -452,13 +517,6 @@
         };
 };
 
-&i2c_2 {
-        status = "okay";
-        /* used by HDMI DDC */
-        samsung,i2c-sda-delay = <100>;
-        samsung,i2c-max-bus-freq = <66000>;
-};
-
 &i2c_3 {
         status = "okay";
 
@@ -535,6 +593,13 @@
         cap-sd-highspeed;
 };
 
+&pinctrl_0 {
+        s5m8767_irq: s5m8767-irq {
+                samsung,pins = "gpx3-2";
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+        };
+};
+
 &rtc {
         status = "okay";
 };
@@ -547,3 +612,22 @@
         status = "okay";
         samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
 };
+
+&soc {
+        /*
+         * For unknown reasons HDMI-DDC does not work with Exynos I2C
+         * controllers. Lets use software I2C over GPIO pins as a workaround.
+         */
+        i2c_ddc: i2c-gpio {
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c2_gpio_bus>;
+                status = "okay";
+                compatible = "i2c-gpio";
+                gpios = <&gpa0 6 0 /* sda */
+                         &gpa0 7 0 /* scl */
+                        >;
+                i2c-gpio,delay-us = <2>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+};
diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
index 6ff6dea29d44..d31a68672bfa 100644
--- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
@@ -225,6 +225,12 @@
                 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
         };
 
+        i2c2_gpio_bus: i2c2-gpio-bus {
+                samsung,pins = "gpa0-6", "gpa0-7";
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
         uart2_data: uart2-data {
                 samsung,pins = "gpa1-0", "gpa1-1";
                 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
@@ -593,6 +599,11 @@
                 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
                 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
         };
+
+        hdmi_hpd: hdmi-hpd {
+                samsung,pins = "gpx3-7";
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+        };
 };
 
 &pinctrl_1 {
diff --git a/arch/arm/boot/dts/exynos5250-snow-rev5.dts b/arch/arm/boot/dts/exynos5250-snow-rev5.dts
index 0348b1c49a69..7cbfc6f1f4b8 100644
--- a/arch/arm/boot/dts/exynos5250-snow-rev5.dts
+++ b/arch/arm/boot/dts/exynos5250-snow-rev5.dts
@@ -20,6 +20,14 @@
 
                 samsung,model = "Snow-I2S-MAX98090";
                 samsung,audio-codec = <&max98090>;
+
+                cpu {
+                        sound-dai = <&i2s0 0>;
+                };
+
+                codec {
+                        sound-dai = <&max98090 0>, <&hdmi>;
+                };
         };
 };
 
@@ -31,6 +39,9 @@
                 interrupt-parent = <&gpx0>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&max98090_irq>;
+                clocks = <&pmu_system_controller 0>;
+                clock-names = "mclk";
+                #sound-dai-cells = <1>;
         };
 };
 
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index da163a40af15..5044f754e6e5 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -54,62 +54,109 @@
                         device_type = "cpu";
                         compatible = "arm,cortex-a15";
                         reg = <0>;
-                        clock-frequency = <1700000000>;
                         clocks = <&clock CLK_ARM_CLK>;
                         clock-names = "cpu";
-                        clock-latency = <140000>;
-
-                        operating-points = <
-                                1700000 1300000
-                                1600000 1250000
-                                1500000 1225000
-                                1400000 1200000
-                                1300000 1150000
-                                1200000 1125000
-                                1100000 1100000
-                                1000000 1075000
-                                 900000 1050000
-                                 800000 1025000
-                                 700000 1012500
-                                 600000 1000000
-                                 500000  975000
-                                 400000  950000
-                                 300000  937500
-                                 200000  925000
-                        >;
+                        operating-points-v2 = <&cpu0_opp_table>;
                         #cooling-cells = <2>; /* min followed by max */
                 };
                 cpu@1 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a15";
                         reg = <1>;
-                        clock-frequency = <1700000000>;
                         clocks = <&clock CLK_ARM_CLK>;
                         clock-names = "cpu";
-                        clock-latency = <140000>;
-
-                        operating-points = <
-                                1700000 1300000
-                                1600000 1250000
-                                1500000 1225000
-                                1400000 1200000
-                                1300000 1150000
-                                1200000 1125000
-                                1100000 1100000
-                                1000000 1075000
-                                 900000 1050000
-                                 800000 1025000
-                                 700000 1012500
-                                 600000 1000000
-                                 500000  975000
-                                 400000  950000
-                                 300000  937500
-                                 200000  925000
-                        >;
+                        operating-points-v2 = <&cpu0_opp_table>;
                         #cooling-cells = <2>; /* min followed by max */
                 };
         };
 
+        cpu0_opp_table: opp_table0 {
+                compatible = "operating-points-v2";
+                opp-shared;
+
+                opp-200000000 {
+                        opp-hz = /bits/ 64 <200000000>;
+                        opp-microvolt = <925000>;
+                        clock-latency-ns = <140000>;
+                };
+                opp-300000000 {
+                        opp-hz = /bits/ 64 <300000000>;
+                        opp-microvolt = <937500>;
+                        clock-latency-ns = <140000>;
+                };
+                opp-400000000 {
+                        opp-hz = /bits/ 64 <400000000>;
+                        opp-microvolt = <950000>;
+                        clock-latency-ns = <140000>;
+                };
+                opp-500000000 {
+                        opp-hz = /bits/ 64 <500000000>;
+                        opp-microvolt = <975000>;
+                        clock-latency-ns = <140000>;
+                };
+                opp-600000000 {
+                        opp-hz = /bits/ 64 <600000000>;
+                        opp-microvolt = <1000000>;
+                        clock-latency-ns = <140000>;
+                };
+                opp-700000000 {
+                        opp-hz = /bits/ 64 <700000000>;
+                        opp-microvolt = <1012500>;
+                        clock-latency-ns = <140000>;
+                };
+                opp-800000000 {
+                        opp-hz = /bits/ 64 <800000000>;
+                        opp-microvolt = <1025000>;
+                        clock-latency-ns = <140000>;
+                };
+                opp-900000000 {
+                        opp-hz = /bits/ 64 <900000000>;
+                        opp-microvolt = <1050000>;
+                        clock-latency-ns = <140000>;
+                };
+                opp-1000000000 {
+                        opp-hz = /bits/ 64 <1000000000>;
+                        opp-microvolt = <1075000>;
+                        clock-latency-ns = <140000>;
+                        opp-suspend;
+                };
+                opp-1100000000 {
+                        opp-hz = /bits/ 64 <1100000000>;
+                        opp-microvolt = <1100000>;
+                        clock-latency-ns = <140000>;
+                };
+                opp-1200000000 {
+                        opp-hz = /bits/ 64 <1200000000>;
+                        opp-microvolt = <1125000>;
+                        clock-latency-ns = <140000>;
+                };
+                opp-1300000000 {
+                        opp-hz = /bits/ 64 <1300000000>;
+                        opp-microvolt = <1150000>;
+                        clock-latency-ns = <140000>;
+                };
+                opp-1400000000 {
+                        opp-hz = /bits/ 64 <1400000000>;
+                        opp-microvolt = <1200000>;
+                        clock-latency-ns = <140000>;
+                };
+                opp-1500000000 {
+                        opp-hz = /bits/ 64 <1500000000>;
+                        opp-microvolt = <1225000>;
+                        clock-latency-ns = <140000>;
+                };
+                opp-1600000000 {
+                        opp-hz = /bits/ 64 <1600000000>;
+                        opp-microvolt = <1250000>;
+                        clock-latency-ns = <140000>;
+                };
+                opp-1700000000 {
+                        opp-hz = /bits/ 64 <1700000000>;
+                        opp-microvolt = <1300000>;
+                        clock-latency-ns = <140000>;
+                };
+        };
+
         soc: soc {
                 sysram@2020000 {
                         compatible = "mmio-sram";
@@ -756,6 +803,27 @@
                         #phy-cells = <0>;
                 };
 
+                mipi_phy: video-phy@10040710 {
+                        compatible = "samsung,s5pv210-mipi-video-phy";
+                        reg = <0x10040710 0x100>;
+                        #phy-cells = <1>;
+                        syscon = <&pmu_system_controller>;
+                };
+
+                dsi_0: dsi@14500000 {
+                        compatible = "samsung,exynos4210-mipi-dsi";
+                        reg = <0x14500000 0x10000>;
+                        interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+                        samsung,power-domain = <&pd_disp1>;
+                        phys = <&mipi_phy 3>;
+                        phy-names = "dsim";
+                        clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI1>;
+                        clock-names = "bus_clk", "sclk_mipi";
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+
                 adc: adc@12d10000 {
                         compatible = "samsung,exynos-adc-v1";
                         reg = <0x12D10000 0x100>;
diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts
index a2046f5f998c..434a7591ff63 100644
--- a/arch/arm/boot/dts/exynos5410-odroidxu.dts
+++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts
@@ -530,7 +530,7 @@
         samsung,dw-mshc-sdr-timing = <0 4>;
         samsung,dw-mshc-ddr-timing = <0 2>;
         pinctrl-names = "default";
-        pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
+        pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4 &sd2_wp>;
         bus-width = <4>;
         cap-sd-highspeed;
         vmmc-supply = <&ldo21_reg>;
@@ -545,6 +545,14 @@
                 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
         };
 
+        sd2_wp: sd2-wp {
+                samsung,pins = "gpm5-0";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                /* Pin is floating so be sure to disable write-protect */
+                samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+                samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
+        };
+
         pmic_dvs_3: pmic-dvs-3 {
                 samsung,pins = "gpx0-0";
                 samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 57c2332bf282..f78db6809cca 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -153,7 +153,7 @@
 
 &clock_audss {
         assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>;
-        assigned-clock-parents = <&clock CLK_FOUT_EPLL>;
+        assigned-clock-parents = <&clock CLK_MAU_EPLL>;
 };
 
 &cpu0 {
@@ -312,6 +312,7 @@
                                 regulator-name = "vdd_1v35";
                                 regulator-min-microvolt = <1350000>;
                                 regulator-max-microvolt = <1350000>;
+                                regulator-always-on;
                                 regulator-boot-on;
                                 regulator-state-mem {
                                         regulator-on-in-suspend;
@@ -333,6 +334,7 @@
                                 regulator-name = "vdd_2v";
                                 regulator-min-microvolt = <2000000>;
                                 regulator-max-microvolt = <2000000>;
+                                regulator-always-on;
                                 regulator-boot-on;
                                 regulator-state-mem {
                                         regulator-on-in-suspend;
@@ -343,6 +345,7 @@
                                 regulator-name = "vdd_1v8";
                                 regulator-min-microvolt = <1800000>;
                                 regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
                                 regulator-boot-on;
                                 regulator-state-mem {
                                         regulator-on-in-suspend;
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 2f4f40882dab..2fac4baf1eb4 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -154,6 +154,13 @@
                                 regulator-always-on;
                         };
 
+                        ldo2_reg: LDO2 {
+                                regulator-name = "vdd_ldo2";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+
                         ldo3_reg: LDO3 {
                                 regulator-name = "vddq_mmc0";
                                 regulator-min-microvolt = <1800000>;
@@ -216,10 +223,10 @@
                         };
 
                         ldo12_reg: LDO12 {
+                                /* Unused */
                                 regulator-name = "vdd_ldo12";
-                                regulator-min-microvolt = <1800000>;
-                                regulator-max-microvolt = <1800000>;
-                                regulator-always-on;
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <2375000>;
                         };
 
                         ldo13_reg: LDO13 {
@@ -228,6 +235,13 @@
                                 regulator-max-microvolt = <2800000>;
                         };
 
+                        ldo14_reg: LDO14 {
+                                /* Unused */
+                                regulator-name = "vdd_ldo14";
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <3950000>;
+                        };
+
                         ldo15_reg: LDO15 {
                                 regulator-name = "vdd_ldo15";
                                 regulator-min-microvolt = <3300000>;
@@ -236,10 +250,10 @@
                         };
 
                         ldo16_reg: LDO16 {
+                                /* Unused */
                                 regulator-name = "vdd_ldo16";
-                                regulator-min-microvolt = <2200000>;
-                                regulator-max-microvolt = <2200000>;
-                                regulator-always-on;
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <3950000>;
                         };
 
                         ldo17_reg: LDO17 {
@@ -261,20 +275,139 @@
                                 regulator-max-microvolt = <2800000>;
                         };
 
-                        ldo24_reg: LDO24 {
-                                regulator-name = "tsp_io";
-                                regulator-min-microvolt = <2800000>;
-                                regulator-max-microvolt = <2800000>;
+                        ldo20_reg: LDO20 {
+                                /* Unused */
+                                regulator-name = "vdd_ldo20";
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <3950000>;
+                        };
+
+                        ldo21_reg: LDO21 {
+                                /* Unused */
+                                regulator-name = "vdd_ldo21";
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <3950000>;
+                        };
+
+                        ldo22_reg: LDO22 {
+                                /* Unused */
+                                regulator-name = "vdd_ldo22";
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <2375000>;
+                        };
+
+                        ldo23_reg: LDO23 {
+                                regulator-name = "vdd_mifs";
+                                regulator-min-microvolt = <1100000>;
+                                regulator-max-microvolt = <1100000>;
                                 regulator-always-on;
                         };
 
+                        ldo24_reg: LDO24 {
+                                /* Unused */
+                                regulator-name = "vdd_ldo24";
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <3950000>;
+                        };
+
+                        ldo25_reg: LDO25 {
+                                /* Unused */
+                                regulator-name = "vdd_ldo25";
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <3950000>;
+                        };
+
                         ldo26_reg: LDO26 {
+                                /* Used on XU3, XU3-Lite and XU4 */
                                 regulator-name = "vdd_ldo26";
-                                regulator-min-microvolt = <3000000>;
-                                regulator-max-microvolt = <3000000>;
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <3950000>;
+                        };
+
+                        ldo27_reg: LDO27 {
+                                regulator-name = "vdd_g3ds";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
                                 regulator-always-on;
                         };
 
+                        ldo28_reg: LDO28 {
+                                /* Used on XU3 */
+                                regulator-name = "vdd_ldo28";
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <3950000>;
+                        };
+
+                        ldo29_reg: LDO29 {
+                                /* Unused */
+                                regulator-name = "vdd_ldo29";
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <3950000>;
+                        };
+
+                        ldo30_reg: LDO30 {
+                                /* Unused */
+                                regulator-name = "vdd_ldo30";
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <3950000>;
+                        };
+
+                        ldo31_reg: LDO31 {
+                                /* Unused */
+                                regulator-name = "vdd_ldo31";
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <3950000>;
+                        };
+
+                        ldo32_reg: LDO32 {
+                                /* Unused */
+                                regulator-name = "vdd_ldo32";
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <3950000>;
+                        };
+
+                        ldo33_reg: LDO33 {
+                                /* Unused */
+                                regulator-name = "vdd_ldo33";
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <3950000>;
+                        };
+
+                        ldo34_reg: LDO34 {
+                                /* Unused */
+                                regulator-name = "vdd_ldo34";
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <3950000>;
+                        };
+
+                        ldo35_reg: LDO35 {
+                                /* Unused */
+                                regulator-name = "vdd_ldo35";
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <2375000>;
+                        };
+
+                        ldo36_reg: LDO36 {
+                                /* Unused */
+                                regulator-name = "vdd_ldo36";
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <3950000>;
+                        };
+
+                        ldo37_reg: LDO37 {
+                                /* Unused */
+                                regulator-name = "vdd_ldo37";
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <3950000>;
+                        };
+
+                        ldo38_reg: LDO38 {
+                                /* Unused */
+                                regulator-name = "vdd_ldo38";
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <3950000>;
+                        };
+
                         buck1_reg: BUCK1 {
                                 regulator-name = "vdd_mif";
                                 regulator-min-microvolt = <800000>;
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
index 96e281c0a118..e522edb2bb82 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
@@ -367,6 +367,12 @@
         status = "okay";
 };
 
+&ldo26_reg {
+        regulator-min-microvolt = <3000000>;
+        regulator-max-microvolt = <3000000>;
+        regulator-always-on;
+};
+
 &mixer {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
index 0322f281912c..db0bc17a667b 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
@@ -49,6 +49,12 @@
         };
 };
 
+&ldo28_reg {
+        regulator-name = "dp_p3v3";
+        regulator-min-microvolt = <3300000>;
+        regulator-max-microvolt = <3300000>;
+};
+
 &pwm {
         /*
          * PWM 0 -- fan
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index d80ab9085da1..e0f470fe54c8 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -153,7 +153,7 @@
 
 &clock_audss {
         assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>;
-        assigned-clock-parents = <&clock CLK_FOUT_EPLL>;
+        assigned-clock-parents = <&clock CLK_MAU_EPLL>;
 };
 
 &cpu0 {
@@ -312,6 +312,7 @@
                                 regulator-name = "vdd_1v35";
                                 regulator-min-microvolt = <1350000>;
                                 regulator-max-microvolt = <1350000>;
+                                regulator-always-on;
                                 regulator-boot-on;
                                 regulator-state-mem {
                                         regulator-on-in-suspend;
@@ -333,6 +334,7 @@
                                 regulator-name = "vdd_2v";
                                 regulator-min-microvolt = <2000000>;
                                 regulator-max-microvolt = <2000000>;
+                                regulator-always-on;
                                 regulator-boot-on;
                                 regulator-state-mem {
                                         regulator-on-in-suspend;
@@ -343,6 +345,7 @@
                                 regulator-name = "vdd_1v8";
                                 regulator-min-microvolt = <1800000>;
                                 regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
                                 regulator-boot-on;
                                 regulator-state-mem {
                                         regulator-on-in-suspend;
diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi
index 44044f275115..0f917b272ff3 100644
--- a/arch/arm/boot/dts/hip04.dtsi
+++ b/arch/arm/boot/dts/hip04.dtsi
@@ -277,10 +277,11 @@
 
                 clocks = <&clk_375m>;
                 clock-names = "apb_pclk";
-                port {
-                        etb0_in_port: endpoint@0 {
-                                slave-mode;
-                                remote-endpoint = <&replicator0_out_port0>;
+                in-ports {
+                        port {
+                                etb0_in_port: endpoint@0 {
+                                        remote-endpoint = <&replicator0_out_port0>;
+                                };
                         };
                 };
         };
@@ -291,10 +292,11 @@
 
                 clocks = <&clk_375m>;
                 clock-names = "apb_pclk";
-                port {
-                        etb1_in_port: endpoint@0 {
-                                slave-mode;
-                                remote-endpoint = <&replicator1_out_port0>;
+                in-ports {
+                        port {
+                                etb1_in_port: endpoint@0 {
+                                        remote-endpoint = <&replicator1_out_port0>;
+                                };
                         };
                 };
         };
@@ -305,10 +307,11 @@
 
                 clocks = <&clk_375m>;
                 clock-names = "apb_pclk";
-                port {
-                        etb2_in_port: endpoint@0 {
-                                slave-mode;
-                                remote-endpoint = <&replicator2_out_port0>;
+                in-ports {
+                        port {
+                                etb2_in_port: endpoint@0 {
+                                        remote-endpoint = <&replicator2_out_port0>;
+                                };
                         };
                 };
         };
@@ -319,10 +322,11 @@
 
                 clocks = <&clk_375m>;
                 clock-names = "apb_pclk";
-                port {
-                        etb3_in_port: endpoint@0 {
-                                slave-mode;
-                                remote-endpoint = <&replicator3_out_port0>;
+                in-ports {
+                        port {
+                                etb3_in_port: endpoint@0 {
+                                        remote-endpoint = <&replicator3_out_port0>;
+                                };
                         };
                 };
         };
@@ -333,10 +337,11 @@
 
                 clocks = <&clk_375m>;
                 clock-names = "apb_pclk";
-                port {
-                        tpiu_in_port: endpoint@0 {
-                                slave-mode;
-                                remote-endpoint = <&funnel4_out_port0>;
+                in-ports {
+                        port {
+                                tpiu_in_port: endpoint@0 {
+                                        remote-endpoint = <&funnel4_out_port0>;
+                                };
                         };
                 };
         };
@@ -347,7 +352,7 @@
                  */
                 compatible = "arm,coresight-replicator";
 
-                ports {
+                out-ports {
                         #address-cells = <1>;
                         #size-cells = <0>;
 
@@ -365,12 +370,11 @@
                                         remote-endpoint = <&funnel4_in_port0>;
                                 };
                         };
+                };
 
-                        /* replicator input port */
-                        port@2 {
-                                reg = <0>;
+                in-ports {
+                        port {
                                 replicator0_in_port0: endpoint {
-                                        slave-mode;
                                         remote-endpoint = <&funnel0_out_port0>;
                                 };
                         };
@@ -383,7 +387,7 @@
                  */
                 compatible = "arm,coresight-replicator";
 
-                ports {
+                out-ports {
                         #address-cells = <1>;
                         #size-cells = <0>;
 
@@ -401,12 +405,11 @@
                                         remote-endpoint = <&funnel4_in_port1>;
                                 };
                         };
+                };
 
-                        /* replicator input port */
-                        port@2 {
-                                reg = <0>;
+                in-ports {
+                        port {
                                 replicator1_in_port0: endpoint {
-                                        slave-mode;
                                         remote-endpoint = <&funnel1_out_port0>;
                                 };
                         };
@@ -419,11 +422,10 @@
                  */
                 compatible = "arm,coresight-replicator";
 
-                ports {
+                out-ports {
                         #address-cells = <1>;
                         #size-cells = <0>;
 
-                        /* replicator output ports */
                         port@0 {
                                 reg = <0>;
                                 replicator2_out_port0: endpoint {
@@ -437,12 +439,11 @@
                                         remote-endpoint = <&funnel4_in_port2>;
                                 };
                         };
+                };
 
-                        /* replicator input port */
-                        port@2 {
-                                reg = <0>;
+                in-ports {
+                        port {
                                 replicator2_in_port0: endpoint {
-                                        slave-mode;
                                         remote-endpoint = <&funnel2_out_port0>;
                                 };
                         };
@@ -455,11 +456,10 @@
                  */
                 compatible = "arm,coresight-replicator";
 
-                ports {
+                out-ports {
                         #address-cells = <1>;
                         #size-cells = <0>;
 
-                        /* replicator output ports */
                         port@0 {
                                 reg = <0>;
                                 replicator3_out_port0: endpoint {
@@ -473,12 +473,11 @@
                                         remote-endpoint = <&funnel4_in_port3>;
                                 };
                         };
+                };
 
-                        /* replicator input port */
-                        port@2 {
-                                reg = <0>;
+                in-ports {
+                        port {
                                 replicator3_in_port0: endpoint {
-                                        slave-mode;
                                         remote-endpoint = <&funnel3_out_port0>;
                                 };
                         };
@@ -491,48 +490,43 @@
 
                 clocks = <&clk_375m>;
                 clock-names = "apb_pclk";
-                ports {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-
-                        /* funnel output port */
-                        port@0 {
-                                reg = <0>;
+                out-ports {
+                        port {
                                 funnel0_out_port0: endpoint {
                                         remote-endpoint =
                                                 <&replicator0_in_port0>;
                                 };
                         };
+                };
 
-                        /* funnel input ports */
-                        port@1 {
+                in-ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@0 {
                                 reg = <0>;
                                 funnel0_in_port0: endpoint {
-                                        slave-mode;
                                         remote-endpoint = <&ptm0_out_port>;
                                 };
                         };
 
-                        port@2 {
+                        port@1 {
                                 reg = <1>;
                                 funnel0_in_port1: endpoint {
-                                        slave-mode;
                                         remote-endpoint = <&ptm1_out_port>;
                                 };
                         };
 
-                        port@3 {
+                        port@2 {
                                 reg = <2>;
                                 funnel0_in_port2: endpoint {
-                                        slave-mode;
                                         remote-endpoint = <&ptm2_out_port>;
                                 };
                         };
 
-                        port@4 {
+                        port@3 {
                                 reg = <3>;
                                 funnel0_in_port3: endpoint {
-                                        slave-mode;
                                         remote-endpoint = <&ptm3_out_port>;
                                 };
                         };
@@ -545,48 +539,43 @@
 
                 clocks = <&clk_375m>;
                 clock-names = "apb_pclk";
-                ports {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-
-                        /* funnel output port */
-                        port@0 {
-                                reg = <0>;
+                out-ports {
+                        port {
                                 funnel1_out_port0: endpoint {
                                         remote-endpoint =
                                                 <&replicator1_in_port0>;
                                 };
                         };
+                };
 
-                        /* funnel input ports */
-                        port@1 {
+                in-ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@0 {
                                 reg = <0>;
                                 funnel1_in_port0: endpoint {
-                                        slave-mode;
                                         remote-endpoint = <&ptm4_out_port>;
                                 };
                         };
 
-                        port@2 {
+                        port@1 {
                                 reg = <1>;
                                 funnel1_in_port1: endpoint {
-                                        slave-mode;
                                         remote-endpoint = <&ptm5_out_port>;
                                 };
                         };
 
-                        port@3 {
+                        port@2 {
                                 reg = <2>;
                                 funnel1_in_port2: endpoint {
-                                        slave-mode;
                                         remote-endpoint = <&ptm6_out_port>;
                                 };
                         };
 
-                        port@4 {
+                        port@3 {
                                 reg = <3>;
                                 funnel1_in_port3: endpoint {
-                                        slave-mode;
                                         remote-endpoint = <&ptm7_out_port>;
                                 };
                         };
@@ -599,48 +588,43 @@
 
                 clocks = <&clk_375m>;
                 clock-names = "apb_pclk";
-                ports {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-
-                        /* funnel output port */
-                        port@0 {
-                                reg = <0>;
+                out-ports {
+                        port {
                                 funnel2_out_port0: endpoint {
                                         remote-endpoint =
                                                 <&replicator2_in_port0>;
                                 };
                         };
+                };
 
-                        /* funnel input ports */
-                        port@1 {
+                in-ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@0 {
                                 reg = <0>;
                                 funnel2_in_port0: endpoint {
-                                        slave-mode;
                                         remote-endpoint = <&ptm8_out_port>;
                                 };
                         };
 
-                        port@2 {
+                        port@1 {
                                 reg = <1>;
                                 funnel2_in_port1: endpoint {
-                                        slave-mode;
                                         remote-endpoint = <&ptm9_out_port>;
                                 };
                         };
 
-                        port@3 {
+                        port@2 {
                                 reg = <2>;
                                 funnel2_in_port2: endpoint {
-                                        slave-mode;
                                         remote-endpoint = <&ptm10_out_port>;
                                 };
                         };
 
-                        port@4 {
+                        port@3 {
                                 reg = <3>;
                                 funnel2_in_port3: endpoint {
-                                        slave-mode;
                                         remote-endpoint = <&ptm11_out_port>;
                                 };
                         };
@@ -653,48 +637,43 @@
 
                 clocks = <&clk_375m>;
                 clock-names = "apb_pclk";
-                ports {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-
-                        /* funnel output port */
-                        port@0 {
-                                reg = <0>;
+                out-ports {
+                        port {
                                 funnel3_out_port0: endpoint {
                                         remote-endpoint =
                                                 <&replicator3_in_port0>;
                                 };
                         };
+                };
 
-                        /* funnel input ports */
-                        port@1 {
+                in-ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@0 {
                                 reg = <0>;
                                 funnel3_in_port0: endpoint {
-                                        slave-mode;
                                         remote-endpoint = <&ptm12_out_port>;
                                 };
                         };
 
-                        port@2 {
+                        port@1 {
                                 reg = <1>;
                                 funnel3_in_port1: endpoint {
-                                        slave-mode;
                                         remote-endpoint = <&ptm13_out_port>;
                                 };
                         };
 
-                        port@3 {
+                        port@2 {
                                 reg = <2>;
                                 funnel3_in_port2: endpoint {
-                                        slave-mode;
                                         remote-endpoint = <&ptm14_out_port>;
                                 };
                         };
 
-                        port@4 {
+                        port@3 {
                                 reg = <3>;
                                 funnel3_in_port3: endpoint {
-                                        slave-mode;
                                         remote-endpoint = <&ptm15_out_port>;
                                 };
                         };
@@ -707,50 +686,45 @@
 
                 clocks = <&clk_375m>;
                 clock-names = "apb_pclk";
-                ports {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-
-                        /* funnel output port */
-                        port@0 {
-                                reg = <0>;
+                out-ports {
+                        port {
                                 funnel4_out_port0: endpoint {
                                         remote-endpoint = <&tpiu_in_port>;
                                 };
                         };
+                };
 
-                        /* funnel input ports */
-                        port@1 {
+                in-ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@0 {
                                 reg = <0>;
                                 funnel4_in_port0: endpoint {
-                                        slave-mode;
                                         remote-endpoint =
                                                 <&replicator0_out_port1>;
                                 };
                         };
 
-                        port@2 {
+                        port@1 {
                                 reg = <1>;
                                 funnel4_in_port1: endpoint {
-                                        slave-mode;
                                         remote-endpoint =
                                                 <&replicator1_out_port1>;
                                 };
                         };
 
-                        port@3 {
+                        port@2 {
                                 reg = <2>;
                                 funnel4_in_port2: endpoint {
-                                        slave-mode;
                                         remote-endpoint =
                                                 <&replicator2_out_port1>;
                                 };
                         };
 
-                        port@4 {
+                        port@3 {
                                 reg = <3>;
                                 funnel4_in_port3: endpoint {
-                                        slave-mode;
                                         remote-endpoint =
                                                 <&replicator3_out_port1>;
                                 };
@@ -765,9 +739,11 @@
                 clocks = <&clk_375m>;
                 clock-names = "apb_pclk";
                 cpu = <&CPU0>;
-                port {
-                        ptm0_out_port: endpoint {
-                                remote-endpoint = <&funnel0_in_port0>;
+                out-ports {
+                        port {
+                                ptm0_out_port: endpoint {
+                                        remote-endpoint = <&funnel0_in_port0>;
+                                };
                         };
                 };
         };
@@ -779,9 +755,11 @@
                 clocks = <&clk_375m>;
                 clock-names = "apb_pclk";
                 cpu = <&CPU1>;
-                port {
-                        ptm1_out_port: endpoint {
-                                remote-endpoint = <&funnel0_in_port1>;
+                out-ports {
+                        port {
+                                ptm1_out_port: endpoint {
+                                        remote-endpoint = <&funnel0_in_port1>;
+                                };
                         };
                 };
         };
@@ -793,9 +771,11 @@
                 clocks = <&clk_375m>;
                 clock-names = "apb_pclk";
                 cpu = <&CPU2>;
-                port {
-                        ptm2_out_port: endpoint {
-                                remote-endpoint = <&funnel0_in_port2>;
+                out-ports {
+                        port {
+                                ptm2_out_port: endpoint {
+                                        remote-endpoint = <&funnel0_in_port2>;
+                                };
                         };
                 };
         };
@@ -807,9 +787,11 @@
                 clocks = <&clk_375m>;
                 clock-names = "apb_pclk";
                 cpu = <&CPU3>;
-                port {
-                        ptm3_out_port: endpoint {
-                                remote-endpoint = <&funnel0_in_port3>;
+                out-ports {
+                        port {
+                                ptm3_out_port: endpoint {
+                                        remote-endpoint = <&funnel0_in_port3>;
+                                };
                         };
                 };
         };
@@ -821,9 +803,11 @@
                 clocks = <&clk_375m>;
                 clock-names = "apb_pclk";
                 cpu = <&CPU4>;
-                port {
-                        ptm4_out_port: endpoint {
-                                remote-endpoint = <&funnel1_in_port0>;
+                out-ports {
+                        port {
+                                ptm4_out_port: endpoint {
+                                        remote-endpoint = <&funnel1_in_port0>;
+                                };
                         };
                 };
         };
@@ -835,9 +819,11 @@
                 clocks = <&clk_375m>;
                 clock-names = "apb_pclk";
                 cpu = <&CPU5>;
-                port {
-                        ptm5_out_port: endpoint {
-                                remote-endpoint = <&funnel1_in_port1>;
+                out-ports {
+                        port {
+                                ptm5_out_port: endpoint {
+                                        remote-endpoint = <&funnel1_in_port1>;
+                                };
                         };
                 };
         };
@@ -849,9 +835,11 @@
                 clocks = <&clk_375m>;
                 clock-names = "apb_pclk";
                 cpu = <&CPU6>;
-                port {
-                        ptm6_out_port: endpoint {
-                                remote-endpoint = <&funnel1_in_port2>;
+                out-ports {
+                        port {
+                                ptm6_out_port: endpoint {
+                                        remote-endpoint = <&funnel1_in_port2>;
+                                };
                         };
                 };
         };
@@ -863,9 +851,11 @@
                 clocks = <&clk_375m>;
                 clock-names = "apb_pclk";
                 cpu = <&CPU7>;
-                port {
-                        ptm7_out_port: endpoint {
-                                remote-endpoint = <&funnel1_in_port3>;
+                out-ports {
+                        port {
+                                ptm7_out_port: endpoint {
+                                        remote-endpoint = <&funnel1_in_port3>;
+                                };
                         };
                 };
         };
@@ -877,9 +867,11 @@
                 clocks = <&clk_375m>;
                 clock-names = "apb_pclk";
                 cpu = <&CPU8>;
-                port {
-                        ptm8_out_port: endpoint {
-                                remote-endpoint = <&funnel2_in_port0>;
+                out-ports {
+                        port {
+                                ptm8_out_port: endpoint {
+                                        remote-endpoint = <&funnel2_in_port0>;
+                                };
                         };
                 };
         };
@@ -890,9 +882,11 @@
                 clocks = <&clk_375m>;
                 clock-names = "apb_pclk";
                 cpu = <&CPU9>;
-                port {
-                        ptm9_out_port: endpoint {
-                                remote-endpoint = <&funnel2_in_port1>;
+                out-ports {
+                        port {
+                                ptm9_out_port: endpoint {
+                                        remote-endpoint = <&funnel2_in_port1>;
+                                };
                         };
                 };
         };
@@ -904,9 +898,11 @@
                 clocks = <&clk_375m>;
                 clock-names = "apb_pclk";
                 cpu = <&CPU10>;
-                port {
-                        ptm10_out_port: endpoint {
-                                remote-endpoint = <&funnel2_in_port2>;
+                out-ports {
+                        port {
+                                ptm10_out_port: endpoint {
+                                        remote-endpoint = <&funnel2_in_port2>;
+                                };
                         };
                 };
         };
@@ -918,9 +914,11 @@
                 clocks = <&clk_375m>;
                 clock-names = "apb_pclk";
                 cpu = <&CPU11>;
-                port {
-                        ptm11_out_port: endpoint {
-                                remote-endpoint = <&funnel2_in_port3>;
+                out-ports {
+                        port {
+                                ptm11_out_port: endpoint {
+                                        remote-endpoint = <&funnel2_in_port3>;
+                                };
                         };
                 };
         };
@@ -932,9 +930,11 @@
                 clocks = <&clk_375m>;
                 clock-names = "apb_pclk";
                 cpu = <&CPU12>;
-                port {
-                        ptm12_out_port: endpoint {
-                                remote-endpoint = <&funnel3_in_port0>;
+                out-ports {
+                        port {
+                                ptm12_out_port: endpoint {
+                                        remote-endpoint = <&funnel3_in_port0>;
+                                };
                         };
                 };
         };
@@ -946,9 +946,11 @@
                 clocks = <&clk_375m>;
                 clock-names = "apb_pclk";
                 cpu = <&CPU13>;
-                port {
-                        ptm13_out_port: endpoint {
-                                remote-endpoint = <&funnel3_in_port1>;
+                out-ports {
+                        port {
+                                ptm13_out_port: endpoint {
+                                        remote-endpoint = <&funnel3_in_port1>;
+                                };
                         };
                 };
         };
@@ -960,9 +962,11 @@
                 clocks = <&clk_375m>;
                 clock-names = "apb_pclk";
                 cpu = <&CPU14>;
-                port {
-                        ptm14_out_port: endpoint {
-                                remote-endpoint = <&funnel3_in_port2>;
+                out-ports {
+                        port {
+                                ptm14_out_port: endpoint {
+                                        remote-endpoint = <&funnel3_in_port2>;
+                                };
                         };
                 };
         };
@@ -974,9 +978,11 @@
                 clocks = <&clk_375m>;
                 clock-names = "apb_pclk";
                 cpu = <&CPU15>;
-                port {
-                        ptm15_out_port: endpoint {
-                                remote-endpoint = <&funnel3_in_port3>;
+                out-ports {
+                        port {
+                                ptm15_out_port: endpoint {
+                                        remote-endpoint = <&funnel3_in_port3>;
+                                };
                         };
                 };
         };
diff --git a/arch/arm/boot/dts/imx1.dtsi b/arch/arm/boot/dts/imx1.dtsi
index 3edc7b5550d8..b00ece16b853 100644
--- a/arch/arm/boot/dts/imx1.dtsi
+++ b/arch/arm/boot/dts/imx1.dtsi
@@ -164,7 +164,7 @@
                         reg = <0x00210000 0x10000>;
                         ranges;
 
-                        cspi1: cspi@213000 {
+                        cspi1: spi@213000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 compatible = "fsl,imx1-cspi";
@@ -186,7 +186,7 @@
                                 status = "disabled";
                         };
 
-                        cspi2: cspi@219000 {
+                        cspi2: spi@219000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 compatible = "fsl,imx1-cspi";
diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts
index ad2ae25b7b4d..98efe1aeb26a 100644
--- a/arch/arm/boot/dts/imx23-evk.dts
+++ b/arch/arm/boot/dts/imx23-evk.dts
@@ -58,7 +58,7 @@
                                 status = "okay";
                         };
 
-                        ssp0: ssp@80010000 {
+                        ssp0: spi@80010000 {
                                 compatible = "fsl,imx23-mmc";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts
index e9351774c619..31b1e3581ac0 100644
--- a/arch/arm/boot/dts/imx23-olinuxino.dts
+++ b/arch/arm/boot/dts/imx23-olinuxino.dts
@@ -25,7 +25,7 @@
 
         apb@80000000 {
                 apbh@80000000 {
-                        ssp0: ssp@80010000 {
+                        ssp0: spi@80010000 {
                                 compatible = "fsl,imx23-mmc";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
@@ -59,7 +59,7 @@
                                 };
                         };
 
-                        ssp1: ssp@80034000 {
+                        ssp1: spi@80034000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 compatible = "fsl,imx23-spi";
diff --git a/arch/arm/boot/dts/imx23-sansa.dts b/arch/arm/boot/dts/imx23-sansa.dts
index 67de7863ad79..faf701b2adb2 100644
--- a/arch/arm/boot/dts/imx23-sansa.dts
+++ b/arch/arm/boot/dts/imx23-sansa.dts
@@ -55,7 +55,7 @@
 
         apb@80000000 {
                 apbh@80000000 {
-                        ssp0: ssp@80010000 {
+                        ssp0: spi@80010000 {
                                 compatible = "fsl,imx23-mmc";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
@@ -65,7 +65,7 @@
                                 status = "okay";
                         };
 
-                        ssp1: ssp@80034000 {
+                        ssp1: spi@80034000 {
                                 compatible = "fsl,imx23-mmc";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&mmc1_8bit_pins_a>;
diff --git a/arch/arm/boot/dts/imx23-stmp378x_devb.dts b/arch/arm/boot/dts/imx23-stmp378x_devb.dts
index 95c7b918f6d6..2ff6cdf71a55 100644
--- a/arch/arm/boot/dts/imx23-stmp378x_devb.dts
+++ b/arch/arm/boot/dts/imx23-stmp378x_devb.dts
@@ -22,7 +22,7 @@
 
         apb@80000000 {
                 apbh@80000000 {
-                        ssp0: ssp@80010000 {
+                        ssp0: spi@80010000 {
                                 compatible = "fsl,imx23-mmc";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
diff --git a/arch/arm/boot/dts/imx23-xfi3.dts b/arch/arm/boot/dts/imx23-xfi3.dts
index 9616e500b996..db53089fb7fb 100644
--- a/arch/arm/boot/dts/imx23-xfi3.dts
+++ b/arch/arm/boot/dts/imx23-xfi3.dts
@@ -54,7 +54,7 @@
 
         apb@80000000 {
                 apbh@80000000 {
-                        ssp0: ssp@80010000 {
+                        ssp0: spi@80010000 {
                                 compatible = "fsl,imx23-mmc";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
@@ -64,7 +64,7 @@
                                 status = "okay";
                         };
 
-                        ssp1: ssp@80034000 {
+                        ssp1: spi@80034000 {
                                 compatible = "fsl,imx23-mmc";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&mmc1_4bit_pins_a>;
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 71bfd2b15609..ea259927eef6 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -93,7 +93,7 @@
                                 status = "disabled";
                         };
 
-                        ssp0: ssp@80010000 {
+                        ssp0: spi@80010000 {
                                 reg = <0x80010000 0x2000>;
                                 interrupts = <15>;
                                 clocks = <&clks 33>;
@@ -457,7 +457,7 @@
                                 status = "disabled";
                         };
 
-                        ssp1: ssp@80034000 {
+                        ssp1: spi@80034000 {
                                 reg = <0x80034000 0x2000>;
                                 interrupts = <2>;
                                 clocks = <&clks 33>;
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index 85c15ee63272..b25309d26ea5 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -168,7 +168,7 @@
                                 status = "disabled";
                         };
 
-                        spi1: cspi@43fa4000 {
+                        spi1: spi@43fa4000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
@@ -209,7 +209,7 @@
                         reg = <0x50000000 0x40000>;
                         ranges;
 
-                        spi3: cspi@50004000 {
+                        spi3: spi@50004000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
@@ -238,7 +238,7 @@
                                 status = "disabled";
                         };
 
-                        spi2: cspi@50010000 {
+                        spi2: spi@50010000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 753d88df1627..151b0eb17dda 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -209,7 +209,7 @@
                                 status = "disabled";
                         };
 
-                        cspi1: cspi@1000e000 {
+                        cspi1: spi@1000e000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 compatible = "fsl,imx27-cspi";
@@ -221,7 +221,7 @@
                                 status = "disabled";
                         };
 
-                        cspi2: cspi@1000f000 {
+                        cspi2: spi@1000f000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 compatible = "fsl,imx27-cspi";
@@ -373,7 +373,7 @@
                                 status = "disabled";
                         };
 
-                        cspi3: cspi@10017000 {
+                        cspi3: spi@10017000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 compatible = "fsl,imx27-cspi";
diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts
index c4fadbc1b400..8df5ec470376 100644
--- a/arch/arm/boot/dts/imx28-apf28dev.dts
+++ b/arch/arm/boot/dts/imx28-apf28dev.dts
@@ -18,7 +18,7 @@
 
         apb@80000000 {
                 apbh@80000000 {
-                        ssp0: ssp@80010000 {
+                        ssp0: spi@80010000 {
                                 compatible = "fsl,imx28-mmc";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&mmc0_4bit_pins_a
@@ -27,7 +27,7 @@
                                 status = "okay";
                         };
 
-                        ssp2: ssp@80014000 {
+                        ssp2: spi@80014000 {
                                 compatible = "fsl,imx28-spi";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&spi2_pins_a>;
diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts
index 96faa53ba44c..6c9b498305c0 100644
--- a/arch/arm/boot/dts/imx28-apx4devkit.dts
+++ b/arch/arm/boot/dts/imx28-apx4devkit.dts
@@ -18,7 +18,7 @@
                                 status = "okay";
                         };
 
-                        ssp0: ssp@80010000 {
+                        ssp0: spi@80010000 {
                                 compatible = "fsl,imx28-mmc";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_sck_cfg>;
@@ -26,7 +26,7 @@
                                 status = "okay";
                         };
 
-                        ssp2: ssp@80014000 {
+                        ssp2: spi@80014000 {
                                 compatible = "fsl,imx28-mmc";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&mmc2_4bit_pins_apx4 &mmc2_sck_cfg_apx4>;
diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts
index e54f5aba7091..8337ca21e281 100644
--- a/arch/arm/boot/dts/imx28-cfa10036.dts
+++ b/arch/arm/boot/dts/imx28-cfa10036.dts
@@ -66,7 +66,7 @@
 
                         };
 
-                        ssp0: ssp@80010000 {
+                        ssp0: spi@80010000 {
                                 compatible = "fsl,imx28-mmc";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&mmc0_4bit_pins_a
diff --git a/arch/arm/boot/dts/imx28-duckbill-2-485.dts b/arch/arm/boot/dts/imx28-duckbill-2-485.dts
index 97084e463d7c..f4f2b3d16c8e 100644
--- a/arch/arm/boot/dts/imx28-duckbill-2-485.dts
+++ b/arch/arm/boot/dts/imx28-duckbill-2-485.dts
@@ -25,7 +25,7 @@
 
         apb@80000000 {
                 apbh@80000000 {
-                        ssp0: ssp@80010000 {
+                        ssp0: spi@80010000 {
                                 compatible = "fsl,imx28-mmc";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&mmc0_8bit_pins_a
@@ -36,7 +36,7 @@
                                 non-removable;
                         };
 
-                        ssp2: ssp@80014000 {
+                        ssp2: spi@80014000 {
                                 compatible = "fsl,imx28-mmc";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&mmc2_4bit_pins_b
diff --git a/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts b/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts
index 22215337f72a..71d0fcbc2d8c 100644
--- a/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts
+++ b/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts
@@ -26,7 +26,7 @@
 
         apb@80000000 {
                 apbh@80000000 {
-                        ssp0: ssp@80010000 {
+                        ssp0: spi@80010000 {
                                 compatible = "fsl,imx28-mmc";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&mmc0_8bit_pins_a
@@ -37,7 +37,7 @@
                                 non-removable;
                         };
 
-                        ssp2: ssp@80014000 {
+                        ssp2: spi@80014000 {
                                 compatible = "fsl,imx28-mmc";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&mmc2_4bit_pins_b
diff --git a/arch/arm/boot/dts/imx28-duckbill-2-spi.dts b/arch/arm/boot/dts/imx28-duckbill-2-spi.dts
index 13e7b134da9e..6580ec6e26ba 100644
--- a/arch/arm/boot/dts/imx28-duckbill-2-spi.dts
+++ b/arch/arm/boot/dts/imx28-duckbill-2-spi.dts
@@ -29,7 +29,7 @@
 
         apb@80000000 {
                 apbh@80000000 {
-                        ssp0: ssp@80010000 {
+                        ssp0: spi@80010000 {
                                 compatible = "fsl,imx28-mmc";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&mmc0_8bit_pins_a
@@ -40,7 +40,7 @@
                                 non-removable;
                         };
 
-                        ssp2: ssp@80014000 {
+                        ssp2: spi@80014000 {
                                 compatible = "fsl,imx28-spi";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&spi2_pins_a>;
diff --git a/arch/arm/boot/dts/imx28-duckbill-2.dts b/arch/arm/boot/dts/imx28-duckbill-2.dts
index 88556c93b00f..693634edae99 100644
--- a/arch/arm/boot/dts/imx28-duckbill-2.dts
+++ b/arch/arm/boot/dts/imx28-duckbill-2.dts
@@ -25,7 +25,7 @@
 
         apb@80000000 {
                 apbh@80000000 {
-                        ssp0: ssp@80010000 {
+                        ssp0: spi@80010000 {
                                 compatible = "fsl,imx28-mmc";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&mmc0_8bit_pins_a
@@ -36,7 +36,7 @@
                                 non-removable;
                         };
 
-                        ssp2: ssp@80014000 {
+                        ssp2: spi@80014000 {
                                 compatible = "fsl,imx28-mmc";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&mmc2_4bit_pins_b
diff --git a/arch/arm/boot/dts/imx28-duckbill.dts b/arch/arm/boot/dts/imx28-duckbill.dts
index f286bfe699be..16f524428ed7 100644
--- a/arch/arm/boot/dts/imx28-duckbill.dts
+++ b/arch/arm/boot/dts/imx28-duckbill.dts
@@ -24,7 +24,7 @@
 
         apb@80000000 {
                 apbh@80000000 {
-                        ssp0: ssp@80010000 {
+                        ssp0: spi@80010000 {
                                 compatible = "fsl,imx28-mmc";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&mmc0_4bit_pins_a
@@ -34,7 +34,7 @@
                                 status = "okay";
                         };
 
-                        ssp2: ssp@80014000 {
+                        ssp2: spi@80014000 {
                                 compatible = "fsl,imx28-spi";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&spi2_pins_a>;
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index 93ab5bdfe068..5778300f44e8 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -103,7 +103,7 @@
                                 status = "okay";
                         };
 
-                        ssp0: ssp@80010000 {
+                        ssp0: spi@80010000 {
                                 compatible = "fsl,imx28-mmc";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&mmc0_8bit_pins_a
@@ -114,13 +114,13 @@
                                 status = "okay";
                         };
 
-                        ssp1: ssp@80012000 {
+                        ssp1: spi@80012000 {
                                 compatible = "fsl,imx28-mmc";
                                 bus-width = <8>;
                                 wp-gpios = <&gpio0 28 0>;
                         };
 
-                        ssp2: ssp@80014000 {
+                        ssp2: spi@80014000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 compatible = "fsl,imx28-spi";
diff --git a/arch/arm/boot/dts/imx28-m28cu3.dts b/arch/arm/boot/dts/imx28-m28cu3.dts
index 3bb5ffc644d6..8883d36a51b5 100644
--- a/arch/arm/boot/dts/imx28-m28cu3.dts
+++ b/arch/arm/boot/dts/imx28-m28cu3.dts
@@ -41,7 +41,7 @@
                                 };
                         };
 
-                        ssp0: ssp@80010000 {
+                        ssp0: spi@80010000 {
                                 compatible = "fsl,imx28-mmc";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&mmc0_4bit_pins_a
@@ -52,7 +52,7 @@
                                 status = "okay";
                         };
 
-                        ssp2: ssp@80014000 {
+                        ssp2: spi@80014000 {
                                 compatible = "fsl,imx28-mmc";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&mmc2_4bit_pins_a
diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts
index 7d97a0ce74a3..893886d17b2d 100644
--- a/arch/arm/boot/dts/imx28-m28evk.dts
+++ b/arch/arm/boot/dts/imx28-m28evk.dts
@@ -18,7 +18,7 @@
 
         apb@80000000 {
                 apbh@80000000 {
-                        ssp0: ssp@80010000 {
+                        ssp0: spi@80010000 {
                                 compatible = "fsl,imx28-mmc";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&mmc0_8bit_pins_a
@@ -30,7 +30,7 @@
                                 status = "okay";
                         };
 
-                        ssp2: ssp@80014000 {
+                        ssp2: spi@80014000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 compatible = "fsl,imx28-spi";
diff --git a/arch/arm/boot/dts/imx28-sps1.dts b/arch/arm/boot/dts/imx28-sps1.dts
index 2393e83979e0..ea9212f6ecda 100644
--- a/arch/arm/boot/dts/imx28-sps1.dts
+++ b/arch/arm/boot/dts/imx28-sps1.dts
@@ -40,7 +40,7 @@
 
                         };
 
-                        ssp0: ssp@80010000 {
+                        ssp0: spi@80010000 {
                                 compatible = "fsl,imx28-mmc";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&mmc0_4bit_pins_a>;
@@ -48,7 +48,7 @@
                                 status = "okay";
                         };
 
-                        ssp2: ssp@80014000 {
+                        ssp2: spi@80014000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 compatible = "fsl,imx28-spi";
diff --git a/arch/arm/boot/dts/imx28-ts4600.dts b/arch/arm/boot/dts/imx28-ts4600.dts
index f8a09a8c2c36..dccdd6bcd0b2 100644
--- a/arch/arm/boot/dts/imx28-ts4600.dts
+++ b/arch/arm/boot/dts/imx28-ts4600.dts
@@ -25,7 +25,7 @@
 
         apb@80000000 {
                 apbh@80000000 {
-                        ssp0: ssp@80010000 {
+                        ssp0: spi@80010000 {
                                 compatible = "fsl,imx28-mmc";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&mmc0_4bit_pins_a
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 5107fdc482ea..2b7efb659fc0 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -117,7 +117,7 @@
                                 status = "disabled";
                         };
 
-                        ssp0: ssp@80010000 {
+                        ssp0: spi@80010000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 reg = <0x80010000 0x2000>;
@@ -128,7 +128,7 @@
                                 status = "disabled";
                         };
 
-                        ssp1: ssp@80012000 {
+                        ssp1: spi@80012000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 reg = <0x80012000 0x2000>;
@@ -139,7 +139,7 @@
                                 status = "disabled";
                         };
 
-                        ssp2: ssp@80014000 {
+                        ssp2: spi@80014000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 reg = <0x80014000 0x2000>;
@@ -150,7 +150,7 @@
                                 status = "disabled";
                         };
 
-                        ssp3: ssp@80016000 {
+                        ssp3: spi@80016000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 reg = <0x80016000 0x2000>;
diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi
index ca1419ca303c..af7afccf5f2f 100644
--- a/arch/arm/boot/dts/imx31.dtsi
+++ b/arch/arm/boot/dts/imx31.dtsi
@@ -206,7 +206,7 @@
                                 status = "disabled";
                         };
 
-                        spi2: cspi@50010000 {
+                        spi2: spi@50010000 {
                                 compatible = "fsl,imx31-cspi";
                                 reg = <0x50010000 0x4000>;
                                 interrupts = <13>;
@@ -241,7 +241,7 @@
                                 #clock-cells = <1>;
                         };
 
-                        spi3: cspi@53f84000 {
+                        spi3: spi@53f84000 {
                                 compatible = "fsl,imx31-cspi";
                                 reg = <0x53f84000 0x4000>;
                                 interrupts = <17>;
diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi
index 1c50b785cad4..a1c3d28e8771 100644
--- a/arch/arm/boot/dts/imx35.dtsi
+++ b/arch/arm/boot/dts/imx35.dtsi
@@ -133,7 +133,7 @@
                                 status = "disabled";
                         };
 
-                        spi1: cspi@43fa4000 {
+                        spi1: spi@43fa4000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 compatible = "fsl,imx35-cspi";
@@ -174,7 +174,7 @@
                                 status = "disabled";
                         };
 
-                        spi2: cspi@50010000 {
+                        spi2: spi@50010000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 compatible = "fsl,imx35-cspi";
diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi
index 7fae2ffb76fe..95b7fba58300 100644
--- a/arch/arm/boot/dts/imx50.dtsi
+++ b/arch/arm/boot/dts/imx50.dtsi
@@ -140,7 +140,7 @@
                                         status = "disabled";
                                 };
 
-                                ecspi1: ecspi@50010000 {
+                                ecspi1: spi@50010000 {
                                         #address-cells = <1>;
                                         #size-cells = <0>;
                                         compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
@@ -403,7 +403,7 @@
                                 status = "disabled";
                         };
 
-                        ecspi2: ecspi@63fac000 {
+                        ecspi2: spi@63fac000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 compatible = "fsl,imx50-ecspi", "fsl,imx51-ecspi";
@@ -426,7 +426,7 @@
                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";
                         };
 
-                        cspi: cspi@63fc0000 {
+                        cspi: spi@63fc0000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 compatible = "fsl,imx50-cspi", "fsl,imx35-cspi";
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index ba60b0cb3cc1..35ee1b4247c3 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -204,6 +204,7 @@
                 reg = <0>;
                 interrupt-parent = <&gpio1>;
                 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+                fsl,mc13xxx-uses-adc;
                 fsl,mc13xxx-uses-rtc;
 
                 regulators {
diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts
index 469cce2c0357..e45a15ceb94b 100644
--- a/arch/arm/boot/dts/imx51-zii-rdu1.dts
+++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts
@@ -508,7 +508,7 @@
         };
 
         ds1341: rtc@68 {
-                compatible = "maxim,ds1341";
+                compatible = "dallas,ds1341";
                 reg = <0x68>;
         };
 
diff --git a/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts b/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts
index 26cf08549df4..243d1c8cab0a 100644
--- a/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts
+++ b/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts
@@ -342,6 +342,14 @@
         vcc-supply = <&vusb2_reg>;
 };
 
+&vpu {
+        status = "disabled";
+};
+
+&wdog1 {
+        status = "disabled";
+};
+
 &iomuxc {
         pinctrl_ecspi1: ecspi1grp {
                 fsl,pins = <
diff --git a/arch/arm/boot/dts/imx51-zii-scu3-esb.dts b/arch/arm/boot/dts/imx51-zii-scu3-esb.dts
index e6ebac8f43e4..14b207778114 100644
--- a/arch/arm/boot/dts/imx51-zii-scu3-esb.dts
+++ b/arch/arm/boot/dts/imx51-zii-scu3-esb.dts
@@ -350,6 +350,10 @@
         vcc-supply = <&vusb2_reg>;
 };
 
+&vpu {
+        status = "disabled";
+};
+
 &wdog1 {
         status = "disabled";
 };
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 5c4ba91e43ba..67d462715048 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -197,7 +197,7 @@
                                         status = "disabled";
                                 };
 
-                                ecspi1: ecspi@70010000 {
+                                ecspi1: spi@70010000 {
                                         #address-cells = <1>;
                                         #size-cells = <0>;
                                         compatible = "fsl,imx51-ecspi";
@@ -464,7 +464,7 @@
                                 status = "disabled";
                         };
 
-                        ecspi2: ecspi@83fac000 {
+                        ecspi2: spi@83fac000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 compatible = "fsl,imx51-ecspi";
@@ -487,7 +487,7 @@
                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
                         };
 
-                        cspi: cspi@83fc0000 {
+                        cspi: spi@83fc0000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
@@ -608,7 +608,7 @@
                                 status = "disabled";
                         };
 
-                        vpu@83ff4000 {
+                        vpu: vpu@83ff4000 {
                                 compatible = "fsl,imx51-vpu", "cnm,codahx4";
                                 reg = <0x83ff4000 0x1000>;
                                 interrupts = <9>;
diff --git a/arch/arm/boot/dts/imx53-ppd.dts b/arch/arm/boot/dts/imx53-ppd.dts
index cdb90bee7b4a..b560ff88459b 100644
--- a/arch/arm/boot/dts/imx53-ppd.dts
+++ b/arch/arm/boot/dts/imx53-ppd.dts
@@ -319,7 +319,6 @@
 &ecspi2 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_ecspi2>;
-        num-chipselects = <1>;
         cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
         status = "okay";
 
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 6386185ae234..207eb557c90e 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -259,7 +259,7 @@
                                         status = "disabled";
                                 };
 
-                                ecspi1: ecspi@50010000 {
+                                ecspi1: spi@50010000 {
                                         #address-cells = <1>;
                                         #size-cells = <0>;
                                         compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
@@ -684,7 +684,7 @@
                                 status = "disabled";
                         };
 
-                        ecspi2: ecspi@63fac000 {
+                        ecspi2: spi@63fac000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
@@ -707,7 +707,7 @@
                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
                         };
 
-                        cspi: cspi@63fc0000 {
+                        cspi: spi@63fc0000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
index 9de45a717356..d08e0402793b 100644
--- a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
@@ -146,7 +146,7 @@
 &ecspi4 {
         status = "okay";
 
-        mcp251x0: mcp251x@1 {
+        mcp251x0: mcp251x@0 {
                 compatible = "microchip,mcp2515";
                 reg = <0>;
                 clocks = <&clk16m>;
diff --git a/arch/arm/boot/dts/imx6dl-icore-mipi.dts b/arch/arm/boot/dts/imx6dl-icore-mipi.dts
index bf53f0552aa1..e43bccb78ab2 100644
--- a/arch/arm/boot/dts/imx6dl-icore-mipi.dts
+++ b/arch/arm/boot/dts/imx6dl-icore-mipi.dts
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// SPDX-License-Identifier: GPL-2.0 OR X11
 /*
  * Copyright (C) 2018 Engicam S.r.l.
  * Copyright (C) 2018 Amarula Solutions B.V.
diff --git a/arch/arm/boot/dts/imx6dl-icore-rqs.dts b/arch/arm/boot/dts/imx6dl-icore-rqs.dts
index 1281bc39b7ab..73d710d34b9d 100644
--- a/arch/arm/boot/dts/imx6dl-icore-rqs.dts
+++ b/arch/arm/boot/dts/imx6dl-icore-rqs.dts
@@ -1,43 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
 /*
  * Copyright (C) 2016 Amarula Solutions B.V.
  * Copyright (C) 2016 Engicam S.r.l.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License
- *     version 2 as published by the Free Software Foundation.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
diff --git a/arch/arm/boot/dts/imx6dl-icore.dts b/arch/arm/boot/dts/imx6dl-icore.dts
index 971f9fc39c66..80fa60607ab1 100644
--- a/arch/arm/boot/dts/imx6dl-icore.dts
+++ b/arch/arm/boot/dts/imx6dl-icore.dts
@@ -1,43 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
 /*
  * Copyright (C) 2016 Amarula Solutions B.V.
  * Copyright (C) 2016 Engicam S.r.l.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License
- *     version 2 as published by the Free Software Foundation.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts
index dd3226fe5ecd..8e51491e68cf 100644
--- a/arch/arm/boot/dts/imx6dl-riotboard.dts
+++ b/arch/arm/boot/dts/imx6dl-riotboard.dts
@@ -84,6 +84,10 @@
         status = "okay";
 };
 
+&clks {
+        fsl,pmic-stby-poweroff;
+};
+
 &fec {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_enet>;
@@ -164,6 +168,7 @@
                 reg = <0x08>;
                 interrupt-parent = <&gpio5>;
                 interrupts = <16 8>;
+                fsl,pmic-stby-poweroff;
 
                 regulators {
                         reg_vddcore: sw1ab {                            /* VDDARM_IN */
diff --git a/arch/arm/boot/dts/imx6q-apalis-eval.dts b/arch/arm/boot/dts/imx6q-apalis-eval.dts
index 707ac9a46115..0edd3043d9c1 100644
--- a/arch/arm/boot/dts/imx6q-apalis-eval.dts
+++ b/arch/arm/boot/dts/imx6q-apalis-eval.dts
@@ -196,6 +196,8 @@
 };
 
 &pcie {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_reset_moci>;
         /* active-high meaning opposite of regular PERST# active-low polarity */
         reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
         reset-gpio-active-high;
diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
index 4e1c8feaef82..b94bb687be6b 100644
--- a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
+++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
@@ -196,6 +196,8 @@
 };
 
 &pcie {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_reset_moci>;
         /* active-high meaning opposite of regular PERST# active-low polarity */
         reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
         reset-gpio-active-high;
diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora.dts b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
index 469e3d0e2827..302fd6adc8a7 100644
--- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts
+++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
@@ -200,6 +200,8 @@
 };
 
 &pcie {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_reset_moci>;
         /* active-high meaning opposite of regular PERST# active-low polarity */
         reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
         reset-gpio-active-high;
diff --git a/arch/arm/boot/dts/imx6q-icore-mipi.dts b/arch/arm/boot/dts/imx6q-icore-mipi.dts
index 95b2efda17b4..d51745268dbf 100644
--- a/arch/arm/boot/dts/imx6q-icore-mipi.dts
+++ b/arch/arm/boot/dts/imx6q-icore-mipi.dts
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// SPDX-License-Identifier: GPL-2.0 OR X11
 /*
  * Copyright (C) 2017 Engicam S.r.l.
  * Copyright (C) 2017 Amarula Solutions B.V.
@@ -8,10 +8,10 @@
 /dts-v1/;
 
 #include "imx6q.dtsi"
-#include "imx6qdl-icore.dtsi"
+#include "imx6qdl-icore-1.5.dtsi"
 
 / {
-        model = "Engicam i.CoreM6 Quad/Dual MIPI Starter Kit";
+        model = "Engicam i.CoreM6 1.5 Quad/Dual MIPI Starter Kit";
         compatible = "engicam,imx6-icore", "fsl,imx6q";
 };
 
diff --git a/arch/arm/boot/dts/imx6q-icore-ofcap10.dts b/arch/arm/boot/dts/imx6q-icore-ofcap10.dts
index 49b60ca20e6d..81cc346dd149 100644
--- a/arch/arm/boot/dts/imx6q-icore-ofcap10.dts
+++ b/arch/arm/boot/dts/imx6q-icore-ofcap10.dts
@@ -1,43 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (C) 2016 Amarula Solutions B.V.
  * Copyright (C) 2016 Engicam S.r.l.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License
- *     version 2 as published by the Free Software Foundation.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
diff --git a/arch/arm/boot/dts/imx6q-icore-ofcap12.dts b/arch/arm/boot/dts/imx6q-icore-ofcap12.dts
index 6e27c8143f82..241811c52b62 100644
--- a/arch/arm/boot/dts/imx6q-icore-ofcap12.dts
+++ b/arch/arm/boot/dts/imx6q-icore-ofcap12.dts
@@ -1,43 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (C) 2016 Amarula Solutions B.V.
  * Copyright (C) 2016 Engicam S.r.l.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License
- *     version 2 as published by the Free Software Foundation.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
diff --git a/arch/arm/boot/dts/imx6q-icore-rqs.dts b/arch/arm/boot/dts/imx6q-icore-rqs.dts
index b81f48c6a8c6..cf6ba724f497 100644
--- a/arch/arm/boot/dts/imx6q-icore-rqs.dts
+++ b/arch/arm/boot/dts/imx6q-icore-rqs.dts
@@ -1,42 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (C) 2015 Amarula Solutions B.V.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License
- *     version 2 as published by the Free Software Foundation.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
+ * Copyright (C) 2015 Engicam S.r.l.
  */
 
 /dts-v1/;
diff --git a/arch/arm/boot/dts/imx6q-icore.dts b/arch/arm/boot/dts/imx6q-icore.dts
index 5613dd9dc469..fe28c3cf54c0 100644
--- a/arch/arm/boot/dts/imx6q-icore.dts
+++ b/arch/arm/boot/dts/imx6q-icore.dts
@@ -1,43 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
 /*
  * Copyright (C) 2016 Amarula Solutions B.V.
  * Copyright (C) 2016 Engicam S.r.l.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License
- *     version 2 as published by the Free Software Foundation.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 0193ee6fe964..8381d24eff7d 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -163,7 +163,7 @@
 
                 aips-bus@2000000 { /* AIPS1 */
                         spba-bus@2000000 {
-                                ecspi5: ecspi@2018000 {
+                                ecspi5: spi@2018000 {
                                         #address-cells = <1>;
                                         #size-cells = <0>;
                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
index 05f07ea3e8c8..3dc99dd8dde1 100644
--- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
@@ -482,10 +482,6 @@
 };
 
 &iomuxc {
-        /* pins used on module */
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_reset_moci>;
-
         pinctrl_apalis_gpio1: gpio2io04grp {
                 fsl,pins = <
                         MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0
diff --git a/arch/arm/boot/dts/imx6qdl-icore-1.5.dtsi b/arch/arm/boot/dts/imx6qdl-icore-1.5.dtsi
new file mode 100644
index 000000000000..d91d46b5898f
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-icore-1.5.dtsi
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Jacopo Mondi <jacopo@jmondi.org>
+ */
+
+#include "imx6qdl-icore.dtsi"
+
+&iomuxc {
+        pinctrl_enet: enetgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN      0x1b0b0
+                        MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0b0
+                        MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
+                        MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1     0x1b0b0
+                        MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0     0x1b0b0
+                        MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1     0x1b0b0
+                        MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0     0x1b0b0
+                        MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
+                        MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
+                        MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x1b0b0
+                >;
+        };
+};
+
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet>;
+        phy-reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
+        clocks = <&clks IMX6QDL_CLK_ENET>,
+                 <&clks IMX6QDL_CLK_ENET>,
+                 <&clks IMX6QDL_CLK_ENET_REF>;
+        phy-mode = "rmii";
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
index acc3b11fba2a..ba93026ecee8 100644
--- a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
@@ -1,42 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
 /*
  * Copyright (C) 2015 Amarula Solutions B.V.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License
- *     version 2 as published by the Free Software Foundation.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
+ * Copyright (C) 2015 Engicam S.r.l.
  */
 
 #include <dt-bindings/gpio/gpio.h>
@@ -316,7 +281,7 @@
 };
 
 &iomuxc {
-        pinctrl_audmux: audmux {
+        pinctrl_audmux: audmuxgrp {
                 fsl,pins = <
                         MX6QDL_PAD_DISP0_DAT20__AUD4_TXC  0x130b0
                         MX6QDL_PAD_DISP0_DAT21__AUD4_TXD  0x110b0
diff --git a/arch/arm/boot/dts/imx6qdl-icore.dtsi b/arch/arm/boot/dts/imx6qdl-icore.dtsi
index 9ce993776160..84d03c65f4c8 100644
--- a/arch/arm/boot/dts/imx6qdl-icore.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-icore.dtsi
@@ -1,43 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
 /*
  * Copyright (C) 2016 Amarula Solutions B.V.
  * Copyright (C) 2016 Engicam S.r.l.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License
- *     version 2 as published by the Free Software Foundation.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 #include <dt-bindings/gpio/gpio.h>
@@ -310,7 +274,7 @@
 };
 
 &iomuxc {
-        pinctrl_audmux: audmux {
+        pinctrl_audmux: audmuxgrp {
                 fsl,pins = <
                         MX6QDL_PAD_DISP0_DAT20__AUD4_TXC  0x130b0
                         MX6QDL_PAD_DISP0_DAT21__AUD4_TXD  0x110b0
@@ -349,7 +313,7 @@
                 >;
         };
 
-        pinctrl_gpmi_nand: gpmi-nand {
+        pinctrl_gpmi_nand: gpminandgrp {
                 fsl,pins = <
                         MX6QDL_PAD_NANDF_CLE__NAND_CLE     0xb0b1
                         MX6QDL_PAD_NANDF_ALE__NAND_ALE     0xb0b1
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index 9f11f1fcc3e6..a6dc5c42c632 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -4,6 +4,7 @@
 // Copyright 2011 Linaro Ltd.
 
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
 
 / {
         chosen {
@@ -25,6 +26,47 @@
                 };
         };
 
+        gpio-keys {
+                compatible = "gpio-keys";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_gpio_keys>;
+
+                home {
+                        label = "Home";
+                        gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_HOME>;
+                        wakeup-source;
+                };
+
+                back {
+                        label = "Back";
+                        gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_BACK>;
+                        wakeup-source;
+                };
+
+                program {
+                        label = "Program";
+                        gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_PROGRAM>;
+                        wakeup-source;
+                };
+
+                volume-up {
+                        label = "Volume Up";
+                        gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_VOLUMEUP>;
+                        wakeup-source;
+                };
+
+                volume-down {
+                        label = "Volume Down";
+                        gpios = <&gpio5 14 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_VOLUMEDOWN>;
+                        wakeup-source;
+                };
+        };
+
         clocks {
                 codec_osc: anaclk2 {
                         compatible = "fixed-clock";
@@ -375,6 +417,15 @@
                 VLC-supply = <&reg_audio>;
         };
 
+        touchscreen@4 {
+                compatible = "eeti,egalax_ts";
+                reg = <0x04>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_egalax_int>;
+                interrupt-parent = <&gpio2>;
+                interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
+                wakeup-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
+        };
 };
 
 &i2c3 {
@@ -410,6 +461,12 @@
                         >;
                 };
 
+                pinctrl_egalax_int: egalax-intgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_EB0__GPIO2_IO28          0xb0b1
+                        >;
+                };
+
                 pinctrl_enet: enetgrp {
                         fsl,pins = <
                                 MX6QDL_PAD_KEY_COL1__ENET_MDIO          0x1b0b0
@@ -446,6 +503,16 @@
                         >;
                 };
 
+                pinctrl_gpio_keys: gpiokeysgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD2_CMD__GPIO1_IO11          0x1b0b0
+                                MX6QDL_PAD_SD2_DAT3__GPIO1_IO12         0x1b0b0
+                                MX6QDL_PAD_SD4_DAT4__GPIO2_IO12         0x1b0b0
+                                MX6QDL_PAD_SD4_DAT7__GPIO2_IO15         0x1b0b0
+                                MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14      0x1b0b0
+                        >;
+                };
+
                 pinctrl_gpio_leds: gpioledsgrp {
                         fsl,pins = <
                                 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15      0x80000000
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
index 381bf61fcd28..b7d5fb421404 100644
--- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
@@ -8,6 +8,10 @@
 #include <dt-bindings/gpio/gpio.h>
 
 / {
+        chosen {
+                stdout-path = &uart1;
+        };
+
         sound {
                 compatible = "fsl,imx6-wandboard-sgtl5000",
                              "fsl,imx-audio-sgtl5000";
diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
index 7fff3717cf7c..85e79a33bcd4 100644
--- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
@@ -813,6 +813,10 @@
         status = "okay";
 };
 
+&snvs_rtc {
+        status = "disabled";
+};
+
 &ssi1 {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 61d2d26afbf4..e4daf150881a 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -317,7 +317,7 @@
                                         status = "disabled";
                                 };
 
-                                ecspi1: ecspi@2008000 {
+                                ecspi1: spi@2008000 {
                                         #address-cells = <1>;
                                         #size-cells = <0>;
                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
@@ -331,7 +331,7 @@
                                         status = "disabled";
                                 };
 
-                                ecspi2: ecspi@200c000 {
+                                ecspi2: spi@200c000 {
                                         #address-cells = <1>;
                                         #size-cells = <0>;
                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
@@ -345,7 +345,7 @@
                                         status = "disabled";
                                 };
 
-                                ecspi3: ecspi@2010000 {
+                                ecspi3: spi@2010000 {
                                         #address-cells = <1>;
                                         #size-cells = <0>;
                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
@@ -359,7 +359,7 @@
                                         status = "disabled";
                                 };
 
-                                ecspi4: ecspi@2014000 {
+                                ecspi4: spi@2014000 {
                                         #address-cells = <1>;
                                         #size-cells = <0>;
                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 7a4f5dace902..7a3ae7160c12 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -168,7 +168,7 @@
                                         status = "disabled";
                                 };
 
-                                ecspi1: ecspi@2008000 {
+                                ecspi1: spi@2008000 {
                                         #address-cells = <1>;
                                         #size-cells = <0>;
                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
@@ -180,7 +180,7 @@
                                         status = "disabled";
                                 };
 
-                                ecspi2: ecspi@200c000 {
+                                ecspi2: spi@200c000 {
                                         #address-cells = <1>;
                                         #size-cells = <0>;
                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
@@ -192,7 +192,7 @@
                                         status = "disabled";
                                 };
 
-                                ecspi3: ecspi@2010000 {
+                                ecspi3: spi@2010000 {
                                         #address-cells = <1>;
                                         #size-cells = <0>;
                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
@@ -204,7 +204,7 @@
                                         status = "disabled";
                                 };
 
-                                ecspi4: ecspi@2014000 {
+                                ecspi4: spi@2014000 {
                                         #address-cells = <1>;
                                         #size-cells = <0>;
                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi
index 000e6136a9d6..ed9a980bce85 100644
--- a/arch/arm/boot/dts/imx6sll.dtsi
+++ b/arch/arm/boot/dts/imx6sll.dtsi
@@ -375,10 +375,12 @@
                                 reg = <0x0209c000 0x4000>;
                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX6SLL_CLK_GPIO1>;
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
                                 #interrupt-cells = <2>;
+                                gpio-ranges = <&iomuxc 0 94 7>, <&iomuxc 7 25 25>;
                         };
 
                         gpio2: gpio@20a0000 {
@@ -386,10 +388,12 @@
                                 reg = <0x020a0000 0x4000>;
                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX6SLL_CLK_GPIO2>;
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
                                 #interrupt-cells = <2>;
+                                gpio-ranges = <&iomuxc 0 50 32>;
                         };
 
                         gpio3: gpio@20a4000 {
@@ -397,10 +401,14 @@
                                 reg = <0x020a4000 0x4000>;
                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX6SLL_CLK_GPIO3>;
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
                                 #interrupt-cells = <2>;
+                                gpio-ranges = <&iomuxc 0 82 12>, <&iomuxc 12 103 4>,
+                                              <&iomuxc 16 101 2>, <&iomuxc 18 5 1>,
+                                              <&iomuxc 21 6 11>;
                         };
 
                         gpio4: gpio@20a8000 {
@@ -408,10 +416,20 @@
                                 reg = <0x020a8000 0x4000>;
                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX6SLL_CLK_GPIO4>;
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
                                 #interrupt-cells = <2>;
+                                gpio-ranges = <&iomuxc 0 17 8>, <&iomuxc 8 107 8>,
+                                              <&iomuxc 16 151 1>, <&iomuxc 17 149 1>,
+                                              <&iomuxc 18 146 1>, <&iomuxc 19 144 1>,
+                                              <&iomuxc 20 142 1>, <&iomuxc 21 143 1>,
+                                              <&iomuxc 22 150 1>, <&iomuxc 23 148 1>,
+                                              <&iomuxc 24 147 1>, <&iomuxc 25 145 1>,
+                                              <&iomuxc 26 152 1>, <&iomuxc 27 125 1>,
+                                              <&iomuxc 28 131 1>, <&iomuxc 29 134 1>,
+                                              <&iomuxc 30 129 1>, <&iomuxc 31 133 1>;
                         };
 
                         gpio5: gpio@20ac000 {
@@ -419,10 +437,22 @@
                                 reg = <0x020ac000 0x4000>;
                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX6SLL_CLK_GPIO5>;
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
                                 #interrupt-cells = <2>;
+                                gpio-ranges = <&iomuxc 0 135 1>, <&iomuxc 1 128 1>,
+                                              <&iomuxc 2 132 1>, <&iomuxc 3 130 1>,
+                                              <&iomuxc 4 127 1>, <&iomuxc 5 126 1>,
+                                              <&iomuxc 6 120 1>, <&iomuxc 7 123 1>,
+                                              <&iomuxc 8 118 1>, <&iomuxc 9 122 1>,
+                                              <&iomuxc 10 124 1>, <&iomuxc 11 117 1>,
+                                              <&iomuxc 12 121 1>, <&iomuxc 13 119 1>,
+                                              <&iomuxc 14 116 1>, <&iomuxc 15 115 1>,
+                                              <&iomuxc 16 140 2>, <&iomuxc 18 136 1>,
+                                              <&iomuxc 19 138 1>, <&iomuxc 20 139 1>,
+                                              <&iomuxc 21 137 1>;
                         };
 
                         gpio6: gpio@20b0000 {
@@ -430,6 +460,7 @@
                                 reg = <0x020b0000 0x4000>;
                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
                                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX6SLL_CLK_GPIO6>;
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/imx6sx-sdb.dtsi
index f8f31872fa14..53b3408b5fab 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dtsi
+++ b/arch/arm/boot/dts/imx6sx-sdb.dtsi
@@ -40,12 +40,14 @@
                         label = "Volume Up";
                         gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
                         linux,code = <KEY_VOLUMEUP>;
+                        wakeup-source;
                 };
 
                 volume-down {
                         label = "Volume Down";
                         gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
                         linux,code = <KEY_VOLUMEDOWN>;
+                        wakeup-source;
                 };
         };
 
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 844caa39364f..95a3c1cb877d 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -268,7 +268,7 @@
                                         status = "disabled";
                                 };
 
-                                ecspi1: ecspi@2008000 {
+                                ecspi1: spi@2008000 {
                                         #address-cells = <1>;
                                         #size-cells = <0>;
                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
@@ -280,7 +280,7 @@
                                         status = "disabled";
                                 };
 
-                                ecspi2: ecspi@200c000 {
+                                ecspi2: spi@200c000 {
                                         #address-cells = <1>;
                                         #size-cells = <0>;
                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
@@ -292,7 +292,7 @@
                                         status = "disabled";
                                 };
 
-                                ecspi3: ecspi@2010000 {
+                                ecspi3: spi@2010000 {
                                         #address-cells = <1>;
                                         #size-cells = <0>;
                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
@@ -304,7 +304,7 @@
                                         status = "disabled";
                                 };
 
-                                ecspi4: ecspi@2014000 {
+                                ecspi4: spi@2014000 {
                                         #address-cells = <1>;
                                         #size-cells = <0>;
                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
@@ -1079,7 +1079,7 @@
                                 status = "disabled";
                         };
 
-                        qspi1: qspi@21e0000 {
+                        qspi1: spi@21e0000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 compatible = "fsl,imx6sx-qspi";
@@ -1092,7 +1092,7 @@
                                 status = "disabled";
                         };
 
-                        qspi2: qspi@21e4000 {
+                        qspi2: spi@21e4000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 compatible = "fsl,imx6sx-qspi";
@@ -1273,7 +1273,7 @@
                                 status = "disabled";
                         };
 
-                        ecspi5: ecspi@228c000 {
+                        ecspi5: spi@228c000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
diff --git a/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts b/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts
new file mode 100644
index 000000000000..11966d12af76
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts
@@ -0,0 +1,390 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Digi International's ConnectCore6UL SBC Pro board device tree source
+ *
+ * Copyright 2018 Digi International, Inc.
+ *
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "imx6ul.dtsi"
+#include "imx6ul-ccimx6ulsom.dtsi"
+
+/ {
+        model = "Digi International ConnectCore 6UL SBC Pro.";
+        compatible = "digi,ccimx6ulsbcpro", "digi,ccimx6ulsom", "fsl,imx6ul";
+
+        lcd_backlight: backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm5 0 50000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+                status = "okay";
+        };
+
+        reg_usb_otg1_vbus: regulator-usb-otg1 {
+                compatible = "regulator-fixed";
+                regulator-name = "usb_otg1_vbus";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+        };
+};
+
+&adc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_adc1>;
+        status = "okay";
+};
+
+&can1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_flexcan1>;
+        xceiver-supply = <&ext_3v3>;
+        status = "okay";
+};
+
+/* CAN2 is multiplexed with UART2 RTS/CTS */
+&can2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_flexcan2>;
+        xceiver-supply = <&ext_3v3>;
+        status = "disabled";
+};
+
+&ecspi1 {
+        cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ecspi1_master>;
+        status = "okay";
+};
+
+&fec1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet1>;
+        phy-mode = "rmii";
+        phy-handle = <&ethphy0>;
+        status = "okay";
+};
+
+&fec2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
+        phy-mode = "rmii";
+        phy-handle = <&ethphy1>;
+        phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
+        phy-reset-duration = <26>;
+        status = "okay";
+
+        mdio {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                ethphy0: ethernet-phy@0 {
+                        compatible = "ethernet-phy-ieee802.3-c22";
+                        smsc,disable-energy-detect;
+                        reg = <0>;
+                };
+
+                ethphy1: ethernet-phy@1 {
+                        compatible = "ethernet-phy-ieee802.3-c22";
+                        smsc,disable-energy-detect;
+                        reg = <1>;
+                };
+        };
+};
+
+&gpio5 {
+        emmc-usd-mux {
+                gpio-hog;
+                gpios = <1 GPIO_ACTIVE_LOW>;
+                output-high;
+        };
+};
+
+&lcdif {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_lcdif_dat0_17
+                     &pinctrl_lcdif_clken
+                     &pinctrl_lcdif_hvsync>;
+        lcd-supply = <&ldo4_ext>;       /* BU90T82 LVDS bridge power */
+        status = "okay";
+};
+
+&ldo4_ext {
+        regulator-max-microvolt = <1800000>;
+};
+
+&pwm1 {
+        status = "okay";
+};
+
+&pwm2 {
+        status = "okay";
+};
+
+&pwm3 {
+        status = "okay";
+};
+
+&pwm4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm4>;
+        status = "okay";
+};
+
+&pwm5 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm5>;
+        status = "okay";
+};
+
+&pwm6 {
+        status = "okay";
+};
+
+&pwm7 {
+        status = "okay";
+};
+
+&pwm8 {
+        status = "okay";
+};
+
+&sai2 {
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&pinctrl_sai2>;
+        pinctrl-1 = <&pinctrl_sai2_sleep>;
+        assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
+                          <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>,
+                          <&clks IMX6UL_CLK_SAI2>;
+        assigned-clock-rates = <0>, <786432000>, <12288000>;
+        assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+        status = "okay";
+};
+
+/* UART2 RTS/CTS muxed with CAN2 */
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2_4wires>;
+        uart-has-rtscts;
+        status = "okay";
+};
+
+/* UART3 RTS/CTS muxed with CAN 1 */
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart3_2wires>;
+        status = "okay";
+};
+
+&uart5 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart5>;
+        status = "okay";
+};
+
+&usbotg1 {
+        dr_mode = "otg";
+        vbus-supply = <&reg_usb_otg1_vbus>;
+        pinctrl-0 = <&pinctrl_usbotg1>;
+        status = "okay";
+};
+
+&usbotg2 {
+        dr_mode = "host";
+        disable-over-current;
+        status = "okay";
+};
+
+/* USDHC2 (microSD conflicts with eMMC) */
+&usdhc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc2>;
+        no-1-8-v;
+        broken-cd;      /* no carrier detect line (use polling) */
+        status = "okay";
+};
+
+&iomuxc {
+        pinctrl_adc1: adc1grp {
+                fsl,pins = <
+                        /* EXP_GPIO_2 -> GPIO1_3/ADC1_IN3 */
+                        MX6UL_PAD_GPIO1_IO03__GPIO1_IO03        0xb0
+                >;
+        };
+
+        pinctrl_ecspi1_master: ecspi1grp1 {
+                fsl,pins = <
+                        MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK       0x10b0
+                        MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI       0x10b0
+                        MX6UL_PAD_LCD_DATA23__ECSPI1_MISO       0x10b0
+                        MX6UL_PAD_LCD_DATA21__GPIO3_IO26        0x10b0
+                >;
+        };
+
+        pinctrl_enet1: enet1grp {
+                fsl,pins = <
+                        MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
+                        MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x1b0b0
+                        MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
+                        MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
+                        MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
+                        MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
+                        MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
+                        MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x40017051
+                >;
+        };
+
+        pinctrl_enet2: enet2grp {
+                fsl,pins = <
+                        MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x1b0b0
+                        MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x1b0b0
+                        MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
+                        MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
+                        MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x1b0b0
+                        MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
+                        MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
+                        MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x40017051
+                >;
+        };
+
+        pinctrl_enet2_mdio: mdioenet2grp {
+                fsl,pins = <
+                        MX6UL_PAD_GPIO1_IO07__ENET2_MDC         0x1b0b0
+                        MX6UL_PAD_GPIO1_IO06__ENET2_MDIO        0x1b0b0
+                >;
+        };
+
+        pinctrl_flexcan1: flexcan1grp{
+                fsl,pins = <
+                        MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX      0x1b020
+                        MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX      0x1b020
+                >;
+        };
+        pinctrl_flexcan2: flexcan2grp{
+                fsl,pins = <
+                        MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX      0x1b020
+                        MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX      0x1b020
+                >;
+        };
+
+        pinctrl_lcdif_dat0_17: lcdifdatgrp0-17 {
+                fsl,pins = <
+                        MX6UL_PAD_LCD_DATA00__LCDIF_DATA00      0x79
+                        MX6UL_PAD_LCD_DATA01__LCDIF_DATA01      0x79
+                        MX6UL_PAD_LCD_DATA02__LCDIF_DATA02      0x79
+                        MX6UL_PAD_LCD_DATA03__LCDIF_DATA03      0x79
+                        MX6UL_PAD_LCD_DATA04__LCDIF_DATA04      0x79
+                        MX6UL_PAD_LCD_DATA05__LCDIF_DATA05      0x79
+                        MX6UL_PAD_LCD_DATA06__LCDIF_DATA06      0x79
+                        MX6UL_PAD_LCD_DATA07__LCDIF_DATA07      0x79
+                        MX6UL_PAD_LCD_DATA08__LCDIF_DATA08      0x79
+                        MX6UL_PAD_LCD_DATA09__LCDIF_DATA09      0x79
+                        MX6UL_PAD_LCD_DATA10__LCDIF_DATA10      0x79
+                        MX6UL_PAD_LCD_DATA11__LCDIF_DATA11      0x79
+                        MX6UL_PAD_LCD_DATA12__LCDIF_DATA12      0x79
+                        MX6UL_PAD_LCD_DATA13__LCDIF_DATA13      0x79
+                        MX6UL_PAD_LCD_DATA14__LCDIF_DATA14      0x79
+                        MX6UL_PAD_LCD_DATA15__LCDIF_DATA15      0x79
+                        MX6UL_PAD_LCD_DATA16__LCDIF_DATA16      0x79
+                        MX6UL_PAD_LCD_DATA17__LCDIF_DATA17      0x79
+                >;
+        };
+
+        pinctrl_lcdif_clken: lcdifctrlgrp1 {
+                fsl,pins = <
+                        MX6UL_PAD_LCD_CLK__LCDIF_CLK            0x17050
+                        MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE      0x79
+                >;
+        };
+
+        pinctrl_lcdif_hvsync: lcdifctrlgrp2 {
+                fsl,pins = <
+                        MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC        0x79
+                        MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC        0x79
+                >;
+        };
+
+        pinctrl_pwm4: pwm4grp {
+                fsl,pins = <
+                        MX6UL_PAD_GPIO1_IO05__PWM4_OUT          0x110b0
+                >;
+        };
+
+        pinctrl_pwm5: pwm5grp {
+                fsl,pins = <
+                        MX6UL_PAD_NAND_DQS__PWM5_OUT            0x110b0
+                >;
+        };
+
+        pinctrl_sai2: sai2grp {
+                fsl,pins = <
+                        MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA     0x11088
+                        MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA        0x11088
+                        MX6UL_PAD_JTAG_TMS__SAI2_MCLK           0x17088
+                        MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK        0x17088
+                        MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC        0x17088
+                        /* Interrupt */
+                        MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07      0x10b0
+                >;
+        };
+
+        pinctrl_sai2_sleep: sai2grp-sleep {
+                fsl,pins = <
+                        MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15       0x3000
+                        MX6UL_PAD_JTAG_TCK__GPIO1_IO14          0x3000
+                        MX6UL_PAD_JTAG_TMS__GPIO1_IO11          0x3000
+                        MX6UL_PAD_JTAG_TDO__GPIO1_IO12          0x3000
+                        /* Interrupt */
+                        MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07      0x3000
+                >;
+        };
+
+        pinctrl_uart2_4wires: uart2grp-4wires {
+                fsl,pins = <
+                        MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x1b0b1
+                        MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x1b0b1
+                        MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS    0x1b0b1
+                        MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS    0x1b0b1
+                >;
+        };
+
+        pinctrl_uart3_2wires: uart3grp-2wires {
+                fsl,pins = <
+                        MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX   0x1b0b1
+                        MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX   0x1b0b1
+                >;
+        };
+
+        pinctrl_uart5: uart5grp {
+                fsl,pins = <
+                        MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX   0x1b0b1
+                        MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX   0x1b0b1
+                >;
+        };
+
+        pinctrl_usdhc2: usdhc2grp {
+                fsl,pins = <
+                        MX6UL_PAD_CSI_HSYNC__USDHC2_CMD         0x17059
+                        MX6UL_PAD_CSI_VSYNC__USDHC2_CLK         0x10039
+                        MX6UL_PAD_CSI_DATA00__USDHC2_DATA0      0x17059
+                        MX6UL_PAD_CSI_DATA01__USDHC2_DATA1      0x17059
+                        MX6UL_PAD_CSI_DATA02__USDHC2_DATA2      0x17059
+                        MX6UL_PAD_CSI_DATA03__USDHC2_DATA3      0x17059
+                        /* Mux selector between eMMC/SD# */
+                        MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01      0x79
+                >;
+        };
+
+        pinctrl_usbotg1: usbotg1grp {
+                fsl,pins = <
+                        MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID    0x17059
+                        MX6UL_PAD_GPIO1_IO04__GPIO1_IO04        0x17059
+                        MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC       0x17059
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/imx6ul-geam.dts b/arch/arm/boot/dts/imx6ul-geam.dts
index d81d20f8fc8d..e22ec5be2b78 100644
--- a/arch/arm/boot/dts/imx6ul-geam.dts
+++ b/arch/arm/boot/dts/imx6ul-geam.dts
@@ -1,43 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
 /*
  * Copyright (C) 2016 Amarula Solutions B.V.
  * Copyright (C) 2016 Engicam S.r.l.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License
- *     version 2 as published by the Free Software Foundation.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
@@ -328,7 +292,7 @@
                 >;
         };
 
-        pinctrl_gpmi_nand: gpmi-nand {
+        pinctrl_gpmi_nand: gpminandgrp {
                 fsl,pins = <
                         MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0xb0b1
                         MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0xb0b1
diff --git a/arch/arm/boot/dts/imx6ul-isiot-emmc.dts b/arch/arm/boot/dts/imx6ul-isiot-emmc.dts
index f5b422898e61..1df3e376ae2c 100644
--- a/arch/arm/boot/dts/imx6ul-isiot-emmc.dts
+++ b/arch/arm/boot/dts/imx6ul-isiot-emmc.dts
@@ -1,43 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
 /*
  * Copyright (C) 2016 Amarula Solutions B.V.
  * Copyright (C) 2016 Engicam S.r.l.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License
- *     version 2 as published by the Free Software Foundation.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
@@ -50,28 +14,5 @@
 };
 
 &usdhc2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usdhc2>;
-        cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
-        bus-width = <8>;
-        no-1-8-v;
         status = "okay";
 };
-
-&iomuxc {
-        pinctrl_usdhc2: usdhc2grp {
-                fsl,pins = <
-                        MX6UL_PAD_NAND_RE_B__USDHC2_CLK      0x17070
-                        MX6UL_PAD_NAND_WE_B__USDHC2_CMD      0x10070
-                        MX6UL_PAD_NAND_DATA00__USDHC2_DATA0  0x17070
-                        MX6UL_PAD_NAND_DATA01__USDHC2_DATA1  0x17070
-                        MX6UL_PAD_NAND_DATA02__USDHC2_DATA2  0x17070
-                        MX6UL_PAD_NAND_DATA03__USDHC2_DATA3  0x17070
-                        MX6UL_PAD_NAND_DATA04__USDHC2_DATA4  0x17070
-                        MX6UL_PAD_NAND_DATA05__USDHC2_DATA5  0x17070
-                        MX6UL_PAD_NAND_DATA06__USDHC2_DATA6  0x17070
-                        MX6UL_PAD_NAND_DATA07__USDHC2_DATA7  0x17070
-                        MX6UL_PAD_NAND_ALE__USDHC2_RESET_B   0x17070
-                >;
-        };
-};
diff --git a/arch/arm/boot/dts/imx6ul-isiot-nand.dts b/arch/arm/boot/dts/imx6ul-isiot-nand.dts
index de15e1c75dd1..8c26d4d1a7bf 100644
--- a/arch/arm/boot/dts/imx6ul-isiot-nand.dts
+++ b/arch/arm/boot/dts/imx6ul-isiot-nand.dts
@@ -1,43 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
 /*
  * Copyright (C) 2016 Amarula Solutions B.V.
  * Copyright (C) 2016 Engicam S.r.l.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License
- *     version 2 as published by the Free Software Foundation.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
@@ -50,30 +14,5 @@
 };
 
 &gpmi {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_gpmi_nand>;
-        nand-on-flash-bbt;
         status = "okay";
 };
-
-&iomuxc {
-        pinctrl_gpmi_nand: gpmi-nand {
-                fsl,pins = <
-                        MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0xb0b1
-                        MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0xb0b1
-                        MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0xb0b1
-                        MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
-                        MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0xb0b1
-                        MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0xb0b1
-                        MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0xb0b1
-                        MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0xb0b1
-                        MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0xb0b1
-                        MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0xb0b1
-                        MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0xb0b1
-                        MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0xb0b1
-                        MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0xb0b1
-                        MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0xb0b1
-                        MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0xb0b1
-                >;
-        };
-};
diff --git a/arch/arm/boot/dts/imx6ul-isiot.dtsi b/arch/arm/boot/dts/imx6ul-isiot.dtsi
index cd9928551154..b1fa3f0a684d 100644
--- a/arch/arm/boot/dts/imx6ul-isiot.dtsi
+++ b/arch/arm/boot/dts/imx6ul-isiot.dtsi
@@ -1,43 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
 /*
  * Copyright (C) 2016 Amarula Solutions B.V.
  * Copyright (C) 2016 Engicam S.r.l.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License
- *     version 2 as published by the Free Software Foundation.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 #include <dt-bindings/gpio/gpio.h>
@@ -133,6 +97,13 @@
         };
 };
 
+&gpmi {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_gpmi_nand>;
+        nand-on-flash-bbt;
+        status = "disabled";
+};
+
 &i2c1 {
         clock-frequency = <100000>;
         pinctrl-names = "default";
@@ -243,6 +214,15 @@
         status = "okay";
 };
 
+&usdhc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc2>;
+        cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
+        bus-width = <8>;
+        no-1-8-v;
+        status = "disabled";
+};
+
 &iomuxc {
         pinctrl_enet1: enet1grp {
                 fsl,pins = <
@@ -259,6 +239,26 @@
                 >;
         };
 
+        pinctrl_gpmi_nand: gpminandgrp {
+                fsl,pins = <
+                        MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0xb0b1
+                        MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0xb0b1
+                        MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0xb0b1
+                        MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
+                        MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0xb0b1
+                        MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0xb0b1
+                        MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0xb0b1
+                        MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0xb0b1
+                        MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0xb0b1
+                        MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0xb0b1
+                        MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0xb0b1
+                        MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0xb0b1
+                        MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0xb0b1
+                        MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0xb0b1
+                        MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0xb0b1
+                >;
+        };
+
         pinctrl_i2c1: i2c1grp {
                 fsl,pins = <
                         MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
@@ -366,4 +366,20 @@
                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
                 >;
         };
+
+        pinctrl_usdhc2: usdhc2grp {
+                fsl,pins = <
+                        MX6UL_PAD_NAND_RE_B__USDHC2_CLK      0x17070
+                        MX6UL_PAD_NAND_WE_B__USDHC2_CMD      0x10070
+                        MX6UL_PAD_NAND_DATA00__USDHC2_DATA0  0x17070
+                        MX6UL_PAD_NAND_DATA01__USDHC2_DATA1  0x17070
+                        MX6UL_PAD_NAND_DATA02__USDHC2_DATA2  0x17070
+                        MX6UL_PAD_NAND_DATA03__USDHC2_DATA3  0x17070
+                        MX6UL_PAD_NAND_DATA04__USDHC2_DATA4  0x17070
+                        MX6UL_PAD_NAND_DATA05__USDHC2_DATA5  0x17070
+                        MX6UL_PAD_NAND_DATA06__USDHC2_DATA6  0x17070
+                        MX6UL_PAD_NAND_DATA07__USDHC2_DATA7  0x17070
+                        MX6UL_PAD_NAND_ALE__USDHC2_RESET_B   0x17070
+                >;
+        };
 };
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index 6dc0b569acdf..083d3446c41d 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -89,6 +89,8 @@
                                       "pll1_sys";
                         arm-supply = <&reg_arm>;
                         soc-supply = <&reg_soc>;
+                        nvmem-cells = <&cpu_speed_grade>;
+                        nvmem-cell-names = "speed_grade";
                 };
         };
 
@@ -156,7 +158,6 @@
                 compatible = "arm,cortex-a7-pmu";
                 interrupt-parent = <&gpc>;
                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
-                status = "disabled";
         };
 
         soc {
@@ -218,7 +219,7 @@
                                 reg = <0x02000000 0x40000>;
                                 ranges;
 
-                                ecspi1: ecspi@2008000 {
+                                ecspi1: spi@2008000 {
                                         #address-cells = <1>;
                                         #size-cells = <0>;
                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
@@ -230,7 +231,7 @@
                                         status = "disabled";
                                 };
 
-                                ecspi2: ecspi@200c000 {
+                                ecspi2: spi@200c000 {
                                         #address-cells = <1>;
                                         #size-cells = <0>;
                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
@@ -242,7 +243,7 @@
                                         status = "disabled";
                                 };
 
-                                ecspi3: ecspi@2010000 {
+                                ecspi3: spi@2010000 {
                                         #address-cells = <1>;
                                         #size-cells = <0>;
                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
@@ -254,7 +255,7 @@
                                         status = "disabled";
                                 };
 
-                                ecspi4: ecspi@2014000 {
+                                ecspi4: spi@2014000 {
                                         #address-cells = <1>;
                                         #size-cells = <0>;
                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
@@ -918,6 +919,17 @@
                                 reg = <0x021b0000 0x4000>;
                         };
 
+                        weim: weim@21b8000 {
+                                #address-cells = <2>;
+                                #size-cells = <1>;
+                                compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim";
+                                reg = <0x021b8000 0x4000>;
+                                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX6UL_CLK_EIM>;
+                                fsl,weim-cs-gpr = <&gpr>;
+                                status = "disabled";
+                        };
+
                         ocotp: ocotp-ctrl@21bc000 {
                                 #address-cells = <1>;
                                 #size-cells = <1>;
@@ -932,6 +944,10 @@
                                 tempmon_temp_grade: temp-grade@20 {
                                         reg = <0x20 4>;
                                 };
+
+                                cpu_speed_grade: speed-grade@10 {
+                                        reg = <0x10 4>;
+                                };
                         };
 
                         lcdif: lcdif@21c8000 {
@@ -945,7 +961,7 @@
                                 status = "disabled";
                         };
 
-                        qspi: qspi@21e0000 {
+                        qspi: spi@21e0000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
diff --git a/arch/arm/boot/dts/imx6ull-14x14-evk.dts b/arch/arm/boot/dts/imx6ull-14x14-evk.dts
index 30ef60344af3..0ba64546c13b 100644
--- a/arch/arm/boot/dts/imx6ull-14x14-evk.dts
+++ b/arch/arm/boot/dts/imx6ull-14x14-evk.dts
@@ -45,7 +45,7 @@
 #include "imx6ul-14x14-evk.dtsi"
 
 / {
-        model = "Freescale i.MX6 UlltraLite 14x14 EVK Board";
+        model = "Freescale i.MX6 UltraLiteLite 14x14 EVK Board";
         compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";
 };
 
diff --git a/arch/arm/boot/dts/imx6ull-pinfunc.h b/arch/arm/boot/dts/imx6ull-pinfunc.h
index fdc46bb09cc1..a282a31a4bae 100644
--- a/arch/arm/boot/dts/imx6ull-pinfunc.h
+++ b/arch/arm/boot/dts/imx6ull-pinfunc.h
@@ -14,14 +14,38 @@
  * The pin function ID is a tuple of
  * <mux_reg conf_reg input_reg mux_mode input_val>
  */
+/* signals common for i.MX6UL and i.MX6ULL */
+#undef MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX
+#define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX                    0x00BC 0x0348 0x0644 0x0 0x6
+#undef MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX
+#define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX                    0x00C0 0x034C 0x0644 0x0 0x7
+#undef MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS
+#define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS                     0x00CC 0x0358 0x0640 0x1 0x5
+#undef MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS
+#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS                  0x00D0 0x035C 0x0640 0x1 0x6
+#undef MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS
+#define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS                      0x01EC 0x0478 0x0640 0x8 0x7
+
+/* signals for i.MX6ULL only */
+#define MX6ULL_PAD_UART1_TX_DATA__UART5_DCE_TX                    0x0084 0x0310 0x0000 0x9 0x0
 #define MX6ULL_PAD_UART1_TX_DATA__UART5_DTE_RX                    0x0084 0x0310 0x0644 0x9 0x4
 #define MX6ULL_PAD_UART1_RX_DATA__UART5_DCE_RX                    0x0088 0x0314 0x0644 0x9 0x5
-#define MX6ULL_PAD_UART1_CTS_B__UART5_DCE_RTS                     0x008C 0x0318 0x0640 0x9 0x3
-#define MX6ULL_PAD_UART1_RTS_B__UART5_DTE_RTS                     0x0090 0x031C 0x0640 0x9 0x4
-#define MX6ULL_PAD_UART5_TX_DATA__UART5_DTE_RX                    0x00BC 0x0348 0x0644 0x0 0x6
-#define MX6ULL_PAD_UART5_RX_DATA__UART5_DCE_RX                    0x00C0 0x034C 0x0644 0x0 0x7
-#define MX6ULL_PAD_ENET1_RX_EN__UART5_DCE_RTS                     0x00CC 0x0358 0x0640 0x1 0x5
-#define MX6ULL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS                  0x00D0 0x035C 0x0640 0x1 0x6
+#define MX6ULL_PAD_UART1_RX_DATA__UART5_DTE_TX                    0x0088 0x0314 0x0000 0x9 0x0
+#define MX6ULL_PAD_UART1_CTS_B__UART5_DCE_CTS                     0x008C 0x0318 0x0000 0x9 0x0
+#define MX6ULL_PAD_UART1_CTS_B__UART5_DTE_RTS                     0x008C 0x0318 0x0640 0x9 0x3
+#define MX6ULL_PAD_UART1_RTS_B__UART5_DCE_RTS                     0x0090 0x031C 0x0640 0x9 0x4
+#define MX6ULL_PAD_UART1_RTS_B__UART5_DTE_CTS                     0x0090 0x031C 0x0000 0x9 0x0
+#define MX6ULL_PAD_UART4_RX_DATA__EPDC_PWRCTRL01                  0x00B8 0x0344 0x0000 0x9 0x0
+#define MX6ULL_PAD_UART5_TX_DATA__EPDC_PWRCTRL02                  0x00BC 0x0348 0x0000 0x9 0x0
+#define MX6ULL_PAD_UART5_RX_DATA__EPDC_PWRCTRL03                  0x00C0 0x034C 0x0000 0x9 0x0
+#define MX6ULL_PAD_ENET1_RX_DATA0__EPDC_SDCE04                    0x00C4 0x0350 0x0000 0x9 0x0
+#define MX6ULL_PAD_ENET1_RX_DATA1__EPDC_SDCE05                    0x00C8 0x0354 0x0000 0x9 0x0
+#define MX6ULL_PAD_ENET1_RX_EN__EPDC_SDCE06                       0x00CC 0x0358 0x0000 0x9 0x0
+#define MX6ULL_PAD_ENET1_TX_DATA0__EPDC_SDCE07                    0x00D0 0x035C 0x0000 0x9 0x0
+#define MX6ULL_PAD_ENET1_TX_DATA1__EPDC_SDCE08                    0x00D4 0x0360 0x0000 0x9 0x0
+#define MX6ULL_PAD_ENET1_TX_EN__EPDC_SDCE09                       0x00D8 0x0364 0x0000 0x9 0x0
+#define MX6ULL_PAD_ENET1_TX_CLK__EPDC_SDOED                       0x00DC 0x0368 0x0000 0x9 0x0
+#define MX6ULL_PAD_ENET1_RX_ER__EPDC_SDOEZ                        0x00E0 0x036C 0x0000 0x9 0x0
 #define MX6ULL_PAD_ENET2_RX_DATA0__EPDC_SDDO08                    0x00E4 0x0370 0x0000 0x9 0x0
 #define MX6ULL_PAD_ENET2_RX_DATA1__EPDC_SDDO09                    0x00E8 0x0374 0x0000 0x9 0x0
 #define MX6ULL_PAD_ENET2_RX_EN__EPDC_SDDO10                       0x00EC 0x0378 0x0000 0x9 0x0
@@ -48,6 +72,8 @@
 #define MX6ULL_PAD_LCD_DATA16__EPDC_GDCLK                         0x0158 0x03E4 0x0000 0x9 0x0
 #define MX6ULL_PAD_LCD_DATA17__EPDC_GDSP                          0x015C 0x03E8 0x0000 0x9 0x0
 #define MX6ULL_PAD_LCD_DATA21__EPDC_SDCE1                         0x016C 0x03F8 0x0000 0x9 0x0
+#define MX6ULL_PAD_LCD_DATA22__EPDC_SDCE02                        0x0170 0x03FC 0x0000 0x9 0x0
+#define MX6ULL_PAD_LCD_DATA23__EPDC_SDCE03                        0x0174 0x0400 0x0000 0x9 0x0
 #define MX6ULL_PAD_CSI_MCLK__ESAI_TX3_RX2                         0x01D4 0x0460 0x0000 0x9 0x0
 #define MX6ULL_PAD_CSI_PIXCLK__ESAI_TX2_RX3                       0x01D8 0x0464 0x0000 0x9 0x0
 #define MX6ULL_PAD_CSI_VSYNC__ESAI_TX4_RX1                        0x01DC 0x0468 0x0000 0x9 0x0
@@ -55,7 +81,6 @@
 #define MX6ULL_PAD_CSI_DATA00__ESAI_TX_HF_CLK                     0x01E4 0x0470 0x0000 0x9 0x0
 #define MX6ULL_PAD_CSI_DATA01__ESAI_RX_HF_CLK                     0x01E8 0x0474 0x0000 0x9 0x0
 #define MX6ULL_PAD_CSI_DATA02__ESAI_RX_FS                         0x01EC 0x0478 0x0000 0x9 0x0
-#define MX6ULL_PAD_CSI_DATA02__UART5_DCE_RTS                      0x01EC 0x0478 0x0640 0x8 0x7
 #define MX6ULL_PAD_CSI_DATA03__ESAI_RX_CLK                        0x01F0 0x047C 0x0000 0x9 0x0
 #define MX6ULL_PAD_CSI_DATA04__ESAI_TX_FS                         0x01F4 0x0480 0x0000 0x9 0x0
 #define MX6ULL_PAD_CSI_DATA05__ESAI_TX_CLK                        0x01F8 0x0484 0x0000 0x9 0x0
diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi
index cd1776a7015a..796ed35d4ac9 100644
--- a/arch/arm/boot/dts/imx6ull.dtsi
+++ b/arch/arm/boot/dts/imx6ull.dtsi
@@ -22,7 +22,7 @@
         >;
         fsl,soc-operating-points = <
                 /* KHz  uV */
-                900000  1175000
+                900000  1250000
                 792000  1175000
                 528000  1175000
                 396000  1175000
diff --git a/arch/arm/boot/dts/imx6ulz-14x14-evk.dts b/arch/arm/boot/dts/imx6ulz-14x14-evk.dts
new file mode 100644
index 000000000000..6f1af240e0ce
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ulz-14x14-evk.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Copyright 2018 NXP.
+
+/dts-v1/;
+
+#include "imx6ulz.dtsi"
+#include "imx6ul-14x14-evk.dtsi"
+
+/delete-node/ &fec1;
+/delete-node/ &fec2;
+/delete-node/ &lcdif;
+/delete-node/ &tsc;
+
+/ {
+        model = "Freescale i.MX6 ULZ 14x14 EVK Board";
+        compatible = "fsl,imx6ulz-14x14-evk", "fsl,imx6ull", "fsl,imx6ulz";
+
+        /delete-node/ panel;
+};
diff --git a/arch/arm/boot/dts/imx6ulz.dtsi b/arch/arm/boot/dts/imx6ulz.dtsi
new file mode 100644
index 000000000000..ae6d7e593769
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ulz.dtsi
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Copyright 2018 NXP.
+
+#include "imx6ull.dtsi"
+
+/ {
+        aliases {
+                /delete-property/ ethernet0;
+                /delete-property/ ethernet1;
+                /delete-property/ i2c2;
+                /delete-property/ i2c3;
+                /delete-property/ serial4;
+                /delete-property/ serial5;
+                /delete-property/ serial6;
+                /delete-property/ serial7;
+                /delete-property/ spi2;
+                /delete-property/ spi3;
+        };
+};
+
+/delete-node/ &adc1;
+/delete-node/ &can1;
+/delete-node/ &can2;
+/delete-node/ &ecspi3;
+/delete-node/ &ecspi4;
+/delete-node/ &epit2;
+/delete-node/ &gpt2;
+/delete-node/ &i2c3;
+/delete-node/ &i2c4;
+/delete-node/ &pwm5;
+/delete-node/ &pwm6;
+/delete-node/ &pwm7;
+/delete-node/ &pwm8;
+/delete-node/ &uart5;
+/delete-node/ &uart6;
+/delete-node/ &uart7;
+/delete-node/ &uart8;
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index c9b3c60b0eb2..f1bafdaa7e1a 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -27,12 +27,14 @@
                         label = "Volume Up";
                         gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
                         linux,code = <KEY_VOLUMEUP>;
+                        wakeup-source;
                 };
 
                 volume-down {
                         label = "Volume Down";
                         gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
                         linux,code = <KEY_VOLUMEDOWN>;
+                        wakeup-source;
                 };
         };
 
diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi
index efbdeaaa8dcd..826224bf7f4f 100644
--- a/arch/arm/boot/dts/imx7d.dtsi
+++ b/arch/arm/boot/dts/imx7d.dtsi
@@ -20,6 +20,7 @@
                         reg = <1>;
                         clock-frequency = <996000000>;
                         operating-points-v2 = <&cpu0_opp_table>;
+                        cpu-idle-states = <&cpu_sleep_wait>;
                 };
         };
 
@@ -63,9 +64,11 @@
                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
                         clock-names = "apb_pclk";
 
-                        port {
-                                etm1_out_port: endpoint {
-                                        remote-endpoint = <&ca_funnel_in_port1>;
+                        out-ports {
+                                port {
+                                        etm1_out_port: endpoint {
+                                                remote-endpoint = <&ca_funnel_in_port1>;
+                                        };
                                 };
                         };
                 };
@@ -153,11 +156,13 @@
         };
 };
 
-&ca_funnel_ports {
+&ca_funnel_in_ports {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
         port@1 {
                 reg = <1>;
                 ca_funnel_in_port1: endpoint {
-                        slave-mode;
                         remote-endpoint = <&etm1_out_port>;
                 };
         };
diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts
index fa390da636de..f7ba2c0a24ad 100644
--- a/arch/arm/boot/dts/imx7s-warp.dts
+++ b/arch/arm/boot/dts/imx7s-warp.dts
@@ -1,44 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (C) 2016 NXP Semiconductors.
  * Author: Fabio Estevam <fabio.estevam@nxp.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
@@ -216,6 +179,13 @@
         status = "okay";
 };
 
+&i2c3 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c3>;
+        status = "okay";
+};
+
 &i2c4 {
         clock-frequency = <100000>;
         pinctrl-names = "default";
@@ -346,6 +316,13 @@
                 >;
         };
 
+        pinctrl_i2c3: i2c3grp {
+                fsl,pins = <
+                        MX7D_PAD_I2C3_SDA__I2C3_SDA     0x4000007f
+                        MX7D_PAD_I2C3_SCL__I2C3_SCL     0x4000007f
+                >;
+        };
+
         pinctrl_i2c4: i2c4grp {
                 fsl,pins = <
                         MX7D_PAD_I2C4_SCL__I2C4_SCL     0x4000007f
diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
index a052198f6e96..aa8df7d93b2e 100644
--- a/arch/arm/boot/dts/imx7s.dtsi
+++ b/arch/arm/boot/dts/imx7s.dtsi
@@ -54,6 +54,19 @@
                 #address-cells = <1>;
                 #size-cells = <0>;
 
+                idle-states {
+                        entry-method = "psci";
+
+                        cpu_sleep_wait: cpu-sleep-wait {
+                                compatible = "arm,idle-state";
+                                arm,psci-suspend-param = <0x0010000>;
+                                local-timer-stop;
+                                entry-latency-us = <100>;
+                                exit-latency-us = <50>;
+                                min-residency-us = <1000>;
+                        };
+                };
+
                 cpu0: cpu@0 {
                         compatible = "arm,cortex-a7";
                         device_type = "cpu";
@@ -61,6 +74,7 @@
                         clock-frequency = <792000000>;
                         clock-latency = <61036>; /* two CLK32 periods */
                         clocks = <&clks IMX7D_CLK_ARM>;
+                        cpu-idle-states = <&cpu_sleep_wait>;
                 };
         };
 
@@ -106,7 +120,7 @@
                  */
                 compatible = "arm,coresight-replicator";
 
-                ports {
+                out-ports {
                         #address-cells = <1>;
                         #size-cells = <0>;
                                 /* replicator output ports */
@@ -123,12 +137,11 @@
                                         remote-endpoint = <&etr_in_port>;
                                 };
                         };
+                };
 
-                        /* replicator input port */
-                        port@2 {
-                                reg = <0>;
+                in-ports {
+                        port {
                                 replicator_in_port0: endpoint {
-                                        slave-mode;
                                         remote-endpoint = <&etf_out_port>;
                                 };
                         };
@@ -168,28 +181,23 @@
                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
                         clock-names = "apb_pclk";
 
-                        ca_funnel_ports: ports {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-
-                                /* funnel input ports */
-                                port@0 {
-                                        reg = <0>;
+                        ca_funnel_in_ports: in-ports {
+                                port {
                                         ca_funnel_in_port0: endpoint {
-                                                slave-mode;
                                                 remote-endpoint = <&etm0_out_port>;
                                         };
                                 };
 
-                                /* funnel output port */
-                                port@2 {
-                                        reg = <0>;
+                                /* the other input ports are not connect to anything */
+                        };
+
+                        out-ports {
+                                port {
                                         ca_funnel_out_port0: endpoint {
                                                 remote-endpoint = <&hugo_funnel_in_port0>;
                                         };
                                 };
 
-                                /* the other input ports are not connect to anything */
                         };
                 };
 
@@ -200,9 +208,11 @@
                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
                         clock-names = "apb_pclk";
 
-                        port {
-                                etm0_out_port: endpoint {
-                                        remote-endpoint = <&ca_funnel_in_port0>;
+                        out-ports {
+                                port {
+                                        etm0_out_port: endpoint {
+                                                remote-endpoint = <&ca_funnel_in_port0>;
+                                        };
                                 };
                         };
                 };
@@ -213,15 +223,13 @@
                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
                         clock-names = "apb_pclk";
 
-                        ports {
+                        in-ports {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
 
-                                /* funnel input ports */
                                 port@0 {
                                         reg = <0>;
                                         hugo_funnel_in_port0: endpoint {
-                                                slave-mode;
                                                 remote-endpoint = <&ca_funnel_out_port0>;
                                         };
                                 };
@@ -229,18 +237,18 @@
                                 port@1 {
                                         reg = <1>;
                                         hugo_funnel_in_port1: endpoint {
-                                                slave-mode; /* M4 input */
+                                                /* M4 input */
                                         };
                                 };
+                                /* the other input ports are not connect to anything */
+                        };
 
-                                port@2 {
-                                        reg = <0>;
+                        out-ports {
+                                port {
                                         hugo_funnel_out_port0: endpoint {
                                                 remote-endpoint = <&etf_in_port>;
                                         };
                                 };
-
-                                /* the other input ports are not connect to anything */
                         };
                 };
 
@@ -250,20 +258,16 @@
                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
                         clock-names = "apb_pclk";
 
-                        ports {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-
-                                port@0 {
-                                        reg = <0>;
+                        in-ports {
+                                port {
                                         etf_in_port: endpoint {
-                                                slave-mode;
                                                 remote-endpoint = <&hugo_funnel_out_port0>;
                                         };
                                 };
+                        };
 
-                                port@1 {
-                                        reg = <0>;
+                        out-ports {
+                                port {
                                         etf_out_port: endpoint {
                                                 remote-endpoint = <&replicator_in_port0>;
                                         };
@@ -277,10 +281,11 @@
                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
                         clock-names = "apb_pclk";
 
-                        port {
-                                etr_in_port: endpoint {
-                                        slave-mode;
-                                        remote-endpoint = <&replicator_out_port1>;
+                        in-ports {
+                                port {
+                                        etr_in_port: endpoint {
+                                                remote-endpoint = <&replicator_out_port1>;
+                                        };
                                 };
                         };
                 };
@@ -291,10 +296,11 @@
                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
                         clock-names = "apb_pclk";
 
-                        port {
-                                tpiu_in_port: endpoint {
-                                        slave-mode;
-                                        remote-endpoint = <&replicator_out_port0>;
+                        in-ports {
+                                port {
+                                        tpiu_in_port: endpoint {
+                                                remote-endpoint = <&replicator_out_port0>;
+                                        };
                                 };
                         };
                 };
@@ -563,14 +569,6 @@
                                         clock-names = "snvs-rtc";
                                 };
 
-                                snvs_poweroff: snvs-poweroff {
-                                        compatible = "syscon-poweroff";
-                                        regmap = <&snvs>;
-                                        offset = <0x38>;
-                                        value = <0x60>;
-                                        mask = <0x60>;
-                                };
-
                                 snvs_pwrkey: snvs-powerkey {
                                         compatible = "fsl,sec-v4.0-pwrkey";
                                         regmap = <&snvs>;
@@ -644,7 +642,7 @@
                                 status = "disabled";
                         };
 
-                        ecspi4: ecspi@30630000 {
+                        ecspi4: spi@30630000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
@@ -725,7 +723,7 @@
                                 reg = <0x30800000 0x100000>;
                                 ranges;
 
-                                ecspi1: ecspi@30820000 {
+                                ecspi1: spi@30820000 {
                                         #address-cells = <1>;
                                         #size-cells = <0>;
                                         compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
@@ -737,7 +735,7 @@
                                         status = "disabled";
                                 };
 
-                                ecspi2: ecspi@30830000 {
+                                ecspi2: spi@30830000 {
                                         #address-cells = <1>;
                                         #size-cells = <0>;
                                         compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
@@ -749,7 +747,7 @@
                                         status = "disabled";
                                 };
 
-                                ecspi3: ecspi@30840000 {
+                                ecspi3: spi@30840000 {
                                         #address-cells = <1>;
                                         #size-cells = <0>;
                                         compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
@@ -974,6 +972,25 @@
                                 status = "disabled";
                         };
 
+                        mu0a: mailbox@30aa0000 {
+                                compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
+                                reg = <0x30aa0000 0x10000>;
+                                interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_MU_ROOT_CLK>;
+                                #mbox-cells = <2>;
+                                status = "disabled";
+                        };
+
+                        mu0b: mailbox@30ab0000 {
+                                compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
+                                reg = <0x30ab0000 0x10000>;
+                                interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_MU_ROOT_CLK>;
+                                #mbox-cells = <2>;
+                                fsl,mu-side-b;
+                                status = "disabled";
+                        };
+
                         usbotg1: usb@30b10000 {
                                 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
                                 reg = <0x30b10000 0x200>;
diff --git a/arch/arm/boot/dts/imx7ulp-pinfunc.h b/arch/arm/boot/dts/imx7ulp-pinfunc.h
index fe511775b518..85f6b017803a 100644
--- a/arch/arm/boot/dts/imx7ulp-pinfunc.h
+++ b/arch/arm/boot/dts/imx7ulp-pinfunc.h
@@ -116,6 +116,7 @@
 #define IMX7ULP_PAD_PTC13__LPI2C7_SDA                                0x0034 0x030c 0x5 0x1
 #define IMX7ULP_PAD_PTC13__TPM7_CLKIN                                0x0034 0x02f4 0x6 0x1
 #define IMX7ULP_PAD_PTC13__FB_AD13                                   0x0034 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC13__USB0_ID                                   0x0034 0x0338 0xb 0x1
 #define IMX7ULP_PAD_PTC14__PTC14                                     0x0038 0x0000 0x1 0x0
 #define IMX7ULP_PAD_PTC14__TRACE_D1                                  0x0038 0x0000 0xa 0x0
 #define IMX7ULP_PAD_PTC14__FXIO1_D10                                 0x0038 0x022c 0x2 0x1
@@ -136,6 +137,7 @@
 #define IMX7ULP_PAD_PTC16__LPSPI3_SIN                                0x0040 0x0324 0x3 0x1
 #define IMX7ULP_PAD_PTC16__TPM7_CH2                                  0x0040 0x02e4 0x6 0x1
 #define IMX7ULP_PAD_PTC16__FB_ALE_FB_CS1_B_FB_TS_B                   0x0040 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC16__USB1_OC2                                  0x0040 0x0334 0xb 0x1
 #define IMX7ULP_PAD_PTC17__PTC17                                     0x0044 0x0000 0x1 0x0
 #define IMX7ULP_PAD_PTC17__FXIO1_D13                                 0x0044 0x0238 0x2 0x1
 #define IMX7ULP_PAD_PTC17__LPSPI3_SOUT                               0x0044 0x0328 0x3 0x1
@@ -146,11 +148,16 @@
 #define IMX7ULP_PAD_PTC18__LPSPI3_SCK                                0x0048 0x0320 0x3 0x1
 #define IMX7ULP_PAD_PTC18__TPM6_CH0                                  0x0048 0x02d0 0x6 0x1
 #define IMX7ULP_PAD_PTC18__FB_OE_B                                   0x0048 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC18__USB0_ID                                   0x0048 0x0338 0xb 0x2
+#define IMX7ULP_PAD_PTC18__VIU_DE                                    0x0048 0x033c 0xc 0x1
 #define IMX7ULP_PAD_PTC19__PTC19                                     0x004c 0x0000 0x1 0x0
 #define IMX7ULP_PAD_PTC19__FXIO1_D15                                 0x004c 0x0240 0x2 0x1
 #define IMX7ULP_PAD_PTC19__LPSPI3_PCS0                               0x004c 0x0310 0x3 0x1
 #define IMX7ULP_PAD_PTC19__TPM6_CH1                                  0x004c 0x02d4 0x6 0x1
 #define IMX7ULP_PAD_PTC19__FB_A16                                    0x004c 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTC19__USB0_ID                                   0x004c 0x0338 0xa 0x3
+#define IMX7ULP_PAD_PTC19__USB1_PWR2                                 0x004c 0x0000 0xb 0x0
+#define IMX7ULP_PAD_PTC19__VIU_DE                                    0x004c 0x033c 0xc 0x3
 #define IMX7ULP_PAD_PTD0__PTD0                                       0x0080 0x0000 0x1 0x0
 #define IMX7ULP_PAD_PTD0__SDHC0_RESET_B                              0x0080 0x0000 0x8 0x0
 #define IMX7ULP_PAD_PTD1__PTD1                                       0x0084 0x0000 0x1 0x0
@@ -218,6 +225,7 @@
 #define IMX7ULP_PAD_PTE5__LPI2C5_SDA                                 0x0114 0x02c0 0x5 0x2
 #define IMX7ULP_PAD_PTE5__TPM5_CH0                                   0x0114 0x02c4 0x6 0x2
 #define IMX7ULP_PAD_PTE5__SDHC1_D2                                   0x0114 0x0000 0x8 0x0
+#define IMX7ULP_PAD_PTE5__VIU_DE                                     0x0114 0x033c 0xc 0x2
 #define IMX7ULP_PAD_PTE6__PTE6                                       0x0118 0x0000 0x1 0x0
 #define IMX7ULP_PAD_PTE6__FXIO1_D25                                  0x0118 0x0000 0x2 0x0
 #define IMX7ULP_PAD_PTE6__LPSPI2_SCK                                 0x0118 0x02ac 0x3 0x2
@@ -226,8 +234,10 @@
 #define IMX7ULP_PAD_PTE6__TPM7_CH3                                   0x0118 0x02e8 0x6 0x2
 #define IMX7ULP_PAD_PTE6__SDHC1_D4                                   0x0118 0x0000 0x8 0x0
 #define IMX7ULP_PAD_PTE6__FB_A17                                     0x0118 0x0000 0x9 0x0
+#define IMX7ULP_PAD_PTE6__USB0_OC                                    0x0118 0x0330 0xb 0x1
 #define IMX7ULP_PAD_PTE7__PTE7                                       0x011c 0x0000 0x1 0x0
 #define IMX7ULP_PAD_PTE7__TRACE_D7                                   0x011c 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTE7__USB0_PWR                                   0x011c 0x0000 0xb 0x0
 #define IMX7ULP_PAD_PTE7__VIU_FID                                    0x011c 0x0000 0xc 0x0
 #define IMX7ULP_PAD_PTE7__FXIO1_D24                                  0x011c 0x0000 0x2 0x0
 #define IMX7ULP_PAD_PTE7__LPSPI2_PCS0                                0x011c 0x029c 0x3 0x2
@@ -278,6 +288,7 @@
 #define IMX7ULP_PAD_PTE11__FB_A20                                    0x012c 0x0000 0x9 0x0
 #define IMX7ULP_PAD_PTE12__PTE12                                     0x0130 0x0000 0x1 0x0
 #define IMX7ULP_PAD_PTE12__TRACE_D2                                  0x0130 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTE12__USB1_OC2                                  0x0130 0x0334 0xb 0x2
 #define IMX7ULP_PAD_PTE12__VIU_D20                                   0x0130 0x0000 0xc 0x0
 #define IMX7ULP_PAD_PTE12__FXIO1_D19                                 0x0130 0x0000 0x2 0x0
 #define IMX7ULP_PAD_PTE12__LPSPI3_SIN                                0x0130 0x0324 0x3 0x2
@@ -288,6 +299,7 @@
 #define IMX7ULP_PAD_PTE12__FB_A21                                    0x0130 0x0000 0x9 0x0
 #define IMX7ULP_PAD_PTE13__PTE13                                     0x0134 0x0000 0x1 0x0
 #define IMX7ULP_PAD_PTE13__TRACE_D1                                  0x0134 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTE13__USB1_PWR2                                 0x0134 0x0000 0xb 0x0
 #define IMX7ULP_PAD_PTE13__VIU_D21                                   0x0134 0x0000 0xc 0x0
 #define IMX7ULP_PAD_PTE13__FXIO1_D18                                 0x0134 0x0000 0x2 0x0
 #define IMX7ULP_PAD_PTE13__LPSPI3_SOUT                               0x0134 0x0328 0x3 0x2
@@ -298,6 +310,7 @@
 #define IMX7ULP_PAD_PTE13__FB_A22                                    0x0134 0x0000 0x9 0x0
 #define IMX7ULP_PAD_PTE14__PTE14                                     0x0138 0x0000 0x1 0x0
 #define IMX7ULP_PAD_PTE14__TRACE_D0                                  0x0138 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTE14__USB0_OC                                   0x0138 0x0330 0xb 0x2
 #define IMX7ULP_PAD_PTE14__VIU_D22                                   0x0138 0x0000 0xc 0x0
 #define IMX7ULP_PAD_PTE14__FXIO1_D17                                 0x0138 0x0000 0x2 0x0
 #define IMX7ULP_PAD_PTE14__LPSPI3_SCK                                0x0138 0x0320 0x3 0x2
@@ -308,6 +321,7 @@
 #define IMX7ULP_PAD_PTE14__FB_A23                                    0x0138 0x0000 0x9 0x0
 #define IMX7ULP_PAD_PTE15__PTE15                                     0x013c 0x0000 0x1 0x0
 #define IMX7ULP_PAD_PTE15__TRACE_CLKOUT                              0x013c 0x0000 0xa 0x0
+#define IMX7ULP_PAD_PTE15__USB0_PWR                                  0x013c 0x0000 0xb 0x0
 #define IMX7ULP_PAD_PTE15__VIU_D23                                   0x013c 0x0000 0xc 0x0
 #define IMX7ULP_PAD_PTE15__FXIO1_D16                                 0x013c 0x0000 0x2 0x0
 #define IMX7ULP_PAD_PTE15__LPSPI3_PCS0                               0x013c 0x0310 0x3 0x2
@@ -315,7 +329,7 @@
 #define IMX7ULP_PAD_PTE15__TPM6_CH1                                  0x013c 0x02d4 0x6 0x2
 #define IMX7ULP_PAD_PTE15__FB_A24                                    0x013c 0x0000 0x9 0x0
 #define IMX7ULP_PAD_PTF0__PTF0                                       0x0180 0x0000 0x1 0x0
-#define IMX7ULP_PAD_PTF0__VIU_DE                                     0x0180 0x0000 0xc 0x0
+#define IMX7ULP_PAD_PTF0__VIU_DE                                     0x0180 0x033c 0xc 0x0
 #define IMX7ULP_PAD_PTF0__LPUART4_CTS_B                              0x0180 0x0244 0x4 0x3
 #define IMX7ULP_PAD_PTF0__LPI2C4_SCL                                 0x0180 0x0278 0x5 0x3
 #define IMX7ULP_PAD_PTF0__TPM4_CLKIN                                 0x0180 0x0298 0x6 0x3
diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
index 5cae74eb6cdd..ca9154dd8052 100644
--- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi
+++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
@@ -160,10 +160,6 @@
         clock-frequency = <100000000>;
 };
 
-&pciec {
-        status = "okay";
-};
-
 &pfc {
         can0_pins: can0 {
                 groups = "can0_data_d";
diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi
index 738b44cf2b0b..1c833105d6c5 100644
--- a/arch/arm/boot/dts/keystone-k2g.dtsi
+++ b/arch/arm/boot/dts/keystone-k2g.dtsi
@@ -416,7 +416,7 @@
                         clock-names = "fck", "mmchsdb_fck";
                 };
 
-                qspi: qspi@2940000 {
+                qspi: spi@2940000 {
                         compatible = "ti,k2g-qspi", "cdns,qspi-nor";
                         #address-cells = <1>;
                         #size-cells = <0>;
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index abff7ef7c9cd..b7303a4e4236 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -179,7 +179,7 @@
                          * ssp0 and spi1 are shared pins;
                          * enable one in your board dts, as needed.
                          */
-                        ssp0: ssp@20084000 {
+                        ssp0: spi@20084000 {
                                 compatible = "arm,pl022", "arm,primecell";
                                 reg = <0x20084000 0x1000>;
                                 interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
@@ -199,7 +199,7 @@
                          * ssp1 and spi2 are shared pins;
                          * enable one in your board dts, as needed.
                          */
-                        ssp1: ssp@2008c000 {
+                        ssp1: spi@2008c000 {
                                 compatible = "arm,pl022", "arm,primecell";
                                 reg = <0x2008c000 0x1000>;
                                 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
index 499f41a2c6f0..923a25760516 100644
--- a/arch/arm/boot/dts/ls1021a-qds.dts
+++ b/arch/arm/boot/dts/ls1021a-qds.dts
@@ -1,5 +1,6 @@
 /*
  * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ * Copyright 2018 NXP
  *
  * This file is dual-licensed: you can use it either under the terms
  * of the GPL or the X11 license, at your option. Note that this dual
@@ -235,6 +236,7 @@
                 #size-cells = <1>;
                 compatible = "cfi-flash";
                 reg = <0x0 0x0 0x8000000>;
+                big-endian;
                 bank-width = <2>;
                 device-width = <1>;
         };
diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
index f0c949d74833..8b48c3c7cd21 100644
--- a/arch/arm/boot/dts/ls1021a-twr.dts
+++ b/arch/arm/boot/dts/ls1021a-twr.dts
@@ -1,5 +1,6 @@
 /*
  * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ * Copyright 2018 NXP
  *
  * This file is dual-licensed: you can use it either under the terms
  * of the GPL or the X11 license, at your option. Note that this dual
@@ -203,6 +204,7 @@
                 #size-cells = <1>;
                 compatible = "cfi-flash";
                 reg = <0x0 0x0 0x8000000>;
+                big-endian;
                 bank-width = <2>;
                 device-width = <1>;
         };
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index f18490548c78..bdd6e66a79ad 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -163,7 +163,7 @@
                         big-endian;
                 };
 
-                qspi: quadspi@1550000 {
+                qspi: spi@1550000 {
                         compatible = "fsl,ls1021a-qspi";
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -330,7 +330,7 @@
                         };
                 };
 
-                dspi0: dspi@2100000 {
+                dspi0: spi@2100000 {
                         compatible = "fsl,ls1021a-v1.0-dspi";
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -343,7 +343,7 @@
                         status = "disabled";
                 };
 
-                dspi1: dspi@2110000 {
+                dspi1: spi@2110000 {
                         compatible = "fsl,ls1021a-v1.0-dspi";
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -364,6 +364,8 @@
                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
                         clock-names = "i2c";
                         clocks = <&clockgen 4 1>;
+                        dma-names = "tx", "rx";
+                        dmas = <&edma0 1 39>, <&edma0 1 38>;
                         status = "disabled";
                 };
 
@@ -375,6 +377,8 @@
                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
                         clock-names = "i2c";
                         clocks = <&clockgen 4 1>;
+                        dma-names = "tx", "rx";
+                        dmas = <&edma0 1 37>, <&edma0 1 36>;
                         status = "disabled";
                 };
 
@@ -386,6 +390,8 @@
                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
                         clock-names = "i2c";
                         clocks = <&clockgen 4 1>;
+                        dma-names = "tx", "rx";
+                        dmas = <&edma0 1 35>, <&edma0 1 34>;
                         status = "disabled";
                 };
 
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index d77dcf890cfc..7162e0ca05b0 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -194,7 +194,7 @@
                 #clock-cells = <1>;
                 #reset-cells = <1>;
                 compatible = "amlogic,meson8-clkc";
-                reg = <0x8000 0x4>, <0x4000 0x460>;
+                reg = <0x8000 0x4>, <0x4000 0x400>;
         };
 
         reset: reset-controller@4404 {
diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts
new file mode 100644
index 000000000000..0872f6e3abf5
--- /dev/null
+++ b/arch/arm/boot/dts/meson8b-ec100.dts
@@ -0,0 +1,248 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+#include "meson8b.dtsi"
+
+/ {
+        model = "Endless Computers Endless Mini";
+        compatible = "endless,ec100", "amlogic,meson8b";
+
+        aliases {
+                serial0 = &uart_AO;
+        };
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+
+        memory {
+                reg = <0x40000000 0x40000000>;
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys-polled";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                poll-interval = <100>;
+
+                pal-switch {
+                        label = "pal";
+                        linux,input-type = <EV_SW>;
+                        linux,code = <KEY_SWITCHVIDEOMODE>;
+                        gpios = <&gpio GPIOH_7 GPIO_ACTIVE_LOW>;
+                };
+
+                ntsc-switch {
+                        label = "ntsc";
+                        linux,input-type = <EV_SW>;
+                        linux,code = <KEY_SWITCHVIDEOMODE>;
+                        gpios = <&gpio GPIOH_8 GPIO_ACTIVE_HIGH>;
+                };
+
+                power-button {
+                        label = "power";
+                        linux,code = <KEY_POWER>;
+                        gpios = <&gpio GPIOH_9 GPIO_ACTIVE_LOW>;
+                };
+        };
+
+        gpio-poweroff {
+                compatible = "gpio-poweroff";
+                /*
+                 * shutdown is managed by the EC (embedded micro-controller)
+                 * which is configured through GPIOAO_2 (poweroff GPIO) and
+                 * GPIOAO_7 (power LED, which has to go LOW as well).
+                 */
+                gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
+                timeout-ms = <20000>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                power {
+                        label = "ec100:red:power";
+                        /*
+                         * Needs to go LOW (together with the poweroff GPIO)
+                         * during shutdown to allow the EC (embedded
+                         * micro-controller) to shutdown the system. Setting
+                         * the output to LOW signals the EC to start a
+                         * "breathing"/pulsing effect until the power is fully
+                         * turned off.
+                         */
+                        gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_HIGH>;
+                        default-state = "on";
+                };
+        };
+
+        usb_vbus: regulator-usb-vbus {
+                compatible = "regulator-fixed";
+
+                regulator-name = "USB_VBUS";
+
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+
+                gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+        };
+
+        vcc_5v: regulator-vcc5v {
+                compatible = "regulator-fixed";
+
+                regulator-name = "VCC5V";
+
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+
+                gpio = <&gpio GPIODV_29 GPIO_ACTIVE_LOW>;
+
+                regulator-boot-on;
+                regulator-always-on;
+        };
+
+        vcck: regulator-vcck {
+                compatible = "pwm-regulator";
+
+                regulator-name = "VCCK";
+                regulator-min-microvolt = <860000>;
+                regulator-max-microvolt = <1140000>;
+
+                pwms = <&pwm_cd 0 1148 0>;
+                pwm-dutycycle-range = <100 0>;
+
+                regulator-boot-on;
+                regulator-always-on;
+        };
+
+        vcc_1v8: regulator-vcc1v8 {
+                compatible = "regulator-fixed";
+
+                regulator-name = "VCC1V8";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+        };
+
+        vcc_3v3: regulator-vcc3v3 {
+                compatible = "regulator-fixed";
+
+                regulator-name = "VCC3V3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
+};
+
+&cpu0 {
+        cpu-supply = <&vcck>;
+};
+
+&ethmac {
+        status = "okay";
+
+        pinctrl-0 = <&eth_rmii_pins>;
+        pinctrl-names = "default";
+
+        phy-handle = <&eth_phy0>;
+        phy-mode = "rmii";
+
+        snps,reset-gpio = <&gpio GPIOH_4 0>;
+        snps,reset-delays-us = <0 10000 1000000>;
+        snps,reset-active-low;
+
+        mdio {
+                compatible = "snps,dwmac-mdio";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                eth_phy0: ethernet-phy@0 {
+                        /* IC Plus IP101A/G (0x02430c54) */
+                        reg = <0>;
+                };
+        };
+};
+
+&i2c_A {
+        status = "okay";
+        pinctrl-0 = <&i2c_a_pins>;
+        pinctrl-names = "default";
+
+        rt5640: codec@1c {
+                compatible = "realtek,rt5640";
+                reg = <0x1c>;
+                interrupt-parent = <&gpio_intc>;
+                interrupts = <13 IRQ_TYPE_EDGE_BOTH>; /* GPIOAO_13 */
+                realtek,in1-differential;
+        };
+};
+
+&saradc {
+        status = "okay";
+        vref-supply = <&vcc_1v8>;
+};
+
+&sdio {
+        status = "okay";
+
+        pinctrl-0 = <&sd_b_pins>;
+        pinctrl-names = "default";
+
+        /* SD card */
+        sd_card_slot: slot@1 {
+                compatible = "mmc-slot";
+                reg = <1>;
+                status = "okay";
+
+                bus-width = <4>;
+                no-sdio;
+                cap-mmc-highspeed;
+                cap-sd-highspeed;
+                disable-wp;
+
+                cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
+                cd-inverted;
+
+                vmmc-supply = <&vcc_3v3>;
+        };
+};
+
+&pwm_cd {
+        status = "okay";
+        pinctrl-0 = <&pwm_c1_pins>;
+        pinctrl-names = "default";
+        clocks = <&clkc CLKID_XTAL>;
+        clock-names = "clkin0";
+};
+
+/* exposed through the pin headers labeled "URDUG1" on the top of the PCB */
+&uart_AO {
+        status = "okay";
+        pinctrl-0 = <&uart_ao_a_pins>;
+        pinctrl-names = "default";
+};
+
+/*
+ * connected to the Bluetooth part of the RTL8723BS SDIO wifi / Bluetooth
+ * combo chip. This is only available on the variant with 2GB RAM.
+ */
+&uart_B {
+        status = "okay";
+        pinctrl-0 = <&uart_b0_pins>, <&uart_b0_cts_rts_pins>;
+        pinctrl-names = "default";
+        uart-has-rtscts;
+};
+
+&usb1 {
+        status = "okay";
+        vbus-supply = <&usb_vbus>;
+};
+
+&usb1_phy {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts
index ef3177d3da3d..58669abda259 100644
--- a/arch/arm/boot/dts/meson8b-odroidc1.dts
+++ b/arch/arm/boot/dts/meson8b-odroidc1.dts
@@ -57,6 +57,10 @@
                 mmc0 = &sd_card_slot;
         };
 
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+
         memory {
                 reg = <0x40000000 0x40000000>;
         };
@@ -71,6 +75,14 @@
                 };
         };
 
+        p5v0: regulator-p5v0 {
+                compatible = "regulator-fixed";
+
+                regulator-name = "P5V0";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+        };
+
         tflash_vdd: regulator-tflash_vdd {
                 /*
                  * signal name from schematics: TFLASH_VDD_EN
@@ -81,6 +93,8 @@
                 regulator-min-microvolt = <3300000>;
                 regulator-max-microvolt = <3300000>;
 
+                vin-supply = <&vcc_3v3>;
+
                 gpio = <&gpio GPIOY_12 GPIO_ACTIVE_HIGH>;
                 enable-active-high;
         };
@@ -92,6 +106,8 @@
                 regulator-min-microvolt = <1800000>;
                 regulator-max-microvolt = <3300000>;
 
+                vin-supply = <&vcc_3v3>;
+
                 /*
                  * signal name from schematics: TF_3V3N_1V8_EN
                  */
@@ -101,6 +117,86 @@
                 states = <3300000 0
                           1800000 1>;
         };
+
+        vcc_1v8: regulator-vcc-1v8 {
+                /*
+                 * RICHTEK RT9179 configured for a fixed output voltage of
+                 * 1.8V. This supplies not only VCC1V8 but also IOREF_1V8 and
+                 * VDD1V8 according to the schematics.
+                 */
+                compatible = "regulator-fixed";
+
+                regulator-name = "VCC1V8";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+
+                vin-supply = <&p5v0>;
+        };
+
+        vcc_3v3: regulator-vcc-3v3 {
+                /*
+                 * Monolithic Power Systems MP2161 configured for a fixed
+                 * output voltage of 3.3V. This supplies not only VCC3V3 but
+                 * also VDD3V3 and VDDIO_AO3V3 according to the schematics.
+                 */
+                compatible = "regulator-fixed";
+
+                regulator-name = "VCC3V3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+
+                vin-supply = <&p5v0>;
+        };
+
+        vcck: regulator-vcck {
+                /* Monolithic Power Systems MP2161 */
+                compatible = "pwm-regulator";
+
+                regulator-name = "VCCK";
+                regulator-min-microvolt = <860000>;
+                regulator-max-microvolt = <1140000>;
+
+                vin-supply = <&p5v0>;
+
+                pwms = <&pwm_cd 0 12218 0>;
+                pwm-dutycycle-range = <91 0>;
+
+                regulator-boot-on;
+                regulator-always-on;
+        };
+
+        vddc_ddr: regulator-vddc-ddr {
+                /*
+                 * Monolithic Power Systems MP2161 configured for a fixed
+                 * output voltage of 1.5V. This supplies not only DDR_VDDC but
+                 * also DDR3_1V5 according to the schematics.
+                 */
+                compatible = "regulator-fixed";
+
+                regulator-name = "DDR_VDDC";
+                regulator-min-microvolt = <1500000>;
+                regulator-max-microvolt = <1500000>;
+
+                vin-supply = <&p5v0>;
+        };
+
+        vdd_rtc: regulator-vdd-rtc {
+                /*
+                 * Torex Semiconductor XC6215 configured for a fixed output of
+                 * 0.9V.
+                 */
+                compatible = "regulator-fixed";
+
+                regulator-name = "VDD_RTC";
+                regulator-min-microvolt = <900000>;
+                regulator-max-microvolt = <900000>;
+
+                vin-supply = <&vcc_3v3>;
+        };
+};
+
+&cpu0 {
+        cpu-supply = <&vcck>;
 };
 
 &ethmac {
@@ -154,6 +250,11 @@
         pinctrl-names = "default";
 };
 
+&saradc {
+        status = "okay";
+        vref-supply = <&vcc_1v8>;
+};
+
 &sdio {
         status = "okay";
 
@@ -180,6 +281,14 @@
         };
 };
 
+&pwm_cd {
+        status = "okay";
+        pinctrl-0 = <&pwm_c1_pins>;
+        pinctrl-names = "default";
+        clocks = <&clkc CLKID_XTAL>;
+        clock-names = "clkin0";
+};
+
 &uart_AO {
         status = "okay";
         pinctrl-0 = <&uart_ao_a_pins>;
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 08f7f6be7254..cd1ca9dda126 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -163,7 +163,7 @@
                 #clock-cells = <1>;
                 #reset-cells = <1>;
                 compatible = "amlogic,meson8b-clkc";
-                reg = <0x8000 0x4>, <0x4000 0x460>;
+                reg = <0x8000 0x4>, <0x4000 0x400>;
         };
 
         reset: reset-controller@4404 {
@@ -223,6 +223,28 @@
                         };
                 };
 
+                eth_rmii_pins: eth-rmii {
+                        mux {
+                                groups = "eth_tx_en",
+                                         "eth_txd1_0",
+                                         "eth_txd0_0",
+                                         "eth_rx_clk",
+                                         "eth_rx_dv",
+                                         "eth_rxd1",
+                                         "eth_rxd0",
+                                         "eth_mdio_en",
+                                         "eth_mdc";
+                                function = "ethernet";
+                        };
+                };
+
+                i2c_a_pins: i2c-a {
+                        mux {
+                                groups = "i2c_sda_a", "i2c_sck_a";
+                                function = "i2c_a";
+                        };
+                };
+
                 sd_b_pins: sd-b {
                         mux {
                                 groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
@@ -230,6 +252,29 @@
                                 function = "sd_b";
                         };
                 };
+
+                pwm_c1_pins: pwm-c1 {
+                        mux {
+                                groups = "pwm_c1";
+                                function = "pwm_c";
+                        };
+                };
+
+                uart_b0_pins: uart-b0 {
+                        mux {
+                                groups = "uart_tx_b0",
+                                       "uart_rx_b0";
+                                function = "uart_b";
+                        };
+                };
+
+                uart_b0_cts_rts_pins: uart-b0-cts-rts {
+                        mux {
+                                groups = "uart_cts_b0",
+                                       "uart_rts_b0";
+                                function = "uart_b";
+                        };
+                };
         };
 };
 
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
index 1cdc346a05e8..d01bdee6f2f3 100644
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -13,6 +13,7 @@
 #include <dt-bindings/power/mt2701-power.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/phy/phy.h>
+#include <dt-bindings/memory/mt2701-larb-port.h>
 #include <dt-bindings/reset/mt2701-resets.h>
 #include <dt-bindings/thermal/thermal.h>
 
@@ -121,6 +122,15 @@
                 };
         };
 
+        pmu {
+                compatible = "arm,cortex-a7-pmu";
+                interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_LOW>,
+                             <GIC_SPI 5 IRQ_TYPE_LEVEL_LOW>,
+                             <GIC_SPI 6 IRQ_TYPE_LEVEL_LOW>,
+                             <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>;
+                interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+        };
+
         system_clk: dummy13m {
                 compatible = "fixed-clock";
                 clock-frequency = <13000000>;
@@ -277,6 +287,17 @@
                 clock-names = "system-clk", "rtc-clk";
         };
 
+        smi_common: smi@1000c000 {
+                compatible = "mediatek,mt7623-smi-common",
+                             "mediatek,mt2701-smi-common";
+                reg = <0 0x1000c000 0 0x1000>;
+                clocks = <&infracfg CLK_INFRA_SMI>,
+                         <&mmsys CLK_MM_SMI_COMMON>,
+                         <&infracfg CLK_INFRA_SMI>;
+                clock-names = "apb", "smi", "async";
+                power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
+        };
+
         pwrap: pwrap@1000d000 {
                 compatible = "mediatek,mt7623-pwrap",
                              "mediatek,mt2701-pwrap";
@@ -308,6 +329,17 @@
                 reg = <0 0x10200100 0 0x1c>;
         };
 
+        iommu: mmsys_iommu@10205000 {
+                compatible = "mediatek,mt7623-m4u",
+                             "mediatek,mt2701-m4u";
+                reg = <0 0x10205000 0 0x1000>;
+                interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
+                clocks = <&infracfg CLK_INFRA_M4U>;
+                clock-names = "bclk";
+                mediatek,larbs = <&larb0 &larb1 &larb2>;
+                #iommu-cells = <1>;
+        };
+
         efuse: efuse@10206000 {
                 compatible = "mediatek,mt7623-efuse",
                              "mediatek,mt8173-efuse";
@@ -683,6 +715,90 @@
                 status = "disabled";
         };
 
+        g3dsys: syscon@13000000 {
+                compatible = "mediatek,mt7623-g3dsys",
+                             "mediatek,mt2701-g3dsys",
+                             "syscon";
+                reg = <0 0x13000000 0 0x200>;
+                #clock-cells = <1>;
+                #reset-cells = <1>;
+        };
+
+        mmsys: syscon@14000000 {
+                compatible = "mediatek,mt7623-mmsys",
+                             "mediatek,mt2701-mmsys",
+                             "syscon";
+                reg = <0 0x14000000 0 0x1000>;
+                #clock-cells = <1>;
+        };
+
+        larb0: larb@14010000 {
+                compatible = "mediatek,mt7623-smi-larb",
+                             "mediatek,mt2701-smi-larb";
+                reg = <0 0x14010000 0 0x1000>;
+                mediatek,smi = <&smi_common>;
+                mediatek,larb-id = <0>;
+                clocks = <&mmsys CLK_MM_SMI_LARB0>,
+                         <&mmsys CLK_MM_SMI_LARB0>;
+                clock-names = "apb", "smi";
+                power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
+        };
+
+        imgsys: syscon@15000000 {
+                compatible = "mediatek,mt7623-imgsys",
+                             "mediatek,mt2701-imgsys",
+                             "syscon";
+                reg = <0 0x15000000 0 0x1000>;
+                #clock-cells = <1>;
+        };
+
+        larb2: larb@15001000 {
+                compatible = "mediatek,mt7623-smi-larb",
+                             "mediatek,mt2701-smi-larb";
+                reg = <0 0x15001000 0 0x1000>;
+                mediatek,smi = <&smi_common>;
+                mediatek,larb-id = <2>;
+                clocks = <&imgsys CLK_IMG_SMI_COMM>,
+                         <&imgsys CLK_IMG_SMI_COMM>;
+                clock-names = "apb", "smi";
+                power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
+        };
+
+        jpegdec: jpegdec@15004000 {
+                compatible = "mediatek,mt7623-jpgdec",
+                             "mediatek,mt2701-jpgdec";
+                reg = <0 0x15004000 0 0x1000>;
+                interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
+                clocks =  <&imgsys CLK_IMG_JPGDEC_SMI>,
+                          <&imgsys CLK_IMG_JPGDEC>;
+                clock-names = "jpgdec-smi",
+                              "jpgdec";
+                power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
+                mediatek,larb = <&larb2>;
+                iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
+                         <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
+        };
+
+        vdecsys: syscon@16000000 {
+                compatible = "mediatek,mt7623-vdecsys",
+                             "mediatek,mt2701-vdecsys",
+                             "syscon";
+                reg = <0 0x16000000 0 0x1000>;
+                #clock-cells = <1>;
+        };
+
+        larb1: larb@16010000 {
+                compatible = "mediatek,mt7623-smi-larb",
+                             "mediatek,mt2701-smi-larb";
+                reg = <0 0x16010000 0 0x1000>;
+                mediatek,smi = <&smi_common>;
+                mediatek,larb-id = <1>;
+                clocks = <&vdecsys CLK_VDEC_CKGEN>,
+                         <&vdecsys CLK_VDEC_LARB>;
+                clock-names = "apb", "smi";
+                power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
+        };
+
         hifsys: syscon@1a000000 {
                 compatible = "mediatek,mt7623-hifsys",
                              "mediatek,mt2701-hifsys",
@@ -937,6 +1053,14 @@
                 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
                 status = "disabled";
         };
+
+        bdpsys: syscon@1c000000 {
+                compatible = "mediatek,mt7623-bdpsys",
+                             "mediatek,mt2701-bdpsys",
+                             "syscon";
+                reg = <0 0x1c000000 0 0x1000>;
+                #clock-cells = <1>;
+        };
 };
 
 &pio {
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index f1d6de8b3c19..000bf16de651 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -114,7 +114,7 @@
                         dma-names = "tx", "rx";
                 };
 
-                mcspi1: mcspi@48098000 {
+                mcspi1: spi@48098000 {
                         compatible = "ti,omap2-mcspi";
                         ti,hwmods = "mcspi1";
                         reg = <0x48098000 0x100>;
@@ -125,7 +125,7 @@
                                     "tx2", "rx2", "tx3", "rx3";
                 };
 
-                mcspi2: mcspi@4809a000 {
+                mcspi2: spi@4809a000 {
                         compatible = "ti,omap2-mcspi";
                         ti,hwmods = "mcspi2";
                         reg = <0x4809a000 0x100>;
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index 84635eeb99cd..7f57af2f10ac 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -285,7 +285,7 @@
                         ti,timer-alwon;
                 };
 
-                mcspi3: mcspi@480b8000 {
+                mcspi3: spi@480b8000 {
                         compatible = "ti,omap2-mcspi";
                         ti,hwmods = "mcspi3";
                         reg = <0x480b8000 0x100>;
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index d80587de0bbf..9985ee2aae0c 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -160,10 +160,11 @@
 
                 clocks = <&emu_src_ck>;
                 clock-names = "apb_pclk";
-                port {
-                        etb_in: endpoint {
-                                slave-mode;
-                                remote-endpoint = <&etm_out>;
+                in-ports {
+                        port {
+                                etb_in: endpoint {
+                                        remote-endpoint = <&etm_out>;
+                                };
                         };
                 };
         };
@@ -174,9 +175,11 @@
 
                 clocks = <&emu_src_ck>;
                 clock-names = "apb_pclk";
-                port {
-                        etm_out: endpoint {
-                                remote-endpoint = <&etb_in>;
+                out-ports {
+                        port {
+                                etm_out: endpoint {
+                                        remote-endpoint = <&etb_in>;
+                                };
                         };
                 };
         };
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index 3ca8991a6c3e..91bb50ad9a4f 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -147,10 +147,11 @@
 
                 clocks = <&emu_src_ck>;
                 clock-names = "apb_pclk";
-                port {
-                        etb_in: endpoint {
-                                slave-mode;
-                                remote-endpoint = <&etm_out>;
+                in-ports {
+                        port {
+                                etb_in: endpoint {
+                                        remote-endpoint = <&etm_out>;
+                                };
                         };
                 };
         };
@@ -161,9 +162,11 @@
 
                 clocks = <&emu_src_ck>;
                 clock-names = "apb_pclk";
-                port {
-                        etm_out: endpoint {
-                                remote-endpoint = <&etb_in>;
+                out-ports {
+                        port {
+                                etm_out: endpoint {
+                                        remote-endpoint = <&etb_in>;
+                                };
                         };
                 };
         };
diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi
index ac830b917776..d5fe55392230 100644
--- a/arch/arm/boot/dts/omap3-gta04.dtsi
+++ b/arch/arm/boot/dts/omap3-gta04.dtsi
@@ -10,6 +10,7 @@
 /dts-v1/;
 
 #include "omap36xx.dtsi"
+#include <dt-bindings/input/input.h>
 
 / {
         model = "OMAP3 GTA04";
@@ -28,6 +29,7 @@
 
         aliases {
                 display0 = &lcd;
+                display1 = &tv0;
         };
 
         /* fixed 26MHz oscillator */
@@ -42,12 +44,27 @@
 
                 aux-button {
                         label = "aux";
-                        linux,code = <169>;
+                        linux,code = <KEY_PHONE>;
                         gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
                         wakeup-source;
                 };
         };
 
+        antenna-detect {
+                compatible = "gpio-keys";
+
+                gps_antenna_button: gps-antenna-button {
+                        label = "GPS_EXT_ANT";
+                        linux,input-type = <EV_SW>;
+                        linux,code = <SW_LINEIN_INSERT>;
+                        gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* GPIO144 */
+                        interrupt-parent = <&gpio5>;
+                        interrupts = <16 IRQ_TYPE_EDGE_BOTH>;
+                        debounce-interval = <10>;
+                        wakeup-source;
+                };
+        };
+
         sound {
                 compatible = "ti,omap-twl4030";
                 ti,model = "gta04";
@@ -55,7 +72,7 @@
                 ti,mcbsp = <&mcbsp2>;
         };
 
-         /* GSM audio */
+        /* GSM audio */
         sound_telephony {
                 compatible = "simple-audio-card";
                 simple-audio-card,name = "GTA04 voice";
@@ -78,7 +95,7 @@
                 #sound-dai-cells = <0>;
         };
 
-        spi_lcd {
+        spi_lcd: spi_lcd {
                 compatible = "spi-gpio";
                 #address-cells = <0x1>;
                 #size-cells = <0x0>;
@@ -131,7 +148,7 @@
         };
 
         tv0: connector {
-                compatible = "svideo-connector";
+                compatible = "composite-video-connector";
                 label = "tv";
 
                 port {
@@ -143,7 +160,7 @@
 
         tv_amp: opa362 {
                 compatible = "ti,opa362";
-                enable-gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
+                enable-gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;    /* GPIO_23 to enable video out amplifier */
 
                 ports {
                         #address-cells = <1>;
@@ -169,6 +186,42 @@
                 compatible = "mmc-pwrseq-simple";
                 reset-gpios = <&tca6507 0 GPIO_ACTIVE_LOW>;     /* W2CBW003 reset through tca6507 */
         };
+
+        /* devconf0 setup for mcbsp1 clock pins */
+        pinmux_mcbsp1@48002274 {
+                compatible = "pinctrl-single";
+                reg = <0x48002274 4>;   /* CONTROL_DEVCONF0 */
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-single,bit-per-mux;
+                pinctrl-single,register-width = <32>;
+                pinctrl-single,function-mask = <0x7>;   /* MCBSP1 CLK pinmux */
+                #pinctrl-cells = <2>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&mcbsp1_devconf0_pins>;
+                mcbsp1_devconf0_pins: pinmux_mcbsp1_devconf0_pins {
+                        /*                   offset bits mask */
+                        pinctrl-single,bits = <0x00 0x08 0x1c>; /* set MCBSP1_CLKR */
+                };
+        };
+
+        /* devconf1 setup for tvout pins */
+        pinmux_tv_out@480022d8 {
+                compatible = "pinctrl-single";
+                reg = <0x480022d8 4>;   /* CONTROL_DEVCONF1 */
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-single,bit-per-mux;
+                pinctrl-single,register-width = <32>;
+                pinctrl-single,function-mask = <0x81>;  /* TV out pin control */
+                #pinctrl-cells = <2>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&tv_acbias_devconf1_pins>;
+                tv_acbias_devconf1_pins: pinmux_tv_acbias_devconf1_pins {
+                        /*                      offset  bits    mask */
+                        pinctrl-single,bits = <0x00 0x40800 0x40800>;   /* set TVOUTBYPASS and TVOUTACEN */
+                };
+        };
 };
 
 &omap3_pmx_core {
@@ -220,14 +273,14 @@
                 >;
         };
 
-        backlight_pins: backlight_pins_pimnux {
+        backlight_pins: backlight_pins_pinmux {
                 pinctrl-single,pins = <
                         OMAP3_CORE1_IOPAD(0x20ba, MUX_MODE3)            /* gpt11/gpio57 */
                 >;
         };
 
         dss_dpi_pins: pinmux_dss_dpi_pins {
-               pinctrl-single,pins = <
+                pinctrl-single,pins = <
                         OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0)   /* dss_pclk.dss_pclk */
                         OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0)   /* dss_hsync.dss_hsync */
                         OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0)   /* dss_vsync.dss_vsync */
@@ -265,6 +318,12 @@
                 >;
         };
 
+        bmp085_pins: pinmux_bmp085_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2136, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio113 */
+                >;
+        };
+
         bma180_pins: pinmux_bma180_pins {
                 pinctrl-single,pins = <
                         OMAP3_CORE1_IOPAD(0x213a, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio115 */
@@ -282,6 +341,78 @@
                         OMAP3_CORE1_IOPAD(0x2134, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio112 */
                 >;
         };
+
+        penirq_pins: pinmux_penirq_pins {
+                pinctrl-single,pins = <
+                        /* here we could enable to wakeup the cpu from suspend by a pen touch */
+                        OMAP3_CORE1_IOPAD(0x2194, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio160 */
+                >;
+        };
+
+        camera_pins: pinmux_camera_pins {
+                pinctrl-single,pins = <
+                        /* set up parallel camera interface */
+                        OMAP3_CORE1_IOPAD(0x210c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_hs */
+                        OMAP3_CORE1_IOPAD(0x210e, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_vs */
+                        OMAP3_CORE1_IOPAD(0x2110, PIN_OUTPUT | MUX_MODE0) /* cam_xclka */
+                        OMAP3_CORE1_IOPAD(0x2112, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_pclk */
+                        OMAP3_CORE1_IOPAD(0x2114, PIN_OUTPUT | MUX_MODE4) /* cam_fld = gpio_98 */
+                        OMAP3_CORE1_IOPAD(0x2116, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d0 */
+                        OMAP3_CORE1_IOPAD(0x2118, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d1 */
+                        OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d2 */
+                        OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d3 */
+                        OMAP3_CORE1_IOPAD(0x211e, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d4 */
+                        OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d5 */
+                        OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d6 */
+                        OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d7 */
+                        OMAP3_CORE1_IOPAD(0x2126, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d8 */
+                        OMAP3_CORE1_IOPAD(0x2128, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d9 */
+                        OMAP3_CORE1_IOPAD(0x212a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d10 */
+                        OMAP3_CORE1_IOPAD(0x212c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* cam_d10 */
+                        OMAP3_CORE1_IOPAD(0x212e, PIN_OUTPUT | MUX_MODE0) /* cam_xclkb */
+                        OMAP3_CORE1_IOPAD(0x2130, PIN_OUTPUT | MUX_MODE4) /* cam_wen = gpio_167 */
+                        OMAP3_CORE1_IOPAD(0x2132, PIN_INPUT_PULLDOWN | MUX_MODE4) /* cam_strobe */
+                >;
+        };
+
+        mcbsp1_pins: pinmux_mcbsp1_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x218c, PIN_INPUT | MUX_MODE4)        /* mcbsp1_clkr.mcbsp1_clkr - gpio_156 FM interrupt */
+                        OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE0)       /* mcbsp1_clkr.mcbsp1_fsr */
+                        OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE0)       /* mcbsp1_dx.mcbsp1_dx */
+                        OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT | MUX_MODE0)        /* mcbsp1_dx.mcbsp1_dr */
+                        /* mcbsp_clks is used as PENIRQ */
+                        /* OMAP3_CORE1_IOPAD(0x2194, PIN_INPUT | MUX_MODE0)     /* mcbsp_clks.mcbsp_clks */
+                        OMAP3_CORE1_IOPAD(0x2196, PIN_INPUT | MUX_MODE0)        /* mcbsp_clks.mcbsp1_fsx */
+                        OMAP3_CORE1_IOPAD(0x2198, PIN_INPUT | MUX_MODE0)        /* mcbsp1_clkx.mcbsp1_clkx */
+                >;
+        };
+
+        mcbsp2_pins: pinmux_mcbsp2_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0)        /* mcbsp2_fsx.mcbsp2_fsx */
+                        OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0)        /* mcbsp2_fsx.mcbsp2_clkx */
+                        OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0)        /* mcbsp2_dr.mcbsp2_dr */
+                        OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0)       /* mcbsp2_dr.mcbsp2_dx */
+                >;
+        };
+
+        mcbsp3_pins: pinmux_mcbsp3_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x216c, PIN_OUTPUT | MUX_MODE0)       /* mcbsp3_dx.mcbsp3_dx */
+                        OMAP3_CORE1_IOPAD(0x216e, PIN_INPUT | MUX_MODE0)        /* mcbsp3_dx.mcbsp3_dr */
+                        OMAP3_CORE1_IOPAD(0x2170, PIN_INPUT | MUX_MODE0)        /* mcbsp3_clkx.mcbsp3_clkx */
+                        OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE0)        /* mcbsp3_clkx.mcbsp3_fsx */
+                >;
+        };
+
+        mcbsp4_pins: pinmux_mcbsp4_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT_PULLDOWN | MUX_MODE0)       /* mcbsp4_clkx.mcbsp4_clkx */
+                        OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT_PULLDOWN | MUX_MODE0)       /* mcbsp4_clkx.mcbsp4_dr */
+                        OMAP3_CORE1_IOPAD(0x218a, PIN_INPUT_PULLDOWN | MUX_MODE0)       /* mcbsp4_dx.mcbsp4_fsx */
+                >;
+        };
 };
 
 &omap3_pmx_core2 {
@@ -347,6 +478,8 @@
         bmp085@77 {
                 compatible = "bosch,bmp085";
                 reg = <0x77>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&bmp085_pins>;
                 interrupt-parent = <&gpio4>;
                 interrupts = <17 IRQ_TYPE_EDGE_RISING>; /* GPIO_113 */
         };
@@ -402,7 +535,7 @@
                         reg = <0x4>;
                 };
 
-                wifi_reset: wifi_reset@6 {
+                wifi_reset: wifi_reset@6 { /* reference as <&tca_gpios 0 0> since it is currently the only GPIO */
                         reg = <0x6>;
                         compatible = "gpio";
                 };
@@ -422,10 +555,19 @@
         tsc2007@48 {
                 compatible = "ti,tsc2007";
                 reg = <0x48>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&penirq_pins>;
                 interrupt-parent = <&gpio6>;
                 interrupts = <0 IRQ_TYPE_EDGE_FALLING>; /* GPIO_160 */
-                gpios = <&gpio6 0 GPIO_ACTIVE_LOW>;
+                gpios = <&gpio6 0 GPIO_ACTIVE_LOW>;     /* GPIO_160 */
                 ti,x-plate-ohms = <600>;
+                touchscreen-size-x = <480>;
+                touchscreen-size-y = <640>;
+                touchscreen-max-pressure = <1000>;
+                touchscreen-fuzz-x = <3>;
+                touchscreen-fuzz-y = <8>;
+                touchscreen-fuzz-pressure = <10>;
+                touchscreen-inverted-y;
         };
 
         /* RFID EEPROM */
@@ -462,6 +604,7 @@
         vmmc-supply = <&vmmc1>;
         bus-width = <4>;
         ti,non-removable;
+        broken-cd;      /* hardware has no CD */
 };
 
 &mmc2 {
@@ -476,6 +619,19 @@
         status = "disabled";
 };
 
+#define BIT(x) (1 << (x))
+&twl_gpio {
+        /* pullups: BIT(2) */
+        ti,pullups = <BIT(2)>;
+        /*
+         * pulldowns:
+         * BIT(0),  BIT(1), BIT(6), BIT(7), BIT(8), BIT(13)
+         * BIT(15), BIT(16), BIT(17)
+         */
+        ti,pulldowns = <(BIT(0) | BIT(1) | BIT(6) | BIT(7) | BIT(8) |
+                         BIT(13) | BIT(15) | BIT(16) | BIT(17))>;
+};
+
 &twl_keypad {
         status = "disabled";
 };
@@ -493,6 +649,7 @@
 &uart3 {
         pinctrl-names = "default";
         pinctrl-0 = <&uart3_pins>;
+        interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
 };
 
 &charger {
@@ -510,7 +667,7 @@
 &vaux2 {
         regulator-min-microvolt = <2800000>;
         regulator-max-microvolt = <2800000>;
-        regulator-always-on;
+        regulator-always-on;    /* we should never switch off while vio is on! */
 };
 
 /* camera */
@@ -531,6 +688,12 @@
         regulator-max-microvolt = <3150000>;
 };
 
+/* Needed to power the DPI pins */
+
+&vpll2 {
+        regulator-always-on;
+};
+
 &dss {
         pinctrl-names = "default";
         pinctrl-0 = < &dss_dpi_pins >;
@@ -551,10 +714,14 @@
 
         vdda-supply = <&vdac>;
 
+        #address-cells = <1>;
+        #size-cells = <0>;
+
         port {
+                reg = <0>;
                 venc_out: endpoint {
                         remote-endpoint = <&opa_in>;
-                        ti,channels = <2>;
+                        ti,channels = <1>;
                         ti,invert-polarity;
                 };
         };
@@ -569,27 +736,27 @@
                 interrupt-parent = <&gpmc>;
                 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
                              <1 IRQ_TYPE_NONE>; /* termcount */
+                ti,nand-ecc-opt = "ham1";
+                rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
                 nand-bus-width = <16>;
-                ti,nand-ecc-opt = "bch8";
+                #address-cells = <1>;
+                #size-cells = <1>;
 
-                gpmc,sync-clk-ps = <0>;
+                gpmc,device-width = <2>;
                 gpmc,cs-on-ns = <0>;
                 gpmc,cs-rd-off-ns = <44>;
                 gpmc,cs-wr-off-ns = <44>;
                 gpmc,adv-on-ns = <6>;
                 gpmc,adv-rd-off-ns = <34>;
                 gpmc,adv-wr-off-ns = <44>;
-                gpmc,we-off-ns = <40>;
                 gpmc,oe-off-ns = <54>;
+                gpmc,we-off-ns = <40>;
                 gpmc,access-ns = <64>;
                 gpmc,rd-cycle-ns = <82>;
                 gpmc,wr-cycle-ns = <82>;
                 gpmc,wr-access-ns = <40>;
                 gpmc,wr-data-mux-bus-ns = <0>;
-                gpmc,device-width = <2>;
-
-                #address-cells = <1>;
-                #size-cells = <1>;
+                gpmc,sync-clk-ps = <0>;
 
                 x-loader@0 {
                         label = "X-Loader";
@@ -598,28 +765,51 @@
 
                 bootloaders@80000 {
                         label = "U-Boot";
-                        reg = <0x80000 0x1e0000>;
+                        reg = <0x80000 0x1c0000>;
                 };
 
-                bootloaders_env@260000 {
+                bootloaders_env@240000 {
                         label = "U-Boot Env";
-                        reg = <0x260000 0x20000>;
+                        reg = <0x240000 0x40000>;
                 };
 
                 kernel@280000 {
                         label = "Kernel";
-                        reg = <0x280000 0x400000>;
+                        reg = <0x280000 0x600000>;
                 };
 
-                filesystem@680000 {
+                filesystem@880000 {
                         label = "File System";
-                        reg = <0x680000 0xf980000>;
+                        reg = <0x880000 0>;     /* 0 = MTDPART_SIZ_FULL */
                 };
         };
 };
 
-&mcbsp2 {
-        status = "okay";
+&mcbsp1 { /* FM Transceiver PCM */
+        status = "ok";
+        #sound-dai-cells = <0>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&mcbsp1_pins>;
+};
+
+&mcbsp2 { /* TPS65950 I2S */
+        status = "ok";
+        pinctrl-names = "default";
+        pinctrl-0 = <&mcbsp2_pins>;
+};
+
+&mcbsp3 { /* Bluetooth PCM */
+        status = "ok";
+        #sound-dai-cells = <0>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&mcbsp3_pins>;
+};
+
+&mcbsp4 { /* GSM voice PCM */
+        status = "ok";
+        #sound-dai-cells = <0>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&mcbsp4_pins>;
 };
 
 &hdqw1w {
@@ -627,6 +817,22 @@
         pinctrl-0 = <&hdq_pins>;
 };
 
-&mcbsp4 {
-        status = "okay";
+/* image signal processor within OMAP3 SoC */
+&isp {
+        ports {
+                port@0 {
+                        reg = <0>;
+                        parallel_ep: endpoint {
+                                ti,isp-clock-divisor = <1>;
+                                ti,strobe-mode;
+                                bus-width = <8>;/* Used data lines */
+                                data-shift = <2>; /* Lines 9:2 are used */
+                                hsync-active = <0>; /* Active low */
+                                vsync-active = <1>; /* Active high */
+                                data-active = <1>;/* Active high */
+                                pclk-sample = <1>;/* Falling */
+                        };
+                };
+                /* port@1 and port@2 are not used by GTA04 */
+        };
 };
diff --git a/arch/arm/boot/dts/omap3-gta04a3.dts b/arch/arm/boot/dts/omap3-gta04a3.dts
index 3099a892cf50..cc9244956679 100644
--- a/arch/arm/boot/dts/omap3-gta04a3.dts
+++ b/arch/arm/boot/dts/omap3-gta04a3.dts
@@ -9,7 +9,7 @@
 #include "omap3-gta04.dtsi"
 
 / {
-        model = "Goldelico GTA04A3";
+        model = "Goldelico GTA04A3/Letux 2804";
 };
 
 &i2c2 {
diff --git a/arch/arm/boot/dts/omap3-gta04a4.dts b/arch/arm/boot/dts/omap3-gta04a4.dts
index c918bb1f0529..77afc711fe4f 100644
--- a/arch/arm/boot/dts/omap3-gta04a4.dts
+++ b/arch/arm/boot/dts/omap3-gta04a4.dts
@@ -9,5 +9,5 @@
 #include "omap3-gta04.dtsi"
 
 / {
-        model = "Goldelico GTA04A4";
+        model = "Goldelico GTA04A4/Letux 2804";
 };
diff --git a/arch/arm/boot/dts/omap3-gta04a5.dts b/arch/arm/boot/dts/omap3-gta04a5.dts
index 600b6ca5a1bd..bd232b1b24cb 100644
--- a/arch/arm/boot/dts/omap3-gta04a5.dts
+++ b/arch/arm/boot/dts/omap3-gta04a5.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2014 H. Nikolaus Schaller <hns@goldelico.com>
+ * Copyright (C) 2014-18 H. Nikolaus Schaller <hns@goldelico.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -9,9 +9,132 @@
 #include "omap3-gta04.dtsi"
 
 / {
-        model = "Goldelico GTA04A5";
+        model = "Goldelico GTA04A5/Letux 2804";
 
         sound {
-                ti,jack-det-gpio = <&twl_gpio 2 GPIO_ACTIVE_HIGH>;    /* GTA04A5 only */
+                ti,jack-det-gpio = <&twl_gpio 2 GPIO_ACTIVE_HIGH>;      /* GTA04A5 only */
+        };
+
+        wlan_en: wlan_en_regulator {
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&wlan_pins>;
+                regulator-name = "wlan-en-regulator";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+
+                gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>;    /* GPIO_138 */
+
+                startup-delay-us = <70000>;
+                enable-active-high;
+        };
+
+        pps {
+                compatible = "pps-gpio";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pps_pins>;
+
+                gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>; /* GPIN_114 */
+        };
+
+};
+
+&gpio5 {
+        irda_en {
+                gpio-hog;
+                gpios = <(175-160) GPIO_ACTIVE_HIGH>;
+                output-high;    /* activate gpio_175 to disable IrDA receiver */
+        };
+};
+
+&omap3_pmx_core {
+        bt_pins: pinmux_bt_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4)       /* mmc2_dat5 = mmc3_dat1 = gpio137 */
+                >;
+        };
+
+        wlan_pins: pinmux_wlan_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4)       /* mmc2_dat6 = mmc3_dat2 = gpio138 */
+                >;
+        };
+
+        wlan_irq_pin: pinmux_wlan_irq_pin {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE4) /* mmc2_dat7 = mmc3_dat3 = gpio139 */
+                >;
+        };
+
+        irda_pins: pinmux_irda {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x21d0, PIN_OUTPUT_PULLUP | MUX_MODE4)        /* mcspi1_cs1 = gpio175 */
+                >;
+        };
+
+        pps_pins: pinmux_pps_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2138, PIN_INPUT | MUX_MODE4) /* gpin114 */
+                >;
+        };
+
+};
+
+/*
+ * for WL183x module see
+ * http://lxr.free-electrons.com/source/Documentation/devicetree/bindings/net/wireless/ti,wlcore.txt
+ */
+
+&wifi_pwrseq {
+        /delete-property/ reset-gpios;
+};
+
+&mmc2 {
+        vmmc-supply = <&wlan_en>;
+        bus-width = <4>;
+        cap-power-off-card;
+        non-removable;
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&wlan_irq_pin>;
+
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        /delete-property/ mmc-pwrseq;
+
+        wlcore: wlcore@2 {
+                compatible = "ti,wl1837";
+                reg = <2>;
+                interrupt-parent = <&gpio5>;
+                interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;  /* GPIO_139 */
+                ref-clock-frequency = <26000000>;
+        };
+};
+
+&i2c2 {
+        /delete-node/ bmp085@77;
+        /delete-node/ bma180@41;
+        /delete-node/ itg3200@68;
+        /delete-node/ hmc5843@1e;
+
+        bmg160@69 {
+                compatible = "bosch,bmg160";
+                reg = <0x69>;
+        };
+
+        bmc150@10 {
+                compatible = "bosch,bmc150_accel";
+                reg = <0x10>;
+        };
+
+        bmc150@12 {
+                compatible = "bosch,bmc150_magn";
+                reg = <0x12>;
+        };
+
+        bme280@76 {
+                compatible = "bosch,bme280";
+                reg = <0x76>;
         };
 };
diff --git a/arch/arm/boot/dts/omap3-gta04a5one.dts b/arch/arm/boot/dts/omap3-gta04a5one.dts
new file mode 100644
index 000000000000..9b7bbdc344b3
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-gta04a5one.dts
@@ -0,0 +1,114 @@
+/*
+ * Copyright (C) 2014-18 H. Nikolaus Schaller <hns@goldelico.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "omap3-gta04a5.dts"
+
+&omap3_pmx_core {
+        model = "Goldelico GTA04A5/Letux 2804 with OneNAND";
+
+        gpmc_pins: pinmux_gpmc_pins {
+                pinctrl-single,pins = <
+
+                        /* address lines */
+                        OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0)       /* gpmc_a1.gpmc_a1 */
+                        OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0)       /* gpmc_a2.gpmc_a2 */
+                        OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0)       /* gpmc_a3.gpmc_a3 */
+
+                        /* data lines, gpmc_d0..d7 not muxable according to TRM */
+                        OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0)        /* gpmc_d8.gpmc_d8 */
+                        OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0)        /* gpmc_d9.gpmc_d9 */
+                        OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0)        /* gpmc_d10.gpmc_d10 */
+                        OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0)        /* gpmc_d11.gpmc_d11 */
+                        OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0)        /* gpmc_d12.gpmc_d12 */
+                        OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0)        /* gpmc_d13.gpmc_d13 */
+                        OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0)        /* gpmc_d14.gpmc_d14 */
+                        OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0)        /* gpmc_d15.gpmc_d15 */
+
+                        /*
+                         * gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable
+                         * according to TRM. OneNAND seems to require PIN_INPUT on clock.
+                         */
+                        OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0)       /* gpmc_ncs1.gpmc_ncs1 */
+                        OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0)        /* gpmc_clk.gpmc_clk */
+                >;
+        };
+};
+
+&gpmc {
+        /* switch inherited setup to OneNAND */
+
+        ranges = <0 0 0x04000000 0x1000000>;    /* CS0: 16MB for OneNAND */
+        pinctrl-names = "default";
+        pinctrl-0 = <&gpmc_pins>;
+
+        /delete-node/ nand@0,0;
+
+        onenand@0,0 {
+
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "ti,omap2-onenand";
+                reg = <0 0 0x20000>;    /* CS0, offset 0, IO size 128K */
+
+                gpmc,sync-read;
+                gpmc,sync-write;
+                gpmc,burst-length = <16>;
+                gpmc,burst-read;
+                gpmc,burst-wrap;
+                gpmc,burst-write;
+                gpmc,device-width = <2>;
+                gpmc,mux-add-data = <2>;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <87>;
+                gpmc,cs-wr-off-ns = <87>;
+                gpmc,adv-on-ns = <0>;
+                gpmc,adv-rd-off-ns = <10>;
+                gpmc,adv-wr-off-ns = <10>;
+                gpmc,oe-on-ns = <15>;
+                gpmc,oe-off-ns = <87>;
+                gpmc,we-on-ns = <0>;
+                gpmc,we-off-ns = <87>;
+                gpmc,rd-cycle-ns = <112>;
+                gpmc,wr-cycle-ns = <112>;
+                gpmc,access-ns = <81>;
+                gpmc,page-burst-access-ns = <15>;
+                gpmc,bus-turnaround-ns = <0>;
+                gpmc,cycle2cycle-delay-ns = <0>;
+                gpmc,wait-monitoring-ns = <0>;
+                gpmc,clk-activation-ns = <5>;
+                gpmc,wr-data-mux-bus-ns = <30>;
+                gpmc,wr-access-ns = <81>;
+                gpmc,sync-clk-ps = <15000>;
+
+                x-loader@0 {
+                        label = "X-Loader";
+                        reg = <0 0x80000>;
+                };
+
+                bootloaders@80000 {
+                        label = "U-Boot";
+                        reg = <0x80000 0x1c0000>;
+                };
+
+                bootloaders_env@240000 {
+                        label = "U-Boot Env";
+                        reg = <0x240000 0x40000>;
+                };
+
+                kernel@280000 {
+                        label = "Kernel";
+                        reg = <0x280000 0x600000>;
+                };
+
+                filesystem@880000 {
+                        label = "File System";
+                        reg = <0x880000 0>;     /* 0 = MTDPART_SIZ_FULL */
+                };
+
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-n9.dts b/arch/arm/boot/dts/omap3-n9.dts
index ded5fcf084eb..1f91646b8951 100644
--- a/arch/arm/boot/dts/omap3-n9.dts
+++ b/arch/arm/boot/dts/omap3-n9.dts
@@ -40,7 +40,7 @@
 };
 
 &i2c3 {
-        ak8975@0f {
+        ak8975@f {
                 compatible = "asahi-kasei,ak8975";
                 reg = <0x0f>;
         };
diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi b/arch/arm/boot/dts/omap5-board-common.dtsi
index ab6f640b282b..bf7ca00f4c21 100644
--- a/arch/arm/boot/dts/omap5-board-common.dtsi
+++ b/arch/arm/boot/dts/omap5-board-common.dtsi
@@ -700,6 +700,10 @@
         vbus-supply = <&smps10_out1_reg>;
 };
 
+&dwc3 {
+        dr_mode = "otg";
+};
+
 &mcspi1 {
 
 };
diff --git a/arch/arm/boot/dts/orion5x-linkstation.dtsi b/arch/arm/boot/dts/orion5x-linkstation.dtsi
index ebd93df5d07a..b6c9b85951ea 100644
--- a/arch/arm/boot/dts/orion5x-linkstation.dtsi
+++ b/arch/arm/boot/dts/orion5x-linkstation.dtsi
@@ -156,7 +156,7 @@
 &i2c {
         status = "okay";
 
-        rtc {
+        rtc@32 {
                 compatible = "ricoh,rs5c372a";
                 reg = <0x32>;
         };
diff --git a/arch/arm/boot/dts/owl-s500-cubieboard6.dts b/arch/arm/boot/dts/owl-s500-cubieboard6.dts
index ea4e01bce8d1..7c96c59b610d 100644
--- a/arch/arm/boot/dts/owl-s500-cubieboard6.dts
+++ b/arch/arm/boot/dts/owl-s500-cubieboard6.dts
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Cubietech CubieBoard6
  *
  * Copyright (c) 2017 Andreas Färber
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
 /dts-v1/;
diff --git a/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts b/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts
index 7be1d2eaf3f0..e610d49395d2 100644
--- a/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts
+++ b/arch/arm/boot/dts/owl-s500-guitar-bb-rev-b.dts
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2016-2017 Andreas Färber
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
 /dts-v1/;
diff --git a/arch/arm/boot/dts/owl-s500-guitar.dtsi b/arch/arm/boot/dts/owl-s500-guitar.dtsi
index 079b2c02cc13..81cc39871f17 100644
--- a/arch/arm/boot/dts/owl-s500-guitar.dtsi
+++ b/arch/arm/boot/dts/owl-s500-guitar.dtsi
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * LeMaker Guitar SoM
  *
  * Copyright (c) 2016-2017 Andreas Färber
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
 #include "owl-s500.dtsi"
diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
index 43c9980a4260..5ceb6cc4451d 100644
--- a/arch/arm/boot/dts/owl-s500.dtsi
+++ b/arch/arm/boot/dts/owl-s500.dtsi
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Actions Semi S500 SoC
  *
  * Copyright (c) 2016-2017 Andreas Färber
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/arch/arm/boot/dts/pxa25x.dtsi b/arch/arm/boot/dts/pxa25x.dtsi
index 95d59be97213..8494b5787170 100644
--- a/arch/arm/boot/dts/pxa25x.dtsi
+++ b/arch/arm/boot/dts/pxa25x.dtsi
@@ -80,6 +80,10 @@
                         #pwm-cells = <1>;
                         clocks = <&clks CLK_PWM1>;
                 };
+
+                rtc@40900000 {
+                        clocks = <&clks CLK_OSC32k768>;
+                };
         };
 
         timer@40a00000 {
diff --git a/arch/arm/boot/dts/pxa27x.dtsi b/arch/arm/boot/dts/pxa27x.dtsi
index 747f750f675d..3228ad5fb725 100644
--- a/arch/arm/boot/dts/pxa27x.dtsi
+++ b/arch/arm/boot/dts/pxa27x.dtsi
@@ -71,7 +71,7 @@
                         clocks = <&clks CLK_PWM1>;
                 };
 
-                pwri2c: i2c@40f000180 {
+                pwri2c: i2c@40f00180 {
                         compatible = "mrvl,pxa-i2c";
                         reg = <0x40f00180 0x24>;
                         interrupts = <6>;
@@ -113,6 +113,10 @@
 
                         status = "disabled";
                 };
+
+                rtc@40900000 {
+                        clocks = <&clks CLK_OSC32k768>;
+                };
         };
 
         clocks {
diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi
index a520b4c14ea9..080d5c5169b5 100644
--- a/arch/arm/boot/dts/pxa2xx.dtsi
+++ b/arch/arm/boot/dts/pxa2xx.dtsi
@@ -9,6 +9,25 @@
 #include "skeleton.dtsi"
 #include "dt-bindings/clock/pxa-clock.h"
 
+#define PMGROUP(pin) #pin
+#define PMMUX(func, pin, af)                    \
+        mux- ## func {                          \
+                groups = PMGROUP(P ## pin);     \
+                function = #af;                 \
+        }
+#define PMMUX_LPM_LOW(func, pin, af)            \
+        mux- ## func {                          \
+                groups = PMGROUP(P ## pin);     \
+                function = #af;                 \
+                low-power-disable;              \
+        }
+#define PMMUX_LPM_HIGH(func, pin, af)           \
+        mux- ## func {                          \
+                groups = PMGROUP(P ## pin);     \
+                function = #af;                 \
+                low-power-enable;               \
+        }
+
 / {
         model = "Marvell PXA2xx family SoC";
         compatible = "marvell,pxa2xx";
@@ -76,7 +95,7 @@
                         };
                 };
 
-                ffuart: uart@40100000 {
+                ffuart: serial@40100000 {
                         compatible = "mrvl,pxa-uart";
                         reg = <0x40100000 0x30>;
                         interrupts = <22>;
@@ -84,7 +103,7 @@
                         status = "disabled";
                 };
 
-                btuart: uart@40200000 {
+                btuart: serial@40200000 {
                         compatible = "mrvl,pxa-uart";
                         reg = <0x40200000 0x30>;
                         interrupts = <21>;
@@ -92,7 +111,7 @@
                         status = "disabled";
                 };
 
-                stuart: uart@40700000 {
+                stuart: serial@40700000 {
                         compatible = "mrvl,pxa-uart";
                         reg = <0x40700000 0x30>;
                         interrupts = <20>;
@@ -100,7 +119,7 @@
                         status = "disabled";
                 };
 
-                hwuart: uart@41100000 {
+                hwuart: serial@41100000 {
                         compatible = "mrvl,pxa-uart";
                         reg = <0x41100000 0x30>;
                         interrupts = <7>;
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 4a99c9255104..48c3cf427610 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -1611,10 +1611,11 @@
                         clocks = <&rpmcc RPM_QDSS_CLK>;
                         clock-names = "apb_pclk";
 
-                        port {
-                                etb_in: endpoint {
-                                        slave-mode;
-                                        remote-endpoint = <&replicator_out0>;
+                        in-ports {
+                                port {
+                                        etb_in: endpoint {
+                                                remote-endpoint = <&replicator_out0>;
+                                        };
                                 };
                         };
                 };
@@ -1626,10 +1627,11 @@
                         clocks = <&rpmcc RPM_QDSS_CLK>;
                         clock-names = "apb_pclk";
 
-                        port {
-                                tpiu_in: endpoint {
-                                        slave-mode;
-                                        remote-endpoint = <&replicator_out1>;
+                        in-ports {
+                                port {
+                                        tpiu_in: endpoint {
+                                                remote-endpoint = <&replicator_out1>;
+                                        };
                                 };
                         };
                 };
@@ -1640,7 +1642,7 @@
                         clocks = <&rpmcc RPM_QDSS_CLK>;
                         clock-names = "apb_pclk";
 
-                        ports {
+                        out-ports {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
 
@@ -1656,10 +1658,11 @@
                                                 remote-endpoint = <&tpiu_in>;
                                         };
                                 };
-                                port@2 {
-                                        reg = <0>;
+                        };
+
+                        in-ports {
+                                port {
                                         replicator_in: endpoint {
-                                                slave-mode;
                                                 remote-endpoint = <&funnel_out>;
                                         };
                                 };
@@ -1673,7 +1676,7 @@
                         clocks = <&rpmcc RPM_QDSS_CLK>;
                         clock-names = "apb_pclk";
 
-                        ports {
+                        in-ports {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
 
@@ -1687,33 +1690,31 @@
                                 port@0 {
                                         reg = <0>;
                                         funnel_in0: endpoint {
-                                                slave-mode;
                                                 remote-endpoint = <&etm0_out>;
                                         };
                                 };
                                 port@1 {
                                         reg = <1>;
                                         funnel_in1: endpoint {
-                                                slave-mode;
                                                 remote-endpoint = <&etm1_out>;
                                         };
                                 };
                                 port@4 {
                                         reg = <4>;
                                         funnel_in4: endpoint {
-                                                slave-mode;
                                                 remote-endpoint = <&etm2_out>;
                                         };
                                 };
                                 port@5 {
                                         reg = <5>;
                                         funnel_in5: endpoint {
-                                                slave-mode;
                                                 remote-endpoint = <&etm3_out>;
                                         };
                                 };
-                                port@8 {
-                                        reg = <0>;
+                        };
+
+                        out-ports {
+                                port {
                                         funnel_out: endpoint {
                                                 remote-endpoint = <&replicator_in>;
                                         };
@@ -1730,9 +1731,11 @@
 
                         cpu = <&CPU0>;
 
-                        port {
-                                etm0_out: endpoint {
-                                        remote-endpoint = <&funnel_in0>;
+                        out-ports {
+                                port {
+                                        etm0_out: endpoint {
+                                                remote-endpoint = <&funnel_in0>;
+                                        };
                                 };
                         };
                 };
@@ -1746,9 +1749,11 @@
 
                         cpu = <&CPU1>;
 
-                        port {
-                                etm1_out: endpoint {
-                                        remote-endpoint = <&funnel_in1>;
+                        out-ports {
+                                port {
+                                        etm1_out: endpoint {
+                                                remote-endpoint = <&funnel_in1>;
+                                        };
                                 };
                         };
                 };
@@ -1762,9 +1767,11 @@
 
                         cpu = <&CPU2>;
 
-                        port {
-                                etm2_out: endpoint {
-                                        remote-endpoint = <&funnel_in4>;
+                        out-ports {
+                                port {
+                                        etm2_out: endpoint {
+                                                remote-endpoint = <&funnel_in4>;
+                                        };
                                 };
                         };
                 };
@@ -1778,9 +1785,11 @@
 
                         cpu = <&CPU3>;
 
-                        port {
-                                etm3_out: endpoint {
-                                        remote-endpoint = <&funnel_in5>;
+                        out-ports {
+                                port {
+                                        etm3_out: endpoint {
+                                                remote-endpoint = <&funnel_in5>;
+                                        };
                                 };
                         };
                 };
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 78db67337ed4..2d56008d8d6b 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -52,78 +52,85 @@
                 cpu@0 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a7";
-                        enable-method = "qcom,kpss-acc-v1";
+                        enable-method = "qcom,kpss-acc-v2";
+                        next-level-cache = <&L2>;
                         qcom,acc = <&acc0>;
                         qcom,saw = <&saw0>;
                         reg = <0x0>;
                         clocks = <&gcc GCC_APPS_CLK_SRC>;
                         clock-frequency = <0>;
-                        operating-points = <
-                                /* kHz  uV (fixed) */
-                                48000   1100000
-                                200000  1100000
-                                500000  1100000
-                                716000  1100000
-                        >;
                         clock-latency = <256000>;
+                        operating-points-v2 = <&cpu0_opp_table>;
                 };
 
                 cpu@1 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a7";
-                        enable-method = "qcom,kpss-acc-v1";
+                        enable-method = "qcom,kpss-acc-v2";
+                        next-level-cache = <&L2>;
                         qcom,acc = <&acc1>;
                         qcom,saw = <&saw1>;
                         reg = <0x1>;
                         clocks = <&gcc GCC_APPS_CLK_SRC>;
                         clock-frequency = <0>;
-                        operating-points = <
-                                /* kHz  uV (fixed) */
-                                48000   1100000
-                                200000  1100000
-                                500000  1100000
-                                666000  1100000
-                        >;
                         clock-latency = <256000>;
+                        operating-points-v2 = <&cpu0_opp_table>;
                 };
 
                 cpu@2 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a7";
-                        enable-method = "qcom,kpss-acc-v1";
+                        enable-method = "qcom,kpss-acc-v2";
+                        next-level-cache = <&L2>;
                         qcom,acc = <&acc2>;
                         qcom,saw = <&saw2>;
                         reg = <0x2>;
                         clocks = <&gcc GCC_APPS_CLK_SRC>;
                         clock-frequency = <0>;
-                        operating-points = <
-                                /* kHz  uV (fixed) */
-                                48000   1100000
-                                200000  1100000
-                                500000  1100000
-                                666000  1100000
-                        >;
                         clock-latency = <256000>;
+                        operating-points-v2 = <&cpu0_opp_table>;
                 };
 
                 cpu@3 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a7";
-                        enable-method = "qcom,kpss-acc-v1";
+                        enable-method = "qcom,kpss-acc-v2";
+                        next-level-cache = <&L2>;
                         qcom,acc = <&acc3>;
                         qcom,saw = <&saw3>;
                         reg = <0x3>;
                         clocks = <&gcc GCC_APPS_CLK_SRC>;
                         clock-frequency = <0>;
-                        operating-points = <
-                                /* kHz  uV (fixed) */
-                                48000   1100000
-                                200000  1100000
-                                500000  1100000
-                                666000  1100000
-                        >;
                         clock-latency = <256000>;
+                        operating-points-v2 = <&cpu0_opp_table>;
                 };
+
+                L2: l2-cache {
+                        compatible = "cache";
+                        cache-level = <2>;
+                };
+        };
+
+        cpu0_opp_table: opp_table0 {
+                compatible = "operating-points-v2";
+                opp-shared;
+
+                opp-48000000 {
+                        opp-hz = /bits/ 64 <48000000>;
+                        clock-latency-ns = <256000>;
+                };
+                opp-200000000 {
+                        opp-hz = /bits/ 64 <200000000>;
+                        clock-latency-ns = <256000>;
+                };
+                opp-500000000 {
+                        opp-hz = /bits/ 64 <500000000>;
+                        clock-latency-ns = <256000>;
+                };
+                opp-716000000 {
+                        opp-hz = /bits/ 64 <716000000>;
+                        clock-latency-ns = <256000>;
+                };
         };
 
         pmu {
@@ -291,49 +298,49 @@
                         status = "disabled";
                 };
 
-                acc0: clock-controller@b088000 {
-                        compatible = "qcom,kpss-acc-v1";
-                        reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
-                };
+                acc0: clock-controller@b088000 {
+                        compatible = "qcom,kpss-acc-v2";
+                        reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
+                };
 
-                acc1: clock-controller@b098000 {
-                        compatible = "qcom,kpss-acc-v1";
-                        reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
-                };
+                acc1: clock-controller@b098000 {
+                        compatible = "qcom,kpss-acc-v2";
+                        reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
+                };
 
-                acc2: clock-controller@b0a8000 {
-                        compatible = "qcom,kpss-acc-v1";
-                        reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
-                };
+                acc2: clock-controller@b0a8000 {
+                        compatible = "qcom,kpss-acc-v2";
+                        reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
+                };
 
-                acc3: clock-controller@b0b8000 {
-                        compatible = "qcom,kpss-acc-v1";
-                        reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
-                };
+                acc3: clock-controller@b0b8000 {
+                        compatible = "qcom,kpss-acc-v2";
+                        reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
+                };
 
-                saw0: regulator@b089000 {
-                        compatible = "qcom,saw2";
-                        reg = <0x02089000 0x1000>, <0x0b009000 0x1000>;
+                saw0: regulator@b089000 {
+                        compatible = "qcom,saw2";
+                        reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>;
                         regulator;
-                };
+                };
 
-                saw1: regulator@b099000 {
-                        compatible = "qcom,saw2";
-                        reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
-                        regulator;
-                };
+                saw1: regulator@b099000 {
+                        compatible = "qcom,saw2";
+                        reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
+                        regulator;
+                };
 
-                saw2: regulator@b0a9000 {
-                        compatible = "qcom,saw2";
-                        reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
-                        regulator;
-                };
+                saw2: regulator@b0a9000 {
+                        compatible = "qcom,saw2";
+                        reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
+                        regulator;
+                };
 
-                saw3: regulator@b0b9000 {
-                        compatible = "qcom,saw2";
-                        reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
-                        regulator;
-                };
+                saw3: regulator@b0b9000 {
+                        compatible = "qcom,saw2";
+                        reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
+                        regulator;
+                };
 
                 blsp1_uart1: serial@78af000 {
                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
@@ -387,7 +394,7 @@
                         #size-cells = <2>;
 
                         ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
-                                  0x82000000 0 0x48000000 0x48000000 0 0x10000000>;
+                                  0x82000000 0 0x40300000 0x40300000 0 0x400000>;
 
                         interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
                         interrupt-names = "msi";
diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
index bcf53e37ed93..554c65e7aa0e 100644
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
@@ -2,26 +2,8 @@
 #include "qcom-ipq8064-v1.0.dtsi"
 
 / {
-        model = "Qualcomm IPQ8064/AP148";
-        compatible = "qcom,ipq8064-ap148", "qcom,ipq8064";
-
-        aliases {
-                serial0 = &gsbi4_serial;
-        };
-
-        chosen {
-                stdout-path = "serial0:115200n8";
-        };
-
-        reserved-memory {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges;
-                rsvd@41200000 {
-                        reg = <0x41200000 0x300000>;
-                        no-map;
-                };
-        };
+        model = "Qualcomm Technologies, Inc. IPQ8064/AP-148";
+        compatible = "qcom,ipq8064-ap148";
 
         soc {
                 pinmux@800000 {
@@ -31,73 +13,22 @@
                                 bias-disable;
                         };
 
-                        spi_pins: spi_pins {
+                        buttons_pins: buttons_pins {
                                 mux {
-                                        pins = "gpio18", "gpio19", "gpio21";
-                                        function = "gsbi5";
-                                        drive-strength = <10>;
-                                        bias-none;
+                                        pins = "gpio54", "gpio65";
+                                        drive-strength = <2>;
+                                        bias-pull-up;
                                 };
                         };
                 };
 
                 gsbi@16300000 {
-                        qcom,mode = <GSBI_PROT_I2C_UART>;
-                        status = "ok";
-                        serial@16340000 {
+                        i2c@16380000 {
                                 status = "ok";
-                        };
-
-                        i2c4: i2c@16380000 {
-                                status = "ok";
-
                                 clock-frequency = <200000>;
-
                                 pinctrl-0 = <&i2c4_pins>;
                                 pinctrl-names = "default";
                         };
                 };
-
-                gsbi5: gsbi@1a200000 {
-                        qcom,mode = <GSBI_PROT_SPI>;
-                        status = "ok";
-
-                        spi4: spi@1a280000 {
-                                status = "ok";
-                                spi-max-frequency = <50000000>;
-
-                                pinctrl-0 = <&spi_pins>;
-                                pinctrl-names = "default";
-
-                                cs-gpios = <&qcom_pinmux 20 0>;
-
-                                flash: m25p80@0 {
-                                        compatible = "s25fl256s1";
-                                        #address-cells = <1>;
-                                        #size-cells = <1>;
-                                        spi-max-frequency = <50000000>;
-                                        reg = <0>;
-
-                                        partition@0 {
-                                                label = "rootfs";
-                                                reg = <0x0 0x1000000>;
-                                        };
-
-                                        partition@1 {
-                                                label = "scratch";
-                                                reg = <0x1000000 0x1000000>;
-                                        };
-                                };
-                        };
-                };
-
-                sata-phy@1b400000 {
-                        status = "ok";
-                };
-
-                sata@29000000 {
-                        ports-implemented = <0x1>;
-                        status = "ok";
-                };
         };
 };
diff --git a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
index e1181194e8d3..e239a0486936 100644
--- a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
@@ -1,2 +1,127 @@
 // SPDX-License-Identifier: GPL-2.0
 #include "qcom-ipq8064.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+        model = "Qualcomm Technologies, Inc. IPQ8064-v1.0";
+
+        aliases {
+                serial0 = &gsbi4_serial;
+        };
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+
+        soc {
+                gsbi@16300000 {
+                        qcom,mode = <GSBI_PROT_I2C_UART>;
+                        status = "ok";
+
+                        serial@16340000 {
+                                status = "ok";
+                        };
+                };
+
+                gsbi5: gsbi@1a200000 {
+                        qcom,mode = <GSBI_PROT_SPI>;
+                        status = "ok";
+
+                        spi4: spi@1a280000 {
+                                status = "ok";
+                                spi-max-frequency = <50000000>;
+
+                                pinctrl-0 = <&spi_pins>;
+                                pinctrl-names = "default";
+
+                                cs-gpios = <&qcom_pinmux 20 0>;
+
+                                flash: m25p80@0 {
+                                        compatible = "s25fl256s1";
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        spi-max-frequency = <50000000>;
+                                        reg = <0>;
+
+                                        partition@0 {
+                                                label = "rootfs";
+                                                reg = <0x0 0x1000000>;
+                                        };
+
+                                        partition@1 {
+                                                label = "scratch";
+                                                reg = <0x1000000 0x1000000>;
+                                        };
+                                };
+                        };
+                };
+
+                sata-phy@1b400000 {
+                        status = "ok";
+                };
+
+                sata@29000000 {
+                        ports-implemented = <0x1>;
+                        status = "ok";
+                };
+
+                gpio_keys {
+                        compatible = "gpio-keys";
+                        pinctrl-0 = <&buttons_pins>;
+                        pinctrl-names = "default";
+
+                        button@1 {
+                                label = "reset";
+                                linux,code = <KEY_RESTART>;
+                                gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
+                                linux,input-type = <1>;
+                                debounce-interval = <60>;
+                        };
+                        button@2 {
+                                label = "wps";
+                                linux,code = <KEY_WPS_BUTTON>;
+                                gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
+                                linux,input-type = <1>;
+                                debounce-interval = <60>;
+                        };
+                };
+
+                leds {
+                        compatible = "gpio-leds";
+                        pinctrl-0 = <&leds_pins>;
+                        pinctrl-names = "default";
+
+                        led@7 {
+                                label = "led_usb1";
+                                gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
+                                linux,default-trigger = "usbdev";
+                                default-state = "off";
+                        };
+
+                        led@8 {
+                                label = "led_usb3";
+                                gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
+                                linux,default-trigger = "usbdev";
+                                default-state = "off";
+                        };
+
+                        led@9 {
+                                label = "status_led_fail";
+                                gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
+                                default-state = "off";
+                        };
+
+                        led@26 {
+                                label = "sata_led";
+                                gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
+                                default-state = "off";
+                        };
+
+                        led@53 {
+                                label = "status_led_pass";
+                                gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
+                                default-state = "off";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 70790ac242d1..f793cd1ad6d0 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -2,8 +2,11 @@
 /dts-v1/;
 
 #include "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
 #include <dt-bindings/soc/qcom,gsbi.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
@@ -114,6 +117,61 @@
                         interrupt-controller;
                         #interrupt-cells = <2>;
                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+
+                        pcie0_pins: pcie0_pinmux {
+                                mux {
+                                        pins = "gpio3";
+                                        function = "pcie1_rst";
+                                        drive-strength = <12>;
+                                        bias-disable;
+                                };
+                        };
+
+                        pcie1_pins: pcie1_pinmux {
+                                mux {
+                                        pins = "gpio48";
+                                        function = "pcie2_rst";
+                                        drive-strength = <12>;
+                                        bias-disable;
+                                };
+                        };
+
+                        pcie2_pins: pcie2_pinmux {
+                                mux {
+                                        pins = "gpio63";
+                                        function = "pcie3_rst";
+                                        drive-strength = <12>;
+                                        bias-disable;
+                                };
+                        };
+
+                        spi_pins: spi_pins {
+                                mux {
+                                        pins = "gpio18", "gpio19", "gpio21";
+                                        function = "gsbi5";
+                                        drive-strength = <10>;
+                                        bias-none;
+                                };
+                        };
+
+                        leds_pins: leds_pins {
+                                mux {
+                                        pins = "gpio7", "gpio8", "gpio9",
+                                               "gpio26", "gpio53";
+                                        function = "gpio";
+                                        drive-strength = <2>;
+                                        bias-pull-down;
+                                        output-low;
+                                };
+                        };
+
+                        buttons_pins: buttons_pins {
+                                mux {
+                                        pins = "gpio54";
+                                        drive-strength = <2>;
+                                        bias-pull-up;
+                                };
+                        };
                 };
 
                 intc: interrupt-controller@2000000 {
@@ -373,5 +431,233 @@
                         #reset-cells = <1>;
                 };
 
+                pcie0: pci@1b500000 {
+                        compatible = "qcom,pcie-ipq8064";
+                        reg = <0x1b500000 0x1000
+                               0x1b502000 0x80
+                               0x1b600000 0x100
+                               0x0ff00000 0x100000>;
+                        reg-names = "dbi", "elbi", "parf", "config";
+                        device_type = "pci";
+                        linux,pci-domain = <0>;
+                        bus-range = <0x00 0xff>;
+                        num-lanes = <1>;
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+
+                        ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000   /* downstream I/O */
+                                  0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
+
+                        interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "msi";
+                        #interrupt-cells = <1>;
+                        interrupt-map-mask = <0 0 0 0x7>;
+                        interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+                                        <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+                                        <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+                                        <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+                        clocks = <&gcc PCIE_A_CLK>,
+                                 <&gcc PCIE_H_CLK>,
+                                 <&gcc PCIE_PHY_CLK>,
+                                 <&gcc PCIE_AUX_CLK>,
+                                 <&gcc PCIE_ALT_REF_CLK>;
+                        clock-names = "core", "iface", "phy", "aux", "ref";
+
+                        assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
+                        assigned-clock-rates = <100000000>;
+
+                        resets = <&gcc PCIE_ACLK_RESET>,
+                                 <&gcc PCIE_HCLK_RESET>,
+                                 <&gcc PCIE_POR_RESET>,
+                                 <&gcc PCIE_PCI_RESET>,
+                                 <&gcc PCIE_PHY_RESET>,
+                                 <&gcc PCIE_EXT_RESET>;
+                        reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
+
+                        pinctrl-0 = <&pcie0_pins>;
+                        pinctrl-names = "default";
+
+                        status = "disabled";
+                        perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
+                };
+
+                pcie1: pci@1b700000 {
+                        compatible = "qcom,pcie-ipq8064";
+                        reg = <0x1b700000 0x1000
+                               0x1b702000 0x80
+                               0x1b800000 0x100
+                               0x31f00000 0x100000>;
+                        reg-names = "dbi", "elbi", "parf", "config";
+                        device_type = "pci";
+                        linux,pci-domain = <1>;
+                        bus-range = <0x00 0xff>;
+                        num-lanes = <1>;
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+
+                        ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000   /* downstream I/O */
+                                  0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
+
+                        interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "msi";
+                        #interrupt-cells = <1>;
+                        interrupt-map-mask = <0 0 0 0x7>;
+                        interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+                                        <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+                                        <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+                                        <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+                        clocks = <&gcc PCIE_1_A_CLK>,
+                                 <&gcc PCIE_1_H_CLK>,
+                                 <&gcc PCIE_1_PHY_CLK>,
+                                 <&gcc PCIE_1_AUX_CLK>,
+                                 <&gcc PCIE_1_ALT_REF_CLK>;
+                        clock-names = "core", "iface", "phy", "aux", "ref";
+
+                        assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
+                        assigned-clock-rates = <100000000>;
+
+                        resets = <&gcc PCIE_1_ACLK_RESET>,
+                                 <&gcc PCIE_1_HCLK_RESET>,
+                                 <&gcc PCIE_1_POR_RESET>,
+                                 <&gcc PCIE_1_PCI_RESET>,
+                                 <&gcc PCIE_1_PHY_RESET>,
+                                 <&gcc PCIE_1_EXT_RESET>;
+                        reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
+
+                        pinctrl-0 = <&pcie1_pins>;
+                        pinctrl-names = "default";
+
+                        status = "disabled";
+                        perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
+                };
+
+                pcie2: pci@1b900000 {
+                        compatible = "qcom,pcie-ipq8064";
+                        reg = <0x1b900000 0x1000
+                               0x1b902000 0x80
+                               0x1ba00000 0x100
+                               0x35f00000 0x100000>;
+                        reg-names = "dbi", "elbi", "parf", "config";
+                        device_type = "pci";
+                        linux,pci-domain = <2>;
+                        bus-range = <0x00 0xff>;
+                        num-lanes = <1>;
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+
+                        ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000   /* downstream I/O */
+                                  0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
+
+                        interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "msi";
+                        #interrupt-cells = <1>;
+                        interrupt-map-mask = <0 0 0 0x7>;
+                        interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+                                        <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+                                        <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+                                        <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+                        clocks = <&gcc PCIE_2_A_CLK>,
+                                 <&gcc PCIE_2_H_CLK>,
+                                 <&gcc PCIE_2_PHY_CLK>,
+                                 <&gcc PCIE_2_AUX_CLK>,
+                                 <&gcc PCIE_2_ALT_REF_CLK>;
+                        clock-names = "core", "iface", "phy", "aux", "ref";
+
+                        assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
+                        assigned-clock-rates = <100000000>;
+
+                        resets = <&gcc PCIE_2_ACLK_RESET>,
+                                 <&gcc PCIE_2_HCLK_RESET>,
+                                 <&gcc PCIE_2_POR_RESET>,
+                                 <&gcc PCIE_2_PCI_RESET>,
+                                 <&gcc PCIE_2_PHY_RESET>,
+                                 <&gcc PCIE_2_EXT_RESET>;
+                        reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
+
+                        pinctrl-0 = <&pcie2_pins>;
+                        pinctrl-names = "default";
+
+                        status = "disabled";
+                        perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
+                };
+
+                vsdcc_fixed: vsdcc-regulator {
+                        compatible = "regulator-fixed";
+                        regulator-name = "SDCC Power";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
+
+                sdcc1bam:dma@12402000 {
+                        compatible = "qcom,bam-v1.3.0";
+                        reg = <0x12402000 0x8000>;
+                        interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&gcc SDC1_H_CLK>;
+                        clock-names = "bam_clk";
+                        #dma-cells = <1>;
+                        qcom,ee = <0>;
+                };
+
+                sdcc3bam:dma@12182000 {
+                        compatible = "qcom,bam-v1.3.0";
+                        reg = <0x12182000 0x8000>;
+                        interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&gcc SDC3_H_CLK>;
+                        clock-names = "bam_clk";
+                        #dma-cells = <1>;
+                        qcom,ee = <0>;
+                };
+
+                amba {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        sdcc@12400000 {
+                                status          = "disabled";
+                                compatible      = "arm,pl18x", "arm,primecell";
+                                arm,primecell-periphid = <0x00051180>;
+                                reg             = <0x12400000 0x2000>;
+                                interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-names = "cmd_irq";
+                                clocks          = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
+                                clock-names     = "mclk", "apb_pclk";
+                                bus-width       = <8>;
+                                max-frequency   = <96000000>;
+                                non-removable;
+                                cap-sd-highspeed;
+                                cap-mmc-highspeed;
+                                mmc-ddr-1_8v;
+                                vmmc-supply = <&vsdcc_fixed>;
+                                dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
+                                dma-names = "tx", "rx";
+                        };
+
+                        sdcc@12180000 {
+                                compatible      = "arm,pl18x", "arm,primecell";
+                                arm,primecell-periphid = <0x00051180>;
+                                status          = "disabled";
+                                reg             = <0x12180000 0x2000>;
+                                interrupts      = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-names = "cmd_irq";
+                                clocks          = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
+                                clock-names     = "mclk", "apb_pclk";
+                                bus-width       = <8>;
+                                cap-sd-highspeed;
+                                cap-mmc-highspeed;
+                                max-frequency   = <192000000>;
+                                #mmc-ddr-1_8v;
+                                sd-uhs-sdr104;
+                                sd-uhs-ddr50;
+                                vqmmc-supply = <&vsdcc_fixed>;
+                                dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
+                                dma-names = "tx", "rx";
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts
index c2dc9d09484a..ed8f064d0895 100644
--- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts
+++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts
@@ -241,6 +241,33 @@
                                 bias-pull-up;
                         };
                 };
+
+                i2c3_pins: i2c3 {
+                        mux {
+                                pins = "gpio10", "gpio11";
+                                function = "blsp_i2c3";
+                                drive-strength = <2>;
+                                bias-disable;
+                        };
+                };
+
+                i2c12_pins: i2c12 {
+                        mux {
+                                pins = "gpio87", "gpio88";
+                                function = "blsp_i2c12";
+                                drive-strength = <2>;
+                                bias-disable;
+                        };
+                };
+
+                mpu6515_pin: mpu6515 {
+                        irq {
+                                pins = "gpio73";
+                                function = "gpio";
+                                bias-disable;
+                                input-enable;
+                        };
+                };
         };
 
         sdhci@f9824900 {
@@ -277,6 +304,62 @@
                         linux,code = <KEY_VOLUMEDOWN>;
                 };
         };
+
+        i2c@f9968000 {
+                status = "ok";
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c12_pins>;
+                clock-frequency = <100000>;
+                qcom,src-freq = <50000000>;
+
+                mpu6515@68 {
+                        compatible = "invensense,mpu6515";
+                        reg = <0x68>;
+                        interrupts-extended = <&msmgpio 73 IRQ_TYPE_EDGE_FALLING>;
+                        vddio-supply = <&pm8941_lvs1>;
+
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mpu6515_pin>;
+
+                        i2c-gate {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                ak8963@f {
+                                        compatible = "asahi-kasei,ak8963";
+                                        reg = <0x0f>;
+                                        // Currently only works in polling mode.
+                                        // gpios = <&msmgpio 61 0>;
+                                        vid-supply = <&pm8941_lvs1>;
+                                        vdd-supply = <&pm8941_l17>;
+                                };
+
+                                bmp280@76 {
+                                        compatible = "bosch,bmp280";
+                                        reg = <0x76>;
+                                        vdda-supply = <&pm8941_lvs1>;
+                                        vddd-supply = <&pm8941_l17>;
+                                };
+                        };
+                };
+        };
+
+        i2c@f9925000 {
+                status = "ok";
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c3_pins>;
+                clock-frequency = <100000>;
+                qcom,src-freq = <50000000>;
+
+                avago_apds993@39 {
+                        compatible = "avago,apds9930";
+                        reg = <0x39>;
+                        interrupts-extended = <&msmgpio 61 IRQ_TYPE_EDGE_FALLING>;
+                        vdd-supply = <&pm8941_l17>;
+                        vddio-supply = <&pm8941_lvs1>;
+                        led-max-microamp = <100000>;
+                        amstaos,proximity-diodes = <0>;
+                };
+        };
 };
 
 &spmi_bus {
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index d9019a49b292..aba159d5a95a 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -67,7 +67,7 @@
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
-                interrupts = <1 9 0xf04>;
+                interrupts = <GIC_PPI 9 0xf04>;
 
                 CPU0: cpu@0 {
                         compatible = "qcom,krait";
@@ -214,7 +214,7 @@
 
         cpu-pmu {
                 compatible = "qcom,krait-pmu";
-                interrupts = <1 7 0xf04>;
+                interrupts = <GIC_PPI 7 0xf04>;
         };
 
         clocks {
@@ -233,17 +233,17 @@
 
         timer {
                 compatible = "arm,armv7-timer";
-                interrupts = <1 2 0xf08>,
-                             <1 3 0xf08>,
-                             <1 4 0xf08>,
-                             <1 1 0xf08>;
+                interrupts = <GIC_PPI 2 0xf08>,
+                             <GIC_PPI 3 0xf08>,
+                             <GIC_PPI 4 0xf08>,
+                             <GIC_PPI 1 0xf08>;
                 clock-frequency = <19200000>;
         };
 
         adsp-pil {
                 compatible = "qcom,msm8974-adsp-pil";
 
-                interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
+                interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
                                       <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
                                       <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
                                       <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
@@ -275,7 +275,7 @@
                 qcom,smem = <443>, <429>;
 
                 interrupt-parent = <&intc>;
-                interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
+                interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 
                 qcom,ipc = <&apcs 8 10>;
 
@@ -300,7 +300,7 @@
                 qcom,smem = <435>, <428>;
 
                 interrupt-parent = <&intc>;
-                interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
+                interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
 
                 qcom,ipc = <&apcs 8 14>;
 
@@ -325,7 +325,7 @@
                 qcom,smem = <451>, <431>;
 
                 interrupt-parent = <&intc>;
-                interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
+                interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
 
                 qcom,ipc = <&apcs 8 18>;
 
@@ -364,7 +364,7 @@
 
                 modem_smsm: modem@1 {
                         reg = <1>;
-                        interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
+                        interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
 
                         interrupt-controller;
                         #interrupt-cells = <2>;
@@ -372,7 +372,7 @@
 
                 adsp_smsm: adsp@2 {
                         reg = <2>;
-                        interrupts = <0 157 IRQ_TYPE_EDGE_RISING>;
+                        interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
 
                         interrupt-controller;
                         #interrupt-cells = <2>;
@@ -380,7 +380,7 @@
 
                 wcnss_smsm: wcnss@7 {
                         reg = <7>;
-                        interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
+                        interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
 
                         interrupt-controller;
                         #interrupt-cells = <2>;
@@ -445,50 +445,50 @@
 
                         frame@f9021000 {
                                 frame-number = <0>;
-                                interrupts = <0 8 0x4>,
-                                             <0 7 0x4>;
+                                interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+                                             <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
                                 reg = <0xf9021000 0x1000>,
                                       <0xf9022000 0x1000>;
                         };
 
                         frame@f9023000 {
                                 frame-number = <1>;
-                                interrupts = <0 9 0x4>;
+                                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
                                 reg = <0xf9023000 0x1000>;
                                 status = "disabled";
                         };
 
                         frame@f9024000 {
                                 frame-number = <2>;
-                                interrupts = <0 10 0x4>;
+                                interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
                                 reg = <0xf9024000 0x1000>;
                                 status = "disabled";
                         };
 
                         frame@f9025000 {
                                 frame-number = <3>;
-                                interrupts = <0 11 0x4>;
+                                interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
                                 reg = <0xf9025000 0x1000>;
                                 status = "disabled";
                         };
 
                         frame@f9026000 {
                                 frame-number = <4>;
-                                interrupts = <0 12 0x4>;
+                                interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
                                 reg = <0xf9026000 0x1000>;
                                 status = "disabled";
                         };
 
                         frame@f9027000 {
                                 frame-number = <5>;
-                                interrupts = <0 13 0x4>;
+                                interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
                                 reg = <0xf9027000 0x1000>;
                                 status = "disabled";
                         };
 
                         frame@f9028000 {
                                 frame-number = <6>;
-                                interrupts = <0 14 0x4>;
+                                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
                                 reg = <0xf9028000 0x1000>;
                                 status = "disabled";
                         };
@@ -586,7 +586,7 @@
                 blsp1_uart1: serial@f991d000 {
                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
                         reg = <0xf991d000 0x1000>;
-                        interrupts = <0 107 0x0>;
+                        interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
                         clock-names = "core", "iface";
                         status = "disabled";
@@ -595,7 +595,7 @@
                 blsp1_uart2: serial@f991e000 {
                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
                         reg = <0xf991e000 0x1000>;
-                        interrupts = <0 108 0x0>;
+                        interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
                         clock-names = "core", "iface";
                         status = "disabled";
@@ -605,7 +605,8 @@
                         compatible = "qcom,sdhci-msm-v4";
                         reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
                         reg-names = "hc_mem", "core_mem";
-                        interrupts = <0 123 0>, <0 138 0>;
+                        interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-names = "hc_irq", "pwr_irq";
                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
                                  <&gcc GCC_SDCC1_AHB_CLK>,
@@ -618,8 +619,8 @@
                         compatible = "qcom,sdhci-msm-v4";
                         reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
                         reg-names = "hc_mem", "core_mem";
-                        interrupts = <GIC_SPI 127 IRQ_TYPE_NONE>,
-                                     <GIC_SPI 224 IRQ_TYPE_NONE>;
+                        interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-names = "hc_irq", "pwr_irq";
                         clocks = <&gcc GCC_SDCC3_APPS_CLK>,
                                  <&gcc GCC_SDCC3_AHB_CLK>,
@@ -632,7 +633,8 @@
                         compatible = "qcom,sdhci-msm-v4";
                         reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
                         reg-names = "hc_mem", "core_mem";
-                        interrupts = <0 125 0>, <0 221 0>;
+                        interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-names = "hc_irq", "pwr_irq";
                         clocks = <&gcc GCC_SDCC2_APPS_CLK>,
                                  <&gcc GCC_SDCC2_AHB_CLK>,
@@ -699,25 +701,36 @@
                         #gpio-cells = <2>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
-                        interrupts = <0 208 0>;
+                        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
                 };
 
                 i2c@f9924000 {
                         status = "disabled";
                         compatible = "qcom,i2c-qup-v2.1.1";
                         reg = <0xf9924000 0x1000>;
-                        interrupts = <0 96 IRQ_TYPE_NONE>;
+                        interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
                         clock-names = "core", "iface";
                         #address-cells = <1>;
                         #size-cells = <0>;
                 };
 
+                blsp_i2c3: i2c@f9925000 {
+                        status = "disabled";
+                        compatible = "qcom,i2c-qup-v2.1.1";
+                        reg = <0xf9925000 0x1000>;
+                        interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+                        clock-names = "core", "iface";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+
                 blsp_i2c8: i2c@f9964000 {
                         status = "disabled";
                         compatible = "qcom,i2c-qup-v2.1.1";
                         reg = <0xf9964000 0x1000>;
-                        interrupts = <0 102 IRQ_TYPE_NONE>;
+                        interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
                         clock-names = "core", "iface";
                         #address-cells = <1>;
@@ -728,7 +741,7 @@
                         status = "disabled";
                         compatible = "qcom,i2c-qup-v2.1.1";
                         reg = <0xf9967000 0x1000>;
-                        interrupts = <0 105 IRQ_TYPE_NONE>;
+                        interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
                         clock-names = "core", "iface";
                         #address-cells = <1>;
@@ -737,6 +750,17 @@
                         dma-names = "tx", "rx";
                 };
 
+                blsp_i2c12: i2c@f9968000 {
+                        status = "disabled";
+                        compatible = "qcom,i2c-qup-v2.1.1";
+                        reg = <0xf9968000 0x1000>;
+                        interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
+                        clock-names = "core", "iface";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+
                 spmi_bus: spmi@fc4cf000 {
                         compatible = "qcom,spmi-pmic-arb";
                         reg-names = "core", "intr", "cnfg";
@@ -744,7 +768,7 @@
                               <0xfc4cb000 0x1000>,
                               <0xfc4ca000 0x1000>;
                         interrupt-names = "periph_irq";
-                        interrupts = <0 190 0>;
+                        interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
                         qcom,ee = <0>;
                         qcom,channel = <0>;
                         #address-cells = <2>;
@@ -770,10 +794,11 @@
                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
                         clock-names = "apb_pclk", "atclk";
 
-                        port {
-                                etr_in: endpoint {
-                                        slave-mode;
-                                        remote-endpoint = <&replicator_out0>;
+                        in-ports {
+                                port {
+                                        etr_in: endpoint {
+                                                remote-endpoint = <&replicator_out0>;
+                                        };
                                 };
                         };
                 };
@@ -785,10 +810,11 @@
                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
                         clock-names = "apb_pclk", "atclk";
 
-                        port {
-                                tpiu_in: endpoint {
-                                         slave-mode;
-                                         remote-endpoint = <&replicator_out1>;
+                        in-ports {
+                                port {
+                                        tpiu_in: endpoint {
+                                                remote-endpoint = <&replicator_out1>;
+                                        };
                                  };
                         };
                 };
@@ -800,7 +826,7 @@
                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
                         clock-names = "apb_pclk", "atclk";
 
-                        ports {
+                        out-ports {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
 
@@ -816,10 +842,11 @@
                                                 remote-endpoint = <&tpiu_in>;
                                         };
                                 };
-                                port@2 {
-                                        reg = <0>;
+                        };
+
+                        in-ports {
+                                port {
                                         replicator_in: endpoint {
-                                                slave-mode;
                                                 remote-endpoint = <&etf_out>;
                                         };
                                 };
@@ -833,20 +860,17 @@
                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
                         clock-names = "apb_pclk", "atclk";
 
-                        ports {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-
-                                port@0 {
-                                        reg = <0>;
+                        out-ports {
+                                port {
                                         etf_out: endpoint {
                                                 remote-endpoint = <&replicator_in>;
                                         };
                                 };
-                                port@1 {
-                                        reg = <0>;
+                        };
+
+                        in-ports {
+                                port {
                                         etf_in: endpoint {
-                                                slave-mode;
                                                 remote-endpoint = <&merger_out>;
                                         };
                                 };
@@ -860,7 +884,7 @@
                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
                         clock-names = "apb_pclk", "atclk";
 
-                        ports {
+                        in-ports {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
 
@@ -873,12 +897,13 @@
                                 port@1 {
                                         reg = <1>;
                                         merger_in1: endpoint {
-                                                slave-mode;
                                                 remote-endpoint = <&funnel1_out>;
                                         };
                                 };
-                                port@8 {
-                                        reg = <0>;
+                        };
+
+                        out-ports {
+                                port {
                                         merger_out: endpoint {
                                                 remote-endpoint = <&etf_in>;
                                         };
@@ -893,7 +918,7 @@
                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
                         clock-names = "apb_pclk", "atclk";
 
-                        ports {
+                        in-ports {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
 
@@ -910,12 +935,13 @@
                                 port@5 {
                                         reg = <5>;
                                         funnel1_in5: endpoint {
-                                                slave-mode;
                                                 remote-endpoint = <&kpss_out>;
                                         };
                                 };
-                                port@8 {
-                                        reg = <0>;
+                        };
+
+                        out-ports {
+                                port {
                                         funnel1_out: endpoint {
                                                 remote-endpoint = <&merger_in1>;
                                         };
@@ -930,40 +956,38 @@
                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
                         clock-names = "apb_pclk", "atclk";
 
-                        ports {
+                        in-ports {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
 
                                 port@0 {
                                         reg = <0>;
                                         kpss_in0: endpoint {
-                                                slave-mode;
                                                 remote-endpoint = <&etm0_out>;
                                         };
                                 };
                                 port@1 {
                                         reg = <1>;
                                         kpss_in1: endpoint {
-                                                slave-mode;
                                                 remote-endpoint = <&etm1_out>;
                                         };
                                 };
                                 port@2 {
                                         reg = <2>;
                                         kpss_in2: endpoint {
-                                                slave-mode;
                                                 remote-endpoint = <&etm2_out>;
                                         };
                                 };
                                 port@3 {
                                         reg = <3>;
                                         kpss_in3: endpoint {
-                                                slave-mode;
                                                 remote-endpoint = <&etm3_out>;
                                         };
                                 };
-                                port@8 {
-                                        reg = <0>;
+                        };
+
+                        out-ports {
+                                port {
                                         kpss_out: endpoint {
                                                 remote-endpoint = <&funnel1_in5>;
                                         };
@@ -980,9 +1004,11 @@
 
                         cpu = <&CPU0>;
 
-                        port {
-                                etm0_out: endpoint {
-                                        remote-endpoint = <&kpss_in0>;
+                        out-ports {
+                                port {
+                                        etm0_out: endpoint {
+                                                remote-endpoint = <&kpss_in0>;
+                                        };
                                 };
                         };
                 };
@@ -996,9 +1022,11 @@
 
                         cpu = <&CPU1>;
 
-                        port {
-                                etm1_out: endpoint {
-                                        remote-endpoint = <&kpss_in1>;
+                        out-ports {
+                                port {
+                                        etm1_out: endpoint {
+                                                remote-endpoint = <&kpss_in1>;
+                                        };
                                 };
                         };
                 };
@@ -1012,9 +1040,11 @@
 
                         cpu = <&CPU2>;
 
-                        port {
-                                etm2_out: endpoint {
-                                        remote-endpoint = <&kpss_in2>;
+                        out-ports {
+                                port {
+                                        etm2_out: endpoint {
+                                                remote-endpoint = <&kpss_in2>;
+                                        };
                                 };
                         };
                 };
@@ -1028,9 +1058,11 @@
 
                         cpu = <&CPU3>;
 
-                        port {
-                                etm3_out: endpoint {
-                                        remote-endpoint = <&kpss_in3>;
+                        out-ports {
+                                port {
+                                        etm3_out: endpoint {
+                                                remote-endpoint = <&kpss_in3>;
+                                        };
                                 };
                         };
                 };
@@ -1040,21 +1072,21 @@
                 compatible = "qcom,smd";
 
                 adsp {
-                        interrupts = <0 156 IRQ_TYPE_EDGE_RISING>;
+                        interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
 
                         qcom,ipc = <&apcs 8 8>;
                         qcom,smd-edge = <1>;
                 };
 
                 modem {
-                        interrupts = <0 25 IRQ_TYPE_EDGE_RISING>;
+                        interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
 
                         qcom,ipc = <&apcs 8 12>;
                         qcom,smd-edge = <0>;
                 };
 
                 rpm {
-                        interrupts = <0 168 1>;
+                        interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
                         qcom,ipc = <&apcs 8 0>;
                         qcom,smd-edge = <15>;
 
diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts
index 327545119ee3..0d006aea99da 100644
--- a/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts
+++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts
@@ -14,3 +14,7 @@
         model = "iW-RainboW-G20D-Q7 RZ/G1M based plus camera daughter board";
         compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743";
 };
+
+&pciec {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
index b683db4da8b1..498e223a5f93 100644
--- a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
+++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
@@ -13,3 +13,7 @@
         model = "iWave Systems RainboW-G20D-Qseven board based on RZ/G1M";
         compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743";
 };
+
+&pciec {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
index e3585daafdd6..22da819f186b 100644
--- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
+++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
@@ -35,6 +35,8 @@
 
         phy3: ethernet-phy@3 {
                 reg = <3>;
+                interrupt-parent = <&gpio5>;
+                interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
                 micrel,led-mode = <1>;
         };
 };
@@ -43,6 +45,16 @@
         clock-frequency = <20000000>;
 };
 
+&pfc {
+        scif1_pins: scif1 {
+                groups = "scif1_data_b";
+                function = "scif1";
+        };
+};
+
 &scif1 {
+        pinctrl-0 = <&scif1_pins>;
+        pinctrl-names = "default";
+
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index 87d32d3e23de..9ec78d3d0ca8 100644
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -8,6 +8,7 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/r8a77470-cpg-mssr.h>
+#include <dt-bindings/power/r8a77470-sysc.h>
 / {
         compatible = "renesas,r8a77470";
         #address-cells = <2>;
@@ -16,6 +17,7 @@
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
+                enable-method = "renesas,apmu";
 
                 cpu0: cpu@0 {
                         device_type = "cpu";
@@ -23,16 +25,25 @@
                         reg = <0>;
                         clock-frequency = <1000000000>;
                         clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
-                        power-domains = <&sysc 5>;
+                        power-domains = <&sysc R8A77470_PD_CA7_CPU0>;
                         next-level-cache = <&L2_CA7>;
                 };
 
+                cpu1: cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <1>;
+                        clock-frequency = <1000000000>;
+                        clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
+                        power-domains = <&sysc R8A77470_PD_CA7_CPU1>;
+                        next-level-cache = <&L2_CA7>;
+                };
 
                 L2_CA7: cache-controller-0 {
                         compatible = "cache";
                         cache-unified;
                         cache-level = <2>;
-                        power-domains = <&sysc 21>;
+                        power-domains = <&sysc R8A77470_PD_CA7_SCU>;
                 };
         };
 
@@ -60,6 +71,102 @@
                 #size-cells = <2>;
                 ranges;
 
+                gpio0: gpio@e6050000 {
+                        compatible = "renesas,gpio-r8a77470",
+                                     "renesas,rcar-gen2-gpio";
+                        reg = <0 0xe6050000 0 0x50>;
+                        interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 0 23>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 912>;
+                        power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+                        resets = <&cpg 912>;
+                };
+
+                gpio1: gpio@e6051000 {
+                        compatible = "renesas,gpio-r8a77470",
+                                     "renesas,rcar-gen2-gpio";
+                        reg = <0 0xe6051000 0 0x50>;
+                        interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 32 23>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 911>;
+                        power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+                        resets = <&cpg 911>;
+                };
+
+                gpio2: gpio@e6052000 {
+                        compatible = "renesas,gpio-r8a77470",
+                                     "renesas,rcar-gen2-gpio";
+                        reg = <0 0xe6052000 0 0x50>;
+                        interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 64 32>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 910>;
+                        power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+                        resets = <&cpg 910>;
+                };
+
+                gpio3: gpio@e6053000 {
+                        compatible = "renesas,gpio-r8a77470",
+                                     "renesas,rcar-gen2-gpio";
+                        reg = <0 0xe6053000 0 0x50>;
+                        interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 96 30>;
+                        gpio-reserved-ranges = <17 10>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 909>;
+                        power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+                        resets = <&cpg 909>;
+                };
+
+                gpio4: gpio@e6054000 {
+                        compatible = "renesas,gpio-r8a77470",
+                                     "renesas,rcar-gen2-gpio";
+                        reg = <0 0xe6054000 0 0x50>;
+                        interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 128 26>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 908>;
+                        power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+                        resets = <&cpg 908>;
+                };
+
+                gpio5: gpio@e6055000 {
+                        compatible = "renesas,gpio-r8a77470",
+                                     "renesas,rcar-gen2-gpio";
+                        reg = <0 0xe6055000 0 0x50>;
+                        interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 160 32>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 907>;
+                        power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+                        resets = <&cpg 907>;
+                };
+
+                pfc: pin-controller@e6060000 {
+                        compatible = "renesas,pfc-r8a77470";
+                        reg = <0 0xe6060000 0 0x118>;
+                };
+
                 cpg: clock-controller@e6150000 {
                         compatible = "renesas,r8a77470-cpg-mssr";
                         reg = <0 0xe6150000 0 0x1000>;
@@ -70,6 +177,12 @@
                         #reset-cells = <1>;
                 };
 
+                apmu@e6151000 {
+                        compatible = "renesas,r8a77470-apmu", "renesas,apmu";
+                        reg = <0 0xe6151000 0 0x188>;
+                        cpus = <&cpu0 &cpu1>;
+                };
+
                 rst: reset-controller@e6160000 {
                         compatible = "renesas,r8a77470-rst";
                         reg = <0 0xe6160000 0 0x100>;
@@ -97,7 +210,7 @@
                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&cpg CPG_MOD 407>;
-                        power-domains = <&sysc 32>;
+                        power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
                         resets = <&cpg 407>;
                 };
 
@@ -124,6 +237,20 @@
                         reg = <0 0xe6300000 0 0x20000>;
                 };
 
+                i2c4: i2c@e6520000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a77470",
+                                     "renesas,rcar-gen2-i2c";
+                        reg = <0 0xe6520000 0 0x40>;
+                        interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 927>;
+                        power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+                        resets = <&cpg 927>;
+                        i2c-scl-internal-delay-ns = <6>;
+                        status = "disabled";
+                };
+
                 dmac0: dma-controller@e6700000 {
                         compatible = "renesas,dmac-r8a77470",
                                      "renesas,rcar-dmac";
@@ -151,7 +278,7 @@
                                           "ch12", "ch13", "ch14";
                         clocks = <&cpg CPG_MOD 219>;
                         clock-names = "fck";
-                        power-domains = <&sysc 32>;
+                        power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
                         resets = <&cpg 219>;
                         #dma-cells = <1>;
                         dma-channels = <15>;
@@ -184,7 +311,7 @@
                                           "ch12", "ch13", "ch14";
                         clocks = <&cpg CPG_MOD 218>;
                         clock-names = "fck";
-                        power-domains = <&sysc 32>;
+                        power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
                         resets = <&cpg 218>;
                         #dma-cells = <1>;
                         dma-channels = <15>;
@@ -196,7 +323,7 @@
                         reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
                         interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&cpg CPG_MOD 812>;
-                        power-domains = <&sysc 32>;
+                        power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
                         resets = <&cpg 812>;
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -214,7 +341,7 @@
                         dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
                                <&dmac1 0x29>, <&dmac1 0x2a>;
                         dma-names = "tx", "rx", "tx", "rx";
-                        power-domains = <&sysc 32>;
+                        power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
                         resets = <&cpg 721>;
                         status = "disabled";
                 };
@@ -230,7 +357,7 @@
                         dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
                                <&dmac1 0x2d>, <&dmac1 0x2e>;
                         dma-names = "tx", "rx", "tx", "rx";
-                        power-domains = <&sysc 32>;
+                        power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
                         resets = <&cpg 720>;
                         status = "disabled";
                 };
@@ -246,7 +373,7 @@
                         dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
                                <&dmac1 0x2b>, <&dmac1 0x2c>;
                         dma-names = "tx", "rx", "tx", "rx";
-                        power-domains = <&sysc 32>;
+                        power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
                         resets = <&cpg 719>;
                         status = "disabled";
                 };
@@ -262,7 +389,7 @@
                         dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
                                <&dmac1 0x2f>, <&dmac1 0x30>;
                         dma-names = "tx", "rx", "tx", "rx";
-                        power-domains = <&sysc 32>;
+                        power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
                         resets = <&cpg 718>;
                         status = "disabled";
                 };
@@ -278,7 +405,7 @@
                         dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
                                <&dmac1 0xfb>, <&dmac1 0xfc>;
                         dma-names = "tx", "rx", "tx", "rx";
-                        power-domains = <&sysc 32>;
+                        power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
                         resets = <&cpg 715>;
                         status = "disabled";
                 };
@@ -294,11 +421,26 @@
                         dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
                                <&dmac1 0xfd>, <&dmac1 0xfe>;
                         dma-names = "tx", "rx", "tx", "rx";
-                        power-domains = <&sysc 32>;
+                        power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
                         resets = <&cpg 714>;
                         status = "disabled";
                 };
 
+                sdhi2: sd@ee160000 {
+                        compatible = "renesas,sdhi-r8a77470",
+                                     "renesas,rcar-gen2-sdhi";
+                        reg = <0 0xee160000 0 0x328>;
+                        interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 312>;
+                        dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+                               <&dmac1 0xd3>, <&dmac1 0xd4>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        max-frequency = <97500000>;
+                        power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+                        resets = <&cpg 312>;
+                        status = "disabled";
+                };
+
                 gic: interrupt-controller@f1001000 {
                         compatible = "arm,gic-400";
                         #interrupt-cells = <3>;
@@ -309,7 +451,7 @@
                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
                         clocks = <&cpg CPG_MOD 408>;
                         clock-names = "clk";
-                        power-domains = <&sysc 32>;
+                        power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
                         resets = <&cpg 408>;
                 };
 
diff --git a/arch/arm/boot/dts/r8a7778-bockw.dts b/arch/arm/boot/dts/r8a7778-bockw.dts
index de808d2ea856..cecb22924ec4 100644
--- a/arch/arm/boot/dts/r8a7778-bockw.dts
+++ b/arch/arm/boot/dts/r8a7778-bockw.dts
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Reference Device Tree Source for the Bock-W board
+ * Reference Device Tree Source for the R-Car M1A (R8A77781) Bock-W board
  *
  * Copyright (C) 2013  Renesas Solutions Corp.
  * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index 1bce16cc6b20..05db0ccad7a6 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source for Renesas r8a7778
+ * Device Tree Source for the R-Car M1A (R8A77781) SoC
  *
  * Copyright (C) 2013  Renesas Solutions Corp.
  * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
index a4d0038363f0..abc14e7a4c93 100644
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source for the Marzen board
+ * Device Tree Source for the R-Car H1 (R8A77790) Marzen board
  *
  * Copyright (C) 2013 Renesas Solutions Corp.
  * Copyright (C) 2013 Simon Horman
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index 6b997bc016ee..3bc133d9489c 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source for Renesas r8a7779
+ * Device Tree Source for the R-Car H1 (R8A77790) SoC
  *
  * Copyright (C) 2013 Renesas Solutions Corp.
  * Copyright (C) 2013 Simon Horman
@@ -344,7 +344,7 @@
 
         sata: sata@fc600000 {
                 compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
-                reg = <0xfc600000 0x2000>;
+                reg = <0xfc600000 0x200000>;
                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp1_clks R8A7779_CLK_SATA>;
                 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
diff --git a/arch/arm/boot/dts/r8a7790-stout.dts b/arch/arm/boot/dts/r8a7790-stout.dts
index a13a92c26645..629da4cee1b9 100644
--- a/arch/arm/boot/dts/r8a7790-stout.dts
+++ b/arch/arm/boot/dts/r8a7790-stout.dts
@@ -318,6 +318,10 @@
                 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
                 interrupt-controller;
 
+                onkey {
+                        compatible = "dlg,da9063-onkey";
+                };
+
                 rtc {
                         compatible = "dlg,da9063-rtc";
                 };
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 0925bdca438f..5a2747758f67 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source for the r8a7790 SoC
+ * Device Tree Source for the R-Car H2 (R8A77900) SoC
  *
  * Copyright (C) 2015 Renesas Electronics Corporation
  * Copyright (C) 2013-2014 Renesas Solutions Corp.
@@ -1559,7 +1559,7 @@
                 sata0: sata@ee300000 {
                         compatible = "renesas,sata-r8a7790",
                                      "renesas,rcar-gen2-sata";
-                        reg = <0 0xee300000 0 0x2000>;
+                        reg = <0 0xee300000 0 0x200000>;
                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&cpg CPG_MOD 815>;
                         power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
@@ -1570,7 +1570,7 @@
                 sata1: sata@ee500000 {
                         compatible = "renesas,sata-r8a7790",
                                      "renesas,rcar-gen2-sata";
-                        reg = <0 0xee500000 0 0x2000>;
+                        reg = <0 0xee500000 0 0x200000>;
                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&cpg CPG_MOD 814>;
                         power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 991ac6feedd5..6f875502453c 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source for the r8a7791 SoC
+ * Device Tree Source for the R-Car M2-W (R8A77910) SoC
  *
  * Copyright (C) 2013-2015 Renesas Electronics Corporation
  * Copyright (C) 2013-2014 Renesas Solutions Corp.
@@ -1543,7 +1543,7 @@
                 sata0: sata@ee300000 {
                         compatible = "renesas,sata-r8a7791",
                                      "renesas,rcar-gen2-sata";
-                        reg = <0 0xee300000 0 0x2000>;
+                        reg = <0 0xee300000 0 0x200000>;
                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&cpg CPG_MOD 815>;
                         power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
@@ -1554,7 +1554,7 @@
                 sata1: sata@ee500000 {
                         compatible = "renesas,sata-r8a7791",
                                      "renesas,rcar-gen2-sata";
-                        reg = <0 0xee500000 0 0x2000>;
+                        reg = <0 0xee500000 0 0x200000>;
                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&cpg CPG_MOD 814>;
                         power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
index 63a978ec81cc..8e9eb4b704d3 100644
--- a/arch/arm/boot/dts/r8a7792.dtsi
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source for the r8a7792 SoC
+ * Device Tree Source for the R-Car V2H (R8A77920) SoC
  *
  * Copyright (C) 2016 Cogent Embedded Inc.
  */
@@ -829,7 +829,6 @@
                 du: display@feb00000 {
                         compatible = "renesas,du-r8a7792";
                         reg = <0 0xfeb00000 0 0x40000>;
-                        reg-names = "du";
                         interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
                                      <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&cpg CPG_MOD 724>,
diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts
index 6b2f3a4fd13d..f51601af89a2 100644
--- a/arch/arm/boot/dts/r8a7793-gose.dts
+++ b/arch/arm/boot/dts/r8a7793-gose.dts
@@ -596,6 +596,10 @@
         status = "okay";
 };
 
+&cpu0 {
+        cpu0-supply = <&vdd_dvfs>;
+};
+
 &rwdt {
         timeout-sec = <60>;
         status = "okay";
@@ -725,6 +729,18 @@
                         compatible = "dlg,da9063-watchdog";
                 };
         };
+
+        vdd_dvfs: regulator@68 {
+                compatible = "dlg,da9210";
+                reg = <0x68>;
+                interrupt-parent = <&irqc0>;
+                interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+
+                regulator-min-microvolt = <1000000>;
+                regulator-max-microvolt = <1000000>;
+                regulator-boot-on;
+                regulator-always-on;
+        };
 };
 
 &i2c4 {
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 620a570307ff..bf05110fac4e 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source for the r8a7793 SoC
+ * Device Tree Source for the R-Car M2-N (R8A77930) SoC
  *
  * Copyright (C) 2014-2015 Renesas Electronics Corporation
  */
diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts
index daec965889d3..60e91ebfa65d 100644
--- a/arch/arm/boot/dts/r8a7794-silk.dts
+++ b/arch/arm/boot/dts/r8a7794-silk.dts
@@ -405,6 +405,31 @@
         clock-frequency = <400000>;
 };
 
+&i2c7 {
+        status = "okay";
+        clock-frequency = <100000>;
+
+        pmic@58 {
+                compatible = "dlg,da9063";
+                reg = <0x58>;
+                interrupt-parent = <&gpio3>;
+                interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
+                interrupt-controller;
+
+                onkey {
+                        compatible = "dlg,da9063-onkey";
+                };
+
+                rtc {
+                        compatible = "dlg,da9063-rtc";
+                };
+
+                wdt {
+                        compatible = "dlg,da9063-watchdog";
+                };
+        };
+};
+
 &mmcif0 {
         pinctrl-0 = <&mmcif0_pins>;
         pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index ea2ca4bdaf1c..8d797d34816e 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source for the r8a7794 SoC
+ * Device Tree Source for the R-Car E2 (R8A77940) SoC
  *
  * Copyright (C) 2014 Renesas Electronics Corporation
  * Copyright (C) 2014 Ulrich Hecht
@@ -1349,7 +1349,6 @@
                 du: display@feb00000 {
                         compatible = "renesas,du-r8a7794";
                         reg = <0 0xfeb00000 0 0x40000>;
-                        reg-names = "du";
                         interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
                                      <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
index afe29c95a006..eaf94976ed6d 100644
--- a/arch/arm/boot/dts/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -7,6 +7,7 @@
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/r9a06g032-sysctrl.h>
 
 / {
         compatible = "renesas,r9a06g032";
@@ -21,14 +22,14 @@
                         device_type = "cpu";
                         compatible = "arm,cortex-a7";
                         reg = <0>;
-                        clocks = <&sysctrl 84>;
+                        clocks = <&sysctrl R9A06G032_CLK_A7MP>;
                 };
 
                 cpu@1 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a7";
                         reg = <1>;
-                        clocks = <&sysctrl 84>;
+                        clocks = <&sysctrl R9A06G032_CLK_A7MP>;
                         enable-method = "renesas,r9a06g032-smp";
                         cpu-release-addr = <0 0x4000c204>;
                 };
@@ -77,13 +78,90 @@
                 };
 
                 uart0: serial@40060000 {
-                        compatible = "snps,dw-apb-uart";
+                        compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
                         reg = <0x40060000 0x400>;
                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
                         reg-shift = <2>;
                         reg-io-width = <4>;
-                        clocks = <&sysctrl 146>;
-                        clock-names = "baudclk";
+                        clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>;
+                        clock-names = "baudclk", "apb_pclk";
+                        status = "disabled";
+                };
+
+                uart1: serial@40061000 {
+                        compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
+                        reg = <0x40061000 0x400>;
+                        interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&sysctrl R9A06G032_CLK_UART1>, <&sysctrl R9A06G032_HCLK_UART1>;
+                        clock-names = "baudclk", "apb_pclk";
+                        status = "disabled";
+                };
+
+                uart2: serial@40062000 {
+                        compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
+                        reg = <0x40062000 0x400>;
+                        interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&sysctrl R9A06G032_CLK_UART2>, <&sysctrl R9A06G032_HCLK_UART2>;
+                        clock-names = "baudclk", "apb_pclk";
+                        status = "disabled";
+                };
+
+                uart3: serial@50000000 {
+                        compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
+                        reg = <0x50000000 0x400>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>;
+                        clock-names = "baudclk", "apb_pclk";
+                        status = "disabled";
+                };
+
+                uart4: serial@50001000 {
+                        compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
+                        reg = <0x50001000 0x400>;
+                        interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>;
+                        clock-names = "baudclk", "apb_pclk";
+                        status = "disabled";
+                };
+
+                uart5: serial@50002000 {
+                        compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
+                        reg = <0x50002000 0x400>;
+                        interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>;
+                        clock-names = "baudclk", "apb_pclk";
+                        status = "disabled";
+                };
+
+                uart6: serial@50003000 {
+                        compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
+                        reg = <0x50003000 0x400>;
+                        interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>;
+                        clock-names = "baudclk", "apb_pclk";
+                        status = "disabled";
+                };
+
+                uart7: serial@50004000 {
+                        compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
+                        reg = <0x50004000 0x400>;
+                        interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>;
+                        clock-names = "baudclk", "apb_pclk";
                         status = "disabled";
                 };
 
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index 67f57200d9a0..d560fc4051c5 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -733,7 +733,7 @@
                         /* no rts / cts for uart2 */
                 };
 
-                spi {
+                spi-pins {
                         spi_txd:spi-txd {
                                 rockchip,pins = <1 29 RK_FUNC_3 &pcfg_pull_default>;
                         };
diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts
index 45fd2b302dda..4a2890618f6f 100644
--- a/arch/arm/boot/dts/rk3188-radxarock.dts
+++ b/arch/arm/boot/dts/rk3188-radxarock.dts
@@ -93,6 +93,8 @@
                 regulator-min-microvolt = <3300000>;
                 regulator-max-microvolt = <3300000>;
                 gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&sdmmc_pwr>;
                 startup-delay-us = <100000>;
                 vin-supply = <&vcc_io>;
         };
@@ -315,6 +317,12 @@
                 };
         };
 
+        sd0 {
+                sdmmc_pwr: sdmmc-pwr {
+                        rockchip,pins = <RK_GPIO3 1 RK_FUNC_GPIO &pcfg_pull_none>;
+                };
+        };
+
         usb {
                 host_vbus_drv: host-vbus-drv {
                         rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index aa123f93f181..b6f790973736 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -56,6 +56,11 @@
                 };
         };
 
+        display-subsystem {
+                compatible = "rockchip,display-subsystem";
+                ports = <&vop0_out>, <&vop1_out>;
+        };
+
         sram: sram@10080000 {
                 compatible = "mmio-sram";
                 reg = <0x10080000 0x8000>;
@@ -69,6 +74,38 @@
                 };
         };
 
+        vop0: vop@1010c000 {
+                compatible = "rockchip,rk3188-vop";
+                reg = <0x1010c000 0x1000>;
+                interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>;
+                clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+                resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
+                reset-names = "axi", "ahb", "dclk";
+                status = "disabled";
+
+                vop0_out: port {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+        };
+
+        vop1: vop@1010e000 {
+                compatible = "rockchip,rk3188-vop";
+                reg = <0x1010e000 0x1000>;
+                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>;
+                clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+                resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
+                reset-names = "axi", "ahb", "dclk";
+                status = "disabled";
+
+                vop1_out: port {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+        };
+
         timer3: timer@2000e000 {
                 compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
                 reg = <0x2000e000 0x20>;
@@ -309,6 +346,51 @@
                         };
                 };
 
+                lcdc1 {
+                        lcdc1_dclk: lcdc1-dclk {
+                                rockchip,pins = <2 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
+                        };
+
+                        lcdc1_den: lcdc1-den {
+                                rockchip,pins = <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
+                        };
+
+                        lcdc1_hsync: lcdc1-hsync {
+                                rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
+                        };
+
+                        lcdc1_vsync: lcdc1-vsync {
+                                rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_none>;
+                        };
+
+                        lcdc1_rgb24: ldcd1-rgb24 {
+                                rockchip,pins = <2 RK_PA0 RK_FUNC_1 &pcfg_pull_none>,
+                                                <2 RK_PA1 RK_FUNC_1 &pcfg_pull_none>,
+                                                <2 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,
+                                                <2 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,
+                                                <2 RK_PA4 RK_FUNC_1 &pcfg_pull_none>,
+                                                <2 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,
+                                                <2 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,
+                                                <2 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,
+                                                <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
+                                                <2 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,
+                                                <2 RK_PB2 RK_FUNC_1 &pcfg_pull_none>,
+                                                <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
+                                                <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
+                                                <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none>,
+                                                <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
+                                                <2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>,
+                                                <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>,
+                                                <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>,
+                                                <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>,
+                                                <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>,
+                                                <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>,
+                                                <2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>,
+                                                <2 RK_PC6 RK_FUNC_1 &pcfg_pull_none>,
+                                                <2 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
+                        };
+                };
+
                 pwm0 {
                         pwm0_out: pwm0-out {
                                 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
diff --git a/arch/arm/boot/dts/rk3288-tinker-s.dts b/arch/arm/boot/dts/rk3288-tinker-s.dts
new file mode 100644
index 000000000000..37093922b482
--- /dev/null
+++ b/arch/arm/boot/dts/rk3288-tinker-s.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
+ */
+
+/dts-v1/;
+
+#include "rk3288-tinker.dtsi"
+
+/ {
+        model = "Rockchip RK3288 Asus Tinker Board S";
+        compatible = "asus,rk3288-tinker-s", "rockchip,rk3288";
+};
+
+&emmc {
+        bus-width = <8>;
+        cap-mmc-highspeed;
+        disable-wp;
+        non-removable;
+        pinctrl-names = "default";
+        pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
+        max-frequency = <150000000>;
+        mmc-hs200-1_8v;
+        mmc-ddr-1_8v;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts
index ceade5962899..1e43527aa196 100644
--- a/arch/arm/boot/dts/rk3288-tinker.dts
+++ b/arch/arm/boot/dts/rk3288-tinker.dts
@@ -5,503 +5,9 @@
 
 /dts-v1/;
 
-#include "rk3288.dtsi"
-#include <dt-bindings/input/input.h>
+#include "rk3288-tinker.dtsi"
 
 / {
-        model = "Rockchip RK3288 Tinker Board";
+        model = "Rockchip RK3288 Asus Tinker Board";
         compatible = "asus,rk3288-tinker", "rockchip,rk3288";
-
-        chosen {
-                stdout-path = "serial2:115200n8";
-        };
-
-        memory {
-                reg = <0x0 0x0 0x0 0x80000000>;
-                device_type = "memory";
-        };
-
-        ext_gmac: external-gmac-clock {
-                compatible = "fixed-clock";
-                #clock-cells = <0>;
-                clock-frequency = <125000000>;
-                clock-output-names = "ext_gmac";
-        };
-
-        gpio-keys {
-                compatible = "gpio-keys";
-                #address-cells = <1>;
-                #size-cells = <0>;
-                autorepeat;
-
-                pinctrl-names = "default";
-                pinctrl-0 = <&pwrbtn>;
-
-                button@0 {
-                        gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
-                        linux,code = <KEY_POWER>;
-                        label = "GPIO Key Power";
-                        linux,input-type = <1>;
-                        wakeup-source;
-                        debounce-interval = <100>;
-                };
-        };
-
-        gpio-leds {
-                compatible = "gpio-leds";
-
-                act-led {
-                        gpios=<&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger="mmc0";
-                };
-
-                heartbeat-led {
-                        gpios=<&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger="heartbeat";
-                };
-
-                pwr-led {
-                        gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
-                        linux,default-trigger = "default-on";
-                };
-        };
-
-        sound {
-                compatible = "simple-audio-card";
-                simple-audio-card,format = "i2s";
-                simple-audio-card,name = "rockchip,tinker-codec";
-                simple-audio-card,mclk-fs = <512>;
-
-                simple-audio-card,codec {
-                        sound-dai = <&hdmi>;
-                };
-
-                simple-audio-card,cpu {
-                        sound-dai = <&i2s>;
-                };
-        };
-
-        vcc_sys: vsys-regulator {
-                compatible = "regulator-fixed";
-                regulator-name = "vcc_sys";
-                regulator-min-microvolt = <5000000>;
-                regulator-max-microvolt = <5000000>;
-                regulator-always-on;
-                regulator-boot-on;
-        };
-
-        vcc_sd: sdmmc-regulator {
-                compatible = "regulator-fixed";
-                gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
-                pinctrl-names = "default";
-                pinctrl-0 = <&sdmmc_pwr>;
-                regulator-name = "vcc_sd";
-                regulator-min-microvolt = <3300000>;
-                regulator-max-microvolt = <3300000>;
-                startup-delay-us = <100000>;
-                vin-supply = <&vcc_io>;
-        };
-};
-
-&cpu0 {
-        cpu0-supply = <&vdd_cpu>;
-};
-
-&gmac {
-        assigned-clocks = <&cru SCLK_MAC>;
-        assigned-clock-parents = <&ext_gmac>;
-        clock_in_out = "input";
-        phy-mode = "rgmii";
-        phy-supply = <&vcc33_lan>;
-        pinctrl-names = "default";
-        pinctrl-0 = <&rgmii_pins>;
-        snps,reset-gpio = <&gpio4 7 0>;
-        snps,reset-active-low;
-        snps,reset-delays-us = <0 10000 1000000>;
-        tx_delay = <0x30>;
-        rx_delay = <0x10>;
-        status = "ok";
-};
-
-&gpu {
-        mali-supply = <&vdd_gpu>;
-        status = "okay";
-};
-
-&hdmi {
-        ddc-i2c-bus = <&i2c5>;
-        status = "okay";
-};
-
-&i2c0 {
-        clock-frequency = <400000>;
-        status = "okay";
-
-        rk808: pmic@1b {
-                compatible = "rockchip,rk808";
-                reg = <0x1b>;
-                interrupt-parent = <&gpio0>;
-                interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
-                #clock-cells = <1>;
-                clock-output-names = "xin32k", "rk808-clkout2";
-                dvs-gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>,
-                                <&gpio0 12 GPIO_ACTIVE_HIGH>;
-                pinctrl-names = "default";
-                pinctrl-0 = <&pmic_int &global_pwroff &dvs_1 &dvs_2>;
-                rockchip,system-power-controller;
-                wakeup-source;
-
-                vcc1-supply = <&vcc_sys>;
-                vcc2-supply = <&vcc_sys>;
-                vcc3-supply = <&vcc_sys>;
-                vcc4-supply = <&vcc_sys>;
-                vcc6-supply = <&vcc_sys>;
-                vcc7-supply = <&vcc_sys>;
-                vcc8-supply = <&vcc_io>;
-                vcc9-supply = <&vcc_io>;
-                vcc10-supply = <&vcc_io>;
-                vcc11-supply = <&vcc_sys>;
-                vcc12-supply = <&vcc_io>;
-                vddio-supply = <&vcc_io>;
-
-                regulators {
-                        vdd_cpu: DCDC_REG1 {
-                                regulator-always-on;
-                                regulator-boot-on;
-                                regulator-min-microvolt = <750000>;
-                                regulator-max-microvolt = <1350000>;
-                                regulator-name = "vdd_arm";
-                                regulator-ramp-delay = <6000>;
-                                regulator-state-mem {
-                                        regulator-off-in-suspend;
-                                };
-                        };
-
-                        vdd_gpu: DCDC_REG2 {
-                                regulator-always-on;
-                                regulator-boot-on;
-                                regulator-min-microvolt = <850000>;
-                                regulator-max-microvolt = <1250000>;
-                                regulator-name = "vdd_gpu";
-                                regulator-ramp-delay = <6000>;
-                                regulator-state-mem {
-                                        regulator-on-in-suspend;
-                                        regulator-suspend-microvolt = <1000000>;
-                                };
-                        };
-
-                        vcc_ddr: DCDC_REG3 {
-                                regulator-always-on;
-                                regulator-boot-on;
-                                regulator-name = "vcc_ddr";
-                                regulator-state-mem {
-                                        regulator-on-in-suspend;
-                                };
-                        };
-
-                        vcc_io: DCDC_REG4 {
-                                regulator-always-on;
-                                regulator-boot-on;
-                                regulator-min-microvolt = <3300000>;
-                                regulator-max-microvolt = <3300000>;
-                                regulator-name = "vcc_io";
-                                regulator-state-mem {
-                                        regulator-on-in-suspend;
-                                        regulator-suspend-microvolt = <3300000>;
-                                };
-                        };
-
-                        vcc18_ldo1: LDO_REG1 {
-                                regulator-always-on;
-                                regulator-boot-on;
-                                regulator-min-microvolt = <1800000>;
-                                regulator-max-microvolt = <1800000>;
-                                regulator-name = "vcc18_ldo1";
-                                regulator-state-mem {
-                                        regulator-on-in-suspend;
-                                        regulator-suspend-microvolt = <1800000>;
-                                };
-                        };
-
-                        vcc33_mipi: LDO_REG2 {
-                                regulator-always-on;
-                                regulator-boot-on;
-                                regulator-min-microvolt = <3300000>;
-                                regulator-max-microvolt = <3300000>;
-                                regulator-name = "vcc33_mipi";
-                                regulator-state-mem {
-                                        regulator-off-in-suspend;
-                                };
-                        };
-
-                        vdd_10: LDO_REG3 {
-                                regulator-always-on;
-                                regulator-boot-on;
-                                regulator-min-microvolt = <1000000>;
-                                regulator-max-microvolt = <1000000>;
-                                regulator-name = "vdd_10";
-                                regulator-state-mem {
-                                        regulator-on-in-suspend;
-                                        regulator-suspend-microvolt = <1000000>;
-                                };
-                        };
-
-                        vcc18_codec: LDO_REG4 {
-                                regulator-always-on;
-                                regulator-boot-on;
-                                regulator-min-microvolt = <1800000>;
-                                regulator-max-microvolt = <1800000>;
-                                regulator-name = "vcc18_codec";
-                                regulator-state-mem {
-                                        regulator-on-in-suspend;
-                                        regulator-suspend-microvolt = <1800000>;
-                                };
-                        };
-
-                        vccio_sd: LDO_REG5 {
-                                regulator-min-microvolt = <1800000>;
-                                regulator-max-microvolt = <3300000>;
-                                regulator-name = "vccio_sd";
-                                regulator-state-mem {
-                                        regulator-on-in-suspend;
-                                        regulator-suspend-microvolt = <3300000>;
-                                };
-                        };
-
-                        vdd10_lcd: LDO_REG6 {
-                                regulator-always-on;
-                                regulator-boot-on;
-                                regulator-min-microvolt = <1000000>;
-                                regulator-max-microvolt = <1000000>;
-                                regulator-name = "vdd10_lcd";
-                                regulator-state-mem {
-                                        regulator-on-in-suspend;
-                                        regulator-suspend-microvolt = <1000000>;
-                                };
-                        };
-
-                        vcc_18: LDO_REG7 {
-                                regulator-always-on;
-                                regulator-boot-on;
-                                regulator-min-microvolt = <1800000>;
-                                regulator-max-microvolt = <1800000>;
-                                regulator-name = "vcc_18";
-                                regulator-state-mem {
-                                        regulator-on-in-suspend;
-                                        regulator-suspend-microvolt = <1800000>;
-                                };
-                        };
-
-                        vcc18_lcd: LDO_REG8 {
-                                regulator-always-on;
-                                regulator-boot-on;
-                                regulator-min-microvolt = <1800000>;
-                                regulator-max-microvolt = <1800000>;
-                                regulator-name = "vcc18_lcd";
-                                regulator-state-mem {
-                                        regulator-on-in-suspend;
-                                        regulator-suspend-microvolt = <1800000>;
-                                };
-                        };
-
-                        vcc33_sd: SWITCH_REG1 {
-                                regulator-always-on;
-                                regulator-boot-on;
-                                regulator-name = "vcc33_sd";
-                                regulator-state-mem {
-                                        regulator-on-in-suspend;
-                                };
-                        };
-
-                        vcc33_lan: SWITCH_REG2 {
-                                regulator-always-on;
-                                regulator-boot-on;
-                                regulator-name = "vcc33_lan";
-                                regulator-state-mem {
-                                        regulator-on-in-suspend;
-                                };
-                        };
-                };
-        };
-};
-
-&i2c2 {
-        status = "okay";
-};
-
-&i2c5 {
-        status = "okay";
-};
-
-&i2s {
-        #sound-dai-cells = <0>;
-        status = "okay";
-};
-
-&io_domains {
-        status = "okay";
-
-        sdcard-supply = <&vccio_sd>;
-};
-
-&pinctrl {
-        pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
-                drive-strength = <8>;
-        };
-
-        pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
-                bias-pull-up;
-                drive-strength = <8>;
-        };
-
-        backlight {
-                bl_en: bl-en {
-                        rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
-                };
-        };
-
-        buttons {
-                pwrbtn: pwrbtn {
-                        rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
-                };
-        };
-
-        eth_phy {
-                eth_phy_pwr: eth-phy-pwr {
-                        rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
-                };
-        };
-
-        pmic {
-                pmic_int: pmic-int {
-                        rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO \
-                                        &pcfg_pull_up>;
-                };
-
-                dvs_1: dvs-1 {
-                        rockchip,pins = <RK_GPIO0 11 RK_FUNC_GPIO \
-                                        &pcfg_pull_down>;
-                };
-
-                dvs_2: dvs-2 {
-                        rockchip,pins = <RK_GPIO0 12 RK_FUNC_GPIO \
-                                        &pcfg_pull_down>;
-                };
-        };
-
-        sdmmc {
-                sdmmc_bus4: sdmmc-bus4 {
-                        rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
-                                        <6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
-                                        <6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
-                                        <6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
-                };
-
-                sdmmc_clk: sdmmc-clk {
-                        rockchip,pins = <6 20 RK_FUNC_1 \
-                                        &pcfg_pull_none_drv_8ma>;
-                };
-
-                sdmmc_cmd: sdmmc-cmd {
-                        rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
-                };
-
-                sdmmc_pwr: sdmmc-pwr {
-                        rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
-                };
-        };
-
-        usb {
-                host_vbus_drv: host-vbus-drv {
-                        rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
-                };
-
-                pwr_3g: pwr-3g {
-                        rockchip,pins = <7 8 RK_FUNC_GPIO &pcfg_pull_none>;
-                };
-        };
-};
-
-&pwm0 {
-        status = "okay";
-};
-
-&saradc {
-        vref-supply = <&vcc18_ldo1>;
-        status ="okay";
-};
-
-&sdmmc {
-        bus-width = <4>;
-        cap-mmc-highspeed;
-        cap-sd-highspeed;
-        card-detect-delay = <200>;
-        disable-wp;                     /* wp not hooked up */
-        pinctrl-names = "default";
-        pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
-        status = "okay";
-        vmmc-supply = <&vcc33_sd>;
-        vqmmc-supply = <&vccio_sd>;
-};
-
-&tsadc {
-        rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
-        rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
-        status = "okay";
-};
-
-&uart0 {
-        status = "okay";
-};
-
-&uart1 {
-        status = "okay";
-};
-
-&uart2 {
-        status = "okay";
-};
-
-&uart3 {
-        status = "okay";
-};
-
-&uart4 {
-        status = "okay";
-};
-
-&usbphy {
-        status = "okay";
-};
-
-&usb_host0_ehci {
-        status = "okay";
-};
-
-&usb_host1 {
-        status = "okay";
-};
-
-&usb_otg {
-        status= "okay";
-};
-
-&vopb {
-        status = "okay";
-};
-
-&vopb_mmu {
-        status = "okay";
-};
-
-&vopl {
-        status = "okay";
-};
-
-&vopl_mmu {
-        status = "okay";
-};
-
-&wdt {
-        status = "okay";
 };
diff --git a/arch/arm/boot/dts/rk3288-tinker.dtsi b/arch/arm/boot/dts/rk3288-tinker.dtsi
new file mode 100644
index 000000000000..aa107ee41b8b
--- /dev/null
+++ b/arch/arm/boot/dts/rk3288-tinker.dtsi
@@ -0,0 +1,502 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
+ */
+
+#include "rk3288.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+        chosen {
+                stdout-path = "serial2:115200n8";
+        };
+
+        memory {
+                reg = <0x0 0x0 0x0 0x80000000>;
+                device_type = "memory";
+        };
+
+        ext_gmac: external-gmac-clock {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <125000000>;
+                clock-output-names = "ext_gmac";
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                autorepeat;
+
+                pinctrl-names = "default";
+                pinctrl-0 = <&pwrbtn>;
+
+                button@0 {
+                        gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_POWER>;
+                        label = "GPIO Key Power";
+                        linux,input-type = <1>;
+                        wakeup-source;
+                        debounce-interval = <100>;
+                };
+        };
+
+        gpio-leds {
+                compatible = "gpio-leds";
+
+                act-led {
+                        gpios=<&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger="mmc0";
+                };
+
+                heartbeat-led {
+                        gpios=<&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger="heartbeat";
+                };
+
+                pwr-led {
+                        gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "default-on";
+                };
+        };
+
+        sound {
+                compatible = "simple-audio-card";
+                simple-audio-card,format = "i2s";
+                simple-audio-card,name = "rockchip,tinker-codec";
+                simple-audio-card,mclk-fs = <512>;
+
+                simple-audio-card,codec {
+                        sound-dai = <&hdmi>;
+                };
+
+                simple-audio-card,cpu {
+                        sound-dai = <&i2s>;
+                };
+        };
+
+        vcc_sys: vsys-regulator {
+                compatible = "regulator-fixed";
+                regulator-name = "vcc_sys";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-always-on;
+                regulator-boot-on;
+        };
+
+        vcc_sd: sdmmc-regulator {
+                compatible = "regulator-fixed";
+                gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&sdmmc_pwr>;
+                regulator-name = "vcc_sd";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                startup-delay-us = <100000>;
+                vin-supply = <&vcc_io>;
+        };
+};
+
+&cpu0 {
+        cpu0-supply = <&vdd_cpu>;
+};
+
+&gmac {
+        assigned-clocks = <&cru SCLK_MAC>;
+        assigned-clock-parents = <&ext_gmac>;
+        clock_in_out = "input";
+        phy-mode = "rgmii";
+        phy-supply = <&vcc33_lan>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&rgmii_pins>;
+        snps,reset-gpio = <&gpio4 7 0>;
+        snps,reset-active-low;
+        snps,reset-delays-us = <0 10000 1000000>;
+        tx_delay = <0x30>;
+        rx_delay = <0x10>;
+        status = "ok";
+};
+
+&gpu {
+        mali-supply = <&vdd_gpu>;
+        status = "okay";
+};
+
+&hdmi {
+        ddc-i2c-bus = <&i2c5>;
+        status = "okay";
+};
+
+&i2c0 {
+        clock-frequency = <400000>;
+        status = "okay";
+
+        rk808: pmic@1b {
+                compatible = "rockchip,rk808";
+                reg = <0x1b>;
+                interrupt-parent = <&gpio0>;
+                interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+                #clock-cells = <1>;
+                clock-output-names = "xin32k", "rk808-clkout2";
+                dvs-gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>,
+                                <&gpio0 12 GPIO_ACTIVE_HIGH>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pmic_int &global_pwroff &dvs_1 &dvs_2>;
+                rockchip,system-power-controller;
+                wakeup-source;
+
+                vcc1-supply = <&vcc_sys>;
+                vcc2-supply = <&vcc_sys>;
+                vcc3-supply = <&vcc_sys>;
+                vcc4-supply = <&vcc_sys>;
+                vcc6-supply = <&vcc_sys>;
+                vcc7-supply = <&vcc_sys>;
+                vcc8-supply = <&vcc_io>;
+                vcc9-supply = <&vcc_io>;
+                vcc10-supply = <&vcc_io>;
+                vcc11-supply = <&vcc_sys>;
+                vcc12-supply = <&vcc_io>;
+                vddio-supply = <&vcc_io>;
+
+                regulators {
+                        vdd_cpu: DCDC_REG1 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <750000>;
+                                regulator-max-microvolt = <1350000>;
+                                regulator-name = "vdd_arm";
+                                regulator-ramp-delay = <6000>;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        vdd_gpu: DCDC_REG2 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <850000>;
+                                regulator-max-microvolt = <1250000>;
+                                regulator-name = "vdd_gpu";
+                                regulator-ramp-delay = <6000>;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1000000>;
+                                };
+                        };
+
+                        vcc_ddr: DCDC_REG3 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-name = "vcc_ddr";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                };
+                        };
+
+                        vcc_io: DCDC_REG4 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-name = "vcc_io";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <3300000>;
+                                };
+                        };
+
+                        vcc18_ldo1: LDO_REG1 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-name = "vcc18_ldo1";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1800000>;
+                                };
+                        };
+
+                        vcc33_mipi: LDO_REG2 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-name = "vcc33_mipi";
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        vdd_10: LDO_REG3 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-name = "vdd_10";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1000000>;
+                                };
+                        };
+
+                        vcc18_codec: LDO_REG4 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-name = "vcc18_codec";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1800000>;
+                                };
+                        };
+
+                        vccio_sd: LDO_REG5 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-name = "vccio_sd";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <3300000>;
+                                };
+                        };
+
+                        vdd10_lcd: LDO_REG6 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-name = "vdd10_lcd";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1000000>;
+                                };
+                        };
+
+                        vcc_18: LDO_REG7 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-name = "vcc_18";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1800000>;
+                                };
+                        };
+
+                        vcc18_lcd: LDO_REG8 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-name = "vcc18_lcd";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1800000>;
+                                };
+                        };
+
+                        vcc33_sd: SWITCH_REG1 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-name = "vcc33_sd";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                };
+                        };
+
+                        vcc33_lan: SWITCH_REG2 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-name = "vcc33_lan";
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                };
+                        };
+                };
+        };
+};
+
+&i2c2 {
+        status = "okay";
+};
+
+&i2c5 {
+        status = "okay";
+};
+
+&i2s {
+        #sound-dai-cells = <0>;
+        status = "okay";
+};
+
+&io_domains {
+        status = "okay";
+
+        sdcard-supply = <&vccio_sd>;
+};
+
+&pinctrl {
+        pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
+                drive-strength = <8>;
+        };
+
+        pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
+                bias-pull-up;
+                drive-strength = <8>;
+        };
+
+        backlight {
+                bl_en: bl-en {
+                        rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
+                };
+        };
+
+        buttons {
+                pwrbtn: pwrbtn {
+                        rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
+                };
+        };
+
+        eth_phy {
+                eth_phy_pwr: eth-phy-pwr {
+                        rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
+                };
+        };
+
+        pmic {
+                pmic_int: pmic-int {
+                        rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO \
+                                        &pcfg_pull_up>;
+                };
+
+                dvs_1: dvs-1 {
+                        rockchip,pins = <RK_GPIO0 11 RK_FUNC_GPIO \
+                                        &pcfg_pull_down>;
+                };
+
+                dvs_2: dvs-2 {
+                        rockchip,pins = <RK_GPIO0 12 RK_FUNC_GPIO \
+                                        &pcfg_pull_down>;
+                };
+        };
+
+        sdmmc {
+                sdmmc_bus4: sdmmc-bus4 {
+                        rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
+                                        <6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
+                                        <6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
+                                        <6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
+                };
+
+                sdmmc_clk: sdmmc-clk {
+                        rockchip,pins = <6 20 RK_FUNC_1 \
+                                        &pcfg_pull_none_drv_8ma>;
+                };
+
+                sdmmc_cmd: sdmmc-cmd {
+                        rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
+                };
+
+                sdmmc_pwr: sdmmc-pwr {
+                        rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
+                };
+        };
+
+        usb {
+                host_vbus_drv: host-vbus-drv {
+                        rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
+                };
+
+                pwr_3g: pwr-3g {
+                        rockchip,pins = <7 8 RK_FUNC_GPIO &pcfg_pull_none>;
+                };
+        };
+};
+
+&pwm0 {
+        status = "okay";
+};
+
+&saradc {
+        vref-supply = <&vcc18_ldo1>;
+        status ="okay";
+};
+
+&sdmmc {
+        bus-width = <4>;
+        cap-mmc-highspeed;
+        cap-sd-highspeed;
+        card-detect-delay = <200>;
+        disable-wp;                     /* wp not hooked up */
+        pinctrl-names = "default";
+        pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+        status = "okay";
+        vmmc-supply = <&vcc33_sd>;
+        vqmmc-supply = <&vccio_sd>;
+};
+
+&tsadc {
+        rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
+        rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
+        status = "okay";
+};
+
+&uart0 {
+        status = "okay";
+};
+
+&uart1 {
+        status = "okay";
+};
+
+&uart2 {
+        status = "okay";
+};
+
+&uart3 {
+        status = "okay";
+};
+
+&uart4 {
+        status = "okay";
+};
+
+&usbphy {
+        status = "okay";
+};
+
+&usb_host0_ehci {
+        status = "okay";
+};
+
+&usb_host1 {
+        status = "okay";
+};
+
+&usb_otg {
+        status= "okay";
+};
+
+&vopb {
+        status = "okay";
+};
+
+&vopb_mmu {
+        status = "okay";
+};
+
+&vopl {
+        status = "okay";
+};
+
+&vopl_mmu {
+        status = "okay";
+};
+
+&wdt {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi
index 67358562a6ea..75f454a210d6 100644
--- a/arch/arm/boot/dts/s5pv210.dtsi
+++ b/arch/arm/boot/dts/s5pv210.dtsi
@@ -120,7 +120,7 @@
                         interrupts = <30>;
 
                         wakeup-interrupt-controller {
-                                compatible = "samsung,exynos4210-wakeup-eint";
+                                compatible = "samsung,s5pv210-wakeup-eint";
                                 interrupts = <16>;
                                 interrupt-parent = <&vic0>;
                         };
diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi
index 61f68e5c48e9..843052f14f1c 100644
--- a/arch/arm/boot/dts/sama5d2.dtsi
+++ b/arch/arm/boot/dts/sama5d2.dtsi
@@ -47,6 +47,7 @@
 #include <dt-bindings/dma/at91.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/clock/at91.h>
+#include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
 
 / {
         model = "Atmel SAMA5D2 family SoC";
@@ -58,6 +59,8 @@
                 serial1 = &uart3;
                 tcb0 = &tcb0;
                 tcb1 = &tcb1;
+                i2s0 = &i2s0;
+                i2s1 = &i2s1;
         };
 
         cpus {
@@ -84,10 +87,11 @@
                 clocks = <&mck>;
                 clock-names = "apb_pclk";
 
-                port {
-                        etb_in: endpoint {
-                                slave-mode;
-                                remote-endpoint = <&etm_out>;
+                in-ports {
+                        port {
+                                etb_in: endpoint {
+                                        remote-endpoint = <&etm_out>;
+                                };
                         };
                 };
         };
@@ -99,9 +103,11 @@
                 clocks = <&mck>;
                 clock-names = "apb_pclk";
 
-                port {
-                        etm_out: endpoint {
-                                remote-endpoint = <&etb_in>;
+                out-ports {
+                        port {
+                                etm_out: endpoint {
+                                        remote-endpoint = <&etb_in>;
+                                };
                         };
                 };
         };
@@ -323,44 +329,6 @@
                         };
                 };
 
-                nand0: nand@80000000 {
-                        compatible = "atmel,sama5d2-nand";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        ranges;
-                        reg = < /* EBI CS3 */
-                                0x80000000 0x08000000
-                                /* SMC PMECC regs */
-                                0xf8014070 0x00000490
-                                /* SMC PMECC Error Location regs */
-                                0xf8014500 0x00000200
-                                /* ROM Galois tables */
-                                0x00040000 0x00018000
-                                >;
-                        interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
-                        atmel,nand-addr-offset = <21>;
-                        atmel,nand-cmd-offset = <22>;
-                        atmel,nand-has-dma;
-                        atmel,has-pmecc;
-                        atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
-                        status = "disabled";
-
-                        nfc@c0000000 {
-                                compatible = "atmel,sama5d3-nfc";
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                reg = < /* NFC Command Registers */
-                                        0xc0000000 0x08000000
-                                        /* NFC HSMC regs */
-                                        0xf8014000 0x00000070
-                                        /* NFC SRAM banks */
-                                        0x00100000 0x00100000
-                                        >;
-                                clocks = <&hsmc_clk>;
-                                atmel,write-by-sram;
-                        };
-                };
-
                 sdmmc0: sdio-host@a0000000 {
                         compatible = "atmel,sama5d2-sdhci";
                         reg = <0xa0000000 0x300>;
@@ -992,6 +960,24 @@
                                                 atmel,clk-output-range = <0 100000000>;
                                         };
                                 };
+
+                                i2s_clkmux {
+                                        compatible = "atmel,sama5d2-clk-i2s-mux";
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+
+                                        i2s0muxck: i2s0_muxclk {
+                                                clocks = <&i2s0_clk>, <&i2s0_gclk>;
+                                                #clock-cells = <0>;
+                                                reg = <0>;
+                                        };
+
+                                        i2s1muxck: i2s1_muxclk {
+                                                clocks = <&i2s1_clk>, <&i2s1_gclk>;
+                                                #clock-cells = <0>;
+                                                reg = <1>;
+                                        };
+                                };
                         };
 
                         qspi0: spi@f0020000 {
@@ -1295,6 +1281,24 @@
                                 clocks = <&clk32k>;
                         };
 
+                        i2s0: i2s@f8050000 {
+                                compatible = "atmel,sama5d2-i2s";
+                                reg = <0xf8050000 0x100>;
+                                interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>;
+                                dmas = <&dma0
+                                        (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+                                         AT91_XDMAC_DT_PERID(31))>,
+                                       <&dma0
+                                        (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+                                         AT91_XDMAC_DT_PERID(32))>;
+                                dma-names = "tx", "rx";
+                                clocks = <&i2s0_clk>, <&i2s0_gclk>;
+                                clock-names = "pclk", "gclk";
+                                assigned-clocks = <&i2s0muxck>;
+                                assigned-clock-parents = <&i2s0_gclk>;
+                                status = "disabled";
+                        };
+
                         can0: can@f8054000 {
                                 compatible = "bosch,m_can";
                                 reg = <0xf8054000 0x4000>, <0x210000 0x4000>;
@@ -1437,6 +1441,17 @@
                                 atmel,max-sample-rate-hz = <20000000>;
                                 atmel,startup-time-ms = <4>;
                                 atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>;
+                                #io-channel-cells = <1>;
+                                status = "disabled";
+                        };
+
+                        resistive_touch: resistive-touch {
+                                compatible = "resistive-adc-touch";
+                                io-channels = <&adc AT91_SAMA5D2_ADC_X_CHANNEL>,
+                                              <&adc AT91_SAMA5D2_ADC_Y_CHANNEL>,
+                                              <&adc AT91_SAMA5D2_ADC_P_CHANNEL>;
+                                io-channel-names = "x", "y", "pressure";
+                                touchscreen-min-pressure = <50000>;
                                 status = "disabled";
                         };
 
@@ -1488,6 +1503,24 @@
                                 status = "disabled";
                         };
 
+                        i2s1: i2s@fc04c000 {
+                                compatible = "atmel,sama5d2-i2s";
+                                reg = <0xfc04c000 0x100>;
+                                interrupts = <55 IRQ_TYPE_LEVEL_HIGH 7>;
+                                dmas = <&dma0
+                                        (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+                                         AT91_XDMAC_DT_PERID(33))>,
+                                       <&dma0
+                                        (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+                                         AT91_XDMAC_DT_PERID(34))>;
+                                dma-names = "tx", "rx";
+                                clocks = <&i2s1_clk>, <&i2s1_gclk>;
+                                clock-names = "pclk", "gclk";
+                                assigned-clocks = <&i2s1muxck>;
+                                assigned-parrents = <&i2s1_gclk>;
+                                status = "disabled";
+                        };
+
                         can1: can@fc050000 {
                                 compatible = "bosch,m_can";
                                 reg = <0xfc050000 0x4000>, <0x210000 0x4000>;
diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
index 92a35a1942b6..7371f2a0460f 100644
--- a/arch/arm/boot/dts/sama5d4.dtsi
+++ b/arch/arm/boot/dts/sama5d4.dtsi
@@ -1323,13 +1323,13 @@
                                 };
                         };
 
-                        rstc@fc068600 {
+                        reset_controller: rstc@fc068600 {
                                 compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc";
                                 reg = <0xfc068600 0x10>;
                                 clocks = <&clk32k>;
                         };
 
-                        shdwc@fc068610 {
+                        shutdown_controller: shdwc@fc068610 {
                                 compatible = "atmel,at91sam9x5-shdwc";
                                 reg = <0xfc068610 0x10>;
                                 clocks = <&clk32k>;
@@ -1342,7 +1342,7 @@
                                 clocks = <&h32ck>;
                         };
 
-                        watchdog@fc068640 {
+                        watchdog: watchdog@fc068640 {
                                 compatible = "atmel,sama5d4-wdt";
                                 reg = <0xfc068640 0x10>;
                                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
@@ -1376,7 +1376,7 @@
                         };
 
 
-                        pinctrl@fc06a000 {
+                        pinctrl: pinctrl@fc06a000 {
                                 #address-cells = <1>;
                                 #size-cells = <1>;
                                 compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus";
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index b38f8c240558..2d300396f0ed 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -22,8 +22,6 @@
         #size-cells = <1>;
 
         aliases {
-                ethernet0 = &gmac0;
-                ethernet1 = &gmac1;
                 serial0 = &uart0;
                 serial1 = &uart1;
                 timer0 = &timer0;
@@ -483,10 +481,17 @@
                                                 clk-gate = <0xa0 9>;
                                         };
 
+                                        nand_ecc_clk: nand_ecc_clk {
+                                                #clock-cells = <0>;
+                                                compatible = "altr,socfpga-gate-clk";
+                                                clocks = <&nand_x_clk>;
+                                                clk-gate = <0xa0 9>;
+                                        };
+
                                         nand_clk: nand_clk {
                                                 #clock-cells = <0>;
                                                 compatible = "altr,socfpga-gate-clk";
-                                                clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+                                                clocks = <&nand_x_clk>;
                                                 clk-gate = <0xa0 10>;
                                                 fixed-divider = <4>;
                                         };
@@ -754,7 +759,8 @@
                         reg-names = "nand_data", "denali_reg";
                         interrupts = <0x0 0x90 0x4>;
                         dma-mask = <0xffffffff>;
-                        clocks = <&nand_x_clk>;
+                        clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
+                        clock-names = "nand", "nand_x", "ecc";
                         status = "disabled";
                 };
 
@@ -841,6 +847,8 @@
                         reg = <0xffc08000 0x1000>;
                         clocks = <&l4_sp_clk>;
                         clock-names = "timer";
+                        resets = <&rst SPTIMER0_RESET>;
+                        reset-names = "timer";
                 };
 
                 timer1: timer1@ffc09000 {
@@ -849,6 +857,8 @@
                         reg = <0xffc09000 0x1000>;
                         clocks = <&l4_sp_clk>;
                         clock-names = "timer";
+                        resets = <&rst SPTIMER1_RESET>;
+                        reset-names = "timer";
                 };
 
                 timer2: timer2@ffd00000 {
@@ -857,6 +867,8 @@
                         reg = <0xffd00000 0x1000>;
                         clocks = <&osc1>;
                         clock-names = "timer";
+                        resets = <&rst OSC1TIMER0_RESET>;
+                        reset-names = "timer";
                 };
 
                 timer3: timer3@ffd01000 {
@@ -865,6 +877,8 @@
                         reg = <0xffd01000 0x1000>;
                         clocks = <&osc1>;
                         clock-names = "timer";
+                        resets = <&rst OSC1TIMER1_RESET>;
+                        reset-names = "timer";
                 };
 
                 uart0: serial0@ffc02000 {
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index a4dcb68f4322..59ef13e37536 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -377,13 +377,28 @@
                                                 clk-gate = <0xC8 11>;
                                         };
 
-                                        nand_clk: nand_clk {
+                                        nand_x_clk: nand_x_clk {
                                                 #clock-cells = <0>;
                                                 compatible = "altr,socfpga-a10-gate-clk";
                                                 clocks = <&l4_mp_clk>;
                                                 clk-gate = <0xC8 10>;
                                         };
 
+                                        nand_ecc_clk: nand_ecc_clk {
+                                                #clock-cells = <0>;
+                                                compatible = "altr,socfpga-a10-gate-clk";
+                                                clocks = <&nand_x_clk>;
+                                                clk-gate = <0xC8 10>;
+                                        };
+
+                                        nand_clk: nand_clk {
+                                                #clock-cells = <0>;
+                                                compatible = "altr,socfpga-a10-gate-clk";
+                                                clocks = <&nand_x_clk>;
+                                                fixed-divider = <4>;
+                                                clk-gate = <0xC8 10>;
+                                        };
+
                                         spi_m_clk: spi_m_clk {
                                                 #clock-cells = <0>;
                                                 compatible = "altr,socfpga-a10-gate-clk";
@@ -613,7 +628,7 @@
                         status = "disabled";
                 };
 
-                sdr: sdr@ffc25000 {
+                sdr: sdr@ffcfb100 {
                         compatible = "altr,sdr-ctl", "syscon";
                         reg = <0xffcfb100 0x80>;
                 };
@@ -650,7 +665,8 @@
                         reg-names = "nand_data", "denali_reg";
                         interrupts = <0 99 4>;
                         dma-mask = <0xffffffff>;
-                        clocks = <&nand_clk>;
+                        clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
+                        clock-names = "nand", "nand_x", "ecc";
                         status = "disabled";
                 };
 
@@ -760,7 +776,7 @@
                 timer@ffffc600 {
                         compatible = "arm,cortex-a9-twd-timer";
                         reg = <0xffffc600 0x100>;
-                        interrupts = <1 13 0xf04>;
+                        interrupts = <1 13 0xf01>;
                         clocks = <&mpu_periph_clk>;
                 };
 
@@ -770,6 +786,8 @@
                         reg = <0xffc02700 0x100>;
                         clocks = <&l4_sp_clk>;
                         clock-names = "timer";
+                        resets = <&rst SPTIMER0_RESET>;
+                        reset-names = "timer";
                 };
 
                 timer1: timer1@ffc02800 {
@@ -778,6 +796,8 @@
                         reg = <0xffc02800 0x100>;
                         clocks = <&l4_sp_clk>;
                         clock-names = "timer";
+                        resets = <&rst SPTIMER1_RESET>;
+                        reset-names = "timer";
                 };
 
                 timer2: timer2@ffd00000 {
@@ -786,6 +806,8 @@
                         reg = <0xffd00000 0x100>;
                         clocks = <&l4_sys_free_clk>;
                         clock-names = "timer";
+                        resets = <&rst L4SYSTIMER0_RESET>;
+                        reset-names = "timer";
                 };
 
                 timer3: timer3@ffd00100 {
@@ -794,6 +816,8 @@
                         reg = <0xffd01000 0x100>;
                         clocks = <&l4_sys_free_clk>;
                         clock-names = "timer";
+                        resets = <&rst L4SYSTIMER1_RESET>;
+                        reset-names = "timer";
                 };
 
                 uart0: serial0@ffc02000 {
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts
index b280e6494193..31b01a998b2e 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts
@@ -88,7 +88,7 @@
         status = "okay";
         clock-frequency = <100000>;
 
-        adxl345: adxl345@0 {
+        adxl345: adxl345@53 {
                 compatible = "adi,adxl345";
                 reg = <0x53>;
 
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
index 53bf99eef66d..031c721441ff 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
@@ -21,8 +21,13 @@
         model = "EBV SOCrates";
         compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga";
 
+        aliases {
+                ethernet0 = &gmac1;
+        };
+
         chosen {
-                bootargs = "console=ttyS0,115200";
+                bootargs = "earlyprintk";
+                stdout-path = "serial0:115200n8";
         };
 
         memory@0 {
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
index f50b19447de6..e61efe16e79c 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
@@ -54,7 +54,8 @@
         compatible = "samtec,vining", "altr,socfpga-cyclone5", "altr,socfpga";
 
         chosen {
-                bootargs = "console=ttyS0,115200";
+                bootargs = "earlyprintk";
+                stdout-path = "serial0:115200n8";
         };
 
         memory@0 {
diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi
index 2310a4e97768..e6ed7c0354a2 100644
--- a/arch/arm/boot/dts/ste-dbx5x0.dtsi
+++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi
@@ -15,9 +15,14 @@
 #include <dt-bindings/arm/ux500_pm_domains.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/clock/ste-ab8500.h>
-#include "skeleton.dtsi"
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        chosen {
+        };
+
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -67,9 +72,11 @@
                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
                         clock-names = "apb_pclk", "atclk";
                         cpu = <&CPU0>;
-                        port {
-                                ptm0_out_port: endpoint {
-                                        remote-endpoint = <&funnel_in_port0>;
+                        out-ports {
+                                port {
+                                        ptm0_out_port: endpoint {
+                                                remote-endpoint = <&funnel_in_port0>;
+                                        };
                                 };
                         };
                 };
@@ -81,9 +88,11 @@
                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
                         clock-names = "apb_pclk", "atclk";
                         cpu = <&CPU1>;
-                        port {
-                                ptm1_out_port: endpoint {
-                                        remote-endpoint = <&funnel_in_port1>;
+                        out-ports {
+                                port {
+                                        ptm1_out_port: endpoint {
+                                                remote-endpoint = <&funnel_in_port1>;
+                                        };
                                 };
                         };
                 };
@@ -94,32 +103,29 @@
 
                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
                         clock-names = "apb_pclk", "atclk";
-                        ports {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-
-                                /* funnel output ports */
-                                port@0 {
-                                        reg = <0>;
+                        out-ports {
+                                port {
                                         funnel_out_port: endpoint {
                                                 remote-endpoint =
                                                         <&replicator_in_port0>;
                                         };
                                 };
+                        };
 
-                                /* funnel input ports */
-                                port@1 {
+                        in-ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@0 {
                                         reg = <0>;
                                         funnel_in_port0: endpoint {
-                                                slave-mode;
                                                 remote-endpoint = <&ptm0_out_port>;
                                         };
                                 };
 
-                                port@2 {
+                                port@1 {
                                         reg = <1>;
                                         funnel_in_port1: endpoint {
-                                                slave-mode;
                                                 remote-endpoint = <&ptm1_out_port>;
                                         };
                                 };
@@ -131,11 +137,10 @@
                         clocks = <&prcmu_clk PRCMU_APEATCLK>;
                         clock-names = "atclk";
 
-                        ports {
+                        out-ports {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
 
-                                /* replicator output ports */
                                 port@0 {
                                         reg = <0>;
                                         replicator_out_port0: endpoint {
@@ -148,12 +153,11 @@
                                                 remote-endpoint = <&etb_in_port>;
                                         };
                                 };
+                        };
 
-                                /* replicator input port */
-                                port@2 {
-                                        reg = <0>;
+                        in-ports {
+                                port {
                                         replicator_in_port0: endpoint {
-                                                slave-mode;
                                                 remote-endpoint = <&funnel_out_port>;
                                         };
                                 };
@@ -166,10 +170,11 @@
 
                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
                         clock-names = "apb_pclk", "atclk";
-                        port {
-                                tpiu_in_port: endpoint {
-                                        slave-mode;
-                                        remote-endpoint = <&replicator_out_port0>;
+                        in-ports {
+                                port {
+                                        tpiu_in_port: endpoint {
+                                                remote-endpoint = <&replicator_out_port0>;
+                                        };
                                 };
                         };
                 };
@@ -180,10 +185,11 @@
 
                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
                         clock-names = "apb_pclk", "atclk";
-                        port {
-                                etb_in_port: endpoint {
-                                        slave-mode;
-                                        remote-endpoint = <&replicator_out_port1>;
+                        in-ports {
+                                port {
+                                        etb_in_port: endpoint {
+                                                remote-endpoint = <&replicator_out_port1>;
+                                        };
                                 };
                         };
                 };
@@ -197,7 +203,7 @@
                               <0xa0410100 0x100>;
                 };
 
-                scu@a04100000 {
+                scu@a0410000 {
                         compatible = "arm,cortex-a9-scu";
                         reg = <0xa0410000 0x100>;
                 };
@@ -487,7 +493,7 @@
                 };
 
                 prcmu: prcmu@80157000 {
-                        compatible = "stericsson,db8500-prcmu";
+                        compatible = "stericsson,db8500-prcmu", "syscon";
                         reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
                         reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
@@ -878,7 +884,7 @@
                         power-domains = <&pm_domains DOMAIN_VAPE>;
                 };
 
-                ssp@80002000 {
+                spi@80002000 {
                         compatible = "arm,pl022", "arm,primecell";
                         reg = <0x80002000 0x1000>;
                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
@@ -892,7 +898,7 @@
                         power-domains = <&pm_domains DOMAIN_VAPE>;
                 };
 
-                ssp@80003000 {
+                spi@80003000 {
                         compatible = "arm,pl022", "arm,primecell";
                         reg = <0x80003000 0x1000>;
                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi
index 5c5cea232743..1ec193b0c506 100644
--- a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi
+++ b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi
@@ -607,16 +607,20 @@
 
                         mcde {
                                 lcd_default_mode: lcd_default {
-                                        default_mux {
+                                        default_mux1 {
                                                 /* Mux in VSI0 and all the data lines */
                                                 function = "lcd";
                                                 groups =
                                                 "lcdvsi0_a_1", /* VSI0 for LCD */
                                                 "lcd_d0_d7_a_1", /* Data lines */
                                                 "lcd_d8_d11_a_1", /* TV-out */
-                                                "lcdaclk_b_1", /* Clock line for TV-out */
                                                 "lcdvsi1_a_1"; /* VSI1 for HDMI */
                                         };
+                                        default_mux2 {
+                                                function = "lcda";
+                                                groups =
+                                                "lcdaclk_b_1"; /* Clock line for TV-out */
+                                        };
                                         default_cfg1 {
                                                 pins =
                                                 "GPIO68_E1", /* VSI0 */
diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi
index 9e359e4f342e..feb682a3d363 100644
--- a/arch/arm/boot/dts/ste-href.dtsi
+++ b/arch/arm/boot/dts/ste-href.dtsi
@@ -15,6 +15,7 @@
 
 / {
         memory {
+                device_type = "memory";
                 reg = <0x00000000 0x20000000>;
         };
 
diff --git a/arch/arm/boot/dts/ste-hrefprev60.dtsi b/arch/arm/boot/dts/ste-hrefprev60.dtsi
index 3f14b4df69b4..94eeb7f1c947 100644
--- a/arch/arm/boot/dts/ste-hrefprev60.dtsi
+++ b/arch/arm/boot/dts/ste-hrefprev60.dtsi
@@ -57,7 +57,7 @@
                         };
                 };
 
-                ssp@80002000 {
+                spi@80002000 {
                         /*
                          * On the first generation boards, this SSP/SPI port was connected
                          * to the AB8500.
diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts
index b0b94d053098..2de3ce79e496 100644
--- a/arch/arm/boot/dts/ste-snowball.dts
+++ b/arch/arm/boot/dts/ste-snowball.dts
@@ -26,6 +26,7 @@
         };
 
         memory {
+                device_type = "memory";
                 reg = <0x00000000 0x20000000>;
         };
 
@@ -376,7 +377,7 @@
                         pinctrl-1 = <&i2c3_sleep_mode>;
                 };
 
-                ssp@80002000 {
+                spi@80002000 {
                         pinctrl-names = "default";
                         pinctrl-0 = <&ssp0_snowball_mode>;
                 };
diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
index 62ecb6a2fa39..1bd1aba3322f 100644
--- a/arch/arm/boot/dts/ste-u300.dts
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -442,7 +442,7 @@
                         dma-names = "rx";
                 };
 
-                spi: ssp@c0006000 {
+                spi: spi@c0006000 {
                         compatible = "arm,pl022", "arm,primecell";
                         reg = <0xc0006000 0x1000>;
                         interrupt-parent = <&vica>;
diff --git a/arch/arm/boot/dts/stih410-b2260.dts b/arch/arm/boot/dts/stih410-b2260.dts
index 155caa8c002a..4ee6d51d8d1e 100644
--- a/arch/arm/boot/dts/stih410-b2260.dts
+++ b/arch/arm/boot/dts/stih410-b2260.dts
@@ -61,8 +61,11 @@
                 compatible = "simple-audio-card";
                 simple-audio-card,name = "STI-B2260";
                 status = "okay";
+                #address-cells = <1>;
+                #size-cells = <0>;
 
-                simple-audio-card,dai-link0 {
+                simple-audio-card,dai-link@0 {
+                        reg = <0>;
                         /* DAC */
                         format = "i2s";
                         mclk-fs = <128>;
diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi
index 4dedfcb0fcb3..97e05f55fb6e 100644
--- a/arch/arm/boot/dts/stihxxx-b2120.dtsi
+++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi
@@ -27,8 +27,11 @@
                 compatible = "simple-audio-card";
                 simple-audio-card,name = "STI-B2120";
                 status = "okay";
+                #address-cells = <1>;
+                #size-cells = <0>;
 
-                simple-audio-card,dai-link0 {
+                simple-audio-card,dai-link@0 {
+                        reg = <0>;
                         /* HDMI */
                         format = "i2s";
                         mclk-fs = <128>;
@@ -41,7 +44,8 @@
                         };
                 };
 
-                simple-audio-card,dai-link1 {
+                simple-audio-card,dai-link@1 {
+                        reg = <1>;
                         /* DAC */
                         format = "i2s";
                         mclk-fs = <256>;
@@ -55,7 +59,8 @@
                         };
                 };
 
-                simple-audio-card,dai-link2 {
+                simple-audio-card,dai-link@2 {
+                        reg = <2>;
                         /* SPDIF */
                         format = "left_j";
                         mclk-fs = <128>;
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts
index 7eb786a2d624..ed7d7f46465e 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -264,8 +264,7 @@
 &sdio {
         status = "okay";
         vmmc-supply = <&mmc_vcard>;
-        cd-gpios = <&stmpegpio 15 GPIO_ACTIVE_HIGH>;
-        cd-inverted;
+        cd-gpios = <&stmpegpio 15 GPIO_ACTIVE_LOW>;
         pinctrl-names = "default", "opendrain";
         pinctrl-0 = <&sdio_pins>;
         pinctrl-1 = <&sdio_pins_od>;
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index e35d782e7e5f..8d6f028ae285 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -58,7 +58,7 @@
                         clock-frequency = <0>;
                 };
 
-                clk-lse {
+                clk_lse: clk-lse {
                         #clock-cells = <0>;
                         compatible = "fixed-clock";
                         clock-frequency = <32768>;
diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts
index 3ee768cb86fc..7937b43d7788 100644
--- a/arch/arm/boot/dts/stm32f469-disco.dts
+++ b/arch/arm/boot/dts/stm32f469-disco.dts
@@ -210,8 +210,7 @@
 &sdio {
         status = "okay";
         vmmc-supply = <&mmc_vcard>;
-        cd-gpios = <&gpiog 2 GPIO_ACTIVE_HIGH>;
-        cd-inverted;
+        cd-gpios = <&gpiog 2 GPIO_ACTIVE_LOW>;
         broken-cd;
         pinctrl-names = "default", "opendrain";
         pinctrl-0 = <&sdio_pins>;
diff --git a/arch/arm/boot/dts/stm32f746-disco.dts b/arch/arm/boot/dts/stm32f746-disco.dts
index f9ad71f7c807..e3a7bd338d61 100644
--- a/arch/arm/boot/dts/stm32f746-disco.dts
+++ b/arch/arm/boot/dts/stm32f746-disco.dts
@@ -101,8 +101,7 @@
 &sdio1 {
         status = "okay";
         vmmc-supply = <&mmc_vcard>;
-        cd-gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
-        cd-inverted;
+        cd-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
         pinctrl-names = "default", "opendrain";
         pinctrl-0 = <&sdio_pins_a>;
         pinctrl-1 = <&sdio_pins_od_a>;
diff --git a/arch/arm/boot/dts/stm32f769-disco.dts b/arch/arm/boot/dts/stm32f769-disco.dts
index 677276ba4dbe..483d896e2bc1 100644
--- a/arch/arm/boot/dts/stm32f769-disco.dts
+++ b/arch/arm/boot/dts/stm32f769-disco.dts
@@ -126,8 +126,7 @@
 &sdio2 {
         status = "okay";
         vmmc-supply = <&mmc_vcard>;
-        cd-gpios = <&gpioi 15 GPIO_ACTIVE_HIGH>;
-        cd-inverted;
+        cd-gpios = <&gpioi 15 GPIO_ACTIVE_LOW>;
         broken-cd;
         pinctrl-names = "default", "opendrain";
         pinctrl-0 = <&sdio_pins_b>;
diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi
index 637beffe5067..cbdd69ca9e7a 100644
--- a/arch/arm/boot/dts/stm32h743.dtsi
+++ b/arch/arm/boot/dts/stm32h743.dtsi
@@ -472,7 +472,7 @@
                         interrupt-parent = <&exti>;
                         interrupts = <17 IRQ_TYPE_EDGE_RISING>;
                         interrupt-names = "alarm";
-                        st,syscfg = <&pwrcfg>;
+                        st,syscfg = <&pwrcfg 0x00 0x100>;
                         status = "disabled";
                 };
 
diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts
index 372bc2ea6b92..063ee8ac5dcb 100644
--- a/arch/arm/boot/dts/stm32mp157c-ev1.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts
@@ -6,6 +6,7 @@
 /dts-v1/;
 
 #include "stm32mp157c-ed1.dts"
+#include <dt-bindings/gpio/gpio.h>
 
 / {
         model = "STMicroelectronics STM32MP157C eval daughter on eval mother";
@@ -19,6 +20,58 @@
                 serial0 = &uart4;
                 ethernet0 = &ethernet0;
         };
+
+        panel_backlight: panel-backlight {
+                compatible = "gpio-backlight";
+                gpios = <&gpiod 13 GPIO_ACTIVE_LOW>;
+                default-on;
+                status = "okay";
+        };
+};
+
+&cec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&cec_pins_a>;
+        status = "okay";
+};
+
+&dsi {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        status = "okay";
+
+        ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                port@0 {
+                        reg = <0>;
+                        dsi_in: endpoint {
+                                remote-endpoint = <&ltdc_ep0_out>;
+                        };
+                };
+
+                port@1 {
+                        reg = <1>;
+                        dsi_out: endpoint {
+                                remote-endpoint = <&dsi_panel_in>;
+                        };
+                };
+        };
+
+        panel-dsi@0 {
+                compatible = "raydium,rm68200";
+                reg = <0>;
+                reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
+                backlight = <&panel_backlight>;
+                status = "okay";
+
+                port {
+                        dsi_panel_in: endpoint {
+                                remote-endpoint = <&dsi_out>;
+                        };
+                };
+        };
 };
 
 &ethernet0 {
@@ -40,12 +93,6 @@
         };
 };
 
-&cec {
-        pinctrl-names = "default";
-        pinctrl-0 = <&cec_pins_a>;
-        status = "okay";
-};
-
 &i2c2 {
         pinctrl-names = "default";
         pinctrl-0 = <&i2c2_pins_a>;
@@ -62,6 +109,20 @@
         status = "okay";
 };
 
+&ltdc {
+        status = "okay";
+
+        port {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                ltdc_ep0_out: endpoint@0 {
+                        reg = <0>;
+                        remote-endpoint = <&dsi_in>;
+                };
+        };
+};
+
 &m_can1 {
         pinctrl-names = "default";
         pinctrl-0 = <&m_can1_pins_a>;
diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi
index 185541a5b69f..c50c36baba75 100644
--- a/arch/arm/boot/dts/stm32mp157c.dtsi
+++ b/arch/arm/boot/dts/stm32mp157c.dtsi
@@ -947,7 +947,7 @@
                         dma-requests = <48>;
                 };
 
-                qspi: qspi@58003000 {
+                qspi: spi@58003000 {
                         compatible = "st,stm32f469-qspi";
                         reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
                         reg-names = "qspi", "qspi_mm";
diff --git a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi
index 8acbaab14fe5..d2a2eb8b3f26 100644
--- a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi
+++ b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi
@@ -92,7 +92,8 @@
          */
         clock-frequency = <400000>;
 
-        touchscreen: touchscreen {
+        touchscreen: touchscreen@40 {
+                reg = <0x40>;
                 interrupt-parent = <&pio>;
                 interrupts = <6 11 IRQ_TYPE_EDGE_FALLING>; /* EINT11 (PG11) */
                 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 8bfb36651177..9cd65c46720b 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -108,6 +108,21 @@
                 };
         };
 
+        reserved-memory {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                /* Address must be kept in the lower 256 MiBs of DRAM for VE. */
+                cma_pool: cma@4a000000 {
+                        compatible = "shared-dma-pool";
+                        size = <0x6000000>;
+                        alloc-ranges = <0x4a000000 0x6000000>;
+                        reusable;
+                        linux,cma-default;
+                };
+        };
+
         soc@1c00000 {
                 compatible = "simple-bus";
                 #address-cells = <1>;
@@ -294,6 +309,17 @@
                         };
                 };
 
+                video-codec@1c0e000 {
+                        compatible = "allwinner,sun5i-a13-video-engine";
+                        reg = <0x01c0e000 0x1000>;
+                        clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
+                                 <&ccu CLK_DRAM_VE>;
+                        clock-names = "ahb", "mod", "ram";
+                        resets = <&ccu RST_VE>;
+                        interrupts = <53>;
+                        allwinner,sram = <&ve_sram 1>;
+                };
+
                 mmc0: mmc@1c0f000 {
                         compatible = "allwinner,sun5i-a13-mmc";
                         reg = <0x01c0f000 0x1000>;
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 9c52712af241..02e40da9f028 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -174,6 +174,21 @@
                 reg = <0x40000000 0x80000000>;
         };
 
+        reserved-memory {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                /* Address must be kept in the lower 256 MiBs of DRAM for VE. */
+                cma_pool: cma@4a000000 {
+                        compatible = "shared-dma-pool";
+                        size = <0x6000000>;
+                        alloc-ranges = <0x4a000000 0x6000000>;
+                        reusable;
+                        linux,cma-default;
+                };
+        };
+
         timer {
                 compatible = "arm,armv7-timer";
                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
@@ -479,6 +494,17 @@
                         };
                 };
 
+                video-codec@1c0e000 {
+                        compatible = "allwinner,sun7i-a20-video-engine";
+                        reg = <0x01c0e000 0x1000>;
+                        clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
+                                 <&ccu CLK_DRAM_VE>;
+                        clock-names = "ahb", "mod", "ram";
+                        resets = <&ccu RST_VE>;
+                        interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+                        allwinner,sram = <&ve_sram 1>;
+                };
+
                 mmc0: mmc@1c0f000 {
                         compatible = "allwinner,sun7i-a20-mmc";
                         reg = <0x01c0f000 0x1000>;
diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi
index 4e92741b24a7..c1cc8f09dd9a 100644
--- a/arch/arm/boot/dts/sun8i-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a33.dtsi
@@ -190,6 +190,21 @@
                 reg = <0x40000000 0x80000000>;
         };
 
+        reserved-memory {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                /* Address must be kept in the lower 256 MiBs of DRAM for VE. */
+                cma_pool: cma@4a000000 {
+                        compatible = "shared-dma-pool";
+                        size = <0x6000000>;
+                        alloc-ranges = <0x4a000000 0x6000000>;
+                        reusable;
+                        linux,cma-default;
+                };
+        };
+
         sound: sound {
                 compatible = "simple-audio-card";
                 simple-audio-card,name = "sun8i-a33-audio";
@@ -254,6 +269,17 @@
                         };
                 };
 
+                video-codec@01c0e000 {
+                        compatible = "allwinner,sun8i-a33-video-engine";
+                        reg = <0x01c0e000 0x1000>;
+                        clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
+                                 <&ccu CLK_DRAM_VE>;
+                        clock-names = "ahb", "mod", "ram";
+                        resets = <&ccu RST_BUS_VE>;
+                        interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+                        allwinner,sram = <&ve_sram 1>;
+                };
+
                 crypto: crypto-engine@1c15000 {
                         compatible = "allwinner,sun4i-a10-crypto";
                         reg = <0x01c15000 0x1000>;
diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
index c7ce4158d6c8..742d2946b08b 100644
--- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
@@ -191,6 +191,11 @@
         status = "okay";
 };
 
+&r_cir {
+        clock-frequency = <3000000>;
+        status = "okay";
+};
+
 &r_rsb {
         status = "okay";
 
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 00a02b037320..5617dd387fd3 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -990,6 +990,19 @@
                         reg = <0x1f01c00 0x400>;
                 };
 
+                r_cir: ir@1f02000 {
+                        compatible = "allwinner,sun8i-a83t-ir",
+                                "allwinner,sun5i-a13-ir";
+                        clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
+                        clock-names = "apb", "ir";
+                        resets = <&r_ccu RST_APB0_IR>;
+                        interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+                        reg = <0x01f02000 0x400>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&r_cir_pin>;
+                        status = "disabled";
+                };
+
                 r_pio: pinctrl@1f02c00 {
                         compatible = "allwinner,sun8i-a83t-r-pinctrl";
                         reg = <0x01f02c00 0x400>;
@@ -1002,6 +1015,11 @@
                         interrupt-controller;
                         #interrupt-cells = <3>;
 
+                        r_cir_pin: r-cir-pin {
+                                pins = "PL12";
+                                function = "s_cir_rx";
+                        };
+
                         r_rsb_pins: r-rsb-pins {
                                 pins = "PL0", "PL1";
                                 function = "s_rsb";
diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus-v1.2.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus-v1.2.dts
new file mode 100644
index 000000000000..fc4a8c3d084d
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus-v1.2.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 Chen-Yu Tsai <wens@csie.org>
+ */
+
+/dts-v1/;
+#include "sun8i-h3.dtsi"
+#include "sunxi-bananapi-m2-plus-v1.2.dtsi"
+
+/ {
+        model = "Banana Pi BPI-M2-Plus v1.2 H3";
+        compatible = "bananapi,bpi-m2-plus-v1.2", "allwinner,sun8i-h3";
+};
diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
index 30540dc8e0c5..195a75da13f1 100644
--- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
@@ -42,195 +42,9 @@
 
 /dts-v1/;
 #include "sun8i-h3.dtsi"
-#include "sunxi-common-regulators.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
+#include "sunxi-bananapi-m2-plus.dtsi"
 
 / {
-        model = "Banana Pi BPI-M2-Plus";
+        model = "Banana Pi BPI-M2-Plus H3";
         compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3";
-
-        aliases {
-                ethernet0 = &emac;
-                serial0 = &uart0;
-                serial1 = &uart1;
-        };
-
-        chosen {
-                stdout-path = "serial0:115200n8";
-        };
-
-        connector {
-                compatible = "hdmi-connector";
-                type = "a";
-
-                port {
-                        hdmi_con_in: endpoint {
-                                remote-endpoint = <&hdmi_out_con>;
-                        };
-                };
-        };
-
-        leds {
-                compatible = "gpio-leds";
-                pinctrl-names = "default";
-
-                pwr_led {
-                        label = "bananapi-m2-plus:red:pwr";
-                        gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
-                        default-state = "on";
-                };
-        };
-
-        gpio_keys {
-                compatible = "gpio-keys";
-                pinctrl-names = "default";
-
-                sw4 {
-                        label = "power";
-                        linux,code = <BTN_0>;
-                        gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
-                };
-        };
-
-        reg_gmac_3v3: gmac-3v3 {
-                      compatible = "regulator-fixed";
-                      regulator-name = "gmac-3v3";
-                      regulator-min-microvolt = <3300000>;
-                      regulator-max-microvolt = <3300000>;
-                      startup-delay-us = <100000>;
-                      enable-active-high;
-                      gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
-        };
-
-        wifi_pwrseq: wifi_pwrseq {
-                compatible = "mmc-pwrseq-simple";
-                pinctrl-names = "default";
-                reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
-        };
-};
-
-&de {
-        status = "okay";
-};
-
-&ehci0 {
-        status = "okay";
-};
-
-&ehci1 {
-        status = "okay";
-};
-
-&ehci2 {
-        status = "okay";
-};
-
-&emac {
-        pinctrl-names = "default";
-        pinctrl-0 = <&emac_rgmii_pins>;
-        phy-supply = <&reg_gmac_3v3>;
-        phy-handle = <&ext_rgmii_phy>;
-        phy-mode = "rgmii";
-
-        status = "okay";
-};
-
-&external_mdio {
-        ext_rgmii_phy: ethernet-phy@1 {
-                compatible = "ethernet-phy-ieee802.3-c22";
-                reg = <0>;
-        };
-};
-
-&hdmi {
-        status = "okay";
-};
-
-&hdmi_out {
-        hdmi_out_con: endpoint {
-                remote-endpoint = <&hdmi_con_in>;
-        };
-};
-
-&ir {
-        pinctrl-names = "default";
-        pinctrl-0 = <&ir_pins_a>;
-        status = "okay";
-};
-
-&mmc0 {
-        vmmc-supply = <&reg_vcc3v3>;
-        bus-width = <4>;
-        cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
-        status = "okay";
-};
-
-&mmc1 {
-        vmmc-supply = <&reg_vcc3v3>;
-        vqmmc-supply = <&reg_vcc3v3>;
-        mmc-pwrseq = <&wifi_pwrseq>;
-        bus-width = <4>;
-        non-removable;
-        status = "okay";
-
-        brcmf: wifi@1 {
-                reg = <1>;
-                compatible = "brcm,bcm4329-fmac";
-                interrupt-parent = <&pio>;
-                interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */
-                interrupt-names = "host-wake";
-        };
-};
-
-&mmc2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mmc2_8bit_pins>;
-        vmmc-supply = <&reg_vcc3v3>;
-        vqmmc-supply = <&reg_vcc3v3>;
-        bus-width = <8>;
-        non-removable;
-        status = "okay";
-};
-
-&ohci0 {
-        status = "okay";
-};
-
-&ohci1 {
-        status = "okay";
-};
-
-&ohci2 {
-        status = "okay";
-};
-
-&reg_usb0_vbus {
-        gpio = <&pio 3 11 GPIO_ACTIVE_HIGH>; /* PD11 */
-        status = "okay";
-};
-
-&uart0 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&uart0_pins_a>;
-        status = "okay";
-};
-
-&uart1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
-        status = "okay";
-};
-
-&usb_otg {
-        dr_mode = "otg";
-        status = "okay";
-};
-
-&usbphy {
-        usb0_id_det-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
-        usb0_vbus-supply = <&reg_usb0_vbus>;
-        /* USB host VBUS is on as long as VCC-IO is on */
-        status = "okay";
 };
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-zero-plus2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-zero-plus2.dts
new file mode 100644
index 000000000000..c834048c325e
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-zero-plus2.dts
@@ -0,0 +1,140 @@
+/*
+ * Copyright (C) 2017 Jagan Teki <jteki@openedev.com>
+ * Copyright (C) 2018 Diego Rondini <diego.rondini@kynetics.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "sun8i-h3.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+        model = "OrangePi Zero Plus2 H3";
+        compatible = "xunlong,orangepi-zero-plus2-h3", "allwinner,sun8i-h3";
+
+        aliases {
+                serial0 = &uart0;
+        };
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+
+        connector {
+                compatible = "hdmi-connector";
+                type = "a";
+
+                port {
+                        hdmi_con_in: endpoint {
+                                remote-endpoint = <&hdmi_out_con>;
+                        };
+                };
+        };
+
+        reg_vcc3v3: vcc3v3 {
+                compatible = "regulator-fixed";
+                regulator-name = "vcc3v3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
+
+        wifi_pwrseq: wifi_pwrseq {
+                compatible = "mmc-pwrseq-simple";
+                pinctrl-names = "default";
+                reset-gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */
+                post-power-on-delay-ms = <200>;
+        };
+};
+
+&de {
+        status = "okay";
+};
+
+&hdmi {
+        status = "okay";
+};
+
+&hdmi_out {
+        hdmi_out_con: endpoint {
+                remote-endpoint = <&hdmi_con_in>;
+        };
+};
+
+&mmc0 {
+        vmmc-supply = <&reg_vcc3v3>;
+        bus-width = <4>;
+        cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
+        status = "okay";
+};
+
+&mmc1 {
+        vmmc-supply = <&reg_vcc3v3>;
+        vqmmc-supply = <&reg_vcc3v3>;
+        mmc-pwrseq = <&wifi_pwrseq>;
+        bus-width = <4>;
+        non-removable;
+        status = "okay";
+
+        brcmf: wifi@1 {
+                reg = <1>;
+                compatible = "brcm,bcm4329-fmac";
+                interrupt-parent = <&r_pio>;
+                interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>;  /* PL7 */
+                interrupt-names = "host-wake";
+        };
+};
+
+&mmc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc2_8bit_pins>;
+        vmmc-supply = <&reg_vcc3v3>;
+        bus-width = <8>;
+        non-removable;
+        cap-mmc-hw-reset;
+        status = "okay";
+};
+
+&uart0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart0_pins_a>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index f0096074a467..3ecfabb10151 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -119,6 +119,20 @@
                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
         };
 
+        reserved-memory {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                cma_pool: cma@4a000000 {
+                        compatible = "shared-dma-pool";
+                        size = <0x6000000>;
+                        alloc-ranges = <0x4a000000 0x6000000>;
+                        reusable;
+                        linux,cma-default;
+                };
+        };
+
         soc {
                 system-control@1c00000 {
                         compatible = "allwinner,sun8i-h3-system-control";
@@ -142,6 +156,17 @@
                         };
                 };
 
+                video-codec@01c0e000 {
+                        compatible = "allwinner,sun8i-h3-video-engine";
+                        reg = <0x01c0e000 0x1000>;
+                        clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
+                                 <&ccu CLK_DRAM_VE>;
+                        clock-names = "ahb", "mod", "ram";
+                        resets = <&ccu RST_BUS_VE>;
+                        interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+                        allwinner,sram = <&ve_sram 1>;
+                };
+
                 mali: gpu@1c40000 {
                         compatible = "allwinner,sun8i-h3-mali", "arm,mali-400";
                         reg = <0x01c40000 0x10000>;
diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
index c39b9169ea64..438b7b44dab3 100644
--- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
+++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
@@ -105,6 +105,12 @@
         };
 };
 
+&ahci {
+        ahci-supply = <&reg_dldo4>;
+        phy-supply = <&reg_eldo3>;
+        status = "okay";
+};
+
 &de {
         status = "okay";
 };
@@ -159,8 +165,7 @@
 &mmc0 {
         vmmc-supply = <&reg_dcdc1>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; /* PH13 */
-        cd-inverted;
+        cd-gpios = <&pio 7 13 GPIO_ACTIVE_LOW>; /* PH13 */
         status = "okay";
 };
 
@@ -251,6 +256,18 @@
         regulator-name = "vcc-wifi";
 };
 
+&reg_dldo4 {
+        regulator-min-microvolt = <2500000>;
+        regulator-max-microvolt = <2500000>;
+        regulator-name = "vdd2v5-sata";
+};
+
+&reg_eldo3 {
+        regulator-min-microvolt = <1200000>;
+        regulator-max-microvolt = <1200000>;
+        regulator-name = "vdd1v2-sata";
+};
+
 &tcon_tv0 {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index 5f547c161baf..6f4c9ca5a3ee 100644
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -529,6 +529,19 @@
                         #size-cells = <0>;
                 };
 
+                ahci: sata@1c18000 {
+                        compatible = "allwinner,sun8i-r40-ahci";
+                        reg = <0x01c18000 0x1000>;
+                        interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
+                        resets = <&ccu RST_BUS_SATA>;
+                        resets-name = "ahci";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+
+                };
+
                 gmac: ethernet@1c50000 {
                         compatible = "allwinner,sun8i-r40-gmac";
                         syscon = <&ccu>;
diff --git a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi
index 880096c7e252..5e8a95af89b8 100644
--- a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi
+++ b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi
@@ -69,7 +69,8 @@
          */
         clock-frequency = <400000>;
 
-        touchscreen: touchscreen@0 {
+        touchscreen: touchscreen@40 {
+                reg = <0x40>;
                 interrupt-parent = <&pio>;
                 interrupts = <1 5 IRQ_TYPE_EDGE_FALLING>; /* PB5 */
                 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
index 35859d8f3267..bf97f6244c23 100644
--- a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
+++ b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
@@ -95,7 +95,7 @@
 &i2c0 {
         status = "okay";
 
-        axp22x: pmic@68 {
+        axp22x: pmic@34 {
                 compatible = "x-powers,axp221";
                 reg = <0x34>;
                 interrupt-parent = <&nmi_intc>;
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index 25591d6883ef..d9532fb1ef65 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -1196,7 +1196,7 @@
                         };
                 };
 
-                r_rsb: i2c@8003400 {
+                r_rsb: rsb@8003400 {
                         compatible = "allwinner,sun8i-a23-rsb";
                         reg = <0x08003400 0x400>;
                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi b/arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi
new file mode 100644
index 000000000000..53edd1faee99
--- /dev/null
+++ b/arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 Chen-Yu Tsai <wens@csie.org>
+ */
+
+#include "sunxi-bananapi-m2-plus.dtsi"
+
+/ {
+        /*
+         * Bananapi M2+ v1.2 uses a GPIO line to change the effective
+         * resistance on the CPU regulator's feedback pin.
+         */
+        reg_vdd_cpux: vdd-cpux {
+                compatible = "regulator-gpio";
+                regulator-name = "vdd-cpux";
+                regulator-type = "voltage";
+                regulator-boot-on;
+                regulator-always-on;
+                regulator-min-microvolt = <1100000>;
+                regulator-max-microvolt = <1300000>;
+                regulator-ramp-delay = <50>; /* 4ms */
+                gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */
+                gpios-states = <0x1>;
+                states = <1100000 0x0
+                          1300000 0x1>;
+        };
+};
+
+&cpu0 {
+        cpu-supply = <&reg_vdd_cpux>;
+};
diff --git a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi
new file mode 100644
index 000000000000..b3283aeb5b7d
--- /dev/null
+++ b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi
@@ -0,0 +1,231 @@
+/*
+ * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+        aliases {
+                ethernet0 = &emac;
+                serial0 = &uart0;
+                serial1 = &uart1;
+        };
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+
+        connector {
+                compatible = "hdmi-connector";
+                type = "a";
+
+                port {
+                        hdmi_con_in: endpoint {
+                                remote-endpoint = <&hdmi_out_con>;
+                        };
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+
+                pwr_led {
+                        label = "bananapi-m2-plus:red:pwr";
+                        gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
+                        default-state = "on";
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                pinctrl-names = "default";
+
+                sw4 {
+                        label = "power";
+                        linux,code = <BTN_0>;
+                        gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+                };
+        };
+
+        reg_gmac_3v3: gmac-3v3 {
+                      compatible = "regulator-fixed";
+                      regulator-name = "gmac-3v3";
+                      regulator-min-microvolt = <3300000>;
+                      regulator-max-microvolt = <3300000>;
+                      startup-delay-us = <100000>;
+                      enable-active-high;
+                      gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
+        };
+
+        wifi_pwrseq: wifi_pwrseq {
+                compatible = "mmc-pwrseq-simple";
+                pinctrl-names = "default";
+                reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
+        };
+};
+
+&de {
+        status = "okay";
+};
+
+&ehci0 {
+        status = "okay";
+};
+
+&ehci1 {
+        status = "okay";
+};
+
+&ehci2 {
+        status = "okay";
+};
+
+&emac {
+        pinctrl-names = "default";
+        pinctrl-0 = <&emac_rgmii_pins>;
+        phy-supply = <&reg_gmac_3v3>;
+        phy-handle = <&ext_rgmii_phy>;
+        phy-mode = "rgmii";
+
+        status = "okay";
+};
+
+&external_mdio {
+        ext_rgmii_phy: ethernet-phy@1 {
+                compatible = "ethernet-phy-ieee802.3-c22";
+                reg = <1>;
+        };
+};
+
+&hdmi {
+        status = "okay";
+};
+
+&hdmi_out {
+        hdmi_out_con: endpoint {
+                remote-endpoint = <&hdmi_con_in>;
+        };
+};
+
+&ir {
+        pinctrl-names = "default";
+        pinctrl-0 = <&ir_pins_a>;
+        status = "okay";
+};
+
+&mmc0 {
+        vmmc-supply = <&reg_vcc3v3>;
+        bus-width = <4>;
+        cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+        status = "okay";
+};
+
+&mmc1 {
+        vmmc-supply = <&reg_vcc3v3>;
+        vqmmc-supply = <&reg_vcc3v3>;
+        mmc-pwrseq = <&wifi_pwrseq>;
+        bus-width = <4>;
+        non-removable;
+        status = "okay";
+
+        brcmf: wifi@1 {
+                reg = <1>;
+                compatible = "brcm,bcm4329-fmac";
+                interrupt-parent = <&pio>;
+                interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */
+                interrupt-names = "host-wake";
+        };
+};
+
+&mmc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc2_8bit_pins>;
+        vmmc-supply = <&reg_vcc3v3>;
+        vqmmc-supply = <&reg_vcc3v3>;
+        bus-width = <8>;
+        non-removable;
+        status = "okay";
+};
+
+&ohci0 {
+        status = "okay";
+};
+
+&ohci1 {
+        status = "okay";
+};
+
+&ohci2 {
+        status = "okay";
+};
+
+&reg_usb0_vbus {
+        gpio = <&pio 3 11 GPIO_ACTIVE_HIGH>; /* PD11 */
+        status = "okay";
+};
+
+&uart0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart0_pins_a>;
+        status = "okay";
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+        status = "okay";
+};
+
+&usb_otg {
+        dr_mode = "otg";
+        status = "okay";
+};
+
+&usbphy {
+        usb0_id_det-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
+        usb0_vbus-supply = <&reg_usb0_vbus>;
+        /* USB host VBUS is on as long as VCC-IO is on */
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index fc6131315c47..4b1530ebe427 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -816,7 +816,7 @@
                         clock-names = "apb", "ir";
                         resets = <&r_ccu RST_APB0_IR>;
                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-                        reg = <0x01f02000 0x40>;
+                        reg = <0x01f02000 0x400>;
                         status = "disabled";
                 };
 
diff --git a/arch/arm/boot/dts/tegra124-apalis-eval.dts b/arch/arm/boot/dts/tegra124-apalis-eval.dts
index a6ad759dddb4..eaee10ef6512 100644
--- a/arch/arm/boot/dts/tegra124-apalis-eval.dts
+++ b/arch/arm/boot/dts/tegra124-apalis-eval.dts
@@ -72,6 +72,7 @@
         host1x@50000000 {
                 hdmi@54280000 {
                         status = "okay";
+                        hdmi-supply = <&reg_5v0>;
                 };
         };
 
@@ -122,7 +123,7 @@
         /*
          * GEN2_I2C: I2C2_SDA/SCL (DDC) on MXM3 pin 205/207 (e.g. display EDID)
          */
-        hdmi_ddc: i2c@7000c400 {
+        i2c@7000c400 {
                 status = "okay";
         };
 
@@ -141,29 +142,19 @@
         spi@7000d400 {
                 status = "okay";
                 spi-max-frequency = <50000000>;
-
-                spidev0: spidev@0 {
-                        compatible = "spidev";
-                        reg = <0>;
-                        spi-max-frequency = <50000000>;
-                };
         };
 
         /* SPI4: Apalis SPI2 */
         spi@7000da00 {
                 status = "okay";
                 spi-max-frequency = <50000000>;
-
-                spidev1: spidev@0 {
-                        compatible = "spidev";
-                        reg = <0>;
-                        spi-max-frequency = <50000000>;
-                };
         };
 
         /* Apalis Serial ATA */
         sata@70020000 {
                 status = "okay";
+                target-5v-supply = <&reg_5v0>;
+                target-12v-supply = <&reg_12v0>;
         };
 
         hda@70030000 {
@@ -177,18 +168,18 @@
         /* Apalis MMC1 */
         sdhci@700b0000 {
                 status = "okay";
+                bus-width = <4>;
                 /* MMC1_CD# */
                 cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
-                bus-width = <4>;
                 vqmmc-supply = <&vddio_sdmmc1>;
         };
 
         /* Apalis SD1 */
         sdhci@700b0400 {
                 status = "okay";
+                bus-width = <4>;
                 /* SD1_CD# */
                 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
-                bus-width = <4>;
                 vqmmc-supply = <&vddio_sdmmc3>;
         };
 
@@ -225,11 +216,12 @@
 
         backlight: backlight {
                 compatible = "pwm-backlight";
-                pwms = <&pwm 3 5000000>; /* BKL1_PWM */
                 brightness-levels = <255 231 223 207 191 159 127 0>;
                 default-brightness-level = <6>;
                 /* BKL1_ON */
                 enable-gpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_HIGH>;
+                power-supply = <&reg_3v3>;
+                pwms = <&pwm 3 5000000>; /* BKL1_PWM */
         };
 
         gpio-keys {
@@ -244,6 +236,13 @@
                 };
         };
 
+        reg_3v3: regulator-3v3 {
+                compatible = "regulator-fixed";
+                regulator-name = "3.3V_SW";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
+
         reg_5v0: regulator-5v0 {
                 compatible = "regulator-fixed";
                 regulator-name = "5V_SW";
@@ -251,6 +250,13 @@
                 regulator-max-microvolt = <5000000>;
         };
 
+        reg_12v0: regulator-12v0 {
+                compatible = "regulator-fixed";
+                regulator-name = "12V_SW";
+                regulator-min-microvolt = <12000000>;
+                regulator-max-microvolt = <12000000>;
+        };
+
         /* USBO1_EN */
         reg_usbo1_vbus: regulator-usbo1-vbus {
                 compatible = "regulator-fixed";
@@ -276,7 +282,7 @@
 
 &gpio {
         /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */
-        pex_perst_n {
+        pex-perst-n {
                 gpio-hog;
                 gpios = <TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
                 output-high;
diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts
index 8a8d5fa0ecd1..7961eb4bd803 100644
--- a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts
+++ b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts
@@ -11,7 +11,8 @@
 / {
         model = "Toradex Apalis TK1 on Apalis Evaluation Board";
         compatible = "toradex,apalis-tk1-v1.2-eval", "toradex,apalis-tk1-eval",
-                     "toradex,apalis-tk1", "nvidia,tegra124";
+                     "toradex,apalis-tk1-v1.2", "toradex,apalis-tk1",
+                     "nvidia,tegra124";
 
         aliases {
                 rtc0 = "/i2c@7000c000/rtc@68";
@@ -36,6 +37,7 @@
         host1x@50000000 {
                 hdmi@54280000 {
                         status = "okay";
+                        hdmi-supply = <&reg_5v0>;
                 };
         };
 
@@ -98,7 +100,7 @@
          * I2C4 (DDC): I2C4_SDA/SCL (DDC) on MXM3 pin 205/207
          * (e.g. display EDID)
          */
-        hdmi_ddc: i2c@7000c700 {
+        i2c@7000c700 {
                 status = "okay";
         };
 
@@ -106,29 +108,19 @@
         spi@7000d400 {
                 status = "okay";
                 spi-max-frequency = <50000000>;
-
-                spidev0: spidev@0 {
-                        compatible = "spidev";
-                        reg = <0>;
-                        spi-max-frequency = <50000000>;
-                };
         };
 
         /* SPI4: Apalis SPI2 */
         spi@7000da00 {
                 status = "okay";
                 spi-max-frequency = <50000000>;
-
-                spidev1: spidev@0 {
-                        compatible = "spidev";
-                        reg = <0>;
-                        spi-max-frequency = <50000000>;
-                };
         };
 
         /* Apalis Serial ATA */
         sata@70020000 {
                 status = "okay";
+                target-5v-supply = <&reg_5v0>;
+                target-12v-supply = <&reg_12v0>;
         };
 
         hda@70030000 {
@@ -142,18 +134,18 @@
         /* Apalis MMC1 */
         sdhci@700b0000 {
                 status = "okay";
+                bus-width = <4>;
                 /* MMC1_CD# */
                 cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
-                bus-width = <4>;
                 vqmmc-supply = <&vddio_sdmmc1>;
         };
 
         /* Apalis SD1 */
         sdhci@700b0400 {
                 status = "okay";
+                bus-width = <4>;
                 /* SD1_CD# */
                 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
-                bus-width = <4>;
                 vqmmc-supply = <&vddio_sdmmc3>;
         };
 
@@ -190,11 +182,12 @@
 
         backlight: backlight {
                 compatible = "pwm-backlight";
-                pwms = <&pwm 3 5000000>; /* BKL1_PWM */
                 brightness-levels = <255 231 223 207 191 159 127 0>;
                 default-brightness-level = <6>;
                 /* BKL1_ON */
                 enable-gpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_HIGH>;
+                power-supply = <&reg_3v3>;
+                pwms = <&pwm 3 5000000>; /* BKL1_PWM */
         };
 
         gpio-keys {
@@ -209,6 +202,13 @@
                 };
         };
 
+        reg_3v3: regulator-3v3 {
+                compatible = "regulator-fixed";
+                regulator-name = "3.3V_SW";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
+
         reg_5v0: regulator-5v0 {
                 compatible = "regulator-fixed";
                 regulator-name = "5V_SW";
@@ -216,6 +216,13 @@
                 regulator-max-microvolt = <5000000>;
         };
 
+        reg_12v0: regulator-12v0 {
+                compatible = "regulator-fixed";
+                regulator-name = "12V_SW";
+                regulator-min-microvolt = <12000000>;
+                regulator-max-microvolt = <12000000>;
+        };
+
         /* USBO1_EN */
         reg_usbo1_vbus: regulator-usbo1-vbus {
                 compatible = "regulator-fixed";
@@ -241,7 +248,7 @@
 
 &gpio {
         /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */
-        pex_perst_n {
+        pex-perst-n {
                 gpio-hog;
                 gpios = <TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
                 output-high;
diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
index 573aaa50fff1..367eb8c86098 100644
--- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
+++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
@@ -11,23 +11,19 @@
  * Compatible for Revisions 2GB: V1.2A
  */
 / {
-        model = "Toradex Apalis TK1";
-        compatible = "toradex,apalis-tk1-v1.2", "toradex,apalis-tk1",
-                     "nvidia,tegra124";
-
         memory@80000000 {
                 reg = <0x0 0x80000000 0x0 0x80000000>;
         };
 
         pcie@1003000 {
                 status = "okay";
-                avddio-pex-supply = <&vdd_1v05>;
-                avdd-pex-pll-supply = <&vdd_1v05>;
-                avdd-pll-erefe-supply = <&avdd_1v05>;
-                dvddio-pex-supply = <&vdd_1v05>;
-                hvdd-pex-pll-e-supply = <&reg_3v3>;
-                hvdd-pex-supply = <&reg_3v3>;
-                vddio-pex-ctl-supply = <&reg_3v3>;
+                avddio-pex-supply = <&reg_1v05_vdd>;
+                avdd-pex-pll-supply = <&reg_1v05_vdd>;
+                avdd-pll-erefe-supply = <&reg_1v05_avdd>;
+                dvddio-pex-supply = <&reg_1v05_vdd>;
+                hvdd-pex-pll-e-supply = <&reg_module_3v3>;
+                hvdd-pex-supply = <&reg_module_3v3>;
+                vddio-pex-ctl-supply = <&reg_module_3v3>;
 
                 /* Apalis PCIe (additional lane Apalis type specific) */
                 pci@1,0 {
@@ -42,16 +38,21 @@
                         phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
                         phy-names = "pcie-0";
                         status = "okay";
+
+                        pcie@0 {
+                                reg = <0 0 0 0 0>;
+                                local-mac-address = [00 00 00 00 00 00];
+                        };
                 };
         };
 
         host1x@50000000 {
                 hdmi@54280000 {
-                        pll-supply = <&reg_1v05_avdd_hdmi_pll>;
-                        vdd-supply = <&reg_3v3_avdd_hdmi>;
                         nvidia,ddc-i2c-bus = <&hdmi_ddc>;
                         nvidia,hpd-gpio =
                                 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
+                        pll-supply = <&reg_1v05_avdd_hdmi_pll>;
+                        vdd-supply = <&reg_3v3_avdd_hdmi>;
                 };
         };
 
@@ -60,44 +61,44 @@
                  * Node left disabled on purpose - the bootloader will enable
                  * it after having set the VPR up
                  */
-                vdd-supply = <&vdd_gpu>;
+                vdd-supply = <&reg_vdd_gpu>;
         };
 
-        pinmux: pinmux@70000868 {
+        pinmux@70000868 {
                 pinctrl-names = "default";
                 pinctrl-0 = <&state_default>;
 
                 state_default: pinmux {
                         /* Analogue Audio (On-module) */
-                        dap3_fs_pp0 {
+                        dap3-fs-pp0 {
                                 nvidia,pins = "dap3_fs_pp0";
                                 nvidia,function = "i2s2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        dap3_din_pp1 {
+                        dap3-din-pp1 {
                                 nvidia,pins = "dap3_din_pp1";
                                 nvidia,function = "i2s2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        dap3_dout_pp2 {
+                        dap3-dout-pp2 {
                                 nvidia,pins = "dap3_dout_pp2";
                                 nvidia,function = "i2s2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        dap3_sclk_pp3 {
+                        dap3-sclk-pp3 {
                                 nvidia,pins = "dap3_sclk_pp3";
                                 nvidia,function = "i2s2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        dap_mclk1_pw4 {
+                        dap-mclk1-pw4 {
                                 nvidia,pins = "dap_mclk1_pw4";
                                 nvidia,function = "extperiph1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -124,7 +125,7 @@
                         };
 
                         /* Apalis CAM1_MCLK */
-                        cam_mclk_pcc0 {
+                        cam-mclk-pcc0 {
                                 nvidia,pins = "cam_mclk_pcc0";
                                 nvidia,function = "vi_alt3";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -133,28 +134,28 @@
                         };
 
                         /* Apalis Digital Audio */
-                        dap2_fs_pa2 {
+                        dap2-fs-pa2 {
                                 nvidia,pins = "dap2_fs_pa2";
                                 nvidia,function = "hda";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        dap2_sclk_pa3 {
+                        dap2-sclk-pa3 {
                                 nvidia,pins = "dap2_sclk_pa3";
                                 nvidia,function = "hda";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        dap2_din_pa4 {
+                        dap2-din-pa4 {
                                 nvidia,pins = "dap2_din_pa4";
                                 nvidia,function = "hda";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        dap2_dout_pa5 {
+                        dap2-dout-pa5 {
                                 nvidia,pins = "dap2_dout_pa5";
                                 nvidia,function = "hda";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -167,7 +168,7 @@
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        clk3_out_pee0 {
+                        clk3-out-pee0 {
                                 nvidia,pins = "clk3_out_pee0";
                                 nvidia,function = "extperiph3";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -176,7 +177,7 @@
                         };
 
                         /* Apalis GPIO */
-                        usb_vbus_en0_pn4 {
+                        usb-vbus-en0-pn4 {
                                 nvidia,pins = "usb_vbus_en0_pn4";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -184,7 +185,7 @@
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
                         };
-                        usb_vbus_en1_pn5 {
+                        usb-vbus-en1-pn5 {
                                 nvidia,pins = "usb_vbus_en1_pn5";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -192,35 +193,35 @@
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
                         };
-                        pex_l0_rst_n_pdd1 {
+                        pex-l0-rst-n-pdd1 {
                                 nvidia,pins = "pex_l0_rst_n_pdd1";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        pex_l0_clkreq_n_pdd2 {
+                        pex-l0-clkreq-n-pdd2 {
                                 nvidia,pins = "pex_l0_clkreq_n_pdd2";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        pex_l1_rst_n_pdd5 {
+                        pex-l1-rst-n-pdd5 {
                                 nvidia,pins = "pex_l1_rst_n_pdd5";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        pex_l1_clkreq_n_pdd6 {
+                        pex-l1-clkreq-n-pdd6 {
                                 nvidia,pins = "pex_l1_clkreq_n_pdd6";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        dp_hpd_pff0 {
+                        dp-hpd-pff0 {
                                 nvidia,pins = "dp_hpd_pff0";
                                 nvidia,function = "dp";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -244,7 +245,7 @@
                         };
 
                         /* Apalis HDMI1_CEC */
-                        hdmi_cec_pee3 {
+                        hdmi-cec-pee3 {
                                 nvidia,pins = "hdmi_cec_pee3";
                                 nvidia,function = "cec";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -254,7 +255,7 @@
                         };
 
                         /* Apalis HDMI1_HPD */
-                        hdmi_int_pn7 {
+                        hdmi-int-pn7 {
                                 nvidia,pins = "hdmi_int_pn7";
                                 nvidia,function = "rsvd1";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
@@ -264,7 +265,7 @@
                         };
 
                         /* Apalis I2C1 */
-                        gen1_i2c_scl_pc4 {
+                        gen1-i2c-scl-pc4 {
                                 nvidia,pins = "gen1_i2c_scl_pc4";
                                 nvidia,function = "i2c1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -272,7 +273,7 @@
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
                         };
-                        gen1_i2c_sda_pc5 {
+                        gen1-i2c-sda-pc5 {
                                 nvidia,pins = "gen1_i2c_sda_pc5";
                                 nvidia,function = "i2c1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -282,7 +283,7 @@
                         };
 
                         /* Apalis I2C3 (CAM) */
-                        cam_i2c_scl_pbb1 {
+                        cam-i2c-scl-pbb1 {
                                 nvidia,pins = "cam_i2c_scl_pbb1";
                                 nvidia,function = "i2c3";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -290,7 +291,7 @@
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
                         };
-                        cam_i2c_sda_pbb2 {
+                        cam-i2c-sda-pbb2 {
                                 nvidia,pins = "cam_i2c_sda_pbb2";
                                 nvidia,function = "i2c3";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -300,7 +301,7 @@
                         };
 
                         /* Apalis I2C4 (DDC) */
-                        ddc_scl_pv4 {
+                        ddc-scl-pv4 {
                                 nvidia,pins = "ddc_scl_pv4";
                                 nvidia,function = "i2c4";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -308,7 +309,7 @@
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                 nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
                         };
-                        ddc_sda_pv5 {
+                        ddc-sda-pv5 {
                                 nvidia,pins = "ddc_sda_pv5";
                                 nvidia,function = "i2c4";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -318,77 +319,77 @@
                         };
 
                         /* Apalis MMC1 */
-                        sdmmc1_cd_n_pv3 { /* CD# GPIO */
+                        sdmmc1-cd-n-pv3 { /* CD# GPIO */
                                 nvidia,pins = "sdmmc1_wp_n_pv3";
                                 nvidia,function = "sdmmc1";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        clk2_out_pw5 { /* D5 GPIO */
+                        clk2-out-pw5 { /* D5 GPIO */
                                 nvidia,pins = "clk2_out_pw5";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc1_dat3_py4 {
+                        sdmmc1-dat3-py4 {
                                 nvidia,pins = "sdmmc1_dat3_py4";
                                 nvidia,function = "sdmmc1";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc1_dat2_py5 {
+                        sdmmc1-dat2-py5 {
                                 nvidia,pins = "sdmmc1_dat2_py5";
                                 nvidia,function = "sdmmc1";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc1_dat1_py6 {
+                        sdmmc1-dat1-py6 {
                                 nvidia,pins = "sdmmc1_dat1_py6";
                                 nvidia,function = "sdmmc1";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc1_dat0_py7 {
+                        sdmmc1-dat0-py7 {
                                 nvidia,pins = "sdmmc1_dat0_py7";
                                 nvidia,function = "sdmmc1";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc1_clk_pz0 {
+                        sdmmc1-clk-pz0 {
                                 nvidia,pins = "sdmmc1_clk_pz0";
                                 nvidia,function = "sdmmc1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc1_cmd_pz1 {
+                        sdmmc1-cmd-pz1 {
                                 nvidia,pins = "sdmmc1_cmd_pz1";
                                 nvidia,function = "sdmmc1";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        clk2_req_pcc5 { /* D4 GPIO */
+                        clk2-req-pcc5 { /* D4 GPIO */
                                 nvidia,pins = "clk2_req_pcc5";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc3_clk_lb_in_pee5 { /* D6 GPIO */
+                        sdmmc3-clk-lb-in-pee5 { /* D6 GPIO */
                                 nvidia,pins = "sdmmc3_clk_lb_in_pee5";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        usb_vbus_en2_pff1 { /* D7 GPIO */
+                        usb-vbus-en2-pff1 { /* D7 GPIO */
                                 nvidia,pins = "usb_vbus_en2_pff1";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -428,7 +429,7 @@
                         };
 
                         /* Apalis SATA1_ACT# */
-                        dap1_dout_pn2 {
+                        dap1-dout-pn2 {
                                 nvidia,pins = "dap1_dout_pn2";
                                 nvidia,function = "gmi";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -437,49 +438,49 @@
                         };
 
                         /* Apalis SD1 */
-                        sdmmc3_clk_pa6 {
+                        sdmmc3-clk-pa6 {
                                 nvidia,pins = "sdmmc3_clk_pa6";
                                 nvidia,function = "sdmmc3";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc3_cmd_pa7 {
+                        sdmmc3-cmd-pa7 {
                                 nvidia,pins = "sdmmc3_cmd_pa7";
                                 nvidia,function = "sdmmc3";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc3_dat3_pb4 {
+                        sdmmc3-dat3-pb4 {
                                 nvidia,pins = "sdmmc3_dat3_pb4";
                                 nvidia,function = "sdmmc3";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc3_dat2_pb5 {
+                        sdmmc3-dat2-pb5 {
                                 nvidia,pins = "sdmmc3_dat2_pb5";
                                 nvidia,function = "sdmmc3";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc3_dat1_pb6 {
+                        sdmmc3-dat1-pb6 {
                                 nvidia,pins = "sdmmc3_dat1_pb6";
                                 nvidia,function = "sdmmc3";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc3_dat0_pb7 {
+                        sdmmc3-dat0-pb7 {
                                 nvidia,pins = "sdmmc3_dat0_pb7";
                                 nvidia,function = "sdmmc3";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc3_cd_n_pv2 { /* CD# GPIO */
+                        sdmmc3-cd-n-pv2 { /* CD# GPIO */
                                 nvidia,pins = "sdmmc3_cd_n_pv2";
                                 nvidia,function = "rsvd3";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
@@ -488,14 +489,14 @@
                         };
 
                         /* Apalis SPDIF */
-                        spdif_out_pk5 {
+                        spdif-out-pk5 {
                                 nvidia,pins = "spdif_out_pk5";
                                 nvidia,function = "spdif";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        spdif_in_pk6 {
+                        spdif-in-pk6 {
                                 nvidia,pins = "spdif_in_pk6";
                                 nvidia,function = "spdif";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -504,28 +505,28 @@
                         };
 
                         /* Apalis SPI1 */
-                        ulpi_clk_py0 {
+                        ulpi-clk-py0 {
                                 nvidia,pins = "ulpi_clk_py0";
                                 nvidia,function = "spi1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        ulpi_dir_py1 {
+                        ulpi-dir-py1 {
                                 nvidia,pins = "ulpi_dir_py1";
                                 nvidia,function = "spi1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        ulpi_nxt_py2 {
+                        ulpi-nxt-py2 {
                                 nvidia,pins = "ulpi_nxt_py2";
                                 nvidia,function = "spi1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        ulpi_stp_py3 {
+                        ulpi-stp-py3 {
                                 nvidia,pins = "ulpi_stp_py3";
                                 nvidia,function = "spi1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -578,42 +579,42 @@
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        uart1_txd_pu0 {
+                        uart1-txd-pu0 {
                                 nvidia,pins = "pu0";
                                 nvidia,function = "uarta";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        uart1_rxd_pu1 {
+                        uart1-rxd-pu1 {
                                 nvidia,pins = "pu1";
                                 nvidia,function = "uarta";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        uart1_cts_n_pu2 {
+                        uart1-cts-n-pu2 {
                                 nvidia,pins = "pu2";
                                 nvidia,function = "uarta";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        uart1_rts_n_pu3 {
+                        uart1-rts-n-pu3 {
                                 nvidia,pins = "pu3";
                                 nvidia,function = "uarta";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        uart3_cts_n_pa1 { /* DSR GPIO */
+                        uart3-cts-n-pa1 { /* DSR GPIO */
                                 nvidia,pins = "uart3_cts_n_pa1";
                                 nvidia,function = "gmi";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        uart3_rts_n_pc0 { /* DTR GPIO */
+                        uart3-rts-n-pc0 { /* DTR GPIO */
                                 nvidia,pins = "uart3_rts_n_pc0";
                                 nvidia,function = "gmi";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -622,28 +623,28 @@
                         };
 
                         /* Apalis UART2 */
-                        uart2_txd_pc2 {
+                        uart2-txd-pc2 {
                                 nvidia,pins = "uart2_txd_pc2";
                                 nvidia,function = "irda";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        uart2_rxd_pc3 {
+                        uart2-rxd-pc3 {
                                 nvidia,pins = "uart2_rxd_pc3";
                                 nvidia,function = "irda";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        uart2_cts_n_pj5 {
+                        uart2-cts-n-pj5 {
                                 nvidia,pins = "uart2_cts_n_pj5";
                                 nvidia,function = "uartb";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        uart2_rts_n_pj6 {
+                        uart2-rts-n-pj6 {
                                 nvidia,pins = "uart2_rts_n_pj6";
                                 nvidia,function = "uartb";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -652,14 +653,14 @@
                         };
 
                         /* Apalis UART3 */
-                        uart3_txd_pw6 {
+                        uart3-txd-pw6 {
                                 nvidia,pins = "uart3_txd_pw6";
                                 nvidia,function = "uartc";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        uart3_rxd_pw7 {
+                        uart3-rxd-pw7 {
                                 nvidia,pins = "uart3_rxd_pw7";
                                 nvidia,function = "uartc";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -668,14 +669,14 @@
                         };
 
                         /* Apalis UART4 */
-                        uart4_rxd_pb0 {
+                        uart4-rxd-pb0 {
                                 nvidia,pins = "pb0";
                                 nvidia,function = "uartd";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        uart4_txd_pj7 {
+                        uart4-txd-pj7 {
                                 nvidia,pins = "pj7";
                                 nvidia,function = "uartd";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -684,7 +685,7 @@
                         };
 
                         /* Apalis USBH_EN */
-                        gen2_i2c_sda_pt6 {
+                        gen2-i2c-sda-pt6 {
                                 nvidia,pins = "gen2_i2c_sda_pt6";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -703,7 +704,7 @@
                         };
 
                         /* Apalis USBO1_EN */
-                        gen2_i2c_scl_pt5 {
+                        gen2-i2c-scl-pt5 {
                                 nvidia,pins = "gen2_i2c_scl_pt5";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -722,7 +723,7 @@
                         };
 
                         /* Apalis WAKE1_MICO */
-                        pex_wake_n_pdd3 {
+                        pex-wake-n-pdd3 {
                                 nvidia,pins = "pex_wake_n_pdd3";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -731,7 +732,7 @@
                         };
 
                         /* CORE_PWR_REQ */
-                        core_pwr_req {
+                        core-pwr-req {
                                 nvidia,pins = "core_pwr_req";
                                 nvidia,function = "pwron";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -740,7 +741,7 @@
                         };
 
                         /* CPU_PWR_REQ */
-                        cpu_pwr_req {
+                        cpu-pwr-req {
                                 nvidia,pins = "cpu_pwr_req";
                                 nvidia,function = "cpu";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -749,14 +750,14 @@
                         };
 
                         /* DVFS */
-                        dvfs_pwm_px0 {
+                        dvfs-pwm-px0 {
                                 nvidia,pins = "dvfs_pwm_px0";
                                 nvidia,function = "cldvfs";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        dvfs_clk_px2 {
+                        dvfs-clk-px2 {
                                 nvidia,pins = "dvfs_clk_px2";
                                 nvidia,function = "cldvfs";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -765,70 +766,70 @@
                         };
 
                         /* eMMC */
-                        sdmmc4_dat0_paa0 {
+                        sdmmc4-dat0-paa0 {
                                 nvidia,pins = "sdmmc4_dat0_paa0";
                                 nvidia,function = "sdmmc4";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc4_dat1_paa1 {
+                        sdmmc4-dat1-paa1 {
                                 nvidia,pins = "sdmmc4_dat1_paa1";
                                 nvidia,function = "sdmmc4";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc4_dat2_paa2 {
+                        sdmmc4-dat2-paa2 {
                                 nvidia,pins = "sdmmc4_dat2_paa2";
                                 nvidia,function = "sdmmc4";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc4_dat3_paa3 {
+                        sdmmc4-dat3-paa3 {
                                 nvidia,pins = "sdmmc4_dat3_paa3";
                                 nvidia,function = "sdmmc4";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc4_dat4_paa4 {
+                        sdmmc4-dat4-paa4 {
                                 nvidia,pins = "sdmmc4_dat4_paa4";
                                 nvidia,function = "sdmmc4";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc4_dat5_paa5 {
+                        sdmmc4-dat5-paa5 {
                                 nvidia,pins = "sdmmc4_dat5_paa5";
                                 nvidia,function = "sdmmc4";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc4_dat6_paa6 {
+                        sdmmc4-dat6-paa6 {
                                 nvidia,pins = "sdmmc4_dat6_paa6";
                                 nvidia,function = "sdmmc4";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc4_dat7_paa7 {
+                        sdmmc4-dat7-paa7 {
                                 nvidia,pins = "sdmmc4_dat7_paa7";
                                 nvidia,function = "sdmmc4";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc4_clk_pcc4 {
+                        sdmmc4-clk-pcc4 {
                                 nvidia,pins = "sdmmc4_clk_pcc4";
                                 nvidia,function = "sdmmc4";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc4_cmd_pt7 {
+                        sdmmc4-cmd-pt7 {
                                 nvidia,pins = "sdmmc4_cmd_pt7";
                                 nvidia,function = "sdmmc4";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
@@ -837,7 +838,7 @@
                         };
 
                         /* JTAG_RTCK */
-                        jtag_rtck {
+                        jtag-rtck {
                                 nvidia,pins = "jtag_rtck";
                                 nvidia,function = "rtck";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
@@ -846,7 +847,7 @@
                         };
 
                         /* LAN_DEV_OFF# */
-                        ulpi_data5_po6 {
+                        ulpi-data5-po6 {
                                 nvidia,pins = "ulpi_data5_po6";
                                 nvidia,function = "ulpi";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
@@ -855,7 +856,7 @@
                         };
 
                         /* LAN_RESET# */
-                        kb_row10_ps2 {
+                        kb-row10-ps2 {
                                 nvidia,pins = "kb_row10_ps2";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
@@ -864,7 +865,7 @@
                         };
 
                         /* LAN_WAKE# */
-                        ulpi_data4_po5 {
+                        ulpi-data4-po5 {
                                 nvidia,pins = "ulpi_data4_po5";
                                 nvidia,function = "ulpi";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -918,35 +919,35 @@
                         };
 
                         /* MCU SPI */
-                        gpio_x4_aud_px4 {
+                        gpio-x4-aud-px4 {
                                 nvidia,pins = "gpio_x4_aud_px4";
                                 nvidia,function = "spi2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        gpio_x5_aud_px5 {
+                        gpio-x5-aud-px5 {
                                 nvidia,pins = "gpio_x5_aud_px5";
                                 nvidia,function = "spi2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        gpio_x6_aud_px6 { /* MCU_CS */
+                        gpio-x6-aud-px6 { /* MCU_CS */
                                 nvidia,pins = "gpio_x6_aud_px6";
                                 nvidia,function = "spi2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        gpio_x7_aud_px7 {
+                        gpio-x7-aud-px7 {
                                 nvidia,pins = "gpio_x7_aud_px7";
                                 nvidia,function = "spi2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        gpio_w2_aud_pw2 { /* MCU_CSEZP */
+                        gpio-w2-aud-pw2 { /* MCU_CSEZP */
                                 nvidia,pins = "gpio_w2_aud_pw2";
                                 nvidia,function = "spi2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -955,7 +956,7 @@
                         };
 
                         /* PMIC_CLK_32K */
-                        clk_32k_in {
+                        clk-32k-in {
                                 nvidia,pins = "clk_32k_in";
                                 nvidia,function = "clk";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -964,7 +965,7 @@
                         };
 
                         /* PMIC_CPU_OC_INT */
-                        clk_32k_out_pa0 {
+                        clk-32k-out-pa0 {
                                 nvidia,pins = "clk_32k_out_pa0";
                                 nvidia,function = "soc";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -973,7 +974,7 @@
                         };
 
                         /* PWR_I2C */
-                        pwr_i2c_scl_pz6 {
+                        pwr-i2c-scl-pz6 {
                                 nvidia,pins = "pwr_i2c_scl_pz6";
                                 nvidia,function = "i2cpwr";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -981,7 +982,7 @@
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
                         };
-                        pwr_i2c_sda_pz7 {
+                        pwr-i2c-sda-pz7 {
                                 nvidia,pins = "pwr_i2c_sda_pz7";
                                 nvidia,function = "i2cpwr";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -991,7 +992,7 @@
                         };
 
                         /* PWR_INT_N */
-                        pwr_int_n {
+                        pwr-int-n {
                                 nvidia,pins = "pwr_int_n";
                                 nvidia,function = "pmi";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
@@ -1009,7 +1010,7 @@
                         };
 
                         /* RESET_OUT_N */
-                        reset_out_n {
+                        reset-out-n {
                                 nvidia,pins = "reset_out_n";
                                 nvidia,function = "reset_out_n";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -1018,14 +1019,14 @@
                         };
 
                         /* SHIFT_CTRL_DIR_IN */
-                        kb_row0_pr0 {
+                        kb-row0-pr0 {
                                 nvidia,pins = "kb_row0_pr0";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_row1_pr1 {
+                        kb-row1-pr1 {
                                 nvidia,pins = "kb_row1_pr1";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
@@ -1034,7 +1035,7 @@
                         };
 
                         /* Configure level-shifter as output for HDA */
-                        kb_row11_ps3 {
+                        kb-row11-ps3 {
                                 nvidia,pins = "kb_row11_ps3";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
@@ -1043,21 +1044,21 @@
                         };
 
                         /* SHIFT_CTRL_DIR_OUT */
-                        kb_col5_pq5 {
+                        kb-col5-pq5 {
                                 nvidia,pins = "kb_col5_pq5";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_col6_pq6 {
+                        kb-col6-pq6 {
                                 nvidia,pins = "kb_col6_pq6";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_col7_pq7 {
+                        kb-col7-pq7 {
                                 nvidia,pins = "kb_col7_pq7";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
@@ -1066,35 +1067,35 @@
                         };
 
                         /* SHIFT_CTRL_OE */
-                        kb_col0_pq0 {
+                        kb-col0-pq0 {
                                 nvidia,pins = "kb_col0_pq0";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_col1_pq1 {
+                        kb-col1-pq1 {
                                 nvidia,pins = "kb_col1_pq1";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_col2_pq2 {
+                        kb-col2-pq2 {
                                 nvidia,pins = "kb_col2_pq2";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_col4_pq4 {
+                        kb-col4-pq4 {
                                 nvidia,pins = "kb_col4_pq4";
                                 nvidia,function = "kbc";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_row2_pr2 {
+                        kb-row2-pr2 {
                                 nvidia,pins = "kb_row2_pr2";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
@@ -1112,7 +1113,7 @@
                         };
 
                         /* TOUCH_INT */
-                        gpio_w3_aud_pw3 {
+                        gpio-w3-aud-pw3 {
                                 nvidia,pins = "gpio_w3_aud_pw3";
                                 nvidia,function = "spi6";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -1253,189 +1254,189 @@
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        dap1_fs_pn0 { /* NC */
+                        dap1-fs-pn0 { /* NC */
                                 nvidia,pins = "dap1_fs_pn0";
                                 nvidia,function = "rsvd4";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        dap1_din_pn1 { /* NC */
+                        dap1-din-pn1 { /* NC */
                                 nvidia,pins = "dap1_din_pn1";
                                 nvidia,function = "rsvd4";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        dap1_sclk_pn3 { /* NC */
+                        dap1-sclk-pn3 { /* NC */
                                 nvidia,pins = "dap1_sclk_pn3";
                                 nvidia,function = "rsvd4";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        ulpi_data7_po0 { /* NC */
+                        ulpi-data7-po0 { /* NC */
                                 nvidia,pins = "ulpi_data7_po0";
                                 nvidia,function = "ulpi";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        ulpi_data0_po1 { /* NC */
+                        ulpi-data0-po1 { /* NC */
                                 nvidia,pins = "ulpi_data0_po1";
                                 nvidia,function = "ulpi";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        ulpi_data1_po2 { /* NC */
+                        ulpi-data1-po2 { /* NC */
                                 nvidia,pins = "ulpi_data1_po2";
                                 nvidia,function = "ulpi";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        ulpi_data2_po3 { /* NC */
+                        ulpi-data2-po3 { /* NC */
                                 nvidia,pins = "ulpi_data2_po3";
                                 nvidia,function = "ulpi";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        ulpi_data3_po4 { /* NC */
+                        ulpi-data3-po4 { /* NC */
                                 nvidia,pins = "ulpi_data3_po4";
                                 nvidia,function = "ulpi";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        ulpi_data6_po7 { /* NC */
+                        ulpi-data6-po7 { /* NC */
                                 nvidia,pins = "ulpi_data6_po7";
                                 nvidia,function = "ulpi";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        dap4_fs_pp4 { /* NC */
+                        dap4-fs-pp4 { /* NC */
                                 nvidia,pins = "dap4_fs_pp4";
                                 nvidia,function = "rsvd4";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        dap4_din_pp5 { /* NC */
+                        dap4-din-pp5 { /* NC */
                                 nvidia,pins = "dap4_din_pp5";
                                 nvidia,function = "rsvd3";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        dap4_dout_pp6 { /* NC */
+                        dap4-dout-pp6 { /* NC */
                                 nvidia,pins = "dap4_dout_pp6";
                                 nvidia,function = "rsvd4";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        dap4_sclk_pp7 { /* NC */
+                        dap4-sclk-pp7 { /* NC */
                                 nvidia,pins = "dap4_sclk_pp7";
                                 nvidia,function = "rsvd3";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_col3_pq3 { /* NC */
+                        kb-col3-pq3 { /* NC */
                                 nvidia,pins = "kb_col3_pq3";
                                 nvidia,function = "kbc";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_row3_pr3 { /* NC */
+                        kb-row3-pr3 { /* NC */
                                 nvidia,pins = "kb_row3_pr3";
                                 nvidia,function = "kbc";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_row4_pr4 { /* NC */
+                        kb-row4-pr4 { /* NC */
                                 nvidia,pins = "kb_row4_pr4";
                                 nvidia,function = "rsvd3";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_row5_pr5 { /* NC */
+                        kb-row5-pr5 { /* NC */
                                 nvidia,pins = "kb_row5_pr5";
                                 nvidia,function = "rsvd3";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_row6_pr6 { /* NC */
+                        kb-row6-pr6 { /* NC */
                                 nvidia,pins = "kb_row6_pr6";
                                 nvidia,function = "kbc";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_row7_pr7 { /* NC */
+                        kb-row7-pr7 { /* NC */
                                 nvidia,pins = "kb_row7_pr7";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_row8_ps0 { /* NC */
+                        kb-row8-ps0 { /* NC */
                                 nvidia,pins = "kb_row8_ps0";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_row9_ps1 { /* NC */
+                        kb-row9-ps1 { /* NC */
                                 nvidia,pins = "kb_row9_ps1";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_row12_ps4 { /* NC */
+                        kb-row12-ps4 { /* NC */
                                 nvidia,pins = "kb_row12_ps4";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_row13_ps5 { /* NC */
+                        kb-row13-ps5 { /* NC */
                                 nvidia,pins = "kb_row13_ps5";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_row14_ps6 { /* NC */
+                        kb-row14-ps6 { /* NC */
                                 nvidia,pins = "kb_row14_ps6";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_row15_ps7 { /* NC */
+                        kb-row15-ps7 { /* NC */
                                 nvidia,pins = "kb_row15_ps7";
                                 nvidia,function = "rsvd3";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_row16_pt0 { /* NC */
+                        kb-row16-pt0 { /* NC */
                                 nvidia,pins = "kb_row16_pt0";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_row17_pt1 { /* NC */
+                        kb-row17-pt1 { /* NC */
                                 nvidia,pins = "kb_row17_pt1";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
@@ -1467,14 +1468,14 @@
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        gpio_x1_aud_px1 { /* NC */
+                        gpio-x1-aud-px1 { /* NC */
                                 nvidia,pins = "gpio_x1_aud_px1";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        gpio_x3_aud_px3 { /* NC */
+                        gpio-x3-aud-px3 { /* NC */
                                 nvidia,pins = "gpio_x3_aud_px3";
                                 nvidia,function = "rsvd4";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
@@ -1502,14 +1503,14 @@
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        clk3_req_pee1 { /* NC */
+                        clk3-req-pee1 { /* NC */
                                 nvidia,pins = "clk3_req_pee1";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        dap_mclk1_req_pee2 { /* NC */
+                        dap-mclk1-req-pee2 { /* NC */
                                 nvidia,pins = "dap_mclk1_req_pee2";
                                 nvidia,function = "rsvd4";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
@@ -1525,7 +1526,7 @@
                          * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
                          * bits being set to 0xfffd according to the TRM!
                          */
-                        sdmmc3_clk_lb_out_pee4 { /* NC */
+                        sdmmc3-clk-lb-out-pee4 { /* NC */
                                 nvidia,pins = "sdmmc3_clk_lb_out_pee4";
                                 nvidia,function = "sdmmc3";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -1560,8 +1561,9 @@
                 sgtl5000: codec@a {
                         compatible = "fsl,sgtl5000";
                         reg = <0x0a>;
-                        VDDA-supply = <&reg_3v3>;
-                        VDDIO-supply = <&vddio_1v8>;
+                        VDDA-supply = <&reg_module_3v3_audio>;
+                        VDDD-supply = <&reg_1v8_vddio>;
+                        VDDIO-supply = <&reg_1v8_vddio>;
                         clocks = <&tegra_car TEGRA124_CLK_EXTERN1>;
                 };
 
@@ -1578,14 +1580,14 @@
                         pinctrl-0 = <&as3722_default>;
 
                         as3722_default: pinmux {
-                                gpio2_7 {
+                                gpio2-7 {
                                         pins = "gpio2", /* PWR_EN_+V3.3 */
                                                "gpio7"; /* +V1.6_LPO */
                                         function = "gpio";
                                         bias-pull-up;
                                 };
 
-                                gpio0_1_3_4_5_6 {
+                                gpio0-1-3-4-5-6 {
                                         pins = "gpio0", "gpio1", "gpio3",
                                                "gpio4", "gpio5", "gpio6";
                                         bias-high-impedance;
@@ -1593,18 +1595,18 @@
                         };
 
                         regulators {
-                                vsup-sd2-supply = <&reg_3v3>;
-                                vsup-sd3-supply = <&reg_3v3>;
-                                vsup-sd4-supply = <&reg_3v3>;
-                                vsup-sd5-supply = <&reg_3v3>;
-                                vin-ldo0-supply = <&vddio_ddr_1v35>;
-                                vin-ldo1-6-supply = <&reg_3v3>;
-                                vin-ldo2-5-7-supply = <&vddio_1v8>;
-                                vin-ldo3-4-supply = <&reg_3v3>;
-                                vin-ldo9-10-supply = <&reg_3v3>;
-                                vin-ldo11-supply = <&reg_3v3>;
-
-                                vdd_cpu: sd0 {
+                                vsup-sd2-supply = <&reg_module_3v3>;
+                                vsup-sd3-supply = <&reg_module_3v3>;
+                                vsup-sd4-supply = <&reg_module_3v3>;
+                                vsup-sd5-supply = <&reg_module_3v3>;
+                                vin-ldo0-supply = <&reg_1v35_vddio_ddr>;
+                                vin-ldo1-6-supply = <&reg_module_3v3>;
+                                vin-ldo2-5-7-supply = <&reg_1v8_vddio>;
+                                vin-ldo3-4-supply = <&reg_module_3v3>;
+                                vin-ldo9-10-supply = <&reg_module_3v3>;
+                                vin-ldo11-supply = <&reg_module_3v3>;
+
+                                reg_vdd_cpu: sd0 {
                                         regulator-name = "+VDD_CPU_AP";
                                         regulator-min-microvolt = <700000>;
                                         regulator-max-microvolt = <1400000>;
@@ -1626,7 +1628,7 @@
                                         ams,ext-control = <1>;
                                 };
 
-                                vddio_ddr_1v35: sd2 {
+                                reg_1v35_vddio_ddr: sd2 {
                                         regulator-name =
                                                 "+V1.35_VDDIO_DDR(sd2)";
                                         regulator-min-microvolt = <1350000>;
@@ -1644,13 +1646,13 @@
                                         regulator-boot-on;
                                 };
 
-                                vdd_1v05: sd4 {
+                                reg_1v05_vdd: sd4 {
                                         regulator-name = "+V1.05";
                                         regulator-min-microvolt = <1050000>;
                                         regulator-max-microvolt = <1050000>;
                                 };
 
-                                vddio_1v8: sd5 {
+                                reg_1v8_vddio: sd5 {
                                         regulator-name = "+V1.8";
                                         regulator-min-microvolt = <1800000>;
                                         regulator-max-microvolt = <1800000>;
@@ -1658,7 +1660,7 @@
                                         regulator-always-on;
                                 };
 
-                                vdd_gpu: sd6 {
+                                reg_vdd_gpu: sd6 {
                                         regulator-name = "+VDD_GPU_AP";
                                         regulator-min-microvolt = <650000>;
                                         regulator-max-microvolt = <1200000>;
@@ -1668,7 +1670,7 @@
                                         regulator-always-on;
                                 };
 
-                                avdd_1v05: ldo0 {
+                                reg_1v05_avdd: ldo0 {
                                         regulator-name = "+V1.05_AVDD";
                                         regulator-min-microvolt = <1050000>;
                                         regulator-max-microvolt = <1050000>;
@@ -1743,12 +1745,13 @@
                  * TMP451 temperature sensor
                  * Note: THERM_N directly connected to AS3722 PMIC THERM
                  */
-                temperature-sensor@4c {
+                temp-sensor@4c {
                         compatible = "ti,tmp451";
                         reg = <0x4c>;
                         interrupt-parent = <&gpio>;
                         interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
                         #thermal-sensor-cells = <1>;
+                        vcc-supply = <&reg_module_3v3>;
                 };
         };
 
@@ -1780,9 +1783,9 @@
         sata@70020000 {
                 phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
                 phy-names = "sata-0";
-                avdd-supply = <&vdd_1v05>;
-                hvdd-supply = <&reg_3v3>;
-                vddio-supply = <&vdd_1v05>;
+                avdd-supply = <&reg_1v05_vdd>;
+                hvdd-supply = <&reg_module_3v3>;
+                vddio-supply = <&reg_1v05_vdd>;
         };
 
         usb@70090000 {
@@ -1793,14 +1796,14 @@
                        <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
                        <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
                 phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0";
-                avddio-pex-supply = <&vdd_1v05>;
-                avdd-pll-erefe-supply = <&avdd_1v05>;
-                avdd-pll-utmip-supply = <&vddio_1v8>;
-                avdd-usb-ss-pll-supply = <&vdd_1v05>;
-                avdd-usb-supply = <&reg_3v3>;
-                dvddio-pex-supply = <&vdd_1v05>;
-                hvdd-usb-ss-pll-e-supply = <&reg_3v3>;
-                hvdd-usb-ss-supply = <&reg_3v3>;
+                avddio-pex-supply = <&reg_1v05_vdd>;
+                avdd-pll-erefe-supply = <&reg_1v05_avdd>;
+                avdd-pll-utmip-supply = <&reg_1v8_vddio>;
+                avdd-usb-ss-pll-supply = <&reg_1v05_vdd>;
+                avdd-usb-supply = <&reg_module_3v3>;
+                dvddio-pex-supply = <&reg_1v05_vdd>;
+                hvdd-usb-ss-pll-e-supply = <&reg_module_3v3>;
+                hvdd-usb-ss-supply = <&reg_module_3v3>;
         };
 
         padctl@7009f000 {
@@ -1810,18 +1813,18 @@
 
                                 lanes {
                                         usb2-0 {
-                                                nvidia,function = "xusb";
                                                 status = "okay";
+                                                nvidia,function = "xusb";
                                         };
 
                                         usb2-1 {
-                                                nvidia,function = "xusb";
                                                 status = "okay";
+                                                nvidia,function = "xusb";
                                         };
 
                                         usb2-2 {
-                                                nvidia,function = "xusb";
                                                 status = "okay";
+                                                nvidia,function = "xusb";
                                         };
                                 };
                         };
@@ -1831,28 +1834,28 @@
 
                                 lanes {
                                         pcie-0 {
-                                                nvidia,function = "usb3-ss";
                                                 status = "okay";
+                                                nvidia,function = "usb3-ss";
                                         };
 
                                         pcie-1 {
-                                                nvidia,function = "usb3-ss";
                                                 status = "okay";
+                                                nvidia,function = "usb3-ss";
                                         };
 
                                         pcie-2 {
-                                                nvidia,function = "pcie";
                                                 status = "okay";
+                                                nvidia,function = "pcie";
                                         };
 
                                         pcie-3 {
-                                                nvidia,function = "pcie";
                                                 status = "okay";
+                                                nvidia,function = "pcie";
                                         };
 
                                         pcie-4 {
-                                                nvidia,function = "pcie";
                                                 status = "okay";
+                                                nvidia,function = "pcie";
                                         };
                                 };
                         };
@@ -1862,8 +1865,8 @@
 
                                 lanes {
                                         sata-0 {
-                                                nvidia,function = "sata";
                                                 status = "okay";
+                                                nvidia,function = "sata";
                                         };
                                 };
                         };
@@ -1874,7 +1877,6 @@
                         usb2-0 {
                                 status = "okay";
                                 mode = "otg";
-
                                 vbus-supply = <&reg_usbo1_vbus>;
                         };
 
@@ -1882,7 +1884,6 @@
                         usb2-1 {
                                 status = "okay";
                                 mode = "host";
-
                                 vbus-supply = <&reg_usbh_vbus>;
                         };
 
@@ -1890,18 +1891,19 @@
                         usb2-2 {
                                 status = "okay";
                                 mode = "host";
-
                                 vbus-supply = <&reg_usbh_vbus>;
                         };
 
                         usb3-0 {
-                                nvidia,usb2-companion = <2>;
                                 status = "okay";
+                                nvidia,usb2-companion = <2>;
+                                vbus-supply = <&reg_usbh_vbus>;
                         };
 
                         usb3-1 {
-                                nvidia,usb2-companion = <0>;
                                 status = "okay";
+                                nvidia,usb2-companion = <0>;
+                                vbus-supply = <&reg_usbo1_vbus>;
                         };
                 };
         };
@@ -1911,13 +1913,16 @@
                 status = "okay";
                 bus-width = <8>;
                 non-removable;
+                vmmc-supply = <&reg_module_3v3>; /* VCC */
+                vqmmc-supply = <&reg_1v8_vddio>; /* VCCQ */
+                mmc-ddr-1_8v;
         };
 
         /* CPU DFLL clock */
         clock@70110000 {
                 status = "okay";
-                vdd-cpu-supply = <&vdd_cpu>;
                 nvidia,i2c-fs-rate = <400000>;
+                vdd-cpu-supply = <&reg_vdd_cpu>;
         };
 
         ahub@70300000 {
@@ -1926,22 +1931,15 @@
                 };
         };
 
-        clocks {
-                compatible = "simple-bus";
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                clk32k_in: clock@0 {
-                        compatible = "fixed-clock";
-                        reg = <0>;
-                        #clock-cells = <0>;
-                        clock-frequency = <32768>;
-                };
+        clk32k_in: osc3 {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <32768>;
         };
 
         cpus {
                 cpu@0 {
-                        vdd-cpu-supply = <&vdd_cpu>;
+                        vdd-cpu-supply = <&reg_vdd_cpu>;
                 };
         };
 
@@ -1951,7 +1949,7 @@
                 regulator-min-microvolt = <1050000>;
                 regulator-max-microvolt = <1050000>;
                 gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
-                vin-supply = <&vdd_1v05>;
+                vin-supply = <&reg_1v05_vdd>;
         };
 
         reg_3v3_mxm: regulator-3v3-mxm {
@@ -1963,7 +1961,15 @@
                 regulator-boot-on;
         };
 
-        reg_3v3: regulator-3v3 {
+        reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
+                compatible = "regulator-fixed";
+                regulator-name = "+V3.3_AVDD_HDMI";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                vin-supply = <&reg_1v05_vdd>;
+        };
+
+        reg_module_3v3: regulator-module-3v3 {
                 compatible = "regulator-fixed";
                 regulator-name = "+V3.3";
                 regulator-min-microvolt = <3300000>;
@@ -1976,12 +1982,12 @@
                 vin-supply = <&reg_3v3_mxm>;
         };
 
-        reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
+        reg_module_3v3_audio: regulator-module-3v3-audio {
                 compatible = "regulator-fixed";
-                regulator-name = "+V3.3_AVDD_HDMI";
+                regulator-name = "+V3.3_AUDIO_AVDD_S";
                 regulator-min-microvolt = <3300000>;
                 regulator-max-microvolt = <3300000>;
-                vin-supply = <&vdd_1v05>;
+                regulator-always-on;
         };
 
         sound {
@@ -2035,7 +2041,7 @@
 
 &gpio {
         /* I210 Gigabit Ethernet Controller Reset */
-        lan_reset_n {
+        lan-reset-n {
                 gpio-hog;
                 gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
                 output-high;
@@ -2043,7 +2049,7 @@
         };
 
         /* Control MXM3 pin 26 Reset Module Output Carrier Input */
-        reset_moci_ctrl {
+        reset-moci-ctrl {
                 gpio-hog;
                 gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
                 output-high;
diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi
index 0f0d4a4988b9..13c93cd507d8 100644
--- a/arch/arm/boot/dts/tegra124-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra124-apalis.dtsi
@@ -47,22 +47,19 @@
  * Compatible for Revisions 2GB: V1.0A, V1.0B, V1.1A
  */
 / {
-        model = "Toradex Apalis TK1";
-        compatible = "toradex,apalis-tk1", "nvidia,tegra124";
-
         memory@80000000 {
                 reg = <0x0 0x80000000 0x0 0x80000000>;
         };
 
         pcie@1003000 {
                 status = "okay";
-                avddio-pex-supply = <&vdd_1v05>;
-                avdd-pex-pll-supply = <&vdd_1v05>;
-                avdd-pll-erefe-supply = <&avdd_1v05>;
-                dvddio-pex-supply = <&vdd_1v05>;
-                hvdd-pex-pll-e-supply = <&reg_3v3>;
-                hvdd-pex-supply = <&reg_3v3>;
-                vddio-pex-ctl-supply = <&reg_3v3>;
+                avddio-pex-supply = <&reg_1v05_vdd>;
+                avdd-pex-pll-supply = <&reg_1v05_vdd>;
+                avdd-pll-erefe-supply = <&reg_1v05_avdd>;
+                dvddio-pex-supply = <&reg_1v05_vdd>;
+                hvdd-pex-pll-e-supply = <&reg_module_3v3>;
+                hvdd-pex-supply = <&reg_module_3v3>;
+                vddio-pex-ctl-supply = <&reg_module_3v3>;
 
                 /* Apalis PCIe (additional lane Apalis type specific) */
                 pci@1,0 {
@@ -77,16 +74,21 @@
                         phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
                         phy-names = "pcie-0";
                         status = "okay";
+
+                        pcie@0 {
+                                reg = <0 0 0 0 0>;
+                                local-mac-address = [00 00 00 00 00 00];
+                        };
                 };
         };
 
         host1x@50000000 {
                 hdmi@54280000 {
-                        pll-supply = <&reg_1v05_avdd_hdmi_pll>;
-                        vdd-supply = <&reg_3v3_avdd_hdmi>;
                         nvidia,ddc-i2c-bus = <&hdmi_ddc>;
                         nvidia,hpd-gpio =
                                 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
+                        pll-supply = <&reg_1v05_avdd_hdmi_pll>;
+                        vdd-supply = <&reg_3v3_avdd_hdmi>;
                 };
         };
 
@@ -95,44 +97,44 @@
                  * Node left disabled on purpose - the bootloader will enable
                  * it after having set the VPR up
                  */
-                vdd-supply = <&vdd_gpu>;
+                vdd-supply = <&reg_vdd_gpu>;
         };
 
-        pinmux: pinmux@70000868 {
+        pinmux@70000868 {
                 pinctrl-names = "default";
                 pinctrl-0 = <&state_default>;
 
                 state_default: pinmux {
                         /* Analogue Audio (On-module) */
-                        dap3_fs_pp0 {
+                        dap3-fs-pp0 {
                                 nvidia,pins = "dap3_fs_pp0";
                                 nvidia,function = "i2s2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        dap3_din_pp1 {
+                        dap3-din-pp1 {
                                 nvidia,pins = "dap3_din_pp1";
                                 nvidia,function = "i2s2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        dap3_dout_pp2 {
+                        dap3-dout-pp2 {
                                 nvidia,pins = "dap3_dout_pp2";
                                 nvidia,function = "i2s2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        dap3_sclk_pp3 {
+                        dap3-sclk-pp3 {
                                 nvidia,pins = "dap3_sclk_pp3";
                                 nvidia,function = "i2s2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        dap_mclk1_pw4 {
+                        dap-mclk1-pw4 {
                                 nvidia,pins = "dap_mclk1_pw4";
                                 nvidia,function = "extperiph1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -159,7 +161,7 @@
                         };
 
                         /* Apalis CAM1_MCLK */
-                        cam_mclk_pcc0 {
+                        cam-mclk-pcc0 {
                                 nvidia,pins = "cam_mclk_pcc0";
                                 nvidia,function = "vi_alt3";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -168,28 +170,28 @@
                         };
 
                         /* Apalis Digital Audio */
-                        dap2_fs_pa2 {
+                        dap2-fs-pa2 {
                                 nvidia,pins = "dap2_fs_pa2";
                                 nvidia,function = "hda";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        dap2_sclk_pa3 {
+                        dap2-sclk-pa3 {
                                 nvidia,pins = "dap2_sclk_pa3";
                                 nvidia,function = "hda";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        dap2_din_pa4 {
+                        dap2-din-pa4 {
                                 nvidia,pins = "dap2_din_pa4";
                                 nvidia,function = "hda";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        dap2_dout_pa5 {
+                        dap2-dout-pa5 {
                                 nvidia,pins = "dap2_dout_pa5";
                                 nvidia,function = "hda";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -202,7 +204,7 @@
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        clk3_out_pee0 {
+                        clk3-out-pee0 {
                                 nvidia,pins = "clk3_out_pee0";
                                 nvidia,function = "extperiph3";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -211,49 +213,49 @@
                         };
 
                         /* Apalis GPIO */
-                        ddc_scl_pv4 {
+                        ddc-scl-pv4 {
                                 nvidia,pins = "ddc_scl_pv4";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        ddc_sda_pv5 {
+                        ddc-sda-pv5 {
                                 nvidia,pins = "ddc_sda_pv5";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        pex_l0_rst_n_pdd1 {
+                        pex-l0-rst-n-pdd1 {
                                 nvidia,pins = "pex_l0_rst_n_pdd1";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        pex_l0_clkreq_n_pdd2 {
+                        pex-l0-clkreq-n-pdd2 {
                                 nvidia,pins = "pex_l0_clkreq_n_pdd2";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        pex_l1_rst_n_pdd5 {
+                        pex-l1-rst-n-pdd5 {
                                 nvidia,pins = "pex_l1_rst_n_pdd5";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        pex_l1_clkreq_n_pdd6 {
+                        pex-l1-clkreq-n-pdd6 {
                                 nvidia,pins = "pex_l1_clkreq_n_pdd6";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        dp_hpd_pff0 {
+                        dp-hpd-pff0 {
                                 nvidia,pins = "dp_hpd_pff0";
                                 nvidia,function = "dp";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -277,7 +279,7 @@
                         };
 
                         /* Apalis HDMI1_CEC */
-                        hdmi_cec_pee3 {
+                        hdmi-cec-pee3 {
                                 nvidia,pins = "hdmi_cec_pee3";
                                 nvidia,function = "cec";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -287,7 +289,7 @@
                         };
 
                         /* Apalis HDMI1_HPD */
-                        hdmi_int_pn7 {
+                        hdmi-int-pn7 {
                                 nvidia,pins = "hdmi_int_pn7";
                                 nvidia,function = "rsvd1";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
@@ -297,7 +299,7 @@
                         };
 
                         /* Apalis I2C1 */
-                        gen1_i2c_scl_pc4 {
+                        gen1-i2c-scl-pc4 {
                                 nvidia,pins = "gen1_i2c_scl_pc4";
                                 nvidia,function = "i2c1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -305,7 +307,7 @@
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
                         };
-                        gen1_i2c_sda_pc5 {
+                        gen1-i2c-sda-pc5 {
                                 nvidia,pins = "gen1_i2c_sda_pc5";
                                 nvidia,function = "i2c1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -315,7 +317,7 @@
                         };
 
                         /* Apalis I2C2 (DDC) */
-                        gen2_i2c_scl_pt5 {
+                        gen2-i2c-scl-pt5 {
                                 nvidia,pins = "gen2_i2c_scl_pt5";
                                 nvidia,function = "i2c2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -323,7 +325,7 @@
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
                         };
-                        gen2_i2c_sda_pt6 {
+                        gen2-i2c-sda-pt6 {
                                 nvidia,pins = "gen2_i2c_sda_pt6";
                                 nvidia,function = "i2c2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -333,7 +335,7 @@
                         };
 
                         /* Apalis I2C3 (CAM) */
-                        cam_i2c_scl_pbb1 {
+                        cam-i2c-scl-pbb1 {
                                 nvidia,pins = "cam_i2c_scl_pbb1";
                                 nvidia,function = "i2c3";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -341,7 +343,7 @@
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
                         };
-                        cam_i2c_sda_pbb2 {
+                        cam-i2c-sda-pbb2 {
                                 nvidia,pins = "cam_i2c_sda_pbb2";
                                 nvidia,function = "i2c3";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -351,77 +353,77 @@
                         };
 
                         /* Apalis MMC1 */
-                        sdmmc1_cd_n_pv3 { /* CD# GPIO */
+                        sdmmc1-cd-n-pv3 { /* CD# GPIO */
                                 nvidia,pins = "sdmmc1_wp_n_pv3";
                                 nvidia,function = "sdmmc1";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        clk2_out_pw5 { /* D5 GPIO */
+                        clk2-out-pw5 { /* D5 GPIO */
                                 nvidia,pins = "clk2_out_pw5";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc1_dat3_py4 {
+                        sdmmc1-dat3-py4 {
                                 nvidia,pins = "sdmmc1_dat3_py4";
                                 nvidia,function = "sdmmc1";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc1_dat2_py5 {
+                        sdmmc1-dat2-py5 {
                                 nvidia,pins = "sdmmc1_dat2_py5";
                                 nvidia,function = "sdmmc1";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc1_dat1_py6 {
+                        sdmmc1-dat1-py6 {
                                 nvidia,pins = "sdmmc1_dat1_py6";
                                 nvidia,function = "sdmmc1";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc1_dat0_py7 {
+                        sdmmc1-dat0-py7 {
                                 nvidia,pins = "sdmmc1_dat0_py7";
                                 nvidia,function = "sdmmc1";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc1_clk_pz0 {
+                        sdmmc1-clk-pz0 {
                                 nvidia,pins = "sdmmc1_clk_pz0";
                                 nvidia,function = "sdmmc1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc1_cmd_pz1 {
+                        sdmmc1-cmd-pz1 {
                                 nvidia,pins = "sdmmc1_cmd_pz1";
                                 nvidia,function = "sdmmc1";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        clk2_req_pcc5 { /* D4 GPIO */
+                        clk2-req-pcc5 { /* D4 GPIO */
                                 nvidia,pins = "clk2_req_pcc5";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc3_clk_lb_in_pee5 { /* D6 GPIO */
+                        sdmmc3-clk-lb-in-pee5 { /* D6 GPIO */
                                 nvidia,pins = "sdmmc3_clk_lb_in_pee5";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        usb_vbus_en2_pff1 { /* D7 GPIO */
+                        usb-vbus-en2-pff1 { /* D7 GPIO */
                                 nvidia,pins = "usb_vbus_en2_pff1";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -461,7 +463,7 @@
                         };
 
                         /* Apalis SATA1_ACT# */
-                        dap1_dout_pn2 {
+                        dap1-dout-pn2 {
                                 nvidia,pins = "dap1_dout_pn2";
                                 nvidia,function = "gmi";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -470,49 +472,49 @@
                         };
 
                         /* Apalis SD1 */
-                        sdmmc3_clk_pa6 {
+                        sdmmc3-clk-pa6 {
                                 nvidia,pins = "sdmmc3_clk_pa6";
                                 nvidia,function = "sdmmc3";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc3_cmd_pa7 {
+                        sdmmc3-cmd-pa7 {
                                 nvidia,pins = "sdmmc3_cmd_pa7";
                                 nvidia,function = "sdmmc3";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc3_dat3_pb4 {
+                        sdmmc3-dat3-pb4 {
                                 nvidia,pins = "sdmmc3_dat3_pb4";
                                 nvidia,function = "sdmmc3";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc3_dat2_pb5 {
+                        sdmmc3-dat2-pb5 {
                                 nvidia,pins = "sdmmc3_dat2_pb5";
                                 nvidia,function = "sdmmc3";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc3_dat1_pb6 {
+                        sdmmc3-dat1-pb6 {
                                 nvidia,pins = "sdmmc3_dat1_pb6";
                                 nvidia,function = "sdmmc3";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc3_dat0_pb7 {
+                        sdmmc3-dat0-pb7 {
                                 nvidia,pins = "sdmmc3_dat0_pb7";
                                 nvidia,function = "sdmmc3";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc3_cd_n_pv2 { /* CD# GPIO */
+                        sdmmc3-cd-n-pv2 { /* CD# GPIO */
                                 nvidia,pins = "sdmmc3_cd_n_pv2";
                                 nvidia,function = "rsvd3";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
@@ -521,14 +523,14 @@
                         };
 
                         /* Apalis SPDIF */
-                        spdif_out_pk5 {
+                        spdif-out-pk5 {
                                 nvidia,pins = "spdif_out_pk5";
                                 nvidia,function = "spdif";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        spdif_in_pk6 {
+                        spdif-in-pk6 {
                                 nvidia,pins = "spdif_in_pk6";
                                 nvidia,function = "spdif";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -537,28 +539,28 @@
                         };
 
                         /* Apalis SPI1 */
-                        ulpi_clk_py0 {
+                        ulpi-clk-py0 {
                                 nvidia,pins = "ulpi_clk_py0";
                                 nvidia,function = "spi1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        ulpi_dir_py1 {
+                        ulpi-dir-py1 {
                                 nvidia,pins = "ulpi_dir_py1";
                                 nvidia,function = "spi1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        ulpi_nxt_py2 {
+                        ulpi-nxt-py2 {
                                 nvidia,pins = "ulpi_nxt_py2";
                                 nvidia,function = "spi1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        ulpi_stp_py3 {
+                        ulpi-stp-py3 {
                                 nvidia,pins = "ulpi_stp_py3";
                                 nvidia,function = "spi1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -611,42 +613,42 @@
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        uart1_txd_pu0 {
+                        uart1-txd-pu0 {
                                 nvidia,pins = "pu0";
                                 nvidia,function = "uarta";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        uart1_rxd_pu1 {
+                        uart1-rxd-pu1 {
                                 nvidia,pins = "pu1";
                                 nvidia,function = "uarta";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        uart1_cts_n_pu2 {
+                        uart1-cts-n-pu2 {
                                 nvidia,pins = "pu2";
                                 nvidia,function = "uarta";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        uart1_rts_n_pu3 {
+                        uart1-rts-n-pu3 {
                                 nvidia,pins = "pu3";
                                 nvidia,function = "uarta";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        uart3_cts_n_pa1 { /* DSR GPIO */
+                        uart3-cts-n-pa1 { /* DSR GPIO */
                                 nvidia,pins = "uart3_cts_n_pa1";
                                 nvidia,function = "gmi";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        uart3_rts_n_pc0 { /* DTR GPIO */
+                        uart3-rts-n-pc0 { /* DTR GPIO */
                                 nvidia,pins = "uart3_rts_n_pc0";
                                 nvidia,function = "gmi";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -655,28 +657,28 @@
                         };
 
                         /* Apalis UART2 */
-                        uart2_txd_pc2 {
+                        uart2-txd-pc2 {
                                 nvidia,pins = "uart2_txd_pc2";
                                 nvidia,function = "irda";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        uart2_rxd_pc3 {
+                        uart2-rxd-pc3 {
                                 nvidia,pins = "uart2_rxd_pc3";
                                 nvidia,function = "irda";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        uart2_cts_n_pj5 {
+                        uart2-cts-n-pj5 {
                                 nvidia,pins = "uart2_cts_n_pj5";
                                 nvidia,function = "uartb";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        uart2_rts_n_pj6 {
+                        uart2-rts-n-pj6 {
                                 nvidia,pins = "uart2_rts_n_pj6";
                                 nvidia,function = "uartb";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -685,14 +687,14 @@
                         };
 
                         /* Apalis UART3 */
-                        uart3_txd_pw6 {
+                        uart3-txd-pw6 {
                                 nvidia,pins = "uart3_txd_pw6";
                                 nvidia,function = "uartc";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        uart3_rxd_pw7 {
+                        uart3-rxd-pw7 {
                                 nvidia,pins = "uart3_rxd_pw7";
                                 nvidia,function = "uartc";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -701,14 +703,14 @@
                         };
 
                         /* Apalis UART4 */
-                        uart4_rxd_pb0 {
+                        uart4-rxd-pb0 {
                                 nvidia,pins = "pb0";
                                 nvidia,function = "uartd";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        uart4_txd_pj7 {
+                        uart4-txd-pj7 {
                                 nvidia,pins = "pj7";
                                 nvidia,function = "uartd";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -717,7 +719,7 @@
                         };
 
                         /* Apalis USBH_EN */
-                        usb_vbus_en1_pn5 {
+                        usb-vbus-en1-pn5 {
                                 nvidia,pins = "usb_vbus_en1_pn5";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -736,7 +738,7 @@
                         };
 
                         /* Apalis USBO1_EN */
-                        usb_vbus_en0_pn4 {
+                        usb-vbus-en0-pn4 {
                                 nvidia,pins = "usb_vbus_en0_pn4";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -755,7 +757,7 @@
                         };
 
                         /* Apalis WAKE1_MICO */
-                        pex_wake_n_pdd3 {
+                        pex-wake-n-pdd3 {
                                 nvidia,pins = "pex_wake_n_pdd3";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -764,7 +766,7 @@
                         };
 
                         /* CORE_PWR_REQ */
-                        core_pwr_req {
+                        core-pwr-req {
                                 nvidia,pins = "core_pwr_req";
                                 nvidia,function = "pwron";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -773,7 +775,7 @@
                         };
 
                         /* CPU_PWR_REQ */
-                        cpu_pwr_req {
+                        cpu-pwr-req {
                                 nvidia,pins = "cpu_pwr_req";
                                 nvidia,function = "cpu";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -782,14 +784,14 @@
                         };
 
                         /* DVFS */
-                        dvfs_pwm_px0 {
+                        dvfs-pwm-px0 {
                                 nvidia,pins = "dvfs_pwm_px0";
                                 nvidia,function = "cldvfs";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        dvfs_clk_px2 {
+                        dvfs-clk-px2 {
                                 nvidia,pins = "dvfs_clk_px2";
                                 nvidia,function = "cldvfs";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -798,70 +800,70 @@
                         };
 
                         /* eMMC */
-                        sdmmc4_dat0_paa0 {
+                        sdmmc4-dat0-paa0 {
                                 nvidia,pins = "sdmmc4_dat0_paa0";
                                 nvidia,function = "sdmmc4";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc4_dat1_paa1 {
+                        sdmmc4-dat1-paa1 {
                                 nvidia,pins = "sdmmc4_dat1_paa1";
                                 nvidia,function = "sdmmc4";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc4_dat2_paa2 {
+                        sdmmc4-dat2-paa2 {
                                 nvidia,pins = "sdmmc4_dat2_paa2";
                                 nvidia,function = "sdmmc4";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc4_dat3_paa3 {
+                        sdmmc4-dat3-paa3 {
                                 nvidia,pins = "sdmmc4_dat3_paa3";
                                 nvidia,function = "sdmmc4";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc4_dat4_paa4 {
+                        sdmmc4-dat4-paa4 {
                                 nvidia,pins = "sdmmc4_dat4_paa4";
                                 nvidia,function = "sdmmc4";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc4_dat5_paa5 {
+                        sdmmc4-dat5-paa5 {
                                 nvidia,pins = "sdmmc4_dat5_paa5";
                                 nvidia,function = "sdmmc4";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc4_dat6_paa6 {
+                        sdmmc4-dat6-paa6 {
                                 nvidia,pins = "sdmmc4_dat6_paa6";
                                 nvidia,function = "sdmmc4";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc4_dat7_paa7 {
+                        sdmmc4-dat7-paa7 {
                                 nvidia,pins = "sdmmc4_dat7_paa7";
                                 nvidia,function = "sdmmc4";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc4_clk_pcc4 {
+                        sdmmc4-clk-pcc4 {
                                 nvidia,pins = "sdmmc4_clk_pcc4";
                                 nvidia,function = "sdmmc4";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc4_cmd_pt7 {
+                        sdmmc4-cmd-pt7 {
                                 nvidia,pins = "sdmmc4_cmd_pt7";
                                 nvidia,function = "sdmmc4";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
@@ -870,7 +872,7 @@
                         };
 
                         /* JTAG_RTCK */
-                        jtag_rtck {
+                        jtag-rtck {
                                 nvidia,pins = "jtag_rtck";
                                 nvidia,function = "rtck";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
@@ -879,7 +881,7 @@
                         };
 
                         /* LAN_DEV_OFF# */
-                        ulpi_data5_po6 {
+                        ulpi-data5-po6 {
                                 nvidia,pins = "ulpi_data5_po6";
                                 nvidia,function = "ulpi";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
@@ -888,7 +890,7 @@
                         };
 
                         /* LAN_RESET# */
-                        kb_row10_ps2 {
+                        kb-row10-ps2 {
                                 nvidia,pins = "kb_row10_ps2";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
@@ -897,7 +899,7 @@
                         };
 
                         /* LAN_WAKE# */
-                        ulpi_data4_po5 {
+                        ulpi-data4-po5 {
                                 nvidia,pins = "ulpi_data4_po5";
                                 nvidia,function = "ulpi";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -951,35 +953,35 @@
                         };
 
                         /* MCU SPI */
-                        gpio_x4_aud_px4 {
+                        gpio-x4-aud-px4 {
                                 nvidia,pins = "gpio_x4_aud_px4";
                                 nvidia,function = "spi2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        gpio_x5_aud_px5 {
+                        gpio-x5-aud-px5 {
                                 nvidia,pins = "gpio_x5_aud_px5";
                                 nvidia,function = "spi2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        gpio_x6_aud_px6 { /* MCU_CS */
+                        gpio-x6-aud-px6 { /* MCU_CS */
                                 nvidia,pins = "gpio_x6_aud_px6";
                                 nvidia,function = "spi2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        gpio_x7_aud_px7 {
+                        gpio-x7-aud-px7 {
                                 nvidia,pins = "gpio_x7_aud_px7";
                                 nvidia,function = "spi2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        gpio_w2_aud_pw2 { /* MCU_CSEZP */
+                        gpio-w2-aud-pw2 { /* MCU_CSEZP */
                                 nvidia,pins = "gpio_w2_aud_pw2";
                                 nvidia,function = "spi2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -988,7 +990,7 @@
                         };
 
                         /* PMIC_CLK_32K */
-                        clk_32k_in {
+                        clk-32k-in {
                                 nvidia,pins = "clk_32k_in";
                                 nvidia,function = "clk";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -997,7 +999,7 @@
                         };
 
                         /* PMIC_CPU_OC_INT */
-                        clk_32k_out_pa0 {
+                        clk-32k-out-pa0 {
                                 nvidia,pins = "clk_32k_out_pa0";
                                 nvidia,function = "soc";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -1006,7 +1008,7 @@
                         };
 
                         /* PWR_I2C */
-                        pwr_i2c_scl_pz6 {
+                        pwr-i2c-scl-pz6 {
                                 nvidia,pins = "pwr_i2c_scl_pz6";
                                 nvidia,function = "i2cpwr";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -1014,7 +1016,7 @@
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
                         };
-                        pwr_i2c_sda_pz7 {
+                        pwr-i2c-sda-pz7 {
                                 nvidia,pins = "pwr_i2c_sda_pz7";
                                 nvidia,function = "i2cpwr";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -1024,7 +1026,7 @@
                         };
 
                         /* PWR_INT_N */
-                        pwr_int_n {
+                        pwr-int-n {
                                 nvidia,pins = "pwr_int_n";
                                 nvidia,function = "pmi";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
@@ -1042,7 +1044,7 @@
                         };
 
                         /* RESET_OUT_N */
-                        reset_out_n {
+                        reset-out-n {
                                 nvidia,pins = "reset_out_n";
                                 nvidia,function = "reset_out_n";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -1051,14 +1053,14 @@
                         };
 
                         /* SHIFT_CTRL_DIR_IN */
-                        kb_row0_pr0 {
+                        kb-row0-pr0 {
                                 nvidia,pins = "kb_row0_pr0";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_row1_pr1 {
+                        kb-row1-pr1 {
                                 nvidia,pins = "kb_row1_pr1";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
@@ -1067,7 +1069,7 @@
                         };
 
                         /* Configure level-shifter as output for HDA */
-                        kb_row11_ps3 {
+                        kb-row11-ps3 {
                                 nvidia,pins = "kb_row11_ps3";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
@@ -1076,21 +1078,21 @@
                         };
 
                         /* SHIFT_CTRL_DIR_OUT */
-                        kb_col5_pq5 {
+                        kb-col5-pq5 {
                                 nvidia,pins = "kb_col5_pq5";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_col6_pq6 {
+                        kb-col6-pq6 {
                                 nvidia,pins = "kb_col6_pq6";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_col7_pq7 {
+                        kb-col7-pq7 {
                                 nvidia,pins = "kb_col7_pq7";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
@@ -1099,35 +1101,35 @@
                         };
 
                         /* SHIFT_CTRL_OE */
-                        kb_col0_pq0 {
+                        kb-col0-pq0 {
                                 nvidia,pins = "kb_col0_pq0";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_col1_pq1 {
+                        kb-col1-pq1 {
                                 nvidia,pins = "kb_col1_pq1";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_col2_pq2 {
+                        kb-col2-pq2 {
                                 nvidia,pins = "kb_col2_pq2";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_col4_pq4 {
+                        kb-col4-pq4 {
                                 nvidia,pins = "kb_col4_pq4";
                                 nvidia,function = "kbc";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_row2_pr2 {
+                        kb-row2-pr2 {
                                 nvidia,pins = "kb_row2_pr2";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
@@ -1145,7 +1147,7 @@
                         };
 
                         /* TOUCH_INT */
-                        gpio_w3_aud_pw3 {
+                        gpio-w3-aud-pw3 {
                                 nvidia,pins = "gpio_w3_aud_pw3";
                                 nvidia,function = "spi6";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -1286,189 +1288,189 @@
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        dap1_fs_pn0 { /* NC */
+                        dap1-fs-pn0 { /* NC */
                                 nvidia,pins = "dap1_fs_pn0";
                                 nvidia,function = "rsvd4";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        dap1_din_pn1 { /* NC */
+                        dap1-din-pn1 { /* NC */
                                 nvidia,pins = "dap1_din_pn1";
                                 nvidia,function = "rsvd4";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        dap1_sclk_pn3 { /* NC */
+                        dap1-sclk-pn3 { /* NC */
                                 nvidia,pins = "dap1_sclk_pn3";
                                 nvidia,function = "rsvd4";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        ulpi_data7_po0 { /* NC */
+                        ulpi-data7-po0 { /* NC */
                                 nvidia,pins = "ulpi_data7_po0";
                                 nvidia,function = "ulpi";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        ulpi_data0_po1 { /* NC */
+                        ulpi-data0-po1 { /* NC */
                                 nvidia,pins = "ulpi_data0_po1";
                                 nvidia,function = "ulpi";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        ulpi_data1_po2 { /* NC */
+                        ulpi-data1-po2 { /* NC */
                                 nvidia,pins = "ulpi_data1_po2";
                                 nvidia,function = "ulpi";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        ulpi_data2_po3 { /* NC */
+                        ulpi-data2-po3 { /* NC */
                                 nvidia,pins = "ulpi_data2_po3";
                                 nvidia,function = "ulpi";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        ulpi_data3_po4 { /* NC */
+                        ulpi-data3-po4 { /* NC */
                                 nvidia,pins = "ulpi_data3_po4";
                                 nvidia,function = "ulpi";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        ulpi_data6_po7 { /* NC */
+                        ulpi-data6-po7 { /* NC */
                                 nvidia,pins = "ulpi_data6_po7";
                                 nvidia,function = "ulpi";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        dap4_fs_pp4 { /* NC */
+                        dap4-fs-pp4 { /* NC */
                                 nvidia,pins = "dap4_fs_pp4";
                                 nvidia,function = "rsvd4";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        dap4_din_pp5 { /* NC */
+                        dap4-din-pp5 { /* NC */
                                 nvidia,pins = "dap4_din_pp5";
                                 nvidia,function = "rsvd3";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        dap4_dout_pp6 { /* NC */
+                        dap4-dout-pp6 { /* NC */
                                 nvidia,pins = "dap4_dout_pp6";
                                 nvidia,function = "rsvd4";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        dap4_sclk_pp7 { /* NC */
+                        dap4-sclk-pp7 { /* NC */
                                 nvidia,pins = "dap4_sclk_pp7";
                                 nvidia,function = "rsvd3";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_col3_pq3 { /* NC */
+                        kb-col3-pq3 { /* NC */
                                 nvidia,pins = "kb_col3_pq3";
                                 nvidia,function = "kbc";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_row3_pr3 { /* NC */
+                        kb-row3-pr3 { /* NC */
                                 nvidia,pins = "kb_row3_pr3";
                                 nvidia,function = "kbc";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_row4_pr4 { /* NC */
+                        kb-row4-pr4 { /* NC */
                                 nvidia,pins = "kb_row4_pr4";
                                 nvidia,function = "rsvd3";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_row5_pr5 { /* NC */
+                        kb-row5-pr5 { /* NC */
                                 nvidia,pins = "kb_row5_pr5";
                                 nvidia,function = "rsvd3";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_row6_pr6 { /* NC */
+                        kb-row6-pr6 { /* NC */
                                 nvidia,pins = "kb_row6_pr6";
                                 nvidia,function = "kbc";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_row7_pr7 { /* NC */
+                        kb-row7-pr7 { /* NC */
                                 nvidia,pins = "kb_row7_pr7";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_row8_ps0 { /* NC */
+                        kb-row8-ps0 { /* NC */
                                 nvidia,pins = "kb_row8_ps0";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_row9_ps1 { /* NC */
+                        kb-row9-ps1 { /* NC */
                                 nvidia,pins = "kb_row9_ps1";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_row12_ps4 { /* NC */
+                        kb-row12-ps4 { /* NC */
                                 nvidia,pins = "kb_row12_ps4";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_row13_ps5 { /* NC */
+                        kb-row13-ps5 { /* NC */
                                 nvidia,pins = "kb_row13_ps5";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_row14_ps6 { /* NC */
+                        kb-row14-ps6 { /* NC */
                                 nvidia,pins = "kb_row14_ps6";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_row15_ps7 { /* NC */
+                        kb-row15-ps7 { /* NC */
                                 nvidia,pins = "kb_row15_ps7";
                                 nvidia,function = "rsvd3";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_row16_pt0 { /* NC */
+                        kb-row16-pt0 { /* NC */
                                 nvidia,pins = "kb_row16_pt0";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_row17_pt1 { /* NC */
+                        kb-row17-pt1 { /* NC */
                                 nvidia,pins = "kb_row17_pt1";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
@@ -1496,14 +1498,14 @@
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        gpio_x1_aud_px1 { /* NC */
+                        gpio-x1-aud-px1 { /* NC */
                                 nvidia,pins = "gpio_x1_aud_px1";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        gpio_x3_aud_px3 { /* NC */
+                        gpio-x3-aud-px3 { /* NC */
                                 nvidia,pins = "gpio_x3_aud_px3";
                                 nvidia,function = "rsvd4";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
@@ -1531,14 +1533,14 @@
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        clk3_req_pee1 { /* NC */
+                        clk3-req-pee1 { /* NC */
                                 nvidia,pins = "clk3_req_pee1";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        dap_mclk1_req_pee2 { /* NC */
+                        dap-mclk1-req-pee2 { /* NC */
                                 nvidia,pins = "dap_mclk1_req_pee2";
                                 nvidia,function = "rsvd4";
                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
@@ -1554,7 +1556,7 @@
                          * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
                          * bits being set to 0xfffd according to the TRM!
                          */
-                        sdmmc3_clk_lb_out_pee4 { /* NC */
+                        sdmmc3-clk-lb-out-pee4 { /* NC */
                                 nvidia,pins = "sdmmc3_clk_lb_out_pee4";
                                 nvidia,function = "sdmmc3";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -1589,8 +1591,9 @@
                 sgtl5000: codec@a {
                         compatible = "fsl,sgtl5000";
                         reg = <0x0a>;
-                        VDDA-supply = <&reg_3v3>;
-                        VDDIO-supply = <&vddio_1v8>;
+                        VDDA-supply = <&reg_module_3v3_audio>;
+                        VDDD-supply = <&reg_1v8_vddio>;
+                        VDDIO-supply = <&reg_1v8_vddio>;
                         clocks = <&tegra_car TEGRA124_CLK_EXTERN1>;
                 };
 
@@ -1607,14 +1610,14 @@
                         pinctrl-0 = <&as3722_default>;
 
                         as3722_default: pinmux {
-                                gpio2_7 {
+                                gpio2-7 {
                                         pins = "gpio2", /* PWR_EN_+V3.3 */
                                                "gpio7"; /* +V1.6_LPO */
                                         function = "gpio";
                                         bias-pull-up;
                                 };
 
-                                gpio0_1_3_4_5_6 {
+                                gpio0-1-3-4-5-6 {
                                         pins = "gpio0", "gpio1", "gpio3",
                                                "gpio4", "gpio5", "gpio6";
                                         bias-high-impedance;
@@ -1622,18 +1625,18 @@
                         };
 
                         regulators {
-                                vsup-sd2-supply = <&reg_3v3>;
-                                vsup-sd3-supply = <&reg_3v3>;
-                                vsup-sd4-supply = <&reg_3v3>;
-                                vsup-sd5-supply = <&reg_3v3>;
-                                vin-ldo0-supply = <&vddio_ddr_1v35>;
-                                vin-ldo1-6-supply = <&reg_3v3>;
-                                vin-ldo2-5-7-supply = <&vddio_1v8>;
-                                vin-ldo3-4-supply = <&reg_3v3>;
-                                vin-ldo9-10-supply = <&reg_3v3>;
-                                vin-ldo11-supply = <&reg_3v3>;
-
-                                vdd_cpu: sd0 {
+                                vsup-sd2-supply = <&reg_module_3v3>;
+                                vsup-sd3-supply = <&reg_module_3v3>;
+                                vsup-sd4-supply = <&reg_module_3v3>;
+                                vsup-sd5-supply = <&reg_module_3v3>;
+                                vin-ldo0-supply = <&reg_1v35_vddio_ddr>;
+                                vin-ldo1-6-supply = <&reg_module_3v3>;
+                                vin-ldo2-5-7-supply = <&reg_1v8_vddio>;
+                                vin-ldo3-4-supply = <&reg_module_3v3>;
+                                vin-ldo9-10-supply = <&reg_module_3v3>;
+                                vin-ldo11-supply = <&reg_module_3v3>;
+
+                                reg_vdd_cpu: sd0 {
                                         regulator-name = "+VDD_CPU_AP";
                                         regulator-min-microvolt = <700000>;
                                         regulator-max-microvolt = <1400000>;
@@ -1655,7 +1658,7 @@
                                         ams,ext-control = <1>;
                                 };
 
-                                vddio_ddr_1v35: sd2 {
+                                reg_1v35_vddio_ddr: sd2 {
                                         regulator-name =
                                                 "+V1.35_VDDIO_DDR(sd2)";
                                         regulator-min-microvolt = <1350000>;
@@ -1673,13 +1676,13 @@
                                         regulator-boot-on;
                                 };
 
-                                vdd_1v05: sd4 {
+                                reg_1v05_vdd: sd4 {
                                         regulator-name = "+V1.05";
                                         regulator-min-microvolt = <1050000>;
                                         regulator-max-microvolt = <1050000>;
                                 };
 
-                                vddio_1v8: sd5 {
+                                reg_1v8_vddio: sd5 {
                                         regulator-name = "+V1.8";
                                         regulator-min-microvolt = <1800000>;
                                         regulator-max-microvolt = <1800000>;
@@ -1687,7 +1690,7 @@
                                         regulator-always-on;
                                 };
 
-                                vdd_gpu: sd6 {
+                                reg_vdd_gpu: sd6 {
                                         regulator-name = "+VDD_GPU_AP";
                                         regulator-min-microvolt = <650000>;
                                         regulator-max-microvolt = <1200000>;
@@ -1697,7 +1700,7 @@
                                         regulator-always-on;
                                 };
 
-                                avdd_1v05: ldo0 {
+                                reg_1v05_avdd: ldo0 {
                                         regulator-name = "+V1.05_AVDD";
                                         regulator-min-microvolt = <1050000>;
                                         regulator-max-microvolt = <1050000>;
@@ -1772,12 +1775,13 @@
                  * TMP451 temperature sensor
                  * Note: THERM_N directly connected to AS3722 PMIC THERM
                  */
-                temperature-sensor@4c {
+                temp-sensor@4c {
                         compatible = "ti,tmp451";
                         reg = <0x4c>;
                         interrupt-parent = <&gpio>;
                         interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
                         #thermal-sensor-cells = <1>;
+                        vcc-supply = <&reg_module_3v3>;
                 };
         };
 
@@ -1809,9 +1813,9 @@
         sata@70020000 {
                 phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
                 phy-names = "sata-0";
-                avdd-supply = <&vdd_1v05>;
-                hvdd-supply = <&reg_3v3>;
-                vddio-supply = <&vdd_1v05>;
+                avdd-supply = <&reg_1v05_vdd>;
+                hvdd-supply = <&reg_module_3v3>;
+                vddio-supply = <&reg_1v05_vdd>;
         };
 
         usb@70090000 {
@@ -1822,14 +1826,14 @@
                        <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
                        <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
                 phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0";
-                avddio-pex-supply = <&vdd_1v05>;
-                avdd-pll-erefe-supply = <&avdd_1v05>;
-                avdd-pll-utmip-supply = <&vddio_1v8>;
-                avdd-usb-ss-pll-supply = <&vdd_1v05>;
-                avdd-usb-supply = <&reg_3v3>;
-                dvddio-pex-supply = <&vdd_1v05>;
-                hvdd-usb-ss-pll-e-supply = <&reg_3v3>;
-                hvdd-usb-ss-supply = <&reg_3v3>;
+                avddio-pex-supply = <&reg_1v05_vdd>;
+                avdd-pll-erefe-supply = <&reg_1v05_avdd>;
+                avdd-pll-utmip-supply = <&reg_1v8_vddio>;
+                avdd-usb-ss-pll-supply = <&reg_1v05_vdd>;
+                avdd-usb-supply = <&reg_module_3v3>;
+                dvddio-pex-supply = <&reg_1v05_vdd>;
+                hvdd-usb-ss-pll-e-supply = <&reg_module_3v3>;
+                hvdd-usb-ss-supply = <&reg_module_3v3>;
         };
 
         padctl@7009f000 {
@@ -1839,18 +1843,18 @@
 
                                 lanes {
                                         usb2-0 {
-                                                nvidia,function = "xusb";
                                                 status = "okay";
+                                                nvidia,function = "xusb";
                                         };
 
                                         usb2-1 {
-                                                nvidia,function = "xusb";
                                                 status = "okay";
+                                                nvidia,function = "xusb";
                                         };
 
                                         usb2-2 {
-                                                nvidia,function = "xusb";
                                                 status = "okay";
+                                                nvidia,function = "xusb";
                                         };
                                 };
                         };
@@ -1860,28 +1864,28 @@
 
                                 lanes {
                                         pcie-0 {
-                                                nvidia,function = "usb3-ss";
                                                 status = "okay";
+                                                nvidia,function = "usb3-ss";
                                         };
 
                                         pcie-1 {
-                                                nvidia,function = "usb3-ss";
                                                 status = "okay";
+                                                nvidia,function = "usb3-ss";
                                         };
 
                                         pcie-2 {
-                                                nvidia,function = "pcie";
                                                 status = "okay";
+                                                nvidia,function = "pcie";
                                         };
 
                                         pcie-3 {
-                                                nvidia,function = "pcie";
                                                 status = "okay";
+                                                nvidia,function = "pcie";
                                         };
 
                                         pcie-4 {
-                                                nvidia,function = "pcie";
                                                 status = "okay";
+                                                nvidia,function = "pcie";
                                         };
                                 };
                         };
@@ -1891,8 +1895,8 @@
 
                                 lanes {
                                         sata-0 {
-                                                nvidia,function = "sata";
                                                 status = "okay";
+                                                nvidia,function = "sata";
                                         };
                                 };
                         };
@@ -1903,7 +1907,6 @@
                         usb2-0 {
                                 status = "okay";
                                 mode = "otg";
-
                                 vbus-supply = <&reg_usbo1_vbus>;
                         };
 
@@ -1911,7 +1914,6 @@
                         usb2-1 {
                                 status = "okay";
                                 mode = "host";
-
                                 vbus-supply = <&reg_usbh_vbus>;
                         };
 
@@ -1919,18 +1921,19 @@
                         usb2-2 {
                                 status = "okay";
                                 mode = "host";
-
                                 vbus-supply = <&reg_usbh_vbus>;
                         };
 
                         usb3-0 {
-                                nvidia,usb2-companion = <2>;
                                 status = "okay";
+                                nvidia,usb2-companion = <2>;
+                                vbus-supply = <&reg_usbh_vbus>;
                         };
 
                         usb3-1 {
-                                nvidia,usb2-companion = <0>;
                                 status = "okay";
+                                nvidia,usb2-companion = <0>;
+                                vbus-supply = <&reg_usbo1_vbus>;
                         };
                 };
         };
@@ -1940,13 +1943,16 @@
                 status = "okay";
                 bus-width = <8>;
                 non-removable;
+                vmmc-supply = <&reg_module_3v3>; /* VCC */
+                vqmmc-supply = <&reg_1v8_vddio>; /* VCCQ */
+                mmc-ddr-1_8v;
         };
 
         /* CPU DFLL clock */
         clock@70110000 {
                 status = "okay";
-                vdd-cpu-supply = <&vdd_cpu>;
                 nvidia,i2c-fs-rate = <400000>;
+                vdd-cpu-supply = <&reg_vdd_cpu>;
         };
 
         ahub@70300000 {
@@ -1955,22 +1961,15 @@
                 };
         };
 
-        clocks {
-                compatible = "simple-bus";
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                clk32k_in: clock@0 {
-                        compatible = "fixed-clock";
-                        reg = <0>;
-                        #clock-cells = <0>;
-                        clock-frequency = <32768>;
-                };
+        clk32k_in: osc3 {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <32768>;
         };
 
         cpus {
                 cpu@0 {
-                        vdd-cpu-supply = <&vdd_cpu>;
+                        vdd-cpu-supply = <&reg_vdd_cpu>;
                 };
         };
 
@@ -1980,7 +1979,7 @@
                 regulator-min-microvolt = <1050000>;
                 regulator-max-microvolt = <1050000>;
                 gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
-                vin-supply = <&vdd_1v05>;
+                vin-supply = <&reg_1v05_vdd>;
         };
 
         reg_3v3_mxm: regulator-3v3-mxm {
@@ -1992,7 +1991,15 @@
                 regulator-boot-on;
         };
 
-        reg_3v3: regulator-3v3 {
+        reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
+                compatible = "regulator-fixed";
+                regulator-name = "+V3.3_AVDD_HDMI";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                vin-supply = <&reg_1v05_vdd>;
+        };
+
+        reg_module_3v3: regulator-module-3v3 {
                 compatible = "regulator-fixed";
                 regulator-name = "+V3.3";
                 regulator-min-microvolt = <3300000>;
@@ -2005,12 +2012,12 @@
                 vin-supply = <&reg_3v3_mxm>;
         };
 
-        reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
+        reg_module_3v3_audio: regulator-module-3v3-audio {
                 compatible = "regulator-fixed";
-                regulator-name = "+V3.3_AVDD_HDMI";
+                regulator-name = "+V3.3_AUDIO_AVDD_S";
                 regulator-min-microvolt = <3300000>;
                 regulator-max-microvolt = <3300000>;
-                vin-supply = <&vdd_1v05>;
+                regulator-always-on;
         };
 
         sound {
@@ -2064,7 +2071,7 @@
 
 &gpio {
         /* I210 Gigabit Ethernet Controller Reset */
-        lan_reset_n {
+        lan-reset-n {
                 gpio-hog;
                 gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
                 output-high;
@@ -2072,7 +2079,7 @@
         };
 
         /* Control MXM3 pin 26 Reset Module Output Carrier Input */
-        reset_moci_ctrl {
+        reset-moci-ctrl {
                 gpio-hog;
                 gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
                 output-high;
diff --git a/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts
new file mode 100644
index 000000000000..3c0f2681fcde
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts
@@ -0,0 +1,262 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "tegra20-colibri.dtsi"
+
+/ {
+        model = "Toradex Colibri T20 on Colibri Evaluation Board";
+        compatible = "toradex,colibri_t20-eval-v3", "toradex,colibri_t20",
+                     "nvidia,tegra20";
+
+        aliases {
+                rtc0 = "/i2c@7000c000/rtc@68";
+                rtc1 = "/i2c@7000d000/pmic@34";
+                rtc2 = "/rtc@7000e000";
+                serial0 = &uarta;
+                serial1 = &uartd;
+                serial2 = &uartb;
+        };
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+
+        host1x@50000000 {
+                dc@54200000 {
+                        rgb {
+                                status = "okay";
+                                nvidia,panel = <&panel>;
+                        };
+                };
+
+                hdmi@54280000 {
+                        status = "okay";
+                        hdmi-supply = <&reg_5v0>;
+                };
+        };
+
+        pinmux@70000014 {
+                state_default: pinmux {
+                        bl-on {
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        ddc {
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        hotplug-detect {
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        i2c {
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        lcd {
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        lm1 {
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        mmc {
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        mmccd {
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        pwm-a-b {
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        pwm-c-d {
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        ssp {
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        uart-a {
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        uart-b {
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        uart-c {
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        usbh-pen {
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                };
+        };
+
+        /* Colibri UART-A */
+        serial@70006000 {
+                status = "okay";
+        };
+
+        /* Colibri UART-C */
+        serial@70006040 {
+                status = "okay";
+        };
+
+        /* Colibri UART-B */
+        serial@70006300 {
+                status = "okay";
+        };
+
+        pwm@7000a000 {
+                status = "okay";
+        };
+
+        /*
+         * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
+         * board)
+         */
+        i2c@7000c000 {
+                status = "okay";
+                clock-frequency = <400000>;
+
+                /* M41T0M6 real time clock on carrier board */
+                rtc@68 {
+                        compatible = "st,m41t0";
+                        reg = <0x68>;
+                };
+        };
+
+        /* GEN2_I2C: unused */
+
+        /* CAM_I2C (I2C3): unused */
+
+        /* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */
+        i2c@7000c400 {
+                status = "okay";
+        };
+
+        /* EHCI instance 0: USB1_DP/N -> USBC_P/N */
+        usb@c5000000 {
+                status = "okay";
+                dr_mode = "otg";
+        };
+
+        usb-phy@c5000000 {
+                status = "okay";
+                vbus-supply = <&reg_usbc_vbus>;
+        };
+
+        /* EHCI instance 2: USB3_DP/N -> USBH_P/N */
+        usb@c5008000 {
+                status = "okay";
+        };
+
+        usb-phy@c5008000 {
+                status = "okay";
+                vbus-supply = <&reg_usbh_vbus>;
+        };
+
+        /* SPI4: Colibri SSP */
+        spi@7000da00 {
+                status = "okay";
+                spi-max-frequency = <25000000>;
+
+                can@0 {
+                        compatible = "microchip,mcp2515";
+                        reg = <0>;
+                        clocks = <&clk16m>;
+                        interrupt-parent = <&gpio>;
+                        /* CAN_INT */
+                        interrupts = <TEGRA_GPIO(A, 0) IRQ_TYPE_EDGE_FALLING>;
+                        spi-max-frequency = <10000000>;
+                        vdd-supply = <&reg_3v3>;
+                        xceiver-supply = <&reg_5v0>;
+                };
+        };
+
+        /* SD/MMC */
+        sdhci@c8000600 {
+                status = "okay";
+                bus-width = <4>;
+                cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */
+                no-1-8-v;
+        };
+
+        backlight: backlight {
+                compatible = "pwm-backlight";
+                brightness-levels = <255 128 64 32 16 8 4 0>;
+                default-brightness-level = <6>;
+                /* BL_ON */
+                enable-gpios = <&gpio TEGRA_GPIO(T, 4) GPIO_ACTIVE_HIGH>;
+                power-supply = <&reg_3v3>;
+                pwms = <&pwm 0 5000000>; /* PWM<A> */
+        };
+
+        clk16m: osc3 {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <16000000>;
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+
+                wakeup {
+                        label = "SODIMM pin 45 wakeup";
+                        gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
+                        linux,code = <KEY_WAKEUP>;
+                        debounce-interval = <10>;
+                        wakeup-source;
+                };
+        };
+
+        panel: panel {
+                /*
+                 * edt,et057090dhu: EDT 5.7" LCD TFT
+                 * edt,et070080dh6: EDT 7.0" LCD TFT
+                 */
+                compatible = "edt,et057090dhu", "simple-panel";
+                backlight = <&backlight>;
+                power-supply = <&reg_3v3>;
+        };
+
+        reg_3v3: regulator-3v3 {
+                compatible = "regulator-fixed";
+                regulator-name = "3.3V_SW";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
+
+        reg_5v0: regulator-5v0 {
+                compatible = "regulator-fixed";
+                regulator-name = "5V_SW";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+        };
+
+        reg_usbc_vbus: regulator-usbc-vbus {
+                compatible = "regulator-fixed";
+                regulator-name = "VCC_USB5";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                vin-supply = <&reg_5v0>;
+        };
+
+        /* USBH_PEN resp. USB_P_EN */
+        reg_usbh_vbus: regulator-usbh-vbus {
+                compatible = "regulator-fixed";
+                regulator-name = "VCC_USB[1-4]";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
+                vin-supply = <&reg_5v0>;
+        };
+};
diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts
index 57f16c0e9917..d8004d68efa0 100644
--- a/arch/arm/boot/dts/tegra20-colibri-iris.dts
+++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts
@@ -1,15 +1,21 @@
 // SPDX-License-Identifier: GPL-2.0
 /dts-v1/;
 
+#include <dt-bindings/input/input.h>
 #include "tegra20-colibri.dtsi"
 
 / {
-        model = "Toradex Colibri T20 256/512 MB on Iris";
-        compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20";
+        model = "Toradex Colibri T20 on Iris";
+        compatible = "toradex,colibri_t20-iris", "toradex,colibri_t20",
+                     "nvidia,tegra20";
 
         aliases {
+                rtc0 = "/i2c@7000c000/rtc@68";
+                rtc1 = "/i2c@7000d000/pmic@34";
+                rtc2 = "/rtc@7000e000";
                 serial0 = &uarta;
                 serial1 = &uartd;
+                serial2 = &uartb;
         };
 
         chosen {
@@ -17,90 +23,222 @@
         };
 
         host1x@50000000 {
+                dc@54200000 {
+                        rgb {
+                                status = "okay";
+                                nvidia,panel = <&panel>;
+                        };
+                };
+
                 hdmi@54280000 {
                         status = "okay";
+                        hdmi-supply = <&reg_5v0>;
                 };
         };
 
         pinmux@70000014 {
                 state_default: pinmux {
-                        hdint {
+                        bl-on {
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        ddc {
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        hotplug-detect {
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        i2c {
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        lcd {
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        lm1 {
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        mmc {
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        mmccd {
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        pwm-a-b {
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        pwm-c-d {
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        ssp {
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
 
-                        i2cddc {
+                        uart-a {
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
 
-                        sdio4 {
+                        uart-b {
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
 
-                        uarta {
+                        uart-c {
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
 
-                        uartd {
+                        usbh-pen {
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                 };
         };
 
+        /* Colibri UART-A */
         serial@70006000 {
                 status = "okay";
         };
 
+        /* Colibri UART-C */
+        serial@70006040 {
+                status = "okay";
+        };
+
+        /* Colibri UART-B */
         serial@70006300 {
                 status = "okay";
         };
 
-        i2c_ddc: i2c@7000c400 {
+        pwm@7000a000 {
+                status = "okay";
+        };
+
+        /*
+         * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
+         * board)
+         */
+        i2c@7000c000 {
+                status = "okay";
+                clock-frequency = <400000>;
+
+                /* M41T0M6 real time clock on carrier board */
+                rtc@68 {
+                        compatible = "st,m41t0";
+                        reg = <0x68>;
+                };
+        };
+
+        /* GEN2_I2C: unused */
+
+        /* CAM_I2C (I2C3): unused */
+
+        /* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */
+        i2c@7000c400 {
                 status = "okay";
         };
 
+        /* EHCI instance 0: USB1_DP/N -> USBC_P/N */
         usb@c5000000 {
                 status = "okay";
+                dr_mode = "otg";
         };
 
         usb-phy@c5000000 {
                 status = "okay";
+                vbus-supply = <&reg_usbc_vbus>;
         };
 
+        /* EHCI instance 2: USB3_DP/N -> USBH_P/N */
         usb@c5008000 {
                 status = "okay";
         };
 
         usb-phy@c5008000 {
                 status = "okay";
+                vbus-supply = <&reg_usbh_vbus>;
+        };
+
+        /* SPI4: Colibri SSP */
+        spi@7000da00 {
+                status = "okay";
+                spi-max-frequency = <25000000>;
         };
 
+        /* SD/MMC */
         sdhci@c8000600 {
                 status = "okay";
                 bus-width = <4>;
-                vmmc-supply = <&vcc_sd_reg>;
-                vqmmc-supply = <&vcc_sd_reg>;
-        };
-
-        regulators {
-                regulator@0 {
-                        compatible = "regulator-fixed";
-                        reg = <0>;
-                        regulator-name = "usb_host_vbus";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
-                        regulator-boot-on;
-                        regulator-always-on;
-                        gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
-                };
+                cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */
+                no-1-8-v;
+        };
+
+        backlight: backlight {
+                compatible = "pwm-backlight";
+                brightness-levels = <255 128 64 32 16 8 4 0>;
+                default-brightness-level = <6>;
+                /* BL_ON */
+                enable-gpios = <&gpio TEGRA_GPIO(T, 4) GPIO_ACTIVE_HIGH>;
+                power-supply = <&reg_3v3>;
+                pwms = <&pwm 0 5000000>; /* PWM<A> */
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
 
-                vcc_sd_reg: regulator@1 {
-                        compatible = "regulator-fixed";
-                        reg = <1>;
-                        regulator-name = "vcc_sd";
-                        regulator-min-microvolt = <3300000>;
-                        regulator-max-microvolt = <3300000>;
-                        regulator-boot-on;
-                        regulator-always-on;
+                wakeup {
+                        label = "SODIMM pin 45 wakeup";
+                        gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
+                        linux,code = <KEY_WAKEUP>;
+                        debounce-interval = <10>;
+                        wakeup-source;
                 };
         };
+
+        panel: panel {
+                /*
+                 * edt,et057090dhu: EDT 5.7" LCD TFT
+                 * edt,et070080dh6: EDT 7.0" LCD TFT
+                 */
+                compatible = "edt,et057090dhu", "simple-panel";
+                backlight = <&backlight>;
+                power-supply = <&reg_3v3>;
+        };
+
+        reg_3v3: regulator-3v3 {
+                compatible = "regulator-fixed";
+                regulator-name = "3.3V";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
+
+        reg_5v0: regulator-5v0 {
+                compatible = "regulator-fixed";
+                regulator-name = "5V";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+        };
+
+        reg_usbc_vbus: regulator-usbc-vbus {
+                compatible = "regulator-fixed";
+                regulator-name = "VCC_USB2";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                vin-supply = <&reg_5v0>;
+        };
+
+        /* USBH_PEN resp. USB_P_EN */
+        reg_usbh_vbus: regulator-usbh-vbus {
+                compatible = "regulator-fixed";
+                regulator-name = "VCC_USB1";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
+                vin-supply = <&reg_5v0>;
+        };
 };
diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi
index e7b9ab09908a..6162d193e12c 100644
--- a/arch/arm/boot/dts/tegra20-colibri.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri.dtsi
@@ -1,15 +1,13 @@
 // SPDX-License-Identifier: GPL-2.0
 #include "tegra20.dtsi"
 
+/*
+ * Toradex Colibri T20 Module Device Tree
+ * Compatible for Revisions Colibri T20 256MB V1.1B, V1.2A;
+ * Colibri T20 256MB IT V1.2A; Colibri T20 512MB V1.1C, V1.2A;
+ * Colibri T20 512MB IT V1.2A
+ */
 / {
-        model = "Toradex Colibri T20 256/512 MB";
-        compatible = "toradex,colibri_t20-512", "nvidia,tegra20";
-
-        aliases {
-                rtc0 = "/i2c@7000d000/tps6586x@34";
-                rtc1 = "/rtc@7000e000";
-        };
-
         memory@0 {
                 /*
                  * Set memory to 256 MB to be safe as this could be used on
@@ -21,12 +19,11 @@
 
         host1x@50000000 {
                 hdmi@54280000 {
-                        vdd-supply = <&hdmi_vdd_reg>;
-                        pll-supply = <&hdmi_pll_reg>;
-
-                        nvidia,ddc-i2c-bus = <&i2c_ddc>;
-                        nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
-                                GPIO_ACTIVE_HIGH>;
+                        nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+                        nvidia,hpd-gpio =
+                                <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
+                        pll-supply = <&reg_1v8_avdd_hdmi_pll>;
+                        vdd-supply = <&reg_3v3_avdd_hdmi>;
                 };
         };
 
@@ -35,187 +32,406 @@
                 pinctrl-0 = <&state_default>;
 
                 state_default: pinmux {
-                        audio_refclk {
+                        /* Analogue Audio AC97 to WM9712 (On-module) */
+                        audio-refclk {
                                 nvidia,pins = "cdev1";
                                 nvidia,function = "plla_out";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
-                        crt {
-                                nvidia,pins = "crtp";
-                                nvidia,function = "crt";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                        };
                         dap3 {
                                 nvidia,pins = "dap3";
                                 nvidia,function = "dap3";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
-                        displaya {
-                                nvidia,pins = "ld0", "ld1", "ld2", "ld3",
-                                        "ld4", "ld5", "ld6", "ld7", "ld8",
-                                        "ld9", "ld10", "ld11", "ld12", "ld13",
-                                        "ld14", "ld15", "ld16", "ld17",
-                                        "lhs", "lpw0", "lpw2", "lsc0",
-                                        "lsc1", "lsck", "lsda", "lspi", "lvs";
-                                nvidia,function = "displaya";
-                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                        };
-                        gpio_dte {
-                                nvidia,pins = "dte";
-                                nvidia,function = "rsvd1";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                        };
-                        gpio_gmi {
-                                nvidia,pins = "ata", "atc", "atd", "ate",
-                                        "dap1", "dap2", "dap4", "gpu", "irrx",
-                                        "irtx", "spia", "spib", "spic";
-                                nvidia,function = "gmi";
+
+                        /*
+                         * AC97_RESET, ULPI_RESET, AC97_INT aka WM9712 GENIRQ
+                         * (All on-module), SODIMM Pin 45 Wakeup
+                         */
+                        gpio-uac {
+                                nvidia,pins = "uac";
+                                nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
-                        gpio_pta {
+
+                        /*
+                         * Buffer Enables for nPWE and RDnWR (On-module,
+                         * see GPIO hogging further down below)
+                         */
+                        gpio-pta {
                                 nvidia,pins = "pta";
                                 nvidia,function = "rsvd4";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
-                        gpio_uac {
-                                nvidia,pins = "uac";
-                                nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+
+                        /*
+                         * CLK_32K_OUT, CORE_PWR_REQ, CPU_PWR_REQ, PWR_INT_N,
+                         * SYS_CLK_REQ (All on-module)
+                         */
+                        pmc {
+                                nvidia,pins = "pmc";
+                                nvidia,function = "pwr_on";
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
-                        hdint {
-                                nvidia,pins = "hdint";
+
+                        /*
+                         * Colibri Address/Data Bus (GMI)
+                         * Note: spid and spie optionally used for SPI1
+                         */
+                        gmi {
+                                nvidia,pins = "atc", "atd", "ate", "dap1",
+                                              "dap2", "dap4", "gmd", "gpu",
+                                              "irrx", "irtx", "spia", "spib",
+                                              "spic", "spid", "spie", "uca",
+                                              "ucb";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                        };
+                        /* Further pins may be used as GPIOs */
+                        gmi-gpio1 {
+                                nvidia,pins = "lpw0", "lsc1", "lsck", "lsda";
                                 nvidia,function = "hdmi";
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
-                        i2c1 {
-                                nvidia,pins = "rm";
-                                nvidia,function = "i2c1";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                        gmi-gpio2 {
+                                nvidia,pins = "lcsn", "ldc", "lm0", "lsdi";
+                                nvidia,function = "rsvd4";
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
-                        i2c3 {
-                                nvidia,pins = "dtf";
-                                nvidia,function = "i2c3";
+
+                        /* Colibri BL_ON */
+                        bl-on {
+                                nvidia,pins = "dta";
+                                nvidia,function = "rsvd1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
-                        i2cddc {
+
+                        /* Colibri Backlight PWM<A>, PWM<B> */
+                        pwm-a-b {
+                                nvidia,pins = "sdc";
+                                nvidia,function = "pwm";
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Colibri DDC */
+                        ddc {
                                 nvidia,pins = "ddc";
                                 nvidia,function = "i2c2";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
-                        i2cp {
-                                nvidia,pins = "i2cp";
-                                nvidia,function = "i2cp";
+
+                        /*
+                         * Colibri EXT_IO*
+                         * Note: dtf optionally used for I2C3
+                         */
+                        ext-io {
+                                nvidia,pins = "dtf", "spdi";
+                                nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
-                        irda {
-                                nvidia,pins = "uad";
-                                nvidia,function = "irda";
+
+                        /*
+                         * Colibri Ethernet (On-module)
+                         * ULPI EHCI instance 1 USB2_DP/N -> AX88772B
+                         */
+                        ulpi {
+                                nvidia,pins = "uaa", "uab", "uda";
+                                nvidia,function = "ulpi";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
-                        nand {
-                                nvidia,pins = "kbca", "kbcc", "kbcd",
-                                        "kbce", "kbcf";
-                                nvidia,function = "nand";
+                        ulpi-refclk {
+                                nvidia,pins = "cdev2";
+                                nvidia,function = "pllp_out4";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
-                        owc {
-                                nvidia,pins = "owc";
-                                nvidia,function = "owr";
+
+                        /* Colibri HOTPLUG_DETECT (HDMI) */
+                        hotplug-detect {
+                                nvidia,pins = "hdint";
+                                nvidia,function = "hdmi";
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Colibri I2C */
+                        i2c {
+                                nvidia,pins = "rm";
+                                nvidia,function = "i2c1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
-                        pmc {
-                                nvidia,pins = "pmc";
-                                nvidia,function = "pwr_on";
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+
+                        /*
+                         * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE
+                         * today's display need DE, disable LCD_M1
+                         */
+                        lm1 {
+                                nvidia,pins = "lm1";
+                                nvidia,function = "rsvd3";
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
-                        pwm {
-                                nvidia,pins = "sdb", "sdc", "sdd";
-                                nvidia,function = "pwm";
+
+                        /* Colibri LCD (L_* resp. LDD<*>) */
+                        lcd {
+                                nvidia,pins = "ld0", "ld1", "ld2", "ld3",
+                                              "ld4", "ld5", "ld6", "ld7",
+                                              "ld8", "ld9", "ld10", "ld11",
+                                              "ld12", "ld13", "ld14", "ld15",
+                                              "ld16", "ld17", "lhs", "lsc0",
+                                              "lspi", "lvs";
+                                nvidia,function = "displaya";
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
-                        sdio4 {
-                                nvidia,pins = "atb", "gma", "gme";
+                        /* Colibri LCD (Optional 24 BPP Support) */
+                        lcd-24 {
+                                nvidia,pins = "ldi", "lhp0", "lhp1", "lhp2",
+                                              "lpp", "lvp1";
+                                nvidia,function = "displaya";
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Colibri MMC */
+                        mmc {
+                                nvidia,pins = "atb", "gma";
                                 nvidia,function = "sdio4";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
-                        spi1 {
-                                nvidia,pins = "spid", "spie", "spif";
-                                nvidia,function = "spi1";
+
+                        /* Colibri MMCCD */
+                        mmccd {
+                                nvidia,pins = "gmb";
+                                nvidia,function = "gmi_int";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
-                        spi4 {
+
+                        /* Colibri MMC (Optional 8-bit) */
+                        mmc-8bit {
+                                nvidia,pins = "gme";
+                                nvidia,function = "sdio4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /*
+                         * Colibri Parallel Camera (Optional)
+                         * pins multiplexed with others and therefore disabled
+                         * Note: dta used for BL_ON by default
+                         */
+                        cif-mclk {
+                                nvidia,pins = "csus";
+                                nvidia,function = "vi_sensor_clk";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                        };
+                        cif {
+                                nvidia,pins = "dtb", "dtc", "dtd";
+                                nvidia,function = "vi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Colibri PWM<C>, PWM<D> */
+                        pwm-c-d {
+                                nvidia,pins = "sdb", "sdd";
+                                nvidia,function = "pwm";
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Colibri SSP */
+                        ssp {
                                 nvidia,pins = "slxa", "slxc", "slxd", "slxk";
                                 nvidia,function = "spi4";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
-                        uarta {
+
+                        /* Colibri UART-A */
+                        uart-a {
                                 nvidia,pins = "sdio1";
                                 nvidia,function = "uarta";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
-                        uartd {
+                        uart-a-dsr {
+                                nvidia,pins = "lpw1";
+                                nvidia,function = "rsvd3";
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart-a-dcd {
+                                nvidia,pins = "lpw2";
+                                nvidia,function = "hdmi";
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Colibri UART-B */
+                        uart-b {
                                 nvidia,pins = "gmc";
                                 nvidia,function = "uartd";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
-                        ulpi {
-                                nvidia,pins = "uaa", "uab", "uda";
-                                nvidia,function = "ulpi";
+
+                        /* Colibri UART-C */
+                        uart-c {
+                                nvidia,pins = "uad";
+                                nvidia,function = "irda";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Colibri USB_CDET */
+                        usb-cdet {
+                                nvidia,pins = "spdo";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Colibri USBH_OC */
+                        usbh-oc {
+                                nvidia,pins = "spih";
+                                nvidia,function = "spi2_alt";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Colibri USBH_PEN */
+                        usbh-pen {
+                                nvidia,pins = "spig";
+                                nvidia,function = "spi2_alt";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Colibri VGA not supported */
+                        vga {
+                                nvidia,pins = "crtp";
+                                nvidia,function = "crt";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* I2C3 (Optional) */
+                        i2c3 {
+                                nvidia,pins = "dtf";
+                                nvidia,function = "i2c3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* JTAG_RTCK */
+                        jtag-rtck {
+                                nvidia,pins = "gpu7";
+                                nvidia,function = "rtck";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /*
+                         * LAN_RESET, LAN_EXT_WAKEUP and LAN_PME
+                         * (All On-module)
+                         */
+                        gpio-gpv {
+                                nvidia,pins = "gpv";
+                                nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
-                        ulpi_refclk {
-                                nvidia,pins = "cdev2";
-                                nvidia,function = "pllp_out4";
+
+                        /*
+                         * LAN_V_BUS, VDD_FAULT, BATT_FAULT, WM9712 PENDOWN
+                         * (All On-module); Colibri CAN_INT
+                         */
+                        gpio-dte {
+                                nvidia,pins = "dte";
+                                nvidia,function = "rsvd1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
-                        usb_gpio {
-                                nvidia,pins = "spig", "spih";
-                                nvidia,function = "spi2_alt";
+
+                        /* NAND (On-module) */
+                        nand {
+                                nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+                                              "kbce", "kbcf";
+                                nvidia,function = "nand";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
-                        vi {
-                                nvidia,pins = "dta", "dtb", "dtc", "dtd";
-                                nvidia,function = "vi";
+
+                        /* Onewire (Optional) */
+                        owr {
+                                nvidia,pins = "owc";
+                                nvidia,function = "owr";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
-                        vi_sc {
-                                nvidia,pins = "csus";
-                                nvidia,function = "vi_sensor_clk";
+
+                        /* Power I2C (On-module) */
+                        i2cp {
+                                nvidia,pins = "i2cp";
+                                nvidia,function = "i2cp";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* RESET_OUT */
+                        reset-out {
+                                nvidia,pins = "ata";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /*
+                         * SPI1 (Optional)
+                         * Note: spid and spie used for Colibri Address/Data
+                         *       Bus (GMI)
+                         */
+                        spi1 {
+                                nvidia,pins = "spid", "spie", "spif";
+                                nvidia,function = "spi1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                         };
+
+                        /*
+                         * THERMD_ALERT# (On-module), unlatched I2C address pin
+                         * of LM95245 temperature sensor therefore requires
+                         * disabling for now
+                         */
+                        lvp0 {
+                                nvidia,pins = "lvp0";
+                                nvidia,function = "rsvd3";
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                        };
                 };
         };
 
-        ac97: ac97@70002000 {
+        tegra_ac97: ac97@70002000 {
                 status = "okay";
-                nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
-                        GPIO_ACTIVE_HIGH>;
-                nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0)
-                        GPIO_ACTIVE_HIGH>;
+                nvidia,codec-reset-gpio =
+                        <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_HIGH>;
+                nvidia,codec-sync-gpio =
+                        <&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>;
+        };
+
+        serial@70006040 {
+                compatible = "nvidia,tegra20-hsuart";
+        };
+
+        serial@70006300 {
+                compatible = "nvidia,tegra20-hsuart";
         };
 
         nand-controller@70008000 {
@@ -243,7 +459,7 @@
         };
 
         /* DDC_SCL/SDA on X3 pin 15/16 (e.g. display EDID) */
-        i2c_ddc: i2c@7000c400 {
+        hdmi_ddc: i2c@7000c400 {
                 clock-frequency = <10000>;
         };
 
@@ -256,59 +472,45 @@
                 status = "okay";
                 clock-frequency = <100000>;
 
-                pmic: tps6586x@34 {
+                pmic@34 {
                         compatible = "ti,tps6586x";
                         reg = <0x34>;
                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
-
                         ti,system-power-controller;
-
                         #gpio-cells = <2>;
                         gpio-controller;
-
-                        sys-supply = <&vdd_3v3_reg>;
-                        vin-sm0-supply = <&sys_reg>;
-                        vin-sm1-supply = <&sys_reg>;
-                        vin-sm2-supply = <&sys_reg>;
-                        vinldo01-supply = <&sm2_reg>;
-                        vinldo23-supply = <&vdd_3v3_reg>;
-                        vinldo4-supply = <&vdd_3v3_reg>;
-                        vinldo678-supply = <&vdd_3v3_reg>;
-                        vinldo9-supply = <&vdd_3v3_reg>;
+                        sys-supply = <&reg_module_3v3>;
+                        vin-sm0-supply = <&reg_3v3_vsys>;
+                        vin-sm1-supply = <&reg_3v3_vsys>;
+                        vin-sm2-supply = <&reg_3v3_vsys>;
+                        vinldo01-supply = <&reg_1v8_vdd_ddr2>;
+                        vinldo23-supply = <&reg_module_3v3>;
+                        vinldo4-supply = <&reg_module_3v3>;
+                        vinldo678-supply = <&reg_module_3v3>;
+                        vinldo9-supply = <&reg_module_3v3>;
 
                         regulators {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-
-                                sys_reg: regulator@0 {
-                                        reg = <0>;
-                                        regulator-compatible = "sys";
-                                        regulator-name = "vdd_sys";
+                                reg_3v3_vsys: sys {
+                                        regulator-name = "VSYS_3.3V";
                                         regulator-always-on;
                                 };
 
-                                regulator@1 {
-                                        reg = <1>;
-                                        regulator-compatible = "sm0";
-                                        regulator-name = "vdd_sm0,vdd_core";
+                                sm0 {
+                                        regulator-name = "VDD_CORE_1.2V";
                                         regulator-min-microvolt = <1200000>;
                                         regulator-max-microvolt = <1200000>;
                                         regulator-always-on;
                                 };
 
-                                regulator@2 {
-                                        reg = <2>;
-                                        regulator-compatible = "sm1";
-                                        regulator-name = "vdd_sm1,vdd_cpu";
+                                sm1 {
+                                        regulator-name = "VDD_CPU_1.0V";
                                         regulator-min-microvolt = <1000000>;
                                         regulator-max-microvolt = <1000000>;
                                         regulator-always-on;
                                 };
 
-                                sm2_reg: regulator@3 {
-                                        reg = <3>;
-                                        regulator-compatible = "sm2";
-                                        regulator-name = "vdd_sm2,vin_ldo*";
+                                reg_1v8_vdd_ddr2: sm2 {
+                                        regulator-name = "VDD_DDR2_1.8V";
                                         regulator-min-microvolt = <1800000>;
                                         regulator-max-microvolt = <1800000>;
                                         regulator-always-on;
@@ -316,80 +518,68 @@
 
                                 /* LDO0 is not connected to anything */
 
-                                regulator@5 {
-                                        reg = <5>;
-                                        regulator-compatible = "ldo1";
-                                        regulator-name = "vdd_ldo1,avdd_pll*";
+                                /*
+                                 * +3.3V_ENABLE_N switching via FET:
+                                 * AVDD_AUDIO_S and +3.3V
+                                 * see also +3.3V fixed supply
+                                 */
+                                ldo1 {
+                                        regulator-name = "AVDD_PLL_1.1V";
                                         regulator-min-microvolt = <1100000>;
                                         regulator-max-microvolt = <1100000>;
                                         regulator-always-on;
                                 };
 
-                                regulator@6 {
-                                        reg = <6>;
-                                        regulator-compatible = "ldo2";
-                                        regulator-name = "vdd_ldo2,vdd_rtc";
+                                ldo2 {
+                                        regulator-name = "VDD_RTC_1.2V";
                                         regulator-min-microvolt = <1200000>;
                                         regulator-max-microvolt = <1200000>;
                                 };
 
                                 /* LDO3 is not connected to anything */
 
-                                regulator@8 {
-                                        reg = <8>;
-                                        regulator-compatible = "ldo4";
-                                        regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+                                ldo4 {
+                                        regulator-name = "VDDIO_SYS_1.8V";
                                         regulator-min-microvolt = <1800000>;
                                         regulator-max-microvolt = <1800000>;
                                         regulator-always-on;
                                 };
 
-                                ldo5_reg: regulator@9 {
-                                        reg = <9>;
-                                        regulator-compatible = "ldo5";
-                                        regulator-name = "vdd_ldo5,vdd_fuse";
+                                /* Switched via FET from regular +3.3V */
+                                ldo5 {
+                                        regulator-name = "+3.3V_USB";
                                         regulator-min-microvolt = <3300000>;
                                         regulator-max-microvolt = <3300000>;
                                         regulator-always-on;
                                 };
 
-                                regulator@10 {
-                                        reg = <10>;
-                                        regulator-compatible = "ldo6";
-                                        regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
+                                ldo6 {
+                                        regulator-name = "AVDD_VDAC_2.85V";
                                         regulator-min-microvolt = <2850000>;
                                         regulator-max-microvolt = <2850000>;
                                 };
 
-                                hdmi_vdd_reg: regulator@11 {
-                                        reg = <11>;
-                                        regulator-compatible = "ldo7";
-                                        regulator-name = "vdd_ldo7,avdd_hdmi";
+                                reg_3v3_avdd_hdmi: ldo7 {
+                                        regulator-name = "AVDD_HDMI_3.3V";
                                         regulator-min-microvolt = <3300000>;
                                         regulator-max-microvolt = <3300000>;
                                 };
 
-                                hdmi_pll_reg: regulator@12 {
-                                        reg = <12>;
-                                        regulator-compatible = "ldo8";
-                                        regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+                                reg_1v8_avdd_hdmi_pll: ldo8 {
+                                        regulator-name = "AVDD_HDMI_PLL_1.8V";
                                         regulator-min-microvolt = <1800000>;
                                         regulator-max-microvolt = <1800000>;
                                 };
 
-                                regulator@13 {
-                                        reg = <13>;
-                                        regulator-compatible = "ldo9";
-                                        regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
+                                ldo9 {
+                                        regulator-name = "VDDIO_RX_DDR_2.85V";
                                         regulator-min-microvolt = <2850000>;
                                         regulator-max-microvolt = <2850000>;
                                         regulator-always-on;
                                 };
 
-                                regulator@14 {
-                                        reg = <14>;
-                                        regulator-compatible = "ldo_rtc";
-                                        regulator-name = "vdd_rtc_out,vdd_cell";
+                                ldo_rtc {
+                                        regulator-name = "VCC_BATT";
                                         regulator-min-microvolt = <3300000>;
                                         regulator-max-microvolt = <3300000>;
                                         regulator-always-on;
@@ -397,7 +587,8 @@
                         };
                 };
 
-                temperature-sensor@4c {
+                /* LM95245 temperature sensor */
+                temp-sensor@4c {
                         compatible = "national,lm95245";
                         reg = <0x4c>;
                 };
@@ -410,6 +601,14 @@
                 nvidia,core-pwr-good-time = <3845 3845>;
                 nvidia,core-pwr-off-time = <3875>;
                 nvidia,sys-clock-req-active-high;
+
+                /* Set SLEEP MODE bit in SUPPLYENE register of TPS658643 PMIC */
+                i2c-thermtrip {
+                        nvidia,i2c-controller-id = <3>;
+                        nvidia,bus-addr = <0x34>;
+                        nvidia,reg-addr = <0x14>;
+                        nvidia,reg-data = <0x8>;
+                };
         };
 
         memory-controller@7000f400 {
@@ -483,79 +682,87 @@
                 };
         };
 
+        /* EHCI instance 1: ULPI PHY -> AX88772B (On-module) */
         usb@c5004000 {
                 status = "okay";
-                nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
-                        GPIO_ACTIVE_LOW>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                asix@1 {
+                        reg = <1>;
+                        local-mac-address = [00 00 00 00 00 00];
+                };
         };
 
         usb-phy@c5004000 {
                 status = "okay";
-                nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
-                        GPIO_ACTIVE_LOW>;
+                nvidia,phy-reset-gpio =
+                        <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>;
+                vbus-supply = <&reg_lan_v_bus>;
         };
 
-        sdhci@c8000600 {
-                cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
+        clk32k_in: xtal3 {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <32768>;
         };
 
-        clocks {
-                compatible = "simple-bus";
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                clk32k_in: clock@0 {
-                        compatible = "fixed-clock";
-                        reg = <0>;
-                        #clock-cells = <0>;
-                        clock-frequency = <32768>;
-                };
+        reg_lan_v_bus: regulator-lan-v-bus {
+                compatible = "regulator-fixed";
+                regulator-name = "LAN_V_BUS";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                enable-active-high;
+                gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
         };
 
-        regulators {
-                compatible = "simple-bus";
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                vdd_3v3_reg: regulator@100 {
-                        compatible = "regulator-fixed";
-                        reg = <100>;
-                        regulator-name = "vdd_3v3";
-                        regulator-min-microvolt = <3300000>;
-                        regulator-max-microvolt = <3300000>;
-                        regulator-always-on;
-                };
-
-                regulator@101 {
-                        compatible = "regulator-fixed";
-                        reg = <101>;
-                        regulator-name = "internal_usb";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
-                        enable-active-high;
-                        regulator-boot-on;
-                        regulator-always-on;
-                        gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
-                };
+        reg_module_3v3: regulator-module-3v3 {
+                compatible = "regulator-fixed";
+                regulator-name = "+V3.3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
         };
 
         sound {
                 compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
-                                 "nvidia,tegra-audio-wm9712";
-                nvidia,model = "Colibri T20 AC97 Audio";
-
+                             "nvidia,tegra-audio-wm9712";
+                nvidia,model = "Toradex Colibri T20";
                 nvidia,audio-routing =
                         "Headphone", "HPOUTL",
                         "Headphone", "HPOUTR",
                         "LineIn", "LINEINL",
                         "LineIn", "LINEINR",
                         "Mic", "MIC1";
-
-                nvidia,ac97-controller = <&ac97>;
-
+                nvidia,ac97-controller = <&tegra_ac97>;
                 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
                          <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
                          <&tegra_car TEGRA20_CLK_CDEV1>;
                 clock-names = "pll_a", "pll_a_out0", "mclk";
         };
 };
+
+&gpio {
+        lan-reset-n {
+                gpio-hog;
+                gpios = <TEGRA_GPIO(V, 4) GPIO_ACTIVE_HIGH>;
+                output-high;
+                line-name = "LAN_RESET#";
+        };
+
+        /* Tri-stating GMI_WR_N on SODIMM pin 99 nPWE */
+        npwe {
+                gpio-hog;
+                gpios = <TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
+                output-high;
+                line-name = "Tri-state nPWE";
+        };
+
+        /* Not tri-stating GMI_WR_N on SODIMM pin 93 RDnWR */
+        rdnwr {
+                gpio-hog;
+                gpios = <TEGRA_GPIO(T, 6) GPIO_ACTIVE_HIGH>;
+                output-low;
+                line-name = "Not tri-state RDnWR";
+        };
+};
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index ef245291924f..8861e0976e37 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -303,7 +303,7 @@
                 request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
                 slave-addr = <138>;
                 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
-                         <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
+                         <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
                 clock-names = "div-clk", "fast-clk";
                 resets = <&tegra_car 67>;
                 reset-names = "i2c";
@@ -524,10 +524,10 @@
         gpio-keys {
                 compatible = "gpio-keys";
 
-                power {
-                        label = "Power";
+                wakeup {
+                        label = "Wakeup";
                         gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>;
-                        linux,code = <KEY_POWER>;
+                        linux,code = <KEY_WAKEUP>;
                         wakeup-source;
                 };
         };
@@ -599,8 +599,8 @@
                         GPIO_ACTIVE_HIGH>;
 
                 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
-                         <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
-                         <&tegra_car TEGRA20_CLK_CDEV1>;
+                         <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA20_CLK_CDEV1>;
                 clock-names = "pll_a", "pll_a_out0", "mclk";
         };
 };
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 15b73bd377f0..20869757d32f 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -419,19 +419,6 @@
                 status = "disabled";
         };
 
-        gmi@70009000 {
-                compatible = "nvidia,tegra20-gmi";
-                reg = <0x70009000 0x1000>;
-                #address-cells = <2>;
-                #size-cells = <1>;
-                ranges = <0 0 0xd0000000 0xfffffff>;
-                clocks = <&tegra_car TEGRA20_CLK_NOR>;
-                clock-names = "gmi";
-                resets = <&tegra_car 42>;
-                reset-names = "gmi";
-                status = "disabled";
-        };
-
         nand-controller@70008000 {
                 compatible = "nvidia,tegra20-nand";
                 reg = <0x70008000 0x100>;
@@ -447,6 +434,19 @@
                 status = "disabled";
         };
 
+        gmi@70009000 {
+                compatible = "nvidia,tegra20-gmi";
+                reg = <0x70009000 0x1000>;
+                #address-cells = <2>;
+                #size-cells = <1>;
+                ranges = <0 0 0xd0000000 0xfffffff>;
+                clocks = <&tegra_car TEGRA20_CLK_NOR>;
+                clock-names = "gmi";
+                resets = <&tegra_car 42>;
+                reset-names = "gmi";
+                status = "disabled";
+        };
+
         pwm: pwm@7000a000 {
                 compatible = "nvidia,tegra20-pwm";
                 reg = <0x7000a000 0x100>;
@@ -865,5 +865,7 @@
                 compatible = "arm,cortex-a9-pmu";
                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
                              <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-affinity = <&{/cpus/cpu@0}>,
+                                     <&{/cpus/cpu@1}>;
         };
 };
diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts
index 0dc85a20bd45..749fc6d1ff70 100644
--- a/arch/arm/boot/dts/tegra30-apalis-eval.dts
+++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts
@@ -6,11 +6,12 @@
 
 / {
         model = "Toradex Apalis T30 on Apalis Evaluation Board";
-        compatible = "toradex,apalis_t30-eval", "toradex,apalis_t30", "nvidia,tegra30";
+        compatible = "toradex,apalis_t30-eval", "toradex,apalis_t30",
+                     "nvidia,tegra30";
 
         aliases {
                 rtc0 = "/i2c@7000c000/rtc@68";
-                rtc1 = "/i2c@7000d000/tps65911@2d";
+                rtc1 = "/i2c@7000d000/pmic@2d";
                 rtc2 = "/rtc@7000e000";
                 serial0 = &uarta;
                 serial1 = &uartb;
@@ -23,8 +24,6 @@
         };
 
         pcie@3000 {
-                status = "okay";
-
                 pci@1,0 {
                         status = "okay";
                 };
@@ -32,10 +31,6 @@
                 pci@2,0 {
                         status = "okay";
                 };
-
-                pci@3,0 {
-                        status = "okay";
-                };
         };
 
         host1x@50000000 {
@@ -45,27 +40,30 @@
                                 nvidia,panel = <&panel>;
                         };
                 };
+
                 hdmi@54280000 {
                         status = "okay";
+                        hdmi-supply = <&reg_5v0>;
                 };
         };
 
+        /* Apalis UART1 */
         serial@70006000 {
                 status = "okay";
         };
 
+        /* Apalis UART2 */
         serial@70006040 {
-                compatible = "nvidia,tegra30-hsuart";
                 status = "okay";
         };
 
+        /* Apalis UART3 */
         serial@70006200 {
-                compatible = "nvidia,tegra30-hsuart";
                 status = "okay";
         };
 
+        /* Apalis UART4 */
         serial@70006300 {
-                compatible = "nvidia,tegra30-hsuart";
                 status = "okay";
         };
 
@@ -99,13 +97,13 @@
          * CAM_I2C: I2C3_SDA/SCL on MXM3 pin 201/203 (e.g. camera sensor on
          * carrier board)
          */
-        cami2c: i2c@7000c500 {
+        i2c@7000c500 {
                 status = "okay";
                 clock-frequency = <400000>;
         };
 
         /* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */
-        hdmiddc: i2c@7000c700 {
+        i2c@7000c700 {
                 status = "okay";
         };
 
@@ -113,29 +111,16 @@
         spi@7000d400 {
                 status = "okay";
                 spi-max-frequency = <25000000>;
-                spidev0: spidev@1 {
-                        compatible = "spidev";
-                        reg = <1>;
-                        spi-max-frequency = <25000000>;
-                };
         };
 
         /* SPI5: Apalis SPI2 */
         spi@7000dc00 {
                 status = "okay";
                 spi-max-frequency = <25000000>;
-                spidev1: spidev@2 {
-                        compatible = "spidev";
-                        reg = <2>;
-                        spi-max-frequency = <25000000>;
-                };
-        };
-
-        hda@70030000 {
-                status = "okay";
         };
 
-        sd1: sdhci@78000000 {
+        /* Apalis SD1 */
+        sdhci@78000000 {
                 status = "okay";
                 bus-width = <4>;
                 /* SD1_CD# */
@@ -143,7 +128,8 @@
                 no-1-8-v;
         };
 
-        mmc1: sdhci@78000400 {
+        /* Apalis MMC1 */
+        sdhci@78000400 {
                 status = "okay";
                 bus-width = <8>;
                 /* MMC1_CD# */
@@ -154,12 +140,12 @@
         /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */
         usb@7d000000 {
                 status = "okay";
+                dr_mode = "otg";
         };
 
         usb-phy@7d000000 {
                 status = "okay";
-                dr_mode = "otg";
-                vbus-supply = <&usbo1_vbus_reg>;
+                vbus-supply = <&reg_usbo1_vbus>;
         };
 
         /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */
@@ -169,7 +155,7 @@
 
         usb-phy@7d004000 {
                 status = "okay";
-                vbus-supply = <&usbh_vbus_reg>;
+                vbus-supply = <&reg_usbh_vbus>;
         };
 
         /* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */
@@ -179,18 +165,17 @@
 
         usb-phy@7d008000 {
                 status = "okay";
-                vbus-supply = <&usbh_vbus_reg>;
+                vbus-supply = <&reg_usbh_vbus>;
         };
 
         backlight: backlight {
                 compatible = "pwm-backlight";
-
-                /* PWM_BKL1 */
-                pwms = <&pwm 0 5000000>;
                 brightness-levels = <255 231 223 207 191 159 127 0>;
                 default-brightness-level = <6>;
                 /* BKL1_ON */
                 enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
+                power-supply = <&reg_3v3>;
+                pwms = <&pwm 0 5000000>; /* BKL1_PWM */
         };
 
         gpio-keys {
@@ -211,64 +196,53 @@
                  * edt,et070080dh6: EDT 7.0" LCD TFT
                  */
                 compatible = "edt,et057090dhu", "simple-panel";
-
                 backlight = <&backlight>;
+                power-supply = <&reg_3v3>;
         };
 
-        pwmleds {
-                compatible = "pwm-leds";
-
-                pwm1 {
-                        label = "PWM1";
-                        pwms = <&pwm 3 19600>;
-                        max-brightness = <255>;
-                };
-
-                pwm2 {
-                        label = "PWM2";
-                        pwms = <&pwm 2 19600>;
-                        max-brightness = <255>;
-                };
+        reg_3v3: regulator-3v3 {
+                compatible = "regulator-fixed";
+                regulator-name = "3.3V_SW";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
 
-                pwm3 {
-                        label = "PWM3";
-                        pwms = <&pwm 1 19600>;
-                        max-brightness = <255>;
-                };
+        reg_5v0: regulator-5v0 {
+                compatible = "regulator-fixed";
+                regulator-name = "5V_SW";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
         };
 
-        regulators {
-                sys_5v0_reg: regulator@1 {
-                        compatible = "regulator-fixed";
-                        reg = <1>;
-                        regulator-name = "5v0";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
-                        regulator-always-on;
-                };
+        /* USBO1_EN */
+        reg_usbo1_vbus: regulator-usbo1-vbus {
+                compatible = "regulator-fixed";
+                regulator-name = "VCC_USBO1";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+                vin-supply = <&reg_5v0>;
+        };
 
-                /* USBO1_EN */
-                usbo1_vbus_reg: regulator@2 {
-                        compatible = "regulator-fixed";
-                        reg = <2>;
-                        regulator-name = "usbo1_vbus";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
-                        gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
-                        enable-active-high;
-                        vin-supply = <&sys_5v0_reg>;
-                };
+        /* USBH_EN */
+        reg_usbh_vbus: regulator-usbh-vbus {
+                compatible = "regulator-fixed";
+                regulator-name = "VCC_USBH(2A|2C|2D|3|4)";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+                vin-supply = <&reg_5v0>;
+        };
+};
 
-                /* USBH_EN */
-                usbh_vbus_reg: regulator@3 {
-                        compatible = "regulator-fixed";
-                        reg = <3>;
-                        regulator-name = "usbh_vbus";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
-                        gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
-                        enable-active-high;
-                        vin-supply = <&sys_5v0_reg>;
-                };
+&gpio {
+        /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */
+        pex-perst-n {
+                gpio-hog;
+                gpios = <TEGRA_GPIO(S, 7) GPIO_ACTIVE_HIGH>;
+                output-high;
+                line-name = "PEX_PERST_N";
         };
 };
diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts
new file mode 100644
index 000000000000..0be50e881684
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts
@@ -0,0 +1,266 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "tegra30-apalis-v1.1.dtsi"
+
+/ {
+        model = "Toradex Apalis T30 on Apalis Evaluation Board";
+        compatible = "toradex,apalis_t30-v1.1-eval", "toradex,apalis_t30-eval",
+                     "toradex,apalis_t30-v1.1", "toradex,apalis_t30",
+                     "nvidia,tegra30";
+
+        aliases {
+                rtc0 = "/i2c@7000c000/rtc@68";
+                rtc1 = "/i2c@7000d000/pmic@2d";
+                rtc2 = "/rtc@7000e000";
+                serial0 = &uarta;
+                serial1 = &uartb;
+                serial2 = &uartc;
+                serial3 = &uartd;
+        };
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+
+        pcie@3000 {
+                pci@1,0 {
+                        status = "okay";
+                };
+
+                pci@2,0 {
+                        status = "okay";
+                };
+        };
+
+        host1x@50000000 {
+                dc@54200000 {
+                        rgb {
+                                status = "okay";
+                                nvidia,panel = <&panel>;
+                        };
+                };
+
+                hdmi@54280000 {
+                        status = "okay";
+                        hdmi-supply = <&reg_5v0>;
+                };
+        };
+
+        /* Apalis UART1 */
+        serial@70006000 {
+                status = "okay";
+        };
+
+        /* Apalis UART2 */
+        serial@70006040 {
+                status = "okay";
+        };
+
+        /* Apalis UART3 */
+        serial@70006200 {
+                status = "okay";
+        };
+
+        /* Apalis UART4 */
+        serial@70006300 {
+                status = "okay";
+        };
+
+        pwm@7000a000 {
+                status = "okay";
+        };
+
+        /*
+         * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier
+         * board)
+         */
+        i2c@7000c000 {
+                status = "okay";
+                clock-frequency = <400000>;
+
+                pcie-switch@58 {
+                        compatible = "plx,pex8605";
+                        reg = <0x58>;
+                };
+
+                /* M41T0M6 real time clock on carrier board */
+                rtc@68 {
+                        compatible = "st,m41t0";
+                        reg = <0x68>;
+                };
+        };
+
+        /* GEN2_I2C: unused */
+
+        /*
+         * CAM_I2C: I2C3_SDA/SCL on MXM3 pin 201/203 (e.g. camera sensor on
+         * carrier board)
+         */
+        i2c@7000c500 {
+                status = "okay";
+                clock-frequency = <400000>;
+        };
+
+        /* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */
+        i2c@7000c700 {
+                status = "okay";
+        };
+
+        /* SPI1: Apalis SPI1 */
+        spi@7000d400 {
+                status = "okay";
+                spi-max-frequency = <25000000>;
+        };
+
+        /* SPI5: Apalis SPI2 */
+        spi@7000dc00 {
+                status = "okay";
+                spi-max-frequency = <25000000>;
+        };
+
+        /* Apalis SD1 */
+        sdhci@78000000 {
+                status = "okay";
+                bus-width = <4>;
+                /* SD1_CD# */
+                cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_LOW>;
+                no-1-8-v;
+        };
+
+        /* Apalis MMC1 */
+        sdhci@78000400 {
+                status = "okay";
+                bus-width = <8>;
+                /* MMC1_CD# */
+                cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
+                vqmmc-supply = <&reg_vddio_sdmmc3>;
+        };
+
+        /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */
+        usb@7d000000 {
+                status = "okay";
+                dr_mode = "otg";
+        };
+
+        usb-phy@7d000000 {
+                status = "okay";
+                vbus-supply = <&reg_usbo1_vbus>;
+        };
+
+        /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */
+        usb@7d004000 {
+                status = "okay";
+        };
+
+        usb-phy@7d004000 {
+                status = "okay";
+                vbus-supply = <&reg_usbh_vbus>;
+        };
+
+        /* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */
+        usb@7d008000 {
+                status = "okay";
+        };
+
+        usb-phy@7d008000 {
+                status = "okay";
+                vbus-supply = <&reg_usbh_vbus>;
+        };
+
+        backlight: backlight {
+                compatible = "pwm-backlight";
+                brightness-levels = <255 231 223 207 191 159 127 0>;
+                default-brightness-level = <6>;
+                /* BKL1_ON */
+                enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
+                power-supply = <&reg_3v3>;
+                pwms = <&pwm 0 5000000>; /* BKL1_PWM */
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+
+                wakeup {
+                        label = "WAKE1_MICO";
+                        gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_WAKEUP>;
+                        debounce-interval = <10>;
+                        wakeup-source;
+                };
+        };
+
+        panel: panel {
+                /*
+                 * edt,et057090dhu: EDT 5.7" LCD TFT
+                 * edt,et070080dh6: EDT 7.0" LCD TFT
+                 */
+                compatible = "edt,et057090dhu", "simple-panel";
+                backlight = <&backlight>;
+                power-supply = <&reg_3v3>;
+        };
+
+        reg_3v3: regulator-3v3 {
+                compatible = "regulator-fixed";
+                regulator-name = "3.3V_SW";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
+
+        reg_5v0: regulator-5v0 {
+                compatible = "regulator-fixed";
+                regulator-name = "5V_SW";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+        };
+
+        /* USBO1_EN */
+        reg_usbo1_vbus: regulator-usbo1-vbus {
+                compatible = "regulator-fixed";
+                regulator-name = "VCC_USBO1";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+                vin-supply = <&reg_5v0>;
+        };
+
+        /* USBH_EN */
+        reg_usbh_vbus: regulator-usbh-vbus {
+                compatible = "regulator-fixed";
+                regulator-name = "VCC_USBH(2A|2C|2D|3|4)";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+                vin-supply = <&reg_5v0>;
+        };
+
+        /*
+         * 1.8 volt resp. 3.3 volt VDDIO_SDMMC3 depending on
+         * EN_+3.3_SDMMC3 GPIO
+         */
+        reg_vddio_sdmmc3: regulator-vddio-sdmmc3 {
+                compatible = "regulator-gpio";
+                regulator-name = "VDDIO_SDMMC3";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-type = "voltage";
+                gpios = <&gpio TEGRA_GPIO(J, 5) GPIO_ACTIVE_HIGH>;
+                states = <1800000 0x0
+                          3300000 0x1>;
+                startup-delay-us = <100000>;
+                vin-supply = <&vddio_sdmmc_1v8_reg>;
+        };
+};
+
+&gpio {
+        /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */
+        pex-perst-n {
+                gpio-hog;
+                gpios = <TEGRA_GPIO(S, 7) GPIO_ACTIVE_HIGH>;
+                output-high;
+                line-name = "PEX_PERST_N";
+        };
+};
diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi
new file mode 100644
index 000000000000..02f8126481a2
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi
@@ -0,0 +1,1189 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+#include "tegra30.dtsi"
+
+/*
+ * Toradex Apalis T30 Module Device Tree
+ * Compatible for Revisions 1GB: V1.1A, V1.1B; 1GB IT: V1.1A, V1.1B;
+ * 2GB: V1.1A, V1.1B
+ */
+/ {
+        memory@80000000 {
+                reg = <0x80000000 0x40000000>;
+        };
+
+        pcie@3000 {
+                status = "okay";
+                avdd-pexa-supply = <&vdd2_reg>;
+                avdd-pexb-supply = <&vdd2_reg>;
+                avdd-pex-pll-supply = <&vdd2_reg>;
+                avdd-plle-supply = <&ldo6_reg>;
+                hvdd-pex-supply = <&reg_module_3v3>;
+                vddio-pex-ctl-supply = <&reg_module_3v3>;
+                vdd-pexa-supply = <&vdd2_reg>;
+                vdd-pexb-supply = <&vdd2_reg>;
+
+                /* Apalis type specific */
+                pci@1,0 {
+                        nvidia,num-lanes = <4>;
+                };
+
+                /* Apalis PCIe */
+                pci@2,0 {
+                        nvidia,num-lanes = <1>;
+                };
+
+                /* I210/I211 Gigabit Ethernet Controller (on-module) */
+                pci@3,0 {
+                        status = "okay";
+                        nvidia,num-lanes = <1>;
+
+                        pcie@0 {
+                                reg = <0 0 0 0 0>;
+                                local-mac-address = [00 00 00 00 00 00];
+                        };
+                };
+        };
+
+        host1x@50000000 {
+                hdmi@54280000 {
+                        nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+                        nvidia,hpd-gpio =
+                                <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
+                        pll-supply = <&reg_1v8_avdd_hdmi_pll>;
+                        vdd-supply = <&reg_3v3_avdd_hdmi>;
+                };
+        };
+
+        pinmux@70000868 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&state_default>;
+
+                state_default: pinmux {
+                        /* Analogue Audio (On-module) */
+                        clk1-out-pw4 {
+                                nvidia,pins = "clk1_out_pw4";
+                                nvidia,function = "extperiph1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap3-fs-pp0 {
+                                nvidia,pins = "dap3_fs_pp0",
+                                              "dap3_sclk_pp3",
+                                              "dap3_din_pp1",
+                                              "dap3_dout_pp2";
+                                nvidia,function = "i2s2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis BKL1_ON */
+                        pv2 {
+                                nvidia,pins = "pv2";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis BKL1_PWM */
+                        uart3-rts-n-pc0 {
+                                nvidia,pins = "uart3_rts_n_pc0";
+                                nvidia,function = "pwm0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        /* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */
+                        uart3-cts-n-pa1 {
+                                nvidia,pins = "uart3_cts_n_pa1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis CAN1 on SPI6 */
+                        spi2-cs0-n-px3 {
+                                nvidia,pins = "spi2_cs0_n_px3",
+                                              "spi2_miso_px1",
+                                              "spi2_mosi_px0",
+                                              "spi2_sck_px2";
+                                nvidia,function = "spi6";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        /* CAN_INT1 */
+                        spi2-cs1-n-pw2 {
+                                nvidia,pins = "spi2_cs1_n_pw2";
+                                nvidia,function = "spi3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Apalis CAN2 on SPI4 */
+                        gmi-a16-pj7 {
+                                nvidia,pins = "gmi_a16_pj7",
+                                              "gmi_a17_pb0",
+                                              "gmi_a18_pb1",
+                                              "gmi_a19_pk7";
+                                nvidia,function = "spi4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        /* CAN_INT2 */
+                        spi2-cs2-n-pw3 {
+                                nvidia,pins = "spi2_cs2_n_pw3";
+                                nvidia,function = "spi3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Apalis Digital Audio */
+                        clk1-req-pee2 {
+                                nvidia,pins = "clk1_req_pee2";
+                                nvidia,function = "hda";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        clk2-out-pw5 {
+                                nvidia,pins = "clk2_out_pw5";
+                                nvidia,function = "extperiph2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap1-fs-pn0 {
+                                nvidia,pins = "dap1_fs_pn0",
+                                              "dap1_din_pn1",
+                                              "dap1_dout_pn2",
+                                              "dap1_sclk_pn3";
+                                nvidia,function = "hda";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis GPIO */
+                        kb-col0-pq0 {
+                                nvidia,pins = "kb_col0_pq0",
+                                              "kb_col1_pq1",
+                                              "kb_row10_ps2",
+                                              "kb_row11_ps3",
+                                              "kb_row12_ps4",
+                                              "kb_row13_ps5",
+                                              "kb_row14_ps6",
+                                              "kb_row15_ps7";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        /* Multiplexed and therefore disabled */
+                        owr {
+                                nvidia,pins = "owr";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis HDMI1 */
+                        hdmi-cec-pee3 {
+                                nvidia,pins = "hdmi_cec_pee3";
+                                nvidia,function = "cec";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+                        hdmi-int-pn7 {
+                                nvidia,pins = "hdmi_int_pn7";
+                                nvidia,function = "hdmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Apalis I2C1 */
+                        gen1-i2c-scl-pc4 {
+                                nvidia,pins = "gen1_i2c_scl_pc4",
+                                              "gen1_i2c_sda_pc5";
+                                nvidia,function = "i2c1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Apalis I2C2 (DDC) */
+                        ddc-scl-pv4 {
+                                nvidia,pins = "ddc_scl_pv4",
+                                              "ddc_sda_pv5";
+                                nvidia,function = "i2c4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Apalis I2C3 (CAM) */
+                        cam-i2c-scl-pbb1 {
+                                nvidia,pins = "cam_i2c_scl_pbb1",
+                                              "cam_i2c_sda_pbb2";
+                                nvidia,function = "i2c3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Apalis LCD1 */
+                        lcd-d0-pe0 {
+                                nvidia,pins = "lcd_d0_pe0",
+                                              "lcd_d1_pe1",
+                                              "lcd_d2_pe2",
+                                              "lcd_d3_pe3",
+                                              "lcd_d4_pe4",
+                                              "lcd_d5_pe5",
+                                              "lcd_d6_pe6",
+                                              "lcd_d7_pe7",
+                                              "lcd_d8_pf0",
+                                              "lcd_d9_pf1",
+                                              "lcd_d10_pf2",
+                                              "lcd_d11_pf3",
+                                              "lcd_d12_pf4",
+                                              "lcd_d13_pf5",
+                                              "lcd_d14_pf6",
+                                              "lcd_d15_pf7",
+                                              "lcd_d16_pm0",
+                                              "lcd_d17_pm1",
+                                              "lcd_d18_pm2",
+                                              "lcd_d19_pm3",
+                                              "lcd_d20_pm4",
+                                              "lcd_d21_pm5",
+                                              "lcd_d22_pm6",
+                                              "lcd_d23_pm7",
+                                              "lcd_de_pj1",
+                                              "lcd_hsync_pj3",
+                                              "lcd_pclk_pb3",
+                                              "lcd_vsync_pj4";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Apalis MMC1 */
+                        sdmmc3-clk-pa6 {
+                                nvidia,pins = "sdmmc3_clk_pa6";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc3-dat0-pb7 {
+                                nvidia,pins = "sdmmc3_cmd_pa7",
+                                              "sdmmc3_dat0_pb7",
+                                              "sdmmc3_dat1_pb6",
+                                              "sdmmc3_dat2_pb5",
+                                              "sdmmc3_dat3_pb4",
+                                              "sdmmc3_dat4_pd1",
+                                              "sdmmc3_dat5_pd0",
+                                              "sdmmc3_dat6_pd3",
+                                              "sdmmc3_dat7_pd4";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        /* Apalis MMC1_CD# */
+                        pv3 {
+                                nvidia,pins = "pv3";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Apalis Parallel Camera */
+                        cam-mclk-pcc0 {
+                                nvidia,pins = "cam_mclk_pcc0";
+                                nvidia,function = "vi_alt3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        vi-vsync-pd6 {
+                                nvidia,pins = "vi_d0_pt4",
+                                              "vi_d1_pd5",
+                                              "vi_d2_pl0",
+                                              "vi_d3_pl1",
+                                              "vi_d4_pl2",
+                                              "vi_d5_pl3",
+                                              "vi_d6_pl4",
+                                              "vi_d7_pl5",
+                                              "vi_d8_pl6",
+                                              "vi_d9_pl7",
+                                              "vi_d10_pt2",
+                                              "vi_d11_pt3",
+                                              "vi_hsync_pd7",
+                                              "vi_pclk_pt0",
+                                              "vi_vsync_pd6";
+                                nvidia,function = "vi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        /* Multiplexed and therefore disabled */
+                        kb-col2-pq2 {
+                                nvidia,pins = "kb_col2_pq2",
+                                              "kb_col3_pq3",
+                                              "kb_col4_pq4",
+                                              "kb_row4_pr4";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb-row0-pr0 {
+                                nvidia,pins = "kb_row0_pr0",
+                                              "kb_row1_pr1",
+                                              "kb_row2_pr2",
+                                              "kb_row3_pr3";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb-row5-pr5 {
+                                nvidia,pins = "kb_row5_pr5",
+                                              "kb_row6_pr6",
+                                              "kb_row7_pr7";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        /*
+                         * VI level-shifter direction
+                         * (pull-down => default direction input)
+                         */
+                        vi-mclk-pt1 {
+                                nvidia,pins = "vi_mclk_pt1";
+                                nvidia,function = "vi_alt3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis PWM1 */
+                        pu6 {
+                                nvidia,pins = "pu6";
+                                nvidia,function = "pwm3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis PWM2 */
+                        pu5 {
+                                nvidia,pins = "pu5";
+                                nvidia,function = "pwm2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis PWM3 */
+                        pu4 {
+                                nvidia,pins = "pu4";
+                                nvidia,function = "pwm1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis PWM4 */
+                        pu3 {
+                                nvidia,pins = "pu3";
+                                nvidia,function = "pwm0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis RESET_MOCI# */
+                        gmi-rst-n-pi4 {
+                                nvidia,pins = "gmi_rst_n_pi4";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis SATA1_ACT# */
+                        pex-l0-prsnt-n-pdd0 {
+                                nvidia,pins = "pex_l0_prsnt_n_pdd0";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis SD1 */
+                        sdmmc1-clk-pz0 {
+                                nvidia,pins = "sdmmc1_clk_pz0";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc1-cmd-pz1 {
+                                nvidia,pins = "sdmmc1_cmd_pz1",
+                                              "sdmmc1_dat0_py7",
+                                              "sdmmc1_dat1_py6",
+                                              "sdmmc1_dat2_py5",
+                                              "sdmmc1_dat3_py4";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        /* Apalis SD1_CD# */
+                        clk2-req-pcc5 {
+                                nvidia,pins = "clk2_req_pcc5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Apalis SPDIF1 */
+                        spdif-out-pk5 {
+                                nvidia,pins = "spdif_out_pk5",
+                                              "spdif_in_pk6";
+                                nvidia,function = "spdif";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Apalis SPI1 */
+                        spi1-sck-px5 {
+                                nvidia,pins = "spi1_sck_px5",
+                                              "spi1_mosi_px4",
+                                              "spi1_miso_px7",
+                                              "spi1_cs0_n_px6";
+                                nvidia,function = "spi1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis SPI2 */
+                        lcd-sck-pz4 {
+                                nvidia,pins = "lcd_sck_pz4",
+                                              "lcd_sdout_pn5",
+                                              "lcd_sdin_pz2",
+                                              "lcd_cs0_n_pn4";
+                                nvidia,function = "spi5";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /*
+                         * Apalis TS (Low-speed type specific)
+                         * pins may be used as GPIOs
+                         */
+                        kb-col5-pq5 {
+                                nvidia,pins = "kb_col5_pq5";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb-col6-pq6 {
+                                nvidia,pins = "kb_col6_pq6",
+                                              "kb_col7_pq7",
+                                              "kb_row8_ps0",
+                                              "kb_row9_ps1";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Apalis UART1 */
+                        ulpi-data0 {
+                                nvidia,pins = "ulpi_data0_po1",
+                                              "ulpi_data1_po2",
+                                              "ulpi_data2_po3",
+                                              "ulpi_data3_po4",
+                                              "ulpi_data4_po5",
+                                              "ulpi_data5_po6",
+                                              "ulpi_data6_po7",
+                                              "ulpi_data7_po0";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis UART2 */
+                        ulpi-clk-py0 {
+                                nvidia,pins = "ulpi_clk_py0",
+                                              "ulpi_dir_py1",
+                                              "ulpi_nxt_py2",
+                                              "ulpi_stp_py3";
+                                nvidia,function = "uartd";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis UART3 */
+                        uart2-rxd-pc3 {
+                                nvidia,pins = "uart2_rxd_pc3",
+                                              "uart2_txd_pc2";
+                                nvidia,function = "uartb";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis UART4 */
+                        uart3-rxd-pw7 {
+                                nvidia,pins = "uart3_rxd_pw7",
+                                              "uart3_txd_pw6";
+                                nvidia,function = "uartc";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis USBH_EN */
+                        pex-l0-rst-n-pdd1 {
+                                nvidia,pins = "pex_l0_rst_n_pdd1";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis USBH_OC# */
+                        pex-l0-clkreq-n-pdd2 {
+                                nvidia,pins = "pex_l0_clkreq_n_pdd2";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Apalis USBO1_EN */
+                        gen2-i2c-scl-pt5 {
+                                nvidia,pins = "gen2_i2c_scl_pt5";
+                                nvidia,function = "rsvd4";
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis USBO1_OC# */
+                        gen2-i2c-sda-pt6 {
+                                nvidia,pins = "gen2_i2c_sda_pt6";
+                                nvidia,function = "rsvd4";
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Apalis VGA1 not supported and therefore disabled */
+                        crt-hsync-pv6 {
+                                nvidia,pins = "crt_hsync_pv6",
+                                              "crt_vsync_pv7";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis WAKE1_MICO */
+                        pv1 {
+                                nvidia,pins = "pv1";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* eMMC (On-module) */
+                        sdmmc4-clk-pcc4 {
+                                nvidia,pins = "sdmmc4_clk_pcc4",
+                                              "sdmmc4_cmd_pt7",
+                                              "sdmmc4_rst_n_pcc3";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4-dat0-paa0 {
+                                nvidia,pins = "sdmmc4_dat0_paa0",
+                                              "sdmmc4_dat1_paa1",
+                                              "sdmmc4_dat2_paa2",
+                                              "sdmmc4_dat3_paa3",
+                                              "sdmmc4_dat4_paa4",
+                                              "sdmmc4_dat5_paa5",
+                                              "sdmmc4_dat6_paa6",
+                                              "sdmmc4_dat7_paa7";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* EN_+3.3_SDMMC3 */
+                        uart2-cts-n-pj5 {
+                                nvidia,pins = "uart2_cts_n_pj5";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* LAN i210/i211 DEV_OFF_N, PE_RST_N (On-module) */
+                        pex-l2-prsnt-n-pdd7 {
+                                nvidia,pins = "pex_l2_prsnt_n_pdd7",
+                                              "pex_l2_rst_n_pcc6";
+                                nvidia,function = "pcie";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        /* LAN i210/i211 PE_WAKE_N, SDP3 (On-module) */
+                        pex-wake-n-pdd3 {
+                                nvidia,pins = "pex_wake_n_pdd3",
+                                              "pex_l2_clkreq_n_pcc7";
+                                nvidia,function = "pcie";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        /* LAN i210/i211 SMB_ALERT_N (On-module) */
+                        sys-clk-req-pz5 {
+                                nvidia,pins = "sys_clk_req_pz5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* LVDS Transceiver Configuration */
+                        pbb0 {
+                                nvidia,pins = "pbb0",
+                                              "pbb7",
+                                              "pcc1",
+                                              "pcc2";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pbb3 {
+                                nvidia,pins = "pbb3",
+                                              "pbb4",
+                                              "pbb5",
+                                              "pbb6";
+                                nvidia,function = "displayb";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Not connected and therefore disabled */
+                        clk-32k-out-pa0 {
+                                nvidia,pins = "clk3_out_pee0",
+                                              "clk3_req_pee1",
+                                              "clk_32k_out_pa0",
+                                              "dap4_din_pp5",
+                                              "dap4_dout_pp6",
+                                              "dap4_fs_pp4",
+                                              "dap4_sclk_pp7";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap2-fs-pa2 {
+                                nvidia,pins = "dap2_fs_pa2",
+                                              "dap2_sclk_pa3",
+                                              "dap2_din_pa4",
+                                              "dap2_dout_pa5",
+                                              "lcd_dc0_pn6",
+                                              "lcd_m1_pw1",
+                                              "lcd_pwr1_pc1",
+                                              "pex_l1_clkreq_n_pdd6",
+                                              "pex_l1_prsnt_n_pdd4",
+                                              "pex_l1_rst_n_pdd5";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi-ad0-pg0 {
+                                nvidia,pins = "gmi_ad0_pg0",
+                                              "gmi_ad2_pg2",
+                                              "gmi_ad3_pg3",
+                                              "gmi_ad4_pg4",
+                                              "gmi_ad5_pg5",
+                                              "gmi_ad6_pg6",
+                                              "gmi_ad7_pg7",
+                                              "gmi_ad8_ph0",
+                                              "gmi_ad9_ph1",
+                                              "gmi_ad10_ph2",
+                                              "gmi_ad11_ph3",
+                                              "gmi_ad12_ph4",
+                                              "gmi_ad13_ph5",
+                                              "gmi_ad14_ph6",
+                                              "gmi_ad15_ph7",
+                                              "gmi_adv_n_pk0",
+                                              "gmi_clk_pk1",
+                                              "gmi_cs4_n_pk2",
+                                              "gmi_cs2_n_pk3",
+                                              "gmi_dqs_pi2",
+                                              "gmi_iordy_pi5",
+                                              "gmi_oe_n_pi1",
+                                              "gmi_wait_pi7",
+                                              "gmi_wr_n_pi0",
+                                              "lcd_cs1_n_pw0",
+                                              "pu0",
+                                              "pu1",
+                                              "pu2";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi-cs0-n-pj0 {
+                                nvidia,pins = "gmi_cs0_n_pj0",
+                                              "gmi_cs1_n_pj2",
+                                              "gmi_cs3_n_pk4";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi-cs6-n-pi3 {
+                                nvidia,pins = "gmi_cs6_n_pi3";
+                                nvidia,function = "sata";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi-cs7-n-pi6 {
+                                nvidia,pins = "gmi_cs7_n_pi6";
+                                nvidia,function = "gmi_alt";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        lcd-pwr0-pb2 {
+                                nvidia,pins = "lcd_pwr0_pb2",
+                                              "lcd_pwr2_pc6",
+                                              "lcd_wr_n_pz3";
+                                nvidia,function = "hdcp";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart2-rts-n-pj6 {
+                                nvidia,pins = "uart2_rts_n_pj6";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Power I2C (On-module) */
+                        pwr-i2c-scl-pz6 {
+                                nvidia,pins = "pwr_i2c_scl_pz6",
+                                              "pwr_i2c_sda_pz7";
+                                nvidia,function = "i2cpwr";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /*
+                         * THERMD_ALERT#, unlatched I2C address pin of LM95245
+                         * temperature sensor therefore requires disabling for
+                         * now
+                         */
+                        lcd-dc1-pd2 {
+                                nvidia,pins = "lcd_dc1_pd2";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* TOUCH_PEN_INT# (On-module) */
+                        pv0 {
+                                nvidia,pins = "pv0";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                };
+        };
+
+        serial@70006040 {
+                compatible = "nvidia,tegra30-hsuart";
+        };
+
+        serial@70006200 {
+                compatible = "nvidia,tegra30-hsuart";
+        };
+
+        serial@70006300 {
+                compatible = "nvidia,tegra30-hsuart";
+        };
+
+        hdmi_ddc: i2c@7000c700 {
+                clock-frequency = <10000>;
+        };
+
+        /*
+         * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
+         * touch screen controller
+         */
+        i2c@7000d000 {
+                status = "okay";
+                clock-frequency = <100000>;
+
+                /* SGTL5000 audio codec */
+                sgtl5000: codec@a {
+                        compatible = "fsl,sgtl5000";
+                        reg = <0x0a>;
+                        VDDA-supply = <&reg_module_3v3_audio>;
+                        VDDD-supply = <&reg_1v8_vio>;
+                        VDDIO-supply = <&reg_module_3v3>;
+                        clocks = <&tegra_car TEGRA30_CLK_EXTERN1>;
+                };
+
+                pmic: pmic@2d {
+                        compatible = "ti,tps65911";
+                        reg = <0x2d>;
+
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+
+                        ti,system-power-controller;
+
+                        #gpio-cells = <2>;
+                        gpio-controller;
+
+                        vcc1-supply = <&reg_module_3v3>;
+                        vcc2-supply = <&reg_module_3v3>;
+                        vcc3-supply = <&reg_1v8_vio>;
+                        vcc4-supply = <&reg_module_3v3>;
+                        vcc5-supply = <&reg_module_3v3>;
+                        vcc6-supply = <&reg_1v8_vio>;
+                        vcc7-supply = <&reg_5v0_charge_pump>;
+                        vccio-supply = <&reg_module_3v3>;
+
+                        regulators {
+                                vdd1_reg: vdd1 {
+                                        regulator-name = "+V1.35_VDDIO_DDR";
+                                        regulator-min-microvolt = <1350000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-always-on;
+                                };
+
+                                vdd2_reg: vdd2 {
+                                        regulator-name = "+V1.05";
+                                        regulator-min-microvolt = <1050000>;
+                                        regulator-max-microvolt = <1050000>;
+                                };
+
+                                vddctrl_reg: vddctrl {
+                                        regulator-name = "+V1.0_VDD_CPU";
+                                        regulator-min-microvolt = <1150000>;
+                                        regulator-max-microvolt = <1150000>;
+                                        regulator-always-on;
+                                };
+
+                                reg_1v8_vio: vio {
+                                        regulator-name = "+V1.8";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                /*
+                                 * 1.8 volt +VDDIO_SDMMC3 in case EN_+3.3_SDMMC3
+                                 * is off
+                                 */
+                                vddio_sdmmc_1v8_reg: ldo1 {
+                                        regulator-name = "+VDDIO_SDMMC3_1V8";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                /*
+                                 * EN_+V3.3 switching via FET:
+                                 * +V3.3_AUDIO_AVDD_S, +V3.3
+                                 * see also +V3.3 fixed supply
+                                 */
+                                ldo2_reg: ldo2 {
+                                        regulator-name = "EN_+V3.3";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo3_reg: ldo3 {
+                                        regulator-name = "+V1.2_CSI";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                };
+
+                                ldo4_reg: ldo4 {
+                                        regulator-name = "+V1.2_VDD_RTC";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+
+                                /*
+                                 * +V2.8_AVDD_VDAC:
+                                 * only required for (unsupported) analog RGB
+                                 */
+                                ldo5_reg: ldo5 {
+                                        regulator-name = "+V2.8_AVDD_VDAC";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                };
+
+                                /*
+                                 * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V
+                                 * but LDO6 can't set voltage in 50mV
+                                 * granularity
+                                 */
+                                ldo6_reg: ldo6 {
+                                        regulator-name = "+V1.05_AVDD_PLLE";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                };
+
+                                ldo7_reg: ldo7 {
+                                        regulator-name = "+V1.2_AVDD_PLL";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo8_reg: ldo8 {
+                                        regulator-name = "+V1.0_VDD_DDR_HS";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+                        };
+                };
+
+                /* STMPE811 touch screen controller */
+                touchscreen@41 {
+                        compatible = "st,stmpe811";
+                        reg = <0x41>;
+                        irq-gpio = <&gpio TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
+                        interrupt-controller;
+                        id = <0>;
+                        blocks = <0x5>;
+                        irq-trigger = <0x1>;
+
+                        stmpe_touchscreen {
+                                compatible = "st,stmpe-ts";
+                                /* 3.25 MHz ADC clock speed */
+                                st,adc-freq = <1>;
+                                /* 8 sample average control */
+                                st,ave-ctrl = <3>;
+                                /* 7 length fractional part in z */
+                                st,fraction-z = <7>;
+                                /*
+                                 * 50 mA typical 80 mA max touchscreen drivers
+                                 * current limit value
+                                 */
+                                st,i-drive = <1>;
+                                /* 12-bit ADC */
+                                st,mod-12b = <1>;
+                                /* internal ADC reference */
+                                st,ref-sel = <0>;
+                                /* ADC converstion time: 80 clocks */
+                                st,sample-time = <4>;
+                                /* 1 ms panel driver settling time */
+                                st,settling = <3>;
+                                /* 5 ms touch detect interrupt delay */
+                                st,touch-det-delay = <5>;
+                        };
+                };
+
+                /*
+                 * LM95245 temperature sensor
+                 * Note: OVERT1# directly connected to TPS65911 PMIC PWRDN
+                 */
+                temp-sensor@4c {
+                        compatible = "national,lm95245";
+                        reg = <0x4c>;
+                };
+
+                /* SW: +V1.2_VDD_CORE */
+                regulator@60 {
+                        compatible = "ti,tps62362";
+                        reg = <0x60>;
+
+                        regulator-name = "tps62362-vout";
+                        regulator-min-microvolt = <900000>;
+                        regulator-max-microvolt = <1400000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                        ti,vsel0-state-low;
+                        /* VSEL1: EN_CORE_DVFS_N low for DVFS */
+                        ti,vsel1-state-low;
+                };
+        };
+
+        /* SPI4: CAN2 */
+        spi@7000da00 {
+                status = "okay";
+                spi-max-frequency = <10000000>;
+
+                can@1 {
+                        compatible = "microchip,mcp2515";
+                        reg = <1>;
+                        clocks = <&clk16m>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_FALLING>;
+                        spi-max-frequency = <10000000>;
+                };
+        };
+
+        /* SPI6: CAN1 */
+        spi@7000de00 {
+                status = "okay";
+                spi-max-frequency = <10000000>;
+
+                can@0 {
+                        compatible = "microchip,mcp2515";
+                        reg = <0>;
+                        clocks = <&clk16m>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <TEGRA_GPIO(W, 2) IRQ_TYPE_EDGE_FALLING>;
+                        spi-max-frequency = <10000000>;
+                };
+        };
+
+        pmc@7000e400 {
+                nvidia,invert-interrupt;
+                nvidia,suspend-mode = <1>;
+                nvidia,cpu-pwr-good-time = <5000>;
+                nvidia,cpu-pwr-off-time = <5000>;
+                nvidia,core-pwr-good-time = <3845 3845>;
+                nvidia,core-pwr-off-time = <0>;
+                nvidia,core-power-req-active-high;
+                nvidia,sys-clock-req-active-high;
+
+                /* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */
+                i2c-thermtrip {
+                        nvidia,i2c-controller-id = <4>;
+                        nvidia,bus-addr = <0x2d>;
+                        nvidia,reg-addr = <0x3f>;
+                        nvidia,reg-data = <0x1>;
+                };
+        };
+
+        hda@70030000 {
+                status = "okay";
+        };
+
+        ahub@70080000 {
+                i2s@70080500 {
+                        status = "okay";
+                };
+        };
+
+        /* eMMC */
+        sdhci@78000600 {
+                status = "okay";
+                bus-width = <8>;
+                non-removable;
+                vmmc-supply = <&reg_module_3v3>; /* VCC */
+                vqmmc-supply = <&reg_1v8_vio>; /* VCCQ */
+                mmc-ddr-1_8v;
+        };
+
+        clk32k_in: xtal1 {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <32768>;
+        };
+
+        clk16m: osc4 {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <16000000>;
+        };
+
+        reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll {
+                compatible = "regulator-fixed";
+                regulator-name = "+V1.8_AVDD_HDMI_PLL";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                enable-active-high;
+                gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
+                vin-supply = <&reg_1v8_vio>;
+        };
+
+        reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
+                compatible = "regulator-fixed";
+                regulator-name = "+V3.3_AVDD_HDMI";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                enable-active-high;
+                gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
+                vin-supply = <&reg_module_3v3>;
+        };
+
+        reg_5v0_charge_pump: regulator-5v0-charge-pump {
+                compatible = "regulator-fixed";
+                regulator-name = "+V5.0";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-always-on;
+        };
+
+        reg_module_3v3: regulator-module-3v3 {
+                compatible = "regulator-fixed";
+                regulator-name = "+V3.3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+        };
+
+        reg_module_3v3_audio: regulator-module-3v3-audio {
+                compatible = "regulator-fixed";
+                regulator-name = "+V3.3_AUDIO_AVDD_S";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+        };
+
+        sound {
+                compatible = "toradex,tegra-audio-sgtl5000-apalis_t30",
+                             "nvidia,tegra-audio-sgtl5000";
+                nvidia,model = "Toradex Apalis T30";
+                nvidia,audio-routing =
+                        "Headphone Jack", "HP_OUT",
+                        "LINE_IN", "Line In Jack",
+                        "MIC_IN", "Mic Jack";
+                nvidia,i2s-controller = <&tegra_i2s2>;
+                nvidia,audio-codec = <&sgtl5000>;
+                clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
+                         <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA30_CLK_EXTERN1>;
+                clock-names = "pll_a", "pll_a_out0", "mclk";
+        };
+};
diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi
index 2f807d40c1b7..7f112f192fe9 100644
--- a/arch/arm/boot/dts/tegra30-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra30-apalis.dtsi
@@ -3,48 +3,53 @@
 
 /*
  * Toradex Apalis T30 Module Device Tree
- * Compatible for Revisions 1GB: V1.0A, V1.1A; 1GB IT: V1.1A;
- * 2GB: V1.0B, V1.0C, V1.0E, V1.1A
+ * Compatible for Revisions 1GB: V1.0A; 2GB: V1.0B, V1.0C, V1.0E
  */
 / {
-        model = "Toradex Apalis T30";
-        compatible = "toradex,apalis_t30", "nvidia,tegra30";
-
         memory@80000000 {
                 reg = <0x80000000 0x40000000>;
         };
 
         pcie@3000 {
+                status = "okay";
                 avdd-pexa-supply = <&vdd2_reg>;
-                vdd-pexa-supply = <&vdd2_reg>;
                 avdd-pexb-supply = <&vdd2_reg>;
-                vdd-pexb-supply = <&vdd2_reg>;
                 avdd-pex-pll-supply = <&vdd2_reg>;
                 avdd-plle-supply = <&ldo6_reg>;
-                vddio-pex-ctl-supply = <&sys_3v3_reg>;
-                hvdd-pex-supply = <&sys_3v3_reg>;
+                hvdd-pex-supply = <&reg_module_3v3>;
+                vddio-pex-ctl-supply = <&reg_module_3v3>;
+                vdd-pexa-supply = <&vdd2_reg>;
+                vdd-pexb-supply = <&vdd2_reg>;
 
+                /* Apalis type specific */
                 pci@1,0 {
                         nvidia,num-lanes = <4>;
                 };
 
+                /* Apalis PCIe */
                 pci@2,0 {
                         nvidia,num-lanes = <1>;
                 };
 
+                /* I210/I211 Gigabit Ethernet Controller (on-module) */
                 pci@3,0 {
+                        status = "okay";
                         nvidia,num-lanes = <1>;
+
+                        pcie@0 {
+                                reg = <0 0 0 0 0>;
+                                local-mac-address = [00 00 00 00 00 00];
+                        };
                 };
         };
 
         host1x@50000000 {
                 hdmi@54280000 {
-                        vdd-supply = <&avdd_hdmi_3v3_reg>;
-                        pll-supply = <&avdd_hdmi_pll_1v8_reg>;
-
+                        nvidia,ddc-i2c-bus = <&hdmi_ddc>;
                         nvidia,hpd-gpio =
                                 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
-                        nvidia,ddc-i2c-bus = <&hdmiddc>;
+                        pll-supply = <&reg_1v8_avdd_hdmi_pll>;
+                        vdd-supply = <&reg_3v3_avdd_hdmi>;
                 };
         };
 
@@ -54,18 +59,18 @@
 
                 state_default: pinmux {
                         /* Analogue Audio (On-module) */
-                        clk1_out_pw4 {
+                        clk1-out-pw4 {
                                 nvidia,pins = "clk1_out_pw4";
                                 nvidia,function = "extperiph1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        dap3_fs_pp0 {
-                                nvidia,pins =   "dap3_fs_pp0",
-                                                "dap3_sclk_pp3",
-                                                "dap3_din_pp1",
-                                                "dap3_dout_pp2";
+                        dap3-fs-pp0 {
+                                nvidia,pins = "dap3_fs_pp0",
+                                              "dap3_sclk_pp3",
+                                              "dap3_din_pp1",
+                                              "dap3_dout_pp2";
                                 nvidia,function = "i2s2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
@@ -77,25 +82,28 @@
                                 nvidia,function = "rsvd4";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
 
                         /* Apalis BKL1_PWM */
-                        uart3_rts_n_pc0 {
+                        uart3-rts-n-pc0 {
                                 nvidia,pins = "uart3_rts_n_pc0";
                                 nvidia,function = "pwm0";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
                         /* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */
-                        uart3_cts_n_pa1 {
+                        uart3-cts-n-pa1 {
                                 nvidia,pins = "uart3_cts_n_pa1";
                                 nvidia,function = "rsvd2";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
 
                         /* Apalis CAN1 on SPI6 */
-                        spi2_cs0_n_px3 {
+                        spi2-cs0-n-px3 {
                                 nvidia,pins = "spi2_cs0_n_px3",
                                               "spi2_miso_px1",
                                               "spi2_mosi_px0",
@@ -105,7 +113,7 @@
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         /* CAN_INT1 */
-                        spi2_cs1_n_pw2 {
+                        spi2-cs1-n-pw2 {
                                 nvidia,pins = "spi2_cs1_n_pw2";
                                 nvidia,function = "spi3";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -114,7 +122,7 @@
                         };
 
                         /* Apalis CAN2 on SPI4 */
-                        gmi_a16_pj7 {
+                        gmi-a16-pj7 {
                                 nvidia,pins = "gmi_a16_pj7",
                                               "gmi_a17_pb0",
                                               "gmi_a18_pb1",
@@ -125,7 +133,7 @@
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         /* CAN_INT2 */
-                        spi2_cs2_n_pw3 {
+                        spi2-cs2-n-pw3 {
                                 nvidia,pins = "spi2_cs2_n_pw3";
                                 nvidia,function = "spi3";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -134,20 +142,20 @@
                         };
 
                         /* Apalis Digital Audio */
-                        clk1_req_pee2 {
+                        clk1-req-pee2 {
                                 nvidia,pins = "clk1_req_pee2";
                                 nvidia,function = "hda";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
-                        clk2_out_pw5 {
+                        clk2-out-pw5 {
                                 nvidia,pins = "clk2_out_pw5";
                                 nvidia,function = "extperiph2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        dap1_fs_pn0 {
+                        dap1-fs-pn0 {
                                 nvidia,pins = "dap1_fs_pn0",
                                               "dap1_din_pn1",
                                               "dap1_dout_pn2",
@@ -157,28 +165,125 @@
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
 
-                        /* Apalis I2C3 */
-                        cam_i2c_scl_pbb1 {
+                        /* Apalis GPIO */
+                        kb-col0-pq0 {
+                                nvidia,pins = "kb_col0_pq0",
+                                              "kb_col1_pq1",
+                                              "kb_row10_ps2",
+                                              "kb_row11_ps3",
+                                              "kb_row12_ps4",
+                                              "kb_row13_ps5",
+                                              "kb_row14_ps6",
+                                              "kb_row15_ps7";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        /* Multiplexed and therefore disabled */
+                        owr {
+                                nvidia,pins = "owr";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis HDMI1 */
+                        hdmi-cec-pee3 {
+                                nvidia,pins = "hdmi_cec_pee3";
+                                nvidia,function = "cec";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+                        hdmi-int-pn7 {
+                                nvidia,pins = "hdmi_int_pn7";
+                                nvidia,function = "hdmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Apalis I2C1 */
+                        gen1-i2c-scl-pc4 {
+                                nvidia,pins = "gen1_i2c_scl_pc4",
+                                              "gen1_i2c_sda_pc5";
+                                nvidia,function = "i2c1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Apalis I2C2 (DDC) */
+                        ddc-scl-pv4 {
+                                nvidia,pins = "ddc_scl_pv4",
+                                              "ddc_sda_pv5";
+                                nvidia,function = "i2c4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Apalis I2C3 (CAM) */
+                        cam-i2c-scl-pbb1 {
                                 nvidia,pins = "cam_i2c_scl_pbb1",
                                               "cam_i2c_sda_pbb2";
                                 nvidia,function = "i2c3";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-                                nvidia,lock = <TEGRA_PIN_DISABLE>;
                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
                         };
 
+                        /* Apalis LCD1 */
+                        lcd-d0-pe0 {
+                                nvidia,pins = "lcd_d0_pe0",
+                                              "lcd_d1_pe1",
+                                              "lcd_d2_pe2",
+                                              "lcd_d3_pe3",
+                                              "lcd_d4_pe4",
+                                              "lcd_d5_pe5",
+                                              "lcd_d6_pe6",
+                                              "lcd_d7_pe7",
+                                              "lcd_d8_pf0",
+                                              "lcd_d9_pf1",
+                                              "lcd_d10_pf2",
+                                              "lcd_d11_pf3",
+                                              "lcd_d12_pf4",
+                                              "lcd_d13_pf5",
+                                              "lcd_d14_pf6",
+                                              "lcd_d15_pf7",
+                                              "lcd_d16_pm0",
+                                              "lcd_d17_pm1",
+                                              "lcd_d18_pm2",
+                                              "lcd_d19_pm3",
+                                              "lcd_d20_pm4",
+                                              "lcd_d21_pm5",
+                                              "lcd_d22_pm6",
+                                              "lcd_d23_pm7",
+                                              "lcd_de_pj1",
+                                              "lcd_hsync_pj3",
+                                              "lcd_pclk_pb3",
+                                              "lcd_vsync_pj4";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
                         /* Apalis MMC1 */
-                        sdmmc3_clk_pa6 {
-                                nvidia,pins = "sdmmc3_clk_pa6",
-                                              "sdmmc3_cmd_pa7";
+                        sdmmc3-clk-pa6 {
+                                nvidia,pins = "sdmmc3_clk_pa6";
                                 nvidia,function = "sdmmc3";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
-                        sdmmc3_dat0_pb7 {
-                                nvidia,pins = "sdmmc3_dat0_pb7",
+                        sdmmc3-dat0-pb7 {
+                                nvidia,pins = "sdmmc3_cmd_pa7",
+                                              "sdmmc3_dat0_pb7",
                                               "sdmmc3_dat1_pb6",
                                               "sdmmc3_dat2_pb5",
                                               "sdmmc3_dat3_pb4",
@@ -194,10 +299,81 @@
                         pv3 {
                                 nvidia,pins = "pv3";
                                 nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Apalis Parallel Camera */
+                        cam-mclk-pcc0 {
+                                nvidia,pins = "cam_mclk_pcc0";
+                                nvidia,function = "vi_alt3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        vi-vsync-pd6 {
+                                nvidia,pins = "vi_d0_pt4",
+                                              "vi_d1_pd5",
+                                              "vi_d2_pl0",
+                                              "vi_d3_pl1",
+                                              "vi_d4_pl2",
+                                              "vi_d5_pl3",
+                                              "vi_d6_pl4",
+                                              "vi_d7_pl5",
+                                              "vi_d8_pl6",
+                                              "vi_d9_pl7",
+                                              "vi_d10_pt2",
+                                              "vi_d11_pt3",
+                                              "vi_hsync_pd7",
+                                              "vi_pclk_pt0",
+                                              "vi_vsync_pd6";
+                                nvidia,function = "vi";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
+                        /* Multiplexed and therefore disabled */
+                        kb-col2-pq2 {
+                                nvidia,pins = "kb_col2_pq2",
+                                              "kb_col3_pq3",
+                                              "kb_col4_pq4",
+                                              "kb_row4_pr4";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb-row0-pr0 {
+                                nvidia,pins = "kb_row0_pr0",
+                                              "kb_row1_pr1",
+                                              "kb_row2_pr2",
+                                              "kb_row3_pr3";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb-row5-pr5 {
+                                nvidia,pins = "kb_row5_pr5",
+                                              "kb_row6_pr6",
+                                              "kb_row7_pr7";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        /*
+                         * VI level-shifter direction
+                         * (pull-down => default direction input)
+                         */
+                        vi-mclk-pt1 {
+                                nvidia,pins = "vi_mclk_pt1";
+                                nvidia,function = "vi_alt3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
 
                         /* Apalis PWM1 */
                         pu6 {
@@ -232,21 +408,30 @@
                         };
 
                         /* Apalis RESET_MOCI# */
-                        gmi_rst_n_pi4 {
+                        gmi-rst-n-pi4 {
                                 nvidia,pins = "gmi_rst_n_pi4";
                                 nvidia,function = "gmi";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
 
+                        /* Apalis SATA1_ACT# */
+                        pex-l0-prsnt-n-pdd0 {
+                                nvidia,pins = "pex_l0_prsnt_n_pdd0";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
                         /* Apalis SD1 */
-                        sdmmc1_clk_pz0 {
+                        sdmmc1-clk-pz0 {
                                 nvidia,pins = "sdmmc1_clk_pz0";
                                 nvidia,function = "sdmmc1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
-                        sdmmc1_cmd_pz1 {
+                        sdmmc1-cmd-pz1 {
                                 nvidia,pins = "sdmmc1_cmd_pz1",
                                               "sdmmc1_dat0_py7",
                                               "sdmmc1_dat1_py6",
@@ -257,16 +442,26 @@
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
                         /* Apalis SD1_CD# */
-                        clk2_req_pcc5 {
+                        clk2-req-pcc5 {
                                 nvidia,pins = "clk2_req_pcc5";
                                 nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Apalis SPDIF1 */
+                        spdif-out-pk5 {
+                                nvidia,pins = "spdif_out_pk5",
+                                              "spdif_in_pk6";
+                                nvidia,function = "spdif";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
 
                         /* Apalis SPI1 */
-                        spi1_sck_px5 {
+                        spi1-sck-px5 {
                                 nvidia,pins = "spi1_sck_px5",
                                               "spi1_mosi_px4",
                                               "spi1_miso_px7",
@@ -277,7 +472,7 @@
                         };
 
                         /* Apalis SPI2 */
-                        lcd_sck_pz4 {
+                        lcd-sck-pz4 {
                                 nvidia,pins = "lcd_sck_pz4",
                                               "lcd_sdout_pn5",
                                               "lcd_sdin_pz2",
@@ -287,8 +482,30 @@
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
 
+                        /*
+                         * Apalis TS (Low-speed type specific)
+                         * pins may be used as GPIOs
+                         */
+                        kb-col5-pq5 {
+                                nvidia,pins = "kb_col5_pq5";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb-col6-pq6 {
+                                nvidia,pins = "kb_col6_pq6",
+                                              "kb_col7_pq7",
+                                              "kb_row8_ps0",
+                                              "kb_row9_ps1";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
                         /* Apalis UART1 */
-                        ulpi_data0 {
+                        ulpi-data0 {
                                 nvidia,pins = "ulpi_data0_po1",
                                               "ulpi_data1_po2",
                                               "ulpi_data2_po3",
@@ -303,7 +520,7 @@
                         };
 
                         /* Apalis UART2 */
-                        ulpi_clk_py0 {
+                        ulpi-clk-py0 {
                                 nvidia,pins = "ulpi_clk_py0",
                                               "ulpi_dir_py1",
                                               "ulpi_nxt_py2",
@@ -314,7 +531,7 @@
                         };
 
                         /* Apalis UART3 */
-                        uart2_rxd_pc3 {
+                        uart2-rxd-pc3 {
                                 nvidia,pins = "uart2_rxd_pc3",
                                               "uart2_txd_pc2";
                                 nvidia,function = "uartb";
@@ -323,7 +540,7 @@
                         };
 
                         /* Apalis UART4 */
-                        uart3_rxd_pw7 {
+                        uart3-rxd-pw7 {
                                 nvidia,pins = "uart3_rxd_pw7",
                                               "uart3_txd_pw6";
                                 nvidia,function = "uartc";
@@ -331,8 +548,26 @@
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
 
+                        /* Apalis USBH_EN */
+                        pex-l0-rst-n-pdd1 {
+                                nvidia,pins = "pex_l0_rst_n_pdd1";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis USBH_OC# */
+                        pex-l0-clkreq-n-pdd2 {
+                                nvidia,pins = "pex_l0_clkreq_n_pdd2";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
                         /* Apalis USBO1_EN */
-                        gen2_i2c_scl_pt5 {
+                        gen2-i2c-scl-pt5 {
                                 nvidia,pins = "gen2_i2c_scl_pt5";
                                 nvidia,function = "rsvd4";
                                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
@@ -341,7 +576,7 @@
                         };
 
                         /* Apalis USBO1_OC# */
-                        gen2_i2c_sda_pt6 {
+                        gen2-i2c-sda-pt6 {
                                 nvidia,pins = "gen2_i2c_sda_pt6";
                                 nvidia,function = "rsvd4";
                                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
@@ -350,6 +585,16 @@
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
 
+                        /* Apalis VGA1 not supported and therefore disabled */
+                        crt-hsync-pv6 {
+                                nvidia,pins = "crt_hsync_pv6",
+                                              "crt_vsync_pv7";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
                         /* Apalis WAKE1_MICO */
                         pv1 {
                                 nvidia,pins = "pv1";
@@ -360,14 +605,16 @@
                         };
 
                         /* eMMC (On-module) */
-                        sdmmc4_clk_pcc4 {
+                        sdmmc4-clk-pcc4 {
                                 nvidia,pins = "sdmmc4_clk_pcc4",
+                                              "sdmmc4_cmd_pt7",
                                               "sdmmc4_rst_n_pcc3";
                                 nvidia,function = "sdmmc4";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc4_dat0_paa0 {
+                        sdmmc4-dat0-paa0 {
                                 nvidia,pins = "sdmmc4_dat0_paa0",
                                               "sdmmc4_dat1_paa1",
                                               "sdmmc4_dat2_paa2",
@@ -379,6 +626,34 @@
                                 nvidia,function = "sdmmc4";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* LAN i210/i211 DEV_OFF_N, PE_RST_N (On-module) */
+                        pex-l2-prsnt-n-pdd7 {
+                                nvidia,pins = "pex_l2_prsnt_n_pdd7",
+                                              "pex_l2_rst_n_pcc6";
+                                nvidia,function = "pcie";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        /* LAN i210/i211 PE_WAKE_N, SDP3 (On-module) */
+                        pex-wake-n-pdd3 {
+                                nvidia,pins = "pex_wake_n_pdd3",
+                                              "pex_l2_clkreq_n_pcc7";
+                                nvidia,function = "pcie";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        /* LAN i210/i211 SMB_ALERT_N (On-module) */
+                        sys-clk-req-pz5 {
+                                nvidia,pins = "sys_clk_req_pz5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
 
                         /* LVDS Transceiver Configuration */
@@ -391,7 +666,6 @@
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
-                                nvidia,lock = <TEGRA_PIN_DISABLE>;
                         };
                         pbb3 {
                                 nvidia,pins = "pbb3",
@@ -402,18 +676,121 @@
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
-                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Not connected and therefore disabled */
+                        clk-32k-out-pa0 {
+                                nvidia,pins = "clk3_out_pee0",
+                                              "clk3_req_pee1",
+                                              "clk_32k_out_pa0",
+                                              "dap4_din_pp5",
+                                              "dap4_dout_pp6",
+                                              "dap4_fs_pp4",
+                                              "dap4_sclk_pp7";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap2-fs-pa2 {
+                                nvidia,pins = "dap2_fs_pa2",
+                                              "dap2_sclk_pa3",
+                                              "dap2_din_pa4",
+                                              "dap2_dout_pa5",
+                                              "lcd_dc0_pn6",
+                                              "lcd_m1_pw1",
+                                              "lcd_pwr1_pc1",
+                                              "pex_l1_clkreq_n_pdd6",
+                                              "pex_l1_prsnt_n_pdd4",
+                                              "pex_l1_rst_n_pdd5";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi-ad0-pg0 {
+                                nvidia,pins = "gmi_ad0_pg0",
+                                              "gmi_ad2_pg2",
+                                              "gmi_ad3_pg3",
+                                              "gmi_ad4_pg4",
+                                              "gmi_ad5_pg5",
+                                              "gmi_ad6_pg6",
+                                              "gmi_ad7_pg7",
+                                              "gmi_ad8_ph0",
+                                              "gmi_ad9_ph1",
+                                              "gmi_ad10_ph2",
+                                              "gmi_ad11_ph3",
+                                              "gmi_ad12_ph4",
+                                              "gmi_ad13_ph5",
+                                              "gmi_ad14_ph6",
+                                              "gmi_ad15_ph7",
+                                              "gmi_adv_n_pk0",
+                                              "gmi_clk_pk1",
+                                              "gmi_cs4_n_pk2",
+                                              "gmi_cs2_n_pk3",
+                                              "gmi_dqs_pi2",
+                                              "gmi_iordy_pi5",
+                                              "gmi_oe_n_pi1",
+                                              "gmi_wait_pi7",
+                                              "gmi_wr_n_pi0",
+                                              "lcd_cs1_n_pw0",
+                                              "pu0",
+                                              "pu1",
+                                              "pu2";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi-cs0-n-pj0 {
+                                nvidia,pins = "gmi_cs0_n_pj0",
+                                              "gmi_cs1_n_pj2",
+                                              "gmi_cs3_n_pk4";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi-cs6-n-pi3 {
+                                nvidia,pins = "gmi_cs6_n_pi3";
+                                nvidia,function = "sata";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi-cs7-n-pi6 {
+                                nvidia,pins = "gmi_cs7_n_pi6";
+                                nvidia,function = "gmi_alt";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        lcd-pwr0-pb2 {
+                                nvidia,pins = "lcd_pwr0_pb2",
+                                              "lcd_pwr2_pc6",
+                                              "lcd_wr_n_pz3";
+                                nvidia,function = "hdcp";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart2-cts-n-pj5 {
+                                nvidia,pins = "uart2_cts_n_pj5",
+                                              "uart2_rts_n_pj6";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
 
                         /* Power I2C (On-module) */
-                        pwr_i2c_scl_pz6 {
+                        pwr-i2c-scl-pz6 {
                                 nvidia,pins = "pwr_i2c_scl_pz6",
                                               "pwr_i2c_sda_pz7";
                                 nvidia,function = "i2cpwr";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-                                nvidia,lock = <TEGRA_PIN_DISABLE>;
                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
                         };
 
@@ -422,15 +799,15 @@
                          * temperature sensor therefore requires disabling for
                          * now
                          */
-                        lcd_dc1_pd2 {
+                        lcd-dc1-pd2 {
                                 nvidia,pins = "lcd_dc1_pd2";
                                 nvidia,function = "rsvd3";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
 
-                        /* TOUCH_PEN_INT# */
+                        /* TOUCH_PEN_INT# (On-module) */
                         pv0 {
                                 nvidia,pins = "pv0";
                                 nvidia,function = "rsvd1";
@@ -441,7 +818,19 @@
                 };
         };
 
-        hdmiddc: i2c@7000c700 {
+        serial@70006040 {
+                compatible = "nvidia,tegra30-hsuart";
+        };
+
+        serial@70006200 {
+                compatible = "nvidia,tegra30-hsuart";
+        };
+
+        serial@70006300 {
+                compatible = "nvidia,tegra30-hsuart";
+        };
+
+        hdmi_ddc: i2c@7000c700 {
                 clock-frequency = <10000>;
         };
 
@@ -457,12 +846,13 @@
                 sgtl5000: codec@a {
                         compatible = "fsl,sgtl5000";
                         reg = <0x0a>;
-                        VDDA-supply = <&sys_3v3_reg>;
-                        VDDIO-supply = <&sys_3v3_reg>;
+                        VDDA-supply = <&reg_module_3v3_audio>;
+                        VDDD-supply = <&reg_1v8_vio>;
+                        VDDIO-supply = <&reg_module_3v3>;
                         clocks = <&tegra_car TEGRA30_CLK_EXTERN1>;
                 };
 
-                pmic: tps65911@2d {
+                pmic: pmic@2d {
                         compatible = "ti,tps65911";
                         reg = <0x2d>;
 
@@ -475,43 +865,38 @@
                         #gpio-cells = <2>;
                         gpio-controller;
 
-                        vcc1-supply = <&sys_3v3_reg>;
-                        vcc2-supply = <&sys_3v3_reg>;
-                        vcc3-supply = <&vio_reg>;
-                        vcc4-supply = <&sys_3v3_reg>;
-                        vcc5-supply = <&sys_3v3_reg>;
-                        vcc6-supply = <&vio_reg>;
-                        vcc7-supply = <&charge_pump_5v0_reg>;
-                        vccio-supply = <&sys_3v3_reg>;
+                        vcc1-supply = <&reg_module_3v3>;
+                        vcc2-supply = <&reg_module_3v3>;
+                        vcc3-supply = <&reg_1v8_vio>;
+                        vcc4-supply = <&reg_module_3v3>;
+                        vcc5-supply = <&reg_module_3v3>;
+                        vcc6-supply = <&reg_1v8_vio>;
+                        vcc7-supply = <&reg_5v0_charge_pump>;
+                        vccio-supply = <&reg_module_3v3>;
 
                         regulators {
-                                /* SW1: +V1.35_VDDIO_DDR */
                                 vdd1_reg: vdd1 {
-                                        regulator-name = "vddio_ddr_1v35";
+                                        regulator-name = "+V1.35_VDDIO_DDR";
                                         regulator-min-microvolt = <1350000>;
                                         regulator-max-microvolt = <1350000>;
                                         regulator-always-on;
                                 };
 
-                                /* SW2: +V1.05 */
                                 vdd2_reg: vdd2 {
-                                        regulator-name =
-                                                "vdd_pexa,vdd_pexb,vdd_sata";
+                                        regulator-name = "+V1.05";
                                         regulator-min-microvolt = <1050000>;
                                         regulator-max-microvolt = <1050000>;
                                 };
 
-                                /* SW CTRL: +V1.0_VDD_CPU */
                                 vddctrl_reg: vddctrl {
-                                        regulator-name = "vdd_cpu,vdd_sys";
+                                        regulator-name = "+V1.0_VDD_CPU";
                                         regulator-min-microvolt = <1150000>;
                                         regulator-max-microvolt = <1150000>;
                                         regulator-always-on;
                                 };
 
-                                /* SWIO: +V1.8 */
-                                vio_reg: vio {
-                                        regulator-name = "vdd_1v8_gen";
+                                reg_1v8_vio: vio {
+                                        regulator-name = "+V1.8";
                                         regulator-min-microvolt = <1800000>;
                                         regulator-max-microvolt = <1800000>;
                                         regulator-always-on;
@@ -521,27 +906,24 @@
 
                                 /*
                                  * EN_+V3.3 switching via FET:
-                                 * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN
-                                 * see also v3_3 fixed supply
+                                 * +V3.3_AUDIO_AVDD_S, +V3.3
+                                 * see also +V3.3 fixed supply
                                  */
                                 ldo2_reg: ldo2 {
-                                        regulator-name = "en_3v3";
+                                        regulator-name = "EN_+V3.3";
                                         regulator-min-microvolt = <3300000>;
                                         regulator-max-microvolt = <3300000>;
                                         regulator-always-on;
                                 };
 
-                                /* +V1.2_CSI */
                                 ldo3_reg: ldo3 {
-                                        regulator-name =
-                                                "avdd_dsi_csi,pwrdet_mipi";
+                                        regulator-name = "+V1.2_CSI";
                                         regulator-min-microvolt = <1200000>;
                                         regulator-max-microvolt = <1200000>;
                                 };
 
-                                /* +V1.2_VDD_RTC */
                                 ldo4_reg: ldo4 {
-                                        regulator-name = "vdd_rtc";
+                                        regulator-name = "+V1.2_VDD_RTC";
                                         regulator-min-microvolt = <1200000>;
                                         regulator-max-microvolt = <1200000>;
                                         regulator-always-on;
@@ -549,10 +931,10 @@
 
                                 /*
                                  * +V2.8_AVDD_VDAC:
-                                 * only required for analog RGB
+                                 * only required for (unsupported) analog RGB
                                  */
                                 ldo5_reg: ldo5 {
-                                        regulator-name = "avdd_vdac";
+                                        regulator-name = "+V2.8_AVDD_VDAC";
                                         regulator-min-microvolt = <2800000>;
                                         regulator-max-microvolt = <2800000>;
                                         regulator-always-on;
@@ -564,22 +946,20 @@
                                  * granularity
                                  */
                                 ldo6_reg: ldo6 {
-                                        regulator-name = "avdd_plle";
+                                        regulator-name = "+V1.05_AVDD_PLLE";
                                         regulator-min-microvolt = <1100000>;
                                         regulator-max-microvolt = <1100000>;
                                 };
 
-                                /* +V1.2_AVDD_PLL */
                                 ldo7_reg: ldo7 {
-                                        regulator-name = "avdd_pll";
+                                        regulator-name = "+V1.2_AVDD_PLL";
                                         regulator-min-microvolt = <1200000>;
                                         regulator-max-microvolt = <1200000>;
                                         regulator-always-on;
                                 };
 
-                                /* +V1.0_VDD_DDR_HS */
                                 ldo8_reg: ldo8 {
-                                        regulator-name = "vdd_ddr_hs";
+                                        regulator-name = "+V1.0_VDD_DDR_HS";
                                         regulator-min-microvolt = <1000000>;
                                         regulator-max-microvolt = <1000000>;
                                         regulator-always-on;
@@ -588,11 +968,10 @@
                 };
 
                 /* STMPE811 touch screen controller */
-                stmpe811@41 {
+                touchscreen@41 {
                         compatible = "st,stmpe811";
                         reg = <0x41>;
-                        interrupts = <TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
-                        interrupt-parent = <&gpio>;
+                        irq-gpio = <&gpio TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
                         interrupt-controller;
                         id = <0>;
                         blocks = <0x5>;
@@ -626,7 +1005,7 @@
 
                 /*
                  * LM95245 temperature sensor
-                 * Note: OVERT_N directly connected to PMIC PWRDN
+                 * Note: OVERT1# directly connected to TPS65911 PMIC PWRDN
                  */
                 temp-sensor@4c {
                         compatible = "national,lm95245";
@@ -634,7 +1013,7 @@
                 };
 
                 /* SW: +V1.2_VDD_CORE */
-                tps62362@60 {
+                regulator@60 {
                         compatible = "ti,tps62362";
                         reg = <0x60>;
 
@@ -659,7 +1038,7 @@
                         reg = <1>;
                         clocks = <&clk16m>;
                         interrupt-parent = <&gpio>;
-                        interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_RISING>;
+                        interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_FALLING>;
                         spi-max-frequency = <10000000>;
                 };
         };
@@ -674,7 +1053,7 @@
                         reg = <0>;
                         clocks = <&clk16m>;
                         interrupt-parent = <&gpio>;
-                        interrupts = <TEGRA_GPIO(W, 2) IRQ_TYPE_EDGE_RISING>;
+                        interrupts = <TEGRA_GPIO(W, 2) IRQ_TYPE_EDGE_FALLING>;
                         spi-max-frequency = <10000000>;
                 };
         };
@@ -688,6 +1067,18 @@
                 nvidia,core-pwr-off-time = <0>;
                 nvidia,core-power-req-active-high;
                 nvidia,sys-clock-req-active-high;
+
+                /* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */
+                i2c-thermtrip {
+                        nvidia,i2c-controller-id = <4>;
+                        nvidia,bus-addr = <0x2d>;
+                        nvidia,reg-addr = <0x3f>;
+                        nvidia,reg-data = <0x1>;
+                };
+        };
+
+        hda@70030000 {
+                status = "okay";
         };
 
         ahub@70080000 {
@@ -701,73 +1092,65 @@
                 status = "okay";
                 bus-width = <8>;
                 non-removable;
+                vmmc-supply = <&reg_module_3v3>; /* VCC */
+                vqmmc-supply = <&reg_1v8_vio>; /* VCCQ */
+                mmc-ddr-1_8v;
         };
 
-        clocks {
-                compatible = "simple-bus";
-                #address-cells = <1>;
-                #size-cells = <0>;
+        clk32k_in: xtal1 {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <32768>;
+        };
 
-                clk32k_in: clk@0 {
-                        compatible = "fixed-clock";
-                        reg = <0>;
-                        #clock-cells = <0>;
-                        clock-frequency = <32768>;
-                };
+        clk16m: osc4 {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <16000000>;
+        };
 
-                clk16m: clk@1 {
-                        compatible = "fixed-clock";
-                        reg = <1>;
-                        #clock-cells = <0>;
-                        clock-frequency = <16000000>;
-                        clock-output-names = "clk16m";
-                };
+        reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll {
+                compatible = "regulator-fixed";
+                regulator-name = "+V1.8_AVDD_HDMI_PLL";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                enable-active-high;
+                gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
+                vin-supply = <&reg_1v8_vio>;
         };
 
-        regulators {
-                compatible = "simple-bus";
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                avdd_hdmi_pll_1v8_reg: regulator@100 {
-                        compatible = "regulator-fixed";
-                        reg = <100>;
-                        regulator-name = "+V1.8_AVDD_HDMI_PLL";
-                        regulator-min-microvolt = <1800000>;
-                        regulator-max-microvolt = <1800000>;
-                        enable-active-high;
-                        gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
-                        vin-supply = <&vio_reg>;
-                };
+        reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
+                compatible = "regulator-fixed";
+                regulator-name = "+V3.3_AVDD_HDMI";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                enable-active-high;
+                gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
+                vin-supply = <&reg_module_3v3>;
+        };
 
-                sys_3v3_reg: regulator@101 {
-                        compatible = "regulator-fixed";
-                        reg = <101>;
-                        regulator-name = "3v3";
-                        regulator-min-microvolt = <3300000>;
-                        regulator-max-microvolt = <3300000>;
-                        regulator-always-on;
-                };
+        reg_5v0_charge_pump: regulator-5v0-charge-pump {
+                compatible = "regulator-fixed";
+                regulator-name = "+V5.0";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-always-on;
+        };
 
-                avdd_hdmi_3v3_reg: regulator@102 {
-                        compatible = "regulator-fixed";
-                        reg = <102>;
-                        regulator-name = "+V3.3_AVDD_HDMI";
-                        regulator-min-microvolt = <3300000>;
-                        regulator-max-microvolt = <3300000>;
-                        enable-active-high;
-                        gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
-                        vin-supply = <&sys_3v3_reg>;
-                };
+        reg_module_3v3: regulator-module-3v3 {
+                compatible = "regulator-fixed";
+                regulator-name = "+V3.3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+        };
 
-                charge_pump_5v0_reg: regulator@103 {
-                        compatible = "regulator-fixed";
-                        reg = <103>;
-                        regulator-name = "5v0";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
-                        regulator-always-on;
-                };
+        reg_module_3v3_audio: regulator-module-3v3-audio {
+                compatible = "regulator-fixed";
+                regulator-name = "+V3.3_AUDIO_AVDD_S";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
         };
 
         sound {
diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
index 16e1f387aa6d..5965150ecdd2 100644
--- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
@@ -1,15 +1,17 @@
 // SPDX-License-Identifier: GPL-2.0
 /dts-v1/;
 
+#include <dt-bindings/input/input.h>
 #include "tegra30-colibri.dtsi"
 
 / {
         model = "Toradex Colibri T30 on Colibri Evaluation Board";
-        compatible = "toradex,colibri_t30-eval-v3", "toradex,colibri_t30", "nvidia,tegra30";
+        compatible = "toradex,colibri_t30-eval-v3", "toradex,colibri_t30",
+                     "nvidia,tegra30";
 
         aliases {
                 rtc0 = "/i2c@7000c000/rtc@68";
-                rtc1 = "/i2c@7000d000/tps65911@2d";
+                rtc1 = "/i2c@7000d000/pmic@2d";
                 rtc2 = "/rtc@7000e000";
                 serial0 = &uarta;
                 serial1 = &uartb;
@@ -27,22 +29,25 @@
                                 nvidia,panel = <&panel>;
                         };
                 };
+
                 hdmi@54280000 {
                         status = "okay";
+                        hdmi-supply = <&reg_5v0>;
                 };
         };
 
+        /* Colibri UART-A */
         serial@70006000 {
                 status = "okay";
         };
 
+        /* Colibri UART-C */
         serial@70006040 {
-                compatible = "nvidia,tegra30-hsuart";
                 status = "okay";
         };
 
+        /* Colibri UART-B */
         serial@70006300 {
-                compatible = "nvidia,tegra30-hsuart";
                 status = "okay";
         };
 
@@ -65,8 +70,12 @@
                 };
         };
 
+        /* GEN2_I2C: unused */
+
+        /* CAM_I2C (I2C3): unused */
+
         /* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */
-        hdmiddc: i2c@7000c700 {
+        i2c@7000c700 {
                 status = "okay";
         };
 
@@ -74,18 +83,17 @@
         spi@7000d400 {
                 status = "okay";
                 spi-max-frequency = <25000000>;
-                can0: can@0 {
+
+                can@0 {
                         compatible = "microchip,mcp2515";
                         reg = <0>;
                         clocks = <&clk16m>;
                         interrupt-parent = <&gpio>;
-                        interrupts = <TEGRA_GPIO(S, 0) IRQ_TYPE_EDGE_RISING>;
+                        /* CAN_INT */
+                        interrupts = <TEGRA_GPIO(S, 0) IRQ_TYPE_EDGE_FALLING>;
                         spi-max-frequency = <10000000>;
-                };
-                spidev0: spi@1 {
-                        compatible = "spidev";
-                        reg = <1>;
-                        spi-max-frequency = <25000000>;
+                        vdd-supply = <&reg_3v3>;
+                        xceiver-supply = <&reg_5v0>;
                 };
         };
 
@@ -93,19 +101,19 @@
         sdhci@78000200 {
                 status = "okay";
                 bus-width = <4>;
-                cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
+                cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; /* MMCD */
                 no-1-8-v;
         };
 
         /* EHCI instance 0: USB1_DP/N -> USBC_P/N */
         usb@7d000000 {
                 status = "okay";
+                dr_mode = "otg";
         };
 
         usb-phy@7d000000 {
                 status = "okay";
-                dr_mode = "otg";
-                vbus-supply = <&usbc_vbus_reg>;
+                vbus-supply = <&reg_usbc_vbus>;
         };
 
         /* EHCI instance 2: USB3_DP/N -> USBH_P/N */
@@ -115,28 +123,23 @@
 
         usb-phy@7d008000 {
                 status = "okay";
-                vbus-supply = <&usbh_vbus_reg>;
+                vbus-supply = <&reg_usbh_vbus>;
         };
 
         backlight: backlight {
                 compatible = "pwm-backlight";
-
-                /* PWM<A> */
-                pwms = <&pwm 0 5000000>;
                 brightness-levels = <255 128 64 32 16 8 4 0>;
                 default-brightness-level = <6>;
                 /* BL_ON */
                 enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
+                power-supply = <&reg_3v3>;
+                pwms = <&pwm 0 5000000>; /* PWM<A> */
         };
 
-        clocks {
-                clk16m: clk@1 {
-                        compatible = "fixed-clock";
-                        reg = <1>;
-                        #clock-cells = <0>;
-                        clock-frequency = <16000000>;
-                        clock-output-names = "clk16m";
-                };
+        clk16m: osc3 {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <16000000>;
         };
 
         gpio-keys {
@@ -157,58 +160,39 @@
                  * edt,et070080dh6: EDT 7.0" LCD TFT
                  */
                 compatible = "edt,et057090dhu", "simple-panel";
-
                 backlight = <&backlight>;
+                power-supply = <&reg_3v3>;
         };
 
-        pwmleds {
-                compatible = "pwm-leds";
-
-                pwmb {
-                        label = "PWM<B>";
-                        pwms = <&pwm 1 19600>;
-                        max-brightness = <255>;
-                };
-                pwmc {
-                        label = "PWM<C>";
-                        pwms = <&pwm 2 19600>;
-                        max-brightness = <255>;
-                };
-                pwmd {
-                        label = "PWM<D>";
-                        pwms = <&pwm 3 19600>;
-                        max-brightness = <255>;
-                };
+        reg_3v3: regulator-3v3 {
+                compatible = "regulator-fixed";
+                regulator-name = "3.3V_SW";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
         };
 
-        regulators {
-                sys_5v0_reg: regulator@1 {
-                        compatible = "regulator-fixed";
-                        reg = <1>;
-                        regulator-name = "5v0";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
-                        regulator-always-on;
-                };
+        reg_5v0: regulator-5v0 {
+                compatible = "regulator-fixed";
+                regulator-name = "5V_SW";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+        };
 
-                usbc_vbus_reg: regulator@2 {
-                        compatible = "regulator-fixed";
-                        reg = <2>;
-                        regulator-name = "usbc_vbus";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
-                        vin-supply = <&sys_5v0_reg>;
-                };
+        reg_usbc_vbus: regulator-usbc-vbus {
+                compatible = "regulator-fixed";
+                regulator-name = "VCC_USB5";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                vin-supply = <&reg_5v0>;
+        };
 
-                /* USBH_PEN */
-                usbh_vbus_reg: regulator@3 {
-                        compatible = "regulator-fixed";
-                        reg = <3>;
-                        regulator-name = "usbh_vbus";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
-                        gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
-                        vin-supply = <&sys_5v0_reg>;
-                };
+        /* USBH_PEN resp. USB_P_EN */
+        reg_usbh_vbus: regulator-usbh-vbus {
+                compatible = "regulator-fixed";
+                regulator-name = "VCC_USB[1-4]";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
+                vin-supply = <&reg_5v0>;
         };
 };
diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi
index 526ed71cf7a3..35af03ca9e90 100644
--- a/arch/arm/boot/dts/tegra30-colibri.dtsi
+++ b/arch/arm/boot/dts/tegra30-colibri.dtsi
@@ -1,27 +1,22 @@
 // SPDX-License-Identifier: GPL-2.0
-#include <dt-bindings/input/input.h>
 #include "tegra30.dtsi"
 
 /*
  * Toradex Colibri T30 Module Device Tree
- * Compatible for Revisions V1.1B, V1.1C, V1.1D, V1.1E; IT: V1.1A
+ * Compatible for Revisions V1.1B, V1.1C, V1.1D, V1.1E, V1.1F; IT: V1.1A, V1.1B
  */
 / {
-        model = "Toradex Colibri T30";
-        compatible = "toradex,colibri_t30", "nvidia,tegra30";
-
         memory@80000000 {
                 reg = <0x80000000 0x40000000>;
         };
 
         host1x@50000000 {
                 hdmi@54280000 {
-                        vdd-supply = <&avdd_hdmi_3v3_reg>;
-                        pll-supply = <&avdd_hdmi_pll_1v8_reg>;
-
+                        nvidia,ddc-i2c-bus = <&hdmi_ddc>;
                         nvidia,hpd-gpio =
                                 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
-                        nvidia,ddc-i2c-bus = <&hdmiddc>;
+                        pll-supply = <&reg_1v8_avdd_hdmi_pll>;
+                        vdd-supply = <&reg_3v3_avdd_hdmi>;
                 };
         };
 
@@ -31,23 +26,173 @@
 
                 state_default: pinmux {
                         /* Analogue Audio (On-module) */
-                        clk1_out_pw4 {
+                        clk1-out-pw4 {
                                 nvidia,pins = "clk1_out_pw4";
                                 nvidia,function = "extperiph1";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        dap3_fs_pp0 {
-                                nvidia,pins =   "dap3_fs_pp0",
-                                                "dap3_sclk_pp3",
-                                                "dap3_din_pp1",
-                                                "dap3_dout_pp2";
+                        dap3-fs-pp0 {
+                                nvidia,pins = "dap3_fs_pp0",
+                                              "dap3_sclk_pp3",
+                                              "dap3_din_pp1",
+                                              "dap3_dout_pp2";
                                 nvidia,function = "i2s2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
 
+                        /* Colibri Address/Data Bus (GMI) */
+                        gmi-ad0-pg0 {
+                                nvidia,pins = "gmi_ad0_pg0",
+                                              "gmi_ad2_pg2",
+                                              "gmi_ad3_pg3",
+                                              "gmi_ad4_pg4",
+                                              "gmi_ad5_pg5",
+                                              "gmi_ad6_pg6",
+                                              "gmi_ad7_pg7",
+                                              "gmi_ad8_ph0",
+                                              "gmi_ad9_ph1",
+                                              "gmi_ad10_ph2",
+                                              "gmi_ad11_ph3",
+                                              "gmi_ad12_ph4",
+                                              "gmi_ad13_ph5",
+                                              "gmi_ad14_ph6",
+                                              "gmi_ad15_ph7",
+                                              "gmi_adv_n_pk0",
+                                              "gmi_clk_pk1",
+                                              "gmi_cs4_n_pk2",
+                                              "gmi_cs2_n_pk3",
+                                              "gmi_iordy_pi5",
+                                              "gmi_oe_n_pi1",
+                                              "gmi_wait_pi7",
+                                              "gmi_wr_n_pi0",
+                                              "dap1_fs_pn0",
+                                              "dap1_din_pn1",
+                                              "dap1_dout_pn2",
+                                              "dap1_sclk_pn3",
+                                              "dap2_fs_pa2",
+                                              "dap2_sclk_pa3",
+                                              "dap2_din_pa4",
+                                              "dap2_dout_pa5",
+                                              "spi1_sck_px5",
+                                              "spi1_mosi_px4",
+                                              "spi1_cs0_n_px6",
+                                              "spi2_cs0_n_px3",
+                                              "spi2_miso_px1",
+                                              "spi2_mosi_px0",
+                                              "spi2_sck_px2",
+                                              "uart2_cts_n_pj5",
+                                              "uart2_rts_n_pj6";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        /* Further pins may be used as GPIOs */
+                        dap4-din-pp5 {
+                                nvidia,pins = "dap4_din_pp5",
+                                              "dap4_dout_pp6",
+                                              "dap4_fs_pp4",
+                                              "dap4_sclk_pp7",
+                                              "pbb7",
+                                              "sdmmc1_clk_pz0",
+                                              "sdmmc1_cmd_pz1",
+                                              "sdmmc1_dat0_py7",
+                                              "sdmmc1_dat1_py6",
+                                              "sdmmc1_dat3_py4",
+                                              "uart3_cts_n_pa1",
+                                              "uart3_txd_pw6",
+                                              "uart3_rxd_pw7";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd-d18-pm2 {
+                                nvidia,pins = "lcd_d18_pm2",
+                                              "lcd_d19_pm3",
+                                              "lcd_d20_pm4",
+                                              "lcd_d21_pm5",
+                                              "lcd_d22_pm6",
+                                              "lcd_d23_pm7",
+                                              "lcd_dc0_pn6",
+                                              "pex_l2_clkreq_n_pcc7";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd-cs0-n-pn4 {
+                                nvidia,pins = "lcd_cs0_n_pn4",
+                                              "lcd_sdin_pz2",
+                                              "pu0",
+                                              "pu1",
+                                              "pu2",
+                                              "pu3",
+                                              "pu4",
+                                              "pu5",
+                                              "pu6",
+                                              "spi1_miso_px7",
+                                              "uart3_rts_n_pc0";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd-pwr0-pb2 {
+                                nvidia,pins = "lcd_pwr0_pb2",
+                                              "lcd_sck_pz4",
+                                              "lcd_sdout_pn5",
+                                              "lcd_wr_n_pz3";
+                                nvidia,function = "hdcp";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pbb4 {
+                                nvidia,pins = "pbb4",
+                                              "pbb5",
+                                              "pbb6";
+                                nvidia,function = "displayb";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        /* Multiplexed RDnWR and therefore disabled */
+                        lcd-cs1-n-pw0 {
+                                nvidia,pins = "lcd_cs1_n_pw0";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        /* Multiplexed GMI_CLK and therefore disabled */
+                        owr {
+                                nvidia,pins = "owr";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        /* Tri-stating GMI_WR_N on nPWE SODIMM pin 99 */
+                        sdmmc3-dat4-pd1 {
+                                nvidia,pins = "sdmmc3_dat4_pd1";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        /* Not tri-stating GMI_WR_N on RDnWR SODIMM pin 93 */
+                        sdmmc3-dat5-pd0 {
+                                nvidia,pins = "sdmmc3_dat5_pd0";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
                         /* Colibri BL_ON */
                         pv2 {
                                 nvidia,pins = "pv2";
@@ -57,7 +202,7 @@
                         };
 
                         /* Colibri Backlight PWM<A> */
-                        sdmmc3_dat3_pb4 {
+                        sdmmc3-dat3-pb4 {
                                 nvidia,pins = "sdmmc3_dat3_pb4";
                                 nvidia,function = "pwm0";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -65,7 +210,7 @@
                         };
 
                         /* Colibri CAN_INT */
-                        kb_row8_ps0 {
+                        kb-row8-ps0 {
                                 nvidia,pins = "kb_row8_ps0";
                                 nvidia,function = "kbc";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
@@ -73,26 +218,133 @@
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
 
+                        /* Colibri DDC */
+                        ddc-scl-pv4 {
+                                nvidia,pins = "ddc_scl_pv4",
+                                              "ddc_sda_pv5";
+                                nvidia,function = "i2c4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Colibri EXT_IO* */
+                        gen2-i2c-scl-pt5 {
+                                nvidia,pins = "gen2_i2c_scl_pt5",
+                                              "gen2_i2c_sda_pt6";
+                                nvidia,function = "rsvd4";
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        spdif-in-pk6 {
+                                nvidia,pins =   "spdif_in_pk6";
+                                nvidia,function = "hda";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Colibri GPIO */
+                        clk2-out-pw5 {
+                                nvidia,pins = "clk2_out_pw5",
+                                              "pcc2",
+                                              "pv3",
+                                              "sdmmc1_dat2_py5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        lcd-pwr1-pc1 {
+                                nvidia,pins = "lcd_pwr1_pc1",
+                                              "pex_l1_clkreq_n_pdd6",
+                                              "pex_l1_rst_n_pdd5";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pv1 {
+                                nvidia,pins = "pv1",
+                                              "sdmmc3_dat0_pb7",
+                                              "sdmmc3_dat1_pb6";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Colibri HOTPLUG_DETECT (HDMI) */
+                        hdmi-int-pn7 {
+                                nvidia,pins = "hdmi_int_pn7";
+                                nvidia,function = "hdmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Colibri I2C */
+                        gen1-i2c-scl-pc4 {
+                                nvidia,pins = "gen1_i2c_scl_pc4",
+                                              "gen1_i2c_sda_pc5";
+                                nvidia,function = "i2c1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Colibri LCD (L_* resp. LDD<*>) */
+                        lcd-d0-pe0 {
+                                nvidia,pins = "lcd_d0_pe0",
+                                              "lcd_d1_pe1",
+                                              "lcd_d2_pe2",
+                                              "lcd_d3_pe3",
+                                              "lcd_d4_pe4",
+                                              "lcd_d5_pe5",
+                                              "lcd_d6_pe6",
+                                              "lcd_d7_pe7",
+                                              "lcd_d8_pf0",
+                                              "lcd_d9_pf1",
+                                              "lcd_d10_pf2",
+                                              "lcd_d11_pf3",
+                                              "lcd_d12_pf4",
+                                              "lcd_d13_pf5",
+                                              "lcd_d14_pf6",
+                                              "lcd_d15_pf7",
+                                              "lcd_d16_pm0",
+                                              "lcd_d17_pm1",
+                                              "lcd_de_pj1",
+                                              "lcd_hsync_pj3",
+                                              "lcd_pclk_pb3",
+                                              "lcd_vsync_pj4";
+                                nvidia,function = "displaya";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
                         /*
                          * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE
-                         * todays display need DE, disable LCD_M1
+                         * today's display need DE, disable LCD_M1
                          */
-                        lcd_m1_pw1 {
+                        lcd-m1-pw1 {
                                 nvidia,pins = "lcd_m1_pw1";
                                 nvidia,function = "rsvd3";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
 
                         /* Colibri MMC */
-                        kb_row10_ps2 {
+                        kb-row10-ps2 {
                                 nvidia,pins = "kb_row10_ps2";
                                 nvidia,function = "sdmmc2";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
-                        kb_row11_ps3 {
+                        kb-row11-ps3 {
                                 nvidia,pins = "kb_row11_ps3",
                                               "kb_row12_ps4",
                                               "kb_row13_ps5",
@@ -102,9 +354,108 @@
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
+                        /* Colibri MMC_CD */
+                        gmi-wp-n-pc7 {
+                                nvidia,pins = "gmi_wp_n_pc7";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        /* Multiplexed and therefore disabled */
+                        cam-mclk-pcc0 {
+                                nvidia,pins =   "cam_mclk_pcc0";
+                                nvidia,function = "vi_alt3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        cam-i2c-scl-pbb1 {
+                                nvidia,pins = "cam_i2c_scl_pbb1",
+                                              "cam_i2c_sda_pbb2";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+                        pbb0 {
+                                nvidia,pins = "pbb0",
+                                              "pcc1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pbb3 {
+                                nvidia,pins = "pbb3";
+                                nvidia,function = "displayb";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Colibri nRESET_OUT */
+                        gmi-rst-n-pi4 {
+                                nvidia,pins = "gmi_rst_n_pi4";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /*
+                         * Colibri Parallel Camera (Optional)
+                         * pins multiplexed with others and therefore disabled
+                         */
+                        vi-vsync-pd6 {
+                                nvidia,pins = "vi_d0_pt4",
+                                              "vi_d1_pd5",
+                                              "vi_d2_pl0",
+                                              "vi_d3_pl1",
+                                              "vi_d4_pl2",
+                                              "vi_d5_pl3",
+                                              "vi_d6_pl4",
+                                              "vi_d7_pl5",
+                                              "vi_d8_pl6",
+                                              "vi_d9_pl7",
+                                              "vi_d10_pt2",
+                                              "vi_d11_pt3",
+                                              "vi_hsync_pd7",
+                                              "vi_mclk_pt1",
+                                              "vi_pclk_pt0",
+                                              "vi_vsync_pd6";
+                                nvidia,function = "vi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Colibri PWM<B> */
+                        sdmmc3-dat2-pb5 {
+                                nvidia,pins = "sdmmc3_dat2_pb5";
+                                nvidia,function = "pwm1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Colibri PWM<C> */
+                        sdmmc3-clk-pa6 {
+                                nvidia,pins = "sdmmc3_clk_pa6";
+                                nvidia,function = "pwm2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Colibri PWM<D> */
+                        sdmmc3-cmd-pa7 {
+                                nvidia,pins = "sdmmc3_cmd_pa7";
+                                nvidia,function = "pwm3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
 
                         /* Colibri SSP */
-                        ulpi_clk_py0 {
+                        ulpi-clk-py0 {
                                 nvidia,pins = "ulpi_clk_py0",
                                               "ulpi_dir_py1",
                                               "ulpi_nxt_py2",
@@ -113,16 +464,18 @@
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
-                        sdmmc3_dat6_pd3 {
+                        /* Multiplexed SSPFRM, SSPTXD and therefore disabled */
+                        sdmmc3-dat6-pd3 {
                                 nvidia,pins = "sdmmc3_dat6_pd3",
                                               "sdmmc3_dat7_pd4";
                                 nvidia,function = "spdif";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
 
-                        /* Colibri UART_A */
-                        ulpi_data0 {
+                        /* Colibri UART-A */
+                        ulpi-data0 {
                                 nvidia,pins = "ulpi_data0_po1",
                                               "ulpi_data1_po2",
                                               "ulpi_data2_po3",
@@ -136,8 +489,8 @@
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
 
-                        /* Colibri UART_B */
-                        gmi_a16_pj7 {
+                        /* Colibri UART-B */
+                        gmi-a16-pj7 {
                                 nvidia,pins = "gmi_a16_pj7",
                                               "gmi_a17_pb0",
                                               "gmi_a18_pb1",
@@ -147,8 +500,8 @@
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
 
-                        /* Colibri UART_C */
-                        uart2_rxd {
+                        /* Colibri UART-C */
+                        uart2-rxd {
                                 nvidia,pins = "uart2_rxd_pc3",
                                               "uart2_txd_pc2";
                                 nvidia,function = "uartb";
@@ -156,15 +509,53 @@
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                         };
 
-                        /* eMMC */
-                        sdmmc4_clk_pcc4 {
+                        /* Colibri USBC_DET */
+                        spdif-out-pk5 {
+                                nvidia,pins =   "spdif_out_pk5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Colibri USBH_PEN */
+                        spi2-cs1-n-pw2 {
+                                nvidia,pins = "spi2_cs1_n_pw2";
+                                nvidia,function = "spi2_alt";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Colibri USBH_OC */
+                        spi2-cs2-n-pw3, {
+                                nvidia,pins = "spi2_cs2_n_pw3";
+                                nvidia,function = "spi2_alt";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Colibri VGA not supported and therefore disabled */
+                        crt-hsync-pv6 {
+                                nvidia,pins = "crt_hsync_pv6",
+                                              "crt_vsync_pv7";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* eMMC (On-module) */
+                        sdmmc4-clk-pcc4 {
                                 nvidia,pins = "sdmmc4_clk_pcc4",
+                                              "sdmmc4_cmd_pt7",
                                               "sdmmc4_rst_n_pcc3";
                                 nvidia,function = "sdmmc4";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        sdmmc4_dat0_paa0 {
+                        sdmmc4-dat0-paa0 {
                                 nvidia,pins = "sdmmc4_dat0_paa0",
                                               "sdmmc4_dat1_paa1",
                                               "sdmmc4_dat2_paa2",
@@ -176,17 +567,111 @@
                                 nvidia,function = "sdmmc4";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* LAN_EXT_WAKEUP#, LAN_PME (On-module) */
+                        pex-l0-rst-n-pdd1 {
+                                nvidia,pins = "pex_l0_rst_n_pdd1",
+                                              "pex_wake_n_pdd3";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        /* LAN_V_BUS, LAN_RESET# (On-module) */
+                        pex-l0-clkreq-n-pdd2 {
+                                nvidia,pins = "pex_l0_clkreq_n_pdd2",
+                                              "pex_l0_prsnt_n_pdd0";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* nBATT_FAULT(SENSE), nVDD_FAULT(SENSE) */
+                        pex-l2-rst-n-pcc6 {
+                                nvidia,pins = "pex_l2_rst_n_pcc6",
+                                              "pex_l2_prsnt_n_pdd7";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Not connected and therefore disabled */
+                        clk1-req-pee2 {
+                                nvidia,pins = "clk1_req_pee2",
+                                              "pex_l1_prsnt_n_pdd4";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        clk2-req-pcc5 {
+                                nvidia,pins = "clk2_req_pcc5",
+                                              "clk3_out_pee0",
+                                              "clk3_req_pee1",
+                                              "clk_32k_out_pa0",
+                                              "hdmi_cec_pee3",
+                                              "sys_clk_req_pz5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi-dqs-pi2 {
+                                nvidia,pins = "gmi_dqs_pi2",
+                                              "kb_col2_pq2",
+                                              "kb_col3_pq3",
+                                              "kb_col4_pq4",
+                                              "kb_col5_pq5",
+                                              "kb_row4_pr4";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb-col0-pq0 {
+                                nvidia,pins = "kb_col0_pq0",
+                                              "kb_col1_pq1",
+                                              "kb_col6_pq6",
+                                              "kb_col7_pq7",
+                                              "kb_row5_pr5",
+                                              "kb_row6_pr6",
+                                              "kb_row7_pr7",
+                                              "kb_row9_ps1";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb-row0-pr0 {
+                                nvidia,pins = "kb_row0_pr0",
+                                              "kb_row1_pr1",
+                                              "kb_row2_pr2",
+                                              "kb_row3_pr3";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        lcd-pwr2-pc6 {
+                                nvidia,pins = "lcd_pwr2_pc6";
+                                nvidia,function = "hdcp";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
 
                         /* Power I2C (On-module) */
-                        pwr_i2c_scl_pz6 {
+                        pwr-i2c-scl-pz6 {
                                 nvidia,pins = "pwr_i2c_scl_pz6",
                                               "pwr_i2c_sda_pz7";
                                 nvidia,function = "i2cpwr";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
-                                nvidia,lock = <TEGRA_PIN_DISABLE>;
                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
                         };
 
@@ -195,15 +680,15 @@
                          * temperature sensor therefore requires disabling for
                          * now
                          */
-                        lcd_dc1_pd2 {
+                        lcd-dc1-pd2 {
                                 nvidia,pins = "lcd_dc1_pd2";
                                 nvidia,function = "rsvd3";
-                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
-                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
 
-                        /* TOUCH_PEN_INT# */
+                        /* TOUCH_PEN_INT# (On-module) */
                         pv0 {
                                 nvidia,pins = "pv0";
                                 nvidia,function = "rsvd1";
@@ -214,13 +699,21 @@
                 };
         };
 
-        hdmiddc: i2c@7000c700 {
+        serial@70006040 {
+                compatible = "nvidia,tegra30-hsuart";
+        };
+
+        serial@70006300 {
+                compatible = "nvidia,tegra30-hsuart";
+        };
+
+        hdmi_ddc: i2c@7000c700 {
                 clock-frequency = <10000>;
         };
 
         /*
          * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
-         * touch screen controller
+         * touch screen controller (On-module)
          */
         i2c@7000d000 {
                 status = "okay";
@@ -230,12 +723,13 @@
                 sgtl5000: codec@a {
                         compatible = "fsl,sgtl5000";
                         reg = <0x0a>;
-                        VDDA-supply = <&sys_3v3_reg>;
-                        VDDIO-supply = <&sys_3v3_reg>;
+                        VDDA-supply = <&reg_module_3v3_audio>;
+                        VDDD-supply = <&reg_1v8_vio>;
+                        VDDIO-supply = <&reg_module_3v3>;
                         clocks = <&tegra_car TEGRA30_CLK_EXTERN1>;
                 };
 
-                pmic: tps65911@2d {
+                pmic: pmic@2d {
                         compatible = "ti,tps65911";
                         reg = <0x2d>;
 
@@ -248,19 +742,18 @@
                         #gpio-cells = <2>;
                         gpio-controller;
 
-                        vcc1-supply = <&sys_3v3_reg>;
-                        vcc2-supply = <&sys_3v3_reg>;
-                        vcc3-supply = <&vio_reg>;
-                        vcc4-supply = <&sys_3v3_reg>;
-                        vcc5-supply = <&sys_3v3_reg>;
-                        vcc6-supply = <&vio_reg>;
-                        vcc7-supply = <&charge_pump_5v0_reg>;
-                        vccio-supply = <&sys_3v3_reg>;
+                        vcc1-supply = <&reg_module_3v3>;
+                        vcc2-supply = <&reg_module_3v3>;
+                        vcc3-supply = <&reg_1v8_vio>;
+                        vcc4-supply = <&reg_module_3v3>;
+                        vcc5-supply = <&reg_module_3v3>;
+                        vcc6-supply = <&reg_1v8_vio>;
+                        vcc7-supply = <&reg_5v0_charge_pump>;
+                        vccio-supply = <&reg_module_3v3>;
 
                         regulators {
-                                /* SW1: +V1.35_VDDIO_DDR */
                                 vdd1_reg: vdd1 {
-                                        regulator-name = "vddio_ddr_1v35";
+                                        regulator-name = "+V1.35_VDDIO_DDR";
                                         regulator-min-microvolt = <1350000>;
                                         regulator-max-microvolt = <1350000>;
                                         regulator-always-on;
@@ -268,17 +761,15 @@
 
                                 /* SW2: unused */
 
-                                /* SW CTRL: +V1.0_VDD_CPU */
                                 vddctrl_reg: vddctrl {
-                                        regulator-name = "vdd_cpu,vdd_sys";
+                                        regulator-name = "+V1.0_VDD_CPU";
                                         regulator-min-microvolt = <1150000>;
                                         regulator-max-microvolt = <1150000>;
                                         regulator-always-on;
                                 };
 
-                                /* SWIO: +V1.8 */
-                                vio_reg: vio {
-                                        regulator-name = "vdd_1v8_gen";
+                                reg_1v8_vio: vio {
+                                        regulator-name = "+V1.8";
                                         regulator-min-microvolt = <1800000>;
                                         regulator-max-microvolt = <1800000>;
                                         regulator-always-on;
@@ -289,10 +780,10 @@
                                 /*
                                  * EN_+V3.3 switching via FET:
                                  * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN
-                                 * see also 3v3 fixed supply
+                                 * see also +V3.3 fixed supply
                                  */
                                 ldo2_reg: ldo2 {
-                                        regulator-name = "en_3v3";
+                                        regulator-name = "EN_+V3.3";
                                         regulator-min-microvolt = <3300000>;
                                         regulator-max-microvolt = <3300000>;
                                         regulator-always-on;
@@ -300,9 +791,8 @@
 
                                 /* LDO3: unused */
 
-                                /* +V1.2_VDD_RTC */
                                 ldo4_reg: ldo4 {
-                                        regulator-name = "vdd_rtc";
+                                        regulator-name = "+V1.2_VDD_RTC";
                                         regulator-min-microvolt = <1200000>;
                                         regulator-max-microvolt = <1200000>;
                                         regulator-always-on;
@@ -310,10 +800,10 @@
 
                                 /*
                                  * +V2.8_AVDD_VDAC:
-                                 * only required for analog RGB
+                                 * only required for (unsupported) analog RGB
                                  */
                                 ldo5_reg: ldo5 {
-                                        regulator-name = "avdd_vdac";
+                                        regulator-name = "+V2.8_AVDD_VDAC";
                                         regulator-min-microvolt = <2800000>;
                                         regulator-max-microvolt = <2800000>;
                                         regulator-always-on;
@@ -325,22 +815,20 @@
                                  * granularity
                                  */
                                 ldo6_reg: ldo6 {
-                                        regulator-name = "avdd_plle";
+                                        regulator-name = "+V1.05_AVDD_PLLE";
                                         regulator-min-microvolt = <1100000>;
                                         regulator-max-microvolt = <1100000>;
                                 };
 
-                                /* +V1.2_AVDD_PLL */
                                 ldo7_reg: ldo7 {
-                                        regulator-name = "avdd_pll";
+                                        regulator-name = "+V1.2_AVDD_PLL";
                                         regulator-min-microvolt = <1200000>;
                                         regulator-max-microvolt = <1200000>;
                                         regulator-always-on;
                                 };
 
-                                /* +V1.0_VDD_DDR_HS */
                                 ldo8_reg: ldo8 {
-                                        regulator-name = "vdd_ddr_hs";
+                                        regulator-name = "+V1.0_VDD_DDR_HS";
                                         regulator-min-microvolt = <1000000>;
                                         regulator-max-microvolt = <1000000>;
                                         regulator-always-on;
@@ -349,11 +837,10 @@
                 };
 
                 /* STMPE811 touch screen controller */
-                stmpe811@41 {
+                touchscreen@41 {
                         compatible = "st,stmpe811";
                         reg = <0x41>;
-                        interrupts = <TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
-                        interrupt-parent = <&gpio>;
+                        irq-gpio = <&gpio TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
                         interrupt-controller;
                         id = <0>;
                         blocks = <0x5>;
@@ -387,7 +874,7 @@
 
                 /*
                  * LM95245 temperature sensor
-                 * Note: OVERT_N directly connected to PMIC PWRDN
+                 * Note: OVERT1# directly connected to TPS65911 PMIC PWRDN
                  */
                 temp-sensor@4c {
                         compatible = "national,lm95245";
@@ -395,7 +882,7 @@
                 };
 
                 /* SW: +V1.2_VDD_CORE */
-                tps62362@60 {
+                regulator@60 {
                         compatible = "ti,tps62362";
                         reg = <0x60>;
 
@@ -419,6 +906,18 @@
                 nvidia,core-pwr-off-time = <0>;
                 nvidia,core-power-req-active-high;
                 nvidia,sys-clock-req-active-high;
+
+                /* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */
+                i2c-thermtrip {
+                        nvidia,i2c-controller-id = <4>;
+                        nvidia,bus-addr = <0x2d>;
+                        nvidia,reg-addr = <0x3f>;
+                        nvidia,reg-data = <0x1>;
+                };
+        };
+
+        hda@70030000 {
+                status = "okay";
         };
 
         ahub@70080000 {
@@ -432,75 +931,85 @@
                 status = "okay";
                 bus-width = <8>;
                 non-removable;
+                vmmc-supply = <&reg_module_3v3>; /* VCC */
+                vqmmc-supply = <&reg_1v8_vio>; /* VCCQ */
+                mmc-ddr-1_8v;
         };
 
-        /* EHCI instance 1: USB2_DP/N -> AX88772B */
+        /* EHCI instance 1: USB2_DP/N -> AX88772B (On-module) */
         usb@7d004000 {
                 status = "okay";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                asix@1 {
+                        reg = <1>;
+                        local-mac-address = [00 00 00 00 00 00];
+                };
         };
 
         usb-phy@7d004000 {
                 status = "okay";
-                nvidia,is-wired = <1>;
+                vbus-supply = <&reg_lan_v_bus>;
         };
 
-        clocks {
-                compatible = "simple-bus";
-                #address-cells = <1>;
-                #size-cells = <0>;
+        clk32k_in: xtal1 {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <32768>;
+        };
 
-                clk32k_in: clk@0 {
-                        compatible = "fixed-clock";
-                        reg = <0>;
-                        #clock-cells = <0>;
-                        clock-frequency = <32768>;
-                };
+        reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll {
+                compatible = "regulator-fixed";
+                regulator-name = "+V1.8_AVDD_HDMI_PLL";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                enable-active-high;
+                gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
+                vin-supply = <&reg_1v8_vio>;
         };
 
-        regulators {
-                compatible = "simple-bus";
-                #address-cells = <1>;
-                #size-cells = <0>;
+        reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
+                compatible = "regulator-fixed";
+                regulator-name = "+V3.3_AVDD_HDMI";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                enable-active-high;
+                gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
+                vin-supply = <&reg_module_3v3>;
+        };
 
-                avdd_hdmi_pll_1v8_reg: regulator@100 {
-                        compatible = "regulator-fixed";
-                        reg = <100>;
-                        regulator-name = "+V1.8_AVDD_HDMI_PLL";
-                        regulator-min-microvolt = <1800000>;
-                        regulator-max-microvolt = <1800000>;
-                        enable-active-high;
-                        gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
-                        vin-supply = <&vio_reg>;
-                };
+        reg_5v0_charge_pump: regulator-5v0-charge-pump {
+                compatible = "regulator-fixed";
+                regulator-name = "+V5.0";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-always-on;
+        };
 
-                sys_3v3_reg: regulator@101 {
-                        compatible = "regulator-fixed";
-                        reg = <101>;
-                        regulator-name = "3v3";
-                        regulator-min-microvolt = <3300000>;
-                        regulator-max-microvolt = <3300000>;
-                        regulator-always-on;
-                };
+        reg_lan_v_bus: regulator-lan-v-bus {
+                compatible = "regulator-fixed";
+                regulator-name = "LAN_V_BUS";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                enable-active-high;
+                gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
+        };
 
-                avdd_hdmi_3v3_reg: regulator@102 {
-                        compatible = "regulator-fixed";
-                        reg = <102>;
-                        regulator-name = "+V3.3_AVDD_HDMI";
-                        regulator-min-microvolt = <3300000>;
-                        regulator-max-microvolt = <3300000>;
-                        enable-active-high;
-                        gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
-                        vin-supply = <&sys_3v3_reg>;
-                };
+        reg_module_3v3: regulator-module-3v3 {
+                compatible = "regulator-fixed";
+                regulator-name = "+V3.3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+        };
 
-                charge_pump_5v0_reg: regulator@103 {
-                        compatible = "regulator-fixed";
-                        reg = <103>;
-                        regulator-name = "5v0";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
-                        regulator-always-on;
-                };
+        reg_module_3v3_audio: regulator-module-3v3-audio {
+                compatible = "regulator-fixed";
+                regulator-name = "+V3.3_AUDIO_AVDD_S";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
         };
 
         sound {
@@ -519,3 +1028,12 @@
                 clock-names = "pll_a", "pll_a_out0", "mclk";
         };
 };
+
+&gpio {
+        lan-reset-n {
+                gpio-hog;
+                gpios = <TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>;
+                output-high;
+                line-name = "LAN_RESET#";
+        };
+};
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index a6781f653310..d2b553f76719 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -896,7 +896,7 @@
                 nvidia,elastic-limit = <16>;
                 nvidia,term-range-adj = <6>;
                 nvidia,xcvr-setup = <51>;
-                nvidia.xcvr-setup-use-fuses;
+                nvidia,xcvr-setup-use-fuses;
                 nvidia,xcvr-lsfslew = <1>;
                 nvidia,xcvr-lsrslew = <1>;
                 nvidia,xcvr-hsslew = <32>;
@@ -933,7 +933,7 @@
                 nvidia,elastic-limit = <16>;
                 nvidia,term-range-adj = <6>;
                 nvidia,xcvr-setup = <51>;
-                nvidia.xcvr-setup-use-fuses;
+                nvidia,xcvr-setup-use-fuses;
                 nvidia,xcvr-lsfslew = <2>;
                 nvidia,xcvr-lsrslew = <2>;
                 nvidia,xcvr-hsslew = <32>;
@@ -969,7 +969,7 @@
                 nvidia,elastic-limit = <16>;
                 nvidia,term-range-adj = <6>;
                 nvidia,xcvr-setup = <51>;
-                nvidia.xcvr-setup-use-fuses;
+                nvidia,xcvr-setup-use-fuses;
                 nvidia,xcvr-lsfslew = <2>;
                 nvidia,xcvr-lsrslew = <2>;
                 nvidia,xcvr-hsslew = <32>;
@@ -1013,5 +1013,9 @@
                              <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
                              <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-affinity = <&{/cpus/cpu@0}>,
+                                     <&{/cpus/cpu@1}>,
+                                     <&{/cpus/cpu@2}>,
+                                     <&{/cpus/cpu@3}>;
         };
 };
diff --git a/arch/arm/boot/dts/uniphier-ld4-ref.dts b/arch/arm/boot/dts/uniphier-ld4-ref.dts
index 21407e159bf7..3aaca10f6644 100644
--- a/arch/arm/boot/dts/uniphier-ld4-ref.dts
+++ b/arch/arm/boot/dts/uniphier-ld4-ref.dts
@@ -63,6 +63,10 @@
         status = "okay";
 };
 
+&sd {
+        status = "okay";
+};
+
 &usb0 {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi
index 37950ad2de7c..b73d594b6dcd 100644
--- a/arch/arm/boot/dts/uniphier-ld4.dtsi
+++ b/arch/arm/boot/dts/uniphier-ld4.dtsi
@@ -63,6 +63,17 @@
                         cache-level = <2>;
                 };
 
+                spi: spi@54006000 {
+                        compatible = "socionext,uniphier-scssi";
+                        status = "disabled";
+                        reg = <0x54006000 0x100>;
+                        interrupts = <0 39 4>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_spi0>;
+                        clocks = <&peri_clk 11>;
+                        resets = <&peri_rst 11>;
+                };
+
                 serial0: serial@54006800 {
                         compatible = "socionext,uniphier-uart";
                         status = "disabled";
@@ -224,6 +235,40 @@
                         };
                 };
 
+                sd: sdhc@5a400000 {
+                        compatible = "socionext,uniphier-sd-v2.91";
+                        status = "disabled";
+                        reg = <0x5a400000 0x200>;
+                        interrupts = <0 76 4>;
+                        pinctrl-names = "default", "uhs";
+                        pinctrl-0 = <&pinctrl_sd>;
+                        pinctrl-1 = <&pinctrl_sd_uhs>;
+                        clocks = <&mio_clk 0>;
+                        reset-names = "host", "bridge";
+                        resets = <&mio_rst 0>, <&mio_rst 3>;
+                        bus-width = <4>;
+                        cap-sd-highspeed;
+                        sd-uhs-sdr12;
+                        sd-uhs-sdr25;
+                        sd-uhs-sdr50;
+                };
+
+                emmc: sdhc@5a500000 {
+                        compatible = "socionext,uniphier-sd-v2.91";
+                        status = "disabled";
+                        reg = <0x5a500000 0x200>;
+                        interrupts = <0 78 4>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_emmc>;
+                        clocks = <&mio_clk 1>;
+                        reset-names = "host", "bridge", "hw";
+                        resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
+                        bus-width = <8>;
+                        cap-mmc-highspeed;
+                        cap-mmc-hw-reset;
+                        non-removable;
+                };
+
                 usb0: usb@5a800100 {
                         compatible = "socionext,uniphier-ehci", "generic-ehci";
                         status = "disabled";
@@ -347,7 +392,8 @@
                         interrupts = <0 65 4>;
                         pinctrl-names = "default";
                         pinctrl-0 = <&pinctrl_nand2cs>;
-                        clocks = <&sys_clk 2>;
+                        clock-names = "nand", "nand_x", "ecc";
+                        clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
                         resets = <&sys_rst 2>;
                 };
         };
diff --git a/arch/arm/boot/dts/uniphier-ld6b-ref.dts b/arch/arm/boot/dts/uniphier-ld6b-ref.dts
index a0a44a422e12..3d9080ee7aef 100644
--- a/arch/arm/boot/dts/uniphier-ld6b-ref.dts
+++ b/arch/arm/boot/dts/uniphier-ld6b-ref.dts
@@ -65,6 +65,10 @@
         status = "okay";
 };
 
+&sd {
+        status = "okay";
+};
+
 &eth {
         status = "okay";
         phy-handle = <&ethphy>;
@@ -76,6 +80,14 @@
         };
 };
 
+&usb0 {
+        status = "okay";
+};
+
+&usb1 {
+        status = "okay";
+};
+
 &nand {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/uniphier-pinctrl.dtsi b/arch/arm/boot/dts/uniphier-pinctrl.dtsi
index 51f0e69f49fd..1fee5ffbfb9c 100644
--- a/arch/arm/boot/dts/uniphier-pinctrl.dtsi
+++ b/arch/arm/boot/dts/uniphier-pinctrl.dtsi
@@ -121,11 +121,36 @@
                 function = "sd";
         };
 
+        pinctrl_sd_uhs: sd-uhs {
+                groups = "sd";
+                function = "sd";
+        };
+
         pinctrl_sd1: sd1 {
                 groups = "sd1";
                 function = "sd1";
         };
 
+        pinctrl_spi0: spi0 {
+                groups = "spi0";
+                function = "spi0";
+        };
+
+        pinctrl_spi1: spi1 {
+                groups = "spi1";
+                function = "spi1";
+        };
+
+        pinctrl_spi2: spi2 {
+                groups = "spi2";
+                function = "spi2";
+        };
+
+        pinctrl_spi3: spi3 {
+                groups = "spi3";
+                function = "spi3";
+        };
+
         pinctrl_system_bus: system-bus {
                 groups = "system_bus", "system_bus_cs1";
                 function = "system_bus";
diff --git a/arch/arm/boot/dts/uniphier-pro4-ace.dts b/arch/arm/boot/dts/uniphier-pro4-ace.dts
index db1b08935ae5..92cc48dd86d0 100644
--- a/arch/arm/boot/dts/uniphier-pro4-ace.dts
+++ b/arch/arm/boot/dts/uniphier-pro4-ace.dts
@@ -68,6 +68,10 @@
         status = "okay";
 };
 
+&sd {
+        status = "okay";
+};
+
 &usb2 {
         status = "okay";
 };
@@ -86,3 +90,11 @@
                 reg = <1>;
         };
 };
+
+&usb0 {
+        status = "okay";
+};
+
+&usb1 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/uniphier-pro4-ref.dts b/arch/arm/boot/dts/uniphier-pro4-ref.dts
index efb084983b82..28038b17bbb3 100644
--- a/arch/arm/boot/dts/uniphier-pro4-ref.dts
+++ b/arch/arm/boot/dts/uniphier-pro4-ref.dts
@@ -65,6 +65,10 @@
         status = "okay";
 };
 
+&sd {
+        status = "okay";
+};
+
 &usb2 {
         status = "okay";
 };
@@ -84,6 +88,14 @@
         };
 };
 
+&usb0 {
+        status = "okay";
+};
+
+&usb1 {
+        status = "okay";
+};
+
 &nand {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/uniphier-pro4-sanji.dts b/arch/arm/boot/dts/uniphier-pro4-sanji.dts
index dac4d6679a32..dda1a2f214a8 100644
--- a/arch/arm/boot/dts/uniphier-pro4-sanji.dts
+++ b/arch/arm/boot/dts/uniphier-pro4-sanji.dts
@@ -71,6 +71,10 @@
         status = "okay";
 };
 
+&emmc {
+        status = "okay";
+};
+
 &eth {
         status = "okay";
         phy-handle = <&ethphy>;
@@ -81,3 +85,11 @@
                 reg = <1>;
         };
 };
+
+&usb0 {
+        status = "okay";
+};
+
+&usb1 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi
index 49539f035219..0beb606cf3c8 100644
--- a/arch/arm/boot/dts/uniphier-pro4.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro4.dtsi
@@ -71,6 +71,17 @@
                         cache-level = <2>;
                 };
 
+                spi0: spi@54006000 {
+                        compatible = "socionext,uniphier-scssi";
+                        status = "disabled";
+                        reg = <0x54006000 0x100>;
+                        interrupts = <0 39 4>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_spi0>;
+                        clocks = <&peri_clk 11>;
+                        resets = <&peri_rst 11>;
+                };
+
                 serial0: serial@54006800 {
                         compatible = "socionext,uniphier-uart";
                         status = "disabled";
@@ -258,6 +269,54 @@
                         };
                 };
 
+                sd: sdhc@5a400000 {
+                        compatible = "socionext,uniphier-sd-v2.91";
+                        status = "disabled";
+                        reg = <0x5a400000 0x200>;
+                        interrupts = <0 76 4>;
+                        pinctrl-names = "default", "uhs";
+                        pinctrl-0 = <&pinctrl_sd>;
+                        pinctrl-1 = <&pinctrl_sd_uhs>;
+                        clocks = <&mio_clk 0>;
+                        reset-names = "host", "bridge";
+                        resets = <&mio_rst 0>, <&mio_rst 3>;
+                        bus-width = <4>;
+                        cap-sd-highspeed;
+                        sd-uhs-sdr12;
+                        sd-uhs-sdr25;
+                        sd-uhs-sdr50;
+                };
+
+                emmc: sdhc@5a500000 {
+                        compatible = "socionext,uniphier-sd-v2.91";
+                        status = "disabled";
+                        reg = <0x5a500000 0x200>;
+                        interrupts = <0 78 4>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_emmc>;
+                        clocks = <&mio_clk 1>;
+                        reset-names = "host", "bridge", "hw";
+                        resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
+                        bus-width = <8>;
+                        cap-mmc-highspeed;
+                        cap-mmc-hw-reset;
+                        non-removable;
+                };
+
+                sd1: sdhc@5a600000 {
+                        compatible = "socionext,uniphier-sd-v2.91";
+                        status = "disabled";
+                        reg = <0x5a600000 0x200>;
+                        interrupts = <0 85 4>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_sd1>;
+                        clocks = <&mio_clk 2>;
+                        reset-names = "host", "bridge";
+                        resets = <&mio_rst 2>, <&mio_rst 5>;
+                        bus-width = <4>;
+                        cap-sd-highspeed;
+                };
+
                 usb2: usb@5a800100 {
                         compatible = "socionext,uniphier-ehci", "generic-ehci";
                         status = "disabled";
@@ -269,6 +328,8 @@
                                  <&mio_clk 12>;
                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
                                  <&mio_rst 12>;
+                        phy-names = "usb";
+                        phys = <&usb_phy0>;
                         has-transaction-translator;
                 };
 
@@ -283,6 +344,8 @@
                                  <&mio_clk 13>;
                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
                                  <&mio_rst 13>;
+                        phy-names = "usb";
+                        phys = <&usb_phy1>;
                         has-transaction-translator;
                 };
 
@@ -294,6 +357,34 @@
                         pinctrl: pinctrl {
                                 compatible = "socionext,uniphier-pro4-pinctrl";
                         };
+
+                        usb-phy {
+                                compatible = "socionext,uniphier-pro4-usb2-phy";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                usb_phy0: phy@0 {
+                                        reg = <0>;
+                                        #phy-cells = <0>;
+                                };
+
+                                usb_phy1: phy@1 {
+                                        reg = <1>;
+                                        #phy-cells = <0>;
+                                };
+
+                                usb_phy2: phy@2 {
+                                        reg = <2>;
+                                        #phy-cells = <0>;
+                                        vbus-supply = <&usb0_vbus>;
+                                };
+
+                                usb_phy3: phy@3 {
+                                        reg = <3>;
+                                        #phy-cells = <0>;
+                                        vbus-supply = <&usb1_vbus>;
+                                };
+                        };
                 };
 
                 soc-glue@5f900000 {
@@ -386,6 +477,101 @@
                         };
                 };
 
+                usb0: usb@65a00000 {
+                        compatible = "socionext,uniphier-dwc3", "snps,dwc3";
+                        status = "disabled";
+                        reg = <0x65a00000 0xcd00>;
+                        interrupt-names = "host", "peripheral";
+                        interrupts = <0 134 4>, <0 135 4>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_usb0>;
+                        clock-names = "ref", "bus_early", "suspend";
+                        clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
+                        resets = <&usb0_rst 4>;
+                        phys = <&usb_phy2>, <&usb0_ssphy>;
+                        dr_mode = "host";
+                };
+
+                usb-glue@65b00000 {
+                        compatible = "socionext,uniphier-pro4-dwc3-glue",
+                                     "simple-mfd";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x65b00000 0x100>;
+
+                        usb0_vbus: regulator@0 {
+                                compatible = "socionext,uniphier-pro4-usb3-regulator";
+                                reg = <0 0x10>;
+                                clock-names = "gio", "link";
+                                clocks = <&sys_clk 12>, <&sys_clk 14>;
+                                reset-names = "gio", "link";
+                                resets = <&sys_rst 12>, <&sys_rst 14>;
+                        };
+
+                        usb0_ssphy: ss-phy@10 {
+                                compatible = "socionext,uniphier-pro4-usb3-ssphy";
+                                reg = <0x10 0x10>;
+                                #phy-cells = <0>;
+                                clock-names = "gio", "link";
+                                clocks = <&sys_clk 12>, <&sys_clk 14>;
+                                reset-names = "gio", "link";
+                                resets = <&sys_rst 12>, <&sys_rst 14>;
+                                vbus-supply = <&usb0_vbus>;
+                        };
+
+                        usb0_rst: reset@40 {
+                                compatible = "socionext,uniphier-pro4-usb3-reset";
+                                reg = <0x40 0x4>;
+                                #reset-cells = <1>;
+                                clock-names = "gio", "link";
+                                clocks = <&sys_clk 12>, <&sys_clk 14>;
+                                reset-names = "gio", "link";
+                                resets = <&sys_rst 12>, <&sys_rst 14>;
+                        };
+                };
+
+                usb1: usb@65c00000 {
+                        compatible = "socionext,uniphier-dwc3", "snps,dwc3";
+                        status = "disabled";
+                        reg = <0x65c00000 0xcd00>;
+                        interrupt-names = "host", "peripheral";
+                        interrupts = <0 137 4>, <0 138 4>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_usb1>;
+                        clock-names = "ref", "bus_early", "suspend";
+                        clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
+                        resets = <&usb1_rst 4>;
+                        phys = <&usb_phy3>;
+                        dr_mode = "host";
+                };
+
+                usb-glue@65d00000 {
+                        compatible = "socionext,uniphier-pro4-dwc3-glue",
+                                     "simple-mfd";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x65d00000 0x100>;
+
+                        usb1_vbus: regulator@0 {
+                                compatible = "socionext,uniphier-pro4-usb3-regulator";
+                                reg = <0 0x10>;
+                                clock-names = "gio", "link";
+                                clocks = <&sys_clk 12>, <&sys_clk 15>;
+                                reset-names = "gio", "link";
+                                resets = <&sys_rst 12>, <&sys_rst 15>;
+                        };
+
+                        usb1_rst: reset@40 {
+                                compatible = "socionext,uniphier-pro4-usb3-reset";
+                                reg = <0x40 0x4>;
+                                #reset-cells = <1>;
+                                clock-names = "gio", "link";
+                                clocks = <&sys_clk 12>, <&sys_clk 15>;
+                                reset-names = "gio", "link";
+                                resets = <&sys_rst 12>, <&sys_rst 15>;
+                        };
+                };
+
                 nand: nand@68000000 {
                         compatible = "socionext,uniphier-denali-nand-v5a";
                         status = "disabled";
@@ -394,7 +580,8 @@
                         interrupts = <0 65 4>;
                         pinctrl-names = "default";
                         pinctrl-0 = <&pinctrl_nand>;
-                        clocks = <&sys_clk 2>;
+                        clock-names = "nand", "nand_x", "ecc";
+                        clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
                         resets = <&sys_rst 2>;
                 };
         };
diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi
index 06c2cef91ec7..365738739412 100644
--- a/arch/arm/boot/dts/uniphier-pro5.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro5.dtsi
@@ -156,6 +156,28 @@
                         cache-level = <3>;
                 };
 
+                spi0: spi@54006000 {
+                        compatible = "socionext,uniphier-scssi";
+                        status = "disabled";
+                        reg = <0x54006000 0x100>;
+                        interrupts = <0 39 4>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_spi0>;
+                        clocks = <&peri_clk 11>;
+                        resets = <&peri_rst 11>;
+                };
+
+                spi1: spi@54006100 {
+                        compatible = "socionext,uniphier-scssi";
+                        status = "disabled";
+                        reg = <0x54006100 0x100>;
+                        interrupts = <0 216 4>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_spi1>;
+                        clocks = <&peri_clk 11>;
+                        resets = <&peri_rst 11>;
+                };
+
                 serial0: serial@54006800 {
                         compatible = "socionext,uniphier-uart";
                         status = "disabled";
@@ -439,9 +461,44 @@
                         interrupts = <0 65 4>;
                         pinctrl-names = "default";
                         pinctrl-0 = <&pinctrl_nand2cs>;
-                        clocks = <&sys_clk 2>;
+                        clock-names = "nand", "nand_x", "ecc";
+                        clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
                         resets = <&sys_rst 2>;
                 };
+
+                emmc: sdhc@68400000 {
+                        compatible = "socionext,uniphier-sd-v3.1";
+                        status = "disabled";
+                        reg = <0x68400000 0x800>;
+                        interrupts = <0 78 4>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_emmc>;
+                        clocks = <&sd_clk 1>;
+                        reset-names = "host", "hw";
+                        resets = <&sd_rst 1>, <&sd_rst 6>;
+                        bus-width = <8>;
+                        cap-mmc-highspeed;
+                        cap-mmc-hw-reset;
+                        non-removable;
+                };
+
+                sd: sdhc@68800000 {
+                        compatible = "socionext,uniphier-sd-v3.1";
+                        status = "disabled";
+                        reg = <0x68800000 0x800>;
+                        interrupts = <0 76 4>;
+                        pinctrl-names = "default", "uhs";
+                        pinctrl-0 = <&pinctrl_sd>;
+                        pinctrl-1 = <&pinctrl_sd_uhs>;
+                        clocks = <&sd_clk 0>;
+                        reset-names = "host";
+                        resets = <&sd_rst 0>;
+                        bus-width = <4>;
+                        cap-sd-highspeed;
+                        sd-uhs-sdr12;
+                        sd-uhs-sdr25;
+                        sd-uhs-sdr50;
+                };
         };
 };
 
diff --git a/arch/arm/boot/dts/uniphier-pxs2-gentil.dts b/arch/arm/boot/dts/uniphier-pxs2-gentil.dts
index bed26b8ed9a3..e27fd4f2a569 100644
--- a/arch/arm/boot/dts/uniphier-pxs2-gentil.dts
+++ b/arch/arm/boot/dts/uniphier-pxs2-gentil.dts
@@ -76,6 +76,10 @@
         };
 };
 
+&emmc {
+        status = "okay";
+};
+
 &eth {
         status = "okay";
         phy-handle = <&ethphy>;
@@ -86,3 +90,11 @@
                 reg = <1>;
         };
 };
+
+&usb0 {
+        status = "okay";
+};
+
+&usb1 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/uniphier-pxs2-vodka.dts b/arch/arm/boot/dts/uniphier-pxs2-vodka.dts
index b13d2d16ddad..23fe42b7408b 100644
--- a/arch/arm/boot/dts/uniphier-pxs2-vodka.dts
+++ b/arch/arm/boot/dts/uniphier-pxs2-vodka.dts
@@ -77,6 +77,10 @@
         status = "okay";
 };
 
+&emmc {
+        status = "okay";
+};
+
 &eth {
         status = "okay";
         phy-handle = <&ethphy>;
@@ -87,3 +91,7 @@
                 reg = <1>;
         };
 };
+
+&usb0 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi
index e2d1a22c5950..8d20e9548e39 100644
--- a/arch/arm/boot/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi
@@ -167,6 +167,28 @@
                         cache-level = <2>;
                 };
 
+                spi0: spi@54006000 {
+                        compatible = "socionext,uniphier-scssi";
+                        status = "disabled";
+                        reg = <0x54006000 0x100>;
+                        interrupts = <0 39 4>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_spi0>;
+                        clocks = <&peri_clk 11>;
+                        resets = <&peri_rst 11>;
+                };
+
+                spi1: spi@54006100 {
+                        compatible = "socionext,uniphier-scssi";
+                        status = "disabled";
+                        reg = <0x54006100 0x100>;
+                        interrupts = <0 216 4>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_spi1>;
+                        clocks = <&peri_clk 11>;
+                        resets = <&peri_rst 11>;
+                };
+
                 serial0: serial@54006800 {
                         compatible = "socionext,uniphier-uart";
                         status = "disabled";
@@ -422,6 +444,40 @@
                         };
                 };
 
+                emmc: sdhc@5a000000 {
+                        compatible = "socionext,uniphier-sd-v3.1.1";
+                        status = "disabled";
+                        reg = <0x5a000000 0x800>;
+                        interrupts = <0 78 4>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_emmc>;
+                        clocks = <&sd_clk 1>;
+                        reset-names = "host", "hw";
+                        resets = <&sd_rst 1>, <&sd_rst 6>;
+                        bus-width = <8>;
+                        cap-mmc-highspeed;
+                        cap-mmc-hw-reset;
+                        non-removable;
+                };
+
+                sd: sdhc@5a400000 {
+                        compatible = "socionext,uniphier-sd-v3.1.1";
+                        status = "disabled";
+                        reg = <0x5a400000 0x800>;
+                        interrupts = <0 76 4>;
+                        pinctrl-names = "default", "uhs";
+                        pinctrl-0 = <&pinctrl_sd>;
+                        pinctrl-1 = <&pinctrl_sd_uhs>;
+                        clocks = <&sd_clk 0>;
+                        reset-names = "host";
+                        resets = <&sd_rst 0>;
+                        bus-width = <4>;
+                        cap-sd-highspeed;
+                        sd-uhs-sdr12;
+                        sd-uhs-sdr25;
+                        sd-uhs-sdr50;
+                };
+
                 soc_glue: soc-glue@5f800000 {
                         compatible = "socionext,uniphier-pxs2-soc-glue",
                                      "simple-mfd", "syscon";
@@ -523,6 +579,186 @@
                         };
                 };
 
+                usb0: usb@65a00000 {
+                        compatible = "socionext,uniphier-dwc3", "snps,dwc3";
+                        status = "disabled";
+                        reg = <0x65a00000 0xcd00>;
+                        interrupt-names = "host", "peripheral";
+                        interrupts = <0 134 4>, <0 135 4>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
+                        clock-names = "ref", "bus_early", "suspend";
+                        clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>;
+                        resets = <&usb0_rst 15>;
+                        phys = <&usb0_hsphy0>, <&usb0_hsphy1>,
+                               <&usb0_ssphy0>, <&usb0_ssphy1>;
+                        dr_mode = "host";
+                };
+
+                usb-glue@65b00000 {
+                        compatible = "socionext,uniphier-pxs2-dwc3-glue",
+                                     "simple-mfd";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x65b00000 0x400>;
+
+                        usb0_rst: reset@0 {
+                                compatible = "socionext,uniphier-pxs2-usb3-reset";
+                                reg = <0x0 0x4>;
+                                #reset-cells = <1>;
+                                clock-names = "link";
+                                clocks = <&sys_clk 14>;
+                                reset-names = "link";
+                                resets = <&sys_rst 14>;
+                        };
+
+                        usb0_vbus0: regulator@100 {
+                                compatible = "socionext,uniphier-pxs2-usb3-regulator";
+                                reg = <0x100 0x10>;
+                                clock-names = "link";
+                                clocks = <&sys_clk 14>;
+                                reset-names = "link";
+                                resets = <&sys_rst 14>;
+                        };
+
+                        usb0_vbus1: regulator@110 {
+                                compatible = "socionext,uniphier-pxs2-usb3-regulator";
+                                reg = <0x110 0x10>;
+                                clock-names = "link";
+                                clocks = <&sys_clk 14>;
+                                reset-names = "link";
+                                resets = <&sys_rst 14>;
+                        };
+
+                        usb0_hsphy0: hs-phy@200 {
+                                compatible = "socionext,uniphier-pxs2-usb3-hsphy";
+                                reg = <0x200 0x10>;
+                                #phy-cells = <0>;
+                                clock-names = "link", "phy";
+                                clocks = <&sys_clk 14>, <&sys_clk 16>;
+                                reset-names = "link", "phy";
+                                resets = <&sys_rst 14>, <&sys_rst 16>;
+                                vbus-supply = <&usb0_vbus0>;
+                        };
+
+                        usb0_hsphy1: hs-phy@210 {
+                                compatible = "socionext,uniphier-pxs2-usb3-hsphy";
+                                reg = <0x210 0x10>;
+                                #phy-cells = <0>;
+                                clock-names = "link", "phy";
+                                clocks = <&sys_clk 14>, <&sys_clk 16>;
+                                reset-names = "link", "phy";
+                                resets = <&sys_rst 14>, <&sys_rst 16>;
+                                vbus-supply = <&usb0_vbus1>;
+                        };
+
+                        usb0_ssphy0: ss-phy@300 {
+                                compatible = "socionext,uniphier-pxs2-usb3-ssphy";
+                                reg = <0x300 0x10>;
+                                #phy-cells = <0>;
+                                clock-names = "link", "phy";
+                                clocks = <&sys_clk 14>, <&sys_clk 17>;
+                                reset-names = "link", "phy";
+                                resets = <&sys_rst 14>, <&sys_rst 17>;
+                                vbus-supply = <&usb0_vbus0>;
+                        };
+
+                        usb0_ssphy1: ss-phy@310 {
+                                compatible = "socionext,uniphier-pxs2-usb3-ssphy";
+                                reg = <0x310 0x10>;
+                                #phy-cells = <0>;
+                                clock-names = "link", "phy";
+                                clocks = <&sys_clk 14>, <&sys_clk 18>;
+                                reset-names = "link", "phy";
+                                resets = <&sys_rst 14>, <&sys_rst 18>;
+                                vbus-supply = <&usb0_vbus1>;
+                        };
+                };
+
+                usb1: usb@65c00000 {
+                        compatible = "socionext,uniphier-dwc3", "snps,dwc3";
+                        status = "disabled";
+                        reg = <0x65c00000 0xcd00>;
+                        interrupt-names = "host", "peripheral";
+                        interrupts = <0 137 4>, <0 138 4>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
+                        clock-names = "ref", "bus_early", "suspend";
+                        clocks = <&sys_clk 15>, <&sys_clk 15>, <&sys_clk 15>;
+                        resets = <&usb1_rst 15>;
+                        phys = <&usb1_hsphy0>, <&usb1_hsphy1>, <&usb1_ssphy0>;
+                        dr_mode = "host";
+                };
+
+                usb-glue@65d00000 {
+                        compatible = "socionext,uniphier-pxs2-dwc3-glue",
+                                     "simple-mfd";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x65d00000 0x400>;
+
+                        usb1_rst: reset@0 {
+                                compatible = "socionext,uniphier-pxs2-usb3-reset";
+                                reg = <0x0 0x4>;
+                                #reset-cells = <1>;
+                                clock-names = "link";
+                                clocks = <&sys_clk 15>;
+                                reset-names = "link";
+                                resets = <&sys_rst 15>;
+                        };
+
+                        usb1_vbus0: regulator@100 {
+                                compatible = "socionext,uniphier-pxs2-usb3-regulator";
+                                reg = <0x100 0x10>;
+                                clock-names = "link";
+                                clocks = <&sys_clk 15>;
+                                reset-names = "link";
+                                resets = <&sys_rst 15>;
+                        };
+
+                        usb1_vbus1: regulator@110 {
+                                compatible = "socionext,uniphier-pxs2-usb3-regulator";
+                                reg = <0x110 0x10>;
+                                clock-names = "link";
+                                clocks = <&sys_clk 15>;
+                                reset-names = "link";
+                                resets = <&sys_rst 15>;
+                        };
+
+                        usb1_hsphy0: hs-phy@200 {
+                                compatible = "socionext,uniphier-pxs2-usb3-hsphy";
+                                reg = <0x200 0x10>;
+                                #phy-cells = <0>;
+                                clock-names = "link", "phy";
+                                clocks = <&sys_clk 15>, <&sys_clk 20>;
+                                reset-names = "link", "phy";
+                                resets = <&sys_rst 15>, <&sys_rst 20>;
+                                vbus-supply = <&usb1_vbus0>;
+                        };
+
+                        usb1_hsphy1: hs-phy@210 {
+                                compatible = "socionext,uniphier-pxs2-usb3-hsphy";
+                                reg = <0x210 0x10>;
+                                #phy-cells = <0>;
+                                clock-names = "link", "phy";
+                                clocks = <&sys_clk 15>, <&sys_clk 20>;
+                                reset-names = "link", "phy";
+                                resets = <&sys_rst 15>, <&sys_rst 20>;
+                                vbus-supply = <&usb1_vbus1>;
+                        };
+
+                        usb1_ssphy0: ss-phy@300 {
+                                compatible = "socionext,uniphier-pxs2-usb3-ssphy";
+                                reg = <0x300 0x10>;
+                                #phy-cells = <0>;
+                                clock-names = "link", "phy";
+                                clocks = <&sys_clk 15>, <&sys_clk 21>;
+                                reset-names = "link", "phy";
+                                resets = <&sys_rst 15>, <&sys_rst 21>;
+                                vbus-supply = <&usb1_vbus0>;
+                        };
+                };
+
                 nand: nand@68000000 {
                         compatible = "socionext,uniphier-denali-nand-v5b";
                         status = "disabled";
@@ -531,7 +767,8 @@
                         interrupts = <0 65 4>;
                         pinctrl-names = "default";
                         pinctrl-0 = <&pinctrl_nand2cs>;
-                        clocks = <&sys_clk 2>;
+                        clock-names = "nand", "nand_x", "ecc";
+                        clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
                         resets = <&sys_rst 2>;
                 };
         };
diff --git a/arch/arm/boot/dts/uniphier-sld8-ref.dts b/arch/arm/boot/dts/uniphier-sld8-ref.dts
index fe386fa2ea4b..01bf94c6b93a 100644
--- a/arch/arm/boot/dts/uniphier-sld8-ref.dts
+++ b/arch/arm/boot/dts/uniphier-sld8-ref.dts
@@ -63,6 +63,10 @@
         status = "okay";
 };
 
+&sd {
+        status = "okay";
+};
+
 &usb0 {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi
index e9b9b4f3c558..f7fcf6b45995 100644
--- a/arch/arm/boot/dts/uniphier-sld8.dtsi
+++ b/arch/arm/boot/dts/uniphier-sld8.dtsi
@@ -63,6 +63,17 @@
                         cache-level = <2>;
                 };
 
+                spi: spi@54006000 {
+                        compatible = "socionext,uniphier-scssi";
+                        status = "disabled";
+                        reg = <0x54006000 0x100>;
+                        interrupts = <0 39 4>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_spi0>;
+                        clocks = <&peri_clk 11>;
+                        resets = <&peri_rst 11>;
+                };
+
                 serial0: serial@54006800 {
                         compatible = "socionext,uniphier-uart";
                         status = "disabled";
@@ -228,6 +239,40 @@
                         };
                 };
 
+                sd: sdhc@5a400000 {
+                        compatible = "socionext,uniphier-sd-v2.91";
+                        status = "disabled";
+                        reg = <0x5a400000 0x200>;
+                        interrupts = <0 76 4>;
+                        pinctrl-names = "default", "uhs";
+                        pinctrl-0 = <&pinctrl_sd>;
+                        pinctrl-1 = <&pinctrl_sd_uhs>;
+                        clocks = <&mio_clk 0>;
+                        reset-names = "host", "bridge";
+                        resets = <&mio_rst 0>, <&mio_rst 3>;
+                        bus-width = <4>;
+                        cap-sd-highspeed;
+                        sd-uhs-sdr12;
+                        sd-uhs-sdr25;
+                        sd-uhs-sdr50;
+                };
+
+                emmc: sdhc@5a500000 {
+                        compatible = "socionext,uniphier-sd-v2.91";
+                        status = "disabled";
+                        reg = <0x5a500000 0x200>;
+                        interrupts = <0 78 4>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_emmc>;
+                        clocks = <&mio_clk 1>;
+                        reset-names = "host", "bridge", "hw";
+                        resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
+                        bus-width = <8>;
+                        cap-mmc-highspeed;
+                        cap-mmc-hw-reset;
+                        non-removable;
+                };
+
                 usb0: usb@5a800100 {
                         compatible = "socionext,uniphier-ehci", "generic-ehci";
                         status = "disabled";
@@ -351,7 +396,8 @@
                         interrupts = <0 65 4>;
                         pinctrl-names = "default";
                         pinctrl-0 = <&pinctrl_nand2cs>;
-                        clocks = <&sys_clk 2>;
+                        clock-names = "nand", "nand_x", "ecc";
+                        clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
                         resets = <&sys_rst 2>;
                 };
         };
diff --git a/arch/arm/boot/dts/versatile-ab.dts b/arch/arm/boot/dts/versatile-ab.dts
index 5f61d3609027..6f4f60ba5429 100644
--- a/arch/arm/boot/dts/versatile-ab.dts
+++ b/arch/arm/boot/dts/versatile-ab.dts
@@ -373,7 +373,7 @@
                         clock-names = "apb_pclk";
                 };
 
-                ssp@101f4000 {
+                spi@101f4000 {
                         compatible = "arm,pl022", "arm,primecell";
                         reg = <0x101f4000 0x1000>;
                         interrupts = <11>;
diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi
index bbff0115e2fb..76a0949df4a8 100644
--- a/arch/arm/boot/dts/vf500.dtsi
+++ b/arch/arm/boot/dts/vf500.dtsi
@@ -1,43 +1,6 @@
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License
- *     version 2 as published by the Free Software Foundation.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Copyright 2013 Freescale Semiconductor, Inc.
 
 #include "vfxxx.dtsi"
 #include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts
index 6be7a828ae64..59fceea8805d 100644
--- a/arch/arm/boot/dts/vf610-twr.dts
+++ b/arch/arm/boot/dts/vf610-twr.dts
@@ -1,43 +1,6 @@
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License
- *     version 2 as published by the Free Software Foundation.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Copyright 2013 Freescale Semiconductor, Inc.
 
 /dts-v1/;
 #include "vf610.dtsi"
diff --git a/arch/arm/boot/dts/vf610-zii-cfu1.dts b/arch/arm/boot/dts/vf610-zii-cfu1.dts
index 37777cf22e67..b76c3d0413df 100644
--- a/arch/arm/boot/dts/vf610-zii-cfu1.dts
+++ b/arch/arm/boot/dts/vf610-zii-cfu1.dts
@@ -66,6 +66,15 @@
                  regulator-min-microvolt = <3300000>;
                  regulator-max-microvolt = <3300000>;
         };
+
+        sff: sfp {
+                compatible = "sff,sff";
+                pinctrl-0 = <&pinctrl_optical>;
+                pinctrl-names = "default";
+                i2c-bus = <&i2c0>;
+                los-gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>;
+                tx-disable-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+        };
 };
 
 &adc0 {
@@ -113,6 +122,8 @@
         non-removable;
         no-1-8-v;
         keep-power-in-suspend;
+        no-sdio;
+        no-sd;
         status = "okay";
 };
 
@@ -120,6 +131,7 @@
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_esdhc1>;
         bus-width = <4>;
+        no-sdio;
         status = "okay";
 };
 
@@ -170,6 +182,14 @@
                                         label = "eth_cu_1000_3";
                                 };
 
+                                port@5 {
+                                        reg = <5>;
+                                        label = "eth_fc_1000_1";
+                                        phy-mode = "1000base-x";
+                                        managed = "in-band-status";
+                                        sfp = <&sff>;
+                                };
+
                                 port@6 {
                                         reg = <6>;
                                         label = "cpu";
@@ -289,6 +309,16 @@
                 >;
         };
 
+        pinctrl_optical: optical-grp {
+                fsl,pins = <
+                /* SFF SD input */
+                VF610_PAD_PTE27__GPIO_132       0x3061
+
+                /* SFF Transmit disable output */
+                VF610_PAD_PTE13__GPIO_118       0x3043
+                >;
+        };
+
         pinctrl_switch: switch-grp {
                 fsl,pins = <
                         VF610_PAD_PTB28__GPIO_98                0x3061
diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts
index 0b1e94c6f25b..6f4a5602cefd 100644
--- a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts
+++ b/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts
@@ -200,6 +200,13 @@
                                                 phy-handle = <&switch1phy4>;
                                         };
 
+                                        port@9 {
+                                                reg = <9>;
+                                                label = "sff2";
+                                                phy-mode = "sgmii";
+                                                managed = "in-band-status";
+                                                sfp = <&sff2>;
+                                        };
 
                                         switch1port10: port@10 {
                                                 reg = <10>;
@@ -245,6 +252,22 @@
                         #size-cells = <0>;
                 };
         };
+
+        sff2: sff2 {
+                /* lower */
+                compatible = "sff,sff";
+                i2c-bus = <&sff2_i2c>;
+                los-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
+                tx-disable-gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>;
+        };
+
+        sff3: sff3 {
+                /* upper */
+                compatible = "sff,sff";
+                i2c-bus = <&sff3_i2c>;
+                los-gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
+                tx-disable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
+        };
 };
 
 &dspi0 {
@@ -329,13 +352,6 @@
                 interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
                 gpio-controller;
                 interrupt-controller;
-
-                enet_swr_en {
-                        gpio-hog;
-                        gpios = <0 GPIO_ACTIVE_HIGH>;
-                        output-high;
-                        line-name = "enet-swr-en";
-                };
         };
 
         /*
@@ -378,26 +394,16 @@
                         reg = <0>;
                 };
 
-                i2c@1 {
+                sff2_i2c: i2c@1 {
                         #address-cells = <1>;
                         #size-cells = <0>;
                         reg = <1>;
-
-                        sfp2: at24c04@50 {
-                                compatible = "atmel,24c02";
-                                reg = <0x50>;
-                        };
                 };
 
-                i2c@2 {
+                sff3_i2c: i2c@2 {
                         #address-cells = <1>;
                         #size-cells = <0>;
                         reg = <2>;
-
-                        sfp3: at24c04@50 {
-                                compatible = "atmel,24c02";
-                                reg = <0x50>;
-                        };
                 };
 
                 i2c@3 {
diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi
index 80fef182c672..7fd39817f8ab 100644
--- a/arch/arm/boot/dts/vf610.dtsi
+++ b/arch/arm/boot/dts/vf610.dtsi
@@ -1,43 +1,7 @@
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License
- *     version 2 as published by the Free Software Foundation.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Copyright 2013 Freescale Semiconductor, Inc.
+
 
 #include "vf500.dtsi"
 
diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
index d392794d9c13..028e0ec30e0c 100644
--- a/arch/arm/boot/dts/vfxxx.dtsi
+++ b/arch/arm/boot/dts/vfxxx.dtsi
@@ -1,43 +1,6 @@
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License
- *     version 2 as published by the Free Software Foundation.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Copyright 2013 Freescale Semiconductor, Inc.
 
 #include "vf610-pinfunc.h"
 #include <dt-bindings/clock/vf610-clock.h>
@@ -190,7 +153,7 @@
                                 status = "disabled";
                         };
 
-                        dspi0: dspi0@4002c000 {
+                        dspi0: spi@4002c000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 compatible = "fsl,vf610-dspi";
@@ -205,7 +168,7 @@
                                 status = "disabled";
                         };
 
-                        dspi1: dspi1@4002d000 {
+                        dspi1: spi@4002d000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 compatible = "fsl,vf610-dspi";
@@ -339,7 +302,7 @@
                                 status = "disabled";
                         };
 
-                        qspi0: quadspi@40044000 {
+                        qspi0: spi@40044000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 compatible = "fsl,vf610-qspi";
@@ -569,7 +532,7 @@
                                 status = "disabled";
                         };
 
-                        dspi2: dspi2@400ac000 {
+                        dspi2: spi@400ac000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 compatible = "fsl,vf610-dspi";
@@ -584,7 +547,7 @@
                                 status = "disabled";
                         };
 
-                        dspi3: dspi3@400ad000 {
+                        dspi3: spi@400ad000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 compatible = "fsl,vf610-dspi";
@@ -665,7 +628,7 @@
                                 status = "disabled";
                         };
 
-                        qspi1: quadspi@400c4000 {
+                        qspi1: spi@400c4000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 compatible = "fsl,vf610-qspi";
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
index cc5a3dc2b4a0..27cd6cb52f1b 100644
--- a/arch/arm/boot/dts/zynq-zc702.dts
+++ b/arch/arm/boot/dts/zynq-zc702.dts
@@ -174,17 +174,17 @@
                         #address-cells = <1>;
                         #size-cells = <0>;
                         reg = <7>;
-                        hwmon@52 {
+                        hwmon@34 {
                                 compatible = "ti,ucd9248";
-                                reg = <52>;
+                                reg = <0x34>;
                         };
-                        hwmon@53 {
+                        hwmon@35 {
                                 compatible = "ti,ucd9248";
-                                reg = <53>;
+                                reg = <0x35>;
                         };
-                        hwmon@54 {
+                        hwmon@36 {
                                 compatible = "ti,ucd9248";
-                                reg = <54>;
+                                reg = <0x36>;
                         };
                 };
         };
diff --git a/arch/arm/boot/dts/zynq-zc770-xm010.dts b/arch/arm/boot/dts/zynq-zc770-xm010.dts
index 0e1bfdd3421f..0dd352289a45 100644
--- a/arch/arm/boot/dts/zynq-zc770-xm010.dts
+++ b/arch/arm/boot/dts/zynq-zc770-xm010.dts
@@ -68,7 +68,7 @@
         status = "okay";
         num-cs = <4>;
         is-decoded-cs = <0>;
-        flash@0 {
+        flash@1 {
                 compatible = "sst25wf080", "jedec,spi-nor";
                 reg = <1>;
                 spi-max-frequency = <1000000>;
diff --git a/arch/arm/boot/dts/zynq-zc770-xm013.dts b/arch/arm/boot/dts/zynq-zc770-xm013.dts
index 651913f1afa2..4ae2c85df3a0 100644
--- a/arch/arm/boot/dts/zynq-zc770-xm013.dts
+++ b/arch/arm/boot/dts/zynq-zc770-xm013.dts
@@ -62,7 +62,7 @@
         status = "okay";
         num-cs = <4>;
         is-decoded-cs = <0>;
-        eeprom: eeprom@0 {
+        eeprom: eeprom@2 {
                 at25,byte-len = <8192>;
                 at25,addr-mode = <2>;
                 at25,page-size = <32>;
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index dcd21bb95e3b..f96730cce6e8 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -110,6 +110,7 @@ void exynos_firmware_init(void);
 #define EXYNOS_SLEEP_MAGIC      0x00000bad
 #define EXYNOS_AFTR_MAGIC       0xfcba0d10
 
+bool __init exynos_secure_firmware_available(void);
 void exynos_set_boot_flag(unsigned int cpu, unsigned int mode);
 void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode);
 
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index be1f20fe28f4..d602e3bf3f96 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -185,7 +185,7 @@ static void exynos_l2_configure(const struct l2x0_regs *regs)
         exynos_smc(SMC_CMD_L2X0SETUP2, regs->pwr_ctrl, regs->aux_ctrl, 0);
 }
 
-void __init exynos_firmware_init(void)
+bool __init exynos_secure_firmware_available(void)
 {
         struct device_node *nd;
         const __be32 *addr;
@@ -193,14 +193,22 @@ void __init exynos_firmware_init(void)
         nd = of_find_compatible_node(NULL, NULL,
                                         "samsung,secure-firmware");
         if (!nd)
-                return;
+                return false;
 
         addr = of_get_address(nd, 0, NULL, NULL);
         if (!addr) {
                 pr_err("%s: No address specified.\n", __func__);
-                return;
+                return false;
         }
 
+        return true;
+}
+
+void __init exynos_firmware_init(void)
+{
+        if (!exynos_secure_firmware_available())
+                return;
+
         pr_info("Running under secure firmware.\n");
 
         register_firmware_ops(&exynos_firmware_ops);
diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index 7ead3acd6fa4..bb8e3985acdb 100644
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@ -59,10 +59,15 @@ struct exynos_pm_data {
         int (*cpu_suspend)(unsigned long);
 };
 
-static const struct exynos_pm_data *pm_data __ro_after_init;
+/* Used only on Exynos542x/5800 */
+struct exynos_pm_state {
+        int cpu_state;
+        unsigned int pmu_spare3;
+        void __iomem *sysram_base;
+};
 
-static int exynos5420_cpu_state;
-static unsigned int exynos_pmu_spare3;
+static const struct exynos_pm_data *pm_data __ro_after_init;
+static struct exynos_pm_state pm_state;
 
 /*
  * GIC wake-up support
@@ -257,7 +262,7 @@ static int exynos5420_cpu_suspend(unsigned long arg)
         unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
         unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
 
-        writel_relaxed(0x0, sysram_base_addr + EXYNOS5420_CPU_STATE);
+        writel_relaxed(0x0, pm_state.sysram_base + EXYNOS5420_CPU_STATE);
 
         if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) {
                 mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume);
@@ -321,7 +326,7 @@ static void exynos5420_pm_prepare(void)
         /* Set wake-up mask registers */
         exynos_pm_set_wakeup_mask();
 
-        exynos_pmu_spare3 = pmu_raw_readl(S5P_PMU_SPARE3);
+        pm_state.pmu_spare3 = pmu_raw_readl(S5P_PMU_SPARE3);
         /*
          * The cpu state needs to be saved and restored so that the
          * secondary CPUs will enter low power start. Though the U-Boot
@@ -329,8 +334,8 @@ static void exynos5420_pm_prepare(void)
          * needs to restore it back in case, the primary cpu fails to
          * suspend for any reason.
          */
-        exynos5420_cpu_state = readl_relaxed(sysram_base_addr +
-                                             EXYNOS5420_CPU_STATE);
+        pm_state.cpu_state = readl_relaxed(pm_state.sysram_base +
+                                           EXYNOS5420_CPU_STATE);
 
         exynos_pm_enter_sleep_mode();
 
@@ -448,8 +453,8 @@ static void exynos5420_pm_resume(void)
                        EXYNOS5_ARM_CORE0_SYS_PWR_REG);
 
         /* Restore the sysram cpu state register */
-        writel_relaxed(exynos5420_cpu_state,
-                       sysram_base_addr + EXYNOS5420_CPU_STATE);
+        writel_relaxed(pm_state.cpu_state,
+                       pm_state.sysram_base + EXYNOS5420_CPU_STATE);
 
         pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL,
                         S5P_CENTRAL_SEQ_OPTION);
@@ -457,7 +462,7 @@ static void exynos5420_pm_resume(void)
         if (exynos_pm_central_resume())
                 goto early_wakeup;
 
-        pmu_raw_writel(exynos_pmu_spare3, S5P_PMU_SPARE3);
+        pmu_raw_writel(pm_state.pmu_spare3, S5P_PMU_SPARE3);
 
 early_wakeup:
 
@@ -654,4 +659,13 @@ void __init exynos_pm_init(void)
 
         register_syscore_ops(&exynos_pm_syscore_ops);
         suspend_set_ops(&exynos_suspend_ops);
+
+        /*
+         * Applicable as of now only to Exynos542x. If booted under secure
+         * firmware, the non-secure region of sysram should be used.
+         */
+        if (exynos_secure_firmware_available())
+                pm_state.sysram_base = sysram_ns_base_addr;
+        else
+                pm_state.sysram_base = sysram_base_addr;
 }
diff --git a/arch/arm/mach-s3c24xx/mach-gta02.c b/arch/arm/mach-s3c24xx/mach-gta02.c
index 9d5595c4ad99..594901f3b8e5 100644
--- a/arch/arm/mach-s3c24xx/mach-gta02.c
+++ b/arch/arm/mach-s3c24xx/mach-gta02.c
@@ -219,17 +219,6 @@ static void gta02_udc_vbus_draw(unsigned int ma)
 #define gta02_udc_vbus_draw             NULL
 #endif
 
-/*
- * This is called when pc50633 is probed, unfortunately quite late in the
- * day since it is an I2C bus device. Here we can belatedly define some
- * platform devices with the advantage that we can mark the pcf50633 as the
- * parent. This makes them get suspended and resumed with their parent
- * the pcf50633 still around.
- */
-
-static void gta02_pmu_attach_child_devices(struct pcf50633 *pcf);
-
-
 static char *gta02_batteries[] = {
         "battery",
 };
@@ -355,7 +344,6 @@ static struct pcf50633_platform_data gta02_pcf_pdata = {
                 },
 
         },
-        .probe_done = gta02_pmu_attach_child_devices,
         .mbc_event_callback = gta02_pmu_event_callback,
 };
 
@@ -512,36 +500,6 @@ static struct platform_device *gta02_devices[] __initdata = {
         &s3c_device_ts,
 };
 
-/* These guys DO need to be children of PMU. */
-
-static struct platform_device *gta02_devices_pmu_children[] = {
-};
-
-
-/*
- * This is called when pc50633 is probed, quite late in the day since it is an
- * I2C bus device.  Here we can define platform devices with the advantage that
- * we can mark the pcf50633 as the parent.  This makes them get suspended and
- * resumed with their parent the pcf50633 still around.  All devices whose
- * operation depends on something from pcf50633 must have this relationship
- * made explicit like this, or suspend and resume will become an unreliable
- * hellworld.
- */
-
-static void gta02_pmu_attach_child_devices(struct pcf50633 *pcf)
-{
-        int n;
-
-        /* Grab a copy of the now probed PMU pointer. */
-        gta02_pcf = pcf;
-
-        for (n = 0; n < ARRAY_SIZE(gta02_devices_pmu_children); n++)
-                gta02_devices_pmu_children[n]->dev.parent = pcf->dev;
-
-        platform_add_devices(gta02_devices_pmu_children,
-                             ARRAY_SIZE(gta02_devices_pmu_children));
-}
-
 static void gta02_poweroff(void)
 {
         pcf50633_reg_set_bit_mask(gta02_pcf, PCF50633_REG_OOCSHDWN, 1, 1);
diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c
index f9fc1f8d2b28..50d67d760efd 100644
--- a/arch/arm/mach-s3c24xx/mach-mini2440.c
+++ b/arch/arm/mach-s3c24xx/mach-mini2440.c
@@ -64,31 +64,31 @@ static struct map_desc mini2440_iodesc[] __initdata = {
 };
 
 #define UCON S3C2410_UCON_DEFAULT
-#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
-#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
+#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
+#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
 
 
 static struct s3c2410_uartcfg mini2440_uartcfgs[] __initdata = {
         [0] = {
-                .hwport      = 0,
-                .flags       = 0,
-                .ucon        = UCON,
-                .ulcon       = ULCON,
-                .ufcon       = UFCON,
+                .hwport         = 0,
+                .flags          = 0,
+                .ucon           = UCON,
+                .ulcon          = ULCON,
+                .ufcon          = UFCON,
         },
         [1] = {
-                .hwport      = 1,
-                .flags       = 0,
-                .ucon        = UCON,
-                .ulcon       = ULCON,
-                .ufcon       = UFCON,
+                .hwport         = 1,
+                .flags          = 0,
+                .ucon           = UCON,
+                .ulcon          = ULCON,
+                .ufcon          = UFCON,
         },
         [2] = {
-                .hwport      = 2,
-                .flags       = 0,
-                .ucon        = UCON,
-                .ulcon       = ULCON,
-                .ufcon       = UFCON,
+                .hwport         = 2,
+                .flags          = 0,
+                .ucon           = UCON,
+                .ulcon          = ULCON,
+                .ufcon          = UFCON,
         },
 };
 
@@ -104,8 +104,8 @@ static struct s3c2410_udc_mach_info mini2440_udc_cfg __initdata = {
 /*
  * This macro simplifies the table bellow
  */
-#define _LCD_DECLARE(_clock,_xres,margin_left,margin_right,hsync, \
-                        _yres,margin_top,margin_bottom,vsync, refresh) \
+#define _LCD_DECLARE(_clock, _xres, margin_left, margin_right, hsync, \
+                        _yres, margin_top, margin_bottom, vsync, refresh) \
         .width = _xres, \
         .xres = _xres, \
         .height = _yres, \
@@ -128,7 +128,7 @@ static struct s3c2410fb_display mini2440_lcd_cfg[] __initdata = {
         [0] = { /* mini2440 + 3.5" TFT + touchscreen */
                 _LCD_DECLARE(
                         7,                      /* The 3.5 is quite fast */
-                        240, 21, 38, 6,         /* x timing */
+                        240, 21, 38, 6,         /* x timing */
                         320, 4, 4, 2,           /* y timing */
                         60),                    /* refresh rate */
                 .lcdcon5        = (S3C2410_LCDCON5_FRM565 |
@@ -140,7 +140,7 @@ static struct s3c2410fb_display mini2440_lcd_cfg[] __initdata = {
         [1] = { /* mini2440 + 7" TFT + touchscreen */
                 _LCD_DECLARE(
                         10,                     /* the 7" runs slower */
-                        800, 40, 40, 48,        /* x timing */
+                        800, 40, 40, 48,        /* x timing */
                         480, 29, 3, 3,          /* y timing */
                         50),                    /* refresh rate */
                 .lcdcon5        = (S3C2410_LCDCON5_FRM565 |
@@ -148,7 +148,7 @@ static struct s3c2410fb_display mini2440_lcd_cfg[] __initdata = {
                                    S3C2410_LCDCON5_INVVFRAME |
                                    S3C2410_LCDCON5_PWREN),
         },
-        /* The VGA shield can outout at several resolutions. All share 
+        /* The VGA shield can outout at several resolutions. All share
          * the same timings, however, anything smaller than 1024x768
          * will only be displayed in the top left corner of a 1024x768
          * XGA output unless you add optional dip switches to the shield.
@@ -158,9 +158,10 @@ static struct s3c2410fb_display mini2440_lcd_cfg[] __initdata = {
                 _LCD_DECLARE(
                         10,
                         1024, 1, 2, 2,          /* y timing */
-                        768, 200, 16, 16,       /* x timing */
+                        768, 200, 16, 16,       /* x timing */
                         24),    /* refresh rate, maximum stable,
-                                 tested with the FPGA shield */
+                                 * tested with the FPGA shield
+                                 */
                 .lcdcon5        = (S3C2410_LCDCON5_FRM565 |
                                    S3C2410_LCDCON5_HWSWP),
         },
@@ -196,7 +197,8 @@ static struct s3c2410fb_mach_info mini2440_fb_info __initdata = {
 
         /* Enable VD[2..7], VD[10..15], VD[18..23] and VCLK, syncs, VDEN
          * and disable the pull down resistors on pins we are using for LCD
-         * data. */
+         * data.
+         */
 
         .gpcup          = (0xf << 1) | (0x3f << 10),
 
@@ -232,10 +234,11 @@ static struct s3c2410fb_mach_info mini2440_fb_info __initdata = {
 /* MMC/SD  */
 
 static struct s3c24xx_mci_pdata mini2440_mmc_cfg __initdata = {
-   .gpio_detect   = S3C2410_GPG(8),
-   .gpio_wprotect = S3C2410_GPH(8),
-   .set_power     = NULL,
-   .ocr_avail     = MMC_VDD_32_33|MMC_VDD_33_34,
+        .gpio_detect            = S3C2410_GPG(8),
+        .gpio_wprotect          = S3C2410_GPH(8),
+        .wprotect_invert        = 1,
+        .set_power              = NULL,
+        .ocr_avail              = MMC_VDD_32_33|MMC_VDD_33_34,
 };
 
 /* NAND Flash on MINI2440 board */
@@ -254,7 +257,8 @@ static struct mtd_partition mini2440_default_nand_part[] __initdata = {
         [2] = {
                 .name   = "kernel",
                 /* 5 megabytes, for a kernel with no modules
-                 * or a uImage with a ramdisk attached */
+                 * or a uImage with a ramdisk attached
+                 */
                 .size   = 0x00500000,
                 .offset = SZ_256K + SZ_128K,
         },
@@ -271,7 +275,7 @@ static struct s3c2410_nand_set mini2440_nand_sets[] __initdata = {
                 .nr_chips       = 1,
                 .nr_partitions  = ARRAY_SIZE(mini2440_default_nand_part),
                 .partitions     = mini2440_default_nand_part,
-                .flash_bbt      = 1, /* we use u-boot to create a BBT */
+                .flash_bbt      = 1, /* we use u-boot to create a BBT */
         },
 };
 
@@ -282,7 +286,7 @@ static struct s3c2410_platform_nand mini2440_nand_info __initdata = {
         .nr_sets        = ARRAY_SIZE(mini2440_nand_sets),
         .sets           = mini2440_nand_sets,
         .ignore_unset_ecc = 1,
-        .ecc_mode       = NAND_ECC_HW,
+        .ecc_mode       = NAND_ECC_HW,
 };
 
 /* DM9000AEP 10/100 ethernet controller */
@@ -290,7 +294,7 @@ static struct s3c2410_platform_nand mini2440_nand_info __initdata = {
 static struct resource mini2440_dm9k_resource[] = {
         [0] = DEFINE_RES_MEM(MACH_MINI2440_DM9K_BASE, 4),
         [1] = DEFINE_RES_MEM(MACH_MINI2440_DM9K_BASE + 4, 4),
-        [2] = DEFINE_RES_NAMED(IRQ_EINT7, 1, NULL, IORESOURCE_IRQ \
+        [2] = DEFINE_RES_NAMED(IRQ_EINT7, 1, NULL, IORESOURCE_IRQ
                                                 | IORESOURCE_IRQ_HIGHEDGE),
 };
 
@@ -362,7 +366,8 @@ static struct gpio_keys_button mini2440_buttons[] = {
         },
 #if 0
         /* this pin is also known as TCLK1 and seems to already
-         * marked as "in use" somehow in the kernel -- possibly wrongly */
+         * marked as "in use" somehow in the kernel -- possibly wrongly
+         */
         {
                 .gpio           = S3C2410_GPG(11),      /* K6 */
                 .code           = KEY_F6,
@@ -564,7 +569,8 @@ static char mini2440_features_str[12] __initdata = "0tb";
 static int __init mini2440_features_setup(char *str)
 {
         if (str)
-                strlcpy(mini2440_features_str, str, sizeof(mini2440_features_str));
+                strlcpy(mini2440_features_str, str,
+                        sizeof(mini2440_features_str));
         return 1;
 }
 
@@ -583,10 +589,10 @@ struct mini2440_features_t {
 };
 
 static void __init mini2440_parse_features(
-                struct mini2440_features_t * features,
-                const char * features_str )
+                struct mini2440_features_t *features,
+                const char *features_str)
 {
-        const char * fp = features_str;
+        const char *fp = features_str;
 
         features->count = 0;
         features->done = 0;
@@ -598,13 +604,14 @@ static void __init mini2440_parse_features(
                 switch (f) {
                 case '0'...'9': /* tft screen */
                         if (features->done & FEATURE_SCREEN) {
-                                printk(KERN_INFO "MINI2440: '%c' ignored, "
-                                        "screen type already set\n", f);
+                                pr_info("MINI2440: '%c' ignored, screen type already set\n",
+                                        f);
                         } else {
                                 int li = f - '0';
+
                                 if (li >= ARRAY_SIZE(mini2440_lcd_cfg))
-                                        printk(KERN_INFO "MINI2440: "
-                                                "'%c' out of range LCD mode\n", f);
+                                        pr_info("MINI2440: '%c' out of range LCD mode\n",
+                                                f);
                                 else {
                                         features->optional[features->count++] =
                                                         &s3c_device_lcd;
@@ -615,8 +622,8 @@ static void __init mini2440_parse_features(
                         break;
                 case 'b':
                         if (features->done & FEATURE_BACKLIGHT)
-                                printk(KERN_INFO "MINI2440: '%c' ignored, "
-                                        "backlight already set\n", f);
+                                pr_info("MINI2440: '%c' ignored, backlight already set\n",
+                                        f);
                         else {
                                 features->optional[features->count++] =
                                                 &mini2440_led_backlight;
@@ -624,13 +631,13 @@ static void __init mini2440_parse_features(
                         features->done |= FEATURE_BACKLIGHT;
                         break;
                 case 't':
-                        printk(KERN_INFO "MINI2440: '%c' ignored, "
-                                "touchscreen not compiled in\n", f);
+                        pr_info("MINI2440: '%c' ignored, touchscreen not compiled in\n",
+                                f);
                         break;
                 case 'c':
                         if (features->done & FEATURE_CAMERA)
-                                printk(KERN_INFO "MINI2440: '%c' ignored, "
-                                        "camera already registered\n", f);
+                                pr_info("MINI2440: '%c' ignored, camera already registered\n",
+                                        f);
                         else
                                 features->optional[features->count++] =
                                         &s3c_device_camif;
@@ -645,7 +652,7 @@ static void __init mini2440_init(void)
         struct mini2440_features_t features = { 0 };
         int i;
 
-        printk(KERN_INFO "MINI2440: Option string mini2440=%s\n",
+        pr_info("MINI2440: Option string mini2440=%s\n",
                         mini2440_features_str);
 
         /* Parse the feature string */
@@ -674,17 +681,17 @@ static void __init mini2440_init(void)
                 mini2440_fb_info.displays =
                         &mini2440_lcd_cfg[features.lcd_index];
 
-                printk(KERN_INFO "MINI2440: LCD");
+                pr_info("MINI2440: LCD");
                 for (li = 0; li < ARRAY_SIZE(mini2440_lcd_cfg); li++)
                         if (li == features.lcd_index)
-                                printk(" [%d:%dx%d]", li,
+                                pr_cont(" [%d:%dx%d]", li,
                                         mini2440_lcd_cfg[li].width,
                                         mini2440_lcd_cfg[li].height);
                         else
-                                printk(" %d:%dx%d", li,
+                                pr_cont(" %d:%dx%d", li,
                                         mini2440_lcd_cfg[li].width,
                                         mini2440_lcd_cfg[li].height);
-                printk("\n");
+                pr_cont("\n");
                 s3c24xx_fb_set_platdata(&mini2440_fb_info);
         }
 
diff --git a/arch/arm64/boot/dts/actions/Makefile b/arch/arm64/boot/dts/actions/Makefile
index d8b923480f5a..b57fd2372ecd 100644
--- a/arch/arm64/boot/dts/actions/Makefile
+++ b/arch/arm64/boot/dts/actions/Makefile
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+
 dtb-$(CONFIG_ARCH_ACTIONS) += s700-cubieboard7.dtb
 
 dtb-$(CONFIG_ARCH_ACTIONS) += s900-bubblegum-96.dtb
diff --git a/arch/arm64/boot/dts/actions/s700-cubieboard7.dts b/arch/arm64/boot/dts/actions/s700-cubieboard7.dts
index ef79d7905f44..28f3f4a0f7f0 100644
--- a/arch/arm64/boot/dts/actions/s700-cubieboard7.dts
+++ b/arch/arm64/boot/dts/actions/s700-cubieboard7.dts
@@ -28,12 +28,6 @@
                 device_type = "memory";
                 reg = <0x1 0xe0000000 0x0 0x0>;
         };
-
-        uart3_clk: uart3-clk {
-                compatible = "fixed-clock";
-                clock-frequency = <921600>;
-                #clock-cells = <0>;
-        };
 };
 
 &timer {
@@ -42,5 +36,4 @@
 
 &uart3 {
         status = "okay";
-        clocks = <&uart3_clk>;
 };
diff --git a/arch/arm64/boot/dts/actions/s700.dtsi b/arch/arm64/boot/dts/actions/s700.dtsi
index 66dd5309f0a2..192c7b39c8c1 100644
--- a/arch/arm64/boot/dts/actions/s700.dtsi
+++ b/arch/arm64/boot/dts/actions/s700.dtsi
@@ -3,6 +3,7 @@
  * Copyright (c) 2017 Andreas Färber
  */
 
+#include <dt-bindings/clock/actions,s700-cmu.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
 / {
@@ -87,6 +88,12 @@
                 #clock-cells = <0>;
         };
 
+        losc: losc {
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+                #clock-cells = <0>;
+        };
+
         soc {
                 compatible = "simple-bus";
                 #address-cells = <2>;
@@ -107,6 +114,7 @@
                 uart0: serial@e0120000 {
                         compatible = "actions,s900-uart", "actions,owl-uart";
                         reg = <0x0 0xe0120000 0x0 0x2000>;
+                        clocks = <&cmu CLK_UART0>;
                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
                         status = "disabled";
                 };
@@ -114,6 +122,7 @@
                 uart1: serial@e0122000 {
                         compatible = "actions,s900-uart", "actions,owl-uart";
                         reg = <0x0 0xe0122000 0x0 0x2000>;
+                        clocks = <&cmu CLK_UART1>;
                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
                         status = "disabled";
                 };
@@ -121,6 +130,7 @@
                 uart2: serial@e0124000 {
                         compatible = "actions,s900-uart", "actions,owl-uart";
                         reg = <0x0 0xe0124000 0x0 0x2000>;
+                        clocks = <&cmu CLK_UART2>;
                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
                         status = "disabled";
                 };
@@ -128,6 +138,7 @@
                 uart3: serial@e0126000 {
                         compatible = "actions,s900-uart", "actions,owl-uart";
                         reg = <0x0 0xe0126000 0x0 0x2000>;
+                        clocks = <&cmu CLK_UART3>;
                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
                         status = "disabled";
                 };
@@ -135,6 +146,7 @@
                 uart4: serial@e0128000 {
                         compatible = "actions,s900-uart", "actions,owl-uart";
                         reg = <0x0 0xe0128000 0x0 0x2000>;
+                        clocks = <&cmu CLK_UART4>;
                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
                         status = "disabled";
                 };
@@ -142,6 +154,7 @@
                 uart5: serial@e012a000 {
                         compatible = "actions,s900-uart", "actions,owl-uart";
                         reg = <0x0 0xe012a000 0x0 0x2000>;
+                        clocks = <&cmu CLK_UART5>;
                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
                         status = "disabled";
                 };
@@ -149,10 +162,18 @@
                 uart6: serial@e012c000 {
                         compatible = "actions,s900-uart", "actions,owl-uart";
                         reg = <0x0 0xe012c000 0x0 0x2000>;
+                        clocks = <&cmu CLK_UART6>;
                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
                         status = "disabled";
                 };
 
+                cmu: clock-controller@e0168000 {
+                        compatible = "actions,s700-cmu";
+                        reg = <0x0 0xe0168000 0x0 0x1000>;
+                        clocks = <&hosc>, <&losc>;
+                        #clock-cells = <1>;
+                };
+
                 sps: power-controller@e01b0100 {
                         compatible = "actions,s700-sps";
                         reg = <0x0 0xe01b0100 0x0 0x100>;
diff --git a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
index 21ca80f9941c..732daaa6e9d3 100644
--- a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
+++ b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2017 Andreas Färber
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
 /dts-v1/;
@@ -24,11 +23,223 @@
                 device_type = "memory";
                 reg = <0x0 0x0 0x0 0x80000000>;
         };
+};
+
+&i2c0 {
+        status = "disabled";
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c0_default>;
+};
+
+&i2c1 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c1_default>;
+};
+
+&i2c2 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c2_default>;
+};
+
+/*
+ * GPIO name legend: proper name = the GPIO line is used as GPIO
+ *         NC = not connected (pin out but not routed from the chip to
+ *              anything the board)
+ *         "[PER]" = pin is muxed for [peripheral] (not GPIO)
+ *         LSEC = Low Speed External Connector
+ *         HSEC = High Speed External Connector
+ *
+ * Line names are taken from the schematic "Schematics Bubblegum96"
+ * version v1.0
+ *
+ * For the lines routed to the external connectors the
+ * lines are named after the 96Boards CE Specification 1.0,
+ * Appendix "Expansion Connector Signal Description".
+ *
+ * When the 96Boards naming of a line and the schematic name of
+ * the same line are in conflict, the 96Boards specification
+ * takes precedence, which means that the external UART on the
+ * LSEC is named UART0 while the schematic and SoC names this
+ * UART2. Only exception is the I2C lines for which the schematic
+ * naming has been preferred. This is only for the informational
+ * lines i.e. "[FOO]", the GPIO named lines "GPIO-A" thru "GPIO-L"
+ * are the only ones actually used for GPIO.
+ */
+
+&pinctrl {
+        gpio-line-names =
+                "GPIO-A", /* GPIO_0, LSEC pin 23 */
+                "GPIO-B", /* GPIO_1, LSEC pin 24 */
+                "GPIO-C", /* GPIO_2, LSEC pin 25 */
+                "GPIO-D", /* GPIO_3, LSEC pin 26 */
+                "GPIO-E", /* GPIO_4, LSEC pin 27 */
+                "GPIO-F", /* GPIO_5, LSEC pin 28 */
+                "GPIO-G", /* GPIO_6, LSEC pin 29 */
+                "GPIO-H", /* GPIO_7, LSEC pin 30 */
+                "GPIO-I", /* GPIO_8, LSEC pin 31 */
+                "GPIO-J", /* GPIO_9, LSEC pin 32 */
+                "NC", /* GPIO_10 */
+                "NC", /* GPIO_11 */
+                "SIRQ2_1V8", /* GPIO_12 */
+                "PCM0_OUT", /* GPIO_13 */
+                "WIFI_LED", /* GPIO_14 */
+                "PCM0_SYNC", /* GPIO_15 */
+                "PCM0_CLK", /* GPIO_16 */
+                "PCM0_IN", /* GPIO_17 */
+                "BT_LED", /* GPIO_18 */
+                "LED0", /* GPIO_19 */
+                "LED1", /* GPIO_20 */
+                "JTAG_TCK", /* GPIO_21 */
+                "JTAG_TMS", /* GPIO_22 */
+                "JTAG_TDI", /* GPIO_23 */
+                "JTAG_TDO", /* GPIO_24 */
+                "[UART1_RxD]", /* GPIO_25, LSEC pin 13 */
+                "NC", /* GPIO_26 */
+                "[UART1_TxD]", /* GPIO_27, LSEC pin 11 */
+                "SD0_D0", /* GPIO_28 */
+                "SD0_D1", /* GPIO_29 */
+                "SD0_D2", /* GPIO_30 */
+                "SD0_D3", /* GPIO_31 */
+                "SD1_D0", /* GPIO_32 */
+                "SD1_D1", /* GPIO_33 */
+                "SD1_D2", /* GPIO_34 */
+                "SD1_D3", /* GPIO_35 */
+                "SD0_CMD", /* GPIO_36 */
+                "SD0_CLK", /* GPIO_37 */
+                "SD1_CMD", /* GPIO_38 */
+                "SD1_CLK", /* GPIO_39 */
+                "SPI0_SCLK", /* GPIO_40, LSEC pin 8 */
+                "SPI0_CS", /* GPIO_41, LSEC pin 12 */
+                "SPI0_DIN", /* GPIO_42, LSEC pin 10 */
+                "SPI0_DOUT", /* GPIO_43, LSEC pin 14 */
+                "I2C5_SDATA", /* GPIO_44, HSEC pin 36 */
+                "I2C5_SCLK", /* GPIO_45, HSEC pin 38 */
+                "UART0_RX", /* GPIO_46, LSEC pin 7 */
+                "UART0_TX", /* GPIO_47, LSEC pin 5 */
+                "UART0_RTSB", /* GPIO_48, LSEC pin 9 */
+                "UART0_CTSB", /* GPIO_49, LSEC pin 3 */
+                "I2C4_SCLK", /* GPIO_50, HSEC pin 32 */
+                "I2C4_SDATA", /* GPIO_51, HSEC pin 34 */
+                "I2C0_SCLK", /* GPIO_52 */
+                "I2C0_SDATA", /* GPIO_53 */
+                "I2C1_SCLK", /* GPIO_54, LSEC pin 15 */
+                "I2C1_SDATA", /* GPIO_55, LSEC pin 17 */
+                "I2C2_SCLK", /* GPIO_56, LSEC pin 19 */
+                "I2C2_SDATA", /* GPIO_57, LSEC pin 21 */
+                "CSI0_DN0", /* GPIO_58, HSEC pin 10 */
+                "CSI0_DP0", /* GPIO_59, HSEC pin 8 */
+                "CSI0_DN1", /* GPIO_60, HSEC pin 16 */
+                "CSI0_DP1", /* GPIO_61, HSEC pin 14 */
+                "CSI0_CN", /* GPIO_62, HSEC pin 4 */
+                "CSI0_CP", /* GPIO_63, HSEC pin 2 */
+                "CSI0_DN2", /* GPIO_64, HSEC pin 22 */
+                "CSI0_DP2", /* GPIO_65, HSEC pin 20 */
+                "CSI0_DN3", /* GPIO_66, HSEC pin 28 */
+                "CSI0_DP3", /* GPIO_67, HSEC pin 26 */
+                "[CLK0]", /* GPIO_68, HSEC pin 15 */
+                "CSI1_DN0", /* GPIO_69, HSEC pin 44 */
+                "CSI1_DP0", /* GPIO_70, HSEC pin 42 */
+                "CSI1_DN1", /* GPIO_71, HSEC pin 50 */
+                "CSI1_DP1", /* GPIO_72, HSEC pin 48 */
+                "CSI1_CN", /* GPIO_73, HSEC pin 56 */
+                "CSI1_CP", /* GPIO_74, HSEC pin 54 */
+                "[CLK1]", /* GPIO_75, HSEC pin 17 */
+                "[GPIOD0]", /* GPIO_76 */
+                "[GPIOD1]", /* GPIO_77 */
+                "BT_RST_N", /* GPIO_78 */
+                "EXT_DC_EN", /* GPIO_79 */
+                "[PCM_DI]", /* GPIO_80, LSEC pin 22 */
+                "[PCM_DO]", /* GPIO_81, LSEC pin 20 */
+                "[PCM_CLK]", /* GPIO_82, LSEC pin 18 */
+                "[PCM_FS]", /* GPIO_83, LSEC pin 16 */
+                "WAKE_BT", /* GPIO_84 */
+                "WL_REG_ON", /* GPIO_85 */
+                "NC", /* GPIO_86 */
+                "NC", /* GPIO_87 */
+                "NC", /* GPIO_88 */
+                "NC", /* GPIO_89 */
+                "NC", /* GPIO_90 */
+                "WIFI_WAKE", /* GPIO_91 */
+                "BT_WAKE", /* GPIO_92 */
+                "NC", /* GPIO_93 */
+                "OTG_EN2", /* GPIO_94 */
+                "OTG_EN", /* GPIO_95 */
+                "DSI_DP3", /* GPIO_96, HSEC pin 45 */
+                "DSI_DN3", /* GPIO_97, HSEC pin 47 */
+                "DSI_DP1", /* GPIO_98, HSEC pin 33 */
+                "DSI_DN1", /* GPIO_99, HSEC pin 35 */
+                "DSI_CP", /* GPIO_100, HSEC pin 21 */
+                "DSI_CN", /* GPIO_101, HSEC pin 23 */
+                "DSI_DP0", /* GPIO_102, HSEC pin 27 */
+                "DSI_DN0", /* GPIO_103, HSEC pin 29 */
+                "DSI_DP2", /* GPIO_104, HSEC pin 39 */
+                "DSI_DN2", /* GPIO_105, HSEC pin 41 */
+                "N0_D0", /* GPIO_106 */
+                "N0_D1", /* GPIO_107 */
+                "N0_D2", /* GPIO_108 */
+                "N0_D3", /* GPIO_109 */
+                "N0_D4", /* GPIO_110 */
+                "N0_D5", /* GPIO_111 */
+                "N0_D6", /* GPIO_112 */
+                "N0_D7", /* GPIO_113 */
+                "N0_DQS", /* GPIO_114 */
+                "N0_DQSN", /* GPIO_115 */
+                "NC", /* GPIO_116 */
+                "NC", /* GPIO_117 */
+                "NC", /* GPIO_118 */
+                "N0_CEB1", /* GPIO_119 */
+                "CARD_DT", /* GPIO_120 */
+                "N0_CEB3", /* GPIO_121 */
+                "SD_DAT0", /* GPIO_122, HSEC pin 1 */
+                "SD_DAT1", /* GPIO_123, HSEC pin 3 */
+                "SD_DAT2", /* GPIO_124, HSEC pin 5 */
+                "SD_DAT3", /* GPIO_125, HSEC pin 7 */
+                "NC", /* GPIO_126 */
+                "NC", /* GPIO_127 */
+                "[PWR_BTN_N]", /* GPIO_128, LSEC pin 4 */
+                "[RST_BTN_N]", /* GPIO_129, LSEC pin 6 */
+                "NC", /* GPIO_130 */
+                "SD_CMD", /* GPIO_131 */
+                "GPIO-L", /* GPIO_132, LSEC pin 34 */
+                "GPIO-K", /* GPIO_133, LSEC pin 33 */
+                "NC", /* GPIO_134 */
+                "SD_SCLK", /* GPIO_135 */
+                "NC", /* GPIO_136 */
+                "JTAG_TRST", /* GPIO_137 */
+                "I2C3_SCLK", /* GPIO_138 */
+                "LED2", /* GPIO_139 */
+                "LED3", /* GPIO_140 */
+                "I2C3_SDATA", /* GPIO_141 */
+                "UART3_RX", /* GPIO_142 */
+                "UART3_TX", /* GPIO_143 */
+                "UART3_RTSB", /* GPIO_144 */
+                "UART3_CTSB"; /* GPIO_145 */
+
+        i2c0_default: i2c0-default {
+                pinmux {
+                        groups = "i2c0_mfp";
+                        function = "i2c0";
+                };
+                pinconf {
+                        pins = "i2c0_sclk", "i2c0_sdata";
+                        bias-pull-up;
+                };
+        };
+
+        i2c1_default: i2c1-default {
+                pinconf {
+                        pins = "i2c1_sclk", "i2c1_sdata";
+                        bias-pull-up;
+                };
+        };
 
-        uart5_clk: uart5-clk {
-                compatible = "fixed-clock";
-                clock-frequency = <921600>;
-                #clock-cells = <0>;
+        i2c2_default: i2c2-default {
+                pinconf {
+                        pins = "i2c2_sclk", "i2c2_sdata";
+                        bias-pull-up;
+                };
         };
 };
 
@@ -38,5 +249,4 @@
 
 &uart5 {
         status = "okay";
-        clocks = <&uart5_clk>;
 };
diff --git a/arch/arm64/boot/dts/actions/s900.dtsi b/arch/arm64/boot/dts/actions/s900.dtsi
index 11406f6d3a6d..491ddccc9038 100644
--- a/arch/arm64/boot/dts/actions/s900.dtsi
+++ b/arch/arm64/boot/dts/actions/s900.dtsi
@@ -1,9 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2017 Andreas Färber
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
+#include <dt-bindings/clock/actions,s900-cmu.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
 / {
@@ -88,6 +88,18 @@
                 #clock-cells = <0>;
         };
 
+        losc: losc {
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+                #clock-cells = <0>;
+        };
+
+        diff24M: diff24M {
+                compatible = "fixed-clock";
+                clock-frequency = <24000000>;
+                #clock-cells = <0>;
+        };
+
         soc {
                 compatible = "simple-bus";
                 #address-cells = <2>;
@@ -108,6 +120,7 @@
                 uart0: serial@e0120000 {
                         compatible = "actions,s900-uart", "actions,owl-uart";
                         reg = <0x0 0xe0120000 0x0 0x2000>;
+                        clocks = <&cmu CLK_UART0>;
                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
                         status = "disabled";
                 };
@@ -115,6 +128,7 @@
                 uart1: serial@e0122000 {
                         compatible = "actions,s900-uart", "actions,owl-uart";
                         reg = <0x0 0xe0122000 0x0 0x2000>;
+                        clocks = <&cmu CLK_UART1>;
                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
                         status = "disabled";
                 };
@@ -122,6 +136,7 @@
                 uart2: serial@e0124000 {
                         compatible = "actions,s900-uart", "actions,owl-uart";
                         reg = <0x0 0xe0124000 0x0 0x2000>;
+                        clocks = <&cmu CLK_UART2>;
                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
                         status = "disabled";
                 };
@@ -129,6 +144,7 @@
                 uart3: serial@e0126000 {
                         compatible = "actions,s900-uart", "actions,owl-uart";
                         reg = <0x0 0xe0126000 0x0 0x2000>;
+                        clocks = <&cmu CLK_UART3>;
                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
                         status = "disabled";
                 };
@@ -136,6 +152,7 @@
                 uart4: serial@e0128000 {
                         compatible = "actions,s900-uart", "actions,owl-uart";
                         reg = <0x0 0xe0128000 0x0 0x2000>;
+                        clocks = <&cmu CLK_UART4>;
                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
                         status = "disabled";
                 };
@@ -143,6 +160,7 @@
                 uart5: serial@e012a000 {
                         compatible = "actions,s900-uart", "actions,owl-uart";
                         reg = <0x0 0xe012a000 0x0 0x2000>;
+                        clocks = <&cmu CLK_UART5>;
                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
                         status = "disabled";
                 };
@@ -150,15 +168,111 @@
                 uart6: serial@e012c000 {
                         compatible = "actions,s900-uart", "actions,owl-uart";
                         reg = <0x0 0xe012c000 0x0 0x2000>;
+                        clocks = <&cmu CLK_UART6>;
                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
                         status = "disabled";
                 };
 
+                sps: power-controller@e012e000 {
+                        compatible = "actions,s900-sps";
+                        reg = <0x0 0xe012e000 0x0 0x2000>;
+                        #power-domain-cells = <1>;
+                };
+
+                cmu: clock-controller@e0160000 {
+                        compatible = "actions,s900-cmu";
+                        reg = <0x0 0xe0160000 0x0 0x1000>;
+                        clocks = <&hosc>, <&losc>;
+                        #clock-cells = <1>;
+                };
+
+                i2c0: i2c@e0170000 {
+                        compatible = "actions,s900-i2c";
+                        reg = <0 0xe0170000 0 0x1000>;
+                        clocks = <&cmu CLK_I2C0>;
+                        interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                i2c1: i2c@e0172000 {
+                        compatible = "actions,s900-i2c";
+                        reg = <0 0xe0172000 0 0x1000>;
+                        clocks = <&cmu CLK_I2C1>;
+                        interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                i2c2: i2c@e0174000 {
+                        compatible = "actions,s900-i2c";
+                        reg = <0 0xe0174000 0 0x1000>;
+                        clocks = <&cmu CLK_I2C2>;
+                        interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                i2c3: i2c@e0176000 {
+                        compatible = "actions,s900-i2c";
+                        reg = <0 0xe0176000 0 0x1000>;
+                        clocks = <&cmu CLK_I2C3>;
+                        interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                i2c4: i2c@e0178000 {
+                        compatible = "actions,s900-i2c";
+                        reg = <0 0xe0178000 0 0x1000>;
+                        clocks = <&cmu CLK_I2C4>;
+                        interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                i2c5: i2c@e017a000 {
+                        compatible = "actions,s900-i2c";
+                        reg = <0 0xe017a000 0 0x1000>;
+                        clocks = <&cmu CLK_I2C5>;
+                        interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                pinctrl: pinctrl@e01b0000 {
+                        compatible = "actions,s900-pinctrl";
+                        reg = <0x0 0xe01b0000 0x0 0x1000>;
+                        clocks = <&cmu CLK_GPIO>;
+                        gpio-controller;
+                        gpio-ranges = <&pinctrl 0 0 146>;
+                        #gpio-cells = <2>;
+                };
+
                 timer: timer@e0228000 {
                         compatible = "actions,s900-timer";
                         reg = <0x0 0xe0228000 0x0 0x8000>;
                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-names = "timer1";
                 };
+
+                dma: dma-controller@e0260000 {
+                        compatible = "actions,s900-dma";
+                        reg = <0x0 0xe0260000 0x0 0x1000>;
+                        interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+                        #dma-cells = <1>;
+                        dma-channels = <12>;
+                        dma-requests = <46>;
+                        clocks = <&cmu CLK_DMAC>;
+                };
         };
 };
diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
index 9ffa7a038791..8d4f97f279e0 100644
--- a/arch/arm64/boot/dts/allwinner/Makefile
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -4,10 +4,13 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-bananapi-m64.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-nanopi-a64.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-orangepi-win.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-lts.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinebook.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-teres-i.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus-v1.2.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h3-cc.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-plus2.dtb
@@ -15,4 +18,5 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts
index eac4793c8502..6cb2b7f0c817 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts
@@ -203,7 +203,7 @@
 
 &uart0 {
         pinctrl-names = "default";
-        pinctrl-0 = <&uart0_pins_a>;
+        pinctrl-0 = <&uart0_pb_pins>;
         status = "okay";
 };
 
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
index 094cfed13df9..ef1c90401bb2 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
@@ -60,6 +60,17 @@
                 stdout-path = "serial0:115200n8";
         };
 
+        hdmi-connector {
+                compatible = "hdmi-connector";
+                type = "a";
+
+                port {
+                        hdmi_con_in: endpoint {
+                                remote-endpoint = <&hdmi_out_con>;
+                        };
+                };
+        };
+
         leds {
                 compatible = "gpio-leds";
 
@@ -86,6 +97,10 @@
         };
 };
 
+&de {
+        status = "okay";
+};
+
 &ehci0 {
         status = "okay";
 };
@@ -103,6 +118,17 @@
         status = "okay";
 };
 
+&hdmi {
+        hvcc-supply = <&reg_dldo1>;
+        status = "okay";
+};
+
+&hdmi_out {
+        hdmi_out_con: endpoint {
+                remote-endpoint = <&hdmi_con_in>;
+        };
+};
+
 &i2c1 {
         pinctrl-names = "default";
         pinctrl-0 = <&i2c1_pins>;
@@ -151,7 +177,7 @@
 
 &mmc2 {
         pinctrl-names = "default";
-        pinctrl-0 = <&mmc2_pins>;
+        pinctrl-0 = <&mmc2_pins>, <&mmc2_ds_pin>;
         vmmc-supply = <&reg_dcdc1>;
         bus-width = <8>;
         non-removable;
@@ -302,7 +328,7 @@
 
 &uart0 {
         pinctrl-names = "default";
-        pinctrl-0 = <&uart0_pins_a>;
+        pinctrl-0 = <&uart0_pb_pins>;
         status = "okay";
 };
 
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
index 98dbff19f5cc..31884dbc8838 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
@@ -51,12 +51,44 @@
         compatible = "friendlyarm,nanopi-a64", "allwinner,sun50i-a64";
 
         aliases {
+                ethernet0 = &emac;
                 serial0 = &uart0;
         };
 
         chosen {
                 stdout-path = "serial0:115200n8";
         };
+
+        hdmi-connector {
+                compatible = "hdmi-connector";
+                type = "a";
+
+                port {
+                        hdmi_con_in: endpoint {
+                                remote-endpoint = <&hdmi_out_con>;
+                        };
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                blue {
+                        label = "nanopi-a64:blue:status";
+                        gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */
+                };
+        };
+
+        wifi_pwrseq: wifi_pwrseq {
+                compatible = "mmc-pwrseq-simple";
+                clocks = <&rtc 1>;
+                clock-names = "ext_clock";
+                reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
+        };
+};
+
+&de {
+        status = "okay";
 };
 
 &ehci0 {
@@ -67,6 +99,26 @@
         status = "okay";
 };
 
+&emac {
+        pinctrl-names = "default";
+        pinctrl-0 = <&rgmii_pins>;
+        phy-mode = "rgmii";
+        phy-handle = <&ext_rgmii_phy>;
+        phy-supply = <&reg_dcdc1>;
+        status = "okay";
+};
+
+&hdmi {
+        hvcc-supply = <&reg_dldo1>;
+        status = "okay";
+};
+
+&hdmi_out {
+        hdmi_out_con: endpoint {
+                remote-endpoint = <&hdmi_con_in>;
+        };
+};
+
 /* i2c1 connected with gpio headers like pine64, bananapi */
 &i2c1 {
         pinctrl-names = "default";
@@ -78,6 +130,13 @@
         bias-pull-up;
 };
 
+&mdio {
+        ext_rgmii_phy: ethernet-phy@1 {
+                compatible = "ethernet-phy-ieee802.3-c22";
+                reg = <7>;
+        };
+};
+
 &mmc0 {
         pinctrl-names = "default";
         pinctrl-0 = <&mmc0_pins>;
@@ -88,6 +147,24 @@
         status = "okay";
 };
 
+&mmc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc1_pins>;
+        vmmc-supply = <&reg_dcdc1>;
+        vqmmc-supply = <&reg_dldo4>;
+        mmc-pwrseq = <&wifi_pwrseq>;
+        bus-width = <4>;
+        non-removable;
+        status = "okay";
+
+        rtl8189etv: wifi@1 {
+                reg = <1>;
+                interrupt-parent = <&r_pio>;
+                interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */
+                interrupt-names = "host-wake";
+        };
+};
+
 &ohci0 {
         status = "okay";
 };
@@ -125,9 +202,9 @@
 
 &reg_dcdc1 {
         regulator-always-on;
-        regulator-min-microvolt = <3000000>;
-        regulator-max-microvolt = <3000000>;
-        regulator-name = "vcc-3v";
+        regulator-min-microvolt = <3300000>;
+        regulator-max-microvolt = <3300000>;
+        regulator-name = "vcc-3v3";
 };
 
 &reg_dcdc2 {
@@ -201,7 +278,7 @@
 
 &uart0 {
         pinctrl-names = "default";
-        pinctrl-0 = <&uart0_pins_a>;
+        pinctrl-0 = <&uart0_pb_pins>;
         status = "okay";
 };
 
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
index 3f531393eaee..f7a4bccaa5d4 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
@@ -51,6 +51,7 @@
         compatible = "olimex,a64-olinuxino", "allwinner,sun50i-a64";
 
         aliases {
+                ethernet0 = &emac;
                 serial0 = &uart0;
         };
 
@@ -58,12 +59,74 @@
                 stdout-path = "serial0:115200n8";
         };
 
+        hdmi-connector {
+                compatible = "hdmi-connector";
+                type = "a";
+
+                port {
+                        hdmi_con_in: endpoint {
+                                remote-endpoint = <&hdmi_out_con>;
+                        };
+                };
+        };
+
+        reg_usb1_vbus: usb1-vbus {
+                compatible = "regulator-fixed";
+                regulator-name = "usb1-vbus";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-boot-on;
+                enable-active-high;
+                gpio = <&pio 6 9 GPIO_ACTIVE_HIGH>; /* PG9 */
+                status = "okay";
+        };
+
         wifi_pwrseq: wifi_pwrseq {
                 compatible = "mmc-pwrseq-simple";
                 reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
         };
 };
 
+&de {
+        status = "okay";
+};
+
+&ehci0 {
+        status = "okay";
+};
+
+&ehci1 {
+        status = "okay";
+};
+
+&emac {
+        pinctrl-names = "default";
+        pinctrl-0 = <&rgmii_pins>;
+        phy-mode = "rgmii";
+        phy-handle = <&ext_rgmii_phy>;
+        phy-supply = <&reg_dcdc1>;
+        allwinner,tx-delay-ps = <600>;
+        status = "okay";
+};
+
+&hdmi {
+        hvcc-supply = <&reg_dldo1>;
+        status = "okay";
+};
+
+&hdmi_out {
+        hdmi_out_con: endpoint {
+                remote-endpoint = <&hdmi_con_in>;
+        };
+};
+
+&mdio {
+        ext_rgmii_phy: ethernet-phy@1 {
+                compatible = "ethernet-phy-ieee802.3-c22";
+                reg = <1>;
+        };
+};
+
 &mmc0 {
         pinctrl-names = "default";
         pinctrl-0 = <&mmc0_pins>;
@@ -92,6 +155,14 @@
         };
 };
 
+&ohci0 {
+        status = "okay";
+};
+
+&ohci1 {
+        status = "okay";
+};
+
 &r_rsb {
         status = "okay";
 
@@ -100,6 +171,7 @@
                 reg = <0x3a3>;
                 interrupt-parent = <&r_intc>;
                 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+                x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */
         };
 };
 
@@ -142,10 +214,14 @@
 
 /* DCDC3 is polyphased with DCDC2 */
 
+/*
+ * The board uses DDR3L DRAM chips. 1.36V is the closest to the nominal
+ * 1.35V that the PMIC can drive.
+ */
 &reg_dcdc5 {
         regulator-always-on;
-        regulator-min-microvolt = <1500000>;
-        regulator-max-microvolt = <1500000>;
+        regulator-min-microvolt = <1360000>;
+        regulator-max-microvolt = <1360000>;
         regulator-name = "vcc-ddr3";
 };
 
@@ -180,6 +256,11 @@
         regulator-name = "vcc-wifi-io";
 };
 
+&reg_drivevbus {
+        regulator-name = "usb0-vbus";
+        status = "okay";
+};
+
 &reg_eldo1 {
         regulator-min-microvolt = <1800000>;
         regulator-max-microvolt = <1800000>;
@@ -220,6 +301,18 @@
 
 &uart0 {
         pinctrl-names = "default";
-        pinctrl-0 = <&uart0_pins_a>;
+        pinctrl-0 = <&uart0_pb_pins>;
+        status = "okay";
+};
+
+&usb_otg {
+        dr_mode = "otg";
+        status = "okay";
+};
+
+&usbphy {
         status = "okay";
+        usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
+        usb0_vbus-supply = <&reg_drivevbus>;
+        usb1_vbus-supply = <&reg_usb1_vbus>;
 };
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
index 1221764f5719..b0c64f75792c 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
@@ -1,5 +1,6 @@
 /*
  * Copyright (C) 2017 Jagan Teki <jteki@openedev.com>
+ * Copyright (C) 2017-2018 Samuel Holland <samuel@sholland.org>
  *
  * This file is dual-licensed: you can use it either under the terms
  * of the GPL or the X11 license, at your option. Note that this dual
@@ -51,23 +52,127 @@
         compatible = "xunlong,orangepi-win", "allwinner,sun50i-a64";
 
         aliases {
+                ethernet0 = &emac;
                 serial0 = &uart0;
+                serial1 = &uart1;
+                serial2 = &uart2;
+                serial3 = &uart3;
+                serial4 = &uart4;
         };
 
         chosen {
                 stdout-path = "serial0:115200n8";
         };
+
+        hdmi-connector {
+                compatible = "hdmi-connector";
+                type = "a";
+
+                port {
+                        hdmi_con_in: endpoint {
+                                remote-endpoint = <&hdmi_out_con>;
+                        };
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                status {
+                        label = "orangepi:green:status";
+                        gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */
+                };
+        };
+
+        reg_gmac_3v3: gmac-3v3 {
+                compatible = "regulator-fixed";
+                regulator-name = "gmac-3v3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-boot-on;
+                enable-active-high;
+                gpio = <&pio 3 14 GPIO_ACTIVE_HIGH>; /* PD14 */
+                status = "okay";
+        };
+
+        reg_usb1_vbus: usb1-vbus {
+                compatible = "regulator-fixed";
+                regulator-name = "usb1-vbus";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-boot-on;
+                enable-active-high;
+                gpio = <&pio 3 7 GPIO_ACTIVE_HIGH>; /* PD7 */
+                status = "okay";
+        };
+
+        wifi_pwrseq: wifi_pwrseq {
+                compatible = "mmc-pwrseq-simple";
+                reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 */
+        };
+};
+
+&de {
+        status = "okay";
+};
+
+&ehci0 {
+        status = "okay";
 };
 
 &ehci1 {
         status = "okay";
 };
 
+&emac {
+        pinctrl-names = "default";
+        pinctrl-0 = <&rgmii_pins>;
+        phy-mode = "rgmii";
+        phy-handle = <&ext_rgmii_phy>;
+        phy-supply = <&reg_gmac_3v3>;
+        status = "okay";
+};
+
+&hdmi {
+        hvcc-supply = <&reg_dldo1>;
+        status = "okay";
+};
+
+&hdmi_out {
+        hdmi_out_con: endpoint {
+                remote-endpoint = <&hdmi_con_in>;
+        };
+};
+
+&mdio {
+        ext_rgmii_phy: ethernet-phy@1 {
+                compatible = "ethernet-phy-ieee802.3-c22";
+                reg = <1>;
+        };
+};
+
 &mmc0 {
         pinctrl-names = "default";
         pinctrl-0 = <&mmc0_pins>;
         vmmc-supply = <&reg_dcdc1>;
-        cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
+        cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+        disable-wp;
+        bus-width = <4>;
+        status = "okay";
+};
+
+&mmc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc1_pins>;
+        vmmc-supply = <&reg_dldo2>;
+        vqmmc-supply = <&reg_dldo4>;
+        mmc-pwrseq = <&wifi_pwrseq>;
+        bus-width = <4>;
+        non-removable;
+        status = "okay";
+};
+
+&ohci0 {
         status = "okay";
 };
 
@@ -89,9 +194,8 @@
 #include "axp803.dtsi"
 
 &reg_aldo1 {
-        regulator-always-on;
-        regulator-min-microvolt = <1800000>;
-        regulator-max-microvolt = <3300000>;
+        regulator-min-microvolt = <2800000>;
+        regulator-max-microvolt = <2800000>;
         regulator-name = "afvcc-csi";
 };
 
@@ -163,12 +267,23 @@
         regulator-name = "vcc-wifi-io";
 };
 
+&reg_drivevbus {
+        regulator-name = "usb0-vbus";
+        status = "okay";
+};
+
 &reg_eldo1 {
         regulator-min-microvolt = <1800000>;
         regulator-max-microvolt = <1800000>;
         regulator-name = "cpvdd";
 };
 
+&reg_eldo3 {
+        regulator-min-microvolt = <1500000>;
+        regulator-max-microvolt = <1800000>;
+        regulator-name = "dvdd-csi";
+};
+
 &reg_fldo1 {
         regulator-min-microvolt = <1200000>;
         regulator-max-microvolt = <1200000>;
@@ -195,13 +310,61 @@
         vcc-hdmi-supply = <&reg_dldo1>;
 };
 
+&spi0 {
+        status = "okay";
+
+        spi-flash@0 {
+                compatible = "mxicy,mx25l1606e", "jedec,spi-nor";
+                reg = <0>;
+                spi-max-frequency = <80000000>;
+                m25p,fast-read;
+                status = "okay";
+        };
+};
+
+/* On debug connector */
 &uart0 {
         pinctrl-names = "default";
-        pinctrl-0 = <&uart0_pins_a>;
+        pinctrl-0 = <&uart0_pb_pins>;
         status = "okay";
 };
 
-&usbphy {
+/* Bluetooth */
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
         status = "okay";
 };
 
+/* On Pi-2 connector, RTS/CTS optional */
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart2_pins>;
+        status = "disabled";
+};
+
+/* On Pi-2 connector, RTS/CTS optional */
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart3_pins>;
+        status = "disabled";
+};
+
+/* On Pi-2 connector (labeled for SPI1), RTS/CTS optional */
+&uart4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart4_pins>;
+        status = "disabled";
+};
+
+&usb_otg {
+        dr_mode = "otg";
+        status = "okay";
+};
+
+&usbphy {
+        usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
+        usb0_vbus-supply = <&reg_drivevbus>;
+        usb1_vbus-supply = <&reg_usb1_vbus>;
+        status = "okay";
+};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts
new file mode 100644
index 000000000000..72d6961dc312
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts
@@ -0,0 +1,13 @@
+/*
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ *
+ * Copyright (c) 2018 ARM Ltd.
+ */
+
+#include "sun50i-a64-sopine-baseboard.dts"
+
+/ {
+        model = "Pine64 LTS";
+        compatible = "pine64,pine64-lts", "allwinner,sun50i-r18",
+                     "allwinner,sun50i-a64";
+};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
index 1b9b92e541d2..c077b6c1f458 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
@@ -62,6 +62,21 @@
         chosen {
                 stdout-path = "serial0:115200n8";
         };
+
+        hdmi-connector {
+                compatible = "hdmi-connector";
+                type = "a";
+
+                port {
+                        hdmi_con_in: endpoint {
+                                remote-endpoint = <&hdmi_out_con>;
+                        };
+                };
+        };
+};
+
+&de {
+        status = "okay";
 };
 
 &ehci0 {
@@ -82,6 +97,17 @@
 
 };
 
+&hdmi {
+        hvcc-supply = <&reg_dldo1>;
+        status = "okay";
+};
+
+&hdmi_out {
+        hdmi_out_con: endpoint {
+                remote-endpoint = <&hdmi_con_in>;
+        };
+};
+
 &i2c1 {
         pinctrl-names = "default";
         pinctrl-0 = <&i2c1_pins>;
@@ -241,7 +267,7 @@
 /* On Exp and Euler connectors */
 &uart0 {
         pinctrl-names = "default";
-        pinctrl-0 = <&uart0_pins_a>;
+        pinctrl-0 = <&uart0_pb_pins>;
         status = "okay";
 };
 
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
index 897e60cbe38d..77fac84797e9 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
@@ -80,8 +80,7 @@
         pinctrl-names = "default";
         pinctrl-0 = <&mmc0_pins>;
         vmmc-supply = <&reg_dcdc1>;
-        cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
-        cd-inverted;
+        cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
         disable-wp;
         bus-width = <4>;
         status = "okay";
@@ -104,7 +103,7 @@
 
 &mmc2 {
         pinctrl-names = "default";
-        pinctrl-0 = <&mmc2_pins>;
+        pinctrl-0 = <&mmc2_pins>, <&mmc2_ds_pin>;
         vmmc-supply = <&reg_dcdc1>;
         vqmmc-supply = <&reg_eldo1>;
         bus-width = <8>;
@@ -143,7 +142,7 @@
 &r_i2c {
         clock-frequency = <100000>;
         pinctrl-names = "default";
-        pinctrl-0 = <&r_i2c_pins_a>;
+        pinctrl-0 = <&r_i2c_pl89_pins>;
         status = "okay";
 };
 
@@ -270,7 +269,7 @@
 
 &uart0 {
         pinctrl-names = "default";
-        pinctrl-0 = <&uart0_pins_a>;
+        pinctrl-0 = <&uart0_pb_pins>;
         status = "okay";
 };
 
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
index c21f2331add6..53fcc9098df3 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
@@ -61,6 +61,17 @@
                 stdout-path = "serial0:115200n8";
         };
 
+        hdmi-connector {
+                compatible = "hdmi-connector";
+                type = "a";
+
+                port {
+                        hdmi_con_in: endpoint {
+                                remote-endpoint = <&hdmi_out_con>;
+                        };
+                };
+        };
+
         reg_vcc1v8: vcc1v8 {
                 compatible = "regulator-fixed";
                 regulator-name = "vcc1v8";
@@ -69,6 +80,10 @@
         };
 };
 
+&de {
+        status = "okay";
+};
+
 &ehci0 {
         status = "okay";
 };
@@ -86,6 +101,17 @@
         status = "okay";
 };
 
+&hdmi {
+        hvcc-supply = <&reg_dldo1>;
+        status = "okay";
+};
+
+&hdmi_out {
+        hdmi_out_con: endpoint {
+                remote-endpoint = <&hdmi_con_in>;
+        };
+};
+
 &mdio {
         ext_rgmii_phy: ethernet-phy@1 {
                 compatible = "ethernet-phy-ieee802.3-c22";
@@ -140,7 +166,7 @@
 
 &uart0 {
         pinctrl-names = "default";
-        pinctrl-0 = <&uart0_pins_a>;
+        pinctrl-0 = <&uart0_pb_pins>;
         status = "okay";
 };
 
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts
index 81f8e0098699..c455b24dd079 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts
@@ -260,7 +260,7 @@
 
 &uart0 {
         pinctrl-names = "default";
-        pinctrl-0 = <&uart0_pins_a>;
+        pinctrl-0 = <&uart0_pb_pins>;
         status = "okay";
 };
 
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index d3daf90a8715..f3a66f888205 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -88,6 +88,7 @@
                         device_type = "cpu";
                         reg = <0>;
                         enable-method = "psci";
+                        next-level-cache = <&L2>;
                 };
 
                 cpu1: cpu@1 {
@@ -95,6 +96,7 @@
                         device_type = "cpu";
                         reg = <1>;
                         enable-method = "psci";
+                        next-level-cache = <&L2>;
                 };
 
                 cpu2: cpu@2 {
@@ -102,6 +104,7 @@
                         device_type = "cpu";
                         reg = <2>;
                         enable-method = "psci";
+                        next-level-cache = <&L2>;
                 };
 
                 cpu3: cpu@3 {
@@ -109,7 +112,20 @@
                         device_type = "cpu";
                         reg = <3>;
                         enable-method = "psci";
+                        next-level-cache = <&L2>;
                 };
+
+                L2: l2-cache {
+                        compatible = "cache";
+                        cache-level = <2>;
+                };
+        };
+
+        de: display-engine {
+                compatible = "allwinner,sun50i-a64-display-engine";
+                allwinner,pipelines = <&mixer0>,
+                                      <&mixer1>;
+                status = "disabled";
         };
 
         osc24M: osc24M_clk {
@@ -194,6 +210,52 @@
                                 #clock-cells = <1>;
                                 #reset-cells = <1>;
                         };
+
+                        mixer0: mixer@100000 {
+                                compatible = "allwinner,sun50i-a64-de2-mixer-0";
+                                reg = <0x100000 0x100000>;
+                                clocks = <&display_clocks CLK_BUS_MIXER0>,
+                                         <&display_clocks CLK_MIXER0>;
+                                clock-names = "bus",
+                                              "mod";
+                                resets = <&display_clocks RST_MIXER0>;
+
+                                ports {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+
+                                        mixer0_out: port@1 {
+                                                reg = <1>;
+
+                                                mixer0_out_tcon0: endpoint {
+                                                        remote-endpoint = <&tcon0_in_mixer0>;
+                                                };
+                                        };
+                                };
+                        };
+
+                        mixer1: mixer@200000 {
+                                compatible = "allwinner,sun50i-a64-de2-mixer-1";
+                                reg = <0x200000 0x100000>;
+                                clocks = <&display_clocks CLK_BUS_MIXER1>,
+                                         <&display_clocks CLK_MIXER1>;
+                                clock-names = "bus",
+                                              "mod";
+                                resets = <&display_clocks RST_MIXER1>;
+
+                                ports {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+
+                                        mixer1_out: port@1 {
+                                                reg = <1>;
+
+                                                mixer1_out_tcon1: endpoint {
+                                                        remote-endpoint = <&tcon1_in_mixer1>;
+                                                };
+                                        };
+                                };
+                        };
                 };
 
                 syscon: syscon@1c00000 {
@@ -228,6 +290,75 @@
                         #dma-cells = <1>;
                 };
 
+                tcon0: lcd-controller@1c0c000 {
+                        compatible = "allwinner,sun50i-a64-tcon-lcd",
+                                     "allwinner,sun8i-a83t-tcon-lcd";
+                        reg = <0x01c0c000 0x1000>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
+                        clock-names = "ahb", "tcon-ch0";
+                        clock-output-names = "tcon-pixel-clock";
+                        resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
+                        reset-names = "lcd", "lvds";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                tcon0_in: port@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <0>;
+
+                                        tcon0_in_mixer0: endpoint@0 {
+                                                reg = <0>;
+                                                remote-endpoint = <&mixer0_out_tcon0>;
+                                        };
+                                };
+
+                                tcon0_out: port@1 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <1>;
+                                };
+                        };
+                };
+
+                tcon1: lcd-controller@1c0d000 {
+                        compatible = "allwinner,sun50i-a64-tcon-tv",
+                                     "allwinner,sun8i-a83t-tcon-tv";
+                        reg = <0x01c0d000 0x1000>;
+                        interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
+                        clock-names = "ahb", "tcon-ch1";
+                        resets = <&ccu RST_BUS_TCON1>;
+                        reset-names = "lcd";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                tcon1_in: port@0 {
+                                        reg = <0>;
+
+                                        tcon1_in_mixer1: endpoint {
+                                                remote-endpoint = <&mixer1_out_tcon1>;
+                                        };
+                                };
+
+                                tcon1_out: port@1 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <1>;
+
+                                        tcon1_out_hdmi: endpoint@1 {
+                                                reg = <1>;
+                                                remote-endpoint = <&hdmi_in_tcon1>;
+                                        };
+                                };
+                        };
+                };
+
                 mmc0: mmc@1c0f000 {
                         compatible = "allwinner,sun50i-a64-mmc";
                         reg = <0x01c0f000 0x1000>;
@@ -270,6 +401,11 @@
                         #size-cells = <0>;
                 };
 
+                sid: eeprom@1c14000 {
+                        compatible = "allwinner,sun50i-a64-sid";
+                        reg = <0x1c14000 0x400>;
+                };
+
                 usb_otg: usb@1c19000 {
                         compatible = "allwinner,sun8i-a33-musb";
                         reg = <0x01c19000 0x0400>;
@@ -399,7 +535,7 @@
                         };
 
                         mmc2_pins: mmc2-pins {
-                                pins = "PC1", "PC5", "PC6", "PC8", "PC9",
+                                pins = "PC5", "PC6", "PC8", "PC9",
                                        "PC10","PC11", "PC12", "PC13",
                                        "PC14", "PC15", "PC16";
                                 function = "mmc2";
@@ -407,6 +543,13 @@
                                 bias-pull-up;
                         };
 
+                        mmc2_ds_pin: mmc2-ds-pin {
+                                pins = "PC1";
+                                function = "mmc2";
+                                drive-strength = <30>;
+                                bias-pull-up;
+                        };
+
                         pwm_pin: pwm_pin {
                                 pins = "PD22";
                                 function = "pwm";
@@ -442,7 +585,7 @@
                                 function = "spi1";
                         };
 
-                        uart0_pins_a: uart0 {
+                        uart0_pb_pins: uart0-pb-pins {
                                 pins = "PB8", "PB9";
                                 function = "uart0";
                         };
@@ -686,6 +829,50 @@
                         status = "disabled";
                 };
 
+                hdmi: hdmi@1ee0000 {
+                        compatible = "allwinner,sun50i-a64-dw-hdmi",
+                                     "allwinner,sun8i-a83t-dw-hdmi";
+                        reg = <0x01ee0000 0x10000>;
+                        reg-io-width = <1>;
+                        interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
+                                 <&ccu CLK_HDMI>;
+                        clock-names = "iahb", "isfr", "tmds";
+                        resets = <&ccu RST_BUS_HDMI1>;
+                        reset-names = "ctrl";
+                        phys = <&hdmi_phy>;
+                        phy-names = "hdmi-phy";
+                        status = "disabled";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                hdmi_in: port@0 {
+                                        reg = <0>;
+
+                                        hdmi_in_tcon1: endpoint {
+                                                remote-endpoint = <&tcon1_out_hdmi>;
+                                        };
+                                };
+
+                                hdmi_out: port@1 {
+                                        reg = <1>;
+                                };
+                        };
+                };
+
+                hdmi_phy: hdmi-phy@1ef0000 {
+                        compatible = "allwinner,sun50i-a64-hdmi-phy";
+                        reg = <0x01ef0000 0x10000>;
+                        clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
+                                 <&ccu 7>;
+                        clock-names = "bus", "mod", "pll-0";
+                        resets = <&ccu RST_BUS_HDMI0>;
+                        reset-names = "phy";
+                        #phy-cells = <0>;
+                };
+
                 rtc: rtc@1f00000 {
                         compatible = "allwinner,sun6i-a31-rtc";
                         reg = <0x01f00000 0x54>;
@@ -749,7 +936,7 @@
                         interrupt-controller;
                         #interrupt-cells = <3>;
 
-                        r_i2c_pins_a: i2c-a {
+                        r_i2c_pl89_pins: r-i2c-pl89-pins {
                                 pins = "PL8", "PL9";
                                 function = "s_i2c";
                         };
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dts
new file mode 100644
index 000000000000..2e2b14c0ae75
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dts
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2018 Chen-Yu Tsai <wens@csie.org>
+
+/dts-v1/;
+#include "sun50i-h5.dtsi"
+#include <arm/sunxi-bananapi-m2-plus-v1.2.dtsi>
+
+/ {
+        model = "Banana Pi BPI-M2-Plus v1.2 H5";
+        compatible = "bananapi,bpi-m2-plus-v1.2", "allwinner,sun50i-h5";
+};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts
new file mode 100644
index 000000000000..77661006dfba
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2018 Chen-Yu Tsai <wens@csie.org>
+
+/dts-v1/;
+#include "sun50i-h5.dtsi"
+#include <arm/sunxi-bananapi-m2-plus.dtsi>
+
+/ {
+        model = "Banana Pi BPI-M2-Plus H5";
+        compatible = "sinovoip,bpi-m2-plus", "allwinner,sun50i-h5";
+};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
index 62d646baac3c..b41dc1aab67d 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
@@ -92,6 +92,49 @@
                              <GIC_PPI 10
                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
         };
+
+        soc {
+                mali: gpu@1e80000 {
+                        compatible = "allwinner,sun50i-h5-mali", "arm,mali-450";
+                        reg = <0x01e80000 0x30000>;
+                        /*
+                         * While the datasheet lists an interrupt for the
+                         * PMU, the actual silicon does not have the PMU
+                         * block. Reads all return zero, and writes are
+                         * ignored.
+                         */
+                        interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "gp",
+                                          "gpmmu",
+                                          "pp",
+                                          "pp0",
+                                          "ppmmu0",
+                                          "pp1",
+                                          "ppmmu1",
+                                          "pp2",
+                                          "ppmmu2",
+                                          "pp3",
+                                          "ppmmu3",
+                                          "pmu";
+                        clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
+                        clock-names = "bus", "core";
+                        resets = <&ccu RST_BUS_GPU>;
+
+                        assigned-clocks = <&ccu CLK_GPU>;
+                        assigned-clock-rates = <384000000>;
+                };
+        };
 };
 
 &ccu {
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts
new file mode 100644
index 000000000000..0612c19cd994
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2018 Amarula Solutions
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+/dts-v1/;
+
+#include "sun50i-h6.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+        model = "OrangePi One Plus";
+        compatible = "xunlong,orangepi-one-plus", "allwinner,sun50i-h6";
+
+        aliases {
+                serial0 = &uart0;
+        };
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+};
+
+&mmc0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc0_pins>;
+        vmmc-supply = <&reg_cldo1>;
+        cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
+        bus-width = <4>;
+        status = "okay";
+};
+
+&r_i2c {
+        status = "okay";
+
+        axp805: pmic@36 {
+                compatible = "x-powers,axp805", "x-powers,axp806";
+                reg = <0x36>;
+                interrupt-parent = <&r_intc>;
+                interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+                interrupt-controller;
+                #interrupt-cells = <1>;
+                x-powers,self-working-mode;
+
+                regulators {
+                        reg_aldo1: aldo1 {
+                                regulator-always-on;
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-name = "vcc-pl";
+                        };
+
+                        reg_aldo2: aldo2 {
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-name = "vcc-ac200";
+                        };
+
+                        reg_aldo3: aldo3 {
+                                regulator-always-on;
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-name = "vcc25-dram";
+                        };
+
+                        reg_bldo1: bldo1 {
+                                regulator-always-on;
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-name = "vcc-bias-pll";
+                        };
+
+                        reg_bldo2: bldo2 {
+                                regulator-always-on;
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-name = "vcc-efuse-pcie-hdmi-io";
+                        };
+
+                        reg_bldo3: bldo3 {
+                                regulator-always-on;
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-name = "vcc-dcxoio";
+                        };
+
+                        bldo4 {
+                                /* unused */
+                        };
+
+                        reg_cldo1: cldo1 {
+                                regulator-always-on;
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-name = "vcc-3v3";
+                        };
+
+                        reg_cldo2: cldo2 {
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-name = "vcc-wifi-1";
+                        };
+
+                        reg_cldo3: cldo3 {
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-name = "vcc-wifi-2";
+                        };
+
+                        reg_dcdca: dcdca {
+                                regulator-always-on;
+                                regulator-min-microvolt = <810000>;
+                                regulator-max-microvolt = <1080000>;
+                                regulator-name = "vdd-cpu";
+                        };
+
+                        reg_dcdcc: dcdcc {
+                                regulator-min-microvolt = <810000>;
+                                regulator-max-microvolt = <1080000>;
+                                regulator-name = "vdd-gpu";
+                        };
+
+                        reg_dcdcd: dcdcd {
+                                regulator-always-on;
+                                regulator-min-microvolt = <960000>;
+                                regulator-max-microvolt = <960000>;
+                                regulator-name = "vdd-sys";
+                        };
+
+                        reg_dcdce: dcdce {
+                                regulator-always-on;
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-name = "vcc-dram";
+                        };
+
+                        sw {
+                                /* unused */
+                        };
+                };
+        };
+};
+
+&uart0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart0_ph_pins>;
+        status = "okay";
+};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index cfa5fffcf62b..040828d2e2c0 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -92,6 +92,29 @@
                 #size-cells = <1>;
                 ranges;
 
+                syscon: syscon@3000000 {
+                        compatible = "allwinner,sun50i-h6-system-control",
+                                     "allwinner,sun50i-a64-system-control";
+                        reg = <0x03000000 0x1000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        sram_c: sram@28000 {
+                                compatible = "mmio-sram";
+                                reg = <0x00028000 0x1e000>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0 0x00028000 0x1e000>;
+
+                                de2_sram: sram-section@0 {
+                                        compatible = "allwinner,sun50i-h6-sram-c",
+                                                     "allwinner,sun50i-a64-sram-c";
+                                        reg = <0x0000 0x1e000>;
+                                };
+                        };
+                };
+
                 ccu: clock@3001000 {
                         compatible = "allwinner,sun50i-h6-ccu";
                         reg = <0x03001000 0x1000>;
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index fb3d2ee77c56..8253a1a9e985 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -341,7 +341,7 @@
 
                 sysmgr: sysmgr@ffd12000 {
                         compatible = "altr,sys-mgr", "syscon";
-                        reg = <0xffd12000 0x1000>;
+                        reg = <0xffd12000 0x228>;
                 };
 
                 /* Local timer */
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
index 7c661753bfaf..2e3863ee12b3 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
@@ -21,6 +21,9 @@
 
         aliases {
                 serial0 = &uart0;
+                ethernet0 = &gmac0;
+                ethernet1 = &gmac1;
+                ethernet2 = &gmac2;
         };
 
         chosen {
@@ -124,6 +127,8 @@
 &i2c1 {
         status = "okay";
         clock-frequency = <100000>;
+        i2c-sda-falling-time-ns = <890>;  /* hcnt */
+        i2c-sdl-falling-time-ns = <890>;  /* lcnt */
 
         adc@14 {
                 compatible = "lltc,ltc2497";
diff --git a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi
index 125f4deb52fe..b664e7af74eb 100644
--- a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi
+++ b/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi
@@ -107,7 +107,7 @@
                         clock-names = "uartclk", "apb_pclk";
                 };
 
-                spi0: ssp@e1020000 {
+                spi0: spi@e1020000 {
                         status = "disabled";
                         compatible = "arm,pl022", "arm,primecell";
                         reg = <0 0xe1020000 0 0x1000>;
@@ -117,7 +117,7 @@
                         clock-names = "apb_pclk";
                 };
 
-                spi1: ssp@e1030000 {
+                spi1: spi@e1030000 {
                         status = "disabled";
                         compatible = "arm,pl022", "arm,primecell";
                         reg = <0 0xe1030000 0 0x1000>;
diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile
index a97c0e2d7bc6..c31f29d660de 100644
--- a/arch/arm64/boot/dts/amlogic/Makefile
+++ b/arch/arm64/boot/dts/amlogic/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 dtb-$(CONFIG_ARCH_MESON) += meson-axg-s400.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-g12a-u200.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nanopi-k2.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nexbox-a95x.dtb
 dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-odroidc2.dtb
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index d5c01427a5ca..18778ada7bd3 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -60,6 +60,55 @@
                 serial1 = &uart_A;
         };
 
+        linein: audio-codec@0 {
+                #sound-dai-cells = <0>;
+                compatible = "everest,es7241";
+                VDDA-supply = <&vcc_3v3>;
+                VDDP-supply = <&vcc_3v3>;
+                VDDD-supply = <&vcc_3v3>;
+                status = "okay";
+                sound-name-prefix = "Linein";
+        };
+
+        lineout: audio-codec@1 {
+                #sound-dai-cells = <0>;
+                compatible = "everest,es7154";
+                VDD-supply = <&vcc_3v3>;
+                PVDD-supply = <&vcc_5v>;
+                status = "okay";
+                sound-name-prefix = "Lineout";
+        };
+
+        spdif_dit: audio-codec@2 {
+                #sound-dai-cells = <0>;
+                compatible = "linux,spdif-dit";
+                status = "okay";
+                sound-name-prefix = "DIT";
+        };
+
+        dmics: audio-codec@3 {
+                #sound-dai-cells = <0>;
+                compatible = "dmic-codec";
+                num-channels = <7>;
+                wakeup-delay-ms = <50>;
+                status = "okay";
+                sound-name-prefix = "MIC";
+        };
+
+        emmc_pwrseq: emmc-pwrseq {
+                compatible = "mmc-pwrseq-emmc";
+                reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+        };
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x0 0x0 0x40000000>;
+        };
+
         main_12v: regulator-main_12v {
                 compatible = "regulator-fixed";
                 regulator-name = "12V";
@@ -68,15 +117,26 @@
                 regulator-always-on;
         };
 
-        vddio_boot: regulator-vddio_boot {
+        vcc_3v3: regulator-vcc_3v3 {
                 compatible = "regulator-fixed";
-                regulator-name = "VDDIO_BOOT";
-                regulator-min-microvolt = <1800000>;
-                regulator-max-microvolt = <1800000>;
+                regulator-name = "VCC_3V3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
                 vin-supply = <&vddao_3v3>;
                 regulator-always-on;
         };
 
+        vcc_5v: regulator-vcc_5v {
+                compatible = "regulator-fixed";
+                regulator-name = "VCC5V";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                vin-supply = <&main_12v>;
+
+                gpio = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+        };
+
         vddao_3v3: regulator-vddao_3v3 {
                 compatible = "regulator-fixed";
                 regulator-name = "VDDAO_3V3";
@@ -95,26 +155,15 @@
                 regulator-always-on;
         };
 
-        vcc_3v3: regulator-vcc_3v3 {
+        vddio_boot: regulator-vddio_boot {
                 compatible = "regulator-fixed";
-                regulator-name = "VCC_3V3";
-                regulator-min-microvolt = <3300000>;
-                regulator-max-microvolt = <3300000>;
+                regulator-name = "VDDIO_BOOT";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
                 vin-supply = <&vddao_3v3>;
                 regulator-always-on;
         };
 
-        vcc_5v: regulator-vcc_5v {
-                compatible = "regulator-fixed";
-                regulator-name = "VCC5V";
-                regulator-min-microvolt = <5000000>;
-                regulator-max-microvolt = <5000000>;
-                vin-supply = <&main_12v>;
-
-                gpio = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>;
-                enable-active-high;
-        };
-
         usb_pwr: regulator-usb_pwr {
                 compatible = "regulator-fixed";
                 regulator-name = "USB_PWR";
@@ -126,11 +175,6 @@
                 enable-active-high;
         };
 
-        emmc_pwrseq: emmc-pwrseq {
-                compatible = "mmc-pwrseq-emmc";
-                reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
-        };
-
         sdio_pwrseq: sdio-pwrseq {
                 compatible = "mmc-pwrseq-simple";
                 reset-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>;
@@ -138,13 +182,6 @@
                 clock-names = "ext_clock";
         };
 
-        wifi32k: wifi32k {
-                compatible = "pwm-clock";
-                #clock-cells = <0>;
-                clock-frequency = <32768>;
-                pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */
-        };
-
         speaker-leds {
                 compatible = "gpio-leds";
 
@@ -179,30 +216,129 @@
                 };
         };
 
-        linein: audio-codec@0 {
-                #sound-dai-cells = <0>;
-                compatible = "everest,es7241";
-                VDDA-supply = <&vcc_3v3>;
-                VDDP-supply = <&vcc_3v3>;
-                VDDD-supply = <&vcc_3v3>;
+        sound {
+                compatible = "amlogic,axg-sound-card";
+                model = "AXG-S400";
+                audio-aux-devs = <&tdmin_a>, <&tdmin_b>,  <&tdmin_c>,
+                                 <&tdmin_lb>, <&tdmout_c>;
+                audio-widgets = "Line", "Lineout",
+                                "Line", "Linein",
+                                "Speaker", "Speaker1 Left",
+                                "Speaker", "Speaker1 Right";
+                audio-routing = "TDMOUT_C IN 0", "FRDDR_A OUT 2",
+                                "SPDIFOUT IN 0", "FRDDR_A OUT 3",
+                                "TDMOUT_C IN 1", "FRDDR_B OUT 2",
+                                "SPDIFOUT IN 1", "FRDDR_B OUT 3",
+                                "TDMOUT_C IN 2", "FRDDR_C OUT 2",
+                                "SPDIFOUT IN 2", "FRDDR_C OUT 3",
+                                "TDM_C Playback", "TDMOUT_C OUT",
+                                "TDMIN_A IN 2", "TDM_C Capture",
+                                "TDMIN_A IN 5", "TDM_C Loopback",
+                                "TDMIN_B IN 2", "TDM_C Capture",
+                                "TDMIN_B IN 5", "TDM_C Loopback",
+                                "TDMIN_C IN 2", "TDM_C Capture",
+                                "TDMIN_C IN 5", "TDM_C Loopback",
+                                "TDMIN_LB IN 2", "TDM_C Loopback",
+                                "TDMIN_LB IN 5", "TDM_C Capture",
+                                "TODDR_A IN 0", "TDMIN_A OUT",
+                                "TODDR_B IN 0", "TDMIN_A OUT",
+                                "TODDR_C IN 0", "TDMIN_A OUT",
+                                "TODDR_A IN 1", "TDMIN_B OUT",
+                                "TODDR_B IN 1", "TDMIN_B OUT",
+                                "TODDR_C IN 1", "TDMIN_B OUT",
+                                "TODDR_A IN 2", "TDMIN_C OUT",
+                                "TODDR_B IN 2", "TDMIN_C OUT",
+                                "TODDR_C IN 2", "TDMIN_C OUT",
+                                "TODDR_A IN 4", "PDM Capture",
+                                "TODDR_B IN 4", "PDM Capture",
+                                "TODDR_C IN 4", "PDM Capture",
+                                "TODDR_A IN 6", "TDMIN_LB OUT",
+                                "TODDR_B IN 6", "TDMIN_LB OUT",
+                                "TODDR_C IN 6", "TDMIN_LB OUT",
+                                "Lineout", "Lineout AOUTL",
+                                "Lineout", "Lineout AOUTR",
+                                "Speaker1 Left", "SPK1 OUT_A",
+                                "Speaker1 Left", "SPK1 OUT_B",
+                                "Speaker1 Right", "SPK1 OUT_C",
+                                "Speaker1 Right", "SPK1 OUT_D",
+                                "Linein AINL", "Linein",
+                                "Linein AINR", "Linein";
+                assigned-clocks = <&clkc CLKID_HIFI_PLL>,
+                                  <&clkc CLKID_MPLL0>,
+                                  <&clkc CLKID_MPLL1>;
+                assigned-clock-parents = <0>, <0>, <0>;
+                assigned-clock-rates = <589824000>,
+                                       <270950400>,
+                                       <393216000>;
                 status = "okay";
-                sound-name-prefix = "Linein";
-        };
 
-        lineout: audio-codec@1 {
-                #sound-dai-cells = <0>;
-                compatible = "everest,es7154";
-                VDD-supply = <&vcc_3v3>;
-                PVDD-supply = <&vcc_5v>;
-                status = "okay";
-                sound-name-prefix = "Lineout";
+                dai-link@0 {
+                        sound-dai = <&frddr_a>;
+                };
+
+                dai-link@1 {
+                        sound-dai = <&frddr_b>;
+                };
+
+                dai-link@2 {
+                        sound-dai = <&frddr_c>;
+                };
+
+                dai-link@3 {
+                        sound-dai = <&toddr_a>;
+                };
+
+                dai-link@4 {
+                        sound-dai = <&toddr_b>;
+                };
+
+                dai-link@5 {
+                        sound-dai = <&toddr_c>;
+                };
+
+                dai-link@6 {
+                        sound-dai = <&tdmif_c>;
+                        dai-format = "i2s";
+                        dai-tdm-slot-tx-mask-2 = <1 1>;
+                        dai-tdm-slot-rx-mask-1 = <1 1>;
+                        mclk-fs = <256>;
+
+                        codec@0 {
+                                sound-dai = <&lineout>;
+                        };
+
+                        codec@1 {
+                                sound-dai = <&speaker_amp1>;
+                        };
+
+                        codec@2 {
+                                sound-dai = <&linein>;
+                        };
+
+                };
+
+                dai-link@7 {
+                        sound-dai = <&spdifout>;
+
+                        codec {
+                                sound-dai = <&spdif_dit>;
+                        };
+                };
+
+                dai-link@8 {
+                        sound-dai = <&pdm>;
+
+                        codec {
+                                sound-dai = <&dmics>;
+                        };
+                };
         };
 
-        spdif_dit: audio-codec@2 {
-                #sound-dai-cells = <0>;
-                compatible = "linux,spdif-dit";
-                status = "okay";
-                sound-name-prefix = "DIT";
+        wifi32k: wifi32k {
+                compatible = "pwm-clock";
+                #clock-cells = <0>;
+                clock-frequency = <32768>;
+                pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */
         };
 };
 
@@ -226,16 +362,16 @@
         };
 };
 
-&uart_A {
+&frddr_a {
         status = "okay";
-        pinctrl-0 = <&uart_a_pins>;
-        pinctrl-names = "default";
 };
 
-&uart_AO {
+&frddr_b {
+        status = "okay";
+};
+
+&frddr_c {
         status = "okay";
-        pinctrl-0 = <&uart_ao_a_pins>;
-        pinctrl-names = "default";
 };
 
 &ir {
@@ -260,6 +396,7 @@
                 PVDD_B-supply = <&main_12v>;
                 PVDD_C-supply = <&main_12v>;
                 PVDD_D-supply = <&main_12v>;
+                sound-name-prefix = "SPK1";
         };
 };
 
@@ -277,30 +414,22 @@
         };
 };
 
+&pdm {
+        pinctrl-0 = <&pdm_dclk_a14_pins>, <&pdm_din0_pins>,
+                    <&pdm_din1_pins>, <&pdm_din2_pins>, <&pdm_din3_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+};
+
 &pwm_ab {
         status = "okay";
         pinctrl-0 = <&pwm_a_x20_pins>;
         pinctrl-names = "default";
 };
 
-/* emmc storage */
-&sd_emmc_c {
+&saradc {
         status = "okay";
-        pinctrl-0 = <&emmc_pins>;
-        pinctrl-1 = <&emmc_clk_gate_pins>;
-        pinctrl-names = "default", "clk-gate";
-
-        bus-width = <8>;
-        cap-sd-highspeed;
-        cap-mmc-highspeed;
-        max-frequency = <180000000>;
-        non-removable;
-        disable-wp;
-        mmc-ddr-1_8v;
-        mmc-hs200-1_8v;
-
-        vmmc-supply = <&vcc_3v3>;
-        vqmmc-supply = <&vddio_boot>;
+        vref-supply = <&vddio_ao18>;
 };
 
 /* wifi module */
@@ -330,7 +459,96 @@
         };
 };
 
-&saradc {
+/* emmc storage */
+&sd_emmc_c {
+        status = "disabled";
+        pinctrl-0 = <&emmc_pins>;
+        pinctrl-1 = <&emmc_clk_gate_pins>;
+        pinctrl-names = "default", "clk-gate";
+
+        bus-width = <8>;
+        cap-sd-highspeed;
+        cap-mmc-highspeed;
+        max-frequency = <180000000>;
+        non-removable;
+        disable-wp;
+        mmc-ddr-1_8v;
+        mmc-hs200-1_8v;
+
+        mmc-pwrseq = <&emmc_pwrseq>;
+
+        vmmc-supply = <&vcc_3v3>;
+        vqmmc-supply = <&vddio_boot>;
+};
+
+&spdifout {
+        pinctrl-0 = <&spdif_out_a20_pins>;
+        pinctrl-names = "default";
         status = "okay";
-        vref-supply = <&vddio_ao18>;
+};
+
+&tdmif_a {
+        pinctrl-0 = <&tdma_sclk_pins>, <&tdma_fs_pins>,
+                    <&tdma_din0_pins>, <&tdma_dout0_x15_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+};
+
+&tdmif_b {
+        pinctrl-0 = <&tdmb_sclk_pins>, <&tdmb_fs_pins>,
+                    <&tdmb_din3_pins>, <&mclk_b_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+};
+
+&tdmif_c {
+        pinctrl-0 = <&tdmc_sclk_pins>, <&tdmc_fs_pins>,
+                    <&tdmc_din1_pins>, <&tdmc_dout2_pins>,
+                    <&mclk_c_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+};
+
+&tdmin_a {
+        status = "okay";
+};
+
+&tdmin_b {
+        status = "okay";
+};
+
+&tdmin_c {
+        status = "okay";
+};
+
+&tdmin_lb {
+        status = "okay";
+};
+
+&tdmout_c {
+        status = "okay";
+};
+
+&toddr_a {
+        status = "okay";
+};
+
+&toddr_b {
+        status = "okay";
+};
+
+&toddr_c {
+        status = "okay";
+};
+
+&uart_A {
+        status = "okay";
+        pinctrl-0 = <&uart_a_pins>;
+        pinctrl-names = "default";
+};
+
+&uart_AO {
+        status = "okay";
+        pinctrl-0 = <&uart_ao_a_pins>;
+        pinctrl-names = "default";
 };
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index c518130e5ce7..df017dbd2e57 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -3,13 +3,14 @@
  * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
  */
 
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/axg-aoclkc.h>
 #include <dt-bindings/clock/axg-audio-clkc.h>
 #include <dt-bindings/clock/axg-clkc.h>
-#include <dt-bindings/clock/axg-aoclkc.h>
+#include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/gpio/meson-axg-gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
 #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
 
 / {
@@ -19,22 +20,53 @@
         #address-cells = <2>;
         #size-cells = <2>;
 
-        reserved-memory {
-                #address-cells = <2>;
-                #size-cells = <2>;
-                ranges;
+        tdmif_a: audio-controller@0 {
+                compatible = "amlogic,axg-tdm-iface";
+                #sound-dai-cells = <0>;
+                sound-name-prefix = "TDM_A";
+                clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
+                         <&clkc_audio AUD_CLKID_MST_A_SCLK>,
+                         <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
+                clock-names = "mclk", "sclk", "lrclk";
+                status = "disabled";
+        };
 
-                /* 16 MiB reserved for Hardware ROM Firmware */
-                hwrom_reserved: hwrom@0 {
-                        reg = <0x0 0x0 0x0 0x1000000>;
-                        no-map;
-                };
+        tdmif_b: audio-controller@1 {
+                compatible = "amlogic,axg-tdm-iface";
+                #sound-dai-cells = <0>;
+                sound-name-prefix = "TDM_B";
+                clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
+                         <&clkc_audio AUD_CLKID_MST_B_SCLK>,
+                         <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
+                clock-names = "mclk", "sclk", "lrclk";
+                status = "disabled";
+        };
 
-                /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
-                secmon_reserved: secmon@5000000 {
-                        reg = <0x0 0x05000000 0x0 0x300000>;
-                        no-map;
-                };
+        tdmif_c: audio-controller@2 {
+                compatible = "amlogic,axg-tdm-iface";
+                #sound-dai-cells = <0>;
+                sound-name-prefix = "TDM_C";
+                clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
+                         <&clkc_audio AUD_CLKID_MST_C_SCLK>,
+                         <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
+                clock-names = "mclk", "sclk", "lrclk";
+                status = "disabled";
+        };
+
+        ao_alt_xtal: ao_alt_xtal-clk {
+                compatible = "fixed-clock";
+                clock-frequency = <32000000>;
+                clock-output-names = "ao_alt_xtal";
+                #clock-cells = <0>;
+        };
+
+        arm-pmu {
+                compatible = "arm,cortex-a53-pmu";
+                interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
         };
 
         cpus {
@@ -78,77 +110,27 @@
                 };
         };
 
-        arm-pmu {
-                compatible = "arm,cortex-a53-pmu";
-                interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
-                interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
-        };
-
         psci {
                 compatible = "arm,psci-1.0";
                 method = "smc";
         };
 
-        tdmif_a: audio-controller@0 {
-                compatible = "amlogic,axg-tdm-iface";
-                #sound-dai-cells = <0>;
-                sound-name-prefix = "TDM_A";
-                clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
-                         <&clkc_audio AUD_CLKID_MST_A_SCLK>,
-                         <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
-                clock-names = "mclk", "sclk", "lrclk";
-                status = "disabled";
-        };
-
-        tdmif_b: audio-controller@1 {
-                compatible = "amlogic,axg-tdm-iface";
-                #sound-dai-cells = <0>;
-                sound-name-prefix = "TDM_B";
-                clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
-                         <&clkc_audio AUD_CLKID_MST_B_SCLK>,
-                         <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
-                clock-names = "mclk", "sclk", "lrclk";
-                status = "disabled";
-        };
-
-        tdmif_c: audio-controller@2 {
-                compatible = "amlogic,axg-tdm-iface";
-                #sound-dai-cells = <0>;
-                sound-name-prefix = "TDM_C";
-                clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
-                         <&clkc_audio AUD_CLKID_MST_C_SCLK>,
-                         <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
-                clock-names = "mclk", "sclk", "lrclk";
-                status = "disabled";
-        };
-
-        timer {
-                compatible = "arm,armv8-timer";
-                interrupts = <GIC_PPI 13
-                        (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
-                             <GIC_PPI 14
-                        (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
-                             <GIC_PPI 11
-                        (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
-                             <GIC_PPI 10
-                        (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
-        };
+        reserved-memory {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
 
-        xtal: xtal-clk {
-                compatible = "fixed-clock";
-                clock-frequency = <24000000>;
-                clock-output-names = "xtal";
-                #clock-cells = <0>;
-        };
+                /* 16 MiB reserved for Hardware ROM Firmware */
+                hwrom_reserved: hwrom@0 {
+                        reg = <0x0 0x0 0x0 0x1000000>;
+                        no-map;
+                };
 
-        ao_alt_xtal: ao_alt_xtal-clk {
-                compatible = "fixed-clock";
-                clock-frequency = <32000000>;
-                clock-output-names = "ao_alt_xtal";
-                #clock-cells = <0>;
+                /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
+                secmon_reserved: secmon@5000000 {
+                        reg = <0x0 0x05000000 0x0 0x300000>;
+                        no-map;
+                };
         };
 
         soc {
@@ -157,310 +139,10 @@
                 #size-cells = <2>;
                 ranges;
 
-                apb: apb@ffe00000 {
-                        compatible = "simple-bus";
-                        reg = <0x0 0xffe00000 0x0 0x200000>;
-                        #address-cells = <2>;
-                        #size-cells = <2>;
-                        ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
-
-                        sd_emmc_b: sd@5000 {
-                                compatible = "amlogic,meson-axg-mmc";
-                                reg = <0x0 0x5000 0x0 0x800>;
-                                interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
-                                status = "disabled";
-                                clocks = <&clkc CLKID_SD_EMMC_B>,
-                                        <&clkc CLKID_SD_EMMC_B_CLK0>,
-                                        <&clkc CLKID_FCLK_DIV2>;
-                                clock-names = "core", "clkin0", "clkin1";
-                                resets = <&reset RESET_SD_EMMC_B>;
-                        };
-
-                        sd_emmc_c: mmc@7000 {
-                                compatible = "amlogic,meson-axg-mmc";
-                                reg = <0x0 0x7000 0x0 0x800>;
-                                interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
-                                status = "disabled";
-                                clocks = <&clkc CLKID_SD_EMMC_C>,
-                                        <&clkc CLKID_SD_EMMC_C_CLK0>,
-                                        <&clkc CLKID_FCLK_DIV2>;
-                                clock-names = "core", "clkin0", "clkin1";
-                                resets = <&reset RESET_SD_EMMC_C>;
-                        };
-                };
-
-                audio: bus@ff642000 {
-                        compatible = "simple-bus";
-                        reg = <0x0 0xff642000 0x0 0x2000>;
-                        #address-cells = <2>;
-                        #size-cells = <2>;
-                        ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
-
-                        clkc_audio: clock-controller@0 {
-                                compatible = "amlogic,axg-audio-clkc";
-                                reg = <0x0 0x0 0x0 0xb4>;
-                                #clock-cells = <1>;
-
-                                clocks = <&clkc CLKID_AUDIO>,
-                                         <&clkc CLKID_MPLL0>,
-                                         <&clkc CLKID_MPLL1>,
-                                         <&clkc CLKID_MPLL2>,
-                                         <&clkc CLKID_MPLL3>,
-                                         <&clkc CLKID_HIFI_PLL>,
-                                         <&clkc CLKID_FCLK_DIV3>,
-                                         <&clkc CLKID_FCLK_DIV4>,
-                                         <&clkc CLKID_GP0_PLL>;
-                                clock-names = "pclk",
-                                              "mst_in0",
-                                              "mst_in1",
-                                              "mst_in2",
-                                              "mst_in3",
-                                              "mst_in4",
-                                              "mst_in5",
-                                              "mst_in6",
-                                              "mst_in7";
-
-                                resets = <&reset RESET_AUDIO>;
-                        };
-
-                        arb: reset-controller@280 {
-                                compatible = "amlogic,meson-axg-audio-arb";
-                                reg = <0x0 0x280 0x0 0x4>;
-                                #reset-cells = <1>;
-                                clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
-                        };
-
-                        tdmin_a: audio-controller@300 {
-                                compatible = "amlogic,axg-tdmin";
-                                reg = <0x0 0x300 0x0 0x40>;
-                                sound-name-prefix = "TDMIN_A";
-                                clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
-                                         <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
-                                         <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
-                                         <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
-                                         <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
-                                clock-names = "pclk", "sclk", "sclk_sel",
-                                              "lrclk", "lrclk_sel";
-                                status = "disabled";
-                        };
-
-                        tdmin_b: audio-controller@340 {
-                                compatible = "amlogic,axg-tdmin";
-                                reg = <0x0 0x340 0x0 0x40>;
-                                sound-name-prefix = "TDMIN_B";
-                                clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
-                                         <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
-                                         <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
-                                         <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
-                                         <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
-                                clock-names = "pclk", "sclk", "sclk_sel",
-                                              "lrclk", "lrclk_sel";
-                                status = "disabled";
-                        };
-
-                        tdmin_c: audio-controller@380 {
-                                compatible = "amlogic,axg-tdmin";
-                                reg = <0x0 0x380 0x0 0x40>;
-                                sound-name-prefix = "TDMIN_C";
-                                clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
-                                         <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
-                                         <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
-                                         <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
-                                         <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
-                                clock-names = "pclk", "sclk", "sclk_sel",
-                                              "lrclk", "lrclk_sel";
-                                status = "disabled";
-                        };
-
-                        tdmin_lb: audio-controller@3c0 {
-                                compatible = "amlogic,axg-tdmin";
-                                reg = <0x0 0x3c0 0x0 0x40>;
-                                sound-name-prefix = "TDMIN_LB";
-                                clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
-                                         <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
-                                         <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
-                                         <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
-                                         <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
-                                clock-names = "pclk", "sclk", "sclk_sel",
-                                              "lrclk", "lrclk_sel";
-                                status = "disabled";
-                        };
-
-                        spdifout: audio-controller@480 {
-                                compatible = "amlogic,axg-spdifout";
-                                reg = <0x0 0x480 0x0 0x50>;
-                                #sound-dai-cells = <0>;
-                                sound-name-prefix = "SPDIFOUT";
-                                clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
-                                         <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
-                                clock-names = "pclk", "mclk";
-                                status = "disabled";
-                        };
-
-                        tdmout_a: audio-controller@500 {
-                                compatible = "amlogic,axg-tdmout";
-                                reg = <0x0 0x500 0x0 0x40>;
-                                sound-name-prefix = "TDMOUT_A";
-                                clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
-                                         <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
-                                         <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
-                                         <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
-                                         <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
-                                clock-names = "pclk", "sclk", "sclk_sel",
-                                              "lrclk", "lrclk_sel";
-                                status = "disabled";
-                        };
-
-                        tdmout_b: audio-controller@540 {
-                                compatible = "amlogic,axg-tdmout";
-                                reg = <0x0 0x540 0x0 0x40>;
-                                sound-name-prefix = "TDMOUT_B";
-                                clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
-                                         <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
-                                         <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
-                                         <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
-                                         <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
-                                clock-names = "pclk", "sclk", "sclk_sel",
-                                              "lrclk", "lrclk_sel";
-                                status = "disabled";
-                        };
-
-                        tdmout_c: audio-controller@580 {
-                                compatible = "amlogic,axg-tdmout";
-                                reg = <0x0 0x580 0x0 0x40>;
-                                sound-name-prefix = "TDMOUT_C";
-                                clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
-                                         <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
-                                         <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
-                                         <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
-                                         <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
-                                clock-names = "pclk", "sclk", "sclk_sel",
-                                              "lrclk", "lrclk_sel";
-                                status = "disabled";
-                        };
-                };
-
-                cbus: bus@ffd00000 {
-                        compatible = "simple-bus";
-                        reg = <0x0 0xffd00000 0x0 0x25000>;
-                        #address-cells = <2>;
-                        #size-cells = <2>;
-                        ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
-
-                        gpio_intc: interrupt-controller@f080 {
-                                compatible = "amlogic,meson-gpio-intc";
-                                reg = <0x0 0xf080 0x0 0x10>;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                                amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
-                                status = "disabled";
-                        };
-
-                        pwm_ab: pwm@1b000 {
-                                compatible = "amlogic,meson-axg-ee-pwm";
-                                reg = <0x0 0x1b000 0x0 0x20>;
-                                #pwm-cells = <3>;
-                                status = "disabled";
-                        };
-
-                        pwm_cd: pwm@1a000 {
-                                compatible = "amlogic,meson-axg-ee-pwm";
-                                reg = <0x0 0x1a000 0x0 0x20>;
-                                #pwm-cells = <3>;
-                                status = "disabled";
-                        };
-
-                        reset: reset-controller@1004 {
-                                compatible = "amlogic,meson-axg-reset";
-                                reg = <0x0 0x01004 0x0 0x9c>;
-                                #reset-cells = <1>;
-                        };
-
-                        spicc0: spi@13000 {
-                                compatible = "amlogic,meson-axg-spicc";
-                                reg = <0x0 0x13000 0x0 0x3c>;
-                                interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clkc CLKID_SPICC0>;
-                                clock-names = "core";
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                status = "disabled";
-                        };
-
-                        spicc1: spi@15000 {
-                                compatible = "amlogic,meson-axg-spicc";
-                                reg = <0x0 0x15000 0x0 0x3c>;
-                                interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clkc CLKID_SPICC1>;
-                                clock-names = "core";
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                status = "disabled";
-                        };
-
-                        i2c0: i2c@1f000 {
-                                compatible = "amlogic,meson-axg-i2c";
-                                reg = <0x0 0x1f000 0x0 0x20>;
-                                interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
-                                clocks = <&clkc CLKID_I2C>;
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                status = "disabled";
-                        };
-
-                        i2c1: i2c@1e000 {
-                                compatible = "amlogic,meson-axg-i2c";
-                                reg = <0x0 0x1e000 0x0 0x20>;
-                                interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
-                                clocks = <&clkc CLKID_I2C>;
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                status = "disabled";
-                        };
-
-                        i2c2: i2c@1d000 {
-                                compatible = "amlogic,meson-axg-i2c";
-                                reg = <0x0 0x1d000 0x0 0x20>;
-                                interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
-                                clocks = <&clkc CLKID_I2C>;
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                status = "disabled";
-                        };
-
-                        i2c3: i2c@1c000 {
-                                compatible = "amlogic,meson-axg-i2c";
-                                reg = <0x0 0x1c000 0x0 0x20>;
-                                interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
-                                clocks = <&clkc CLKID_I2C>;
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                status = "disabled";
-                        };
-
-                        uart_A: serial@24000 {
-                                compatible = "amlogic,meson-gx-uart";
-                                reg = <0x0 0x24000 0x0 0x18>;
-                                interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
-                                status = "disabled";
-                                clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
-                                clock-names = "xtal", "pclk", "baud";
-                        };
-
-                        uart_B: serial@23000 {
-                                compatible = "amlogic,meson-gx-uart";
-                                reg = <0x0 0x23000 0x0 0x18>;
-                                interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
-                                status = "disabled";
-                                clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
-                                clock-names = "xtal", "pclk", "baud";
-                        };
-                };
-
                 ethmac: ethernet@ff3f0000 {
-                        compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
+                        compatible = "amlogic,meson-axg-dwmac", "snps,dwmac";
                         reg = <0x0 0xff3f0000 0x0 0x10000
-                                0x0 0xff634540 0x0 0x8>;
+                               0x0 0xff634540 0x0 0x8>;
                         interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
                         interrupt-names = "macirq";
                         clocks = <&clkc CLKID_ETH>,
@@ -470,54 +152,26 @@
                         status = "disabled";
                 };
 
-                gic: interrupt-controller@ffc01000 {
-                        compatible = "arm,gic-400";
-                        reg = <0x0 0xffc01000 0 0x1000>,
-                              <0x0 0xffc02000 0 0x2000>,
-                              <0x0 0xffc04000 0 0x2000>,
-                              <0x0 0xffc06000 0 0x2000>;
-                        interrupt-controller;
-                        interrupts = <GIC_PPI 9
-                                (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
-                        #interrupt-cells = <3>;
-                        #address-cells = <0>;
-                };
-
-                hiubus: bus@ff63c000 {
-                        compatible = "simple-bus";
-                        reg = <0x0 0xff63c000 0x0 0x1c00>;
-                        #address-cells = <2>;
-                        #size-cells = <2>;
-                        ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
-
-                        sysctrl: system-controller@0 {
-                                compatible = "amlogic,meson-axg-hhi-sysctrl", "syscon", "simple-mfd";
-                                reg = <0 0 0 0x400>;
-
-                                clkc: clock-controller {
-                                        compatible = "amlogic,axg-clkc";
-                                        #clock-cells = <1>;
-                                };
-                        };
-                };
-
-                mailbox: mailbox@ff63dc00 {
-                        compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
-                        reg = <0 0xff63dc00 0 0x400>;
-                        interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
-                                     <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
-                                     <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
-                        #mbox-cells = <1>;
+                pdm: audio-controller@ff632000 {
+                        compatible = "amlogic,axg-pdm";
+                        reg = <0x0 0xff632000 0x0 0x34>;
+                        #sound-dai-cells = <0>;
+                        sound-name-prefix = "PDM";
+                        clocks = <&clkc_audio AUD_CLKID_PDM>,
+                                 <&clkc_audio AUD_CLKID_PDM_DCLK>,
+                                 <&clkc_audio AUD_CLKID_PDM_SYSCLK>;
+                        clock-names = "pclk", "dclk", "sysclk";
+                        status = "disabled";
                 };
 
-                periphs: periphs@ff634000 {
+                periphs: bus@ff634000 {
                         compatible = "simple-bus";
                         reg = <0x0 0xff634000 0x0 0x2000>;
                         #address-cells = <2>;
                         #size-cells = <2>;
                         ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
 
-                        hwrng: rng {
+                        hwrng: rng@18 {
                                 compatible = "amlogic,meson-rng";
                                 reg = <0x0 0x18 0x0 0x4>;
                                 clocks = <&clkc CLKID_RNG0>;
@@ -532,28 +186,92 @@
 
                                 gpio: bank@480 {
                                         reg = <0x0 0x00480 0x0 0x40>,
-                                                <0x0 0x004e8 0x0 0x14>,
-                                                <0x0 0x00520 0x0 0x14>,
-                                                <0x0 0x00430 0x0 0x3c>;
+                                              <0x0 0x004e8 0x0 0x14>,
+                                              <0x0 0x00520 0x0 0x14>,
+                                              <0x0 0x00430 0x0 0x3c>;
                                         reg-names = "mux", "pull", "pull-enable", "gpio";
                                         gpio-controller;
                                         #gpio-cells = <2>;
                                         gpio-ranges = <&pinctrl_periphs 0 0 86>;
                                 };
 
+                                i2c0_pins: i2c0 {
+                                        mux {
+                                                groups = "i2c0_sck",
+                                                         "i2c0_sda";
+                                                function = "i2c0";
+                                        };
+                                };
+
+                                i2c1_x_pins: i2c1_x {
+                                        mux {
+                                                groups = "i2c1_sck_x",
+                                                         "i2c1_sda_x";
+                                                function = "i2c1";
+                                        };
+                                };
+
+                                i2c1_z_pins: i2c1_z {
+                                        mux {
+                                                groups = "i2c1_sck_z",
+                                                         "i2c1_sda_z";
+                                                function = "i2c1";
+                                        };
+                                };
+
+                                i2c2_a_pins: i2c2_a {
+                                        mux {
+                                                groups = "i2c2_sck_a",
+                                                         "i2c2_sda_a";
+                                                function = "i2c2";
+                                        };
+                                };
+
+                                i2c2_x_pins: i2c2_x {
+                                        mux {
+                                                groups = "i2c2_sck_x",
+                                                         "i2c2_sda_x";
+                                                function = "i2c2";
+                                        };
+                                };
+
+                                i2c3_a6_pins: i2c3_a6 {
+                                        mux {
+                                                groups = "i2c3_sda_a6",
+                                                         "i2c3_sck_a7";
+                                                function = "i2c3";
+                                        };
+                                };
+
+                                i2c3_a12_pins: i2c3_a12 {
+                                        mux {
+                                                groups = "i2c3_sda_a12",
+                                                         "i2c3_sck_a13";
+                                                function = "i2c3";
+                                        };
+                                };
+
+                                i2c3_a19_pins: i2c3_a19 {
+                                        mux {
+                                                groups = "i2c3_sda_a19",
+                                                         "i2c3_sck_a20";
+                                                function = "i2c3";
+                                        };
+                                };
+
                                 emmc_pins: emmc {
                                         mux {
                                                 groups = "emmc_nand_d0",
-                                                        "emmc_nand_d1",
-                                                        "emmc_nand_d2",
-                                                        "emmc_nand_d3",
-                                                        "emmc_nand_d4",
-                                                        "emmc_nand_d5",
-                                                        "emmc_nand_d6",
-                                                        "emmc_nand_d7",
-                                                        "emmc_clk",
-                                                        "emmc_cmd",
-                                                        "emmc_ds";
+                                                         "emmc_nand_d1",
+                                                         "emmc_nand_d2",
+                                                         "emmc_nand_d3",
+                                                         "emmc_nand_d4",
+                                                         "emmc_nand_d5",
+                                                         "emmc_nand_d6",
+                                                         "emmc_nand_d7",
+                                                         "emmc_clk",
+                                                         "emmc_cmd",
+                                                         "emmc_ds";
                                                 function = "emmc";
                                         };
                                 };
@@ -569,40 +287,57 @@
                                         };
                                 };
 
-                                sdio_pins: sdio {
+                                eth_rgmii_x_pins: eth-x-rgmii {
                                         mux {
-                                                groups = "sdio_d0",
-                                                        "sdio_d1",
-                                                        "sdio_d2",
-                                                        "sdio_d3",
-                                                        "sdio_cmd",
-                                                        "sdio_clk";
-                                                function = "sdio";
+                                                groups = "eth_mdio_x",
+                                                         "eth_mdc_x",
+                                                         "eth_rgmii_rx_clk_x",
+                                                         "eth_rx_dv_x",
+                                                         "eth_rxd0_x",
+                                                         "eth_rxd1_x",
+                                                         "eth_rxd2_rgmii",
+                                                         "eth_rxd3_rgmii",
+                                                         "eth_rgmii_tx_clk",
+                                                         "eth_txen_x",
+                                                         "eth_txd0_x",
+                                                         "eth_txd1_x",
+                                                         "eth_txd2_rgmii",
+                                                         "eth_txd3_rgmii";
+                                                function = "eth";
                                         };
                                 };
 
-                                sdio_clk_gate_pins: sdio_clk_gate {
+                                eth_rgmii_y_pins: eth-y-rgmii {
                                         mux {
-                                                groups = "GPIOX_4";
-                                                function = "gpio_periphs";
-                                        };
-                                        cfg-pull-down {
-                                                pins = "GPIOX_4";
-                                                bias-pull-down;
+                                                groups = "eth_mdio_y",
+                                                         "eth_mdc_y",
+                                                         "eth_rgmii_rx_clk_y",
+                                                         "eth_rx_dv_y",
+                                                         "eth_rxd0_y",
+                                                         "eth_rxd1_y",
+                                                         "eth_rxd2_rgmii",
+                                                         "eth_rxd3_rgmii",
+                                                         "eth_rgmii_tx_clk",
+                                                         "eth_txen_y",
+                                                         "eth_txd0_y",
+                                                         "eth_txd1_y",
+                                                         "eth_txd2_rgmii",
+                                                         "eth_txd3_rgmii";
+                                                function = "eth";
                                         };
                                 };
 
                                 eth_rmii_x_pins: eth-x-rmii {
                                         mux {
                                                 groups = "eth_mdio_x",
-                                                       "eth_mdc_x",
-                                                       "eth_rgmii_rx_clk_x",
-                                                       "eth_rx_dv_x",
-                                                       "eth_rxd0_x",
-                                                       "eth_rxd1_x",
-                                                       "eth_txen_x",
-                                                       "eth_txd0_x",
-                                                       "eth_txd1_x";
+                                                         "eth_mdc_x",
+                                                         "eth_rgmii_rx_clk_x",
+                                                         "eth_rx_dv_x",
+                                                         "eth_rxd0_x",
+                                                         "eth_rxd1_x",
+                                                         "eth_txen_x",
+                                                         "eth_txd0_x",
+                                                         "eth_txd1_x";
                                                 function = "eth";
                                         };
                                 };
@@ -610,55 +345,29 @@
                                 eth_rmii_y_pins: eth-y-rmii {
                                         mux {
                                                 groups = "eth_mdio_y",
-                                                       "eth_mdc_y",
-                                                       "eth_rgmii_rx_clk_y",
-                                                       "eth_rx_dv_y",
-                                                       "eth_rxd0_y",
-                                                       "eth_rxd1_y",
-                                                       "eth_txen_y",
-                                                       "eth_txd0_y",
-                                                       "eth_txd1_y";
+                                                         "eth_mdc_y",
+                                                         "eth_rgmii_rx_clk_y",
+                                                         "eth_rx_dv_y",
+                                                         "eth_rxd0_y",
+                                                         "eth_rxd1_y",
+                                                         "eth_txen_y",
+                                                         "eth_txd0_y",
+                                                         "eth_txd1_y";
                                                 function = "eth";
                                         };
                                 };
 
-                                eth_rgmii_x_pins: eth-x-rgmii {
+                                mclk_b_pins: mclk_b {
                                         mux {
-                                                groups = "eth_mdio_x",
-                                                       "eth_mdc_x",
-                                                       "eth_rgmii_rx_clk_x",
-                                                       "eth_rx_dv_x",
-                                                       "eth_rxd0_x",
-                                                       "eth_rxd1_x",
-                                                       "eth_rxd2_rgmii",
-                                                       "eth_rxd3_rgmii",
-                                                       "eth_rgmii_tx_clk",
-                                                       "eth_txen_x",
-                                                       "eth_txd0_x",
-                                                       "eth_txd1_x",
-                                                       "eth_txd2_rgmii",
-                                                       "eth_txd3_rgmii";
-                                                function = "eth";
+                                                groups = "mclk_b";
+                                                function = "mclk_b";
                                         };
                                 };
 
-                                eth_rgmii_y_pins: eth-y-rgmii {
+                                mclk_c_pins: mclk_c {
                                         mux {
-                                                groups = "eth_mdio_y",
-                                                       "eth_mdc_y",
-                                                       "eth_rgmii_rx_clk_y",
-                                                       "eth_rx_dv_y",
-                                                       "eth_rxd0_y",
-                                                       "eth_rxd1_y",
-                                                       "eth_rxd2_rgmii",
-                                                       "eth_rxd3_rgmii",
-                                                       "eth_rgmii_tx_clk",
-                                                       "eth_txen_y",
-                                                       "eth_txd0_y",
-                                                       "eth_txd1_y",
-                                                       "eth_txd2_rgmii",
-                                                       "eth_txd3_rgmii";
-                                                function = "eth";
+                                                groups = "mclk_c";
+                                                function = "mclk_c";
                                         };
                                 };
 
@@ -788,6 +497,29 @@
                                         };
                                 };
 
+                                sdio_pins: sdio {
+                                        mux {
+                                                groups = "sdio_d0",
+                                                         "sdio_d1",
+                                                         "sdio_d2",
+                                                         "sdio_d3",
+                                                         "sdio_cmd",
+                                                         "sdio_clk";
+                                                function = "sdio";
+                                        };
+                                };
+
+                                sdio_clk_gate_pins: sdio_clk_gate {
+                                        mux {
+                                                groups = "GPIOX_4";
+                                                function = "gpio_periphs";
+                                        };
+                                        cfg-pull-down {
+                                                pins = "GPIOX_4";
+                                                bias-pull-down;
+                                        };
+                                };
+
                                 spdif_in_z_pins: spdif_in_z {
                                         mux {
                                                 groups = "spdif_in_z";
@@ -823,13 +555,6 @@
                                         };
                                 };
 
-                                spdif_out_z_pins: spdif_out_z {
-                                        mux {
-                                                groups = "spdif_out_z";
-                                                function = "spdif_out";
-                                        };
-                                };
-
                                 spdif_out_a1_pins: spdif_out_a1 {
                                         mux {
                                                 groups = "spdif_out_a1";
@@ -858,11 +583,18 @@
                                         };
                                 };
 
+                                spdif_out_z_pins: spdif_out_z {
+                                        mux {
+                                                groups = "spdif_out_z";
+                                                function = "spdif_out";
+                                        };
+                                };
+
                                 spi0_pins: spi0 {
                                         mux {
                                                 groups = "spi0_miso",
-                                                        "spi0_mosi",
-                                                        "spi0_clk";
+                                                         "spi0_mosi",
+                                                         "spi0_clk";
                                                 function = "spi0";
                                         };
                                 };
@@ -888,12 +620,11 @@
                                         };
                                 };
 
-
                                 spi1_a_pins: spi1_a {
                                         mux {
                                                 groups = "spi1_miso_a",
-                                                        "spi1_mosi_a",
-                                                        "spi1_clk_a";
+                                                         "spi1_mosi_a",
+                                                         "spi1_clk_a";
                                                 function = "spi1";
                                         };
                                 };
@@ -915,8 +646,8 @@
                                 spi1_x_pins: spi1_x {
                                         mux {
                                                 groups = "spi1_miso_x",
-                                                        "spi1_mosi_x",
-                                                        "spi1_clk_x";
+                                                         "spi1_mosi_x",
+                                                         "spi1_clk_x";
                                                 function = "spi1";
                                         };
                                 };
@@ -928,145 +659,52 @@
                                         };
                                 };
 
-                                i2c0_pins: i2c0 {
-                                        mux {
-                                                groups = "i2c0_sck",
-                                                        "i2c0_sda";
-                                                function = "i2c0";
-                                        };
-                                };
-
-                                i2c1_z_pins: i2c1_z {
-                                        mux {
-                                                groups = "i2c1_sck_z",
-                                                        "i2c1_sda_z";
-                                                function = "i2c1";
-                                        };
-                                };
-
-                                i2c1_x_pins: i2c1_x {
-                                        mux {
-                                                groups = "i2c1_sck_x",
-                                                        "i2c1_sda_x";
-                                                function = "i2c1";
-                                        };
-                                };
-
-                                i2c2_x_pins: i2c2_x {
-                                        mux {
-                                                groups = "i2c2_sck_x",
-                                                        "i2c2_sda_x";
-                                                function = "i2c2";
-                                        };
-                                };
-
-                                i2c2_a_pins: i2c2_a {
-                                        mux {
-                                                groups = "i2c2_sck_a",
-                                                        "i2c2_sda_a";
-                                                function = "i2c2";
-                                        };
-                                };
-
-                                i2c3_a6_pins: i2c3_a6 {
-                                        mux {
-                                                groups = "i2c3_sda_a6",
-                                                        "i2c3_sck_a7";
-                                                function = "i2c3";
-                                        };
-                                };
-
-                                i2c3_a12_pins: i2c3_a12 {
-                                        mux {
-                                                groups = "i2c3_sda_a12",
-                                                        "i2c3_sck_a13";
-                                                function = "i2c3";
-                                        };
-                                };
-
-                                i2c3_a19_pins: i2c3_a19 {
-                                        mux {
-                                                groups = "i2c3_sda_a19",
-                                                        "i2c3_sck_a20";
-                                                function = "i2c3";
-                                        };
-                                };
-
-                                uart_a_pins: uart_a {
-                                        mux {
-                                                groups = "uart_tx_a",
-                                                        "uart_rx_a";
-                                                function = "uart_a";
-                                        };
-                                };
-
-                                uart_a_cts_rts_pins: uart_a_cts_rts {
-                                        mux {
-                                                groups = "uart_cts_a",
-                                                        "uart_rts_a";
-                                                function = "uart_a";
-                                        };
-                                };
-
-                                uart_b_x_pins: uart_b_x {
-                                        mux {
-                                                groups = "uart_tx_b_x",
-                                                        "uart_rx_b_x";
-                                                function = "uart_b";
-                                        };
-                                };
-
-                                uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
+                                tdma_din0_pins: tdma_din0 {
                                         mux {
-                                                groups = "uart_cts_b_x",
-                                                        "uart_rts_b_x";
-                                                function = "uart_b";
+                                                groups = "tdma_din0";
+                                                function = "tdma";
                                         };
                                 };
 
-                                uart_b_z_pins: uart_b_z {
+                                tdma_dout0_x14_pins: tdma_dout0_x14 {
                                         mux {
-                                                groups = "uart_tx_b_z",
-                                                        "uart_rx_b_z";
-                                                function = "uart_b";
+                                                groups = "tdma_dout0_x14";
+                                                function = "tdma";
                                         };
                                 };
 
-                                uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
+                                tdma_dout0_x15_pins: tdma_dout0_x15 {
                                         mux {
-                                                groups = "uart_cts_b_z",
-                                                        "uart_rts_b_z";
-                                                function = "uart_b";
+                                                groups = "tdma_dout0_x15";
+                                                function = "tdma";
                                         };
                                 };
 
-                                uart_ao_b_z_pins: uart_ao_b_z {
+                                tdma_dout1_pins: tdma_dout1 {
                                         mux {
-                                                groups = "uart_ao_tx_b_z",
-                                                        "uart_ao_rx_b_z";
-                                                function = "uart_ao_b_z";
+                                                groups = "tdma_dout1";
+                                                function = "tdma";
                                         };
                                 };
 
-                                uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
+                                tdma_din1_pins: tdma_din1 {
                                         mux {
-                                                groups = "uart_ao_cts_b_z",
-                                                        "uart_ao_rts_b_z";
-                                                function = "uart_ao_b_z";
+                                                groups = "tdma_din1";
+                                                function = "tdma";
                                         };
                                 };
 
-                                mclk_b_pins: mclk_b {
+                                tdma_fs_pins: tdma_fs {
                                         mux {
-                                                groups = "mclk_b";
-                                                function = "mclk_b";
+                                                groups = "tdma_fs";
+                                                function = "tdma";
                                         };
                                 };
 
-                                mclk_c_pins: mclk_c {
+                                tdma_fs_slv_pins: tdma_fs_slv {
                                         mux {
-                                                groups = "mclk_c";
-                                                function = "mclk_c";
+                                                groups = "tdma_fs_slv";
+                                                function = "tdma";
                                         };
                                 };
 
@@ -1084,65 +722,58 @@
                                         };
                                 };
 
-                                tdma_fs_pins: tdma_fs {
-                                        mux {
-                                                groups = "tdma_fs";
-                                                function = "tdma";
-                                        };
-                                };
-
-                                tdma_fs_slv_pins: tdma_fs_slv {
+                                tdmb_din0_pins: tdmb_din0 {
                                         mux {
-                                                groups = "tdma_fs_slv";
-                                                function = "tdma";
+                                                groups = "tdmb_din0";
+                                                function = "tdmb";
                                         };
                                 };
 
-                                tdma_din0_pins: tdma_din0 {
+                                tdmb_din1_pins: tdmb_din1 {
                                         mux {
-                                                groups = "tdma_din0";
-                                                function = "tdma";
+                                                groups = "tdmb_din1";
+                                                function = "tdmb";
                                         };
                                 };
 
-                                tdma_dout0_x14_pins: tdma_dout0_x14 {
+                                tdmb_din2_pins: tdmb_din2 {
                                         mux {
-                                                groups = "tdma_dout0_x14";
-                                                function = "tdma";
+                                                groups = "tdmb_din2";
+                                                function = "tdmb";
                                         };
                                 };
 
-                                tdma_dout0_x15_pins: tdma_dout0_x15 {
+                                tdmb_din3_pins: tdmb_din3 {
                                         mux {
-                                                groups = "tdma_dout0_x15";
-                                                function = "tdma";
+                                                groups = "tdmb_din3";
+                                                function = "tdmb";
                                         };
                                 };
 
-                                tdma_dout1_pins: tdma_dout1 {
+                                tdmb_dout0_pins: tdmb_dout0 {
                                         mux {
-                                                groups = "tdma_dout1";
-                                                function = "tdma";
+                                                groups = "tdmb_dout0";
+                                                function = "tdmb";
                                         };
                                 };
 
-                                tdma_din1_pins: tdma_din1 {
+                                tdmb_dout1_pins: tdmb_dout1 {
                                         mux {
-                                                groups = "tdma_din1";
-                                                function = "tdma";
+                                                groups = "tdmb_dout1";
+                                                function = "tdmb";
                                         };
                                 };
 
-                                tdmb_sclk_pins: tdmb_sclk {
+                                tdmb_dout2_pins: tdmb_dout2 {
                                         mux {
-                                                groups = "tdmb_sclk";
+                                                groups = "tdmb_dout2";
                                                 function = "tdmb";
                                         };
                                 };
 
-                                tdmb_sclk_slv_pins: tdmb_sclk_slv {
+                                tdmb_dout3_pins: tdmb_dout3 {
                                         mux {
-                                                groups = "tdmb_sclk_slv";
+                                                groups = "tdmb_dout3";
                                                 function = "tdmb";
                                         };
                                 };
@@ -1161,163 +792,412 @@
                                         };
                                 };
 
-                                tdmb_din0_pins: tdmb_din0 {
+                                tdmb_sclk_pins: tdmb_sclk {
                                         mux {
-                                                groups = "tdmb_din0";
+                                                groups = "tdmb_sclk";
                                                 function = "tdmb";
                                         };
                                 };
 
-                                tdmb_dout0_pins: tdmb_dout0 {
+                                tdmb_sclk_slv_pins: tdmb_sclk_slv {
                                         mux {
-                                                groups = "tdmb_dout0";
+                                                groups = "tdmb_sclk_slv";
                                                 function = "tdmb";
                                         };
                                 };
 
-                                tdmb_din1_pins: tdmb_din1 {
+                                tdmc_fs_pins: tdmc_fs {
                                         mux {
-                                                groups = "tdmb_din1";
-                                                function = "tdmb";
+                                                groups = "tdmc_fs";
+                                                function = "tdmc";
                                         };
                                 };
 
-                                tdmb_dout1_pins: tdmb_dout1 {
+                                tdmc_fs_slv_pins: tdmc_fs_slv {
                                         mux {
-                                                groups = "tdmb_dout1";
-                                                function = "tdmb";
+                                                groups = "tdmc_fs_slv";
+                                                function = "tdmc";
                                         };
                                 };
 
-                                tdmb_din2_pins: tdmb_din2 {
+                                tdmc_sclk_pins: tdmc_sclk {
                                         mux {
-                                                groups = "tdmb_din2";
-                                                function = "tdmb";
+                                                groups = "tdmc_sclk";
+                                                function = "tdmc";
                                         };
                                 };
 
-                                tdmb_dout2_pins: tdmb_dout2 {
+                                tdmc_sclk_slv_pins: tdmc_sclk_slv {
                                         mux {
-                                                groups = "tdmb_dout2";
-                                                function = "tdmb";
+                                                groups = "tdmc_sclk_slv";
+                                                function = "tdmc";
                                         };
                                 };
 
-                                tdmb_din3_pins: tdmb_din3 {
+                                tdmc_din0_pins: tdmc_din0 {
                                         mux {
-                                                groups = "tdmb_din3";
-                                                function = "tdmb";
+                                                groups = "tdmc_din0";
+                                                function = "tdmc";
                                         };
                                 };
 
-                                tdmb_dout3_pins: tdmb_dout3 {
+                                tdmc_din1_pins: tdmc_din1 {
                                         mux {
-                                                groups = "tdmb_dout3";
-                                                function = "tdmb";
+                                                groups = "tdmc_din1";
+                                                function = "tdmc";
                                         };
                                 };
 
-                                tdmc_sclk_pins: tdmc_sclk {
+                                tdmc_din2_pins: tdmc_din2 {
                                         mux {
-                                                groups = "tdmc_sclk";
+                                                groups = "tdmc_din2";
                                                 function = "tdmc";
                                         };
                                 };
 
-                                tdmc_sclk_slv_pins: tdmc_sclk_slv {
+                                tdmc_din3_pins: tdmc_din3 {
                                         mux {
-                                                groups = "tdmc_sclk_slv";
+                                                groups = "tdmc_din3";
                                                 function = "tdmc";
                                         };
                                 };
 
-                                tdmc_fs_pins: tdmc_fs {
+                                tdmc_dout0_pins: tdmc_dout0 {
                                         mux {
-                                                groups = "tdmc_fs";
+                                                groups = "tdmc_dout0";
                                                 function = "tdmc";
                                         };
                                 };
 
-                                tdmc_fs_slv_pins: tdmc_fs_slv {
+                                tdmc_dout1_pins: tdmc_dout1 {
                                         mux {
-                                                groups = "tdmc_fs_slv";
+                                                groups = "tdmc_dout1";
                                                 function = "tdmc";
                                         };
                                 };
 
-                                tdmc_din0_pins: tdmc_din0 {
+                                tdmc_dout2_pins: tdmc_dout2 {
                                         mux {
-                                                groups = "tdmc_din0";
+                                                groups = "tdmc_dout2";
                                                 function = "tdmc";
                                         };
                                 };
 
-                                tdmc_dout0_pins: tdmc_dout0 {
+                                tdmc_dout3_pins: tdmc_dout3 {
                                         mux {
-                                                groups = "tdmc_dout0";
+                                                groups = "tdmc_dout3";
                                                 function = "tdmc";
                                         };
                                 };
 
-                                tdmc_din1_pins: tdmc_din1 {
+                                uart_a_pins: uart_a {
                                         mux {
-                                                groups = "tdmc_din1";
-                                                function = "tdmc";
+                                                groups = "uart_tx_a",
+                                                         "uart_rx_a";
+                                                function = "uart_a";
                                         };
                                 };
 
-                                tdmc_dout1_pins: tdmc_dout1 {
+                                uart_a_cts_rts_pins: uart_a_cts_rts {
                                         mux {
-                                                groups = "tdmc_dout1";
-                                                function = "tdmc";
+                                                groups = "uart_cts_a",
+                                                         "uart_rts_a";
+                                                function = "uart_a";
                                         };
                                 };
 
-                                tdmc_din2_pins: tdmc_din2 {
+                                uart_b_x_pins: uart_b_x {
                                         mux {
-                                                groups = "tdmc_din2";
-                                                function = "tdmc";
+                                                groups = "uart_tx_b_x",
+                                                         "uart_rx_b_x";
+                                                function = "uart_b";
                                         };
                                 };
 
-                                tdmc_dout2_pins: tdmc_dout2 {
+                                uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
                                         mux {
-                                                groups = "tdmc_dout2";
-                                                function = "tdmc";
+                                                groups = "uart_cts_b_x",
+                                                         "uart_rts_b_x";
+                                                function = "uart_b";
                                         };
                                 };
 
-                                tdmc_din3_pins: tdmc_din3 {
+                                uart_b_z_pins: uart_b_z {
                                         mux {
-                                                groups = "tdmc_din3";
-                                                function = "tdmc";
+                                                groups = "uart_tx_b_z",
+                                                         "uart_rx_b_z";
+                                                function = "uart_b";
                                         };
                                 };
 
-                                tdmc_dout3_pins: tdmc_dout3 {
+                                uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
                                         mux {
-                                                groups = "tdmc_dout3";
-                                                function = "tdmc";
+                                                groups = "uart_cts_b_z",
+                                                         "uart_rts_b_z";
+                                                function = "uart_b";
+                                        };
+                                };
+
+                                uart_ao_b_z_pins: uart_ao_b_z {
+                                        mux {
+                                                groups = "uart_ao_tx_b_z",
+                                                         "uart_ao_rx_b_z";
+                                                function = "uart_ao_b_z";
+                                        };
+                                };
+
+                                uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
+                                        mux {
+                                                groups = "uart_ao_cts_b_z",
+                                                         "uart_ao_rts_b_z";
+                                                function = "uart_ao_b_z";
                                         };
                                 };
                         };
                 };
 
-                sram: sram@fffc0000 {
-                        compatible = "amlogic,meson-axg-sram", "mmio-sram";
-                        reg = <0x0 0xfffc0000 0x0 0x20000>;
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        ranges = <0 0x0 0xfffc0000 0x20000>;
+                hiubus: bus@ff63c000 {
+                        compatible = "simple-bus";
+                        reg = <0x0 0xff63c000 0x0 0x1c00>;
+                        #address-cells = <2>;
+                        #size-cells = <2>;
+                        ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
 
-                        cpu_scp_lpri: scp-shmem@0 {
-                                compatible = "amlogic,meson-axg-scp-shmem";
-                                reg = <0x13000 0x400>;
+                        sysctrl: system-controller@0 {
+                                compatible = "amlogic,meson-axg-hhi-sysctrl",
+                                             "simple-mfd", "syscon";
+                                reg = <0 0 0 0x400>;
+
+                                clkc: clock-controller {
+                                        compatible = "amlogic,axg-clkc";
+                                        #clock-cells = <1>;
+                                };
                         };
+                };
 
-                        cpu_scp_hpri: scp-shmem@200 {
-                                compatible = "amlogic,meson-axg-scp-shmem";
-                                reg = <0x13400 0x400>;
+                mailbox: mailbox@ff63dc00 {
+                        compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
+                        reg = <0 0xff63dc00 0 0x400>;
+                        interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
+                                     <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
+                                     <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
+                        #mbox-cells = <1>;
+                };
+
+                audio: bus@ff642000 {
+                        compatible = "simple-bus";
+                        reg = <0x0 0xff642000 0x0 0x2000>;
+                        #address-cells = <2>;
+                        #size-cells = <2>;
+                        ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
+
+                        clkc_audio: clock-controller@0 {
+                                compatible = "amlogic,axg-audio-clkc";
+                                reg = <0x0 0x0 0x0 0xb4>;
+                                #clock-cells = <1>;
+
+                                clocks = <&clkc CLKID_AUDIO>,
+                                         <&clkc CLKID_MPLL0>,
+                                         <&clkc CLKID_MPLL1>,
+                                         <&clkc CLKID_MPLL2>,
+                                         <&clkc CLKID_MPLL3>,
+                                         <&clkc CLKID_HIFI_PLL>,
+                                         <&clkc CLKID_FCLK_DIV3>,
+                                         <&clkc CLKID_FCLK_DIV4>,
+                                         <&clkc CLKID_GP0_PLL>;
+                                clock-names = "pclk",
+                                              "mst_in0",
+                                              "mst_in1",
+                                              "mst_in2",
+                                              "mst_in3",
+                                              "mst_in4",
+                                              "mst_in5",
+                                              "mst_in6",
+                                              "mst_in7";
+
+                                resets = <&reset RESET_AUDIO>;
+                        };
+
+                        toddr_a: audio-controller@100 {
+                                compatible = "amlogic,axg-toddr";
+                                reg = <0x0 0x100 0x0 0x1c>;
+                                #sound-dai-cells = <0>;
+                                sound-name-prefix = "TODDR_A";
+                                interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
+                                clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
+                                resets = <&arb AXG_ARB_TODDR_A>;
+                                status = "disabled";
+                        };
+
+                        toddr_b: audio-controller@140 {
+                                compatible = "amlogic,axg-toddr";
+                                reg = <0x0 0x140 0x0 0x1c>;
+                                #sound-dai-cells = <0>;
+                                sound-name-prefix = "TODDR_B";
+                                interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
+                                clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
+                                resets = <&arb AXG_ARB_TODDR_B>;
+                                status = "disabled";
+                        };
+
+                        toddr_c: audio-controller@180 {
+                                compatible = "amlogic,axg-toddr";
+                                reg = <0x0 0x180 0x0 0x1c>;
+                                #sound-dai-cells = <0>;
+                                sound-name-prefix = "TODDR_C";
+                                interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
+                                clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
+                                resets = <&arb AXG_ARB_TODDR_C>;
+                                status = "disabled";
+                        };
+
+                        frddr_a: audio-controller@1c0 {
+                                compatible = "amlogic,axg-frddr";
+                                reg = <0x0 0x1c0 0x0 0x1c>;
+                                #sound-dai-cells = <0>;
+                                sound-name-prefix = "FRDDR_A";
+                                interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
+                                clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
+                                resets = <&arb AXG_ARB_FRDDR_A>;
+                                status = "disabled";
+                        };
+
+                        frddr_b: audio-controller@200 {
+                                compatible = "amlogic,axg-frddr";
+                                reg = <0x0 0x200 0x0 0x1c>;
+                                #sound-dai-cells = <0>;
+                                sound-name-prefix = "FRDDR_B";
+                                interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
+                                clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
+                                resets = <&arb AXG_ARB_FRDDR_B>;
+                                status = "disabled";
+                        };
+
+                        frddr_c: audio-controller@240 {
+                                compatible = "amlogic,axg-frddr";
+                                reg = <0x0 0x240 0x0 0x1c>;
+                                #sound-dai-cells = <0>;
+                                sound-name-prefix = "FRDDR_C";
+                                interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
+                                clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
+                                resets = <&arb AXG_ARB_FRDDR_C>;
+                                status = "disabled";
+                        };
+
+                        arb: reset-controller@280 {
+                                compatible = "amlogic,meson-axg-audio-arb";
+                                reg = <0x0 0x280 0x0 0x4>;
+                                #reset-cells = <1>;
+                                clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
+                        };
+
+                        tdmin_a: audio-controller@300 {
+                                compatible = "amlogic,axg-tdmin";
+                                reg = <0x0 0x300 0x0 0x40>;
+                                sound-name-prefix = "TDMIN_A";
+                                clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
+                                         <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
+                                         <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
+                                         <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
+                                         <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
+                                clock-names = "pclk", "sclk", "sclk_sel",
+                                              "lrclk", "lrclk_sel";
+                                status = "disabled";
+                        };
+
+                        tdmin_b: audio-controller@340 {
+                                compatible = "amlogic,axg-tdmin";
+                                reg = <0x0 0x340 0x0 0x40>;
+                                sound-name-prefix = "TDMIN_B";
+                                clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
+                                         <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
+                                         <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
+                                         <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
+                                         <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
+                                clock-names = "pclk", "sclk", "sclk_sel",
+                                              "lrclk", "lrclk_sel";
+                                status = "disabled";
+                        };
+
+                        tdmin_c: audio-controller@380 {
+                                compatible = "amlogic,axg-tdmin";
+                                reg = <0x0 0x380 0x0 0x40>;
+                                sound-name-prefix = "TDMIN_C";
+                                clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
+                                         <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
+                                         <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
+                                         <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
+                                         <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
+                                clock-names = "pclk", "sclk", "sclk_sel",
+                                              "lrclk", "lrclk_sel";
+                                status = "disabled";
+                        };
+
+                        tdmin_lb: audio-controller@3c0 {
+                                compatible = "amlogic,axg-tdmin";
+                                reg = <0x0 0x3c0 0x0 0x40>;
+                                sound-name-prefix = "TDMIN_LB";
+                                clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
+                                         <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
+                                         <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
+                                         <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
+                                         <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
+                                clock-names = "pclk", "sclk", "sclk_sel",
+                                              "lrclk", "lrclk_sel";
+                                status = "disabled";
+                        };
+
+                        spdifout: audio-controller@480 {
+                                compatible = "amlogic,axg-spdifout";
+                                reg = <0x0 0x480 0x0 0x50>;
+                                #sound-dai-cells = <0>;
+                                sound-name-prefix = "SPDIFOUT";
+                                clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
+                                         <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
+                                clock-names = "pclk", "mclk";
+                                status = "disabled";
+                        };
+
+                        tdmout_a: audio-controller@500 {
+                                compatible = "amlogic,axg-tdmout";
+                                reg = <0x0 0x500 0x0 0x40>;
+                                sound-name-prefix = "TDMOUT_A";
+                                clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
+                                         <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
+                                         <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
+                                         <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
+                                         <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
+                                clock-names = "pclk", "sclk", "sclk_sel",
+                                              "lrclk", "lrclk_sel";
+                                status = "disabled";
+                        };
+
+                        tdmout_b: audio-controller@540 {
+                                compatible = "amlogic,axg-tdmout";
+                                reg = <0x0 0x540 0x0 0x40>;
+                                sound-name-prefix = "TDMOUT_B";
+                                clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
+                                         <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
+                                         <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
+                                         <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
+                                         <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
+                                clock-names = "pclk", "sclk", "sclk_sel",
+                                              "lrclk", "lrclk_sel";
+                                status = "disabled";
+                        };
+
+                        tdmout_c: audio-controller@580 {
+                                compatible = "amlogic,axg-tdmout";
+                                reg = <0x0 0x580 0x0 0x40>;
+                                sound-name-prefix = "TDMOUT_C";
+                                clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
+                                         <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
+                                         <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
+                                         <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
+                                         <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
+                                clock-names = "pclk", "sclk", "sclk_sel",
+                                              "lrclk", "lrclk_sel";
+                                status = "disabled";
                         };
                 };
 
@@ -1329,7 +1209,7 @@
                         ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
 
                         sysctrl_AO: sys-ctrl@0 {
-                                compatible = "amlogic,meson-axg-ao-sysctrl", "syscon", "simple-mfd";
+                                compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon";
                                 reg =  <0x0 0x0 0x0 0x100>;
 
                                 clkc_AO: clock-controller {
@@ -1347,8 +1227,8 @@
 
                                 gpio_ao: bank@14 {
                                         reg = <0x0 0x00014 0x0 0x8>,
-                                                <0x0 0x0002c 0x0 0x4>,
-                                                <0x0 0x00024 0x0 0x8>;
+                                              <0x0 0x0002c 0x0 0x4>,
+                                              <0x0 0x00024 0x0 0x8>;
                                         reg-names = "mux", "pull", "gpio";
                                         gpio-controller;
                                         #gpio-cells = <2>;
@@ -1407,7 +1287,7 @@
                                 uart_ao_a_pins: uart_ao_a {
                                         mux {
                                                 groups = "uart_ao_tx_a",
-                                                        "uart_ao_rx_a";
+                                                         "uart_ao_rx_a";
                                                 function = "uart_ao_a";
                                         };
                                 };
@@ -1415,7 +1295,7 @@
                                 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
                                         mux {
                                                 groups = "uart_ao_cts_a",
-                                                        "uart_ao_rts_a";
+                                                         "uart_ao_rts_a";
                                                 function = "uart_ao_a";
                                         };
                                 };
@@ -1423,7 +1303,7 @@
                                 uart_ao_b_pins: uart_ao_b {
                                         mux {
                                                 groups = "uart_ao_tx_b",
-                                                        "uart_ao_rx_b";
+                                                         "uart_ao_rx_b";
                                                 function = "uart_ao_b";
                                         };
                                 };
@@ -1431,7 +1311,7 @@
                                 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
                                         mux {
                                                 groups = "uart_ao_cts_b",
-                                                        "uart_ao_rts_b";
+                                                         "uart_ao_rts_b";
                                                 function = "uart_ao_b";
                                         };
                                 };
@@ -1443,13 +1323,6 @@
                                 amlogic,has-chip-id;
                         };
 
-                        pwm_AO_ab: pwm@7000 {
-                                compatible = "amlogic,meson-axg-ao-pwm";
-                                reg = <0x0 0x07000 0x0 0x20>;
-                                #pwm-cells = <3>;
-                                status = "disabled";
-                        };
-
                         pwm_AO_cd: pwm@2000 {
                                 compatible = "amlogic,meson-axg-ao-pwm";
                                 reg = <0x0 0x02000  0x0 0x20>;
@@ -1457,16 +1330,6 @@
                                 status = "disabled";
                         };
 
-                        i2c_AO: i2c@5000 {
-                                compatible = "amlogic,meson-axg-i2c";
-                                reg = <0x0 0x05000 0x0 0x20>;
-                                interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
-                                clocks = <&clkc CLKID_AO_I2C>;
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                status = "disabled";
-                        };
-
                         uart_AO: serial@3000 {
                                 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
                                 reg = <0x0 0x3000 0x0 0x18>;
@@ -1485,6 +1348,23 @@
                                 status = "disabled";
                         };
 
+                        i2c_AO: i2c@5000 {
+                                compatible = "amlogic,meson-axg-i2c";
+                                reg = <0x0 0x05000 0x0 0x20>;
+                                interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
+                                clocks = <&clkc CLKID_AO_I2C>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
+
+                        pwm_AO_ab: pwm@7000 {
+                                compatible = "amlogic,meson-axg-ao-pwm";
+                                reg = <0x0 0x07000 0x0 0x20>;
+                                #pwm-cells = <3>;
+                                status = "disabled";
+                        };
+
                         ir: ir@8000 {
                                 compatible = "amlogic,meson-gxbb-ir";
                                 reg = <0x0 0x8000 0x0 0x20>;
@@ -1499,12 +1379,211 @@
                                 #io-channel-cells = <1>;
                                 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
                                 clocks = <&xtal>,
-                                        <&clkc_AO CLKID_AO_SAR_ADC>,
-                                        <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
-                                        <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
+                                         <&clkc_AO CLKID_AO_SAR_ADC>,
+                                         <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
+                                         <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
                                 clock-names = "clkin", "core", "adc_clk", "adc_sel";
                                 status = "disabled";
                         };
                 };
+
+                gic: interrupt-controller@ffc01000 {
+                        compatible = "arm,gic-400";
+                        reg = <0x0 0xffc01000 0 0x1000>,
+                              <0x0 0xffc02000 0 0x2000>,
+                              <0x0 0xffc04000 0 0x2000>,
+                              <0x0 0xffc06000 0 0x2000>;
+                        interrupt-controller;
+                        interrupts = <GIC_PPI 9
+                                (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+                        #interrupt-cells = <3>;
+                        #address-cells = <0>;
+                };
+
+                cbus: bus@ffd00000 {
+                        compatible = "simple-bus";
+                        reg = <0x0 0xffd00000 0x0 0x25000>;
+                        #address-cells = <2>;
+                        #size-cells = <2>;
+                        ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
+
+                        reset: reset-controller@1004 {
+                                compatible = "amlogic,meson-axg-reset";
+                                reg = <0x0 0x01004 0x0 0x9c>;
+                                #reset-cells = <1>;
+                        };
+
+                        gpio_intc: interrupt-controller@f080 {
+                                compatible = "amlogic,meson-gpio-intc";
+                                reg = <0x0 0xf080 0x0 0x10>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
+                                status = "disabled";
+                        };
+
+                        pwm_ab: pwm@1b000 {
+                                compatible = "amlogic,meson-axg-ee-pwm";
+                                reg = <0x0 0x1b000 0x0 0x20>;
+                                #pwm-cells = <3>;
+                                status = "disabled";
+                        };
+
+                        pwm_cd: pwm@1a000 {
+                                compatible = "amlogic,meson-axg-ee-pwm";
+                                reg = <0x0 0x1a000 0x0 0x20>;
+                                #pwm-cells = <3>;
+                                status = "disabled";
+                        };
+
+                        spicc0: spi@13000 {
+                                compatible = "amlogic,meson-axg-spicc";
+                                reg = <0x0 0x13000 0x0 0x3c>;
+                                interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clkc CLKID_SPICC0>;
+                                clock-names = "core";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
+
+                        spicc1: spi@15000 {
+                                compatible = "amlogic,meson-axg-spicc";
+                                reg = <0x0 0x15000 0x0 0x3c>;
+                                interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clkc CLKID_SPICC1>;
+                                clock-names = "core";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
+
+                        i2c3: i2c@1c000 {
+                                compatible = "amlogic,meson-axg-i2c";
+                                reg = <0x0 0x1c000 0x0 0x20>;
+                                interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
+                                clocks = <&clkc CLKID_I2C>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
+
+                        i2c2: i2c@1d000 {
+                                compatible = "amlogic,meson-axg-i2c";
+                                reg = <0x0 0x1d000 0x0 0x20>;
+                                interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
+                                clocks = <&clkc CLKID_I2C>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
+
+                        i2c1: i2c@1e000 {
+                                compatible = "amlogic,meson-axg-i2c";
+                                reg = <0x0 0x1e000 0x0 0x20>;
+                                interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
+                                clocks = <&clkc CLKID_I2C>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
+
+                        i2c0: i2c@1f000 {
+                                compatible = "amlogic,meson-axg-i2c";
+                                reg = <0x0 0x1f000 0x0 0x20>;
+                                interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
+                                clocks = <&clkc CLKID_I2C>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
+
+                        uart_B: serial@23000 {
+                                compatible = "amlogic,meson-gx-uart";
+                                reg = <0x0 0x23000 0x0 0x18>;
+                                interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
+                                status = "disabled";
+                                clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
+                                clock-names = "xtal", "pclk", "baud";
+                        };
+
+                        uart_A: serial@24000 {
+                                compatible = "amlogic,meson-gx-uart";
+                                reg = <0x0 0x24000 0x0 0x18>;
+                                interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
+                                status = "disabled";
+                                clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
+                                clock-names = "xtal", "pclk", "baud";
+                        };
+                };
+
+                apb: bus@ffe00000 {
+                        compatible = "simple-bus";
+                        reg = <0x0 0xffe00000 0x0 0x200000>;
+                        #address-cells = <2>;
+                        #size-cells = <2>;
+                        ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
+
+                        sd_emmc_b: sd@5000 {
+                                compatible = "amlogic,meson-axg-mmc";
+                                reg = <0x0 0x5000 0x0 0x800>;
+                                interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
+                                status = "disabled";
+                                clocks = <&clkc CLKID_SD_EMMC_B>,
+                                        <&clkc CLKID_SD_EMMC_B_CLK0>,
+                                        <&clkc CLKID_FCLK_DIV2>;
+                                clock-names = "core", "clkin0", "clkin1";
+                                resets = <&reset RESET_SD_EMMC_B>;
+                        };
+
+                        sd_emmc_c: mmc@7000 {
+                                compatible = "amlogic,meson-axg-mmc";
+                                reg = <0x0 0x7000 0x0 0x800>;
+                                interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
+                                status = "disabled";
+                                clocks = <&clkc CLKID_SD_EMMC_C>,
+                                        <&clkc CLKID_SD_EMMC_C_CLK0>,
+                                        <&clkc CLKID_FCLK_DIV2>;
+                                clock-names = "core", "clkin0", "clkin1";
+                                resets = <&reset RESET_SD_EMMC_C>;
+                        };
+                };
+
+                sram: sram@fffc0000 {
+                        compatible = "amlogic,meson-axg-sram", "mmio-sram";
+                        reg = <0x0 0xfffc0000 0x0 0x20000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x0 0xfffc0000 0x20000>;
+
+                        cpu_scp_lpri: scp-shmem@0 {
+                                compatible = "amlogic,meson-axg-scp-shmem";
+                                reg = <0x13000 0x400>;
+                        };
+
+                        cpu_scp_hpri: scp-shmem@200 {
+                                compatible = "amlogic,meson-axg-scp-shmem";
+                                reg = <0x13400 0x400>;
+                        };
+                };
+        };
+
+        timer {
+                compatible = "arm,armv8-timer";
+                interrupts = <GIC_PPI 13
+                        (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 14
+                        (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 11
+                        (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 10
+                        (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
+        };
+
+        xtal: xtal-clk {
+                compatible = "fixed-clock";
+                clock-frequency = <24000000>;
+                clock-output-names = "xtal";
+                #clock-cells = <0>;
         };
 };
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
new file mode 100644
index 000000000000..c44dbdddf2cf
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "meson-g12a.dtsi"
+
+/ {
+        compatible = "amlogic,u200", "amlogic,g12a";
+        model = "Amlogic Meson G12A U200 Development Board";
+
+        aliases {
+                serial0 = &uart_AO;
+        };
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x0 0x0 0x40000000>;
+        };
+};
+
+&uart_AO {
+        status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
new file mode 100644
index 000000000000..3b82a975c663
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
@@ -0,0 +1,172 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+        compatible = "amlogic,g12a";
+
+        interrupt-parent = <&gic>;
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        cpus {
+                #address-cells = <0x2>;
+                #size-cells = <0x0>;
+
+                cpu0: cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a53", "arm,armv8";
+                        reg = <0x0 0x0>;
+                        enable-method = "psci";
+                        next-level-cache = <&l2>;
+                };
+
+                cpu1: cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a53", "arm,armv8";
+                        reg = <0x0 0x1>;
+                        enable-method = "psci";
+                        next-level-cache = <&l2>;
+                };
+
+                cpu2: cpu@2 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a53", "arm,armv8";
+                        reg = <0x0 0x2>;
+                        enable-method = "psci";
+                        next-level-cache = <&l2>;
+                };
+
+                cpu3: cpu@3 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a53", "arm,armv8";
+                        reg = <0x0 0x3>;
+                        enable-method = "psci";
+                        next-level-cache = <&l2>;
+                };
+
+                l2: l2-cache0 {
+                        compatible = "cache";
+                };
+        };
+
+        psci {
+                compatible = "arm,psci-1.0";
+                method = "smc";
+        };
+
+        reserved-memory {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
+
+                /* 3 MiB reserved for ARM Trusted Firmware (BL31) */
+                secmon_reserved: secmon@5000000 {
+                        reg = <0x0 0x05000000 0x0 0x300000>;
+                        no-map;
+                };
+        };
+
+        soc {
+                compatible = "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
+
+                periphs: periphs@ff634000 {
+                        compatible = "simple-bus";
+                        reg = <0x0 0xff634000 0x0 0x2000>;
+                        #address-cells = <2>;
+                        #size-cells = <2>;
+                        ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
+                };
+
+                hiubus: bus@ff63c000 {
+                        compatible = "simple-bus";
+                        reg = <0x0 0xff63c000 0x0 0x1c00>;
+                        #address-cells = <2>;
+                        #size-cells = <2>;
+                        ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
+                };
+
+                aobus: bus@ff800000 {
+                        compatible = "simple-bus";
+                        reg = <0x0 0xff800000 0x0 0x100000>;
+                        #address-cells = <2>;
+                        #size-cells = <2>;
+                        ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
+
+                        uart_AO: serial@3000 {
+                                compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
+                                reg = <0x0 0x3000 0x0 0x18>;
+                                interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
+                                clocks = <&xtal>, <&xtal>, <&xtal>;
+                                clock-names = "xtal", "pclk", "baud";
+                                status = "disabled";
+                        };
+
+                        uart_AO_B: serial@4000 {
+                                compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
+                                reg = <0x0 0x4000 0x0 0x18>;
+                                interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
+                                clocks = <&xtal>, <&xtal>, <&xtal>;
+                                clock-names = "xtal", "pclk", "baud";
+                                status = "disabled";
+                        };
+                };
+
+                gic: interrupt-controller@ffc01000 {
+                        compatible = "arm,gic-400";
+                        reg = <0x0 0xffc01000 0 0x1000>,
+                              <0x0 0xffc02000 0 0x2000>,
+                              <0x0 0xffc04000 0 0x2000>,
+                              <0x0 0xffc06000 0 0x2000>;
+                        interrupt-controller;
+                        interrupts = <GIC_PPI 9
+                                (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+                        #interrupt-cells = <3>;
+                        #address-cells = <0>;
+                };
+
+                cbus: bus@ffd00000 {
+                        compatible = "simple-bus";
+                        reg = <0x0 0xffd00000 0x0 0x25000>;
+                        #address-cells = <2>;
+                        #size-cells = <2>;
+                        ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
+                };
+
+                apb: apb@ffe00000 {
+                        compatible = "simple-bus";
+                        reg = <0x0 0xffe00000 0x0 0x200000>;
+                        #address-cells = <2>;
+                        #size-cells = <2>;
+                        ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
+                };
+        };
+
+        timer {
+                compatible = "arm,armv8-timer";
+                interrupts = <GIC_PPI 13
+                        (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 14
+                        (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 11
+                        (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 10
+                        (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
+        };
+
+        xtal: xtal-clk {
+                compatible = "fixed-clock";
+                clock-frequency = <24000000>;
+                clock-output-names = "xtal";
+                #clock-cells = <0>;
+        };
+
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index b8dc4dbb391b..f1e5cdbade5e 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -44,7 +44,7 @@
                 linux,cma {
                         compatible = "shared-dma-pool";
                         reusable;
-                        size = <0x0 0xbc00000>;
+                        size = <0x0 0x10000000>;
                         alignment = <0x0 0x400000>;
                         linux,cma-default;
                 };
@@ -344,7 +344,7 @@
                         ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
 
                         sysctrl_AO: sys-ctrl@0 {
-                                compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
+                                compatible = "amlogic,meson-gx-ao-sysctrl", "simple-mfd", "syscon";
                                 reg =  <0x0 0x0 0x0 0x100>;
 
                                 pwrc_vpu: power-controller-vpu {
@@ -423,6 +423,19 @@
                         };
                 };
 
+                dmcbus: bus@c8838000 {
+                        compatible = "simple-bus";
+                        reg = <0x0 0xc8838000 0x0 0x400>;
+                        #address-cells = <2>;
+                        #size-cells = <2>;
+                        ranges = <0x0 0x0 0x0 0xc8838000 0x0 0x400>;
+
+                        canvas: video-lut@48 {
+                                compatible = "amlogic,canvas";
+                                reg = <0x0 0x48 0x0 0x14>;
+                        };
+                };
+
                 hiubus: bus@c883c000 {
                         compatible = "simple-bus";
                         reg = <0x0 0xc883c000 0x0 0x2000>;
@@ -431,7 +444,7 @@
                         ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
 
                         sysctrl: system-controller@0 {
-                                compatible = "amlogic,meson-gx-hhi-sysctrl", "syscon", "simple-mfd";
+                                compatible = "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon";
                                 reg = <0 0 0 0x400>;
                         };
 
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 98cbba6809ca..1ade7e486828 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -390,7 +390,7 @@
                         };
                 };
 
-                spi_pins: spi {
+                spi_pins: spi-pins {
                         mux {
                                 groups = "spi_miso",
                                         "spi_mosi",
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
index f63bceb88caa..90a56af967a7 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
@@ -13,7 +13,7 @@
 
 / {
         compatible = "libretech,cc", "amlogic,s905x", "amlogic,meson-gxl";
-        model = "Libre Technology CC";
+        model = "Libre Computer Board AML-S905X-CC";
 
         aliases {
                 serial0 = &uart_AO;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
index c87a80e9bcc6..8f0bb3c44bd6 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
@@ -337,7 +337,7 @@
                         };
                 };
 
-                spi_pins: spi {
+                spi_pins: spi-pins {
                         mux {
                                 groups = "spi_miso",
                                         "spi_mosi",
diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
index ce56a4acda4f..ed774ee8f659 100644
--- a/arch/arm64/boot/dts/arm/juno-base.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
@@ -115,22 +115,17 @@
                 clocks = <&soc_smc50mhz>;
                 clock-names = "apb_pclk";
                 power-domains = <&scpi_devpd 0>;
-                ports {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
 
-                        /* input port */
-                        port@0 {
-                                reg = <0>;
+                in-ports {
+                        port {
                                 etf0_in_port: endpoint {
-                                        slave-mode;
                                         remote-endpoint = <&main_funnel_out_port>;
                                 };
                         };
+                };
 
-                        /* output port */
-                        port@1 {
-                                reg = <0>;
+                out-ports {
+                        port {
                                 etf0_out_port: endpoint {
                                 };
                         };
@@ -144,10 +139,11 @@
                 clocks = <&soc_smc50mhz>;
                 clock-names = "apb_pclk";
                 power-domains = <&scpi_devpd 0>;
-                port {
-                        tpiu_in_port: endpoint {
-                                slave-mode;
-                                remote-endpoint = <&replicator_out_port0>;
+                in-ports {
+                        port {
+                                tpiu_in_port: endpoint {
+                                        remote-endpoint = <&replicator_out_port0>;
+                                };
                         };
                 };
         };
@@ -160,31 +156,29 @@
                 clocks = <&soc_smc50mhz>;
                 clock-names = "apb_pclk";
                 power-domains = <&scpi_devpd 0>;
-                ports {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
 
-                        /* output port */
-                        port@0 {
-                                reg = <0>;
+                out-ports {
+                        port {
                                 main_funnel_out_port: endpoint {
                                         remote-endpoint = <&etf0_in_port>;
                                 };
                         };
+                };
 
-                        /* input ports */
-                        port@1 {
+                main_funnel_in_ports: in-ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@0 {
                                 reg = <0>;
                                 main_funnel_in_port0: endpoint {
-                                        slave-mode;
                                         remote-endpoint = <&cluster0_funnel_out_port>;
                                 };
                         };
 
-                        port@2 {
+                        port@1 {
                                 reg = <1>;
                                 main_funnel_in_port1: endpoint {
-                                        slave-mode;
                                         remote-endpoint = <&cluster1_funnel_out_port>;
                                 };
                         };
@@ -199,10 +193,12 @@
                 clocks = <&soc_smc50mhz>;
                 clock-names = "apb_pclk";
                 power-domains = <&scpi_devpd 0>;
-                port {
-                        etr_in_port: endpoint {
-                                slave-mode;
-                                remote-endpoint = <&replicator_out_port1>;
+                arm,scatter-gather;
+                in-ports {
+                        port {
+                                etr_in_port: endpoint {
+                                        remote-endpoint = <&replicator_out_port1>;
+                                };
                         };
                 };
         };
@@ -216,8 +212,10 @@
                 clocks = <&soc_smc50mhz>;
                 clock-names = "apb_pclk";
                 power-domains = <&scpi_devpd 0>;
-                port {
-                        stm_out_port: endpoint {
+                out-ports {
+                        port {
+                                stm_out_port: endpoint {
+                                };
                         };
                 };
         };
@@ -238,9 +236,11 @@
                 clocks = <&soc_smc50mhz>;
                 clock-names = "apb_pclk";
                 power-domains = <&scpi_devpd 0>;
-                port {
-                        cluster0_etm0_out_port: endpoint {
-                                remote-endpoint = <&cluster0_funnel_in_port0>;
+                out-ports {
+                        port {
+                                cluster0_etm0_out_port: endpoint {
+                                        remote-endpoint = <&cluster0_funnel_in_port0>;
+                                };
                         };
                 };
         };
@@ -252,29 +252,28 @@
                 clocks = <&soc_smc50mhz>;
                 clock-names = "apb_pclk";
                 power-domains = <&scpi_devpd 0>;
-                ports {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-
-                        port@0 {
-                                reg = <0>;
+                out-ports {
+                        port {
                                 cluster0_funnel_out_port: endpoint {
                                         remote-endpoint = <&main_funnel_in_port0>;
                                 };
                         };
+                };
 
-                        port@1 {
+                in-ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@0 {
                                 reg = <0>;
                                 cluster0_funnel_in_port0: endpoint {
-                                        slave-mode;
                                         remote-endpoint = <&cluster0_etm0_out_port>;
                                 };
                         };
 
-                        port@2 {
+                        port@1 {
                                 reg = <1>;
                                 cluster0_funnel_in_port1: endpoint {
-                                        slave-mode;
                                         remote-endpoint = <&cluster0_etm1_out_port>;
                                 };
                         };
@@ -297,9 +296,11 @@
                 clocks = <&soc_smc50mhz>;
                 clock-names = "apb_pclk";
                 power-domains = <&scpi_devpd 0>;
-                port {
-                        cluster0_etm1_out_port: endpoint {
-                                remote-endpoint = <&cluster0_funnel_in_port1>;
+                out-ports {
+                        port {
+                                cluster0_etm1_out_port: endpoint {
+                                        remote-endpoint = <&cluster0_funnel_in_port1>;
+                                };
                         };
                 };
         };
@@ -320,9 +321,11 @@
                 clocks = <&soc_smc50mhz>;
                 clock-names = "apb_pclk";
                 power-domains = <&scpi_devpd 0>;
-                port {
-                        cluster1_etm0_out_port: endpoint {
-                                remote-endpoint = <&cluster1_funnel_in_port0>;
+                out-ports {
+                        port {
+                                cluster1_etm0_out_port: endpoint {
+                                        remote-endpoint = <&cluster1_funnel_in_port0>;
+                                };
                         };
                 };
         };
@@ -334,43 +337,40 @@
                 clocks = <&soc_smc50mhz>;
                 clock-names = "apb_pclk";
                 power-domains = <&scpi_devpd 0>;
-                ports {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-
-                        port@0 {
-                                reg = <0>;
+                out-ports {
+                        port {
                                 cluster1_funnel_out_port: endpoint {
                                         remote-endpoint = <&main_funnel_in_port1>;
                                 };
                         };
+                };
 
-                        port@1 {
+                in-ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@0 {
                                 reg = <0>;
                                 cluster1_funnel_in_port0: endpoint {
-                                        slave-mode;
                                         remote-endpoint = <&cluster1_etm0_out_port>;
                                 };
                         };
 
-                        port@2 {
+                        port@1 {
                                 reg = <1>;
                                 cluster1_funnel_in_port1: endpoint {
-                                        slave-mode;
                                         remote-endpoint = <&cluster1_etm1_out_port>;
                                 };
                         };
-                        port@3 {
+                        port@2 {
                                 reg = <2>;
                                 cluster1_funnel_in_port2: endpoint {
-                                        slave-mode;
                                         remote-endpoint = <&cluster1_etm2_out_port>;
                                 };
                         };
-                        port@4 {
+                        port@3 {
                                 reg = <3>;
                                 cluster1_funnel_in_port3: endpoint {
-                                        slave-mode;
                                         remote-endpoint = <&cluster1_etm3_out_port>;
                                 };
                         };
@@ -393,9 +393,11 @@
                 clocks = <&soc_smc50mhz>;
                 clock-names = "apb_pclk";
                 power-domains = <&scpi_devpd 0>;
-                port {
-                        cluster1_etm1_out_port: endpoint {
-                                remote-endpoint = <&cluster1_funnel_in_port1>;
+                out-ports {
+                        port {
+                                cluster1_etm1_out_port: endpoint {
+                                        remote-endpoint = <&cluster1_funnel_in_port1>;
+                                };
                         };
                 };
         };
@@ -416,9 +418,11 @@
                 clocks = <&soc_smc50mhz>;
                 clock-names = "apb_pclk";
                 power-domains = <&scpi_devpd 0>;
-                port {
-                        cluster1_etm2_out_port: endpoint {
-                                remote-endpoint = <&cluster1_funnel_in_port2>;
+                out-ports {
+                        port {
+                                cluster1_etm2_out_port: endpoint {
+                                        remote-endpoint = <&cluster1_funnel_in_port2>;
+                                };
                         };
                 };
         };
@@ -439,9 +443,11 @@
                 clocks = <&soc_smc50mhz>;
                 clock-names = "apb_pclk";
                 power-domains = <&scpi_devpd 0>;
-                port {
-                        cluster1_etm3_out_port: endpoint {
-                                remote-endpoint = <&cluster1_funnel_in_port3>;
+                out-ports {
+                        port {
+                                cluster1_etm3_out_port: endpoint {
+                                        remote-endpoint = <&cluster1_funnel_in_port3>;
+                                };
                         };
                 };
         };
@@ -454,7 +460,7 @@
                 clock-names = "apb_pclk";
                 power-domains = <&scpi_devpd 0>;
 
-                ports {
+                out-ports {
                         #address-cells = <1>;
                         #size-cells = <0>;
 
@@ -472,12 +478,10 @@
                                         remote-endpoint = <&etr_in_port>;
                                 };
                         };
-
-                        /* replicator input port */
-                        port@2 {
-                                reg = <0>;
+                };
+                in-ports {
+                        port {
                                 replicator_in_port0: endpoint {
-                                        slave-mode;
                                 };
                         };
                 };
diff --git a/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi b/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi
index 0c43fb3525eb..cf285152deab 100644
--- a/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi
@@ -7,23 +7,16 @@
                 clocks = <&soc_smc50mhz>;
                 clock-names = "apb_pclk";
                 power-domains = <&scpi_devpd 0>;
-                ports {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-
-                        /* output port */
-                        port@0 {
-                                reg = <0>;
+                out-ports {
+                        port {
                                 csys1_funnel_out_port: endpoint {
                                         remote-endpoint = <&etf1_in_port>;
                                 };
                         };
-
-                        /* input port */
-                        port@1 {
-                                reg = <0>;
+                };
+                in-ports {
+                        port {
                                 csys1_funnel_in_port0: endpoint {
-                                        slave-mode;
                                 };
                         };
 
@@ -37,22 +30,15 @@
                 clocks = <&soc_smc50mhz>;
                 clock-names = "apb_pclk";
                 power-domains = <&scpi_devpd 0>;
-                ports {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-
-                        /* input port */
-                        port@0 {
-                                reg = <0>;
+                in-ports {
+                        port {
                                 etf1_in_port: endpoint {
-                                        slave-mode;
                                         remote-endpoint = <&csys1_funnel_out_port>;
                                 };
                         };
-
-                        /* output port */
-                        port@1 {
-                                reg = <0>;
+                };
+                out-ports {
+                        port {
                                 etf1_out_port: endpoint {
                                         remote-endpoint = <&csys2_funnel_in_port1>;
                                 };
@@ -67,20 +53,18 @@
                 clocks = <&soc_smc50mhz>;
                 clock-names = "apb_pclk";
                 power-domains = <&scpi_devpd 0>;
-                ports {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-
-                        /* output port */
-                        port@0 {
-                                reg = <0>;
+                out-ports {
+                        port {
                                 csys2_funnel_out_port: endpoint {
                                         remote-endpoint = <&replicator_in_port0>;
                                 };
                         };
+                };
 
-                        /* input ports */
-                        port@1 {
+                in-ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        port@0 {
                                 reg = <0>;
                                 csys2_funnel_in_port0: endpoint {
                                         slave-mode;
@@ -88,7 +72,7 @@
                                 };
                         };
 
-                        port@2 {
+                        port@1 {
                                 reg = <1>;
                                 csys2_funnel_in_port1: endpoint {
                                         slave-mode;
diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts
index 1fb5c5a0f32e..08d4ba1716c3 100644
--- a/arch/arm64/boot/dts/arm/juno.dts
+++ b/arch/arm64/boot/dts/arm/juno.dts
@@ -257,14 +257,11 @@
         remote-endpoint = <&main_funnel_in_port2>;
 };
 
-&main_funnel {
-        ports {
-                port@3 {
-                        reg = <2>;
-                        main_funnel_in_port2: endpoint {
-                                slave-mode;
-                                remote-endpoint = <&stm_out_port>;
-                        };
+&main_funnel_in_ports {
+        port@2 {
+                reg = <2>;
+                main_funnel_in_port2: endpoint {
+                        remote-endpoint = <&stm_out_port>;
                 };
         };
 };
diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile
index 1193a9e34bbb..667ca989c11b 100644
--- a/arch/arm64/boot/dts/broadcom/Makefile
+++ b/arch/arm64/boot/dts/broadcom/Makefile
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rpi-3-b.dtb \
-                              bcm2837-rpi-3-b-plus.dtb
+                              bcm2837-rpi-3-b-plus.dtb \
+                              bcm2837-rpi-cm3-io3.dtb
 
 subdir-y        += northstar2
 subdir-y        += stingray
diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts
new file mode 100644
index 000000000000..b1c4ab212c64
--- /dev/null
+++ b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts
@@ -0,0 +1,2 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "arm/bcm2837-rpi-cm3-io3.dts"
diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
index 1a406a76c86a..ea854f689fda 100644
--- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
+++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
@@ -639,7 +639,7 @@
                         status = "disabled";
                 };
 
-                ssp0: ssp@66180000 {
+                ssp0: spi@66180000 {
                         compatible = "arm,pl022", "arm,primecell";
                         reg = <0x66180000 0x1000>;
                         interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
@@ -650,7 +650,7 @@
                         status = "disabled";
                 };
 
-                ssp1: ssp@66190000 {
+                ssp1: spi@66190000 {
                         compatible = "arm,pl022", "arm,primecell";
                         reg = <0x66190000 0x1000>;
                         interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi b/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi
index bc299c3d9068..a9b92e52d50e 100644
--- a/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi
+++ b/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi
@@ -138,7 +138,7 @@
 &i2c1 {
         status = "okay";
 
-        pcf8574: pcf8574@20 {
+        pcf8574: pcf8574@27 {
                 compatible = "nxp,pcf8574a";
                 gpio-controller;
                 #gpio-cells = <2>;
diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
index e283480bfc7e..cfeaa855bd05 100644
--- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
+++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
@@ -521,7 +521,7 @@
                         status = "disabled";
                 };
 
-                ssp0: ssp@180000 {
+                ssp0: spi@180000 {
                         compatible = "arm,pl022", "arm,primecell";
                         reg = <0x00180000 0x1000>;
                         interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
@@ -533,7 +533,7 @@
                         status = "disabled";
                 };
 
-                ssp1: ssp@190000 {
+                ssp1: spi@190000 {
                         compatible = "arm,pl022", "arm,primecell";
                         reg = <0x00190000 0x1000>;
                         interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
index a1e3194b7483..f3ed4c078ba5 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
@@ -868,6 +868,14 @@
                                         };
                                 };
                         };
+
+                        ports {
+                                port {
+                                        muic_to_usb: endpoint {
+                                                remote-endpoint = <&usb_to_muic>;
+                                        };
+                                };
+                        };
                 };
 
                 regulators {
@@ -939,8 +947,7 @@
         status = "okay";
         cap-sd-highspeed;
         disable-wp;
-        cd-gpios = <&gpa2 4 GPIO_ACTIVE_HIGH>;
-        cd-inverted;
+        cd-gpios = <&gpa2 4 GPIO_ACTIVE_LOW>;
         card-detect-delay = <200>;
         samsung,dw-mshc-ciu-div = <3>;
         samsung,dw-mshc-sdr-timing = <0 4>;
@@ -1283,12 +1290,17 @@
 
 &usbdrd_dwc3 {
         dr_mode = "otg";
-        extcon = <&muic>;
 };
 
 &usbdrd30_phy {
         vbus-supply = <&safeout1_reg>;
         status = "okay";
+
+        port {
+                usb_to_muic: endpoint {
+                        remote-endpoint = <&muic_to_usb>;
+                };
+        };
 };
 
 &xxti {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
index 68ac78c4564d..5da732f82fa0 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -337,7 +337,7 @@
                         status = "disabled";
                 };
 
-                dspi: dspi@2100000 {
+                dspi: spi@2100000 {
                         compatible = "fsl,ls1012a-dspi", "fsl,ls1021a-v1.0-dspi";
                         #address-cells = <1>;
                         #size-cells = <0>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
index c7b8d2c009cd..dff3d648172e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
@@ -3,6 +3,7 @@
  * Device Tree Include file for Freescale Layerscape-1043A family SoC.
  *
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
+ * Copyright 2018 NXP
  *
  * Mingkai Hu <Mingkai.hu@freescale.com>
  */
@@ -50,6 +51,7 @@
         nor@0,0 {
                 compatible = "cfi-flash";
                 reg = <0x0 0x0 0x8000000>;
+                big-endian;
                 bank-width = <2>;
                 device-width = <1>;
         };
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
index 7b01ba8d3b7e..17ca357e854f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
@@ -3,6 +3,7 @@
  * Device Tree Include file for Freescale Layerscape-1043A family SoC.
  *
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
+ * Copyright 2018 NXP
  *
  * Mingkai Hu <Mingkai.hu@freescale.com>
  */
@@ -65,6 +66,7 @@
                         #address-cells = <1>;
                         #size-cells = <1>;
                         reg = <0x0 0x0 0x8000000>;
+                        big-endian;
                         bank-width = <2>;
                         device-width = <1>;
                 };
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 7881e3d81a9a..3fed504b5381 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -3,6 +3,7 @@
  * Device Tree Include file for Freescale Layerscape-1043A family SoC.
  *
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
+ * Copyright 2018 NXP
  *
  * Mingkai Hu <Mingkai.hu@freescale.com>
  */
@@ -280,11 +281,10 @@
                 ifc: ifc@1530000 {
                         compatible = "fsl,ifc", "simple-bus";
                         reg = <0x0 0x1530000 0x0 0x10000>;
-                        big-endian;
                         interrupts = <0 43 0x4>;
                 };
 
-                qspi: quadspi@1550000 {
+                qspi: spi@1550000 {
                         compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -382,7 +382,7 @@
                         ranges = <0x0 0x5 0x00000000 0x8000000>;
                 };
 
-                dspi0: dspi@2100000 {
+                dspi0: spi@2100000 {
                         compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -395,7 +395,7 @@
                         status = "disabled";
                 };
 
-                dspi1: dspi@2110000 {
+                dspi1: spi@2110000 {
                         compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
                         #address-cells = <1>;
                         #size-cells = <0>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
index e69306e6b0b1..e58a8ca1386c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
@@ -3,6 +3,7 @@
  * Device Tree Include file for Freescale Layerscape-1046A family SoC.
  *
  * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2018 NXP
  *
  * Shaohui Xie <Shaohui.Xie@nxp.com>
  */
@@ -141,6 +142,7 @@
         nor@0,0 {
                 compatible = "cfi-flash";
                 reg = <0x0 0x0 0x8000000>;
+                big-endian;
                 bank-width = <2>;
                 device-width = <1>;
         };
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
index 440e111651d5..a59b48203688 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
@@ -57,12 +57,12 @@
                 reg = <0x4c>;
         };
 
-        eeprom@56 {
+        eeprom@52 {
                 compatible = "atmel,24c512";
                 reg = <0x52>;
         };
 
-        eeprom@57 {
+        eeprom@53 {
                 compatible = "atmel,24c512";
                 reg = <0x53>;
         };
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index ef83786b8b90..51cbd50012d6 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -3,6 +3,7 @@
  * Device Tree Include file for Freescale Layerscape-1046A family SoC.
  *
  * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2018 NXP
  *
  * Mingkai Hu <mingkai.hu@nxp.com>
  */
@@ -198,11 +199,10 @@
                 ifc: ifc@1530000 {
                         compatible = "fsl,ifc", "simple-bus";
                         reg = <0x0 0x1530000 0x0 0x10000>;
-                        big-endian;
                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
                 };
 
-                qspi: quadspi@1550000 {
+                qspi: spi@1550000 {
                         compatible = "fsl,ls1021a-qspi";
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -361,7 +361,7 @@
                         #thermal-sensor-cells = <1>;
                 };
 
-                dspi: dspi@2100000 {
+                dspi: spi@2100000 {
                         compatible = "fsl,ls1021a-v1.0-dspi";
                         #address-cells = <1>;
                         #size-cells = <0>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index 90c0faf8579f..d188774a36e8 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -22,6 +22,8 @@
                 crypto = &crypto;
                 serial0 = &serial0;
                 serial1 = &serial1;
+                serial2 = &serial2;
+                serial3 = &serial3;
         };
 
         cpu: cpus {
@@ -222,6 +224,20 @@
                         interrupts = <0 32 0x4>; /* Level high type */
                 };
 
+                serial2: serial@21d0500 {
+                        compatible = "fsl,ns16550", "ns16550a";
+                        reg = <0x0 0x21d0500 0x0 0x100>;
+                        clocks = <&clockgen 4 3>;
+                        interrupts = <0 33 0x4>; /* Level high type */
+                };
+
+                serial3: serial@21d0600 {
+                        compatible = "fsl,ns16550", "ns16550a";
+                        reg = <0x0 0x21d0600 0x0 0x100>;
+                        clocks = <&clockgen 4 3>;
+                        interrupts = <0 33 0x4>; /* Level high type */
+                };
+
                 cluster1_core0_watchdog: wdt@c000000 {
                         compatible = "arm,sp805-wdt", "arm,primecell";
                         reg = <0x0 0xc000000 0x0 0x1000>;
@@ -474,7 +490,7 @@
                                      <0 208 4>, <0 209 4>;
                 };
 
-                dspi: dspi@2100000 {
+                dspi: spi@2100000 {
                         status = "disabled";
                         compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
                         #address-cells = <1>;
@@ -600,7 +616,7 @@
                                   3 0 0x5 0x20000000 0x00010000>;
                 };
 
-                qspi: quadspi@20c0000 {
+                qspi: spi@20c0000 {
                         status = "disabled";
                         compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
                         #address-cells = <1>;
diff --git a/arch/arm64/boot/dts/hisilicon/Makefile b/arch/arm64/boot/dts/hisilicon/Makefile
index 03d93f8ef8a9..f4d68caeba83 100644
--- a/arch/arm64/boot/dts/hisilicon/Makefile
+++ b/arch/arm64/boot/dts/hisilicon/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 dtb-$(CONFIG_ARCH_HISI) += hi3660-hikey960.dtb
+dtb-$(CONFIG_ARCH_HISI) += hi3670-hikey970.dtb
 dtb-$(CONFIG_ARCH_HISI) += hi3798cv200-poplar.dtb
 dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb
 dtb-$(CONFIG_ARCH_HISI) += hip05-d02.dtb
diff --git a/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts
new file mode 100644
index 000000000000..4f5118642024
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Hisilicon HiKey970 Development Board
+ *
+ * Copyright (C) 2016, Hisilicon Ltd.
+ * Copyright (C) 2018, Linaro Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include "hi3670.dtsi"
+
+/ {
+        model = "HiKey970";
+        compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670";
+
+        aliases {
+                serial6 = &uart6;       /* console UART */
+        };
+
+        chosen {
+                stdout-path = "serial6:115200n8";
+        };
+
+        memory@0 {
+                device_type = "memory";
+                /* expect bootloader to fill in this region */
+                reg = <0x0 0x0 0x0 0x0>;
+        };
+};
+
+&uart6 {
+        status = "okay";
+};
diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
new file mode 100644
index 000000000000..c90e6f6a34ec
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
@@ -0,0 +1,162 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Hisilicon Hi3670 SoC
+ *
+ * Copyright (C) 2016, Hisilicon Ltd.
+ * Copyright (C) 2018, Linaro Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+        compatible = "hisilicon,hi3670";
+        interrupt-parent = <&gic>;
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        psci {
+                compatible = "arm,psci-0.2";
+                method = "smc";
+        };
+
+        cpus {
+                #address-cells = <2>;
+                #size-cells = <0>;
+
+                cpu-map {
+                        cluster0 {
+                                core0 {
+                                        cpu = <&cpu0>;
+                                };
+                                core1 {
+                                        cpu = <&cpu1>;
+                                };
+                                core2 {
+                                        cpu = <&cpu2>;
+                                };
+                                core3 {
+                                        cpu = <&cpu3>;
+                                };
+                        };
+                        cluster1 {
+                                core0 {
+                                        cpu = <&cpu4>;
+                                };
+                                core1 {
+                                        cpu = <&cpu5>;
+                                };
+                                core2 {
+                                        cpu = <&cpu6>;
+                                };
+                                core3 {
+                                        cpu = <&cpu7>;
+                                };
+                        };
+                };
+
+                cpu0: cpu@0 {
+                        compatible = "arm,cortex-a53", "arm,armv8";
+                        device_type = "cpu";
+                        reg = <0x0 0x0>;
+                        enable-method = "psci";
+                };
+
+                cpu1: cpu@1 {
+                        compatible = "arm,cortex-a53", "arm,armv8";
+                        device_type = "cpu";
+                        reg = <0x0 0x1>;
+                        enable-method = "psci";
+                };
+
+                cpu2: cpu@2 {
+                        compatible = "arm,cortex-a53", "arm,armv8";
+                        device_type = "cpu";
+                        reg = <0x0 0x2>;
+                        enable-method = "psci";
+                };
+
+                cpu3: cpu@3 {
+                        compatible = "arm,cortex-a53", "arm,armv8";
+                        device_type = "cpu";
+                        reg = <0x0 0x3>;
+                        enable-method = "psci";
+                };
+
+                cpu4: cpu@100 {
+                        compatible = "arm,cortex-a73", "arm,armv8";
+                        device_type = "cpu";
+                        reg = <0x0 0x100>;
+                        enable-method = "psci";
+                };
+
+                cpu5: cpu@101 {
+                        compatible = "arm,cortex-a73", "arm,armv8";
+                        device_type = "cpu";
+                        reg = <0x0 0x101>;
+                        enable-method = "psci";
+                };
+
+                cpu6: cpu@102 {
+                        compatible = "arm,cortex-a73", "arm,armv8";
+                        device_type = "cpu";
+                        reg = <0x0 0x102>;
+                        enable-method = "psci";
+                };
+
+                cpu7: cpu@103 {
+                        compatible = "arm,cortex-a73", "arm,armv8";
+                        device_type = "cpu";
+                        reg = <0x0 0x103>;
+                        enable-method = "psci";
+                };
+        };
+
+        gic: interrupt-controller@e82b0000 {
+                compatible = "arm,gic-400";
+                reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */
+                      <0x0 0xe82b2000 0 0x2000>, /* GICC */
+                      <0x0 0xe82b4000 0 0x2000>, /* GICH */
+                      <0x0 0xe82b6000 0 0x2000>; /* GICV */
+                #interrupt-cells = <3>;
+                #address-cells = <0>;
+                interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
+                                         IRQ_TYPE_LEVEL_HIGH)>;
+                interrupt-controller;
+        };
+
+        timer {
+                compatible = "arm,armv8-timer";
+                interrupt-parent = <&gic>;
+                interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) |
+                                          IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) |
+                                          IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) |
+                                          IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) |
+                                          IRQ_TYPE_LEVEL_LOW)>;
+                clock-frequency = <1920000>;
+        };
+
+        soc {
+                compatible = "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
+
+                uart6_clk: clk_19_2M {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <19200000>;
+                };
+
+                uart6: serial@fff32000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0x0 0xfff32000 0x0 0x1000>;
+                        interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&uart6_clk &uart6_clk>;
+                        clock-names = "uartclk", "apb_pclk";
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi
index 7afee5d5087b..68c52f1149be 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi
@@ -20,22 +20,18 @@
                         clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
                         clock-names = "apb_pclk";
 
-                        ports {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-
-                                port@0 {
-                                        reg = <0>;
+                        out-ports {
+                                port {
                                         soc_funnel_out: endpoint {
                                                 remote-endpoint =
                                                         <&etf_in>;
                                         };
                                 };
+                        };
 
-                                port@1 {
-                                        reg = <0>;
+                        in-ports {
+                                port {
                                         soc_funnel_in: endpoint {
-                                                slave-mode;
                                                 remote-endpoint =
                                                         <&acpu_funnel_out>;
                                         };
@@ -49,21 +45,17 @@
                         clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
                         clock-names = "apb_pclk";
 
-                        ports {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-
-                                port@0 {
-                                        reg = <0>;
+                        in-ports {
+                                port {
                                         etf_in: endpoint {
-                                                slave-mode;
                                                 remote-endpoint =
                                                         <&soc_funnel_out>;
                                         };
                                 };
+                        };
 
-                                port@1 {
-                                        reg = <0>;
+                        out-ports {
+                                port {
                                         etf_out: endpoint {
                                                 remote-endpoint =
                                                         <&replicator_in>;
@@ -77,20 +69,20 @@
                         clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
                         clock-names = "apb_pclk";
 
-                        ports {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-
-                                port@0 {
-                                        reg = <0>;
+                        in-ports {
+                                port {
                                         replicator_in: endpoint {
-                                                slave-mode;
                                                 remote-endpoint =
                                                         <&etf_out>;
                                         };
                                 };
+                        };
 
-                                port@1 {
+                        out-ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@0 {
                                         reg = <0>;
                                         replicator_out0: endpoint {
                                                 remote-endpoint =
@@ -98,7 +90,7 @@
                                         };
                                 };
 
-                                port@2 {
+                                port@1 {
                                         reg = <1>;
                                         replicator_out1: endpoint {
                                                 remote-endpoint =
@@ -114,14 +106,9 @@
                         clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
                         clock-names = "apb_pclk";
 
-                        ports {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-
-                                port@0 {
-                                        reg = <0>;
+                        in-ports {
+                                port {
                                         etr_in: endpoint {
-                                                slave-mode;
                                                 remote-endpoint =
                                                         <&replicator_out0>;
                                         };
@@ -135,14 +122,9 @@
                         clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
                         clock-names = "apb_pclk";
 
-                        ports {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-
-                                port@0 {
-                                        reg = <0>;
+                        in-ports {
+                                port {
                                         tpiu_in: endpoint {
-                                                slave-mode;
                                                 remote-endpoint =
                                                         <&replicator_out1>;
                                         };
@@ -156,85 +138,78 @@
                         clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
                         clock-names = "apb_pclk";
 
-                        ports {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-
-                                port@0 {
-                                        reg = <0>;
+                        out-ports {
+                                port {
                                         acpu_funnel_out: endpoint {
                                                 remote-endpoint =
                                                         <&soc_funnel_in>;
                                         };
                                 };
+                        };
 
-                                port@1 {
+                        in-ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@0 {
                                         reg = <0>;
                                         acpu_funnel_in0: endpoint {
-                                                slave-mode;
                                                 remote-endpoint =
                                                         <&etm0_out>;
                                         };
                                 };
 
-                                port@2 {
+                                port@1 {
                                         reg = <1>;
                                         acpu_funnel_in1: endpoint {
-                                                slave-mode;
                                                 remote-endpoint =
                                                         <&etm1_out>;
                                         };
                                 };
 
-                                port@3 {
+                                port@2 {
                                         reg = <2>;
                                         acpu_funnel_in2: endpoint {
-                                                slave-mode;
                                                 remote-endpoint =
                                                         <&etm2_out>;
                                         };
                                 };
 
-                                port@4 {
+                                port@3 {
                                         reg = <3>;
                                         acpu_funnel_in3: endpoint {
-                                                slave-mode;
                                                 remote-endpoint =
                                                         <&etm3_out>;
                                         };
                                 };
 
-                                port@5 {
+                                port@4 {
                                         reg = <4>;
                                         acpu_funnel_in4: endpoint {
-                                                slave-mode;
                                                 remote-endpoint =
                                                         <&etm4_out>;
                                         };
                                 };
 
-                                port@6 {
+                                port@5 {
                                         reg = <5>;
                                         acpu_funnel_in5: endpoint {
-                                                slave-mode;
                                                 remote-endpoint =
                                                         <&etm5_out>;
                                         };
                                 };
 
-                                port@7 {
+                                port@6 {
                                         reg = <6>;
                                         acpu_funnel_in6: endpoint {
-                                                slave-mode;
                                                 remote-endpoint =
                                                         <&etm6_out>;
                                         };
                                 };
 
-                                port@8 {
+                                port@7 {
                                         reg = <7>;
                                         acpu_funnel_in7: endpoint {
-                                                slave-mode;
                                                 remote-endpoint =
                                                         <&etm7_out>;
                                         };
@@ -251,10 +226,12 @@
 
                         cpu = <&cpu0>;
 
-                        port {
-                                etm0_out: endpoint {
-                                        remote-endpoint =
-                                                <&acpu_funnel_in0>;
+                        out-ports {
+                                port {
+                                        etm0_out: endpoint {
+                                                remote-endpoint =
+                                                        <&acpu_funnel_in0>;
+                                        };
                                 };
                         };
                 };
@@ -268,10 +245,12 @@
 
                         cpu = <&cpu1>;
 
-                        port {
-                                etm1_out: endpoint {
-                                        remote-endpoint =
-                                                <&acpu_funnel_in1>;
+                        out-ports {
+                                port {
+                                        etm1_out: endpoint {
+                                                remote-endpoint =
+                                                        <&acpu_funnel_in1>;
+                                        };
                                 };
                         };
                 };
@@ -285,10 +264,12 @@
 
                         cpu = <&cpu2>;
 
-                        port {
-                                etm2_out: endpoint {
-                                        remote-endpoint =
-                                                <&acpu_funnel_in2>;
+                        out-ports {
+                                port {
+                                        etm2_out: endpoint {
+                                                remote-endpoint =
+                                                        <&acpu_funnel_in2>;
+                                        };
                                 };
                         };
                 };
@@ -302,10 +283,12 @@
 
                         cpu = <&cpu3>;
 
-                        port {
-                                etm3_out: endpoint {
-                                        remote-endpoint =
-                                                <&acpu_funnel_in3>;
+                        out-ports {
+                                port {
+                                        etm3_out: endpoint {
+                                                remote-endpoint =
+                                                        <&acpu_funnel_in3>;
+                                        };
                                 };
                         };
                 };
@@ -319,10 +302,12 @@
 
                         cpu = <&cpu4>;
 
-                        port {
-                                etm4_out: endpoint {
-                                        remote-endpoint =
-                                                <&acpu_funnel_in4>;
+                        out-ports {
+                                port {
+                                        etm4_out: endpoint {
+                                                remote-endpoint =
+                                                        <&acpu_funnel_in4>;
+                                        };
                                 };
                         };
                 };
@@ -336,10 +321,12 @@
 
                         cpu = <&cpu5>;
 
-                        port {
-                                etm5_out: endpoint {
-                                        remote-endpoint =
-                                                <&acpu_funnel_in5>;
+                        out-ports {
+                                port {
+                                        etm5_out: endpoint {
+                                                remote-endpoint =
+                                                        <&acpu_funnel_in5>;
+                                        };
                                 };
                         };
                 };
@@ -353,10 +340,12 @@
 
                         cpu = <&cpu6>;
 
-                        port {
-                                etm6_out: endpoint {
-                                        remote-endpoint =
-                                                <&acpu_funnel_in6>;
+                        out-ports {
+                                port {
+                                        etm6_out: endpoint {
+                                                remote-endpoint =
+                                                        <&acpu_funnel_in6>;
+                                        };
                                 };
                         };
                 };
@@ -370,10 +359,12 @@
 
                         cpu = <&cpu7>;
 
-                        port {
-                                etm7_out: endpoint {
-                                        remote-endpoint =
-                                                <&acpu_funnel_in7>;
+                        out-ports {
+                                port {
+                                        etm7_out: endpoint {
+                                                remote-endpoint =
+                                                        <&acpu_funnel_in7>;
+                                        };
                                 };
                         };
                 };
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 247024df714f..97d5bf2c6ec5 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -99,6 +99,7 @@
                         reg = <0x0 0x1>;
                         enable-method = "psci";
                         next-level-cache = <&CLUSTER0_L2>;
+                        clocks = <&stub_clock 0>;
                         operating-points-v2 = <&cpu_opp_table>;
                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
                         #cooling-cells = <2>; /* min followed by max */
@@ -111,6 +112,7 @@
                         reg = <0x0 0x2>;
                         enable-method = "psci";
                         next-level-cache = <&CLUSTER0_L2>;
+                        clocks = <&stub_clock 0>;
                         operating-points-v2 = <&cpu_opp_table>;
                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
                         #cooling-cells = <2>; /* min followed by max */
@@ -123,6 +125,7 @@
                         reg = <0x0 0x3>;
                         enable-method = "psci";
                         next-level-cache = <&CLUSTER0_L2>;
+                        clocks = <&stub_clock 0>;
                         operating-points-v2 = <&cpu_opp_table>;
                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
                         #cooling-cells = <2>; /* min followed by max */
@@ -135,6 +138,7 @@
                         reg = <0x0 0x100>;
                         enable-method = "psci";
                         next-level-cache = <&CLUSTER1_L2>;
+                        clocks = <&stub_clock 0>;
                         operating-points-v2 = <&cpu_opp_table>;
                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
                         #cooling-cells = <2>; /* min followed by max */
@@ -147,6 +151,7 @@
                         reg = <0x0 0x101>;
                         enable-method = "psci";
                         next-level-cache = <&CLUSTER1_L2>;
+                        clocks = <&stub_clock 0>;
                         operating-points-v2 = <&cpu_opp_table>;
                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
                         #cooling-cells = <2>; /* min followed by max */
@@ -159,6 +164,7 @@
                         reg = <0x0 0x102>;
                         enable-method = "psci";
                         next-level-cache = <&CLUSTER1_L2>;
+                        clocks = <&stub_clock 0>;
                         operating-points-v2 = <&cpu_opp_table>;
                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
                         #cooling-cells = <2>; /* min followed by max */
@@ -171,6 +177,7 @@
                         reg = <0x0 0x103>;
                         enable-method = "psci";
                         next-level-cache = <&CLUSTER1_L2>;
+                        clocks = <&stub_clock 0>;
                         operating-points-v2 = <&cpu_opp_table>;
                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
                         #cooling-cells = <2>; /* min followed by max */
diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi b/arch/arm64/boot/dts/lg/lg1312.dtsi
index 860c8fb10795..4bde7b6f2b11 100644
--- a/arch/arm64/boot/dts/lg/lg1312.dtsi
+++ b/arch/arm64/boot/dts/lg/lg1312.dtsi
@@ -168,14 +168,14 @@
                         clock-names = "apb_pclk";
                         status="disabled";
                 };
-                spi0: ssp@fe800000 {
+                spi0: spi@fe800000 {
                         compatible = "arm,pl022", "arm,primecell";
                         reg = <0x0 0xfe800000 0x1000>;
                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&clk_bus>;
                         clock-names = "apb_pclk";
                 };
-                spi1: ssp@fe900000 {
+                spi1: spi@fe900000 {
                         compatible = "arm,pl022", "arm,primecell";
                         reg = <0x0 0xfe900000 0x1000>;
                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/lg/lg1313.dtsi b/arch/arm64/boot/dts/lg/lg1313.dtsi
index 1887af654a7d..16ced1ff1ad3 100644
--- a/arch/arm64/boot/dts/lg/lg1313.dtsi
+++ b/arch/arm64/boot/dts/lg/lg1313.dtsi
@@ -168,14 +168,14 @@
                         clock-names = "apb_pclk";
                         status="disabled";
                 };
-                spi0: ssp@fe800000 {
+                spi0: spi@fe800000 {
                         compatible = "arm,pl022", "arm,primecell";
                         reg = <0x0 0xfe800000 0x1000>;
                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&clk_bus>;
                         clock-names = "apb_pclk";
                 };
-                spi1: ssp@fe900000 {
+                spi1: spi@fe900000 {
                         compatible = "arm,pl022", "arm,primecell";
                         reg = <0x0 0xfe900000 0x1000>;
                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile
index ea9d49f2a911..eca8bac6303a 100644
--- a/arch/arm64/boot/dts/marvell/Makefile
+++ b/arch/arm64/boot/dts/marvell/Makefile
@@ -3,6 +3,7 @@
 dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-db.dtb
 dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin.dtb
 dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-db.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-clearfog-gt-8k.dtb
 dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-db.dtb
 dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin.dtb
 dtb-$(CONFIG_ARCH_MVEBU) += armada-8080-db.dtb
diff --git a/arch/arm64/boot/dts/marvell/armada-372x.dtsi b/arch/arm64/boot/dts/marvell/armada-372x.dtsi
index 97558a64e276..6800945a88ad 100644
--- a/arch/arm64/boot/dts/marvell/armada-372x.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-372x.dtsi
@@ -16,7 +16,7 @@
         compatible = "marvell,armada3720", "marvell,armada3710";
 
         cpus {
-                cpu@1 {
+                cpu1: cpu@1 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a53","arm,armv8";
                         reg = <0x1>;
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index d9531e242eb4..4472bcd8f9fb 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -40,7 +40,7 @@
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
-                cpu@0 {
+                cpu0: cpu@0 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a53", "arm,armv8";
                         reg = <0>;
@@ -80,6 +80,19 @@
                         /* 32M internal register @ 0xd000_0000 */
                         ranges = <0x0 0x0 0xd0000000 0x2000000>;
 
+                        wdt: watchdog@8300 {
+                                compatible = "marvell,armada-3700-wdt";
+                                reg = <0x8300 0x40>;
+                                marvell,system-controller = <&cpu_misc>;
+                                clocks = <&xtalclk>;
+                        };
+
+                        cpu_misc: system-controller@d000 {
+                                compatible = "marvell,armada-3700-cpu-misc",
+                                             "syscon";
+                                reg = <0xd000 0x1000>;
+                        };
+
                         spi0: spi@10600 {
                                 compatible = "marvell,armada-3700-spi";
                                 #address-cells = <1>;
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
new file mode 100644
index 000000000000..9473d40a292a
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
@@ -0,0 +1,441 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 SolidRun ltd.
+ * Based on Marvell MACCHIATOBin board
+ *
+ * Device Tree file for SolidRun's ClearFog GT 8K
+ */
+
+#include "armada-8040.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+        model = "SolidRun ClearFog GT 8K";
+        compatible = "solidrun,clearfog-gt-8k", "marvell,armada8040",
+                        "marvell,armada-ap806-quad", "marvell,armada-ap806";
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+
+        memory@00000000 {
+                device_type = "memory";
+                reg = <0x0 0x0 0x0 0x80000000>;
+        };
+
+        aliases {
+                ethernet0 = &cp1_eth1;
+                ethernet1 = &cp0_eth0;
+                ethernet2 = &cp1_eth2;
+        };
+
+        v_3_3: regulator-3-3v {
+                compatible = "regulator-fixed";
+                regulator-name = "v_3_3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+                status = "okay";
+        };
+
+        v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {
+                compatible = "regulator-fixed";
+                gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&cp0_xhci_vbus_pins>;
+                regulator-name = "v_5v0_usb3_hst_vbus";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                status = "okay";
+        };
+
+        usb3h0_phy: usb3_phy0 {
+                compatible = "usb-nop-xceiv";
+                vcc-supply = <&v_5v0_usb3_hst_vbus>;
+        };
+
+        sfp_cp0_eth0: sfp-cp0-eth0 {
+                compatible = "sff,sfp";
+                i2c-bus = <&cp0_i2c1>;
+                mod-def0-gpio = <&cp0_gpio2 17 GPIO_ACTIVE_LOW>;
+                tx-disable-gpio = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&cp0_sfp_present_pins &cp1_sfp_tx_disable_pins>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-0 = <&cp0_led0_pins
+                             &cp0_led1_pins>;
+                pinctrl-names = "default";
+                /* No designated function for these LEDs at the moment */
+                led0 {
+                        label = "clearfog-gt-8k:green:led0";
+                        gpios = <&cp0_gpio2 8 GPIO_ACTIVE_LOW>;
+                        default-state = "on";
+                };
+                led1 {
+                        label = "clearfog-gt-8k:green:led1";
+                        gpios = <&cp0_gpio2 9 GPIO_ACTIVE_LOW>;
+                        default-state = "on";
+                };
+        };
+
+        keys {
+                compatible = "gpio-keys";
+                pinctrl-0 = <&cp0_gpio_reset_pins &cp1_wps_button_pins>;
+                pinctrl-names = "default";
+
+                button_0 {
+                        /* The rear button */
+                        label = "Rear Button";
+                        gpios = <&cp0_gpio2 7 GPIO_ACTIVE_LOW>;
+                        linux,can-disable;
+                        linux,code = <BTN_0>;
+                };
+
+                button_1 {
+                        /* The wps button */
+                        label = "WPS Button";
+                        gpios = <&cp1_gpio1 30 GPIO_ACTIVE_LOW>;
+                        linux,can-disable;
+                        linux,code = <KEY_WPS_BUTTON>;
+                };
+        };
+};
+
+&uart0 {
+        status = "okay";
+        pinctrl-0 = <&uart0_pins>;
+        pinctrl-names = "default";
+};
+
+&ap_sdhci0 {
+        bus-width = <8>;
+        no-1-8-v;
+        no-sd;
+        no-sdio;
+        non-removable;
+        status = "okay";
+        vqmmc-supply = <&v_3_3>;
+};
+
+&cp0_i2c0 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&cp0_i2c0_pins>;
+        status = "okay";
+};
+
+&cp0_i2c1 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&cp0_i2c1_pins>;
+        status = "okay";
+};
+
+&cp0_pinctrl {
+        /*
+         * MPP Bus:
+         * [0-31] = 0xff: Keep default CP0_shared_pins:
+         * [11] CLKOUT_MPP_11 (out)
+         * [23] LINK_RD_IN_CP2CP (in)
+         * [25] CLKOUT_MPP_25 (out)
+         * [29] AVS_FB_IN_CP2CP (in)
+         * [32, 33, 34] pci0/1/2 reset
+         * [35-38] CP0 I2C1 and I2C0
+         * [39] GPIO reset button
+         * [40,41] LED0 and LED1
+         * [43] 1512 phy reset
+         * [47] USB VBUS EN (active low)
+         * [48] FAN PWM
+         * [49] SFP+ present signal
+         * [50] TPM interrupt
+         * [51] WLAN0 disable
+         * [52] WLAN1 disable
+         * [53] LTE disable
+         * [54] NFC reset
+         * [55] Micro SD card detect
+         * [56-61] Micro SD
+         */
+
+        cp0_pci0_reset_pins: pci0-reset-pins {
+                marvell,pins = "mpp32";
+                marvell,function = "gpio";
+        };
+
+        cp0_pci1_reset_pins: pci1-reset-pins {
+                marvell,pins = "mpp33";
+                marvell,function = "gpio";
+        };
+
+        cp0_pci2_reset_pins: pci2-reset-pins {
+                marvell,pins = "mpp34";
+                marvell,function = "gpio";
+        };
+
+        cp0_i2c1_pins: i2c1-pins {
+                marvell,pins = "mpp35", "mpp36";
+                marvell,function = "i2c1";
+        };
+
+        cp0_i2c0_pins: i2c0-pins {
+                marvell,pins = "mpp37", "mpp38";
+                marvell,function = "i2c0";
+        };
+
+        cp0_gpio_reset_pins: gpio-reset-pins {
+                marvell,pins = "mpp39";
+                marvell,function = "gpio";
+        };
+
+        cp0_led0_pins: led0-pins {
+                marvell,pins = "mpp40";
+                marvell,function = "gpio";
+        };
+
+        cp0_led1_pins: led1-pins {
+                marvell,pins = "mpp41";
+                marvell,function = "gpio";
+        };
+
+        cp0_copper_eth_phy_reset: copper-eth-phy-reset {
+                marvell,pins = "mpp43";
+                marvell,function = "gpio";
+        };
+
+        cp0_xhci_vbus_pins: xhci0-vbus-pins {
+                marvell,pins = "mpp47";
+                marvell,function = "gpio";
+        };
+
+        cp0_fan_pwm_pins: fan-pwm-pins {
+                marvell,pins = "mpp48";
+                marvell,function = "gpio";
+        };
+
+        cp0_sfp_present_pins: sfp-present-pins {
+                marvell,pins = "mpp49";
+                marvell,function = "gpio";
+        };
+
+        cp0_tpm_irq_pins: tpm-irq-pins {
+                marvell,pins = "mpp50";
+                marvell,function = "gpio";
+        };
+
+        cp0_sdhci_pins: sdhci-pins {
+                marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59",
+                               "mpp60", "mpp61";
+                marvell,function = "sdio";
+        };
+};
+
+&cp0_pcie0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&cp0_pci0_reset_pins>;
+        reset-gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>;
+        status = "okay";
+};
+
+&cp0_gpio2 {
+        sata_reset {
+                gpio-hog;
+                gpios = <1 GPIO_ACTIVE_HIGH>;
+                output-high;
+        };
+};
+
+&cp0_ethernet {
+        status = "okay";
+};
+
+/* SFP */
+&cp0_eth0 {
+        status = "okay";
+        phy-mode = "10gbase-kr";
+        managed = "in-band-status";
+        phys = <&cp0_comphy2 0>;
+        sfp = <&sfp_cp0_eth0>;
+};
+
+&cp0_sdhci0 {
+        broken-cd;
+        bus-width = <4>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&cp0_sdhci_pins>;
+        status = "okay";
+        vqmmc-supply = <&v_3_3>;
+};
+
+&cp1_pinctrl {
+        /*
+         * MPP Bus:
+         * [0-5] TDM
+         * [6]   VHV Enable
+         * [7]   CP1 SPI0 CSn1 (FXS)
+         * [8]   CP1 SPI0 CSn0 (TPM)
+         * [9.11]CP1 SPI0 MOSI/MISO/CLK
+         * [13]  CP1 SPI1 MISO (TDM and SPI ROM shared)
+         * [14]  CP1 SPI1 CS0n (64Mb SPI ROM)
+         * [15]  CP1 SPI1 MOSI (TDM and SPI ROM shared)
+         * [16]  CP1 SPI1 CLK (TDM and SPI ROM shared)
+         * [24]  Topaz switch reset
+         * [26]  Buzzer
+         * [27]  CP1 SMI MDIO
+         * [28]  CP1 SMI MDC
+         * [29]  CP0 10G SFP TX Disable
+         * [30]  WPS button
+         * [31]  Front panel button
+         */
+
+        cp1_spi1_pins: spi1-pins {
+                marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
+                marvell,function = "spi1";
+        };
+
+        cp1_switch_reset_pins: switch-reset-pins {
+                marvell,pins = "mpp24";
+                marvell,function = "gpio";
+        };
+
+        cp1_ge_mdio_pins: ge-mdio-pins {
+                marvell,pins = "mpp27", "mpp28";
+                marvell,function = "ge";
+        };
+
+        cp1_sfp_tx_disable_pins: sfp-tx-disable-pins {
+                marvell,pins = "mpp29";
+                marvell,function = "gpio";
+        };
+
+        cp1_wps_button_pins: wps-button-pins {
+                marvell,pins = "mpp30";
+                marvell,function = "gpio";
+        };
+};
+
+&cp1_sata0 {
+        pinctrl-0 = <&cp0_pci1_reset_pins>;
+        status = "okay";
+};
+
+&cp1_mdio {
+        pinctrl-names = "default";
+        pinctrl-0 = <&cp1_ge_mdio_pins>;
+        status = "okay";
+
+        ge_phy: ethernet-phy@0 {
+                /* LED0 - GB link
+                 * LED1 - on: link, blink: activity
+                 */
+                marvell,reg-init = <3 16 0 0x1017>;
+                reg = <0>;
+        };
+
+        switch0: switch0@4 {
+                compatible = "marvell,mv88e6085";
+                reg = <4>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&cp1_switch_reset_pins>;
+                reset-gpios = <&cp1_gpio1 24 GPIO_ACTIVE_LOW>;
+
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@1 {
+                                reg = <1>;
+                                label = "lan2";
+                                phy-handle = <&switch0phy0>;
+                        };
+
+                        port@2 {
+                                reg = <2>;
+                                label = "lan1";
+                                phy-handle = <&switch0phy1>;
+                        };
+
+                        port@3 {
+                                reg = <3>;
+                                label = "lan4";
+                                phy-handle = <&switch0phy2>;
+                        };
+
+                        port@4 {
+                                reg = <4>;
+                                label = "lan3";
+                                phy-handle = <&switch0phy3>;
+                        };
+
+                        port@5 {
+                                reg = <5>;
+                                label = "cpu";
+                                ethernet = <&cp1_eth2>;
+                        };
+                };
+
+                mdio {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        switch0phy0: switch0phy0@11 {
+                                reg = <0x11>;
+                        };
+
+                        switch0phy1: switch0phy1@12 {
+                                reg = <0x12>;
+                        };
+
+                        switch0phy2: switch0phy2@13 {
+                                reg = <0x13>;
+                        };
+
+                        switch0phy3: switch0phy3@14 {
+                                reg = <0x14>;
+                        };
+                };
+        };
+};
+
+&cp1_ethernet {
+        status = "okay";
+};
+
+/* 1G copper */
+&cp1_eth1 {
+        status = "okay";
+        phy-mode = "sgmii";
+        phy = <&ge_phy>;
+        phys = <&cp1_comphy3 1>;
+};
+
+/* Switch uplink */
+&cp1_eth2 {
+        status = "okay";
+        phy-mode = "2500base-x";
+        phys = <&cp1_comphy5 2>;
+        fixed-link {
+                speed = <2500>;
+                full-duplex;
+        };
+};
+
+&cp1_spi1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&cp1_spi1_pins>;
+        status = "okay";
+
+        spi-flash@0 {
+                compatible = "st,w25q32";
+                spi-max-frequency = <50000000>;
+                reg = <0>;
+        };
+};
+
+&cp1_usb3_0 {
+        usb-phy = <&usb3h0_phy>;
+        status = "okay";
+};
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
index 64b5e61a698e..d3c0636558ff 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
@@ -15,13 +15,13 @@
                 #address-cells = <1>;
                 #size-cells = <0>;
 
-                cpu@0 {
+                cpu0: cpu@0 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a72", "arm,armv8";
                         reg = <0x000>;
                         enable-method = "psci";
                 };
-                cpu@1 {
+                cpu1: cpu@1 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a72", "arm,armv8";
                         reg = <0x001>;
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
index 746e792767f5..64632c873888 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
@@ -15,29 +15,33 @@
                 #address-cells = <1>;
                 #size-cells = <0>;
 
-                cpu@0 {
+                cpu0: cpu@0 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a72", "arm,armv8";
                         reg = <0x000>;
                         enable-method = "psci";
+                        cpu-idle-states = <&CPU_SLEEP_0>;
                 };
-                cpu@1 {
+                cpu1: cpu@1 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a72", "arm,armv8";
                         reg = <0x001>;
                         enable-method = "psci";
+                        cpu-idle-states = <&CPU_SLEEP_0>;
                 };
-                cpu@100 {
+                cpu2: cpu@100 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a72", "arm,armv8";
                         reg = <0x100>;
                         enable-method = "psci";
+                        cpu-idle-states = <&CPU_SLEEP_0>;
                 };
-                cpu@101 {
+                cpu3: cpu@101 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a72", "arm,armv8";
                         reg = <0x101>;
                         enable-method = "psci";
+                        cpu-idle-states = <&CPU_SLEEP_0>;
                 };
         };
 };
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index 176e38d54872..073610ac0a53 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -6,6 +6,7 @@
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/thermal.h>
 
 /dts-v1/;
 
@@ -27,6 +28,33 @@
                 method = "smc";
         };
 
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                idle_states {
+                        entry_method = "arm,pcsi";
+
+                        CPU_SLEEP_0: cpu-sleep-0 {
+                                compatible = "arm,idle-state";
+                                local-timer-stop;
+                                arm,psci-suspend-param = <0x0010000>;
+                                entry-latency-us = <80>;
+                                exit-latency-us  = <160>;
+                                min-residency-us = <320>;
+                        };
+
+                        CLUSTER_SLEEP_0: cluster-sleep-0 {
+                                compatible = "arm,idle-state";
+                                local-timer-stop;
+                                arm,psci-suspend-param = <0x1010000>;
+                                entry-latency-us = <500>;
+                                exit-latency-us = <1000>;
+                                min-residency-us = <2500>;
+                        };
+                };
+        };
+
         ap806 {
                 #address-cells = <2>;
                 #size-cells = <2>;
@@ -124,6 +152,15 @@
                                 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
                         };
 
+                        sei: interrupt-controller@3f0200 {
+                                compatible = "marvell,ap806-sei";
+                                reg = <0x3f0200 0x40>;
+                                interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+                                #interrupt-cells = <1>;
+                                interrupt-controller;
+                                msi-controller;
+                        };
+
                         xor@400000 {
                                 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
                                 reg = <0x400000 0x1000>,
@@ -247,11 +284,76 @@
                                 };
                         };
 
-                        ap_thermal: thermal@6f808c {
-                                compatible = "marvell,armada-ap806-thermal";
-                                reg = <0x6f808c 0x4>,
-                                      <0x6f8084 0x8>;
+                        ap_syscon1: system-controller@6f8000 {
+                                compatible = "syscon", "simple-mfd";
+                                reg = <0x6f8000 0x1000>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+
+                                ap_thermal: thermal-sensor@80 {
+                                        compatible = "marvell,armada-ap806-thermal";
+                                        reg = <0x80 0x10>;
+                                        #thermal-sensor-cells = <1>;
+                                };
                         };
                 };
         };
+
+        /*
+         * The thermal IP features one internal sensor plus, if applicable, one
+         * remote channel wired to one sensor per CPU.
+         *
+         * The cooling maps are always empty as there are no cooling devices.
+         */
+        thermal-zones {
+                ap_thermal_ic: ap-thermal-ic {
+                        polling-delay-passive = <1000>;
+                        polling-delay = <1000>;
+
+                        thermal-sensors = <&ap_thermal 0>;
+
+                        trips { };
+                        cooling-maps { };
+                };
+
+                ap_thermal_cpu1: ap-thermal-cpu1 {
+                        polling-delay-passive = <1000>;
+                        polling-delay = <1000>;
+
+                        thermal-sensors = <&ap_thermal 1>;
+
+                        trips { };
+                        cooling-maps { };
+                };
+
+                ap_thermal_cpu2: ap-thermal-cpu2 {
+                        polling-delay-passive = <1000>;
+                        polling-delay = <1000>;
+
+                        thermal-sensors = <&ap_thermal 2>;
+
+                        trips { };
+                        cooling-maps { };
+                };
+
+                ap_thermal_cpu3: ap-thermal-cpu3 {
+                        polling-delay-passive = <1000>;
+                        polling-delay = <1000>;
+
+                        thermal-sensors = <&ap_thermal 3>;
+
+                        trips { };
+                        cooling-maps { };
+                };
+
+                ap_thermal_cpu4: ap-thermal-cpu4 {
+                        polling-delay-passive = <1000>;
+                        polling-delay = <1000>;
+
+                        thermal-sensors = <&ap_thermal 4>;
+
+                        trips { };
+                        cooling-maps { };
+                };
+        };
 };
diff --git a/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi b/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi
index 7d00ae78fc79..b788cb63caf2 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi
@@ -13,49 +13,49 @@
                 #size-cells = <0>;
                 compatible = "marvell,armada-ap810-octa";
 
-                cpu@0 {
+                cpu0: cpu@0 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a72", "arm,armv8";
                         reg = <0x000>;
                         enable-method = "psci";
                 };
-                cpu@1 {
+                cpu1: cpu@1 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a72", "arm,armv8";
                         reg = <0x001>;
                         enable-method = "psci";
                 };
-                cpu@100 {
+                cpu2: cpu@100 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a72", "arm,armv8";
                         reg = <0x100>;
                         enable-method = "psci";
                 };
-                cpu@101 {
+                cpu3: cpu@101 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a72", "arm,armv8";
                         reg = <0x101>;
                         enable-method = "psci";
                 };
-                cpu@200 {
+                cpu4: cpu@200 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a72", "arm,armv8";
                         reg = <0x200>;
                         enable-method = "psci";
                 };
-                cpu@201 {
+                cpu5: cpu@201 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a72", "arm,armv8";
                         reg = <0x201>;
                         enable-method = "psci";
                 };
-                cpu@300 {
+                cpu6: cpu@300 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a72", "arm,armv8";
                         reg = <0x300>;
                         enable-method = "psci";
                 };
-                cpu@301 {
+                cpu7: cpu@301 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a72", "arm,armv8";
                         reg = <0x301>;
diff --git a/arch/arm64/boot/dts/marvell/armada-common.dtsi b/arch/arm64/boot/dts/marvell/armada-common.dtsi
index d5e8aedec188..b29c6405d214 100644
--- a/arch/arm64/boot/dts/marvell/armada-common.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-common.dtsi
@@ -7,4 +7,5 @@
 #define PASTER(x, y) x ## y
 #define EVALUATOR(x, y) PASTER(x, y)
 #define CP110_LABEL(name) EVALUATOR(CP110_NAME, EVALUATOR(_, name))
+#define CP110_NODE_NAME(name) EVALUATOR(CP110_NAME, EVALUATOR(-, name))
 #define ADDRESSIFY(addr) EVALUATOR(0x, addr)
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
index 840c8454d03e..b9d9f31e3ba1 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
@@ -6,6 +6,7 @@
  */
 
 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
+#include <dt-bindings/thermal/thermal.h>
 
 #include "armada-common.dtsi"
 
@@ -19,13 +20,30 @@
          * save one indentation level
          */
         CP110_NAME: CP110_NAME { };
+
+        /*
+         * CPs only have one sensor in the thermal IC.
+         *
+         * The cooling maps are empty as there are no cooling devices.
+         */
+        thermal-zones {
+                CP110_LABEL(thermal_ic): CP110_NODE_NAME(thermal-ic) {
+                        polling-delay-passive = <1000>;
+                        polling-delay = <1000>;
+
+                        thermal-sensors = <&CP110_LABEL(thermal) 0>;
+
+                        trips { };
+                        cooling-maps { };
+                };
+        };
 };
 
 &CP110_NAME {
         #address-cells = <2>;
         #size-cells = <2>;
         compatible = "simple-bus";
-        interrupt-parent = <&CP110_LABEL(icu)>;
+        interrupt-parent = <&CP110_LABEL(icu_nsr)>;
         ranges;
 
         config-space@CP110_BASE {
@@ -47,42 +65,57 @@
                         dma-coherent;
 
                         CP110_LABEL(eth0): eth0 {
-                                interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
-                                        <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
-                                        <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
-                                        <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
-                                        <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
-                                        <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
-                                interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
-                                        "tx-cpu3", "rx-shared", "link";
+                                interrupts = <39 IRQ_TYPE_LEVEL_HIGH>,
+                                        <43 IRQ_TYPE_LEVEL_HIGH>,
+                                        <47 IRQ_TYPE_LEVEL_HIGH>,
+                                        <51 IRQ_TYPE_LEVEL_HIGH>,
+                                        <55 IRQ_TYPE_LEVEL_HIGH>,
+                                        <59 IRQ_TYPE_LEVEL_HIGH>,
+                                        <63 IRQ_TYPE_LEVEL_HIGH>,
+                                        <67 IRQ_TYPE_LEVEL_HIGH>,
+                                        <71 IRQ_TYPE_LEVEL_HIGH>,
+                                        <129 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-names = "hif0", "hif1", "hif2",
+                                        "hif3", "hif4", "hif5", "hif6", "hif7",
+                                        "hif8", "link";
                                 port-id = <0>;
                                 gop-port-id = <0>;
                                 status = "disabled";
                         };
 
                         CP110_LABEL(eth1): eth1 {
-                                interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
-                                        <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
-                                        <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
-                                        <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
-                                        <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
-                                        <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
-                                interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
-                                        "tx-cpu3", "rx-shared", "link";
+                                interrupts = <40 IRQ_TYPE_LEVEL_HIGH>,
+                                        <44 IRQ_TYPE_LEVEL_HIGH>,
+                                        <48 IRQ_TYPE_LEVEL_HIGH>,
+                                        <52 IRQ_TYPE_LEVEL_HIGH>,
+                                        <56 IRQ_TYPE_LEVEL_HIGH>,
+                                        <60 IRQ_TYPE_LEVEL_HIGH>,
+                                        <64 IRQ_TYPE_LEVEL_HIGH>,
+                                        <68 IRQ_TYPE_LEVEL_HIGH>,
+                                        <72 IRQ_TYPE_LEVEL_HIGH>,
+                                        <128 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-names = "hif0", "hif1", "hif2",
+                                        "hif3", "hif4", "hif5", "hif6", "hif7",
+                                        "hif8", "link";
                                 port-id = <1>;
                                 gop-port-id = <2>;
                                 status = "disabled";
                         };
 
                         CP110_LABEL(eth2): eth2 {
-                                interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
-                                        <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
-                                        <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
-                                        <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
-                                        <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
-                                        <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
-                                interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
-                                        "tx-cpu3", "rx-shared", "link";
+                                interrupts = <41 IRQ_TYPE_LEVEL_HIGH>,
+                                        <45 IRQ_TYPE_LEVEL_HIGH>,
+                                        <49 IRQ_TYPE_LEVEL_HIGH>,
+                                        <53 IRQ_TYPE_LEVEL_HIGH>,
+                                        <57 IRQ_TYPE_LEVEL_HIGH>,
+                                        <61 IRQ_TYPE_LEVEL_HIGH>,
+                                        <65 IRQ_TYPE_LEVEL_HIGH>,
+                                        <69 IRQ_TYPE_LEVEL_HIGH>,
+                                        <73 IRQ_TYPE_LEVEL_HIGH>,
+                                        <127 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-names = "hif0", "hif1", "hif2",
+                                        "hif3", "hif4", "hif5", "hif6", "hif7",
+                                        "hif8", "link";
                                 port-id = <2>;
                                 gop-port-id = <3>;
                                 status = "disabled";
@@ -150,22 +183,31 @@
                 CP110_LABEL(icu): interrupt-controller@1e0000 {
                         compatible = "marvell,cp110-icu";
                         reg = <0x1e0000 0x440>;
-                        #interrupt-cells = <3>;
-                        interrupt-controller;
-                        msi-parent = <&gicp>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        CP110_LABEL(icu_nsr): interrupt-controller@10 {
+                                compatible = "marvell,cp110-icu-nsr";
+                                reg = <0x10 0x20>;
+                                #interrupt-cells = <2>;
+                                interrupt-controller;
+                                msi-parent = <&gicp>;
+                        };
+
+                        CP110_LABEL(icu_sei): interrupt-controller@50 {
+                                compatible = "marvell,cp110-icu-sei";
+                                reg = <0x50 0x10>;
+                                #interrupt-cells = <2>;
+                                interrupt-controller;
+                                msi-parent = <&sei>;
+                        };
                 };
 
                 CP110_LABEL(rtc): rtc@284000 {
                         compatible = "marvell,armada-8k-rtc";
                         reg = <0x284000 0x20>, <0x284080 0x24>;
                         reg-names = "rtc", "rtc-soc";
-                        interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
-                };
-
-                CP110_LABEL(thermal): thermal@400078 {
-                        compatible = "marvell,armada-cp110-thermal";
-                        reg = <0x400078 0x4>,
-                        <0x400070 0x8>;
+                        interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
                 };
 
                 CP110_LABEL(syscon0): system-controller@440000 {
@@ -185,10 +227,10 @@
                                 #gpio-cells = <2>;
                                 gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>;
                                 interrupt-controller;
-                                interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
-                                        <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
-                                        <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
-                                        <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupts = <86 IRQ_TYPE_LEVEL_HIGH>,
+                                        <85 IRQ_TYPE_LEVEL_HIGH>,
+                                        <84 IRQ_TYPE_LEVEL_HIGH>,
+                                        <83 IRQ_TYPE_LEVEL_HIGH>;
                                 status = "disabled";
                         };
 
@@ -200,20 +242,33 @@
                                 #gpio-cells = <2>;
                                 gpio-ranges = <&CP110_LABEL(pinctrl) 0 32 31>;
                                 interrupt-controller;
-                                interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
-                                        <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
-                                        <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
-                                        <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupts = <82 IRQ_TYPE_LEVEL_HIGH>,
+                                        <81 IRQ_TYPE_LEVEL_HIGH>,
+                                        <80 IRQ_TYPE_LEVEL_HIGH>,
+                                        <79 IRQ_TYPE_LEVEL_HIGH>;
                                 status = "disabled";
                         };
                 };
 
+                CP110_LABEL(syscon1): system-controller@400000 {
+                        compatible = "syscon", "simple-mfd";
+                        reg = <0x400000 0x1000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        CP110_LABEL(thermal): thermal-sensor@70 {
+                                compatible = "marvell,armada-cp110-thermal";
+                                reg = <0x70 0x10>;
+                                #thermal-sensor-cells = <1>;
+                        };
+                };
+
                 CP110_LABEL(usb3_0): usb3@500000 {
                         compatible = "marvell,armada-8k-xhci",
                         "generic-xhci";
                         reg = <0x500000 0x4000>;
                         dma-coherent;
-                        interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
                         clock-names = "core", "reg";
                         clocks = <&CP110_LABEL(clk) 1 22>,
                                  <&CP110_LABEL(clk) 1 16>;
@@ -225,7 +280,7 @@
                         "generic-xhci";
                         reg = <0x510000 0x4000>;
                         dma-coherent;
-                        interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <105 IRQ_TYPE_LEVEL_HIGH>;
                         clock-names = "core", "reg";
                         clocks = <&CP110_LABEL(clk) 1 23>,
                                  <&CP110_LABEL(clk) 1 16>;
@@ -237,7 +292,7 @@
                         "generic-ahci";
                         reg = <0x540000 0x30000>;
                         dma-coherent;
-                        interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&CP110_LABEL(clk) 1 15>,
                                  <&CP110_LABEL(clk) 1 16>;
                         status = "disabled";
@@ -290,7 +345,7 @@
                         reg = <0x701000 0x20>;
                         #address-cells = <1>;
                         #size-cells = <0>;
-                        interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <120 IRQ_TYPE_LEVEL_HIGH>;
                         clock-names = "core", "reg";
                         clocks = <&CP110_LABEL(clk) 1 21>,
                                  <&CP110_LABEL(clk) 1 17>;
@@ -302,7 +357,7 @@
                         reg = <0x701100 0x20>;
                         #address-cells = <1>;
                         #size-cells = <0>;
-                        interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <121 IRQ_TYPE_LEVEL_HIGH>;
                         clock-names = "core", "reg";
                         clocks = <&CP110_LABEL(clk) 1 21>,
                                  <&CP110_LABEL(clk) 1 17>;
@@ -313,7 +368,7 @@
                         compatible = "snps,dw-apb-uart";
                         reg = <0x702000 0x100>;
                         reg-shift = <2>;
-                        interrupts = <ICU_GRP_NSR 122 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <122 IRQ_TYPE_LEVEL_HIGH>;
                         reg-io-width = <1>;
                         clock-names = "baudclk", "apb_pclk";
                         clocks = <&CP110_LABEL(clk) 1 21>,
@@ -325,7 +380,7 @@
                         compatible = "snps,dw-apb-uart";
                         reg = <0x702100 0x100>;
                         reg-shift = <2>;
-                        interrupts = <ICU_GRP_NSR 123 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
                         reg-io-width = <1>;
                         clock-names = "baudclk", "apb_pclk";
                         clocks = <&CP110_LABEL(clk) 1 21>,
@@ -337,7 +392,7 @@
                         compatible = "snps,dw-apb-uart";
                         reg = <0x702200 0x100>;
                         reg-shift = <2>;
-                        interrupts = <ICU_GRP_NSR 124 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <124 IRQ_TYPE_LEVEL_HIGH>;
                         reg-io-width = <1>;
                         clock-names = "baudclk", "apb_pclk";
                         clocks = <&CP110_LABEL(clk) 1 21>,
@@ -349,7 +404,7 @@
                         compatible = "snps,dw-apb-uart";
                         reg = <0x702300 0x100>;
                         reg-shift = <2>;
-                        interrupts = <ICU_GRP_NSR 125 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
                         reg-io-width = <1>;
                         clock-names = "baudclk", "apb_pclk";
                         clocks = <&CP110_LABEL(clk) 1 21>,
@@ -368,7 +423,7 @@
                         reg = <0x720000 0x54>;
                         #address-cells = <1>;
                         #size-cells = <0>;
-                        interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <115 IRQ_TYPE_LEVEL_HIGH>;
                         clock-names = "core", "reg";
                         clocks = <&CP110_LABEL(clk) 1 2>,
                                  <&CP110_LABEL(clk) 1 17>;
@@ -380,7 +435,7 @@
                         compatible = "marvell,armada-8k-rng",
                         "inside-secure,safexcel-eip76";
                         reg = <0x760000 0x7d>;
-                        interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
                         clock-names = "core", "reg";
                         clocks = <&CP110_LABEL(clk) 1 25>,
                                  <&CP110_LABEL(clk) 1 17>;
@@ -390,7 +445,7 @@
                 CP110_LABEL(sdhci0): sdhci@780000 {
                         compatible = "marvell,armada-cp110-sdhci";
                         reg = <0x780000 0x300>;
-                        interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
                         clock-names = "core", "axi";
                         clocks = <&CP110_LABEL(clk) 1 4>, <&CP110_LABEL(clk) 1 18>;
                         dma-coherent;
@@ -400,12 +455,12 @@
                 CP110_LABEL(crypto): crypto@800000 {
                         compatible = "inside-secure,safexcel-eip197b";
                         reg = <0x800000 0x200000>;
-                        interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
-                                <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
-                                <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
-                                <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
-                                <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
-                                <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <87 IRQ_TYPE_LEVEL_HIGH>,
+                                <88 IRQ_TYPE_LEVEL_HIGH>,
+                                <89 IRQ_TYPE_LEVEL_HIGH>,
+                                <90 IRQ_TYPE_LEVEL_HIGH>,
+                                <91 IRQ_TYPE_LEVEL_HIGH>,
+                                <92 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-names = "mem", "ring0", "ring1",
                                 "ring2", "ring3", "eip";
                         clock-names = "core", "reg";
@@ -434,8 +489,8 @@
                 /* non-prefetchable memory */
                 0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0  CP110_PCIEx_MEM_BASE(0) 0 0xf00000>;
                 interrupt-map-mask = <0 0 0 0>;
-                interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
-                interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
+                interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
                 num-lanes = <1>;
                 clock-names = "core", "reg";
                 clocks = <&CP110_LABEL(clk) 1 13>, <&CP110_LABEL(clk) 1 14>;
@@ -461,8 +516,8 @@
                 /* non-prefetchable memory */
                 0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0  CP110_PCIEx_MEM_BASE(1) 0 0xf00000>;
                 interrupt-map-mask = <0 0 0 0>;
-                interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
-                interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
+                interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
 
                 num-lanes = <1>;
                 clock-names = "core", "reg";
@@ -489,8 +544,8 @@
                 /* non-prefetchable memory */
                 0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0  CP110_PCIEx_MEM_BASE(2) 0 0xf00000>;
                 interrupt-map-mask = <0 0 0 0>;
-                interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
-                interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;
+                interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
 
                 num-lanes = <1>;
                 clock-names = "core", "reg";
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index 5b7fd6ad96e4..e8f952fb279b 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -5,4 +5,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
 dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index 75cc0f7cc088..ee627a7c7b45 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -301,6 +301,17 @@
                 status = "disabled";
         };
 
+        spis1: spi@10013000 {
+                compatible = "mediatek,mt2712-spi-slave";
+                reg = <0 0x10013000 0 0x100>;
+                interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_LOW>;
+                clocks = <&infracfg CLK_INFRA_AO_SPI1>;
+                clock-names = "spi";
+                assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
+                assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
+                status = "disabled";
+        };
+
         apmixedsys: syscon@10209000 {
                 compatible = "mediatek,mt2712-apmixedsys", "syscon";
                 reg = <0 0x10209000 0 0x1000>;
diff --git a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
new file mode 100644
index 000000000000..5d6005c9b097
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
@@ -0,0 +1,530 @@
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Ryder Lee <ryder.lee@mediatek.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+#include "mt7622.dtsi"
+#include "mt6380.dtsi"
+
+/ {
+        model = "Bananapi BPI-R64";
+        compatible = "bananapi,bpi-r64", "mediatek,mt7622";
+
+        chosen {
+                bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
+        };
+
+        cpus {
+                cpu@0 {
+                        proc-supply = <&mt6380_vcpu_reg>;
+                        sram-supply = <&mt6380_vm_reg>;
+                };
+
+                cpu@1 {
+                        proc-supply = <&mt6380_vcpu_reg>;
+                        sram-supply = <&mt6380_vm_reg>;
+                };
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+
+                factory {
+                        label = "factory";
+                        linux,code = <BTN_0>;
+                        gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
+                };
+
+                wps {
+                        label = "wps";
+                        linux,code = <KEY_WPS_BUTTON>;
+                        gpios = <&pio 102 GPIO_ACTIVE_HIGH>;
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                green {
+                        label = "bpi-r64:pio:green";
+                        gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+
+                red {
+                        label = "bpi-r64:pio:red";
+                        gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+        };
+
+        memory {
+                reg = <0 0x40000000 0 0x40000000>;
+        };
+
+        reg_1p8v: regulator-1p8v {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-1.8V";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                regulator-always-on;
+        };
+
+        reg_3p3v: regulator-3p3v {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-3.3V";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-boot-on;
+                regulator-always-on;
+        };
+
+        reg_5v: regulator-5v {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-5V";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-boot-on;
+                regulator-always-on;
+        };
+};
+
+&bch {
+        status = "disabled";
+};
+
+&btif {
+        status = "okay";
+};
+
+&cir {
+        pinctrl-names = "default";
+        pinctrl-0 = <&irrx_pins>;
+        status = "okay";
+};
+
+&eth {
+        pinctrl-names = "default";
+        pinctrl-0 = <&eth_pins>;
+        status = "okay";
+
+        gmac1: mac@1 {
+                compatible = "mediatek,eth-mac";
+                reg = <1>;
+                phy-handle = <&phy5>;
+        };
+
+        mdio-bus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                phy5: ethernet-phy@5 {
+                        reg = <5>;
+                        phy-mode = "sgmii";
+                };
+        };
+};
+
+&i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c1_pins>;
+        status = "okay";
+};
+
+&i2c2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c2_pins>;
+        status = "okay";
+};
+
+&mmc0 {
+        pinctrl-names = "default", "state_uhs";
+        pinctrl-0 = <&emmc_pins_default>;
+        pinctrl-1 = <&emmc_pins_uhs>;
+        status = "okay";
+        bus-width = <8>;
+        max-frequency = <50000000>;
+        cap-mmc-highspeed;
+        mmc-hs200-1_8v;
+        vmmc-supply = <&reg_3p3v>;
+        vqmmc-supply = <&reg_1p8v>;
+        assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
+        assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
+        non-removable;
+};
+
+&mmc1 {
+        pinctrl-names = "default", "state_uhs";
+        pinctrl-0 = <&sd0_pins_default>;
+        pinctrl-1 = <&sd0_pins_uhs>;
+        status = "okay";
+        bus-width = <4>;
+        max-frequency = <50000000>;
+        cap-sd-highspeed;
+        r_smpl = <1>;
+        cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
+        vmmc-supply = <&reg_3p3v>;
+        vqmmc-supply = <&reg_3p3v>;
+        assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
+        assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
+};
+
+&nandc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&parallel_nand_pins>;
+        status = "disabled";
+};
+
+&nor_flash {
+        pinctrl-names = "default";
+        pinctrl-0 = <&spi_nor_pins>;
+        status = "disabled";
+
+        flash@0 {
+                compatible = "jedec,spi-nor";
+                reg = <0>;
+        };
+};
+
+&pcie {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
+        status = "okay";
+
+        pcie@0,0 {
+                status = "okay";
+        };
+
+        pcie@1,0 {
+                status = "okay";
+        };
+};
+
+&pio {
+        /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
+         * SATA functions. i.e. output-high: PCIe, output-low: SATA
+         */
+        asm_sel {
+                gpio-hog;
+                gpios = <90 GPIO_ACTIVE_HIGH>;
+                output-high;
+        };
+
+        /* eMMC is shared pin with parallel NAND */
+        emmc_pins_default: emmc-pins-default {
+                mux {
+                        function = "emmc", "emmc_rst";
+                        groups = "emmc";
+                };
+
+                /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
+                 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
+                 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
+                 */
+                conf-cmd-dat {
+                        pins = "NDL0", "NDL1", "NDL2",
+                               "NDL3", "NDL4", "NDL5",
+                               "NDL6", "NDL7", "NRB";
+                        input-enable;
+                        bias-pull-up;
+                };
+
+                conf-clk {
+                        pins = "NCLE";
+                        bias-pull-down;
+                };
+        };
+
+        emmc_pins_uhs: emmc-pins-uhs {
+                mux {
+                        function = "emmc";
+                        groups = "emmc";
+                };
+
+                conf-cmd-dat {
+                        pins = "NDL0", "NDL1", "NDL2",
+                               "NDL3", "NDL4", "NDL5",
+                               "NDL6", "NDL7", "NRB";
+                        input-enable;
+                        drive-strength = <4>;
+                        bias-pull-up;
+                };
+
+                conf-clk {
+                        pins = "NCLE";
+                        drive-strength = <4>;
+                        bias-pull-down;
+                };
+        };
+
+        eth_pins: eth-pins {
+                mux {
+                        function = "eth";
+                        groups = "mdc_mdio", "rgmii_via_gmac2";
+                };
+        };
+
+        i2c1_pins: i2c1-pins {
+                mux {
+                        function = "i2c";
+                        groups =  "i2c1_0";
+                };
+        };
+
+        i2c2_pins: i2c2-pins {
+                mux {
+                        function = "i2c";
+                        groups =  "i2c2_0";
+                };
+        };
+
+        i2s1_pins: i2s1-pins {
+                mux {
+                        function = "i2s";
+                        groups =  "i2s_out_mclk_bclk_ws",
+                                  "i2s1_in_data",
+                                  "i2s1_out_data";
+                };
+
+                conf {
+                        pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
+                               "I2S_WS", "I2S_MCLK";
+                        drive-strength = <12>;
+                        bias-pull-down;
+                };
+        };
+
+        irrx_pins: irrx-pins {
+                mux {
+                        function = "ir";
+                        groups =  "ir_1_rx";
+                };
+        };
+
+        irtx_pins: irtx-pins {
+                mux {
+                        function = "ir";
+                        groups =  "ir_1_tx";
+                };
+        };
+
+        /* Parallel nand is shared pin with eMMC */
+        parallel_nand_pins: parallel-nand-pins {
+                mux {
+                        function = "flash";
+                        groups = "par_nand";
+                };
+        };
+
+        pcie0_pins: pcie0-pins {
+                mux {
+                        function = "pcie";
+                        groups = "pcie0_pad_perst",
+                                 "pcie0_1_waken",
+                                 "pcie0_1_clkreq";
+                };
+        };
+
+        pcie1_pins: pcie1-pins {
+                mux {
+                        function = "pcie";
+                        groups = "pcie1_pad_perst",
+                                 "pcie1_0_waken",
+                                 "pcie1_0_clkreq";
+                };
+        };
+
+        pmic_bus_pins: pmic-bus-pins {
+                mux {
+                        function = "pmic";
+                        groups = "pmic_bus";
+                };
+        };
+
+        pwm7_pins: pwm1-2-pins {
+                mux {
+                        function = "pwm";
+                        groups = "pwm_ch7_2";
+                };
+        };
+
+        wled_pins: wled-pins {
+                mux {
+                        function = "led";
+                        groups = "wled";
+                };
+        };
+
+        sd0_pins_default: sd0-pins-default {
+                mux {
+                        function = "sd";
+                        groups = "sd_0";
+                };
+
+                /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
+                 *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
+                 *  DAT2, DAT3, CMD, CLK for SD respectively.
+                 */
+                conf-cmd-data {
+                        pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
+                               "I2S2_IN","I2S4_OUT";
+                        input-enable;
+                        drive-strength = <8>;
+                        bias-pull-up;
+                };
+                conf-clk {
+                        pins = "I2S3_OUT";
+                        drive-strength = <12>;
+                        bias-pull-down;
+                };
+                conf-cd {
+                        pins = "TXD3";
+                        bias-pull-up;
+                };
+        };
+
+        sd0_pins_uhs: sd0-pins-uhs {
+                mux {
+                        function = "sd";
+                        groups = "sd_0";
+                };
+
+                conf-cmd-data {
+                        pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
+                               "I2S2_IN","I2S4_OUT";
+                        input-enable;
+                        bias-pull-up;
+                };
+
+                conf-clk {
+                        pins = "I2S3_OUT";
+                        bias-pull-down;
+                };
+        };
+
+        /* Serial NAND is shared pin with SPI-NOR */
+        serial_nand_pins: serial-nand-pins {
+                mux {
+                        function = "flash";
+                        groups = "snfi";
+                };
+        };
+
+        spic0_pins: spic0-pins {
+                mux {
+                        function = "spi";
+                        groups = "spic0_0";
+                };
+        };
+
+        spic1_pins: spic1-pins {
+                mux {
+                        function = "spi";
+                        groups = "spic1_0";
+                };
+        };
+
+        /* SPI-NOR is shared pin with serial NAND */
+        spi_nor_pins: spi-nor-pins {
+                mux {
+                        function = "flash";
+                        groups = "spi_nor";
+                };
+        };
+
+        /* serial NAND is shared pin with SPI-NOR */
+        serial_nand_pins: serial-nand-pins {
+                mux {
+                        function = "flash";
+                        groups = "snfi";
+                };
+        };
+
+        uart0_pins: uart0-pins {
+                mux {
+                        function = "uart";
+                        groups = "uart0_0_tx_rx" ;
+                };
+        };
+
+        uart2_pins: uart2-pins {
+                mux {
+                        function = "uart";
+                        groups = "uart2_1_tx_rx" ;
+                };
+        };
+
+        watchdog_pins: watchdog-pins {
+                mux {
+                        function = "watchdog";
+                        groups = "watchdog";
+                };
+        };
+};
+
+&pwm {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pwm7_pins>;
+        status = "okay";
+};
+
+&pwrap {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pmic_bus_pins>;
+
+        status = "okay";
+};
+
+&sata {
+        status = "disable";
+};
+
+&sata_phy {
+        status = "disable";
+};
+
+&spi0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&spic0_pins>;
+        status = "okay";
+};
+
+&spi1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&spic1_pins>;
+        status = "okay";
+};
+
+&ssusb {
+        vusb33-supply = <&reg_3p3v>;
+        vbus-supply = <&reg_5v>;
+        status = "okay";
+};
+
+&u3phy {
+        status = "okay";
+};
+
+&uart0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart0_pins>;
+        status = "okay";
+};
+
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart2_pins>;
+        status = "okay";
+};
+
+&watchdog {
+        pinctrl-names = "default";
+        pinctrl-0 = <&watchdog_pins>;
+        status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
index a747b7bf132d..dcad0869b84c 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
@@ -51,7 +51,7 @@
         };
 
         memory {
-                reg = <0 0x40000000 0 0x3F000000>;
+                reg = <0 0x40000000 0 0x20000000>;
         };
 
         reg_1p8v: regulator-1p8v {
@@ -81,6 +81,103 @@
         };
 };
 
+&bch {
+        status = "disabled";
+};
+
+&btif {
+        status = "okay";
+};
+
+&cir {
+        pinctrl-names = "default";
+        pinctrl-0 = <&irrx_pins>;
+        status = "okay";
+};
+
+&eth {
+        pinctrl-names = "default";
+        pinctrl-0 = <&eth_pins>;
+        status = "okay";
+
+        gmac1: mac@1 {
+                compatible = "mediatek,eth-mac";
+                reg = <1>;
+                phy-handle = <&phy5>;
+        };
+
+        mdio-bus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                phy5: ethernet-phy@5 {
+                        reg = <5>;
+                        phy-mode = "sgmii";
+                };
+        };
+};
+
+&i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c1_pins>;
+        status = "okay";
+};
+
+&i2c2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c2_pins>;
+        status = "okay";
+};
+
+&mmc0 {
+        pinctrl-names = "default", "state_uhs";
+        pinctrl-0 = <&emmc_pins_default>;
+        pinctrl-1 = <&emmc_pins_uhs>;
+        status = "okay";
+        bus-width = <8>;
+        max-frequency = <50000000>;
+        cap-mmc-highspeed;
+        mmc-hs200-1_8v;
+        vmmc-supply = <&reg_3p3v>;
+        vqmmc-supply = <&reg_1p8v>;
+        assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
+        assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
+        non-removable;
+};
+
+&mmc1 {
+        pinctrl-names = "default", "state_uhs";
+        pinctrl-0 = <&sd0_pins_default>;
+        pinctrl-1 = <&sd0_pins_uhs>;
+        status = "okay";
+        bus-width = <4>;
+        max-frequency = <50000000>;
+        cap-sd-highspeed;
+        r_smpl = <1>;
+        cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
+        vmmc-supply = <&reg_3p3v>;
+        vqmmc-supply = <&reg_3p3v>;
+        assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
+        assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
+};
+
+&nandc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&parallel_nand_pins>;
+        status = "disabled";
+};
+
+&nor_flash {
+        pinctrl-names = "default";
+        pinctrl-0 = <&spi_nor_pins>;
+        status = "disabled";
+
+        flash@0 {
+                compatible = "jedec,spi-nor";
+                reg = <0>;
+        };
+};
+
 &pcie {
         pinctrl-names = "default";
         pinctrl-0 = <&pcie0_pins>;
@@ -344,103 +441,6 @@
         };
 };
 
-&bch {
-        status = "disabled";
-};
-
-&btif {
-        status = "okay";
-};
-
-&cir {
-        pinctrl-names = "default";
-        pinctrl-0 = <&irrx_pins>;
-        status = "okay";
-};
-
-&eth {
-        pinctrl-names = "default";
-        pinctrl-0 = <&eth_pins>;
-        status = "okay";
-
-        gmac1: mac@1 {
-                compatible = "mediatek,eth-mac";
-                reg = <1>;
-                phy-handle = <&phy5>;
-        };
-
-        mdio-bus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                phy5: ethernet-phy@5 {
-                        reg = <5>;
-                        phy-mode = "sgmii";
-                };
-        };
-};
-
-&i2c1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&i2c1_pins>;
-        status = "okay";
-};
-
-&i2c2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&i2c2_pins>;
-        status = "okay";
-};
-
-&mmc0 {
-        pinctrl-names = "default", "state_uhs";
-        pinctrl-0 = <&emmc_pins_default>;
-        pinctrl-1 = <&emmc_pins_uhs>;
-        status = "okay";
-        bus-width = <8>;
-        max-frequency = <50000000>;
-        cap-mmc-highspeed;
-        mmc-hs200-1_8v;
-        vmmc-supply = <&reg_3p3v>;
-        vqmmc-supply = <&reg_1p8v>;
-        assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
-        assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
-        non-removable;
-};
-
-&mmc1 {
-        pinctrl-names = "default", "state_uhs";
-        pinctrl-0 = <&sd0_pins_default>;
-        pinctrl-1 = <&sd0_pins_uhs>;
-        status = "okay";
-        bus-width = <4>;
-        max-frequency = <50000000>;
-        cap-sd-highspeed;
-        r_smpl = <1>;
-        cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
-        vmmc-supply = <&reg_3p3v>;
-        vqmmc-supply = <&reg_3p3v>;
-        assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
-        assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
-};
-
-&nandc {
-        pinctrl-names = "default";
-        pinctrl-0 = <&parallel_nand_pins>;
-        status = "disabled";
-};
-
-&nor_flash {
-        pinctrl-names = "default";
-        pinctrl-0 = <&spi_nor_pins>;
-        status = "disabled";
-
-        flash@0 {
-                compatible = "jedec,spi-nor";
-                reg = <0>;
-        };
-};
-
 &pwm {
         pinctrl-names = "default";
         pinctrl-0 = <&pwm7_pins>;
diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
index de2c47bdbe64..fe0c875f1d95 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -79,6 +79,7 @@
                         #cooling-cells = <2>;
                         enable-method = "psci";
                         clock-frequency = <1300000000>;
+                        cci-control-port = <&cci_control2>;
                 };
 
                 cpu1: cpu@1 {
@@ -92,6 +93,7 @@
                         #cooling-cells = <2>;
                         enable-method = "psci";
                         clock-frequency = <1300000000>;
+                        cci-control-port = <&cci_control2>;
                 };
         };
 
@@ -113,6 +115,13 @@
                 method      = "smc";
         };
 
+        pmu {
+                compatible = "arm,cortex-a53-pmu";
+                interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
+                             <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
+                interrupt-affinity = <&cpu0>, <&cpu1>;
+        };
+
         reserved-memory {
                 #address-cells = <2>;
                 #size-cells = <2>;
@@ -218,6 +227,16 @@
                 #reset-cells = <1>;
         };
 
+        timer: timer@10004000 {
+                compatible = "mediatek,mt7622-timer",
+                             "mediatek,mt6577-timer";
+                reg = <0 0x10004000 0 0x80>;
+                interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
+                clocks = <&infracfg CLK_INFRA_APXGPT_PD>,
+                         <&topckgen CLK_TOP_RTC>;
+                clock-names = "system-clk", "rtc-clk";
+        };
+
         scpsys: scpsys@10006000 {
                 compatible = "mediatek,mt7622-scpsys",
                              "syscon";
@@ -325,6 +344,42 @@
                       <0 0x10360000 0 0x2000>;
         };
 
+        cci: cci@10390000 {
+                compatible = "arm,cci-400";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0 0x10390000 0 0x1000>;
+                ranges = <0 0 0x10390000 0x10000>;
+
+                cci_control0: slave-if@1000 {
+                        compatible = "arm,cci-400-ctrl-if";
+                        interface-type = "ace-lite";
+                        reg = <0x1000 0x1000>;
+                };
+
+                cci_control1: slave-if@4000 {
+                        compatible = "arm,cci-400-ctrl-if";
+                        interface-type = "ace";
+                        reg = <0x4000 0x1000>;
+                };
+
+                cci_control2: slave-if@5000 {
+                        compatible = "arm,cci-400-ctrl-if";
+                        interface-type = "ace";
+                        reg = <0x5000 0x1000>;
+                };
+
+                pmu@9000 {
+                        compatible = "arm,cci-400-pmu,r1";
+                        reg = <0x9000 0x5000>;
+                        interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+                };
+        };
+
         auxadc: adc@11001000 {
                 compatible = "mediatek,mt7622-auxadc";
                 reg = <0 0x11001000 0 0x1000>;
@@ -475,6 +530,13 @@
                 reg-shift = <2>;
                 reg-io-width = <4>;
                 status = "disabled";
+
+                bluetooth {
+                        compatible = "mediatek,mt7622-bluetooth";
+                        power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
+                        clocks = <&clk25m>;
+                        clock-names = "ref";
+                };
         };
 
         nandc: nfi@1100d000 {
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index b762227f6aa1..2f3c8e29520d 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -4,6 +4,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/mailbox/tegra186-hsp.h>
 #include <dt-bindings/memory/tegra186-mc.h>
+#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
 #include <dt-bindings/power/tegra186-powergate.h>
 #include <dt-bindings/reset/tegra186-reset.h>
 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
@@ -236,6 +237,20 @@
                 clock-names = "sdhci";
                 resets = <&bpmp TEGRA186_RESET_SDMMC1>;
                 reset-names = "sdhci";
+                pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
+                pinctrl-0 = <&sdmmc1_3v3>;
+                pinctrl-1 = <&sdmmc1_1v8>;
+                nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
+                nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
+                nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
+                nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
+                nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>;
+                nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>;
+                nvidia,default-tap = <0x5>;
+                nvidia,default-trim = <0xb>;
+                assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
+                                  <&bpmp TEGRA186_CLK_PLLP_OUT0>;
+                assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
                 status = "disabled";
         };
 
@@ -247,6 +262,15 @@
                 clock-names = "sdhci";
                 resets = <&bpmp TEGRA186_RESET_SDMMC2>;
                 reset-names = "sdhci";
+                pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
+                pinctrl-0 = <&sdmmc2_3v3>;
+                pinctrl-1 = <&sdmmc2_1v8>;
+                nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
+                nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
+                nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
+                nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
+                nvidia,default-tap = <0x5>;
+                nvidia,default-trim = <0xb>;
                 status = "disabled";
         };
 
@@ -258,6 +282,17 @@
                 clock-names = "sdhci";
                 resets = <&bpmp TEGRA186_RESET_SDMMC3>;
                 reset-names = "sdhci";
+                pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
+                pinctrl-0 = <&sdmmc3_3v3>;
+                pinctrl-1 = <&sdmmc3_1v8>;
+                nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
+                nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
+                nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
+                nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
+                nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
+                nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
+                nvidia,default-tap = <0x5>;
+                nvidia,default-trim = <0xb>;
                 status = "disabled";
         };
 
@@ -267,8 +302,19 @@
                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&bpmp TEGRA186_CLK_SDMMC4>;
                 clock-names = "sdhci";
+                assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
+                                  <&bpmp TEGRA186_CLK_PLLC4_VCO>;
+                assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;
                 resets = <&bpmp TEGRA186_RESET_SDMMC4>;
                 reset-names = "sdhci";
+                nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>;
+                nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
+                nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
+                nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
+                nvidia,default-tap = <0x5>;
+                nvidia,default-trim = <0x9>;
+                nvidia,dqs-trim = <63>;
+                mmc-hs400-1_8v;
                 status = "disabled";
         };
 
@@ -368,6 +414,36 @@
                       <0 0x0c380000 0 0x10000>,
                       <0 0x0c390000 0 0x10000>;
                 reg-names = "pmc", "wake", "aotag", "scratch";
+
+                sdmmc1_3v3: sdmmc1-3v3 {
+                        pins = "sdmmc1-hv";
+                        power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
+                };
+
+                sdmmc1_1v8: sdmmc1-1v8 {
+                        pins = "sdmmc1-hv";
+                        power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
+                };
+
+                sdmmc2_3v3: sdmmc2-3v3 {
+                        pins = "sdmmc2-hv";
+                        power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
+                };
+
+                sdmmc2_1v8: sdmmc2-1v8 {
+                        pins = "sdmmc2-hv";
+                        power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
+                };
+
+                sdmmc3_3v3: sdmmc3-3v3 {
+                        pins = "sdmmc3-hv";
+                        power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
+                };
+
+                sdmmc3_1v8: sdmmc3-1v8 {
+                        pins = "sdmmc3-hv";
+                        power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
+                };
         };
 
         ccplex@e000000 {
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index a4dfcd19b9e8..9fc14bb9a0af 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -118,7 +118,7 @@
                 };
 
                 gen1_i2c: i2c@3160000 {
-                        compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
+                        compatible = "nvidia,tegra194-i2c";
                         reg = <0x03160000 0x10000>;
                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
@@ -143,7 +143,7 @@
                 };
 
                 cam_i2c: i2c@3180000 {
-                        compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
+                        compatible = "nvidia,tegra194-i2c";
                         reg = <0x03180000 0x10000>;
                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
@@ -157,7 +157,7 @@
 
                 /* shares pads with dpaux1 */
                 dp_aux_ch1_i2c: i2c@3190000 {
-                        compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
+                        compatible = "nvidia,tegra194-i2c";
                         reg = <0x03190000 0x10000>;
                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
@@ -171,7 +171,7 @@
 
                 /* shares pads with dpaux0 */
                 dp_aux_ch0_i2c: i2c@31b0000 {
-                        compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
+                        compatible = "nvidia,tegra194-i2c";
                         reg = <0x031b0000 0x10000>;
                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
@@ -184,7 +184,7 @@
                 };
 
                 gen7_i2c: i2c@31c0000 {
-                        compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
+                        compatible = "nvidia,tegra194-i2c";
                         reg = <0x031c0000 0x10000>;
                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
@@ -197,7 +197,7 @@
                 };
 
                 gen9_i2c: i2c@31e0000 {
-                        compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
+                        compatible = "nvidia,tegra194-i2c";
                         reg = <0x031e0000 0x10000>;
                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
@@ -264,7 +264,7 @@
                 };
 
                 gen2_i2c: i2c@c240000 {
-                        compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
+                        compatible = "nvidia,tegra194-i2c";
                         reg = <0x0c240000 0x10000>;
                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
@@ -277,7 +277,7 @@
                 };
 
                 gen8_i2c: i2c@c250000 {
-                        compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
+                        compatible = "nvidia,tegra194-i2c";
                         reg = <0x0c250000 0x10000>;
                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
index 212e6634c9ba..053458a5db55 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
@@ -178,16 +178,7 @@
 
                                 vddio_sdmmc: ldo2 {
                                         regulator-name = "VDDIO_SDMMC";
-                                        /*
-                                         * Technically this supply should have
-                                         * a supported range from 1.8 - 3.3 V.
-                                         * However, that would cause the SDHCI
-                                         * driver to request 2.7 V upon access
-                                         * and that in turn will cause traffic
-                                         * to be broken. Leave it at 3.3 V for
-                                         * now.
-                                         */
-                                        regulator-min-microvolt = <3300000>;
+                                        regulator-min-microvolt = <1800000>;
                                         regulator-max-microvolt = <3300000>;
                                         regulator-always-on;
                                         regulator-boot-on;
@@ -282,6 +273,7 @@
                 status = "okay";
                 bus-width = <8>;
                 non-removable;
+                vqmmc-supply = <&vdd_1v8>;
         };
 
         clocks {
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
index 9d5a0e6b2ca4..365726ddd418 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
@@ -1452,7 +1452,6 @@
         sdhci@700b0000 {
                 status = "okay";
                 bus-width = <4>;
-                no-1-8-v;
 
                 cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
 
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 3be920efee82..8fe47d6445a5 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -3,6 +3,7 @@
 #include <dt-bindings/gpio/tegra-gpio.h>
 #include <dt-bindings/memory/tegra210-mc.h>
 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
+#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/thermal/tegra124-soctherm.h>
 
@@ -776,6 +777,26 @@
                                 #power-domain-cells = <0>;
                         };
                 };
+
+                sdmmc1_3v3: sdmmc1-3v3 {
+                        pins = "sdmmc1";
+                        power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
+                };
+
+                sdmmc1_1v8: sdmmc1-1v8 {
+                        pins = "sdmmc1";
+                        power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
+                };
+
+                sdmmc3_3v3: sdmmc3-3v3 {
+                        pins = "sdmmc3";
+                        power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
+                };
+
+                sdmmc3_1v8: sdmmc3-1v8 {
+                        pins = "sdmmc3";
+                        power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
+                };
         };
 
         fuse@7000f800 {
@@ -1027,6 +1048,20 @@
                 clock-names = "sdhci";
                 resets = <&tegra_car 14>;
                 reset-names = "sdhci";
+                pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
+                pinctrl-0 = <&sdmmc1_3v3>;
+                pinctrl-1 = <&sdmmc1_1v8>;
+                nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
+                nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
+                nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
+                nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
+                nvidia,default-tap = <0x2>;
+                nvidia,default-trim = <0x4>;
+                assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
+                                  <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,
+                                  <&tegra_car TEGRA210_CLK_PLL_C4>;
+                assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
+                assigned-clock-rates = <200000000>, <1000000000>, <1000000000>;
                 status = "disabled";
         };
 
@@ -1038,6 +1073,10 @@
                 clock-names = "sdhci";
                 resets = <&tegra_car 9>;
                 reset-names = "sdhci";
+                nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
+                nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
+                nvidia,default-tap = <0x8>;
+                nvidia,default-trim = <0x0>;
                 status = "disabled";
         };
 
@@ -1049,6 +1088,15 @@
                 clock-names = "sdhci";
                 resets = <&tegra_car 69>;
                 reset-names = "sdhci";
+                pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
+                pinctrl-0 = <&sdmmc3_3v3>;
+                pinctrl-1 = <&sdmmc3_1v8>;
+                nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
+                nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
+                nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
+                nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
+                nvidia,default-tap = <0x3>;
+                nvidia,default-trim = <0x3>;
                 status = "disabled";
         };
 
@@ -1060,6 +1108,15 @@
                 clock-names = "sdhci";
                 resets = <&tegra_car 15>;
                 reset-names = "sdhci";
+                nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
+                nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
+                nvidia,default-tap = <0x8>;
+                nvidia,default-trim = <0x0>;
+                assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
+                                  <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
+                assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
+                nvidia,dqs-trim = <40>;
+                mmc-hs400-1_8v;
                 status = "disabled";
         };
 
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 9319e74b8906..a658c07652a7 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -6,4 +6,5 @@ dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-mtp.dtb
 dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb
 dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb
 dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb
+dtb-$(CONFIG_ARCH_QCOM) += msm8998-mtp.dtb
 dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb
diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
index 78ce3979ef09..46feedf7c989 100644
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
@@ -545,6 +545,20 @@
         };
 };
 
+&spmi_bus {
+        pm8916_0: pm8916@0 {
+                pon@800 {
+                        resin {
+                                compatible = "qcom,pm8941-resin";
+                                interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
+                                debounce = <15625>;
+                                bias-pull-up;
+                                linux,code = <KEY_VOLUMEDOWN>;
+                        };
+                };
+        };
+};
+
 &wcd_codec {
         status = "okay";
         clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>;
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts
index 230e9c8484ac..da23bdafbd33 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts
@@ -17,5 +17,5 @@
 
 / {
         model = "Qualcomm Technologies, Inc. DB820c";
-        compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc";
+        compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc", "qcom,apq8096";
 };
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
index 0ef90c6554a9..bf20c55a6bc4 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
@@ -623,3 +623,17 @@
                 };
         };
 };
+
+&spmi_bus {
+        pmic@0 {
+                pon@800 {
+                        resin {
+                                compatible = "qcom,pm8941-resin";
+                                interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
+                                debounce = <15625>;
+                                bias-pull-up;
+                                linux,code = <KEY_VOLUMEDOWN>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 7b32b8990d62..d302d8d639a1 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -18,9 +18,6 @@
 #include <dt-bindings/thermal/thermal.h>
 
 / {
-        model = "Qualcomm Technologies, Inc. MSM8916";
-        compatible = "qcom,msm8916";
-
         interrupt-parent = <&intc>;
 
         #address-cells = <2>;
@@ -1099,10 +1096,11 @@
                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
                         clock-names = "apb_pclk", "atclk";
 
-                        port {
-                                tpiu_in: endpoint {
-                                        slave-mode;
-                                        remote-endpoint = <&replicator_out1>;
+                        in-ports {
+                                port {
+                                        tpiu_in: endpoint {
+                                                remote-endpoint = <&replicator_out1>;
+                                        };
                                 };
                         };
                 };
@@ -1114,7 +1112,7 @@
                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
                         clock-names = "apb_pclk", "atclk";
 
-                        ports {
+                        in-ports {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
 
@@ -1132,12 +1130,13 @@
                                 port@4 {
                                         reg = <4>;
                                         funnel0_in4: endpoint {
-                                                slave-mode;
                                                 remote-endpoint = <&funnel1_out>;
                                         };
                                 };
-                                port@8 {
-                                        reg = <0>;
+                        };
+
+                        out-ports {
+                                port {
                                         funnel0_out: endpoint {
                                                 remote-endpoint = <&etf_in>;
                                         };
@@ -1152,7 +1151,7 @@
                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
                         clock-names = "apb_pclk", "atclk";
 
-                        ports {
+                        out-ports {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
 
@@ -1168,10 +1167,11 @@
                                                 remote-endpoint = <&tpiu_in>;
                                         };
                                 };
-                                port@2 {
-                                        reg = <0>;
+                        };
+
+                        in-ports {
+                                port {
                                         replicator_in: endpoint {
-                                                slave-mode;
                                                 remote-endpoint = <&etf_out>;
                                         };
                                 };
@@ -1185,19 +1185,16 @@
                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
                         clock-names = "apb_pclk", "atclk";
 
-                        ports {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-
-                                port@0 {
-                                        reg = <0>;
+                        in-ports {
+                                port {
                                         etf_in: endpoint {
-                                                slave-mode;
                                                 remote-endpoint = <&funnel0_out>;
                                         };
                                 };
-                                port@1 {
-                                        reg = <0>;
+                        };
+
+                        out-ports {
+                                port {
                                         etf_out: endpoint {
                                                 remote-endpoint = <&replicator_in>;
                                         };
@@ -1212,10 +1209,11 @@
                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
                         clock-names = "apb_pclk", "atclk";
 
-                        port {
-                                etr_in: endpoint {
-                                        slave-mode;
-                                        remote-endpoint = <&replicator_out0>;
+                        in-ports {
+                                port {
+                                        etr_in: endpoint {
+                                                remote-endpoint = <&replicator_out0>;
+                                        };
                                 };
                         };
                 };
@@ -1227,40 +1225,38 @@
                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
                         clock-names = "apb_pclk", "atclk";
 
-                        ports {
+                        in-ports {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
 
                                 port@0 {
                                         reg = <0>;
                                         funnel1_in0: endpoint {
-                                                slave-mode;
                                                 remote-endpoint = <&etm0_out>;
                                         };
                                 };
                                 port@1 {
                                         reg = <1>;
                                         funnel1_in1: endpoint {
-                                                slave-mode;
                                                 remote-endpoint = <&etm1_out>;
                                         };
                                 };
                                 port@2 {
                                         reg = <2>;
                                         funnel1_in2: endpoint {
-                                                slave-mode;
                                                 remote-endpoint = <&etm2_out>;
                                         };
                                 };
                                 port@3 {
                                         reg = <3>;
                                         funnel1_in3: endpoint {
-                                                slave-mode;
                                                 remote-endpoint = <&etm3_out>;
                                         };
                                 };
-                                port@4 {
-                                        reg = <0>;
+                        };
+
+                        out-ports {
+                                port {
                                         funnel1_out: endpoint {
                                                 remote-endpoint = <&funnel0_in4>;
                                         };
@@ -1309,9 +1305,11 @@
 
                         cpu = <&CPU0>;
 
-                        port {
-                                etm0_out: endpoint {
-                                remote-endpoint = <&funnel1_in0>;
+                        out-ports {
+                                port {
+                                        etm0_out: endpoint {
+                                                remote-endpoint = <&funnel1_in0>;
+                                        };
                                 };
                         };
                 };
@@ -1325,9 +1323,11 @@
 
                         cpu = <&CPU1>;
 
-                        port {
-                                etm1_out: endpoint {
-                                        remote-endpoint = <&funnel1_in1>;
+                        out-ports {
+                                port {
+                                        etm1_out: endpoint {
+                                                remote-endpoint = <&funnel1_in1>;
+                                        };
                                 };
                         };
                 };
@@ -1341,9 +1341,11 @@
 
                         cpu = <&CPU2>;
 
-                        port {
-                                etm2_out: endpoint {
-                                        remote-endpoint = <&funnel1_in2>;
+                        out-ports {
+                                port {
+                                        etm2_out: endpoint {
+                                                remote-endpoint = <&funnel1_in2>;
+                                        };
                                 };
                         };
                 };
@@ -1357,9 +1359,11 @@
 
                         cpu = <&CPU3>;
 
-                        port {
-                                etm3_out: endpoint {
-                                        remote-endpoint = <&funnel1_in3>;
+                        out-ports {
+                                port {
+                                        etm3_out: endpoint {
+                                                remote-endpoint = <&funnel1_in3>;
+                                        };
                                 };
                         };
                 };
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index cd3865e7a270..b29fe80d7288 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -16,8 +16,6 @@
 #include <dt-bindings/clock/qcom,rpmcc.h>
 
 / {
-        model = "Qualcomm Technologies, Inc. MSM8996";
-
         interrupt-parent = <&intc>;
 
         #address-cells = <2>;
@@ -409,11 +407,6 @@
                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
                 };
 
-                apcs: syscon@9820000 {
-                        compatible = "syscon";
-                        reg = <0x9820000 0x1000>;
-                };
-
                 apcs_glb: mailbox@9820000 {
                         compatible = "qcom,msm8996-apcs-hmss-global";
                         reg = <0x9820000 0x1000>;
@@ -1140,7 +1133,7 @@
                         interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
 
                         label = "lpass";
-                        qcom,ipc = <&apcs 16 8>;
+                        mboxes = <&apcs_glb 8>;
                         qcom,smd-edge = <1>;
                         qcom,remote-pid = <2>;
                 };
@@ -1152,7 +1145,7 @@
 
                 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
 
-                qcom,ipc = <&apcs 16 10>;
+                mboxes = <&apcs_glb 10>;
 
                 qcom,local-pid = <0>;
                 qcom,remote-pid = <2>;
@@ -1176,7 +1169,7 @@
 
                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
 
-                qcom,ipc = <&apcs 16 14>;
+                mboxes = <&apcs_glb 14>;
 
                 qcom,local-pid = <0>;
                 qcom,remote-pid = <1>;
@@ -1200,7 +1193,7 @@
 
                 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
 
-                qcom,ipc = <&apcs 16 26>;
+                mboxes = <&apcs_glb 26>;
 
                 qcom,local-pid = <0>;
                 qcom,remote-pid = <3>;
diff --git a/arch/arm64/boot/dts/qcom/msm8998-mtp.dts b/arch/arm64/boot/dts/qcom/msm8998-mtp.dts
new file mode 100644
index 000000000000..66540d2ca13b
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8998-mtp.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
+
+/dts-v1/;
+
+#include "msm8998-mtp.dtsi"
+
+/ {
+        model = "Qualcomm Technologies, Inc. MSM8998 v1 MTP";
+        compatible = "qcom,msm8998-mtp";
+
+        qcom,board-id = <8 0>;
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
new file mode 100644
index 000000000000..b4276da1fb0d
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
@@ -0,0 +1,243 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
+
+#include "msm8998.dtsi"
+#include "pm8998.dtsi"
+#include "pmi8998.dtsi"
+#include "pm8005.dtsi"
+
+/ {
+        aliases {
+                serial0 = &blsp2_uart1;
+        };
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+
+        thermal-zones {
+                battery-thermal {
+                        polling-delay-passive = <250>;
+                        polling-delay = <1000>;
+
+                        thermal-sensors = <&tsens0 0>;
+
+                        trips {
+                                battery_crit: trip0 {
+                                        temperature = <60000>;
+                                        hysteresis = <2000>;
+                                        type = "critical";
+                                };
+                        };
+                };
+
+                skin-thermal {
+                        polling-delay-passive = <250>;
+                        polling-delay = <1000>;
+
+                        thermal-sensors = <&tsens1 5>;
+
+                        trips {
+                                skin_alert: trip0 {
+                                        temperature = <44000>;
+                                        hysteresis = <2000>;
+                                        type = "passive";
+                                };
+
+                                skip_crit: trip1 {
+                                        temperature = <70000>;
+                                        hysteresis = <2000>;
+                                        type = "critical";
+                                };
+                        };
+                };
+        };
+
+        vph_pwr: vph-pwr-regulator {
+                compatible = "regulator-fixed";
+                regulator-name = "vph_pwr";
+                regulator-always-on;
+                regulator-boot-on;
+        };
+};
+
+&blsp2_uart1 {
+        status = "okay";
+};
+
+&rpm_requests {
+        pm8998-regulators {
+                compatible = "qcom,rpm-pm8998-regulators";
+
+                vdd_s1-supply = <&vph_pwr>;
+                vdd_s2-supply = <&vph_pwr>;
+                vdd_s3-supply = <&vph_pwr>;
+                vdd_s4-supply = <&vph_pwr>;
+                vdd_s5-supply = <&vph_pwr>;
+                vdd_s6-supply = <&vph_pwr>;
+                vdd_s7-supply = <&vph_pwr>;
+                vdd_s8-supply = <&vph_pwr>;
+                vdd_s9-supply = <&vph_pwr>;
+                vdd_s10-supply = <&vph_pwr>;
+                vdd_s11-supply = <&vph_pwr>;
+                vdd_s12-supply = <&vph_pwr>;
+                vdd_s13-supply = <&vph_pwr>;
+                vdd_l1_l27-supply = <&vreg_s7a_1p025>;
+                vdd_l2_l8_l17-supply = <&vreg_s3a_1p35>;
+                vdd_l3_l11-supply = <&vreg_s7a_1p025>;
+                vdd_l4_l5-supply = <&vreg_s7a_1p025>;
+                vdd_l6-supply = <&vreg_s5a_2p04>;
+                vdd_l7_l12_l14_l15-supply = <&vreg_s5a_2p04>;
+                vdd_l9-supply = <&vreg_bob>;
+                vdd_l10_l23_l25-supply = <&vreg_bob>;
+                vdd_l13_l19_l21-supply = <&vreg_bob>;
+                vdd_l16_l28-supply = <&vreg_bob>;
+                vdd_l18_l22-supply = <&vreg_bob>;
+                vdd_l20_l24-supply = <&vreg_bob>;
+                vdd_l26-supply = <&vreg_s3a_1p35>;
+                vdd_lvs1_lvs2-supply = <&vreg_s4a_1p8>;
+
+                vreg_s3a_1p35: s3 {
+                        regulator-min-microvolt = <1352000>;
+                        regulator-max-microvolt = <1352000>;
+                };
+                vreg_s4a_1p8: s4 {
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                };
+                vreg_s5a_2p04: s5 {
+                        regulator-min-microvolt = <1904000>;
+                        regulator-max-microvolt = <2040000>;
+                };
+                vreg_s7a_1p025: s7 {
+                        regulator-min-microvolt = <900000>;
+                        regulator-max-microvolt = <1028000>;
+                };
+                vreg_l1a_0p875: l1 {
+                        regulator-min-microvolt = <880000>;
+                        regulator-max-microvolt = <880000>;
+                };
+                vreg_l2a_1p2: l2 {
+                        regulator-min-microvolt = <1200000>;
+                        regulator-max-microvolt = <1200000>;
+                };
+                vreg_l3a_1p0: l3 {
+                        regulator-min-microvolt = <1000000>;
+                        regulator-max-microvolt = <1000000>;
+                };
+                vreg_l5a_0p8: l5 {
+                        regulator-min-microvolt = <800000>;
+                        regulator-max-microvolt = <800000>;
+                };
+                vreg_l6a_1p8: l6 {
+                        regulator-min-microvolt = <1808000>;
+                        regulator-max-microvolt = <1808000>;
+                };
+                vreg_l7a_1p8: l7 {
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                };
+                vreg_l8a_1p2: l8 {
+                        regulator-min-microvolt = <1200000>;
+                        regulator-max-microvolt = <1200000>;
+                };
+                vreg_l9a_1p8: l9 {
+                        regulator-min-microvolt = <1808000>;
+                        regulator-max-microvolt = <2960000>;
+                };
+                vreg_l10a_1p8: l10 {
+                        regulator-min-microvolt = <1808000>;
+                        regulator-max-microvolt = <2960000>;
+                };
+                vreg_l11a_1p0: l11 {
+                        regulator-min-microvolt = <1000000>;
+                        regulator-max-microvolt = <1000000>;
+                };
+                vreg_l12a_1p8: l12 {
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                };
+                vreg_l13a_2p95: l13 {
+                        regulator-min-microvolt = <1808000>;
+                        regulator-max-microvolt = <2960000>;
+                };
+                vreg_l14a_1p88: l14 {
+                        regulator-min-microvolt = <1880000>;
+                        regulator-max-microvolt = <1880000>;
+                };
+                vreg_15a_1p8: l15 {
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                };
+                vreg_l16a_2p7: l16 {
+                        regulator-min-microvolt = <2704000>;
+                        regulator-max-microvolt = <2704000>;
+                };
+                vreg_l17a_1p3: l17 {
+                        regulator-min-microvolt = <1304000>;
+                        regulator-max-microvolt = <1304000>;
+                };
+                vreg_l18a_2p7: l18 {
+                        regulator-min-microvolt = <2704000>;
+                        regulator-max-microvolt = <2704000>;
+                };
+                vreg_l19a_3p0: l19 {
+                        regulator-min-microvolt = <3008000>;
+                        regulator-max-microvolt = <3008000>;
+                };
+                vreg_l20a_2p95: l20 {
+                        regulator-min-microvolt = <2960000>;
+                        regulator-max-microvolt = <2960000>;
+                };
+                vreg_l21a_2p95: l21 {
+                        regulator-min-microvolt = <2960000>;
+                        regulator-max-microvolt = <2960000>;
+                };
+                vreg_l22a_2p85: l22 {
+                        regulator-min-microvolt = <2864000>;
+                        regulator-max-microvolt = <2864000>;
+                };
+                vreg_l23a_3p3: l23 {
+                        regulator-min-microvolt = <3312000>;
+                        regulator-max-microvolt = <3312000>;
+                };
+                vreg_l24a_3p075: l24 {
+                        regulator-min-microvolt = <3088000>;
+                        regulator-max-microvolt = <3088000>;
+                };
+                vreg_l25a_3p3: l25 {
+                        regulator-min-microvolt = <3104000>;
+                        regulator-max-microvolt = <3312000>;
+                };
+                vreg_l26a_1p2: l26 {
+                        regulator-min-microvolt = <1200000>;
+                        regulator-max-microvolt = <1200000>;
+                };
+                vreg_l28_3p0: l28 {
+                        regulator-min-microvolt = <3008000>;
+                        regulator-max-microvolt = <3008000>;
+                };
+
+                vreg_lvs1a_1p8: lvs1 {
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                };
+
+                vreg_lvs2a_1p8: lvs2 {
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                };
+
+        };
+
+        pmi8998-regulators {
+                compatible = "qcom,rpm-pmi8998-regulators";
+
+                vdd_bob-supply = <&vph_pwr>;
+
+                vreg_bob: bob {
+                        regulator-min-microvolt = <3312000>;
+                        regulator-max-microvolt = <3600000>;
+                };
+        };
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
new file mode 100644
index 000000000000..78227cce16db
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -0,0 +1,690 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,gcc-msm8998.h>
+
+/ {
+        interrupt-parent = <&intc>;
+
+        qcom,msm-id = <292 0x0>;
+
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        chosen { };
+
+        memory {
+                device_type = "memory";
+                /* We expect the bootloader to fill in the reg */
+                reg = <0 0 0 0>;
+        };
+
+        reserved-memory {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
+
+                memory@85800000 {
+                        reg = <0x0 0x85800000 0x0 0x800000>;
+                        no-map;
+                };
+
+                smem_mem: smem-mem@86000000 {
+                        reg = <0x0 0x86000000 0x0 0x200000>;
+                        no-map;
+                };
+
+                memory@86200000 {
+                        reg = <0x0 0x86200000 0x0 0x2600000>;
+                        no-map;
+                };
+
+                rmtfs {
+                        compatible = "qcom,rmtfs-mem";
+
+                        size = <0x0 0x200000>;
+                        alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
+                        no-map;
+
+                        qcom,client-id = <1>;
+                        qcom,vmid = <15>;
+                };
+        };
+
+        clocks {
+                xo_board {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <19200000>;
+                };
+
+                sleep_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <32764>;
+                };
+        };
+
+        cpus {
+                #address-cells = <2>;
+                #size-cells = <0>;
+
+                CPU0: cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,armv8";
+                        reg = <0x0 0x0>;
+                        enable-method = "psci";
+                        efficiency = <1024>;
+                        next-level-cache = <&L2_0>;
+                        L2_0: l2-cache {
+                                compatible = "arm,arch-cache";
+                                cache-level = <2>;
+                        };
+                        L1_I_0: l1-icache {
+                                compatible = "arm,arch-cache";
+                        };
+                        L1_D_0: l1-dcache {
+                                compatible = "arm,arch-cache";
+                        };
+                };
+
+                CPU1: cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,armv8";
+                        reg = <0x0 0x1>;
+                        enable-method = "psci";
+                        efficiency = <1024>;
+                        next-level-cache = <&L2_0>;
+                        L1_I_1: l1-icache {
+                                compatible = "arm,arch-cache";
+                        };
+                        L1_D_1: l1-dcache {
+                                compatible = "arm,arch-cache";
+                        };
+                };
+
+                CPU2: cpu@2 {
+                        device_type = "cpu";
+                        compatible = "arm,armv8";
+                        reg = <0x0 0x2>;
+                        enable-method = "psci";
+                        efficiency = <1024>;
+                        next-level-cache = <&L2_0>;
+                        L1_I_2: l1-icache {
+                                compatible = "arm,arch-cache";
+                        };
+                        L1_D_2: l1-dcache {
+                                compatible = "arm,arch-cache";
+                        };
+                };
+
+                CPU3: cpu@3 {
+                        device_type = "cpu";
+                        compatible = "arm,armv8";
+                        reg = <0x0 0x3>;
+                        enable-method = "psci";
+                        efficiency = <1024>;
+                        next-level-cache = <&L2_0>;
+                        L1_I_3: l1-icache {
+                                compatible = "arm,arch-cache";
+                        };
+                        L1_D_3: l1-dcache {
+                                compatible = "arm,arch-cache";
+                        };
+                };
+
+                CPU4: cpu@100 {
+                        device_type = "cpu";
+                        compatible = "arm,armv8";
+                        reg = <0x0 0x100>;
+                        enable-method = "psci";
+                        efficiency = <1536>;
+                        next-level-cache = <&L2_1>;
+                        L2_1: l2-cache {
+                                compatible = "arm,arch-cache";
+                                cache-level = <2>;
+                        };
+                        L1_I_100: l1-icache {
+                                compatible = "arm,arch-cache";
+                        };
+                        L1_D_100: l1-dcache {
+                                compatible = "arm,arch-cache";
+                        };
+                };
+
+                CPU5: cpu@101 {
+                        device_type = "cpu";
+                        compatible = "arm,armv8";
+                        reg = <0x0 0x101>;
+                        enable-method = "psci";
+                        efficiency = <1536>;
+                        next-level-cache = <&L2_1>;
+                        L1_I_101: l1-icache {
+                                compatible = "arm,arch-cache";
+                        };
+                        L1_D_101: l1-dcache {
+                                compatible = "arm,arch-cache";
+                        };
+                };
+
+                CPU6: cpu@102 {
+                        device_type = "cpu";
+                        compatible = "arm,armv8";
+                        reg = <0x0 0x102>;
+                        enable-method = "psci";
+                        efficiency = <1536>;
+                        next-level-cache = <&L2_1>;
+                        L1_I_102: l1-icache {
+                                compatible = "arm,arch-cache";
+                        };
+                        L1_D_102: l1-dcache {
+                                compatible = "arm,arch-cache";
+                        };
+                };
+
+                CPU7: cpu@103 {
+                        device_type = "cpu";
+                        compatible = "arm,armv8";
+                        reg = <0x0 0x103>;
+                        enable-method = "psci";
+                        efficiency = <1536>;
+                        next-level-cache = <&L2_1>;
+                        L1_I_103: l1-icache {
+                                compatible = "arm,arch-cache";
+                        };
+                        L1_D_103: l1-dcache {
+                                compatible = "arm,arch-cache";
+                        };
+                };
+
+                cpu-map {
+                        cluster0 {
+                                core0 {
+                                        cpu = <&CPU0>;
+                                };
+
+                                core1 {
+                                        cpu = <&CPU1>;
+                                };
+
+                                core2 {
+                                        cpu = <&CPU2>;
+                                };
+
+                                core3 {
+                                        cpu = <&CPU3>;
+                                };
+                        };
+
+                        cluster1 {
+                                core0 {
+                                        cpu = <&CPU4>;
+                                };
+
+                                core1 {
+                                        cpu = <&CPU5>;
+                                };
+
+                                core2 {
+                                        cpu = <&CPU6>;
+                                };
+
+                                core3 {
+                                        cpu = <&CPU7>;
+                                };
+                        };
+                };
+        };
+
+        firmware {
+                scm {
+                        compatible = "qcom,scm-msm8998";
+                };
+        };
+
+        tcsr_mutex: hwlock {
+                compatible = "qcom,tcsr-mutex";
+                syscon = <&tcsr_mutex_regs 0 0x1000>;
+                #hwlock-cells = <1>;
+        };
+
+        psci {
+                compatible = "arm,psci-1.0";
+                method = "smc";
+        };
+
+        rpm-glink {
+                compatible = "qcom,glink-rpm";
+
+                interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+                qcom,rpm-msg-ram = <&rpm_msg_ram>;
+                mboxes = <&apcs_glb 0>;
+
+                rpm_requests: rpm-requests {
+                        compatible = "qcom,rpm-msm8998";
+                        qcom,glink-channels = "rpm_requests";
+                };
+        };
+
+        smem {
+                compatible = "qcom,smem";
+                memory-region = <&smem_mem>;
+                hwlocks = <&tcsr_mutex 3>;
+        };
+
+        smp2p-lpass {
+                compatible = "qcom,smp2p";
+                qcom,smem = <443>, <429>;
+
+                interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
+
+                mboxes = <&apcs_glb 10>;
+
+                qcom,local-pid = <0>;
+                qcom,remote-pid = <2>;
+
+                adsp_smp2p_out: master-kernel {
+                        qcom,entry-name = "master-kernel";
+                        #qcom,smem-state-cells = <1>;
+                };
+
+                adsp_smp2p_in: slave-kernel {
+                        qcom,entry-name = "slave-kernel";
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+        };
+
+        smp2p-mpss {
+                compatible = "qcom,smp2p";
+                qcom,smem = <435>, <428>;
+                interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
+                mboxes = <&apcs_glb 14>;
+                qcom,local-pid = <0>;
+                qcom,remote-pid = <1>;
+
+                modem_smp2p_out: master-kernel {
+                        qcom,entry-name = "master-kernel";
+                        #qcom,smem-state-cells = <1>;
+                };
+
+                modem_smp2p_in: slave-kernel {
+                        qcom,entry-name = "slave-kernel";
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+        };
+
+        smp2p-slpi {
+                compatible = "qcom,smp2p";
+                qcom,smem = <481>, <430>;
+                interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
+                mboxes = <&apcs_glb 26>;
+                qcom,local-pid = <0>;
+                qcom,remote-pid = <3>;
+
+                slpi_smp2p_out: master-kernel {
+                        qcom,entry-name = "master-kernel";
+                        #qcom,smem-state-cells = <1>;
+                };
+
+                slpi_smp2p_in: slave-kernel {
+                        qcom,entry-name = "slave-kernel";
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+        };
+
+        thermal-zones {
+                cpu-thermal0 {
+                        polling-delay-passive = <250>;
+                        polling-delay = <1000>;
+
+                        thermal-sensors = <&tsens0 6>;
+
+                        trips {
+                                cpu_alert0: trip0 {
+                                        temperature = <75000>;
+                                        hysteresis = <2000>;
+                                        type = "passive";
+                                };
+
+                                cpu_crit0: trip1 {
+                                        temperature = <110000>;
+                                        hysteresis = <2000>;
+                                        type = "critical";
+                                };
+                        };
+                };
+
+                cpu-thermal1 {
+                        polling-delay-passive = <250>;
+                        polling-delay = <1000>;
+
+                        thermal-sensors = <&tsens0 7>;
+
+                        trips {
+                                cpu_alert1: trip0 {
+                                        temperature = <75000>;
+                                        hysteresis = <2000>;
+                                        type = "passive";
+                                };
+
+                                cpu_crit1: trip1 {
+                                        temperature = <110000>;
+                                        hysteresis = <2000>;
+                                        type = "critical";
+                                };
+                        };
+                };
+
+                cpu-thermal2 {
+                        polling-delay-passive = <250>;
+                        polling-delay = <1000>;
+
+                        thermal-sensors = <&tsens0 8>;
+
+                        trips {
+                                cpu_alert2: trip0 {
+                                        temperature = <75000>;
+                                        hysteresis = <2000>;
+                                        type = "passive";
+                                };
+
+                                cpu_crit2: trip1 {
+                                        temperature = <110000>;
+                                        hysteresis = <2000>;
+                                        type = "critical";
+                                };
+                        };
+                };
+
+                cpu-thermal3 {
+                        polling-delay-passive = <250>;
+                        polling-delay = <1000>;
+
+                        thermal-sensors = <&tsens0 9>;
+
+                        trips {
+                                cpu_alert3: trip0 {
+                                        temperature = <75000>;
+                                        hysteresis = <2000>;
+                                        type = "passive";
+                                };
+
+                                cpu_crit3: trip1 {
+                                        temperature = <110000>;
+                                        hysteresis = <2000>;
+                                        type = "critical";
+                                };
+                        };
+                };
+
+                cpu-thermal4 {
+                        polling-delay-passive = <250>;
+                        polling-delay = <1000>;
+
+                        thermal-sensors = <&tsens0 10>;
+
+                        trips {
+                                cpu_alert4: trip0 {
+                                        temperature = <75000>;
+                                        hysteresis = <2000>;
+                                        type = "passive";
+                                };
+
+                                cpu_crit4: trip1 {
+                                        temperature = <110000>;
+                                        hysteresis = <2000>;
+                                        type = "critical";
+                                };
+                        };
+                };
+
+                cpu-thermal5 {
+                        polling-delay-passive = <250>;
+                        polling-delay = <1000>;
+
+                        thermal-sensors = <&tsens0 11>;
+
+                        trips {
+                                cpu_alert5: trip0 {
+                                        temperature = <75000>;
+                                        hysteresis = <2000>;
+                                        type = "passive";
+                                };
+
+                                cpu_crit5: trip1 {
+                                        temperature = <110000>;
+                                        hysteresis = <2000>;
+                                        type = "critical";
+                                };
+                        };
+                };
+
+                cpu-thermal6 {
+                        polling-delay-passive = <250>;
+                        polling-delay = <1000>;
+
+                        thermal-sensors = <&tsens1 0>;
+
+                        trips {
+                                cpu_alert6: trip0 {
+                                        temperature = <75000>;
+                                        hysteresis = <2000>;
+                                        type = "passive";
+                                };
+
+                                cpu_crit6: trip1 {
+                                        temperature = <110000>;
+                                        hysteresis = <2000>;
+                                        type = "critical";
+                                };
+                        };
+                };
+
+                cpu-thermal7 {
+                        polling-delay-passive = <250>;
+                        polling-delay = <1000>;
+
+                        thermal-sensors = <&tsens1 1>;
+
+                        trips {
+                                cpu_alert7: trip0 {
+                                        temperature = <75000>;
+                                        hysteresis = <2000>;
+                                        type = "passive";
+                                };
+
+                                cpu_crit7: trip1 {
+                                        temperature = <110000>;
+                                        hysteresis = <2000>;
+                                        type = "critical";
+                                };
+                        };
+                };
+
+                gpu-thermal {
+                        polling-delay-passive = <250>;
+                        polling-delay = <1000>;
+
+                        thermal-sensors = <&tsens1 3>;
+                };
+        };
+
+        timer {
+                compatible = "arm,armv8-timer";
+                interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
+                             <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
+                             <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
+                             <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
+        };
+
+        soc: soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0 0 0 0xffffffff>;
+                compatible = "simple-bus";
+
+                rpm_msg_ram: memory@68000 {
+                        compatible = "qcom,rpm-msg-ram";
+                        reg = <0x778000 0x7000>;
+                };
+
+                qfprom: qfprom@780000 {
+                        compatible = "qcom,qfprom";
+                        reg = <0x780000 0x621c>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                };
+
+                gcc: clock-controller@100000 {
+                        compatible = "qcom,gcc-msm8998";
+                        #clock-cells = <1>;
+                        #reset-cells = <1>;
+                        #power-domain-cells = <1>;
+                        reg = <0x100000 0xb0000>;
+                };
+
+                tlmm: pinctrl@3400000 {
+                        compatible = "qcom,msm8998-pinctrl";
+                        reg = <0x3400000 0xc00000>;
+                        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+                        gpio-controller;
+                        #gpio-cells = <0x2>;
+                        interrupt-controller;
+                        #interrupt-cells = <0x2>;
+                };
+
+                spmi_bus: spmi@800f000 {
+                        compatible = "qcom,spmi-pmic-arb";
+                        reg =   <0x800f000 0x1000>,
+                                <0x8400000 0x1000000>,
+                                <0x9400000 0x1000000>,
+                                <0xa400000 0x220000>,
+                                <0x800a000 0x3000>;
+                        reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+                        interrupt-names = "periph_irq";
+                        interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
+                        qcom,ee = <0>;
+                        qcom,channel = <0>;
+                        #address-cells = <2>;
+                        #size-cells = <0>;
+                        interrupt-controller;
+                        #interrupt-cells = <4>;
+                        cell-index = <0>;
+                };
+
+                tsens0: thermal@10aa000 {
+                        compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
+                        reg = <0x10aa000 0x2000>;
+
+                        #qcom,sensors = <12>;
+                        #thermal-sensor-cells = <1>;
+                };
+
+                tsens1: thermal@10ad000 {
+                        compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
+                        reg = <0x10ad000 0x2000>;
+
+                        #qcom,sensors = <8>;
+                        #thermal-sensor-cells = <1>;
+                };
+
+                tcsr_mutex_regs: syscon@1f40000 {
+                        compatible = "syscon";
+                        reg = <0x1f40000 0x20000>;
+                };
+
+                apcs_glb: mailbox@9820000 {
+                        compatible = "qcom,msm8998-apcs-hmss-global";
+                        reg = <0x17911000 0x1000>;
+
+                        #mbox-cells = <1>;
+                };
+
+                blsp2_uart1: serial@c1b0000 {
+                        compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+                        reg = <0xc1b0000 0x1000>;
+                        interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
+                                 <&gcc GCC_BLSP2_AHB_CLK>;
+                        clock-names = "core", "iface";
+                        status = "disabled";
+                };
+
+                timer@17920000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+                        compatible = "arm,armv7-timer-mem";
+                        reg = <0x17920000 0x1000>;
+
+                        frame@17921000 {
+                                frame-number = <0>;
+                                interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+                                             <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+                                reg = <0x17921000 0x1000>,
+                                      <0x17922000 0x1000>;
+                        };
+
+                        frame@17923000 {
+                                frame-number = <1>;
+                                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+                                reg = <0x17923000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        frame@17924000 {
+                                frame-number = <2>;
+                                interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+                                reg = <0x17924000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        frame@17925000 {
+                                frame-number = <3>;
+                                interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+                                reg = <0x17925000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        frame@17926000 {
+                                frame-number = <4>;
+                                interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+                                reg = <0x17926000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        frame@17927000 {
+                                frame-number = <5>;
+                                interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+                                reg = <0x17927000 0x1000>;
+                                status = "disabled";
+                        };
+
+                        frame@17928000 {
+                                frame-number = <6>;
+                                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+                                reg = <0x17928000 0x1000>;
+                                status = "disabled";
+                        };
+                };
+
+                intc: interrupt-controller@17a00000 {
+                        compatible = "arm,gic-v3";
+                        reg = <0x17a00000 0x10000>,       /* GICD */
+                              <0x17b00000 0x100000>;      /* GICR * 8 */
+                        #interrupt-cells = <3>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+                        interrupt-controller;
+                        #redistributor-regions = <1>;
+                        redistributor-stride = <0x0 0x20000>;
+                        interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+                };
+        };
+};
diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi
index 196b1c0ceb9b..15a37cbcd216 100644
--- a/arch/arm64/boot/dts/qcom/pm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 #include <dt-bindings/iio/qcom,spmi-vadc.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/input/linux-event-codes.h>
 #include <dt-bindings/spmi/spmi.h>
 
 &spmi_bus {
@@ -18,12 +19,19 @@
                         interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
                 };
 
-                pwrkey@800 {
-                        compatible = "qcom,pm8941-pwrkey";
+                pon@800 {
+                        compatible = "qcom,pm8916-pon";
                         reg = <0x800>;
-                        interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
-                        debounce = <15625>;
-                        bias-pull-up;
+                        mode-bootloader = <0x2>;
+                        mode-recovery = <0x1>;
+
+                        pwrkey {
+                                compatible = "qcom,pm8941-pwrkey";
+                                interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
+                                debounce = <15625>;
+                                bias-pull-up;
+                                linux,code = <KEY_POWER>;
+                        };
                 };
 
                 pm8916_gpios: gpios@c000 {
diff --git a/arch/arm64/boot/dts/qcom/pm8994.dtsi b/arch/arm64/boot/dts/qcom/pm8994.dtsi
index 80024c0b1c7c..76b5a3e6a2b5 100644
--- a/arch/arm64/boot/dts/qcom/pm8994.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8994.dtsi
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/input/linux-event-codes.h>
 
 &spmi_bus {
 
@@ -17,6 +18,23 @@
                         interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
                 };
 
+                pon@800 {
+                        compatible = "qcom,pm8916-pon";
+
+                        reg = <0x800>;
+                        mode-bootloader = <0x2>;
+                        mode-recovery = <0x1>;
+
+                        pwrkey {
+                                compatible = "qcom,pm8941-pwrkey";
+                                interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
+                                debounce = <15625>;
+                                bias-pull-up;
+                                linux,code = <KEY_POWER>;
+                        };
+
+                };
+
                 pm8994_gpios: gpios@c000 {
                         compatible = "qcom,pm8994-gpio";
                         reg = <0xc000>;
diff --git a/arch/arm64/boot/dts/qcom/pm8998.dtsi b/arch/arm64/boot/dts/qcom/pm8998.dtsi
index 92bed1e7d4bb..048f19fa0150 100644
--- a/arch/arm64/boot/dts/qcom/pm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8998.dtsi
@@ -1,8 +1,35 @@
 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /* Copyright 2018 Google LLC. */
 
-#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/input/linux-event-codes.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+        thermal-zones {
+                pm8998 {
+                        polling-delay-passive = <250>;
+                        polling-delay = <1000>;
+
+                        thermal-sensors = <&pm8998_temp>;
+
+                        trips {
+                                pm8998_alert0: pm8998-alert0 {
+                                        temperature = <105000>;
+                                        hysteresis = <2000>;
+                                        type = "passive";
+                                };
+                                pm8998_crit: pm8998-crit {
+                                        temperature = <125000>;
+                                        hysteresis = <2000>;
+                                        type = "critical";
+                                };
+                        };
+                };
+        };
+};
 
 &spmi_bus {
         pm8998_lsid0: pmic@0 {
@@ -11,6 +38,52 @@
                 #address-cells = <1>;
                 #size-cells = <0>;
 
+                pm8998_pon: pon@800 {
+                        compatible = "qcom,pm8916-pon";
+
+                        reg = <0x800>;
+                        mode-bootloader = <0x2>;
+                        mode-recovery = <0x1>;
+
+                        pwrkey {
+                                compatible = "qcom,pm8941-pwrkey";
+                                interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
+                                debounce = <15625>;
+                                bias-pull-up;
+                                linux,code = <KEY_POWER>;
+                        };
+                };
+
+                pm8998_temp: temp-alarm@2400 {
+                        compatible = "qcom,spmi-temp-alarm";
+                        reg = <0x2400>;
+                        interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
+                        #thermal-sensor-cells = <0>;
+                };
+
+                pm8998_coincell: coincell@2800 {
+                        compatible = "qcom,pm8941-coincell";
+                        reg = <0x2800>;
+
+                        status = "disabled";
+                };
+
+                pm8998_adc: adc@3100 {
+                        compatible = "qcom,spmi-adc-rev2";
+                        reg = <0x3100>;
+                        interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        #io-channel-cells = <1>;
+                };
+
+                rtc@6000 {
+                        compatible = "qcom,pm8941-rtc";
+                        reg = <0x6000>, <0x6100>;
+                        reg-names = "rtc", "alarm";
+                        interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
+                };
+
                 pm8998_gpio: gpios@c000 {
                         compatible = "qcom,pm8998-gpio", "qcom,spmi-gpio";
                         reg = <0xc000>;
diff --git a/arch/arm64/boot/dts/qcom/pmi8998.dtsi b/arch/arm64/boot/dts/qcom/pmi8998.dtsi
new file mode 100644
index 000000000000..da3285e216e2
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pmi8998.dtsi
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+        pmi8998_lsid0: pmic@2 {
+                compatible = "qcom,pmi8998", "qcom,spmi-pmic";
+                reg = <0x2 SPMI_USID>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                pmi8998_gpio: gpios@c000 {
+                        compatible = "qcom,pmi8998-gpio", "qcom,spmi-gpio";
+                        reg = <0xc000>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupts = <0 0xc0 0 IRQ_TYPE_NONE>,
+                                     <0 0xc1 0 IRQ_TYPE_NONE>,
+                                     <0 0xc2 0 IRQ_TYPE_NONE>,
+                                     <0 0xc3 0 IRQ_TYPE_NONE>,
+                                     <0 0xc4 0 IRQ_TYPE_NONE>,
+                                     <0 0xc5 0 IRQ_TYPE_NONE>,
+                                     <0 0xc6 0 IRQ_TYPE_NONE>,
+                                     <0 0xc7 0 IRQ_TYPE_NONE>,
+                                     <0 0xc8 0 IRQ_TYPE_NONE>,
+                                     <0 0xc9 0 IRQ_TYPE_NONE>,
+                                     <0 0xca 0 IRQ_TYPE_NONE>,
+                                     <0 0xcb 0 IRQ_TYPE_NONE>,
+                                     <0 0xcc 0 IRQ_TYPE_NONE>,
+                                     <0 0xcd 0 IRQ_TYPE_NONE>;
+                };
+        };
+
+        pmi8998_lsid1: pmic@3 {
+                compatible = "qcom,pmi8998", "qcom,spmi-pmic";
+                reg = <0x3 SPMI_USID>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
index 6d651f314193..eedfaf8922e2 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
@@ -7,6 +7,7 @@
 
 /dts-v1/;
 
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
 #include "sdm845.dtsi"
 
 / {
@@ -20,6 +21,326 @@
         chosen {
                 stdout-path = "serial0:115200n8";
         };
+
+        vph_pwr: vph-pwr-regulator {
+                compatible = "regulator-fixed";
+                regulator-name = "vph_pwr";
+                regulator-min-microvolt = <3700000>;
+                regulator-max-microvolt = <3700000>;
+        };
+
+        /*
+         * Apparently RPMh does not provide support for PM8998 S4 because it
+         * is always-on; model it as a fixed regulator.
+         */
+        vreg_s4a_1p8: pm8998-smps4 {
+                compatible = "regulator-fixed";
+                regulator-name = "vreg_s4a_1p8";
+
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+
+                regulator-always-on;
+                regulator-boot-on;
+
+                vin-supply = <&vph_pwr>;
+        };
+};
+
+&apps_rsc {
+        pm8998-rpmh-regulators {
+                compatible = "qcom,pm8998-rpmh-regulators";
+                qcom,pmic-id = "a";
+
+                vdd-s1-supply = <&vph_pwr>;
+                vdd-s2-supply = <&vph_pwr>;
+                vdd-s3-supply = <&vph_pwr>;
+                vdd-s4-supply = <&vph_pwr>;
+                vdd-s5-supply = <&vph_pwr>;
+                vdd-s6-supply = <&vph_pwr>;
+                vdd-s7-supply = <&vph_pwr>;
+                vdd-s8-supply = <&vph_pwr>;
+                vdd-s9-supply = <&vph_pwr>;
+                vdd-s10-supply = <&vph_pwr>;
+                vdd-s11-supply = <&vph_pwr>;
+                vdd-s12-supply = <&vph_pwr>;
+                vdd-s13-supply = <&vph_pwr>;
+                vdd-l1-l27-supply = <&vreg_s7a_1p025>;
+                vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>;
+                vdd-l3-l11-supply = <&vreg_s7a_1p025>;
+                vdd-l4-l5-supply = <&vreg_s7a_1p025>;
+                vdd-l6-supply = <&vph_pwr>;
+                vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>;
+                vdd-l9-supply = <&vreg_bob>;
+                vdd-l10-l23-l25-supply = <&vreg_bob>;
+                vdd-l13-l19-l21-supply = <&vreg_bob>;
+                vdd-l16-l28-supply = <&vreg_bob>;
+                vdd-l18-l22-supply = <&vreg_bob>;
+                vdd-l20-l24-supply = <&vreg_bob>;
+                vdd-l26-supply = <&vreg_s3a_1p35>;
+                vin-lvs-1-2-supply = <&vreg_s4a_1p8>;
+
+                vreg_s2a_1p125: smps2 {
+                        regulator-min-microvolt = <1100000>;
+                        regulator-max-microvolt = <1100000>;
+                };
+
+                vreg_s3a_1p35: smps3 {
+                        regulator-min-microvolt = <1352000>;
+                        regulator-max-microvolt = <1352000>;
+                };
+
+                vreg_s5a_2p04: smps5 {
+                        regulator-min-microvolt = <1904000>;
+                        regulator-max-microvolt = <2040000>;
+                };
+
+                vreg_s7a_1p025: smps7 {
+                        regulator-min-microvolt = <900000>;
+                        regulator-max-microvolt = <1028000>;
+                };
+
+                vdd_qusb_hs0:
+                vdda_hp_pcie_core:
+                vdda_mipi_csi0_0p9:
+                vdda_mipi_csi1_0p9:
+                vdda_mipi_csi2_0p9:
+                vdda_mipi_dsi0_pll:
+                vdda_mipi_dsi1_pll:
+                vdda_qlink_lv:
+                vdda_qlink_lv_ck:
+                vdda_qrefs_0p875:
+                vdda_pcie_core:
+                vdda_pll_cc_ebi01:
+                vdda_pll_cc_ebi23:
+                vdda_sp_sensor:
+                vdda_ufs1_core:
+                vdda_ufs2_core:
+                vdda_usb1_ss_core:
+                vdda_usb2_ss_core:
+                vreg_l1a_0p875: ldo1 {
+                        regulator-min-microvolt = <880000>;
+                        regulator-max-microvolt = <880000>;
+                        regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+                };
+
+                vddpx_10:
+                vreg_l2a_1p2: ldo2 {
+                        regulator-min-microvolt = <1200000>;
+                        regulator-max-microvolt = <1200000>;
+                        regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+                        regulator-always-on;
+                };
+
+                vreg_l3a_1p0: ldo3 {
+                        regulator-min-microvolt = <1000000>;
+                        regulator-max-microvolt = <1000000>;
+                        regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+                };
+
+                vdd_wcss_cx:
+                vdd_wcss_mx:
+                vdda_wcss_pll:
+                vreg_l5a_0p8: ldo5 {
+                        regulator-min-microvolt = <800000>;
+                        regulator-max-microvolt = <800000>;
+                        regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+                };
+
+                vddpx_13:
+                vreg_l6a_1p8: ldo6 {
+                        regulator-min-microvolt = <1856000>;
+                        regulator-max-microvolt = <1856000>;
+                        regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+                };
+
+                vreg_l7a_1p8: ldo7 {
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                        regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+                };
+
+                vreg_l8a_1p2: ldo8 {
+                        regulator-min-microvolt = <1200000>;
+                        regulator-max-microvolt = <1248000>;
+                        regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+                };
+
+                vreg_l9a_1p8: ldo9 {
+                        regulator-min-microvolt = <1704000>;
+                        regulator-max-microvolt = <2928000>;
+                        regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+                };
+
+                vreg_l10a_1p8: ldo10 {
+                        regulator-min-microvolt = <1704000>;
+                        regulator-max-microvolt = <2928000>;
+                        regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+                };
+
+                vreg_l11a_1p0: ldo11 {
+                        regulator-min-microvolt = <1000000>;
+                        regulator-max-microvolt = <1048000>;
+                        regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+                };
+
+                vdd_qfprom:
+                vdd_qfprom_sp:
+                vdda_apc1_cs_1p8:
+                vdda_gfx_cs_1p8:
+                vdda_qrefs_1p8:
+                vdda_qusb_hs0_1p8:
+                vddpx_11:
+                vreg_l12a_1p8: ldo12 {
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                        regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+                };
+
+                vddpx_2:
+                vreg_l13a_2p95: ldo13 {
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <2960000>;
+                        regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+                };
+
+                vreg_l14a_1p88: ldo14 {
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                        regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+                };
+
+                vreg_l15a_1p8: ldo15 {
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                        regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+                };
+
+                vreg_l16a_2p7: ldo16 {
+                        regulator-min-microvolt = <2704000>;
+                        regulator-max-microvolt = <2704000>;
+                        regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+                };
+
+                vreg_l17a_1p3: ldo17 {
+                        regulator-min-microvolt = <1304000>;
+                        regulator-max-microvolt = <1304000>;
+                        regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+                };
+
+                vreg_l18a_2p7: ldo18 {
+                        regulator-min-microvolt = <2704000>;
+                        regulator-max-microvolt = <2960000>;
+                        regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+                };
+
+                vreg_l19a_3p0: ldo19 {
+                        regulator-min-microvolt = <2856000>;
+                        regulator-max-microvolt = <3104000>;
+                        regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+                };
+
+                vreg_l20a_2p95: ldo20 {
+                        regulator-min-microvolt = <2704000>;
+                        regulator-max-microvolt = <2960000>;
+                        regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+                };
+
+                vreg_l21a_2p95: ldo21 {
+                        regulator-min-microvolt = <2704000>;
+                        regulator-max-microvolt = <2960000>;
+                        regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+                };
+
+                vreg_l22a_2p85: ldo22 {
+                        regulator-min-microvolt = <2864000>;
+                        regulator-max-microvolt = <3312000>;
+                        regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+                };
+
+                vreg_l23a_3p3: ldo23 {
+                        regulator-min-microvolt = <3000000>;
+                        regulator-max-microvolt = <3312000>;
+                        regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+                };
+
+                vdda_qusb_hs0_3p1:
+                vreg_l24a_3p075: ldo24 {
+                        regulator-min-microvolt = <3088000>;
+                        regulator-max-microvolt = <3088000>;
+                        regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+                };
+
+                vreg_l25a_3p3: ldo25 {
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3312000>;
+                        regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+                };
+
+                vdda_hp_pcie_1p2:
+                vdda_hv_ebi0:
+                vdda_hv_ebi1:
+                vdda_hv_ebi2:
+                vdda_hv_ebi3:
+                vdda_mipi_csi_1p25:
+                vdda_mipi_dsi0_1p2:
+                vdda_mipi_dsi1_1p2:
+                vdda_pcie_1p2:
+                vdda_ufs1_1p2:
+                vdda_ufs2_1p2:
+                vdda_usb1_ss_1p2:
+                vdda_usb2_ss_1p2:
+                vreg_l26a_1p2: ldo26 {
+                        regulator-min-microvolt = <1200000>;
+                        regulator-max-microvolt = <1200000>;
+                        regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+                };
+
+                vreg_l28a_3p0: ldo28 {
+                        regulator-min-microvolt = <2856000>;
+                        regulator-max-microvolt = <3008000>;
+                        regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+                };
+
+                vreg_lvs1a_1p8: lvs1 {
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                };
+
+                vreg_lvs2a_1p8: lvs2 {
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                };
+        };
+
+        pmi8998-rpmh-regulators {
+                compatible = "qcom,pmi8998-rpmh-regulators";
+                qcom,pmic-id = "b";
+
+                vdd-bob-supply = <&vph_pwr>;
+
+                vreg_bob: bob {
+                        regulator-min-microvolt = <3312000>;
+                        regulator-max-microvolt = <3600000>;
+                        regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+                        regulator-allow-bypass;
+                };
+        };
+
+        pm8005-rpmh-regulators {
+                compatible = "qcom,pm8005-rpmh-regulators";
+                qcom,pmic-id = "c";
+
+                vdd-s1-supply = <&vph_pwr>;
+                vdd-s2-supply = <&vph_pwr>;
+                vdd-s3-supply = <&vph_pwr>;
+                vdd-s4-supply = <&vph_pwr>;
+
+                vreg_s3c_0p6: smps3 {
+                        regulator-min-microvolt = <600000>;
+                        regulator-max-microvolt = <600000>;
+                };
+        };
 };
 
 &i2c10 {
@@ -35,6 +356,67 @@
         status = "okay";
 };
 
+&usb_1 {
+        status = "okay";
+};
+
+&usb_1_dwc3 {
+        /* Until we have Type C hooked up we'll force this as host. */
+        dr_mode = "host";
+};
+
+&usb_1_hsphy {
+        status = "okay";
+
+        vdd-supply = <&vdda_usb1_ss_core>;
+        vdda-pll-supply = <&vdda_qusb_hs0_1p8>;
+        vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>;
+
+        qcom,imp-res-offset-value = <8>;
+        qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
+        qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>;
+        qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>;
+};
+
+&usb_1_qmpphy {
+        status = "okay";
+
+        vdda-phy-supply = <&vdda_usb1_ss_1p2>;
+        vdda-pll-supply = <&vdda_usb1_ss_core>;
+};
+
+&usb_2 {
+        status = "okay";
+};
+
+&usb_2_dwc3 {
+        /*
+         * Though the USB block on SDM845 can support host, there's no vbus
+         * signal for this port on MTP.  Thus (unless you have a non-compliant
+         * hub that works without vbus) the only sensible thing is to force
+         * peripheral mode.
+         */
+        dr_mode = "peripheral";
+};
+
+&usb_2_hsphy {
+        status = "okay";
+
+        vdd-supply = <&vdda_usb2_ss_core>;
+        vdda-pll-supply = <&vdda_qusb_hs0_1p8>;
+        vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>;
+
+        qcom,imp-res-offset-value = <8>;
+        qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>;
+};
+
+&usb_2_qmpphy {
+        status = "okay";
+
+        vdda-phy-supply = <&vdda_usb2_ss_1p2>;
+        vdda-pll-supply = <&vdda_usb2_ss_core>;
+};
+
 /* PINCTRL - additions to nodes defined in sdm845.dtsi */
 
 &qup_i2c10_default {
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 0c9a2aa6a1b5..b72bdb0a31a5 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -5,9 +5,12 @@
  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
  */
 
+#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy-qcom-qusb2.h>
+#include <dt-bindings/reset/qcom,sdm845-aoss.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
 
 / {
@@ -230,6 +233,94 @@
                 hwlocks = <&tcsr_mutex 3>;
         };
 
+        smp2p-cdsp {
+                compatible = "qcom,smp2p";
+                qcom,smem = <94>, <432>;
+
+                interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
+
+                mboxes = <&apss_shared 6>;
+
+                qcom,local-pid = <0>;
+                qcom,remote-pid = <5>;
+
+                cdsp_smp2p_out: master-kernel {
+                        qcom,entry-name = "master-kernel";
+                        #qcom,smem-state-cells = <1>;
+                };
+
+                cdsp_smp2p_in: slave-kernel {
+                        qcom,entry-name = "slave-kernel";
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+        };
+
+        smp2p-lpass {
+                compatible = "qcom,smp2p";
+                qcom,smem = <443>, <429>;
+
+                interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
+
+                mboxes = <&apss_shared 10>;
+
+                qcom,local-pid = <0>;
+                qcom,remote-pid = <2>;
+
+                adsp_smp2p_out: master-kernel {
+                        qcom,entry-name = "master-kernel";
+                        #qcom,smem-state-cells = <1>;
+                };
+
+                adsp_smp2p_in: slave-kernel {
+                        qcom,entry-name = "slave-kernel";
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+        };
+
+        smp2p-mpss {
+                compatible = "qcom,smp2p";
+                qcom,smem = <435>, <428>;
+                interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
+                mboxes = <&apss_shared 14>;
+                qcom,local-pid = <0>;
+                qcom,remote-pid = <1>;
+
+                modem_smp2p_out: master-kernel {
+                        qcom,entry-name = "master-kernel";
+                        #qcom,smem-state-cells = <1>;
+                };
+
+                modem_smp2p_in: slave-kernel {
+                        qcom,entry-name = "slave-kernel";
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+        };
+
+        smp2p-slpi {
+                compatible = "qcom,smp2p";
+                qcom,smem = <481>, <430>;
+                interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
+                mboxes = <&apss_shared 26>;
+                qcom,local-pid = <0>;
+                qcom,remote-pid = <3>;
+
+                slpi_smp2p_out: master-kernel {
+                        qcom,entry-name = "master-kernel";
+                        #qcom,smem-state-cells = <1>;
+                };
+
+                slpi_smp2p_in: slave-kernel {
+                        qcom,entry-name = "slave-kernel";
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+        };
+
         psci {
                 compatible = "arm,psci-1.0";
                 method = "smc";
@@ -249,6 +340,23 @@
                         #power-domain-cells = <1>;
                 };
 
+                qfprom@784000 {
+                        compatible = "qcom,qfprom";
+                        reg = <0x784000 0x8ff>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        qusb2p_hstx_trim: hstx-trim-primary@1eb {
+                                reg = <0x1eb 0x1>;
+                                bits = <1 4>;
+                        };
+
+                        qusb2s_hstx_trim: hstx-trim-secondary@1eb {
+                                reg = <0x1eb 0x2>;
+                                bits = <6 4>;
+                        };
+                };
+
                 qupv3_id_0: geniqup@8c0000 {
                         compatible = "qcom,geni-se-qup";
                         reg = <0x8c0000 0x6000>;
@@ -962,6 +1070,192 @@
                         };
                 };
 
+                usb_1_hsphy: phy@88e2000 {
+                        compatible = "qcom,sdm845-qusb2-phy";
+                        reg = <0x88e2000 0x400>;
+                        status = "disabled";
+                        #phy-cells = <0>;
+
+                        clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+                                 <&rpmhcc RPMH_CXO_CLK>;
+                        clock-names = "cfg_ahb", "ref";
+
+                        resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+
+                        nvmem-cells = <&qusb2p_hstx_trim>;
+                };
+
+                usb_2_hsphy: phy@88e3000 {
+                        compatible = "qcom,sdm845-qusb2-phy";
+                        reg = <0x88e3000 0x400>;
+                        status = "disabled";
+                        #phy-cells = <0>;
+
+                        clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+                                 <&rpmhcc RPMH_CXO_CLK>;
+                        clock-names = "cfg_ahb", "ref";
+
+                        resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
+
+                        nvmem-cells = <&qusb2s_hstx_trim>;
+                };
+
+                usb_1_qmpphy: phy@88e9000 {
+                        compatible = "qcom,sdm845-qmp-usb3-phy";
+                        reg = <0x88e9000 0x18c>,
+                              <0x88e8000 0x10>;
+                        reg-names = "reg-base", "dp_com";
+                        status = "disabled";
+                        #clock-cells = <1>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+                                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+                                 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+                                 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
+                        clock-names = "aux", "cfg_ahb", "ref", "com_aux";
+
+                        resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
+                                 <&gcc GCC_USB3_PHY_PRIM_BCR>;
+                        reset-names = "phy", "common";
+
+                        usb_1_ssphy: lane@88e9200 {
+                                reg = <0x88e9200 0x128>,
+                                      <0x88e9400 0x200>,
+                                      <0x88e9c00 0x218>,
+                                      <0x88e9a00 0x100>;
+                                #phy-cells = <0>;
+                                clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+                                clock-names = "pipe0";
+                                clock-output-names = "usb3_phy_pipe_clk_src";
+                        };
+                };
+
+                usb_2_qmpphy: phy@88eb000 {
+                        compatible = "qcom,sdm845-qmp-usb3-uni-phy";
+                        reg = <0x88eb000 0x18c>;
+                        status = "disabled";
+                        #clock-cells = <1>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
+                                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+                                 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
+                                 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
+                        clock-names = "aux", "cfg_ahb", "ref", "com_aux";
+
+                        resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
+                                 <&gcc GCC_USB3_PHY_SEC_BCR>;
+                        reset-names = "phy", "common";
+
+                        usb_2_ssphy: lane@88eb200 {
+                                reg = <0x88eb200 0x128>,
+                                      <0x88eb400 0x1fc>,
+                                      <0x88eb800 0x218>,
+                                      <0x88e9600 0x70>;
+                                #phy-cells = <0>;
+                                clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
+                                clock-names = "pipe0";
+                                clock-output-names = "usb3_uni_phy_pipe_clk_src";
+                        };
+                };
+
+                usb_1: usb@a6f8800 {
+                        compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
+                        reg = <0xa6f8800 0x400>;
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+                                 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+                                 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+                                 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+                                 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
+                        clock-names = "cfg_noc", "core", "iface", "mock_utmi",
+                                      "sleep";
+
+                        assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+                                          <&gcc GCC_USB30_PRIM_MASTER_CLK>;
+                        assigned-clock-rates = <19200000>, <150000000>;
+
+                        interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "hs_phy_irq", "ss_phy_irq",
+                                          "dm_hs_phy_irq", "dp_hs_phy_irq";
+
+                        power-domains = <&gcc USB30_PRIM_GDSC>;
+
+                        resets = <&gcc GCC_USB30_PRIM_BCR>;
+
+                        usb_1_dwc3: dwc3@a600000 {
+                                compatible = "snps,dwc3";
+                                reg = <0xa600000 0xcd00>;
+                                interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+                                snps,dis_u2_susphy_quirk;
+                                snps,dis_enblslpm_quirk;
+                                phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
+                                phy-names = "usb2-phy", "usb3-phy";
+                        };
+                };
+
+                usb_2: usb@a8f8800 {
+                        compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
+                        reg = <0xa8f8800 0x400>;
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
+                                 <&gcc GCC_USB30_SEC_MASTER_CLK>,
+                                 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
+                                 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
+                                 <&gcc GCC_USB30_SEC_SLEEP_CLK>;
+                        clock-names = "cfg_noc", "core", "iface", "mock_utmi",
+                                      "sleep";
+
+                        assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
+                                          <&gcc GCC_USB30_SEC_MASTER_CLK>;
+                        assigned-clock-rates = <19200000>, <150000000>;
+
+                        interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "hs_phy_irq", "ss_phy_irq",
+                                          "dm_hs_phy_irq", "dp_hs_phy_irq";
+
+                        power-domains = <&gcc USB30_SEC_GDSC>;
+
+                        resets = <&gcc GCC_USB30_SEC_BCR>;
+
+                        usb_2_dwc3: dwc3@a800000 {
+                                compatible = "snps,dwc3";
+                                reg = <0xa800000 0xcd00>;
+                                interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+                                snps,dis_u2_susphy_quirk;
+                                snps,dis_enblslpm_quirk;
+                                phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
+                                phy-names = "usb2-phy", "usb3-phy";
+                        };
+                };
+
+                dispcc: clock-controller@af00000 {
+                        compatible = "qcom,sdm845-dispcc";
+                        reg = <0xaf00000 0x10000>;
+                        #clock-cells = <1>;
+                        #reset-cells = <1>;
+                        #power-domain-cells = <1>;
+                };
+
                 tsens0: thermal-sensor@c263000 {
                         compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
                         reg = <0xc263000 0x1ff>, /* TM */
@@ -978,6 +1272,12 @@
                         #thermal-sensor-cells = <1>;
                 };
 
+                aoss_reset: reset-controller@c2a0000 {
+                        compatible = "qcom,sdm845-aoss-cc";
+                        reg = <0xc2a0000 0x31000>;
+                        #reset-cells = <1>;
+                };
+
                 spmi_bus: spmi@c440000 {
                         compatible = "qcom,spmi-pmic-arb";
                         reg = <0xc440000 0x1100>,
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 9e2394bc3c62..a8ce6594342d 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -8,6 +8,8 @@ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb
 dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb
 dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb
 dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb r8a77965-salvator-xs.dtb
+dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-m3nulcb.dtb
+dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-m3nulcb-kf.dtb
 dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb
 dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb r8a77980-v3hsk.dtb
 dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-ebisu.dtb
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
new file mode 100644
index 000000000000..012cbb64246e
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -0,0 +1,1663 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the r8a774a1 SoC
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/ {
+        compatible = "renesas,r8a774a1";
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        aliases {
+                i2c0 = &i2c0;
+                i2c1 = &i2c1;
+                i2c2 = &i2c2;
+                i2c3 = &i2c3;
+                i2c4 = &i2c4;
+                i2c5 = &i2c5;
+                i2c6 = &i2c6;
+                i2c7 = &i2c_dvfs;
+        };
+
+        /*
+         * The external audio clocks are configured as 0 Hz fixed frequency
+         * clocks by default.
+         * Boards that provide audio clocks should override them.
+         */
+        audio_clk_a: audio_clk_a {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+
+        audio_clk_b: audio_clk_b {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+
+        audio_clk_c: audio_clk_c {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+
+        /* External CAN clock - to be overridden by boards that provide it */
+        can_clk: can {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                a57_0: cpu@0 {
+                        compatible = "arm,cortex-a57", "arm,armv8";
+                        reg = <0x0>;
+                        device_type = "cpu";
+                        power-domains = <&sysc 0>;
+                        next-level-cache = <&L2_CA57>;
+                        enable-method = "psci";
+                        clocks = <&cpg CPG_CORE 0>;
+                };
+
+                a57_1: cpu@1 {
+                        compatible = "arm,cortex-a57", "arm,armv8";
+                        reg = <0x1>;
+                        device_type = "cpu";
+                        power-domains = <&sysc 1>;
+                        next-level-cache = <&L2_CA57>;
+                        enable-method = "psci";
+                        clocks = <&cpg CPG_CORE 0>;
+                };
+
+                a53_0: cpu@100 {
+                        compatible = "arm,cortex-a53", "arm,armv8";
+                        reg = <0x100>;
+                        device_type = "cpu";
+                        power-domains = <&sysc 5>;
+                        next-level-cache = <&L2_CA53>;
+                        enable-method = "psci";
+                        clocks =<&cpg CPG_CORE 1>;
+                };
+
+                a53_1: cpu@101 {
+                        compatible = "arm,cortex-a53", "arm,armv8";
+                        reg = <0x101>;
+                        device_type = "cpu";
+                        power-domains = <&sysc 6>;
+                        next-level-cache = <&L2_CA53>;
+                        enable-method = "psci";
+                        clocks =<&cpg CPG_CORE 1>;
+                };
+
+                a53_2: cpu@102 {
+                        compatible = "arm,cortex-a53", "arm,armv8";
+                        reg = <0x102>;
+                        device_type = "cpu";
+                        power-domains = <&sysc 7>;
+                        next-level-cache = <&L2_CA53>;
+                        enable-method = "psci";
+                        clocks =<&cpg CPG_CORE 1>;
+                };
+
+                a53_3: cpu@103 {
+                        compatible = "arm,cortex-a53", "arm,armv8";
+                        reg = <0x103>;
+                        device_type = "cpu";
+                        power-domains = <&sysc 8>;
+                        next-level-cache = <&L2_CA53>;
+                        enable-method = "psci";
+                        clocks =<&cpg CPG_CORE 1>;
+                };
+
+                L2_CA57: cache-controller-0 {
+                        compatible = "cache";
+                        power-domains = <&sysc 12>;
+                        cache-unified;
+                        cache-level = <2>;
+                };
+
+                L2_CA53: cache-controller-1 {
+                        compatible = "cache";
+                        power-domains = <&sysc 21>;
+                        cache-unified;
+                        cache-level = <2>;
+                };
+        };
+
+        extal_clk: extal {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                /* This value must be overridden by the board */
+                clock-frequency = <0>;
+        };
+
+        extalr_clk: extalr {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                /* This value must be overridden by the board */
+                clock-frequency = <0>;
+        };
+
+        /* External PCIe clock - can be overridden by the board */
+        pcie_bus_clk: pcie_bus {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+
+        pmu_a53 {
+                compatible = "arm,cortex-a53-pmu";
+                interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+                                      <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+                                      <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+                                      <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
+        };
+
+        pmu_a57 {
+                compatible = "arm,cortex-a57-pmu";
+                interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+                                      <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-affinity = <&a57_0>, <&a57_1>;
+        };
+
+        psci {
+                compatible = "arm,psci-1.0", "arm,psci-0.2";
+                method = "smc";
+        };
+
+        /* External SCIF clock - to be overridden by boards that provide it */
+        scif_clk: scif {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+
+        soc {
+                compatible = "simple-bus";
+                interrupt-parent = <&gic>;
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
+
+                rwdt: watchdog@e6020000 {
+                        compatible = "renesas,r8a774a1-wdt",
+                                     "renesas,rcar-gen3-wdt";
+                        reg = <0 0xe6020000 0 0x0c>;
+                        clocks = <&cpg CPG_MOD 402>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 402>;
+                        status = "disabled";
+                };
+
+                gpio0: gpio@e6050000 {
+                        compatible = "renesas,gpio-r8a774a1",
+                                     "renesas,rcar-gen3-gpio";
+                        reg = <0 0xe6050000 0 0x50>;
+                        interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 0 16>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 912>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 912>;
+                };
+
+                gpio1: gpio@e6051000 {
+                        compatible = "renesas,gpio-r8a774a1",
+                                     "renesas,rcar-gen3-gpio";
+                        reg = <0 0xe6051000 0 0x50>;
+                        interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 32 29>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 911>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 911>;
+                };
+
+                gpio2: gpio@e6052000 {
+                        compatible = "renesas,gpio-r8a774a1",
+                                     "renesas,rcar-gen3-gpio";
+                        reg = <0 0xe6052000 0 0x50>;
+                        interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 64 15>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 910>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 910>;
+                };
+
+                gpio3: gpio@e6053000 {
+                        compatible = "renesas,gpio-r8a774a1",
+                                     "renesas,rcar-gen3-gpio";
+                        reg = <0 0xe6053000 0 0x50>;
+                        interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 96 16>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 909>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 909>;
+                };
+
+                gpio4: gpio@e6054000 {
+                        compatible = "renesas,gpio-r8a774a1",
+                                     "renesas,rcar-gen3-gpio";
+                        reg = <0 0xe6054000 0 0x50>;
+                        interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 128 18>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 908>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 908>;
+                };
+
+                gpio5: gpio@e6055000 {
+                        compatible = "renesas,gpio-r8a774a1",
+                                     "renesas,rcar-gen3-gpio";
+                        reg = <0 0xe6055000 0 0x50>;
+                        interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 160 26>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 907>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 907>;
+                };
+
+                gpio6: gpio@e6055400 {
+                        compatible = "renesas,gpio-r8a774a1",
+                                     "renesas,rcar-gen3-gpio";
+                        reg = <0 0xe6055400 0 0x50>;
+                        interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 192 32>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 906>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 906>;
+                };
+
+                gpio7: gpio@e6055800 {
+                        compatible = "renesas,gpio-r8a774a1",
+                                     "renesas,rcar-gen3-gpio";
+                        reg = <0 0xe6055800 0 0x50>;
+                        interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 224 4>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 905>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 905>;
+                };
+
+                pfc: pin-controller@e6060000 {
+                        compatible = "renesas,pfc-r8a774a1";
+                        reg = <0 0xe6060000 0 0x50c>;
+                };
+
+                cpg: clock-controller@e6150000 {
+                        compatible = "renesas,r8a774a1-cpg-mssr";
+                        reg = <0 0xe6150000 0 0x0bb0>;
+                        clocks = <&extal_clk>, <&extalr_clk>;
+                        clock-names = "extal", "extalr";
+                        #clock-cells = <2>;
+                        #power-domain-cells = <0>;
+                        #reset-cells = <1>;
+                };
+
+                rst: reset-controller@e6160000 {
+                        compatible = "renesas,r8a774a1-rst";
+                        reg = <0 0xe6160000 0 0x018c>;
+                };
+
+                sysc: system-controller@e6180000 {
+                        compatible = "renesas,r8a774a1-sysc";
+                        reg = <0 0xe6180000 0 0x0400>;
+                        #power-domain-cells = <1>;
+                };
+
+                tsc: thermal@e6198000 {
+                        compatible = "renesas,r8a774a1-thermal";
+                        reg = <0 0xe6198000 0 0x100>,
+                              <0 0xe61a0000 0 0x100>,
+                              <0 0xe61a8000 0 0x100>;
+                        interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 522>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 522>;
+                        #thermal-sensor-cells = <1>;
+                };
+
+                intc_ex: interrupt-controller@e61c0000 {
+                        compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc";
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        reg = <0 0xe61c0000 0 0x200>;
+                        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 407>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 407>;
+                };
+
+                i2c0: i2c@e6500000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a774a1",
+                                     "renesas,rcar-gen3-i2c";
+                        reg = <0 0xe6500000 0 0x40>;
+                        interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 931>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 931>;
+                        dmas = <&dmac1 0x91>, <&dmac1 0x90>,
+                               <&dmac2 0x91>, <&dmac2 0x90>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        i2c-scl-internal-delay-ns = <110>;
+                        status = "disabled";
+                };
+
+                i2c1: i2c@e6508000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a774a1",
+                                     "renesas,rcar-gen3-i2c";
+                        reg = <0 0xe6508000 0 0x40>;
+                        interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 930>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 930>;
+                        dmas = <&dmac1 0x93>, <&dmac1 0x92>,
+                               <&dmac2 0x93>, <&dmac2 0x92>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        i2c-scl-internal-delay-ns = <6>;
+                        status = "disabled";
+                };
+
+                i2c2: i2c@e6510000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a774a1",
+                                     "renesas,rcar-gen3-i2c";
+                        reg = <0 0xe6510000 0 0x40>;
+                        interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 929>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 929>;
+                        dmas = <&dmac1 0x95>, <&dmac1 0x94>,
+                               <&dmac2 0x95>, <&dmac2 0x94>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        i2c-scl-internal-delay-ns = <6>;
+                        status = "disabled";
+                };
+
+                i2c3: i2c@e66d0000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a774a1",
+                                     "renesas,rcar-gen3-i2c";
+                        reg = <0 0xe66d0000 0 0x40>;
+                        interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 928>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 928>;
+                        dmas = <&dmac0 0x97>, <&dmac0 0x96>;
+                        dma-names = "tx", "rx";
+                        i2c-scl-internal-delay-ns = <110>;
+                        status = "disabled";
+                };
+
+                i2c4: i2c@e66d8000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a774a1",
+                                     "renesas,rcar-gen3-i2c";
+                        reg = <0 0xe66d8000 0 0x40>;
+                        interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 927>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 927>;
+                        dmas = <&dmac0 0x99>, <&dmac0 0x98>;
+                        dma-names = "tx", "rx";
+                        i2c-scl-internal-delay-ns = <110>;
+                        status = "disabled";
+                };
+
+                i2c5: i2c@e66e0000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a774a1",
+                                     "renesas,rcar-gen3-i2c";
+                        reg = <0 0xe66e0000 0 0x40>;
+                        interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 919>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 919>;
+                        dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
+                        dma-names = "tx", "rx";
+                        i2c-scl-internal-delay-ns = <110>;
+                        status = "disabled";
+                };
+
+                i2c6: i2c@e66e8000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a774a1",
+                                     "renesas,rcar-gen3-i2c";
+                        reg = <0 0xe66e8000 0 0x40>;
+                        interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 918>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 918>;
+                        dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
+                        dma-names = "tx", "rx";
+                        i2c-scl-internal-delay-ns = <6>;
+                        status = "disabled";
+                };
+
+                i2c_dvfs: i2c@e60b0000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,iic-r8a774a1",
+                                     "renesas,rcar-gen3-iic",
+                                     "renesas,rmobile-iic";
+                        reg = <0 0xe60b0000 0 0x425>;
+                        interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 926>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 926>;
+                        dmas = <&dmac0 0x11>, <&dmac0 0x10>;
+                        dma-names = "tx", "rx";
+                        status = "disabled";
+                };
+
+                hscif0: serial@e6540000 {
+                        compatible = "renesas,hscif-r8a774a1",
+                                     "renesas,rcar-gen3-hscif",
+                                     "renesas,hscif";
+                        reg = <0 0xe6540000 0 0x60>;
+                        interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 520>,
+                                 <&cpg CPG_CORE 19>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac1 0x31>, <&dmac1 0x30>,
+                               <&dmac2 0x31>, <&dmac2 0x30>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 520>;
+                        status = "disabled";
+                };
+
+                hscif1: serial@e6550000 {
+                        compatible = "renesas,hscif-r8a774a1",
+                                     "renesas,rcar-gen3-hscif",
+                                     "renesas,hscif";
+                        reg = <0 0xe6550000 0 0x60>;
+                        interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 519>,
+                                 <&cpg CPG_CORE 19>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac1 0x33>, <&dmac1 0x32>,
+                               <&dmac2 0x33>, <&dmac2 0x32>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 519>;
+                        status = "disabled";
+                };
+
+                hscif2: serial@e6560000 {
+                        compatible = "renesas,hscif-r8a774a1",
+                                     "renesas,rcar-gen3-hscif",
+                                     "renesas,hscif";
+                        reg = <0 0xe6560000 0 0x60>;
+                        interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 518>,
+                                 <&cpg CPG_CORE 19>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac1 0x35>, <&dmac1 0x34>,
+                               <&dmac2 0x35>, <&dmac2 0x34>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 518>;
+                        status = "disabled";
+                };
+
+                hscif3: serial@e66a0000 {
+                        compatible = "renesas,hscif-r8a774a1",
+                                     "renesas,rcar-gen3-hscif",
+                                     "renesas,hscif";
+                        reg = <0 0xe66a0000 0 0x60>;
+                        interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 517>,
+                                 <&cpg CPG_CORE 19>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0x37>, <&dmac0 0x36>;
+                        dma-names = "tx", "rx";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 517>;
+                        status = "disabled";
+                };
+
+                hscif4: serial@e66b0000 {
+                        compatible = "renesas,hscif-r8a774a1",
+                                     "renesas,rcar-gen3-hscif",
+                                     "renesas,hscif";
+                        reg = <0 0xe66b0000 0 0x60>;
+                        interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 516>,
+                                 <&cpg CPG_CORE 19>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0x39>, <&dmac0 0x38>;
+                        dma-names = "tx", "rx";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 516>;
+                        status = "disabled";
+                };
+
+                hsusb: usb@e6590000 {
+                        compatible = "renesas,usbhs-r8a774a1",
+                                     "renesas,rcar-gen3-usbhs";
+                        reg = <0 0xe6590000 0 0x100>;
+                        interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 704>;
+                        dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
+                               <&usb_dmac1 0>, <&usb_dmac1 1>;
+                        dma-names = "ch0", "ch1", "ch2", "ch3";
+                        renesas,buswait = <11>;
+                        phys = <&usb2_phy0>;
+                        phy-names = "usb";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 704>;
+                        status = "disabled";
+                };
+
+                usb_dmac0: dma-controller@e65a0000 {
+                        compatible = "renesas,r8a774a1-usb-dmac",
+                                     "renesas,usb-dmac";
+                        reg = <0 0xe65a0000 0 0x100>;
+                        interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "ch0", "ch1";
+                        clocks = <&cpg CPG_MOD 330>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 330>;
+                        #dma-cells = <1>;
+                        dma-channels = <2>;
+                };
+
+                usb_dmac1: dma-controller@e65b0000 {
+                        compatible = "renesas,r8a774a1-usb-dmac",
+                                     "renesas,usb-dmac";
+                        reg = <0 0xe65b0000 0 0x100>;
+                        interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "ch0", "ch1";
+                        clocks = <&cpg CPG_MOD 331>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 331>;
+                        #dma-cells = <1>;
+                        dma-channels = <2>;
+                };
+
+                usb3_phy0: usb-phy@e65ee000 {
+                        compatible = "renesas,r8a774a1-usb3-phy",
+                                     "renesas,rcar-gen3-usb3-phy";
+                        reg = <0 0xe65ee000 0 0x90>;
+                        clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
+                                 <&usb_extal_clk>;
+                        clock-names = "usb3-if", "usb3s_clk", "usb_extal";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 328>;
+                        #phy-cells = <0>;
+                        status = "disabled";
+                };
+
+                dmac0: dma-controller@e6700000 {
+                        compatible = "renesas,dmac-r8a774a1",
+                                     "renesas,rcar-dmac";
+                        reg = <0 0xe6700000 0 0x10000>;
+                        interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "error",
+                                        "ch0", "ch1", "ch2", "ch3",
+                                        "ch4", "ch5", "ch6", "ch7",
+                                        "ch8", "ch9", "ch10", "ch11",
+                                        "ch12", "ch13", "ch14", "ch15";
+                        clocks = <&cpg CPG_MOD 219>;
+                        clock-names = "fck";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 219>;
+                        #dma-cells = <1>;
+                        dma-channels = <16>;
+                };
+
+                dmac1: dma-controller@e7300000 {
+                        compatible = "renesas,dmac-r8a774a1",
+                                     "renesas,rcar-dmac";
+                        reg = <0 0xe7300000 0 0x10000>;
+                        interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "error",
+                                        "ch0", "ch1", "ch2", "ch3",
+                                        "ch4", "ch5", "ch6", "ch7",
+                                        "ch8", "ch9", "ch10", "ch11",
+                                        "ch12", "ch13", "ch14", "ch15";
+                        clocks = <&cpg CPG_MOD 218>;
+                        clock-names = "fck";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 218>;
+                        #dma-cells = <1>;
+                        dma-channels = <16>;
+                };
+
+                dmac2: dma-controller@e7310000 {
+                        compatible = "renesas,dmac-r8a774a1",
+                                     "renesas,rcar-dmac";
+                        reg = <0 0xe7310000 0 0x10000>;
+                        interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "error",
+                                        "ch0", "ch1", "ch2", "ch3",
+                                        "ch4", "ch5", "ch6", "ch7",
+                                        "ch8", "ch9", "ch10", "ch11",
+                                        "ch12", "ch13", "ch14", "ch15";
+                        clocks = <&cpg CPG_MOD 217>;
+                        clock-names = "fck";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 217>;
+                        #dma-cells = <1>;
+                        dma-channels = <16>;
+                };
+
+                ipmmu_ds0: mmu@e6740000 {
+                        compatible = "renesas,ipmmu-r8a774a1";
+                        reg = <0 0xe6740000 0 0x1000>;
+                        renesas,ipmmu-main = <&ipmmu_mm 0>;
+                        power-domains = <&sysc 32>;
+                        #iommu-cells = <1>;
+                };
+
+                ipmmu_ds1: mmu@e7740000 {
+                        compatible = "renesas,ipmmu-r8a774a1";
+                        reg = <0 0xe7740000 0 0x1000>;
+                        renesas,ipmmu-main = <&ipmmu_mm 1>;
+                        power-domains = <&sysc 32>;
+                        #iommu-cells = <1>;
+                };
+
+                ipmmu_hc: mmu@e6570000 {
+                        compatible = "renesas,ipmmu-r8a774a1";
+                        reg = <0 0xe6570000 0 0x1000>;
+                        renesas,ipmmu-main = <&ipmmu_mm 2>;
+                        power-domains = <&sysc 32>;
+                        #iommu-cells = <1>;
+                };
+
+                ipmmu_mm: mmu@e67b0000 {
+                        compatible = "renesas,ipmmu-r8a774a1";
+                        reg = <0 0xe67b0000 0 0x1000>;
+                        interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+                        power-domains = <&sysc 32>;
+                        #iommu-cells = <1>;
+                };
+
+                ipmmu_mp: mmu@ec670000 {
+                        compatible = "renesas,ipmmu-r8a774a1";
+                        reg = <0 0xec670000 0 0x1000>;
+                        renesas,ipmmu-main = <&ipmmu_mm 4>;
+                        power-domains = <&sysc 32>;
+                        #iommu-cells = <1>;
+                };
+
+                ipmmu_pv0: mmu@fd800000 {
+                        compatible = "renesas,ipmmu-r8a774a1";
+                        reg = <0 0xfd800000 0 0x1000>;
+                        renesas,ipmmu-main = <&ipmmu_mm 5>;
+                        power-domains = <&sysc 32>;
+                        #iommu-cells = <1>;
+                };
+
+                ipmmu_pv1: mmu@fd950000 {
+                        compatible = "renesas,ipmmu-r8a774a1";
+                        reg = <0 0xfd950000 0 0x1000>;
+                        renesas,ipmmu-main = <&ipmmu_mm 6>;
+                        power-domains = <&sysc 32>;
+                        #iommu-cells = <1>;
+                };
+
+                ipmmu_vc0: mmu@fe6b0000 {
+                        compatible = "renesas,ipmmu-r8a774a1";
+                        reg = <0 0xfe6b0000 0 0x1000>;
+                        renesas,ipmmu-main = <&ipmmu_mm 8>;
+                        power-domains = <&sysc 14>;
+                        #iommu-cells = <1>;
+                };
+
+                ipmmu_vi0: mmu@febd0000 {
+                        compatible = "renesas,ipmmu-r8a774a1";
+                        reg = <0 0xfebd0000 0 0x1000>;
+                        renesas,ipmmu-main = <&ipmmu_mm 9>;
+                        power-domains = <&sysc 32>;
+                        #iommu-cells = <1>;
+                };
+
+                avb: ethernet@e6800000 {
+                        compatible = "renesas,etheravb-r8a774a1",
+                                     "renesas,etheravb-rcar-gen3";
+                        reg = <0 0xe6800000 0 0x800>;
+                        interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "ch0", "ch1", "ch2", "ch3",
+                                          "ch4", "ch5", "ch6", "ch7",
+                                          "ch8", "ch9", "ch10", "ch11",
+                                          "ch12", "ch13", "ch14", "ch15",
+                                          "ch16", "ch17", "ch18", "ch19",
+                                          "ch20", "ch21", "ch22", "ch23",
+                                          "ch24";
+                        clocks = <&cpg CPG_MOD 812>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 812>;
+                        phy-mode = "rgmii";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                pwm0: pwm@e6e30000 {
+                        compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
+                        reg = <0 0xe6e30000 0 0x8>;
+                        #pwm-cells = <2>;
+                        clocks = <&cpg CPG_MOD 523>;
+                        resets = <&cpg 523>;
+                        power-domains = <&sysc 32>;
+                        status = "disabled";
+                };
+
+                pwm1: pwm@e6e31000 {
+                        compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
+                        reg = <0 0xe6e31000 0 0x8>;
+                        #pwm-cells = <2>;
+                        clocks = <&cpg CPG_MOD 523>;
+                        resets = <&cpg 523>;
+                        power-domains = <&sysc 32>;
+                        status = "disabled";
+                };
+
+                pwm2: pwm@e6e32000 {
+                        compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
+                        reg = <0 0xe6e32000 0 0x8>;
+                        #pwm-cells = <2>;
+                        clocks = <&cpg CPG_MOD 523>;
+                        resets = <&cpg 523>;
+                        power-domains = <&sysc 32>;
+                        status = "disabled";
+                };
+
+                pwm3: pwm@e6e33000 {
+                        compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
+                        reg = <0 0xe6e33000 0 0x8>;
+                        #pwm-cells = <2>;
+                        clocks = <&cpg CPG_MOD 523>;
+                        resets = <&cpg 523>;
+                        power-domains = <&sysc 32>;
+                        status = "disabled";
+                };
+
+                pwm4: pwm@e6e34000 {
+                        compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
+                        reg = <0 0xe6e34000 0 0x8>;
+                        #pwm-cells = <2>;
+                        clocks = <&cpg CPG_MOD 523>;
+                        resets = <&cpg 523>;
+                        power-domains = <&sysc 32>;
+                        status = "disabled";
+                };
+
+                pwm5: pwm@e6e35000 {
+                        compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
+                        reg = <0 0xe6e35000 0 0x8>;
+                        #pwm-cells = <2>;
+                        clocks = <&cpg CPG_MOD 523>;
+                        resets = <&cpg 523>;
+                        power-domains = <&sysc 32>;
+                        status = "disabled";
+                };
+
+                pwm6: pwm@e6e36000 {
+                        compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
+                        reg = <0 0xe6e36000 0 0x8>;
+                        #pwm-cells = <2>;
+                        clocks = <&cpg CPG_MOD 523>;
+                        resets = <&cpg 523>;
+                        power-domains = <&sysc 32>;
+                        status = "disabled";
+                };
+
+                scif0: serial@e6e60000 {
+                        compatible = "renesas,scif-r8a774a1",
+                                     "renesas,rcar-gen3-scif", "renesas,scif";
+                        reg = <0 0xe6e60000 0 0x40>;
+                        interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 207>,
+                                 <&cpg CPG_CORE 19>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac1 0x51>, <&dmac1 0x50>,
+                               <&dmac2 0x51>, <&dmac2 0x50>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 207>;
+                        status = "disabled";
+                };
+
+                scif1: serial@e6e68000 {
+                        compatible = "renesas,scif-r8a774a1",
+                                     "renesas,rcar-gen3-scif", "renesas,scif";
+                        reg = <0 0xe6e68000 0 0x40>;
+                        interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 206>,
+                                 <&cpg CPG_CORE 19>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac1 0x53>, <&dmac1 0x52>,
+                               <&dmac2 0x53>, <&dmac2 0x52>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 206>;
+                        status = "disabled";
+                };
+
+                scif2: serial@e6e88000 {
+                        compatible = "renesas,scif-r8a774a1",
+                                     "renesas,rcar-gen3-scif", "renesas,scif";
+                        reg = <0 0xe6e88000 0 0x40>;
+                        interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 310>,
+                                 <&cpg CPG_CORE 19>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 310>;
+                        status = "disabled";
+                };
+
+                scif3: serial@e6c50000 {
+                        compatible = "renesas,scif-r8a774a1",
+                                     "renesas,rcar-gen3-scif", "renesas,scif";
+                        reg = <0 0xe6c50000 0 0x40>;
+                        interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 204>,
+                                 <&cpg CPG_CORE 19>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0x57>, <&dmac0 0x56>;
+                        dma-names = "tx", "rx";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 204>;
+                        status = "disabled";
+                };
+
+                scif4: serial@e6c40000 {
+                        compatible = "renesas,scif-r8a774a1",
+                                     "renesas,rcar-gen3-scif", "renesas,scif";
+                        reg = <0 0xe6c40000 0 0x40>;
+                        interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 203>,
+                                 <&cpg CPG_CORE 19>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0x59>, <&dmac0 0x58>;
+                        dma-names = "tx", "rx";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 203>;
+                        status = "disabled";
+                };
+
+                scif5: serial@e6f30000 {
+                        compatible = "renesas,scif-r8a774a1",
+                                     "renesas,rcar-gen3-scif", "renesas,scif";
+                        reg = <0 0xe6f30000 0 0x40>;
+                        interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 202>,
+                                 <&cpg CPG_CORE 19>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
+                               <&dmac2 0x5b>, <&dmac2 0x5a>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 202>;
+                        status = "disabled";
+                };
+
+                msiof0: spi@e6e90000 {
+                        compatible = "renesas,msiof-r8a774a1",
+                                     "renesas,rcar-gen3-msiof";
+                        reg = <0 0xe6e90000 0 0x0064>;
+                        interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 211>;
+                        dmas = <&dmac1 0x41>, <&dmac1 0x40>,
+                               <&dmac2 0x41>, <&dmac2 0x40>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 211>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                msiof1: spi@e6ea0000 {
+                        compatible = "renesas,msiof-r8a774a1",
+                                     "renesas,rcar-gen3-msiof";
+                        reg = <0 0xe6ea0000 0 0x0064>;
+                        interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 210>;
+                        dmas = <&dmac1 0x43>, <&dmac1 0x42>,
+                               <&dmac2 0x43>, <&dmac2 0x42>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 210>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                msiof2: spi@e6c00000 {
+                        compatible = "renesas,msiof-r8a774a1",
+                                     "renesas,rcar-gen3-msiof";
+                        reg = <0 0xe6c00000 0 0x0064>;
+                        interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 209>;
+                        dmas = <&dmac0 0x45>, <&dmac0 0x44>;
+                        dma-names = "tx", "rx";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 209>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                msiof3: spi@e6c10000 {
+                        compatible = "renesas,msiof-r8a774a1",
+                                     "renesas,rcar-gen3-msiof";
+                        reg = <0 0xe6c10000 0 0x0064>;
+                        interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 208>;
+                        dmas = <&dmac0 0x47>, <&dmac0 0x46>;
+                        dma-names = "tx", "rx";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 208>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                rcar_sound: sound@ec500000 {
+                        /*
+                         * #sound-dai-cells is required
+                         *
+                         * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
+                         * Multi  DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
+                         */
+                        /*
+                         * #clock-cells is required for audio_clkout0/1/2/3
+                         *
+                         * clkout       : #clock-cells = <0>;   <&rcar_sound>;
+                         * clkout0/1/2/3: #clock-cells = <1>;   <&rcar_sound N>;
+                         */
+                        compatible =  "renesas,rcar_sound-r8a774a1", "renesas,rcar_sound-gen3";
+                        reg =   <0 0xec500000 0 0x1000>, /* SCU */
+                                <0 0xec5a0000 0 0x100>,  /* ADG */
+                                <0 0xec540000 0 0x1000>, /* SSIU */
+                                <0 0xec541000 0 0x280>,  /* SSI */
+                                <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
+                        reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+                        clocks = <&cpg CPG_MOD 1005>,
+                                 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+                                 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+                                 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+                                 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+                                 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+                                 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+                                 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+                                 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+                                 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+                                 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+                                 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+                                 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+                                 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+                                 <&audio_clk_a>, <&audio_clk_b>,
+                                 <&audio_clk_c>,
+                                 <&cpg CPG_CORE 10>;
+                        clock-names = "ssi-all",
+                                      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+                                      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+                                      "ssi.1", "ssi.0",
+                                      "src.9", "src.8", "src.7", "src.6",
+                                      "src.5", "src.4", "src.3", "src.2",
+                                      "src.1", "src.0",
+                                      "mix.1", "mix.0",
+                                      "ctu.1", "ctu.0",
+                                      "dvc.0", "dvc.1",
+                                      "clk_a", "clk_b", "clk_c", "clk_i";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 1005>,
+                                 <&cpg 1006>, <&cpg 1007>,
+                                 <&cpg 1008>, <&cpg 1009>,
+                                 <&cpg 1010>, <&cpg 1011>,
+                                 <&cpg 1012>, <&cpg 1013>,
+                                 <&cpg 1014>, <&cpg 1015>;
+                        reset-names = "ssi-all",
+                                      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+                                      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+                                      "ssi.1", "ssi.0";
+                        status = "disabled";
+
+                        rcar_sound,dvc {
+                                dvc0: dvc-0 {
+                                        dmas = <&audma1 0xbc>;
+                                        dma-names = "tx";
+                                };
+                                dvc1: dvc-1 {
+                                        dmas = <&audma1 0xbe>;
+                                        dma-names = "tx";
+                                };
+                        };
+
+                        rcar_sound,mix {
+                                mix0: mix-0 { };
+                                mix1: mix-1 { };
+                        };
+
+                        rcar_sound,ctu {
+                                ctu00: ctu-0 { };
+                                ctu01: ctu-1 { };
+                                ctu02: ctu-2 { };
+                                ctu03: ctu-3 { };
+                                ctu10: ctu-4 { };
+                                ctu11: ctu-5 { };
+                                ctu12: ctu-6 { };
+                                ctu13: ctu-7 { };
+                        };
+
+                        rcar_sound,src {
+                                src0: src-0 {
+                                        interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x85>, <&audma1 0x9a>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src1: src-1 {
+                                        interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x87>, <&audma1 0x9c>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src2: src-2 {
+                                        interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x89>, <&audma1 0x9e>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src3: src-3 {
+                                        interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x8b>, <&audma1 0xa0>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src4: src-4 {
+                                        interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x8d>, <&audma1 0xb0>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src5: src-5 {
+                                        interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x8f>, <&audma1 0xb2>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src6: src-6 {
+                                        interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x91>, <&audma1 0xb4>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src7: src-7 {
+                                        interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x93>, <&audma1 0xb6>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src8: src-8 {
+                                        interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x95>, <&audma1 0xb8>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src9: src-9 {
+                                        interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x97>, <&audma1 0xba>;
+                                        dma-names = "rx", "tx";
+                                };
+                        };
+
+                        rcar_sound,ssi {
+                                ssi0: ssi-0 {
+                                        interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi1: ssi-1 {
+                                        interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi2: ssi-2 {
+                                        interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi3: ssi-3 {
+                                        interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi4: ssi-4 {
+                                        interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi5: ssi-5 {
+                                        interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi6: ssi-6 {
+                                        interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi7: ssi-7 {
+                                        interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi8: ssi-8 {
+                                        interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi9: ssi-9 {
+                                        interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                        };
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                port@0 {
+                                        reg = <0>;
+                                };
+                                port@1 {
+                                        reg = <1>;
+                                };
+                        };
+                };
+
+                audma0: dma-controller@ec700000 {
+                        compatible = "renesas,dmac-r8a774a1",
+                                     "renesas,rcar-dmac";
+                        reg = <0 0xec700000 0 0x10000>;
+                        interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "error",
+                                        "ch0", "ch1", "ch2", "ch3",
+                                        "ch4", "ch5", "ch6", "ch7",
+                                        "ch8", "ch9", "ch10", "ch11",
+                                        "ch12", "ch13", "ch14", "ch15";
+                        clocks = <&cpg CPG_MOD 502>;
+                        clock-names = "fck";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 502>;
+                        #dma-cells = <1>;
+                        dma-channels = <16>;
+                };
+
+                audma1: dma-controller@ec720000 {
+                        compatible = "renesas,dmac-r8a774a1",
+                                     "renesas,rcar-dmac";
+                        reg = <0 0xec720000 0 0x10000>;
+                        interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "error",
+                                        "ch0", "ch1", "ch2", "ch3",
+                                        "ch4", "ch5", "ch6", "ch7",
+                                        "ch8", "ch9", "ch10", "ch11",
+                                        "ch12", "ch13", "ch14", "ch15";
+                        clocks = <&cpg CPG_MOD 501>;
+                        clock-names = "fck";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 501>;
+                        #dma-cells = <1>;
+                        dma-channels = <16>;
+                };
+
+                xhci0: usb@ee000000 {
+                        compatible = "renesas,xhci-r8a774a1",
+                                     "renesas,rcar-gen3-xhci";
+                        reg = <0 0xee000000 0 0xc00>;
+                        interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 328>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 328>;
+                        status = "disabled";
+                };
+
+                usb3_peri0: usb@ee020000 {
+                        compatible = "renesas,r8a774a1-usb3-peri",
+                                     "renesas,rcar-gen3-usb3-peri";
+                        reg = <0 0xee020000 0 0x400>;
+                        interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 328>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 328>;
+                        status = "disabled";
+                };
+
+                ohci0: usb@ee080000 {
+                        compatible = "generic-ohci";
+                        reg = <0 0xee080000 0 0x100>;
+                        interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 703>;
+                        phys = <&usb2_phy0>;
+                        phy-names = "usb";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 703>;
+                        status = "disabled";
+                };
+
+                ohci1: usb@ee0a0000 {
+                        compatible = "generic-ohci";
+                        reg = <0 0xee0a0000 0 0x100>;
+                        interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 702>;
+                        phys = <&usb2_phy1>;
+                        phy-names = "usb";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 702>;
+                        status = "disabled";
+                };
+
+                ehci0: usb@ee080100 {
+                        compatible = "generic-ehci";
+                        reg = <0 0xee080100 0 0x100>;
+                        interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 703>;
+                        phys = <&usb2_phy0>;
+                        phy-names = "usb";
+                        companion = <&ohci0>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 703>;
+                        status = "disabled";
+                };
+
+                ehci1: usb@ee0a0100 {
+                        compatible = "generic-ehci";
+                        reg = <0 0xee0a0100 0 0x100>;
+                        interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 702>;
+                        phys = <&usb2_phy1>;
+                        phy-names = "usb";
+                        companion = <&ohci1>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 702>;
+                        status = "disabled";
+                };
+
+                usb2_phy0: usb-phy@ee080200 {
+                        compatible = "renesas,usb2-phy-r8a774a1",
+                                     "renesas,rcar-gen3-usb2-phy";
+                        reg = <0 0xee080200 0 0x700>;
+                        interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 703>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 703>;
+                        #phy-cells = <0>;
+                        status = "disabled";
+                };
+
+                usb2_phy1: usb-phy@ee0a0200 {
+                        compatible = "renesas,usb2-phy-r8a774a1",
+                                     "renesas,rcar-gen3-usb2-phy";
+                        reg = <0 0xee0a0200 0 0x700>;
+                        clocks = <&cpg CPG_MOD 702>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 702>;
+                        #phy-cells = <0>;
+                        status = "disabled";
+                };
+
+                sdhi0: sd@ee100000 {
+                        compatible = "renesas,sdhi-r8a774a1",
+                                     "renesas,rcar-gen3-sdhi";
+                        reg = <0 0xee100000 0 0x2000>;
+                        interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 314>;
+                        max-frequency = <200000000>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 314>;
+                        status = "disabled";
+                };
+
+                sdhi1: sd@ee120000 {
+                        compatible = "renesas,sdhi-r8a774a1",
+                                     "renesas,rcar-gen3-sdhi";
+                        reg = <0 0xee120000 0 0x2000>;
+                        interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 313>;
+                        max-frequency = <200000000>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 313>;
+                        status = "disabled";
+                };
+
+                sdhi2: sd@ee140000 {
+                        compatible = "renesas,sdhi-r8a774a1",
+                                     "renesas,rcar-gen3-sdhi";
+                        reg = <0 0xee140000 0 0x2000>;
+                        interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 312>;
+                        max-frequency = <200000000>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 312>;
+                        status = "disabled";
+                };
+
+                sdhi3: sd@ee160000 {
+                        compatible = "renesas,sdhi-r8a774a1",
+                                     "renesas,rcar-gen3-sdhi";
+                        reg = <0 0xee160000 0 0x2000>;
+                        interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 311>;
+                        max-frequency = <200000000>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 311>;
+                        status = "disabled";
+                };
+
+                gic: interrupt-controller@f1010000 {
+                        compatible = "arm,gic-400";
+                        #interrupt-cells = <3>;
+                        #address-cells = <0>;
+                        interrupt-controller;
+                        reg = <0x0 0xf1010000 0 0x1000>,
+                              <0x0 0xf1020000 0 0x20000>,
+                              <0x0 0xf1040000 0 0x20000>,
+                              <0x0 0xf1060000 0 0x20000>;
+                        interrupts = <GIC_PPI 9
+                                        (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
+                        clocks = <&cpg CPG_MOD 408>;
+                        clock-names = "clk";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 408>;
+                };
+
+                fcpf0: fcp@fe950000 {
+                        compatible = "renesas,fcpf";
+                        reg = <0 0xfe950000 0 0x200>;
+                        clocks = <&cpg CPG_MOD 615>;
+                        power-domains = <&sysc 14>;
+                        resets = <&cpg 615>;
+                };
+
+                fcpvb0: fcp@fe96f000 {
+                        compatible = "renesas,fcpv";
+                        reg = <0 0xfe96f000 0 0x200>;
+                        clocks = <&cpg CPG_MOD 607>;
+                        power-domains = <&sysc 14>;
+                        resets = <&cpg 607>;
+                };
+
+                fcpvd0: fcp@fea27000 {
+                        compatible = "renesas,fcpv";
+                        reg = <0 0xfea27000 0 0x200>;
+                        clocks = <&cpg CPG_MOD 603>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 603>;
+                        iommus = <&ipmmu_vi0 8>;
+                };
+
+                fcpvd1: fcp@fea2f000 {
+                        compatible = "renesas,fcpv";
+                        reg = <0 0xfea2f000 0 0x200>;
+                        clocks = <&cpg CPG_MOD 602>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 602>;
+                        iommus = <&ipmmu_vi0 9>;
+                };
+
+                fcpvd2: fcp@fea37000 {
+                        compatible = "renesas,fcpv";
+                        reg = <0 0xfea37000 0 0x200>;
+                        clocks = <&cpg CPG_MOD 601>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 601>;
+                        iommus = <&ipmmu_vi0 10>;
+                };
+
+                fcpvi0: fcp@fe9af000 {
+                        compatible = "renesas,fcpv";
+                        reg = <0 0xfe9af000 0 0x200>;
+                        clocks = <&cpg CPG_MOD 611>;
+                        power-domains = <&sysc 14>;
+                        resets = <&cpg 611>;
+                        iommus = <&ipmmu_vc0 19>;
+                };
+
+                prr: chipid@fff00044 {
+                        compatible = "renesas,prr";
+                        reg = <0 0xfff00044 0 4>;
+                };
+        };
+
+        thermal-zones {
+                sensor_thermal1: sensor-thermal1 {
+                        polling-delay-passive = <250>;
+                        polling-delay = <1000>;
+                        thermal-sensors = <&tsc 0>;
+
+                        trips {
+                                sensor1_crit: sensor1-crit {
+                                        temperature = <120000>;
+                                        hysteresis = <1000>;
+                                        type = "critical";
+                                };
+                        };
+                };
+
+                sensor_thermal2: sensor-thermal2 {
+                        polling-delay-passive = <250>;
+                        polling-delay = <1000>;
+                        thermal-sensors = <&tsc 1>;
+
+                        trips {
+                                sensor2_crit: sensor2-crit {
+                                        temperature = <120000>;
+                                        hysteresis = <1000>;
+                                        type = "critical";
+                                };
+                        };
+
+                };
+
+                sensor_thermal3: sensor-thermal3 {
+                        polling-delay-passive = <250>;
+                        polling-delay = <1000>;
+                        thermal-sensors = <&tsc 2>;
+
+                        trips {
+                                sensor3_crit: sensor3-crit {
+                                        temperature = <120000>;
+                                        hysteresis = <1000>;
+                                        type = "critical";
+                                };
+                        };
+                };
+        };
+
+        timer {
+                compatible = "arm,armv8-timer";
+                interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+                                      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+                                      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+                                      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
+        };
+
+        /* External USB clocks - can be overridden by the board */
+        usb3s0_clk: usb3s0 {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+
+        usb_extal_clk: usb_extal {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts
index 6b5fa91f1d5d..0895503b69d0 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts
@@ -40,12 +40,11 @@
                  <&cpg CPG_MOD 723>,
                  <&cpg CPG_MOD 722>,
                  <&cpg CPG_MOD 721>,
-                 <&cpg CPG_MOD 727>,
                  <&versaclock5 1>,
                  <&x21_clk>,
                  <&x22_clk>,
                  <&versaclock5 2>;
-        clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",
+        clock-names = "du.0", "du.1", "du.2", "du.3",
                       "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
 };
 
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
index 7b2fbaec9aef..0fb84c219b2f 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source for the r8a7795 ES1.x SoC
+ * Device Tree Source for the R-Car H3 (R8A77950) ES1.x SoC
  *
  * Copyright (C) 2015 Renesas Electronics Corp.
  */
@@ -232,7 +232,7 @@
                 port@1 {
                         vin0csi21: endpoint@1 {
                                 reg = <1>;
-                                remote-endpoint= <&csi21vin0>;
+                                remote-endpoint = <&csi21vin0>;
                         };
                 };
         };
@@ -243,7 +243,7 @@
                 port@1 {
                         vin1csi21: endpoint@1 {
                                 reg = <1>;
-                                remote-endpoint= <&csi21vin1>;
+                                remote-endpoint = <&csi21vin1>;
                         };
                 };
         };
@@ -254,7 +254,7 @@
                 port@1 {
                         vin2csi21: endpoint@1 {
                                 reg = <1>;
-                                remote-endpoint= <&csi21vin2>;
+                                remote-endpoint = <&csi21vin2>;
                         };
                 };
         };
@@ -265,7 +265,7 @@
                 port@1 {
                         vin3csi21: endpoint@1 {
                                 reg = <1>;
-                                remote-endpoint= <&csi21vin3>;
+                                remote-endpoint = <&csi21vin3>;
                         };
                 };
         };
@@ -276,7 +276,7 @@
                 port@1 {
                         vin4csi21: endpoint@1 {
                                 reg = <1>;
-                                remote-endpoint= <&csi21vin4>;
+                                remote-endpoint = <&csi21vin4>;
                         };
                 };
         };
@@ -287,7 +287,7 @@
                 port@1 {
                         vin5csi21: endpoint@1 {
                                 reg = <1>;
-                                remote-endpoint= <&csi21vin5>;
+                                remote-endpoint = <&csi21vin5>;
                         };
                 };
         };
@@ -298,7 +298,7 @@
                 port@1 {
                         vin6csi21: endpoint@1 {
                                 reg = <1>;
-                                remote-endpoint= <&csi21vin6>;
+                                remote-endpoint = <&csi21vin6>;
                         };
                 };
         };
@@ -309,7 +309,7 @@
                 port@1 {
                         vin7csi21: endpoint@1 {
                                 reg = <1>;
-                                remote-endpoint= <&csi21vin7>;
+                                remote-endpoint = <&csi21vin7>;
                         };
                 };
         };
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
index df50bf46406e..54515eaf0310 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
@@ -41,11 +41,10 @@
                  <&cpg CPG_MOD 723>,
                  <&cpg CPG_MOD 722>,
                  <&cpg CPG_MOD 721>,
-                 <&cpg CPG_MOD 727>,
                  <&versaclock5 1>,
                  <&versaclock5 3>,
                  <&versaclock5 4>,
                  <&versaclock5 2>;
-        clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",
+        clock-names = "du.0", "du.1", "du.2", "du.3",
                       "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
 };
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
index 446822f5751c..1620e8d8dacc 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
@@ -40,12 +40,11 @@
                  <&cpg CPG_MOD 723>,
                  <&cpg CPG_MOD 722>,
                  <&cpg CPG_MOD 721>,
-                 <&cpg CPG_MOD 727>,
                  <&versaclock5 1>,
                  <&x21_clk>,
                  <&x22_clk>,
                  <&versaclock5 2>;
-        clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",
+        clock-names = "du.0", "du.1", "du.2", "du.3",
                       "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
 };
 
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
index 8ded64d0a4d5..cf08a119eec0 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
@@ -40,12 +40,11 @@
                  <&cpg CPG_MOD 723>,
                  <&cpg CPG_MOD 722>,
                  <&cpg CPG_MOD 721>,
-                 <&cpg CPG_MOD 727>,
                  <&versaclock6 1>,
                  <&x21_clk>,
                  <&x22_clk>,
                  <&versaclock6 2>;
-        clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",
+        clock-names = "du.0", "du.1", "du.2", "du.3",
                       "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
 };
 
@@ -152,6 +151,15 @@
         };
 };
 
+&pca9654 {
+        pcie_sata_switch {
+                gpio-hog;
+                gpios = <7 GPIO_ACTIVE_HIGH>;
+                output-low; /* enable SATA by default */
+                line-name = "PCIE/SATA switch";
+        };
+};
+
 &pfc {
         usb2_pins: usb2 {
                 groups = "usb2";
@@ -176,6 +184,11 @@
         };
 };
 
+/* SW12-7 must be set 'Off' (MD12 set to 1) which is not the default! */
+&sata {
+        status = "okay";
+};
+
 &usb2_phy2 {
         pinctrl-0 = <&usb2_pins>;
         pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index fb9d08ad7659..b5f2273caca4 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source for the r8a7795 SoC
+ * Device Tree Source for the R-Car H3 (R8A77950) SoC
  *
  * Copyright (C) 2015 Renesas Electronics Corp.
  */
@@ -123,7 +123,7 @@
                         power-domains = <&sysc R8A7795_PD_CA57_CPU0>;
                         next-level-cache = <&L2_CA57>;
                         enable-method = "psci";
-                        clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
+                        clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
                         operating-points-v2 = <&cluster0_opp>;
                         #cooling-cells = <2>;
                 };
@@ -135,7 +135,7 @@
                         power-domains = <&sysc R8A7795_PD_CA57_CPU1>;
                         next-level-cache = <&L2_CA57>;
                         enable-method = "psci";
-                        clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
+                        clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
                         operating-points-v2 = <&cluster0_opp>;
                         #cooling-cells = <2>;
                 };
@@ -147,7 +147,7 @@
                         power-domains = <&sysc R8A7795_PD_CA57_CPU2>;
                         next-level-cache = <&L2_CA57>;
                         enable-method = "psci";
-                        clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
+                        clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
                         operating-points-v2 = <&cluster0_opp>;
                         #cooling-cells = <2>;
                 };
@@ -159,7 +159,7 @@
                         power-domains = <&sysc R8A7795_PD_CA57_CPU3>;
                         next-level-cache = <&L2_CA57>;
                         enable-method = "psci";
-                        clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
+                        clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
                         operating-points-v2 = <&cluster0_opp>;
                         #cooling-cells = <2>;
                 };
@@ -171,7 +171,7 @@
                         power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
                         next-level-cache = <&L2_CA53>;
                         enable-method = "psci";
-                        clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
+                        clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
                         operating-points-v2 = <&cluster1_opp>;
                 };
 
@@ -182,7 +182,7 @@
                         power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
                         next-level-cache = <&L2_CA53>;
                         enable-method = "psci";
-                        clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
+                        clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
                         operating-points-v2 = <&cluster1_opp>;
                 };
 
@@ -193,7 +193,7 @@
                         power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
                         next-level-cache = <&L2_CA53>;
                         enable-method = "psci";
-                        clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
+                        clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
                         operating-points-v2 = <&cluster1_opp>;
                 };
 
@@ -204,7 +204,7 @@
                         power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
                         next-level-cache = <&L2_CA53>;
                         enable-method = "psci";
-                        clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
+                        clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
                         operating-points-v2 = <&cluster1_opp>;
                 };
 
@@ -455,7 +455,6 @@
                         power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
                         resets = <&cpg 522>;
                         #thermal-sensor-cells = <1>;
-                        status = "okay";
                 };
 
                 intc_ex: interrupt-controller@e61c0000 {
@@ -525,15 +524,6 @@
                         status = "disabled";
                 };
 
-                arm_cc630p: crypto@e6601000 {
-                        compatible = "arm,cryptocell-630p-ree";
-                        interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
-                        reg = <0x0 0xe6601000 0 0x1000>;
-                        clocks = <&cpg CPG_MOD 229>;
-                        resets = <&cpg 229>;
-                        power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
-                };
-
                 i2c3: i2c@e66d0000 {
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -707,7 +697,7 @@
                                      "renesas,rcar-gen3-usbhs";
                         reg = <0 0xe6590000 0 0x100>;
                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 704>;
+                        clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
                         dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
                                <&usb_dmac1 0>, <&usb_dmac1 1>;
                         dma-names = "ch0", "ch1", "ch2", "ch3";
@@ -715,7 +705,7 @@
                         phys = <&usb2_phy0>;
                         phy-names = "usb";
                         power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
-                        resets = <&cpg 704>;
+                        resets = <&cpg 704>, <&cpg 703>;
                         status = "disabled";
                 };
 
@@ -724,7 +714,7 @@
                                      "renesas,rcar-gen3-usbhs";
                         reg = <0 0xe659c000 0 0x100>;
                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 705>;
+                        clocks = <&cpg CPG_MOD 705>, <&cpg CPG_MOD 700>;
                         dmas = <&usb_dmac2 0>, <&usb_dmac2 1>,
                                <&usb_dmac3 0>, <&usb_dmac3 1>;
                         dma-names = "ch0", "ch1", "ch2", "ch3";
@@ -732,7 +722,7 @@
                         phys = <&usb2_phy3>;
                         phy-names = "usb";
                         power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
-                        resets = <&cpg 705>;
+                        resets = <&cpg 705>, <&cpg 700>;
                         status = "disabled";
                 };
 
@@ -805,6 +795,15 @@
                         status = "disabled";
                 };
 
+                arm_cc630p: crypto@e6601000 {
+                        compatible = "arm,cryptocell-630p-ree";
+                        interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+                        reg = <0x0 0xe6601000 0 0x1000>;
+                        clocks = <&cpg CPG_MOD 229>;
+                        resets = <&cpg 229>;
+                        power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+                };
+
                 dmac0: dma-controller@e6700000 {
                         compatible = "renesas,dmac-r8a7795",
                                      "renesas,rcar-dmac";
@@ -1425,11 +1424,11 @@
 
                                         vin0csi20: endpoint@0 {
                                                 reg = <0>;
-                                                remote-endpoint= <&csi20vin0>;
+                                                remote-endpoint = <&csi20vin0>;
                                         };
                                         vin0csi40: endpoint@2 {
                                                 reg = <2>;
-                                                remote-endpoint= <&csi40vin0>;
+                                                remote-endpoint = <&csi40vin0>;
                                         };
                                 };
                         };
@@ -1457,11 +1456,11 @@
 
                                         vin1csi20: endpoint@0 {
                                                 reg = <0>;
-                                                remote-endpoint= <&csi20vin1>;
+                                                remote-endpoint = <&csi20vin1>;
                                         };
                                         vin1csi40: endpoint@2 {
                                                 reg = <2>;
-                                                remote-endpoint= <&csi40vin1>;
+                                                remote-endpoint = <&csi40vin1>;
                                         };
                                 };
                         };
@@ -1489,11 +1488,11 @@
 
                                         vin2csi20: endpoint@0 {
                                                 reg = <0>;
-                                                remote-endpoint= <&csi20vin2>;
+                                                remote-endpoint = <&csi20vin2>;
                                         };
                                         vin2csi40: endpoint@2 {
                                                 reg = <2>;
-                                                remote-endpoint= <&csi40vin2>;
+                                                remote-endpoint = <&csi40vin2>;
                                         };
                                 };
                         };
@@ -1521,11 +1520,11 @@
 
                                         vin3csi20: endpoint@0 {
                                                 reg = <0>;
-                                                remote-endpoint= <&csi20vin3>;
+                                                remote-endpoint = <&csi20vin3>;
                                         };
                                         vin3csi40: endpoint@2 {
                                                 reg = <2>;
-                                                remote-endpoint= <&csi40vin3>;
+                                                remote-endpoint = <&csi40vin3>;
                                         };
                                 };
                         };
@@ -1553,11 +1552,11 @@
 
                                         vin4csi20: endpoint@0 {
                                                 reg = <0>;
-                                                remote-endpoint= <&csi20vin4>;
+                                                remote-endpoint = <&csi20vin4>;
                                         };
                                         vin4csi41: endpoint@3 {
                                                 reg = <3>;
-                                                remote-endpoint= <&csi41vin4>;
+                                                remote-endpoint = <&csi41vin4>;
                                         };
                                 };
                         };
@@ -1585,11 +1584,11 @@
 
                                         vin5csi20: endpoint@0 {
                                                 reg = <0>;
-                                                remote-endpoint= <&csi20vin5>;
+                                                remote-endpoint = <&csi20vin5>;
                                         };
                                         vin5csi41: endpoint@3 {
                                                 reg = <3>;
-                                                remote-endpoint= <&csi41vin5>;
+                                                remote-endpoint = <&csi41vin5>;
                                         };
                                 };
                         };
@@ -1617,11 +1616,11 @@
 
                                         vin6csi20: endpoint@0 {
                                                 reg = <0>;
-                                                remote-endpoint= <&csi20vin6>;
+                                                remote-endpoint = <&csi20vin6>;
                                         };
                                         vin6csi41: endpoint@3 {
                                                 reg = <3>;
-                                                remote-endpoint= <&csi41vin6>;
+                                                remote-endpoint = <&csi41vin6>;
                                         };
                                 };
                         };
@@ -1649,11 +1648,11 @@
 
                                         vin7csi20: endpoint@0 {
                                                 reg = <0>;
-                                                remote-endpoint= <&csi20vin7>;
+                                                remote-endpoint = <&csi20vin7>;
                                         };
                                         vin7csi41: endpoint@3 {
                                                 reg = <3>;
-                                                remote-endpoint= <&csi41vin7>;
+                                                remote-endpoint = <&csi41vin7>;
                                         };
                                 };
                         };
@@ -2098,11 +2097,11 @@
                         compatible = "generic-ohci";
                         reg = <0 0xee080000 0 0x100>;
                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 703>;
+                        clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
                         phys = <&usb2_phy0>;
                         phy-names = "usb";
                         power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
-                        resets = <&cpg 703>;
+                        resets = <&cpg 703>, <&cpg 704>;
                         status = "disabled";
                 };
 
@@ -2134,11 +2133,11 @@
                         compatible = "generic-ohci";
                         reg = <0 0xee0e0000 0 0x100>;
                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 700>;
+                        clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>;
                         phys = <&usb2_phy3>;
                         phy-names = "usb";
                         power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
-                        resets = <&cpg 700>;
+                        resets = <&cpg 700>, <&cpg 705>;
                         status = "disabled";
                 };
 
@@ -2146,12 +2145,12 @@
                         compatible = "generic-ehci";
                         reg = <0 0xee080100 0 0x100>;
                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 703>;
+                        clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
                         phys = <&usb2_phy0>;
                         phy-names = "usb";
                         companion = <&ohci0>;
                         power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
-                        resets = <&cpg 703>;
+                        resets = <&cpg 703>, <&cpg 704>;
                         status = "disabled";
                 };
 
@@ -2185,12 +2184,12 @@
                         compatible = "generic-ehci";
                         reg = <0 0xee0e0100 0 0x100>;
                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 700>;
+                        clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>;
                         phys = <&usb2_phy3>;
                         phy-names = "usb";
                         companion = <&ohci3>;
                         power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
-                        resets = <&cpg 700>;
+                        resets = <&cpg 700>, <&cpg 705>;
                         status = "disabled";
                 };
 
@@ -2199,9 +2198,9 @@
                                      "renesas,rcar-gen3-usb2-phy";
                         reg = <0 0xee080200 0 0x700>;
                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 703>;
+                        clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
                         power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
-                        resets = <&cpg 703>;
+                        resets = <&cpg 703>, <&cpg 704>;
                         #phy-cells = <0>;
                         status = "disabled";
                 };
@@ -2233,9 +2232,9 @@
                                      "renesas,rcar-gen3-usb2-phy";
                         reg = <0 0xee0e0200 0 0x700>;
                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 700>;
+                        clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>;
                         power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
-                        resets = <&cpg 700>;
+                        resets = <&cpg 700>, <&cpg 705>;
                         #phy-cells = <0>;
                         status = "disabled";
                 };
@@ -2782,9 +2781,7 @@
 
                 du: display@feb00000 {
                         compatible = "renesas,du-r8a7795";
-                        reg = <0 0xfeb00000 0 0x80000>,
-                              <0 0xfeb90000 0 0x14>;
-                        reg-names = "du", "lvds.0";
+                        reg = <0 0xfeb00000 0 0x80000>;
                         interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
                                      <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
                                      <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
@@ -2792,9 +2789,8 @@
                         clocks = <&cpg CPG_MOD 724>,
                                  <&cpg CPG_MOD 723>,
                                  <&cpg CPG_MOD 722>,
-                                 <&cpg CPG_MOD 721>,
-                                 <&cpg CPG_MOD 727>;
-                        clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0";
+                                 <&cpg CPG_MOD 721>;
+                        clock-names = "du.0", "du.1", "du.2", "du.3";
                         vsps = <&vspd0 0 &vspd1 0 &vspd2 0 &vspd0 1>;
                         status = "disabled";
 
@@ -2822,6 +2818,33 @@
                                 port@3 {
                                         reg = <3>;
                                         du_out_lvds0: endpoint {
+                                                remote-endpoint = <&lvds0_in>;
+                                        };
+                                };
+                        };
+                };
+
+                lvds0: lvds@feb90000 {
+                        compatible = "renesas,r8a7795-lvds";
+                        reg = <0 0xfeb90000 0 0x14>;
+                        clocks = <&cpg CPG_MOD 727>;
+                        power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+                        resets = <&cpg 727>;
+                        status = "disabled";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@0 {
+                                        reg = <0>;
+                                        lvds0_in: endpoint {
+                                                remote-endpoint = <&du_out_lvds0>;
+                                        };
+                                };
+                                port@1 {
+                                        reg = <1>;
+                                        lvds0_out: endpoint {
                                         };
                                 };
                         };
diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
index cbd8acbf537e..9e4594c27fa6 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
@@ -30,10 +30,9 @@
         clocks = <&cpg CPG_MOD 724>,
                  <&cpg CPG_MOD 723>,
                  <&cpg CPG_MOD 722>,
-                 <&cpg CPG_MOD 727>,
                  <&versaclock5 1>,
                  <&versaclock5 3>,
                  <&versaclock5 2>;
-        clock-names = "du.0", "du.1", "du.2", "lvds.0",
+        clock-names = "du.0", "du.1", "du.2",
                       "dclkin.0", "dclkin.1", "dclkin.2";
 };
diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
index 052d72acc862..b4f9567cb9f8 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
@@ -29,11 +29,10 @@
         clocks = <&cpg CPG_MOD 724>,
                  <&cpg CPG_MOD 723>,
                  <&cpg CPG_MOD 722>,
-                 <&cpg CPG_MOD 727>,
                  <&versaclock5 1>,
                  <&x21_clk>,
                  <&versaclock5 2>;
-        clock-names = "du.0", "du.1", "du.2", "lvds.0",
+        clock-names = "du.0", "du.1", "du.2",
                       "dclkin.0", "dclkin.1", "dclkin.2";
 };
 
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index cbd35c00b4af..1ec6aaa520c1 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source for the r8a7796 SoC
+ * Device Tree Source for the R-Car M3-W (R8A77960) SoC
  *
  * Copyright (C) 2016-2017 Renesas Electronics Corp.
  */
@@ -134,7 +134,7 @@
                         power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
                         next-level-cache = <&L2_CA57>;
                         enable-method = "psci";
-                        clocks =<&cpg CPG_CORE R8A7796_CLK_Z>;
+                        clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
                         operating-points-v2 = <&cluster0_opp>;
                         #cooling-cells = <2>;
                 };
@@ -146,7 +146,7 @@
                         power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
                         next-level-cache = <&L2_CA57>;
                         enable-method = "psci";
-                        clocks =<&cpg CPG_CORE R8A7796_CLK_Z>;
+                        clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
                         operating-points-v2 = <&cluster0_opp>;
                         #cooling-cells = <2>;
                 };
@@ -158,7 +158,7 @@
                         power-domains = <&sysc R8A7796_PD_CA53_CPU0>;
                         next-level-cache = <&L2_CA53>;
                         enable-method = "psci";
-                        clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
+                        clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
                         operating-points-v2 = <&cluster1_opp>;
                 };
 
@@ -169,7 +169,7 @@
                         power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
                         next-level-cache = <&L2_CA53>;
                         enable-method = "psci";
-                        clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
+                        clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
                         operating-points-v2 = <&cluster1_opp>;
                 };
 
@@ -180,7 +180,7 @@
                         power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
                         next-level-cache = <&L2_CA53>;
                         enable-method = "psci";
-                        clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
+                        clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
                         operating-points-v2 = <&cluster1_opp>;
                 };
 
@@ -191,7 +191,7 @@
                         power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
                         next-level-cache = <&L2_CA53>;
                         enable-method = "psci";
-                        clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
+                        clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
                         operating-points-v2 = <&cluster1_opp>;
                 };
 
@@ -434,7 +434,6 @@
                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
                         resets = <&cpg 522>;
                         #thermal-sensor-cells = <1>;
-                        status = "okay";
                 };
 
                 intc_ex: interrupt-controller@e61c0000 {
@@ -677,7 +676,7 @@
                                      "renesas,rcar-gen3-usbhs";
                         reg = <0 0xe6590000 0 0x100>;
                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 704>;
+                        clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
                         dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
                                <&usb_dmac1 0>, <&usb_dmac1 1>;
                         dma-names = "ch0", "ch1", "ch2", "ch3";
@@ -685,7 +684,7 @@
                         phys = <&usb2_phy0>;
                         phy-names = "usb";
                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
-                        resets = <&cpg 704>;
+                        resets = <&cpg 704>, <&cpg 703>;
                         status = "disabled";
                 };
 
@@ -1299,11 +1298,11 @@
 
                                         vin0csi20: endpoint@0 {
                                                 reg = <0>;
-                                                remote-endpoint= <&csi20vin0>;
+                                                remote-endpoint = <&csi20vin0>;
                                         };
                                         vin0csi40: endpoint@2 {
                                                 reg = <2>;
-                                                remote-endpoint= <&csi40vin0>;
+                                                remote-endpoint = <&csi40vin0>;
                                         };
                                 };
                         };
@@ -1331,11 +1330,11 @@
 
                                         vin1csi20: endpoint@0 {
                                                 reg = <0>;
-                                                remote-endpoint= <&csi20vin1>;
+                                                remote-endpoint = <&csi20vin1>;
                                         };
                                         vin1csi40: endpoint@2 {
                                                 reg = <2>;
-                                                remote-endpoint= <&csi40vin1>;
+                                                remote-endpoint = <&csi40vin1>;
                                         };
                                 };
                         };
@@ -1363,11 +1362,11 @@
 
                                         vin2csi20: endpoint@0 {
                                                 reg = <0>;
-                                                remote-endpoint= <&csi20vin2>;
+                                                remote-endpoint = <&csi20vin2>;
                                         };
                                         vin2csi40: endpoint@2 {
                                                 reg = <2>;
-                                                remote-endpoint= <&csi40vin2>;
+                                                remote-endpoint = <&csi40vin2>;
                                         };
                                 };
                         };
@@ -1395,11 +1394,11 @@
 
                                         vin3csi20: endpoint@0 {
                                                 reg = <0>;
-                                                remote-endpoint= <&csi20vin3>;
+                                                remote-endpoint = <&csi20vin3>;
                                         };
                                         vin3csi40: endpoint@2 {
                                                 reg = <2>;
-                                                remote-endpoint= <&csi40vin3>;
+                                                remote-endpoint = <&csi40vin3>;
                                         };
                                 };
                         };
@@ -1427,11 +1426,11 @@
 
                                         vin4csi20: endpoint@0 {
                                                 reg = <0>;
-                                                remote-endpoint= <&csi20vin4>;
+                                                remote-endpoint = <&csi20vin4>;
                                         };
                                         vin4csi40: endpoint@2 {
                                                 reg = <2>;
-                                                remote-endpoint= <&csi40vin4>;
+                                                remote-endpoint = <&csi40vin4>;
                                         };
                                 };
                         };
@@ -1459,11 +1458,11 @@
 
                                         vin5csi20: endpoint@0 {
                                                 reg = <0>;
-                                                remote-endpoint= <&csi20vin5>;
+                                                remote-endpoint = <&csi20vin5>;
                                         };
                                         vin5csi40: endpoint@2 {
                                                 reg = <2>;
-                                                remote-endpoint= <&csi40vin5>;
+                                                remote-endpoint = <&csi40vin5>;
                                         };
                                 };
                         };
@@ -1491,11 +1490,11 @@
 
                                         vin6csi20: endpoint@0 {
                                                 reg = <0>;
-                                                remote-endpoint= <&csi20vin6>;
+                                                remote-endpoint = <&csi20vin6>;
                                         };
                                         vin6csi40: endpoint@2 {
                                                 reg = <2>;
-                                                remote-endpoint= <&csi40vin6>;
+                                                remote-endpoint = <&csi40vin6>;
                                         };
                                 };
                         };
@@ -1523,11 +1522,11 @@
 
                                         vin7csi20: endpoint@0 {
                                                 reg = <0>;
-                                                remote-endpoint= <&csi20vin7>;
+                                                remote-endpoint = <&csi20vin7>;
                                         };
                                         vin7csi40: endpoint@2 {
                                                 reg = <2>;
-                                                remote-endpoint= <&csi40vin7>;
+                                                remote-endpoint = <&csi40vin7>;
                                         };
                                 };
                         };
@@ -1970,11 +1969,11 @@
                         compatible = "generic-ohci";
                         reg = <0 0xee080000 0 0x100>;
                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 703>;
+                        clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
                         phys = <&usb2_phy0>;
                         phy-names = "usb";
                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
-                        resets = <&cpg 703>;
+                        resets = <&cpg 703>, <&cpg 704>;
                         status = "disabled";
                 };
 
@@ -1994,12 +1993,12 @@
                         compatible = "generic-ehci";
                         reg = <0 0xee080100 0 0x100>;
                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 703>;
+                        clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
                         phys = <&usb2_phy0>;
                         phy-names = "usb";
-                        companion= <&ohci0>;
+                        companion = <&ohci0>;
                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
-                        resets = <&cpg 703>;
+                        resets = <&cpg 703>, <&cpg 704>;
                         status = "disabled";
                 };
 
@@ -2010,7 +2009,7 @@
                         clocks = <&cpg CPG_MOD 702>;
                         phys = <&usb2_phy1>;
                         phy-names = "usb";
-                        companion= <&ohci1>;
+                        companion = <&ohci1>;
                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
                         resets = <&cpg 702>;
                         status = "disabled";
@@ -2021,9 +2020,9 @@
                                      "renesas,rcar-gen3-usb2-phy";
                         reg = <0 0xee080200 0 0x700>;
                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 703>;
+                        clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
-                        resets = <&cpg 703>;
+                        resets = <&cpg 703>, <&cpg 704>;
                         #phy-cells = <0>;
                         status = "disabled";
                 };
@@ -2437,17 +2436,14 @@
 
                 du: display@feb00000 {
                         compatible = "renesas,du-r8a7796";
-                        reg = <0 0xfeb00000 0 0x70000>,
-                              <0 0xfeb90000 0 0x14>;
-                        reg-names = "du", "lvds.0";
+                        reg = <0 0xfeb00000 0 0x70000>;
                         interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
                                      <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
                                      <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&cpg CPG_MOD 724>,
                                  <&cpg CPG_MOD 723>,
-                                 <&cpg CPG_MOD 722>,
-                                 <&cpg CPG_MOD 727>;
-                        clock-names = "du.0", "du.1", "du.2", "lvds.0";
+                                 <&cpg CPG_MOD 722>;
+                        clock-names = "du.0", "du.1", "du.2";
                         status = "disabled";
 
                         vsps = <&vspd0 &vspd1 &vspd2>;
@@ -2470,6 +2466,33 @@
                                 port@2 {
                                         reg = <2>;
                                         du_out_lvds0: endpoint {
+                                                remote-endpoint = <&lvds0_in>;
+                                        };
+                                };
+                        };
+                };
+
+                lvds0: lvds@feb90000 {
+                        compatible = "renesas,r8a7796-lvds";
+                        reg = <0 0xfeb90000 0 0x14>;
+                        clocks = <&cpg CPG_MOD 727>;
+                        power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+                        resets = <&cpg 727>;
+                        status = "disabled";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@0 {
+                                        reg = <0>;
+                                        lvds0_in: endpoint {
+                                                remote-endpoint = <&du_out_lvds0>;
+                                        };
+                                };
+                                port@1 {
+                                        reg = <1>;
+                                        lvds0_out: endpoint {
                                         };
                                 };
                         };
diff --git a/arch/arm64/boot/dts/renesas/r8a77965-m3nulcb-kf.dts b/arch/arm64/boot/dts/renesas/r8a77965-m3nulcb-kf.dts
new file mode 100644
index 000000000000..dadad97051b9
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a77965-m3nulcb-kf.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the M3NULCB Kingfisher board
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
+ */
+
+#include "r8a77965-m3nulcb.dts"
+#include "ulcb-kf.dtsi"
+
+/ {
+        model = "Renesas M3NULCB Kingfisher board based on r8a77965";
+        compatible = "shimafuji,kingfisher", "renesas,m3nulcb",
+                     "renesas,r8a77965";
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a77965-m3nulcb.dts b/arch/arm64/boot/dts/renesas/r8a77965-m3nulcb.dts
new file mode 100644
index 000000000000..964078b6cc49
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a77965-m3nulcb.dts
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the M3NULCB (R-Car Starter Kit Pro) board
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
+ */
+
+/dts-v1/;
+#include "r8a77965.dtsi"
+#include "ulcb.dtsi"
+
+/ {
+        model = "Renesas M3NULCB board based on r8a77965";
+        compatible = "renesas,m3nulcb", "renesas,r8a77965";
+
+        memory@48000000 {
+                device_type = "memory";
+                /* first 128MB is reserved for secure area. */
+                reg = <0x0 0x48000000 0x0 0x78000000>;
+        };
+};
+
+&du {
+        clocks = <&cpg CPG_MOD 724>,
+                 <&cpg CPG_MOD 723>,
+                 <&cpg CPG_MOD 721>,
+                 <&versaclock5 1>,
+                 <&versaclock5 3>,
+                 <&versaclock5 2>;
+        clock-names = "du.0", "du.1", "du.3",
+                      "dclkin.0", "dclkin.1", "dclkin.3";
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
index 9de4e3db1621..f03a5e9e0c42 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
@@ -47,3 +47,17 @@
 &hdmi0_con {
         remote-endpoint = <&rcar_dw_hdmi0_out>;
 };
+
+&pca9654 {
+        pcie_sata_switch {
+                gpio-hog;
+                gpios = <7 GPIO_ACTIVE_HIGH>;
+                output-low; /* enable SATA by default */
+                line-name = "PCIE/SATA switch";
+        };
+};
+
+/* SW12-7 must be set 'Off' (MD12 set to 1) which is not the default! */
+&sata {
+        status = "okay";
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index 0cd44461a0bd..83946ca2eba5 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source for the r8a77965 SoC
+ * Device Tree Source for the R-Car M3-N (R8A77965) SoC
  *
  * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
  *
@@ -12,7 +12,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/power/r8a77965-sysc.h>
 
-#define CPG_AUDIO_CLK_I         10
+#define CPG_AUDIO_CLK_I         R8A77965_CLK_S0D4
 
 / {
         compatible = "renesas,r8a77965";
@@ -60,6 +60,46 @@
                 clock-frequency = <0>;
         };
 
+        cluster0_opp: opp_table0 {
+                compatible = "operating-points-v2";
+                opp-shared;
+
+                opp-500000000 {
+                        opp-hz = /bits/ 64 <500000000>;
+                        opp-microvolt = <830000>;
+                        clock-latency-ns = <300000>;
+                };
+                opp-1000000000 {
+                        opp-hz = /bits/ 64 <1000000000>;
+                        opp-microvolt = <830000>;
+                        clock-latency-ns = <300000>;
+                };
+                opp-1500000000 {
+                        opp-hz = /bits/ 64 <1500000000>;
+                        opp-microvolt = <830000>;
+                        clock-latency-ns = <300000>;
+                        opp-suspend;
+                };
+                opp-1600000000 {
+                        opp-hz = /bits/ 64 <1600000000>;
+                        opp-microvolt = <900000>;
+                        clock-latency-ns = <300000>;
+                        turbo-mode;
+                };
+                opp-1700000000 {
+                        opp-hz = /bits/ 64 <1700000000>;
+                        opp-microvolt = <900000>;
+                        clock-latency-ns = <300000>;
+                        turbo-mode;
+                };
+                opp-1800000000 {
+                        opp-hz = /bits/ 64 <1800000000>;
+                        opp-microvolt = <960000>;
+                        clock-latency-ns = <300000>;
+                        turbo-mode;
+                };
+        };
+
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -71,6 +111,8 @@
                         power-domains = <&sysc R8A77965_PD_CA57_CPU0>;
                         next-level-cache = <&L2_CA57>;
                         enable-method = "psci";
+                        clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
+                        operating-points-v2 = <&cluster0_opp>;
                 };
 
                 a57_1: cpu@1 {
@@ -80,6 +122,8 @@
                         power-domains = <&sysc R8A77965_PD_CA57_CPU1>;
                         next-level-cache = <&L2_CA57>;
                         enable-method = "psci";
+                        clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
+                        operating-points-v2 = <&cluster0_opp>;
                 };
 
                 L2_CA57: cache-controller-0 {
@@ -306,7 +350,6 @@
                         power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
                         resets = <&cpg 522>;
                         #thermal-sensor-cells = <1>;
-                        status = "okay";
                 };
 
                 intc_ex: interrupt-controller@e61c0000 {
@@ -545,11 +588,11 @@
                 };
 
                 hsusb: usb@e6590000 {
-                        compatible = "renesas,usbhs-r8a7796",
+                        compatible = "renesas,usbhs-r8a77965",
                                      "renesas,rcar-gen3-usbhs";
                         reg = <0 0xe6590000 0 0x100>;
                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 704>;
+                        clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
                         dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
                                <&usb_dmac1 0>, <&usb_dmac1 1>;
                         dma-names = "ch0", "ch1", "ch2", "ch3";
@@ -557,7 +600,7 @@
                         phys = <&usb2_phy0>;
                         phy-names = "usb";
                         power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
-                        resets = <&cpg 704>;
+                        resets = <&cpg 704>, <&cpg 703>;
                         status = "disabled";
                 };
 
@@ -634,6 +677,14 @@
                         resets = <&cpg 219>;
                         #dma-cells = <1>;
                         dma-channels = <16>;
+                        iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
+                               <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
+                               <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
+                               <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
+                               <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
+                               <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
+                               <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
+                               <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
                 };
 
                 dmac1: dma-controller@e7300000 {
@@ -668,6 +719,14 @@
                         resets = <&cpg 218>;
                         #dma-cells = <1>;
                         dma-channels = <16>;
+                        iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
+                               <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
+                               <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
+                               <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
+                               <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
+                               <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
+                               <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
+                               <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
                 };
 
                 dmac2: dma-controller@e7310000 {
@@ -702,6 +761,14 @@
                         resets = <&cpg 217>;
                         #dma-cells = <1>;
                         dma-channels = <16>;
+                        iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
+                               <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
+                               <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
+                               <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
+                               <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
+                               <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
+                               <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
+                               <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
                 };
 
                 ipmmu_ds0: mmu@e6740000 {
@@ -838,6 +905,16 @@
                         status = "disabled";
                 };
 
+                can0: can@e6c30000 {
+                        reg = <0 0xe6c30000 0 0x1000>;
+                        /* placeholder */
+                };
+
+                can1: can@e6c38000 {
+                        reg = <0 0xe6c38000 0 0x1000>;
+                        /* placeholder */
+                };
+
                 pwm0: pwm@e6e30000 {
                         compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
                         reg = <0 0xe6e30000 0 8>;
@@ -1089,11 +1166,11 @@
 
                                         vin0csi20: endpoint@0 {
                                                 reg = <0>;
-                                                remote-endpoint= <&csi20vin0>;
+                                                remote-endpoint = <&csi20vin0>;
                                         };
                                         vin0csi40: endpoint@2 {
                                                 reg = <2>;
-                                                remote-endpoint= <&csi40vin0>;
+                                                remote-endpoint = <&csi40vin0>;
                                         };
                                 };
                         };
@@ -1121,11 +1198,11 @@
 
                                         vin1csi20: endpoint@0 {
                                                 reg = <0>;
-                                                remote-endpoint= <&csi20vin1>;
+                                                remote-endpoint = <&csi20vin1>;
                                         };
                                         vin1csi40: endpoint@2 {
                                                 reg = <2>;
-                                                remote-endpoint= <&csi40vin1>;
+                                                remote-endpoint = <&csi40vin1>;
                                         };
                                 };
                         };
@@ -1153,11 +1230,11 @@
 
                                         vin2csi20: endpoint@0 {
                                                 reg = <0>;
-                                                remote-endpoint= <&csi20vin2>;
+                                                remote-endpoint = <&csi20vin2>;
                                         };
                                         vin2csi40: endpoint@2 {
                                                 reg = <2>;
-                                                remote-endpoint= <&csi40vin2>;
+                                                remote-endpoint = <&csi40vin2>;
                                         };
                                 };
                         };
@@ -1185,11 +1262,11 @@
 
                                         vin3csi20: endpoint@0 {
                                                 reg = <0>;
-                                                remote-endpoint= <&csi20vin3>;
+                                                remote-endpoint = <&csi20vin3>;
                                         };
                                         vin3csi40: endpoint@2 {
                                                 reg = <2>;
-                                                remote-endpoint= <&csi40vin3>;
+                                                remote-endpoint = <&csi40vin3>;
                                         };
                                 };
                         };
@@ -1217,11 +1294,11 @@
 
                                         vin4csi20: endpoint@0 {
                                                 reg = <0>;
-                                                remote-endpoint= <&csi20vin4>;
+                                                remote-endpoint = <&csi20vin4>;
                                         };
                                         vin4csi40: endpoint@2 {
                                                 reg = <2>;
-                                                remote-endpoint= <&csi40vin4>;
+                                                remote-endpoint = <&csi40vin4>;
                                         };
                                 };
                         };
@@ -1249,11 +1326,11 @@
 
                                         vin5csi20: endpoint@0 {
                                                 reg = <0>;
-                                                remote-endpoint= <&csi20vin5>;
+                                                remote-endpoint = <&csi20vin5>;
                                         };
                                         vin5csi40: endpoint@2 {
                                                 reg = <2>;
-                                                remote-endpoint= <&csi40vin5>;
+                                                remote-endpoint = <&csi40vin5>;
                                         };
                                 };
                         };
@@ -1281,11 +1358,11 @@
 
                                         vin6csi20: endpoint@0 {
                                                 reg = <0>;
-                                                remote-endpoint= <&csi20vin6>;
+                                                remote-endpoint = <&csi20vin6>;
                                         };
                                         vin6csi40: endpoint@2 {
                                                 reg = <2>;
-                                                remote-endpoint= <&csi40vin6>;
+                                                remote-endpoint = <&csi40vin6>;
                                         };
                                 };
                         };
@@ -1313,57 +1390,280 @@
 
                                         vin7csi20: endpoint@0 {
                                                 reg = <0>;
-                                                remote-endpoint= <&csi20vin7>;
+                                                remote-endpoint = <&csi20vin7>;
                                         };
                                         vin7csi40: endpoint@2 {
                                                 reg = <2>;
-                                                remote-endpoint= <&csi40vin7>;
+                                                remote-endpoint = <&csi40vin7>;
                                         };
                                 };
                         };
                 };
 
                 rcar_sound: sound@ec500000 {
+                        /*
+                         * #sound-dai-cells is required
+                         *
+                         * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
+                         * Multi  DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
+                         */
+                        /*
+                         * #clock-cells is required for audio_clkout0/1/2/3
+                         *
+                         * clkout       : #clock-cells = <0>;   <&rcar_sound>;
+                         * clkout0/1/2/3: #clock-cells = <1>;   <&rcar_sound N>;
+                         */
+                        compatible =  "renesas,rcar_sound-r8a77965", "renesas,rcar_sound-gen3";
                         reg =   <0 0xec500000 0 0x1000>, /* SCU */
                                 <0 0xec5a0000 0 0x100>,  /* ADG */
                                 <0 0xec540000 0 0x1000>, /* SSIU */
                                 <0 0xec541000 0 0x280>,  /* SSI */
                                 <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
-                        /* placeholder */
+                        reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+                        clocks = <&cpg CPG_MOD 1005>,
+                                 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+                                 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+                                 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+                                 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+                                 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+                                 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+                                 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+                                 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+                                 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+                                 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+                                 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+                                 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+                                 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+                                 <&audio_clk_a>, <&audio_clk_b>,
+                                 <&audio_clk_c>,
+                                 <&cpg CPG_CORE R8A77965_CLK_S0D4>;
+                        clock-names = "ssi-all",
+                                      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+                                      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+                                      "ssi.1", "ssi.0",
+                                      "src.9", "src.8", "src.7", "src.6",
+                                      "src.5", "src.4", "src.3", "src.2",
+                                      "src.1", "src.0",
+                                      "mix.1", "mix.0",
+                                      "ctu.1", "ctu.0",
+                                      "dvc.0", "dvc.1",
+                                      "clk_a", "clk_b", "clk_c", "clk_i";
+                        power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+                        resets = <&cpg 1005>,
+                                 <&cpg 1006>, <&cpg 1007>,
+                                 <&cpg 1008>, <&cpg 1009>,
+                                 <&cpg 1010>, <&cpg 1011>,
+                                 <&cpg 1012>, <&cpg 1013>,
+                                 <&cpg 1014>, <&cpg 1015>;
+                        reset-names = "ssi-all",
+                                      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+                                      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+                                      "ssi.1", "ssi.0";
+                        status = "disabled";
 
                         rcar_sound,dvc {
                                 dvc0: dvc-0 {
+                                        dmas = <&audma1 0xbc>;
+                                        dma-names = "tx";
                                 };
                                 dvc1: dvc-1 {
+                                        dmas = <&audma1 0xbe>;
+                                        dma-names = "tx";
                                 };
                         };
 
+                        rcar_sound,mix {
+                                mix0: mix-0 { };
+                                mix1: mix-1 { };
+                        };
+
+                        rcar_sound,ctu {
+                                ctu00: ctu-0 { };
+                                ctu01: ctu-1 { };
+                                ctu02: ctu-2 { };
+                                ctu03: ctu-3 { };
+                                ctu10: ctu-4 { };
+                                ctu11: ctu-5 { };
+                                ctu12: ctu-6 { };
+                                ctu13: ctu-7 { };
+                        };
+
                         rcar_sound,src {
                                 src0: src-0 {
+                                        interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x85>, <&audma1 0x9a>;
+                                        dma-names = "rx", "tx";
                                 };
                                 src1: src-1 {
+                                        interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x87>, <&audma1 0x9c>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src2: src-2 {
+                                        interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x89>, <&audma1 0x9e>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src3: src-3 {
+                                        interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x8b>, <&audma1 0xa0>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src4: src-4 {
+                                        interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x8d>, <&audma1 0xb0>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src5: src-5 {
+                                        interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x8f>, <&audma1 0xb2>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src6: src-6 {
+                                        interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x91>, <&audma1 0xb4>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src7: src-7 {
+                                        interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x93>, <&audma1 0xb6>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src8: src-8 {
+                                        interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x95>, <&audma1 0xb8>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src9: src-9 {
+                                        interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x97>, <&audma1 0xba>;
+                                        dma-names = "rx", "tx";
                                 };
                         };
 
                         rcar_sound,ssi {
                                 ssi0: ssi-0 {
+                                        interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
                                 };
                                 ssi1: ssi-1 {
+                                        interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
                                 };
-                        };
-
-                        ports {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                port@0 {
-                                        reg = <0>;
+                                ssi2: ssi-2 {
+                                        interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
                                 };
-                                port@1 {
-                                        reg = <1>;
+                                ssi3: ssi-3 {
+                                        interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi4: ssi-4 {
+                                        interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi5: ssi-5 {
+                                        interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi6: ssi-6 {
+                                        interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi7: ssi-7 {
+                                        interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi8: ssi-8 {
+                                        interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi9: ssi-9 {
+                                        interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
                                 };
                         };
                 };
 
+                audma0: dma-controller@ec700000 {
+                        compatible = "renesas,dmac-r8a77965",
+                                     "renesas,rcar-dmac";
+                        reg = <0 0xec700000 0 0x10000>;
+                        interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "error",
+                                        "ch0", "ch1", "ch2", "ch3",
+                                        "ch4", "ch5", "ch6", "ch7",
+                                        "ch8", "ch9", "ch10", "ch11",
+                                        "ch12", "ch13", "ch14", "ch15";
+                        clocks = <&cpg CPG_MOD 502>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+                        resets = <&cpg 502>;
+                        #dma-cells = <1>;
+                        dma-channels = <16>;
+                };
+
+                audma1: dma-controller@ec720000 {
+                        compatible = "renesas,dmac-r8a77965",
+                                     "renesas,rcar-dmac";
+                        reg = <0 0xec720000 0 0x10000>;
+                        interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "error",
+                                        "ch0", "ch1", "ch2", "ch3",
+                                        "ch4", "ch5", "ch6", "ch7",
+                                        "ch8", "ch9", "ch10", "ch11",
+                                        "ch12", "ch13", "ch14", "ch15";
+                        clocks = <&cpg CPG_MOD 501>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+                        resets = <&cpg 501>;
+                        #dma-cells = <1>;
+                        dma-channels = <16>;
+                };
+
                 xhci0: usb@ee000000 {
                         compatible = "renesas,xhci-r8a77965",
                                      "renesas,rcar-gen3-xhci";
@@ -1390,11 +1690,11 @@
                         compatible = "generic-ohci";
                         reg = <0 0xee080000 0 0x100>;
                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 703>;
+                        clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
                         phys = <&usb2_phy0>;
                         phy-names = "usb";
                         power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
-                        resets = <&cpg 703>;
+                        resets = <&cpg 703>, <&cpg 704>;
                         status = "disabled";
                 };
 
@@ -1414,12 +1714,12 @@
                         compatible = "generic-ehci";
                         reg = <0 0xee080100 0 0x100>;
                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 703>;
+                        clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
                         phys = <&usb2_phy0>;
                         phy-names = "usb";
                         companion = <&ohci0>;
                         power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
-                        resets = <&cpg 703>;
+                        resets = <&cpg 703>, <&cpg 704>;
                         status = "disabled";
                 };
 
@@ -1441,9 +1741,9 @@
                                      "renesas,rcar-gen3-usb2-phy";
                         reg = <0 0xee080200 0 0x700>;
                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 703>;
+                        clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
                         power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
-                        resets = <&cpg 703>;
+                        resets = <&cpg 703>, <&cpg 704>;
                         #phy-cells = <0>;
                         status = "disabled";
                 };
@@ -1452,9 +1752,9 @@
                         compatible = "renesas,usb2-phy-r8a77965",
                                      "renesas,rcar-gen3-usb2-phy";
                         reg = <0 0xee0a0200 0 0x700>;
-                        clocks = <&cpg CPG_MOD 703>;
+                        clocks = <&cpg CPG_MOD 702>;
                         power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
-                        resets = <&cpg 703>;
+                        resets = <&cpg 702>;
                         #phy-cells = <0>;
                         status = "disabled";
                 };
@@ -1507,6 +1807,17 @@
                         status = "disabled";
                 };
 
+                sata: sata@ee300000 {
+                        compatible = "renesas,sata-r8a77965",
+                                     "renesas,rcar-gen3-sata";
+                        reg = <0 0xee300000 0 0x200000>;
+                        interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 815>;
+                        power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+                        resets = <&cpg 815>;
+                        status = "disabled";
+                };
+
                 gic: interrupt-controller@f1010000 {
                         compatible = "arm,gic-400";
                         #interrupt-cells = <3>;
@@ -1578,6 +1889,16 @@
                         status = "disabled";
                 };
 
+                fdp1@fe940000 {
+                        compatible = "renesas,fdp1";
+                        reg = <0 0xfe940000 0 0x2400>;
+                        interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 119>;
+                        power-domains = <&sysc R8A77965_PD_A3VP>;
+                        resets = <&cpg 119>;
+                        renesas,fcp = <&fcpf0>;
+                };
+
                 fcpf0: fcp@fe950000 {
                         compatible = "renesas,fcpf";
                         reg = <0 0xfe950000 0 0x200>;
@@ -1843,14 +2164,6 @@
                 };
         };
 
-        timer {
-                compatible = "arm,armv8-timer";
-                interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-                                      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-                                      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-                                      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
-        };
-
         thermal-zones {
                 sensor_thermal1: sensor-thermal1 {
                         polling-delay-passive = <250>;
@@ -1895,6 +2208,14 @@
                 };
         };
 
+        timer {
+                compatible = "arm,armv8-timer";
+                interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                                      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                                      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                                      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+        };
+
         /* External USB clocks - can be overridden by the board */
         usb3s0_clk: usb3s0 {
                 compatible = "fixed-clock";
diff --git a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
index 8eac8ca6550b..0dbcb4cccc18 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
@@ -51,6 +51,15 @@
                 regulator-always-on;
         };
 
+        vcc_vddq_vin0: regulator-2 {
+                compatible = "regulator-fixed";
+                regulator-name = "VCC_VDDQ_VIN0";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-boot-on;
+                regulator-always-on;
+        };
+
         lvds-decoder {
                 compatible = "thine,thc63lvd1024";
                 vcc-supply = <&vcc_d3_3v>;
@@ -128,6 +137,12 @@
                 function = "i2c0";
         };
 
+        mmc_pins: mmc_3_3v {
+                groups = "mmc_data8", "mmc_ctrl";
+                function = "mmc";
+                power-source = <3300>;
+        };
+
         scif0_pins: scif0 {
                 groups = "scif0_data";
                 function = "scif0";
@@ -192,6 +207,17 @@
         };
 };
 
+&mmc0 {
+        pinctrl-0 = <&mmc_pins>;
+        pinctrl-names = "default";
+
+        vmmc-supply = <&vcc_d3_3v>;
+        vqmmc-supply = <&vcc_vddq_vin0>;
+        bus-width = <8>;
+        non-removable;
+        status = "okay";
+};
+
 &scif0 {
         pinctrl-0 = <&scif0_pins>;
         pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
index 954168858fed..cba7885cf7c3 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source for the r8a77970 SoC
+ * Device Tree Source for the R-Car V3M (R8A77970) SoC
  *
  * Copyright (C) 2016-2017 Renesas Electronics Corp.
  * Copyright (C) 2017 Cogent Embedded, Inc.
@@ -24,6 +24,13 @@
                 i2c4 = &i2c4;
         };
 
+        /* External CAN clock - to be overridden by boards that provide it */
+        can_clk: can {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -82,13 +89,6 @@
                 method = "smc";
         };
 
-        /* External CAN clock - to be overridden by boards that provide it */
-        can_clk: can {
-                compatible = "fixed-clock";
-                #clock-cells = <0>;
-                clock-frequency = <0>;
-        };
-
         /* External SCIF clock - to be overridden by boards that provide it */
         scif_clk: scif {
                 compatible = "fixed-clock";
@@ -209,6 +209,76 @@
                         reg = <0 0xe6060000 0 0x504>;
                 };
 
+                cmt0: timer@e60f0000 {
+                        compatible = "renesas,r8a77970-cmt0",
+                                     "renesas,rcar-gen3-cmt0";
+                        reg = <0 0xe60f0000 0 0x1004>;
+                        interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 303>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+                        resets = <&cpg 303>;
+                        status = "disabled";
+                };
+
+                cmt1: timer@e6130000 {
+                        compatible = "renesas,r8a77970-cmt1",
+                                     "renesas,rcar-gen3-cmt1";
+                        reg = <0 0xe6130000 0 0x1004>;
+                        interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 302>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+                        resets = <&cpg 302>;
+                        status = "disabled";
+                };
+
+                cmt2: timer@e6140000 {
+                        compatible = "renesas,r8a77970-cmt1",
+                                     "renesas,rcar-gen3-cmt1";
+                        reg = <0 0xe6140000 0 0x1004>;
+                        interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 301>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+                        resets = <&cpg 301>;
+                        status = "disabled";
+                };
+
+                cmt3: timer@e6148000 {
+                        compatible = "renesas,r8a77970-cmt1",
+                                     "renesas,rcar-gen3-cmt1";
+                        reg = <0 0xe6148000 0 0x1004>;
+                        interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 300>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+                        resets = <&cpg 300>;
+                        status = "disabled";
+                };
+
                 cpg: clock-controller@e6150000 {
                         compatible = "renesas,r8a77970-cpg-mssr";
                         reg = <0 0xe6150000 0 0x1000>;
@@ -544,6 +614,16 @@
                         status = "disabled";
                 };
 
+                tpu: pwm@e6e80000 {
+                        compatible = "renesas,tpu-r8a77970", "renesas,tpu";
+                        reg = <0 0xe6e80000 0 0x148>;
+                        interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 304>;
+                        power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+                        resets = <&cpg 304>;
+                        #pwm-cells = <3>;
+                        status = "disabled";
+                };
 
                 vin0: video@e6ef0000 {
                         compatible = "renesas,vin-r8a77970";
@@ -567,7 +647,7 @@
 
                                         vin0csi40: endpoint@2 {
                                                 reg = <2>;
-                                                remote-endpoint= <&csi40vin0>;
+                                                remote-endpoint = <&csi40vin0>;
                                         };
                                 };
                         };
@@ -595,7 +675,7 @@
 
                                         vin1csi40: endpoint@2 {
                                                 reg = <2>;
-                                                remote-endpoint= <&csi40vin1>;
+                                                remote-endpoint = <&csi40vin1>;
                                         };
                                 };
                         };
@@ -623,7 +703,7 @@
 
                                         vin2csi40: endpoint@2 {
                                                 reg = <2>;
-                                                remote-endpoint= <&csi40vin2>;
+                                                remote-endpoint = <&csi40vin2>;
                                         };
                                 };
                         };
@@ -651,7 +731,7 @@
 
                                         vin3csi40: endpoint@2 {
                                                 reg = <2>;
-                                                remote-endpoint= <&csi40vin3>;
+                                                remote-endpoint = <&csi40vin3>;
                                         };
                                 };
                         };
@@ -754,6 +834,18 @@
                         #iommu-cells = <1>;
                 };
 
+                mmc0: mmc@ee140000 {
+                        compatible = "renesas,sdhi-r8a77970",
+                                     "renesas,rcar-gen3-sdhi";
+                        reg = <0 0xee140000 0 0x2000>;
+                        interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 314>;
+                        power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+                        resets = <&cpg 314>;
+                        max-frequency = <200000000>;
+                        status = "disabled";
+                };
+
                 gic: interrupt-controller@f1010000 {
                         compatible = "arm,gic-400";
                         #interrupt-cells = <3>;
diff --git a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
index 9f25c407dfd7..fe2e2c051cc9 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
@@ -45,6 +45,56 @@
                 regulator-boot-on;
                 regulator-always-on;
         };
+
+        d1_8v: regulator-2 {
+                compatible = "regulator-fixed";
+                regulator-name = "D1.8V";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                regulator-boot-on;
+                regulator-always-on;
+        };
+
+        hdmi-out {
+                compatible = "hdmi-connector";
+                type = "a";
+
+                port {
+                        hdmi_con: endpoint {
+                                remote-endpoint = <&adv7511_out>;
+                        };
+                };
+        };
+
+        lvds-decoder {
+                compatible = "thine,thc63lvd1024";
+                vcc-supply = <&d3_3v>;
+
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@0 {
+                                reg = <0>;
+                                thc63lvd1024_in: endpoint {
+                                        remote-endpoint = <&lvds0_out>;
+                                };
+                        };
+
+                        port@2 {
+                                reg = <2>;
+                                thc63lvd1024_out: endpoint {
+                                        remote-endpoint = <&adv7511_in>;
+                                };
+                        };
+                };
+        };
+
+        x1_clk: x1-clock {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <148500000>;
+        };
 };
 
 &avb {
@@ -74,6 +124,13 @@
         };
 };
 
+&du {
+        clocks = <&cpg CPG_MOD 724>,
+                 <&x1_clk>;
+        clock-names = "du.0", "dclkin.0";
+        status = "okay";
+};
+
 &extal_clk {
         clock-frequency = <16666666>;
 };
@@ -102,6 +159,55 @@
                 gpio-controller;
                 #gpio-cells = <2>;
         };
+
+        hdmi@39 {
+                compatible = "adi,adv7511w";
+                reg = <0x39>;
+                interrupt-parent = <&gpio1>;
+                interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
+                avdd-supply = <&d1_8v>;
+                dvdd-supply = <&d1_8v>;
+                pvdd-supply = <&d1_8v>;
+                bgvdd-supply = <&d1_8v>;
+                dvdd-3v-supply = <&d3_3v>;
+
+                adi,input-depth = <8>;
+                adi,input-colorspace = "rgb";
+                adi,input-clock = "1x";
+                adi,input-style = <1>;
+                adi,input-justification = "evenly";
+
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@0 {
+                                reg = <0>;
+                                adv7511_in: endpoint {
+                                        remote-endpoint = <&thc63lvd1024_out>;
+                                };
+                        };
+
+                        port@1 {
+                                reg = <1>;
+                                adv7511_out: endpoint {
+                                        remote-endpoint = <&hdmi_con>;
+                                };
+                        };
+                };
+        };
+};
+
+&lvds0 {
+        status = "okay";
+
+        ports {
+                port@1 {
+                        lvds0_out: endpoint {
+                                remote-endpoint = <&thc63lvd1024_in>;
+                        };
+                };
+        };
 };
 
 &mmc0 {
@@ -117,6 +223,18 @@
         status = "okay";
 };
 
+&pciec {
+        status = "okay";
+};
+
+&pcie_bus_clk {
+        clock-frequency = <100000000>;
+};
+
+&pcie_phy {
+        status = "okay";
+};
+
 &pfc {
         avb_pins: avb {
                 groups = "avb_mdio", "avb_rgmii";
@@ -156,6 +274,11 @@
         };
 };
 
+&rwdt {
+        timeout-sec = <60>;
+        status = "okay";
+};
+
 &scif0 {
         pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
         pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
index 9dac42f8f804..dd14a41b32cd 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
@@ -27,6 +27,72 @@
                 /* first 128MB is reserved for secure area. */
                 reg = <0 0x48000000 0 0x78000000>;
         };
+
+        hdmi-out {
+                compatible = "hdmi-connector";
+                type = "a";
+
+                port {
+                        hdmi_con: endpoint {
+                                remote-endpoint = <&adv7511_out>;
+                        };
+                };
+        };
+
+        lvds-decoder {
+                compatible = "thine,thc63lvd1024";
+                vcc-supply = <&vcc3v3_d5>;
+
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@0 {
+                                reg = <0>;
+                                thc63lvd1024_in: endpoint {
+                                        remote-endpoint = <&lvds0_out>;
+                                };
+                        };
+
+                        port@2 {
+                                reg = <2>;
+                                thc63lvd1024_out: endpoint {
+                                        remote-endpoint = <&adv7511_in>;
+                                };
+                        };
+                };
+        };
+
+        osc1_clk: osc1-clock {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <148500000>;
+        };
+
+        vcc1v8_d4: regulator-0 {
+                compatible = "regulator-fixed";
+                regulator-name = "VCC1V8_D4";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                regulator-boot-on;
+                regulator-always-on;
+        };
+
+        vcc3v3_d5: regulator-1 {
+                compatible = "regulator-fixed";
+                regulator-name = "VCC3V3_D5";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-boot-on;
+                regulator-always-on;
+        };
+};
+
+&du {
+        clocks = <&cpg CPG_MOD 724>,
+                 <&osc1_clk>;
+        clock-names = "du.0", "dclkin.0";
+        status = "okay";
 };
 
 &extal_clk {
@@ -53,6 +119,64 @@
         };
 };
 
+&i2c0 {
+        pinctrl-0 = <&i2c0_pins>;
+        pinctrl-names = "default";
+
+        status = "okay";
+        clock-frequency = <400000>;
+
+        hdmi@39 {
+                compatible = "adi,adv7511w";
+                #sound-dai-cells = <0>;
+                reg = <0x39>;
+                interrupt-parent = <&gpio1>;
+                interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
+                avdd-supply = <&vcc1v8_d4>;
+                dvdd-supply = <&vcc1v8_d4>;
+                pvdd-supply = <&vcc1v8_d4>;
+                bgvdd-supply = <&vcc1v8_d4>;
+                dvdd-3v-supply = <&vcc3v3_d5>;
+
+                adi,input-depth = <8>;
+                adi,input-colorspace = "rgb";
+                adi,input-clock = "1x";
+                adi,input-style = <1>;
+                adi,input-justification = "evenly";
+
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@0 {
+                                reg = <0>;
+                                adv7511_in: endpoint {
+                                        remote-endpoint = <&thc63lvd1024_out>;
+                                };
+                        };
+
+                        port@1 {
+                                reg = <1>;
+                                adv7511_out: endpoint {
+                                        remote-endpoint = <&hdmi_con>;
+                                };
+                        };
+                };
+        };
+};
+
+&lvds0 {
+        status = "okay";
+
+        ports {
+                port@1 {
+                        lvds0_out: endpoint {
+                                remote-endpoint = <&thc63lvd1024_in>;
+                        };
+                };
+        };
+};
+
 &pfc {
         gether_pins: gether {
                 groups = "gether_mdio_a", "gether_rgmii",
@@ -60,6 +184,11 @@
                 function = "gether";
         };
 
+        i2c0_pins: i2c0 {
+                groups = "i2c0";
+                function = "i2c0";
+        };
+
         scif0_pins: scif0 {
                 groups = "scif0_data";
                 function = "scif0";
@@ -71,6 +200,11 @@
         };
 };
 
+&rwdt {
+        timeout-sec = <60>;
+        status = "okay";
+};
+
 &scif0 {
         pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
         pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
index b8c9a56562f2..d4952b527d14 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source for the r8a77980 SoC
+ * Device Tree Source for the R-Car V3H (R8A77980) SoC
  *
  * Copyright (C) 2018 Renesas Electronics Corp.
  * Copyright (C) 2018 Cogent Embedded, Inc.
@@ -25,6 +25,13 @@
                 i2c5 = &i2c5;
         };
 
+        /* External CAN clock - to be overridden by boards that provide it */
+        can_clk: can {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -77,27 +84,36 @@
                 };
         };
 
-        /* External CAN clock - to be overridden by boards that provide it */
-        can_clk: can {
+        extal_clk: extal {
                 compatible = "fixed-clock";
                 #clock-cells = <0>;
+                /* This value must be overridden by the board */
                 clock-frequency = <0>;
         };
 
-        extal_clk: extal {
+        extalr_clk: extalr {
                 compatible = "fixed-clock";
                 #clock-cells = <0>;
                 /* This value must be overridden by the board */
                 clock-frequency = <0>;
         };
 
-        extalr_clk: extalr {
+        /* External PCIe clock - can be overridden by the board */
+        pcie_bus_clk: pcie_bus {
                 compatible = "fixed-clock";
                 #clock-cells = <0>;
-                /* This value must be overridden by the board */
                 clock-frequency = <0>;
         };
 
+        pmu_a53 {
+                compatible = "arm,cortex-a53-pmu";
+                interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+                                      <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+                                      <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+                                      <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
+        };
+
         psci {
                 compatible = "arm,psci-1.0", "arm,psci-0.2";
                 method = "smc";
@@ -118,6 +134,16 @@
                 #size-cells = <2>;
                 ranges;
 
+                rwdt: watchdog@e6020000 {
+                        compatible = "renesas,r8a77980-wdt",
+                                     "renesas,rcar-gen3-wdt";
+                        reg = <0 0xe6020000 0 0x0c>;
+                        clocks = <&cpg CPG_MOD 402>;
+                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+                        resets = <&cpg 402>;
+                        status = "disabled";
+                };
+
                 gpio0: gpio@e6050000 {
                         compatible = "renesas,gpio-r8a77980",
                                      "renesas,rcar-gen3-gpio";
@@ -213,6 +239,76 @@
                         reg = <0 0xe6060000 0 0x50c>;
                 };
 
+                cmt0: timer@e60f0000 {
+                        compatible = "renesas,r8a77980-cmt0",
+                                     "renesas,rcar-gen3-cmt0";
+                        reg = <0 0xe60f0000 0 0x1004>;
+                        interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 303>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+                        resets = <&cpg 303>;
+                        status = "disabled";
+                };
+
+                cmt1: timer@e6130000 {
+                        compatible = "renesas,r8a77980-cmt1",
+                                     "renesas,rcar-gen3-cmt1";
+                        reg = <0 0xe6130000 0 0x1004>;
+                        interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 302>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+                        resets = <&cpg 302>;
+                        status = "disabled";
+                };
+
+                cmt2: timer@e6140000 {
+                        compatible = "renesas,r8a77980-cmt1",
+                                     "renesas,rcar-gen3-cmt1";
+                        reg = <0 0xe6140000 0 0x1004>;
+                        interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 301>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+                        resets = <&cpg 301>;
+                        status = "disabled";
+                };
+
+                cmt3: timer@e6148000 {
+                        compatible = "renesas,r8a77980-cmt1",
+                                     "renesas,rcar-gen3-cmt1";
+                        reg = <0 0xe6148000 0 0x1004>;
+                        interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 300>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+                        resets = <&cpg 300>;
+                        status = "disabled";
+                };
+
                 cpg: clock-controller@e6150000 {
                         compatible = "renesas,r8a77980-cpg-mssr";
                         reg = <0 0xe6150000 0 0x1000>;
@@ -418,6 +514,16 @@
                         status = "disabled";
                 };
 
+                pcie_phy: pcie-phy@e65d0000 {
+                        compatible = "renesas,r8a77980-pcie-phy";
+                        reg = <0 0xe65d0000 0 0x8000>;
+                        #phy-cells = <0>;
+                        clocks = <&cpg CPG_MOD 319>;
+                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+                        resets = <&cpg 319>;
+                        status = "disabled";
+                };
+
                 canfd: can@e66c0000 {
                         compatible = "renesas,r8a77980-canfd",
                                      "renesas,rcar-gen3-canfd";
@@ -443,69 +549,6 @@
                         };
                 };
 
-                ipmmu_ds1: mmu@e7740000 {
-                        compatible = "renesas,ipmmu-r8a77980";
-                        reg = <0 0xe7740000 0 0x1000>;
-                        renesas,ipmmu-main = <&ipmmu_mm 0>;
-                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
-                        #iommu-cells = <1>;
-                };
-
-                ipmmu_vip0: mmu@e7b00000 {
-                        compatible = "renesas,ipmmu-r8a77980";
-                        reg = <0 0xe7b00000 0 0x1000>;
-                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
-                        #iommu-cells = <1>;
-                };
-
-                ipmmu_vip1: mmu@e7960000 {
-                        compatible = "renesas,ipmmu-r8a77980";
-                        reg = <0 0xe7960000 0 0x1000>;
-                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
-                        #iommu-cells = <1>;
-                };
-
-                ipmmu_ir: mmu@ff8b0000 {
-                        compatible = "renesas,ipmmu-r8a77980";
-                        reg = <0 0xff8b0000 0 0x1000>;
-                        renesas,ipmmu-main = <&ipmmu_mm 3>;
-                        power-domains = <&sysc R8A77980_PD_A3IR>;
-                        #iommu-cells = <1>;
-                };
-
-                ipmmu_mm: mmu@e67b0000 {
-                        compatible = "renesas,ipmmu-r8a77980";
-                        reg = <0 0xe67b0000 0 0x1000>;
-                        interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
-                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
-                        #iommu-cells = <1>;
-                };
-
-                ipmmu_rt: mmu@ffc80000 {
-                        compatible = "renesas,ipmmu-r8a77980";
-                        reg = <0 0xffc80000 0 0x1000>;
-                        renesas,ipmmu-main = <&ipmmu_mm 10>;
-                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
-                        #iommu-cells = <1>;
-                };
-
-                ipmmu_vc0: mmu@fe6b0000 {
-                        compatible = "renesas,ipmmu-r8a77980";
-                        reg = <0 0xfe6b0000 0 0x1000>;
-                        renesas,ipmmu-main = <&ipmmu_mm 12>;
-                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
-                        #iommu-cells = <1>;
-                };
-
-                ipmmu_vi0: mmu@febd0000 {
-                        compatible = "renesas,ipmmu-r8a77980";
-                        reg = <0 0xfebd0000 0 0x1000>;
-                        renesas,ipmmu-main = <&ipmmu_mm 14>;
-                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
-                        #iommu-cells = <1>;
-                };
-
                 avb: ethernet@e6800000 {
                         compatible = "renesas,etheravb-r8a77980",
                                      "renesas,etheravb-rcar-gen3";
@@ -623,6 +666,313 @@
                         status = "disabled";
                 };
 
+                tpu: pwm@e6e80000 {
+                        compatible = "renesas,tpu-r8a77980", "renesas,tpu";
+                        reg = <0 0xe6e80000 0 0x148>;
+                        interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 304>;
+                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+                        resets = <&cpg 304>;
+                        #pwm-cells = <3>;
+                        status = "disabled";
+                };
+
+                vin0: video@e6ef0000 {
+                        compatible = "renesas,vin-r8a77980";
+                        reg = <0 0xe6ef0000 0 0x1000>;
+                        interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 811>;
+                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+                        resets = <&cpg 811>;
+                        status = "disabled";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@1 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+
+                                        reg = <1>;
+
+                                        vin0csi40: endpoint@2 {
+                                                reg = <2>;
+                                                remote-endpoint = <&csi40vin0>;
+                                        };
+                                };
+                        };
+                };
+
+                vin1: video@e6ef1000 {
+                        compatible = "renesas,vin-r8a77980";
+                        reg = <0 0xe6ef1000 0 0x1000>;
+                        interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 810>;
+                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+                        status = "disabled";
+                        resets = <&cpg 810>;
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@1 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+
+                                        reg = <1>;
+
+                                        vin1csi40: endpoint@2 {
+                                                reg = <2>;
+                                                remote-endpoint = <&csi40vin1>;
+                                        };
+                                };
+                        };
+                };
+
+                vin2: video@e6ef2000 {
+                        compatible = "renesas,vin-r8a77980";
+                        reg = <0 0xe6ef2000 0 0x1000>;
+                        interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 809>;
+                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+                        resets = <&cpg 809>;
+                        status = "disabled";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@1 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+
+                                        reg = <1>;
+
+                                        vin2csi40: endpoint@2 {
+                                                reg = <2>;
+                                                remote-endpoint = <&csi40vin2>;
+                                        };
+                                };
+                        };
+                };
+
+                vin3: video@e6ef3000 {
+                        compatible = "renesas,vin-r8a77980";
+                        reg = <0 0xe6ef3000 0 0x1000>;
+                        interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 808>;
+                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+                        resets = <&cpg 808>;
+                        status = "disabled";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@1 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+
+                                        reg = <1>;
+
+                                        vin3csi40: endpoint@2 {
+                                                reg = <2>;
+                                                remote-endpoint = <&csi40vin3>;
+                                        };
+                                };
+                        };
+                };
+
+                vin4: video@e6ef4000 {
+                        compatible = "renesas,vin-r8a77980";
+                        reg = <0 0xe6ef4000 0 0x1000>;
+                        interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 807>;
+                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+                        resets = <&cpg 807>;
+                        status = "disabled";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@1 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+
+                                        reg = <1>;
+
+                                        vin4csi41: endpoint@2 {
+                                                reg = <2>;
+                                                remote-endpoint = <&csi41vin4>;
+                                        };
+                                };
+                        };
+                };
+
+                vin5: video@e6ef5000 {
+                        compatible = "renesas,vin-r8a77980";
+                        reg = <0 0xe6ef5000 0 0x1000>;
+                        interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 806>;
+                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+                        resets = <&cpg 806>;
+                        status = "disabled";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@1 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+
+                                        reg = <1>;
+
+                                        vin5csi41: endpoint@2 {
+                                                reg = <2>;
+                                                remote-endpoint = <&csi41vin5>;
+                                        };
+                                };
+                        };
+                };
+
+                vin6: video@e6ef6000 {
+                        compatible = "renesas,vin-r8a77980";
+                        reg = <0 0xe6ef6000 0 0x1000>;
+                        interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 805>;
+                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+                        resets = <&cpg 805>;
+                        status = "disabled";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@1 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+
+                                        reg = <1>;
+
+                                        vin6csi41: endpoint@2 {
+                                                reg = <2>;
+                                                remote-endpoint = <&csi41vin6>;
+                                        };
+                                };
+                        };
+                };
+
+                vin7: video@e6ef7000 {
+                        compatible = "renesas,vin-r8a77980";
+                        reg = <0 0xe6ef7000 0 0x1000>;
+                        interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 804>;
+                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+                        resets = <&cpg 804>;
+                        status = "disabled";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@1 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+
+                                        reg = <1>;
+
+                                        vin7csi41: endpoint@2 {
+                                                reg = <2>;
+                                                remote-endpoint = <&csi41vin7>;
+                                        };
+                                };
+                        };
+                };
+
+                vin8: video@e6ef8000 {
+                        compatible = "renesas,vin-r8a77980";
+                        reg = <0 0xe6ef8000 0 0x1000>;
+                        interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 628>;
+                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+                        resets = <&cpg 628>;
+                        status = "disabled";
+                };
+
+                vin9: video@e6ef9000 {
+                        compatible = "renesas,vin-r8a77980";
+                        reg = <0 0xe6ef9000 0 0x1000>;
+                        interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 627>;
+                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+                        resets = <&cpg 627>;
+                        status = "disabled";
+                };
+
+                vin10: video@e6efa000 {
+                        compatible = "renesas,vin-r8a77980";
+                        reg = <0 0xe6efa000 0 0x1000>;
+                        interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 625>;
+                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+                        resets = <&cpg 625>;
+                        status = "disabled";
+                };
+
+                vin11: video@e6efb000 {
+                        compatible = "renesas,vin-r8a77980";
+                        reg = <0 0xe6efb000 0 0x1000>;
+                        interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 618>;
+                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+                        resets = <&cpg 618>;
+                        status = "disabled";
+                };
+
+                vin12: video@e6efc000 {
+                        compatible = "renesas,vin-r8a77980";
+                        reg = <0 0xe6efc000 0 0x1000>;
+                        interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 612>;
+                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+                        resets = <&cpg 612>;
+                        status = "disabled";
+                };
+
+                vin13: video@e6efd000 {
+                        compatible = "renesas,vin-r8a77980";
+                        reg = <0 0xe6efd000 0 0x1000>;
+                        interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 608>;
+                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+                        resets = <&cpg 608>;
+                        status = "disabled";
+                };
+
+                vin14: video@e6efe000 {
+                        compatible = "renesas,vin-r8a77980";
+                        reg = <0 0xe6efe000 0 0x1000>;
+                        interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 605>;
+                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+                        resets = <&cpg 605>;
+                        status = "disabled";
+                };
+
+                vin15: video@e6eff000 {
+                        compatible = "renesas,vin-r8a77980";
+                        reg = <0 0xe6eff000 0 0x1000>;
+                        interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 604>;
+                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+                        resets = <&cpg 604>;
+                        status = "disabled";
+                };
+
                 dmac1: dma-controller@e7300000 {
                         compatible = "renesas,dmac-r8a77980",
                                      "renesas,rcar-dmac";
@@ -655,6 +1005,14 @@
                         resets = <&cpg 218>;
                         #dma-cells = <1>;
                         dma-channels = <16>;
+                        iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
+                               <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
+                               <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
+                               <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
+                               <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
+                               <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
+                               <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
+                               <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
                 };
 
                 dmac2: dma-controller@e7310000 {
@@ -689,6 +1047,14 @@
                         resets = <&cpg 217>;
                         #dma-cells = <1>;
                         dma-channels = <16>;
+                        iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
+                               <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
+                               <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
+                               <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
+                               <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
+                               <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
+                               <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
+                               <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
                 };
 
                 gether: ethernet@e7400000 {
@@ -703,6 +1069,69 @@
                         status = "disabled";
                 };
 
+                ipmmu_ds1: mmu@e7740000 {
+                        compatible = "renesas,ipmmu-r8a77980";
+                        reg = <0 0xe7740000 0 0x1000>;
+                        renesas,ipmmu-main = <&ipmmu_mm 0>;
+                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+                        #iommu-cells = <1>;
+                };
+
+                ipmmu_ir: mmu@ff8b0000 {
+                        compatible = "renesas,ipmmu-r8a77980";
+                        reg = <0 0xff8b0000 0 0x1000>;
+                        renesas,ipmmu-main = <&ipmmu_mm 3>;
+                        power-domains = <&sysc R8A77980_PD_A3IR>;
+                        #iommu-cells = <1>;
+                };
+
+                ipmmu_mm: mmu@e67b0000 {
+                        compatible = "renesas,ipmmu-r8a77980";
+                        reg = <0 0xe67b0000 0 0x1000>;
+                        interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+                        #iommu-cells = <1>;
+                };
+
+                ipmmu_rt: mmu@ffc80000 {
+                        compatible = "renesas,ipmmu-r8a77980";
+                        reg = <0 0xffc80000 0 0x1000>;
+                        renesas,ipmmu-main = <&ipmmu_mm 10>;
+                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+                        #iommu-cells = <1>;
+                };
+
+                ipmmu_vc0: mmu@fe6b0000 {
+                        compatible = "renesas,ipmmu-r8a77980";
+                        reg = <0 0xfe6b0000 0 0x1000>;
+                        renesas,ipmmu-main = <&ipmmu_mm 12>;
+                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+                        #iommu-cells = <1>;
+                };
+
+                ipmmu_vi0: mmu@febd0000 {
+                        compatible = "renesas,ipmmu-r8a77980";
+                        reg = <0 0xfebd0000 0 0x1000>;
+                        renesas,ipmmu-main = <&ipmmu_mm 14>;
+                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+                        #iommu-cells = <1>;
+                };
+
+                ipmmu_vip0: mmu@e7b00000 {
+                        compatible = "renesas,ipmmu-r8a77980";
+                        reg = <0 0xe7b00000 0 0x1000>;
+                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+                        #iommu-cells = <1>;
+                };
+
+                ipmmu_vip1: mmu@e7960000 {
+                        compatible = "renesas,ipmmu-r8a77980";
+                        reg = <0 0xe7960000 0 0x1000>;
+                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+                        #iommu-cells = <1>;
+                };
+
                 mmc0: mmc@ee140000 {
                         compatible = "renesas,sdhi-r8a77980",
                                      "renesas,rcar-gen3-sdhi";
@@ -732,6 +1161,38 @@
                         resets = <&cpg 408>;
                 };
 
+                pciec: pcie@fe000000 {
+                        compatible = "renesas,pcie-r8a77980",
+                                     "renesas,pcie-rcar-gen3";
+                        reg = <0 0xfe000000 0 0x80000>;
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        bus-range = <0x00 0xff>;
+                        device_type = "pci";
+                        ranges = <
+                                0x01000000 0 0x00000000 0 0xfe100000 0 0x0100000
+                                0x02000000 0 0xfe200000 0 0xfe200000 0 0x0200000
+                                0x02000000 0 0x30000000 0 0x30000000 0 0x8000000
+                                0x42000000 0 0x38000000 0 0x38000000 0 0x8000000
+                        >;
+                        dma-ranges = <0x42000000 0 0x40000000 0 0x40000000
+                                      0 0x80000000>;
+                        interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+                        #interrupt-cells = <1>;
+                        interrupt-map-mask = <0 0 0 0>;
+                        interrupt-map = <0 0 0 0 &gic GIC_SPI 148
+                                         IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
+                        clock-names = "pcie", "pcie_bus";
+                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+                        resets = <&cpg 319>;
+                        phys = <&pcie_phy>;
+                        phy-names = "pcie";
+                        status = "disabled";
+                };
+
                 vspd0: vsp@fea20000 {
                         compatible = "renesas,vsp2";
                         reg = <0 0xfea20000 0 0x5000>;
@@ -750,6 +1211,84 @@
                         resets = <&cpg 603>;
                 };
 
+                csi40: csi2@feaa0000 {
+                        compatible = "renesas,r8a77980-csi2";
+                        reg = <0 0xfeaa0000 0 0x10000>;
+                        interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 716>;
+                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+                        resets = <&cpg 716>;
+                        status = "disabled";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@1 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+
+                                        reg = <1>;
+
+                                        csi40vin0: endpoint@0 {
+                                                reg = <0>;
+                                                remote-endpoint = <&vin0csi40>;
+                                        };
+                                        csi40vin1: endpoint@1 {
+                                                reg = <1>;
+                                                remote-endpoint = <&vin1csi40>;
+                                        };
+                                        csi40vin2: endpoint@2 {
+                                                reg = <2>;
+                                                remote-endpoint = <&vin2csi40>;
+                                        };
+                                        csi40vin3: endpoint@3 {
+                                                reg = <3>;
+                                                remote-endpoint = <&vin3csi40>;
+                                        };
+                                };
+                        };
+                };
+
+                csi41: csi2@feab0000 {
+                        compatible = "renesas,r8a77980-csi2";
+                        reg = <0 0xfeab0000 0 0x10000>;
+                        interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 715>;
+                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+                        resets = <&cpg 715>;
+                        status = "disabled";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@1 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+
+                                        reg = <1>;
+
+                                        csi41vin4: endpoint@0 {
+                                                reg = <0>;
+                                                remote-endpoint = <&vin4csi41>;
+                                        };
+                                        csi41vin5: endpoint@1 {
+                                                reg = <1>;
+                                                remote-endpoint = <&vin5csi41>;
+                                        };
+                                        csi41vin6: endpoint@2 {
+                                                reg = <2>;
+                                                remote-endpoint = <&vin6csi41>;
+                                        };
+                                        csi41vin7: endpoint@3 {
+                                                reg = <3>;
+                                                remote-endpoint = <&vin7csi41>;
+                                        };
+                                };
+                        };
+                };
+
                 du: display@feb00000 {
                         compatible = "renesas,du-r8a77980",
                                      "renesas,du-r8a77970";
diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
index 2bc3a4884b00..f342dd85b152 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
@@ -28,6 +28,111 @@
                 /* first 128MB is reserved for secure area. */
                 reg = <0x0 0x48000000 0x0 0x38000000>;
         };
+
+        cvbs-in {
+                compatible = "composite-video-connector";
+                label = "CVBS IN";
+
+                port {
+                        cvbs_con: endpoint {
+                                remote-endpoint = <&adv7482_ain7>;
+                        };
+                };
+        };
+
+        hdmi-in {
+                compatible = "hdmi-connector";
+                label = "HDMI IN";
+                type = "a";
+
+                port {
+                        hdmi_in_con: endpoint {
+                                remote-endpoint = <&adv7482_hdmi>;
+                        };
+                };
+        };
+
+        hdmi-out {
+                compatible = "hdmi-connector";
+                type = "a";
+
+                port {
+                        hdmi_con_out: endpoint {
+                                remote-endpoint = <&adv7511_out>;
+                        };
+                };
+        };
+
+        lvds-decoder {
+                compatible = "thine,thc63lvd1024";
+                vcc-supply = <&reg_3p3v>;
+
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@0 {
+                                reg = <0>;
+                                thc63lvd1024_in: endpoint {
+                                        remote-endpoint = <&lvds0_out>;
+                                };
+                        };
+
+                        port@2 {
+                                reg = <2>;
+                                thc63lvd1024_out: endpoint {
+                                        remote-endpoint = <&adv7511_in>;
+                                };
+                        };
+                };
+        };
+
+        vga {
+                compatible = "vga-connector";
+
+                port {
+                        vga_in: endpoint {
+                                remote-endpoint = <&adv7123_out>;
+                        };
+                };
+        };
+
+        vga-encoder {
+                compatible = "adi,adv7123";
+
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@0 {
+                                reg = <0>;
+                                adv7123_in: endpoint {
+                                        remote-endpoint = <&du_out_rgb>;
+                                };
+                        };
+                        port@1 {
+                                reg = <1>;
+                                adv7123_out: endpoint {
+                                        remote-endpoint = <&vga_in>;
+                                };
+                        };
+                };
+        };
+
+        reg_3p3v: regulator1 {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-3.3V";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-boot-on;
+                regulator-always-on;
+        };
+
+        x13_clk: x13 {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <74250000>;
+        };
 };
 
 &avb {
@@ -47,6 +152,41 @@
         };
 };
 
+&csi40 {
+        status = "okay";
+
+        ports {
+                port@0 {
+                        reg = <0>;
+
+                        csi40_in: endpoint {
+                                clock-lanes = <0>;
+                                data-lanes = <1 2>;
+                                remote-endpoint = <&adv7482_txa>;
+                        };
+                };
+        };
+};
+
+&du {
+        pinctrl-0 = <&du_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+
+        clocks = <&cpg CPG_MOD 724>,
+                 <&cpg CPG_MOD 723>,
+                 <&x13_clk>;
+        clock-names = "du.0", "du.1", "dclkin.0";
+
+        ports {
+                port@0 {
+                        endpoint {
+                                remote-endpoint = <&adv7123_in>;
+                        };
+                };
+        };
+};
+
 &ehci0 {
         status = "okay";
 };
@@ -55,6 +195,105 @@
         clock-frequency = <48000000>;
 };
 
+&i2c0 {
+        status = "okay";
+
+        hdmi-encoder@39 {
+                compatible = "adi,adv7511w";
+                reg = <0x39>;
+                interrupt-parent = <&gpio1>;
+                interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+
+                adi,input-depth = <8>;
+                adi,input-colorspace = "rgb";
+                adi,input-clock = "1x";
+                adi,input-style = <1>;
+                adi,input-justification = "evenly";
+
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@0 {
+                                reg = <0>;
+                                adv7511_in: endpoint {
+                                        remote-endpoint = <&thc63lvd1024_out>;
+                                };
+                        };
+
+                        port@1 {
+                                reg = <1>;
+                                adv7511_out: endpoint {
+                                        remote-endpoint = <&hdmi_con_out>;
+                                };
+                        };
+                };
+        };
+
+        video-receiver@70 {
+                compatible = "adi,adv7482";
+                reg = <0x70>;
+
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                interrupt-parent = <&gpio0>;
+                interrupt-names = "intrq1", "intrq2";
+                interrupts = <7 IRQ_TYPE_LEVEL_LOW>,
+                             <17 IRQ_TYPE_LEVEL_LOW>;
+
+                port@7 {
+                        reg = <7>;
+
+                        adv7482_ain7: endpoint {
+                                remote-endpoint = <&cvbs_con>;
+                        };
+                };
+
+                port@8 {
+                        reg = <8>;
+
+                        adv7482_hdmi: endpoint {
+                                remote-endpoint = <&hdmi_in_con>;
+                        };
+                };
+
+                port@a {
+                        reg = <0xa>;
+
+                        adv7482_txa: endpoint {
+                                clock-lanes = <0>;
+                                data-lanes = <1 2>;
+                                remote-endpoint = <&csi40_in>;
+                        };
+                };
+        };
+};
+
+&lvds0 {
+        status = "okay";
+
+        clocks = <&cpg CPG_MOD 727>,
+                 <&x13_clk>,
+                 <&extal_clk>;
+        clock-names = "fck", "dclkin.0", "extal";
+
+        ports {
+                port@1 {
+                        lvds0_out: endpoint {
+                                remote-endpoint = <&thc63lvd1024_in>;
+                        };
+                };
+        };
+};
+
+&lvds1 {
+        clocks = <&cpg CPG_MOD 727>,
+                 <&x13_clk>,
+                 <&extal_clk>;
+        clock-names = "fck", "dclkin.0", "extal";
+};
+
 &ohci0 {
         status = "okay";
 };
@@ -67,6 +306,21 @@
                 };
         };
 
+        du_pins: du {
+                groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
+                function = "du";
+        };
+
+        pwm3_pins: pwm3 {
+                groups = "pwm3_b";
+                function = "pwm3";
+        };
+
+        pwm5_pins: pwm5 {
+                groups = "pwm5_a";
+                function = "pwm5";
+        };
+
         usb0_pins: usb {
                 groups = "usb0_b";
                 function = "usb0";
@@ -78,6 +332,20 @@
         };
 };
 
+&pwm3 {
+        pinctrl-0 = <&pwm3_pins>;
+        pinctrl-names = "default";
+
+        status = "okay";
+};
+
+&pwm5 {
+        pinctrl-0 = <&pwm5_pins>;
+        pinctrl-names = "default";
+
+        status = "okay";
+};
+
 &rwdt {
         timeout-sec = <60>;
         status = "okay";
@@ -94,6 +362,10 @@
         status = "okay";
 };
 
+&vin4 {
+        status = "okay";
+};
+
 &xhci0 {
         pinctrl-0 = <&usb30_pins>;
         pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index ae89260baad9..9509dc05665f 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -1,11 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
- * Device Tree Source for the r8a77990 SoC
+ * Device Tree Source for the R-Car E3 (R8A77990) SoC
  *
  * Copyright (C) 2018 Renesas Electronics Corp.
  */
 
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
+#include <dt-bindings/clock/r8a77990-cpg-mssr.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/power/r8a77990-sysc.h>
 
@@ -14,6 +14,17 @@
         #address-cells = <2>;
         #size-cells = <2>;
 
+        aliases {
+                i2c0 = &i2c0;
+                i2c1 = &i2c1;
+                i2c2 = &i2c2;
+                i2c3 = &i2c3;
+                i2c4 = &i2c4;
+                i2c5 = &i2c5;
+                i2c6 = &i2c6;
+                i2c7 = &i2c7;
+        };
+
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -22,7 +33,7 @@
                         compatible = "arm,cortex-a53", "arm,armv8";
                         reg = <0>;
                         device_type = "cpu";
-                        power-domains = <&sysc 5>;
+                        power-domains = <&sysc R8A77990_PD_CA53_CPU0>;
                         next-level-cache = <&L2_CA53>;
                         enable-method = "psci";
                 };
@@ -31,14 +42,14 @@
                         compatible = "arm,cortex-a53", "arm,armv8";
                         reg = <1>;
                         device_type = "cpu";
-                        power-domains = <&sysc 6>;
+                        power-domains = <&sysc R8A77990_PD_CA53_CPU1>;
                         next-level-cache = <&L2_CA53>;
                         enable-method = "psci";
                 };
 
                 L2_CA53: cache-controller-0 {
                         compatible = "cache";
-                        power-domains = <&sysc 21>;
+                        power-domains = <&sysc R8A77990_PD_CA53_SCU>;
                         cache-unified;
                         cache-level = <2>;
                 };
@@ -63,6 +74,13 @@
                 method = "smc";
         };
 
+        /* External SCIF clock - to be overridden by boards that provide it */
+        scif_clk: scif {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+
         soc: soc {
                 compatible = "simple-bus";
                 interrupt-parent = <&gic>;
@@ -75,7 +93,7 @@
                                      "renesas,rcar-gen3-wdt";
                         reg = <0 0xe6020000 0 0x0c>;
                         clocks = <&cpg CPG_MOD 402>;
-                        power-domains = <&sysc 32>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
                         resets = <&cpg 402>;
                         status = "disabled";
                 };
@@ -91,7 +109,7 @@
                         #interrupt-cells = <2>;
                         interrupt-controller;
                         clocks = <&cpg CPG_MOD 912>;
-                        power-domains = <&sysc 32>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
                         resets = <&cpg 912>;
                 };
 
@@ -106,7 +124,7 @@
                         #interrupt-cells = <2>;
                         interrupt-controller;
                         clocks = <&cpg CPG_MOD 911>;
-                        power-domains = <&sysc 32>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
                         resets = <&cpg 911>;
                 };
 
@@ -121,7 +139,7 @@
                         #interrupt-cells = <2>;
                         interrupt-controller;
                         clocks = <&cpg CPG_MOD 910>;
-                        power-domains = <&sysc 32>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
                         resets = <&cpg 910>;
                 };
 
@@ -136,7 +154,7 @@
                         #interrupt-cells = <2>;
                         interrupt-controller;
                         clocks = <&cpg CPG_MOD 909>;
-                        power-domains = <&sysc 32>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
                         resets = <&cpg 909>;
                 };
 
@@ -151,7 +169,7 @@
                         #interrupt-cells = <2>;
                         interrupt-controller;
                         clocks = <&cpg CPG_MOD 908>;
-                        power-domains = <&sysc 32>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
                         resets = <&cpg 908>;
                 };
 
@@ -166,7 +184,7 @@
                         #interrupt-cells = <2>;
                         interrupt-controller;
                         clocks = <&cpg CPG_MOD 907>;
-                        power-domains = <&sysc 32>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
                         resets = <&cpg 907>;
                 };
 
@@ -181,10 +199,122 @@
                         #interrupt-cells = <2>;
                         interrupt-controller;
                         clocks = <&cpg CPG_MOD 906>;
-                        power-domains = <&sysc 32>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
                         resets = <&cpg 906>;
                 };
 
+                i2c0: i2c@e6500000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a77990",
+                                     "renesas,rcar-gen3-i2c";
+                        reg = <0 0xe6500000 0 0x40>;
+                        interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 931>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                        resets = <&cpg 931>;
+                        i2c-scl-internal-delay-ns = <110>;
+                        status = "disabled";
+                };
+
+                i2c1: i2c@e6508000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a77990",
+                                     "renesas,rcar-gen3-i2c";
+                        reg = <0 0xe6508000 0 0x40>;
+                        interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 930>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                        resets = <&cpg 930>;
+                        i2c-scl-internal-delay-ns = <6>;
+                        status = "disabled";
+                };
+
+                i2c2: i2c@e6510000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a77990",
+                                     "renesas,rcar-gen3-i2c";
+                        reg = <0 0xe6510000 0 0x40>;
+                        interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 929>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                        resets = <&cpg 929>;
+                        i2c-scl-internal-delay-ns = <6>;
+                        status = "disabled";
+                };
+
+                i2c3: i2c@e66d0000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a77990",
+                                     "renesas,rcar-gen3-i2c";
+                        reg = <0 0xe66d0000 0 0x40>;
+                        interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 928>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                        resets = <&cpg 928>;
+                        i2c-scl-internal-delay-ns = <110>;
+                        status = "disabled";
+                };
+
+                i2c4: i2c@e66d8000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a77990",
+                                     "renesas,rcar-gen3-i2c";
+                        reg = <0 0xe66d8000 0 0x40>;
+                        interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 927>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                        resets = <&cpg 927>;
+                        i2c-scl-internal-delay-ns = <6>;
+                        status = "disabled";
+                };
+
+                i2c5: i2c@e66e0000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a77990",
+                                     "renesas,rcar-gen3-i2c";
+                        reg = <0 0xe66e0000 0 0x40>;
+                        interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 919>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                        resets = <&cpg 919>;
+                        i2c-scl-internal-delay-ns = <6>;
+                        status = "disabled";
+                };
+
+                i2c6: i2c@e66e8000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a77990",
+                                     "renesas,rcar-gen3-i2c";
+                        reg = <0 0xe66e8000 0 0x40>;
+                        interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 918>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                        resets = <&cpg 918>;
+                        i2c-scl-internal-delay-ns = <6>;
+                        status = "disabled";
+                };
+
+                i2c7: i2c@e6690000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a77990",
+                                     "renesas,rcar-gen3-i2c";
+                        reg = <0 0xe6690000 0 0x40>;
+                        interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 1003>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                        resets = <&cpg 1003>;
+                        i2c-scl-internal-delay-ns = <6>;
+                        status = "disabled";
+                };
+
                 pfc: pin-controller@e6060000 {
                         compatible = "renesas,pfc-r8a77990";
                         reg = <0 0xe6060000 0 0x508>;
@@ -211,6 +341,132 @@
                         #power-domain-cells = <1>;
                 };
 
+                dmac0: dma-controller@e6700000 {
+                        compatible = "renesas,dmac-r8a77990",
+                                     "renesas,rcar-dmac";
+                        reg = <0 0xe6700000 0 0x10000>;
+                        interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "error",
+                                        "ch0", "ch1", "ch2", "ch3",
+                                        "ch4", "ch5", "ch6", "ch7",
+                                        "ch8", "ch9", "ch10", "ch11",
+                                        "ch12", "ch13", "ch14", "ch15";
+                        clocks = <&cpg CPG_MOD 219>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                        resets = <&cpg 219>;
+                        #dma-cells = <1>;
+                        dma-channels = <16>;
+                        iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
+                               <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
+                               <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
+                               <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
+                               <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
+                               <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
+                               <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
+                               <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
+                };
+
+                dmac1: dma-controller@e7300000 {
+                        compatible = "renesas,dmac-r8a77990",
+                                     "renesas,rcar-dmac";
+                        reg = <0 0xe7300000 0 0x10000>;
+                        interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "error",
+                                        "ch0", "ch1", "ch2", "ch3",
+                                        "ch4", "ch5", "ch6", "ch7",
+                                        "ch8", "ch9", "ch10", "ch11",
+                                        "ch12", "ch13", "ch14", "ch15";
+                        clocks = <&cpg CPG_MOD 218>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                        resets = <&cpg 218>;
+                        #dma-cells = <1>;
+                        dma-channels = <16>;
+                        iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
+                               <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
+                               <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
+                               <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
+                               <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
+                               <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
+                               <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
+                               <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
+                };
+
+                dmac2: dma-controller@e7310000 {
+                        compatible = "renesas,dmac-r8a77990",
+                                     "renesas,rcar-dmac";
+                        reg = <0 0xe7310000 0 0x10000>;
+                        interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "error",
+                                        "ch0", "ch1", "ch2", "ch3",
+                                        "ch4", "ch5", "ch6", "ch7",
+                                        "ch8", "ch9", "ch10", "ch11",
+                                        "ch12", "ch13", "ch14", "ch15";
+                        clocks = <&cpg CPG_MOD 217>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                        resets = <&cpg 217>;
+                        #dma-cells = <1>;
+                        dma-channels = <16>;
+                        iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
+                               <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
+                               <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
+                               <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
+                               <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
+                               <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
+                               <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
+                               <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
+                };
+
                 ipmmu_ds0: mmu@e6740000 {
                         compatible = "renesas,ipmmu-r8a77990";
                         reg = <0 0xe6740000 0 0x1000>;
@@ -329,7 +585,7 @@
                                           "ch20", "ch21", "ch22", "ch23",
                                           "ch24";
                         clocks = <&cpg CPG_MOD 812>;
-                        power-domains = <&sysc 32>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
                         resets = <&cpg 812>;
                         phy-mode = "rgmii";
                         #address-cells = <1>;
@@ -337,18 +593,191 @@
                         status = "disabled";
                 };
 
+                pwm0: pwm@e6e30000 {
+                        compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
+                        reg = <0 0xe6e30000 0 0x8>;
+                        clocks = <&cpg CPG_MOD 523>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                        resets = <&cpg 523>;
+                        #pwm-cells = <2>;
+                        status = "disabled";
+                };
+
+                pwm1: pwm@e6e31000 {
+                        compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
+                        reg = <0 0xe6e31000 0 0x8>;
+                        clocks = <&cpg CPG_MOD 523>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                        resets = <&cpg 523>;
+                        #pwm-cells = <2>;
+                        status = "disabled";
+                };
+
+                pwm2: pwm@e6e32000 {
+                        compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
+                        reg = <0 0xe6e32000 0 0x8>;
+                        clocks = <&cpg CPG_MOD 523>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                        resets = <&cpg 523>;
+                        #pwm-cells = <2>;
+                        status = "disabled";
+                };
+
+                pwm3: pwm@e6e33000 {
+                        compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
+                        reg = <0 0xe6e33000 0 0x8>;
+                        clocks = <&cpg CPG_MOD 523>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                        resets = <&cpg 523>;
+                        #pwm-cells = <2>;
+                        status = "disabled";
+                };
+
+                pwm4: pwm@e6e34000 {
+                        compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
+                        reg = <0 0xe6e34000 0 0x8>;
+                        clocks = <&cpg CPG_MOD 523>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                        resets = <&cpg 523>;
+                        #pwm-cells = <2>;
+                        status = "disabled";
+                };
+
+                pwm5: pwm@e6e35000 {
+                        compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
+                        reg = <0 0xe6e35000 0 0x8>;
+                        clocks = <&cpg CPG_MOD 523>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                        resets = <&cpg 523>;
+                        #pwm-cells = <2>;
+                        status = "disabled";
+                };
+
+                pwm6: pwm@e6e36000 {
+                        compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
+                        reg = <0 0xe6e36000 0 0x8>;
+                        clocks = <&cpg CPG_MOD 523>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                        resets = <&cpg 523>;
+                        #pwm-cells = <2>;
+                        status = "disabled";
+                };
+
                 scif2: serial@e6e88000 {
                         compatible = "renesas,scif-r8a77990",
                                      "renesas,rcar-gen3-scif", "renesas,scif";
                         reg = <0 0xe6e88000 0 64>;
                         interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 310>;
-                        clock-names = "fck";
-                        power-domains = <&sysc 32>;
+                        clocks = <&cpg CPG_MOD 310>,
+                                 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
                         resets = <&cpg 310>;
                         status = "disabled";
                 };
 
+                msiof0: spi@e6e90000 {
+                        compatible = "renesas,msiof-r8a77990",
+                                     "renesas,rcar-gen3-msiof";
+                        reg = <0 0xe6e90000 0 0x0064>;
+                        interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 211>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                        resets = <&cpg 211>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                msiof1: spi@e6ea0000 {
+                        compatible = "renesas,msiof-r8a77990",
+                                     "renesas,rcar-gen3-msiof";
+                        reg = <0 0xe6ea0000 0 0x0064>;
+                        interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 210>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                        resets = <&cpg 210>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                msiof2: spi@e6c00000 {
+                        compatible = "renesas,msiof-r8a77990",
+                                     "renesas,rcar-gen3-msiof";
+                        reg = <0 0xe6c00000 0 0x0064>;
+                        interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 209>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                        resets = <&cpg 209>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                msiof3: spi@e6c10000 {
+                        compatible = "renesas,msiof-r8a77990",
+                                     "renesas,rcar-gen3-msiof";
+                        reg = <0 0xe6c10000 0 0x0064>;
+                        interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 208>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                        resets = <&cpg 208>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                vin4: video@e6ef4000 {
+                        compatible = "renesas,vin-r8a77990";
+                        reg = <0 0xe6ef4000 0 0x1000>;
+                        interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 807>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                        resets = <&cpg 807>;
+                        renesas,id = <4>;
+                        status = "disabled";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@1 {
+                                        reg = <1>;
+
+                                        vin4csi40: endpoint {
+                                                remote-endpoint= <&csi40vin4>;
+                                        };
+                                };
+                        };
+                };
+
+                vin5: video@e6ef5000 {
+                        compatible = "renesas,vin-r8a77990";
+                        reg = <0 0xe6ef5000 0 0x1000>;
+                        interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 806>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                        resets = <&cpg 806>;
+                        renesas,id = <5>;
+                        status = "disabled";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@1 {
+                                        reg = <1>;
+
+                                        vin5csi40: endpoint {
+                                                remote-endpoint= <&csi40vin5>;
+                                        };
+                                };
+                        };
+                };
+
                 xhci0: usb@ee000000 {
                         compatible = "renesas,xhci-r8a77990",
                                      "renesas,rcar-gen3-xhci";
@@ -364,11 +793,11 @@
                         compatible = "generic-ohci";
                         reg = <0 0xee080000 0 0x100>;
                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 703>;
+                        clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
                         phys = <&usb2_phy0>;
                         phy-names = "usb";
-                        power-domains = <&sysc 32>;
-                        resets = <&cpg 703>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                        resets = <&cpg 703>, <&cpg 704>;
                         status = "disabled";
                 };
 
@@ -376,12 +805,12 @@
                         compatible = "generic-ehci";
                         reg = <0 0xee080100 0 0x100>;
                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 703>;
+                        clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
                         phys = <&usb2_phy0>;
                         phy-names = "usb";
                         companion = <&ohci0>;
-                        power-domains = <&sysc 32>;
-                        resets = <&cpg 703>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                        resets = <&cpg 703>, <&cpg 704>;
                         status = "disabled";
                 };
 
@@ -390,9 +819,9 @@
                                      "renesas,rcar-gen3-usb2-phy";
                         reg = <0 0xee080200 0 0x700>;
                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 703>;
-                        power-domains = <&sysc 32>;
-                        resets = <&cpg 703>;
+                        clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                        resets = <&cpg 703>, <&cpg 704>;
                         #phy-cells = <0>;
                         status = "disabled";
                 };
@@ -410,10 +839,208 @@
                                         (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
                         clocks = <&cpg CPG_MOD 408>;
                         clock-names = "clk";
-                        power-domains = <&sysc 32>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
                         resets = <&cpg 408>;
                 };
 
+                vspb0: vsp@fe960000 {
+                        compatible = "renesas,vsp2";
+                        reg = <0 0xfe960000 0 0x8000>;
+                        interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 626>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                        resets = <&cpg 626>;
+                        renesas,fcp = <&fcpvb0>;
+                };
+
+                fcpvb0: fcp@fe96f000 {
+                        compatible = "renesas,fcpv";
+                        reg = <0 0xfe96f000 0 0x200>;
+                        clocks = <&cpg CPG_MOD 607>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                        resets = <&cpg 607>;
+                        iommus = <&ipmmu_vp0 5>;
+                };
+
+                vspi0: vsp@fe9a0000 {
+                        compatible = "renesas,vsp2";
+                        reg = <0 0xfe9a0000 0 0x8000>;
+                        interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 631>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                        resets = <&cpg 631>;
+                        renesas,fcp = <&fcpvi0>;
+                };
+
+                fcpvi0: fcp@fe9af000 {
+                        compatible = "renesas,fcpv";
+                        reg = <0 0xfe9af000 0 0x200>;
+                        clocks = <&cpg CPG_MOD 611>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                        resets = <&cpg 611>;
+                        iommus = <&ipmmu_vp0 8>;
+                };
+
+                vspd0: vsp@fea20000 {
+                        compatible = "renesas,vsp2";
+                        reg = <0 0xfea20000 0 0x7000>;
+                        interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 623>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                        resets = <&cpg 623>;
+                        renesas,fcp = <&fcpvd0>;
+                };
+
+                fcpvd0: fcp@fea27000 {
+                        compatible = "renesas,fcpv";
+                        reg = <0 0xfea27000 0 0x200>;
+                        clocks = <&cpg CPG_MOD 603>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                        resets = <&cpg 603>;
+                        iommus = <&ipmmu_vi0 8>;
+                };
+
+                vspd1: vsp@fea28000 {
+                        compatible = "renesas,vsp2";
+                        reg = <0 0xfea28000 0 0x7000>;
+                        interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 622>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                        resets = <&cpg 622>;
+                        renesas,fcp = <&fcpvd1>;
+                };
+
+                fcpvd1: fcp@fea2f000 {
+                        compatible = "renesas,fcpv";
+                        reg = <0 0xfea2f000 0 0x200>;
+                        clocks = <&cpg CPG_MOD 602>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                        resets = <&cpg 602>;
+                        iommus = <&ipmmu_vi0 9>;
+                };
+
+                csi40: csi2@feaa0000 {
+                        compatible = "renesas,r8a77990-csi2", "renesas,rcar-gen3-csi2";
+                        reg = <0 0xfeaa0000 0 0x10000>;
+                        interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 716>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                        resets = <&cpg 716>;
+                        status = "disabled";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@1 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+
+                                        reg = <1>;
+
+                                        csi40vin4: endpoint@0 {
+                                                reg = <0>;
+                                                remote-endpoint = <&vin4csi40>;
+                                        };
+                                        csi40vin5: endpoint@1 {
+                                                reg = <1>;
+                                                remote-endpoint = <&vin5csi40>;
+                                        };
+                                };
+                        };
+                };
+
+                du: display@feb00000 {
+                        compatible = "renesas,du-r8a77990";
+                        reg = <0 0xfeb00000 0 0x80000>;
+                        interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 724>,
+                                 <&cpg CPG_MOD 723>;
+                        clock-names = "du.0", "du.1";
+                        vsps = <&vspd0 0 &vspd1 0>;
+                        status = "disabled";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@0 {
+                                        reg = <0>;
+                                        du_out_rgb: endpoint {
+                                        };
+                                };
+
+                                port@1 {
+                                        reg = <1>;
+                                        du_out_lvds0: endpoint {
+                                                remote-endpoint = <&lvds0_in>;
+                                        };
+                                };
+
+                                port@2 {
+                                        reg = <2>;
+                                        du_out_lvds1: endpoint {
+                                                remote-endpoint = <&lvds1_in>;
+                                        };
+                                };
+                        };
+                };
+
+                lvds0: lvds-encoder@feb90000 {
+                        compatible = "renesas,r8a77990-lvds";
+                        reg = <0 0xfeb90000 0 0x20>;
+                        clocks = <&cpg CPG_MOD 727>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                        resets = <&cpg 727>;
+                        status = "disabled";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@0 {
+                                        reg = <0>;
+                                        lvds0_in: endpoint {
+                                                remote-endpoint = <&du_out_lvds0>;
+                                        };
+                                };
+
+                                port@1 {
+                                        reg = <1>;
+                                        lvds0_out: endpoint {
+                                        };
+                                };
+                        };
+                };
+
+                lvds1: lvds-encoder@feb90100 {
+                        compatible = "renesas,r8a77990-lvds";
+                        reg = <0 0xfeb90100 0 0x20>;
+                        clocks = <&cpg CPG_MOD 727>;
+                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+                        resets = <&cpg 726>;
+                        status = "disabled";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@0 {
+                                        reg = <0>;
+                                        lvds1_in: endpoint {
+                                                remote-endpoint = <&du_out_lvds1>;
+                                        };
+                                };
+
+                                port@1 {
+                                        reg = <1>;
+                                        lvds1_out: endpoint {
+                                        };
+                                };
+                        };
+                };
+
                 prr: chipid@fff00044 {
                         compatible = "renesas,prr";
                         reg = <0 0xfff00044 0 4>;
diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
index a8e8f2669d4c..2405eaad0296 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
@@ -2,7 +2,7 @@
 /*
  * Device Tree Source for the Draak board
  *
- * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2016-2018 Renesas Electronics Corp.
  * Copyright (C) 2017 Glider bvba
  */
 
@@ -24,55 +24,58 @@
                 stdout-path = "serial0:115200n8";
         };
 
-        vga {
-                compatible = "vga-connector";
+        composite-in {
+                compatible = "composite-video-connector";
 
                 port {
-                        vga_in: endpoint {
-                                remote-endpoint = <&adv7123_out>;
+                        composite_con_in: endpoint {
+                                remote-endpoint = <&adv7180_in>;
                         };
                 };
         };
 
-        vga-encoder {
-                compatible = "adi,adv7123";
-
-                ports {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
+        hdmi-in {
+                compatible = "hdmi-connector";
+                type = "a";
 
-                        port@0 {
-                                reg = <0>;
-                                adv7123_in: endpoint {
-                                        remote-endpoint = <&du_out_rgb>;
-                                };
-                        };
-                        port@1 {
-                                reg = <1>;
-                                adv7123_out: endpoint {
-                                        remote-endpoint = <&vga_in>;
-                                };
+                port {
+                        hdmi_con_in: endpoint {
+                                remote-endpoint = <&adv7612_in>;
                         };
                 };
         };
 
-        composite-in {
-                compatible = "composite-video-connector";
+        hdmi-out {
+                compatible = "hdmi-connector";
+                type = "a";
 
                 port {
-                        composite_con_in: endpoint {
-                                remote-endpoint = <&adv7180_in>;
+                        hdmi_con_out: endpoint {
+                                remote-endpoint = <&adv7511_out>;
                         };
                 };
         };
 
-        hdmi-in {
-                compatible = "hdmi-connector";
-                type = "a";
+        lvds-decoder {
+                compatible = "thine,thc63lvd1024";
+                vcc-supply = <&reg_3p3v>;
 
-                port {
-                        hdmi_con_in: endpoint {
-                                remote-endpoint = <&adv7612_in>;
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@0 {
+                                reg = <0>;
+                                thc63lvd1024_in: endpoint {
+                                        remote-endpoint = <&lvds0_out>;
+                                };
+                        };
+
+                        port@2 {
+                                reg = <2>;
+                                thc63lvd1024_out: endpoint {
+                                        remote-endpoint = <&adv7511_in>;
+                                };
                         };
                 };
         };
@@ -101,76 +104,86 @@
                 regulator-always-on;
         };
 
-        x12_clk: x12 {
-                compatible = "fixed-clock";
-                #clock-cells = <0>;
-                clock-frequency = <74250000>;
-        };
-};
-
-&extal_clk {
-        clock-frequency = <48000000>;
-};
+        vga {
+                compatible = "vga-connector";
 
-&pfc {
-        avb0_pins: avb {
-                mux {
-                        groups = "avb0_link", "avb0_mdio", "avb0_mii";
-                        function = "avb0";
+                port {
+                        vga_in: endpoint {
+                                remote-endpoint = <&adv7123_out>;
+                        };
                 };
         };
 
-        du_pins: du {
-                groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
-                function = "du";
-        };
+        vga-encoder {
+                compatible = "adi,adv7123";
 
-        i2c0_pins: i2c0 {
-                groups = "i2c0";
-                function = "i2c0";
-        };
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
 
-        i2c1_pins: i2c1 {
-                groups = "i2c1";
-                function = "i2c1";
+                        port@0 {
+                                reg = <0>;
+                                adv7123_in: endpoint {
+                                        remote-endpoint = <&du_out_rgb>;
+                                };
+                        };
+                        port@1 {
+                                reg = <1>;
+                                adv7123_out: endpoint {
+                                        remote-endpoint = <&vga_in>;
+                                };
+                        };
+                };
         };
 
-        pwm0_pins: pwm0 {
-                groups = "pwm0_c";
-                function = "pwm0";
+        x12_clk: x12 {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <74250000>;
         };
+};
 
-        pwm1_pins: pwm1 {
-                groups = "pwm1_c";
-                function = "pwm1";
-        };
+&avb {
+        pinctrl-0 = <&avb0_pins>;
+        pinctrl-names = "default";
+        renesas,no-ether-link;
+        phy-handle = <&phy0>;
+        phy-mode = "rgmii-txid";
+        status = "okay";
 
-        scif2_pins: scif2 {
-                groups = "scif2_data";
-                function = "scif2";
+        phy0: ethernet-phy@0 {
+                rxc-skew-ps = <1500>;
+                reg = <0>;
+                interrupt-parent = <&gpio5>;
+                interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
         };
+};
 
-        sdhi2_pins: sd2 {
-                groups = "mmc_data8", "mmc_ctrl";
-                function = "mmc";
-                power-source = <1800>;
-        };
+&du {
+        pinctrl-0 = <&du_pins>;
+        pinctrl-names = "default";
+        status = "okay";
 
-        sdhi2_pins_uhs: sd2_uhs {
-                groups = "mmc_data8", "mmc_ctrl";
-                function = "mmc";
-                power-source = <1800>;
-        };
+        clocks = <&cpg CPG_MOD 724>,
+                 <&cpg CPG_MOD 723>,
+                 <&x12_clk>;
+        clock-names = "du.0", "du.1", "dclkin.0";
 
-        usb0_pins: usb0 {
-                groups = "usb0";
-                function = "usb0";
+        ports {
+                port@0 {
+                        endpoint {
+                                remote-endpoint = <&adv7123_in>;
+                        };
+                };
         };
+};
 
-        vin4_pins_cvbs: vin4 {
-                groups = "vin4_data8", "vin4_sync", "vin4_clk";
-                function = "vin4";
-        };
+&ehci0 {
+        status = "okay";
+};
+
+&extal_clk {
+        clock-frequency = <48000000>;
 };
 
 &i2c0 {
@@ -178,12 +191,6 @@
         pinctrl-names = "default";
         status = "okay";
 
-        eeprom@50 {
-                compatible = "rohm,br24t01", "atmel,24c01";
-                reg = <0x50>;
-                pagesize = <8>;
-        };
-
         composite-in@20 {
                 compatible = "adi,adv7180cp";
                 reg = <0x20>;
@@ -218,6 +225,43 @@
 
         };
 
+        hdmi-encoder@39 {
+                compatible = "adi,adv7511w";
+                reg = <0x39>, <0x3f>, <0x38>, <0x3c>;
+                reg-names = "main", "edid", "packet", "cec";
+                interrupt-parent = <&gpio1>;
+                interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
+
+                /* Depends on LVDS */
+                max-clock = <135000000>;
+                min-vrefresh = <50>;
+
+                adi,input-depth = <8>;
+                adi,input-colorspace = "rgb";
+                adi,input-clock = "1x";
+                adi,input-style = <1>;
+                adi,input-justification = "evenly";
+
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@0 {
+                                reg = <0>;
+                                adv7511_in: endpoint {
+                                        remote-endpoint = <&thc63lvd1024_out>;
+                                };
+                        };
+
+                        port@1 {
+                                reg = <1>;
+                                adv7511_out: endpoint {
+                                        remote-endpoint = <&hdmi_con_out>;
+                                };
+                        };
+                };
+        };
+
         hdmi-decoder@4c {
                 compatible = "adi,adv7612";
                 reg = <0x4c>;
@@ -254,6 +298,12 @@
                         };
                 };
         };
+
+        eeprom@50 {
+                compatible = "rohm,br24t01", "atmel,24c01";
+                reg = <0x50>;
+                pagesize = <8>;
+        };
 };
 
 &i2c1 {
@@ -262,47 +312,112 @@
         status = "okay";
 };
 
-&du {
-        pinctrl-0 = <&du_pins>;
-        pinctrl-names = "default";
+&lvds0 {
         status = "okay";
 
-        clocks = <&cpg CPG_MOD 724>,
-                 <&cpg CPG_MOD 723>,
-                 <&x12_clk>;
-        clock-names = "du.0", "du.1", "dclkin.0";
+        clocks = <&cpg CPG_MOD 727>,
+                 <&x12_clk>,
+                 <&extal_clk>;
+        clock-names = "fck", "dclkin.0", "extal";
 
         ports {
-                port@0 {
-                        endpoint {
-                                remote-endpoint = <&adv7123_in>;
+                port@1 {
+                        lvds0_out: endpoint {
+                                remote-endpoint = <&thc63lvd1024_in>;
                         };
                 };
         };
 };
 
-&ehci0 {
-        status = "okay";
+&lvds1 {
+        clocks = <&cpg CPG_MOD 727>,
+                 <&x12_clk>,
+                 <&extal_clk>;
+        clock-names = "fck", "dclkin.0", "extal";
 };
 
 &ohci0 {
         status = "okay";
 };
 
-&avb {
-        pinctrl-0 = <&avb0_pins>;
+&pfc {
+        avb0_pins: avb {
+                mux {
+                        groups = "avb0_link", "avb0_mdio", "avb0_mii";
+                        function = "avb0";
+                };
+        };
+
+        du_pins: du {
+                groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
+                function = "du";
+        };
+
+        i2c0_pins: i2c0 {
+                groups = "i2c0";
+                function = "i2c0";
+        };
+
+        i2c1_pins: i2c1 {
+                groups = "i2c1";
+                function = "i2c1";
+        };
+
+        pwm0_pins: pwm0 {
+                groups = "pwm0_c";
+                function = "pwm0";
+        };
+
+        pwm1_pins: pwm1 {
+                groups = "pwm1_c";
+                function = "pwm1";
+        };
+
+        scif2_pins: scif2 {
+                groups = "scif2_data";
+                function = "scif2";
+        };
+
+        sdhi2_pins: sd2 {
+                groups = "mmc_data8", "mmc_ctrl";
+                function = "mmc";
+                power-source = <1800>;
+        };
+
+        sdhi2_pins_uhs: sd2_uhs {
+                groups = "mmc_data8", "mmc_ctrl";
+                function = "mmc";
+                power-source = <1800>;
+        };
+
+        usb0_pins: usb0 {
+                groups = "usb0";
+                function = "usb0";
+        };
+
+        vin4_pins_cvbs: vin4 {
+                groups = "vin4_data8", "vin4_sync", "vin4_clk";
+                function = "vin4";
+        };
+};
+
+&pwm0 {
+        pinctrl-0 = <&pwm0_pins>;
         pinctrl-names = "default";
-        renesas,no-ether-link;
-        phy-handle = <&phy0>;
-        phy-mode = "rgmii-txid";
+
         status = "okay";
+};
 
-        phy0: ethernet-phy@0 {
-                rxc-skew-ps = <1500>;
-                reg = <0>;
-                interrupt-parent = <&gpio5>;
-                interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
-        };
+&pwm1 {
+        pinctrl-0 = <&pwm1_pins>;
+        pinctrl-names = "default";
+
+        status = "okay";
+};
+
+&rwdt {
+        timeout-sec = <60>;
+        status = "okay";
 };
 
 &scif2 {
@@ -333,25 +448,6 @@
         status = "okay";
 };
 
-&pwm0 {
-        pinctrl-0 = <&pwm0_pins>;
-        pinctrl-names = "default";
-
-        status = "okay";
-};
-
-&pwm1 {
-        pinctrl-0 = <&pwm1_pins>;
-        pinctrl-names = "default";
-
-        status = "okay";
-};
-
-&rwdt {
-        timeout-sec = <60>;
-        status = "okay";
-};
-
 &vin4 {
         pinctrl-0 = <&vin4_pins_cvbs>;
         pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index fe77bc43c447..214f4954b321 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source for the r8a77995 SoC
+ * Device Tree Source for the R-Car D3 (R8A77995) SoC
  *
  * Copyright (C) 2016 Renesas Electronics Corp.
  * Copyright (C) 2017 Glider bvba
@@ -391,6 +391,10 @@
                         resets = <&cpg 219>;
                         #dma-cells = <1>;
                         dma-channels = <8>;
+                        iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
+                               <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
+                               <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
+                               <&ipmmu_ds0 6>, <&ipmmu_ds0 7>;
                 };
 
                 dmac1: dma-controller@e7300000 {
@@ -415,6 +419,10 @@
                         resets = <&cpg 218>;
                         #dma-cells = <1>;
                         dma-channels = <8>;
+                        iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
+                               <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
+                               <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
+                               <&ipmmu_ds1 6>, <&ipmmu_ds1 7>;
                 };
 
                 dmac2: dma-controller@e7310000 {
@@ -439,6 +447,10 @@
                         resets = <&cpg 217>;
                         #dma-cells = <1>;
                         dma-channels = <8>;
+                        iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
+                               <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
+                               <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
+                               <&ipmmu_ds1 22>, <&ipmmu_ds1 23>;
                 };
 
                 ipmmu_ds0: mmu@e6740000 {
@@ -817,11 +829,11 @@
                         compatible = "generic-ohci";
                         reg = <0 0xee080000 0 0x100>;
                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 703>;
+                        clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
                         phys = <&usb2_phy0>;
                         phy-names = "usb";
                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
-                        resets = <&cpg 703>;
+                        resets = <&cpg 703>, <&cpg 704>;
                         status = "disabled";
                 };
 
@@ -829,12 +841,12 @@
                         compatible = "generic-ehci";
                         reg = <0 0xee080100 0 0x100>;
                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 703>;
+                        clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
                         phys = <&usb2_phy0>;
                         phy-names = "usb";
                         companion = <&ohci0>;
                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
-                        resets = <&cpg 703>;
+                        resets = <&cpg 703>, <&cpg 704>;
                         status = "disabled";
                 };
 
@@ -843,9 +855,9 @@
                                      "renesas,rcar-gen3-usb2-phy";
                         reg = <0 0xee080200 0 0x700>;
                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 703>;
+                        clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
-                        resets = <&cpg 703>;
+                        resets = <&cpg 703>, <&cpg 704>;
                         #phy-cells = <0>;
                         status = "disabled";
                 };
@@ -960,12 +972,68 @@
                                 port@1 {
                                         reg = <1>;
                                         du_out_lvds0: endpoint {
+                                                remote-endpoint = <&lvds0_in>;
                                         };
                                 };
 
                                 port@2 {
                                         reg = <2>;
                                         du_out_lvds1: endpoint {
+                                                remote-endpoint = <&lvds1_in>;
+                                        };
+                                };
+                        };
+                };
+
+                lvds0: lvds-encoder@feb90000 {
+                        compatible = "renesas,r8a77995-lvds";
+                        reg = <0 0xfeb90000 0 0x20>;
+                        clocks = <&cpg CPG_MOD 727>;
+                        power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+                        resets = <&cpg 727>;
+                        status = "disabled";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@0 {
+                                        reg = <0>;
+                                        lvds0_in: endpoint {
+                                                remote-endpoint = <&du_out_lvds0>;
+                                        };
+                                };
+
+                                port@1 {
+                                        reg = <1>;
+                                        lvds0_out: endpoint {
+                                        };
+                                };
+                        };
+                };
+
+                lvds1: lvds-encoder@feb90100 {
+                        compatible = "renesas,r8a77995-lvds";
+                        reg = <0 0xfeb90100 0 0x20>;
+                        clocks = <&cpg CPG_MOD 727>;
+                        power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+                        resets = <&cpg 726>;
+                        status = "disabled";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@0 {
+                                        reg = <0>;
+                                        lvds1_in: endpoint {
+                                                remote-endpoint = <&du_out_lvds1>;
+                                        };
+                                };
+
+                                port@1 {
+                                        reg = <1>;
+                                        lvds1_out: endpoint {
                                         };
                                 };
                         };
diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
index 7d3d866a0063..7f91ff524109 100644
--- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
@@ -420,7 +420,10 @@
 
         video-receiver@70 {
                 compatible = "adi,adv7482";
-                reg = <0x70>;
+                reg = <0x70 0x71 0x72 0x73 0x74 0x75
+                       0x60 0x61 0x62 0x63 0x64 0x65>;
+                reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater",
+                            "infoframe", "cbus", "cec", "sdp", "txa", "txb" ;
 
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -471,6 +474,8 @@
 &i2c_dvfs {
         status = "okay";
 
+        clock-frequency = <400000>;
+
         pmic: pmic@30 {
                 pinctrl-0 = <&irq0_pins>;
                 pinctrl-names = "default";
@@ -748,6 +753,7 @@
         wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
         bus-width = <4>;
         sd-uhs-sdr50;
+        sd-uhs-sdr104;
         status = "okay";
 };
 
@@ -777,6 +783,7 @@
         wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
         bus-width = <4>;
         sd-uhs-sdr50;
+        sd-uhs-sdr104;
         status = "okay";
 };
 
diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
index 8bf3091a899c..1b316d79df88 100644
--- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
@@ -127,7 +127,7 @@
                 #address-cells = <1>;
                 #size-cells = <0>;
                 reg = <0x71>;
-                reset-gpios= <&gpio3 15 GPIO_ACTIVE_LOW>;
+                reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
         };
 };
 
diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi
index 0ead552d7eae..89daca7356df 100644
--- a/arch/arm64/boot/dts/renesas/ulcb.dtsi
+++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi
@@ -18,6 +18,7 @@
         };
 
         chosen {
+                bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
                 stdout-path = "serial0:115200n8";
         };
 
@@ -241,6 +242,8 @@
 &i2c_dvfs {
         status = "okay";
 
+        clock-frequency = <400000>;
+
         pmic: pmic@30 {
                 pinctrl-0 = <&irq0_pins>;
                 pinctrl-names = "default";
@@ -416,6 +419,7 @@
         cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
         bus-width = <4>;
         sd-uhs-sdr50;
+        sd-uhs-sdr104;
         status = "okay";
 };
 
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index b0092d95b574..49042c477870 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -1,4 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
@@ -14,5 +15,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-bob.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
diff --git a/arch/arm64/boot/dts/rockchip/px30-evb.dts b/arch/arm64/boot/dts/rockchip/px30-evb.dts
new file mode 100644
index 000000000000..263d7f3dbc44
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/px30-evb.dts
@@ -0,0 +1,235 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "px30.dtsi"
+
+/ {
+        model = "Rockchip PX30 EVB";
+        compatible = "rockchip,px30-evb", "rockchip,px30";
+
+        chosen {
+                stdout-path = "serial2:1500000n8";
+        };
+
+        adc-keys {
+                compatible = "adc-keys";
+                io-channels = <&saradc 2>;
+                io-channel-names = "buttons";
+                keyup-threshold-microvolt = <1800000>;
+                poll-interval = <100>;
+
+                esc-key {
+                        label = "esc";
+                        linux,code = <KEY_ESC>;
+                        press-threshold-microvolt = <1310000>;
+                };
+
+                home-key {
+                        label = "home";
+                        linux,code = <KEY_HOME>;
+                        press-threshold-microvolt = <624000>;
+                };
+
+                menu-key {
+                        label = "menu";
+                        linux,code = <KEY_MENU>;
+                        press-threshold-microvolt = <987000>;
+                };
+
+                vol-down-key {
+                        label = "volume down";
+                        linux,code = <KEY_VOLUMEDOWN>;
+                        press-threshold-microvolt = <300000>;
+                };
+
+                vol-up-key {
+                        label = "volume up";
+                        linux,code = <KEY_VOLUMEUP>;
+                        press-threshold-microvolt = <17000>;
+                };
+        };
+
+        backlight: backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm1 0 25000 0>;
+        };
+
+        sdio_pwrseq: sdio-pwrseq {
+                compatible = "mmc-pwrseq-simple";
+                pinctrl-names = "default";
+                pinctrl-0 = <&wifi_enable_h>;
+
+                /*
+                 * On the module itself this is one of these (depending
+                 * on the actual card populated):
+                 * - SDIO_RESET_L_WL_REG_ON
+                 * - PDN (power down when low)
+                 */
+                reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */
+        };
+
+        vcc_phy: vcc-phy-regulator {
+                compatible = "regulator-fixed";
+                regulator-name = "vcc_phy";
+                regulator-always-on;
+                regulator-boot-on;
+        };
+
+        vcc5v0_sys: vccsys {
+                compatible = "regulator-fixed";
+                regulator-name = "vcc5v0_sys";
+                regulator-always-on;
+                regulator-boot-on;
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+        };
+};
+
+&display_subsystem {
+        status = "okay";
+};
+
+&emmc {
+        bus-width = <8>;
+        cap-mmc-highspeed;
+        mmc-hs200-1_8v;
+        non-removable;
+        status = "okay";
+};
+
+&gmac {
+        clock_in_out = "output";
+        phy-supply = <&vcc_phy>;
+        snps,reset-gpio = <&gpio2 13 GPIO_ACTIVE_LOW>;
+        snps,reset-active-low;
+        snps,reset-delays-us = <0 50000 50000>;
+        status = "okay";
+};
+
+&i2c0 {
+        status = "okay";
+};
+
+&i2s1_2ch {
+        status = "okay";
+};
+
+&io_domains {
+        status = "okay";
+};
+
+&pinctrl {
+        headphone {
+                hp_det: hp-det {
+                        rockchip,pins =
+                                <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
+                };
+        };
+
+        pmic {
+                pmic_int: pmic_int {
+                        rockchip,pins =
+                                <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
+                };
+
+                soc_slppin_gpio: soc_slppin_gpio {
+                        rockchip,pins =
+                                <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>;
+                };
+
+                soc_slppin_slp: soc_slppin_slp {
+                        rockchip,pins =
+                                <0 RK_PA4 RK_FUNC_1 &pcfg_pull_none>;
+                };
+
+                soc_slppin_rst: soc_slppin_rst {
+                        rockchip,pins =
+                                <0 RK_PA4 RK_FUNC_2 &pcfg_pull_none>;
+                };
+        };
+
+        sdio-pwrseq {
+                wifi_enable_h: wifi-enable-h {
+                        rockchip,pins =
+                                <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+                };
+        };
+};
+
+&pmu_io_domains {
+        status = "okay";
+};
+
+&pwm1 {
+        status = "okay";
+};
+
+&saradc {
+        status = "okay";
+};
+
+&sdmmc {
+        bus-width = <4>;
+        cap-mmc-highspeed;
+        cap-sd-highspeed;
+        card-detect-delay = <800>;
+        sd-uhs-sdr12;
+        sd-uhs-sdr25;
+        sd-uhs-sdr50;
+        sd-uhs-sdr104;
+        status = "okay";
+};
+
+&sdio {
+        bus-width = <4>;
+        cap-sd-highspeed;
+        keep-power-in-suspend;
+        non-removable;
+        mmc-pwrseq = <&sdio_pwrseq>;
+        sd-uhs-sdr104;
+        status = "okay";
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart1_xfer &uart1_cts>;
+        status = "okay";
+};
+
+&uart2 {
+        status = "okay";
+};
+
+&usb20_otg {
+        status = "okay";
+};
+
+&usb_host0_ehci {
+        status = "okay";
+};
+
+&usb_host0_ohci {
+        status = "okay";
+};
+
+&vopb {
+        status = "okay";
+};
+
+&vopb_mmu {
+        status = "okay";
+};
+
+&vopl {
+        status = "okay";
+};
+
+&vopl_mmu {
+        status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
new file mode 100644
index 000000000000..9aa8d5ef9e45
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -0,0 +1,2047 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
+ */
+
+#include <dt-bindings/clock/px30-cru.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/power/px30-power.h>
+#include <dt-bindings/soc/rockchip,boot-mode.h>
+
+/ {
+        compatible = "rockchip,px30";
+
+        interrupt-parent = <&gic>;
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        aliases {
+                ethernet0 = &gmac;
+                i2c0 = &i2c0;
+                i2c1 = &i2c1;
+                i2c2 = &i2c2;
+                i2c3 = &i2c3;
+                serial0 = &uart0;
+                serial1 = &uart1;
+                serial2 = &uart2;
+                serial3 = &uart3;
+                serial4 = &uart4;
+                serial5 = &uart5;
+                spi0 = &spi0;
+                spi1 = &spi1;
+        };
+
+        cpus {
+                #address-cells = <2>;
+                #size-cells = <0>;
+
+                cpu0: cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a35", "arm,armv8";
+                        reg = <0x0 0x0>;
+                        enable-method = "psci";
+                        clocks = <&cru ARMCLK>;
+                        #cooling-cells = <2>;
+                        cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+                        dynamic-power-coefficient = <90>;
+                        operating-points-v2 = <&cpu0_opp_table>;
+                };
+
+                cpu1: cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a35", "arm,armv8";
+                        reg = <0x0 0x1>;
+                        enable-method = "psci";
+                        clocks = <&cru ARMCLK>;
+                        #cooling-cells = <2>;
+                        cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+                        dynamic-power-coefficient = <90>;
+                        operating-points-v2 = <&cpu0_opp_table>;
+                };
+
+                cpu2: cpu@2 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a35", "arm,armv8";
+                        reg = <0x0 0x2>;
+                        enable-method = "psci";
+                        clocks = <&cru ARMCLK>;
+                        #cooling-cells = <2>;
+                        cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+                        dynamic-power-coefficient = <90>;
+                        operating-points-v2 = <&cpu0_opp_table>;
+                };
+
+                cpu3: cpu@3 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a35", "arm,armv8";
+                        reg = <0x0 0x3>;
+                        enable-method = "psci";
+                        clocks = <&cru ARMCLK>;
+                        #cooling-cells = <2>;
+                        cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+                        dynamic-power-coefficient = <90>;
+                        operating-points-v2 = <&cpu0_opp_table>;
+                };
+
+                idle-states {
+                        entry-method = "psci";
+
+                        CPU_SLEEP: cpu-sleep {
+                                compatible = "arm,idle-state";
+                                local-timer-stop;
+                                arm,psci-suspend-param = <0x0010000>;
+                                entry-latency-us = <120>;
+                                exit-latency-us = <250>;
+                                min-residency-us = <900>;
+                        };
+
+                        CLUSTER_SLEEP: cluster-sleep {
+                                compatible = "arm,idle-state";
+                                local-timer-stop;
+                                arm,psci-suspend-param = <0x1010000>;
+                                entry-latency-us = <400>;
+                                exit-latency-us = <500>;
+                                min-residency-us = <2000>;
+                        };
+                };
+        };
+
+        cpu0_opp_table: cpu0-opp-table {
+                compatible = "operating-points-v2";
+                opp-shared;
+
+                opp-408000000 {
+                        opp-hz = /bits/ 64 <408000000>;
+                        opp-microvolt = <950000 950000 1350000>;
+                        clock-latency-ns = <40000>;
+                        opp-suspend;
+                };
+                opp-600000000 {
+                        opp-hz = /bits/ 64 <600000000>;
+                        opp-microvolt = <950000 950000 1350000>;
+                        clock-latency-ns = <40000>;
+                };
+                opp-816000000 {
+                        opp-hz = /bits/ 64 <816000000>;
+                        opp-microvolt = <1050000 1050000 1350000>;
+                        clock-latency-ns = <40000>;
+                };
+                opp-1008000000 {
+                        opp-hz = /bits/ 64 <1008000000>;
+                        opp-microvolt = <1175000 1175000 1350000>;
+                        clock-latency-ns = <40000>;
+                };
+                opp-1200000000 {
+                        opp-hz = /bits/ 64 <1200000000>;
+                        opp-microvolt = <1300000 1300000 1350000>;
+                        clock-latency-ns = <40000>;
+                };
+                opp-1296000000 {
+                        opp-hz = /bits/ 64 <1296000000>;
+                        opp-microvolt = <1350000 1350000 1350000>;
+                        clock-latency-ns = <40000>;
+                };
+        };
+
+        arm-pmu {
+                compatible = "arm,cortex-a53-pmu";
+                interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+        };
+
+        display_subsystem: display-subsystem {
+                compatible = "rockchip,display-subsystem";
+                ports = <&vopb_out>, <&vopl_out>;
+                status = "disabled";
+        };
+
+        firmware {
+                optee {
+                        compatible = "linaro,optee-tz";
+                        method = "smc";
+                };
+        };
+
+        gmac_clkin: external-gmac-clock {
+                compatible = "fixed-clock";
+                clock-frequency = <50000000>;
+                clock-output-names = "gmac_clkin";
+                #clock-cells = <0>;
+        };
+
+        psci {
+                compatible = "arm,psci-1.0";
+                method = "smc";
+        };
+
+        timer {
+                compatible = "arm,armv8-timer";
+                interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+                             <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+                             <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+                             <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+        };
+
+        xin24m: xin24m {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <24000000>;
+                clock-output-names = "xin24m";
+        };
+
+        xin32k: xin32k {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <32768>;
+                clock-output-names = "xin32k";
+        };
+
+        pmu: power-management@ff000000 {
+                compatible = "rockchip,px30-pmu", "syscon", "simple-mfd";
+                reg = <0x0 0xff000000 0x0 0x1000>;
+
+                power: power-controller {
+                        compatible = "rockchip,px30-power-controller";
+                        #power-domain-cells = <1>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        /* These power domains are grouped by VD_LOGIC */
+                        pd_usb@PX30_PD_USB {
+                                reg = <PX30_PD_USB>;
+                                clocks = <&cru HCLK_HOST>,
+                                         <&cru HCLK_OTG>,
+                                         <&cru SCLK_OTG_ADP>;
+                                pm_qos = <&qos_usb_host>, <&qos_usb_otg>;
+                        };
+                        pd_sdcard@PX30_PD_SDCARD {
+                                reg = <PX30_PD_SDCARD>;
+                                clocks = <&cru HCLK_SDMMC>,
+                                         <&cru SCLK_SDMMC>;
+                                pm_qos = <&qos_sdmmc>;
+                        };
+                        pd_gmac@PX30_PD_GMAC {
+                                reg = <PX30_PD_GMAC>;
+                                clocks = <&cru ACLK_GMAC>,
+                                         <&cru PCLK_GMAC>,
+                                         <&cru SCLK_MAC_REF>,
+                                         <&cru SCLK_GMAC_RX_TX>;
+                                pm_qos = <&qos_gmac>;
+                        };
+                        pd_mmc_nand@PX30_PD_MMC_NAND {
+                                reg = <PX30_PD_MMC_NAND>;
+                                clocks =  <&cru HCLK_NANDC>,
+                                          <&cru HCLK_EMMC>,
+                                          <&cru HCLK_SDIO>,
+                                          <&cru HCLK_SFC>,
+                                          <&cru SCLK_EMMC>,
+                                          <&cru SCLK_NANDC>,
+                                          <&cru SCLK_SDIO>,
+                                          <&cru SCLK_SFC>;
+                                pm_qos = <&qos_emmc>, <&qos_nand>,
+                                         <&qos_sdio>, <&qos_sfc>;
+                        };
+                        pd_vpu@PX30_PD_VPU {
+                                reg = <PX30_PD_VPU>;
+                                clocks = <&cru ACLK_VPU>,
+                                         <&cru HCLK_VPU>,
+                                         <&cru SCLK_CORE_VPU>;
+                                pm_qos = <&qos_vpu>, <&qos_vpu_r128>;
+                        };
+                        pd_vo@PX30_PD_VO {
+                                reg = <PX30_PD_VO>;
+                                clocks = <&cru ACLK_RGA>,
+                                         <&cru ACLK_VOPB>,
+                                         <&cru ACLK_VOPL>,
+                                         <&cru DCLK_VOPB>,
+                                         <&cru DCLK_VOPL>,
+                                         <&cru HCLK_RGA>,
+                                         <&cru HCLK_VOPB>,
+                                         <&cru HCLK_VOPL>,
+                                         <&cru PCLK_MIPI_DSI>,
+                                         <&cru SCLK_RGA_CORE>,
+                                         <&cru SCLK_VOPB_PWM>;
+                                pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
+                                         <&qos_vop_m0>, <&qos_vop_m1>;
+                        };
+                        pd_vi@PX30_PD_VI {
+                                reg = <PX30_PD_VI>;
+                                clocks = <&cru ACLK_CIF>,
+                                         <&cru ACLK_ISP>,
+                                         <&cru HCLK_CIF>,
+                                         <&cru HCLK_ISP>,
+                                         <&cru SCLK_ISP>;
+                                pm_qos = <&qos_isp_128>, <&qos_isp_rd>,
+                                         <&qos_isp_wr>, <&qos_isp_m1>,
+                                         <&qos_vip>;
+                        };
+                        pd_gpu@PX30_PD_GPU {
+                                reg = <PX30_PD_GPU>;
+                                clocks = <&cru SCLK_GPU>;
+                                pm_qos = <&qos_gpu>;
+                        };
+                };
+        };
+
+        pmugrf: syscon@ff010000 {
+                compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd";
+                reg = <0x0 0xff010000 0x0 0x1000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                pmu_io_domains: io-domains {
+                        compatible = "rockchip,px30-pmu-io-voltage-domain";
+                        status = "disabled";
+                };
+
+                reboot-mode {
+                        compatible = "syscon-reboot-mode";
+                        offset = <0x200>;
+                        mode-bootloader = <BOOT_BL_DOWNLOAD>;
+                        mode-fastboot = <BOOT_FASTBOOT>;
+                        mode-loader = <BOOT_BL_DOWNLOAD>;
+                        mode-normal = <BOOT_NORMAL>;
+                        mode-recovery = <BOOT_RECOVERY>;
+                };
+        };
+
+        uart0: serial@ff030000 {
+                compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
+                reg = <0x0 0xff030000 0x0 0x100>;
+                interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
+                clock-names = "baudclk", "apb_pclk";
+                dmas = <&dmac 0>, <&dmac 1>;
+                dma-names = "tx", "rx";
+                reg-shift = <2>;
+                reg-io-width = <4>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+                status = "disabled";
+        };
+
+        i2s1_2ch: i2s@ff070000 {
+                compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
+                reg = <0x0 0xff070000 0x0 0x1000>;
+                interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
+                clock-names = "i2s_clk", "i2s_hclk";
+                dmas = <&dmac 18>, <&dmac 19>;
+                dma-names = "tx", "rx";
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
+                             &i2s1_2ch_sdi &i2s1_2ch_sdo>;
+                #sound-dai-cells = <0>;
+                status = "disabled";
+        };
+
+        i2s2_2ch: i2s@ff080000 {
+                compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
+                reg = <0x0 0xff080000 0x0 0x1000>;
+                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
+                clock-names = "i2s_clk", "i2s_hclk";
+                dmas = <&dmac 20>, <&dmac 21>;
+                dma-names = "tx", "rx";
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
+                             &i2s2_2ch_sdi &i2s2_2ch_sdo>;
+                #sound-dai-cells = <0>;
+                status = "disabled";
+        };
+
+        gic: interrupt-controller@ff131000 {
+                compatible = "arm,gic-400";
+                #interrupt-cells = <3>;
+                #address-cells = <0>;
+                interrupt-controller;
+                reg = <0x0 0xff131000 0 0x1000>,
+                      <0x0 0xff132000 0 0x2000>,
+                      <0x0 0xff134000 0 0x2000>,
+                      <0x0 0xff136000 0 0x2000>;
+                interrupts = <GIC_PPI 9
+                      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+        };
+
+        grf: syscon@ff140000 {
+                compatible = "rockchip,px30-grf", "syscon", "simple-mfd";
+                reg = <0x0 0xff140000 0x0 0x1000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                io_domains: io-domains {
+                        compatible = "rockchip,px30-io-voltage-domain";
+                        status = "disabled";
+                };
+        };
+
+        uart1: serial@ff158000 {
+                compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
+                reg = <0x0 0xff158000 0x0 0x100>;
+                interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+                clock-names = "baudclk", "apb_pclk";
+                dmas = <&dmac 2>, <&dmac 3>;
+                dma-names = "tx", "rx";
+                reg-shift = <2>;
+                reg-io-width = <4>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
+                status = "disabled";
+        };
+
+        uart2: serial@ff160000 {
+                compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
+                reg = <0x0 0xff160000 0x0 0x100>;
+                interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+                clock-names = "baudclk", "apb_pclk";
+                dmas = <&dmac 4>, <&dmac 5>;
+                dma-names = "tx", "rx";
+                reg-shift = <2>;
+                reg-io-width = <4>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&uart2m0_xfer>;
+                status = "disabled";
+        };
+
+        uart3: serial@ff168000 {
+                compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
+                reg = <0x0 0xff168000 0x0 0x100>;
+                interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
+                clock-names = "baudclk", "apb_pclk";
+                dmas = <&dmac 6>, <&dmac 7>;
+                dma-names = "tx", "rx";
+                reg-shift = <2>;
+                reg-io-width = <4>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
+                status = "disabled";
+        };
+
+        uart4: serial@ff170000 {
+                compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
+                reg = <0x0 0xff170000 0x0 0x100>;
+                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
+                clock-names = "baudclk", "apb_pclk";
+                dmas = <&dmac 8>, <&dmac 9>;
+                dma-names = "tx", "rx";
+                reg-shift = <2>;
+                reg-io-width = <4>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
+                status = "disabled";
+        };
+
+        uart5: serial@ff178000 {
+                compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
+                reg = <0x0 0xff178000 0x0 0x100>;
+                interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
+                clock-names = "baudclk", "apb_pclk";
+                dmas = <&dmac 10>, <&dmac 11>;
+                dma-names = "tx", "rx";
+                reg-shift = <2>;
+                reg-io-width = <4>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
+                status = "disabled";
+        };
+
+        i2c0: i2c@ff180000 {
+                compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
+                reg = <0x0 0xff180000 0x0 0x1000>;
+                clocks =  <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
+                clock-names = "i2c", "pclk";
+                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c0_xfer>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+
+        i2c1: i2c@ff190000 {
+                compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
+                reg = <0x0 0xff190000 0x0 0x1000>;
+                clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
+                clock-names = "i2c", "pclk";
+                interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c1_xfer>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+
+        i2c2: i2c@ff1a0000 {
+                compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
+                reg = <0x0 0xff1a0000 0x0 0x1000>;
+                clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
+                clock-names = "i2c", "pclk";
+                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c2_xfer>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+
+        i2c3: i2c@ff1b0000 {
+                compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
+                reg = <0x0 0xff1b0000 0x0 0x1000>;
+                clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
+                clock-names = "i2c", "pclk";
+                interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c3_xfer>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+
+        spi0: spi@ff1d0000 {
+                compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
+                reg = <0x0 0xff1d0000 0x0 0x1000>;
+                interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
+                clock-names = "spiclk", "apb_pclk";
+                dmas = <&dmac 12>, <&dmac 13>;
+                dma-names = "tx", "rx";
+                pinctrl-names = "default";
+                pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+
+        spi1: spi@ff1d8000 {
+                compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
+                reg = <0x0 0xff1d8000 0x0 0x1000>;
+                interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
+                clock-names = "spiclk", "apb_pclk";
+                dmas = <&dmac 14>, <&dmac 15>;
+                dma-names = "tx", "rx";
+                pinctrl-names = "default";
+                pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+
+        wdt: watchdog@ff1e0000 {
+                compatible = "snps,dw-wdt";
+                reg = <0x0 0xff1e0000 0x0 0x100>;
+                clocks = <&cru PCLK_WDT_NS>;
+                interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+        };
+
+        pwm0: pwm@ff200000 {
+                compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
+                reg = <0x0 0xff200000 0x0 0x10>;
+                clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
+                clock-names = "pwm", "pclk";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pwm0_pin>;
+                #pwm-cells = <3>;
+                status = "disabled";
+        };
+
+        pwm1: pwm@ff200010 {
+                compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
+                reg = <0x0 0xff200010 0x0 0x10>;
+                clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
+                clock-names = "pwm", "pclk";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pwm1_pin>;
+                #pwm-cells = <3>;
+                status = "disabled";
+        };
+
+        pwm2: pwm@ff200020 {
+                compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
+                reg = <0x0 0xff200020 0x0 0x10>;
+                clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
+                clock-names = "pwm", "pclk";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pwm2_pin>;
+                #pwm-cells = <3>;
+                status = "disabled";
+        };
+
+        pwm3: pwm@ff200030 {
+                compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
+                reg = <0x0 0xff200030 0x0 0x10>;
+                clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
+                clock-names = "pwm", "pclk";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pwm3_pin>;
+                #pwm-cells = <3>;
+                status = "disabled";
+        };
+
+        pwm4: pwm@ff208000 {
+                compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
+                reg = <0x0 0xff208000 0x0 0x10>;
+                clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
+                clock-names = "pwm", "pclk";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pwm4_pin>;
+                #pwm-cells = <3>;
+                status = "disabled";
+        };
+
+        pwm5: pwm@ff208010 {
+                compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
+                reg = <0x0 0xff208010 0x0 0x10>;
+                clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
+                clock-names = "pwm", "pclk";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pwm5_pin>;
+                #pwm-cells = <3>;
+                status = "disabled";
+        };
+
+        pwm6: pwm@ff208020 {
+                compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
+                reg = <0x0 0xff208020 0x0 0x10>;
+                clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
+                clock-names = "pwm", "pclk";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pwm6_pin>;
+                #pwm-cells = <3>;
+                status = "disabled";
+        };
+
+        pwm7: pwm@ff208030 {
+                compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
+                reg = <0x0 0xff208030 0x0 0x10>;
+                clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
+                clock-names = "pwm", "pclk";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pwm7_pin>;
+                #pwm-cells = <3>;
+                status = "disabled";
+        };
+
+        rktimer: timer@ff210000 {
+                compatible = "rockchip,px30-timer", "rockchip,rk3288-timer";
+                reg = <0x0 0xff210000 0x0 0x1000>;
+                interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
+                clock-names = "pclk", "timer";
+        };
+
+        amba {
+                compatible = "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
+
+                dmac: dmac@ff240000 {
+                        compatible = "arm,pl330", "arm,primecell";
+                        reg = <0x0 0xff240000 0x0 0x4000>;
+                        interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cru ACLK_DMAC>;
+                        clock-names = "apb_pclk";
+                        #dma-cells = <1>;
+                };
+        };
+
+        saradc: saradc@ff288000 {
+                compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc";
+                reg = <0x0 0xff288000 0x0 0x100>;
+                interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+                #io-channel-cells = <1>;
+                clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
+                clock-names = "saradc", "apb_pclk";
+                resets = <&cru SRST_SARADC_P>;
+                reset-names = "saradc-apb";
+                status = "disabled";
+        };
+
+        cru: clock-controller@ff2b0000 {
+                compatible = "rockchip,px30-cru";
+                reg = <0x0 0xff2b0000 0x0 0x1000>;
+                rockchip,grf = <&grf>;
+                #clock-cells = <1>;
+                #reset-cells = <1>;
+
+                assigned-clocks = <&cru PLL_NPLL>;
+                assigned-clock-rates = <1188000000>;
+        };
+
+        pmucru: clock-controller@ff2bc000 {
+                compatible = "rockchip,px30-pmucru";
+                reg = <0x0 0xff2bc000 0x0 0x1000>;
+                rockchip,grf = <&grf>;
+                #clock-cells = <1>;
+                #reset-cells = <1>;
+
+                assigned-clocks =
+                        <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>,
+                        <&pmucru SCLK_WIFI_PMU>, <&cru ARMCLK>,
+                        <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
+                        <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
+                        <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;
+                assigned-clock-rates =
+                        <1200000000>, <100000000>,
+                        <26000000>, <600000000>,
+                        <200000000>, <200000000>,
+                        <150000000>, <150000000>,
+                        <100000000>, <200000000>;
+        };
+
+        usb20_otg: usb@ff300000 {
+                compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
+                             "snps,dwc2";
+                reg = <0x0 0xff300000 0x0 0x40000>;
+                interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cru HCLK_OTG>;
+                clock-names = "otg";
+                dr_mode = "otg";
+                g-np-tx-fifo-size = <16>;
+                g-rx-fifo-size = <280>;
+                g-tx-fifo-size = <256 128 128 64 32 16>;
+                g-use-dma;
+                power-domains = <&power PX30_PD_USB>;
+                status = "disabled";
+        };
+
+        usb_host0_ehci: usb@ff340000 {
+                compatible = "generic-ehci";
+                reg = <0x0 0xff340000 0x0 0x10000>;
+                interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cru HCLK_HOST>;
+                clock-names = "usbhost";
+                power-domains = <&power PX30_PD_USB>;
+                status = "disabled";
+        };
+
+        usb_host0_ohci: usb@ff350000 {
+                compatible = "generic-ohci";
+                reg = <0x0 0xff350000 0x0 0x10000>;
+                interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cru HCLK_HOST>;
+                clock-names = "usbhost";
+                power-domains = <&power PX30_PD_USB>;
+                status = "disabled";
+        };
+
+        gmac: ethernet@ff360000 {
+                compatible = "rockchip,px30-gmac";
+                reg = <0x0 0xff360000 0x0 0x10000>;
+                interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "macirq";
+                clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>,
+                         <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>,
+                         <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
+                         <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>;
+                clock-names = "stmmaceth", "mac_clk_rx",
+                              "mac_clk_tx", "clk_mac_ref",
+                              "clk_mac_refout", "aclk_mac",
+                              "pclk_mac", "clk_mac_speed";
+                rockchip,grf = <&grf>;
+                phy-mode = "rmii";
+                pinctrl-names = "default";
+                pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
+                power-domains = <&power PX30_PD_GMAC>;
+                resets = <&cru SRST_GMAC_A>;
+                reset-names = "stmmaceth";
+                status = "disabled";
+        };
+
+        sdmmc: dwmmc@ff370000 {
+                compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
+                reg = <0x0 0xff370000 0x0 0x4000>;
+                interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
+                         <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+                clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
+                fifo-depth = <0x100>;
+                max-frequency = <150000000>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
+                power-domains = <&power PX30_PD_SDCARD>;
+                status = "disabled";
+        };
+
+        sdio: dwmmc@ff380000 {
+                compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
+                reg = <0x0 0xff380000 0x0 0x4000>;
+                interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
+                         <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
+                clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
+                fifo-depth = <0x100>;
+                max-frequency = <150000000>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
+                power-domains = <&power PX30_PD_MMC_NAND>;
+                status = "disabled";
+        };
+
+        emmc: dwmmc@ff390000 {
+                compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
+                reg = <0x0 0xff390000 0x0 0x4000>;
+                interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
+                         <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
+                clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
+                fifo-depth = <0x100>;
+                max-frequency = <150000000>;
+                power-domains = <&power PX30_PD_MMC_NAND>;
+                status = "disabled";
+        };
+
+        vopb: vop@ff460000 {
+                compatible = "rockchip,px30-vop-big";
+                reg = <0x0 0xff460000 0x0 0xefc>;
+                interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>,
+                         <&cru HCLK_VOPB>;
+                clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+                resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>;
+                reset-names = "axi", "ahb", "dclk";
+                iommus = <&vopb_mmu>;
+                power-domains = <&power PX30_PD_VO>;
+                rockchip,grf = <&grf>;
+                status = "disabled";
+
+                vopb_out: port {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+        };
+
+        vopb_mmu: iommu@ff460f00 {
+                compatible = "rockchip,iommu";
+                reg = <0x0 0xff460f00 0x0 0x100>;
+                interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "vopb_mmu";
+                clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
+                clock-names = "aclk", "hclk";
+                power-domains = <&power PX30_PD_VO>;
+                #iommu-cells = <0>;
+                status = "disabled";
+        };
+
+        vopl: vop@ff470000 {
+                compatible = "rockchip,px30-vop-lit";
+                reg = <0x0 0xff470000 0x0 0xefc>;
+                interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>,
+                         <&cru HCLK_VOPL>;
+                clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+                resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>;
+                reset-names = "axi", "ahb", "dclk";
+                iommus = <&vopl_mmu>;
+                power-domains = <&power PX30_PD_VO>;
+                rockchip,grf = <&grf>;
+                status = "disabled";
+
+                vopl_out: port {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+        };
+
+        vopl_mmu: iommu@ff470f00 {
+                compatible = "rockchip,iommu";
+                reg = <0x0 0xff470f00 0x0 0x100>;
+                interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "vopl_mmu";
+                clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
+                clock-names = "aclk", "hclk";
+                power-domains = <&power PX30_PD_VO>;
+                #iommu-cells = <0>;
+                status = "disabled";
+        };
+
+        qos_gmac: qos@ff518000 {
+                compatible = "syscon";
+                reg = <0x0 0xff518000 0x0 0x20>;
+        };
+
+        qos_gpu: qos@ff520000 {
+                compatible = "syscon";
+                reg = <0x0 0xff520000 0x0 0x20>;
+        };
+
+        qos_sdmmc: qos@ff52c000 {
+                compatible = "syscon";
+                reg = <0x0 0xff52c000 0x0 0x20>;
+        };
+
+        qos_emmc: qos@ff538000 {
+                compatible = "syscon";
+                reg = <0x0 0xff538000 0x0 0x20>;
+        };
+
+        qos_nand: qos@ff538080 {
+                compatible = "syscon";
+                reg = <0x0 0xff538080 0x0 0x20>;
+        };
+
+        qos_sdio: qos@ff538100 {
+                compatible = "syscon";
+                reg = <0x0 0xff538100 0x0 0x20>;
+        };
+
+        qos_sfc: qos@ff538180 {
+                compatible = "syscon";
+                reg = <0x0 0xff538180 0x0 0x20>;
+        };
+
+        qos_usb_host: qos@ff540000 {
+                compatible = "syscon";
+                reg = <0x0 0xff540000 0x0 0x20>;
+        };
+
+        qos_usb_otg: qos@ff540080 {
+                compatible = "syscon";
+                reg = <0x0 0xff540080 0x0 0x20>;
+        };
+
+        qos_isp_128: qos@ff548000 {
+                compatible = "syscon";
+                reg = <0x0 0xff548000 0x0 0x20>;
+        };
+
+        qos_isp_rd: qos@ff548080 {
+                compatible = "syscon";
+                reg = <0x0 0xff548080 0x0 0x20>;
+        };
+
+        qos_isp_wr: qos@ff548100 {
+                compatible = "syscon";
+                reg = <0x0 0xff548100 0x0 0x20>;
+        };
+
+        qos_isp_m1: qos@ff548180 {
+                compatible = "syscon";
+                reg = <0x0 0xff548180 0x0 0x20>;
+        };
+
+        qos_vip: qos@ff548200 {
+                compatible = "syscon";
+                reg = <0x0 0xff548200 0x0 0x20>;
+        };
+
+        qos_rga_rd: qos@ff550000 {
+                compatible = "syscon";
+                reg = <0x0 0xff550000 0x0 0x20>;
+        };
+
+        qos_rga_wr: qos@ff550080 {
+                compatible = "syscon";
+                reg = <0x0 0xff550080 0x0 0x20>;
+        };
+
+        qos_vop_m0: qos@ff550100 {
+                compatible = "syscon";
+                reg = <0x0 0xff550100 0x0 0x20>;
+        };
+
+        qos_vop_m1: qos@ff550180 {
+                compatible = "syscon";
+                reg = <0x0 0xff550180 0x0 0x20>;
+        };
+
+        qos_vpu: qos@ff558000 {
+                compatible = "syscon";
+                reg = <0x0 0xff558000 0x0 0x20>;
+        };
+
+        qos_vpu_r128: qos@ff558080 {
+                compatible = "syscon";
+                reg = <0x0 0xff558080 0x0 0x20>;
+        };
+
+        pinctrl: pinctrl {
+                compatible = "rockchip,px30-pinctrl";
+                rockchip,grf = <&grf>;
+                rockchip,pmu = <&pmugrf>;
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
+
+                gpio0: gpio0@ff040000 {
+                        compatible = "rockchip,gpio-bank";
+                        reg = <0x0 0xff040000 0x0 0x100>;
+                        interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&pmucru PCLK_GPIO0_PMU>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpio1: gpio1@ff250000 {
+                        compatible = "rockchip,gpio-bank";
+                        reg = <0x0 0xff250000 0x0 0x100>;
+                        interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cru PCLK_GPIO1>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpio2: gpio2@ff260000 {
+                        compatible = "rockchip,gpio-bank";
+                        reg = <0x0 0xff260000 0x0 0x100>;
+                        interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cru PCLK_GPIO2>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpio3: gpio3@ff270000 {
+                        compatible = "rockchip,gpio-bank";
+                        reg = <0x0 0xff270000 0x0 0x100>;
+                        interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cru PCLK_GPIO3>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                pcfg_pull_up: pcfg-pull-up {
+                        bias-pull-up;
+                };
+
+                pcfg_pull_down: pcfg-pull-down {
+                        bias-pull-down;
+                };
+
+                pcfg_pull_none: pcfg-pull-none {
+                        bias-disable;
+                };
+
+                pcfg_pull_none_2ma: pcfg-pull-none-2ma {
+                        bias-disable;
+                        drive-strength = <2>;
+                };
+
+                pcfg_pull_up_2ma: pcfg-pull-up-2ma {
+                        bias-pull-up;
+                        drive-strength = <2>;
+                };
+
+                pcfg_pull_up_4ma: pcfg-pull-up-4ma {
+                        bias-pull-up;
+                        drive-strength = <4>;
+                };
+
+                pcfg_pull_none_4ma: pcfg-pull-none-4ma {
+                        bias-disable;
+                        drive-strength = <4>;
+                };
+
+                pcfg_pull_down_4ma: pcfg-pull-down-4ma {
+                        bias-pull-down;
+                        drive-strength = <4>;
+                };
+
+                pcfg_pull_none_8ma: pcfg-pull-none-8ma {
+                        bias-disable;
+                        drive-strength = <8>;
+                };
+
+                pcfg_pull_up_8ma: pcfg-pull-up-8ma {
+                        bias-pull-up;
+                        drive-strength = <8>;
+                };
+
+                pcfg_pull_none_12ma: pcfg-pull-none-12ma {
+                        bias-disable;
+                        drive-strength = <12>;
+                };
+
+                pcfg_pull_up_12ma: pcfg-pull-up-12ma {
+                        bias-pull-up;
+                        drive-strength = <12>;
+                };
+
+                pcfg_pull_none_smt: pcfg-pull-none-smt {
+                        bias-disable;
+                        input-schmitt-enable;
+                };
+
+                pcfg_output_high: pcfg-output-high {
+                        output-high;
+                };
+
+                pcfg_output_low: pcfg-output-low {
+                        output-low;
+                };
+
+                pcfg_input_high: pcfg-input-high {
+                        bias-pull-up;
+                        input-enable;
+                };
+
+                pcfg_input: pcfg-input {
+                        input-enable;
+                };
+
+                i2c0 {
+                        i2c0_xfer: i2c0-xfer {
+                                rockchip,pins =
+                                        <0 RK_PB0 1 &pcfg_pull_none_smt>,
+                                        <0 RK_PB1 1 &pcfg_pull_none_smt>;
+                        };
+                };
+
+                i2c1 {
+                        i2c1_xfer: i2c1-xfer {
+                                rockchip,pins =
+                                        <0 RK_PC2 1 &pcfg_pull_none_smt>,
+                                        <0 RK_PC3 1 &pcfg_pull_none_smt>;
+                        };
+                };
+
+                i2c2 {
+                        i2c2_xfer: i2c2-xfer {
+                                rockchip,pins =
+                                        <2 RK_PB7 2 &pcfg_pull_none_smt>,
+                                        <2 RK_PC0 2 &pcfg_pull_none_smt>;
+                        };
+                };
+
+                i2c3 {
+                        i2c3_xfer: i2c3-xfer {
+                                rockchip,pins =
+                                        <1 RK_PB4 4 &pcfg_pull_none_smt>,
+                                        <1 RK_PB5 4 &pcfg_pull_none_smt>;
+                        };
+                };
+
+                tsadc {
+                        tsadc_otp_gpio: tsadc-otp-gpio {
+                                rockchip,pins =
+                                        <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+                        };
+
+                        tsadc_otp_out: tsadc-otp-out {
+                                rockchip,pins =
+                                        <0 RK_PA6 1 &pcfg_pull_none>;
+                        };
+                };
+
+                uart0 {
+                        uart0_xfer: uart0-xfer {
+                                rockchip,pins =
+                                        <0 RK_PB2 1 &pcfg_pull_up>,
+                                        <0 RK_PB3 1 &pcfg_pull_up>;
+                        };
+
+                        uart0_cts: uart0-cts {
+                                rockchip,pins =
+                                        <0 RK_PB4 1 &pcfg_pull_none>;
+                        };
+
+                        uart0_rts: uart0-rts {
+                                rockchip,pins =
+                                        <0 RK_PB5 1 &pcfg_pull_none>;
+                        };
+
+                        uart0_rts_gpio: uart0-rts-gpio {
+                                rockchip,pins =
+                                        <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+                        };
+                };
+
+                uart1 {
+                        uart1_xfer: uart1-xfer {
+                                rockchip,pins =
+                                        <1 RK_PC1 1 &pcfg_pull_up>,
+                                        <1 RK_PC0 1 &pcfg_pull_up>;
+                        };
+
+                        uart1_cts: uart1-cts {
+                                rockchip,pins =
+                                        <1 RK_PC2 1 &pcfg_pull_none>;
+                        };
+
+                        uart1_rts: uart1-rts {
+                                rockchip,pins =
+                                        <1 RK_PC3 1 &pcfg_pull_none>;
+                        };
+
+                        uart1_rts_gpio: uart1-rts-gpio {
+                                rockchip,pins =
+                                        <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+                        };
+                };
+
+                uart2-m0 {
+                        uart2m0_xfer: uart2m0-xfer {
+                                rockchip,pins =
+                                        <1 RK_PD2 2 &pcfg_pull_up>,
+                                        <1 RK_PD3 2 &pcfg_pull_up>;
+                        };
+                };
+
+                uart2-m1 {
+                        uart2m1_xfer: uart2m1-xfer {
+                                rockchip,pins =
+                                        <2 RK_PB4 2 &pcfg_pull_up>,
+                                        <2 RK_PB6 2 &pcfg_pull_up>;
+                        };
+                };
+
+                uart3-m0 {
+                        uart3m0_xfer: uart3m0-xfer {
+                                rockchip,pins =
+                                        <0 RK_PC0 2 &pcfg_pull_up>,
+                                        <0 RK_PC1 2 &pcfg_pull_up>;
+                        };
+
+                        uart3m0_cts: uart3m0-cts {
+                                rockchip,pins =
+                                        <0 RK_PC2 2 &pcfg_pull_none>;
+                        };
+
+                        uart3m0_rts: uart3m0-rts {
+                                rockchip,pins =
+                                        <0 RK_PC3 2 &pcfg_pull_none>;
+                        };
+
+                        uart3m0_rts_gpio: uart3m0-rts-gpio {
+                                rockchip,pins =
+                                        <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+                        };
+                };
+
+                uart3-m1 {
+                        uart3m1_xfer: uart3m1-xfer {
+                                rockchip,pins =
+                                        <1 RK_PB6 2 &pcfg_pull_up>,
+                                        <1 RK_PB7 2 &pcfg_pull_up>;
+                        };
+
+                        uart3m1_cts: uart3m1-cts {
+                                rockchip,pins =
+                                        <1 RK_PB4 2 &pcfg_pull_none>;
+                        };
+
+                        uart3m1_rts: uart3m1-rts {
+                                rockchip,pins =
+                                        <1 RK_PB5 2 &pcfg_pull_none>;
+                        };
+
+                        uart3m1_rts_gpio: uart3m1-rts-gpio {
+                                rockchip,pins =
+                                        <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+                        };
+                };
+
+                uart4 {
+                        uart4_xfer: uart4-xfer {
+                                rockchip,pins =
+                                        <1 RK_PD4 2 &pcfg_pull_up>,
+                                        <1 RK_PD5 2 &pcfg_pull_up>;
+                        };
+
+                        uart4_cts: uart4-cts {
+                                rockchip,pins =
+                                        <1 RK_PD6 2 &pcfg_pull_none>;
+                        };
+
+                        uart4_rts: uart4-rts {
+                                rockchip,pins =
+                                        <1 RK_PD7 2 &pcfg_pull_none>;
+                        };
+                };
+
+                uart5 {
+                        uart5_xfer: uart5-xfer {
+                                rockchip,pins =
+                                        <3 RK_PA2 4 &pcfg_pull_up>,
+                                        <3 RK_PA1 4 &pcfg_pull_up>;
+                        };
+
+                        uart5_cts: uart5-cts {
+                                rockchip,pins =
+                                        <3 RK_PA3 4 &pcfg_pull_none>;
+                        };
+
+                        uart5_rts: uart5-rts {
+                                rockchip,pins =
+                                        <3 RK_PA5 4 &pcfg_pull_none>;
+                        };
+                };
+
+                spi0 {
+                        spi0_clk: spi0-clk {
+                                rockchip,pins =
+                                        <1 RK_PB7 3 &pcfg_pull_up_4ma>;
+                        };
+
+                        spi0_csn: spi0-csn {
+                                rockchip,pins =
+                                        <1 RK_PB6 3 &pcfg_pull_up_4ma>;
+                        };
+
+                        spi0_miso: spi0-miso {
+                                rockchip,pins =
+                                        <1 RK_PB5 3 &pcfg_pull_up_4ma>;
+                        };
+
+                        spi0_mosi: spi0-mosi {
+                                rockchip,pins =
+                                        <1 RK_PB4 3 &pcfg_pull_up_4ma>;
+                        };
+
+                        spi0_clk_hs: spi0-clk-hs {
+                                rockchip,pins =
+                                        <1 RK_PB7 3 &pcfg_pull_up_8ma>;
+                        };
+
+                        spi0_miso_hs: spi0-miso-hs {
+                                rockchip,pins =
+                                        <1 RK_PB5 3 &pcfg_pull_up_8ma>;
+                        };
+
+                        spi0_mosi_hs: spi0-mosi-hs {
+                                rockchip,pins =
+                                        <1 RK_PB4 3 &pcfg_pull_up_8ma>;
+                        };
+                };
+
+                spi1 {
+                        spi1_clk: spi1-clk {
+                                rockchip,pins =
+                                        <3 RK_PB7 4 &pcfg_pull_up_4ma>;
+                        };
+
+                        spi1_csn0: spi1-csn0 {
+                                rockchip,pins =
+                                        <3 RK_PB1 4 &pcfg_pull_up_4ma>;
+                        };
+
+                        spi1_csn1: spi1-csn1 {
+                                rockchip,pins =
+                                        <3 RK_PB2 2 &pcfg_pull_up_4ma>;
+                        };
+
+                        spi1_miso: spi1-miso {
+                                rockchip,pins =
+                                        <3 RK_PB6 4 &pcfg_pull_up_4ma>;
+                        };
+
+                        spi1_mosi: spi1-mosi {
+                                rockchip,pins =
+                                        <3 RK_PB4 4 &pcfg_pull_up_4ma>;
+                        };
+
+                        spi1_clk_hs: spi1-clk-hs {
+                                rockchip,pins =
+                                        <3 RK_PB7 4 &pcfg_pull_up_8ma>;
+                        };
+
+                        spi1_miso_hs: spi1-miso-hs {
+                                rockchip,pins =
+                                        <3 RK_PB6 4 &pcfg_pull_up_8ma>;
+                        };
+
+                        spi1_mosi_hs: spi1-mosi-hs {
+                                rockchip,pins =
+                                        <3 RK_PB4 4 &pcfg_pull_up_8ma>;
+                        };
+                };
+
+                pdm {
+                        pdm_clk0m0: pdm-clk0m0 {
+                                rockchip,pins =
+                                        <3 RK_PC6 2 &pcfg_pull_none>;
+                        };
+
+                        pdm_clk0m1: pdm-clk0m1 {
+                                rockchip,pins =
+                                        <2 RK_PC6 1 &pcfg_pull_none>;
+                        };
+
+                        pdm_clk1: pdm-clk1 {
+                                rockchip,pins =
+                                        <3 RK_PC7 2 &pcfg_pull_none>;
+                        };
+
+                        pdm_sdi0m0: pdm-sdi0m0 {
+                                rockchip,pins =
+                                        <3 RK_PD3 2 &pcfg_pull_none>;
+                        };
+
+                        pdm_sdi0m1: pdm-sdi0m1 {
+                                rockchip,pins =
+                                        <2 RK_PC5 2 &pcfg_pull_none>;
+                        };
+
+                        pdm_sdi1: pdm-sdi1 {
+                                rockchip,pins =
+                                        <3 RK_PD0 2 &pcfg_pull_none>;
+                        };
+
+                        pdm_sdi2: pdm-sdi2 {
+                                rockchip,pins =
+                                        <3 RK_PD1 2 &pcfg_pull_none>;
+                        };
+
+                        pdm_sdi3: pdm-sdi3 {
+                                rockchip,pins =
+                                        <3 RK_PD2 2 &pcfg_pull_none>;
+                        };
+
+                        pdm_clk0m0_sleep: pdm-clk0m0-sleep {
+                                rockchip,pins =
+                                        <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
+                        };
+
+                        pdm_clk0m_sleep1: pdm-clk0m1-sleep {
+                                rockchip,pins =
+                                        <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
+                        };
+
+                        pdm_clk1_sleep: pdm-clk1-sleep {
+                                rockchip,pins =
+                                        <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
+                        };
+
+                        pdm_sdi0m0_sleep: pdm-sdi0m0-sleep {
+                                rockchip,pins =
+                                        <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>;
+                        };
+
+                        pdm_sdi0m1_sleep: pdm-sdi0m1-sleep {
+                                rockchip,pins =
+                                        <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
+                        };
+
+                        pdm_sdi1_sleep: pdm-sdi1-sleep {
+                                rockchip,pins =
+                                        <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>;
+                        };
+
+                        pdm_sdi2_sleep: pdm-sdi2-sleep {
+                                rockchip,pins =
+                                        <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
+                        };
+
+                        pdm_sdi3_sleep: pdm-sdi3-sleep {
+                                rockchip,pins =
+                                        <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>;
+                        };
+                };
+
+                i2s0 {
+                        i2s0_8ch_mclk: i2s0-8ch-mclk {
+                                rockchip,pins =
+                                        <3 RK_PC1 2 &pcfg_pull_none>;
+                        };
+
+                        i2s0_8ch_sclktx: i2s0-8ch-sclktx {
+                                rockchip,pins =
+                                        <3 RK_PC3 2 &pcfg_pull_none>;
+                        };
+
+                        i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
+                                rockchip,pins =
+                                        <3 RK_PB4 2 &pcfg_pull_none>;
+                        };
+
+                        i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
+                                rockchip,pins =
+                                        <3 RK_PC2 2 &pcfg_pull_none>;
+                        };
+
+                        i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
+                                rockchip,pins =
+                                        <3 RK_PB5 2 &pcfg_pull_none>;
+                        };
+
+                        i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
+                                rockchip,pins =
+                                        <3 RK_PC4 2 &pcfg_pull_none>;
+                        };
+
+                        i2s0_8ch_sdo1: i2s0-8ch-sdo1 {
+                                rockchip,pins =
+                                        <3 RK_PC0 2 &pcfg_pull_none>;
+                        };
+
+                        i2s0_8ch_sdo2: i2s0-8ch-sdo2 {
+                                rockchip,pins =
+                                        <3 RK_PB7 2 &pcfg_pull_none>;
+                        };
+
+                        i2s0_8ch_sdo3: i2s0-8ch-sdo3 {
+                                rockchip,pins =
+                                        <3 RK_PB6 2 &pcfg_pull_none>;
+                        };
+
+                        i2s0_8ch_sdi0: i2s0-8ch-sdi0 {
+                                rockchip,pins =
+                                        <3 RK_PC5 2 &pcfg_pull_none>;
+                        };
+
+                        i2s0_8ch_sdi1: i2s0-8ch-sdi1 {
+                                rockchip,pins =
+                                        <3 RK_PB3 2 &pcfg_pull_none>;
+                        };
+
+                        i2s0_8ch_sdi2: i2s0-8ch-sdi2 {
+                                rockchip,pins =
+                                        <3 RK_PB1 2 &pcfg_pull_none>;
+                        };
+
+                        i2s0_8ch_sdi3: i2s0-8ch-sdi3 {
+                                rockchip,pins =
+                                        <3 RK_PB0 2 &pcfg_pull_none>;
+                        };
+                };
+
+                i2s1 {
+                        i2s1_2ch_mclk: i2s1-2ch-mclk {
+                                rockchip,pins =
+                                        <2 RK_PC3 1 &pcfg_pull_none>;
+                        };
+
+                        i2s1_2ch_sclk: i2s1-2ch-sclk {
+                                rockchip,pins =
+                                        <2 RK_PC2 1 &pcfg_pull_none>;
+                        };
+
+                        i2s1_2ch_lrck: i2s1-2ch-lrck {
+                                rockchip,pins =
+                                        <2 RK_PC1 1 &pcfg_pull_none>;
+                        };
+
+                        i2s1_2ch_sdi: i2s1-2ch-sdi {
+                                rockchip,pins =
+                                        <2 RK_PC5 1 &pcfg_pull_none>;
+                        };
+
+                        i2s1_2ch_sdo: i2s1-2ch-sdo {
+                                rockchip,pins =
+                                        <2 RK_PC4 1 &pcfg_pull_none>;
+                        };
+                };
+
+                i2s2 {
+                        i2s2_2ch_mclk: i2s2-2ch-mclk {
+                                rockchip,pins =
+                                        <3 RK_PA1 2 &pcfg_pull_none>;
+                        };
+
+                        i2s2_2ch_sclk: i2s2-2ch-sclk {
+                                rockchip,pins =
+                                        <3 RK_PA2 2 &pcfg_pull_none>;
+                        };
+
+                        i2s2_2ch_lrck: i2s2-2ch-lrck {
+                                rockchip,pins =
+                                        <3 RK_PA3 2 &pcfg_pull_none>;
+                        };
+
+                        i2s2_2ch_sdi: i2s2-2ch-sdi {
+                                rockchip,pins =
+                                        <3 RK_PA5 2 &pcfg_pull_none>;
+                        };
+
+                        i2s2_2ch_sdo: i2s2-2ch-sdo {
+                                rockchip,pins =
+                                        <3 RK_PA7 2 &pcfg_pull_none>;
+                        };
+                };
+
+                sdmmc {
+                        sdmmc_clk: sdmmc-clk {
+                                rockchip,pins =
+                                        <1 RK_PD6 1 &pcfg_pull_none_8ma>;
+                        };
+
+                        sdmmc_cmd: sdmmc-cmd {
+                                rockchip,pins =
+                                        <1 RK_PD7 1 &pcfg_pull_up_8ma>;
+                        };
+
+                        sdmmc_det: sdmmc-det {
+                                rockchip,pins =
+                                        <0 RK_PA3 1 &pcfg_pull_up_8ma>;
+                        };
+
+                        sdmmc_bus1: sdmmc-bus1 {
+                                rockchip,pins =
+                                        <1 RK_PD2 1 &pcfg_pull_up_8ma>;
+                        };
+
+                        sdmmc_bus4: sdmmc-bus4 {
+                                rockchip,pins =
+                                        <1 RK_PD2 1 &pcfg_pull_up_8ma>,
+                                        <1 RK_PD3 1 &pcfg_pull_up_8ma>,
+                                        <1 RK_PD4 1 &pcfg_pull_up_8ma>,
+                                        <1 RK_PD5 1 &pcfg_pull_up_8ma>;
+                        };
+
+                        sdmmc_gpio: sdmmc-gpio {
+                                rockchip,pins =
+                                        <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+                                        <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+                                        <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+                                        <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+                                        <1 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+                                        <1 RK_PD7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
+                        };
+                };
+
+                sdio {
+                        sdio_clk: sdio-clk {
+                                rockchip,pins =
+                                        <1 RK_PC5 1 &pcfg_pull_none>;
+                        };
+
+                        sdio_cmd: sdio-cmd {
+                                rockchip,pins =
+                                        <1 RK_PC4 1 &pcfg_pull_up>;
+                        };
+
+                        sdio_bus4: sdio-bus4 {
+                                rockchip,pins =
+                                        <1 RK_PC6 1 &pcfg_pull_up>,
+                                        <1 RK_PC7 1 &pcfg_pull_up>,
+                                        <1 RK_PD0 1 &pcfg_pull_up>,
+                                        <1 RK_PD1 1 &pcfg_pull_up>;
+                        };
+
+                        sdio_gpio: sdio-gpio {
+                                rockchip,pins =
+                                        <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>,
+                                        <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>,
+                                        <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>,
+                                        <1 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>,
+                                        <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>,
+                                        <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+                        };
+                };
+
+                emmc {
+                        emmc_clk: emmc-clk {
+                                rockchip,pins =
+                                        <1 RK_PB1 2 &pcfg_pull_none_8ma>;
+                        };
+
+                        emmc_cmd: emmc-cmd {
+                                rockchip,pins =
+                                        <1 RK_PB2 2 &pcfg_pull_up_8ma>;
+                        };
+
+                        emmc_pwren: emmc-pwren {
+                                rockchip,pins =
+                                        <1 RK_PB0 2 &pcfg_pull_none>;
+                        };
+
+                        emmc_rstnout: emmc-rstnout {
+                                rockchip,pins =
+                                        <1 RK_PB3 2 &pcfg_pull_none>;
+                        };
+
+                        emmc_bus1: emmc-bus1 {
+                                rockchip,pins =
+                                        <1 RK_PA0 2 &pcfg_pull_up_8ma>;
+                        };
+
+                        emmc_bus4: emmc-bus4 {
+                                rockchip,pins =
+                                        <1 RK_PA0 2 &pcfg_pull_up_8ma>,
+                                        <1 RK_PA1 2 &pcfg_pull_up_8ma>,
+                                        <1 RK_PA2 2 &pcfg_pull_up_8ma>,
+                                        <1 RK_PA3 2 &pcfg_pull_up_8ma>;
+                        };
+
+                        emmc_bus8: emmc-bus8 {
+                                rockchip,pins =
+                                        <1 RK_PA0 2 &pcfg_pull_up_8ma>,
+                                        <1 RK_PA1 2 &pcfg_pull_up_8ma>,
+                                        <1 RK_PA2 2 &pcfg_pull_up_8ma>,
+                                        <1 RK_PA3 2 &pcfg_pull_up_8ma>,
+                                        <1 RK_PA4 2 &pcfg_pull_up_8ma>,
+                                        <1 RK_PA5 2 &pcfg_pull_up_8ma>,
+                                        <1 RK_PA6 2 &pcfg_pull_up_8ma>,
+                                        <1 RK_PA7 2 &pcfg_pull_up_8ma>;
+                        };
+                };
+
+                flash {
+                        flash_cs0: flash-cs0 {
+                                rockchip,pins =
+                                        <1 RK_PB0 1 &pcfg_pull_none>;
+                        };
+
+                        flash_rdy: flash-rdy {
+                                rockchip,pins =
+                                        <1 RK_PB1 1 &pcfg_pull_none>;
+                        };
+
+                        flash_dqs: flash-dqs {
+                                rockchip,pins =
+                                        <1 RK_PB2 1 &pcfg_pull_none>;
+                        };
+
+                        flash_ale: flash-ale {
+                                rockchip,pins =
+                                        <1 RK_PB3 1 &pcfg_pull_none>;
+                        };
+
+                        flash_cle: flash-cle {
+                                rockchip,pins =
+                                        <1 RK_PB4 1 &pcfg_pull_none>;
+                        };
+
+                        flash_wrn: flash-wrn {
+                                rockchip,pins =
+                                        <1 RK_PB5 1 &pcfg_pull_none>;
+                        };
+
+                        flash_csl: flash-csl {
+                                rockchip,pins =
+                                        <1 RK_PB6 1 &pcfg_pull_none>;
+                        };
+
+                        flash_rdn: flash-rdn {
+                                rockchip,pins =
+                                        <1 RK_PB7 1 &pcfg_pull_none>;
+                        };
+
+                        flash_bus8: flash-bus8 {
+                                rockchip,pins =
+                                        <1 RK_PA0 1 &pcfg_pull_up_12ma>,
+                                        <1 RK_PA1 1 &pcfg_pull_up_12ma>,
+                                        <1 RK_PA2 1 &pcfg_pull_up_12ma>,
+                                        <1 RK_PA3 1 &pcfg_pull_up_12ma>,
+                                        <1 RK_PA4 1 &pcfg_pull_up_12ma>,
+                                        <1 RK_PA5 1 &pcfg_pull_up_12ma>,
+                                        <1 RK_PA6 1 &pcfg_pull_up_12ma>,
+                                        <1 RK_PA7 1 &pcfg_pull_up_12ma>;
+                        };
+                };
+
+                lcdc {
+                        lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
+                                rockchip,pins =
+                                        <3 RK_PA0 1 &pcfg_pull_none_12ma>;
+                        };
+
+                        lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin {
+                                rockchip,pins =
+                                        <3 RK_PA1 1 &pcfg_pull_none_12ma>;
+                        };
+
+                        lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin {
+                                rockchip,pins =
+                                        <3 RK_PA2 1 &pcfg_pull_none_12ma>;
+                        };
+
+                        lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin {
+                                rockchip,pins =
+                                        <3 RK_PA3 1 &pcfg_pull_none_12ma>;
+                        };
+
+                        lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins {
+                                rockchip,pins =
+                                        <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
+                                        <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
+                                        <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
+                                        <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
+                                        <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
+                                        <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
+                                        <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
+                                        <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
+                                        <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
+                                        <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
+                                        <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
+                                        <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
+                                        <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
+                                        <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
+                                        <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
+                                        <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
+                                        <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
+                                        <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
+                                        <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
+                                        <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
+                                        <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
+                                        <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
+                                        <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
+                                        <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
+                        };
+
+                        lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins {
+                                rockchip,pins =
+                                        <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
+                                        <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
+                                        <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
+                                        <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
+                                        <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
+                                        <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
+                                        <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
+                                        <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
+                                        <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
+                                        <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
+                                        <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
+                                        <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
+                                        <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
+                                        <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
+                                        <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
+                                        <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
+                                        <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
+                                        <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
+                        };
+
+                        lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins {
+                                rockchip,pins =
+                                        <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
+                                        <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
+                                        <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
+                                        <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
+                                        <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
+                                        <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
+                                        <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
+                                        <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
+                                        <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
+                                        <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
+                                        <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
+                                        <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
+                                        <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
+                                        <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
+                                        <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
+                                        <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
+                        };
+
+                        lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins {
+                                rockchip,pins =
+                                        <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
+                                        <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
+                                        <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
+                                        <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
+                                        <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
+                                        <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
+                                        <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
+                                        <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
+                                        <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
+                                        <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
+                                        <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
+                                        <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
+                                        <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
+                                        <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
+                                        <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
+                                        <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
+                                        <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
+                        };
+
+                        lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins {
+                                rockchip,pins =
+                                        <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
+                                        <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
+                                        <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
+                                        <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
+                                        <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
+                                        <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
+                                        <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
+                                        <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
+                                        <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
+                                        <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
+                                        <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
+                        };
+
+                        lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins {
+                                rockchip,pins =
+                                        <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
+                                        <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
+                                        <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
+                                        <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
+                                        <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
+                                        <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
+                                        <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
+                                        <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
+                                        <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
+                        };
+                };
+
+                pwm0 {
+                        pwm0_pin: pwm0-pin {
+                                rockchip,pins =
+                                        <0 RK_PB7 1 &pcfg_pull_none>;
+                        };
+                };
+
+                pwm1 {
+                        pwm1_pin: pwm1-pin {
+                                rockchip,pins =
+                                        <0 RK_PC0 1 &pcfg_pull_none>;
+                        };
+                };
+
+                pwm2 {
+                        pwm2_pin: pwm2-pin {
+                                rockchip,pins =
+                                        <2 RK_PB5 1 &pcfg_pull_none>;
+                        };
+                };
+
+                pwm3 {
+                        pwm3_pin: pwm3-pin {
+                                rockchip,pins =
+                                        <0 RK_PC1 1 &pcfg_pull_none>;
+                        };
+                };
+
+                pwm4 {
+                        pwm4_pin: pwm4-pin {
+                                rockchip,pins =
+                                        <3 RK_PC2 3 &pcfg_pull_none>;
+                        };
+                };
+
+                pwm5 {
+                        pwm5_pin: pwm5-pin {
+                                rockchip,pins =
+                                        <3 RK_PC3 3 &pcfg_pull_none>;
+                        };
+                };
+
+                pwm6 {
+                        pwm6_pin: pwm6-pin {
+                                rockchip,pins =
+                                        <3 RK_PC4 3 &pcfg_pull_none>;
+                        };
+                };
+
+                pwm7 {
+                        pwm7_pin: pwm7-pin {
+                                rockchip,pins =
+                                        <3 RK_PC5 3 &pcfg_pull_none>;
+                        };
+                };
+
+                gmac {
+                        rmii_pins: rmii-pins {
+                                rockchip,pins =
+                                        <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */
+                                        <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */
+                                        <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */
+                                        <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */
+                                        <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */
+                                        <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */
+                                        <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */
+                                        <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */
+                                        <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */
+                        };
+
+                        mac_refclk_12ma: mac-refclk-12ma {
+                                rockchip,pins =
+                                        <2 RK_PB2 2 &pcfg_pull_none_12ma>;
+                        };
+
+                        mac_refclk: mac-refclk {
+                                rockchip,pins =
+                                        <2 RK_PB2 2 &pcfg_pull_none>;
+                        };
+                };
+
+                cif-m0 {
+                        cif_clkout_m0: cif-clkout-m0 {
+                                rockchip,pins =
+                                        <2 RK_PB3 1 &pcfg_pull_none>;
+                        };
+
+                        dvp_d2d9_m0: dvp-d2d9-m0 {
+                                rockchip,pins =
+                                        <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */
+                                        <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */
+                                        <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */
+                                        <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */
+                                        <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */
+                                        <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */
+                                        <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */
+                                        <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */
+                                        <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */
+                                        <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */
+                                        <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */
+                                        <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */
+                        };
+
+                        dvp_d0d1_m0: dvp-d0d1-m0 {
+                                rockchip,pins =
+                                        <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */
+                                        <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */
+                        };
+
+                        dvp_d10d11_m0:d10-d11-m0 {
+                                rockchip,pins =
+                                        <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */
+                                        <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */
+                        };
+                };
+
+                cif-m1 {
+                        cif_clkout_m1: cif-clkout-m1 {
+                                rockchip,pins =
+                                        <3 RK_PD0 3 &pcfg_pull_none>;
+                        };
+
+                        dvp_d2d9_m1: dvp-d2d9-m1 {
+                                rockchip,pins =
+                                        <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */
+                                        <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */
+                                        <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */
+                                        <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */
+                                        <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */
+                                        <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */
+                                        <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */
+                                        <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */
+                                        <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */
+                                        <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */
+                                        <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */
+                                        <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */
+                        };
+
+                        dvp_d0d1_m1: dvp-d0d1-m1 {
+                                rockchip,pins =
+                                        <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */
+                                        <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */
+                        };
+
+                        dvp_d10d11_m1:d10-d11-m1 {
+                                rockchip,pins =
+                                        <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */
+                                        <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */
+                        };
+                };
+
+                isp {
+                        isp_prelight: isp-prelight {
+                                rockchip,pins =
+                                        <3 RK_PD1 4 &pcfg_pull_none>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
index 246c317f6a68..99d0d9912950 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
@@ -41,6 +41,19 @@
                 vin-supply = <&vcc_io>;
         };
 
+        vcc_sdio: sdmmcio-regulator {
+                compatible = "regulator-gpio";
+                gpios = <&grf_gpio 0 GPIO_ACTIVE_HIGH>;
+                states = <1800000 0x1
+                          3300000 0x0>;
+                regulator-name = "vcc_sdio";
+                regulator-type = "voltage";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+                vin-supply = <&vcc_sys>;
+        };
+
         vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
                 compatible = "regulator-fixed";
                 enable-active-high;
@@ -208,6 +221,18 @@
         };
 };
 
+&io_domains {
+        status = "okay";
+
+        vccio1-supply = <&vcc_io>;
+        vccio2-supply = <&vcc18_emmc>;
+        vccio3-supply = <&vcc_sdio>;
+        vccio4-supply = <&vcc_18>;
+        vccio5-supply = <&vcc_io>;
+        vccio6-supply = <&vcc_io>;
+        pmuio-supply = <&vcc_io>;
+};
+
 &pinctrl {
         pmic {
                 pmic_int_l: pmic-int-l {
@@ -230,7 +255,12 @@
         max-frequency = <150000000>;
         pinctrl-names = "default";
         pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
+        sd-uhs-sdr12;
+        sd-uhs-sdr25;
+        sd-uhs-sdr50;
+        sd-uhs-sdr104;
         vmmc-supply = <&vcc_sd>;
+        vqmmc-supply = <&vcc_sdio>;
         status = "okay";
 };
 
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
index 5272e887a434..dc20145dd393 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
@@ -46,7 +46,7 @@
         vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
                 compatible = "regulator-fixed";
                 enable-active-high;
-                gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
+                gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&usb20_host_drv>;
                 regulator-name = "vcc_host1_5v";
@@ -62,6 +62,23 @@
                 regulator-min-microvolt = <5000000>;
                 regulator-max-microvolt = <5000000>;
         };
+
+        sound {
+                compatible = "audio-graph-card";
+                label = "rockchip,rk3328";
+                dais = <&spdif_p0>;
+        };
+
+        spdif-dit {
+                compatible = "linux,spdif-dit";
+                #sound-dai-cells = <0>;
+
+                port {
+                        dit_p0_0: endpoint {
+                                remote-endpoint = <&spdif_p0_0>;
+                        };
+                };
+        };
 };
 
 &cpu0 {
@@ -108,6 +125,14 @@
         status = "okay";
 };
 
+&hdmi {
+        status = "okay";
+};
+
+&hdmiphy {
+        status = "okay";
+};
+
 &i2c1 {
         status = "okay";
 
@@ -238,7 +263,7 @@
 
         usb2 {
                 usb20_host_drv: usb20-host-drv {
-                        rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+                        rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
                 };
         };
 
@@ -261,6 +286,30 @@
         status = "okay";
 };
 
+&spdif {
+        pinctrl-0 = <&spdifm0_tx>;
+        status = "okay";
+        #sound-dai-cells = <0>;
+
+        spdif_p0: port {
+                spdif_p0_0: endpoint {
+                        remote-endpoint = <&dit_p0_0>;
+                };
+        };
+};
+
+&spi0 {
+        status = "okay";
+
+        spiflash@0 {
+                compatible = "jedec,spi-nor";
+                reg = <0>;
+
+                /* maximum speed for Rockchip SPI */
+                spi-max-frequency = <50000000>;
+        };
+};
+
 &tsadc {
         rockchip,hw-tshut-mode = <0>;
         rockchip,hw-tshut-polarity = <0>;
@@ -295,3 +344,11 @@
 &usb_host0_ohci {
         status = "okay";
 };
+
+&vop {
+        status = "okay";
+};
+
+&vop_mmu {
+        status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 3f5a2944300f..e1a33dd981e0 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -151,6 +151,11 @@
                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
         };
 
+        display_subsystem: display-subsystem {
+                compatible = "rockchip,display-subsystem";
+                ports = <&vop_out>;
+        };
+
         psci {
                 compatible = "arm,psci-1.0", "arm,psci-0.2";
                 method = "smc";
@@ -249,6 +254,12 @@
                         status = "disabled";
                 };
 
+                grf_gpio: grf-gpio {
+                        compatible = "rockchip,rk3328-grf-gpio";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+
                 power: power-controller {
                         compatible = "rockchip,rk3328-power-controller";
                         #power-domain-cells = <1>;
@@ -274,7 +285,6 @@
                         mode-bootloader = <BOOT_FASTBOOT>;
                         mode-loader = <BOOT_BL_DOWNLOAD>;
                 };
-
         };
 
         uart0: serial@ff110000 {
@@ -600,6 +610,28 @@
                 status = "disabled";
         };
 
+        vop: vop@ff370000 {
+                compatible = "rockchip,rk3328-vop";
+                reg = <0x0 0xff370000 0x0 0x3efc>;
+                interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
+                clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+                resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
+                reset-names = "axi", "ahb", "dclk";
+                iommus = <&vop_mmu>;
+                status = "disabled";
+
+                vop_out: port {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        vop_out_hdmi: endpoint@0 {
+                                reg = <0>;
+                                remote-endpoint = <&hdmi_in_vop>;
+                        };
+                };
+        };
+
         vop_mmu: iommu@ff373f00 {
                 compatible = "rockchip,iommu";
                 reg = <0x0 0xff373f00 0x0 0x100>;
@@ -611,6 +643,46 @@
                 status = "disabled";
         };
 
+        hdmi: hdmi@ff3c0000 {
+                compatible = "rockchip,rk3328-dw-hdmi";
+                reg = <0x0 0xff3c0000 0x0 0x20000>;
+                reg-io-width = <4>;
+                interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cru PCLK_HDMI>,
+                         <&cru SCLK_HDMI_SFC>;
+                clock-names = "iahb",
+                              "isfr";
+                phys = <&hdmiphy>;
+                phy-names = "hdmi";
+                pinctrl-names = "default";
+                pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
+                rockchip,grf = <&grf>;
+                status = "disabled";
+
+                ports {
+                        hdmi_in: port {
+                                hdmi_in_vop: endpoint {
+                                        remote-endpoint = <&vop_out_hdmi>;
+                                };
+                        };
+                };
+        };
+
+        hdmiphy: phy@ff430000 {
+                compatible = "rockchip,rk3328-hdmi-phy";
+                reg = <0x0 0xff430000 0x0 0x10000>;
+                interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;
+                clock-names = "sysclk", "refoclk", "refpclk";
+                clock-output-names = "hdmi_phy";
+                #clock-cells = <0>;
+                nvmem-cells = <&efuse_cpu_version>;
+                nvmem-cell-names = "cpu-version";
+                #phy-cells = <0>;
+                status = "disabled";
+        };
+
         cru: clock-controller@ff440000 {
                 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
                 reg = <0x0 0xff440000 0x0 0x1000>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
index 8978d924eb83..cce266da28cd 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
@@ -7,8 +7,7 @@
  */
 
 /dts-v1/;
-#include "rk3399.dtsi"
-#include "rk3399-opp.dtsi"
+#include "rk3399-rock960.dtsi"
 
 / {
         model = "96boards RK3399 Ficus";
@@ -24,97 +23,6 @@
                 clock-output-names = "clkin_gmac";
                 #clock-cells = <0>;
         };
-
-        vcc1v8_s0: vcc1v8-s0 {
-                compatible = "regulator-fixed";
-                regulator-name = "vcc1v8_s0";
-                regulator-min-microvolt = <1800000>;
-                regulator-max-microvolt = <1800000>;
-                regulator-always-on;
-        };
-
-        vcc_sys: vcc-sys {
-                compatible = "regulator-fixed";
-                regulator-name = "vcc_sys";
-                regulator-min-microvolt = <5000000>;
-                regulator-max-microvolt = <5000000>;
-                regulator-always-on;
-        };
-
-        vcc3v3_sys: vcc3v3-sys {
-                compatible = "regulator-fixed";
-                regulator-name = "vcc3v3_sys";
-                regulator-min-microvolt = <3300000>;
-                regulator-max-microvolt = <3300000>;
-                regulator-always-on;
-                vin-supply = <&vcc_sys>;
-        };
-
-        vcc3v3_pcie: vcc3v3-pcie-regulator {
-                compatible = "regulator-fixed";
-                enable-active-high;
-                gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>;
-                pinctrl-names = "default";
-                pinctrl-0 = <&pcie_drv>;
-                regulator-boot-on;
-                regulator-name = "vcc3v3_pcie";
-                regulator-min-microvolt = <3300000>;
-                regulator-max-microvolt = <3300000>;
-                vin-supply = <&vcc3v3_sys>;
-        };
-
-        vcc5v0_host: vcc5v0-host-regulator {
-                compatible = "regulator-fixed";
-                enable-active-high;
-                gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
-                pinctrl-names = "default";
-                pinctrl-0 = <&host_vbus_drv>;
-                regulator-name = "vcc5v0_host";
-                regulator-min-microvolt = <5000000>;
-                regulator-max-microvolt = <5000000>;
-                regulator-always-on;
-                vin-supply = <&vcc_sys>;
-        };
-
-        vdd_log: vdd-log {
-                compatible = "pwm-regulator";
-                pwms = <&pwm2 0 25000 0>;
-                regulator-name = "vdd_log";
-                regulator-min-microvolt = <800000>;
-                regulator-max-microvolt = <1400000>;
-                regulator-always-on;
-                regulator-boot-on;
-                vin-supply = <&vcc_sys>;
-        };
-
-};
-
-&cpu_l0 {
-        cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l1 {
-        cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l2 {
-        cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_l3 {
-        cpu-supply = <&vdd_cpu_l>;
-};
-
-&cpu_b0 {
-        cpu-supply = <&vdd_cpu_b>;
-};
-
-&cpu_b1 {
-        cpu-supply = <&vdd_cpu_b>;
-};
-
-&emmc_phy {
-        status = "okay";
 };
 
 &gmac {
@@ -133,279 +41,8 @@
         status = "okay";
 };
 
-&hdmi {
-        ddc-i2c-bus = <&i2c3>;
-        pinctrl-names = "default";
-        pinctrl-0 = <&hdmi_cec>;
-        status = "okay";
-};
-
-&i2c0 {
-        clock-frequency = <400000>;
-        i2c-scl-rising-time-ns = <168>;
-        i2c-scl-falling-time-ns = <4>;
-        status = "okay";
-
-        vdd_cpu_b: regulator@40 {
-                compatible = "silergy,syr827";
-                reg = <0x40>;
-                fcs,suspend-voltage-selector = <1>;
-                regulator-name = "vdd_cpu_b";
-                regulator-min-microvolt = <712500>;
-                regulator-max-microvolt = <1500000>;
-                regulator-ramp-delay = <1000>;
-                regulator-always-on;
-                regulator-boot-on;
-                vin-supply = <&vcc_sys>;
-                status = "okay";
-
-                regulator-state-mem {
-                        regulator-off-in-suspend;
-                };
-        };
-
-        vdd_gpu: regulator@41 {
-                compatible = "silergy,syr828";
-                reg = <0x41>;
-                fcs,suspend-voltage-selector = <1>;
-                regulator-name = "vdd_gpu";
-                regulator-min-microvolt = <712500>;
-                regulator-max-microvolt = <1500000>;
-                regulator-ramp-delay = <1000>;
-                regulator-always-on;
-                regulator-boot-on;
-                vin-supply = <&vcc_sys>;
-                regulator-state-mem {
-                        regulator-off-in-suspend;
-                };
-        };
-
-        rk808: pmic@1b {
-                compatible = "rockchip,rk808";
-                reg = <0x1b>;
-                interrupt-parent = <&gpio1>;
-                interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
-                pinctrl-names = "default";
-                pinctrl-0 = <&pmic_int_l>;
-                rockchip,system-power-controller;
-                wakeup-source;
-                #clock-cells = <1>;
-                clock-output-names = "xin32k", "rk808-clkout2";
-
-                vcc1-supply = <&vcc_sys>;
-                vcc2-supply = <&vcc_sys>;
-                vcc3-supply = <&vcc_sys>;
-                vcc4-supply = <&vcc_sys>;
-                vcc6-supply = <&vcc_sys>;
-                vcc7-supply = <&vcc_sys>;
-                vcc8-supply = <&vcc3v3_sys>;
-                vcc9-supply = <&vcc_sys>;
-                vcc10-supply = <&vcc_sys>;
-                vcc11-supply = <&vcc_sys>;
-                vcc12-supply = <&vcc3v3_sys>;
-                vddio-supply = <&vcc_1v8>;
-
-                regulators {
-                        vdd_center: DCDC_REG1 {
-                                regulator-name = "vdd_center";
-                                regulator-min-microvolt = <750000>;
-                                regulator-max-microvolt = <1350000>;
-                                regulator-always-on;
-                                regulator-boot-on;
-                                regulator-state-mem {
-                                        regulator-off-in-suspend;
-                                };
-                        };
-
-                        vdd_cpu_l: DCDC_REG2 {
-                                regulator-name = "vdd_cpu_l";
-                                regulator-min-microvolt = <750000>;
-                                regulator-max-microvolt = <1350000>;
-                                regulator-always-on;
-                                regulator-boot-on;
-                                regulator-state-mem {
-                                        regulator-off-in-suspend;
-                                };
-                        };
-
-                        vcc_ddr: DCDC_REG3 {
-                                regulator-name = "vcc_ddr";
-                                regulator-always-on;
-                                regulator-boot-on;
-                                regulator-state-mem {
-                                        regulator-on-in-suspend;
-                                };
-                        };
-
-                        vcc_1v8: DCDC_REG4 {
-                                regulator-name = "vcc_1v8";
-                                regulator-min-microvolt = <1800000>;
-                                regulator-max-microvolt = <1800000>;
-                                regulator-always-on;
-                                regulator-boot-on;
-                                regulator-state-mem {
-                                        regulator-on-in-suspend;
-                                        regulator-suspend-microvolt = <1800000>;
-                                };
-                        };
-
-                        vcc1v8_dvp: LDO_REG1 {
-                                regulator-name = "vcc1v8_dvp";
-                                regulator-min-microvolt = <1800000>;
-                                regulator-max-microvolt = <1800000>;
-                                regulator-always-on;
-                                regulator-boot-on;
-                                regulator-state-mem {
-                                        regulator-on-in-suspend;
-                                        regulator-suspend-microvolt = <1800000>;
-                                };
-                        };
-
-                        vcca1v8_hdmi: LDO_REG2 {
-                                regulator-name = "vcca1v8_hdmi";
-                                regulator-min-microvolt = <1800000>;
-                                regulator-max-microvolt = <1800000>;
-                                regulator-always-on;
-                                regulator-boot-on;
-                                regulator-state-mem {
-                                        regulator-on-in-suspend;
-                                        regulator-suspend-microvolt = <1800000>;
-                                };
-                        };
-
-                        vcca_1v8: LDO_REG3 {
-                                regulator-name = "vcca_1v8";
-                                regulator-min-microvolt = <1800000>;
-                                regulator-max-microvolt = <1800000>;
-                                regulator-always-on;
-                                regulator-boot-on;
-                                regulator-state-mem {
-                                        regulator-on-in-suspend;
-                                        regulator-suspend-microvolt = <1800000>;
-                                };
-                        };
-
-                        vcc_sd: LDO_REG4 {
-                                regulator-name = "vcc_sd";
-                                regulator-min-microvolt = <1800000>;
-                                regulator-max-microvolt = <3300000>;
-                                regulator-always-on;
-                                regulator-boot-on;
-                                regulator-state-mem {
-                                        regulator-on-in-suspend;
-                                        regulator-suspend-microvolt = <3300000>;
-                                };
-                        };
-
-                        vcc3v0_sd: LDO_REG5 {
-                                regulator-name = "vcc3v0_sd";
-                                regulator-min-microvolt = <3000000>;
-                                regulator-max-microvolt = <3000000>;
-                                regulator-always-on;
-                                regulator-boot-on;
-                                regulator-state-mem {
-                                        regulator-on-in-suspend;
-                                        regulator-suspend-microvolt = <3000000>;
-                                };
-                        };
-
-                        vcc_1v5: LDO_REG6 {
-                                regulator-name = "vcc_1v5";
-                                regulator-min-microvolt = <1500000>;
-                                regulator-max-microvolt = <1500000>;
-                                regulator-always-on;
-                                regulator-boot-on;
-                                regulator-state-mem {
-                                        regulator-on-in-suspend;
-                                        regulator-suspend-microvolt = <1500000>;
-                                };
-                        };
-
-                        vcca0v9_hdmi: LDO_REG7 {
-                                regulator-name = "vcca0v9_hdmi";
-                                regulator-min-microvolt = <900000>;
-                                regulator-max-microvolt = <900000>;
-                                regulator-always-on;
-                                regulator-boot-on;
-                                regulator-state-mem {
-                                        regulator-on-in-suspend;
-                                        regulator-suspend-microvolt = <900000>;
-                                };
-                        };
-
-                        vcc_3v0: LDO_REG8 {
-                                regulator-name = "vcc_3v0";
-                                regulator-min-microvolt = <3000000>;
-                                regulator-max-microvolt = <3000000>;
-                                regulator-always-on;
-                                regulator-boot-on;
-                                regulator-state-mem {
-                                        regulator-on-in-suspend;
-                                        regulator-suspend-microvolt = <3000000>;
-                                };
-                        };
-
-                        vcc3v3_s3: SWITCH_REG1 {
-                                regulator-name = "vcc3v3_s3";
-                                regulator-always-on;
-                                regulator-boot-on;
-                                regulator-state-mem {
-                                        regulator-on-in-suspend;
-                                };
-                        };
-
-                        vcc3v3_s0: SWITCH_REG2 {
-                                regulator-name = "vcc3v3_s0";
-                                regulator-always-on;
-                                regulator-boot-on;
-                                regulator-state-mem {
-                                        regulator-on-in-suspend;
-                                };
-                        };
-                };
-        };
-};
-
-&i2c1 {
-        status = "okay";
-};
-
-&i2c2 {
-        status = "okay";
-};
-
-&i2c3 {
-        status = "okay";
-};
-
-&i2c4 {
-        status = "okay";
-};
-
-&io_domains {
-        bt656-supply = <&vcc1v8_s0>; /* bt656_gpio2ab_ms */
-        audio-supply = <&vcc1v8_s0>; /* audio_gpio3d4a_ms */
-        sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */
-        gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */
-        status = "okay";
-};
-
-&pcie_phy {
-        status = "okay";
-};
-
 &pcie0 {
         ep-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>;
-        num-lanes = <4>;
-        pinctrl-names = "default";
-        pinctrl-0 = <&pcie_clkreqn_cpm>;
-        vpcie3v3-supply = <&vcc3v3_pcie>;
-        status = "okay";
-};
-
-&pmu_io_domains {
-        pmu1830-supply = <&vcc_1v8>;
-        status = "okay";
 };
 
 &pinctrl {
@@ -416,31 +53,6 @@
                 };
         };
 
-        sdmmc {
-                sdmmc_bus1: sdmmc-bus1 {
-                        rockchip,pins =
-                                <4 8 RK_FUNC_1 &pcfg_pull_up_8ma>;
-                };
-
-                sdmmc_bus4: sdmmc-bus4 {
-                        rockchip,pins =
-                                <4 8 RK_FUNC_1 &pcfg_pull_up_8ma>,
-                                <4 9 RK_FUNC_1 &pcfg_pull_up_8ma>,
-                                <4 10 RK_FUNC_1 &pcfg_pull_up_8ma>,
-                                <4 11 RK_FUNC_1 &pcfg_pull_up_8ma>;
-                };
-
-                sdmmc_clk: sdmmc-clk {
-                        rockchip,pins =
-                                <4 12 RK_FUNC_1 &pcfg_pull_none_18ma>;
-                };
-
-                sdmmc_cmd: sdmmc-cmd {
-                        rockchip,pins =
-                                <4 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
-                };
-        };
-
         pcie {
                 pcie_drv: pcie-drv {
                         rockchip,pins =
@@ -448,23 +60,6 @@
                         };
         };
 
-        pmic {
-                pmic_int_l: pmic-int-l {
-                        rockchip,pins =
-                                <1 21 RK_FUNC_GPIO &pcfg_pull_up>;
-                };
-
-                vsel1_gpio: vsel1-gpio {
-                        rockchip,pins =
-                                <1 17 RK_FUNC_GPIO &pcfg_pull_down>;
-                };
-
-                vsel2_gpio: vsel2-gpio {
-                        rockchip,pins =
-                                <1 14 RK_FUNC_GPIO &pcfg_pull_down>;
-                };
-        };
-
         usb2 {
                 host_vbus_drv: host-vbus-drv {
                         rockchip,pins =
@@ -473,127 +68,18 @@
         };
 };
 
-&pwm2 {
-        status = "okay";
-};
-
-&pwm3 {
-        status = "okay";
-};
-
-&sdhci {
-        bus-width = <8>;
-        mmc-hs400-1_8v;
-        mmc-hs400-enhanced-strobe;
-        non-removable;
-        status = "okay";
-};
-
-&sdmmc {
-        bus-width = <4>;
-        cap-mmc-highspeed;
-        cap-sd-highspeed;
-        clock-frequency = <100000000>;
-        clock-freq-min-max = <100000 100000000>;
-        disable-wp;
-        sd-uhs-sdr104;
-        vqmmc-supply = <&vcc_sd>;
-        card-detect-delay = <800>;
-        pinctrl-names = "default";
-        pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
-        status = "okay";
-};
-
-&tcphy0 {
-        status = "okay";
-};
-
-&tcphy1 {
-        status = "okay";
-};
-
-&u2phy0 {
-        status = "okay";
-};
-
-&u2phy1 {
-        status = "okay";
-};
-
-&u2phy0_host {
-        phy-supply = <&vcc5v0_host>;
-        status = "okay";
-};
-
-&u2phy1_host {
-        phy-supply = <&vcc5v0_host>;
-        status = "okay";
-};
-
-&u2phy0_otg {
-        status = "okay";
-};
-
-&u2phy1_otg {
-        status = "okay";
-};
-
-&uart0 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&uart0_xfer &uart0_cts>;
-        status = "okay";
-};
-
-&uart2 {
-        status = "okay";
-};
-
-&usb_host0_ehci {
-        status = "okay";
-};
-
-&usb_host0_ohci {
-        status = "okay";
-};
-
-&usb_host1_ehci {
-        status = "okay";
-};
-
-&usb_host1_ohci {
-        status = "okay";
-};
-
-&usbdrd3_0 {
-        status = "okay";
-};
-
 &usbdrd_dwc3_0 {
-        status = "okay";
         dr_mode = "host";
 };
 
-&usbdrd3_1 {
-        status = "okay";
-};
-
 &usbdrd_dwc3_1 {
-        status = "okay";
         dr_mode = "host";
 };
 
-&vopb {
-        status = "okay";
-};
-
-&vopb_mmu {
-        status = "okay";
-};
-
-&vopl {
-        status = "okay";
+&vcc3v3_pcie {
+        gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>;
 };
 
-&vopl_mmu {
-        status = "okay";
+&vcc5v0_host {
+        gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
 };
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
index 38336ab57cc4..c706db0ee9ec 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
@@ -622,6 +622,12 @@
                 };
         };
 
+        wifi {
+                wifi_host_wake_l: wifi-host-wake-l {
+                        rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+                };
+        };
+
         leds {
                 work_led_gpio: work_led-gpio {
                         rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -646,6 +652,36 @@
         status = "okay";
 };
 
+&sdio0 {
+        /* WiFi & BT combo module Ampak AP6356S */
+        bus-width = <4>;
+        cap-sdio-irq;
+        cap-sd-highspeed;
+        keep-power-in-suspend;
+        mmc-pwrseq = <&sdio_pwrseq>;
+        non-removable;
+        num-slots = <1>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
+        sd-uhs-sdr104;
+
+        /* Power supply */
+        vqmmc-supply = &vcc1v8_s3;      /* IO line */
+        vmmc-supply = &vcc_sdio;        /* card's power */
+
+        status = "okay";
+
+        brcmf: wifi@1 {
+                compatible = "brcm,bcm4329-fmac";
+                interrupt-parent = <&gpio0>;
+                interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
+                interrupt-names = "host-wake";
+                brcm,drive-strength = <5>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&wifi_host_wake_l>;
+        };
+};
+
 &sdmmc {
         bus-width = <4>;
         cap-mmc-highspeed;
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts
index e0d64f862322..2dceeea29b83 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts
@@ -131,7 +131,7 @@
         status = "okay";
         clock-frequency = <400000>;
 
-        sgtl5000: codec@0a {
+        sgtl5000: codec@a {
                 compatible = "fsl,sgtl5000";
                 reg = <0x0a>;
                 clocks = <&sgtl5000_clk>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts
new file mode 100644
index 000000000000..19f7732d728c
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dts
@@ -0,0 +1,680 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
+ */
+
+/dts-v1/;
+#include <dt-bindings/pwm/pwm.h>
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+        model = "Firefly ROC-RK3399-PC Board";
+        compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399";
+
+        chosen {
+                stdout-path = "serial2:1500000n8";
+        };
+
+        backlight: backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm0 0 25000 0>;
+        };
+
+        clkin_gmac: external-gmac-clock {
+                compatible = "fixed-clock";
+                clock-frequency = <125000000>;
+                clock-output-names = "clkin_gmac";
+                #clock-cells = <0>;
+        };
+
+        sdio_pwrseq: sdio-pwrseq {
+                compatible = "mmc-pwrseq-simple";
+                clocks = <&rk808 1>;
+                clock-names = "ext_clock";
+                pinctrl-names = "default";
+                pinctrl-0 = <&wifi_enable_h>;
+
+                /*
+                 * On the module itself this is one of these (depending
+                 * on the actual card populated):
+                 * - SDIO_RESET_L_WL_REG_ON
+                 * - PDN (power down when low)
+                 */
+                reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+        };
+
+        vcc_vbus_typec0: vcc-vbus-typec0 {
+                compatible = "regulator-fixed";
+                regulator-name = "vcc_vbus_typec0";
+                regulator-always-on;
+                regulator-boot-on;
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+        };
+
+        /*
+         * should be placed inside mp8859, but not until mp8859 has
+         * its own dt-binding.
+         */
+        vcc12v_sys: mp8859-dcdc1 {
+                compatible = "regulator-fixed";
+                regulator-name = "vcc12v_sys";
+                regulator-always-on;
+                regulator-boot-on;
+                regulator-min-microvolt = <12000000>;
+                regulator-max-microvolt = <12000000>;
+                vin-supply = <&vcc_vbus_typec0>;
+        };
+
+        /* switched by pmic_sleep */
+        vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
+                compatible = "regulator-fixed";
+                regulator-name = "vcc1v8_s3";
+                regulator-always-on;
+                regulator-boot-on;
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                vin-supply = <&vcc_1v8>;
+        };
+
+        vcc3v3_sys: vcc3v3-sys {
+                compatible = "regulator-fixed";
+                regulator-name = "vcc3v3_sys";
+                regulator-always-on;
+                regulator-boot-on;
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                vin-supply = <&vcc12v_sys>;
+        };
+
+        /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */
+        vcc5v0_host: vcc5v0-host-regulator {
+                compatible = "regulator-fixed";
+                enable-active-high;
+                gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&vcc5v0_host_en &hub_rst>;
+                regulator-name = "vcc5v0_host";
+                regulator-always-on;
+                vin-supply = <&vcc_sys>;
+        };
+
+        vcc_vbus_typec1: vcc-vbus-typec1 {
+                compatible = "regulator-fixed";
+                enable-active-high;
+                gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&vcc_vbus_typec1_en>;
+                regulator-name = "vcc_vbus_typec1";
+                regulator-always-on;
+                vin-supply = <&vcc_sys>;
+        };
+
+        vcc_sys: vcc-sys {
+                compatible = "regulator-fixed";
+                regulator-name = "vcc_sys";
+                regulator-always-on;
+                regulator-boot-on;
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                vin-supply = <&vcc12v_sys>;
+        };
+
+        vdd_log: vdd-log {
+                compatible = "pwm-regulator";
+                pwms = <&pwm2 0 25000 1>;
+                regulator-name = "vdd_log";
+                regulator-always-on;
+                regulator-boot-on;
+                regulator-min-microvolt = <800000>;
+                regulator-max-microvolt = <1400000>;
+                vin-supply = <&vcc3v3_sys>;
+        };
+};
+
+&cpu_l0 {
+        cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+        cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+        cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+        cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+        cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+        cpu-supply = <&vdd_cpu_b>;
+};
+
+&emmc_phy {
+        status = "okay";
+};
+
+&gmac {
+        assigned-clocks = <&cru SCLK_RMII_SRC>;
+        assigned-clock-parents = <&clkin_gmac>;
+        clock_in_out = "input";
+        phy-supply = <&vcc_lan>;
+        phy-mode = "rgmii";
+        pinctrl-names = "default";
+        pinctrl-0 = <&rgmii_pins>;
+        snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+        snps,reset-active-low;
+        snps,reset-delays-us = <0 10000 50000>;
+        tx_delay = <0x28>;
+        rx_delay = <0x11>;
+        status = "okay";
+};
+
+&hdmi {
+        ddc-i2c-bus = <&i2c3>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&hdmi_cec>;
+        status = "okay";
+};
+
+&i2c0 {
+        clock-frequency = <400000>;
+        i2c-scl-rising-time-ns = <168>;
+        i2c-scl-falling-time-ns = <4>;
+        status = "okay";
+
+        rk808: pmic@1b {
+                compatible = "rockchip,rk808";
+                reg = <0x1b>;
+                interrupt-parent = <&gpio1>;
+                interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+                #clock-cells = <1>;
+                clock-output-names = "xin32k", "rk808-clkout2";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pmic_int_l>;
+                rockchip,system-power-controller;
+                wakeup-source;
+
+                vcc1-supply = <&vcc3v3_sys>;
+                vcc2-supply = <&vcc3v3_sys>;
+                vcc3-supply = <&vcc3v3_sys>;
+                vcc4-supply = <&vcc3v3_sys>;
+                vcc6-supply = <&vcc3v3_sys>;
+                vcc7-supply = <&vcc3v3_sys>;
+                vcc8-supply = <&vcc3v3_sys>;
+                vcc9-supply = <&vcc3v3_sys>;
+                vcc10-supply = <&vcc3v3_sys>;
+                vcc11-supply = <&vcc3v3_sys>;
+                vcc12-supply = <&vcc3v3_sys>;
+                vddio-supply = <&vcc1v8_pmu>;
+
+                regulators {
+                        vdd_center: DCDC_REG1 {
+                                regulator-name = "vdd_center";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <750000>;
+                                regulator-max-microvolt = <1350000>;
+                                regulator-ramp-delay = <6001>;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        vdd_cpu_l: DCDC_REG2 {
+                                regulator-name = "vdd_cpu_l";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <750000>;
+                                regulator-max-microvolt = <1350000>;
+                                regulator-ramp-delay = <6001>;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        vcc_ddr: DCDC_REG3 {
+                                regulator-name = "vcc_ddr";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                };
+                        };
+
+                        vcc_1v8: DCDC_REG4 {
+                                regulator-name = "vcc_1v8";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1800000>;
+                                };
+                        };
+
+                        vcca1v8_codec: LDO_REG1 {
+                                regulator-name = "vcca1v8_codec";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        vcc1v8_hdmi: LDO_REG2 {
+                                regulator-name = "vcc1v8_hdmi";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        vcc1v8_pmu: LDO_REG3 {
+                                regulator-name = "vcc1v8_pmu";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1800000>;
+                                };
+                        };
+
+                        vcc_sdio: LDO_REG4 {
+                                regulator-name = "vcc_sdio";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <3000000>;
+                                };
+                        };
+
+                        vcca3v0_codec: LDO_REG5 {
+                                regulator-name = "vcca3v0_codec";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        vcc_1v5: LDO_REG6 {
+                                regulator-name = "vcc_1v5";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1500000>;
+                                regulator-max-microvolt = <1500000>;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1500000>;
+                                };
+                        };
+
+                        vcca0v9_hdmi: LDO_REG7 {
+                                regulator-name = "vcca0v9_hdmi";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <900000>;
+                                regulator-max-microvolt = <900000>;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        vcc_3v0: LDO_REG8 {
+                                regulator-name = "vcc_3v0";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <3000000>;
+                                };
+                        };
+
+                        vcc3v3_s3: vcc_lan: SWITCH_REG1 {
+                                regulator-name = "vcc3v3_s3";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        vcc3v3_s0: SWITCH_REG2 {
+                                regulator-name = "vcc3v3_s0";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+                };
+        };
+
+        vdd_cpu_b: regulator@40 {
+                compatible = "silergy,syr827";
+                reg = <0x40>;
+                fcs,suspend-voltage-selector = <1>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&vsel1_gpio>;
+                regulator-name = "vdd_cpu_b";
+                regulator-min-microvolt = <712500>;
+                regulator-max-microvolt = <1500000>;
+                regulator-ramp-delay = <1000>;
+                regulator-always-on;
+                regulator-boot-on;
+                vin-supply = <&vcc3v3_sys>;
+
+                regulator-state-mem {
+                        regulator-off-in-suspend;
+                };
+        };
+
+        vdd_gpu: regulator@41 {
+                compatible = "silergy,syr828";
+                reg = <0x41>;
+                fcs,suspend-voltage-selector = <1>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&vsel2_gpio>;
+                regulator-name = "vdd_gpu";
+                regulator-min-microvolt = <712500>;
+                regulator-max-microvolt = <1500000>;
+                regulator-ramp-delay = <1000>;
+                regulator-always-on;
+                regulator-boot-on;
+                vin-supply = <&vcc3v3_sys>;
+
+                regulator-state-mem {
+                        regulator-off-in-suspend;
+                };
+        };
+};
+
+&i2c1 {
+        i2c-scl-rising-time-ns = <300>;
+        i2c-scl-falling-time-ns = <15>;
+        status = "okay";
+};
+
+&i2c3 {
+        i2c-scl-rising-time-ns = <450>;
+        i2c-scl-falling-time-ns = <15>;
+        status = "okay";
+};
+
+&i2c4 {
+        i2c-scl-rising-time-ns = <600>;
+        i2c-scl-falling-time-ns = <20>;
+        status = "okay";
+
+        fusb1: usb-typec@22 {
+                compatible = "fcs,fusb302";
+                reg = <0x22>;
+                interrupt-parent = <&gpio1>;
+                interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&fusb1_int>;
+                vbus-supply = <&vcc_vbus_typec1>;
+                status = "okay";
+        };
+};
+
+&i2c7 {
+        i2c-scl-rising-time-ns = <600>;
+        i2c-scl-falling-time-ns = <20>;
+        status = "okay";
+
+        fusb0: usb-typec@22 {
+                compatible = "fcs,fusb302";
+                reg = <0x22>;
+                interrupt-parent = <&gpio1>;
+                interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&fusb0_int>;
+                vbus-supply = <&vcc_vbus_typec0>;
+                status = "okay";
+        };
+};
+
+&i2s0 {
+        rockchip,playback-channels = <8>;
+        rockchip,capture-channels = <8>;
+        status = "okay";
+};
+
+&i2s1 {
+        rockchip,playback-channels = <2>;
+        rockchip,capture-channels = <2>;
+        status = "okay";
+};
+
+&i2s2 {
+        status = "okay";
+};
+
+&io_domains {
+        audio-supply = <&vcca1v8_codec>;
+        bt656-supply = <&vcc_3v0>;
+        gpio1830-supply = <&vcc_3v0>;
+        sdmmc-supply = <&vcc_sdio>;
+        status = "okay";
+};
+
+&pmu_io_domains {
+        pmu1830-supply = <&vcc_3v0>;
+        status = "okay";
+};
+
+&pinctrl {
+        lcd-panel {
+                lcd_panel_reset: lcd-panel-reset {
+                        rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
+                };
+        };
+
+        pmic {
+                vsel1_gpio: vsel1-gpio {
+                        rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
+                };
+
+                vsel2_gpio: vsel2-gpio {
+                        rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+                };
+        };
+
+        sdio-pwrseq {
+                wifi_enable_h: wifi-enable-h {
+                        rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+                };
+        };
+
+        pmic {
+                pmic_int_l: pmic-int-l {
+                        rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+                };
+        };
+
+        usb2 {
+                vcc5v0_host_en: vcc5v0-host-en {
+                        rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+                };
+
+                hub_rst: hub-rst {
+                        rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_output_high>;
+                };
+        };
+
+        usb-typec {
+                vcc_vbus_typec1_en: vcc-vbus-typec1-en {
+                        rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+                };
+        };
+
+        fusb30x {
+                fusb0_int: fusb0-int {
+                        rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+                };
+
+                fusb1_int: fusb1-int {
+                        rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
+                };
+        };
+};
+
+&pwm0 {
+        status = "okay";
+};
+
+&pwm2 {
+        status = "okay";
+};
+
+&saradc {
+        vref-supply = <&vcca1v8_s3>;
+        status = "okay";
+};
+
+&sdmmc {
+        bus-width = <4>;
+        cap-mmc-highspeed;
+        cap-sd-highspeed;
+        cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+        disable-wp;
+        max-frequency = <150000000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
+        status = "okay";
+};
+
+&sdhci {
+        bus-width = <8>;
+        mmc-hs400-1_8v;
+        mmc-hs400-enhanced-strobe;
+        non-removable;
+        status = "okay";
+};
+
+&tcphy0 {
+        status = "okay";
+};
+
+&tcphy1 {
+        status = "okay";
+};
+
+&tsadc {
+        /* tshut mode 0:CRU 1:GPIO */
+        rockchip,hw-tshut-mode = <1>;
+        /* tshut polarity 0:LOW 1:HIGH */
+        rockchip,hw-tshut-polarity = <1>;
+        status = "okay";
+};
+
+&u2phy0 {
+        status = "okay";
+
+        u2phy0_otg: otg-port {
+                phy-supply = <&vcc_vbus_typec0>;
+                status = "okay";
+        };
+
+        u2phy0_host: host-port {
+                phy-supply = <&vcc5v0_host>;
+                status = "okay";
+        };
+};
+
+&u2phy1 {
+        status = "okay";
+
+        u2phy1_otg: otg-port {
+                phy-supply = <&vcc_vbus_typec1>;
+                status = "okay";
+        };
+
+        u2phy1_host: host-port {
+                phy-supply = <&vcc5v0_host>;
+                status = "okay";
+        };
+};
+
+&uart0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart0_xfer &uart0_cts>;
+        status = "okay";
+};
+
+&uart2 {
+        status = "okay";
+};
+
+&usb_host0_ehci {
+        status = "okay";
+};
+
+&usb_host0_ohci {
+        status = "okay";
+};
+
+&usb_host1_ehci {
+        status = "okay";
+};
+
+&usb_host1_ohci {
+        status = "okay";
+};
+
+&usbdrd3_0 {
+        status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+        status = "okay";
+};
+
+&usbdrd3_1 {
+        status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+        status = "okay";
+        dr_mode = "host";
+};
+
+&vopb {
+        status = "okay";
+};
+
+&vopb_mmu {
+        status = "okay";
+};
+
+&vopl {
+        status = "okay";
+};
+
+&vopl_mmu {
+        status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
new file mode 100644
index 000000000000..3c3308daec98
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Linaro Ltd.
+ */
+
+/dts-v1/;
+#include "rk3399-rock960.dtsi"
+
+/ {
+        model = "96boards Rock960";
+        compatible = "vamrs,rock960", "rockchip,rk3399";
+
+        chosen {
+                stdout-path = "serial2:1500000n8";
+        };
+};
+
+&pcie0 {
+        ep-gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>;
+};
+
+&pinctrl {
+        pcie {
+                pcie_drv: pcie-drv {
+                        rockchip,pins =
+                                <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+                        };
+        };
+
+        usb2 {
+                host_vbus_drv: host-vbus-drv {
+                        rockchip,pins =
+                                <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+                };
+        };
+};
+
+&usbdrd_dwc3_0 {
+        dr_mode = "otg";
+};
+
+&usbdrd_dwc3_1 {
+        dr_mode = "host";
+};
+
+&vcc3v3_pcie {
+        gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>;
+};
+
+&vcc5v0_host {
+        gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
new file mode 100644
index 000000000000..6c8c4ab044aa
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
@@ -0,0 +1,542 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Collabora Ltd.
+ * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2018 Linaro Ltd.
+ */
+
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+        vcc1v8_s0: vcc1v8-s0 {
+                compatible = "regulator-fixed";
+                regulator-name = "vcc1v8_s0";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                regulator-always-on;
+        };
+
+        vcc_sys: vcc-sys {
+                compatible = "regulator-fixed";
+                regulator-name = "vcc_sys";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-always-on;
+        };
+
+        vcc3v3_sys: vcc3v3-sys {
+                compatible = "regulator-fixed";
+                regulator-name = "vcc3v3_sys";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+                vin-supply = <&vcc_sys>;
+        };
+
+        vcc3v3_pcie: vcc3v3-pcie-regulator {
+                compatible = "regulator-fixed";
+                enable-active-high;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pcie_drv>;
+                regulator-boot-on;
+                regulator-name = "vcc3v3_pcie";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                vin-supply = <&vcc3v3_sys>;
+        };
+
+        vcc5v0_host: vcc5v0-host-regulator {
+                compatible = "regulator-fixed";
+                enable-active-high;
+                pinctrl-names = "default";
+                pinctrl-0 = <&host_vbus_drv>;
+                regulator-name = "vcc5v0_host";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-always-on;
+                vin-supply = <&vcc_sys>;
+        };
+
+        vdd_log: vdd-log {
+                compatible = "pwm-regulator";
+                pwms = <&pwm2 0 25000 0>;
+                regulator-name = "vdd_log";
+                regulator-min-microvolt = <800000>;
+                regulator-max-microvolt = <1400000>;
+                regulator-always-on;
+                regulator-boot-on;
+                vin-supply = <&vcc_sys>;
+        };
+
+};
+
+&cpu_l0 {
+        cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+        cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+        cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+        cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+        cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+        cpu-supply = <&vdd_cpu_b>;
+};
+
+&emmc_phy {
+        status = "okay";
+};
+
+&hdmi {
+        ddc-i2c-bus = <&i2c3>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&hdmi_cec>;
+        status = "okay";
+};
+
+&i2c0 {
+        clock-frequency = <400000>;
+        i2c-scl-rising-time-ns = <168>;
+        i2c-scl-falling-time-ns = <4>;
+        status = "okay";
+
+        vdd_cpu_b: regulator@40 {
+                compatible = "silergy,syr827";
+                reg = <0x40>;
+                fcs,suspend-voltage-selector = <1>;
+                regulator-name = "vdd_cpu_b";
+                regulator-min-microvolt = <712500>;
+                regulator-max-microvolt = <1500000>;
+                regulator-ramp-delay = <1000>;
+                regulator-always-on;
+                regulator-boot-on;
+                vin-supply = <&vcc_sys>;
+                status = "okay";
+
+                regulator-state-mem {
+                        regulator-off-in-suspend;
+                };
+        };
+
+        vdd_gpu: regulator@41 {
+                compatible = "silergy,syr828";
+                reg = <0x41>;
+                fcs,suspend-voltage-selector = <1>;
+                regulator-name = "vdd_gpu";
+                regulator-min-microvolt = <712500>;
+                regulator-max-microvolt = <1500000>;
+                regulator-ramp-delay = <1000>;
+                regulator-always-on;
+                regulator-boot-on;
+                vin-supply = <&vcc_sys>;
+                regulator-state-mem {
+                        regulator-off-in-suspend;
+                };
+        };
+
+        rk808: pmic@1b {
+                compatible = "rockchip,rk808";
+                reg = <0x1b>;
+                interrupt-parent = <&gpio1>;
+                interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pmic_int_l>;
+                rockchip,system-power-controller;
+                wakeup-source;
+                #clock-cells = <1>;
+                clock-output-names = "xin32k", "rk808-clkout2";
+
+                vcc1-supply = <&vcc_sys>;
+                vcc2-supply = <&vcc_sys>;
+                vcc3-supply = <&vcc_sys>;
+                vcc4-supply = <&vcc_sys>;
+                vcc6-supply = <&vcc_sys>;
+                vcc7-supply = <&vcc_sys>;
+                vcc8-supply = <&vcc3v3_sys>;
+                vcc9-supply = <&vcc_sys>;
+                vcc10-supply = <&vcc_sys>;
+                vcc11-supply = <&vcc_sys>;
+                vcc12-supply = <&vcc3v3_sys>;
+                vddio-supply = <&vcc_1v8>;
+
+                regulators {
+                        vdd_center: DCDC_REG1 {
+                                regulator-name = "vdd_center";
+                                regulator-min-microvolt = <750000>;
+                                regulator-max-microvolt = <1350000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        vdd_cpu_l: DCDC_REG2 {
+                                regulator-name = "vdd_cpu_l";
+                                regulator-min-microvolt = <750000>;
+                                regulator-max-microvolt = <1350000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        vcc_ddr: DCDC_REG3 {
+                                regulator-name = "vcc_ddr";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                };
+                        };
+
+                        vcc_1v8: DCDC_REG4 {
+                                regulator-name = "vcc_1v8";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1800000>;
+                                };
+                        };
+
+                        vcc1v8_dvp: LDO_REG1 {
+                                regulator-name = "vcc1v8_dvp";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1800000>;
+                                };
+                        };
+
+                        vcca1v8_hdmi: LDO_REG2 {
+                                regulator-name = "vcca1v8_hdmi";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1800000>;
+                                };
+                        };
+
+                        vcca_1v8: LDO_REG3 {
+                                regulator-name = "vcca_1v8";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1800000>;
+                                };
+                        };
+
+                        vcc_sd: LDO_REG4 {
+                                regulator-name = "vcc_sd";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <3300000>;
+                                };
+                        };
+
+                        vcc3v0_sd: LDO_REG5 {
+                                regulator-name = "vcc3v0_sd";
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <3000000>;
+                                };
+                        };
+
+                        vcc_1v5: LDO_REG6 {
+                                regulator-name = "vcc_1v5";
+                                regulator-min-microvolt = <1500000>;
+                                regulator-max-microvolt = <1500000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1500000>;
+                                };
+                        };
+
+                        vcca0v9_hdmi: LDO_REG7 {
+                                regulator-name = "vcca0v9_hdmi";
+                                regulator-min-microvolt = <900000>;
+                                regulator-max-microvolt = <900000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <900000>;
+                                };
+                        };
+
+                        vcc_3v0: LDO_REG8 {
+                                regulator-name = "vcc_3v0";
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <3000000>;
+                                };
+                        };
+
+                        vcc3v3_s3: SWITCH_REG1 {
+                                regulator-name = "vcc3v3_s3";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                };
+                        };
+
+                        vcc3v3_s0: SWITCH_REG2 {
+                                regulator-name = "vcc3v3_s0";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                };
+                        };
+                };
+        };
+};
+
+&i2c1 {
+        status = "okay";
+};
+
+&i2c2 {
+        status = "okay";
+};
+
+&i2c3 {
+        status = "okay";
+};
+
+&i2c4 {
+        status = "okay";
+};
+
+&io_domains {
+        bt656-supply = <&vcc1v8_s0>; /* bt656_gpio2ab_ms */
+        audio-supply = <&vcc1v8_s0>; /* audio_gpio3d4a_ms */
+        sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */
+        gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */
+        status = "okay";
+};
+
+&pcie_phy {
+        status = "okay";
+};
+
+&pcie0 {
+        num-lanes = <4>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pcie_clkreqn_cpm>;
+        vpcie3v3-supply = <&vcc3v3_pcie>;
+        status = "okay";
+};
+
+&pmu_io_domains {
+        pmu1830-supply = <&vcc_1v8>;
+        status = "okay";
+};
+
+&pinctrl {
+        sdmmc {
+                sdmmc_bus1: sdmmc-bus1 {
+                        rockchip,pins =
+                                <4 8 RK_FUNC_1 &pcfg_pull_up_8ma>;
+                };
+
+                sdmmc_bus4: sdmmc-bus4 {
+                        rockchip,pins =
+                                <4 8 RK_FUNC_1 &pcfg_pull_up_8ma>,
+                                <4 9 RK_FUNC_1 &pcfg_pull_up_8ma>,
+                                <4 10 RK_FUNC_1 &pcfg_pull_up_8ma>,
+                                <4 11 RK_FUNC_1 &pcfg_pull_up_8ma>;
+                };
+
+                sdmmc_clk: sdmmc-clk {
+                        rockchip,pins =
+                                <4 12 RK_FUNC_1 &pcfg_pull_none_18ma>;
+                };
+
+                sdmmc_cmd: sdmmc-cmd {
+                        rockchip,pins =
+                                <4 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
+                };
+        };
+
+        pmic {
+                pmic_int_l: pmic-int-l {
+                        rockchip,pins =
+                                <1 21 RK_FUNC_GPIO &pcfg_pull_up>;
+                };
+
+                vsel1_gpio: vsel1-gpio {
+                        rockchip,pins =
+                                <1 17 RK_FUNC_GPIO &pcfg_pull_down>;
+                };
+
+                vsel2_gpio: vsel2-gpio {
+                        rockchip,pins =
+                                <1 14 RK_FUNC_GPIO &pcfg_pull_down>;
+                };
+        };
+};
+
+&pwm2 {
+        status = "okay";
+};
+
+&pwm3 {
+        status = "okay";
+};
+
+&sdhci {
+        bus-width = <8>;
+        mmc-hs400-1_8v;
+        mmc-hs400-enhanced-strobe;
+        non-removable;
+        status = "okay";
+};
+
+&sdmmc {
+        bus-width = <4>;
+        cap-mmc-highspeed;
+        cap-sd-highspeed;
+        clock-frequency = <100000000>;
+        clock-freq-min-max = <100000 100000000>;
+        cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
+        disable-wp;
+        sd-uhs-sdr104;
+        vqmmc-supply = <&vcc_sd>;
+        card-detect-delay = <800>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+        status = "okay";
+};
+
+&uart0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart0_xfer &uart0_cts>;
+        status = "okay";
+};
+
+&uart2 {
+        status = "okay";
+};
+
+&tcphy0 {
+        status = "okay";
+};
+
+&tcphy1 {
+        status = "okay";
+};
+
+&u2phy0 {
+        status = "okay";
+};
+
+&u2phy1 {
+        status = "okay";
+};
+
+&u2phy0_host {
+        phy-supply = <&vcc5v0_host>;
+        status = "okay";
+};
+
+&u2phy1_host {
+        phy-supply = <&vcc5v0_host>;
+        status = "okay";
+};
+
+&u2phy0_otg {
+        status = "okay";
+};
+
+&u2phy1_otg {
+        status = "okay";
+};
+
+&usb_host0_ehci {
+        status = "okay";
+};
+
+&usb_host0_ohci {
+        status = "okay";
+};
+
+&usb_host1_ehci {
+        status = "okay";
+};
+
+&usb_host1_ohci {
+        status = "okay";
+};
+
+&usbdrd3_0 {
+        status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+        status = "okay";
+};
+
+&usbdrd3_1 {
+        status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+        status = "okay";
+};
+
+&vopb {
+        status = "okay";
+};
+
+&vopb_mmu {
+        status = "okay";
+};
+
+&vopl {
+        status = "okay";
+};
+
+&vopl_mmu {
+        status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts
new file mode 100644
index 000000000000..1d35f5406b5e
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts
@@ -0,0 +1,692 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2018 Akash Gajjar <Akash_Gajjar@mentor.com>
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/pwm/pwm.h>
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+        model = "Pine64 RockPro64";
+        compatible = "pine64,rockpro64", "rockchip,rk3399";
+
+        chosen {
+                stdout-path = "serial2:1500000n8";
+        };
+
+        clkin_gmac: external-gmac-clock {
+                compatible = "fixed-clock";
+                clock-frequency = <125000000>;
+                clock-output-names = "clkin_gmac";
+                #clock-cells = <0>;
+        };
+
+        dc_12v: dc-12v {
+                compatible = "regulator-fixed";
+                regulator-name = "dc_12v";
+                regulator-always-on;
+                regulator-boot-on;
+                regulator-min-microvolt = <12000000>;
+                regulator-max-microvolt = <12000000>;
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                autorepeat;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pwrbtn>;
+
+                power {
+                        debounce-interval = <100>;
+                        gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
+                        label = "GPIO Key Power";
+                        linux,code = <KEY_POWER>;
+                        wakeup-source;
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&work_led_gpio>, <&diy_led_gpio>;
+
+                work-led {
+                        label = "work";
+                        default-state = "on";
+                        gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
+                };
+
+                diy-led {
+                        label = "diy";
+                        default-state = "off";
+                        gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
+                };
+        };
+
+        sdio_pwrseq: sdio-pwrseq {
+                compatible = "mmc-pwrseq-simple";
+                clocks = <&rk808 1>;
+                clock-names = "ext_clock";
+                pinctrl-names = "default";
+                pinctrl-0 = <&wifi_enable_h>;
+
+                /*
+                 * On the module itself this is one of these (depending
+                 * on the actual card populated):
+                 * - SDIO_RESET_L_WL_REG_ON
+                 * - PDN (power down when low)
+                 */
+                reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+        };
+
+        /* switched by pmic_sleep */
+        vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
+                compatible = "regulator-fixed";
+                regulator-name = "vcc1v8_s3";
+                regulator-always-on;
+                regulator-boot-on;
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                vin-supply = <&vcc_1v8>;
+        };
+
+        vcc3v3_pcie: vcc3v3-pcie-regulator {
+                compatible = "regulator-fixed";
+                enable-active-high;
+                gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pcie_pwr_en>;
+                regulator-name = "vcc3v3_pcie";
+                regulator-always-on;
+                regulator-boot-on;
+                vin-supply = <&dc_12v>;
+        };
+
+        vcc3v3_sys: vcc3v3-sys {
+                compatible = "regulator-fixed";
+                regulator-name = "vcc3v3_sys";
+                regulator-always-on;
+                regulator-boot-on;
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                vin-supply = <&vcc_sys>;
+        };
+
+        /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */
+        vcc5v0_host: vcc5v0-host-regulator {
+                compatible = "regulator-fixed";
+                enable-active-high;
+                gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&vcc5v0_host_en>;
+                regulator-name = "vcc5v0_host";
+                regulator-always-on;
+                vin-supply = <&vcc_sys>;
+        };
+
+        vcc5v0_typec: vcc5v0-typec-regulator {
+                compatible = "regulator-fixed";
+                enable-active-high;
+                gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&vcc5v0_typec_en>;
+                regulator-name = "vcc5v0_typec";
+                regulator-always-on;
+                vin-supply = <&vcc_sys>;
+        };
+
+        vcc_sys: vcc-sys {
+                compatible = "regulator-fixed";
+                regulator-name = "vcc_sys";
+                regulator-always-on;
+                regulator-boot-on;
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                vin-supply = <&dc_12v>;
+        };
+
+        vdd_log: vdd-log {
+                compatible = "pwm-regulator";
+                pwms = <&pwm2 0 25000 1>;
+                regulator-name = "vdd_log";
+                regulator-always-on;
+                regulator-boot-on;
+                regulator-min-microvolt = <800000>;
+                regulator-max-microvolt = <1400000>;
+                vin-supply = <&vcc_sys>;
+        };
+};
+
+&cpu_l0 {
+        cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+        cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+        cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+        cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+        cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+        cpu-supply = <&vdd_cpu_b>;
+};
+
+&emmc_phy {
+        status = "okay";
+};
+
+&gmac {
+        assigned-clocks = <&cru SCLK_RMII_SRC>;
+        assigned-clock-parents = <&clkin_gmac>;
+        clock_in_out = "input";
+        phy-supply = <&vcc_lan>;
+        phy-mode = "rgmii";
+        pinctrl-names = "default";
+        pinctrl-0 = <&rgmii_pins>;
+        snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+        snps,reset-active-low;
+        snps,reset-delays-us = <0 10000 50000>;
+        tx_delay = <0x28>;
+        rx_delay = <0x11>;
+        status = "okay";
+};
+
+&i2c0 {
+        clock-frequency = <400000>;
+        i2c-scl-rising-time-ns = <168>;
+        i2c-scl-falling-time-ns = <4>;
+        status = "okay";
+
+        rk808: pmic@1b {
+                compatible = "rockchip,rk808";
+                reg = <0x1b>;
+                interrupt-parent = <&gpio1>;
+                interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+                #clock-cells = <1>;
+                clock-output-names = "xin32k", "rk808-clkout2";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pmic_int_l>;
+                rockchip,system-power-controller;
+                wakeup-source;
+
+                vcc1-supply = <&vcc_sys>;
+                vcc2-supply = <&vcc_sys>;
+                vcc3-supply = <&vcc_sys>;
+                vcc4-supply = <&vcc_sys>;
+                vcc6-supply = <&vcc_sys>;
+                vcc7-supply = <&vcc_sys>;
+                vcc8-supply = <&vcc3v3_sys>;
+                vcc9-supply = <&vcc_sys>;
+                vcc10-supply = <&vcc_sys>;
+                vcc11-supply = <&vcc_sys>;
+                vcc12-supply = <&vcc3v3_sys>;
+                vddio-supply = <&vcc1v8_pmu>;
+
+                regulators {
+                        vdd_center: DCDC_REG1 {
+                                regulator-name = "vdd_center";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <750000>;
+                                regulator-max-microvolt = <1350000>;
+                                regulator-ramp-delay = <6001>;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        vdd_cpu_l: DCDC_REG2 {
+                                regulator-name = "vdd_cpu_l";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <750000>;
+                                regulator-max-microvolt = <1350000>;
+                                regulator-ramp-delay = <6001>;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        vcc_ddr: DCDC_REG3 {
+                                regulator-name = "vcc_ddr";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                };
+                        };
+
+                        vcc_1v8: DCDC_REG4 {
+                                regulator-name = "vcc_1v8";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1800000>;
+                                };
+                        };
+
+                        vcc1v8_dvp: LDO_REG1 {
+                                regulator-name = "vcc1v8_dvp";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        vcc2v8_dvp: LDO_REG2 {
+                                regulator-name = "vcc2v8_dvp";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        vcc1v8_pmu: LDO_REG3 {
+                                regulator-name = "vcc1v8_pmu";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1800000>;
+                                };
+                        };
+
+                        vcc_sdio: LDO_REG4 {
+                                regulator-name = "vcc_sdio";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <3000000>;
+                                };
+                        };
+
+                        vcca3v0_codec: LDO_REG5 {
+                                regulator-name = "vcca3v0_codec";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        vcc_1v5: LDO_REG6 {
+                                regulator-name = "vcc_1v5";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1500000>;
+                                regulator-max-microvolt = <1500000>;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <1500000>;
+                                };
+                        };
+
+                        vcca1v8_codec: LDO_REG7 {
+                                regulator-name = "vcca1v8_codec";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        vcc_3v0: LDO_REG8 {
+                                regulator-name = "vcc_3v0";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                        regulator-suspend-microvolt = <3000000>;
+                                };
+                        };
+
+                        vcc3v3_s3: vcc_lan: SWITCH_REG1 {
+                                regulator-name = "vcc3v3_s3";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        vcc3v3_s0: SWITCH_REG2 {
+                                regulator-name = "vcc3v3_s0";
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+                };
+        };
+
+        vdd_cpu_b: regulator@40 {
+                compatible = "silergy,syr827";
+                reg = <0x40>;
+                fcs,suspend-voltage-selector = <0>;
+                regulator-name = "vdd_cpu_b";
+                regulator-min-microvolt = <712500>;
+                regulator-max-microvolt = <1500000>;
+                regulator-ramp-delay = <1000>;
+                regulator-always-on;
+                regulator-boot-on;
+                vin-supply = <&vcc_sys>;
+
+                regulator-state-mem {
+                        regulator-off-in-suspend;
+                };
+        };
+
+        vdd_gpu: regulator@41 {
+                compatible = "silergy,syr828";
+                reg = <0x41>;
+                fcs,suspend-voltage-selector = <1>;
+                regulator-name = "vdd_gpu";
+                regulator-min-microvolt = <712500>;
+                regulator-max-microvolt = <1500000>;
+                regulator-ramp-delay = <1000>;
+                regulator-always-on;
+                regulator-boot-on;
+                vin-supply = <&vcc_sys>;
+
+                regulator-state-mem {
+                        regulator-off-in-suspend;
+                };
+        };
+};
+
+&i2c1 {
+        i2c-scl-rising-time-ns = <300>;
+        i2c-scl-falling-time-ns = <15>;
+        status = "okay";
+};
+
+&i2c3 {
+        i2c-scl-rising-time-ns = <450>;
+        i2c-scl-falling-time-ns = <15>;
+        status = "okay";
+};
+
+&i2c4 {
+        i2c-scl-rising-time-ns = <600>;
+        i2c-scl-falling-time-ns = <20>;
+        status = "okay";
+
+        fusb0: typec-portc@22 {
+                compatible = "fcs,fusb302";
+                reg = <0x22>;
+                interrupt-parent = <&gpio1>;
+                interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&fusb0_int>;
+                vbus-supply = <&vcc5v0_typec>;
+                status = "okay";
+        };
+};
+
+&i2s0 {
+        rockchip,playback-channels = <8>;
+        rockchip,capture-channels = <8>;
+        status = "okay";
+};
+
+&i2s1 {
+        rockchip,playback-channels = <2>;
+        rockchip,capture-channels = <2>;
+        status = "okay";
+};
+
+&i2s2 {
+        status = "okay";
+};
+
+&io_domains {
+        status = "okay";
+
+        bt656-supply = <&vcc1v8_dvp>;
+        audio-supply = <&vcca1v8_codec>;
+        sdmmc-supply = <&vcc_sdio>;
+        gpio1830-supply = <&vcc_3v0>;
+};
+
+&pmu_io_domains {
+        pmu1830-supply = <&vcc_3v0>;
+        status = "okay";
+};
+
+&pinctrl {
+        buttons {
+                pwrbtn: pwrbtn {
+                        rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+                };
+        };
+
+        fusb302x {
+                fusb0_int: fusb0-int {
+                        rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+                };
+        };
+
+        leds {
+                work_led_gpio: work_led-gpio {
+                        rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+                };
+
+                diy_led_gpio: diy_led-gpio {
+                        rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+                };
+        };
+
+        lcd-panel {
+                lcd_panel_reset: lcd-panel-reset {
+                        rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
+                };
+        };
+
+        pcie {
+                pcie_pwr_en: pcie-pwr-en {
+                        rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+                };
+        };
+
+        pmic {
+                pmic_int_l: pmic-int-l {
+                        rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+                };
+
+                vsel1_gpio: vsel1-gpio {
+                        rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
+                };
+
+                vsel2_gpio: vsel2-gpio {
+                        rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+                };
+        };
+
+        sdio-pwrseq {
+                wifi_enable_h: wifi-enable-h {
+                        rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+                };
+        };
+
+        usb-typec {
+                vcc5v0_typec_en: vcc5v0_typec_en {
+                        rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+                };
+        };
+
+        usb2 {
+                vcc5v0_host_en: vcc5v0-host-en {
+                        rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+                };
+        };
+};
+
+&pwm0 {
+        status = "okay";
+};
+
+&pwm2 {
+        status = "okay";
+};
+
+&saradc {
+        vref-supply = <&vcca1v8_s3>;
+        status = "okay";
+};
+
+&sdmmc {
+        bus-width = <4>;
+        cap-mmc-highspeed;
+        cap-sd-highspeed;
+        cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
+        disable-wp;
+        max-frequency = <150000000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
+        status = "okay";
+};
+
+&sdhci {
+        bus-width = <8>;
+        mmc-hs400-1_8v;
+        mmc-hs400-enhanced-strobe;
+        non-removable;
+        status = "okay";
+};
+
+&tcphy0 {
+        status = "okay";
+};
+
+&tcphy1 {
+        status = "okay";
+};
+
+&tsadc {
+        /* tshut mode 0:CRU 1:GPIO */
+        rockchip,hw-tshut-mode = <1>;
+        /* tshut polarity 0:LOW 1:HIGH */
+        rockchip,hw-tshut-polarity = <1>;
+        status = "okay";
+};
+
+&u2phy0 {
+        status = "okay";
+
+        u2phy0_otg: otg-port {
+                status = "okay";
+        };
+
+        u2phy0_host: host-port {
+                phy-supply = <&vcc5v0_host>;
+                status = "okay";
+        };
+};
+
+&u2phy1 {
+        status = "okay";
+
+        u2phy1_otg: otg-port {
+                status = "okay";
+        };
+
+        u2phy1_host: host-port {
+                phy-supply = <&vcc5v0_host>;
+                status = "okay";
+        };
+};
+
+&uart0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart0_xfer &uart0_cts>;
+        status = "okay";
+};
+
+&uart2 {
+        status = "okay";
+};
+
+&usb_host0_ehci {
+        status = "okay";
+};
+
+&usb_host0_ohci {
+        status = "okay";
+};
+
+&usb_host1_ehci {
+        status = "okay";
+};
+
+&usb_host1_ohci {
+        status = "okay";
+};
+
+&usbdrd3_0 {
+        status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+        status = "okay";
+        dr_mode = "otg";
+};
+
+&usbdrd3_1 {
+        status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+        status = "okay";
+        dr_mode = "host";
+};
+
+&vopb {
+        status = "okay";
+};
+
+&vopb_mmu {
+        status = "okay";
+};
+
+&vopl {
+        status = "okay";
+};
+
+&vopl_mmu {
+        status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
index 36b60791c156..5421e23760c3 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
@@ -93,6 +93,19 @@
                 vin-supply = <&vcc_1v8>;
         };
 
+        vcc3v0_sd: vcc3v0-sd {
+                compatible = "regulator-fixed";
+                enable-active-high;
+                gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&sdmmc0_pwr_h>;
+                regulator-always-on;
+                regulator-max-microvolt = <3000000>;
+                regulator-min-microvolt = <3000000>;
+                regulator-name = "vcc3v0_sd";
+                vin-supply = <&vcc3v3_sys>;
+        };
+
         vcc3v3_sys: vcc3v3-sys {
                 compatible = "regulator-fixed";
                 regulator-name = "vcc3v3_sys";
@@ -103,20 +116,10 @@
                 vin-supply = <&vcc_sys>;
         };
 
-        vcc_sys: vcc-sys {
-                compatible = "regulator-fixed";
-                regulator-name = "vcc_sys";
-                regulator-always-on;
-                regulator-boot-on;
-                regulator-min-microvolt = <5000000>;
-                regulator-max-microvolt = <5000000>;
-                vin-supply = <&dc_12v>;
-        };
-
         vcc5v0_host: vcc5v0-host-regulator {
                 compatible = "regulator-fixed";
                 enable-active-high;
-                gpio = <&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>;
+                gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&vcc5v0_host_en>;
                 regulator-name = "vcc5v0_host";
@@ -124,6 +127,26 @@
                 vin-supply = <&vcc_sys>;
         };
 
+        vcc5v0_typec0: vcc5v0-typec0-regulator {
+                compatible = "regulator-fixed";
+                enable-active-high;
+                gpio = <&gpio2 RK_PA0 GPIO_ACTIVE_HIGH>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&vcc5v0_typec0_en>;
+                regulator-name = "vcc5v0_typec0";
+                vin-supply = <&vcc_sys>;
+        };
+
+        vcc_sys: vcc-sys {
+                compatible = "regulator-fixed";
+                regulator-name = "vcc_sys";
+                regulator-always-on;
+                regulator-boot-on;
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                vin-supply = <&dc_12v>;
+        };
+
         vdd_log: vdd-log {
                 compatible = "pwm-regulator";
                 pwms = <&pwm2 0 25000 1>;
@@ -208,7 +231,7 @@
                 #clock-cells = <1>;
                 clock-output-names = "xin32k", "rk808-clkout2";
                 pinctrl-names = "default";
-                pinctrl-0 = <&pmic_int_l &pmic_dvs2>;
+                pinctrl-0 = <&pmic_int_l>;
                 rockchip,system-power-controller;
                 wakeup-source;
 
@@ -310,7 +333,7 @@
                                 regulator-always-on;
                                 regulator-boot-on;
                                 regulator-min-microvolt = <1800000>;
-                                regulator-max-microvolt = <3000000>;
+                                regulator-max-microvolt = <3300000>;
                                 regulator-state-mem {
                                         regulator-on-in-suspend;
                                         regulator-suspend-microvolt = <3000000>;
@@ -455,11 +478,6 @@
                                 <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
                 };
 
-                pmic_dvs2: pmic-dvs2 {
-                        rockchip,pins =
-                                <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
-                };
-
                 vsel1_gpio: vsel1-gpio {
                         rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
                 };
@@ -469,11 +487,22 @@
                 };
         };
 
+        sd {
+                sdmmc0_pwr_h: sdmmc0-pwr-h {
+                        rockchip,pins =
+                                <RK_GPIO0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+                };
+        };
+
         usb2 {
                 vcc5v0_host_en: vcc5v0-host-en {
                         rockchip,pins =
                                 <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
                 };
+                vcc5v0_typec0_en: vcc5v0-typec0-en {
+                        rockchip,pins =
+                                <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+                };
         };
 };
 
@@ -499,6 +528,7 @@
 };
 
 &sdmmc {
+        broken-cd;
         bus-width = <4>;
         cap-mmc-highspeed;
         cap-sd-highspeed;
@@ -507,6 +537,7 @@
         max-frequency = <150000000>;
         pinctrl-names = "default";
         pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+        vmmc-supply = <&vcc3v0_sd>;
         vqmmc-supply = <&vcc_sdio>;
         status = "okay";
 };
@@ -531,6 +562,7 @@
         status = "okay";
 
         u2phy0_otg: otg-port {
+                phy-supply = <&vcc5v0_typec0>;
                 status = "okay";
         };
 
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index c88e603396f6..99e7f65c1779 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -74,6 +74,7 @@
                         clocks = <&cru ARMCLKL>;
                         #cooling-cells = <2>; /* min followed by max */
                         dynamic-power-coefficient = <100>;
+                        cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
                 };
 
                 cpu_l1: cpu@1 {
@@ -84,6 +85,7 @@
                         clocks = <&cru ARMCLKL>;
                         #cooling-cells = <2>; /* min followed by max */
                         dynamic-power-coefficient = <100>;
+                        cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
                 };
 
                 cpu_l2: cpu@2 {
@@ -94,6 +96,7 @@
                         clocks = <&cru ARMCLKL>;
                         #cooling-cells = <2>; /* min followed by max */
                         dynamic-power-coefficient = <100>;
+                        cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
                 };
 
                 cpu_l3: cpu@3 {
@@ -104,6 +107,7 @@
                         clocks = <&cru ARMCLKL>;
                         #cooling-cells = <2>; /* min followed by max */
                         dynamic-power-coefficient = <100>;
+                        cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
                 };
 
                 cpu_b0: cpu@100 {
@@ -114,6 +118,7 @@
                         clocks = <&cru ARMCLKB>;
                         #cooling-cells = <2>; /* min followed by max */
                         dynamic-power-coefficient = <436>;
+                        cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
                 };
 
                 cpu_b1: cpu@101 {
@@ -124,6 +129,29 @@
                         clocks = <&cru ARMCLKB>;
                         #cooling-cells = <2>; /* min followed by max */
                         dynamic-power-coefficient = <436>;
+                        cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+                };
+
+                idle-states {
+                        entry-method = "psci";
+
+                        CPU_SLEEP: cpu-sleep {
+                                compatible = "arm,idle-state";
+                                local-timer-stop;
+                                arm,psci-suspend-param = <0x0010000>;
+                                entry-latency-us = <120>;
+                                exit-latency-us = <250>;
+                                min-residency-us = <900>;
+                        };
+
+                        CLUSTER_SLEEP: cluster-sleep {
+                                compatible = "arm,idle-state";
+                                local-timer-stop;
+                                arm,psci-suspend-param = <0x1010000>;
+                                entry-latency-us = <400>;
+                                exit-latency-us = <500>;
+                                min-residency-us = <2000>;
+                        };
                 };
         };
 
@@ -1720,6 +1748,8 @@
                 resets = <&cru SRST_P_MIPI_DSI0>;
                 reset-names = "apb";
                 rockchip,grf = <&grf>;
+                #address-cells = <1>;
+                #size-cells = <0>;
                 status = "disabled";
 
                 ports {
@@ -1754,6 +1784,8 @@
                 resets = <&cru SRST_P_MIPI_DSI1>;
                 reset-names = "apb";
                 rockchip,grf = <&grf>;
+                #address-cells = <1>;
+                #size-cells = <0>;
                 status = "disabled";
 
                 ports {
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
index d63b56e944de..31ba52b14e99 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
@@ -116,6 +116,28 @@
                 #size-cells = <1>;
                 ranges = <0 0 0 0xffffffff>;
 
+                spi0: spi@54006000 {
+                        compatible = "socionext,uniphier-scssi";
+                        status = "disabled";
+                        reg = <0x54006000 0x100>;
+                        interrupts = <0 39 4>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_spi0>;
+                        clocks = <&peri_clk 11>;
+                        resets = <&peri_rst 11>;
+                };
+
+                spi1: spi@54006100 {
+                        compatible = "socionext,uniphier-scssi";
+                        status = "disabled";
+                        reg = <0x54006100 0x100>;
+                        interrupts = <0 216 4>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_spi1>;
+                        clocks = <&peri_clk 11>;
+                        resets = <&peri_rst 11>;
+                };
+
                 serial0: serial@54006800 {
                         compatible = "socionext,uniphier-uart";
                         status = "disabled";
@@ -432,6 +454,8 @@
                                  <&mio_clk 12>;
                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
                                  <&mio_rst 12>;
+                        phy-names = "usb";
+                        phys = <&usb_phy0>;
                         has-transaction-translator;
                 };
 
@@ -446,6 +470,8 @@
                                  <&mio_clk 13>;
                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
                                  <&mio_rst 13>;
+                        phy-names = "usb";
+                        phys = <&usb_phy1>;
                         has-transaction-translator;
                 };
 
@@ -460,6 +486,8 @@
                                  <&mio_clk 14>;
                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
                                  <&mio_rst 14>;
+                        phy-names = "usb";
+                        phys = <&usb_phy2>;
                         has-transaction-translator;
                 };
 
@@ -488,6 +516,27 @@
                         pinctrl: pinctrl {
                                 compatible = "socionext,uniphier-ld11-pinctrl";
                         };
+
+                        usb-phy {
+                                compatible = "socionext,uniphier-ld11-usb2-phy";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                usb_phy0: phy@0 {
+                                        reg = <0>;
+                                        #phy-cells = <0>;
+                                };
+
+                                usb_phy1: phy@1 {
+                                        reg = <1>;
+                                        #phy-cells = <0>;
+                                };
+
+                                usb_phy2: phy@2 {
+                                        reg = <2>;
+                                        #phy-cells = <0>;
+                                };
+                        };
                 };
 
                 soc-glue@5f900000 {
@@ -571,7 +620,8 @@
                         interrupts = <0 65 4>;
                         pinctrl-names = "default";
                         pinctrl-0 = <&pinctrl_nand>;
-                        clocks = <&sys_clk 2>;
+                        clock-names = "nand", "nand_x", "ecc";
+                        clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
                         resets = <&sys_rst 2>;
                 };
         };
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts b/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts
index 1a5e7c24b901..d7ae28afef7d 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts
@@ -148,3 +148,7 @@
 &nand {
         status = "okay";
 };
+
+&usb {
+        status = "okay";
+};
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts
index 440c2e6a638b..406244a5c8e8 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts
@@ -75,3 +75,7 @@
                 drive-strength = <9>;
         };
 };
+
+&usb {
+        status = "okay";
+};
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
index caf112629caa..d7e2d8969601 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
@@ -224,6 +224,50 @@
                 #size-cells = <1>;
                 ranges = <0 0 0 0xffffffff>;
 
+                spi0: spi@54006000 {
+                        compatible = "socionext,uniphier-scssi";
+                        status = "disabled";
+                        reg = <0x54006000 0x100>;
+                        interrupts = <0 39 4>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_spi0>;
+                        clocks = <&peri_clk 11>;
+                        resets = <&peri_rst 11>;
+                };
+
+                spi1: spi@54006100 {
+                        compatible = "socionext,uniphier-scssi";
+                        status = "disabled";
+                        reg = <0x54006100 0x100>;
+                        interrupts = <0 216 4>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_spi1>;
+                        clocks = <&peri_clk 11>;
+                        resets = <&peri_rst 11>;
+                };
+
+                spi2: spi@54006200 {
+                        compatible = "socionext,uniphier-scssi";
+                        status = "disabled";
+                        reg = <0x54006200 0x100>;
+                        interrupts = <0 229 4>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_spi2>;
+                        clocks = <&peri_clk 11>;
+                        resets = <&peri_rst 11>;
+                };
+
+                spi3: spi@54006300 {
+                        compatible = "socionext,uniphier-scssi";
+                        status = "disabled";
+                        reg = <0x54006300 0x100>;
+                        interrupts = <0 230 4>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_spi3>;
+                        clocks = <&peri_clk 11>;
+                        resets = <&peri_rst 11>;
+                };
+
                 serial0: serial@54006800 {
                         compatible = "socionext,uniphier-uart";
                         status = "disabled";
@@ -528,6 +572,20 @@
                         cdns,phy-dll-delay-sdclk-hsmmc = <21>;
                 };
 
+                sd: sdhc@5a400000 {
+                        compatible = "socionext,uniphier-sd-v3.1.1";
+                        status = "disabled";
+                        reg = <0x5a400000 0x800>;
+                        interrupts = <0 76 4>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_sd>;
+                        clocks = <&sd_clk 0>;
+                        reset-names = "host";
+                        resets = <&sd_rst 0>;
+                        bus-width = <4>;
+                        cap-sd-highspeed;
+                };
+
                 soc_glue: soc-glue@5f800000 {
                         compatible = "socionext,uniphier-ld20-soc-glue",
                                      "simple-mfd", "syscon";
@@ -553,6 +611,50 @@
                         efuse@200 {
                                 compatible = "socionext,uniphier-efuse";
                                 reg = <0x200 0x68>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+
+                                /* USB cells */
+                                usb_rterm0: trim@54,4 {
+                                        reg = <0x54 1>;
+                                        bits = <4 2>;
+                                };
+                                usb_rterm1: trim@55,4 {
+                                        reg = <0x55 1>;
+                                        bits = <4 2>;
+                                };
+                                usb_rterm2: trim@58,4 {
+                                        reg = <0x58 1>;
+                                        bits = <4 2>;
+                                };
+                                usb_rterm3: trim@59,4 {
+                                        reg = <0x59 1>;
+                                        bits = <4 2>;
+                                };
+                                usb_sel_t0: trim@54,0 {
+                                        reg = <0x54 1>;
+                                        bits = <0 4>;
+                                };
+                                usb_sel_t1: trim@55,0 {
+                                        reg = <0x55 1>;
+                                        bits = <0 4>;
+                                };
+                                usb_sel_t2: trim@58,0 {
+                                        reg = <0x58 1>;
+                                        bits = <0 4>;
+                                };
+                                usb_sel_t3: trim@59,0 {
+                                        reg = <0x59 1>;
+                                        bits = <0 4>;
+                                };
+                                usb_hs_i0: trim@56,0 {
+                                        reg = <0x56 1>;
+                                        bits = <0 4>;
+                                };
+                                usb_hs_i2: trim@5a,0 {
+                                        reg = <0x5a 1>;
+                                        bits = <0 4>;
+                                };
                         };
                 };
 
@@ -620,6 +722,156 @@
                         };
                 };
 
+                usb: usb@65a00000 {
+                        compatible = "socionext,uniphier-dwc3", "snps,dwc3";
+                        status = "disabled";
+                        reg = <0x65a00000 0xcd00>;
+                        interrupt-names = "host";
+                        interrupts = <0 134 4>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
+                                    <&pinctrl_usb2>, <&pinctrl_usb3>;
+                        clock-names = "ref", "bus_early", "suspend";
+                        clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>;
+                        resets = <&usb_rst 15>;
+                        phys = <&usb_hsphy0>, <&usb_hsphy1>,
+                               <&usb_hsphy2>, <&usb_hsphy3>,
+                               <&usb_ssphy0>, <&usb_ssphy1>;
+                        dr_mode = "host";
+                };
+
+                usb-glue@65b00000 {
+                        compatible = "socionext,uniphier-ld20-dwc3-glue",
+                                     "simple-mfd";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x65b00000 0x400>;
+
+                        usb_rst: reset@0 {
+                                compatible = "socionext,uniphier-ld20-usb3-reset";
+                                reg = <0x0 0x4>;
+                                #reset-cells = <1>;
+                                clock-names = "link";
+                                clocks = <&sys_clk 14>;
+                                reset-names = "link";
+                                resets = <&sys_rst 14>;
+                        };
+
+                        usb_vbus0: regulator@100 {
+                                compatible = "socionext,uniphier-ld20-usb3-regulator";
+                                reg = <0x100 0x10>;
+                                clock-names = "link";
+                                clocks = <&sys_clk 14>;
+                                reset-names = "link";
+                                resets = <&sys_rst 14>;
+                        };
+
+                        usb_vbus1: regulator@110 {
+                                compatible = "socionext,uniphier-ld20-usb3-regulator";
+                                reg = <0x110 0x10>;
+                                clock-names = "link";
+                                clocks = <&sys_clk 14>;
+                                reset-names = "link";
+                                resets = <&sys_rst 14>;
+                        };
+
+                        usb_vbus2: regulator@120 {
+                                compatible = "socionext,uniphier-ld20-usb3-regulator";
+                                reg = <0x120 0x10>;
+                                clock-names = "link";
+                                clocks = <&sys_clk 14>;
+                                reset-names = "link";
+                                resets = <&sys_rst 14>;
+                        };
+
+                        usb_vbus3: regulator@130 {
+                                compatible = "socionext,uniphier-ld20-usb3-regulator";
+                                reg = <0x130 0x10>;
+                                clock-names = "link";
+                                clocks = <&sys_clk 14>;
+                                reset-names = "link";
+                                resets = <&sys_rst 14>;
+                        };
+
+                        usb_hsphy0: hs-phy@200 {
+                                compatible = "socionext,uniphier-ld20-usb3-hsphy";
+                                reg = <0x200 0x10>;
+                                #phy-cells = <0>;
+                                clock-names = "link", "phy";
+                                clocks = <&sys_clk 14>, <&sys_clk 16>;
+                                reset-names = "link", "phy";
+                                resets = <&sys_rst 14>, <&sys_rst 16>;
+                                vbus-supply = <&usb_vbus0>;
+                                nvmem-cell-names = "rterm", "sel_t", "hs_i";
+                                nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
+                                              <&usb_hs_i0>;
+                        };
+
+                        usb_hsphy1: hs-phy@210 {
+                                compatible = "socionext,uniphier-ld20-usb3-hsphy";
+                                reg = <0x210 0x10>;
+                                #phy-cells = <0>;
+                                clock-names = "link", "phy";
+                                clocks = <&sys_clk 14>, <&sys_clk 16>;
+                                reset-names = "link", "phy";
+                                resets = <&sys_rst 14>, <&sys_rst 16>;
+                                vbus-supply = <&usb_vbus1>;
+                                nvmem-cell-names = "rterm", "sel_t", "hs_i";
+                                nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
+                                              <&usb_hs_i0>;
+                        };
+
+                        usb_hsphy2: hs-phy@220 {
+                                compatible = "socionext,uniphier-ld20-usb3-hsphy";
+                                reg = <0x220 0x10>;
+                                #phy-cells = <0>;
+                                clock-names = "link", "phy";
+                                clocks = <&sys_clk 14>, <&sys_clk 17>;
+                                reset-names = "link", "phy";
+                                resets = <&sys_rst 14>, <&sys_rst 17>;
+                                vbus-supply = <&usb_vbus2>;
+                                nvmem-cell-names = "rterm", "sel_t", "hs_i";
+                                nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
+                                              <&usb_hs_i2>;
+                        };
+
+                        usb_hsphy3: hs-phy@230 {
+                                compatible = "socionext,uniphier-ld20-usb3-hsphy";
+                                reg = <0x230 0x10>;
+                                #phy-cells = <0>;
+                                clock-names = "link", "phy";
+                                clocks = <&sys_clk 14>, <&sys_clk 17>;
+                                reset-names = "link", "phy";
+                                resets = <&sys_rst 14>, <&sys_rst 17>;
+                                vbus-supply = <&usb_vbus3>;
+                                nvmem-cell-names = "rterm", "sel_t", "hs_i";
+                                nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
+                                              <&usb_hs_i2>;
+                        };
+
+                        usb_ssphy0: ss-phy@300 {
+                                compatible = "socionext,uniphier-ld20-usb3-ssphy";
+                                reg = <0x300 0x10>;
+                                #phy-cells = <0>;
+                                clock-names = "link", "phy";
+                                clocks = <&sys_clk 14>, <&sys_clk 18>;
+                                reset-names = "link", "phy";
+                                resets = <&sys_rst 14>, <&sys_rst 18>;
+                                vbus-supply = <&usb_vbus0>;
+                        };
+
+                        usb_ssphy1: ss-phy@310 {
+                                compatible = "socionext,uniphier-ld20-usb3-ssphy";
+                                reg = <0x310 0x10>;
+                                #phy-cells = <0>;
+                                clock-names = "link", "phy";
+                                clocks = <&sys_clk 14>, <&sys_clk 19>;
+                                reset-names = "link", "phy";
+                                resets = <&sys_rst 14>, <&sys_rst 19>;
+                                vbus-supply = <&usb_vbus1>;
+                        };
+                };
+
                 nand: nand@68000000 {
                         compatible = "socionext,uniphier-denali-nand-v5b";
                         status = "disabled";
@@ -628,7 +880,8 @@
                         interrupts = <0 65 4>;
                         pinctrl-names = "default";
                         pinctrl-0 = <&pinctrl_nand>;
-                        clocks = <&sys_clk 2>;
+                        clock-names = "nand", "nand_x", "ecc";
+                        clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
                         resets = <&sys_rst 2>;
                 };
         };
diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts
index c1bb607bd211..a41f7cac952a 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts
+++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts
@@ -75,6 +75,10 @@
         status = "okay";
 };
 
+&sd {
+        status = "okay";
+};
+
 &eth0 {
         status = "okay";
         phy-handle = <&ethphy0>;
@@ -100,3 +104,11 @@
 &nand {
         status = "okay";
 };
+
+&usb0 {
+        status = "okay";
+};
+
+&usb1 {
+        status = "okay";
+};
diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
index 2a4cf427f5d3..4f57c9e9d7a8 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
@@ -144,6 +144,28 @@
                 #size-cells = <1>;
                 ranges = <0 0 0 0xffffffff>;
 
+                spi0: spi@54006000 {
+                        compatible = "socionext,uniphier-scssi";
+                        status = "disabled";
+                        reg = <0x54006000 0x100>;
+                        interrupts = <0 39 4>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_spi0>;
+                        clocks = <&peri_clk 11>;
+                        resets = <&peri_rst 11>;
+                };
+
+                spi1: spi@54006100 {
+                        compatible = "socionext,uniphier-scssi";
+                        status = "disabled";
+                        reg = <0x54006100 0x100>;
+                        interrupts = <0 216 4>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_spi1>;
+                        clocks = <&peri_clk 11>;
+                        resets = <&peri_rst 11>;
+                };
+
                 serial0: serial@54006800 {
                         compatible = "socionext,uniphier-uart";
                         status = "disabled";
@@ -341,6 +363,24 @@
                         cdns,phy-dll-delay-sdclk-hsmmc = <21>;
                 };
 
+                sd: sdhc@5a400000 {
+                        compatible = "socionext,uniphier-sd-v3.1.1";
+                        status = "disabled";
+                        reg = <0x5a400000 0x800>;
+                        interrupts = <0 76 4>;
+                        pinctrl-names = "default", "uhs";
+                        pinctrl-0 = <&pinctrl_sd>;
+                        pinctrl-1 = <&pinctrl_sd_uhs>;
+                        clocks = <&sd_clk 0>;
+                        reset-names = "host";
+                        resets = <&sd_rst 0>;
+                        bus-width = <4>;
+                        cap-sd-highspeed;
+                        sd-uhs-sdr12;
+                        sd-uhs-sdr25;
+                        sd-uhs-sdr50;
+                };
+
                 soc_glue: soc-glue@5f800000 {
                         compatible = "socionext,uniphier-pxs3-soc-glue",
                                      "simple-mfd", "syscon";
@@ -366,6 +406,50 @@
                         efuse@200 {
                                 compatible = "socionext,uniphier-efuse";
                                 reg = <0x200 0x68>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+
+                                /* USB cells */
+                                usb_rterm0: trim@54,4 {
+                                        reg = <0x54 1>;
+                                        bits = <4 2>;
+                                };
+                                usb_rterm1: trim@55,4 {
+                                        reg = <0x55 1>;
+                                        bits = <4 2>;
+                                };
+                                usb_rterm2: trim@58,4 {
+                                        reg = <0x58 1>;
+                                        bits = <4 2>;
+                                };
+                                usb_rterm3: trim@59,4 {
+                                        reg = <0x59 1>;
+                                        bits = <4 2>;
+                                };
+                                usb_sel_t0: trim@54,0 {
+                                        reg = <0x54 1>;
+                                        bits = <0 4>;
+                                };
+                                usb_sel_t1: trim@55,0 {
+                                        reg = <0x55 1>;
+                                        bits = <0 4>;
+                                };
+                                usb_sel_t2: trim@58,0 {
+                                        reg = <0x58 1>;
+                                        bits = <0 4>;
+                                };
+                                usb_sel_t3: trim@59,0 {
+                                        reg = <0x59 1>;
+                                        bits = <0 4>;
+                                };
+                                usb_hs_i0: trim@56,0 {
+                                        reg = <0x56 1>;
+                                        bits = <0 4>;
+                                };
+                                usb_hs_i2: trim@5a,0 {
+                                        reg = <0x5a 1>;
+                                        bits = <0 4>;
+                                };
                         };
                 };
 
@@ -447,6 +531,202 @@
                         };
                 };
 
+                usb0: usb@65a00000 {
+                        compatible = "socionext,uniphier-dwc3", "snps,dwc3";
+                        status = "disabled";
+                        reg = <0x65a00000 0xcd00>;
+                        interrupt-names = "host", "peripheral";
+                        interrupts = <0 134 4>, <0 135 4>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
+                        clock-names = "ref", "bus_early", "suspend";
+                        clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
+                        resets = <&usb0_rst 15>;
+                        phys = <&usb0_hsphy0>, <&usb0_hsphy1>,
+                               <&usb0_ssphy0>, <&usb0_ssphy1>;
+                        dr_mode = "host";
+                };
+
+                usb-glue@65b00000 {
+                        compatible = "socionext,uniphier-pxs3-dwc3-glue",
+                                     "simple-mfd";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x65b00000 0x400>;
+
+                        usb0_rst: reset@0 {
+                                compatible = "socionext,uniphier-pxs3-usb3-reset";
+                                reg = <0x0 0x4>;
+                                #reset-cells = <1>;
+                                clock-names = "link";
+                                clocks = <&sys_clk 12>;
+                                reset-names = "link";
+                                resets = <&sys_rst 12>;
+                        };
+
+                        usb0_vbus0: regulator@100 {
+                                compatible = "socionext,uniphier-pxs3-usb3-regulator";
+                                reg = <0x100 0x10>;
+                                clock-names = "link";
+                                clocks = <&sys_clk 12>;
+                                reset-names = "link";
+                                resets = <&sys_rst 12>;
+                        };
+
+                        usb0_vbus1: regulator@110 {
+                                compatible = "socionext,uniphier-pxs3-usb3-regulator";
+                                reg = <0x110 0x10>;
+                                clock-names = "link";
+                                clocks = <&sys_clk 12>;
+                                reset-names = "link";
+                                resets = <&sys_rst 12>;
+                        };
+
+                        usb0_hsphy0: hs-phy@200 {
+                                compatible = "socionext,uniphier-pxs3-usb3-hsphy";
+                                reg = <0x200 0x10>;
+                                #phy-cells = <0>;
+                                clock-names = "link", "phy";
+                                clocks = <&sys_clk 12>, <&sys_clk 16>;
+                                reset-names = "link", "phy";
+                                resets = <&sys_rst 12>, <&sys_rst 16>;
+                                vbus-supply = <&usb0_vbus0>;
+                                nvmem-cell-names = "rterm", "sel_t", "hs_i";
+                                nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
+                                              <&usb_hs_i0>;
+                        };
+
+                        usb0_hsphy1: hs-phy@210 {
+                                compatible = "socionext,uniphier-pxs3-usb3-hsphy";
+                                reg = <0x210 0x10>;
+                                #phy-cells = <0>;
+                                clock-names = "link", "phy";
+                                clocks = <&sys_clk 12>, <&sys_clk 16>;
+                                reset-names = "link", "phy";
+                                resets = <&sys_rst 12>, <&sys_rst 16>;
+                                vbus-supply = <&usb0_vbus1>;
+                                nvmem-cell-names = "rterm", "sel_t", "hs_i";
+                                nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
+                                              <&usb_hs_i0>;
+                        };
+
+                        usb0_ssphy0: ss-phy@300 {
+                                compatible = "socionext,uniphier-pxs3-usb3-ssphy";
+                                reg = <0x300 0x10>;
+                                #phy-cells = <0>;
+                                clock-names = "link", "phy";
+                                clocks = <&sys_clk 12>, <&sys_clk 17>;
+                                reset-names = "link", "phy";
+                                resets = <&sys_rst 12>, <&sys_rst 17>;
+                                vbus-supply = <&usb0_vbus0>;
+                        };
+
+                        usb0_ssphy1: ss-phy@310 {
+                                compatible = "socionext,uniphier-pxs3-usb3-ssphy";
+                                reg = <0x310 0x10>;
+                                #phy-cells = <0>;
+                                clock-names = "link", "phy";
+                                clocks = <&sys_clk 12>, <&sys_clk 18>;
+                                reset-names = "link", "phy";
+                                resets = <&sys_rst 12>, <&sys_rst 18>;
+                                vbus-supply = <&usb0_vbus1>;
+                        };
+                };
+
+                usb1: usb@65c00000 {
+                        compatible = "socionext,uniphier-dwc3", "snps,dwc3";
+                        status = "disabled";
+                        reg = <0x65c00000 0xcd00>;
+                        interrupt-names = "host", "peripheral";
+                        interrupts = <0 137 4>, <0 138 4>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
+                        clock-names = "ref", "bus_early", "suspend";
+                        clocks = <&sys_clk 13>, <&sys_clk 13>, <&sys_clk 13>;
+                        resets = <&usb1_rst 15>;
+                        phys = <&usb1_hsphy0>, <&usb1_hsphy1>,
+                               <&usb1_ssphy0>;
+                        dr_mode = "host";
+                };
+
+                usb-glue@65d00000 {
+                        compatible = "socionext,uniphier-pxs3-dwc3-glue",
+                                     "simple-mfd";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x65d00000 0x400>;
+
+                        usb1_rst: reset@0 {
+                                compatible = "socionext,uniphier-pxs3-usb3-reset";
+                                reg = <0x0 0x4>;
+                                #reset-cells = <1>;
+                                clock-names = "link";
+                                clocks = <&sys_clk 13>;
+                                reset-names = "link";
+                                resets = <&sys_rst 13>;
+                        };
+
+                        usb1_vbus0: regulator@100 {
+                                compatible = "socionext,uniphier-pxs3-usb3-regulator";
+                                reg = <0x100 0x10>;
+                                clock-names = "link";
+                                clocks = <&sys_clk 13>;
+                                reset-names = "link";
+                                resets = <&sys_rst 13>;
+                        };
+
+                        usb1_vbus1: regulator@110 {
+                                compatible = "socionext,uniphier-pxs3-usb3-regulator";
+                                reg = <0x110 0x10>;
+                                clock-names = "link";
+                                clocks = <&sys_clk 13>;
+                                reset-names = "link";
+                                resets = <&sys_rst 13>;
+                        };
+
+                        usb1_hsphy0: hs-phy@200 {
+                                compatible = "socionext,uniphier-pxs3-usb3-hsphy";
+                                reg = <0x200 0x10>;
+                                #phy-cells = <0>;
+                                clock-names = "link", "phy", "phy-ext";
+                                clocks = <&sys_clk 13>, <&sys_clk 20>,
+                                         <&sys_clk 14>;
+                                reset-names = "link", "phy";
+                                resets = <&sys_rst 13>, <&sys_rst 20>;
+                                vbus-supply = <&usb1_vbus0>;
+                                nvmem-cell-names = "rterm", "sel_t", "hs_i";
+                                nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
+                                              <&usb_hs_i2>;
+                        };
+
+                        usb1_hsphy1: hs-phy@210 {
+                                compatible = "socionext,uniphier-pxs3-usb3-hsphy";
+                                reg = <0x210 0x10>;
+                                #phy-cells = <0>;
+                                clock-names = "link", "phy", "phy-ext";
+                                clocks = <&sys_clk 13>, <&sys_clk 20>,
+                                         <&sys_clk 14>;
+                                reset-names = "link", "phy";
+                                resets = <&sys_rst 13>, <&sys_rst 20>;
+                                vbus-supply = <&usb1_vbus1>;
+                                nvmem-cell-names = "rterm", "sel_t", "hs_i";
+                                nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
+                                              <&usb_hs_i2>;
+                        };
+
+                        usb1_ssphy0: ss-phy@300 {
+                                compatible = "socionext,uniphier-pxs3-usb3-ssphy";
+                                reg = <0x300 0x10>;
+                                #phy-cells = <0>;
+                                clock-names = "link", "phy", "phy-ext";
+                                clocks = <&sys_clk 13>, <&sys_clk 21>,
+                                         <&sys_clk 14>;
+                                reset-names = "link", "phy";
+                                resets = <&sys_rst 13>, <&sys_rst 21>;
+                                vbus-supply = <&usb1_vbus0>;
+                        };
+                };
+
                 nand: nand@68000000 {
                         compatible = "socionext,uniphier-denali-nand-v5b";
                         status = "disabled";
@@ -455,7 +735,8 @@
                         interrupts = <0 65 4>;
                         pinctrl-names = "default";
                         pinctrl-0 = <&pinctrl_nand>;
-                        clocks = <&sys_clk 2>;
+                        clock-names = "nand", "nand_x", "ecc";
+                        clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
                         resets = <&sys_rst 2>;
                 };
         };
diff --git a/arch/arm64/boot/dts/synaptics/as370.dtsi b/arch/arm64/boot/dts/synaptics/as370.dtsi
new file mode 100644
index 000000000000..7331acf3874e
--- /dev/null
+++ b/arch/arm64/boot/dts/synaptics/as370.dtsi
@@ -0,0 +1,173 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2018 Synaptics Incorporated
+ *
+ * Author: Jisheng Zhang <jszhang@kernel.org>
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+        compatible = "syna,as370";
+        interrupt-parent = <&gic>;
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        psci {
+                compatible = "arm,psci-1.0";
+                method = "smc";
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu0: cpu@0 {
+                        compatible = "arm,cortex-a53", "arm,armv8";
+                        device_type = "cpu";
+                        reg = <0x0>;
+                        enable-method = "psci";
+                        next-level-cache = <&l2>;
+                        cpu-idle-states = <&CPU_SLEEP_0>;
+                };
+
+                cpu1: cpu@1 {
+                        compatible = "arm,cortex-a53", "arm,armv8";
+                        device_type = "cpu";
+                        reg = <0x1>;
+                        enable-method = "psci";
+                        next-level-cache = <&l2>;
+                        cpu-idle-states = <&CPU_SLEEP_0>;
+                };
+
+                cpu2: cpu@2 {
+                        compatible = "arm,cortex-a53", "arm,armv8";
+                        device_type = "cpu";
+                        reg = <0x2>;
+                        enable-method = "psci";
+                        next-level-cache = <&l2>;
+                        cpu-idle-states = <&CPU_SLEEP_0>;
+                };
+
+                cpu3: cpu@3 {
+                        compatible = "arm,cortex-a53", "arm,armv8";
+                        device_type = "cpu";
+                        reg = <0x3>;
+                        enable-method = "psci";
+                        next-level-cache = <&l2>;
+                        cpu-idle-states = <&CPU_SLEEP_0>;
+                };
+
+                l2: cache {
+                        compatible = "cache";
+                };
+
+                idle-states {
+                        entry-method = "psci";
+                        CPU_SLEEP_0: cpu-sleep-0 {
+                                compatible = "arm,idle-state";
+                                local-timer-stop;
+                                arm,psci-suspend-param = <0x0010000>;
+                                entry-latency-us = <75>;
+                                exit-latency-us = <155>;
+                                min-residency-us = <1000>;
+                        };
+                };
+        };
+
+        osc: osc {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <25000000>;
+        };
+
+        pmu {
+                compatible = "arm,cortex-a53-pmu";
+                interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-affinity = <&cpu0>,
+                                     <&cpu1>,
+                                     <&cpu2>,
+                                     <&cpu3>;
+        };
+
+        timer {
+                compatible = "arm,armv8-timer";
+                interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+        };
+
+        soc@f7000000 {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0 0 0xf7000000 0x1000000>;
+
+                gic: interrupt-controller@901000 {
+                        compatible = "arm,gic-400";
+                        #interrupt-cells = <3>;
+                        interrupt-controller;
+                        reg = <0x901000 0x1000>,
+                              <0x902000 0x2000>,
+                              <0x904000 0x2000>,
+                              <0x906000 0x2000>;
+                        interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+                };
+
+                apb@e80000 {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0xe80000 0x10000>;
+
+                        uart0: serial@c00 {
+                                compatible = "snps,dw-apb-uart";
+                                reg = <0xc00 0x100>;
+                                interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&osc>;
+                                reg-shift = <2>;
+                                status = "disabled";
+                        };
+
+                        gpio0: gpio@1800 {
+                                compatible = "snps,dw-apb-gpio";
+                                reg = <0x1800 0x400>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                porta: gpio-port@0 {
+                                        compatible = "snps,dw-apb-gpio-port";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        snps,nr-gpios = <32>;
+                                        reg = <0>;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                        interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+                                };
+                        };
+
+                        gpio1: gpio@2000 {
+                                compatible = "snps,dw-apb-gpio";
+                                reg = <0x2000 0x400>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                portb: gpio-port@1 {
+                                        compatible = "snps,dw-apb-gpio-port";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        snps,nr-gpios = <32>;
+                                        reg = <0>;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                        interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+                                };
+                        };
+                };
+        };
+};
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index 2409344df4fa..adcd6341e40c 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -8,13 +8,13 @@
 &cbass_main {
         gic500: interrupt-controller@1800000 {
                 compatible = "arm,gic-v3";
-                #address-cells = <1>;
-                #size-cells = <1>;
+                #address-cells = <2>;
+                #size-cells = <2>;
                 ranges;
                 #interrupt-cells = <3>;
                 interrupt-controller;
-                reg = <0x01800000 0x10000>,     /* GICD */
-                      <0x01880000 0x90000>;     /* GICR */
+                reg = <0x00 0x01800000 0x00 0x10000>,   /* GICD */
+                      <0x00 0x01880000 0x00 0x90000>;   /* GICR */
                 /*
                  * vcpumntirq:
                  * virtual CPU interface maintenance interrupt
@@ -23,9 +23,50 @@
 
                 gic_its: gic-its@18200000 {
                         compatible = "arm,gic-v3-its";
-                        reg = <0x01820000 0x10000>;
+                        reg = <0x00 0x01820000 0x00 0x10000>;
                         msi-controller;
                         #msi-cells = <1>;
                 };
         };
+
+        secure_proxy_main: mailbox@32c00000 {
+                compatible = "ti,am654-secure-proxy";
+                #mbox-cells = <1>;
+                reg-names = "target_data", "rt", "scfg";
+                reg = <0x00 0x32c00000 0x00 0x100000>,
+                      <0x00 0x32400000 0x00 0x100000>,
+                      <0x00 0x32800000 0x00 0x100000>;
+                interrupt-names = "rx_011";
+                interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+        };
+
+        main_uart0: serial@2800000 {
+                compatible = "ti,am654-uart";
+                reg = <0x00 0x02800000 0x00 0x100>;
+                reg-shift = <2>;
+                reg-io-width = <4>;
+                interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+                clock-frequency = <48000000>;
+                current-speed = <115200>;
+        };
+
+        main_uart1: serial@2810000 {
+                compatible = "ti,am654-uart";
+                reg = <0x00 0x02810000 0x00 0x100>;
+                reg-shift = <2>;
+                reg-io-width = <4>;
+                interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+                clock-frequency = <48000000>;
+                current-speed = <115200>;
+        };
+
+        main_uart2: serial@2820000 {
+                compatible = "ti,am654-uart";
+                reg = <0x00 0x02820000 0x00 0x100>;
+                reg-shift = <2>;
+                reg-io-width = <4>;
+                interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+                clock-frequency = <48000000>;
+                current-speed = <115200>;
+        };
 };
diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
new file mode 100644
index 000000000000..8c611d16df44
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM6 SoC Family MCU Domain peripherals
+ *
+ * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+&cbass_mcu {
+        mcu_uart0: serial@40a00000 {
+                compatible = "ti,am654-uart";
+                        reg = <0x00 0x40a00000 0x00 0x100>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
+                        clock-frequency = <96000000>;
+                        current-speed = <115200>;
+        };
+};
diff --git a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi
new file mode 100644
index 000000000000..affc3c309353
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM6 SoC Family Wakeup Domain peripherals
+ *
+ * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+&cbass_wakeup {
+        dmsc: dmsc {
+                compatible = "ti,k2g-sci";
+                ti,host-id = <12>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                mbox-names = "rx", "tx";
+
+                mboxes= <&secure_proxy_main 11>,
+                        <&secure_proxy_main 13>;
+
+                k3_pds: power-controller {
+                        compatible = "ti,sci-pm-domain";
+                        #power-domain-cells = <1>;
+                };
+
+                k3_clks: clocks {
+                        compatible = "ti,k2g-sci-clk";
+                        #clock-cells = <2>;
+                };
+
+                k3_reset: reset-controller {
+                        compatible = "ti,sci-reset";
+                        #reset-cells = <2>;
+                };
+        };
+
+        wkup_uart0: serial@42300000 {
+                compatible = "ti,am654-uart";
+                reg = <0x00 0x42300000 0x00 0x100>;
+                reg-shift = <2>;
+                reg-io-width = <4>;
+                interrupts = <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
+                clock-frequency = <48000000>;
+                current-speed = <115200>;
+        };
+};
diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi
index cede1fa0983c..3d4bf369d030 100644
--- a/arch/arm64/boot/dts/ti/k3-am65.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi
@@ -16,6 +16,14 @@
         #address-cells = <2>;
         #size-cells = <2>;
 
+        aliases {
+                serial0 = &wkup_uart0;
+                serial1 = &mcu_uart0;
+                serial2 = &main_uart0;
+                serial3 = &main_uart1;
+                serial4 = &main_uart2;
+        };
+
         chosen { };
 
         firmware {
@@ -46,38 +54,38 @@
 
         cbass_main: interconnect@100000 {
                 compatible = "simple-bus";
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges = <0x00100000 0x00 0x00100000 0x00020000>, /* ctrl mmr */
-                         <0x00600000 0x00 0x00600000 0x00001100>, /* GPIO */
-                         <0x00900000 0x00 0x00900000 0x00012000>, /* serdes */
-                         <0x01000000 0x00 0x01000000 0x0af02400>, /* Most peripherals */
-                         <0x30800000 0x00 0x30800000 0x0bc00000>, /* MAIN NAVSS */
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
+                         <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
+                         <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
+                         <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
+                         <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
                          /* MCUSS Range */
-                         <0x28380000 0x00 0x28380000 0x03880000>,
-                         <0x40200000 0x00 0x40200000 0x00900100>,
-                         <0x42040000 0x00 0x42040000 0x03ac2400>,
-                         <0x45100000 0x00 0x45100000 0x00c24000>,
-                         <0x46000000 0x00 0x46000000 0x00200000>,
-                         <0x47000000 0x00 0x47000000 0x00068400>;
+                         <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
+                         <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
+                         <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
+                         <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
+                         <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
+                         <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>;
 
                 cbass_mcu: interconnect@28380000 {
                         compatible = "simple-bus";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        ranges = <0x28380000 0x28380000 0x03880000>, /* MCU NAVSS*/
-                                 <0x40200000 0x40200000 0x00900100>, /* First peripheral window */
-                                 <0x42040000 0x42040000 0x03ac2400>, /* WKUP */
-                                 <0x45100000 0x45100000 0x00c24000>, /* MMRs, remaining NAVSS */
-                                 <0x46000000 0x46000000 0x00200000>, /* CPSW */
-                                 <0x47000000 0x47000000 0x00068400>; /* OSPI space 1 */
+                        #address-cells = <2>;
+                        #size-cells = <2>;
+                        ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
+                                 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */
+                                 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */
+                                 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
+                                 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
+                                 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>; /* OSPI space 1 */
 
                         cbass_wakeup: interconnect@42040000 {
                                 compatible = "simple-bus";
                                 #address-cells = <1>;
                                 #size-cells = <1>;
                                 /* WKUP  Basic peripherals */
-                                ranges = <0x42040000 0x42040000 0x03ac2400>;
+                                ranges = <0x42040000 0x00 0x42040000 0x03ac2400>;
                         };
                 };
         };
@@ -85,3 +93,5 @@
 
 /* Now include the peripherals for each bus segments */
 #include "k3-am65-main.dtsi"
+#include "k3-am65-mcu.dtsi"
+#include "k3-am65-wakeup.dtsi"
diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
index af6956fdc13f..e146ac2ad781 100644
--- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
@@ -34,3 +34,8 @@
                 };
         };
 };
+
+&wkup_uart0 {
+        /* Wakeup UART is used by System firmware */
+        status = "disabled";
+};
diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h b/include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h
new file mode 100644
index 000000000000..20f43404cac0
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * pinctrl-tegra-io-pad.h: Tegra I/O pad source voltage configuration constants
+ * pinctrl bindings.
+ *
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Author: Aapo Vienamo <avienamo@nvidia.com>
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_TEGRA_IO_PAD_H
+#define _DT_BINDINGS_PINCTRL_TEGRA_IO_PAD_H
+
+/* Voltage levels of the I/O pad's source rail */
+#define TEGRA_IO_PAD_VOLTAGE_1V8        0
+#define TEGRA_IO_PAD_VOLTAGE_3V3        1
+
+#endif
diff --git a/include/dt-bindings/power/owl-s900-powergate.h b/include/dt-bindings/power/owl-s900-powergate.h
new file mode 100644
index 000000000000..d939bd964657
--- /dev/null
+++ b/include/dt-bindings/power/owl-s900-powergate.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) */
+/*
+ * Actions Semi S900 SPS
+ *
+ * Copyright (c) 2018 Linaro Ltd.
+ */
+#ifndef DT_BINDINGS_POWER_OWL_S900_POWERGATE_H
+#define DT_BINDINGS_POWER_OWL_S900_POWERGATE_H
+
+#define S900_PD_GPU_B   0
+#define S900_PD_VCE     1
+#define S900_PD_SENSOR  2
+#define S900_PD_VDE     3
+#define S900_PD_HDE     4
+#define S900_PD_USB3    5
+#define S900_PD_DDR0    6
+#define S900_PD_DDR1    7
+#define S900_PD_DE      8
+#define S900_PD_NAND    9
+#define S900_PD_USB2_H0 10
+#define S900_PD_USB2_H1 11
+
+#endif