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-rw-r--r--arch/powerpc/boot/Makefile5
-rw-r--r--arch/powerpc/boot/cuboot-c2k.c189
-rw-r--r--arch/powerpc/boot/dts/c2k.dts366
-rw-r--r--arch/powerpc/configs/c2k_defconfig389
-rw-r--r--arch/powerpc/platforms/embedded6xx/Kconfig10
-rw-r--r--arch/powerpc/platforms/embedded6xx/Makefile1
-rw-r--r--arch/powerpc/platforms/embedded6xx/c2k.c148
7 files changed, 2 insertions, 1106 deletions
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index 49767e06202c..b5620ef68557 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -149,8 +149,8 @@ src-plat-$(CONFIG_PPC_82xx) += cuboot-pq2.c fixed-head.S ep8248e.c cuboot-824x.c
149src-plat-$(CONFIG_PPC_83xx) += cuboot-83xx.c fixed-head.S redboot-83xx.c 149src-plat-$(CONFIG_PPC_83xx) += cuboot-83xx.c fixed-head.S redboot-83xx.c
150src-plat-$(CONFIG_FSL_SOC_BOOKE) += cuboot-85xx.c cuboot-85xx-cpm2.c 150src-plat-$(CONFIG_FSL_SOC_BOOKE) += cuboot-85xx.c cuboot-85xx-cpm2.c
151src-plat-$(CONFIG_EMBEDDED6xx) += cuboot-pq2.c cuboot-mpc7448hpc2.c \ 151src-plat-$(CONFIG_EMBEDDED6xx) += cuboot-pq2.c cuboot-mpc7448hpc2.c \
152 cuboot-c2k.c gamecube-head.S \ 152 gamecube-head.S gamecube.c \
153 gamecube.c wii-head.S wii.c holly.c \ 153 wii-head.S wii.c holly.c \
154 fixed-head.S mvme5100.c 154 fixed-head.S mvme5100.c
155src-plat-$(CONFIG_AMIGAONE) += cuboot-amigaone.c 155src-plat-$(CONFIG_AMIGAONE) += cuboot-amigaone.c
156src-plat-$(CONFIG_PPC_PS3) += ps3-head.S ps3-hvcall.S ps3.c 156src-plat-$(CONFIG_PPC_PS3) += ps3-head.S ps3-hvcall.S ps3.c
@@ -345,7 +345,6 @@ image-$(CONFIG_MVME7100) += dtbImage.mvme7100
345# Board ports in arch/powerpc/platform/embedded6xx/Kconfig 345# Board ports in arch/powerpc/platform/embedded6xx/Kconfig
346image-$(CONFIG_STORCENTER) += cuImage.storcenter 346image-$(CONFIG_STORCENTER) += cuImage.storcenter
347image-$(CONFIG_MPC7448HPC2) += cuImage.mpc7448hpc2 347image-$(CONFIG_MPC7448HPC2) += cuImage.mpc7448hpc2
348image-$(CONFIG_PPC_C2K) += cuImage.c2k
349image-$(CONFIG_GAMECUBE) += dtbImage.gamecube 348image-$(CONFIG_GAMECUBE) += dtbImage.gamecube
350image-$(CONFIG_WII) += dtbImage.wii 349image-$(CONFIG_WII) += dtbImage.wii
351image-$(CONFIG_MVME5100) += dtbImage.mvme5100 350image-$(CONFIG_MVME5100) += dtbImage.mvme5100
diff --git a/arch/powerpc/boot/cuboot-c2k.c b/arch/powerpc/boot/cuboot-c2k.c
deleted file mode 100644
index 9309c51f1d65..000000000000
--- a/arch/powerpc/boot/cuboot-c2k.c
+++ /dev/null
@@ -1,189 +0,0 @@
1/*
2 * GEFanuc C2K platform code.
3 *
4 * Author: Remi Machet <rmachet@slac.stanford.edu>
5 *
6 * Originated from prpmc2800.c
7 *
8 * 2008 (c) Stanford University
9 * 2007 (c) MontaVista, Software, Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
14 */
15
16#include "types.h"
17#include "stdio.h"
18#include "io.h"
19#include "ops.h"
20#include "elf.h"
21#include "mv64x60.h"
22#include "cuboot.h"
23#include "ppcboot.h"
24
25static u8 *bridge_base;
26
27static void c2k_bridge_setup(u32 mem_size)
28{
29 u32 i, v[30], enables, acc_bits;
30 u32 pci_base_hi, pci_base_lo, size, buf[2];
31 unsigned long cpu_base;
32 int rc;
33 void *devp, *mv64x60_devp;
34 u8 *bridge_pbase, is_coherent;
35 struct mv64x60_cpu2pci_win *tbl;
36 int bus;
37
38 bridge_pbase = mv64x60_get_bridge_pbase();
39 is_coherent = mv64x60_is_coherent();
40
41 if (is_coherent)
42 acc_bits = MV64x60_PCI_ACC_CNTL_SNOOP_WB
43 | MV64x60_PCI_ACC_CNTL_SWAP_NONE
44 | MV64x60_PCI_ACC_CNTL_MBURST_32_BYTES
45 | MV64x60_PCI_ACC_CNTL_RDSIZE_32_BYTES;
46 else
47 acc_bits = MV64x60_PCI_ACC_CNTL_SNOOP_NONE
48 | MV64x60_PCI_ACC_CNTL_SWAP_NONE
49 | MV64x60_PCI_ACC_CNTL_MBURST_128_BYTES
50 | MV64x60_PCI_ACC_CNTL_RDSIZE_256_BYTES;
51
52 mv64x60_config_ctlr_windows(bridge_base, bridge_pbase, is_coherent);
53 mv64x60_devp = find_node_by_compatible(NULL, "marvell,mv64360");
54 if (mv64x60_devp == NULL)
55 fatal("Error: Missing marvell,mv64360 device tree node\n\r");
56
57 enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE));
58 enables |= 0x007ffe00; /* Disable all cpu->pci windows */
59 out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE), enables);
60
61 /* Get the cpu -> pci i/o & mem mappings from the device tree */
62 devp = NULL;
63 for (bus = 0; ; bus++) {
64 char name[] = "pci ";
65
66 name[strlen(name)-1] = bus+'0';
67
68 devp = find_node_by_alias(name);
69 if (devp == NULL)
70 break;
71
72 if (bus >= 2)
73 fatal("Error: Only 2 PCI controllers are supported at" \
74 " this time.\n");
75
76 mv64x60_config_pci_windows(bridge_base, bridge_pbase, bus, 0,
77 mem_size, acc_bits);
78
79 rc = getprop(devp, "ranges", v, sizeof(v));
80 if (rc == 0)
81 fatal("Error: Can't find marvell,mv64360-pci ranges"
82 " property\n\r");
83
84 /* Get the cpu -> pci i/o & mem mappings from the device tree */
85
86 for (i = 0; i < rc; i += 6) {
87 switch (v[i] & 0xff000000) {
88 case 0x01000000: /* PCI I/O Space */
89 tbl = mv64x60_cpu2pci_io;
90 break;
91 case 0x02000000: /* PCI MEM Space */
92 tbl = mv64x60_cpu2pci_mem;
93 break;
94 default:
95 continue;
96 }
97
98 pci_base_hi = v[i+1];
99 pci_base_lo = v[i+2];
100 cpu_base = v[i+3];
101 size = v[i+5];
102
103 buf[0] = cpu_base;
104 buf[1] = size;
105
106 if (!dt_xlate_addr(devp, buf, sizeof(buf), &cpu_base))
107 fatal("Error: Can't translate PCI address " \
108 "0x%x\n\r", (u32)cpu_base);
109
110 mv64x60_config_cpu2pci_window(bridge_base, bus,
111 pci_base_hi, pci_base_lo, cpu_base, size, tbl);
112 }
113
114 enables &= ~(3<<(9+bus*5)); /* Enable cpu->pci<bus> i/o,
115 cpu->pci<bus> mem0 */
116 out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE),
117 enables);
118 };
119}
120
121static void c2k_fixups(void)
122{
123 u32 mem_size;
124
125 mem_size = mv64x60_get_mem_size(bridge_base);
126 c2k_bridge_setup(mem_size); /* Do necessary bridge setup */
127}
128
129#define MV64x60_MPP_CNTL_0 0xf000
130#define MV64x60_MPP_CNTL_2 0xf008
131#define MV64x60_GPP_IO_CNTL 0xf100
132#define MV64x60_GPP_LEVEL_CNTL 0xf110
133#define MV64x60_GPP_VALUE_SET 0xf118
134
135static void c2k_reset(void)
136{
137 u32 temp;
138
139 udelay(5000000);
140
141 if (bridge_base != 0) {
142 temp = in_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_0));
143 temp &= 0xFFFF0FFF;
144 out_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_0), temp);
145
146 temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL));
147 temp |= 0x00000004;
148 out_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL), temp);
149
150 temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL));
151 temp |= 0x00000004;
152 out_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL), temp);
153
154 temp = in_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_2));
155 temp &= 0xFFFF0FFF;
156 out_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_2), temp);
157
158 temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL));
159 temp |= 0x00080000;
160 out_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL), temp);
161
162 temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL));
163 temp |= 0x00080000;
164 out_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL), temp);
165
166 out_le32((u32 *)(bridge_base + MV64x60_GPP_VALUE_SET),
167 0x00080004);
168 }
169
170 for (;;);
171}
172
173static bd_t bd;
174
175void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
176 unsigned long r6, unsigned long r7)
177{
178 CUBOOT_INIT();
179
180 fdt_init(_dtb_start);
181
182 bridge_base = mv64x60_get_bridge_base();
183
184 platform_ops.fixups = c2k_fixups;
185 platform_ops.exit = c2k_reset;
186
187 if (serial_console_init() < 0)
188 exit();
189}
diff --git a/arch/powerpc/boot/dts/c2k.dts b/arch/powerpc/boot/dts/c2k.dts
deleted file mode 100644
index c5beb72d18b7..000000000000
--- a/arch/powerpc/boot/dts/c2k.dts
+++ /dev/null
@@ -1,366 +0,0 @@
1/* Device Tree Source for GEFanuc C2K
2 *
3 * Author: Remi Machet <rmachet@slac.stanford.edu>
4 *
5 * Originated from prpmc2800.dts
6 *
7 * 2008 (c) Stanford University
8 * 2007 (c) MontaVista, Software, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
13 */
14
15/dts-v1/;
16
17/ {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 model = "C2K";
21 compatible = "GEFanuc,C2K";
22 coherency-off;
23
24 aliases {
25 pci0 = &PCI0;
26 pci1 = &PCI1;
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 cpu@0 {
34 device_type = "cpu";
35 compatible = "PowerPC,7447";
36 reg = <0>;
37 clock-frequency = <996000000>; /* 996 MHz */
38 bus-frequency = <166666667>; /* 166.6666 MHz */
39 timebase-frequency = <41666667>; /* 166.6666/4 MHz */
40 i-cache-line-size = <32>;
41 d-cache-line-size = <32>;
42 i-cache-size = <32768>;
43 d-cache-size = <32768>;
44 };
45 };
46
47 memory {
48 device_type = "memory";
49 reg = <0x00000000 0x40000000>; /* 1GB */
50 };
51
52 system-controller@d8000000 { /* Marvell Discovery */
53 #address-cells = <1>;
54 #size-cells = <1>;
55 model = "mv64460";
56 compatible = "marvell,mv64360";
57 clock-frequency = <166666667>; /* 166.66... MHz */
58 reg = <0xd8000000 0x00010000>;
59 virtual-reg = <0xd8000000>;
60 ranges = <0xd4000000 0xd4000000 0x01000000 /* PCI 0 I/O Space */
61 0x80000000 0x80000000 0x08000000 /* PCI 0 MEM Space */
62 0xd0000000 0xd0000000 0x01000000 /* PCI 1 I/O Space */
63 0xa0000000 0xa0000000 0x08000000 /* PCI 1 MEM Space */
64 0xd8100000 0xd8100000 0x00010000 /* FPGA */
65 0xd8110000 0xd8110000 0x00010000 /* FPGA USARTs */
66 0xf8000000 0xf8000000 0x08000000 /* User FLASH */
67 0x00000000 0xd8000000 0x00010000 /* Bridge's regs */
68 0xd8140000 0xd8140000 0x00040000>; /* Integrated SRAM */
69
70 mdio@2000 {
71 #address-cells = <1>;
72 #size-cells = <0>;
73 compatible = "marvell,mv64360-mdio";
74 reg = <0x2000 4>;
75 PHY0: ethernet-phy@0 {
76 interrupts = <76>; /* GPP 12 */
77 interrupt-parent = <&PIC>;
78 reg = <0>;
79 };
80 PHY1: ethernet-phy@1 {
81 interrupts = <76>; /* GPP 12 */
82 interrupt-parent = <&PIC>;
83 reg = <1>;
84 };
85 PHY2: ethernet-phy@2 {
86 interrupts = <76>; /* GPP 12 */
87 interrupt-parent = <&PIC>;
88 reg = <2>;
89 };
90 };
91
92 ethernet-group@2000 {
93 #address-cells = <1>;
94 #size-cells = <0>;
95 compatible = "marvell,mv64360-eth-group";
96 reg = <0x2000 0x2000>;
97 ethernet@0 {
98 device_type = "network";
99 compatible = "marvell,mv64360-eth";
100 reg = <0>;
101 interrupts = <32>;
102 interrupt-parent = <&PIC>;
103 phy = <&PHY0>;
104 local-mac-address = [ 00 00 00 00 00 00 ];
105 };
106 ethernet@1 {
107 device_type = "network";
108 compatible = "marvell,mv64360-eth";
109 reg = <1>;
110 interrupts = <33>;
111 interrupt-parent = <&PIC>;
112 phy = <&PHY1>;
113 local-mac-address = [ 00 00 00 00 00 00 ];
114 };
115 ethernet@2 {
116 device_type = "network";
117 compatible = "marvell,mv64360-eth";
118 reg = <2>;
119 interrupts = <34>;
120 interrupt-parent = <&PIC>;
121 phy = <&PHY2>;
122 local-mac-address = [ 00 00 00 00 00 00 ];
123 };
124 };
125
126 SDMA0: sdma@4000 {
127 compatible = "marvell,mv64360-sdma";
128 reg = <0x4000 0xc18>;
129 virtual-reg = <0xd8004000>;
130 interrupt-base = <0>;
131 interrupts = <36>;
132 interrupt-parent = <&PIC>;
133 };
134
135 SDMA1: sdma@6000 {
136 compatible = "marvell,mv64360-sdma";
137 reg = <0x6000 0xc18>;
138 virtual-reg = <0xd8006000>;
139 interrupt-base = <0>;
140 interrupts = <38>;
141 interrupt-parent = <&PIC>;
142 };
143
144 BRG0: brg@b200 {
145 compatible = "marvell,mv64360-brg";
146 reg = <0xb200 0x8>;
147 clock-src = <8>;
148 clock-frequency = <133333333>;
149 current-speed = <115200>;
150 };
151
152 BRG1: brg@b208 {
153 compatible = "marvell,mv64360-brg";
154 reg = <0xb208 0x8>;
155 clock-src = <8>;
156 clock-frequency = <133333333>;
157 current-speed = <115200>;
158 };
159
160 CUNIT: cunit@f200 {
161 reg = <0xf200 0x200>;
162 };
163
164 MPSCROUTING: mpscrouting@b400 {
165 reg = <0xb400 0xc>;
166 };
167
168 MPSCINTR: mpscintr@b800 {
169 reg = <0xb800 0x100>;
170 virtual-reg = <0xd800b800>;
171 };
172
173 MPSC0: mpsc@8000 {
174 compatible = "marvell,mv64360-mpsc";
175 reg = <0x8000 0x38>;
176 virtual-reg = <0xd8008000>;
177 sdma = <&SDMA0>;
178 brg = <&BRG0>;
179 cunit = <&CUNIT>;
180 mpscrouting = <&MPSCROUTING>;
181 mpscintr = <&MPSCINTR>;
182 cell-index = <0>;
183 interrupts = <40>;
184 interrupt-parent = <&PIC>;
185 };
186
187 MPSC1: mpsc@9000 {
188 compatible = "marvell,mv64360-mpsc";
189 reg = <0x9000 0x38>;
190 virtual-reg = <0xd8009000>;
191 sdma = <&SDMA1>;
192 brg = <&BRG1>;
193 cunit = <&CUNIT>;
194 mpscrouting = <&MPSCROUTING>;
195 mpscintr = <&MPSCINTR>;
196 cell-index = <1>;
197 interrupts = <42>;
198 interrupt-parent = <&PIC>;
199 };
200
201 wdt@b410 { /* watchdog timer */
202 compatible = "marvell,mv64360-wdt";
203 reg = <0xb410 0x8>;
204 };
205
206 i2c@c000 {
207 compatible = "marvell,mv64360-i2c";
208 reg = <0xc000 0x20>;
209 virtual-reg = <0xd800c000>;
210 interrupts = <37>;
211 interrupt-parent = <&PIC>;
212 };
213
214 PIC: pic {
215 #interrupt-cells = <1>;
216 #address-cells = <0>;
217 compatible = "marvell,mv64360-pic";
218 reg = <0x0000 0x88>;
219 interrupt-controller;
220 };
221
222 mpp@f000 {
223 compatible = "marvell,mv64360-mpp";
224 reg = <0xf000 0x10>;
225 };
226
227 gpp@f100 {
228 compatible = "marvell,mv64360-gpp";
229 reg = <0xf100 0x20>;
230 };
231
232 PCI0: pci@80000000 {
233 #address-cells = <3>;
234 #size-cells = <2>;
235 #interrupt-cells = <1>;
236 device_type = "pci";
237 compatible = "marvell,mv64360-pci";
238 reg = <0x0cf8 0x8>;
239 ranges = <0x01000000 0x0 0x00000000 0xd4000000 0x0 0x01000000
240 0x02000000 0x0 0x80000000 0x80000000 0x0 0x08000000>;
241 bus-range = <0 255>;
242 clock-frequency = <66000000>;
243 interrupt-pci-iack = <0x0c34>;
244 interrupt-parent = <&PIC>;
245 interrupt-map-mask = <0x0000 0x0 0x0 0x7>;
246 interrupt-map = <
247 /* Only one interrupt line for PMC0 slot (INTA) */
248 0x0000 0 0 1 &PIC 88
249 >;
250 };
251
252
253 PCI1: pci@a0000000 {
254 #address-cells = <3>;
255 #size-cells = <2>;
256 #interrupt-cells = <1>;
257 device_type = "pci";
258 compatible = "marvell,mv64360-pci";
259 reg = <0x0c78 0x8>;
260 ranges = <0x01000000 0x0 0x00000000 0xd0000000 0x0 0x01000000
261 0x02000000 0x0 0x80000000 0xa0000000 0x0 0x08000000>;
262 bus-range = <0 255>;
263 clock-frequency = <66000000>;
264 interrupt-pci-iack = <0x0cb4>;
265 interrupt-parent = <&PIC>;
266 interrupt-map-mask = <0xf800 0x00 0x00 0x7>;
267 interrupt-map = <
268 /* IDSEL 0x01: PMC1 ? */
269 0x0800 0 0 1 &PIC 88
270 /* IDSEL 0x02: cPCI bridge */
271 0x1000 0 0 1 &PIC 88
272 /* IDSEL 0x03: USB controller */
273 0x1800 0 0 1 &PIC 91
274 /* IDSEL 0x04: SATA controller */
275 0x2000 0 0 1 &PIC 95
276 >;
277 };
278
279 cpu-error@70 {
280 compatible = "marvell,mv64360-cpu-error";
281 reg = <0x0070 0x10 0x0128 0x28>;
282 interrupts = <3>;
283 interrupt-parent = <&PIC>;
284 };
285
286 sram-ctrl@380 {
287 compatible = "marvell,mv64360-sram-ctrl";
288 reg = <0x0380 0x80>;
289 interrupts = <13>;
290 interrupt-parent = <&PIC>;
291 };
292
293 pci-error@1d40 {
294 compatible = "marvell,mv64360-pci-error";
295 reg = <0x1d40 0x40 0x0c28 0x4>;
296 interrupts = <12>;
297 interrupt-parent = <&PIC>;
298 };
299
300 pci-error@1dc0 {
301 compatible = "marvell,mv64360-pci-error";
302 reg = <0x1dc0 0x40 0x0ca8 0x4>;
303 interrupts = <16>;
304 interrupt-parent = <&PIC>;
305 };
306
307 mem-ctrl@1400 {
308 compatible = "marvell,mv64360-mem-ctrl";
309 reg = <0x1400 0x60>;
310 interrupts = <17>;
311 interrupt-parent = <&PIC>;
312 };
313 /* Devices attached to the device controller */
314 devicebus@45c {
315 #address-cells = <2>;
316 #size-cells = <1>;
317 compatible = "marvell,mv64306-devctrl";
318 reg = <0x45C 0x88>;
319 interrupts = <1>;
320 interrupt-parent = <&PIC>;
321 ranges = <0 0 0xd8100000 0x10000
322 2 0 0xd8110000 0x10000
323 4 0 0xf8000000 0x8000000>;
324 fpga@0,0 {
325 compatible = "sbs,fpga-c2k";
326 reg = <0 0 0x10000>;
327 };
328 fpga_usart@2,0 {
329 compatible = "sbs,fpga_usart-c2k";
330 reg = <2 0 0x10000>;
331 };
332 nor_flash@4,0 {
333 compatible = "cfi-flash";
334 reg = <4 0 0x8000000>; /* 128MB */
335 bank-width = <4>;
336 device-width = <1>;
337 #address-cells = <1>;
338 #size-cells = <1>;
339 partition@0 {
340 label = "boot";
341 reg = <0x00000000 0x00080000>;
342 };
343 partition@40000 {
344 label = "kernel";
345 reg = <0x00080000 0x00400000>;
346 };
347 partition@440000 {
348 label = "initrd";
349 reg = <0x00480000 0x00B80000>;
350 };
351 partition@1000000 {
352 label = "rootfs";
353 reg = <0x01000000 0x06800000>;
354 };
355 partition@7800000 {
356 label = "recovery";
357 reg = <0x07800000 0x00800000>;
358 read-only;
359 };
360 };
361 };
362 };
363 chosen {
364 stdout-path = &MPSC0;
365 };
366};
diff --git a/arch/powerpc/configs/c2k_defconfig b/arch/powerpc/configs/c2k_defconfig
deleted file mode 100644
index 6c1196b0f81e..000000000000
--- a/arch/powerpc/configs/c2k_defconfig
+++ /dev/null
@@ -1,389 +0,0 @@
1CONFIG_SYSVIPC=y
2CONFIG_POSIX_MQUEUE=y
3CONFIG_AUDIT=y
4CONFIG_BSD_PROCESS_ACCT=y
5CONFIG_BLK_DEV_INITRD=y
6CONFIG_PROFILING=y
7CONFIG_OPROFILE=m
8CONFIG_KPROBES=y
9CONFIG_MODULES=y
10CONFIG_MODULE_UNLOAD=y
11CONFIG_MODVERSIONS=y
12CONFIG_PARTITION_ADVANCED=y
13CONFIG_OSF_PARTITION=y
14CONFIG_MAC_PARTITION=y
15CONFIG_BSD_DISKLABEL=y
16CONFIG_MINIX_SUBPARTITION=y
17CONFIG_SOLARIS_X86_PARTITION=y
18CONFIG_UNIXWARE_DISKLABEL=y
19CONFIG_SGI_PARTITION=y
20CONFIG_SUN_PARTITION=y
21# CONFIG_PPC_CHRP is not set
22# CONFIG_PPC_PMAC is not set
23CONFIG_EMBEDDED6xx=y
24CONFIG_PPC_C2K=y
25CONFIG_CPU_FREQ=y
26CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
27CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
28CONFIG_CPU_FREQ_GOV_POWERSAVE=m
29CONFIG_CPU_FREQ_GOV_ONDEMAND=m
30CONFIG_GEN_RTC=y
31CONFIG_HIGHMEM=y
32CONFIG_PREEMPT_VOLUNTARY=y
33CONFIG_BINFMT_MISC=y
34CONFIG_PM=y
35CONFIG_PCI_MSI=y
36CONFIG_HOTPLUG_PCI=y
37CONFIG_HOTPLUG_PCI_SHPC=m
38CONFIG_NET=y
39CONFIG_PACKET=y
40CONFIG_UNIX=y
41CONFIG_XFRM_USER=y
42CONFIG_NET_KEY=m
43CONFIG_INET=y
44CONFIG_IP_MULTICAST=y
45CONFIG_IP_ADVANCED_ROUTER=y
46CONFIG_IP_MULTIPLE_TABLES=y
47CONFIG_IP_ROUTE_MULTIPATH=y
48CONFIG_IP_ROUTE_VERBOSE=y
49CONFIG_IP_PNP=y
50CONFIG_IP_PNP_DHCP=y
51CONFIG_NET_IPIP=m
52CONFIG_IP_MROUTE=y
53CONFIG_IP_PIMSM_V1=y
54CONFIG_IP_PIMSM_V2=y
55CONFIG_SYN_COOKIES=y
56CONFIG_INET_AH=m
57CONFIG_INET_ESP=m
58CONFIG_INET_IPCOMP=m
59CONFIG_INET6_AH=m
60CONFIG_INET6_ESP=m
61CONFIG_INET6_IPCOMP=m
62CONFIG_IPV6_TUNNEL=m
63CONFIG_NETFILTER=y
64# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
65CONFIG_IP_NF_IPTABLES=m
66CONFIG_IP_NF_MATCH_ECN=m
67CONFIG_IP_NF_MATCH_TTL=m
68CONFIG_IP_NF_FILTER=m
69CONFIG_IP_NF_TARGET_REJECT=m
70CONFIG_IP_NF_MANGLE=m
71CONFIG_IP_NF_TARGET_ECN=m
72CONFIG_IP_NF_RAW=m
73CONFIG_IP_NF_ARPTABLES=m
74CONFIG_IP_NF_ARPFILTER=m
75CONFIG_IP_NF_ARP_MANGLE=m
76CONFIG_IP6_NF_IPTABLES=m
77CONFIG_IP6_NF_MATCH_EUI64=m
78CONFIG_IP6_NF_MATCH_FRAG=m
79CONFIG_IP6_NF_MATCH_OPTS=m
80CONFIG_IP6_NF_MATCH_HL=m
81CONFIG_IP6_NF_MATCH_IPV6HEADER=m
82CONFIG_IP6_NF_MATCH_RT=m
83CONFIG_IP6_NF_FILTER=m
84CONFIG_IP6_NF_MANGLE=m
85CONFIG_IP6_NF_RAW=m
86CONFIG_BRIDGE_NF_EBTABLES=m
87CONFIG_BRIDGE_EBT_BROUTE=m
88CONFIG_BRIDGE_EBT_T_FILTER=m
89CONFIG_BRIDGE_EBT_T_NAT=m
90CONFIG_BRIDGE_EBT_802_3=m
91CONFIG_BRIDGE_EBT_AMONG=m
92CONFIG_BRIDGE_EBT_ARP=m
93CONFIG_BRIDGE_EBT_IP=m
94CONFIG_BRIDGE_EBT_LIMIT=m
95CONFIG_BRIDGE_EBT_MARK=m
96CONFIG_BRIDGE_EBT_PKTTYPE=m
97CONFIG_BRIDGE_EBT_STP=m
98CONFIG_BRIDGE_EBT_VLAN=m
99CONFIG_BRIDGE_EBT_ARPREPLY=m
100CONFIG_BRIDGE_EBT_DNAT=m
101CONFIG_BRIDGE_EBT_MARK_T=m
102CONFIG_BRIDGE_EBT_REDIRECT=m
103CONFIG_BRIDGE_EBT_SNAT=m
104CONFIG_BRIDGE_EBT_LOG=m
105CONFIG_IP_SCTP=m
106CONFIG_ATM=m
107CONFIG_ATM_CLIP=m
108CONFIG_ATM_LANE=m
109CONFIG_ATM_BR2684=m
110CONFIG_BRIDGE=m
111CONFIG_VLAN_8021Q=m
112CONFIG_NET_SCHED=y
113CONFIG_NET_SCH_CBQ=m
114CONFIG_NET_SCH_HTB=m
115CONFIG_NET_SCH_HFSC=m
116CONFIG_NET_SCH_ATM=m
117CONFIG_NET_SCH_PRIO=m
118CONFIG_NET_SCH_RED=m
119CONFIG_NET_SCH_SFQ=m
120CONFIG_NET_SCH_TEQL=m
121CONFIG_NET_SCH_TBF=m
122CONFIG_NET_SCH_GRED=m
123CONFIG_NET_SCH_DSMARK=m
124CONFIG_NET_SCH_NETEM=m
125CONFIG_NET_CLS_TCINDEX=m
126CONFIG_NET_CLS_ROUTE4=m
127CONFIG_NET_CLS_FW=m
128CONFIG_NET_CLS_U32=m
129CONFIG_CLS_U32_PERF=y
130CONFIG_NET_CLS_RSVP=m
131CONFIG_NET_CLS_RSVP6=m
132CONFIG_NET_CLS_IND=y
133CONFIG_BT=m
134CONFIG_BT_RFCOMM=m
135CONFIG_BT_RFCOMM_TTY=y
136CONFIG_BT_BNEP=m
137CONFIG_BT_BNEP_MC_FILTER=y
138CONFIG_BT_BNEP_PROTO_FILTER=y
139CONFIG_BT_HIDP=m
140CONFIG_BT_HCIUART=m
141CONFIG_BT_HCIUART_H4=y
142CONFIG_BT_HCIUART_BCSP=y
143CONFIG_BT_HCIBCM203X=m
144CONFIG_BT_HCIBFUSB=m
145CONFIG_BT_HCIVHCI=m
146CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
147CONFIG_MTD=y
148CONFIG_MTD_BLOCK=y
149CONFIG_MTD_CFI=y
150CONFIG_MTD_CFI_AMDSTD=y
151CONFIG_MTD_COMPLEX_MAPPINGS=y
152CONFIG_MTD_PHYSMAP_OF=y
153CONFIG_BLK_DEV_LOOP=m
154CONFIG_BLK_DEV_CRYPTOLOOP=m
155CONFIG_BLK_DEV_NBD=m
156CONFIG_BLK_DEV_RAM=y
157CONFIG_BLK_DEV_RAM_SIZE=16384
158CONFIG_SCSI=m
159CONFIG_BLK_DEV_SD=m
160CONFIG_CHR_DEV_ST=m
161CONFIG_CHR_DEV_OSST=m
162CONFIG_BLK_DEV_SR=m
163CONFIG_BLK_DEV_SR_VENDOR=y
164CONFIG_CHR_DEV_SG=m
165CONFIG_SCSI_CONSTANTS=y
166CONFIG_SCSI_LOGGING=y
167CONFIG_SCSI_ISCSI_ATTRS=m
168CONFIG_BLK_DEV_3W_XXXX_RAID=m
169CONFIG_SCSI_3W_9XXX=m
170CONFIG_SCSI_ACARD=m
171CONFIG_SCSI_AACRAID=m
172CONFIG_SCSI_AIC7XXX=m
173CONFIG_AIC7XXX_CMDS_PER_DEVICE=4
174CONFIG_AIC7XXX_RESET_DELAY_MS=15000
175# CONFIG_AIC7XXX_DEBUG_ENABLE is not set
176# CONFIG_AIC7XXX_REG_PRETTY_PRINT is not set
177CONFIG_SCSI_AIC79XX=m
178CONFIG_AIC79XX_CMDS_PER_DEVICE=4
179CONFIG_AIC79XX_RESET_DELAY_MS=15000
180# CONFIG_AIC79XX_DEBUG_ENABLE is not set
181# CONFIG_AIC79XX_REG_PRETTY_PRINT is not set
182CONFIG_SCSI_ARCMSR=m
183CONFIG_MEGARAID_NEWGEN=y
184CONFIG_MEGARAID_MM=m
185CONFIG_MEGARAID_MAILBOX=m
186CONFIG_MEGARAID_SAS=m
187CONFIG_SCSI_GDTH=m
188CONFIG_SCSI_IPS=m
189CONFIG_SCSI_INITIO=m
190CONFIG_SCSI_SYM53C8XX_2=m
191CONFIG_SCSI_QLOGIC_1280=m
192CONFIG_NETDEVICES=y
193CONFIG_BONDING=m
194CONFIG_DUMMY=m
195CONFIG_NETCONSOLE=m
196CONFIG_TUN=m
197# CONFIG_ATM_DRIVERS is not set
198CONFIG_MV643XX_ETH=y
199CONFIG_VITESSE_PHY=y
200CONFIG_INPUT_EVDEV=y
201# CONFIG_INPUT_KEYBOARD is not set
202# CONFIG_INPUT_MOUSE is not set
203CONFIG_INPUT_MISC=y
204CONFIG_INPUT_UINPUT=m
205# CONFIG_SERIO is not set
206# CONFIG_LEGACY_PTYS is not set
207CONFIG_SERIAL_NONSTANDARD=y
208CONFIG_SERIAL_MPSC=y
209CONFIG_SERIAL_MPSC_CONSOLE=y
210CONFIG_NVRAM=m
211CONFIG_RAW_DRIVER=y
212CONFIG_MAX_RAW_DEVS=8192
213CONFIG_I2C=m
214CONFIG_I2C_CHARDEV=m
215CONFIG_I2C_MV64XXX=m
216CONFIG_HWMON=m
217CONFIG_SENSORS_ADM1021=m
218CONFIG_SENSORS_ADM1025=m
219CONFIG_SENSORS_ADM1026=m
220CONFIG_SENSORS_ADM1031=m
221CONFIG_SENSORS_DS1621=m
222CONFIG_SENSORS_GL518SM=m
223CONFIG_SENSORS_MAX1619=m
224CONFIG_SENSORS_LM75=m
225CONFIG_SENSORS_LM77=m
226CONFIG_SENSORS_LM78=m
227CONFIG_SENSORS_LM80=m
228CONFIG_SENSORS_LM83=m
229CONFIG_SENSORS_LM85=m
230CONFIG_SENSORS_LM87=m
231CONFIG_SENSORS_LM90=m
232CONFIG_SENSORS_PCF8591=m
233CONFIG_SENSORS_VIA686A=m
234CONFIG_SENSORS_W83781D=m
235CONFIG_SENSORS_W83L785TS=m
236CONFIG_WATCHDOG=y
237CONFIG_SOFT_WATCHDOG=m
238CONFIG_PCIPCWATCHDOG=m
239CONFIG_WDTPCI=m
240CONFIG_USBPCWATCHDOG=m
241# CONFIG_VGA_CONSOLE is not set
242CONFIG_USB=m
243CONFIG_USB_MON=m
244CONFIG_USB_EHCI_HCD=m
245CONFIG_USB_EHCI_ROOT_HUB_TT=y
246CONFIG_USB_OHCI_HCD=m
247CONFIG_USB_OHCI_HCD_PPC_OF_BE=y
248CONFIG_USB_UHCI_HCD=m
249CONFIG_USB_ACM=m
250CONFIG_USB_PRINTER=m
251CONFIG_USB_STORAGE=m
252CONFIG_USB_STORAGE_DATAFAB=m
253CONFIG_USB_STORAGE_FREECOM=m
254CONFIG_USB_STORAGE_ISD200=m
255CONFIG_USB_STORAGE_SDDR09=m
256CONFIG_USB_STORAGE_SDDR55=m
257CONFIG_USB_STORAGE_JUMPSHOT=m
258CONFIG_USB_MDC800=m
259CONFIG_USB_MICROTEK=m
260CONFIG_USB_SERIAL=m
261CONFIG_USB_SERIAL_GENERIC=y
262CONFIG_USB_SERIAL_BELKIN=m
263CONFIG_USB_SERIAL_WHITEHEAT=m
264CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
265CONFIG_USB_SERIAL_EMPEG=m
266CONFIG_USB_SERIAL_FTDI_SIO=m
267CONFIG_USB_SERIAL_VISOR=m
268CONFIG_USB_SERIAL_IPAQ=m
269CONFIG_USB_SERIAL_IR=m
270CONFIG_USB_SERIAL_EDGEPORT=m
271CONFIG_USB_SERIAL_EDGEPORT_TI=m
272CONFIG_USB_SERIAL_KEYSPAN_PDA=m
273CONFIG_USB_SERIAL_KEYSPAN=m
274CONFIG_USB_SERIAL_KLSI=m
275CONFIG_USB_SERIAL_KOBIL_SCT=m
276CONFIG_USB_SERIAL_MCT_U232=m
277CONFIG_USB_SERIAL_PL2303=m
278CONFIG_USB_SERIAL_SAFE=m
279CONFIG_USB_SERIAL_SAFE_PADDED=y
280CONFIG_USB_SERIAL_CYBERJACK=m
281CONFIG_USB_SERIAL_XIRCOM=m
282CONFIG_USB_SERIAL_OMNINET=m
283CONFIG_USB_EMI62=m
284CONFIG_USB_RIO500=m
285CONFIG_USB_LEGOTOWER=m
286CONFIG_USB_LCD=m
287CONFIG_USB_LED=m
288CONFIG_USB_TEST=m
289CONFIG_USB_ATM=m
290CONFIG_USB_SPEEDTOUCH=m
291CONFIG_INFINIBAND=m
292CONFIG_INFINIBAND_USER_MAD=m
293CONFIG_INFINIBAND_USER_ACCESS=m
294CONFIG_INFINIBAND_MTHCA=m
295CONFIG_INFINIBAND_IPOIB=m
296CONFIG_INFINIBAND_IPOIB_CM=y
297CONFIG_INFINIBAND_SRP=m
298CONFIG_DMADEVICES=y
299CONFIG_EXT4_FS=m
300CONFIG_EXT4_FS_POSIX_ACL=y
301CONFIG_EXT4_FS_SECURITY=y
302CONFIG_QUOTA=y
303CONFIG_QFMT_V2=y
304CONFIG_AUTOFS4_FS=m
305CONFIG_UDF_FS=m
306CONFIG_MSDOS_FS=m
307CONFIG_VFAT_FS=m
308CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
309CONFIG_PROC_KCORE=y
310CONFIG_TMPFS=y
311CONFIG_HFS_FS=m
312CONFIG_HFSPLUS_FS=m
313CONFIG_JFFS2_FS=y
314CONFIG_CRAMFS=m
315CONFIG_VXFS_FS=m
316CONFIG_NFS_FS=y
317CONFIG_NFS_V3_ACL=y
318CONFIG_NFS_V4=y
319CONFIG_ROOT_NFS=y
320CONFIG_CIFS=m
321CONFIG_CIFS_XATTR=y
322CONFIG_CIFS_POSIX=y
323CONFIG_NLS=y
324CONFIG_NLS_DEFAULT="utf8"
325CONFIG_NLS_CODEPAGE_437=y
326CONFIG_NLS_CODEPAGE_737=m
327CONFIG_NLS_CODEPAGE_775=m
328CONFIG_NLS_CODEPAGE_850=m
329CONFIG_NLS_CODEPAGE_852=m
330CONFIG_NLS_CODEPAGE_855=m
331CONFIG_NLS_CODEPAGE_857=m
332CONFIG_NLS_CODEPAGE_860=m
333CONFIG_NLS_CODEPAGE_861=m
334CONFIG_NLS_CODEPAGE_862=m
335CONFIG_NLS_CODEPAGE_863=m
336CONFIG_NLS_CODEPAGE_864=m
337CONFIG_NLS_CODEPAGE_865=m
338CONFIG_NLS_CODEPAGE_866=m
339CONFIG_NLS_CODEPAGE_869=m
340CONFIG_NLS_CODEPAGE_936=m
341CONFIG_NLS_CODEPAGE_950=m
342CONFIG_NLS_CODEPAGE_932=m
343CONFIG_NLS_CODEPAGE_949=m
344CONFIG_NLS_CODEPAGE_874=m
345CONFIG_NLS_ISO8859_8=m
346CONFIG_NLS_CODEPAGE_1250=m
347CONFIG_NLS_CODEPAGE_1251=m
348CONFIG_NLS_ASCII=y
349CONFIG_NLS_ISO8859_1=m
350CONFIG_NLS_ISO8859_2=m
351CONFIG_NLS_ISO8859_3=m
352CONFIG_NLS_ISO8859_4=m
353CONFIG_NLS_ISO8859_5=m
354CONFIG_NLS_ISO8859_6=m
355CONFIG_NLS_ISO8859_7=m
356CONFIG_NLS_ISO8859_9=m
357CONFIG_NLS_ISO8859_13=m
358CONFIG_NLS_ISO8859_14=m
359CONFIG_NLS_ISO8859_15=m
360CONFIG_NLS_KOI8_R=m
361CONFIG_NLS_KOI8_U=m
362CONFIG_CRC_CCITT=m
363CONFIG_CRC_T10DIF=m
364CONFIG_DEBUG_INFO=y
365CONFIG_MAGIC_SYSRQ=y
366CONFIG_DEBUG_KERNEL=y
367CONFIG_DEBUG_STACK_USAGE=y
368CONFIG_DEBUG_HIGHMEM=y
369CONFIG_DEBUG_STACKOVERFLOW=y
370CONFIG_DETECT_HUNG_TASK=y
371CONFIG_DEBUG_SPINLOCK=y
372CONFIG_BOOTX_TEXT=y
373CONFIG_PPC_EARLY_DEBUG=y
374CONFIG_SECURITY=y
375CONFIG_SECURITY_NETWORK=y
376CONFIG_SECURITY_SELINUX=y
377CONFIG_SECURITY_SELINUX_BOOTPARAM=y
378CONFIG_SECURITY_SELINUX_DISABLE=y
379CONFIG_CRYPTO_HMAC=y
380CONFIG_CRYPTO_MICHAEL_MIC=m
381CONFIG_CRYPTO_SHA1=y
382CONFIG_CRYPTO_SHA512=m
383CONFIG_CRYPTO_WP512=m
384CONFIG_CRYPTO_BLOWFISH=m
385CONFIG_CRYPTO_CAST6=m
386CONFIG_CRYPTO_KHAZAD=m
387CONFIG_CRYPTO_SERPENT=m
388CONFIG_CRYPTO_TEA=m
389CONFIG_CRYPTO_TWOFISH=m
diff --git a/arch/powerpc/platforms/embedded6xx/Kconfig b/arch/powerpc/platforms/embedded6xx/Kconfig
index 9fb2d5912c5a..8ea16db5ff48 100644
--- a/arch/powerpc/platforms/embedded6xx/Kconfig
+++ b/arch/powerpc/platforms/embedded6xx/Kconfig
@@ -48,16 +48,6 @@ config PPC_HOLLY
48 Select PPC_HOLLY if configuring for an IBM 750GX/CL Eval 48 Select PPC_HOLLY if configuring for an IBM 750GX/CL Eval
49 Board with TSI108/9 bridge (Hickory/Holly) 49 Board with TSI108/9 bridge (Hickory/Holly)
50 50
51config PPC_C2K
52 bool "SBS/GEFanuc C2K board"
53 depends on EMBEDDED6xx
54 select MV64X60
55 select NOT_COHERENT_CACHE
56 select MTD_CFI_I4
57 help
58 This option enables support for the GE Fanuc C2K board (formerly
59 an SBS board).
60
61config MVME5100 51config MVME5100
62 bool "Motorola/Emerson MVME5100" 52 bool "Motorola/Emerson MVME5100"
63 depends on EMBEDDED6xx 53 depends on EMBEDDED6xx
diff --git a/arch/powerpc/platforms/embedded6xx/Makefile b/arch/powerpc/platforms/embedded6xx/Makefile
index 12154e3257ad..e656ae9f23c6 100644
--- a/arch/powerpc/platforms/embedded6xx/Makefile
+++ b/arch/powerpc/platforms/embedded6xx/Makefile
@@ -6,7 +6,6 @@ obj-$(CONFIG_MPC7448HPC2) += mpc7448_hpc2.o
6obj-$(CONFIG_LINKSTATION) += linkstation.o ls_uart.o 6obj-$(CONFIG_LINKSTATION) += linkstation.o ls_uart.o
7obj-$(CONFIG_STORCENTER) += storcenter.o 7obj-$(CONFIG_STORCENTER) += storcenter.o
8obj-$(CONFIG_PPC_HOLLY) += holly.o 8obj-$(CONFIG_PPC_HOLLY) += holly.o
9obj-$(CONFIG_PPC_C2K) += c2k.o
10obj-$(CONFIG_USBGECKO_UDBG) += usbgecko_udbg.o 9obj-$(CONFIG_USBGECKO_UDBG) += usbgecko_udbg.o
11obj-$(CONFIG_GAMECUBE_COMMON) += flipper-pic.o 10obj-$(CONFIG_GAMECUBE_COMMON) += flipper-pic.o
12obj-$(CONFIG_GAMECUBE) += gamecube.o 11obj-$(CONFIG_GAMECUBE) += gamecube.o
diff --git a/arch/powerpc/platforms/embedded6xx/c2k.c b/arch/powerpc/platforms/embedded6xx/c2k.c
deleted file mode 100644
index d19e4e759597..000000000000
--- a/arch/powerpc/platforms/embedded6xx/c2k.c
+++ /dev/null
@@ -1,148 +0,0 @@
1/*
2 * Board setup routines for the GEFanuc C2K board
3 *
4 * Author: Remi Machet <rmachet@slac.stanford.edu>
5 *
6 * Originated from prpmc2800.c
7 *
8 * 2008 (c) Stanford University
9 * 2007 (c) MontaVista, Software, Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
14 */
15
16#include <linux/stddef.h>
17#include <linux/kernel.h>
18#include <linux/delay.h>
19#include <linux/interrupt.h>
20#include <linux/seq_file.h>
21#include <linux/time.h>
22#include <linux/of.h>
23
24#include <asm/machdep.h>
25#include <asm/prom.h>
26#include <asm/time.h>
27
28#include <mm/mmu_decl.h>
29
30#include <sysdev/mv64x60.h>
31
32#define MV64x60_MPP_CNTL_0 0x0000
33#define MV64x60_MPP_CNTL_2 0x0008
34
35#define MV64x60_GPP_IO_CNTL 0x0000
36#define MV64x60_GPP_LEVEL_CNTL 0x0010
37#define MV64x60_GPP_VALUE_SET 0x0018
38
39static void __iomem *mv64x60_mpp_reg_base;
40static void __iomem *mv64x60_gpp_reg_base;
41
42static void __init c2k_setup_arch(void)
43{
44 struct device_node *np;
45 phys_addr_t paddr;
46 const unsigned int *reg;
47
48 /*
49 * ioremap mpp and gpp registers in case they are later
50 * needed by c2k_reset_board().
51 */
52 np = of_find_compatible_node(NULL, NULL, "marvell,mv64360-mpp");
53 reg = of_get_property(np, "reg", NULL);
54 paddr = of_translate_address(np, reg);
55 of_node_put(np);
56 mv64x60_mpp_reg_base = ioremap(paddr, reg[1]);
57
58 np = of_find_compatible_node(NULL, NULL, "marvell,mv64360-gpp");
59 reg = of_get_property(np, "reg", NULL);
60 paddr = of_translate_address(np, reg);
61 of_node_put(np);
62 mv64x60_gpp_reg_base = ioremap(paddr, reg[1]);
63
64#ifdef CONFIG_PCI
65 mv64x60_pci_init();
66#endif
67}
68
69static void c2k_reset_board(void)
70{
71 u32 temp;
72
73 local_irq_disable();
74
75 temp = in_le32(mv64x60_mpp_reg_base + MV64x60_MPP_CNTL_0);
76 temp &= 0xFFFF0FFF;
77 out_le32(mv64x60_mpp_reg_base + MV64x60_MPP_CNTL_0, temp);
78
79 temp = in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_LEVEL_CNTL);
80 temp |= 0x00000004;
81 out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_LEVEL_CNTL, temp);
82
83 temp = in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_IO_CNTL);
84 temp |= 0x00000004;
85 out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_IO_CNTL, temp);
86
87 temp = in_le32(mv64x60_mpp_reg_base + MV64x60_MPP_CNTL_2);
88 temp &= 0xFFFF0FFF;
89 out_le32(mv64x60_mpp_reg_base + MV64x60_MPP_CNTL_2, temp);
90
91 temp = in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_LEVEL_CNTL);
92 temp |= 0x00080000;
93 out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_LEVEL_CNTL, temp);
94
95 temp = in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_IO_CNTL);
96 temp |= 0x00080000;
97 out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_IO_CNTL, temp);
98
99 out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_VALUE_SET, 0x00080004);
100}
101
102static void __noreturn c2k_restart(char *cmd)
103{
104 c2k_reset_board();
105 msleep(100);
106 panic("restart failed\n");
107}
108
109#ifdef CONFIG_NOT_COHERENT_CACHE
110#define COHERENCY_SETTING "off"
111#else
112#define COHERENCY_SETTING "on"
113#endif
114
115void c2k_show_cpuinfo(struct seq_file *m)
116{
117 seq_printf(m, "Vendor\t\t: GEFanuc\n");
118 seq_printf(m, "coherency\t: %s\n", COHERENCY_SETTING);
119}
120
121/*
122 * Called very early, device-tree isn't unflattened
123 */
124static int __init c2k_probe(void)
125{
126 if (!of_machine_is_compatible("GEFanuc,C2K"))
127 return 0;
128
129 printk(KERN_INFO "Detected a GEFanuc C2K board\n");
130
131 _set_L2CR(0);
132 _set_L2CR(L2CR_L2E | L2CR_L2PE | L2CR_L2I);
133
134 mv64x60_init_early();
135
136 return 1;
137}
138
139define_machine(c2k) {
140 .name = "C2K",
141 .probe = c2k_probe,
142 .setup_arch = c2k_setup_arch,
143 .show_cpuinfo = c2k_show_cpuinfo,
144 .init_IRQ = mv64x60_init_irq,
145 .get_irq = mv64x60_get_irq,
146 .restart = c2k_restart,
147 .calibrate_decr = generic_calibrate_decr,
148};
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-22 17:48:09 -0400