diff options
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 4 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 20 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/atombios_dp.c | 20 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_display.c | 4 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_pm.c | 5 |
5 files changed, 38 insertions, 15 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 8297bc319369..1846d65b7285 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | |||
| @@ -96,7 +96,7 @@ static void amdgpu_flip_work_func(struct work_struct *__work) | |||
| 96 | * In practice this won't execute very often unless on very fast | 96 | * In practice this won't execute very often unless on very fast |
| 97 | * machines because the time window for this to happen is very small. | 97 | * machines because the time window for this to happen is very small. |
| 98 | */ | 98 | */ |
| 99 | while (amdgpuCrtc->enabled && repcnt--) { | 99 | while (amdgpuCrtc->enabled && --repcnt) { |
| 100 | /* GET_DISTANCE_TO_VBLANKSTART returns distance to real vblank | 100 | /* GET_DISTANCE_TO_VBLANKSTART returns distance to real vblank |
| 101 | * start in hpos, and to the "fudged earlier" vblank start in | 101 | * start in hpos, and to the "fudged earlier" vblank start in |
| 102 | * vpos. | 102 | * vpos. |
| @@ -112,13 +112,13 @@ static void amdgpu_flip_work_func(struct work_struct *__work) | |||
| 112 | break; | 112 | break; |
| 113 | 113 | ||
| 114 | /* Sleep at least until estimated real start of hw vblank */ | 114 | /* Sleep at least until estimated real start of hw vblank */ |
| 115 | spin_unlock_irqrestore(&crtc->dev->event_lock, flags); | ||
| 116 | min_udelay = (-hpos + 1) * max(vblank->linedur_ns / 1000, 5); | 115 | min_udelay = (-hpos + 1) * max(vblank->linedur_ns / 1000, 5); |
| 117 | if (min_udelay > vblank->framedur_ns / 2000) { | 116 | if (min_udelay > vblank->framedur_ns / 2000) { |
| 118 | /* Don't wait ridiculously long - something is wrong */ | 117 | /* Don't wait ridiculously long - something is wrong */ |
| 119 | repcnt = 0; | 118 | repcnt = 0; |
| 120 | break; | 119 | break; |
| 121 | } | 120 | } |
| 121 | spin_unlock_irqrestore(&crtc->dev->event_lock, flags); | ||
| 122 | usleep_range(min_udelay, 2 * min_udelay); | 122 | usleep_range(min_udelay, 2 * min_udelay); |
| 123 | spin_lock_irqsave(&crtc->dev->event_lock, flags); | 123 | spin_lock_irqsave(&crtc->dev->event_lock, flags); |
| 124 | }; | 124 | }; |
diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c index 21aacc1f45c1..bf731e9f643e 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c | |||
| @@ -265,15 +265,27 @@ static int amdgpu_atombios_dp_get_dp_link_config(struct drm_connector *connector | |||
| 265 | unsigned max_lane_num = drm_dp_max_lane_count(dpcd); | 265 | unsigned max_lane_num = drm_dp_max_lane_count(dpcd); |
| 266 | unsigned lane_num, i, max_pix_clock; | 266 | unsigned lane_num, i, max_pix_clock; |
| 267 | 267 | ||
| 268 | for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) { | 268 | if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) == |
| 269 | for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) { | 269 | ENCODER_OBJECT_ID_NUTMEG) { |
| 270 | max_pix_clock = (lane_num * link_rates[i] * 8) / bpp; | 270 | for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) { |
| 271 | max_pix_clock = (lane_num * 270000 * 8) / bpp; | ||
| 271 | if (max_pix_clock >= pix_clock) { | 272 | if (max_pix_clock >= pix_clock) { |
| 272 | *dp_lanes = lane_num; | 273 | *dp_lanes = lane_num; |
| 273 | *dp_rate = link_rates[i]; | 274 | *dp_rate = 270000; |
| 274 | return 0; | 275 | return 0; |
| 275 | } | 276 | } |
| 276 | } | 277 | } |
| 278 | } else { | ||
| 279 | for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) { | ||
| 280 | for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) { | ||
| 281 | max_pix_clock = (lane_num * link_rates[i] * 8) / bpp; | ||
| 282 | if (max_pix_clock >= pix_clock) { | ||
| 283 | *dp_lanes = lane_num; | ||
| 284 | *dp_rate = link_rates[i]; | ||
| 285 | return 0; | ||
| 286 | } | ||
| 287 | } | ||
| 288 | } | ||
| 277 | } | 289 | } |
| 278 | 290 | ||
| 279 | return -EINVAL; | 291 | return -EINVAL; |
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c index 44ee72e04df9..6af832545bc5 100644 --- a/drivers/gpu/drm/radeon/atombios_dp.c +++ b/drivers/gpu/drm/radeon/atombios_dp.c | |||
| @@ -315,15 +315,27 @@ int radeon_dp_get_dp_link_config(struct drm_connector *connector, | |||
| 315 | unsigned max_lane_num = drm_dp_max_lane_count(dpcd); | 315 | unsigned max_lane_num = drm_dp_max_lane_count(dpcd); |
| 316 | unsigned lane_num, i, max_pix_clock; | 316 | unsigned lane_num, i, max_pix_clock; |
| 317 | 317 | ||
| 318 | for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) { | 318 | if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == |
| 319 | for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) { | 319 | ENCODER_OBJECT_ID_NUTMEG) { |
| 320 | max_pix_clock = (lane_num * link_rates[i] * 8) / bpp; | 320 | for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) { |
| 321 | max_pix_clock = (lane_num * 270000 * 8) / bpp; | ||
| 321 | if (max_pix_clock >= pix_clock) { | 322 | if (max_pix_clock >= pix_clock) { |
| 322 | *dp_lanes = lane_num; | 323 | *dp_lanes = lane_num; |
| 323 | *dp_rate = link_rates[i]; | 324 | *dp_rate = 270000; |
| 324 | return 0; | 325 | return 0; |
| 325 | } | 326 | } |
| 326 | } | 327 | } |
| 328 | } else { | ||
| 329 | for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) { | ||
| 330 | for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) { | ||
| 331 | max_pix_clock = (lane_num * link_rates[i] * 8) / bpp; | ||
| 332 | if (max_pix_clock >= pix_clock) { | ||
| 333 | *dp_lanes = lane_num; | ||
| 334 | *dp_rate = link_rates[i]; | ||
| 335 | return 0; | ||
| 336 | } | ||
| 337 | } | ||
| 338 | } | ||
| 327 | } | 339 | } |
| 328 | 340 | ||
| 329 | return -EINVAL; | 341 | return -EINVAL; |
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c index 2b9ba03a7c1a..2d9196a447fd 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c | |||
| @@ -455,7 +455,7 @@ static void radeon_flip_work_func(struct work_struct *__work) | |||
| 455 | * In practice this won't execute very often unless on very fast | 455 | * In practice this won't execute very often unless on very fast |
| 456 | * machines because the time window for this to happen is very small. | 456 | * machines because the time window for this to happen is very small. |
| 457 | */ | 457 | */ |
| 458 | while (radeon_crtc->enabled && repcnt--) { | 458 | while (radeon_crtc->enabled && --repcnt) { |
| 459 | /* GET_DISTANCE_TO_VBLANKSTART returns distance to real vblank | 459 | /* GET_DISTANCE_TO_VBLANKSTART returns distance to real vblank |
| 460 | * start in hpos, and to the "fudged earlier" vblank start in | 460 | * start in hpos, and to the "fudged earlier" vblank start in |
| 461 | * vpos. | 461 | * vpos. |
| @@ -471,13 +471,13 @@ static void radeon_flip_work_func(struct work_struct *__work) | |||
| 471 | break; | 471 | break; |
| 472 | 472 | ||
| 473 | /* Sleep at least until estimated real start of hw vblank */ | 473 | /* Sleep at least until estimated real start of hw vblank */ |
| 474 | spin_unlock_irqrestore(&crtc->dev->event_lock, flags); | ||
| 475 | min_udelay = (-hpos + 1) * max(vblank->linedur_ns / 1000, 5); | 474 | min_udelay = (-hpos + 1) * max(vblank->linedur_ns / 1000, 5); |
| 476 | if (min_udelay > vblank->framedur_ns / 2000) { | 475 | if (min_udelay > vblank->framedur_ns / 2000) { |
| 477 | /* Don't wait ridiculously long - something is wrong */ | 476 | /* Don't wait ridiculously long - something is wrong */ |
| 478 | repcnt = 0; | 477 | repcnt = 0; |
| 479 | break; | 478 | break; |
| 480 | } | 479 | } |
| 480 | spin_unlock_irqrestore(&crtc->dev->event_lock, flags); | ||
| 481 | usleep_range(min_udelay, 2 * min_udelay); | 481 | usleep_range(min_udelay, 2 * min_udelay); |
| 482 | spin_lock_irqsave(&crtc->dev->event_lock, flags); | 482 | spin_lock_irqsave(&crtc->dev->event_lock, flags); |
| 483 | }; | 483 | }; |
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c index 0f14d897baf9..7a98823bacd1 100644 --- a/drivers/gpu/drm/radeon/radeon_pm.c +++ b/drivers/gpu/drm/radeon/radeon_pm.c | |||
| @@ -1079,6 +1079,8 @@ force: | |||
| 1079 | 1079 | ||
| 1080 | /* update display watermarks based on new power state */ | 1080 | /* update display watermarks based on new power state */ |
| 1081 | radeon_bandwidth_update(rdev); | 1081 | radeon_bandwidth_update(rdev); |
| 1082 | /* update displays */ | ||
| 1083 | radeon_dpm_display_configuration_changed(rdev); | ||
| 1082 | 1084 | ||
| 1083 | /* wait for the rings to drain */ | 1085 | /* wait for the rings to drain */ |
| 1084 | for (i = 0; i < RADEON_NUM_RINGS; i++) { | 1086 | for (i = 0; i < RADEON_NUM_RINGS; i++) { |
| @@ -1095,9 +1097,6 @@ force: | |||
| 1095 | 1097 | ||
| 1096 | radeon_dpm_post_set_power_state(rdev); | 1098 | radeon_dpm_post_set_power_state(rdev); |
| 1097 | 1099 | ||
| 1098 | /* update displays */ | ||
| 1099 | radeon_dpm_display_configuration_changed(rdev); | ||
| 1100 | |||
| 1101 | rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; | 1100 | rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; |
| 1102 | rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; | 1101 | rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; |
| 1103 | rdev->pm.dpm.single_display = single_display; | 1102 | rdev->pm.dpm.single_display = single_display; |
