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-rw-r--r--arch/x86/include/asm/topology.h12
-rw-r--r--arch/x86/kernel/cpu/intel.c7
2 files changed, 4 insertions, 15 deletions
diff --git a/arch/x86/include/asm/topology.h b/arch/x86/include/asm/topology.h
index 7f991bd5031b..c9a4ed73aef4 100644
--- a/arch/x86/include/asm/topology.h
+++ b/arch/x86/include/asm/topology.h
@@ -25,16 +25,6 @@
25#ifndef _ASM_X86_TOPOLOGY_H 25#ifndef _ASM_X86_TOPOLOGY_H
26#define _ASM_X86_TOPOLOGY_H 26#define _ASM_X86_TOPOLOGY_H
27 27
28#ifdef CONFIG_X86_32
29# ifdef CONFIG_SMP
30# define ENABLE_TOPO_DEFINES
31# endif
32#else
33# ifdef CONFIG_SMP
34# define ENABLE_TOPO_DEFINES
35# endif
36#endif
37
38/* 28/*
39 * to preserve the visibility of NUMA_NO_NODE definition, 29 * to preserve the visibility of NUMA_NO_NODE definition,
40 * moved to there from here. May be used independent of 30 * moved to there from here. May be used independent of
@@ -123,7 +113,7 @@ extern const struct cpumask *cpu_coregroup_mask(int cpu);
123#define topology_physical_package_id(cpu) (cpu_data(cpu).phys_proc_id) 113#define topology_physical_package_id(cpu) (cpu_data(cpu).phys_proc_id)
124#define topology_core_id(cpu) (cpu_data(cpu).cpu_core_id) 114#define topology_core_id(cpu) (cpu_data(cpu).cpu_core_id)
125 115
126#ifdef ENABLE_TOPO_DEFINES 116#ifdef CONFIG_SMP
127#define topology_core_cpumask(cpu) (per_cpu(cpu_core_map, cpu)) 117#define topology_core_cpumask(cpu) (per_cpu(cpu_core_map, cpu))
128#define topology_sibling_cpumask(cpu) (per_cpu(cpu_sibling_map, cpu)) 118#define topology_sibling_cpumask(cpu) (per_cpu(cpu_sibling_map, cpu))
129 119
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 6e2ffbebbcdb..c1a89bc026ac 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -300,15 +300,14 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
300 } 300 }
301 301
302 /* 302 /*
303 * P4 Xeon errata 037 workaround. 303 * P4 Xeon erratum 037 workaround.
304 * Hardware prefetcher may cause stale data to be loaded into the cache. 304 * Hardware prefetcher may cause stale data to be loaded into the cache.
305 */ 305 */
306 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) { 306 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
307 if (msr_set_bit(MSR_IA32_MISC_ENABLE, 307 if (msr_set_bit(MSR_IA32_MISC_ENABLE,
308 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) 308 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) {
309 > 0) {
310 pr_info("CPU: C0 stepping P4 Xeon detected.\n"); 309 pr_info("CPU: C0 stepping P4 Xeon detected.\n");
311 pr_info("CPU: Disabling hardware prefetching (Errata 037)\n"); 310 pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n");
312 } 311 }
313 } 312 }
314 313