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-rw-r--r--arch/arm64/boot/dts/freescale/Makefile3
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1012a-oxalis.dts4
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi2
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts62
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts63
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi64
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts1
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi2
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi2
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts16
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts16
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi69
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mm-evk.dts235
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mm.dtsi733
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mq-evk.dts129
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts95
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-zest.dts24
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi725
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mq.dtsi309
-rw-r--r--arch/arm64/boot/dts/freescale/imx8qxp-mek.dts95
-rw-r--r--arch/arm64/boot/dts/freescale/imx8qxp.dtsi89
21 files changed, 2725 insertions, 13 deletions
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 13604e558dc1..0bd122f60549 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -20,5 +20,8 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
20dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb 20dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
21dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb 21dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
22 22
23dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
23dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb 24dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
25dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
26dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb
24dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb 27dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-oxalis.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-oxalis.dts
index 7c726267ec8f..9927b096d343 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-oxalis.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-oxalis.dts
@@ -87,6 +87,10 @@
87 status = "okay"; 87 status = "okay";
88}; 88};
89 89
90&pcie {
91 status = "okay";
92};
93
90&sai2 { 94&sai2 {
91 status = "okay"; 95 status = "okay";
92}; 96};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
index 1ce0042b2a14..ec6257a5b251 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -475,7 +475,7 @@
475 interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; 475 interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
476 }; 476 };
477 477
478 pcie@3400000 { 478 pcie: pcie@3400000 {
479 compatible = "fsl,ls1012a-pcie"; 479 compatible = "fsl,ls1012a-pcie";
480 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 480 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
481 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ 481 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
index 14c79f4691ea..b359068d9605 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
@@ -32,6 +32,49 @@
32 device_type = "memory"; 32 device_type = "memory";
33 reg = <0x0 0x80000000 0x1 0x00000000>; 33 reg = <0x0 0x80000000 0x1 0x00000000>;
34 }; 34 };
35
36 sys_mclk: clock-mclk {
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
39 clock-frequency = <25000000>;
40 };
41
42 reg_1p8v: regulator-1p8v {
43 compatible = "regulator-fixed";
44 regulator-name = "1P8V";
45 regulator-min-microvolt = <1800000>;
46 regulator-max-microvolt = <1800000>;
47 regulator-always-on;
48 };
49
50 sound {
51 compatible = "simple-audio-card";
52 simple-audio-card,format = "i2s";
53 simple-audio-card,widgets =
54 "Microphone", "Microphone Jack",
55 "Headphone", "Headphone Jack",
56 "Speaker", "Speaker Ext",
57 "Line", "Line In Jack";
58 simple-audio-card,routing =
59 "MIC_IN", "Microphone Jack",
60 "Microphone Jack", "Mic Bias",
61 "LINE_IN", "Line In Jack",
62 "Headphone Jack", "HP_OUT",
63 "Speaker Ext", "LINE_OUT";
64
65 simple-audio-card,cpu {
66 sound-dai = <&sai1>;
67 frame-master;
68 bitclock-master;
69 };
70
71 simple-audio-card,codec {
72 sound-dai = <&sgtl5000>;
73 frame-master;
74 bitclock-master;
75 system-clock-frequency = <25000000>;
76 };
77 };
35}; 78};
36 79
37&duart0 { 80&duart0 {
@@ -89,5 +132,24 @@
89 reg = <0x57>; 132 reg = <0x57>;
90 }; 133 };
91 }; 134 };
135
136 i2c@5 {
137 #address-cells = <1>;
138 #size-cells = <0>;
139 reg = <0x5>;
140
141 sgtl5000: audio-codec@a {
142 #sound-dai-cells = <0>;
143 compatible = "fsl,sgtl5000";
144 reg = <0xa>;
145 VDDA-supply = <&reg_1p8v>;
146 VDDIO-supply = <&reg_1p8v>;
147 clocks = <&sys_mclk>;
148 };
149 };
92 }; 150 };
93}; 151};
152
153&sai1 {
154 status = "okay";
155};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
index f86b054a74ae..f9c272fb0738 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -28,6 +28,49 @@
28 device_type = "memory"; 28 device_type = "memory";
29 reg = <0x0 0x80000000 0x1 0x0000000>; 29 reg = <0x0 0x80000000 0x1 0x0000000>;
30 }; 30 };
31
32 sys_mclk: clock-mclk {
33 compatible = "fixed-clock";
34 #clock-cells = <0>;
35 clock-frequency = <25000000>;
36 };
37
38 reg_1p8v: regulator-1p8v {
39 compatible = "regulator-fixed";
40 regulator-name = "1P8V";
41 regulator-min-microvolt = <1800000>;
42 regulator-max-microvolt = <1800000>;
43 regulator-always-on;
44 };
45
46 sound {
47 compatible = "simple-audio-card";
48 simple-audio-card,format = "i2s";
49 simple-audio-card,widgets =
50 "Microphone", "Microphone Jack",
51 "Headphone", "Headphone Jack",
52 "Speaker", "Speaker Ext",
53 "Line", "Line In Jack";
54 simple-audio-card,routing =
55 "MIC_IN", "Microphone Jack",
56 "Microphone Jack", "Mic Bias",
57 "LINE_IN", "Line In Jack",
58 "Headphone Jack", "HP_OUT",
59 "Speaker Ext", "LINE_OUT";
60
61 simple-audio-card,cpu {
62 sound-dai = <&sai4>;
63 frame-master;
64 bitclock-master;
65 };
66
67 simple-audio-card,codec {
68 sound-dai = <&sgtl5000>;
69 frame-master;
70 bitclock-master;
71 system-clock-frequency = <25000000>;
72 };
73 };
31}; 74};
32 75
33&i2c0 { 76&i2c0 {
@@ -39,6 +82,22 @@
39 #address-cells = <1>; 82 #address-cells = <1>;
40 #size-cells = <0>; 83 #size-cells = <0>;
41 84
85 i2c@1 {
86 #address-cells = <1>;
87 #size-cells = <0>;
88 reg = <0x1>;
89
90 sgtl5000: audio-codec@a {
91 #sound-dai-cells = <0>;
92 compatible = "fsl,sgtl5000";
93 reg = <0xa>;
94 VDDA-supply = <&reg_1p8v>;
95 VDDIO-supply = <&reg_1p8v>;
96 clocks = <&sys_mclk>;
97 sclk-strength = <3>;
98 };
99 };
100
42 i2c@2 { 101 i2c@2 {
43 #address-cells = <1>; 102 #address-cells = <1>;
44 #size-cells = <0>; 103 #size-cells = <0>;
@@ -88,3 +147,7 @@
88&enetc_port1 { 147&enetc_port1 {
89 status = "disabled"; 148 status = "disabled";
90}; 149};
150
151&sai4 {
152 status = "okay";
153};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 2896bbcfa3bb..b04581249f0b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -89,6 +89,11 @@
89 IRQ_TYPE_LEVEL_LOW)>; 89 IRQ_TYPE_LEVEL_LOW)>;
90 }; 90 };
91 91
92 pmu {
93 compatible = "arm,cortex-a72-pmu";
94 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
95 };
96
92 gic: interrupt-controller@6000000 { 97 gic: interrupt-controller@6000000 {
93 compatible= "arm,gic-v3"; 98 compatible= "arm,gic-v3";
94 #address-cells = <2>; 99 #address-cells = <2>;
@@ -235,6 +240,21 @@
235 status = "disabled"; 240 status = "disabled";
236 }; 241 };
237 242
243 edma0: dma-controller@22c0000 {
244 #dma-cells = <2>;
245 compatible = "fsl,vf610-edma";
246 reg = <0x0 0x22c0000 0x0 0x10000>,
247 <0x0 0x22d0000 0x0 0x10000>,
248 <0x0 0x22e0000 0x0 0x10000>;
249 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
251 interrupt-names = "edma-tx", "edma-err";
252 dma-channels = <32>;
253 clock-names = "dmamux0", "dmamux1";
254 clocks = <&clockgen 4 1>,
255 <&clockgen 4 1>;
256 };
257
238 gpio1: gpio@2300000 { 258 gpio1: gpio@2300000 {
239 compatible = "fsl,qoriq-gpio"; 259 compatible = "fsl,qoriq-gpio";
240 reg = <0x0 0x2300000 0x0 0x10000>; 260 reg = <0x0 0x2300000 0x0 0x10000>;
@@ -277,7 +297,7 @@
277 sata: sata@3200000 { 297 sata: sata@3200000 {
278 compatible = "fsl,ls1028a-ahci"; 298 compatible = "fsl,ls1028a-ahci";
279 reg = <0x0 0x3200000 0x0 0x10000>, 299 reg = <0x0 0x3200000 0x0 0x10000>,
280 <0x0 0x20140520 0x0 0x4>; 300 <0x7 0x100520 0x0 0x4>;
281 reg-names = "ahci", "sata-ecc"; 301 reg-names = "ahci", "sata-ecc";
282 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 302 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
283 clocks = <&clockgen 4 1>; 303 clocks = <&clockgen 4 1>;
@@ -336,6 +356,48 @@
336 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 356 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
337 }; 357 };
338 358
359 sai1: audio-controller@f100000 {
360 #sound-dai-cells = <0>;
361 compatible = "fsl,vf610-sai";
362 reg = <0x0 0xf100000 0x0 0x10000>;
363 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
364 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
365 <&clockgen 4 1>, <&clockgen 4 1>;
366 clock-names = "bus", "mclk1", "mclk2", "mclk3";
367 dma-names = "tx", "rx";
368 dmas = <&edma0 1 4>,
369 <&edma0 1 3>;
370 status = "disabled";
371 };
372
373 sai2: audio-controller@f110000 {
374 #sound-dai-cells = <0>;
375 compatible = "fsl,vf610-sai";
376 reg = <0x0 0xf110000 0x0 0x10000>;
377 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
379 <&clockgen 4 1>, <&clockgen 4 1>;
380 clock-names = "bus", "mclk1", "mclk2", "mclk3";
381 dma-names = "tx", "rx";
382 dmas = <&edma0 1 6>,
383 <&edma0 1 5>;
384 status = "disabled";
385 };
386
387 sai4: audio-controller@f130000 {
388 #sound-dai-cells = <0>;
389 compatible = "fsl,vf610-sai";
390 reg = <0x0 0xf130000 0x0 0x10000>;
391 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
392 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
393 <&clockgen 4 1>, <&clockgen 4 1>;
394 clock-names = "bus", "mclk1", "mclk2", "mclk3";
395 dma-names = "tx", "rx";
396 dmas = <&edma0 1 10>,
397 <&edma0 1 9>;
398 status = "disabled";
399 };
400
339 pcie@1f0000000 { /* Integrated Endpoint Root Complex */ 401 pcie@1f0000000 { /* Integrated Endpoint Root Complex */
340 compatible = "pci-host-ecam-generic"; 402 compatible = "pci-host-ecam-generic";
341 reg = <0x01 0xf0000000 0x0 0x100000>; 403 reg = <0x01 0xf0000000 0x0 0x100000>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
index 17ca357e854f..4223a2352d45 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
@@ -15,7 +15,6 @@
15 model = "LS1043A RDB Board"; 15 model = "LS1043A RDB Board";
16 16
17 aliases { 17 aliases {
18 crypto = &crypto;
19 serial0 = &duart0; 18 serial0 = &duart0;
20 serial1 = &duart1; 19 serial1 = &duart1;
21 serial2 = &duart2; 20 serial2 = &duart2;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 6fd6116509cc..71d9ed9ff985 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -18,6 +18,7 @@
18 #size-cells = <2>; 18 #size-cells = <2>;
19 19
20 aliases { 20 aliases {
21 crypto = &crypto;
21 fman0 = &fman0; 22 fman0 = &fman0;
22 ethernet0 = &enet0; 23 ethernet0 = &enet0;
23 ethernet1 = &enet1; 24 ethernet1 = &enet1;
@@ -296,7 +297,6 @@
296 interrupts = <0 99 0x4>; 297 interrupts = <0 99 0x4>;
297 clock-names = "qspi_en", "qspi"; 298 clock-names = "qspi_en", "qspi";
298 clocks = <&clockgen 4 0>, <&clockgen 4 0>; 299 clocks = <&clockgen 4 0>, <&clockgen 4 0>;
299 big-endian;
300 status = "disabled"; 300 status = "disabled";
301 }; 301 };
302 302
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index cb7185014d3a..b0ef08b090dd 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -215,8 +215,6 @@
215 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 215 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
216 clock-names = "qspi_en", "qspi"; 216 clock-names = "qspi_en", "qspi";
217 clocks = <&clockgen 4 1>, <&clockgen 4 1>; 217 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
218 big-endian;
219 fsl,qspi-has-second-chip;
220 status = "disabled"; 218 status = "disabled";
221 }; 219 };
222 220
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
index 99a22abbe725..1a5acf62f23c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
@@ -95,6 +95,22 @@
95 }; 95 };
96}; 96};
97 97
98&sata0 {
99 status = "okay";
100};
101
102&sata1 {
103 status = "okay";
104};
105
106&sata2 {
107 status = "okay";
108};
109
110&sata3 {
111 status = "okay";
112};
113
98&uart0 { 114&uart0 {
99 status = "okay"; 115 status = "okay";
100}; 116};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 9df37b159415..c2817b784232 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -128,6 +128,22 @@
128 }; 128 };
129}; 129};
130 130
131&sata0 {
132 status = "okay";
133};
134
135&sata1 {
136 status = "okay";
137};
138
139&sata2 {
140 status = "okay";
141};
142
143&sata3 {
144 status = "okay";
145};
146
131&uart0 { 147&uart0 {
132 status = "okay"; 148 status = "okay";
133}; 149};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index fe87204850b5..125a8cc2c5b3 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -33,6 +33,7 @@
33 i-cache-line-size = <64>; 33 i-cache-line-size = <64>;
34 i-cache-sets = <192>; 34 i-cache-sets = <192>;
35 next-level-cache = <&cluster0_l2>; 35 next-level-cache = <&cluster0_l2>;
36 cpu-idle-states = <&cpu_pw20>;
36 }; 37 };
37 38
38 cpu@1 { 39 cpu@1 {
@@ -48,6 +49,7 @@
48 i-cache-line-size = <64>; 49 i-cache-line-size = <64>;
49 i-cache-sets = <192>; 50 i-cache-sets = <192>;
50 next-level-cache = <&cluster0_l2>; 51 next-level-cache = <&cluster0_l2>;
52 cpu-idle-states = <&cpu_pw20>;
51 }; 53 };
52 54
53 cpu@100 { 55 cpu@100 {
@@ -63,6 +65,7 @@
63 i-cache-line-size = <64>; 65 i-cache-line-size = <64>;
64 i-cache-sets = <192>; 66 i-cache-sets = <192>;
65 next-level-cache = <&cluster1_l2>; 67 next-level-cache = <&cluster1_l2>;
68 cpu-idle-states = <&cpu_pw20>;
66 }; 69 };
67 70
68 cpu@101 { 71 cpu@101 {
@@ -78,6 +81,7 @@
78 i-cache-line-size = <64>; 81 i-cache-line-size = <64>;
79 i-cache-sets = <192>; 82 i-cache-sets = <192>;
80 next-level-cache = <&cluster1_l2>; 83 next-level-cache = <&cluster1_l2>;
84 cpu-idle-states = <&cpu_pw20>;
81 }; 85 };
82 86
83 cpu@200 { 87 cpu@200 {
@@ -93,6 +97,7 @@
93 i-cache-line-size = <64>; 97 i-cache-line-size = <64>;
94 i-cache-sets = <192>; 98 i-cache-sets = <192>;
95 next-level-cache = <&cluster2_l2>; 99 next-level-cache = <&cluster2_l2>;
100 cpu-idle-states = <&cpu_pw20>;
96 }; 101 };
97 102
98 cpu@201 { 103 cpu@201 {
@@ -108,6 +113,7 @@
108 i-cache-line-size = <64>; 113 i-cache-line-size = <64>;
109 i-cache-sets = <192>; 114 i-cache-sets = <192>;
110 next-level-cache = <&cluster2_l2>; 115 next-level-cache = <&cluster2_l2>;
116 cpu-idle-states = <&cpu_pw20>;
111 }; 117 };
112 118
113 cpu@300 { 119 cpu@300 {
@@ -123,6 +129,7 @@
123 i-cache-line-size = <64>; 129 i-cache-line-size = <64>;
124 i-cache-sets = <192>; 130 i-cache-sets = <192>;
125 next-level-cache = <&cluster3_l2>; 131 next-level-cache = <&cluster3_l2>;
132 cpu-idle-states = <&cpu_pw20>;
126 }; 133 };
127 134
128 cpu@301 { 135 cpu@301 {
@@ -138,6 +145,7 @@
138 i-cache-line-size = <64>; 145 i-cache-line-size = <64>;
139 i-cache-sets = <192>; 146 i-cache-sets = <192>;
140 next-level-cache = <&cluster3_l2>; 147 next-level-cache = <&cluster3_l2>;
148 cpu-idle-states = <&cpu_pw20>;
141 }; 149 };
142 150
143 cpu@400 { 151 cpu@400 {
@@ -153,6 +161,7 @@
153 i-cache-line-size = <64>; 161 i-cache-line-size = <64>;
154 i-cache-sets = <192>; 162 i-cache-sets = <192>;
155 next-level-cache = <&cluster4_l2>; 163 next-level-cache = <&cluster4_l2>;
164 cpu-idle-states = <&cpu_pw20>;
156 }; 165 };
157 166
158 cpu@401 { 167 cpu@401 {
@@ -168,6 +177,7 @@
168 i-cache-line-size = <64>; 177 i-cache-line-size = <64>;
169 i-cache-sets = <192>; 178 i-cache-sets = <192>;
170 next-level-cache = <&cluster4_l2>; 179 next-level-cache = <&cluster4_l2>;
180 cpu-idle-states = <&cpu_pw20>;
171 }; 181 };
172 182
173 cpu@500 { 183 cpu@500 {
@@ -183,6 +193,7 @@
183 i-cache-line-size = <64>; 193 i-cache-line-size = <64>;
184 i-cache-sets = <192>; 194 i-cache-sets = <192>;
185 next-level-cache = <&cluster5_l2>; 195 next-level-cache = <&cluster5_l2>;
196 cpu-idle-states = <&cpu_pw20>;
186 }; 197 };
187 198
188 cpu@501 { 199 cpu@501 {
@@ -198,6 +209,7 @@
198 i-cache-line-size = <64>; 209 i-cache-line-size = <64>;
199 i-cache-sets = <192>; 210 i-cache-sets = <192>;
200 next-level-cache = <&cluster5_l2>; 211 next-level-cache = <&cluster5_l2>;
212 cpu-idle-states = <&cpu_pw20>;
201 }; 213 };
202 214
203 cpu@600 { 215 cpu@600 {
@@ -213,6 +225,7 @@
213 i-cache-line-size = <64>; 225 i-cache-line-size = <64>;
214 i-cache-sets = <192>; 226 i-cache-sets = <192>;
215 next-level-cache = <&cluster6_l2>; 227 next-level-cache = <&cluster6_l2>;
228 cpu-idle-states = <&cpu_pw20>;
216 }; 229 };
217 230
218 cpu@601 { 231 cpu@601 {
@@ -228,6 +241,7 @@
228 i-cache-line-size = <64>; 241 i-cache-line-size = <64>;
229 i-cache-sets = <192>; 242 i-cache-sets = <192>;
230 next-level-cache = <&cluster6_l2>; 243 next-level-cache = <&cluster6_l2>;
244 cpu-idle-states = <&cpu_pw20>;
231 }; 245 };
232 246
233 cpu@700 { 247 cpu@700 {
@@ -243,6 +257,7 @@
243 i-cache-line-size = <64>; 257 i-cache-line-size = <64>;
244 i-cache-sets = <192>; 258 i-cache-sets = <192>;
245 next-level-cache = <&cluster7_l2>; 259 next-level-cache = <&cluster7_l2>;
260 cpu-idle-states = <&cpu_pw20>;
246 }; 261 };
247 262
248 cpu@701 { 263 cpu@701 {
@@ -258,6 +273,7 @@
258 i-cache-line-size = <64>; 273 i-cache-line-size = <64>;
259 i-cache-sets = <192>; 274 i-cache-sets = <192>;
260 next-level-cache = <&cluster7_l2>; 275 next-level-cache = <&cluster7_l2>;
276 cpu-idle-states = <&cpu_pw20>;
261 }; 277 };
262 278
263 cluster0_l2: l2-cache0 { 279 cluster0_l2: l2-cache0 {
@@ -323,6 +339,15 @@
323 cache-sets = <1024>; 339 cache-sets = <1024>;
324 cache-level = <2>; 340 cache-level = <2>;
325 }; 341 };
342
343 cpu_pw20: cpu-pw20 {
344 compatible = "arm,idle-state";
345 idle-state-name = "PW20";
346 arm,psci-suspend-param = <0x0>;
347 entry-latency-us = <2000>;
348 exit-latency-us = <2000>;
349 min-residency-us = <6000>;
350 };
326 }; 351 };
327 352
328 gic: interrupt-controller@6000000 { 353 gic: interrupt-controller@6000000 {
@@ -687,6 +712,50 @@
687 status = "disabled"; 712 status = "disabled";
688 }; 713 };
689 714
715 sata0: sata@3200000 {
716 compatible = "fsl,lx2160a-ahci";
717 reg = <0x0 0x3200000 0x0 0x10000>,
718 <0x7 0x100520 0x0 0x4>;
719 reg-names = "ahci", "sata-ecc";
720 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
721 clocks = <&clockgen 4 3>;
722 dma-coherent;
723 status = "disabled";
724 };
725
726 sata1: sata@3210000 {
727 compatible = "fsl,lx2160a-ahci";
728 reg = <0x0 0x3210000 0x0 0x10000>,
729 <0x7 0x100520 0x0 0x4>;
730 reg-names = "ahci", "sata-ecc";
731 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
732 clocks = <&clockgen 4 3>;
733 dma-coherent;
734 status = "disabled";
735 };
736
737 sata2: sata@3220000 {
738 compatible = "fsl,lx2160a-ahci";
739 reg = <0x0 0x3220000 0x0 0x10000>,
740 <0x7 0x100520 0x0 0x4>;
741 reg-names = "ahci", "sata-ecc";
742 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
743 clocks = <&clockgen 4 3>;
744 dma-coherent;
745 status = "disabled";
746 };
747
748 sata3: sata@3230000 {
749 compatible = "fsl,lx2160a-ahci";
750 reg = <0x0 0x3230000 0x0 0x10000>,
751 <0x7 0x100520 0x0 0x4>;
752 reg-names = "ahci", "sata-ecc";
753 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
754 clocks = <&clockgen 4 3>;
755 dma-coherent;
756 status = "disabled";
757 };
758
690 smmu: iommu@5000000 { 759 smmu: iommu@5000000 {
691 compatible = "arm,mmu-500"; 760 compatible = "arm,mmu-500";
692 reg = <0 0x5000000 0 0x800000>; 761 reg = <0 0x5000000 0 0x800000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
new file mode 100644
index 000000000000..2d5d89475b76
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
@@ -0,0 +1,235 @@
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6/dts-v1/;
7
8#include "imx8mm.dtsi"
9
10/ {
11 model = "FSL i.MX8MM EVK board";
12 compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
13
14 chosen {
15 stdout-path = &uart2;
16 };
17
18 leds {
19 compatible = "gpio-leds";
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_gpio_led>;
22
23 status {
24 label = "status";
25 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
26 default-state = "on";
27 };
28 };
29
30 reg_usdhc2_vmmc: regulator-usdhc2 {
31 compatible = "regulator-fixed";
32 pinctrl-names = "default";
33 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
34 regulator-name = "VSD_3V3";
35 regulator-min-microvolt = <3300000>;
36 regulator-max-microvolt = <3300000>;
37 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
38 enable-active-high;
39 };
40};
41
42&fec1 {
43 pinctrl-names = "default";
44 pinctrl-0 = <&pinctrl_fec1>;
45 phy-mode = "rgmii-id";
46 phy-handle = <&ethphy0>;
47 fsl,magic-packet;
48 status = "okay";
49
50 mdio {
51 #address-cells = <1>;
52 #size-cells = <0>;
53
54 ethphy0: ethernet-phy@0 {
55 compatible = "ethernet-phy-ieee802.3-c22";
56 reg = <0>;
57 at803x,led-act-blind-workaround;
58 at803x,eee-okay;
59 at803x,vddio-1p8v;
60 };
61 };
62};
63
64&uart2 { /* console */
65 pinctrl-names = "default";
66 pinctrl-0 = <&pinctrl_uart2>;
67 status = "okay";
68};
69
70&usdhc2 {
71 pinctrl-names = "default", "state_100mhz", "state_200mhz";
72 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
73 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
74 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
75 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
76 bus-width = <4>;
77 vmmc-supply = <&reg_usdhc2_vmmc>;
78 status = "okay";
79};
80
81&usdhc3 {
82 pinctrl-names = "default", "state_100mhz", "state_200mhz";
83 pinctrl-0 = <&pinctrl_usdhc3>;
84 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
85 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
86 bus-width = <8>;
87 non-removable;
88 status = "okay";
89};
90
91&wdog1 {
92 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_wdog>;
94 fsl,ext-reset-output;
95 status = "okay";
96};
97
98&iomuxc {
99 pinctrl-names = "default";
100
101 pinctrl_fec1: fec1grp {
102 fsl,pins = <
103 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
104 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
105 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
106 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
107 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
108 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
109 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
110 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
111 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
112 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
113 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
114 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
115 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
116 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
117 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
118 >;
119 };
120
121 pinctrl_gpio_led: gpioledgrp {
122 fsl,pins = <
123 MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
124 >;
125 };
126
127 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
128 fsl,pins = <
129 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
130 >;
131 };
132
133 pinctrl_uart2: uart2grp {
134 fsl,pins = <
135 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
136 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
137 >;
138 };
139
140 pinctrl_usdhc2_gpio: usdhc2grpgpio {
141 fsl,pins = <
142 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
143 >;
144 };
145
146 pinctrl_usdhc2: usdhc2grp {
147 fsl,pins = <
148 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
149 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
150 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
151 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
152 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
153 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
154 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
155 >;
156 };
157
158 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
159 fsl,pins = <
160 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
161 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
162 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
163 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
164 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
165 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
166 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
167 >;
168 };
169
170 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
171 fsl,pins = <
172 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
173 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
174 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
175 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
176 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
177 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
178 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
179 >;
180 };
181
182 pinctrl_usdhc3: usdhc3grp {
183 fsl,pins = <
184 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
185 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
186 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
187 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
188 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
189 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
190 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
191 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
192 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
193 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
194 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
195 >;
196 };
197
198 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
199 fsl,pins = <
200 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
201 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
202 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
203 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
204 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
205 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
206 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
207 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
208 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
209 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
210 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
211 >;
212 };
213
214 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
215 fsl,pins = <
216 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
217 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
218 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
219 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
220 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
221 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
222 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
223 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
224 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
225 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
226 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
227 >;
228 };
229
230 pinctrl_wdog: wdoggrp {
231 fsl,pins = <
232 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
233 >;
234 };
235};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
new file mode 100644
index 000000000000..6b407a94c06e
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -0,0 +1,733 @@
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/clock/imx8mm-clock.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/input/input.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/thermal/thermal.h>
11
12#include "imx8mm-pinfunc.h"
13
14/ {
15 compatible = "fsl,imx8mm";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 aliases {
21 ethernet0 = &fec1;
22 i2c0 = &i2c1;
23 i2c1 = &i2c2;
24 i2c2 = &i2c3;
25 i2c3 = &i2c4;
26 serial0 = &uart1;
27 serial1 = &uart2;
28 serial2 = &uart3;
29 serial3 = &uart4;
30 spi0 = &ecspi1;
31 spi1 = &ecspi2;
32 spi2 = &ecspi3;
33 mmc0 = &usdhc1;
34 mmc1 = &usdhc2;
35 mmc2 = &usdhc3;
36 gpio0 = &gpio1;
37 gpio1 = &gpio2;
38 gpio2 = &gpio3;
39 gpio3 = &gpio4;
40 gpio4 = &gpio5;
41 };
42
43 cpus {
44 #address-cells = <1>;
45 #size-cells = <0>;
46
47 A53_0: cpu@0 {
48 device_type = "cpu";
49 compatible = "arm,cortex-a53";
50 reg = <0x0>;
51 clock-latency = <61036>; /* two CLK32 periods */
52 clocks = <&clk IMX8MM_CLK_ARM>;
53 enable-method = "psci";
54 next-level-cache = <&A53_L2>;
55 operating-points-v2 = <&a53_opp_table>;
56 };
57
58 A53_1: cpu@1 {
59 device_type = "cpu";
60 compatible = "arm,cortex-a53";
61 reg = <0x1>;
62 clock-latency = <61036>; /* two CLK32 periods */
63 clocks = <&clk IMX8MM_CLK_ARM>;
64 enable-method = "psci";
65 next-level-cache = <&A53_L2>;
66 operating-points-v2 = <&a53_opp_table>;
67 };
68
69 A53_2: cpu@2 {
70 device_type = "cpu";
71 compatible = "arm,cortex-a53";
72 reg = <0x2>;
73 clock-latency = <61036>; /* two CLK32 periods */
74 clocks = <&clk IMX8MM_CLK_ARM>;
75 enable-method = "psci";
76 next-level-cache = <&A53_L2>;
77 operating-points-v2 = <&a53_opp_table>;
78 };
79
80 A53_3: cpu@3 {
81 device_type = "cpu";
82 compatible = "arm,cortex-a53";
83 reg = <0x3>;
84 clock-latency = <61036>; /* two CLK32 periods */
85 clocks = <&clk IMX8MM_CLK_ARM>;
86 enable-method = "psci";
87 next-level-cache = <&A53_L2>;
88 operating-points-v2 = <&a53_opp_table>;
89 };
90
91 A53_L2: l2-cache0 {
92 compatible = "cache";
93 };
94 };
95
96 a53_opp_table: opp-table {
97 compatible = "operating-points-v2";
98 opp-shared;
99
100 opp-1200000000 {
101 opp-hz = /bits/ 64 <1200000000>;
102 opp-microvolt = <850000>;
103 clock-latency-ns = <150000>;
104 };
105
106 opp-1600000000 {
107 opp-hz = /bits/ 64 <1600000000>;
108 opp-microvolt = <900000>;
109 clock-latency-ns = <150000>;
110 opp-suspend;
111 };
112 };
113
114 memory@40000000 {
115 device_type = "memory";
116 reg = <0x0 0x40000000 0 0x80000000>;
117 };
118
119 osc_32k: clock-osc-32k {
120 compatible = "fixed-clock";
121 #clock-cells = <0>;
122 clock-frequency = <32768>;
123 clock-output-names = "osc_32k";
124 };
125
126 osc_24m: clock-osc-24m {
127 compatible = "fixed-clock";
128 #clock-cells = <0>;
129 clock-frequency = <24000000>;
130 clock-output-names = "osc_24m";
131 };
132
133 clk_ext1: clock-ext1 {
134 compatible = "fixed-clock";
135 #clock-cells = <0>;
136 clock-frequency = <133000000>;
137 clock-output-names = "clk_ext1";
138 };
139
140 clk_ext2: clock-ext2 {
141 compatible = "fixed-clock";
142 #clock-cells = <0>;
143 clock-frequency = <133000000>;
144 clock-output-names = "clk_ext2";
145 };
146
147 clk_ext3: clock-ext3 {
148 compatible = "fixed-clock";
149 #clock-cells = <0>;
150 clock-frequency = <133000000>;
151 clock-output-names = "clk_ext3";
152 };
153
154 clk_ext4: clock-ext4 {
155 compatible = "fixed-clock";
156 #clock-cells = <0>;
157 clock-frequency= <133000000>;
158 clock-output-names = "clk_ext4";
159 };
160
161 gic: interrupt-controller@38800000 {
162 compatible = "arm,gic-v3";
163 reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */
164 <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
165 #interrupt-cells = <3>;
166 interrupt-controller;
167 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
168 };
169
170 psci {
171 compatible = "arm,psci-1.0";
172 method = "smc";
173 };
174
175 pmu {
176 compatible = "arm,armv8-pmuv3";
177 interrupts = <GIC_PPI 7
178 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
179 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
180 };
181
182 timer {
183 compatible = "arm,armv8-timer";
184 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
185 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
186 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
187 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
188 clock-frequency = <8000000>;
189 arm,no-tick-in-suspend;
190 };
191
192 soc {
193 compatible = "simple-bus";
194 #address-cells = <1>;
195 #size-cells = <1>;
196 ranges = <0x0 0x0 0x0 0x3e000000>;
197
198 aips1: bus@30000000 {
199 compatible = "fsl,aips-bus", "simple-bus";
200 #address-cells = <1>;
201 #size-cells = <1>;
202 ranges;
203
204 gpio1: gpio@30200000 {
205 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
206 reg = <0x30200000 0x10000>;
207 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
209 gpio-controller;
210 #gpio-cells = <2>;
211 interrupt-controller;
212 #interrupt-cells = <2>;
213 };
214
215 gpio2: gpio@30210000 {
216 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
217 reg = <0x30210000 0x10000>;
218 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
220 gpio-controller;
221 #gpio-cells = <2>;
222 interrupt-controller;
223 #interrupt-cells = <2>;
224 };
225
226 gpio3: gpio@30220000 {
227 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
228 reg = <0x30220000 0x10000>;
229 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
230 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
231 gpio-controller;
232 #gpio-cells = <2>;
233 interrupt-controller;
234 #interrupt-cells = <2>;
235 };
236
237 gpio4: gpio@30230000 {
238 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
239 reg = <0x30230000 0x10000>;
240 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
242 gpio-controller;
243 #gpio-cells = <2>;
244 interrupt-controller;
245 #interrupt-cells = <2>;
246 };
247
248 gpio5: gpio@30240000 {
249 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
250 reg = <0x30240000 0x10000>;
251 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
253 gpio-controller;
254 #gpio-cells = <2>;
255 interrupt-controller;
256 #interrupt-cells = <2>;
257 };
258
259 wdog1: watchdog@30280000 {
260 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
261 reg = <0x30280000 0x10000>;
262 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
263 clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>;
264 status = "disabled";
265 };
266
267 wdog2: watchdog@30290000 {
268 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
269 reg = <0x30290000 0x10000>;
270 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
271 clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>;
272 status = "disabled";
273 };
274
275 wdog3: watchdog@302a0000 {
276 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
277 reg = <0x302a0000 0x10000>;
278 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>;
280 status = "disabled";
281 };
282
283 sdma2: dma-controller@302c0000 {
284 compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma";
285 reg = <0x302c0000 0x10000>;
286 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
287 clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>,
288 <&clk IMX8MM_CLK_SDMA2_ROOT>;
289 clock-names = "ipg", "ahb";
290 #dma-cells = <3>;
291 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
292 };
293
294 sdma3: dma-controller@302b0000 {
295 compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma";
296 reg = <0x302b0000 0x10000>;
297 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
298 clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>,
299 <&clk IMX8MM_CLK_SDMA3_ROOT>;
300 clock-names = "ipg", "ahb";
301 #dma-cells = <3>;
302 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
303 };
304
305 iomuxc: pinctrl@30330000 {
306 compatible = "fsl,imx8mm-iomuxc";
307 reg = <0x30330000 0x10000>;
308 };
309
310 gpr: iomuxc-gpr@30340000 {
311 compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
312 reg = <0x30340000 0x10000>;
313 };
314
315 ocotp: ocotp-ctrl@30350000 {
316 compatible = "fsl,imx8mm-ocotp", "fsl,imx7d-ocotp", "syscon";
317 reg = <0x30350000 0x10000>;
318 clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>;
319 /* For nvmem subnodes */
320 #address-cells = <1>;
321 #size-cells = <1>;
322 };
323
324 anatop: anatop@30360000 {
325 compatible = "fsl,imx8mm-anatop", "syscon", "simple-bus";
326 reg = <0x30360000 0x10000>;
327 };
328
329 snvs: snvs@30370000 {
330 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
331 reg = <0x30370000 0x10000>;
332
333 snvs_rtc: snvs-rtc-lp {
334 compatible = "fsl,sec-v4.0-mon-rtc-lp";
335 regmap = <&snvs>;
336 offset = <0x34>;
337 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
338 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
339 };
340
341 snvs_pwrkey: snvs-powerkey {
342 compatible = "fsl,sec-v4.0-pwrkey";
343 regmap = <&snvs>;
344 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
345 linux,keycode = <KEY_POWER>;
346 wakeup-source;
347 };
348 };
349
350 clk: clock-controller@30380000 {
351 compatible = "fsl,imx8mm-ccm";
352 reg = <0x30380000 0x10000>;
353 #clock-cells = <1>;
354 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
355 <&clk_ext3>, <&clk_ext4>;
356 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
357 "clk_ext3", "clk_ext4";
358 };
359
360 src: reset-controller@30390000 {
361 compatible = "fsl,imx8mm-src", "syscon";
362 reg = <0x30390000 0x10000>;
363 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
364 #reset-cells = <1>;
365 };
366 };
367
368 aips2: bus@30400000 {
369 compatible = "fsl,aips-bus", "simple-bus";
370 #address-cells = <1>;
371 #size-cells = <1>;
372 ranges;
373
374 pwm1: pwm@30660000 {
375 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
376 reg = <0x30660000 0x10000>;
377 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&clk IMX8MM_CLK_PWM1_ROOT>,
379 <&clk IMX8MM_CLK_PWM1_ROOT>;
380 clock-names = "ipg", "per";
381 #pwm-cells = <2>;
382 status = "disabled";
383 };
384
385 pwm2: pwm@30670000 {
386 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
387 reg = <0x30670000 0x10000>;
388 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
389 clocks = <&clk IMX8MM_CLK_PWM2_ROOT>,
390 <&clk IMX8MM_CLK_PWM2_ROOT>;
391 clock-names = "ipg", "per";
392 #pwm-cells = <2>;
393 status = "disabled";
394 };
395
396 pwm3: pwm@30680000 {
397 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
398 reg = <0x30680000 0x10000>;
399 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
400 clocks = <&clk IMX8MM_CLK_PWM3_ROOT>,
401 <&clk IMX8MM_CLK_PWM3_ROOT>;
402 clock-names = "ipg", "per";
403 #pwm-cells = <2>;
404 status = "disabled";
405 };
406
407 pwm4: pwm@30690000 {
408 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
409 reg = <0x30690000 0x10000>;
410 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
411 clocks = <&clk IMX8MM_CLK_PWM4_ROOT>,
412 <&clk IMX8MM_CLK_PWM4_ROOT>;
413 clock-names = "ipg", "per";
414 #pwm-cells = <2>;
415 status = "disabled";
416 };
417 };
418
419 aips3: bus@30800000 {
420 compatible = "fsl,aips-bus", "simple-bus";
421 #address-cells = <1>;
422 #size-cells = <1>;
423 ranges;
424
425 ecspi1: spi@30820000 {
426 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
427 #address-cells = <1>;
428 #size-cells = <0>;
429 reg = <0x30820000 0x10000>;
430 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>,
432 <&clk IMX8MM_CLK_ECSPI1_ROOT>;
433 clock-names = "ipg", "per";
434 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
435 dma-names = "rx", "tx";
436 status = "disabled";
437 };
438
439 ecspi2: spi@30830000 {
440 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
441 #address-cells = <1>;
442 #size-cells = <0>;
443 reg = <0x30830000 0x10000>;
444 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>,
446 <&clk IMX8MM_CLK_ECSPI2_ROOT>;
447 clock-names = "ipg", "per";
448 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
449 dma-names = "rx", "tx";
450 status = "disabled";
451 };
452
453 ecspi3: spi@30840000 {
454 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
455 #address-cells = <1>;
456 #size-cells = <0>;
457 reg = <0x30840000 0x10000>;
458 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
459 clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>,
460 <&clk IMX8MM_CLK_ECSPI3_ROOT>;
461 clock-names = "ipg", "per";
462 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
463 dma-names = "rx", "tx";
464 status = "disabled";
465 };
466
467 uart1: serial@30860000 {
468 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
469 reg = <0x30860000 0x10000>;
470 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
471 clocks = <&clk IMX8MM_CLK_UART1_ROOT>,
472 <&clk IMX8MM_CLK_UART1_ROOT>;
473 clock-names = "ipg", "per";
474 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
475 dma-names = "rx", "tx";
476 status = "disabled";
477 };
478
479 uart3: serial@30880000 {
480 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
481 reg = <0x30880000 0x10000>;
482 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
483 clocks = <&clk IMX8MM_CLK_UART3_ROOT>,
484 <&clk IMX8MM_CLK_UART3_ROOT>;
485 clock-names = "ipg", "per";
486 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
487 dma-names = "rx", "tx";
488 status = "disabled";
489 };
490
491 uart2: serial@30890000 {
492 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
493 reg = <0x30890000 0x10000>;
494 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
495 clocks = <&clk IMX8MM_CLK_UART2_ROOT>,
496 <&clk IMX8MM_CLK_UART2_ROOT>;
497 clock-names = "ipg", "per";
498 status = "disabled";
499 };
500
501 i2c1: i2c@30a20000 {
502 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
503 #address-cells = <1>;
504 #size-cells = <0>;
505 reg = <0x30a20000 0x10000>;
506 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
507 clocks = <&clk IMX8MM_CLK_I2C1_ROOT>;
508 status = "disabled";
509 };
510
511 i2c2: i2c@30a30000 {
512 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
513 #address-cells = <1>;
514 #size-cells = <0>;
515 reg = <0x30a30000 0x10000>;
516 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&clk IMX8MM_CLK_I2C2_ROOT>;
518 status = "disabled";
519 };
520
521 i2c3: i2c@30a40000 {
522 #address-cells = <1>;
523 #size-cells = <0>;
524 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
525 reg = <0x30a40000 0x10000>;
526 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
527 clocks = <&clk IMX8MM_CLK_I2C3_ROOT>;
528 status = "disabled";
529 };
530
531 i2c4: i2c@30a50000 {
532 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
533 #address-cells = <1>;
534 #size-cells = <0>;
535 reg = <0x30a50000 0x10000>;
536 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
537 clocks = <&clk IMX8MM_CLK_I2C4_ROOT>;
538 status = "disabled";
539 };
540
541 uart4: serial@30a60000 {
542 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
543 reg = <0x30a60000 0x10000>;
544 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&clk IMX8MM_CLK_UART4_ROOT>,
546 <&clk IMX8MM_CLK_UART4_ROOT>;
547 clock-names = "ipg", "per";
548 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
549 dma-names = "rx", "tx";
550 status = "disabled";
551 };
552
553 usdhc1: mmc@30b40000 {
554 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
555 reg = <0x30b40000 0x10000>;
556 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
557 clocks = <&clk IMX8MM_CLK_DUMMY>,
558 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
559 <&clk IMX8MM_CLK_USDHC1_ROOT>;
560 clock-names = "ipg", "ahb", "per";
561 assigned-clocks = <&clk IMX8MM_CLK_USDHC1>;
562 assigned-clock-rates = <400000000>;
563 fsl,tuning-start-tap = <20>;
564 fsl,tuning-step= <2>;
565 bus-width = <4>;
566 status = "disabled";
567 };
568
569 usdhc2: mmc@30b50000 {
570 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
571 reg = <0x30b50000 0x10000>;
572 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
573 clocks = <&clk IMX8MM_CLK_DUMMY>,
574 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
575 <&clk IMX8MM_CLK_USDHC2_ROOT>;
576 clock-names = "ipg", "ahb", "per";
577 fsl,tuning-start-tap = <20>;
578 fsl,tuning-step= <2>;
579 bus-width = <4>;
580 status = "disabled";
581 };
582
583 usdhc3: mmc@30b60000 {
584 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
585 reg = <0x30b60000 0x10000>;
586 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
587 clocks = <&clk IMX8MM_CLK_DUMMY>,
588 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
589 <&clk IMX8MM_CLK_USDHC3_ROOT>;
590 clock-names = "ipg", "ahb", "per";
591 assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
592 assigned-clock-rates = <400000000>;
593 fsl,tuning-start-tap = <20>;
594 fsl,tuning-step= <2>;
595 bus-width = <4>;
596 status = "disabled";
597 };
598
599 sdma1: dma-controller@30bd0000 {
600 compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma";
601 reg = <0x30bd0000 0x10000>;
602 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>,
604 <&clk IMX8MM_CLK_SDMA1_ROOT>;
605 clock-names = "ipg", "ahb";
606 #dma-cells = <3>;
607 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
608 };
609
610 fec1: ethernet@30be0000 {
611 compatible = "fsl,imx8mm-fec", "fsl,imx6sx-fec";
612 reg = <0x30be0000 0x10000>;
613 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
614 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
615 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
616 clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,
617 <&clk IMX8MM_CLK_ENET1_ROOT>,
618 <&clk IMX8MM_CLK_ENET_TIMER>,
619 <&clk IMX8MM_CLK_ENET_REF>,
620 <&clk IMX8MM_CLK_ENET_PHY_REF>;
621 clock-names = "ipg", "ahb", "ptp",
622 "enet_clk_ref", "enet_out";
623 assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
624 <&clk IMX8MM_CLK_ENET_TIMER>,
625 <&clk IMX8MM_CLK_ENET_REF>,
626 <&clk IMX8MM_CLK_ENET_TIMER>;
627 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
628 <&clk IMX8MM_SYS_PLL2_100M>,
629 <&clk IMX8MM_SYS_PLL2_125M>;
630 assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
631 fsl,num-tx-queues = <3>;
632 fsl,num-rx-queues = <3>;
633 status = "disabled";
634 };
635
636 };
637
638 aips4: bus@32c00000 {
639 compatible = "fsl,aips-bus", "simple-bus";
640 #address-cells = <1>;
641 #size-cells = <1>;
642 ranges;
643
644 usbotg1: usb@32e40000 {
645 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
646 reg = <0x32e40000 0x200>;
647 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
648 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
649 clock-names = "usb1_ctrl_root_clk";
650 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>,
651 <&clk IMX8MM_CLK_USB_CORE_REF>;
652 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>,
653 <&clk IMX8MM_SYS_PLL1_100M>;
654 fsl,usbphy = <&usbphynop1>;
655 fsl,usbmisc = <&usbmisc1 0>;
656 status = "disabled";
657 };
658
659 usbphynop1: usbphynop1 {
660 compatible = "usb-nop-xceiv";
661 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
662 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
663 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
664 clock-names = "main_clk";
665 };
666
667 usbmisc1: usbmisc@32e40200 {
668 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
669 #index-cells = <1>;
670 reg = <0x32e40200 0x200>;
671 };
672
673 usbotg2: usb@32e50000 {
674 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
675 reg = <0x32e50000 0x200>;
676 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
677 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
678 clock-names = "usb1_ctrl_root_clk";
679 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>,
680 <&clk IMX8MM_CLK_USB_CORE_REF>;
681 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>,
682 <&clk IMX8MM_SYS_PLL1_100M>;
683 fsl,usbphy = <&usbphynop2>;
684 fsl,usbmisc = <&usbmisc2 0>;
685 status = "disabled";
686 };
687
688 usbphynop2: usbphynop2 {
689 compatible = "usb-nop-xceiv";
690 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
691 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
692 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
693 clock-names = "main_clk";
694 };
695
696 usbmisc2: usbmisc@32e50200 {
697 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
698 #index-cells = <1>;
699 reg = <0x32e50200 0x200>;
700 };
701
702 };
703
704 dma_apbh: dma-controller@33000000 {
705 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
706 reg = <0x33000000 0x2000>;
707 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
708 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
709 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
710 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
711 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
712 #dma-cells = <1>;
713 dma-channels = <4>;
714 clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
715 };
716
717 gpmi: nand-controller@33002000{
718 compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
719 #address-cells = <1>;
720 #size-cells = <1>;
721 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
722 reg-names = "gpmi-nand", "bch";
723 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
724 interrupt-names = "bch";
725 clocks = <&clk IMX8MM_CLK_NAND_ROOT>,
726 <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
727 clock-names = "gpmi_io", "gpmi_bch_apb";
728 dmas = <&dma_apbh 0>;
729 dma-names = "rx-tx";
730 status = "disabled";
731 };
732 };
733};
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index 54737bf1772f..b2038be8bbd7 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -21,6 +21,12 @@
21 reg = <0x00000000 0x40000000 0 0xc0000000>; 21 reg = <0x00000000 0x40000000 0 0xc0000000>;
22 }; 22 };
23 23
24 pcie0_refclk: pcie0-refclk {
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
27 clock-frequency = <100000000>;
28 };
29
24 reg_usdhc2_vmmc: regulator-vsd-3v3 { 30 reg_usdhc2_vmmc: regulator-vsd-3v3 {
25 pinctrl-names = "default"; 31 pinctrl-names = "default";
26 pinctrl-0 = <&pinctrl_reg_usdhc2>; 32 pinctrl-0 = <&pinctrl_reg_usdhc2>;
@@ -31,6 +37,63 @@
31 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 37 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
32 enable-active-high; 38 enable-active-high;
33 }; 39 };
40
41 buck2_reg: regulator-buck2 {
42 pinctrl-names = "default";
43 pinctrl-0 = <&pinctrl_buck2>;
44 compatible = "regulator-gpio";
45 regulator-name = "vdd_arm";
46 regulator-min-microvolt = <900000>;
47 regulator-max-microvolt = <1000000>;
48 gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
49 states = <1000000 0x0
50 900000 0x1>;
51 };
52
53 wm8524: audio-codec {
54 #sound-dai-cells = <0>;
55 compatible = "wlf,wm8524";
56 wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
57 };
58
59 sound-wm8524 {
60 compatible = "simple-audio-card";
61 simple-audio-card,name = "wm8524-audio";
62 simple-audio-card,format = "i2s";
63 simple-audio-card,frame-master = <&cpudai>;
64 simple-audio-card,bitclock-master = <&cpudai>;
65 simple-audio-card,widgets =
66 "Line", "Left Line Out Jack",
67 "Line", "Right Line Out Jack";
68 simple-audio-card,routing =
69 "Left Line Out Jack", "LINEVOUTL",
70 "Right Line Out Jack", "LINEVOUTR";
71
72 cpudai: simple-audio-card,cpu {
73 sound-dai = <&sai2>;
74 };
75
76 link_codec: simple-audio-card,codec {
77 sound-dai = <&wm8524>;
78 clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
79 };
80 };
81};
82
83&A53_0 {
84 cpu-supply = <&buck2_reg>;
85};
86
87&A53_1 {
88 cpu-supply = <&buck2_reg>;
89};
90
91&A53_2 {
92 cpu-supply = <&buck2_reg>;
93};
94
95&A53_3 {
96 cpu-supply = <&buck2_reg>;
34}; 97};
35 98
36&fec1 { 99&fec1 {
@@ -52,6 +115,26 @@
52 }; 115 };
53}; 116};
54 117
118&sai2 {
119 pinctrl-names = "default";
120 pinctrl-0 = <&pinctrl_sai2>;
121 assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
122 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
123 assigned-clock-rates = <24576000>;
124 status = "okay";
125};
126
127&gpio5 {
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_wifi_reset>;
130
131 wl-reg-on {
132 gpio-hog;
133 gpios = <29 GPIO_ACTIVE_HIGH>;
134 output-high;
135 };
136};
137
55&i2c1 { 138&i2c1 {
56 clock-frequency = <100000>; 139 clock-frequency = <100000>;
57 pinctrl-names = "default"; 140 pinctrl-names = "default";
@@ -143,6 +226,22 @@
143 }; 226 };
144}; 227};
145 228
229&pcie0 {
230 pinctrl-names = "default";
231 pinctrl-0 = <&pinctrl_pcie0>;
232 reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
233 clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
234 <&clk IMX8MQ_CLK_PCIE1_AUX>,
235 <&clk IMX8MQ_CLK_PCIE1_PHY>,
236 <&pcie0_refclk>;
237 clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
238 status = "okay";
239};
240
241&pgc_gpu {
242 power-supply = <&sw1a_reg>;
243};
244
146&uart1 { 245&uart1 {
147 pinctrl-names = "default"; 246 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_uart1>; 247 pinctrl-0 = <&pinctrl_uart1>;
@@ -203,6 +302,13 @@
203}; 302};
204 303
205&iomuxc { 304&iomuxc {
305 pinctrl_buck2: vddarmgrp {
306 fsl,pins = <
307 MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
308 >;
309
310 };
311
206 pinctrl_fec1: fec1grp { 312 pinctrl_fec1: fec1grp {
207 fsl,pins = < 313 fsl,pins = <
208 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 314 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
@@ -230,6 +336,13 @@
230 >; 336 >;
231 }; 337 };
232 338
339 pinctrl_pcie0: pcie0grp {
340 fsl,pins = <
341 MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76
342 MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16
343 >;
344 };
345
233 pinctrl_qspi: qspigrp { 346 pinctrl_qspi: qspigrp {
234 fsl,pins = < 347 fsl,pins = <
235 MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 348 MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
@@ -248,6 +361,16 @@
248 >; 361 >;
249 }; 362 };
250 363
364 pinctrl_sai2: sai2grp {
365 fsl,pins = <
366 MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
367 MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
368 MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
369 MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
370 MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6
371 >;
372 };
373
251 pinctrl_uart1: uart1grp { 374 pinctrl_uart1: uart1grp {
252 fsl,pins = < 375 fsl,pins = <
253 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 376 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
@@ -347,4 +470,10 @@
347 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 470 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
348 >; 471 >;
349 }; 472 };
473
474 pinctrl_wifi_reset: wifiresetgrp {
475 fsl,pins = <
476 MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16
477 >;
478 };
350}; 479};
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts
new file mode 100644
index 000000000000..d2a6da479980
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-rmb3.dts
@@ -0,0 +1,95 @@
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2019 Zodiac Inflight Innovations
4 */
5
6/dts-v1/;
7
8#include "imx8mq-zii-ultra.dtsi"
9
10/ {
11 model = "ZII i.MX8MQ Ultra RMB3 Board";
12 compatible = "zii,imx8mq-ultra-rmb3", "zii,imx8mq-ultra", "fsl,imx8mq";
13};
14
15&ecspi1 {
16 pinctrl-names = "default";
17 pinctrl-0 = <&pinctrl_ecspi1>;
18 cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
19 status = "okay";
20 #address-cells = <1>;
21 #size-cells = <0>;
22
23 nor_flash: flash@0 {
24 compatible = "st,n25q128a13", "jedec,spi-nor";
25 spi-max-frequency = <20000000>;
26 reg = <0>;
27 };
28};
29
30&i2c2 {
31 temp-sense@48 {
32 compatible = "national,lm75";
33 reg = <0x48>;
34 };
35};
36
37&i2c4 {
38 touchscreen@20 {
39 compatible = "syna,rmi4-i2c";
40 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_ts>;
42 reg = <0x20>;
43 interrupt-parent = <&gpio1>;
44 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
45
46 #address-cells = <1>;
47 #size-cells = <0>;
48
49 rmi4-f01@1 {
50 reg = <0x1>;
51 syna,nosleep-mode = <2>;
52 };
53
54 rmi4-f11@11 {
55 reg = <0x11>;
56 touchscreen-inverted-x;
57 touchscreen-swapped-x-y;
58 syna,sensor-type = <1>;
59 };
60
61 rmi4-f12@12 {
62 reg = <0x12>;
63 touchscreen-inverted-x;
64 touchscreen-swapped-x-y;
65 syna,sensor-type = <1>;
66 };
67 };
68
69 touchscreen@2a {
70 compatible = "eeti,exc3000";
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_ts>;
73 reg = <0x2a>;
74 interrupt-parent = <&gpio1>;
75 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
76 touchscreen-inverted-x;
77 touchscreen-swapped-x-y;
78 status = "disabled";
79 };
80};
81
82&usbhub {
83 swap-dx-lanes = <0>;
84};
85
86&iomuxc {
87 pinctrl_ecspi1: ecspi1grp {
88 fsl,pins = <
89 MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19
90 MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
91 MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
92 MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
93 >;
94 };
95};
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-zest.dts b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-zest.dts
new file mode 100644
index 000000000000..1084d9330403
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra-zest.dts
@@ -0,0 +1,24 @@
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2019 Zodiac Inflight Innovations
4 */
5
6/dts-v1/;
7
8#include "imx8mq-zii-ultra.dtsi"
9
10/ {
11 model = "ZII i.MX8MQ Ultra Zest Board";
12 compatible = "zii,imx8mq-ultra-zest", "zii,imx8mq-ultra", "fsl,imx8mq";
13};
14
15&i2c4 {
16 touchscreen@4a {
17 compatible = "atmel,maxtouch";
18 pinctrl-names = "default";
19 pinctrl-0 = <&pinctrl_ts>;
20 reg = <0x4a>;
21 interrupt-parent = <&gpio1>;
22 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
23 };
24};
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi
new file mode 100644
index 000000000000..7a1706f969f0
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi
@@ -0,0 +1,725 @@
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2019 Zodiac Inflight Innovations
4 */
5
6#include "imx8mq.dtsi"
7
8/ {
9 aliases {
10 mdio-gpio0 = &mdio0;
11 rtc0 = &ds1341;
12 };
13
14 chosen {
15 stdout-path = &uart1;
16 };
17
18 mdio0: bitbang-mdio {
19 compatible = "virtual,mdio-gpio";
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_mdio_bitbang>, <&pinctrl_fec1_phy_reset>;
22 gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>, /* MDC */
23 <&gpio1 14 GPIO_ACTIVE_HIGH>; /* MDIO */
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 phy0: ethernet-phy@0 {
28 reg = <0>;
29 reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
30 };
31 };
32
33 pcie0_refclk: clock-pcie0-refclk {
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <100000000>;
37 };
38
39 pcie1_refclk: clock-pcie1-refclk {
40 compatible = "fixed-clock";
41 #clock-cells = <0>;
42 clock-frequency = <100000000>;
43 };
44
45 reg_12p0_main: regulator-12p0-main {
46 compatible = "regulator-fixed";
47 regulator-name = "12V_MAIN";
48 regulator-min-microvolt = <5000000>;
49 regulator-max-microvolt = <5000000>;
50 regulator-always-on;
51 };
52
53 reg_5p0_main: regulator-5p0-main {
54 compatible = "regulator-fixed";
55 vin-supply = <&reg_12p0_main>;
56 regulator-name = "5V_MAIN";
57 regulator-min-microvolt = <5000000>;
58 regulator-max-microvolt = <5000000>;
59 regulator-always-on;
60 };
61
62 reg_3p3_main: regulator-3p3-main {
63 compatible = "regulator-fixed";
64 vin-supply = <&reg_12p0_main>;
65 regulator-name = "3V3V_MAIN";
66 regulator-min-microvolt = <3300000>;
67 regulator-max-microvolt = <3300000>;
68 regulator-always-on;
69 };
70
71 reg_5p0_user_usb: regulator-5p0-user-usb {
72 compatible = "regulator-fixed";
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_reg_user_usb>;
75 vin-supply = <&reg_5p0_main>;
76 regulator-name = "5V_USER_USB";
77 regulator-min-microvolt = <5000000>;
78 regulator-max-microvolt = <5000000>;
79 gpio = <&gpio3 12 GPIO_ACTIVE_LOW>;
80 startup-delay-us = <1000>;
81 };
82
83 reg_usdhc2_vmmc: regulator-vsd-3v3 {
84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_reg_usdhc2>;
86 compatible = "regulator-fixed";
87 vin-supply = <&reg_3p3_main>;
88 regulator-name = "3V3_SD";
89 regulator-min-microvolt = <3300000>;
90 regulator-max-microvolt = <3300000>;
91 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
92 enable-active-high;
93 };
94
95 reg_arm: regulator-arm {
96 pinctrl-names = "default";
97 pinctrl-0 = <&pinctrl_reg_arm>;
98 compatible = "regulator-gpio";
99 vin-supply = <&reg_12p0_main>;
100 regulator-name = "0V9_ARM";
101 regulator-min-microvolt = <900000>;
102 regulator-max-microvolt = <1000000>;
103 gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
104 states = <1000000 0x0
105 900000 0x1>;
106 regulator-always-on;
107 };
108};
109
110&A53_0 {
111 cpu-supply = <&reg_arm>;
112};
113
114&A53_1 {
115 cpu-supply = <&reg_arm>;
116};
117
118&A53_2 {
119 cpu-supply = <&reg_arm>;
120};
121
122&A53_3 {
123 cpu-supply = <&reg_arm>;
124};
125
126&fec1 {
127 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_fec1>;
129
130 phy-handle = <&phy0>;
131 phy-mode = "rmii";
132 status = "okay";
133
134 mdio {
135 #address-cells = <1>;
136 #size-cells = <0>;
137 status = "okay";
138
139 switch: switch@0 {
140 compatible = "marvell,mv88e6085";
141 pinctrl-0 = <&pinctrl_switch_irq>;
142 pinctrl-names = "default";
143 reg = <0>;
144 dsa,member = <0 0>;
145 eeprom-length = <512>;
146 interrupt-parent = <&gpio1>;
147 interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
148 interrupt-controller;
149 #interrupt-cells = <2>;
150
151 ports {
152 #address-cells = <1>;
153 #size-cells = <0>;
154
155 port@0 {
156 reg = <0>;
157 label = "gigabit_proc";
158 phy-handle = <&switchphy0>;
159 };
160
161 port@1 {
162 reg = <1>;
163 label = "netaux";
164 phy-handle = <&switchphy1>;
165 };
166
167 port@2 {
168 reg = <2>;
169 label = "cpu";
170 ethernet = <&fec1>;
171
172 fixed-link {
173 speed = <100>;
174 full-duplex;
175 };
176 };
177
178 port@3 {
179 reg = <3>;
180 label = "netright";
181 phy-handle = <&switchphy3>;
182 };
183
184 port@4 {
185 reg = <4>;
186 label = "netleft";
187 phy-handle = <&switchphy4>;
188 };
189 };
190
191 mdio {
192 #address-cells = <1>;
193 #size-cells = <0>;
194
195 switchphy0: switchphy@0 {
196 reg = <0>;
197 interrupt-parent = <&switch>;
198 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
199 };
200
201 switchphy1: switchphy@1 {
202 reg = <1>;
203 interrupt-parent = <&switch>;
204 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
205 };
206
207 switchphy2: switchphy@2 {
208 reg = <2>;
209 interrupt-parent = <&switch>;
210 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
211 };
212
213 switchphy3: switchphy@3 {
214 reg = <3>;
215 interrupt-parent = <&switch>;
216 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
217 };
218
219 switchphy4: switchphy@4 {
220 reg = <4>;
221 interrupt-parent = <&switch>;
222 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
223 };
224 };
225 };
226 };
227};
228
229&gpio3 {
230 pinctrl-names = "default";
231 pinctrl-0 = <&pinctrl_gpio3_hog>;
232
233 usb-emulation {
234 gpio-hog;
235 gpios = <10 GPIO_ACTIVE_HIGH>;
236 output-low;
237 line-name = "usb-emulation";
238 };
239
240 usb-mode1 {
241 gpio-hog;
242 gpios = <11 GPIO_ACTIVE_HIGH>;
243 output-high;
244 line-name = "usb-mode1";
245 };
246
247 usb-mode2 {
248 gpio-hog;
249 gpios = <13 GPIO_ACTIVE_HIGH>;
250 output-high;
251 line-name = "usb-mode2";
252 };
253};
254
255&i2c1 {
256 clock-frequency = <400000>;
257 pinctrl-names = "default";
258 pinctrl-0 = <&pinctrl_i2c1>;
259 status = "okay";
260};
261
262&i2c2 {
263 clock-frequency = <400000>;
264 pinctrl-names = "default";
265 pinctrl-0 = <&pinctrl_i2c2>;
266 status = "okay";
267
268 pmic@8 {
269 compatible = "fsl,pfuze100";
270 reg = <0x8>;
271
272 regulators {
273 sw1a_reg: sw1ab {
274 regulator-min-microvolt = <825000>;
275 regulator-max-microvolt = <1100000>;
276 };
277
278 sw1c_reg: sw1c {
279 regulator-min-microvolt = <825000>;
280 regulator-max-microvolt = <1100000>;
281 };
282
283 sw2_reg: sw2 {
284 regulator-min-microvolt = <1100000>;
285 regulator-max-microvolt = <1100000>;
286 regulator-always-on;
287 };
288
289 sw3a_reg: sw3ab {
290 regulator-min-microvolt = <825000>;
291 regulator-max-microvolt = <1100000>;
292 regulator-always-on;
293 };
294
295 sw4_reg: sw4 {
296 regulator-min-microvolt = <1800000>;
297 regulator-max-microvolt = <1800000>;
298 regulator-always-on;
299 };
300
301 swbst_reg: swbst {
302 regulator-min-microvolt = <5000000>;
303 regulator-max-microvolt = <5150000>;
304 };
305
306 snvs_reg: vsnvs {
307 regulator-min-microvolt = <1000000>;
308 regulator-max-microvolt = <3000000>;
309 regulator-always-on;
310 };
311
312 vref_reg: vrefddr {
313 regulator-always-on;
314 };
315
316 vgen1_reg: vgen1 {
317 regulator-min-microvolt = <800000>;
318 regulator-max-microvolt = <1550000>;
319 };
320
321 vgen2_reg: vgen2 {
322 regulator-min-microvolt = <850000>;
323 regulator-max-microvolt = <975000>;
324 regulator-always-on;
325 };
326
327 vgen3_reg: vgen3 {
328 regulator-min-microvolt = <1675000>;
329 regulator-max-microvolt = <1975000>;
330 regulator-always-on;
331 };
332
333 vgen4_reg: vgen4 {
334 regulator-min-microvolt = <1625000>;
335 regulator-max-microvolt = <1875000>;
336 regulator-always-on;
337 };
338
339 vgen5_reg: vgen5 {
340 regulator-min-microvolt = <3075000>;
341 regulator-max-microvolt = <3625000>;
342 regulator-always-on;
343 };
344
345 vgen6_reg: vgen6 {
346 regulator-min-microvolt = <1800000>;
347 regulator-max-microvolt = <3300000>;
348 };
349 };
350 };
351
352 eeprom@54 {
353 compatible = "atmel,24c128";
354 reg = <0x54>;
355 };
356
357 ds1341: rtc@68 {
358 compatible = "dallas,ds1341";
359 reg = <0x68>;
360 };
361};
362
363&i2c3 {
364 clock-frequency = <100000>;
365 pinctrl-names = "default";
366 pinctrl-0 = <&pinctrl_i2c3>;
367 status = "okay";
368
369 usbhub: usbhub@2c {
370 compatible ="microchip,usb2513b";
371 pinctrl-names = "default";
372 pinctrl-0 = <&pinctrl_usbhub>;
373 reg = <0x2c>;
374 reset-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
375 };
376};
377
378&i2c4 {
379 clock-frequency = <400000>;
380 pinctrl-names = "default";
381 pinctrl-0 = <&pinctrl_i2c4>;
382 status = "okay";
383};
384
385&uart1 {
386 pinctrl-names = "default";
387 pinctrl-0 = <&pinctrl_uart1>;
388 status = "okay";
389};
390
391&uart2 {
392 pinctrl-names = "default";
393 pinctrl-0 = <&pinctrl_uart2>;
394 status = "okay";
395
396 rave-sp {
397 compatible = "zii,rave-sp-rdu2";
398 current-speed = <1000000>;
399 #address-cells = <1>;
400 #size-cells = <1>;
401
402 watchdog {
403 compatible = "zii,rave-sp-watchdog";
404 };
405
406 backlight {
407 compatible = "zii,rave-sp-backlight";
408 };
409
410 pwrbutton {
411 compatible = "zii,rave-sp-pwrbutton";
412 };
413
414 eeprom@a3 {
415 compatible = "zii,rave-sp-eeprom";
416 reg = <0xa3 0x4000>;
417 zii,eeprom-name = "dds-eeprom";
418 };
419
420 eeprom@a4 {
421 compatible = "zii,rave-sp-eeprom";
422 reg = <0xa4 0x4000>;
423 #address-cells = <1>;
424 #size-cells = <1>;
425 zii,eeprom-name = "main-eeprom";
426 };
427 };
428};
429
430&usb3_phy0 {
431 vbus-supply = <&reg_5p0_user_usb>;
432 status = "okay";
433};
434
435&usb_dwc3_0 {
436 dr_mode = "host";
437 status = "okay";
438};
439
440&usb3_phy1 {
441 vbus-supply = <&reg_5p0_main>;
442 status = "okay";
443};
444
445&usb_dwc3_1 {
446 dr_mode = "host";
447 status = "okay";
448};
449
450&pcie0 {
451 pinctrl-names = "default";
452 pinctrl-0 = <&pinctrl_pcie0>;
453 reset-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
454 clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
455 <&clk IMX8MQ_CLK_PCIE1_AUX>,
456 <&clk IMX8MQ_CLK_PCIE1_PHY>,
457 <&pcie0_refclk>;
458 clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
459 status = "okay";
460};
461
462&pcie1 {
463 pinctrl-names = "default";
464 pinctrl-0 = <&pinctrl_pcie1>;
465 reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
466 clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
467 <&clk IMX8MQ_CLK_PCIE2_AUX>,
468 <&clk IMX8MQ_CLK_PCIE2_PHY>,
469 <&pcie1_refclk>;
470 clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
471 status = "okay";
472};
473
474&pgc_gpu {
475 power-supply = <&sw1a_reg>;
476};
477
478&pgc_vpu {
479 power-supply = <&sw1c_reg>;
480};
481
482&usdhc1 {
483 pinctrl-names = "default", "state_100mhz", "state_200mhz";
484 pinctrl-0 = <&pinctrl_usdhc1>;
485 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
486 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
487 vqmmc-supply = <&sw4_reg>;
488 bus-width = <8>;
489 non-removable;
490 no-sd;
491 no-sdio;
492 status = "okay";
493};
494
495&usdhc2 {
496 pinctrl-names = "default", "state_100mhz", "state_200mhz";
497 pinctrl-0 = <&pinctrl_usdhc2>;
498 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
499 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
500 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
501 vmmc-supply = <&reg_usdhc2_vmmc>;
502 status = "okay";
503};
504
505&snvs_rtc {
506 status = "disabled";
507};
508
509&iomuxc {
510 pinctrl_fec1: fec1grp {
511 fsl,pins = <
512 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
513 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
514 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
515 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
516 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
517 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
518 MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x1f
519 MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x91
520 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
521 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
522 >;
523 };
524
525 pinctrl_fec1_phy_reset: fec1phyresetgrp {
526 fsl,pins = <
527 MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29 0x11
528 >;
529 };
530
531 pinctrl_gpio3_hog: gpio3hoggrp {
532 fsl,pins = <
533 MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x6
534 MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x6
535 MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x6
536 >;
537 };
538
539 pinctrl_i2c1: i2c1grp {
540 fsl,pins = <
541 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
542 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
543 >;
544 };
545
546 pinctrl_i2c2: i2c2grp {
547 fsl,pins = <
548 MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
549 MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
550 >;
551 };
552
553 pinctrl_i2c3: i2c3grp {
554 fsl,pins = <
555 MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
556 MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
557 >;
558 };
559
560 pinctrl_i2c4: i2c4grp {
561 fsl,pins = <
562 MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f
563 MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f
564 >;
565 };
566
567 pinctrl_mdio_bitbang: bitbangmdiogrp {
568 fsl,pins = <
569 MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x44
570 MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x64
571 >;
572 };
573
574 pinctrl_pcie0: pcie0grp {
575 fsl,pins = <
576 MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x66
577 MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x6
578 >;
579 };
580
581 pinctrl_pcie1: pcie1grp {
582 fsl,pins = <
583 MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x66
584 MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x6
585 >;
586 };
587
588 pinctrl_reg_arm: regarmgrp {
589 fsl,pins = <
590 MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
591 >;
592 };
593
594 pinctrl_reg_usdhc2: regusdhc2grp {
595 fsl,pins = <
596 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
597 >;
598 };
599
600 pinctrl_reg_user_usb: reguserusbgrp {
601 fsl,pins = <
602 MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x6
603 >;
604 };
605
606 pinctrl_switch_irq: switchgrp {
607 fsl,pins = <
608 MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
609 >;
610 };
611
612 pinctrl_ts: tsgrp {
613 fsl,pins = <
614 MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x96
615 MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x96
616 >;
617 };
618
619 pinctrl_uart1: uart1grp {
620 fsl,pins = <
621 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
622 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
623 >;
624 };
625
626 pinctrl_uart2: uart2grp {
627 fsl,pins = <
628 MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
629 MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
630 >;
631 };
632
633 pinctrl_usbhub: usbhubgrp {
634 fsl,pins = <
635 MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x41
636 >;
637 };
638
639 pinctrl_usdhc1: usdhc1grp {
640 fsl,pins = <
641 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
642 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
643 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
644 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
645 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
646 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
647 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
648 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
649 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
650 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
651 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
652 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
653 >;
654 };
655
656 pinctrl_usdhc1_100mhz: usdhc1-100grp {
657 fsl,pins = <
658 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
659 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
660 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
661 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
662 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
663 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
664 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
665 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
666 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
667 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
668 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
669 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
670 >;
671 };
672
673 pinctrl_usdhc1_200mhz: usdhc1-200grp {
674 fsl,pins = <
675 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
676 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
677 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
678 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
679 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
680 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
681 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
682 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
683 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
684 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
685 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
686 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
687 >;
688 };
689
690 pinctrl_usdhc2: usdhc2grp {
691 fsl,pins = <
692 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
693 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
694 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
695 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
696 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
697 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
698 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
699 >;
700 };
701
702 pinctrl_usdhc2_100mhz: usdhc2-100grp {
703 fsl,pins = <
704 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
705 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
706 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
707 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
708 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
709 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
710 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
711 >;
712 };
713
714 pinctrl_usdhc2_200mhz: usdhc2-200grp {
715 fsl,pins = <
716 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
717 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
718 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
719 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
720 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
721 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
722 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
723 >;
724 };
725};
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 9155bd4784eb..6d635ba0904c 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -6,8 +6,10 @@
6 6
7#include <dt-bindings/clock/imx8mq-clock.h> 7#include <dt-bindings/clock/imx8mq-clock.h>
8#include <dt-bindings/power/imx8mq-power.h> 8#include <dt-bindings/power/imx8mq-power.h>
9#include <dt-bindings/reset/imx8mq-reset.h>
9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include <dt-bindings/thermal/thermal.h>
11#include "imx8mq-pinfunc.h" 13#include "imx8mq-pinfunc.h"
12 14
13/ { 15/ {
@@ -87,32 +89,48 @@
87 device_type = "cpu"; 89 device_type = "cpu";
88 compatible = "arm,cortex-a53"; 90 compatible = "arm,cortex-a53";
89 reg = <0x0>; 91 reg = <0x0>;
92 clock-latency = <61036>; /* two CLK32 periods */
93 clocks = <&clk IMX8MQ_CLK_ARM>;
90 enable-method = "psci"; 94 enable-method = "psci";
91 next-level-cache = <&A53_L2>; 95 next-level-cache = <&A53_L2>;
96 operating-points-v2 = <&a53_opp_table>;
97 #cooling-cells = <2>;
92 }; 98 };
93 99
94 A53_1: cpu@1 { 100 A53_1: cpu@1 {
95 device_type = "cpu"; 101 device_type = "cpu";
96 compatible = "arm,cortex-a53"; 102 compatible = "arm,cortex-a53";
97 reg = <0x1>; 103 reg = <0x1>;
104 clock-latency = <61036>; /* two CLK32 periods */
105 clocks = <&clk IMX8MQ_CLK_ARM>;
98 enable-method = "psci"; 106 enable-method = "psci";
99 next-level-cache = <&A53_L2>; 107 next-level-cache = <&A53_L2>;
108 operating-points-v2 = <&a53_opp_table>;
109 #cooling-cells = <2>;
100 }; 110 };
101 111
102 A53_2: cpu@2 { 112 A53_2: cpu@2 {
103 device_type = "cpu"; 113 device_type = "cpu";
104 compatible = "arm,cortex-a53"; 114 compatible = "arm,cortex-a53";
105 reg = <0x2>; 115 reg = <0x2>;
116 clock-latency = <61036>; /* two CLK32 periods */
117 clocks = <&clk IMX8MQ_CLK_ARM>;
106 enable-method = "psci"; 118 enable-method = "psci";
107 next-level-cache = <&A53_L2>; 119 next-level-cache = <&A53_L2>;
120 operating-points-v2 = <&a53_opp_table>;
121 #cooling-cells = <2>;
108 }; 122 };
109 123
110 A53_3: cpu@3 { 124 A53_3: cpu@3 {
111 device_type = "cpu"; 125 device_type = "cpu";
112 compatible = "arm,cortex-a53"; 126 compatible = "arm,cortex-a53";
113 reg = <0x3>; 127 reg = <0x3>;
128 clock-latency = <61036>; /* two CLK32 periods */
129 clocks = <&clk IMX8MQ_CLK_ARM>;
114 enable-method = "psci"; 130 enable-method = "psci";
115 next-level-cache = <&A53_L2>; 131 next-level-cache = <&A53_L2>;
132 operating-points-v2 = <&a53_opp_table>;
133 #cooling-cells = <2>;
116 }; 134 };
117 135
118 A53_L2: l2-cache0 { 136 A53_L2: l2-cache0 {
@@ -120,6 +138,24 @@
120 }; 138 };
121 }; 139 };
122 140
141 a53_opp_table: opp-table {
142 compatible = "operating-points-v2";
143 opp-shared;
144
145 opp-800000000 {
146 opp-hz = /bits/ 64 <800000000>;
147 opp-microvolt = <900000>;
148 clock-latency-ns = <150000>;
149 };
150
151 opp-1300000000 {
152 opp-hz = /bits/ 64 <1300000000>;
153 opp-microvolt = <1000000>;
154 clock-latency-ns = <150000>;
155 opp-suspend;
156 };
157 };
158
123 pmu { 159 pmu {
124 compatible = "arm,cortex-a53-pmu"; 160 compatible = "arm,cortex-a53-pmu";
125 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 161 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
@@ -132,6 +168,67 @@
132 method = "smc"; 168 method = "smc";
133 }; 169 };
134 170
171 thermal-zones {
172 cpu-thermal {
173 polling-delay-passive = <250>;
174 polling-delay = <2000>;
175 thermal-sensors = <&tmu 0>;
176
177 trips {
178 cpu_alert: cpu-alert {
179 temperature = <80000>;
180 hysteresis = <2000>;
181 type = "passive";
182 };
183
184 cpu-crit {
185 temperature = <90000>;
186 hysteresis = <2000>;
187 type = "critical";
188 };
189 };
190
191 cooling-maps {
192 map0 {
193 trip = <&cpu_alert>;
194 cooling-device =
195 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
196 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
197 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
198 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
199 };
200 };
201 };
202
203 gpu-thermal {
204 polling-delay-passive = <250>;
205 polling-delay = <2000>;
206 thermal-sensors = <&tmu 1>;
207
208 trips {
209 gpu-crit {
210 temperature = <90000>;
211 hysteresis = <2000>;
212 type = "critical";
213 };
214 };
215 };
216
217 vpu-thermal {
218 polling-delay-passive = <250>;
219 polling-delay = <2000>;
220 thermal-sensors = <&tmu 2>;
221
222 trips {
223 vpu-crit {
224 temperature = <90000>;
225 hysteresis = <2000>;
226 type = "critical";
227 };
228 };
229 };
230 };
231
135 timer { 232 timer {
136 compatible = "arm,armv8-timer"; 233 compatible = "arm,armv8-timer";
137 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 234 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
@@ -160,6 +257,7 @@
160 reg = <0x30200000 0x10000>; 257 reg = <0x30200000 0x10000>;
161 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 258 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
162 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 259 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
260 clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>;
163 gpio-controller; 261 gpio-controller;
164 #gpio-cells = <2>; 262 #gpio-cells = <2>;
165 interrupt-controller; 263 interrupt-controller;
@@ -171,6 +269,7 @@
171 reg = <0x30210000 0x10000>; 269 reg = <0x30210000 0x10000>;
172 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 270 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 271 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
272 clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>;
174 gpio-controller; 273 gpio-controller;
175 #gpio-cells = <2>; 274 #gpio-cells = <2>;
176 interrupt-controller; 275 interrupt-controller;
@@ -182,6 +281,7 @@
182 reg = <0x30220000 0x10000>; 281 reg = <0x30220000 0x10000>;
183 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 282 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 283 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
284 clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>;
185 gpio-controller; 285 gpio-controller;
186 #gpio-cells = <2>; 286 #gpio-cells = <2>;
187 interrupt-controller; 287 interrupt-controller;
@@ -193,6 +293,7 @@
193 reg = <0x30230000 0x10000>; 293 reg = <0x30230000 0x10000>;
194 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 294 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 295 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
296 clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>;
196 gpio-controller; 297 gpio-controller;
197 #gpio-cells = <2>; 298 #gpio-cells = <2>;
198 interrupt-controller; 299 interrupt-controller;
@@ -204,12 +305,65 @@
204 reg = <0x30240000 0x10000>; 305 reg = <0x30240000 0x10000>;
205 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 306 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 307 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
308 clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>;
207 gpio-controller; 309 gpio-controller;
208 #gpio-cells = <2>; 310 #gpio-cells = <2>;
209 interrupt-controller; 311 interrupt-controller;
210 #interrupt-cells = <2>; 312 #interrupt-cells = <2>;
211 }; 313 };
212 314
315 tmu: tmu@30260000 {
316 compatible = "fsl,imx8mq-tmu";
317 reg = <0x30260000 0x10000>;
318 interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
319 little-endian;
320 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
321 fsl,tmu-calibration = <0x00000000 0x00000023
322 0x00000001 0x00000029
323 0x00000002 0x0000002f
324 0x00000003 0x00000035
325 0x00000004 0x0000003d
326 0x00000005 0x00000043
327 0x00000006 0x0000004b
328 0x00000007 0x00000051
329 0x00000008 0x00000057
330 0x00000009 0x0000005f
331 0x0000000a 0x00000067
332 0x0000000b 0x0000006f
333
334 0x00010000 0x0000001b
335 0x00010001 0x00000023
336 0x00010002 0x0000002b
337 0x00010003 0x00000033
338 0x00010004 0x0000003b
339 0x00010005 0x00000043
340 0x00010006 0x0000004b
341 0x00010007 0x00000055
342 0x00010008 0x0000005d
343 0x00010009 0x00000067
344 0x0001000a 0x00000070
345
346 0x00020000 0x00000017
347 0x00020001 0x00000023
348 0x00020002 0x0000002d
349 0x00020003 0x00000037
350 0x00020004 0x00000041
351 0x00020005 0x0000004b
352 0x00020006 0x00000057
353 0x00020007 0x00000063
354 0x00020008 0x0000006f
355
356 0x00030000 0x00000015
357 0x00030001 0x00000021
358 0x00030002 0x0000002d
359 0x00030003 0x00000039
360 0x00030004 0x00000045
361 0x00030005 0x00000053
362 0x00030006 0x0000005f
363 0x00030007 0x00000071>;
364 #thermal-sensor-cells = <1>;
365 };
366
213 wdog1: watchdog@30280000 { 367 wdog1: watchdog@30280000 {
214 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; 368 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
215 reg = <0x30280000 0x10000>; 369 reg = <0x30280000 0x10000>;
@@ -234,16 +388,35 @@
234 status = "disabled"; 388 status = "disabled";
235 }; 389 };
236 390
391 sdma2: sdma@302c0000 {
392 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
393 reg = <0x302c0000 0x10000>;
394 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
395 clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>,
396 <&clk IMX8MQ_CLK_SDMA2_ROOT>;
397 clock-names = "ipg", "ahb";
398 #dma-cells = <3>;
399 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
400 };
401
237 iomuxc: iomuxc@30330000 { 402 iomuxc: iomuxc@30330000 {
238 compatible = "fsl,imx8mq-iomuxc"; 403 compatible = "fsl,imx8mq-iomuxc";
239 reg = <0x30330000 0x10000>; 404 reg = <0x30330000 0x10000>;
240 }; 405 };
241 406
242 iomuxc_gpr: syscon@30340000 { 407 iomuxc_gpr: syscon@30340000 {
243 compatible = "fsl,imx8mq-iomuxc-gpr", "syscon"; 408 compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon";
244 reg = <0x30340000 0x10000>; 409 reg = <0x30340000 0x10000>;
245 }; 410 };
246 411
412 ocotp: ocotp-ctrl@30350000 {
413 compatible = "fsl,imx8mq-ocotp", "syscon";
414 reg = <0x30350000 0x10000>;
415 clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>;
416 #address-cells = <1>;
417 #size-cells = <1>;
418 };
419
247 anatop: syscon@30360000 { 420 anatop: syscon@30360000 {
248 compatible = "fsl,imx8mq-anatop", "syscon"; 421 compatible = "fsl,imx8mq-anatop", "syscon";
249 reg = <0x30360000 0x10000>; 422 reg = <0x30360000 0x10000>;
@@ -278,6 +451,12 @@
278 "clk_ext3", "clk_ext4"; 451 "clk_ext3", "clk_ext4";
279 }; 452 };
280 453
454 src: reset-controller@30390000 {
455 compatible = "fsl,imx8mq-src", "syscon";
456 reg = <0x30390000 0x10000>;
457 #reset-cells = <1>;
458 };
459
281 gpc: gpc@303a0000 { 460 gpc: gpc@303a0000 {
282 compatible = "fsl,imx8mq-gpc"; 461 compatible = "fsl,imx8mq-gpc";
283 reg = <0x303a0000 0x10000>; 462 reg = <0x303a0000 0x10000>;
@@ -294,9 +473,25 @@
294 reg = <IMX8M_POWER_DOMAIN_MIPI>; 473 reg = <IMX8M_POWER_DOMAIN_MIPI>;
295 }; 474 };
296 475
297 pgc_pcie1: power-domain@1 { 476 /*
477 * As per comment in ATF source code:
478 *
479 * PCIE1 and PCIE2 share the
480 * same reset signal, if we
481 * power down PCIE2, PCIE1
482 * will be held in reset too.
483 *
484 * So instead of creating two
485 * separate power domains for
486 * PCIE1 and PCIE2 we create a
487 * link between both and use
488 * it as a shared PCIE power
489 * domain.
490 */
491 pgc_pcie: power-domain@1 {
298 #power-domain-cells = <0>; 492 #power-domain-cells = <0>;
299 reg = <IMX8M_POWER_DOMAIN_PCIE1>; 493 reg = <IMX8M_POWER_DOMAIN_PCIE1>;
494 power-domains = <&pgc_pcie2>;
300 }; 495 };
301 496
302 pgc_otg1: power-domain@2 { 497 pgc_otg1: power-domain@2 {
@@ -478,6 +673,21 @@
478 status = "disabled"; 673 status = "disabled";
479 }; 674 };
480 675
676 sai2: sai@308b0000 {
677 #sound-dai-cells = <0>;
678 compatible = "fsl,imx8mq-sai",
679 "fsl,imx6sx-sai";
680 reg = <0x308b0000 0x10000>;
681 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
682 clocks = <&clk IMX8MQ_CLK_SAI2_IPG>,
683 <&clk IMX8MQ_CLK_SAI2_ROOT>,
684 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
685 clock-names = "bus", "mclk1", "mclk2", "mclk3";
686 dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>;
687 dma-names = "rx", "tx";
688 status = "disabled";
689 };
690
481 i2c1: i2c@30a20000 { 691 i2c1: i2c@30a20000 {
482 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 692 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
483 reg = <0x30a20000 0x10000>; 693 reg = <0x30a20000 0x10000>;
@@ -575,6 +785,17 @@
575 status = "disabled"; 785 status = "disabled";
576 }; 786 };
577 787
788 sdma1: sdma@30bd0000 {
789 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
790 reg = <0x30bd0000 0x10000>;
791 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
792 clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>,
793 <&clk IMX8MQ_CLK_AHB>;
794 clock-names = "ipg", "ahb";
795 #dma-cells = <3>;
796 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
797 };
798
578 fec1: ethernet@30be0000 { 799 fec1: ethernet@30be0000 {
579 compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 800 compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
580 reg = <0x30be0000 0x10000>; 801 reg = <0x30be0000 0x10000>;
@@ -594,6 +815,30 @@
594 }; 815 };
595 }; 816 };
596 817
818 gpu: gpu@38000000 {
819 compatible = "vivante,gc";
820 reg = <0x38000000 0x40000>;
821 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
822 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
823 <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
824 <&clk IMX8MQ_CLK_GPU_AXI>,
825 <&clk IMX8MQ_CLK_GPU_AHB>;
826 clock-names = "core", "shader", "bus", "reg";
827 assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>,
828 <&clk IMX8MQ_CLK_GPU_SHADER_SRC>,
829 <&clk IMX8MQ_CLK_GPU_AXI>,
830 <&clk IMX8MQ_CLK_GPU_AHB>,
831 <&clk IMX8MQ_GPU_PLL_BYPASS>;
832 assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>,
833 <&clk IMX8MQ_GPU_PLL_OUT>,
834 <&clk IMX8MQ_GPU_PLL_OUT>,
835 <&clk IMX8MQ_GPU_PLL_OUT>,
836 <&clk IMX8MQ_GPU_PLL>;
837 assigned-clock-rates = <800000000>, <800000000>,
838 <800000000>, <800000000>, <0>;
839 power-domains = <&pgc_gpu>;
840 };
841
597 usb_dwc3_0: usb@38100000 { 842 usb_dwc3_0: usb@38100000 {
598 compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; 843 compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
599 reg = <0x38100000 0x10000>; 844 reg = <0x38100000 0x10000>;
@@ -658,6 +903,66 @@
658 status = "disabled"; 903 status = "disabled";
659 }; 904 };
660 905
906
907 pcie0: pcie@33800000 {
908 compatible = "fsl,imx8mq-pcie";
909 reg = <0x33800000 0x400000>,
910 <0x1ff00000 0x80000>;
911 reg-names = "dbi", "config";
912 #address-cells = <3>;
913 #size-cells = <2>;
914 device_type = "pci";
915 bus-range = <0x00 0xff>;
916 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
917 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
918 num-lanes = <1>;
919 num-viewport = <4>;
920 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
921 interrupt-names = "msi";
922 #interrupt-cells = <1>;
923 interrupt-map-mask = <0 0 0 0x7>;
924 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
925 <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
926 <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
927 <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
928 fsl,max-link-speed = <2>;
929 power-domains = <&pgc_pcie>;
930 resets = <&src IMX8MQ_RESET_PCIEPHY>,
931 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
932 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
933 reset-names = "pciephy", "apps", "turnoff";
934 status = "disabled";
935 };
936
937 pcie1: pcie@33c00000 {
938 compatible = "fsl,imx8mq-pcie";
939 reg = <0x33c00000 0x400000>,
940 <0x27f00000 0x80000>;
941 reg-names = "dbi", "config";
942 #address-cells = <3>;
943 #size-cells = <2>;
944 device_type = "pci";
945 ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */
946 0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
947 num-lanes = <1>;
948 num-viewport = <4>;
949 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
950 interrupt-names = "msi";
951 #interrupt-cells = <1>;
952 interrupt-map-mask = <0 0 0 0x7>;
953 interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
954 <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
955 <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
956 <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
957 fsl,max-link-speed = <2>;
958 power-domains = <&pgc_pcie>;
959 resets = <&src IMX8MQ_RESET_PCIEPHY2>,
960 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
961 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
962 reset-names = "pciephy", "apps", "turnoff";
963 status = "disabled";
964 };
965
661 gic: interrupt-controller@38800000 { 966 gic: interrupt-controller@38800000 {
662 compatible = "arm,gic-v3"; 967 compatible = "arm,gic-v3";
663 reg = <0x38800000 0x10000>, /* GIC Dist */ 968 reg = <0x38800000 0x10000>, /* GIC Dist */
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
index 03aad66545c5..bfdada2db176 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
@@ -60,6 +60,82 @@
60 }; 60 };
61}; 61};
62 62
63&adma_i2c1 {
64 #address-cells = <1>;
65 #size-cells = <0>;
66 clock-frequency = <100000>;
67 pinctrl-names = "default";
68 pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>;
69 status = "okay";
70
71 i2c-switch@71 {
72 compatible = "nxp,pca9646", "nxp,pca9546";
73 #address-cells = <1>;
74 #size-cells = <0>;
75 reg = <0x71>;
76 reset-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_LOW>;
77
78 i2c@0 {
79 #address-cells = <1>;
80 #size-cells = <0>;
81 reg = <0>;
82
83 max7322: gpio@68 {
84 compatible = "maxim,max7322";
85 reg = <0x68>;
86 gpio-controller;
87 #gpio-cells = <2>;
88 };
89 };
90
91 i2c@1 {
92 #address-cells = <1>;
93 #size-cells = <0>;
94 reg = <1>;
95 };
96
97 i2c@2 {
98 #address-cells = <1>;
99 #size-cells = <0>;
100 reg = <2>;
101
102 pressure-sensor@60 {
103 compatible = "fsl,mpl3115";
104 reg = <0x60>;
105 };
106 };
107
108 i2c@3 {
109 #address-cells = <1>;
110 #size-cells = <0>;
111 reg = <3>;
112
113 pca9557_a: gpio@1a {
114 compatible = "nxp,pca9557";
115 reg = <0x1a>;
116 gpio-controller;
117 #gpio-cells = <2>;
118 };
119
120 pca9557_b: gpio@1d {
121 compatible = "nxp,pca9557";
122 reg = <0x1d>;
123 gpio-controller;
124 #gpio-cells = <2>;
125 };
126
127 light-sensor@44 {
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_isl29023>;
130 compatible = "isil,isl29023";
131 reg = <0x44>;
132 interrupt-parent = <&lsio_gpio1>;
133 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
134 };
135 };
136 };
137};
138
63&usdhc1 { 139&usdhc1 {
64 pinctrl-names = "default"; 140 pinctrl-names = "default";
65 pinctrl-0 = <&pinctrl_usdhc1>; 141 pinctrl-0 = <&pinctrl_usdhc1>;
@@ -100,6 +176,25 @@
100 >; 176 >;
101 }; 177 };
102 178
179 pinctrl_ioexp_rst: ioexp_rst_grp {
180 fsl,pins = <
181 IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021
182 >;
183 };
184
185 pinctrl_isl29023: isl29023grp {
186 fsl,pins = <
187 IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02 0x00000021
188 >;
189 };
190
191 pinctrl_lpi2c1: lpi2c1grp {
192 fsl,pins = <
193 IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021
194 IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021
195 >;
196 };
197
103 pinctrl_lpuart0: lpuart0grp { 198 pinctrl_lpuart0: lpuart0grp {
104 fsl,pins = < 199 fsl,pins = <
105 IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 200 IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 4c3dd95ed488..0683ee2a48ae 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -21,6 +21,7 @@
21 mmc1 = &usdhc2; 21 mmc1 = &usdhc2;
22 mmc2 = &usdhc3; 22 mmc2 = &usdhc3;
23 serial0 = &adma_lpuart0; 23 serial0 = &adma_lpuart0;
24 mu1 = &lsio_mu1;
24 }; 25 };
25 26
26 cpus { 27 cpus {
@@ -34,6 +35,9 @@
34 reg = <0x0 0x0>; 35 reg = <0x0 0x0>;
35 enable-method = "psci"; 36 enable-method = "psci";
36 next-level-cache = <&A35_L2>; 37 next-level-cache = <&A35_L2>;
38 clocks = <&clk IMX_A35_CLK>;
39 operating-points-v2 = <&a35_opp_table>;
40 #cooling-cells = <2>;
37 }; 41 };
38 42
39 A35_1: cpu@1 { 43 A35_1: cpu@1 {
@@ -42,6 +46,9 @@
42 reg = <0x0 0x1>; 46 reg = <0x0 0x1>;
43 enable-method = "psci"; 47 enable-method = "psci";
44 next-level-cache = <&A35_L2>; 48 next-level-cache = <&A35_L2>;
49 clocks = <&clk IMX_A35_CLK>;
50 operating-points-v2 = <&a35_opp_table>;
51 #cooling-cells = <2>;
45 }; 52 };
46 53
47 A35_2: cpu@2 { 54 A35_2: cpu@2 {
@@ -50,6 +57,9 @@
50 reg = <0x0 0x2>; 57 reg = <0x0 0x2>;
51 enable-method = "psci"; 58 enable-method = "psci";
52 next-level-cache = <&A35_L2>; 59 next-level-cache = <&A35_L2>;
60 clocks = <&clk IMX_A35_CLK>;
61 operating-points-v2 = <&a35_opp_table>;
62 #cooling-cells = <2>;
53 }; 63 };
54 64
55 A35_3: cpu@3 { 65 A35_3: cpu@3 {
@@ -58,6 +68,9 @@
58 reg = <0x0 0x3>; 68 reg = <0x0 0x3>;
59 enable-method = "psci"; 69 enable-method = "psci";
60 next-level-cache = <&A35_L2>; 70 next-level-cache = <&A35_L2>;
71 clocks = <&clk IMX_A35_CLK>;
72 operating-points-v2 = <&a35_opp_table>;
73 #cooling-cells = <2>;
61 }; 74 };
62 75
63 A35_L2: l2-cache0 { 76 A35_L2: l2-cache0 {
@@ -65,6 +78,24 @@
65 }; 78 };
66 }; 79 };
67 80
81 a35_opp_table: opp-table {
82 compatible = "operating-points-v2";
83 opp-shared;
84
85 opp-900000000 {
86 opp-hz = /bits/ 64 <900000000>;
87 opp-microvolt = <1000000>;
88 clock-latency-ns = <150000>;
89 };
90
91 opp-1200000000 {
92 opp-hz = /bits/ 64 <1200000000>;
93 opp-microvolt = <1100000>;
94 clock-latency-ns = <150000>;
95 opp-suspend;
96 };
97 };
98
68 gic: interrupt-controller@51a00000 { 99 gic: interrupt-controller@51a00000 {
69 compatible = "arm,gic-v3"; 100 compatible = "arm,gic-v3";
70 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ 101 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
@@ -87,7 +118,8 @@
87 scu { 118 scu {
88 compatible = "fsl,imx-scu"; 119 compatible = "fsl,imx-scu";
89 mbox-names = "tx0", "tx1", "tx2", "tx3", 120 mbox-names = "tx0", "tx1", "tx2", "tx3",
90 "rx0", "rx1", "rx2", "rx3"; 121 "rx0", "rx1", "rx2", "rx3",
122 "gip3";
91 mboxes = <&lsio_mu1 0 0 123 mboxes = <&lsio_mu1 0 0
92 &lsio_mu1 0 1 124 &lsio_mu1 0 1
93 &lsio_mu1 0 2 125 &lsio_mu1 0 2
@@ -95,7 +127,8 @@
95 &lsio_mu1 1 0 127 &lsio_mu1 1 0
96 &lsio_mu1 1 1 128 &lsio_mu1 1 1
97 &lsio_mu1 1 2 129 &lsio_mu1 1 2
98 &lsio_mu1 1 3>; 130 &lsio_mu1 1 3
131 &lsio_mu1 3 3>;
99 132
100 clk: clock-controller { 133 clk: clock-controller {
101 compatible = "fsl,imx8qxp-clk"; 134 compatible = "fsl,imx8qxp-clk";
@@ -163,6 +196,39 @@
163 status = "disabled"; 196 status = "disabled";
164 }; 197 };
165 198
199 adma_lpuart1: serial@5a070000 {
200 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
201 reg = <0x5a070000 0x1000>;
202 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
203 interrupt-parent = <&gic>;
204 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>;
205 clock-names = "ipg";
206 power-domains = <&pd IMX_SC_R_UART_1>;
207 status = "disabled";
208 };
209
210 adma_lpuart2: serial@5a080000 {
211 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
212 reg = <0x5a080000 0x1000>;
213 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
214 interrupt-parent = <&gic>;
215 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>;
216 clock-names = "ipg";
217 power-domains = <&pd IMX_SC_R_UART_2>;
218 status = "disabled";
219 };
220
221 adma_lpuart3: serial@5a090000 {
222 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
223 reg = <0x5a090000 0x1000>;
224 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
225 interrupt-parent = <&gic>;
226 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>;
227 clock-names = "ipg";
228 power-domains = <&pd IMX_SC_R_UART_3>;
229 status = "disabled";
230 };
231
166 adma_i2c0: i2c@5a800000 { 232 adma_i2c0: i2c@5a800000 {
167 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 233 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
168 reg = <0x5a800000 0x4000>; 234 reg = <0x5a800000 0x4000>;
@@ -328,7 +394,7 @@
328 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 394 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
329 reg = <0x5d1b0000 0x10000>; 395 reg = <0x5d1b0000 0x10000>;
330 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 396 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
331 #mbox-cells = <0>; 397 #mbox-cells = <2>;
332 status = "disabled"; 398 status = "disabled";
333 }; 399 };
334 400
@@ -339,11 +405,19 @@
339 #mbox-cells = <2>; 405 #mbox-cells = <2>;
340 }; 406 };
341 407
408 lsio_mu2: mailbox@5d1d0000 {
409 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
410 reg = <0x5d1d0000 0x10000>;
411 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
412 #mbox-cells = <2>;
413 status = "disabled";
414 };
415
342 lsio_mu3: mailbox@5d1e0000 { 416 lsio_mu3: mailbox@5d1e0000 {
343 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 417 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
344 reg = <0x5d1e0000 0x10000>; 418 reg = <0x5d1e0000 0x10000>;
345 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 419 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
346 #mbox-cells = <0>; 420 #mbox-cells = <2>;
347 status = "disabled"; 421 status = "disabled";
348 }; 422 };
349 423
@@ -351,7 +425,7 @@
351 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 425 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
352 reg = <0x5d1f0000 0x10000>; 426 reg = <0x5d1f0000 0x10000>;
353 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 427 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
354 #mbox-cells = <0>; 428 #mbox-cells = <2>;
355 status = "disabled"; 429 status = "disabled";
356 }; 430 };
357 431
@@ -443,4 +517,9 @@
443 power-domains = <&pd IMX_SC_R_GPIO_7>; 517 power-domains = <&pd IMX_SC_R_GPIO_7>;
444 }; 518 };
445 }; 519 };
520
521 watchdog {
522 compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
523 timeout-sec = <60>;
524 };
446}; 525};
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-30 12:05:27 -0500