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-rw-r--r--Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt3
-rw-r--r--Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.txt22
-rw-r--r--arch/x86/pci/vmd.c2
-rw-r--r--drivers/irqchip/Kconfig6
-rw-r--r--drivers/irqchip/Makefile2
-rw-r--r--drivers/irqchip/exynos-combiner.c14
-rw-r--r--drivers/irqchip/irq-armada-370-xp.c2
-rw-r--r--drivers/irqchip/irq-aspeed-vic.c230
-rw-r--r--drivers/irqchip/irq-bcm2835.c3
-rw-r--r--drivers/irqchip/irq-bcm2836.c6
-rw-r--r--drivers/irqchip/irq-bcm7120-l2.c10
-rw-r--r--drivers/irqchip/irq-brcmstb-l2.c4
-rw-r--r--drivers/irqchip/irq-gic-common.c4
-rw-r--r--drivers/irqchip/irq-gic-pm.c184
-rw-r--r--drivers/irqchip/irq-gic-v2m.c1
-rw-r--r--drivers/irqchip/irq-gic-v3-its.c404
-rw-r--r--drivers/irqchip/irq-gic.c134
-rw-r--r--drivers/irqchip/irq-mips-gic.c3
-rw-r--r--drivers/irqchip/irq-omap-intc.c2
-rw-r--r--drivers/irqchip/irq-s3c24xx.c36
-rw-r--r--drivers/irqchip/irq-sirfsoc.c11
-rw-r--r--drivers/irqchip/irq-tegra.c4
-rw-r--r--drivers/irqchip/irq-vic.c5
-rw-r--r--include/linux/irq.h5
-rw-r--r--include/linux/irqchip/arm-gic-v3.h4
-rw-r--r--include/linux/irqchip/arm-gic.h11
-rw-r--r--include/linux/irqdomain.h3
-rw-r--r--kernel/irq/chip.c83
-rw-r--r--kernel/irq/handle.c18
-rw-r--r--kernel/irq/internals.h2
-rw-r--r--kernel/irq/irqdomain.c66
-rw-r--r--kernel/irq/manage.c45
-rw-r--r--kernel/irq/proc.c9
33 files changed, 1074 insertions, 264 deletions
diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
index 793c20ff8fcc..5393e2a45a42 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
@@ -21,6 +21,7 @@ Main node required properties:
21 "arm,pl390" 21 "arm,pl390"
22 "arm,tc11mp-gic" 22 "arm,tc11mp-gic"
23 "brcm,brahma-b15-gic" 23 "brcm,brahma-b15-gic"
24 "nvidia,tegra210-agic"
24 "qcom,msm-8660-qgic" 25 "qcom,msm-8660-qgic"
25 "qcom,msm-qgic2" 26 "qcom,msm-qgic2"
26- interrupt-controller : Identifies the node as an interrupt controller 27- interrupt-controller : Identifies the node as an interrupt controller
@@ -68,7 +69,7 @@ Optional
68 "ic_clk" (for "arm,arm11mp-gic") 69 "ic_clk" (for "arm,arm11mp-gic")
69 "PERIPHCLKEN" (for "arm,cortex-a15-gic") 70 "PERIPHCLKEN" (for "arm,cortex-a15-gic")
70 "PERIPHCLK", "PERIPHCLKEN" (for "arm,cortex-a9-gic") 71 "PERIPHCLK", "PERIPHCLKEN" (for "arm,cortex-a9-gic")
71 "clk" (for "arm,gic-400") 72 "clk" (for "arm,gic-400" and "nvidia,tegra210")
72 "gclk" (for "arm,pl390") 73 "gclk" (for "arm,pl390")
73 74
74- power-domains : A phandle and PM domain specifier as defined by bindings of 75- power-domains : A phandle and PM domain specifier as defined by bindings of
diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.txt b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.txt
new file mode 100644
index 000000000000..6c6e85324b9d
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.txt
@@ -0,0 +1,22 @@
1Aspeed Vectored Interrupt Controller
2
3These bindings are for the Aspeed AST2400 interrupt controller register layout.
4The SoC has an legacy register layout, but this driver does not support that
5mode of operation.
6
7Required properties:
8
9- compatible : should be "aspeed,ast2400-vic".
10
11- interrupt-controller : Identifies the node as an interrupt controller
12- #interrupt-cells : Specifies the number of cells needed to encode an
13 interrupt source. The value shall be 1.
14
15Example:
16
17 vic: interrupt-controller@1e6c0080 {
18 compatible = "aspeed,ast2400-vic";
19 interrupt-controller;
20 #interrupt-cells = <1>;
21 reg = <0x1e6c0080 0x80>;
22 };
diff --git a/arch/x86/pci/vmd.c b/arch/x86/pci/vmd.c
index 7792aba266df..613cac7395c4 100644
--- a/arch/x86/pci/vmd.c
+++ b/arch/x86/pci/vmd.c
@@ -195,7 +195,7 @@ static int vmd_msi_init(struct irq_domain *domain, struct msi_domain_info *info,
195 vmdirq->virq = virq; 195 vmdirq->virq = virq;
196 196
197 irq_domain_set_info(domain, virq, vmdirq->irq->vmd_vector, info->chip, 197 irq_domain_set_info(domain, virq, vmdirq->irq->vmd_vector, info->chip,
198 vmdirq, handle_simple_irq, vmd, NULL); 198 vmdirq, handle_untracked_irq, vmd, NULL);
199 return 0; 199 return 0;
200} 200}
201 201
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index fa33c50b0e5a..5495a5ba8039 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -8,6 +8,12 @@ config ARM_GIC
8 select IRQ_DOMAIN_HIERARCHY 8 select IRQ_DOMAIN_HIERARCHY
9 select MULTI_IRQ_HANDLER 9 select MULTI_IRQ_HANDLER
10 10
11config ARM_GIC_PM
12 bool
13 depends on PM
14 select ARM_GIC
15 select PM_CLK
16
11config ARM_GIC_MAX_NR 17config ARM_GIC_MAX_NR
12 int 18 int
13 default 2 if ARCH_REALVIEW 19 default 2 if ARCH_REALVIEW
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 38853a187607..4c203b6b8163 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_ARCH_SUNXI) += irq-sun4i.o
24obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi-nmi.o 24obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi-nmi.o
25obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o 25obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o
26obj-$(CONFIG_ARM_GIC) += irq-gic.o irq-gic-common.o 26obj-$(CONFIG_ARM_GIC) += irq-gic.o irq-gic-common.o
27obj-$(CONFIG_ARM_GIC_PM) += irq-gic-pm.o
27obj-$(CONFIG_REALVIEW_DT) += irq-gic-realview.o 28obj-$(CONFIG_REALVIEW_DT) += irq-gic-realview.o
28obj-$(CONFIG_ARM_GIC_V2M) += irq-gic-v2m.o 29obj-$(CONFIG_ARM_GIC_V2M) += irq-gic-v2m.o
29obj-$(CONFIG_ARM_GIC_V3) += irq-gic-v3.o irq-gic-common.o 30obj-$(CONFIG_ARM_GIC_V3) += irq-gic-v3.o irq-gic-common.o
@@ -69,3 +70,4 @@ obj-$(CONFIG_PIC32_EVIC) += irq-pic32-evic.o
69obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o 70obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o
70obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o 71obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o
71obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o 72obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o
73obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o
diff --git a/drivers/irqchip/exynos-combiner.c b/drivers/irqchip/exynos-combiner.c
index ead15be2d20a..b78a169c9c83 100644
--- a/drivers/irqchip/exynos-combiner.c
+++ b/drivers/irqchip/exynos-combiner.c
@@ -55,14 +55,14 @@ static void combiner_mask_irq(struct irq_data *data)
55{ 55{
56 u32 mask = 1 << (data->hwirq % 32); 56 u32 mask = 1 << (data->hwirq % 32);
57 57
58 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR); 58 writel_relaxed(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
59} 59}
60 60
61static void combiner_unmask_irq(struct irq_data *data) 61static void combiner_unmask_irq(struct irq_data *data)
62{ 62{
63 u32 mask = 1 << (data->hwirq % 32); 63 u32 mask = 1 << (data->hwirq % 32);
64 64
65 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET); 65 writel_relaxed(mask, combiner_base(data) + COMBINER_ENABLE_SET);
66} 66}
67 67
68static void combiner_handle_cascade_irq(struct irq_desc *desc) 68static void combiner_handle_cascade_irq(struct irq_desc *desc)
@@ -75,7 +75,7 @@ static void combiner_handle_cascade_irq(struct irq_desc *desc)
75 chained_irq_enter(chip, desc); 75 chained_irq_enter(chip, desc);
76 76
77 spin_lock(&irq_controller_lock); 77 spin_lock(&irq_controller_lock);
78 status = __raw_readl(chip_data->base + COMBINER_INT_STATUS); 78 status = readl_relaxed(chip_data->base + COMBINER_INT_STATUS);
79 spin_unlock(&irq_controller_lock); 79 spin_unlock(&irq_controller_lock);
80 status &= chip_data->irq_mask; 80 status &= chip_data->irq_mask;
81 81
@@ -135,7 +135,7 @@ static void __init combiner_init_one(struct combiner_chip_data *combiner_data,
135 combiner_data->parent_irq = irq; 135 combiner_data->parent_irq = irq;
136 136
137 /* Disable all interrupts */ 137 /* Disable all interrupts */
138 __raw_writel(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR); 138 writel_relaxed(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR);
139} 139}
140 140
141static int combiner_irq_domain_xlate(struct irq_domain *d, 141static int combiner_irq_domain_xlate(struct irq_domain *d,
@@ -218,7 +218,7 @@ static int combiner_suspend(void)
218 218
219 for (i = 0; i < max_nr; i++) 219 for (i = 0; i < max_nr; i++)
220 combiner_data[i].pm_save = 220 combiner_data[i].pm_save =
221 __raw_readl(combiner_data[i].base + COMBINER_ENABLE_SET); 221 readl_relaxed(combiner_data[i].base + COMBINER_ENABLE_SET);
222 222
223 return 0; 223 return 0;
224} 224}
@@ -235,9 +235,9 @@ static void combiner_resume(void)
235 int i; 235 int i;
236 236
237 for (i = 0; i < max_nr; i++) { 237 for (i = 0; i < max_nr; i++) {
238 __raw_writel(combiner_data[i].irq_mask, 238 writel_relaxed(combiner_data[i].irq_mask,
239 combiner_data[i].base + COMBINER_ENABLE_CLEAR); 239 combiner_data[i].base + COMBINER_ENABLE_CLEAR);
240 __raw_writel(combiner_data[i].pm_save, 240 writel_relaxed(combiner_data[i].pm_save,
241 combiner_data[i].base + COMBINER_ENABLE_SET); 241 combiner_data[i].base + COMBINER_ENABLE_SET);
242 } 242 }
243} 243}
diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c
index e7dc6cbda2a1..7c42b1d13faf 100644
--- a/drivers/irqchip/irq-armada-370-xp.c
+++ b/drivers/irqchip/irq-armada-370-xp.c
@@ -541,7 +541,7 @@ static void armada_370_xp_mpic_resume(void)
541 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); 541 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
542} 542}
543 543
544struct syscore_ops armada_370_xp_mpic_syscore_ops = { 544static struct syscore_ops armada_370_xp_mpic_syscore_ops = {
545 .suspend = armada_370_xp_mpic_suspend, 545 .suspend = armada_370_xp_mpic_suspend,
546 .resume = armada_370_xp_mpic_resume, 546 .resume = armada_370_xp_mpic_resume,
547}; 547};
diff --git a/drivers/irqchip/irq-aspeed-vic.c b/drivers/irqchip/irq-aspeed-vic.c
new file mode 100644
index 000000000000..d24451d5bf8a
--- /dev/null
+++ b/drivers/irqchip/irq-aspeed-vic.c
@@ -0,0 +1,230 @@
1/*
2 * Copyright (C) 2015 - Ben Herrenschmidt, IBM Corp.
3 *
4 * Driver for Aspeed "new" VIC as found in SoC generation 3 and later
5 *
6 * Based on irq-vic.c:
7 *
8 * Copyright (C) 1999 - 2003 ARM Limited
9 * Copyright (C) 2000 Deep Blue Solutions Ltd
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 */
22
23#include <linux/export.h>
24#include <linux/init.h>
25#include <linux/list.h>
26#include <linux/io.h>
27#include <linux/irq.h>
28#include <linux/irqchip.h>
29#include <linux/irqchip/chained_irq.h>
30#include <linux/irqdomain.h>
31#include <linux/of.h>
32#include <linux/of_address.h>
33#include <linux/of_irq.h>
34#include <linux/syscore_ops.h>
35#include <linux/device.h>
36#include <linux/slab.h>
37
38#include <asm/exception.h>
39#include <asm/irq.h>
40
41/* These definitions correspond to the "new mapping" of the
42 * register set that interleaves "high" and "low". The offsets
43 * below are for the "low" register, add 4 to get to the high one
44 */
45#define AVIC_IRQ_STATUS 0x00
46#define AVIC_FIQ_STATUS 0x08
47#define AVIC_RAW_STATUS 0x10
48#define AVIC_INT_SELECT 0x18
49#define AVIC_INT_ENABLE 0x20
50#define AVIC_INT_ENABLE_CLR 0x28
51#define AVIC_INT_TRIGGER 0x30
52#define AVIC_INT_TRIGGER_CLR 0x38
53#define AVIC_INT_SENSE 0x40
54#define AVIC_INT_DUAL_EDGE 0x48
55#define AVIC_INT_EVENT 0x50
56#define AVIC_EDGE_CLR 0x58
57#define AVIC_EDGE_STATUS 0x60
58
59#define NUM_IRQS 64
60
61struct aspeed_vic {
62 void __iomem *base;
63 u32 edge_sources[2];
64 struct irq_domain *dom;
65};
66static struct aspeed_vic *system_avic;
67
68static void vic_init_hw(struct aspeed_vic *vic)
69{
70 u32 sense;
71
72 /* Disable all interrupts */
73 writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR);
74 writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR + 4);
75
76 /* Make sure no soft trigger is on */
77 writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR);
78 writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR + 4);
79
80 /* Set everything to be IRQ */
81 writel(0, vic->base + AVIC_INT_SELECT);
82 writel(0, vic->base + AVIC_INT_SELECT + 4);
83
84 /* Some interrupts have a programable high/low level trigger
85 * (4 GPIO direct inputs), for now we assume this was configured
86 * by firmware. We read which ones are edge now.
87 */
88 sense = readl(vic->base + AVIC_INT_SENSE);
89 vic->edge_sources[0] = ~sense;
90 sense = readl(vic->base + AVIC_INT_SENSE + 4);
91 vic->edge_sources[1] = ~sense;
92
93 /* Clear edge detection latches */
94 writel(0xffffffff, vic->base + AVIC_EDGE_CLR);
95 writel(0xffffffff, vic->base + AVIC_EDGE_CLR + 4);
96}
97
98static void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
99{
100 struct aspeed_vic *vic = system_avic;
101 u32 stat, irq;
102
103 for (;;) {
104 irq = 0;
105 stat = readl_relaxed(vic->base + AVIC_IRQ_STATUS);
106 if (!stat) {
107 stat = readl_relaxed(vic->base + AVIC_IRQ_STATUS + 4);
108 irq = 32;
109 }
110 if (stat == 0)
111 break;
112 irq += ffs(stat) - 1;
113 handle_domain_irq(vic->dom, irq, regs);
114 }
115}
116
117static void avic_ack_irq(struct irq_data *d)
118{
119 struct aspeed_vic *vic = irq_data_get_irq_chip_data(d);
120 unsigned int sidx = d->hwirq >> 5;
121 unsigned int sbit = 1u << (d->hwirq & 0x1f);
122
123 /* Clear edge latch for edge interrupts, nop for level */
124 if (vic->edge_sources[sidx] & sbit)
125 writel(sbit, vic->base + AVIC_EDGE_CLR + sidx * 4);
126}
127
128static void avic_mask_irq(struct irq_data *d)
129{
130 struct aspeed_vic *vic = irq_data_get_irq_chip_data(d);
131 unsigned int sidx = d->hwirq >> 5;
132 unsigned int sbit = 1u << (d->hwirq & 0x1f);
133
134 writel(sbit, vic->base + AVIC_INT_ENABLE_CLR + sidx * 4);
135}
136
137static void avic_unmask_irq(struct irq_data *d)
138{
139 struct aspeed_vic *vic = irq_data_get_irq_chip_data(d);
140 unsigned int sidx = d->hwirq >> 5;
141 unsigned int sbit = 1u << (d->hwirq & 0x1f);
142
143 writel(sbit, vic->base + AVIC_INT_ENABLE + sidx * 4);
144}
145
146/* For level irq, faster than going through a nop "ack" and mask */
147static void avic_mask_ack_irq(struct irq_data *d)
148{
149 struct aspeed_vic *vic = irq_data_get_irq_chip_data(d);
150 unsigned int sidx = d->hwirq >> 5;
151 unsigned int sbit = 1u << (d->hwirq & 0x1f);
152
153 /* First mask */
154 writel(sbit, vic->base + AVIC_INT_ENABLE_CLR + sidx * 4);
155
156 /* Then clear edge latch for edge interrupts */
157 if (vic->edge_sources[sidx] & sbit)
158 writel(sbit, vic->base + AVIC_EDGE_CLR + sidx * 4);
159}
160
161static struct irq_chip avic_chip = {
162 .name = "AVIC",
163 .irq_ack = avic_ack_irq,
164 .irq_mask = avic_mask_irq,
165 .irq_unmask = avic_unmask_irq,
166 .irq_mask_ack = avic_mask_ack_irq,
167};
168
169static int avic_map(struct irq_domain *d, unsigned int irq,
170 irq_hw_number_t hwirq)
171{
172 struct aspeed_vic *vic = d->host_data;
173 unsigned int sidx = hwirq >> 5;
174 unsigned int sbit = 1u << (hwirq & 0x1f);
175
176 /* Check if interrupt exists */
177 if (sidx > 1)
178 return -EPERM;
179
180 if (vic->edge_sources[sidx] & sbit)
181 irq_set_chip_and_handler(irq, &avic_chip, handle_edge_irq);
182 else
183 irq_set_chip_and_handler(irq, &avic_chip, handle_level_irq);
184 irq_set_chip_data(irq, vic);
185 irq_set_probe(irq);
186 return 0;
187}
188
189static struct irq_domain_ops avic_dom_ops = {
190 .map = avic_map,
191 .xlate = irq_domain_xlate_onetwocell,
192};
193
194static int __init avic_of_init(struct device_node *node,
195 struct device_node *parent)
196{
197 void __iomem *regs;
198 struct aspeed_vic *vic;
199
200 if (WARN(parent, "non-root Aspeed VIC not supported"))
201 return -EINVAL;
202 if (WARN(system_avic, "duplicate Aspeed VIC not supported"))
203 return -EINVAL;
204
205 regs = of_iomap(node, 0);
206 if (WARN_ON(!regs))
207 return -EIO;
208
209 vic = kzalloc(sizeof(struct aspeed_vic), GFP_KERNEL);
210 if (WARN_ON(!vic)) {
211 iounmap(regs);
212 return -ENOMEM;
213 }
214 vic->base = regs;
215
216 /* Initialize soures, all masked */
217 vic_init_hw(vic);
218
219 /* Ready to receive interrupts */
220 system_avic = vic;
221 set_handle_irq(avic_handle_irq);
222
223 /* Register our domain */
224 vic->dom = irq_domain_add_simple(node, NUM_IRQS, 0,
225 &avic_dom_ops, vic);
226
227 return 0;
228}
229
230IRQCHIP_DECLARE(aspeed_new_vic, "aspeed,ast2400-vic", avic_of_init);
diff --git a/drivers/irqchip/irq-bcm2835.c b/drivers/irqchip/irq-bcm2835.c
index bf9cc5f2e839..44d7c38dde47 100644
--- a/drivers/irqchip/irq-bcm2835.c
+++ b/drivers/irqchip/irq-bcm2835.c
@@ -52,7 +52,6 @@
52#include <linux/irqdomain.h> 52#include <linux/irqdomain.h>
53 53
54#include <asm/exception.h> 54#include <asm/exception.h>
55#include <asm/mach/irq.h>
56 55
57/* Put the bank and irq (32 bits) into the hwirq */ 56/* Put the bank and irq (32 bits) into the hwirq */
58#define MAKE_HWIRQ(b, n) ((b << 5) | (n)) 57#define MAKE_HWIRQ(b, n) ((b << 5) | (n))
@@ -242,7 +241,7 @@ static void __exception_irq_entry bcm2835_handle_irq(
242 u32 hwirq; 241 u32 hwirq;
243 242
244 while ((hwirq = get_next_armctrl_hwirq()) != ~0) 243 while ((hwirq = get_next_armctrl_hwirq()) != ~0)
245 handle_IRQ(irq_linear_revmap(intc.domain, hwirq), regs); 244 handle_domain_irq(intc.domain, hwirq, regs);
246} 245}
247 246
248static void bcm2836_chained_handle_irq(struct irq_desc *desc) 247static void bcm2836_chained_handle_irq(struct irq_desc *desc)
diff --git a/drivers/irqchip/irq-bcm2836.c b/drivers/irqchip/irq-bcm2836.c
index 72ff1d5c5de6..df1949c0aa23 100644
--- a/drivers/irqchip/irq-bcm2836.c
+++ b/drivers/irqchip/irq-bcm2836.c
@@ -180,7 +180,7 @@ __exception_irq_entry bcm2836_arm_irqchip_handle_irq(struct pt_regs *regs)
180 } else if (stat) { 180 } else if (stat) {
181 u32 hwirq = ffs(stat) - 1; 181 u32 hwirq = ffs(stat) - 1;
182 182
183 handle_IRQ(irq_linear_revmap(intc.domain, hwirq), regs); 183 handle_domain_irq(intc.domain, hwirq, regs);
184 } 184 }
185} 185}
186 186
@@ -224,8 +224,8 @@ static struct notifier_block bcm2836_arm_irqchip_cpu_notifier = {
224}; 224};
225 225
226#ifdef CONFIG_ARM 226#ifdef CONFIG_ARM
227int __init bcm2836_smp_boot_secondary(unsigned int cpu, 227static int __init bcm2836_smp_boot_secondary(unsigned int cpu,
228 struct task_struct *idle) 228 struct task_struct *idle)
229{ 229{
230 unsigned long secondary_startup_phys = 230 unsigned long secondary_startup_phys =
231 (unsigned long)virt_to_phys((void *)secondary_startup); 231 (unsigned long)virt_to_phys((void *)secondary_startup);
diff --git a/drivers/irqchip/irq-bcm7120-l2.c b/drivers/irqchip/irq-bcm7120-l2.c
index 61b18ab33ad9..0ec92631e23c 100644
--- a/drivers/irqchip/irq-bcm7120-l2.c
+++ b/drivers/irqchip/irq-bcm7120-l2.c
@@ -215,7 +215,7 @@ static int __init bcm7120_l2_intc_iomap_3380(struct device_node *dn,
215 return 0; 215 return 0;
216} 216}
217 217
218int __init bcm7120_l2_intc_probe(struct device_node *dn, 218static int __init bcm7120_l2_intc_probe(struct device_node *dn,
219 struct device_node *parent, 219 struct device_node *parent,
220 int (*iomap_regs_fn)(struct device_node *, 220 int (*iomap_regs_fn)(struct device_node *,
221 struct bcm7120_l2_intc_data *), 221 struct bcm7120_l2_intc_data *),
@@ -339,15 +339,15 @@ out_unmap:
339 return ret; 339 return ret;
340} 340}
341 341
342int __init bcm7120_l2_intc_probe_7120(struct device_node *dn, 342static int __init bcm7120_l2_intc_probe_7120(struct device_node *dn,
343 struct device_node *parent) 343 struct device_node *parent)
344{ 344{
345 return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_7120, 345 return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_7120,
346 "BCM7120 L2"); 346 "BCM7120 L2");
347} 347}
348 348
349int __init bcm7120_l2_intc_probe_3380(struct device_node *dn, 349static int __init bcm7120_l2_intc_probe_3380(struct device_node *dn,
350 struct device_node *parent) 350 struct device_node *parent)
351{ 351{
352 return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_3380, 352 return bcm7120_l2_intc_probe(dn, parent, bcm7120_l2_intc_iomap_3380,
353 "BCM3380 L2"); 353 "BCM3380 L2");
diff --git a/drivers/irqchip/irq-brcmstb-l2.c b/drivers/irqchip/irq-brcmstb-l2.c
index 65cd341f331a..1d4a5b46d9ae 100644
--- a/drivers/irqchip/irq-brcmstb-l2.c
+++ b/drivers/irqchip/irq-brcmstb-l2.c
@@ -112,8 +112,8 @@ static void brcmstb_l2_intc_resume(struct irq_data *d)
112 irq_gc_unlock(gc); 112 irq_gc_unlock(gc);
113} 113}
114 114
115int __init brcmstb_l2_intc_of_init(struct device_node *np, 115static int __init brcmstb_l2_intc_of_init(struct device_node *np,
116 struct device_node *parent) 116 struct device_node *parent)
117{ 117{
118 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 118 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
119 struct brcmstb_l2_intc_data *data; 119 struct brcmstb_l2_intc_data *data;
diff --git a/drivers/irqchip/irq-gic-common.c b/drivers/irqchip/irq-gic-common.c
index 89e7423f0ebb..9ae71804b5dd 100644
--- a/drivers/irqchip/irq-gic-common.c
+++ b/drivers/irqchip/irq-gic-common.c
@@ -90,8 +90,8 @@ int gic_configure_irq(unsigned int irq, unsigned int type,
90 return ret; 90 return ret;
91} 91}
92 92
93void __init gic_dist_config(void __iomem *base, int gic_irqs, 93void gic_dist_config(void __iomem *base, int gic_irqs,
94 void (*sync_access)(void)) 94 void (*sync_access)(void))
95{ 95{
96 unsigned int i; 96 unsigned int i;
97 97
diff --git a/drivers/irqchip/irq-gic-pm.c b/drivers/irqchip/irq-gic-pm.c
new file mode 100644
index 000000000000..4cbffba3ff13
--- /dev/null
+++ b/drivers/irqchip/irq-gic-pm.c
@@ -0,0 +1,184 @@
1/*
2 * Copyright (C) 2016 NVIDIA CORPORATION, All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16#include <linux/module.h>
17#include <linux/clk.h>
18#include <linux/of_device.h>
19#include <linux/of_irq.h>
20#include <linux/irqchip/arm-gic.h>
21#include <linux/platform_device.h>
22#include <linux/pm_clock.h>
23#include <linux/pm_runtime.h>
24#include <linux/slab.h>
25
26struct gic_clk_data {
27 unsigned int num_clocks;
28 const char *const *clocks;
29};
30
31static int gic_runtime_resume(struct device *dev)
32{
33 struct gic_chip_data *gic = dev_get_drvdata(dev);
34 int ret;
35
36 ret = pm_clk_resume(dev);
37 if (ret)
38 return ret;
39
40 /*
41 * On the very first resume, the pointer to the driver data
42 * will be NULL and this is intentional, because we do not
43 * want to restore the GIC on the very first resume. So if
44 * the pointer is not valid just return.
45 */
46 if (!gic)
47 return 0;
48
49 gic_dist_restore(gic);
50 gic_cpu_restore(gic);
51
52 return 0;
53}
54
55static int gic_runtime_suspend(struct device *dev)
56{
57 struct gic_chip_data *gic = dev_get_drvdata(dev);
58
59 gic_dist_save(gic);
60 gic_cpu_save(gic);
61
62 return pm_clk_suspend(dev);
63}
64
65static int gic_get_clocks(struct device *dev, const struct gic_clk_data *data)
66{
67 struct clk *clk;
68 unsigned int i;
69 int ret;
70
71 if (!dev || !data)
72 return -EINVAL;
73
74 ret = pm_clk_create(dev);
75 if (ret)
76 return ret;
77
78 for (i = 0; i < data->num_clocks; i++) {
79 clk = of_clk_get_by_name(dev->of_node, data->clocks[i]);
80 if (IS_ERR(clk)) {
81 dev_err(dev, "failed to get clock %s\n",
82 data->clocks[i]);
83 ret = PTR_ERR(clk);
84 goto error;
85 }
86
87 ret = pm_clk_add_clk(dev, clk);
88 if (ret) {
89 dev_err(dev, "failed to add clock at index %d\n", i);
90 clk_put(clk);
91 goto error;
92 }
93 }
94
95 return 0;
96
97error:
98 pm_clk_destroy(dev);
99
100 return ret;
101}
102
103static int gic_probe(struct platform_device *pdev)
104{
105 struct device *dev = &pdev->dev;
106 const struct gic_clk_data *data;
107 struct gic_chip_data *gic;
108 int ret, irq;
109
110 data = of_device_get_match_data(&pdev->dev);
111 if (!data) {
112 dev_err(&pdev->dev, "no device match found\n");
113 return -ENODEV;
114 }
115
116 irq = irq_of_parse_and_map(dev->of_node, 0);
117 if (!irq) {
118 dev_err(dev, "no parent interrupt found!\n");
119 return -EINVAL;
120 }
121
122 ret = gic_get_clocks(dev, data);
123 if (ret)
124 goto irq_dispose;
125
126 pm_runtime_enable(dev);
127
128 ret = pm_runtime_get_sync(dev);
129 if (ret < 0)
130 goto rpm_disable;
131
132 ret = gic_of_init_child(dev, &gic, irq);
133 if (ret)
134 goto rpm_put;
135
136 platform_set_drvdata(pdev, gic);
137
138 pm_runtime_put(dev);
139
140 dev_info(dev, "GIC IRQ controller registered\n");
141
142 return 0;
143
144rpm_put:
145 pm_runtime_put_sync(dev);
146rpm_disable:
147 pm_runtime_disable(dev);
148 pm_clk_destroy(dev);
149irq_dispose:
150 irq_dispose_mapping(irq);
151
152 return ret;
153}
154
155static const struct dev_pm_ops gic_pm_ops = {
156 SET_RUNTIME_PM_OPS(gic_runtime_suspend,
157 gic_runtime_resume, NULL)
158};
159
160static const char * const gic400_clocks[] = {
161 "clk",
162};
163
164static const struct gic_clk_data gic400_data = {
165 .num_clocks = ARRAY_SIZE(gic400_clocks),
166 .clocks = gic400_clocks,
167};
168
169static const struct of_device_id gic_match[] = {
170 { .compatible = "nvidia,tegra210-agic", .data = &gic400_data },
171 {},
172};
173MODULE_DEVICE_TABLE(of, gic_match);
174
175static struct platform_driver gic_driver = {
176 .probe = gic_probe,
177 .driver = {
178 .name = "gic",
179 .of_match_table = gic_match,
180 .pm = &gic_pm_ops,
181 }
182};
183
184builtin_platform_driver(gic_driver);
diff --git a/drivers/irqchip/irq-gic-v2m.c b/drivers/irqchip/irq-gic-v2m.c
index ad0d2960b664..35eb7ac5d21f 100644
--- a/drivers/irqchip/irq-gic-v2m.c
+++ b/drivers/irqchip/irq-gic-v2m.c
@@ -24,6 +24,7 @@
24#include <linux/of_pci.h> 24#include <linux/of_pci.h>
25#include <linux/slab.h> 25#include <linux/slab.h>
26#include <linux/spinlock.h> 26#include <linux/spinlock.h>
27#include <linux/irqchip/arm-gic.h>
27 28
28/* 29/*
29* MSI_TYPER: 30* MSI_TYPER:
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 5eb1f9e17a98..7ceaba81efb4 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -56,13 +56,14 @@ struct its_collection {
56}; 56};
57 57
58/* 58/*
59 * The ITS_BASER structure - contains memory information and cached 59 * The ITS_BASER structure - contains memory information, cached
60 * value of BASER register configuration. 60 * value of BASER register configuration and ITS page size.
61 */ 61 */
62struct its_baser { 62struct its_baser {
63 void *base; 63 void *base;
64 u64 val; 64 u64 val;
65 u32 order; 65 u32 order;
66 u32 psz;
66}; 67};
67 68
68/* 69/*
@@ -824,180 +825,241 @@ static const char *its_base_type_string[] = {
824 [GITS_BASER_TYPE_RESERVED7] = "Reserved (7)", 825 [GITS_BASER_TYPE_RESERVED7] = "Reserved (7)",
825}; 826};
826 827
827static void its_free_tables(struct its_node *its) 828static u64 its_read_baser(struct its_node *its, struct its_baser *baser)
828{ 829{
829 int i; 830 u32 idx = baser - its->tables;
830 831
831 for (i = 0; i < GITS_BASER_NR_REGS; i++) { 832 return readq_relaxed(its->base + GITS_BASER + (idx << 3));
832 if (its->tables[i].base) {
833 free_pages((unsigned long)its->tables[i].base,
834 its->tables[i].order);
835 its->tables[i].base = NULL;
836 }
837 }
838} 833}
839 834
840static int its_alloc_tables(const char *node_name, struct its_node *its) 835static void its_write_baser(struct its_node *its, struct its_baser *baser,
836 u64 val)
841{ 837{
842 int err; 838 u32 idx = baser - its->tables;
843 int i;
844 int psz = SZ_64K;
845 u64 shr = GITS_BASER_InnerShareable;
846 u64 cache;
847 u64 typer;
848 u32 ids;
849 839
850 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375) { 840 writeq_relaxed(val, its->base + GITS_BASER + (idx << 3));
851 /* 841 baser->val = its_read_baser(its, baser);
852 * erratum 22375: only alloc 8MB table size 842}
853 * erratum 24313: ignore memory access type 843
854 */ 844static int its_setup_baser(struct its_node *its, struct its_baser *baser,
855 cache = 0; 845 u64 cache, u64 shr, u32 psz, u32 order,
856 ids = 0x14; /* 20 bits, 8MB */ 846 bool indirect)
857 } else { 847{
858 cache = GITS_BASER_WaWb; 848 u64 val = its_read_baser(its, baser);
859 typer = readq_relaxed(its->base + GITS_TYPER); 849 u64 esz = GITS_BASER_ENTRY_SIZE(val);
860 ids = GITS_TYPER_DEVBITS(typer); 850 u64 type = GITS_BASER_TYPE(val);
851 u32 alloc_pages;
852 void *base;
853 u64 tmp;
854
855retry_alloc_baser:
856 alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
857 if (alloc_pages > GITS_BASER_PAGES_MAX) {
858 pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n",
859 &its->phys_base, its_base_type_string[type],
860 alloc_pages, GITS_BASER_PAGES_MAX);
861 alloc_pages = GITS_BASER_PAGES_MAX;
862 order = get_order(GITS_BASER_PAGES_MAX * psz);
861 } 863 }
862 864
863 its->device_ids = ids; 865 base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
866 if (!base)
867 return -ENOMEM;
864 868
865 for (i = 0; i < GITS_BASER_NR_REGS; i++) { 869retry_baser:
866 u64 val = readq_relaxed(its->base + GITS_BASER + i * 8); 870 val = (virt_to_phys(base) |
867 u64 type = GITS_BASER_TYPE(val); 871 (type << GITS_BASER_TYPE_SHIFT) |
868 u64 entry_size = GITS_BASER_ENTRY_SIZE(val); 872 ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) |
869 int order = get_order(psz); 873 ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT) |
870 int alloc_pages; 874 cache |
871 u64 tmp; 875 shr |
872 void *base; 876 GITS_BASER_VALID);
877
878 val |= indirect ? GITS_BASER_INDIRECT : 0x0;
879
880 switch (psz) {
881 case SZ_4K:
882 val |= GITS_BASER_PAGE_SIZE_4K;
883 break;
884 case SZ_16K:
885 val |= GITS_BASER_PAGE_SIZE_16K;
886 break;
887 case SZ_64K:
888 val |= GITS_BASER_PAGE_SIZE_64K;
889 break;
890 }
873 891
874 if (type == GITS_BASER_TYPE_NONE) 892 its_write_baser(its, baser, val);
875 continue; 893 tmp = baser->val;
876 894
895 if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
877 /* 896 /*
878 * Allocate as many entries as required to fit the 897 * Shareability didn't stick. Just use
879 * range of device IDs that the ITS can grok... The ID 898 * whatever the read reported, which is likely
880 * space being incredibly sparse, this results in a 899 * to be the only thing this redistributor
881 * massive waste of memory. 900 * supports. If that's zero, make it
882 * 901 * non-cacheable as well.
883 * For other tables, only allocate a single page.
884 */ 902 */
885 if (type == GITS_BASER_TYPE_DEVICE) { 903 shr = tmp & GITS_BASER_SHAREABILITY_MASK;
886 /* 904 if (!shr) {
887 * 'order' was initialized earlier to the default page 905 cache = GITS_BASER_nC;
888 * granule of the the ITS. We can't have an allocation 906 __flush_dcache_area(base, PAGE_ORDER_TO_SIZE(order));
889 * smaller than that. If the requested allocation
890 * is smaller, round up to the default page granule.
891 */
892 order = max(get_order((1UL << ids) * entry_size),
893 order);
894 if (order >= MAX_ORDER) {
895 order = MAX_ORDER - 1;
896 pr_warn("%s: Device Table too large, reduce its page order to %u\n",
897 node_name, order);
898 }
899 }
900
901retry_alloc_baser:
902 alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
903 if (alloc_pages > GITS_BASER_PAGES_MAX) {
904 alloc_pages = GITS_BASER_PAGES_MAX;
905 order = get_order(GITS_BASER_PAGES_MAX * psz);
906 pr_warn("%s: Device Table too large, reduce its page order to %u (%u pages)\n",
907 node_name, order, alloc_pages);
908 } 907 }
908 goto retry_baser;
909 }
909 910
910 base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order); 911 if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) {
911 if (!base) { 912 /*
912 err = -ENOMEM; 913 * Page size didn't stick. Let's try a smaller
913 goto out_free; 914 * size and retry. If we reach 4K, then
914 } 915 * something is horribly wrong...
915 916 */
916 its->tables[i].base = base; 917 free_pages((unsigned long)base, order);
917 its->tables[i].order = order; 918 baser->base = NULL;
918
919retry_baser:
920 val = (virt_to_phys(base) |
921 (type << GITS_BASER_TYPE_SHIFT) |
922 ((entry_size - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) |
923 cache |
924 shr |
925 GITS_BASER_VALID);
926 919
927 switch (psz) { 920 switch (psz) {
928 case SZ_4K:
929 val |= GITS_BASER_PAGE_SIZE_4K;
930 break;
931 case SZ_16K: 921 case SZ_16K:
932 val |= GITS_BASER_PAGE_SIZE_16K; 922 psz = SZ_4K;
933 break; 923 goto retry_alloc_baser;
934 case SZ_64K: 924 case SZ_64K:
935 val |= GITS_BASER_PAGE_SIZE_64K; 925 psz = SZ_16K;
936 break; 926 goto retry_alloc_baser;
937 } 927 }
928 }
929
930 if (val != tmp) {
931 pr_err("ITS@%pa: %s doesn't stick: %lx %lx\n",
932 &its->phys_base, its_base_type_string[type],
933 (unsigned long) val, (unsigned long) tmp);
934 free_pages((unsigned long)base, order);
935 return -ENXIO;
936 }
938 937
939 val |= alloc_pages - 1; 938 baser->order = order;
940 its->tables[i].val = val; 939 baser->base = base;
940 baser->psz = psz;
941 tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz;
941 942
942 writeq_relaxed(val, its->base + GITS_BASER + i * 8); 943 pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n",
943 tmp = readq_relaxed(its->base + GITS_BASER + i * 8); 944 &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / tmp),
945 its_base_type_string[type],
946 (unsigned long)virt_to_phys(base),
947 indirect ? "indirect" : "flat", (int)esz,
948 psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT);
944 949
945 if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) { 950 return 0;
951}
952
953static bool its_parse_baser_device(struct its_node *its, struct its_baser *baser,
954 u32 psz, u32 *order)
955{
956 u64 esz = GITS_BASER_ENTRY_SIZE(its_read_baser(its, baser));
957 u64 val = GITS_BASER_InnerShareable | GITS_BASER_WaWb;
958 u32 ids = its->device_ids;
959 u32 new_order = *order;
960 bool indirect = false;
961
962 /* No need to enable Indirection if memory requirement < (psz*2)bytes */
963 if ((esz << ids) > (psz * 2)) {
964 /*
965 * Find out whether hw supports a single or two-level table by
966 * table by reading bit at offset '62' after writing '1' to it.
967 */
968 its_write_baser(its, baser, val | GITS_BASER_INDIRECT);
969 indirect = !!(baser->val & GITS_BASER_INDIRECT);
970
971 if (indirect) {
946 /* 972 /*
947 * Shareability didn't stick. Just use 973 * The size of the lvl2 table is equal to ITS page size
948 * whatever the read reported, which is likely 974 * which is 'psz'. For computing lvl1 table size,
949 * to be the only thing this redistributor 975 * subtract ID bits that sparse lvl2 table from 'ids'
950 * supports. If that's zero, make it 976 * which is reported by ITS hardware times lvl1 table
951 * non-cacheable as well. 977 * entry size.
952 */ 978 */
953 shr = tmp & GITS_BASER_SHAREABILITY_MASK; 979 ids -= ilog2(psz / esz);
954 if (!shr) { 980 esz = GITS_LVL1_ENTRY_SIZE;
955 cache = GITS_BASER_nC;
956 __flush_dcache_area(base, PAGE_ORDER_TO_SIZE(order));
957 }
958 goto retry_baser;
959 } 981 }
982 }
960 983
961 if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) { 984 /*
962 /* 985 * Allocate as many entries as required to fit the
963 * Page size didn't stick. Let's try a smaller 986 * range of device IDs that the ITS can grok... The ID
964 * size and retry. If we reach 4K, then 987 * space being incredibly sparse, this results in a
965 * something is horribly wrong... 988 * massive waste of memory if two-level device table
966 */ 989 * feature is not supported by hardware.
967 free_pages((unsigned long)base, order); 990 */
968 its->tables[i].base = NULL; 991 new_order = max_t(u32, get_order(esz << ids), new_order);
992 if (new_order >= MAX_ORDER) {
993 new_order = MAX_ORDER - 1;
994 ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / esz);
995 pr_warn("ITS@%pa: Device Table too large, reduce ids %u->%u\n",
996 &its->phys_base, its->device_ids, ids);
997 }
969 998
970 switch (psz) { 999 *order = new_order;
971 case SZ_16K: 1000
972 psz = SZ_4K; 1001 return indirect;
973 goto retry_alloc_baser; 1002}
974 case SZ_64K:
975 psz = SZ_16K;
976 goto retry_alloc_baser;
977 }
978 }
979 1003
980 if (val != tmp) { 1004static void its_free_tables(struct its_node *its)
981 pr_err("ITS: %s: GITS_BASER%d doesn't stick: %lx %lx\n", 1005{
982 node_name, i, 1006 int i;
983 (unsigned long) val, (unsigned long) tmp); 1007
984 err = -ENXIO; 1008 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
985 goto out_free; 1009 if (its->tables[i].base) {
1010 free_pages((unsigned long)its->tables[i].base,
1011 its->tables[i].order);
1012 its->tables[i].base = NULL;
986 } 1013 }
1014 }
1015}
1016
1017static int its_alloc_tables(struct its_node *its)
1018{
1019 u64 typer = readq_relaxed(its->base + GITS_TYPER);
1020 u32 ids = GITS_TYPER_DEVBITS(typer);
1021 u64 shr = GITS_BASER_InnerShareable;
1022 u64 cache = GITS_BASER_WaWb;
1023 u32 psz = SZ_64K;
1024 int err, i;
987 1025
988 pr_info("ITS: allocated %d %s @%lx (psz %dK, shr %d)\n", 1026 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375) {
989 (int)(PAGE_ORDER_TO_SIZE(order) / entry_size), 1027 /*
990 its_base_type_string[type], 1028 * erratum 22375: only alloc 8MB table size
991 (unsigned long)virt_to_phys(base), 1029 * erratum 24313: ignore memory access type
992 psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT); 1030 */
1031 cache = GITS_BASER_nCnB;
1032 ids = 0x14; /* 20 bits, 8MB */
993 } 1033 }
994 1034
995 return 0; 1035 its->device_ids = ids;
996 1036
997out_free: 1037 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
998 its_free_tables(its); 1038 struct its_baser *baser = its->tables + i;
1039 u64 val = its_read_baser(its, baser);
1040 u64 type = GITS_BASER_TYPE(val);
1041 u32 order = get_order(psz);
1042 bool indirect = false;
999 1043
1000 return err; 1044 if (type == GITS_BASER_TYPE_NONE)
1045 continue;
1046
1047 if (type == GITS_BASER_TYPE_DEVICE)
1048 indirect = its_parse_baser_device(its, baser, psz, &order);
1049
1050 err = its_setup_baser(its, baser, cache, shr, psz, order, indirect);
1051 if (err < 0) {
1052 its_free_tables(its);
1053 return err;
1054 }
1055
1056 /* Update settings which will be used for next BASERn */
1057 psz = baser->psz;
1058 cache = baser->val & GITS_BASER_CACHEABILITY_MASK;
1059 shr = baser->val & GITS_BASER_SHAREABILITY_MASK;
1060 }
1061
1062 return 0;
1001} 1063}
1002 1064
1003static int its_alloc_collections(struct its_node *its) 1065static int its_alloc_collections(struct its_node *its)
@@ -1185,10 +1247,57 @@ static struct its_baser *its_get_baser(struct its_node *its, u32 type)
1185 return NULL; 1247 return NULL;
1186} 1248}
1187 1249
1250static bool its_alloc_device_table(struct its_node *its, u32 dev_id)
1251{
1252 struct its_baser *baser;
1253 struct page *page;
1254 u32 esz, idx;
1255 __le64 *table;
1256
1257 baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE);
1258
1259 /* Don't allow device id that exceeds ITS hardware limit */
1260 if (!baser)
1261 return (ilog2(dev_id) < its->device_ids);
1262
1263 /* Don't allow device id that exceeds single, flat table limit */
1264 esz = GITS_BASER_ENTRY_SIZE(baser->val);
1265 if (!(baser->val & GITS_BASER_INDIRECT))
1266 return (dev_id < (PAGE_ORDER_TO_SIZE(baser->order) / esz));
1267
1268 /* Compute 1st level table index & check if that exceeds table limit */
1269 idx = dev_id >> ilog2(baser->psz / esz);
1270 if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE))
1271 return false;
1272
1273 table = baser->base;
1274
1275 /* Allocate memory for 2nd level table */
1276 if (!table[idx]) {
1277 page = alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(baser->psz));
1278 if (!page)
1279 return false;
1280
1281 /* Flush Lvl2 table to PoC if hw doesn't support coherency */
1282 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
1283 __flush_dcache_area(page_address(page), baser->psz);
1284
1285 table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID);
1286
1287 /* Flush Lvl1 entry to PoC if hw doesn't support coherency */
1288 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
1289 __flush_dcache_area(table + idx, GITS_LVL1_ENTRY_SIZE);
1290
1291 /* Ensure updated table contents are visible to ITS hardware */
1292 dsb(sy);
1293 }
1294
1295 return true;
1296}
1297
1188static struct its_device *its_create_device(struct its_node *its, u32 dev_id, 1298static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
1189 int nvecs) 1299 int nvecs)
1190{ 1300{
1191 struct its_baser *baser;
1192 struct its_device *dev; 1301 struct its_device *dev;
1193 unsigned long *lpi_map; 1302 unsigned long *lpi_map;
1194 unsigned long flags; 1303 unsigned long flags;
@@ -1199,14 +1308,7 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
1199 int nr_ites; 1308 int nr_ites;
1200 int sz; 1309 int sz;
1201 1310
1202 baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE); 1311 if (!its_alloc_device_table(its, dev_id))
1203
1204 /* Don't allow 'dev_id' that exceeds single, flat table limit */
1205 if (baser) {
1206 if (dev_id >= (PAGE_ORDER_TO_SIZE(baser->order) /
1207 GITS_BASER_ENTRY_SIZE(baser->val)))
1208 return NULL;
1209 } else if (ilog2(dev_id) >= its->device_ids)
1210 return NULL; 1312 return NULL;
1211 1313
1212 dev = kzalloc(sizeof(*dev), GFP_KERNEL); 1314 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
@@ -1569,7 +1671,7 @@ static int __init its_probe(struct device_node *node,
1569 1671
1570 its_enable_quirks(its); 1672 its_enable_quirks(its);
1571 1673
1572 err = its_alloc_tables(node->full_name, its); 1674 err = its_alloc_tables(its);
1573 if (err) 1675 if (err)
1574 goto out_free_cmd; 1676 goto out_free_cmd;
1575 1677
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index fbc4ae2afd29..1de07eb5839c 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -75,7 +75,7 @@ struct gic_chip_data {
75 void __iomem *raw_dist_base; 75 void __iomem *raw_dist_base;
76 void __iomem *raw_cpu_base; 76 void __iomem *raw_cpu_base;
77 u32 percpu_offset; 77 u32 percpu_offset;
78#ifdef CONFIG_CPU_PM 78#if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM)
79 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)]; 79 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
80 u32 saved_spi_active[DIV_ROUND_UP(1020, 32)]; 80 u32 saved_spi_active[DIV_ROUND_UP(1020, 32)];
81 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)]; 81 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
@@ -449,7 +449,7 @@ static void gic_cpu_if_up(struct gic_chip_data *gic)
449} 449}
450 450
451 451
452static void __init gic_dist_init(struct gic_chip_data *gic) 452static void gic_dist_init(struct gic_chip_data *gic)
453{ 453{
454 unsigned int i; 454 unsigned int i;
455 u32 cpumask; 455 u32 cpumask;
@@ -528,14 +528,14 @@ int gic_cpu_if_down(unsigned int gic_nr)
528 return 0; 528 return 0;
529} 529}
530 530
531#ifdef CONFIG_CPU_PM 531#if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM)
532/* 532/*
533 * Saves the GIC distributor registers during suspend or idle. Must be called 533 * Saves the GIC distributor registers during suspend or idle. Must be called
534 * with interrupts disabled but before powering down the GIC. After calling 534 * with interrupts disabled but before powering down the GIC. After calling
535 * this function, no interrupts will be delivered by the GIC, and another 535 * this function, no interrupts will be delivered by the GIC, and another
536 * platform-specific wakeup source must be enabled. 536 * platform-specific wakeup source must be enabled.
537 */ 537 */
538static void gic_dist_save(struct gic_chip_data *gic) 538void gic_dist_save(struct gic_chip_data *gic)
539{ 539{
540 unsigned int gic_irqs; 540 unsigned int gic_irqs;
541 void __iomem *dist_base; 541 void __iomem *dist_base;
@@ -574,7 +574,7 @@ static void gic_dist_save(struct gic_chip_data *gic)
574 * handled normally, but any edge interrupts that occured will not be seen by 574 * handled normally, but any edge interrupts that occured will not be seen by
575 * the GIC and need to be handled by the platform-specific wakeup source. 575 * the GIC and need to be handled by the platform-specific wakeup source.
576 */ 576 */
577static void gic_dist_restore(struct gic_chip_data *gic) 577void gic_dist_restore(struct gic_chip_data *gic)
578{ 578{
579 unsigned int gic_irqs; 579 unsigned int gic_irqs;
580 unsigned int i; 580 unsigned int i;
@@ -620,7 +620,7 @@ static void gic_dist_restore(struct gic_chip_data *gic)
620 writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL); 620 writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL);
621} 621}
622 622
623static void gic_cpu_save(struct gic_chip_data *gic) 623void gic_cpu_save(struct gic_chip_data *gic)
624{ 624{
625 int i; 625 int i;
626 u32 *ptr; 626 u32 *ptr;
@@ -650,7 +650,7 @@ static void gic_cpu_save(struct gic_chip_data *gic)
650 650
651} 651}
652 652
653static void gic_cpu_restore(struct gic_chip_data *gic) 653void gic_cpu_restore(struct gic_chip_data *gic)
654{ 654{
655 int i; 655 int i;
656 u32 *ptr; 656 u32 *ptr;
@@ -727,7 +727,7 @@ static struct notifier_block gic_notifier_block = {
727 .notifier_call = gic_notifier, 727 .notifier_call = gic_notifier,
728}; 728};
729 729
730static int __init gic_pm_init(struct gic_chip_data *gic) 730static int gic_pm_init(struct gic_chip_data *gic)
731{ 731{
732 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, 732 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
733 sizeof(u32)); 733 sizeof(u32));
@@ -757,7 +757,7 @@ free_ppi_enable:
757 return -ENOMEM; 757 return -ENOMEM;
758} 758}
759#else 759#else
760static int __init gic_pm_init(struct gic_chip_data *gic) 760static int gic_pm_init(struct gic_chip_data *gic)
761{ 761{
762 return 0; 762 return 0;
763} 763}
@@ -1032,32 +1032,31 @@ static const struct irq_domain_ops gic_irq_domain_ops = {
1032 .unmap = gic_irq_domain_unmap, 1032 .unmap = gic_irq_domain_unmap,
1033}; 1033};
1034 1034
1035static int __init __gic_init_bases(struct gic_chip_data *gic, int irq_start, 1035static void gic_init_chip(struct gic_chip_data *gic, struct device *dev,
1036 struct fwnode_handle *handle) 1036 const char *name, bool use_eoimode1)
1037{ 1037{
1038 irq_hw_number_t hwirq_base;
1039 int gic_irqs, irq_base, i, ret;
1040
1041 if (WARN_ON(!gic || gic->domain))
1042 return -EINVAL;
1043
1044 /* Initialize irq_chip */ 1038 /* Initialize irq_chip */
1045 gic->chip = gic_chip; 1039 gic->chip = gic_chip;
1040 gic->chip.name = name;
1041 gic->chip.parent_device = dev;
1046 1042
1047 if (static_key_true(&supports_deactivate) && gic == &gic_data[0]) { 1043 if (use_eoimode1) {
1048 gic->chip.irq_mask = gic_eoimode1_mask_irq; 1044 gic->chip.irq_mask = gic_eoimode1_mask_irq;
1049 gic->chip.irq_eoi = gic_eoimode1_eoi_irq; 1045 gic->chip.irq_eoi = gic_eoimode1_eoi_irq;
1050 gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity; 1046 gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity;
1051 gic->chip.name = kasprintf(GFP_KERNEL, "GICv2");
1052 } else {
1053 gic->chip.name = kasprintf(GFP_KERNEL, "GIC-%d",
1054 (int)(gic - &gic_data[0]));
1055 } 1047 }
1056 1048
1057#ifdef CONFIG_SMP 1049#ifdef CONFIG_SMP
1058 if (gic == &gic_data[0]) 1050 if (gic == &gic_data[0])
1059 gic->chip.irq_set_affinity = gic_set_affinity; 1051 gic->chip.irq_set_affinity = gic_set_affinity;
1060#endif 1052#endif
1053}
1054
1055static int gic_init_bases(struct gic_chip_data *gic, int irq_start,
1056 struct fwnode_handle *handle)
1057{
1058 irq_hw_number_t hwirq_base;
1059 int gic_irqs, irq_base, ret;
1061 1060
1062 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) { 1061 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
1063 /* Frankein-GIC without banked registers... */ 1062 /* Frankein-GIC without banked registers... */
@@ -1138,6 +1137,36 @@ static int __init __gic_init_bases(struct gic_chip_data *gic, int irq_start,
1138 goto error; 1137 goto error;
1139 } 1138 }
1140 1139
1140 gic_dist_init(gic);
1141 ret = gic_cpu_init(gic);
1142 if (ret)
1143 goto error;
1144
1145 ret = gic_pm_init(gic);
1146 if (ret)
1147 goto error;
1148
1149 return 0;
1150
1151error:
1152 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
1153 free_percpu(gic->dist_base.percpu_base);
1154 free_percpu(gic->cpu_base.percpu_base);
1155 }
1156
1157 return ret;
1158}
1159
1160static int __init __gic_init_bases(struct gic_chip_data *gic,
1161 int irq_start,
1162 struct fwnode_handle *handle)
1163{
1164 char *name;
1165 int i, ret;
1166
1167 if (WARN_ON(!gic || gic->domain))
1168 return -EINVAL;
1169
1141 if (gic == &gic_data[0]) { 1170 if (gic == &gic_data[0]) {
1142 /* 1171 /*
1143 * Initialize the CPU interface map to all CPUs. 1172 * Initialize the CPU interface map to all CPUs.
@@ -1155,24 +1184,17 @@ static int __init __gic_init_bases(struct gic_chip_data *gic, int irq_start,
1155 pr_info("GIC: Using split EOI/Deactivate mode\n"); 1184 pr_info("GIC: Using split EOI/Deactivate mode\n");
1156 } 1185 }
1157 1186
1158 gic_dist_init(gic); 1187 if (static_key_true(&supports_deactivate) && gic == &gic_data[0]) {
1159 ret = gic_cpu_init(gic); 1188 name = kasprintf(GFP_KERNEL, "GICv2");
1160 if (ret) 1189 gic_init_chip(gic, NULL, name, true);
1161 goto error; 1190 } else {
1162 1191 name = kasprintf(GFP_KERNEL, "GIC-%d", (int)(gic-&gic_data[0]));
1163 ret = gic_pm_init(gic); 1192 gic_init_chip(gic, NULL, name, false);
1164 if (ret)
1165 goto error;
1166
1167 return 0;
1168
1169error:
1170 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
1171 free_percpu(gic->dist_base.percpu_base);
1172 free_percpu(gic->cpu_base.percpu_base);
1173 } 1193 }
1174 1194
1175 kfree(gic->chip.name); 1195 ret = gic_init_bases(gic, irq_start, handle);
1196 if (ret)
1197 kfree(name);
1176 1198
1177 return ret; 1199 return ret;
1178} 1200}
@@ -1250,7 +1272,7 @@ static bool gic_check_eoimode(struct device_node *node, void __iomem **base)
1250 return true; 1272 return true;
1251} 1273}
1252 1274
1253static int __init gic_of_setup(struct gic_chip_data *gic, struct device_node *node) 1275static int gic_of_setup(struct gic_chip_data *gic, struct device_node *node)
1254{ 1276{
1255 if (!gic || !node) 1277 if (!gic || !node)
1256 return -EINVAL; 1278 return -EINVAL;
@@ -1274,6 +1296,34 @@ error:
1274 return -ENOMEM; 1296 return -ENOMEM;
1275} 1297}
1276 1298
1299int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
1300{
1301 int ret;
1302
1303 if (!dev || !dev->of_node || !gic || !irq)
1304 return -EINVAL;
1305
1306 *gic = devm_kzalloc(dev, sizeof(**gic), GFP_KERNEL);
1307 if (!*gic)
1308 return -ENOMEM;
1309
1310 gic_init_chip(*gic, dev, dev->of_node->name, false);
1311
1312 ret = gic_of_setup(*gic, dev->of_node);
1313 if (ret)
1314 return ret;
1315
1316 ret = gic_init_bases(*gic, -1, &dev->of_node->fwnode);
1317 if (ret) {
1318 gic_teardown(*gic);
1319 return ret;
1320 }
1321
1322 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, *gic);
1323
1324 return 0;
1325}
1326
1277static void __init gic_of_setup_kvm_info(struct device_node *node) 1327static void __init gic_of_setup_kvm_info(struct device_node *node)
1278{ 1328{
1279 int ret; 1329 int ret;
@@ -1353,7 +1403,11 @@ IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
1353IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); 1403IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
1354IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); 1404IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
1355IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init); 1405IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init);
1356 1406#else
1407int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
1408{
1409 return -ENOTSUPP;
1410}
1357#endif 1411#endif
1358 1412
1359#ifdef CONFIG_ACPI 1413#ifdef CONFIG_ACPI
diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index 8a4adbeb2b8c..f4dff5665e4e 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -1042,12 +1042,14 @@ static void __init __gic_init(unsigned long gic_base_addr,
1042 &gic_irq_domain_ops, NULL); 1042 &gic_irq_domain_ops, NULL);
1043 if (!gic_irq_domain) 1043 if (!gic_irq_domain)
1044 panic("Failed to add GIC IRQ domain"); 1044 panic("Failed to add GIC IRQ domain");
1045 gic_irq_domain->name = "mips-gic-irq";
1045 1046
1046 gic_dev_domain = irq_domain_add_hierarchy(gic_irq_domain, 0, 1047 gic_dev_domain = irq_domain_add_hierarchy(gic_irq_domain, 0,
1047 GIC_NUM_LOCAL_INTRS + gic_shared_intrs, 1048 GIC_NUM_LOCAL_INTRS + gic_shared_intrs,
1048 node, &gic_dev_domain_ops, NULL); 1049 node, &gic_dev_domain_ops, NULL);
1049 if (!gic_dev_domain) 1050 if (!gic_dev_domain)
1050 panic("Failed to add GIC DEV domain"); 1051 panic("Failed to add GIC DEV domain");
1052 gic_dev_domain->name = "mips-gic-dev";
1051 1053
1052 gic_ipi_domain = irq_domain_add_hierarchy(gic_irq_domain, 1054 gic_ipi_domain = irq_domain_add_hierarchy(gic_irq_domain,
1053 IRQ_DOMAIN_FLAG_IPI_PER_CPU, 1055 IRQ_DOMAIN_FLAG_IPI_PER_CPU,
@@ -1056,6 +1058,7 @@ static void __init __gic_init(unsigned long gic_base_addr,
1056 if (!gic_ipi_domain) 1058 if (!gic_ipi_domain)
1057 panic("Failed to add GIC IPI domain"); 1059 panic("Failed to add GIC IPI domain");
1058 1060
1061 gic_ipi_domain->name = "mips-gic-ipi";
1059 gic_ipi_domain->bus_token = DOMAIN_BUS_IPI; 1062 gic_ipi_domain->bus_token = DOMAIN_BUS_IPI;
1060 1063
1061 if (node && 1064 if (node &&
diff --git a/drivers/irqchip/irq-omap-intc.c b/drivers/irqchip/irq-omap-intc.c
index 9d1bcfc33e4c..b04a8ac6e744 100644
--- a/drivers/irqchip/irq-omap-intc.c
+++ b/drivers/irqchip/irq-omap-intc.c
@@ -23,6 +23,8 @@
23#include <linux/of_address.h> 23#include <linux/of_address.h>
24#include <linux/of_irq.h> 24#include <linux/of_irq.h>
25 25
26#include <linux/irqchip/irq-omap-intc.h>
27
26/* Define these here for now until we drop all board-files */ 28/* Define these here for now until we drop all board-files */
27#define OMAP24XX_IC_BASE 0x480fe000 29#define OMAP24XX_IC_BASE 0x480fe000
28#define OMAP34XX_IC_BASE 0x48200000 30#define OMAP34XX_IC_BASE 0x48200000
diff --git a/drivers/irqchip/irq-s3c24xx.c b/drivers/irqchip/irq-s3c24xx.c
index 5dc5a760c723..c25ce5af091a 100644
--- a/drivers/irqchip/irq-s3c24xx.c
+++ b/drivers/irqchip/irq-s3c24xx.c
@@ -92,9 +92,9 @@ static void s3c_irq_mask(struct irq_data *data)
92 unsigned long mask; 92 unsigned long mask;
93 unsigned int irqno; 93 unsigned int irqno;
94 94
95 mask = __raw_readl(intc->reg_mask); 95 mask = readl_relaxed(intc->reg_mask);
96 mask |= (1UL << irq_data->offset); 96 mask |= (1UL << irq_data->offset);
97 __raw_writel(mask, intc->reg_mask); 97 writel_relaxed(mask, intc->reg_mask);
98 98
99 if (parent_intc) { 99 if (parent_intc) {
100 parent_data = &parent_intc->irqs[irq_data->parent_irq]; 100 parent_data = &parent_intc->irqs[irq_data->parent_irq];
@@ -119,9 +119,9 @@ static void s3c_irq_unmask(struct irq_data *data)
119 unsigned long mask; 119 unsigned long mask;
120 unsigned int irqno; 120 unsigned int irqno;
121 121
122 mask = __raw_readl(intc->reg_mask); 122 mask = readl_relaxed(intc->reg_mask);
123 mask &= ~(1UL << irq_data->offset); 123 mask &= ~(1UL << irq_data->offset);
124 __raw_writel(mask, intc->reg_mask); 124 writel_relaxed(mask, intc->reg_mask);
125 125
126 if (parent_intc) { 126 if (parent_intc) {
127 irqno = irq_find_mapping(parent_intc->domain, 127 irqno = irq_find_mapping(parent_intc->domain,
@@ -136,9 +136,9 @@ static inline void s3c_irq_ack(struct irq_data *data)
136 struct s3c_irq_intc *intc = irq_data->intc; 136 struct s3c_irq_intc *intc = irq_data->intc;
137 unsigned long bitval = 1UL << irq_data->offset; 137 unsigned long bitval = 1UL << irq_data->offset;
138 138
139 __raw_writel(bitval, intc->reg_pending); 139 writel_relaxed(bitval, intc->reg_pending);
140 if (intc->reg_intpnd) 140 if (intc->reg_intpnd)
141 __raw_writel(bitval, intc->reg_intpnd); 141 writel_relaxed(bitval, intc->reg_intpnd);
142} 142}
143 143
144static int s3c_irq_type(struct irq_data *data, unsigned int type) 144static int s3c_irq_type(struct irq_data *data, unsigned int type)
@@ -172,9 +172,9 @@ static int s3c_irqext_type_set(void __iomem *gpcon_reg,
172 unsigned long newvalue = 0, value; 172 unsigned long newvalue = 0, value;
173 173
174 /* Set the GPIO to external interrupt mode */ 174 /* Set the GPIO to external interrupt mode */
175 value = __raw_readl(gpcon_reg); 175 value = readl_relaxed(gpcon_reg);
176 value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset); 176 value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
177 __raw_writel(value, gpcon_reg); 177 writel_relaxed(value, gpcon_reg);
178 178
179 /* Set the external interrupt to pointed trigger type */ 179 /* Set the external interrupt to pointed trigger type */
180 switch (type) 180 switch (type)
@@ -208,9 +208,9 @@ static int s3c_irqext_type_set(void __iomem *gpcon_reg,
208 return -EINVAL; 208 return -EINVAL;
209 } 209 }
210 210
211 value = __raw_readl(extint_reg); 211 value = readl_relaxed(extint_reg);
212 value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset); 212 value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
213 __raw_writel(value, extint_reg); 213 writel_relaxed(value, extint_reg);
214 214
215 return 0; 215 return 0;
216} 216}
@@ -315,8 +315,8 @@ static void s3c_irq_demux(struct irq_desc *desc)
315 315
316 chained_irq_enter(chip, desc); 316 chained_irq_enter(chip, desc);
317 317
318 src = __raw_readl(sub_intc->reg_pending); 318 src = readl_relaxed(sub_intc->reg_pending);
319 msk = __raw_readl(sub_intc->reg_mask); 319 msk = readl_relaxed(sub_intc->reg_mask);
320 320
321 src &= ~msk; 321 src &= ~msk;
322 src &= irq_data->sub_bits; 322 src &= irq_data->sub_bits;
@@ -337,7 +337,7 @@ static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc,
337 int pnd; 337 int pnd;
338 int offset; 338 int offset;
339 339
340 pnd = __raw_readl(intc->reg_intpnd); 340 pnd = readl_relaxed(intc->reg_intpnd);
341 if (!pnd) 341 if (!pnd)
342 return false; 342 return false;
343 343
@@ -352,7 +352,7 @@ static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc,
352 * 352 *
353 * Thanks to Klaus, Shannon, et al for helping to debug this problem 353 * Thanks to Klaus, Shannon, et al for helping to debug this problem
354 */ 354 */
355 offset = __raw_readl(intc->reg_intpnd + 4); 355 offset = readl_relaxed(intc->reg_intpnd + 4);
356 356
357 /* Find the bit manually, when the offset is wrong. 357 /* Find the bit manually, when the offset is wrong.
358 * The pending register only ever contains the one bit of the next 358 * The pending register only ever contains the one bit of the next
@@ -406,7 +406,7 @@ int s3c24xx_set_fiq(unsigned int irq, bool on)
406 intmod = 0; 406 intmod = 0;
407 } 407 }
408 408
409 __raw_writel(intmod, S3C2410_INTMOD); 409 writel_relaxed(intmod, S3C2410_INTMOD);
410 return 0; 410 return 0;
411} 411}
412 412
@@ -508,14 +508,14 @@ static void s3c24xx_clear_intc(struct s3c_irq_intc *intc)
508 508
509 last = 0; 509 last = 0;
510 for (i = 0; i < 4; i++) { 510 for (i = 0; i < 4; i++) {
511 pend = __raw_readl(reg_source); 511 pend = readl_relaxed(reg_source);
512 512
513 if (pend == 0 || pend == last) 513 if (pend == 0 || pend == last)
514 break; 514 break;
515 515
516 __raw_writel(pend, intc->reg_pending); 516 writel_relaxed(pend, intc->reg_pending);
517 if (intc->reg_intpnd) 517 if (intc->reg_intpnd)
518 __raw_writel(pend, intc->reg_intpnd); 518 writel_relaxed(pend, intc->reg_intpnd);
519 519
520 pr_info("irq: clearing pending status %08x\n", (int)pend); 520 pr_info("irq: clearing pending status %08x\n", (int)pend);
521 last = pend; 521 last = pend;
diff --git a/drivers/irqchip/irq-sirfsoc.c b/drivers/irqchip/irq-sirfsoc.c
index 10cb21b9ba3d..e1336848affa 100644
--- a/drivers/irqchip/irq-sirfsoc.c
+++ b/drivers/irqchip/irq-sirfsoc.c
@@ -29,6 +29,11 @@
29 29
30static struct irq_domain *sirfsoc_irqdomain; 30static struct irq_domain *sirfsoc_irqdomain;
31 31
32static void __iomem *sirfsoc_irq_get_regbase(void)
33{
34 return (void __iomem __force *)sirfsoc_irqdomain->host_data;
35}
36
32static __init void sirfsoc_alloc_gc(void __iomem *base) 37static __init void sirfsoc_alloc_gc(void __iomem *base)
33{ 38{
34 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 39 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
@@ -53,7 +58,7 @@ static __init void sirfsoc_alloc_gc(void __iomem *base)
53 58
54static void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs) 59static void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs)
55{ 60{
56 void __iomem *base = sirfsoc_irqdomain->host_data; 61 void __iomem *base = sirfsoc_irq_get_regbase();
57 u32 irqstat; 62 u32 irqstat;
58 63
59 irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID); 64 irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID);
@@ -94,7 +99,7 @@ static struct sirfsoc_irq_status sirfsoc_irq_st;
94 99
95static int sirfsoc_irq_suspend(void) 100static int sirfsoc_irq_suspend(void)
96{ 101{
97 void __iomem *base = sirfsoc_irqdomain->host_data; 102 void __iomem *base = sirfsoc_irq_get_regbase();
98 103
99 sirfsoc_irq_st.mask0 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK0); 104 sirfsoc_irq_st.mask0 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK0);
100 sirfsoc_irq_st.mask1 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK1); 105 sirfsoc_irq_st.mask1 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK1);
@@ -106,7 +111,7 @@ static int sirfsoc_irq_suspend(void)
106 111
107static void sirfsoc_irq_resume(void) 112static void sirfsoc_irq_resume(void)
108{ 113{
109 void __iomem *base = sirfsoc_irqdomain->host_data; 114 void __iomem *base = sirfsoc_irq_get_regbase();
110 115
111 writel_relaxed(sirfsoc_irq_st.mask0, base + SIRFSOC_INT_RISC_MASK0); 116 writel_relaxed(sirfsoc_irq_st.mask0, base + SIRFSOC_INT_RISC_MASK0);
112 writel_relaxed(sirfsoc_irq_st.mask1, base + SIRFSOC_INT_RISC_MASK1); 117 writel_relaxed(sirfsoc_irq_st.mask1, base + SIRFSOC_INT_RISC_MASK1);
diff --git a/drivers/irqchip/irq-tegra.c b/drivers/irqchip/irq-tegra.c
index e902f081e16c..3973a14bb15b 100644
--- a/drivers/irqchip/irq-tegra.c
+++ b/drivers/irqchip/irq-tegra.c
@@ -90,7 +90,7 @@ static struct tegra_ictlr_info *lic;
90 90
91static inline void tegra_ictlr_write_mask(struct irq_data *d, unsigned long reg) 91static inline void tegra_ictlr_write_mask(struct irq_data *d, unsigned long reg)
92{ 92{
93 void __iomem *base = d->chip_data; 93 void __iomem *base = (void __iomem __force *)d->chip_data;
94 u32 mask; 94 u32 mask;
95 95
96 mask = BIT(d->hwirq % 32); 96 mask = BIT(d->hwirq % 32);
@@ -266,7 +266,7 @@ static int tegra_ictlr_domain_alloc(struct irq_domain *domain,
266 266
267 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, 267 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
268 &tegra_ictlr_chip, 268 &tegra_ictlr_chip,
269 info->base[ictlr]); 269 (void __force *)info->base[ictlr]);
270 } 270 }
271 271
272 parent_fwspec = *fwspec; 272 parent_fwspec = *fwspec;
diff --git a/drivers/irqchip/irq-vic.c b/drivers/irqchip/irq-vic.c
index b956dfffe78c..f811a7de5857 100644
--- a/drivers/irqchip/irq-vic.c
+++ b/drivers/irqchip/irq-vic.c
@@ -167,7 +167,7 @@ static int vic_suspend(void)
167 return 0; 167 return 0;
168} 168}
169 169
170struct syscore_ops vic_syscore_ops = { 170static struct syscore_ops vic_syscore_ops = {
171 .suspend = vic_suspend, 171 .suspend = vic_suspend,
172 .resume = vic_resume, 172 .resume = vic_resume,
173}; 173};
@@ -517,7 +517,8 @@ int __init vic_init_cascaded(void __iomem *base, unsigned int parent_irq,
517EXPORT_SYMBOL_GPL(vic_init_cascaded); 517EXPORT_SYMBOL_GPL(vic_init_cascaded);
518 518
519#ifdef CONFIG_OF 519#ifdef CONFIG_OF
520int __init vic_of_init(struct device_node *node, struct device_node *parent) 520static int __init vic_of_init(struct device_node *node,
521 struct device_node *parent)
521{ 522{
522 void __iomem *regs; 523 void __iomem *regs;
523 u32 interrupt_mask = ~0; 524 u32 interrupt_mask = ~0;
diff --git a/include/linux/irq.h b/include/linux/irq.h
index 39ce46ac5c18..b52424eaa0ed 100644
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -322,6 +322,7 @@ static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d)
322/** 322/**
323 * struct irq_chip - hardware interrupt chip descriptor 323 * struct irq_chip - hardware interrupt chip descriptor
324 * 324 *
325 * @parent_device: pointer to parent device for irqchip
325 * @name: name for /proc/interrupts 326 * @name: name for /proc/interrupts
326 * @irq_startup: start up the interrupt (defaults to ->enable if NULL) 327 * @irq_startup: start up the interrupt (defaults to ->enable if NULL)
327 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL) 328 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL)
@@ -361,6 +362,7 @@ static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d)
361 * @flags: chip specific flags 362 * @flags: chip specific flags
362 */ 363 */
363struct irq_chip { 364struct irq_chip {
365 struct device *parent_device;
364 const char *name; 366 const char *name;
365 unsigned int (*irq_startup)(struct irq_data *data); 367 unsigned int (*irq_startup)(struct irq_data *data);
366 void (*irq_shutdown)(struct irq_data *data); 368 void (*irq_shutdown)(struct irq_data *data);
@@ -489,12 +491,15 @@ extern void handle_fasteoi_irq(struct irq_desc *desc);
489extern void handle_edge_irq(struct irq_desc *desc); 491extern void handle_edge_irq(struct irq_desc *desc);
490extern void handle_edge_eoi_irq(struct irq_desc *desc); 492extern void handle_edge_eoi_irq(struct irq_desc *desc);
491extern void handle_simple_irq(struct irq_desc *desc); 493extern void handle_simple_irq(struct irq_desc *desc);
494extern void handle_untracked_irq(struct irq_desc *desc);
492extern void handle_percpu_irq(struct irq_desc *desc); 495extern void handle_percpu_irq(struct irq_desc *desc);
493extern void handle_percpu_devid_irq(struct irq_desc *desc); 496extern void handle_percpu_devid_irq(struct irq_desc *desc);
494extern void handle_bad_irq(struct irq_desc *desc); 497extern void handle_bad_irq(struct irq_desc *desc);
495extern void handle_nested_irq(unsigned int irq); 498extern void handle_nested_irq(unsigned int irq);
496 499
497extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg); 500extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg);
501extern int irq_chip_pm_get(struct irq_data *data);
502extern int irq_chip_pm_put(struct irq_data *data);
498#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 503#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
499extern void irq_chip_enable_parent(struct irq_data *data); 504extern void irq_chip_enable_parent(struct irq_data *data);
500extern void irq_chip_disable_parent(struct irq_data *data); 505extern void irq_chip_disable_parent(struct irq_data *data);
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index dc493e0f0ff7..107eed475b94 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -204,6 +204,7 @@
204#define GITS_BASER_NR_REGS 8 204#define GITS_BASER_NR_REGS 8
205 205
206#define GITS_BASER_VALID (1UL << 63) 206#define GITS_BASER_VALID (1UL << 63)
207#define GITS_BASER_INDIRECT (1UL << 62)
207#define GITS_BASER_nCnB (0UL << 59) 208#define GITS_BASER_nCnB (0UL << 59)
208#define GITS_BASER_nC (1UL << 59) 209#define GITS_BASER_nC (1UL << 59)
209#define GITS_BASER_RaWt (2UL << 59) 210#define GITS_BASER_RaWt (2UL << 59)
@@ -228,6 +229,7 @@
228#define GITS_BASER_PAGE_SIZE_64K (2UL << GITS_BASER_PAGE_SIZE_SHIFT) 229#define GITS_BASER_PAGE_SIZE_64K (2UL << GITS_BASER_PAGE_SIZE_SHIFT)
229#define GITS_BASER_PAGE_SIZE_MASK (3UL << GITS_BASER_PAGE_SIZE_SHIFT) 230#define GITS_BASER_PAGE_SIZE_MASK (3UL << GITS_BASER_PAGE_SIZE_SHIFT)
230#define GITS_BASER_PAGES_MAX 256 231#define GITS_BASER_PAGES_MAX 256
232#define GITS_BASER_PAGES_SHIFT (0)
231 233
232#define GITS_BASER_TYPE_NONE 0 234#define GITS_BASER_TYPE_NONE 0
233#define GITS_BASER_TYPE_DEVICE 1 235#define GITS_BASER_TYPE_DEVICE 1
@@ -238,6 +240,8 @@
238#define GITS_BASER_TYPE_RESERVED6 6 240#define GITS_BASER_TYPE_RESERVED6 6
239#define GITS_BASER_TYPE_RESERVED7 7 241#define GITS_BASER_TYPE_RESERVED7 7
240 242
243#define GITS_LVL1_ENTRY_SIZE (8UL)
244
241/* 245/*
242 * ITS commands 246 * ITS commands
243 */ 247 */
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
index fd051855539b..eafc965b3eb8 100644
--- a/include/linux/irqchip/arm-gic.h
+++ b/include/linux/irqchip/arm-gic.h
@@ -101,9 +101,14 @@
101#include <linux/irqdomain.h> 101#include <linux/irqdomain.h>
102 102
103struct device_node; 103struct device_node;
104struct gic_chip_data;
104 105
105void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); 106void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
106int gic_cpu_if_down(unsigned int gic_nr); 107int gic_cpu_if_down(unsigned int gic_nr);
108void gic_cpu_save(struct gic_chip_data *gic);
109void gic_cpu_restore(struct gic_chip_data *gic);
110void gic_dist_save(struct gic_chip_data *gic);
111void gic_dist_restore(struct gic_chip_data *gic);
107 112
108/* 113/*
109 * Subdrivers that need some preparatory work can initialize their 114 * Subdrivers that need some preparatory work can initialize their
@@ -112,6 +117,12 @@ int gic_cpu_if_down(unsigned int gic_nr);
112int gic_of_init(struct device_node *node, struct device_node *parent); 117int gic_of_init(struct device_node *node, struct device_node *parent);
113 118
114/* 119/*
120 * Initialises and registers a non-root or child GIC chip. Memory for
121 * the gic_chip_data structure is dynamically allocated.
122 */
123int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq);
124
125/*
115 * Legacy platforms not converted to DT yet must use this to init 126 * Legacy platforms not converted to DT yet must use this to init
116 * their GIC 127 * their GIC
117 */ 128 */
diff --git a/include/linux/irqdomain.h b/include/linux/irqdomain.h
index 1aee0fbe900e..ffb84604c1de 100644
--- a/include/linux/irqdomain.h
+++ b/include/linux/irqdomain.h
@@ -455,6 +455,9 @@ static inline int irq_domain_alloc_irqs(struct irq_domain *domain,
455 return -1; 455 return -1;
456} 456}
457 457
458static inline void irq_domain_free_irqs(unsigned int virq,
459 unsigned int nr_irqs) { }
460
458static inline bool irq_domain_is_hierarchy(struct irq_domain *domain) 461static inline bool irq_domain_is_hierarchy(struct irq_domain *domain)
459{ 462{
460 return false; 463 return false;
diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c
index 2f9f2b0e79f2..b4c1bc7c9ca2 100644
--- a/kernel/irq/chip.c
+++ b/kernel/irq/chip.c
@@ -426,6 +426,49 @@ out_unlock:
426} 426}
427EXPORT_SYMBOL_GPL(handle_simple_irq); 427EXPORT_SYMBOL_GPL(handle_simple_irq);
428 428
429/**
430 * handle_untracked_irq - Simple and software-decoded IRQs.
431 * @desc: the interrupt description structure for this irq
432 *
433 * Untracked interrupts are sent from a demultiplexing interrupt
434 * handler when the demultiplexer does not know which device it its
435 * multiplexed irq domain generated the interrupt. IRQ's handled
436 * through here are not subjected to stats tracking, randomness, or
437 * spurious interrupt detection.
438 *
439 * Note: Like handle_simple_irq, the caller is expected to handle
440 * the ack, clear, mask and unmask issues if necessary.
441 */
442void handle_untracked_irq(struct irq_desc *desc)
443{
444 unsigned int flags = 0;
445
446 raw_spin_lock(&desc->lock);
447
448 if (!irq_may_run(desc))
449 goto out_unlock;
450
451 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
452
453 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
454 desc->istate |= IRQS_PENDING;
455 goto out_unlock;
456 }
457
458 desc->istate &= ~IRQS_PENDING;
459 irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS);
460 raw_spin_unlock(&desc->lock);
461
462 __handle_irq_event_percpu(desc, &flags);
463
464 raw_spin_lock(&desc->lock);
465 irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS);
466
467out_unlock:
468 raw_spin_unlock(&desc->lock);
469}
470EXPORT_SYMBOL_GPL(handle_untracked_irq);
471
429/* 472/*
430 * Called unconditionally from handle_level_irq() and only for oneshot 473 * Called unconditionally from handle_level_irq() and only for oneshot
431 * interrupts from handle_fasteoi_irq() 474 * interrupts from handle_fasteoi_irq()
@@ -1093,3 +1136,43 @@ int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
1093 1136
1094 return 0; 1137 return 0;
1095} 1138}
1139
1140/**
1141 * irq_chip_pm_get - Enable power for an IRQ chip
1142 * @data: Pointer to interrupt specific data
1143 *
1144 * Enable the power to the IRQ chip referenced by the interrupt data
1145 * structure.
1146 */
1147int irq_chip_pm_get(struct irq_data *data)
1148{
1149 int retval;
1150
1151 if (IS_ENABLED(CONFIG_PM) && data->chip->parent_device) {
1152 retval = pm_runtime_get_sync(data->chip->parent_device);
1153 if (retval < 0) {
1154 pm_runtime_put_noidle(data->chip->parent_device);
1155 return retval;
1156 }
1157 }
1158
1159 return 0;
1160}
1161
1162/**
1163 * irq_chip_pm_put - Disable power for an IRQ chip
1164 * @data: Pointer to interrupt specific data
1165 *
1166 * Disable the power to the IRQ chip referenced by the interrupt data
1167 * structure, belongs. Note that power will only be disabled, once this
1168 * function has been called for all IRQs that have called irq_chip_pm_get().
1169 */
1170int irq_chip_pm_put(struct irq_data *data)
1171{
1172 int retval = 0;
1173
1174 if (IS_ENABLED(CONFIG_PM) && data->chip->parent_device)
1175 retval = pm_runtime_put(data->chip->parent_device);
1176
1177 return (retval < 0) ? retval : 0;
1178}
diff --git a/kernel/irq/handle.c b/kernel/irq/handle.c
index a15b5485b446..d3f24905852c 100644
--- a/kernel/irq/handle.c
+++ b/kernel/irq/handle.c
@@ -132,10 +132,10 @@ void __irq_wake_thread(struct irq_desc *desc, struct irqaction *action)
132 wake_up_process(action->thread); 132 wake_up_process(action->thread);
133} 133}
134 134
135irqreturn_t handle_irq_event_percpu(struct irq_desc *desc) 135irqreturn_t __handle_irq_event_percpu(struct irq_desc *desc, unsigned int *flags)
136{ 136{
137 irqreturn_t retval = IRQ_NONE; 137 irqreturn_t retval = IRQ_NONE;
138 unsigned int flags = 0, irq = desc->irq_data.irq; 138 unsigned int irq = desc->irq_data.irq;
139 struct irqaction *action; 139 struct irqaction *action;
140 140
141 for_each_action_of_desc(desc, action) { 141 for_each_action_of_desc(desc, action) {
@@ -164,7 +164,7 @@ irqreturn_t handle_irq_event_percpu(struct irq_desc *desc)
164 164
165 /* Fall through to add to randomness */ 165 /* Fall through to add to randomness */
166 case IRQ_HANDLED: 166 case IRQ_HANDLED:
167 flags |= action->flags; 167 *flags |= action->flags;
168 break; 168 break;
169 169
170 default: 170 default:
@@ -174,7 +174,17 @@ irqreturn_t handle_irq_event_percpu(struct irq_desc *desc)
174 retval |= res; 174 retval |= res;
175 } 175 }
176 176
177 add_interrupt_randomness(irq, flags); 177 return retval;
178}
179
180irqreturn_t handle_irq_event_percpu(struct irq_desc *desc)
181{
182 irqreturn_t retval;
183 unsigned int flags = 0;
184
185 retval = __handle_irq_event_percpu(desc, &flags);
186
187 add_interrupt_randomness(desc->irq_data.irq, flags);
178 188
179 if (!noirqdebug) 189 if (!noirqdebug)
180 note_interrupt(desc, retval); 190 note_interrupt(desc, retval);
diff --git a/kernel/irq/internals.h b/kernel/irq/internals.h
index b15aa3b617a2..bc226e783bd2 100644
--- a/kernel/irq/internals.h
+++ b/kernel/irq/internals.h
@@ -7,6 +7,7 @@
7 */ 7 */
8#include <linux/irqdesc.h> 8#include <linux/irqdesc.h>
9#include <linux/kernel_stat.h> 9#include <linux/kernel_stat.h>
10#include <linux/pm_runtime.h>
10 11
11#ifdef CONFIG_SPARSE_IRQ 12#ifdef CONFIG_SPARSE_IRQ
12# define IRQ_BITMAP_BITS (NR_IRQS + 8196) 13# define IRQ_BITMAP_BITS (NR_IRQS + 8196)
@@ -83,6 +84,7 @@ extern void irq_mark_irq(unsigned int irq);
83 84
84extern void init_kstat_irqs(struct irq_desc *desc, int node, int nr); 85extern void init_kstat_irqs(struct irq_desc *desc, int node, int nr);
85 86
87irqreturn_t __handle_irq_event_percpu(struct irq_desc *desc, unsigned int *flags);
86irqreturn_t handle_irq_event_percpu(struct irq_desc *desc); 88irqreturn_t handle_irq_event_percpu(struct irq_desc *desc);
87irqreturn_t handle_irq_event(struct irq_desc *desc); 89irqreturn_t handle_irq_event(struct irq_desc *desc);
88 90
diff --git a/kernel/irq/irqdomain.c b/kernel/irq/irqdomain.c
index 79459b732dc9..a82853739694 100644
--- a/kernel/irq/irqdomain.c
+++ b/kernel/irq/irqdomain.c
@@ -567,6 +567,7 @@ static void of_phandle_args_to_fwspec(struct of_phandle_args *irq_data,
567unsigned int irq_create_fwspec_mapping(struct irq_fwspec *fwspec) 567unsigned int irq_create_fwspec_mapping(struct irq_fwspec *fwspec)
568{ 568{
569 struct irq_domain *domain; 569 struct irq_domain *domain;
570 struct irq_data *irq_data;
570 irq_hw_number_t hwirq; 571 irq_hw_number_t hwirq;
571 unsigned int type = IRQ_TYPE_NONE; 572 unsigned int type = IRQ_TYPE_NONE;
572 int virq; 573 int virq;
@@ -588,15 +589,46 @@ unsigned int irq_create_fwspec_mapping(struct irq_fwspec *fwspec)
588 if (irq_domain_translate(domain, fwspec, &hwirq, &type)) 589 if (irq_domain_translate(domain, fwspec, &hwirq, &type))
589 return 0; 590 return 0;
590 591
591 if (irq_domain_is_hierarchy(domain)) { 592 /*
593 * WARN if the irqchip returns a type with bits
594 * outside the sense mask set and clear these bits.
595 */
596 if (WARN_ON(type & ~IRQ_TYPE_SENSE_MASK))
597 type &= IRQ_TYPE_SENSE_MASK;
598
599 /*
600 * If we've already configured this interrupt,
601 * don't do it again, or hell will break loose.
602 */
603 virq = irq_find_mapping(domain, hwirq);
604 if (virq) {
592 /* 605 /*
593 * If we've already configured this interrupt, 606 * If the trigger type is not specified or matches the
594 * don't do it again, or hell will break loose. 607 * current trigger type then we are done so return the
608 * interrupt number.
595 */ 609 */
596 virq = irq_find_mapping(domain, hwirq); 610 if (type == IRQ_TYPE_NONE || type == irq_get_trigger_type(virq))
597 if (virq) 611 return virq;
612
613 /*
614 * If the trigger type has not been set yet, then set
615 * it now and return the interrupt number.
616 */
617 if (irq_get_trigger_type(virq) == IRQ_TYPE_NONE) {
618 irq_data = irq_get_irq_data(virq);
619 if (!irq_data)
620 return 0;
621
622 irqd_set_trigger_type(irq_data, type);
598 return virq; 623 return virq;
624 }
625
626 pr_warn("type mismatch, failed to map hwirq-%lu for %s!\n",
627 hwirq, of_node_full_name(to_of_node(fwspec->fwnode)));
628 return 0;
629 }
599 630
631 if (irq_domain_is_hierarchy(domain)) {
600 virq = irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, fwspec); 632 virq = irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, fwspec);
601 if (virq <= 0) 633 if (virq <= 0)
602 return 0; 634 return 0;
@@ -607,10 +639,18 @@ unsigned int irq_create_fwspec_mapping(struct irq_fwspec *fwspec)
607 return virq; 639 return virq;
608 } 640 }
609 641
610 /* Set type if specified and different than the current one */ 642 irq_data = irq_get_irq_data(virq);
611 if (type != IRQ_TYPE_NONE && 643 if (!irq_data) {
612 type != irq_get_trigger_type(virq)) 644 if (irq_domain_is_hierarchy(domain))
613 irq_set_irq_type(virq, type); 645 irq_domain_free_irqs(virq, 1);
646 else
647 irq_dispose_mapping(virq);
648 return 0;
649 }
650
651 /* Store trigger type */
652 irqd_set_trigger_type(irq_data, type);
653
614 return virq; 654 return virq;
615} 655}
616EXPORT_SYMBOL_GPL(irq_create_fwspec_mapping); 656EXPORT_SYMBOL_GPL(irq_create_fwspec_mapping);
@@ -640,8 +680,12 @@ void irq_dispose_mapping(unsigned int virq)
640 if (WARN_ON(domain == NULL)) 680 if (WARN_ON(domain == NULL))
641 return; 681 return;
642 682
643 irq_domain_disassociate(domain, virq); 683 if (irq_domain_is_hierarchy(domain)) {
644 irq_free_desc(virq); 684 irq_domain_free_irqs(virq, 1);
685 } else {
686 irq_domain_disassociate(domain, virq);
687 irq_free_desc(virq);
688 }
645} 689}
646EXPORT_SYMBOL_GPL(irq_dispose_mapping); 690EXPORT_SYMBOL_GPL(irq_dispose_mapping);
647 691
diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c
index ad0aac6d1248..73a2b786b5e9 100644
--- a/kernel/irq/manage.c
+++ b/kernel/irq/manage.c
@@ -1133,6 +1133,13 @@ __setup_irq(unsigned int irq, struct irq_desc *desc, struct irqaction *new)
1133 new->irq = irq; 1133 new->irq = irq;
1134 1134
1135 /* 1135 /*
1136 * If the trigger type is not specified by the caller,
1137 * then use the default for this interrupt.
1138 */
1139 if (!(new->flags & IRQF_TRIGGER_MASK))
1140 new->flags |= irqd_get_trigger_type(&desc->irq_data);
1141
1142 /*
1136 * Check whether the interrupt nests into another interrupt 1143 * Check whether the interrupt nests into another interrupt
1137 * thread. 1144 * thread.
1138 */ 1145 */
@@ -1425,10 +1432,18 @@ int setup_irq(unsigned int irq, struct irqaction *act)
1425 1432
1426 if (!desc || WARN_ON(irq_settings_is_per_cpu_devid(desc))) 1433 if (!desc || WARN_ON(irq_settings_is_per_cpu_devid(desc)))
1427 return -EINVAL; 1434 return -EINVAL;
1435
1436 retval = irq_chip_pm_get(&desc->irq_data);
1437 if (retval < 0)
1438 return retval;
1439
1428 chip_bus_lock(desc); 1440 chip_bus_lock(desc);
1429 retval = __setup_irq(irq, desc, act); 1441 retval = __setup_irq(irq, desc, act);
1430 chip_bus_sync_unlock(desc); 1442 chip_bus_sync_unlock(desc);
1431 1443
1444 if (retval)
1445 irq_chip_pm_put(&desc->irq_data);
1446
1432 return retval; 1447 return retval;
1433} 1448}
1434EXPORT_SYMBOL_GPL(setup_irq); 1449EXPORT_SYMBOL_GPL(setup_irq);
@@ -1522,6 +1537,7 @@ static struct irqaction *__free_irq(unsigned int irq, void *dev_id)
1522 } 1537 }
1523 } 1538 }
1524 1539
1540 irq_chip_pm_put(&desc->irq_data);
1525 module_put(desc->owner); 1541 module_put(desc->owner);
1526 kfree(action->secondary); 1542 kfree(action->secondary);
1527 return action; 1543 return action;
@@ -1664,11 +1680,16 @@ int request_threaded_irq(unsigned int irq, irq_handler_t handler,
1664 action->name = devname; 1680 action->name = devname;
1665 action->dev_id = dev_id; 1681 action->dev_id = dev_id;
1666 1682
1683 retval = irq_chip_pm_get(&desc->irq_data);
1684 if (retval < 0)
1685 return retval;
1686
1667 chip_bus_lock(desc); 1687 chip_bus_lock(desc);
1668 retval = __setup_irq(irq, desc, action); 1688 retval = __setup_irq(irq, desc, action);
1669 chip_bus_sync_unlock(desc); 1689 chip_bus_sync_unlock(desc);
1670 1690
1671 if (retval) { 1691 if (retval) {
1692 irq_chip_pm_put(&desc->irq_data);
1672 kfree(action->secondary); 1693 kfree(action->secondary);
1673 kfree(action); 1694 kfree(action);
1674 } 1695 }
@@ -1746,7 +1767,14 @@ void enable_percpu_irq(unsigned int irq, unsigned int type)
1746 if (!desc) 1767 if (!desc)
1747 return; 1768 return;
1748 1769
1770 /*
1771 * If the trigger type is not specified by the caller, then
1772 * use the default for this interrupt.
1773 */
1749 type &= IRQ_TYPE_SENSE_MASK; 1774 type &= IRQ_TYPE_SENSE_MASK;
1775 if (type == IRQ_TYPE_NONE)
1776 type = irqd_get_trigger_type(&desc->irq_data);
1777
1750 if (type != IRQ_TYPE_NONE) { 1778 if (type != IRQ_TYPE_NONE) {
1751 int ret; 1779 int ret;
1752 1780
@@ -1838,6 +1866,7 @@ static struct irqaction *__free_percpu_irq(unsigned int irq, void __percpu *dev_
1838 1866
1839 unregister_handler_proc(irq, action); 1867 unregister_handler_proc(irq, action);
1840 1868
1869 irq_chip_pm_put(&desc->irq_data);
1841 module_put(desc->owner); 1870 module_put(desc->owner);
1842 return action; 1871 return action;
1843 1872
@@ -1900,10 +1929,18 @@ int setup_percpu_irq(unsigned int irq, struct irqaction *act)
1900 1929
1901 if (!desc || !irq_settings_is_per_cpu_devid(desc)) 1930 if (!desc || !irq_settings_is_per_cpu_devid(desc))
1902 return -EINVAL; 1931 return -EINVAL;
1932
1933 retval = irq_chip_pm_get(&desc->irq_data);
1934 if (retval < 0)
1935 return retval;
1936
1903 chip_bus_lock(desc); 1937 chip_bus_lock(desc);
1904 retval = __setup_irq(irq, desc, act); 1938 retval = __setup_irq(irq, desc, act);
1905 chip_bus_sync_unlock(desc); 1939 chip_bus_sync_unlock(desc);
1906 1940
1941 if (retval)
1942 irq_chip_pm_put(&desc->irq_data);
1943
1907 return retval; 1944 return retval;
1908} 1945}
1909 1946
@@ -1947,12 +1984,18 @@ int request_percpu_irq(unsigned int irq, irq_handler_t handler,
1947 action->name = devname; 1984 action->name = devname;
1948 action->percpu_dev_id = dev_id; 1985 action->percpu_dev_id = dev_id;
1949 1986
1987 retval = irq_chip_pm_get(&desc->irq_data);
1988 if (retval < 0)
1989 return retval;
1990
1950 chip_bus_lock(desc); 1991 chip_bus_lock(desc);
1951 retval = __setup_irq(irq, desc, action); 1992 retval = __setup_irq(irq, desc, action);
1952 chip_bus_sync_unlock(desc); 1993 chip_bus_sync_unlock(desc);
1953 1994
1954 if (retval) 1995 if (retval) {
1996 irq_chip_pm_put(&desc->irq_data);
1955 kfree(action); 1997 kfree(action);
1998 }
1956 1999
1957 return retval; 2000 return retval;
1958} 2001}
diff --git a/kernel/irq/proc.c b/kernel/irq/proc.c
index 40bdcdc1f700..feaa813b84a9 100644
--- a/kernel/irq/proc.c
+++ b/kernel/irq/proc.c
@@ -311,7 +311,6 @@ void register_handler_proc(unsigned int irq, struct irqaction *action)
311 !name_unique(irq, action)) 311 !name_unique(irq, action))
312 return; 312 return;
313 313
314 memset(name, 0, MAX_NAMELEN);
315 snprintf(name, MAX_NAMELEN, "%s", action->name); 314 snprintf(name, MAX_NAMELEN, "%s", action->name);
316 315
317 /* create /proc/irq/1234/handler/ */ 316 /* create /proc/irq/1234/handler/ */
@@ -340,7 +339,6 @@ void register_irq_proc(unsigned int irq, struct irq_desc *desc)
340 if (desc->dir) 339 if (desc->dir)
341 goto out_unlock; 340 goto out_unlock;
342 341
343 memset(name, 0, MAX_NAMELEN);
344 sprintf(name, "%d", irq); 342 sprintf(name, "%d", irq);
345 343
346 /* create /proc/irq/1234 */ 344 /* create /proc/irq/1234 */
@@ -386,7 +384,6 @@ void unregister_irq_proc(unsigned int irq, struct irq_desc *desc)
386#endif 384#endif
387 remove_proc_entry("spurious", desc->dir); 385 remove_proc_entry("spurious", desc->dir);
388 386
389 memset(name, 0, MAX_NAMELEN);
390 sprintf(name, "%u", irq); 387 sprintf(name, "%u", irq);
391 remove_proc_entry(name, root_irq_dir); 388 remove_proc_entry(name, root_irq_dir);
392} 389}
@@ -421,12 +418,8 @@ void init_irq_proc(void)
421 /* 418 /*
422 * Create entries for all existing IRQs. 419 * Create entries for all existing IRQs.
423 */ 420 */
424 for_each_irq_desc(irq, desc) { 421 for_each_irq_desc(irq, desc)
425 if (!desc)
426 continue;
427
428 register_irq_proc(irq, desc); 422 register_irq_proc(irq, desc);
429 }
430} 423}
431 424
432#ifdef CONFIG_GENERIC_IRQ_SHOW 425#ifdef CONFIG_GENERIC_IRQ_SHOW
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-15 17:23:43 -0400