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-rw-r--r--Documentation/devicetree/bindings/spi/spi-lantiq-ssc.txt29
-rw-r--r--Documentation/devicetree/bindings/spi/spi-rockchip.txt7
-rw-r--r--Documentation/spi/ep93xx_spi105
-rw-r--r--arch/arm/mach-ep93xx/edb93xx.c31
-rw-r--r--arch/arm/mach-ep93xx/simone.c63
-rw-r--r--arch/arm/mach-ep93xx/vision_ep9307.c88
-rw-r--r--drivers/spi/Kconfig13
-rw-r--r--drivers/spi/Makefile1
-rw-r--r--drivers/spi/spi-armada-3700.c14
-rw-r--r--drivers/spi/spi-ath79.c23
-rw-r--r--drivers/spi/spi-bcm-qspi.c194
-rw-r--r--drivers/spi/spi-bcm53xx.c18
-rw-r--r--drivers/spi/spi-dw.c8
-rw-r--r--drivers/spi/spi-dw.h1
-rw-r--r--drivers/spi/spi-ep93xx.c139
-rw-r--r--drivers/spi/spi-fsl-lpspi.c8
-rw-r--r--drivers/spi/spi-fsl-spi.c17
-rw-r--r--drivers/spi/spi-imx.c16
-rw-r--r--drivers/spi/spi-lantiq-ssc.c983
-rw-r--r--drivers/spi/spi-mpc52xx.c12
-rw-r--r--drivers/spi/spi-mt65xx.c37
-rw-r--r--drivers/spi/spi-ppc4xx.c7
-rw-r--r--drivers/spi/spi-pxa2xx-pci.c32
-rw-r--r--drivers/spi/spi-pxa2xx.c36
-rw-r--r--drivers/spi/spi-rockchip.c5
-rw-r--r--drivers/spi/spi-rspi.c9
-rw-r--r--drivers/spi/spi-s3c64xx.c59
-rw-r--r--drivers/spi/spi-sh-msiof.c4
-rw-r--r--drivers/spi/spi-ti-qspi.c18
-rw-r--r--drivers/spi/spi-topcliff-pch.c31
-rw-r--r--drivers/spi/spi.c78
-rw-r--r--include/linux/platform_data/spi-ep93xx.h17
-rw-r--r--include/linux/pxa2xx_ssp.h14
33 files changed, 1502 insertions, 615 deletions
diff --git a/Documentation/devicetree/bindings/spi/spi-lantiq-ssc.txt b/Documentation/devicetree/bindings/spi/spi-lantiq-ssc.txt
new file mode 100644
index 000000000000..6069b95a883d
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-lantiq-ssc.txt
@@ -0,0 +1,29 @@
1Lantiq Synchronous Serial Controller (SSC) SPI master driver
2
3Required properties:
4- compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi"
5- #address-cells: see spi-bus.txt
6- #size-cells: see spi-bus.txt
7- reg: address and length of the spi master registers
8- interrupts: should contain the "spi_rx", "spi_tx" and "spi_err" interrupt.
9
10
11Optional properties:
12- clocks: spi clock phandle
13- num-cs: see spi-bus.txt, set to 8 if unset
14- base-cs: the number of the first chip select, set to 1 if unset.
15
16Example:
17
18
19spi: spi@E100800 {
20 compatible = "lantiq,xrx200-spi", "lantiq,xrx100-spi";
21 reg = <0xE100800 0x100>;
22 interrupt-parent = <&icu0>;
23 interrupts = <22 23 24>;
24 interrupt-names = "spi_rx", "spi_tx", "spi_err";
25 #address-cells = <1>;
26 #size-cells = <1>;
27 num-cs = <6>;
28 base-cs = <1>;
29};
diff --git a/Documentation/devicetree/bindings/spi/spi-rockchip.txt b/Documentation/devicetree/bindings/spi/spi-rockchip.txt
index d2ca153614f9..83da4931d832 100644
--- a/Documentation/devicetree/bindings/spi/spi-rockchip.txt
+++ b/Documentation/devicetree/bindings/spi/spi-rockchip.txt
@@ -31,6 +31,10 @@ Optional Properties:
31- rx-sample-delay-ns: nanoseconds to delay after the SCLK edge before sampling 31- rx-sample-delay-ns: nanoseconds to delay after the SCLK edge before sampling
32 Rx data (may need to be fine tuned for high capacitance lines). 32 Rx data (may need to be fine tuned for high capacitance lines).
33 No delay (0) by default. 33 No delay (0) by default.
34- pinctrl-names: Names for the pin configuration(s); may be "default" or
35 "sleep", where the "sleep" configuration may describe the state
36 the pins should be in during system suspend. See also
37 pinctrl/pinctrl-bindings.txt.
34 38
35 39
36Example: 40Example:
@@ -46,4 +50,7 @@ Example:
46 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 50 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
47 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 51 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
48 clock-names = "spiclk", "apb_pclk"; 52 clock-names = "spiclk", "apb_pclk";
53 pinctrl-0 = <&spi1_pins>;
54 pinctrl-1 = <&spi1_sleep>;
55 pinctrl-names = "default", "sleep";
49 }; 56 };
diff --git a/Documentation/spi/ep93xx_spi b/Documentation/spi/ep93xx_spi
deleted file mode 100644
index 832ddce6e5fb..000000000000
--- a/Documentation/spi/ep93xx_spi
+++ /dev/null
@@ -1,105 +0,0 @@
1Cirrus EP93xx SPI controller driver HOWTO
2=========================================
3
4ep93xx_spi driver brings SPI master support for EP93xx SPI controller. Chip
5selects are implemented with GPIO lines.
6
7NOTE: If possible, don't use SFRMOUT (SFRM1) signal as a chip select. It will
8not work correctly (it cannot be controlled by software). Use GPIO lines
9instead.
10
11Sample configuration
12====================
13
14Typically driver configuration is done in platform board files (the files under
15arch/arm/mach-ep93xx/*.c). In this example we configure MMC over SPI through
16this driver on TS-7260 board. You can adapt the code to suit your needs.
17
18This example uses EGPIO9 as SD/MMC card chip select (this is wired in DIO1
19header on the board).
20
21You need to select CONFIG_MMC_SPI to use mmc_spi driver.
22
23arch/arm/mach-ep93xx/ts72xx.c:
24
25...
26#include <linux/gpio.h>
27#include <linux/spi/spi.h>
28
29#include <linux/platform_data/spi-ep93xx.h>
30
31/* this is our GPIO line used for chip select */
32#define MMC_CHIP_SELECT_GPIO EP93XX_GPIO_LINE_EGPIO9
33
34static int ts72xx_mmc_spi_setup(struct spi_device *spi)
35{
36 int err;
37
38 err = gpio_request(MMC_CHIP_SELECT_GPIO, spi->modalias);
39 if (err)
40 return err;
41
42 gpio_direction_output(MMC_CHIP_SELECT_GPIO, 1);
43
44 return 0;
45}
46
47static void ts72xx_mmc_spi_cleanup(struct spi_device *spi)
48{
49 gpio_set_value(MMC_CHIP_SELECT_GPIO, 1);
50 gpio_direction_input(MMC_CHIP_SELECT_GPIO);
51 gpio_free(MMC_CHIP_SELECT_GPIO);
52}
53
54static void ts72xx_mmc_spi_cs_control(struct spi_device *spi, int value)
55{
56 gpio_set_value(MMC_CHIP_SELECT_GPIO, value);
57}
58
59static struct ep93xx_spi_chip_ops ts72xx_mmc_spi_ops = {
60 .setup = ts72xx_mmc_spi_setup,
61 .cleanup = ts72xx_mmc_spi_cleanup,
62 .cs_control = ts72xx_mmc_spi_cs_control,
63};
64
65static struct spi_board_info ts72xx_spi_devices[] __initdata = {
66 {
67 .modalias = "mmc_spi",
68 .controller_data = &ts72xx_mmc_spi_ops,
69 /*
70 * We use 10 MHz even though the maximum is 7.4 MHz. The driver
71 * will limit it automatically to max. frequency.
72 */
73 .max_speed_hz = 10 * 1000 * 1000,
74 .bus_num = 0,
75 .chip_select = 0,
76 .mode = SPI_MODE_0,
77 },
78};
79
80static struct ep93xx_spi_info ts72xx_spi_info = {
81 .num_chipselect = ARRAY_SIZE(ts72xx_spi_devices),
82};
83
84static void __init ts72xx_init_machine(void)
85{
86 ...
87 ep93xx_register_spi(&ts72xx_spi_info, ts72xx_spi_devices,
88 ARRAY_SIZE(ts72xx_spi_devices));
89}
90
91The driver can use DMA for the transfers also. In this case ts72xx_spi_info
92becomes:
93
94static struct ep93xx_spi_info ts72xx_spi_info = {
95 .num_chipselect = ARRAY_SIZE(ts72xx_spi_devices),
96 .use_dma = true;
97};
98
99Note that CONFIG_EP93XX_DMA should be enabled as well.
100
101Thanks to
102=========
103Martin Guy, H. Hartley Sweeten and others who helped me during development of
104the driver. Simplemachines.it donated me a Sim.One board which I used testing
105the driver on EP9307.
diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c
index ad92d9f7e4df..0ac176386789 100644
--- a/arch/arm/mach-ep93xx/edb93xx.c
+++ b/arch/arm/mach-ep93xx/edb93xx.c
@@ -27,7 +27,6 @@
27#include <linux/kernel.h> 27#include <linux/kernel.h>
28#include <linux/init.h> 28#include <linux/init.h>
29#include <linux/platform_device.h> 29#include <linux/platform_device.h>
30#include <linux/gpio.h>
31#include <linux/i2c.h> 30#include <linux/i2c.h>
32#include <linux/i2c-gpio.h> 31#include <linux/i2c-gpio.h>
33#include <linux/spi/spi.h> 32#include <linux/spi/spi.h>
@@ -106,33 +105,10 @@ static struct cs4271_platform_data edb93xx_cs4271_data = {
106 .gpio_nreset = -EINVAL, /* filled in later */ 105 .gpio_nreset = -EINVAL, /* filled in later */
107}; 106};
108 107
109static int edb93xx_cs4271_hw_setup(struct spi_device *spi)
110{
111 return gpio_request_one(EP93XX_GPIO_LINE_EGPIO6,
112 GPIOF_OUT_INIT_HIGH, spi->modalias);
113}
114
115static void edb93xx_cs4271_hw_cleanup(struct spi_device *spi)
116{
117 gpio_free(EP93XX_GPIO_LINE_EGPIO6);
118}
119
120static void edb93xx_cs4271_hw_cs_control(struct spi_device *spi, int value)
121{
122 gpio_set_value(EP93XX_GPIO_LINE_EGPIO6, value);
123}
124
125static struct ep93xx_spi_chip_ops edb93xx_cs4271_hw = {
126 .setup = edb93xx_cs4271_hw_setup,
127 .cleanup = edb93xx_cs4271_hw_cleanup,
128 .cs_control = edb93xx_cs4271_hw_cs_control,
129};
130
131static struct spi_board_info edb93xx_spi_board_info[] __initdata = { 108static struct spi_board_info edb93xx_spi_board_info[] __initdata = {
132 { 109 {
133 .modalias = "cs4271", 110 .modalias = "cs4271",
134 .platform_data = &edb93xx_cs4271_data, 111 .platform_data = &edb93xx_cs4271_data,
135 .controller_data = &edb93xx_cs4271_hw,
136 .max_speed_hz = 6000000, 112 .max_speed_hz = 6000000,
137 .bus_num = 0, 113 .bus_num = 0,
138 .chip_select = 0, 114 .chip_select = 0,
@@ -140,8 +116,13 @@ static struct spi_board_info edb93xx_spi_board_info[] __initdata = {
140 }, 116 },
141}; 117};
142 118
119static int edb93xx_spi_chipselects[] __initdata = {
120 EP93XX_GPIO_LINE_EGPIO6,
121};
122
143static struct ep93xx_spi_info edb93xx_spi_info __initdata = { 123static struct ep93xx_spi_info edb93xx_spi_info __initdata = {
144 .num_chipselect = ARRAY_SIZE(edb93xx_spi_board_info), 124 .chipselect = edb93xx_spi_chipselects,
125 .num_chipselect = ARRAY_SIZE(edb93xx_spi_chipselects),
145}; 126};
146 127
147static void __init edb93xx_register_spi(void) 128static void __init edb93xx_register_spi(void)
diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c
index 7bb540c421ee..c7a40f245892 100644
--- a/arch/arm/mach-ep93xx/simone.c
+++ b/arch/arm/mach-ep93xx/simone.c
@@ -49,56 +49,6 @@ static struct ep93xxfb_mach_info __initdata simone_fb_info = {
49#define MMC_CARD_DETECT_GPIO EP93XX_GPIO_LINE_EGPIO0 49#define MMC_CARD_DETECT_GPIO EP93XX_GPIO_LINE_EGPIO0
50 50
51/* 51/*
52 * Up to v1.3, the Sim.One used SFRMOUT as SD card chip select, but this goes
53 * low between multi-message command blocks. From v1.4, it uses a GPIO instead.
54 * v1.3 parts will still work, since the signal on SFRMOUT is automatic.
55 */
56#define MMC_CHIP_SELECT_GPIO EP93XX_GPIO_LINE_EGPIO1
57
58/*
59 * MMC SPI chip select GPIO handling. If you are using SFRMOUT (SFRM1) signal,
60 * you can leave these empty and pass NULL as .controller_data.
61 */
62
63static int simone_mmc_spi_setup(struct spi_device *spi)
64{
65 unsigned int gpio = MMC_CHIP_SELECT_GPIO;
66 int err;
67
68 err = gpio_request(gpio, spi->modalias);
69 if (err)
70 return err;
71
72 err = gpio_direction_output(gpio, 1);
73 if (err) {
74 gpio_free(gpio);
75 return err;
76 }
77
78 return 0;
79}
80
81static void simone_mmc_spi_cleanup(struct spi_device *spi)
82{
83 unsigned int gpio = MMC_CHIP_SELECT_GPIO;
84
85 gpio_set_value(gpio, 1);
86 gpio_direction_input(gpio);
87 gpio_free(gpio);
88}
89
90static void simone_mmc_spi_cs_control(struct spi_device *spi, int value)
91{
92 gpio_set_value(MMC_CHIP_SELECT_GPIO, value);
93}
94
95static struct ep93xx_spi_chip_ops simone_mmc_spi_ops = {
96 .setup = simone_mmc_spi_setup,
97 .cleanup = simone_mmc_spi_cleanup,
98 .cs_control = simone_mmc_spi_cs_control,
99};
100
101/*
102 * MMC card detection GPIO setup. 52 * MMC card detection GPIO setup.
103 */ 53 */
104 54
@@ -152,7 +102,6 @@ static struct mmc_spi_platform_data simone_mmc_spi_data = {
152static struct spi_board_info simone_spi_devices[] __initdata = { 102static struct spi_board_info simone_spi_devices[] __initdata = {
153 { 103 {
154 .modalias = "mmc_spi", 104 .modalias = "mmc_spi",
155 .controller_data = &simone_mmc_spi_ops,
156 .platform_data = &simone_mmc_spi_data, 105 .platform_data = &simone_mmc_spi_data,
157 /* 106 /*
158 * We use 10 MHz even though the maximum is 3.7 MHz. The driver 107 * We use 10 MHz even though the maximum is 3.7 MHz. The driver
@@ -165,8 +114,18 @@ static struct spi_board_info simone_spi_devices[] __initdata = {
165 }, 114 },
166}; 115};
167 116
117/*
118 * Up to v1.3, the Sim.One used SFRMOUT as SD card chip select, but this goes
119 * low between multi-message command blocks. From v1.4, it uses a GPIO instead.
120 * v1.3 parts will still work, since the signal on SFRMOUT is automatic.
121 */
122static int simone_spi_chipselects[] __initdata = {
123 EP93XX_GPIO_LINE_EGPIO1,
124};
125
168static struct ep93xx_spi_info simone_spi_info __initdata = { 126static struct ep93xx_spi_info simone_spi_info __initdata = {
169 .num_chipselect = ARRAY_SIZE(simone_spi_devices), 127 .chipselect = simone_spi_chipselects,
128 .num_chipselect = ARRAY_SIZE(simone_spi_chipselects),
170 .use_dma = 1, 129 .use_dma = 1,
171}; 130};
172 131
diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c b/arch/arm/mach-ep93xx/vision_ep9307.c
index 5cced5988498..1daf9441058c 100644
--- a/arch/arm/mach-ep93xx/vision_ep9307.c
+++ b/arch/arm/mach-ep93xx/vision_ep9307.c
@@ -175,33 +175,9 @@ static struct cs4271_platform_data vision_cs4271_data = {
175 .gpio_nreset = EP93XX_GPIO_LINE_H(2), 175 .gpio_nreset = EP93XX_GPIO_LINE_H(2),
176}; 176};
177 177
178static int vision_cs4271_hw_setup(struct spi_device *spi)
179{
180 return gpio_request_one(EP93XX_GPIO_LINE_EGPIO6,
181 GPIOF_OUT_INIT_HIGH, spi->modalias);
182}
183
184static void vision_cs4271_hw_cleanup(struct spi_device *spi)
185{
186 gpio_free(EP93XX_GPIO_LINE_EGPIO6);
187}
188
189static void vision_cs4271_hw_cs_control(struct spi_device *spi, int value)
190{
191 gpio_set_value(EP93XX_GPIO_LINE_EGPIO6, value);
192}
193
194static struct ep93xx_spi_chip_ops vision_cs4271_hw = {
195 .setup = vision_cs4271_hw_setup,
196 .cleanup = vision_cs4271_hw_cleanup,
197 .cs_control = vision_cs4271_hw_cs_control,
198};
199
200/************************************************************************* 178/*************************************************************************
201 * SPI Flash 179 * SPI Flash
202 *************************************************************************/ 180 *************************************************************************/
203#define VISION_SPI_FLASH_CS EP93XX_GPIO_LINE_EGPIO7
204
205static struct mtd_partition vision_spi_flash_partitions[] = { 181static struct mtd_partition vision_spi_flash_partitions[] = {
206 { 182 {
207 .name = "SPI bootstrap", 183 .name = "SPI bootstrap",
@@ -224,68 +200,20 @@ static struct flash_platform_data vision_spi_flash_data = {
224 .nr_parts = ARRAY_SIZE(vision_spi_flash_partitions), 200 .nr_parts = ARRAY_SIZE(vision_spi_flash_partitions),
225}; 201};
226 202
227static int vision_spi_flash_hw_setup(struct spi_device *spi)
228{
229 return gpio_request_one(VISION_SPI_FLASH_CS, GPIOF_INIT_HIGH,
230 spi->modalias);
231}
232
233static void vision_spi_flash_hw_cleanup(struct spi_device *spi)
234{
235 gpio_free(VISION_SPI_FLASH_CS);
236}
237
238static void vision_spi_flash_hw_cs_control(struct spi_device *spi, int value)
239{
240 gpio_set_value(VISION_SPI_FLASH_CS, value);
241}
242
243static struct ep93xx_spi_chip_ops vision_spi_flash_hw = {
244 .setup = vision_spi_flash_hw_setup,
245 .cleanup = vision_spi_flash_hw_cleanup,
246 .cs_control = vision_spi_flash_hw_cs_control,
247};
248
249/************************************************************************* 203/*************************************************************************
250 * SPI SD/MMC host 204 * SPI SD/MMC host
251 *************************************************************************/ 205 *************************************************************************/
252#define VISION_SPI_MMC_CS EP93XX_GPIO_LINE_G(2)
253#define VISION_SPI_MMC_WP EP93XX_GPIO_LINE_F(0)
254#define VISION_SPI_MMC_CD EP93XX_GPIO_LINE_EGPIO15
255
256static struct mmc_spi_platform_data vision_spi_mmc_data = { 206static struct mmc_spi_platform_data vision_spi_mmc_data = {
257 .detect_delay = 100, 207 .detect_delay = 100,
258 .powerup_msecs = 100, 208 .powerup_msecs = 100,
259 .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, 209 .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
260 .flags = MMC_SPI_USE_CD_GPIO | MMC_SPI_USE_RO_GPIO, 210 .flags = MMC_SPI_USE_CD_GPIO | MMC_SPI_USE_RO_GPIO,
261 .cd_gpio = VISION_SPI_MMC_CD, 211 .cd_gpio = EP93XX_GPIO_LINE_EGPIO15,
262 .cd_debounce = 1, 212 .cd_debounce = 1,
263 .ro_gpio = VISION_SPI_MMC_WP, 213 .ro_gpio = EP93XX_GPIO_LINE_F(0),
264 .caps2 = MMC_CAP2_RO_ACTIVE_HIGH, 214 .caps2 = MMC_CAP2_RO_ACTIVE_HIGH,
265}; 215};
266 216
267static int vision_spi_mmc_hw_setup(struct spi_device *spi)
268{
269 return gpio_request_one(VISION_SPI_MMC_CS, GPIOF_INIT_HIGH,
270 spi->modalias);
271}
272
273static void vision_spi_mmc_hw_cleanup(struct spi_device *spi)
274{
275 gpio_free(VISION_SPI_MMC_CS);
276}
277
278static void vision_spi_mmc_hw_cs_control(struct spi_device *spi, int value)
279{
280 gpio_set_value(VISION_SPI_MMC_CS, value);
281}
282
283static struct ep93xx_spi_chip_ops vision_spi_mmc_hw = {
284 .setup = vision_spi_mmc_hw_setup,
285 .cleanup = vision_spi_mmc_hw_cleanup,
286 .cs_control = vision_spi_mmc_hw_cs_control,
287};
288
289/************************************************************************* 217/*************************************************************************
290 * SPI Bus 218 * SPI Bus
291 *************************************************************************/ 219 *************************************************************************/
@@ -293,7 +221,6 @@ static struct spi_board_info vision_spi_board_info[] __initdata = {
293 { 221 {
294 .modalias = "cs4271", 222 .modalias = "cs4271",
295 .platform_data = &vision_cs4271_data, 223 .platform_data = &vision_cs4271_data,
296 .controller_data = &vision_cs4271_hw,
297 .max_speed_hz = 6000000, 224 .max_speed_hz = 6000000,
298 .bus_num = 0, 225 .bus_num = 0,
299 .chip_select = 0, 226 .chip_select = 0,
@@ -301,7 +228,6 @@ static struct spi_board_info vision_spi_board_info[] __initdata = {
301 }, { 228 }, {
302 .modalias = "sst25l", 229 .modalias = "sst25l",
303 .platform_data = &vision_spi_flash_data, 230 .platform_data = &vision_spi_flash_data,
304 .controller_data = &vision_spi_flash_hw,
305 .max_speed_hz = 20000000, 231 .max_speed_hz = 20000000,
306 .bus_num = 0, 232 .bus_num = 0,
307 .chip_select = 1, 233 .chip_select = 1,
@@ -309,7 +235,6 @@ static struct spi_board_info vision_spi_board_info[] __initdata = {
309 }, { 235 }, {
310 .modalias = "mmc_spi", 236 .modalias = "mmc_spi",
311 .platform_data = &vision_spi_mmc_data, 237 .platform_data = &vision_spi_mmc_data,
312 .controller_data = &vision_spi_mmc_hw,
313 .max_speed_hz = 20000000, 238 .max_speed_hz = 20000000,
314 .bus_num = 0, 239 .bus_num = 0,
315 .chip_select = 2, 240 .chip_select = 2,
@@ -317,8 +242,15 @@ static struct spi_board_info vision_spi_board_info[] __initdata = {
317 }, 242 },
318}; 243};
319 244
245static int vision_spi_chipselects[] __initdata = {
246 EP93XX_GPIO_LINE_EGPIO6,
247 EP93XX_GPIO_LINE_EGPIO7,
248 EP93XX_GPIO_LINE_G(2),
249};
250
320static struct ep93xx_spi_info vision_spi_master __initdata = { 251static struct ep93xx_spi_info vision_spi_master __initdata = {
321 .num_chipselect = ARRAY_SIZE(vision_spi_board_info), 252 .chipselect = vision_spi_chipselects,
253 .num_chipselect = ARRAY_SIZE(vision_spi_chipselects),
322 .use_dma = 1, 254 .use_dma = 1,
323}; 255};
324 256
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 2922a9908302..25ae7f2e44b5 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -162,7 +162,8 @@ config SPI_BCM63XX_HSSPI
162 162
163config SPI_BCM_QSPI 163config SPI_BCM_QSPI
164 tristate "Broadcom BSPI and MSPI controller support" 164 tristate "Broadcom BSPI and MSPI controller support"
165 depends on ARCH_BRCMSTB || ARCH_BCM || ARCH_BCM_IPROC || COMPILE_TEST 165 depends on ARCH_BRCMSTB || ARCH_BCM || ARCH_BCM_IPROC || \
166 BMIPS_GENERIC || COMPILE_TEST
166 default ARCH_BCM_IPROC 167 default ARCH_BCM_IPROC
167 help 168 help
168 Enables support for the Broadcom SPI flash and MSPI controller. 169 Enables support for the Broadcom SPI flash and MSPI controller.
@@ -263,7 +264,7 @@ config SPI_EP93XX
263 mode. 264 mode.
264 265
265config SPI_FALCON 266config SPI_FALCON
266 tristate "Falcon SPI controller support" 267 bool "Falcon SPI controller support"
267 depends on SOC_FALCON 268 depends on SOC_FALCON
268 help 269 help
269 The external bus unit (EBU) found on the FALC-ON SoC has SPI 270 The external bus unit (EBU) found on the FALC-ON SoC has SPI
@@ -416,6 +417,14 @@ config SPI_NUC900
416 help 417 help
417 SPI driver for Nuvoton NUC900 series ARM SoCs 418 SPI driver for Nuvoton NUC900 series ARM SoCs
418 419
420config SPI_LANTIQ_SSC
421 tristate "Lantiq SSC SPI controller"
422 depends on LANTIQ || COMPILE_TEST
423 help
424 This driver supports the Lantiq SSC SPI controller in master
425 mode. This controller is found on Intel (former Lantiq) SoCs like
426 the Danube, Falcon, xRX200, xRX300.
427
419config SPI_OC_TINY 428config SPI_OC_TINY
420 tristate "OpenCores tiny SPI" 429 tristate "OpenCores tiny SPI"
421 depends on GPIOLIB || COMPILE_TEST 430 depends on GPIOLIB || COMPILE_TEST
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 7a6b64662c82..b375a7a89216 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -49,6 +49,7 @@ obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-spi.o
49obj-$(CONFIG_SPI_GPIO) += spi-gpio.o 49obj-$(CONFIG_SPI_GPIO) += spi-gpio.o
50obj-$(CONFIG_SPI_IMG_SPFI) += spi-img-spfi.o 50obj-$(CONFIG_SPI_IMG_SPFI) += spi-img-spfi.o
51obj-$(CONFIG_SPI_IMX) += spi-imx.o 51obj-$(CONFIG_SPI_IMX) += spi-imx.o
52obj-$(CONFIG_SPI_LANTIQ_SSC) += spi-lantiq-ssc.o
52obj-$(CONFIG_SPI_JCORE) += spi-jcore.o 53obj-$(CONFIG_SPI_JCORE) += spi-jcore.o
53obj-$(CONFIG_SPI_LM70_LLP) += spi-lm70llp.o 54obj-$(CONFIG_SPI_LM70_LLP) += spi-lm70llp.o
54obj-$(CONFIG_SPI_LP8841_RTC) += spi-lp8841-rtc.o 55obj-$(CONFIG_SPI_LP8841_RTC) += spi-lp8841-rtc.o
diff --git a/drivers/spi/spi-armada-3700.c b/drivers/spi/spi-armada-3700.c
index 0314c6b9e044..6c7d7a460689 100644
--- a/drivers/spi/spi-armada-3700.c
+++ b/drivers/spi/spi-armada-3700.c
@@ -170,12 +170,12 @@ static int a3700_spi_pin_mode_set(struct a3700_spi *a3700_spi,
170 val &= ~(A3700_SPI_DATA_PIN0 | A3700_SPI_DATA_PIN1); 170 val &= ~(A3700_SPI_DATA_PIN0 | A3700_SPI_DATA_PIN1);
171 171
172 switch (pin_mode) { 172 switch (pin_mode) {
173 case 1: 173 case SPI_NBITS_SINGLE:
174 break; 174 break;
175 case 2: 175 case SPI_NBITS_DUAL:
176 val |= A3700_SPI_DATA_PIN0; 176 val |= A3700_SPI_DATA_PIN0;
177 break; 177 break;
178 case 4: 178 case SPI_NBITS_QUAD:
179 val |= A3700_SPI_DATA_PIN1; 179 val |= A3700_SPI_DATA_PIN1;
180 break; 180 break;
181 default: 181 default:
@@ -340,8 +340,7 @@ static irqreturn_t a3700_spi_interrupt(int irq, void *dev_id)
340 spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, cause); 340 spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, cause);
341 341
342 /* Wake up the transfer */ 342 /* Wake up the transfer */
343 if (a3700_spi->wait_mask & cause) 343 complete(&a3700_spi->done);
344 complete(&a3700_spi->done);
345 344
346 return IRQ_HANDLED; 345 return IRQ_HANDLED;
347} 346}
@@ -421,7 +420,7 @@ static void a3700_spi_fifo_thres_set(struct a3700_spi *a3700_spi,
421} 420}
422 421
423static void a3700_spi_transfer_setup(struct spi_device *spi, 422static void a3700_spi_transfer_setup(struct spi_device *spi,
424 struct spi_transfer *xfer) 423 struct spi_transfer *xfer)
425{ 424{
426 struct a3700_spi *a3700_spi; 425 struct a3700_spi *a3700_spi;
427 unsigned int byte_len; 426 unsigned int byte_len;
@@ -562,6 +561,7 @@ static int a3700_spi_fifo_read(struct a3700_spi *a3700_spi)
562 val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG); 561 val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG);
563 if (a3700_spi->buf_len >= 4) { 562 if (a3700_spi->buf_len >= 4) {
564 u32 data = le32_to_cpu(val); 563 u32 data = le32_to_cpu(val);
564
565 memcpy(a3700_spi->rx_buf, &data, 4); 565 memcpy(a3700_spi->rx_buf, &data, 4);
566 566
567 a3700_spi->buf_len -= 4; 567 a3700_spi->buf_len -= 4;
@@ -901,7 +901,6 @@ static int a3700_spi_remove(struct platform_device *pdev)
901 struct a3700_spi *spi = spi_master_get_devdata(master); 901 struct a3700_spi *spi = spi_master_get_devdata(master);
902 902
903 clk_unprepare(spi->clk); 903 clk_unprepare(spi->clk);
904 spi_master_put(master);
905 904
906 return 0; 905 return 0;
907} 906}
@@ -909,7 +908,6 @@ static int a3700_spi_remove(struct platform_device *pdev)
909static struct platform_driver a3700_spi_driver = { 908static struct platform_driver a3700_spi_driver = {
910 .driver = { 909 .driver = {
911 .name = DRIVER_NAME, 910 .name = DRIVER_NAME,
912 .owner = THIS_MODULE,
913 .of_match_table = of_match_ptr(a3700_spi_dt_ids), 911 .of_match_table = of_match_ptr(a3700_spi_dt_ids),
914 }, 912 },
915 .probe = a3700_spi_probe, 913 .probe = a3700_spi_probe,
diff --git a/drivers/spi/spi-ath79.c b/drivers/spi/spi-ath79.c
index f369174fbd88..b89cee11f418 100644
--- a/drivers/spi/spi-ath79.c
+++ b/drivers/spi/spi-ath79.c
@@ -78,14 +78,16 @@ static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
78 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); 78 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
79 } 79 }
80 80
81 if (spi->chip_select) { 81 if (gpio_is_valid(spi->cs_gpio)) {
82 /* SPI is normally active-low */ 82 /* SPI is normally active-low */
83 gpio_set_value(spi->cs_gpio, cs_high); 83 gpio_set_value_cansleep(spi->cs_gpio, cs_high);
84 } else { 84 } else {
85 u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select);
86
85 if (cs_high) 87 if (cs_high)
86 sp->ioc_base |= AR71XX_SPI_IOC_CS0; 88 sp->ioc_base |= cs_bit;
87 else 89 else
88 sp->ioc_base &= ~AR71XX_SPI_IOC_CS0; 90 sp->ioc_base &= ~cs_bit;
89 91
90 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); 92 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
91 } 93 }
@@ -118,11 +120,8 @@ static int ath79_spi_setup_cs(struct spi_device *spi)
118 struct ath79_spi *sp = ath79_spidev_to_sp(spi); 120 struct ath79_spi *sp = ath79_spidev_to_sp(spi);
119 int status; 121 int status;
120 122
121 if (spi->chip_select && !gpio_is_valid(spi->cs_gpio))
122 return -EINVAL;
123
124 status = 0; 123 status = 0;
125 if (spi->chip_select) { 124 if (gpio_is_valid(spi->cs_gpio)) {
126 unsigned long flags; 125 unsigned long flags;
127 126
128 flags = GPIOF_DIR_OUT; 127 flags = GPIOF_DIR_OUT;
@@ -134,10 +133,12 @@ static int ath79_spi_setup_cs(struct spi_device *spi)
134 status = gpio_request_one(spi->cs_gpio, flags, 133 status = gpio_request_one(spi->cs_gpio, flags,
135 dev_name(&spi->dev)); 134 dev_name(&spi->dev));
136 } else { 135 } else {
136 u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select);
137
137 if (spi->mode & SPI_CS_HIGH) 138 if (spi->mode & SPI_CS_HIGH)
138 sp->ioc_base &= ~AR71XX_SPI_IOC_CS0; 139 sp->ioc_base &= ~cs_bit;
139 else 140 else
140 sp->ioc_base |= AR71XX_SPI_IOC_CS0; 141 sp->ioc_base |= cs_bit;
141 142
142 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); 143 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
143 } 144 }
@@ -147,7 +148,7 @@ static int ath79_spi_setup_cs(struct spi_device *spi)
147 148
148static void ath79_spi_cleanup_cs(struct spi_device *spi) 149static void ath79_spi_cleanup_cs(struct spi_device *spi)
149{ 150{
150 if (spi->chip_select) { 151 if (gpio_is_valid(spi->cs_gpio)) {
151 gpio_free(spi->cs_gpio); 152 gpio_free(spi->cs_gpio);
152 } 153 }
153} 154}
diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c
index d7843fd8c610..b19722ba908c 100644
--- a/drivers/spi/spi-bcm-qspi.c
+++ b/drivers/spi/spi-bcm-qspi.c
@@ -89,7 +89,7 @@
89#define BSPI_BPP_MODE_SELECT_MASK BIT(8) 89#define BSPI_BPP_MODE_SELECT_MASK BIT(8)
90#define BSPI_BPP_ADDR_SELECT_MASK BIT(16) 90#define BSPI_BPP_ADDR_SELECT_MASK BIT(16)
91 91
92#define BSPI_READ_LENGTH 256 92#define BSPI_READ_LENGTH 512
93 93
94/* MSPI register offsets */ 94/* MSPI register offsets */
95#define MSPI_SPCR0_LSB 0x000 95#define MSPI_SPCR0_LSB 0x000
@@ -192,9 +192,11 @@ struct bcm_qspi_dev_id {
192 void *dev; 192 void *dev;
193}; 193};
194 194
195
195struct qspi_trans { 196struct qspi_trans {
196 struct spi_transfer *trans; 197 struct spi_transfer *trans;
197 int byte; 198 int byte;
199 bool mspi_last_trans;
198}; 200};
199 201
200struct bcm_qspi { 202struct bcm_qspi {
@@ -616,6 +618,16 @@ static int bcm_qspi_setup(struct spi_device *spi)
616 return 0; 618 return 0;
617} 619}
618 620
621static bool bcm_qspi_mspi_transfer_is_last(struct bcm_qspi *qspi,
622 struct qspi_trans *qt)
623{
624 if (qt->mspi_last_trans &&
625 spi_transfer_is_last(qspi->master, qt->trans))
626 return true;
627 else
628 return false;
629}
630
619static int update_qspi_trans_byte_count(struct bcm_qspi *qspi, 631static int update_qspi_trans_byte_count(struct bcm_qspi *qspi,
620 struct qspi_trans *qt, int flags) 632 struct qspi_trans *qt, int flags)
621{ 633{
@@ -629,7 +641,6 @@ static int update_qspi_trans_byte_count(struct bcm_qspi *qspi,
629 641
630 if (qt->byte >= qt->trans->len) { 642 if (qt->byte >= qt->trans->len) {
631 /* we're at the end of the spi_transfer */ 643 /* we're at the end of the spi_transfer */
632
633 /* in TX mode, need to pause for a delay or CS change */ 644 /* in TX mode, need to pause for a delay or CS change */
634 if (qt->trans->delay_usecs && 645 if (qt->trans->delay_usecs &&
635 (flags & TRANS_STATUS_BREAK_DELAY)) 646 (flags & TRANS_STATUS_BREAK_DELAY))
@@ -641,7 +652,7 @@ static int update_qspi_trans_byte_count(struct bcm_qspi *qspi,
641 goto done; 652 goto done;
642 653
643 dev_dbg(&qspi->pdev->dev, "advance msg exit\n"); 654 dev_dbg(&qspi->pdev->dev, "advance msg exit\n");
644 if (spi_transfer_is_last(qspi->master, qt->trans)) 655 if (bcm_qspi_mspi_transfer_is_last(qspi, qt))
645 ret = TRANS_STATUS_BREAK_EOM; 656 ret = TRANS_STATUS_BREAK_EOM;
646 else 657 else
647 ret = TRANS_STATUS_BREAK_NO_BYTES; 658 ret = TRANS_STATUS_BREAK_NO_BYTES;
@@ -813,7 +824,7 @@ static int bcm_qspi_bspi_flash_read(struct spi_device *spi,
813 struct spi_flash_read_message *msg) 824 struct spi_flash_read_message *msg)
814{ 825{
815 struct bcm_qspi *qspi = spi_master_get_devdata(spi->master); 826 struct bcm_qspi *qspi = spi_master_get_devdata(spi->master);
816 u32 addr = 0, len, len_words; 827 u32 addr = 0, len, rdlen, len_words;
817 int ret = 0; 828 int ret = 0;
818 unsigned long timeo = msecs_to_jiffies(100); 829 unsigned long timeo = msecs_to_jiffies(100);
819 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc; 830 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
@@ -826,7 +837,7 @@ static int bcm_qspi_bspi_flash_read(struct spi_device *spi,
826 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0); 837 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);
827 838
828 /* 839 /*
829 * when using flex mode mode we need to send 840 * when using flex mode we need to send
830 * the upper address byte to bspi 841 * the upper address byte to bspi
831 */ 842 */
832 if (bcm_qspi_bspi_ver_three(qspi) == false) { 843 if (bcm_qspi_bspi_ver_three(qspi) == false) {
@@ -840,48 +851,127 @@ static int bcm_qspi_bspi_flash_read(struct spi_device *spi,
840 else 851 else
841 addr = msg->from & 0x00ffffff; 852 addr = msg->from & 0x00ffffff;
842 853
843 /* set BSPI RAF buffer max read length */
844 len = msg->len;
845 if (len > BSPI_READ_LENGTH)
846 len = BSPI_READ_LENGTH;
847
848 if (bcm_qspi_bspi_ver_three(qspi) == true) 854 if (bcm_qspi_bspi_ver_three(qspi) == true)
849 addr = (addr + 0xc00000) & 0xffffff; 855 addr = (addr + 0xc00000) & 0xffffff;
850 856
851 reinit_completion(&qspi->bspi_done); 857 /*
852 bcm_qspi_enable_bspi(qspi); 858 * read into the entire buffer by breaking the reads
853 len_words = (len + 3) >> 2; 859 * into RAF buffer read lengths
854 qspi->bspi_rf_msg = msg; 860 */
855 qspi->bspi_rf_msg_status = 0; 861 len = msg->len;
856 qspi->bspi_rf_msg_idx = 0; 862 qspi->bspi_rf_msg_idx = 0;
857 qspi->bspi_rf_msg_len = len;
858 dev_dbg(&qspi->pdev->dev, "bspi xfr addr 0x%x len 0x%x", addr, len);
859 863
860 bcm_qspi_write(qspi, BSPI, BSPI_RAF_START_ADDR, addr); 864 do {
861 bcm_qspi_write(qspi, BSPI, BSPI_RAF_NUM_WORDS, len_words); 865 if (len > BSPI_READ_LENGTH)
862 bcm_qspi_write(qspi, BSPI, BSPI_RAF_WATERMARK, 0); 866 rdlen = BSPI_READ_LENGTH;
867 else
868 rdlen = len;
869
870 reinit_completion(&qspi->bspi_done);
871 bcm_qspi_enable_bspi(qspi);
872 len_words = (rdlen + 3) >> 2;
873 qspi->bspi_rf_msg = msg;
874 qspi->bspi_rf_msg_status = 0;
875 qspi->bspi_rf_msg_len = rdlen;
876 dev_dbg(&qspi->pdev->dev,
877 "bspi xfr addr 0x%x len 0x%x", addr, rdlen);
878 bcm_qspi_write(qspi, BSPI, BSPI_RAF_START_ADDR, addr);
879 bcm_qspi_write(qspi, BSPI, BSPI_RAF_NUM_WORDS, len_words);
880 bcm_qspi_write(qspi, BSPI, BSPI_RAF_WATERMARK, 0);
881 if (qspi->soc_intc) {
882 /*
883 * clear soc MSPI and BSPI interrupts and enable
884 * BSPI interrupts.
885 */
886 soc_intc->bcm_qspi_int_ack(soc_intc, MSPI_BSPI_DONE);
887 soc_intc->bcm_qspi_int_set(soc_intc, BSPI_DONE, true);
888 }
863 889
864 if (qspi->soc_intc) { 890 /* Must flush previous writes before starting BSPI operation */
865 /* 891 mb();
866 * clear soc MSPI and BSPI interrupts and enable 892 bcm_qspi_bspi_lr_start(qspi);
867 * BSPI interrupts. 893 if (!wait_for_completion_timeout(&qspi->bspi_done, timeo)) {
868 */ 894 dev_err(&qspi->pdev->dev, "timeout waiting for BSPI\n");
869 soc_intc->bcm_qspi_int_ack(soc_intc, MSPI_BSPI_DONE); 895 ret = -ETIMEDOUT;
870 soc_intc->bcm_qspi_int_set(soc_intc, BSPI_DONE, true); 896 break;
897 }
898
899 /* set msg return length */
900 msg->retlen += rdlen;
901 addr += rdlen;
902 len -= rdlen;
903 } while (len);
904
905 return ret;
906}
907
908static int bcm_qspi_transfer_one(struct spi_master *master,
909 struct spi_device *spi,
910 struct spi_transfer *trans)
911{
912 struct bcm_qspi *qspi = spi_master_get_devdata(master);
913 int slots;
914 unsigned long timeo = msecs_to_jiffies(100);
915
916 bcm_qspi_chip_select(qspi, spi->chip_select);
917 qspi->trans_pos.trans = trans;
918 qspi->trans_pos.byte = 0;
919
920 while (qspi->trans_pos.byte < trans->len) {
921 reinit_completion(&qspi->mspi_done);
922
923 slots = write_to_hw(qspi, spi);
924 if (!wait_for_completion_timeout(&qspi->mspi_done, timeo)) {
925 dev_err(&qspi->pdev->dev, "timeout waiting for MSPI\n");
926 return -ETIMEDOUT;
927 }
928
929 read_from_hw(qspi, slots);
871 } 930 }
872 931
873 /* Must flush previous writes before starting BSPI operation */ 932 return 0;
874 mb(); 933}
875 934
876 bcm_qspi_bspi_lr_start(qspi); 935static int bcm_qspi_mspi_flash_read(struct spi_device *spi,
877 if (!wait_for_completion_timeout(&qspi->bspi_done, timeo)) { 936 struct spi_flash_read_message *msg)
878 dev_err(&qspi->pdev->dev, "timeout waiting for BSPI\n"); 937{
879 ret = -ETIMEDOUT; 938 struct bcm_qspi *qspi = spi_master_get_devdata(spi->master);
880 } else { 939 struct spi_transfer t[2];
881 /* set the return length for the caller */ 940 u8 cmd[6];
882 msg->retlen = len; 941 int ret;
942
943 memset(cmd, 0, sizeof(cmd));
944 memset(t, 0, sizeof(t));
945
946 /* tx */
947 /* opcode is in cmd[0] */
948 cmd[0] = msg->read_opcode;
949 cmd[1] = msg->from >> (msg->addr_width * 8 - 8);
950 cmd[2] = msg->from >> (msg->addr_width * 8 - 16);
951 cmd[3] = msg->from >> (msg->addr_width * 8 - 24);
952 cmd[4] = msg->from >> (msg->addr_width * 8 - 32);
953 t[0].tx_buf = cmd;
954 t[0].len = msg->addr_width + msg->dummy_bytes + 1;
955 t[0].bits_per_word = spi->bits_per_word;
956 t[0].tx_nbits = msg->opcode_nbits;
957 /* lets mspi know that this is not last transfer */
958 qspi->trans_pos.mspi_last_trans = false;
959 ret = bcm_qspi_transfer_one(spi->master, spi, &t[0]);
960
961 /* rx */
962 qspi->trans_pos.mspi_last_trans = true;
963 if (!ret) {
964 /* rx */
965 t[1].rx_buf = msg->buf;
966 t[1].len = msg->len;
967 t[1].rx_nbits = msg->data_nbits;
968 t[1].bits_per_word = spi->bits_per_word;
969 ret = bcm_qspi_transfer_one(spi->master, spi, &t[1]);
883 } 970 }
884 971
972 if (!ret)
973 msg->retlen = msg->len;
974
885 return ret; 975 return ret;
886} 976}
887 977
@@ -918,8 +1008,7 @@ static int bcm_qspi_flash_read(struct spi_device *spi,
918 mspi_read = true; 1008 mspi_read = true;
919 1009
920 if (mspi_read) 1010 if (mspi_read)
921 /* this will make the m25p80 read to fallback to mspi read */ 1011 return bcm_qspi_mspi_flash_read(spi, msg);
922 return -EAGAIN;
923 1012
924 io_width = msg->data_nbits ? msg->data_nbits : SPI_NBITS_SINGLE; 1013 io_width = msg->data_nbits ? msg->data_nbits : SPI_NBITS_SINGLE;
925 addrlen = msg->addr_width; 1014 addrlen = msg->addr_width;
@@ -931,33 +1020,6 @@ static int bcm_qspi_flash_read(struct spi_device *spi,
931 return ret; 1020 return ret;
932} 1021}
933 1022
934static int bcm_qspi_transfer_one(struct spi_master *master,
935 struct spi_device *spi,
936 struct spi_transfer *trans)
937{
938 struct bcm_qspi *qspi = spi_master_get_devdata(master);
939 int slots;
940 unsigned long timeo = msecs_to_jiffies(100);
941
942 bcm_qspi_chip_select(qspi, spi->chip_select);
943 qspi->trans_pos.trans = trans;
944 qspi->trans_pos.byte = 0;
945
946 while (qspi->trans_pos.byte < trans->len) {
947 reinit_completion(&qspi->mspi_done);
948
949 slots = write_to_hw(qspi, spi);
950 if (!wait_for_completion_timeout(&qspi->mspi_done, timeo)) {
951 dev_err(&qspi->pdev->dev, "timeout waiting for MSPI\n");
952 return -ETIMEDOUT;
953 }
954
955 read_from_hw(qspi, slots);
956 }
957
958 return 0;
959}
960
961static void bcm_qspi_cleanup(struct spi_device *spi) 1023static void bcm_qspi_cleanup(struct spi_device *spi)
962{ 1024{
963 struct bcm_qspi_parms *xp = spi_get_ctldata(spi); 1025 struct bcm_qspi_parms *xp = spi_get_ctldata(spi);
@@ -1187,6 +1249,7 @@ int bcm_qspi_probe(struct platform_device *pdev,
1187 qspi->pdev = pdev; 1249 qspi->pdev = pdev;
1188 qspi->trans_pos.trans = NULL; 1250 qspi->trans_pos.trans = NULL;
1189 qspi->trans_pos.byte = 0; 1251 qspi->trans_pos.byte = 0;
1252 qspi->trans_pos.mspi_last_trans = true;
1190 qspi->master = master; 1253 qspi->master = master;
1191 1254
1192 master->bus_num = -1; 1255 master->bus_num = -1;
@@ -1345,7 +1408,6 @@ int bcm_qspi_remove(struct platform_device *pdev)
1345{ 1408{
1346 struct bcm_qspi *qspi = platform_get_drvdata(pdev); 1409 struct bcm_qspi *qspi = platform_get_drvdata(pdev);
1347 1410
1348 platform_set_drvdata(pdev, NULL);
1349 bcm_qspi_hw_uninit(qspi); 1411 bcm_qspi_hw_uninit(qspi);
1350 clk_disable_unprepare(qspi->clk); 1412 clk_disable_unprepare(qspi->clk);
1351 kfree(qspi->dev_ids); 1413 kfree(qspi->dev_ids);
diff --git a/drivers/spi/spi-bcm53xx.c b/drivers/spi/spi-bcm53xx.c
index afb51699dbb5..6e409eabe1c9 100644
--- a/drivers/spi/spi-bcm53xx.c
+++ b/drivers/spi/spi-bcm53xx.c
@@ -1,3 +1,11 @@
1/*
2 * Copyright (C) 2014-2016 Rafał Miłecki <rafal@milecki.pl>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
1#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 9#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
2 10
3#include <linux/kernel.h> 11#include <linux/kernel.h>
@@ -275,10 +283,6 @@ static int bcm53xxspi_flash_read(struct spi_device *spi,
275 * BCMA 283 * BCMA
276 **************************************************/ 284 **************************************************/
277 285
278static struct spi_board_info bcm53xx_info = {
279 .modalias = "bcm53xxspiflash",
280};
281
282static const struct bcma_device_id bcm53xxspi_bcma_tbl[] = { 286static const struct bcma_device_id bcm53xxspi_bcma_tbl[] = {
283 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_NS_QSPI, BCMA_ANY_REV, BCMA_ANY_CLASS), 287 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_NS_QSPI, BCMA_ANY_REV, BCMA_ANY_CLASS),
284 {}, 288 {},
@@ -311,6 +315,7 @@ static int bcm53xxspi_bcma_probe(struct bcma_device *core)
311 b53spi->bspi = true; 315 b53spi->bspi = true;
312 bcm53xxspi_disable_bspi(b53spi); 316 bcm53xxspi_disable_bspi(b53spi);
313 317
318 master->dev.of_node = dev->of_node;
314 master->transfer_one = bcm53xxspi_transfer_one; 319 master->transfer_one = bcm53xxspi_transfer_one;
315 if (b53spi->mmio_base) 320 if (b53spi->mmio_base)
316 master->spi_flash_read = bcm53xxspi_flash_read; 321 master->spi_flash_read = bcm53xxspi_flash_read;
@@ -324,9 +329,6 @@ static int bcm53xxspi_bcma_probe(struct bcma_device *core)
324 return err; 329 return err;
325 } 330 }
326 331
327 /* Broadcom SoCs (at least with the CC rev 42) use SPI for flash only */
328 spi_new_device(master, &bcm53xx_info);
329
330 return 0; 332 return 0;
331} 333}
332 334
@@ -361,4 +363,4 @@ module_exit(bcm53xxspi_module_exit);
361 363
362MODULE_DESCRIPTION("Broadcom BCM53xx SPI Controller driver"); 364MODULE_DESCRIPTION("Broadcom BCM53xx SPI Controller driver");
363MODULE_AUTHOR("Rafał Miłecki <zajec5@gmail.com>"); 365MODULE_AUTHOR("Rafał Miłecki <zajec5@gmail.com>");
364MODULE_LICENSE("GPL"); 366MODULE_LICENSE("GPL v2");
diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c
index 054012f87567..b217c22ff72f 100644
--- a/drivers/spi/spi-dw.c
+++ b/drivers/spi/spi-dw.c
@@ -107,9 +107,9 @@ static const struct file_operations dw_spi_regs_ops = {
107 107
108static int dw_spi_debugfs_init(struct dw_spi *dws) 108static int dw_spi_debugfs_init(struct dw_spi *dws)
109{ 109{
110 char name[128]; 110 char name[32];
111 111
112 snprintf(name, 128, "dw_spi-%s", dev_name(&dws->master->dev)); 112 snprintf(name, 32, "dw_spi%d", dws->master->bus_num);
113 dws->debugfs = debugfs_create_dir(name, NULL); 113 dws->debugfs = debugfs_create_dir(name, NULL);
114 if (!dws->debugfs) 114 if (!dws->debugfs)
115 return -ENOMEM; 115 return -ENOMEM;
@@ -486,9 +486,9 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
486 dws->type = SSI_MOTO_SPI; 486 dws->type = SSI_MOTO_SPI;
487 dws->dma_inited = 0; 487 dws->dma_inited = 0;
488 dws->dma_addr = (dma_addr_t)(dws->paddr + DW_SPI_DR); 488 dws->dma_addr = (dma_addr_t)(dws->paddr + DW_SPI_DR);
489 snprintf(dws->name, sizeof(dws->name), "dw_spi%d", dws->bus_num);
490 489
491 ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, dws->name, master); 490 ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, dev_name(dev),
491 master);
492 if (ret < 0) { 492 if (ret < 0) {
493 dev_err(dev, "can not get IRQ\n"); 493 dev_err(dev, "can not get IRQ\n");
494 goto err_free_master; 494 goto err_free_master;
diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
index c21ca02f8ec5..da5eab62df34 100644
--- a/drivers/spi/spi-dw.h
+++ b/drivers/spi/spi-dw.h
@@ -101,7 +101,6 @@ struct dw_spi_dma_ops {
101struct dw_spi { 101struct dw_spi {
102 struct spi_master *master; 102 struct spi_master *master;
103 enum dw_ssi_type type; 103 enum dw_ssi_type type;
104 char name[16];
105 104
106 void __iomem *regs; 105 void __iomem *regs;
107 unsigned long paddr; 106 unsigned long paddr;
diff --git a/drivers/spi/spi-ep93xx.c b/drivers/spi/spi-ep93xx.c
index 17a6387e20b5..b5d766064b7b 100644
--- a/drivers/spi/spi-ep93xx.c
+++ b/drivers/spi/spi-ep93xx.c
@@ -28,6 +28,7 @@
28#include <linux/platform_device.h> 28#include <linux/platform_device.h>
29#include <linux/sched.h> 29#include <linux/sched.h>
30#include <linux/scatterlist.h> 30#include <linux/scatterlist.h>
31#include <linux/gpio.h>
31#include <linux/spi/spi.h> 32#include <linux/spi/spi.h>
32 33
33#include <linux/platform_data/dma-ep93xx.h> 34#include <linux/platform_data/dma-ep93xx.h>
@@ -107,16 +108,6 @@ struct ep93xx_spi {
107 void *zeropage; 108 void *zeropage;
108}; 109};
109 110
110/**
111 * struct ep93xx_spi_chip - SPI device hardware settings
112 * @spi: back pointer to the SPI device
113 * @ops: private chip operations
114 */
115struct ep93xx_spi_chip {
116 const struct spi_device *spi;
117 struct ep93xx_spi_chip_ops *ops;
118};
119
120/* converts bits per word to CR0.DSS value */ 111/* converts bits per word to CR0.DSS value */
121#define bits_per_word_to_dss(bpw) ((bpw) - 1) 112#define bits_per_word_to_dss(bpw) ((bpw) - 1)
122 113
@@ -229,104 +220,36 @@ static int ep93xx_spi_calc_divisors(const struct ep93xx_spi *espi,
229 return -EINVAL; 220 return -EINVAL;
230} 221}
231 222
232static void ep93xx_spi_cs_control(struct spi_device *spi, bool control) 223static void ep93xx_spi_cs_control(struct spi_device *spi, bool enable)
233{
234 struct ep93xx_spi_chip *chip = spi_get_ctldata(spi);
235 int value = (spi->mode & SPI_CS_HIGH) ? control : !control;
236
237 if (chip->ops && chip->ops->cs_control)
238 chip->ops->cs_control(spi, value);
239}
240
241/**
242 * ep93xx_spi_setup() - setup an SPI device
243 * @spi: SPI device to setup
244 *
245 * This function sets up SPI device mode, speed etc. Can be called multiple
246 * times for a single device. Returns %0 in case of success, negative error in
247 * case of failure. When this function returns success, the device is
248 * deselected.
249 */
250static int ep93xx_spi_setup(struct spi_device *spi)
251{ 224{
252 struct ep93xx_spi *espi = spi_master_get_devdata(spi->master); 225 if (spi->mode & SPI_CS_HIGH)
253 struct ep93xx_spi_chip *chip; 226 enable = !enable;
254 227
255 chip = spi_get_ctldata(spi); 228 if (gpio_is_valid(spi->cs_gpio))
256 if (!chip) { 229 gpio_set_value(spi->cs_gpio, !enable);
257 dev_dbg(&espi->pdev->dev, "initial setup for %s\n",
258 spi->modalias);
259
260 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
261 if (!chip)
262 return -ENOMEM;
263
264 chip->spi = spi;
265 chip->ops = spi->controller_data;
266
267 if (chip->ops && chip->ops->setup) {
268 int ret = chip->ops->setup(spi);
269
270 if (ret) {
271 kfree(chip);
272 return ret;
273 }
274 }
275
276 spi_set_ctldata(spi, chip);
277 }
278
279 ep93xx_spi_cs_control(spi, false);
280 return 0;
281} 230}
282 231
283/**
284 * ep93xx_spi_cleanup() - cleans up master controller specific state
285 * @spi: SPI device to cleanup
286 *
287 * This function releases master controller specific state for given @spi
288 * device.
289 */
290static void ep93xx_spi_cleanup(struct spi_device *spi)
291{
292 struct ep93xx_spi_chip *chip;
293
294 chip = spi_get_ctldata(spi);
295 if (chip) {
296 if (chip->ops && chip->ops->cleanup)
297 chip->ops->cleanup(spi);
298 spi_set_ctldata(spi, NULL);
299 kfree(chip);
300 }
301}
302
303/**
304 * ep93xx_spi_chip_setup() - configures hardware according to given @chip
305 * @espi: ep93xx SPI controller struct
306 * @chip: chip specific settings
307 * @speed_hz: transfer speed
308 * @bits_per_word: transfer bits_per_word
309 */
310static int ep93xx_spi_chip_setup(const struct ep93xx_spi *espi, 232static int ep93xx_spi_chip_setup(const struct ep93xx_spi *espi,
311 const struct ep93xx_spi_chip *chip, 233 struct spi_device *spi,
312 u32 speed_hz, u8 bits_per_word) 234 struct spi_transfer *xfer)
313{ 235{
314 u8 dss = bits_per_word_to_dss(bits_per_word); 236 u8 dss = bits_per_word_to_dss(xfer->bits_per_word);
315 u8 div_cpsr = 0; 237 u8 div_cpsr = 0;
316 u8 div_scr = 0; 238 u8 div_scr = 0;
317 u16 cr0; 239 u16 cr0;
318 int err; 240 int err;
319 241
320 err = ep93xx_spi_calc_divisors(espi, speed_hz, &div_cpsr, &div_scr); 242 err = ep93xx_spi_calc_divisors(espi, xfer->speed_hz,
243 &div_cpsr, &div_scr);
321 if (err) 244 if (err)
322 return err; 245 return err;
323 246
324 cr0 = div_scr << SSPCR0_SCR_SHIFT; 247 cr0 = div_scr << SSPCR0_SCR_SHIFT;
325 cr0 |= (chip->spi->mode & (SPI_CPHA|SPI_CPOL)) << SSPCR0_MODE_SHIFT; 248 cr0 |= (spi->mode & (SPI_CPHA | SPI_CPOL)) << SSPCR0_MODE_SHIFT;
326 cr0 |= dss; 249 cr0 |= dss;
327 250
328 dev_dbg(&espi->pdev->dev, "setup: mode %d, cpsr %d, scr %d, dss %d\n", 251 dev_dbg(&espi->pdev->dev, "setup: mode %d, cpsr %d, scr %d, dss %d\n",
329 chip->spi->mode, div_cpsr, div_scr, dss); 252 spi->mode, div_cpsr, div_scr, dss);
330 dev_dbg(&espi->pdev->dev, "setup: cr0 %#x\n", cr0); 253 dev_dbg(&espi->pdev->dev, "setup: cr0 %#x\n", cr0);
331 254
332 ep93xx_spi_write_u8(espi, SSPCPSR, div_cpsr); 255 ep93xx_spi_write_u8(espi, SSPCPSR, div_cpsr);
@@ -603,12 +526,11 @@ static void ep93xx_spi_process_transfer(struct ep93xx_spi *espi,
603 struct spi_message *msg, 526 struct spi_message *msg,
604 struct spi_transfer *t) 527 struct spi_transfer *t)
605{ 528{
606 struct ep93xx_spi_chip *chip = spi_get_ctldata(msg->spi);
607 int err; 529 int err;
608 530
609 msg->state = t; 531 msg->state = t;
610 532
611 err = ep93xx_spi_chip_setup(espi, chip, t->speed_hz, t->bits_per_word); 533 err = ep93xx_spi_chip_setup(espi, msg->spi, t);
612 if (err) { 534 if (err) {
613 dev_err(&espi->pdev->dev, 535 dev_err(&espi->pdev->dev,
614 "failed to setup chip for transfer\n"); 536 "failed to setup chip for transfer\n");
@@ -863,8 +785,13 @@ static int ep93xx_spi_probe(struct platform_device *pdev)
863 struct resource *res; 785 struct resource *res;
864 int irq; 786 int irq;
865 int error; 787 int error;
788 int i;
866 789
867 info = dev_get_platdata(&pdev->dev); 790 info = dev_get_platdata(&pdev->dev);
791 if (!info) {
792 dev_err(&pdev->dev, "missing platform data\n");
793 return -EINVAL;
794 }
868 795
869 irq = platform_get_irq(pdev, 0); 796 irq = platform_get_irq(pdev, 0);
870 if (irq < 0) { 797 if (irq < 0) {
@@ -882,14 +809,36 @@ static int ep93xx_spi_probe(struct platform_device *pdev)
882 if (!master) 809 if (!master)
883 return -ENOMEM; 810 return -ENOMEM;
884 811
885 master->setup = ep93xx_spi_setup;
886 master->transfer_one_message = ep93xx_spi_transfer_one_message; 812 master->transfer_one_message = ep93xx_spi_transfer_one_message;
887 master->cleanup = ep93xx_spi_cleanup;
888 master->bus_num = pdev->id; 813 master->bus_num = pdev->id;
889 master->num_chipselect = info->num_chipselect;
890 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 814 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
891 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); 815 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
892 816
817 master->num_chipselect = info->num_chipselect;
818 master->cs_gpios = devm_kzalloc(&master->dev,
819 sizeof(int) * master->num_chipselect,
820 GFP_KERNEL);
821 if (!master->cs_gpios) {
822 error = -ENOMEM;
823 goto fail_release_master;
824 }
825
826 for (i = 0; i < master->num_chipselect; i++) {
827 master->cs_gpios[i] = info->chipselect[i];
828
829 if (!gpio_is_valid(master->cs_gpios[i]))
830 continue;
831
832 error = devm_gpio_request_one(&pdev->dev, master->cs_gpios[i],
833 GPIOF_OUT_INIT_HIGH,
834 "ep93xx-spi");
835 if (error) {
836 dev_err(&pdev->dev, "could not request cs gpio %d\n",
837 master->cs_gpios[i]);
838 goto fail_release_master;
839 }
840 }
841
893 platform_set_drvdata(pdev, master); 842 platform_set_drvdata(pdev, master);
894 843
895 espi = spi_master_get_devdata(master); 844 espi = spi_master_get_devdata(master);
diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c
index 52551f6d0c7d..cb3c73007ca1 100644
--- a/drivers/spi/spi-fsl-lpspi.c
+++ b/drivers/spi/spi-fsl-lpspi.c
@@ -366,7 +366,7 @@ static int fsl_lpspi_transfer_one_msg(struct spi_master *master,
366 struct spi_transfer *xfer; 366 struct spi_transfer *xfer;
367 bool is_first_xfer = true; 367 bool is_first_xfer = true;
368 u32 temp; 368 u32 temp;
369 int ret; 369 int ret = 0;
370 370
371 msg->status = 0; 371 msg->status = 0;
372 msg->actual_length = 0; 372 msg->actual_length = 0;
@@ -512,9 +512,9 @@ static int fsl_lpspi_remove(struct platform_device *pdev)
512 512
513static struct platform_driver fsl_lpspi_driver = { 513static struct platform_driver fsl_lpspi_driver = {
514 .driver = { 514 .driver = {
515 .name = DRIVER_NAME, 515 .name = DRIVER_NAME,
516 .of_match_table = fsl_lpspi_dt_ids, 516 .of_match_table = fsl_lpspi_dt_ids,
517 }, 517 },
518 .probe = fsl_lpspi_probe, 518 .probe = fsl_lpspi_probe,
519 .remove = fsl_lpspi_remove, 519 .remove = fsl_lpspi_remove,
520}; 520};
diff --git a/drivers/spi/spi-fsl-spi.c b/drivers/spi/spi-fsl-spi.c
index 8b290d9d7935..0fc3452652ae 100644
--- a/drivers/spi/spi-fsl-spi.c
+++ b/drivers/spi/spi-fsl-spi.c
@@ -267,10 +267,9 @@ static int fsl_spi_setup_transfer(struct spi_device *spi,
267 if ((mpc8xxx_spi->spibrg / hz) > 64) { 267 if ((mpc8xxx_spi->spibrg / hz) > 64) {
268 cs->hw_mode |= SPMODE_DIV16; 268 cs->hw_mode |= SPMODE_DIV16;
269 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1; 269 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
270 270 WARN_ONCE(pm > 16,
271 WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. " 271 "%s: Requested speed is too low: %d Hz. Will use %d Hz instead.\n",
272 "Will use %d Hz instead.\n", dev_name(&spi->dev), 272 dev_name(&spi->dev), hz, mpc8xxx_spi->spibrg / 1024);
273 hz, mpc8xxx_spi->spibrg / 1024);
274 if (pm > 16) 273 if (pm > 16)
275 pm = 16; 274 pm = 16;
276 } else { 275 } else {
@@ -727,12 +726,13 @@ static int of_fsl_spi_get_chipselects(struct device *dev)
727 return 0; 726 return 0;
728 } 727 }
729 728
730 pinfo->gpios = kmalloc(ngpios * sizeof(*pinfo->gpios), GFP_KERNEL); 729 pinfo->gpios = kmalloc_array(ngpios, sizeof(*pinfo->gpios),
730 GFP_KERNEL);
731 if (!pinfo->gpios) 731 if (!pinfo->gpios)
732 return -ENOMEM; 732 return -ENOMEM;
733 memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios)); 733 memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios));
734 734
735 pinfo->alow_flags = kzalloc(ngpios * sizeof(*pinfo->alow_flags), 735 pinfo->alow_flags = kcalloc(ngpios, sizeof(*pinfo->alow_flags),
736 GFP_KERNEL); 736 GFP_KERNEL);
737 if (!pinfo->alow_flags) { 737 if (!pinfo->alow_flags) {
738 ret = -ENOMEM; 738 ret = -ENOMEM;
@@ -762,8 +762,9 @@ static int of_fsl_spi_get_chipselects(struct device *dev)
762 ret = gpio_direction_output(pinfo->gpios[i], 762 ret = gpio_direction_output(pinfo->gpios[i],
763 pinfo->alow_flags[i]); 763 pinfo->alow_flags[i]);
764 if (ret) { 764 if (ret) {
765 dev_err(dev, "can't set output direction for gpio " 765 dev_err(dev,
766 "#%d: %d\n", i, ret); 766 "can't set output direction for gpio #%d: %d\n",
767 i, ret);
767 goto err_loop; 768 goto err_loop;
768 } 769 }
769 } 770 }
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index 32ced64a5bb9..9a7c62f471dc 100644
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi/spi-imx.c
@@ -211,7 +211,7 @@ static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
211 struct spi_transfer *transfer) 211 struct spi_transfer *transfer)
212{ 212{
213 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 213 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
214 unsigned int bpw; 214 unsigned int bpw, i;
215 215
216 if (!master->dma_rx) 216 if (!master->dma_rx)
217 return false; 217 return false;
@@ -228,12 +228,16 @@ static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
228 if (bpw != 1 && bpw != 2 && bpw != 4) 228 if (bpw != 1 && bpw != 2 && bpw != 4)
229 return false; 229 return false;
230 230
231 if (transfer->len < spi_imx->wml * bpw) 231 for (i = spi_imx_get_fifosize(spi_imx) / 2; i > 0; i--) {
232 return false; 232 if (!(transfer->len % (i * bpw)))
233 break;
234 }
233 235
234 if (transfer->len % (spi_imx->wml * bpw)) 236 if (i == 0)
235 return false; 237 return false;
236 238
239 spi_imx->wml = i;
240
237 return true; 241 return true;
238} 242}
239 243
@@ -837,10 +841,6 @@ static int spi_imx_dma_configure(struct spi_master *master,
837 struct dma_slave_config rx = {}, tx = {}; 841 struct dma_slave_config rx = {}, tx = {};
838 struct spi_imx_data *spi_imx = spi_master_get_devdata(master); 842 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
839 843
840 if (bytes_per_word == spi_imx->bytes_per_word)
841 /* Same as last time */
842 return 0;
843
844 switch (bytes_per_word) { 844 switch (bytes_per_word) {
845 case 4: 845 case 4:
846 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES; 846 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
diff --git a/drivers/spi/spi-lantiq-ssc.c b/drivers/spi/spi-lantiq-ssc.c
new file mode 100644
index 000000000000..8a626f7fccea
--- /dev/null
+++ b/drivers/spi/spi-lantiq-ssc.c
@@ -0,0 +1,983 @@
1/*
2 * Copyright (C) 2011-2015 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
3 * Copyright (C) 2016 Hauke Mehrtens <hauke@hauke-m.de>
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/of_device.h>
13#include <linux/clk.h>
14#include <linux/io.h>
15#include <linux/delay.h>
16#include <linux/interrupt.h>
17#include <linux/sched.h>
18#include <linux/completion.h>
19#include <linux/spinlock.h>
20#include <linux/err.h>
21#include <linux/gpio.h>
22#include <linux/pm_runtime.h>
23#include <linux/spi/spi.h>
24
25#ifdef CONFIG_LANTIQ
26#include <lantiq_soc.h>
27#endif
28
29#define SPI_RX_IRQ_NAME "spi_rx"
30#define SPI_TX_IRQ_NAME "spi_tx"
31#define SPI_ERR_IRQ_NAME "spi_err"
32#define SPI_FRM_IRQ_NAME "spi_frm"
33
34#define SPI_CLC 0x00
35#define SPI_PISEL 0x04
36#define SPI_ID 0x08
37#define SPI_CON 0x10
38#define SPI_STAT 0x14
39#define SPI_WHBSTATE 0x18
40#define SPI_TB 0x20
41#define SPI_RB 0x24
42#define SPI_RXFCON 0x30
43#define SPI_TXFCON 0x34
44#define SPI_FSTAT 0x38
45#define SPI_BRT 0x40
46#define SPI_BRSTAT 0x44
47#define SPI_SFCON 0x60
48#define SPI_SFSTAT 0x64
49#define SPI_GPOCON 0x70
50#define SPI_GPOSTAT 0x74
51#define SPI_FPGO 0x78
52#define SPI_RXREQ 0x80
53#define SPI_RXCNT 0x84
54#define SPI_DMACON 0xec
55#define SPI_IRNEN 0xf4
56#define SPI_IRNICR 0xf8
57#define SPI_IRNCR 0xfc
58
59#define SPI_CLC_SMC_S 16 /* Clock divider for sleep mode */
60#define SPI_CLC_SMC_M (0xFF << SPI_CLC_SMC_S)
61#define SPI_CLC_RMC_S 8 /* Clock divider for normal run mode */
62#define SPI_CLC_RMC_M (0xFF << SPI_CLC_RMC_S)
63#define SPI_CLC_DISS BIT(1) /* Disable status bit */
64#define SPI_CLC_DISR BIT(0) /* Disable request bit */
65
66#define SPI_ID_TXFS_S 24 /* Implemented TX FIFO size */
67#define SPI_ID_TXFS_M (0x3F << SPI_ID_TXFS_S)
68#define SPI_ID_RXFS_S 16 /* Implemented RX FIFO size */
69#define SPI_ID_RXFS_M (0x3F << SPI_ID_RXFS_S)
70#define SPI_ID_MOD_S 8 /* Module ID */
71#define SPI_ID_MOD_M (0xff << SPI_ID_MOD_S)
72#define SPI_ID_CFG_S 5 /* DMA interface support */
73#define SPI_ID_CFG_M (1 << SPI_ID_CFG_S)
74#define SPI_ID_REV_M 0x1F /* Hardware revision number */
75
76#define SPI_CON_BM_S 16 /* Data width selection */
77#define SPI_CON_BM_M (0x1F << SPI_CON_BM_S)
78#define SPI_CON_EM BIT(24) /* Echo mode */
79#define SPI_CON_IDLE BIT(23) /* Idle bit value */
80#define SPI_CON_ENBV BIT(22) /* Enable byte valid control */
81#define SPI_CON_RUEN BIT(12) /* Receive underflow error enable */
82#define SPI_CON_TUEN BIT(11) /* Transmit underflow error enable */
83#define SPI_CON_AEN BIT(10) /* Abort error enable */
84#define SPI_CON_REN BIT(9) /* Receive overflow error enable */
85#define SPI_CON_TEN BIT(8) /* Transmit overflow error enable */
86#define SPI_CON_LB BIT(7) /* Loopback control */
87#define SPI_CON_PO BIT(6) /* Clock polarity control */
88#define SPI_CON_PH BIT(5) /* Clock phase control */
89#define SPI_CON_HB BIT(4) /* Heading control */
90#define SPI_CON_RXOFF BIT(1) /* Switch receiver off */
91#define SPI_CON_TXOFF BIT(0) /* Switch transmitter off */
92
93#define SPI_STAT_RXBV_S 28
94#define SPI_STAT_RXBV_M (0x7 << SPI_STAT_RXBV_S)
95#define SPI_STAT_BSY BIT(13) /* Busy flag */
96#define SPI_STAT_RUE BIT(12) /* Receive underflow error flag */
97#define SPI_STAT_TUE BIT(11) /* Transmit underflow error flag */
98#define SPI_STAT_AE BIT(10) /* Abort error flag */
99#define SPI_STAT_RE BIT(9) /* Receive error flag */
100#define SPI_STAT_TE BIT(8) /* Transmit error flag */
101#define SPI_STAT_ME BIT(7) /* Mode error flag */
102#define SPI_STAT_MS BIT(1) /* Master/slave select bit */
103#define SPI_STAT_EN BIT(0) /* Enable bit */
104#define SPI_STAT_ERRORS (SPI_STAT_ME | SPI_STAT_TE | SPI_STAT_RE | \
105 SPI_STAT_AE | SPI_STAT_TUE | SPI_STAT_RUE)
106
107#define SPI_WHBSTATE_SETTUE BIT(15) /* Set transmit underflow error flag */
108#define SPI_WHBSTATE_SETAE BIT(14) /* Set abort error flag */
109#define SPI_WHBSTATE_SETRE BIT(13) /* Set receive error flag */
110#define SPI_WHBSTATE_SETTE BIT(12) /* Set transmit error flag */
111#define SPI_WHBSTATE_CLRTUE BIT(11) /* Clear transmit underflow error flag */
112#define SPI_WHBSTATE_CLRAE BIT(10) /* Clear abort error flag */
113#define SPI_WHBSTATE_CLRRE BIT(9) /* Clear receive error flag */
114#define SPI_WHBSTATE_CLRTE BIT(8) /* Clear transmit error flag */
115#define SPI_WHBSTATE_SETME BIT(7) /* Set mode error flag */
116#define SPI_WHBSTATE_CLRME BIT(6) /* Clear mode error flag */
117#define SPI_WHBSTATE_SETRUE BIT(5) /* Set receive underflow error flag */
118#define SPI_WHBSTATE_CLRRUE BIT(4) /* Clear receive underflow error flag */
119#define SPI_WHBSTATE_SETMS BIT(3) /* Set master select bit */
120#define SPI_WHBSTATE_CLRMS BIT(2) /* Clear master select bit */
121#define SPI_WHBSTATE_SETEN BIT(1) /* Set enable bit (operational mode) */
122#define SPI_WHBSTATE_CLREN BIT(0) /* Clear enable bit (config mode */
123#define SPI_WHBSTATE_CLR_ERRORS (SPI_WHBSTATE_CLRRUE | SPI_WHBSTATE_CLRME | \
124 SPI_WHBSTATE_CLRTE | SPI_WHBSTATE_CLRRE | \
125 SPI_WHBSTATE_CLRAE | SPI_WHBSTATE_CLRTUE)
126
127#define SPI_RXFCON_RXFITL_S 8 /* FIFO interrupt trigger level */
128#define SPI_RXFCON_RXFITL_M (0x3F << SPI_RXFCON_RXFITL_S)
129#define SPI_RXFCON_RXFLU BIT(1) /* FIFO flush */
130#define SPI_RXFCON_RXFEN BIT(0) /* FIFO enable */
131
132#define SPI_TXFCON_TXFITL_S 8 /* FIFO interrupt trigger level */
133#define SPI_TXFCON_TXFITL_M (0x3F << SPI_TXFCON_TXFITL_S)
134#define SPI_TXFCON_TXFLU BIT(1) /* FIFO flush */
135#define SPI_TXFCON_TXFEN BIT(0) /* FIFO enable */
136
137#define SPI_FSTAT_RXFFL_S 0
138#define SPI_FSTAT_RXFFL_M (0x3f << SPI_FSTAT_RXFFL_S)
139#define SPI_FSTAT_TXFFL_S 8
140#define SPI_FSTAT_TXFFL_M (0x3f << SPI_FSTAT_TXFFL_S)
141
142#define SPI_GPOCON_ISCSBN_S 8
143#define SPI_GPOCON_INVOUTN_S 0
144
145#define SPI_FGPO_SETOUTN_S 8
146#define SPI_FGPO_CLROUTN_S 0
147
148#define SPI_RXREQ_RXCNT_M 0xFFFF /* Receive count value */
149#define SPI_RXCNT_TODO_M 0xFFFF /* Recevie to-do value */
150
151#define SPI_IRNEN_TFI BIT(4) /* TX finished interrupt */
152#define SPI_IRNEN_F BIT(3) /* Frame end interrupt request */
153#define SPI_IRNEN_E BIT(2) /* Error end interrupt request */
154#define SPI_IRNEN_T_XWAY BIT(1) /* Transmit end interrupt request */
155#define SPI_IRNEN_R_XWAY BIT(0) /* Receive end interrupt request */
156#define SPI_IRNEN_R_XRX BIT(1) /* Transmit end interrupt request */
157#define SPI_IRNEN_T_XRX BIT(0) /* Receive end interrupt request */
158#define SPI_IRNEN_ALL 0x1F
159
160struct lantiq_ssc_hwcfg {
161 unsigned int irnen_r;
162 unsigned int irnen_t;
163};
164
165struct lantiq_ssc_spi {
166 struct spi_master *master;
167 struct device *dev;
168 void __iomem *regbase;
169 struct clk *spi_clk;
170 struct clk *fpi_clk;
171 const struct lantiq_ssc_hwcfg *hwcfg;
172
173 spinlock_t lock;
174 struct workqueue_struct *wq;
175 struct work_struct work;
176
177 const u8 *tx;
178 u8 *rx;
179 unsigned int tx_todo;
180 unsigned int rx_todo;
181 unsigned int bits_per_word;
182 unsigned int speed_hz;
183 unsigned int tx_fifo_size;
184 unsigned int rx_fifo_size;
185 unsigned int base_cs;
186};
187
188static u32 lantiq_ssc_readl(const struct lantiq_ssc_spi *spi, u32 reg)
189{
190 return __raw_readl(spi->regbase + reg);
191}
192
193static void lantiq_ssc_writel(const struct lantiq_ssc_spi *spi, u32 val,
194 u32 reg)
195{
196 __raw_writel(val, spi->regbase + reg);
197}
198
199static void lantiq_ssc_maskl(const struct lantiq_ssc_spi *spi, u32 clr,
200 u32 set, u32 reg)
201{
202 u32 val = __raw_readl(spi->regbase + reg);
203
204 val &= ~clr;
205 val |= set;
206 __raw_writel(val, spi->regbase + reg);
207}
208
209static unsigned int tx_fifo_level(const struct lantiq_ssc_spi *spi)
210{
211 u32 fstat = lantiq_ssc_readl(spi, SPI_FSTAT);
212
213 return (fstat & SPI_FSTAT_TXFFL_M) >> SPI_FSTAT_TXFFL_S;
214}
215
216static unsigned int rx_fifo_level(const struct lantiq_ssc_spi *spi)
217{
218 u32 fstat = lantiq_ssc_readl(spi, SPI_FSTAT);
219
220 return fstat & SPI_FSTAT_RXFFL_M;
221}
222
223static unsigned int tx_fifo_free(const struct lantiq_ssc_spi *spi)
224{
225 return spi->tx_fifo_size - tx_fifo_level(spi);
226}
227
228static void rx_fifo_reset(const struct lantiq_ssc_spi *spi)
229{
230 u32 val = spi->rx_fifo_size << SPI_RXFCON_RXFITL_S;
231
232 val |= SPI_RXFCON_RXFEN | SPI_RXFCON_RXFLU;
233 lantiq_ssc_writel(spi, val, SPI_RXFCON);
234}
235
236static void tx_fifo_reset(const struct lantiq_ssc_spi *spi)
237{
238 u32 val = 1 << SPI_TXFCON_TXFITL_S;
239
240 val |= SPI_TXFCON_TXFEN | SPI_TXFCON_TXFLU;
241 lantiq_ssc_writel(spi, val, SPI_TXFCON);
242}
243
244static void rx_fifo_flush(const struct lantiq_ssc_spi *spi)
245{
246 lantiq_ssc_maskl(spi, 0, SPI_RXFCON_RXFLU, SPI_RXFCON);
247}
248
249static void tx_fifo_flush(const struct lantiq_ssc_spi *spi)
250{
251 lantiq_ssc_maskl(spi, 0, SPI_TXFCON_TXFLU, SPI_TXFCON);
252}
253
254static void hw_enter_config_mode(const struct lantiq_ssc_spi *spi)
255{
256 lantiq_ssc_writel(spi, SPI_WHBSTATE_CLREN, SPI_WHBSTATE);
257}
258
259static void hw_enter_active_mode(const struct lantiq_ssc_spi *spi)
260{
261 lantiq_ssc_writel(spi, SPI_WHBSTATE_SETEN, SPI_WHBSTATE);
262}
263
264static void hw_setup_speed_hz(const struct lantiq_ssc_spi *spi,
265 unsigned int max_speed_hz)
266{
267 u32 spi_clk, brt;
268
269 /*
270 * SPI module clock is derived from FPI bus clock dependent on
271 * divider value in CLC.RMS which is always set to 1.
272 *
273 * f_SPI
274 * baudrate = --------------
275 * 2 * (BR + 1)
276 */
277 spi_clk = clk_get_rate(spi->fpi_clk) / 2;
278
279 if (max_speed_hz > spi_clk)
280 brt = 0;
281 else
282 brt = spi_clk / max_speed_hz - 1;
283
284 if (brt > 0xFFFF)
285 brt = 0xFFFF;
286
287 dev_dbg(spi->dev, "spi_clk %u, max_speed_hz %u, brt %u\n",
288 spi_clk, max_speed_hz, brt);
289
290 lantiq_ssc_writel(spi, brt, SPI_BRT);
291}
292
293static void hw_setup_bits_per_word(const struct lantiq_ssc_spi *spi,
294 unsigned int bits_per_word)
295{
296 u32 bm;
297
298 /* CON.BM value = bits_per_word - 1 */
299 bm = (bits_per_word - 1) << SPI_CON_BM_S;
300
301 lantiq_ssc_maskl(spi, SPI_CON_BM_M, bm, SPI_CON);
302}
303
304static void hw_setup_clock_mode(const struct lantiq_ssc_spi *spi,
305 unsigned int mode)
306{
307 u32 con_set = 0, con_clr = 0;
308
309 /*
310 * SPI mode mapping in CON register:
311 * Mode CPOL CPHA CON.PO CON.PH
312 * 0 0 0 0 1
313 * 1 0 1 0 0
314 * 2 1 0 1 1
315 * 3 1 1 1 0
316 */
317 if (mode & SPI_CPHA)
318 con_clr |= SPI_CON_PH;
319 else
320 con_set |= SPI_CON_PH;
321
322 if (mode & SPI_CPOL)
323 con_set |= SPI_CON_PO | SPI_CON_IDLE;
324 else
325 con_clr |= SPI_CON_PO | SPI_CON_IDLE;
326
327 /* Set heading control */
328 if (mode & SPI_LSB_FIRST)
329 con_clr |= SPI_CON_HB;
330 else
331 con_set |= SPI_CON_HB;
332
333 /* Set loopback mode */
334 if (mode & SPI_LOOP)
335 con_set |= SPI_CON_LB;
336 else
337 con_clr |= SPI_CON_LB;
338
339 lantiq_ssc_maskl(spi, con_clr, con_set, SPI_CON);
340}
341
342static void lantiq_ssc_hw_init(const struct lantiq_ssc_spi *spi)
343{
344 const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
345
346 /*
347 * Set clock divider for run mode to 1 to
348 * run at same frequency as FPI bus
349 */
350 lantiq_ssc_writel(spi, 1 << SPI_CLC_RMC_S, SPI_CLC);
351
352 /* Put controller into config mode */
353 hw_enter_config_mode(spi);
354
355 /* Clear error flags */
356 lantiq_ssc_maskl(spi, 0, SPI_WHBSTATE_CLR_ERRORS, SPI_WHBSTATE);
357
358 /* Enable error checking, disable TX/RX */
359 lantiq_ssc_writel(spi, SPI_CON_RUEN | SPI_CON_AEN | SPI_CON_TEN |
360 SPI_CON_REN | SPI_CON_TXOFF | SPI_CON_RXOFF, SPI_CON);
361
362 /* Setup default SPI mode */
363 hw_setup_bits_per_word(spi, spi->bits_per_word);
364 hw_setup_clock_mode(spi, SPI_MODE_0);
365
366 /* Enable master mode and clear error flags */
367 lantiq_ssc_writel(spi, SPI_WHBSTATE_SETMS | SPI_WHBSTATE_CLR_ERRORS,
368 SPI_WHBSTATE);
369
370 /* Reset GPIO/CS registers */
371 lantiq_ssc_writel(spi, 0, SPI_GPOCON);
372 lantiq_ssc_writel(spi, 0xFF00, SPI_FPGO);
373
374 /* Enable and flush FIFOs */
375 rx_fifo_reset(spi);
376 tx_fifo_reset(spi);
377
378 /* Enable interrupts */
379 lantiq_ssc_writel(spi, hwcfg->irnen_t | hwcfg->irnen_r | SPI_IRNEN_E,
380 SPI_IRNEN);
381}
382
383static int lantiq_ssc_setup(struct spi_device *spidev)
384{
385 struct spi_master *master = spidev->master;
386 struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
387 unsigned int cs = spidev->chip_select;
388 u32 gpocon;
389
390 /* GPIOs are used for CS */
391 if (gpio_is_valid(spidev->cs_gpio))
392 return 0;
393
394 dev_dbg(spi->dev, "using internal chipselect %u\n", cs);
395
396 if (cs < spi->base_cs) {
397 dev_err(spi->dev,
398 "chipselect %i too small (min %i)\n", cs, spi->base_cs);
399 return -EINVAL;
400 }
401
402 /* set GPO pin to CS mode */
403 gpocon = 1 << ((cs - spi->base_cs) + SPI_GPOCON_ISCSBN_S);
404
405 /* invert GPO pin */
406 if (spidev->mode & SPI_CS_HIGH)
407 gpocon |= 1 << (cs - spi->base_cs);
408
409 lantiq_ssc_maskl(spi, 0, gpocon, SPI_GPOCON);
410
411 return 0;
412}
413
414static int lantiq_ssc_prepare_message(struct spi_master *master,
415 struct spi_message *message)
416{
417 struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
418
419 hw_enter_config_mode(spi);
420 hw_setup_clock_mode(spi, message->spi->mode);
421 hw_enter_active_mode(spi);
422
423 return 0;
424}
425
426static void hw_setup_transfer(struct lantiq_ssc_spi *spi,
427 struct spi_device *spidev, struct spi_transfer *t)
428{
429 unsigned int speed_hz = t->speed_hz;
430 unsigned int bits_per_word = t->bits_per_word;
431 u32 con;
432
433 if (bits_per_word != spi->bits_per_word ||
434 speed_hz != spi->speed_hz) {
435 hw_enter_config_mode(spi);
436 hw_setup_speed_hz(spi, speed_hz);
437 hw_setup_bits_per_word(spi, bits_per_word);
438 hw_enter_active_mode(spi);
439
440 spi->speed_hz = speed_hz;
441 spi->bits_per_word = bits_per_word;
442 }
443
444 /* Configure transmitter and receiver */
445 con = lantiq_ssc_readl(spi, SPI_CON);
446 if (t->tx_buf)
447 con &= ~SPI_CON_TXOFF;
448 else
449 con |= SPI_CON_TXOFF;
450
451 if (t->rx_buf)
452 con &= ~SPI_CON_RXOFF;
453 else
454 con |= SPI_CON_RXOFF;
455
456 lantiq_ssc_writel(spi, con, SPI_CON);
457}
458
459static int lantiq_ssc_unprepare_message(struct spi_master *master,
460 struct spi_message *message)
461{
462 struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
463
464 flush_workqueue(spi->wq);
465
466 /* Disable transmitter and receiver while idle */
467 lantiq_ssc_maskl(spi, 0, SPI_CON_TXOFF | SPI_CON_RXOFF, SPI_CON);
468
469 return 0;
470}
471
472static void tx_fifo_write(struct lantiq_ssc_spi *spi)
473{
474 const u8 *tx8;
475 const u16 *tx16;
476 const u32 *tx32;
477 u32 data;
478 unsigned int tx_free = tx_fifo_free(spi);
479
480 while (spi->tx_todo && tx_free) {
481 switch (spi->bits_per_word) {
482 case 2 ... 8:
483 tx8 = spi->tx;
484 data = *tx8;
485 spi->tx_todo--;
486 spi->tx++;
487 break;
488 case 16:
489 tx16 = (u16 *) spi->tx;
490 data = *tx16;
491 spi->tx_todo -= 2;
492 spi->tx += 2;
493 break;
494 case 32:
495 tx32 = (u32 *) spi->tx;
496 data = *tx32;
497 spi->tx_todo -= 4;
498 spi->tx += 4;
499 break;
500 default:
501 WARN_ON(1);
502 data = 0;
503 break;
504 }
505
506 lantiq_ssc_writel(spi, data, SPI_TB);
507 tx_free--;
508 }
509}
510
511static void rx_fifo_read_full_duplex(struct lantiq_ssc_spi *spi)
512{
513 u8 *rx8;
514 u16 *rx16;
515 u32 *rx32;
516 u32 data;
517 unsigned int rx_fill = rx_fifo_level(spi);
518
519 while (rx_fill) {
520 data = lantiq_ssc_readl(spi, SPI_RB);
521
522 switch (spi->bits_per_word) {
523 case 2 ... 8:
524 rx8 = spi->rx;
525 *rx8 = data;
526 spi->rx_todo--;
527 spi->rx++;
528 break;
529 case 16:
530 rx16 = (u16 *) spi->rx;
531 *rx16 = data;
532 spi->rx_todo -= 2;
533 spi->rx += 2;
534 break;
535 case 32:
536 rx32 = (u32 *) spi->rx;
537 *rx32 = data;
538 spi->rx_todo -= 4;
539 spi->rx += 4;
540 break;
541 default:
542 WARN_ON(1);
543 break;
544 }
545
546 rx_fill--;
547 }
548}
549
550static void rx_fifo_read_half_duplex(struct lantiq_ssc_spi *spi)
551{
552 u32 data, *rx32;
553 u8 *rx8;
554 unsigned int rxbv, shift;
555 unsigned int rx_fill = rx_fifo_level(spi);
556
557 /*
558 * In RX-only mode the bits per word value is ignored by HW. A value
559 * of 32 is used instead. Thus all 4 bytes per FIFO must be read.
560 * If remaining RX bytes are less than 4, the FIFO must be read
561 * differently. The amount of received and valid bytes is indicated
562 * by STAT.RXBV register value.
563 */
564 while (rx_fill) {
565 if (spi->rx_todo < 4) {
566 rxbv = (lantiq_ssc_readl(spi, SPI_STAT) &
567 SPI_STAT_RXBV_M) >> SPI_STAT_RXBV_S;
568 data = lantiq_ssc_readl(spi, SPI_RB);
569
570 shift = (rxbv - 1) * 8;
571 rx8 = spi->rx;
572
573 while (rxbv) {
574 *rx8++ = (data >> shift) & 0xFF;
575 rxbv--;
576 shift -= 8;
577 spi->rx_todo--;
578 spi->rx++;
579 }
580 } else {
581 data = lantiq_ssc_readl(spi, SPI_RB);
582 rx32 = (u32 *) spi->rx;
583
584 *rx32++ = data;
585 spi->rx_todo -= 4;
586 spi->rx += 4;
587 }
588 rx_fill--;
589 }
590}
591
592static void rx_request(struct lantiq_ssc_spi *spi)
593{
594 unsigned int rxreq, rxreq_max;
595
596 /*
597 * To avoid receive overflows at high clocks it is better to request
598 * only the amount of bytes that fits into all FIFOs. This value
599 * depends on the FIFO size implemented in hardware.
600 */
601 rxreq = spi->rx_todo;
602 rxreq_max = spi->rx_fifo_size * 4;
603 if (rxreq > rxreq_max)
604 rxreq = rxreq_max;
605
606 lantiq_ssc_writel(spi, rxreq, SPI_RXREQ);
607}
608
609static irqreturn_t lantiq_ssc_xmit_interrupt(int irq, void *data)
610{
611 struct lantiq_ssc_spi *spi = data;
612
613 if (spi->tx) {
614 if (spi->rx && spi->rx_todo)
615 rx_fifo_read_full_duplex(spi);
616
617 if (spi->tx_todo)
618 tx_fifo_write(spi);
619 else if (!tx_fifo_level(spi))
620 goto completed;
621 } else if (spi->rx) {
622 if (spi->rx_todo) {
623 rx_fifo_read_half_duplex(spi);
624
625 if (spi->rx_todo)
626 rx_request(spi);
627 else
628 goto completed;
629 } else {
630 goto completed;
631 }
632 }
633
634 return IRQ_HANDLED;
635
636completed:
637 queue_work(spi->wq, &spi->work);
638
639 return IRQ_HANDLED;
640}
641
642static irqreturn_t lantiq_ssc_err_interrupt(int irq, void *data)
643{
644 struct lantiq_ssc_spi *spi = data;
645 u32 stat = lantiq_ssc_readl(spi, SPI_STAT);
646
647 if (!(stat & SPI_STAT_ERRORS))
648 return IRQ_NONE;
649
650 if (stat & SPI_STAT_RUE)
651 dev_err(spi->dev, "receive underflow error\n");
652 if (stat & SPI_STAT_TUE)
653 dev_err(spi->dev, "transmit underflow error\n");
654 if (stat & SPI_STAT_AE)
655 dev_err(spi->dev, "abort error\n");
656 if (stat & SPI_STAT_RE)
657 dev_err(spi->dev, "receive overflow error\n");
658 if (stat & SPI_STAT_TE)
659 dev_err(spi->dev, "transmit overflow error\n");
660 if (stat & SPI_STAT_ME)
661 dev_err(spi->dev, "mode error\n");
662
663 /* Clear error flags */
664 lantiq_ssc_maskl(spi, 0, SPI_WHBSTATE_CLR_ERRORS, SPI_WHBSTATE);
665
666 /* set bad status so it can be retried */
667 if (spi->master->cur_msg)
668 spi->master->cur_msg->status = -EIO;
669 queue_work(spi->wq, &spi->work);
670
671 return IRQ_HANDLED;
672}
673
674static int transfer_start(struct lantiq_ssc_spi *spi, struct spi_device *spidev,
675 struct spi_transfer *t)
676{
677 unsigned long flags;
678
679 spin_lock_irqsave(&spi->lock, flags);
680
681 spi->tx = t->tx_buf;
682 spi->rx = t->rx_buf;
683
684 if (t->tx_buf) {
685 spi->tx_todo = t->len;
686
687 /* initially fill TX FIFO */
688 tx_fifo_write(spi);
689 }
690
691 if (spi->rx) {
692 spi->rx_todo = t->len;
693
694 /* start shift clock in RX-only mode */
695 if (!spi->tx)
696 rx_request(spi);
697 }
698
699 spin_unlock_irqrestore(&spi->lock, flags);
700
701 return t->len;
702}
703
704/*
705 * The driver only gets an interrupt when the FIFO is empty, but there
706 * is an additional shift register from which the data is written to
707 * the wire. We get the last interrupt when the controller starts to
708 * write the last word to the wire, not when it is finished. Do busy
709 * waiting till it finishes.
710 */
711static void lantiq_ssc_bussy_work(struct work_struct *work)
712{
713 struct lantiq_ssc_spi *spi;
714 unsigned long long timeout = 8LL * 1000LL;
715 unsigned long end;
716
717 spi = container_of(work, typeof(*spi), work);
718
719 do_div(timeout, spi->speed_hz);
720 timeout += timeout + 100; /* some tolerance */
721
722 end = jiffies + msecs_to_jiffies(timeout);
723 do {
724 u32 stat = lantiq_ssc_readl(spi, SPI_STAT);
725
726 if (!(stat & SPI_STAT_BSY)) {
727 spi_finalize_current_transfer(spi->master);
728 return;
729 }
730
731 cond_resched();
732 } while (!time_after_eq(jiffies, end));
733
734 if (spi->master->cur_msg)
735 spi->master->cur_msg->status = -EIO;
736 spi_finalize_current_transfer(spi->master);
737}
738
739static void lantiq_ssc_handle_err(struct spi_master *master,
740 struct spi_message *message)
741{
742 struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
743
744 /* flush FIFOs on timeout */
745 rx_fifo_flush(spi);
746 tx_fifo_flush(spi);
747}
748
749static void lantiq_ssc_set_cs(struct spi_device *spidev, bool enable)
750{
751 struct lantiq_ssc_spi *spi = spi_master_get_devdata(spidev->master);
752 unsigned int cs = spidev->chip_select;
753 u32 fgpo;
754
755 if (!!(spidev->mode & SPI_CS_HIGH) == enable)
756 fgpo = (1 << (cs - spi->base_cs));
757 else
758 fgpo = (1 << (cs - spi->base_cs + SPI_FGPO_SETOUTN_S));
759
760 lantiq_ssc_writel(spi, fgpo, SPI_FPGO);
761}
762
763static int lantiq_ssc_transfer_one(struct spi_master *master,
764 struct spi_device *spidev,
765 struct spi_transfer *t)
766{
767 struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
768
769 hw_setup_transfer(spi, spidev, t);
770
771 return transfer_start(spi, spidev, t);
772}
773
774static const struct lantiq_ssc_hwcfg lantiq_ssc_xway = {
775 .irnen_r = SPI_IRNEN_R_XWAY,
776 .irnen_t = SPI_IRNEN_T_XWAY,
777};
778
779static const struct lantiq_ssc_hwcfg lantiq_ssc_xrx = {
780 .irnen_r = SPI_IRNEN_R_XRX,
781 .irnen_t = SPI_IRNEN_T_XRX,
782};
783
784static const struct of_device_id lantiq_ssc_match[] = {
785 { .compatible = "lantiq,ase-spi", .data = &lantiq_ssc_xway, },
786 { .compatible = "lantiq,falcon-spi", .data = &lantiq_ssc_xrx, },
787 { .compatible = "lantiq,xrx100-spi", .data = &lantiq_ssc_xrx, },
788 {},
789};
790MODULE_DEVICE_TABLE(of, lantiq_ssc_match);
791
792static int lantiq_ssc_probe(struct platform_device *pdev)
793{
794 struct device *dev = &pdev->dev;
795 struct spi_master *master;
796 struct resource *res;
797 struct lantiq_ssc_spi *spi;
798 const struct lantiq_ssc_hwcfg *hwcfg;
799 const struct of_device_id *match;
800 int err, rx_irq, tx_irq, err_irq;
801 u32 id, supports_dma, revision;
802 unsigned int num_cs;
803
804 match = of_match_device(lantiq_ssc_match, dev);
805 if (!match) {
806 dev_err(dev, "no device match\n");
807 return -EINVAL;
808 }
809 hwcfg = match->data;
810
811 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
812 if (!res) {
813 dev_err(dev, "failed to get resources\n");
814 return -ENXIO;
815 }
816
817 rx_irq = platform_get_irq_byname(pdev, SPI_RX_IRQ_NAME);
818 if (rx_irq < 0) {
819 dev_err(dev, "failed to get %s\n", SPI_RX_IRQ_NAME);
820 return -ENXIO;
821 }
822
823 tx_irq = platform_get_irq_byname(pdev, SPI_TX_IRQ_NAME);
824 if (tx_irq < 0) {
825 dev_err(dev, "failed to get %s\n", SPI_TX_IRQ_NAME);
826 return -ENXIO;
827 }
828
829 err_irq = platform_get_irq_byname(pdev, SPI_ERR_IRQ_NAME);
830 if (err_irq < 0) {
831 dev_err(dev, "failed to get %s\n", SPI_ERR_IRQ_NAME);
832 return -ENXIO;
833 }
834
835 master = spi_alloc_master(dev, sizeof(struct lantiq_ssc_spi));
836 if (!master)
837 return -ENOMEM;
838
839 spi = spi_master_get_devdata(master);
840 spi->master = master;
841 spi->dev = dev;
842 spi->hwcfg = hwcfg;
843 platform_set_drvdata(pdev, spi);
844
845 spi->regbase = devm_ioremap_resource(dev, res);
846 if (IS_ERR(spi->regbase)) {
847 err = PTR_ERR(spi->regbase);
848 goto err_master_put;
849 }
850
851 err = devm_request_irq(dev, rx_irq, lantiq_ssc_xmit_interrupt,
852 0, SPI_RX_IRQ_NAME, spi);
853 if (err)
854 goto err_master_put;
855
856 err = devm_request_irq(dev, tx_irq, lantiq_ssc_xmit_interrupt,
857 0, SPI_TX_IRQ_NAME, spi);
858 if (err)
859 goto err_master_put;
860
861 err = devm_request_irq(dev, err_irq, lantiq_ssc_err_interrupt,
862 0, SPI_ERR_IRQ_NAME, spi);
863 if (err)
864 goto err_master_put;
865
866 spi->spi_clk = devm_clk_get(dev, "gate");
867 if (IS_ERR(spi->spi_clk)) {
868 err = PTR_ERR(spi->spi_clk);
869 goto err_master_put;
870 }
871 err = clk_prepare_enable(spi->spi_clk);
872 if (err)
873 goto err_master_put;
874
875 /*
876 * Use the old clk_get_fpi() function on Lantiq platform, till it
877 * supports common clk.
878 */
879#if defined(CONFIG_LANTIQ) && !defined(CONFIG_COMMON_CLK)
880 spi->fpi_clk = clk_get_fpi();
881#else
882 spi->fpi_clk = clk_get(dev, "freq");
883#endif
884 if (IS_ERR(spi->fpi_clk)) {
885 err = PTR_ERR(spi->fpi_clk);
886 goto err_clk_disable;
887 }
888
889 num_cs = 8;
890 of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
891
892 spi->base_cs = 1;
893 of_property_read_u32(pdev->dev.of_node, "base-cs", &spi->base_cs);
894
895 spin_lock_init(&spi->lock);
896 spi->bits_per_word = 8;
897 spi->speed_hz = 0;
898
899 master->dev.of_node = pdev->dev.of_node;
900 master->num_chipselect = num_cs;
901 master->setup = lantiq_ssc_setup;
902 master->set_cs = lantiq_ssc_set_cs;
903 master->handle_err = lantiq_ssc_handle_err;
904 master->prepare_message = lantiq_ssc_prepare_message;
905 master->unprepare_message = lantiq_ssc_unprepare_message;
906 master->transfer_one = lantiq_ssc_transfer_one;
907 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH |
908 SPI_LOOP;
909 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 8) |
910 SPI_BPW_MASK(16) | SPI_BPW_MASK(32);
911
912 spi->wq = alloc_ordered_workqueue(dev_name(dev), 0);
913 if (!spi->wq) {
914 err = -ENOMEM;
915 goto err_clk_put;
916 }
917 INIT_WORK(&spi->work, lantiq_ssc_bussy_work);
918
919 id = lantiq_ssc_readl(spi, SPI_ID);
920 spi->tx_fifo_size = (id & SPI_ID_TXFS_M) >> SPI_ID_TXFS_S;
921 spi->rx_fifo_size = (id & SPI_ID_RXFS_M) >> SPI_ID_RXFS_S;
922 supports_dma = (id & SPI_ID_CFG_M) >> SPI_ID_CFG_S;
923 revision = id & SPI_ID_REV_M;
924
925 lantiq_ssc_hw_init(spi);
926
927 dev_info(dev,
928 "Lantiq SSC SPI controller (Rev %i, TXFS %u, RXFS %u, DMA %u)\n",
929 revision, spi->tx_fifo_size, spi->rx_fifo_size, supports_dma);
930
931 err = devm_spi_register_master(dev, master);
932 if (err) {
933 dev_err(dev, "failed to register spi_master\n");
934 goto err_wq_destroy;
935 }
936
937 return 0;
938
939err_wq_destroy:
940 destroy_workqueue(spi->wq);
941err_clk_put:
942 clk_put(spi->fpi_clk);
943err_clk_disable:
944 clk_disable_unprepare(spi->spi_clk);
945err_master_put:
946 spi_master_put(master);
947
948 return err;
949}
950
951static int lantiq_ssc_remove(struct platform_device *pdev)
952{
953 struct lantiq_ssc_spi *spi = platform_get_drvdata(pdev);
954
955 lantiq_ssc_writel(spi, 0, SPI_IRNEN);
956 lantiq_ssc_writel(spi, 0, SPI_CLC);
957 rx_fifo_flush(spi);
958 tx_fifo_flush(spi);
959 hw_enter_config_mode(spi);
960
961 destroy_workqueue(spi->wq);
962 clk_disable_unprepare(spi->spi_clk);
963 clk_put(spi->fpi_clk);
964
965 return 0;
966}
967
968static struct platform_driver lantiq_ssc_driver = {
969 .probe = lantiq_ssc_probe,
970 .remove = lantiq_ssc_remove,
971 .driver = {
972 .name = "spi-lantiq-ssc",
973 .owner = THIS_MODULE,
974 .of_match_table = lantiq_ssc_match,
975 },
976};
977module_platform_driver(lantiq_ssc_driver);
978
979MODULE_DESCRIPTION("Lantiq SSC SPI controller driver");
980MODULE_AUTHOR("Daniel Schwierzeck <daniel.schwierzeck@gmail.com>");
981MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>");
982MODULE_LICENSE("GPL");
983MODULE_ALIAS("platform:spi-lantiq-ssc");
diff --git a/drivers/spi/spi-mpc52xx.c b/drivers/spi/spi-mpc52xx.c
index c36002110c30..e8b59ce4dc3a 100644
--- a/drivers/spi/spi-mpc52xx.c
+++ b/drivers/spi/spi-mpc52xx.c
@@ -437,8 +437,9 @@ static int mpc52xx_spi_probe(struct platform_device *op)
437 ms->gpio_cs_count = of_gpio_count(op->dev.of_node); 437 ms->gpio_cs_count = of_gpio_count(op->dev.of_node);
438 if (ms->gpio_cs_count > 0) { 438 if (ms->gpio_cs_count > 0) {
439 master->num_chipselect = ms->gpio_cs_count; 439 master->num_chipselect = ms->gpio_cs_count;
440 ms->gpio_cs = kmalloc(ms->gpio_cs_count * sizeof(unsigned int), 440 ms->gpio_cs = kmalloc_array(ms->gpio_cs_count,
441 GFP_KERNEL); 441 sizeof(*ms->gpio_cs),
442 GFP_KERNEL);
442 if (!ms->gpio_cs) { 443 if (!ms->gpio_cs) {
443 rc = -ENOMEM; 444 rc = -ENOMEM;
444 goto err_alloc_gpio; 445 goto err_alloc_gpio;
@@ -448,8 +449,7 @@ static int mpc52xx_spi_probe(struct platform_device *op)
448 gpio_cs = of_get_gpio(op->dev.of_node, i); 449 gpio_cs = of_get_gpio(op->dev.of_node, i);
449 if (gpio_cs < 0) { 450 if (gpio_cs < 0) {
450 dev_err(&op->dev, 451 dev_err(&op->dev,
451 "could not parse the gpio field " 452 "could not parse the gpio field in oftree\n");
452 "in oftree\n");
453 rc = -ENODEV; 453 rc = -ENODEV;
454 goto err_gpio; 454 goto err_gpio;
455 } 455 }
@@ -457,8 +457,8 @@ static int mpc52xx_spi_probe(struct platform_device *op)
457 rc = gpio_request(gpio_cs, dev_name(&op->dev)); 457 rc = gpio_request(gpio_cs, dev_name(&op->dev));
458 if (rc) { 458 if (rc) {
459 dev_err(&op->dev, 459 dev_err(&op->dev,
460 "can't request spi cs gpio #%d " 460 "can't request spi cs gpio #%d on gpio line %d\n",
461 "on gpio line %d\n", i, gpio_cs); 461 i, gpio_cs);
462 goto err_gpio; 462 goto err_gpio;
463 } 463 }
464 464
diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c
index 899d7a8f0889..278867a31950 100644
--- a/drivers/spi/spi-mt65xx.c
+++ b/drivers/spi/spi-mt65xx.c
@@ -73,7 +73,7 @@
73#define MTK_SPI_IDLE 0 73#define MTK_SPI_IDLE 0
74#define MTK_SPI_PAUSED 1 74#define MTK_SPI_PAUSED 1
75 75
76#define MTK_SPI_MAX_FIFO_SIZE 32 76#define MTK_SPI_MAX_FIFO_SIZE 32U
77#define MTK_SPI_PACKET_SIZE 1024 77#define MTK_SPI_PACKET_SIZE 1024
78 78
79struct mtk_spi_compatible { 79struct mtk_spi_compatible {
@@ -333,7 +333,7 @@ static int mtk_spi_fifo_transfer(struct spi_master *master,
333 struct mtk_spi *mdata = spi_master_get_devdata(master); 333 struct mtk_spi *mdata = spi_master_get_devdata(master);
334 334
335 mdata->cur_transfer = xfer; 335 mdata->cur_transfer = xfer;
336 mdata->xfer_len = xfer->len; 336 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len);
337 mtk_spi_prepare_transfer(master, xfer); 337 mtk_spi_prepare_transfer(master, xfer);
338 mtk_spi_setup_packet(master); 338 mtk_spi_setup_packet(master);
339 339
@@ -410,7 +410,10 @@ static bool mtk_spi_can_dma(struct spi_master *master,
410 struct spi_device *spi, 410 struct spi_device *spi,
411 struct spi_transfer *xfer) 411 struct spi_transfer *xfer)
412{ 412{
413 return xfer->len > MTK_SPI_MAX_FIFO_SIZE; 413 /* Buffers for DMA transactions must be 4-byte aligned */
414 return (xfer->len > MTK_SPI_MAX_FIFO_SIZE &&
415 (unsigned long)xfer->tx_buf % 4 == 0 &&
416 (unsigned long)xfer->rx_buf % 4 == 0);
414} 417}
415 418
416static int mtk_spi_setup(struct spi_device *spi) 419static int mtk_spi_setup(struct spi_device *spi)
@@ -451,7 +454,33 @@ static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id)
451 &reg_val, remainder); 454 &reg_val, remainder);
452 } 455 }
453 } 456 }
454 spi_finalize_current_transfer(master); 457
458 trans->len -= mdata->xfer_len;
459 if (!trans->len) {
460 spi_finalize_current_transfer(master);
461 return IRQ_HANDLED;
462 }
463
464 if (trans->tx_buf)
465 trans->tx_buf += mdata->xfer_len;
466 if (trans->rx_buf)
467 trans->rx_buf += mdata->xfer_len;
468
469 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, trans->len);
470 mtk_spi_setup_packet(master);
471
472 cnt = trans->len / 4;
473 iowrite32_rep(mdata->base + SPI_TX_DATA_REG, trans->tx_buf, cnt);
474
475 remainder = trans->len % 4;
476 if (remainder > 0) {
477 reg_val = 0;
478 memcpy(&reg_val, trans->tx_buf + (cnt * 4), remainder);
479 writel(reg_val, mdata->base + SPI_TX_DATA_REG);
480 }
481
482 mtk_spi_enable_transfer(master);
483
455 return IRQ_HANDLED; 484 return IRQ_HANDLED;
456 } 485 }
457 486
diff --git a/drivers/spi/spi-ppc4xx.c b/drivers/spi/spi-ppc4xx.c
index dd3d0a218d8b..967d94844b30 100644
--- a/drivers/spi/spi-ppc4xx.c
+++ b/drivers/spi/spi-ppc4xx.c
@@ -411,7 +411,7 @@ static int spi_ppc4xx_of_probe(struct platform_device *op)
411 if (num_gpios > 0) { 411 if (num_gpios > 0) {
412 int i; 412 int i;
413 413
414 hw->gpios = kzalloc(sizeof(int) * num_gpios, GFP_KERNEL); 414 hw->gpios = kcalloc(num_gpios, sizeof(*hw->gpios), GFP_KERNEL);
415 if (!hw->gpios) { 415 if (!hw->gpios) {
416 ret = -ENOMEM; 416 ret = -ENOMEM;
417 goto free_master; 417 goto free_master;
@@ -428,8 +428,9 @@ static int spi_ppc4xx_of_probe(struct platform_device *op)
428 /* Real CS - set the initial state. */ 428 /* Real CS - set the initial state. */
429 ret = gpio_request(gpio, np->name); 429 ret = gpio_request(gpio, np->name);
430 if (ret < 0) { 430 if (ret < 0) {
431 dev_err(dev, "can't request gpio " 431 dev_err(dev,
432 "#%d: %d\n", i, ret); 432 "can't request gpio #%d: %d\n",
433 i, ret);
433 goto free_gpios; 434 goto free_gpios;
434 } 435 }
435 436
diff --git a/drivers/spi/spi-pxa2xx-pci.c b/drivers/spi/spi-pxa2xx-pci.c
index 58d2d48e16a5..869f188b02eb 100644
--- a/drivers/spi/spi-pxa2xx-pci.c
+++ b/drivers/spi/spi-pxa2xx-pci.c
@@ -41,6 +41,13 @@ struct pxa_spi_info {
41static struct dw_dma_slave byt_tx_param = { .dst_id = 0 }; 41static struct dw_dma_slave byt_tx_param = { .dst_id = 0 };
42static struct dw_dma_slave byt_rx_param = { .src_id = 1 }; 42static struct dw_dma_slave byt_rx_param = { .src_id = 1 };
43 43
44static struct dw_dma_slave mrfld3_tx_param = { .dst_id = 15 };
45static struct dw_dma_slave mrfld3_rx_param = { .src_id = 14 };
46static struct dw_dma_slave mrfld5_tx_param = { .dst_id = 13 };
47static struct dw_dma_slave mrfld5_rx_param = { .src_id = 12 };
48static struct dw_dma_slave mrfld6_tx_param = { .dst_id = 11 };
49static struct dw_dma_slave mrfld6_rx_param = { .src_id = 10 };
50
44static struct dw_dma_slave bsw0_tx_param = { .dst_id = 0 }; 51static struct dw_dma_slave bsw0_tx_param = { .dst_id = 0 };
45static struct dw_dma_slave bsw0_rx_param = { .src_id = 1 }; 52static struct dw_dma_slave bsw0_rx_param = { .src_id = 1 };
46static struct dw_dma_slave bsw1_tx_param = { .dst_id = 6 }; 53static struct dw_dma_slave bsw1_tx_param = { .dst_id = 6 };
@@ -93,22 +100,39 @@ static int lpss_spi_setup(struct pci_dev *dev, struct pxa_spi_info *c)
93 100
94static int mrfld_spi_setup(struct pci_dev *dev, struct pxa_spi_info *c) 101static int mrfld_spi_setup(struct pci_dev *dev, struct pxa_spi_info *c)
95{ 102{
103 struct pci_dev *dma_dev = pci_get_slot(dev->bus, PCI_DEVFN(21, 0));
104 struct dw_dma_slave *tx, *rx;
105
96 switch (PCI_FUNC(dev->devfn)) { 106 switch (PCI_FUNC(dev->devfn)) {
97 case 0: 107 case 0:
98 c->port_id = 3; 108 c->port_id = 3;
99 c->num_chipselect = 1; 109 c->num_chipselect = 1;
110 c->tx_param = &mrfld3_tx_param;
111 c->rx_param = &mrfld3_rx_param;
100 break; 112 break;
101 case 1: 113 case 1:
102 c->port_id = 5; 114 c->port_id = 5;
103 c->num_chipselect = 4; 115 c->num_chipselect = 4;
116 c->tx_param = &mrfld5_tx_param;
117 c->rx_param = &mrfld5_rx_param;
104 break; 118 break;
105 case 2: 119 case 2:
106 c->port_id = 6; 120 c->port_id = 6;
107 c->num_chipselect = 1; 121 c->num_chipselect = 1;
122 c->tx_param = &mrfld6_tx_param;
123 c->rx_param = &mrfld6_rx_param;
108 break; 124 break;
109 default: 125 default:
110 return -ENODEV; 126 return -ENODEV;
111 } 127 }
128
129 tx = c->tx_param;
130 tx->dma_dev = &dma_dev->dev;
131
132 rx = c->rx_param;
133 rx->dma_dev = &dma_dev->dev;
134
135 c->dma_filter = lpss_dma_filter;
112 return 0; 136 return 0;
113} 137}
114 138
@@ -203,10 +227,16 @@ static int pxa2xx_spi_pci_probe(struct pci_dev *dev,
203 ssp = &spi_pdata.ssp; 227 ssp = &spi_pdata.ssp;
204 ssp->phys_base = pci_resource_start(dev, 0); 228 ssp->phys_base = pci_resource_start(dev, 0);
205 ssp->mmio_base = pcim_iomap_table(dev)[0]; 229 ssp->mmio_base = pcim_iomap_table(dev)[0];
206 ssp->irq = dev->irq;
207 ssp->port_id = (c->port_id >= 0) ? c->port_id : dev->devfn; 230 ssp->port_id = (c->port_id >= 0) ? c->port_id : dev->devfn;
208 ssp->type = c->type; 231 ssp->type = c->type;
209 232
233 pci_set_master(dev);
234
235 ret = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES);
236 if (ret < 0)
237 return ret;
238 ssp->irq = pci_irq_vector(dev, 0);
239
210 snprintf(buf, sizeof(buf), "pxa2xx-spi.%d", ssp->port_id); 240 snprintf(buf, sizeof(buf), "pxa2xx-spi.%d", ssp->port_id);
211 ssp->clk = clk_register_fixed_rate(&dev->dev, buf , NULL, 0, 241 ssp->clk = clk_register_fixed_rate(&dev->dev, buf , NULL, 0,
212 c->max_clk_rate); 242 c->max_clk_rate);
diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index d6239fa718be..47b65d7c4072 100644
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -732,6 +732,20 @@ static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
732 return IRQ_HANDLED; 732 return IRQ_HANDLED;
733} 733}
734 734
735static void handle_bad_msg(struct driver_data *drv_data)
736{
737 pxa2xx_spi_write(drv_data, SSCR0,
738 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
739 pxa2xx_spi_write(drv_data, SSCR1,
740 pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1);
741 if (!pxa25x_ssp_comp(drv_data))
742 pxa2xx_spi_write(drv_data, SSTO, 0);
743 write_SSSR_CS(drv_data, drv_data->clear_sr);
744
745 dev_err(&drv_data->pdev->dev,
746 "bad message state in interrupt handler\n");
747}
748
735static irqreturn_t ssp_int(int irq, void *dev_id) 749static irqreturn_t ssp_int(int irq, void *dev_id)
736{ 750{
737 struct driver_data *drv_data = dev_id; 751 struct driver_data *drv_data = dev_id;
@@ -771,21 +785,11 @@ static irqreturn_t ssp_int(int irq, void *dev_id)
771 if (!(status & mask)) 785 if (!(status & mask))
772 return IRQ_NONE; 786 return IRQ_NONE;
773 787
774 if (!drv_data->master->cur_msg) { 788 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1);
775 789 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
776 pxa2xx_spi_write(drv_data, SSCR0,
777 pxa2xx_spi_read(drv_data, SSCR0)
778 & ~SSCR0_SSE);
779 pxa2xx_spi_write(drv_data, SSCR1,
780 pxa2xx_spi_read(drv_data, SSCR1)
781 & ~drv_data->int_cr1);
782 if (!pxa25x_ssp_comp(drv_data))
783 pxa2xx_spi_write(drv_data, SSTO, 0);
784 write_SSSR_CS(drv_data, drv_data->clear_sr);
785
786 dev_err(&drv_data->pdev->dev,
787 "bad message state in interrupt handler\n");
788 790
791 if (!drv_data->master->cur_msg) {
792 handle_bad_msg(drv_data);
789 /* Never fail */ 793 /* Never fail */
790 return IRQ_HANDLED; 794 return IRQ_HANDLED;
791 } 795 }
@@ -1458,6 +1462,10 @@ static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
1458 { PCI_VDEVICE(INTEL, 0x1ac2), LPSS_BXT_SSP }, 1462 { PCI_VDEVICE(INTEL, 0x1ac2), LPSS_BXT_SSP },
1459 { PCI_VDEVICE(INTEL, 0x1ac4), LPSS_BXT_SSP }, 1463 { PCI_VDEVICE(INTEL, 0x1ac4), LPSS_BXT_SSP },
1460 { PCI_VDEVICE(INTEL, 0x1ac6), LPSS_BXT_SSP }, 1464 { PCI_VDEVICE(INTEL, 0x1ac6), LPSS_BXT_SSP },
1465 /* GLK */
1466 { PCI_VDEVICE(INTEL, 0x31c2), LPSS_BXT_SSP },
1467 { PCI_VDEVICE(INTEL, 0x31c4), LPSS_BXT_SSP },
1468 { PCI_VDEVICE(INTEL, 0x31c6), LPSS_BXT_SSP },
1461 /* APL */ 1469 /* APL */
1462 { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP }, 1470 { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP },
1463 { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP }, 1471 { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP },
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index 0f89c2169c24..acf31f36b898 100644
--- a/drivers/spi/spi-rockchip.c
+++ b/drivers/spi/spi-rockchip.c
@@ -17,6 +17,7 @@
17#include <linux/dmaengine.h> 17#include <linux/dmaengine.h>
18#include <linux/module.h> 18#include <linux/module.h>
19#include <linux/of.h> 19#include <linux/of.h>
20#include <linux/pinctrl/consumer.h>
20#include <linux/platform_device.h> 21#include <linux/platform_device.h>
21#include <linux/spi/spi.h> 22#include <linux/spi/spi.h>
22#include <linux/pm_runtime.h> 23#include <linux/pm_runtime.h>
@@ -843,6 +844,8 @@ static int rockchip_spi_suspend(struct device *dev)
843 clk_disable_unprepare(rs->apb_pclk); 844 clk_disable_unprepare(rs->apb_pclk);
844 } 845 }
845 846
847 pinctrl_pm_select_sleep_state(dev);
848
846 return ret; 849 return ret;
847} 850}
848 851
@@ -852,6 +855,8 @@ static int rockchip_spi_resume(struct device *dev)
852 struct spi_master *master = dev_get_drvdata(dev); 855 struct spi_master *master = dev_get_drvdata(dev);
853 struct rockchip_spi *rs = spi_master_get_devdata(master); 856 struct rockchip_spi *rs = spi_master_get_devdata(master);
854 857
858 pinctrl_pm_select_default_state(dev);
859
855 if (!pm_runtime_suspended(dev)) { 860 if (!pm_runtime_suspended(dev)) {
856 ret = clk_prepare_enable(rs->apb_pclk); 861 ret = clk_prepare_enable(rs->apb_pclk);
857 if (ret < 0) 862 if (ret < 0)
diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c
index 9daf50031737..2a10b3f94ff7 100644
--- a/drivers/spi/spi-rspi.c
+++ b/drivers/spi/spi-rspi.c
@@ -808,7 +808,7 @@ static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer)
808 for (i = 0; i < len; i++) 808 for (i = 0; i < len; i++)
809 rspi_write_data(rspi, *tx++); 809 rspi_write_data(rspi, *tx++);
810 } else { 810 } else {
811 ret = rspi_pio_transfer(rspi, tx, NULL, n); 811 ret = rspi_pio_transfer(rspi, tx, NULL, len);
812 if (ret < 0) 812 if (ret < 0)
813 return ret; 813 return ret;
814 } 814 }
@@ -845,10 +845,9 @@ static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer)
845 for (i = 0; i < len; i++) 845 for (i = 0; i < len; i++)
846 *rx++ = rspi_read_data(rspi); 846 *rx++ = rspi_read_data(rspi);
847 } else { 847 } else {
848 ret = rspi_pio_transfer(rspi, NULL, rx, n); 848 ret = rspi_pio_transfer(rspi, NULL, rx, len);
849 if (ret < 0) 849 if (ret < 0)
850 return ret; 850 return ret;
851 *rx++ = ret;
852 } 851 }
853 n -= len; 852 n -= len;
854 } 853 }
@@ -1227,10 +1226,8 @@ static int rspi_probe(struct platform_device *pdev)
1227 const struct spi_ops *ops; 1226 const struct spi_ops *ops;
1228 1227
1229 master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data)); 1228 master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data));
1230 if (master == NULL) { 1229 if (master == NULL)
1231 dev_err(&pdev->dev, "spi_alloc_master error.\n");
1232 return -ENOMEM; 1230 return -ENOMEM;
1233 }
1234 1231
1235 of_id = of_match_device(rspi_of_match, &pdev->dev); 1232 of_id = of_match_device(rspi_of_match, &pdev->dev);
1236 if (of_id) { 1233 if (of_id) {
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 28dfdce4beae..b392cca8fa4f 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -341,43 +341,16 @@ static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable)
341static int s3c64xx_spi_prepare_transfer(struct spi_master *spi) 341static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
342{ 342{
343 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi); 343 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
344 struct device *dev = &sdd->pdev->dev;
345 344
346 if (is_polling(sdd)) 345 if (is_polling(sdd))
347 return 0; 346 return 0;
348 347
349 /* Acquire DMA channels */
350 sdd->rx_dma.ch = dma_request_slave_channel(dev, "rx");
351 if (!sdd->rx_dma.ch) {
352 dev_err(dev, "Failed to get RX DMA channel\n");
353 return -EBUSY;
354 }
355 spi->dma_rx = sdd->rx_dma.ch; 348 spi->dma_rx = sdd->rx_dma.ch;
356
357 sdd->tx_dma.ch = dma_request_slave_channel(dev, "tx");
358 if (!sdd->tx_dma.ch) {
359 dev_err(dev, "Failed to get TX DMA channel\n");
360 dma_release_channel(sdd->rx_dma.ch);
361 return -EBUSY;
362 }
363 spi->dma_tx = sdd->tx_dma.ch; 349 spi->dma_tx = sdd->tx_dma.ch;
364 350
365 return 0; 351 return 0;
366} 352}
367 353
368static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
369{
370 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
371
372 /* Free DMA channels */
373 if (!is_polling(sdd)) {
374 dma_release_channel(sdd->rx_dma.ch);
375 dma_release_channel(sdd->tx_dma.ch);
376 }
377
378 return 0;
379}
380
381static bool s3c64xx_spi_can_dma(struct spi_master *master, 354static bool s3c64xx_spi_can_dma(struct spi_master *master,
382 struct spi_device *spi, 355 struct spi_device *spi,
383 struct spi_transfer *xfer) 356 struct spi_transfer *xfer)
@@ -996,7 +969,7 @@ static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
996 sci->num_cs = temp; 969 sci->num_cs = temp;
997 } 970 }
998 971
999 sci->no_cs = of_property_read_bool(dev->of_node, "broken-cs"); 972 sci->no_cs = of_property_read_bool(dev->of_node, "no-cs-readback");
1000 973
1001 return sci; 974 return sci;
1002} 975}
@@ -1094,7 +1067,6 @@ static int s3c64xx_spi_probe(struct platform_device *pdev)
1094 master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer; 1067 master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1095 master->prepare_message = s3c64xx_spi_prepare_message; 1068 master->prepare_message = s3c64xx_spi_prepare_message;
1096 master->transfer_one = s3c64xx_spi_transfer_one; 1069 master->transfer_one = s3c64xx_spi_transfer_one;
1097 master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
1098 master->num_chipselect = sci->num_cs; 1070 master->num_chipselect = sci->num_cs;
1099 master->dma_alignment = 8; 1071 master->dma_alignment = 8;
1100 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | 1072 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
@@ -1161,6 +1133,24 @@ static int s3c64xx_spi_probe(struct platform_device *pdev)
1161 } 1133 }
1162 } 1134 }
1163 1135
1136 if (!is_polling(sdd)) {
1137 /* Acquire DMA channels */
1138 sdd->rx_dma.ch = dma_request_slave_channel_reason(&pdev->dev,
1139 "rx");
1140 if (IS_ERR(sdd->rx_dma.ch)) {
1141 dev_err(&pdev->dev, "Failed to get RX DMA channel\n");
1142 ret = PTR_ERR(sdd->rx_dma.ch);
1143 goto err_disable_io_clk;
1144 }
1145 sdd->tx_dma.ch = dma_request_slave_channel_reason(&pdev->dev,
1146 "tx");
1147 if (IS_ERR(sdd->tx_dma.ch)) {
1148 dev_err(&pdev->dev, "Failed to get TX DMA channel\n");
1149 ret = PTR_ERR(sdd->tx_dma.ch);
1150 goto err_release_rx_dma;
1151 }
1152 }
1153
1164 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT); 1154 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1165 pm_runtime_use_autosuspend(&pdev->dev); 1155 pm_runtime_use_autosuspend(&pdev->dev);
1166 pm_runtime_set_active(&pdev->dev); 1156 pm_runtime_set_active(&pdev->dev);
@@ -1206,6 +1196,12 @@ err_pm_put:
1206 pm_runtime_disable(&pdev->dev); 1196 pm_runtime_disable(&pdev->dev);
1207 pm_runtime_set_suspended(&pdev->dev); 1197 pm_runtime_set_suspended(&pdev->dev);
1208 1198
1199 if (!is_polling(sdd))
1200 dma_release_channel(sdd->tx_dma.ch);
1201err_release_rx_dma:
1202 if (!is_polling(sdd))
1203 dma_release_channel(sdd->rx_dma.ch);
1204err_disable_io_clk:
1209 clk_disable_unprepare(sdd->ioclk); 1205 clk_disable_unprepare(sdd->ioclk);
1210err_disable_src_clk: 1206err_disable_src_clk:
1211 clk_disable_unprepare(sdd->src_clk); 1207 clk_disable_unprepare(sdd->src_clk);
@@ -1226,6 +1222,11 @@ static int s3c64xx_spi_remove(struct platform_device *pdev)
1226 1222
1227 writel(0, sdd->regs + S3C64XX_SPI_INT_EN); 1223 writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1228 1224
1225 if (!is_polling(sdd)) {
1226 dma_release_channel(sdd->rx_dma.ch);
1227 dma_release_channel(sdd->tx_dma.ch);
1228 }
1229
1229 clk_disable_unprepare(sdd->ioclk); 1230 clk_disable_unprepare(sdd->ioclk);
1230 1231
1231 clk_disable_unprepare(sdd->src_clk); 1232 clk_disable_unprepare(sdd->src_clk);
diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c
index 1f00eeb0b5a3..2ce15ca97782 100644
--- a/drivers/spi/spi-sh-msiof.c
+++ b/drivers/spi/spi-sh-msiof.c
@@ -1164,10 +1164,8 @@ static int sh_msiof_spi_probe(struct platform_device *pdev)
1164 int ret; 1164 int ret;
1165 1165
1166 master = spi_alloc_master(&pdev->dev, sizeof(struct sh_msiof_spi_priv)); 1166 master = spi_alloc_master(&pdev->dev, sizeof(struct sh_msiof_spi_priv));
1167 if (master == NULL) { 1167 if (master == NULL)
1168 dev_err(&pdev->dev, "failed to allocate spi master\n");
1169 return -ENOMEM; 1168 return -ENOMEM;
1170 }
1171 1169
1172 p = spi_master_get_devdata(master); 1170 p = spi_master_get_devdata(master);
1173 1171
diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index ec6fb09e2e17..ad76a44fee6f 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -652,7 +652,8 @@ static int ti_qspi_probe(struct platform_device *pdev)
652 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 652 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
653 if (r == NULL) { 653 if (r == NULL) {
654 dev_err(&pdev->dev, "missing platform data\n"); 654 dev_err(&pdev->dev, "missing platform data\n");
655 return -ENODEV; 655 ret = -ENODEV;
656 goto free_master;
656 } 657 }
657 } 658 }
658 659
@@ -669,7 +670,8 @@ static int ti_qspi_probe(struct platform_device *pdev)
669 irq = platform_get_irq(pdev, 0); 670 irq = platform_get_irq(pdev, 0);
670 if (irq < 0) { 671 if (irq < 0) {
671 dev_err(&pdev->dev, "no irq resource?\n"); 672 dev_err(&pdev->dev, "no irq resource?\n");
672 return irq; 673 ret = irq;
674 goto free_master;
673 } 675 }
674 676
675 mutex_init(&qspi->list_lock); 677 mutex_init(&qspi->list_lock);
@@ -685,15 +687,17 @@ static int ti_qspi_probe(struct platform_device *pdev)
685 qspi->ctrl_base = 687 qspi->ctrl_base =
686 syscon_regmap_lookup_by_phandle(np, 688 syscon_regmap_lookup_by_phandle(np,
687 "syscon-chipselects"); 689 "syscon-chipselects");
688 if (IS_ERR(qspi->ctrl_base)) 690 if (IS_ERR(qspi->ctrl_base)) {
689 return PTR_ERR(qspi->ctrl_base); 691 ret = PTR_ERR(qspi->ctrl_base);
692 goto free_master;
693 }
690 ret = of_property_read_u32_index(np, 694 ret = of_property_read_u32_index(np,
691 "syscon-chipselects", 695 "syscon-chipselects",
692 1, &qspi->ctrl_reg); 696 1, &qspi->ctrl_reg);
693 if (ret) { 697 if (ret) {
694 dev_err(&pdev->dev, 698 dev_err(&pdev->dev,
695 "couldn't get ctrl_mod reg index\n"); 699 "couldn't get ctrl_mod reg index\n");
696 return ret; 700 goto free_master;
697 } 701 }
698 } 702 }
699 703
@@ -714,9 +718,10 @@ static int ti_qspi_probe(struct platform_device *pdev)
714 dma_cap_set(DMA_MEMCPY, mask); 718 dma_cap_set(DMA_MEMCPY, mask);
715 719
716 qspi->rx_chan = dma_request_chan_by_mask(&mask); 720 qspi->rx_chan = dma_request_chan_by_mask(&mask);
717 if (!qspi->rx_chan) { 721 if (IS_ERR(qspi->rx_chan)) {
718 dev_err(qspi->dev, 722 dev_err(qspi->dev,
719 "No Rx DMA available, trying mmap mode\n"); 723 "No Rx DMA available, trying mmap mode\n");
724 qspi->rx_chan = NULL;
720 ret = 0; 725 ret = 0;
721 goto no_dma; 726 goto no_dma;
722 } 727 }
@@ -742,6 +747,7 @@ no_dma:
742 if (!ret) 747 if (!ret)
743 return 0; 748 return 0;
744 749
750 pm_runtime_disable(&pdev->dev);
745free_master: 751free_master:
746 spi_master_put(master); 752 spi_master_put(master);
747 return ret; 753 return ret;
diff --git a/drivers/spi/spi-topcliff-pch.c b/drivers/spi/spi-topcliff-pch.c
index fcb991034c3d..97d137591b18 100644
--- a/drivers/spi/spi-topcliff-pch.c
+++ b/drivers/spi/spi-topcliff-pch.c
@@ -591,7 +591,6 @@ static void pch_spi_set_tx(struct pch_spi_data *data, int *bpw)
591 591
592 if (!data->pkt_rx_buff) { 592 if (!data->pkt_rx_buff) {
593 /* flush queue and set status of all transfers to -ENOMEM */ 593 /* flush queue and set status of all transfers to -ENOMEM */
594 dev_err(&data->master->dev, "%s :kzalloc failed\n", __func__);
595 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) { 594 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
596 pmsg->status = -ENOMEM; 595 pmsg->status = -ENOMEM;
597 596
@@ -622,8 +621,9 @@ static void pch_spi_set_tx(struct pch_spi_data *data, int *bpw)
622 if (n_writes > PCH_MAX_FIFO_DEPTH) 621 if (n_writes > PCH_MAX_FIFO_DEPTH)
623 n_writes = PCH_MAX_FIFO_DEPTH; 622 n_writes = PCH_MAX_FIFO_DEPTH;
624 623
625 dev_dbg(&data->master->dev, "\n%s:Pulling down SSN low - writing " 624 dev_dbg(&data->master->dev,
626 "0x2 to SSNXCR\n", __func__); 625 "\n%s:Pulling down SSN low - writing 0x2 to SSNXCR\n",
626 __func__);
627 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW); 627 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
628 628
629 for (j = 0; j < n_writes; j++) 629 for (j = 0; j < n_writes; j++)
@@ -915,7 +915,6 @@ static void pch_spi_release_dma(struct pch_spi_data *data)
915 dma_release_channel(dma->chan_rx); 915 dma_release_channel(dma->chan_rx);
916 dma->chan_rx = NULL; 916 dma->chan_rx = NULL;
917 } 917 }
918 return;
919} 918}
920 919
921static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw) 920static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw)
@@ -1008,7 +1007,7 @@ static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw)
1008 spin_unlock_irqrestore(&data->lock, flags); 1007 spin_unlock_irqrestore(&data->lock, flags);
1009 1008
1010 /* RX */ 1009 /* RX */
1011 dma->sg_rx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC); 1010 dma->sg_rx_p = kcalloc(num, sizeof(*dma->sg_rx_p), GFP_ATOMIC);
1012 sg_init_table(dma->sg_rx_p, num); /* Initialize SG table */ 1011 sg_init_table(dma->sg_rx_p, num); /* Initialize SG table */
1013 /* offset, length setting */ 1012 /* offset, length setting */
1014 sg = dma->sg_rx_p; 1013 sg = dma->sg_rx_p;
@@ -1068,7 +1067,7 @@ static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw)
1068 head = 0; 1067 head = 0;
1069 } 1068 }
1070 1069
1071 dma->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC); 1070 dma->sg_tx_p = kcalloc(num, sizeof(*dma->sg_tx_p), GFP_ATOMIC);
1072 sg_init_table(dma->sg_tx_p, num); /* Initialize SG table */ 1071 sg_init_table(dma->sg_tx_p, num); /* Initialize SG table */
1073 /* offset, length setting */ 1072 /* offset, length setting */
1074 sg = dma->sg_tx_p; 1073 sg = dma->sg_tx_p;
@@ -1181,14 +1180,16 @@ static void pch_spi_process_messages(struct work_struct *pwork)
1181 data->cur_trans = 1180 data->cur_trans =
1182 list_entry(data->current_msg->transfers.next, 1181 list_entry(data->current_msg->transfers.next,
1183 struct spi_transfer, transfer_list); 1182 struct spi_transfer, transfer_list);
1184 dev_dbg(&data->master->dev, "%s " 1183 dev_dbg(&data->master->dev,
1185 ":Getting 1st transfer message\n", __func__); 1184 "%s :Getting 1st transfer message\n",
1185 __func__);
1186 } else { 1186 } else {
1187 data->cur_trans = 1187 data->cur_trans =
1188 list_entry(data->cur_trans->transfer_list.next, 1188 list_entry(data->cur_trans->transfer_list.next,
1189 struct spi_transfer, transfer_list); 1189 struct spi_transfer, transfer_list);
1190 dev_dbg(&data->master->dev, "%s " 1190 dev_dbg(&data->master->dev,
1191 ":Getting next transfer message\n", __func__); 1191 "%s :Getting next transfer message\n",
1192 __func__);
1192 } 1193 }
1193 spin_unlock(&data->lock); 1194 spin_unlock(&data->lock);
1194 1195
@@ -1233,9 +1234,8 @@ static void pch_spi_process_messages(struct work_struct *pwork)
1233 1234
1234 /* check for delay */ 1235 /* check for delay */
1235 if (data->cur_trans->delay_usecs) { 1236 if (data->cur_trans->delay_usecs) {
1236 dev_dbg(&data->master->dev, "%s:" 1237 dev_dbg(&data->master->dev, "%s:delay in usec=%d\n",
1237 "delay in usec=%d\n", __func__, 1238 __func__, data->cur_trans->delay_usecs);
1238 data->cur_trans->delay_usecs);
1239 udelay(data->cur_trans->delay_usecs); 1239 udelay(data->cur_trans->delay_usecs);
1240 } 1240 }
1241 1241
@@ -1292,7 +1292,6 @@ static void pch_free_dma_buf(struct pch_spi_board_data *board_dat,
1292 if (dma->rx_buf_dma) 1292 if (dma->rx_buf_dma)
1293 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE, 1293 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1294 dma->rx_buf_virt, dma->rx_buf_dma); 1294 dma->rx_buf_virt, dma->rx_buf_dma);
1295 return;
1296} 1295}
1297 1296
1298static void pch_alloc_dma_buf(struct pch_spi_board_data *board_dat, 1297static void pch_alloc_dma_buf(struct pch_spi_board_data *board_dat,
@@ -1541,11 +1540,11 @@ static int pch_spi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1541 int i; 1540 int i;
1542 struct pch_pd_dev_save *pd_dev_save; 1541 struct pch_pd_dev_save *pd_dev_save;
1543 1542
1544 pd_dev_save = kzalloc(sizeof(struct pch_pd_dev_save), GFP_KERNEL); 1543 pd_dev_save = kzalloc(sizeof(*pd_dev_save), GFP_KERNEL);
1545 if (!pd_dev_save) 1544 if (!pd_dev_save)
1546 return -ENOMEM; 1545 return -ENOMEM;
1547 1546
1548 board_dat = kzalloc(sizeof(struct pch_spi_board_data), GFP_KERNEL); 1547 board_dat = kzalloc(sizeof(*board_dat), GFP_KERNEL);
1549 if (!board_dat) { 1548 if (!board_dat) {
1550 retval = -ENOMEM; 1549 retval = -ENOMEM;
1551 goto err_no_mem; 1550 goto err_no_mem;
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 656dd3e3220c..f274df9e0e3e 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -621,8 +621,10 @@ void spi_unregister_device(struct spi_device *spi)
621 if (!spi) 621 if (!spi)
622 return; 622 return;
623 623
624 if (spi->dev.of_node) 624 if (spi->dev.of_node) {
625 of_node_clear_flag(spi->dev.of_node, OF_POPULATED); 625 of_node_clear_flag(spi->dev.of_node, OF_POPULATED);
626 of_node_put(spi->dev.of_node);
627 }
626 if (ACPI_COMPANION(&spi->dev)) 628 if (ACPI_COMPANION(&spi->dev))
627 acpi_device_clear_enumerated(ACPI_COMPANION(&spi->dev)); 629 acpi_device_clear_enumerated(ACPI_COMPANION(&spi->dev));
628 device_unregister(&spi->dev); 630 device_unregister(&spi->dev);
@@ -672,7 +674,7 @@ int spi_register_board_info(struct spi_board_info const *info, unsigned n)
672 if (!n) 674 if (!n)
673 return -EINVAL; 675 return -EINVAL;
674 676
675 bi = kzalloc(n * sizeof(*bi), GFP_KERNEL); 677 bi = kcalloc(n, sizeof(*bi), GFP_KERNEL);
676 if (!bi) 678 if (!bi)
677 return -ENOMEM; 679 return -ENOMEM;
678 680
@@ -805,12 +807,12 @@ static int __spi_map_msg(struct spi_master *master, struct spi_message *msg)
805 if (master->dma_tx) 807 if (master->dma_tx)
806 tx_dev = master->dma_tx->device->dev; 808 tx_dev = master->dma_tx->device->dev;
807 else 809 else
808 tx_dev = &master->dev; 810 tx_dev = master->dev.parent;
809 811
810 if (master->dma_rx) 812 if (master->dma_rx)
811 rx_dev = master->dma_rx->device->dev; 813 rx_dev = master->dma_rx->device->dev;
812 else 814 else
813 rx_dev = &master->dev; 815 rx_dev = master->dev.parent;
814 816
815 list_for_each_entry(xfer, &msg->transfers, transfer_list) { 817 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
816 if (!master->can_dma(master, msg->spi, xfer)) 818 if (!master->can_dma(master, msg->spi, xfer))
@@ -852,12 +854,12 @@ static int __spi_unmap_msg(struct spi_master *master, struct spi_message *msg)
852 if (master->dma_tx) 854 if (master->dma_tx)
853 tx_dev = master->dma_tx->device->dev; 855 tx_dev = master->dma_tx->device->dev;
854 else 856 else
855 tx_dev = &master->dev; 857 tx_dev = master->dev.parent;
856 858
857 if (master->dma_rx) 859 if (master->dma_rx)
858 rx_dev = master->dma_rx->device->dev; 860 rx_dev = master->dma_rx->device->dev;
859 else 861 else
860 rx_dev = &master->dev; 862 rx_dev = master->dev.parent;
861 863
862 list_for_each_entry(xfer, &msg->transfers, transfer_list) { 864 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
863 if (!master->can_dma(master, msg->spi, xfer)) 865 if (!master->can_dma(master, msg->spi, xfer))
@@ -1502,37 +1504,18 @@ err_init_queue:
1502/*-------------------------------------------------------------------------*/ 1504/*-------------------------------------------------------------------------*/
1503 1505
1504#if defined(CONFIG_OF) 1506#if defined(CONFIG_OF)
1505static struct spi_device * 1507static int of_spi_parse_dt(struct spi_master *master, struct spi_device *spi,
1506of_register_spi_device(struct spi_master *master, struct device_node *nc) 1508 struct device_node *nc)
1507{ 1509{
1508 struct spi_device *spi;
1509 int rc;
1510 u32 value; 1510 u32 value;
1511 1511 int rc;
1512 /* Alloc an spi_device */
1513 spi = spi_alloc_device(master);
1514 if (!spi) {
1515 dev_err(&master->dev, "spi_device alloc error for %s\n",
1516 nc->full_name);
1517 rc = -ENOMEM;
1518 goto err_out;
1519 }
1520
1521 /* Select device driver */
1522 rc = of_modalias_node(nc, spi->modalias,
1523 sizeof(spi->modalias));
1524 if (rc < 0) {
1525 dev_err(&master->dev, "cannot find modalias for %s\n",
1526 nc->full_name);
1527 goto err_out;
1528 }
1529 1512
1530 /* Device address */ 1513 /* Device address */
1531 rc = of_property_read_u32(nc, "reg", &value); 1514 rc = of_property_read_u32(nc, "reg", &value);
1532 if (rc) { 1515 if (rc) {
1533 dev_err(&master->dev, "%s has no valid 'reg' property (%d)\n", 1516 dev_err(&master->dev, "%s has no valid 'reg' property (%d)\n",
1534 nc->full_name, rc); 1517 nc->full_name, rc);
1535 goto err_out; 1518 return rc;
1536 } 1519 }
1537 spi->chip_select = value; 1520 spi->chip_select = value;
1538 1521
@@ -1590,10 +1573,41 @@ of_register_spi_device(struct spi_master *master, struct device_node *nc)
1590 if (rc) { 1573 if (rc) {
1591 dev_err(&master->dev, "%s has no valid 'spi-max-frequency' property (%d)\n", 1574 dev_err(&master->dev, "%s has no valid 'spi-max-frequency' property (%d)\n",
1592 nc->full_name, rc); 1575 nc->full_name, rc);
1593 goto err_out; 1576 return rc;
1594 } 1577 }
1595 spi->max_speed_hz = value; 1578 spi->max_speed_hz = value;
1596 1579
1580 return 0;
1581}
1582
1583static struct spi_device *
1584of_register_spi_device(struct spi_master *master, struct device_node *nc)
1585{
1586 struct spi_device *spi;
1587 int rc;
1588
1589 /* Alloc an spi_device */
1590 spi = spi_alloc_device(master);
1591 if (!spi) {
1592 dev_err(&master->dev, "spi_device alloc error for %s\n",
1593 nc->full_name);
1594 rc = -ENOMEM;
1595 goto err_out;
1596 }
1597
1598 /* Select device driver */
1599 rc = of_modalias_node(nc, spi->modalias,
1600 sizeof(spi->modalias));
1601 if (rc < 0) {
1602 dev_err(&master->dev, "cannot find modalias for %s\n",
1603 nc->full_name);
1604 goto err_out;
1605 }
1606
1607 rc = of_spi_parse_dt(master, spi, nc);
1608 if (rc)
1609 goto err_out;
1610
1597 /* Store a pointer to the node in the device structure */ 1611 /* Store a pointer to the node in the device structure */
1598 of_node_get(nc); 1612 of_node_get(nc);
1599 spi->dev.of_node = nc; 1613 spi->dev.of_node = nc;
@@ -1603,11 +1617,13 @@ of_register_spi_device(struct spi_master *master, struct device_node *nc)
1603 if (rc) { 1617 if (rc) {
1604 dev_err(&master->dev, "spi_device register error %s\n", 1618 dev_err(&master->dev, "spi_device register error %s\n",
1605 nc->full_name); 1619 nc->full_name);
1606 goto err_out; 1620 goto err_of_node_put;
1607 } 1621 }
1608 1622
1609 return spi; 1623 return spi;
1610 1624
1625err_of_node_put:
1626 of_node_put(nc);
1611err_out: 1627err_out:
1612 spi_dev_put(spi); 1628 spi_dev_put(spi);
1613 return ERR_PTR(rc); 1629 return ERR_PTR(rc);
diff --git a/include/linux/platform_data/spi-ep93xx.h b/include/linux/platform_data/spi-ep93xx.h
index 9bb63ac13f04..171a271c2cbd 100644
--- a/include/linux/platform_data/spi-ep93xx.h
+++ b/include/linux/platform_data/spi-ep93xx.h
@@ -5,25 +5,14 @@ struct spi_device;
5 5
6/** 6/**
7 * struct ep93xx_spi_info - EP93xx specific SPI descriptor 7 * struct ep93xx_spi_info - EP93xx specific SPI descriptor
8 * @num_chipselect: number of chip selects on this board, must be 8 * @chipselect: array of gpio numbers to use as chip selects
9 * at least one 9 * @num_chipselect: ARRAY_SIZE(chipselect)
10 * @use_dma: use DMA for the transfers 10 * @use_dma: use DMA for the transfers
11 */ 11 */
12struct ep93xx_spi_info { 12struct ep93xx_spi_info {
13 int *chipselect;
13 int num_chipselect; 14 int num_chipselect;
14 bool use_dma; 15 bool use_dma;
15}; 16};
16 17
17/**
18 * struct ep93xx_spi_chip_ops - operation callbacks for SPI slave device
19 * @setup: setup the chip select mechanism
20 * @cleanup: cleanup the chip select mechanism
21 * @cs_control: control the device chip select
22 */
23struct ep93xx_spi_chip_ops {
24 int (*setup)(struct spi_device *spi);
25 void (*cleanup)(struct spi_device *spi);
26 void (*cs_control)(struct spi_device *spi, int value);
27};
28
29#endif /* __ASM_MACH_EP93XX_SPI_H */ 18#endif /* __ASM_MACH_EP93XX_SPI_H */
diff --git a/include/linux/pxa2xx_ssp.h b/include/linux/pxa2xx_ssp.h
index 2d6f0c39ed68..a0522328d7aa 100644
--- a/include/linux/pxa2xx_ssp.h
+++ b/include/linux/pxa2xx_ssp.h
@@ -90,9 +90,9 @@
90#define SSSR_RFL_MASK (0xf << 12) /* Receive FIFO Level mask */ 90#define SSSR_RFL_MASK (0xf << 12) /* Receive FIFO Level mask */
91 91
92#define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */ 92#define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */
93#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */ 93#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
94#define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */ 94#define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */
95#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */ 95#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
96 96
97#define RX_THRESH_CE4100_DFLT 2 97#define RX_THRESH_CE4100_DFLT 2
98#define TX_THRESH_CE4100_DFLT 2 98#define TX_THRESH_CE4100_DFLT 2
@@ -106,9 +106,9 @@
106#define CE4100_SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..4] */ 106#define CE4100_SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..4] */
107 107
108/* QUARK_X1000 SSCR0 bit definition */ 108/* QUARK_X1000 SSCR0 bit definition */
109#define QUARK_X1000_SSCR0_DSS (0x1F) /* Data Size Select (mask) */ 109#define QUARK_X1000_SSCR0_DSS (0x1F << 0) /* Data Size Select (mask) */
110#define QUARK_X1000_SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..32] */ 110#define QUARK_X1000_SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..32] */
111#define QUARK_X1000_SSCR0_FRF (0x3 << 5) /* FRame Format (mask) */ 111#define QUARK_X1000_SSCR0_FRF (0x3 << 5) /* FRame Format (mask) */
112#define QUARK_X1000_SSCR0_Motorola (0x0 << 5) /* Motorola's Serial Peripheral Interface (SPI) */ 112#define QUARK_X1000_SSCR0_Motorola (0x0 << 5) /* Motorola's Serial Peripheral Interface (SPI) */
113 113
114#define RX_THRESH_QUARK_X1000_DFLT 1 114#define RX_THRESH_QUARK_X1000_DFLT 1
@@ -121,8 +121,8 @@
121#define QUARK_X1000_SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..32] */ 121#define QUARK_X1000_SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..32] */
122#define QUARK_X1000_SSCR1_RFT (0x1F << 11) /* Receive FIFO Threshold (mask) */ 122#define QUARK_X1000_SSCR1_RFT (0x1F << 11) /* Receive FIFO Threshold (mask) */
123#define QUARK_X1000_SSCR1_RxTresh(x) (((x) - 1) << 11) /* level [1..32] */ 123#define QUARK_X1000_SSCR1_RxTresh(x) (((x) - 1) << 11) /* level [1..32] */
124#define QUARK_X1000_SSCR1_STRF (1 << 17) /* Select FIFO or EFWR */ 124#define QUARK_X1000_SSCR1_STRF (1 << 17) /* Select FIFO or EFWR */
125#define QUARK_X1000_SSCR1_EFWR (1 << 16) /* Enable FIFO Write/Read */ 125#define QUARK_X1000_SSCR1_EFWR (1 << 16) /* Enable FIFO Write/Read */
126 126
127/* extra bits in PXA255, PXA26x and PXA27x SSP ports */ 127/* extra bits in PXA255, PXA26x and PXA27x SSP ports */
128#define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */ 128#define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-08 02:16:04 -0500