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-rw-r--r--MAINTAINERS2
-rw-r--r--arch/alpha/kernel/pci.c11
-rw-r--r--arch/arm/kernel/bios32.c4
-rw-r--r--arch/frv/mb93090-mb00/pci-vdk.c4
-rw-r--r--arch/ia64/pci/pci.c4
-rw-r--r--arch/microblaze/pci/pci-common.c4
-rw-r--r--arch/mips/pci/pci.c2
-rw-r--r--arch/powerpc/include/asm/pci-bridge.h1
-rw-r--r--arch/powerpc/kernel/pci-common.c17
-rw-r--r--arch/powerpc/kernel/pci_64.c2
-rw-r--r--arch/powerpc/kernel/pci_of_scan.c2
-rw-r--r--arch/powerpc/platforms/85xx/tqm85xx.c2
-rw-r--r--arch/powerpc/platforms/86xx/gef_ppc9a.c2
-rw-r--r--arch/powerpc/platforms/86xx/gef_sbc310.c2
-rw-r--r--arch/powerpc/platforms/86xx/gef_sbc610.c2
-rw-r--r--arch/powerpc/platforms/powernv/pci-ioda.c8
-rw-r--r--arch/powerpc/platforms/pseries/pci_dlpar.c2
-rw-r--r--arch/powerpc/sysdev/fsl_pci.c2
-rw-r--r--arch/powerpc/sysdev/mv64x60_pci.c2
-rw-r--r--arch/sh/drivers/pci/fixups-dreamcast.c2
-rw-r--r--arch/sh/drivers/pci/pci.c2
-rw-r--r--arch/sparc/kernel/pci.c8
-rw-r--r--arch/sparc/kernel/pci_impl.h1
-rw-r--r--arch/sparc/kernel/pcic.c5
-rw-r--r--arch/tile/kernel/pci.c9
-rw-r--r--arch/x86/include/asm/pci_x86.h7
-rw-r--r--arch/x86/kernel/quirks.c2
-rw-r--r--arch/x86/pci/acpi.c109
-rw-r--r--arch/x86/pci/amd_bus.c7
-rw-r--r--arch/x86/pci/bus_numa.c22
-rw-r--r--arch/x86/pci/bus_numa.h3
-rw-r--r--arch/x86/pci/mmconfig-shared.c372
-rw-r--r--arch/x86/pci/mmconfig_32.c30
-rw-r--r--arch/x86/pci/mmconfig_64.c52
-rw-r--r--arch/x86/pci/mrst.c2
-rw-r--r--arch/xtensa/kernel/pci.c2
-rw-r--r--drivers/acpi/pci_root.c2
-rw-r--r--drivers/acpi/sleep.c24
-rw-r--r--drivers/iommu/intel-iommu.c2
-rw-r--r--drivers/misc/cb710/core.c2
-rw-r--r--drivers/net/ethernet/broadcom/tg3.c4
-rw-r--r--drivers/parisc/dino.c16
-rw-r--r--drivers/parisc/iosapic.c2
-rw-r--r--drivers/parisc/lba_pci.c26
-rw-r--r--drivers/pci/access.c6
-rw-r--r--drivers/pci/hotplug-pci.c30
-rw-r--r--drivers/pci/hotplug/acpiphp_glue.c64
-rw-r--r--drivers/pci/hotplug/cpci_hotplug_pci.c35
-rw-r--r--drivers/pci/hotplug/cpqphp_pci.c8
-rw-r--r--drivers/pci/hotplug/ibmphp_core.c8
-rw-r--r--drivers/pci/hotplug/pciehp_pci.c28
-rw-r--r--drivers/pci/hotplug/sgi_hotplug.c12
-rw-r--r--drivers/pci/hotplug/shpchp_ctrl.c3
-rw-r--r--drivers/pci/hotplug/shpchp_pci.c45
-rw-r--r--drivers/pci/hotplug/shpchp_sysfs.c6
-rw-r--r--drivers/pci/iov.c4
-rw-r--r--drivers/pci/pci-acpi.c36
-rw-r--r--drivers/pci/pci-driver.c10
-rw-r--r--drivers/pci/pci-sysfs.c31
-rw-r--r--drivers/pci/pci.c395
-rw-r--r--drivers/pci/pci.h10
-rw-r--r--drivers/pci/pcie/aer/aerdrv_acpi.c2
-rw-r--r--drivers/pci/pcie/portdrv_pci.c60
-rw-r--r--drivers/pci/probe.c209
-rw-r--r--drivers/pci/quirks.c116
-rw-r--r--drivers/pci/remove.c1
-rw-r--r--drivers/pci/search.c2
-rw-r--r--drivers/pci/setup-bus.c26
-rw-r--r--drivers/pcmcia/cardbus.c2
-rw-r--r--drivers/pcmcia/yenta_socket.c26
-rw-r--r--drivers/pnp/pnpacpi/core.c4
-rw-r--r--drivers/xen/xen-pciback/conf_space.c6
-rw-r--r--include/acpi/acnames.h1
-rw-r--r--include/acpi/acpi_bus.h7
-rw-r--r--include/linux/pci-acpi.h1
-rw-r--r--include/linux/pci.h80
-rw-r--r--include/linux/pci_regs.h119
-rw-r--r--include/linux/sfi_acpi.h4
-rw-r--r--kernel/resource.c13
-rw-r--r--scripts/mod/modpost.c11
80 files changed, 1570 insertions, 639 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index 14bc7071f9df..28b4679d8c75 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5195,7 +5195,7 @@ PCI SUBSYSTEM
5195M: Bjorn Helgaas <bhelgaas@google.com> 5195M: Bjorn Helgaas <bhelgaas@google.com>
5196L: linux-pci@vger.kernel.org 5196L: linux-pci@vger.kernel.org
5197Q: http://patchwork.ozlabs.org/project/linux-pci/list/ 5197Q: http://patchwork.ozlabs.org/project/linux-pci/list/
5198T: git git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/linux.git 5198T: git git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git
5199S: Supported 5199S: Supported
5200F: Documentation/PCI/ 5200F: Documentation/PCI/
5201F: drivers/pci/ 5201F: drivers/pci/
diff --git a/arch/alpha/kernel/pci.c b/arch/alpha/kernel/pci.c
index 133d2d445a36..9816d5a4d176 100644
--- a/arch/alpha/kernel/pci.c
+++ b/arch/alpha/kernel/pci.c
@@ -59,15 +59,13 @@ struct pci_controller *pci_isa_hose;
59 * Quirks. 59 * Quirks.
60 */ 60 */
61 61
62static void __init 62static void __devinit quirk_isa_bridge(struct pci_dev *dev)
63quirk_isa_bridge(struct pci_dev *dev)
64{ 63{
65 dev->class = PCI_CLASS_BRIDGE_ISA << 8; 64 dev->class = PCI_CLASS_BRIDGE_ISA << 8;
66} 65}
67DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82378, quirk_isa_bridge); 66DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82378, quirk_isa_bridge);
68 67
69static void __init 68static void __devinit quirk_cypress(struct pci_dev *dev)
70quirk_cypress(struct pci_dev *dev)
71{ 69{
72 /* The Notorious Cy82C693 chip. */ 70 /* The Notorious Cy82C693 chip. */
73 71
@@ -106,8 +104,7 @@ quirk_cypress(struct pci_dev *dev)
106DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, quirk_cypress); 104DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, quirk_cypress);
107 105
108/* Called for each device after PCI setup is done. */ 106/* Called for each device after PCI setup is done. */
109static void __init 107static void __devinit pcibios_fixup_final(struct pci_dev *dev)
110pcibios_fixup_final(struct pci_dev *dev)
111{ 108{
112 unsigned int class = dev->class >> 8; 109 unsigned int class = dev->class >> 8;
113 110
@@ -353,7 +350,7 @@ common_init_pci(void)
353 hose, &resources); 350 hose, &resources);
354 hose->bus = bus; 351 hose->bus = bus;
355 hose->need_domain_info = need_domain_info; 352 hose->need_domain_info = need_domain_info;
356 next_busno = bus->subordinate + 1; 353 next_busno = bus->busn_res.end + 1;
357 /* Don't allow 8-bit bus number overflow inside the hose - 354 /* Don't allow 8-bit bus number overflow inside the hose -
358 reserve some space for bridges. */ 355 reserve some space for bridges. */
359 if (next_busno > 224) { 356 if (next_busno > 224) {
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index 25552508c3fd..2b2f25e7fef5 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -253,7 +253,7 @@ static void __devinit pci_fixup_cy82c693(struct pci_dev *dev)
253} 253}
254DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693); 254DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693);
255 255
256static void __init pci_fixup_it8152(struct pci_dev *dev) 256static void __devinit pci_fixup_it8152(struct pci_dev *dev)
257{ 257{
258 int i; 258 int i;
259 /* fixup for ITE 8152 devices */ 259 /* fixup for ITE 8152 devices */
@@ -461,7 +461,7 @@ static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
461 if (!sys->bus) 461 if (!sys->bus)
462 panic("PCI: unable to scan bus!"); 462 panic("PCI: unable to scan bus!");
463 463
464 busnr = sys->bus->subordinate + 1; 464 busnr = sys->bus->busn_res.end + 1;
465 465
466 list_add(&sys->node, head); 466 list_add(&sys->node, head);
467 } else { 467 } else {
diff --git a/arch/frv/mb93090-mb00/pci-vdk.c b/arch/frv/mb93090-mb00/pci-vdk.c
index 6b0b82ff4419..d04ed14bbf0c 100644
--- a/arch/frv/mb93090-mb00/pci-vdk.c
+++ b/arch/frv/mb93090-mb00/pci-vdk.c
@@ -268,7 +268,7 @@ static void __init pci_fixup_umc_ide(struct pci_dev *d)
268 d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO; 268 d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
269} 269}
270 270
271static void __init pci_fixup_ide_bases(struct pci_dev *d) 271static void __devinit pci_fixup_ide_bases(struct pci_dev *d)
272{ 272{
273 int i; 273 int i;
274 274
@@ -287,7 +287,7 @@ static void __init pci_fixup_ide_bases(struct pci_dev *d)
287 } 287 }
288} 288}
289 289
290static void __init pci_fixup_ide_trash(struct pci_dev *d) 290static void __devinit pci_fixup_ide_trash(struct pci_dev *d)
291{ 291{
292 int i; 292 int i;
293 293
diff --git a/arch/ia64/pci/pci.c b/arch/ia64/pci/pci.c
index e51941fe8a04..81acc7a57f3e 100644
--- a/arch/ia64/pci/pci.c
+++ b/arch/ia64/pci/pci.c
@@ -351,6 +351,8 @@ pci_acpi_scan_root(struct acpi_pci_root *root)
351#endif 351#endif
352 352
353 INIT_LIST_HEAD(&info.resources); 353 INIT_LIST_HEAD(&info.resources);
354 /* insert busn resource at first */
355 pci_add_resource(&info.resources, &root->secondary);
354 acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window, 356 acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window,
355 &windows); 357 &windows);
356 if (windows) { 358 if (windows) {
@@ -384,7 +386,7 @@ pci_acpi_scan_root(struct acpi_pci_root *root)
384 return NULL; 386 return NULL;
385 } 387 }
386 388
387 pbus->subordinate = pci_scan_child_bus(pbus); 389 pci_scan_child_bus(pbus);
388 return pbus; 390 return pbus;
389 391
390out3: 392out3:
diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c
index 7b510ae906fa..bd61512a1be4 100644
--- a/arch/microblaze/pci/pci-common.c
+++ b/arch/microblaze/pci/pci-common.c
@@ -1501,10 +1501,10 @@ static void __devinit pcibios_scan_phb(struct pci_controller *hose)
1501 pci_free_resource_list(&resources); 1501 pci_free_resource_list(&resources);
1502 return; 1502 return;
1503 } 1503 }
1504 bus->secondary = hose->first_busno; 1504 bus->busn_res.start = hose->first_busno;
1505 hose->bus = bus; 1505 hose->bus = bus;
1506 1506
1507 hose->last_busno = bus->subordinate; 1507 hose->last_busno = bus->busn_res.end;
1508} 1508}
1509 1509
1510static int __init pcibios_init(void) 1510static int __init pcibios_init(void)
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index 0e111d2741ac..690356808f8a 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -102,7 +102,7 @@ static void __devinit pcibios_scanbus(struct pci_controller *hose)
102 need_domain_info = need_domain_info || hose->index; 102 need_domain_info = need_domain_info || hose->index;
103 hose->need_domain_info = need_domain_info; 103 hose->need_domain_info = need_domain_info;
104 if (bus) { 104 if (bus) {
105 next_busno = bus->subordinate + 1; 105 next_busno = bus->busn_res.end + 1;
106 /* Don't allow 8-bit bus number overflow inside the hose - 106 /* Don't allow 8-bit bus number overflow inside the hose -
107 reserve some space for bridges. */ 107 reserve some space for bridges. */
108 if (next_busno > 224) { 108 if (next_busno > 224) {
diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/powerpc/include/asm/pci-bridge.h
index ac39e6a3b25a..8cccbee61519 100644
--- a/arch/powerpc/include/asm/pci-bridge.h
+++ b/arch/powerpc/include/asm/pci-bridge.h
@@ -30,6 +30,7 @@ struct pci_controller {
30 int first_busno; 30 int first_busno;
31 int last_busno; 31 int last_busno;
32 int self_busno; 32 int self_busno;
33 struct resource busn;
33 34
34 void __iomem *io_base_virt; 35 void __iomem *io_base_virt;
35#ifdef CONFIG_PPC64 36#ifdef CONFIG_PPC64
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index bf2306bfa756..cf40f2c2c08c 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -1632,6 +1632,11 @@ void __devinit pcibios_scan_phb(struct pci_controller *hose)
1632 /* Wire up PHB bus resources */ 1632 /* Wire up PHB bus resources */
1633 pcibios_setup_phb_resources(hose, &resources); 1633 pcibios_setup_phb_resources(hose, &resources);
1634 1634
1635 hose->busn.start = hose->first_busno;
1636 hose->busn.end = hose->last_busno;
1637 hose->busn.flags = IORESOURCE_BUS;
1638 pci_add_resource(&resources, &hose->busn);
1639
1635 /* Create an empty bus for the toplevel */ 1640 /* Create an empty bus for the toplevel */
1636 bus = pci_create_root_bus(hose->parent, hose->first_busno, 1641 bus = pci_create_root_bus(hose->parent, hose->first_busno,
1637 hose->ops, hose, &resources); 1642 hose->ops, hose, &resources);
@@ -1641,7 +1646,6 @@ void __devinit pcibios_scan_phb(struct pci_controller *hose)
1641 pci_free_resource_list(&resources); 1646 pci_free_resource_list(&resources);
1642 return; 1647 return;
1643 } 1648 }
1644 bus->secondary = hose->first_busno;
1645 hose->bus = bus; 1649 hose->bus = bus;
1646 1650
1647 /* Get probe mode and perform scan */ 1651 /* Get probe mode and perform scan */
@@ -1649,13 +1653,14 @@ void __devinit pcibios_scan_phb(struct pci_controller *hose)
1649 if (node && ppc_md.pci_probe_mode) 1653 if (node && ppc_md.pci_probe_mode)
1650 mode = ppc_md.pci_probe_mode(bus); 1654 mode = ppc_md.pci_probe_mode(bus);
1651 pr_debug(" probe mode: %d\n", mode); 1655 pr_debug(" probe mode: %d\n", mode);
1652 if (mode == PCI_PROBE_DEVTREE) { 1656 if (mode == PCI_PROBE_DEVTREE)
1653 bus->subordinate = hose->last_busno;
1654 of_scan_bus(node, bus); 1657 of_scan_bus(node, bus);
1655 }
1656 1658
1657 if (mode == PCI_PROBE_NORMAL) 1659 if (mode == PCI_PROBE_NORMAL) {
1658 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus); 1660 pci_bus_update_busn_res_end(bus, 255);
1661 hose->last_busno = pci_scan_child_bus(bus);
1662 pci_bus_update_busn_res_end(bus, hose->last_busno);
1663 }
1659 1664
1660 /* Platform gets a chance to do some global fixups before 1665 /* Platform gets a chance to do some global fixups before
1661 * we proceed to resource allocation 1666 * we proceed to resource allocation
diff --git a/arch/powerpc/kernel/pci_64.c b/arch/powerpc/kernel/pci_64.c
index 94a54f61d341..4ff190ff24a0 100644
--- a/arch/powerpc/kernel/pci_64.c
+++ b/arch/powerpc/kernel/pci_64.c
@@ -236,7 +236,7 @@ long sys_pciconfig_iobase(long which, unsigned long in_bus,
236 236
237 for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) { 237 for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
238 bus = pci_bus_b(ln); 238 bus = pci_bus_b(ln);
239 if (in_bus >= bus->number && in_bus <= bus->subordinate) 239 if (in_bus >= bus->number && in_bus <= bus->busn_res.end)
240 break; 240 break;
241 bus = NULL; 241 bus = NULL;
242 } 242 }
diff --git a/arch/powerpc/kernel/pci_of_scan.c b/arch/powerpc/kernel/pci_of_scan.c
index 89dde171a6fa..ae5ea5e04d65 100644
--- a/arch/powerpc/kernel/pci_of_scan.c
+++ b/arch/powerpc/kernel/pci_of_scan.c
@@ -240,7 +240,7 @@ void __devinit of_scan_pci_bridge(struct pci_dev *dev)
240 } 240 }
241 241
242 bus->primary = dev->bus->number; 242 bus->primary = dev->bus->number;
243 bus->subordinate = busrange[1]; 243 pci_bus_insert_busn_res(bus, busrange[0], busrange[1]);
244 bus->bridge_ctl = 0; 244 bus->bridge_ctl = 0;
245 245
246 /* parse ranges property */ 246 /* parse ranges property */
diff --git a/arch/powerpc/platforms/85xx/tqm85xx.c b/arch/powerpc/platforms/85xx/tqm85xx.c
index 4d786c25d3e5..3e70a2035e53 100644
--- a/arch/powerpc/platforms/85xx/tqm85xx.c
+++ b/arch/powerpc/platforms/85xx/tqm85xx.c
@@ -102,7 +102,7 @@ static void tqm85xx_show_cpuinfo(struct seq_file *m)
102 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f)); 102 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
103} 103}
104 104
105static void __init tqm85xx_ti1520_fixup(struct pci_dev *pdev) 105static void __devinit tqm85xx_ti1520_fixup(struct pci_dev *pdev)
106{ 106{
107 unsigned int val; 107 unsigned int val;
108 108
diff --git a/arch/powerpc/platforms/86xx/gef_ppc9a.c b/arch/powerpc/platforms/86xx/gef_ppc9a.c
index 1fca663f1b25..563aafa8629c 100644
--- a/arch/powerpc/platforms/86xx/gef_ppc9a.c
+++ b/arch/powerpc/platforms/86xx/gef_ppc9a.c
@@ -164,7 +164,7 @@ static void gef_ppc9a_show_cpuinfo(struct seq_file *m)
164 gef_ppc9a_get_vme_is_syscon() ? "yes" : "no"); 164 gef_ppc9a_get_vme_is_syscon() ? "yes" : "no");
165} 165}
166 166
167static void __init gef_ppc9a_nec_fixup(struct pci_dev *pdev) 167static void __devinit gef_ppc9a_nec_fixup(struct pci_dev *pdev)
168{ 168{
169 unsigned int val; 169 unsigned int val;
170 170
diff --git a/arch/powerpc/platforms/86xx/gef_sbc310.c b/arch/powerpc/platforms/86xx/gef_sbc310.c
index 14e0e576bcbd..cc6a91ae0889 100644
--- a/arch/powerpc/platforms/86xx/gef_sbc310.c
+++ b/arch/powerpc/platforms/86xx/gef_sbc310.c
@@ -152,7 +152,7 @@ static void gef_sbc310_show_cpuinfo(struct seq_file *m)
152 152
153} 153}
154 154
155static void __init gef_sbc310_nec_fixup(struct pci_dev *pdev) 155static void __devinit gef_sbc310_nec_fixup(struct pci_dev *pdev)
156{ 156{
157 unsigned int val; 157 unsigned int val;
158 158
diff --git a/arch/powerpc/platforms/86xx/gef_sbc610.c b/arch/powerpc/platforms/86xx/gef_sbc610.c
index 1638f43599f0..aead6b337f4a 100644
--- a/arch/powerpc/platforms/86xx/gef_sbc610.c
+++ b/arch/powerpc/platforms/86xx/gef_sbc610.c
@@ -141,7 +141,7 @@ static void gef_sbc610_show_cpuinfo(struct seq_file *m)
141 seq_printf(m, "SVR\t\t: 0x%x\n", svid); 141 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
142} 142}
143 143
144static void __init gef_sbc610_nec_fixup(struct pci_dev *pdev) 144static void __devinit gef_sbc610_nec_fixup(struct pci_dev *pdev)
145{ 145{
146 unsigned int val; 146 unsigned int val;
147 147
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
index fbdd74dac3ac..9cda6a1ad0cf 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -589,7 +589,7 @@ static int __devinit pnv_ioda_configure_pe(struct pnv_phb *phb,
589 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; 589 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
590 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; 590 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
591 parent = pe->pbus->self; 591 parent = pe->pbus->self;
592 count = pe->pbus->subordinate - pe->pbus->secondary + 1; 592 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
593 switch(count) { 593 switch(count) {
594 case 1: bcomp = OpalPciBusAll; break; 594 case 1: bcomp = OpalPciBusAll; break;
595 case 2: bcomp = OpalPciBus7Bits; break; 595 case 2: bcomp = OpalPciBus7Bits; break;
@@ -816,11 +816,11 @@ static void __devinit pnv_ioda_setup_bus_PE(struct pci_dev *dev,
816 pe->pdev = NULL; 816 pe->pdev = NULL;
817 pe->tce32_seg = -1; 817 pe->tce32_seg = -1;
818 pe->mve_number = -1; 818 pe->mve_number = -1;
819 pe->rid = bus->secondary << 8; 819 pe->rid = bus->busn_res.start << 8;
820 pe->dma_weight = 0; 820 pe->dma_weight = 0;
821 821
822 pe_info(pe, "Secondary busses %d..%d associated with PE\n", 822 pe_info(pe, "Secondary busses %pR associated with PE\n",
823 bus->secondary, bus->subordinate); 823 &bus->busn_res);
824 824
825 if (pnv_ioda_configure_pe(phb, pe)) { 825 if (pnv_ioda_configure_pe(phb, pe)) {
826 /* XXX What do we do here ? */ 826 /* XXX What do we do here ? */
diff --git a/arch/powerpc/platforms/pseries/pci_dlpar.c b/arch/powerpc/platforms/pseries/pci_dlpar.c
index 8b7bafa489c2..3ccebc83dc02 100644
--- a/arch/powerpc/platforms/pseries/pci_dlpar.c
+++ b/arch/powerpc/platforms/pseries/pci_dlpar.c
@@ -121,7 +121,7 @@ void pcibios_add_pci_devices(struct pci_bus * bus)
121 if (!num) 121 if (!num)
122 return; 122 return;
123 pcibios_setup_bus_devices(bus); 123 pcibios_setup_bus_devices(bus);
124 max = bus->secondary; 124 max = bus->busn_res.start;
125 for (pass=0; pass < 2; pass++) 125 for (pass=0; pass < 2; pass++)
126 list_for_each_entry(dev, &bus->devices, bus_list) { 126 list_for_each_entry(dev, &bus->devices, bus_list) {
127 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 127 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 6073288fed29..edbf79465d50 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -36,7 +36,7 @@
36 36
37static int fsl_pcie_bus_fixup, is_mpc83xx_pci; 37static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
38 38
39static void __init quirk_fsl_pcie_header(struct pci_dev *dev) 39static void __devinit quirk_fsl_pcie_header(struct pci_dev *dev)
40{ 40{
41 u8 progif; 41 u8 progif;
42 42
diff --git a/arch/powerpc/sysdev/mv64x60_pci.c b/arch/powerpc/sysdev/mv64x60_pci.c
index b0037cefaada..364b14d4754b 100644
--- a/arch/powerpc/sysdev/mv64x60_pci.c
+++ b/arch/powerpc/sysdev/mv64x60_pci.c
@@ -104,7 +104,7 @@ subsys_initcall(mv64x60_sysfs_init);
104 104
105#endif /* CONFIG_SYSFS */ 105#endif /* CONFIG_SYSFS */
106 106
107static void __init mv64x60_pci_fixup_early(struct pci_dev *dev) 107static void __devinit mv64x60_pci_fixup_early(struct pci_dev *dev)
108{ 108{
109 /* 109 /*
110 * Set the host bridge hdr_type to an invalid value so that 110 * Set the host bridge hdr_type to an invalid value so that
diff --git a/arch/sh/drivers/pci/fixups-dreamcast.c b/arch/sh/drivers/pci/fixups-dreamcast.c
index edeea8960c30..a5fe1b54c952 100644
--- a/arch/sh/drivers/pci/fixups-dreamcast.c
+++ b/arch/sh/drivers/pci/fixups-dreamcast.c
@@ -28,7 +28,7 @@
28#include <asm/irq.h> 28#include <asm/irq.h>
29#include <mach/pci.h> 29#include <mach/pci.h>
30 30
31static void __init gapspci_fixup_resources(struct pci_dev *dev) 31static void __devinit gapspci_fixup_resources(struct pci_dev *dev)
32{ 32{
33 struct pci_channel *p = dev->sysdata; 33 struct pci_channel *p = dev->sysdata;
34 34
diff --git a/arch/sh/drivers/pci/pci.c b/arch/sh/drivers/pci/pci.c
index 7d42288e1057..40db2d0aef3f 100644
--- a/arch/sh/drivers/pci/pci.c
+++ b/arch/sh/drivers/pci/pci.c
@@ -59,7 +59,7 @@ static void __devinit pcibios_scanbus(struct pci_channel *hose)
59 need_domain_info = need_domain_info || hose->index; 59 need_domain_info = need_domain_info || hose->index;
60 hose->need_domain_info = need_domain_info; 60 hose->need_domain_info = need_domain_info;
61 if (bus) { 61 if (bus) {
62 next_busno = bus->subordinate + 1; 62 next_busno = bus->busn_res.end + 1;
63 /* Don't allow 8-bit bus number overflow inside the hose - 63 /* Don't allow 8-bit bus number overflow inside the hose -
64 reserve some space for bridges. */ 64 reserve some space for bridges. */
65 if (next_busno > 224) { 65 if (next_busno > 224) {
diff --git a/arch/sparc/kernel/pci.c b/arch/sparc/kernel/pci.c
index 3e7fba0a5583..52ee0c7b2521 100644
--- a/arch/sparc/kernel/pci.c
+++ b/arch/sparc/kernel/pci.c
@@ -535,7 +535,7 @@ static void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
535 } 535 }
536 536
537 bus->primary = dev->bus->number; 537 bus->primary = dev->bus->number;
538 bus->subordinate = busrange[1]; 538 pci_bus_insert_busn_res(bus, busrange[0], busrange[1]);
539 bus->bridge_ctl = 0; 539 bus->bridge_ctl = 0;
540 540
541 /* parse ranges property, or cook one up by hand for Simba */ 541 /* parse ranges property, or cook one up by hand for Simba */
@@ -685,6 +685,10 @@ struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm,
685 pbm->io_space.start); 685 pbm->io_space.start);
686 pci_add_resource_offset(&resources, &pbm->mem_space, 686 pci_add_resource_offset(&resources, &pbm->mem_space,
687 pbm->mem_space.start); 687 pbm->mem_space.start);
688 pbm->busn.start = pbm->pci_first_busno;
689 pbm->busn.end = pbm->pci_last_busno;
690 pbm->busn.flags = IORESOURCE_BUS;
691 pci_add_resource(&resources, &pbm->busn);
688 bus = pci_create_root_bus(parent, pbm->pci_first_busno, pbm->pci_ops, 692 bus = pci_create_root_bus(parent, pbm->pci_first_busno, pbm->pci_ops,
689 pbm, &resources); 693 pbm, &resources);
690 if (!bus) { 694 if (!bus) {
@@ -693,8 +697,6 @@ struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm,
693 pci_free_resource_list(&resources); 697 pci_free_resource_list(&resources);
694 return NULL; 698 return NULL;
695 } 699 }
696 bus->secondary = pbm->pci_first_busno;
697 bus->subordinate = pbm->pci_last_busno;
698 700
699 pci_of_scan_bus(pbm, node, bus); 701 pci_of_scan_bus(pbm, node, bus);
700 pci_bus_add_devices(bus); 702 pci_bus_add_devices(bus);
diff --git a/arch/sparc/kernel/pci_impl.h b/arch/sparc/kernel/pci_impl.h
index 6beb60df31d0..918a2031c8bb 100644
--- a/arch/sparc/kernel/pci_impl.h
+++ b/arch/sparc/kernel/pci_impl.h
@@ -97,6 +97,7 @@ struct pci_pbm_info {
97 /* PBM I/O and Memory space resources. */ 97 /* PBM I/O and Memory space resources. */
98 struct resource io_space; 98 struct resource io_space;
99 struct resource mem_space; 99 struct resource mem_space;
100 struct resource busn;
100 101
101 /* Base of PCI Config space, can be per-PBM or shared. */ 102 /* Base of PCI Config space, can be per-PBM or shared. */
102 unsigned long config_space; 103 unsigned long config_space;
diff --git a/arch/sparc/kernel/pcic.c b/arch/sparc/kernel/pcic.c
index 97eb52937b82..521fdf1b20e5 100644
--- a/arch/sparc/kernel/pcic.c
+++ b/arch/sparc/kernel/pcic.c
@@ -876,11 +876,6 @@ void __init sun4m_pci_init_IRQ(void)
876 sparc_config.load_profile_irq = pcic_load_profile_irq; 876 sparc_config.load_profile_irq = pcic_load_profile_irq;
877} 877}
878 878
879int pcibios_assign_resource(struct pci_dev *pdev, int resource)
880{
881 return -ENXIO;
882}
883
884/* 879/*
885 * This probably belongs here rather than ioport.c because 880 * This probably belongs here rather than ioport.c because
886 * we do not want this crud linked into SBus kernels. 881 * we do not want this crud linked into SBus kernels.
diff --git a/arch/tile/kernel/pci.c b/arch/tile/kernel/pci.c
index e25722658c14..0fdd99d0d8b7 100644
--- a/arch/tile/kernel/pci.c
+++ b/arch/tile/kernel/pci.c
@@ -310,6 +310,7 @@ int __init pcibios_init(void)
310 if (pci_scan_flags[i] == 0 && controllers[i].ops != NULL) { 310 if (pci_scan_flags[i] == 0 && controllers[i].ops != NULL) {
311 struct pci_controller *controller = &controllers[i]; 311 struct pci_controller *controller = &controllers[i];
312 struct pci_bus *bus; 312 struct pci_bus *bus;
313 LIST_HEAD(resources);
313 314
314 if (tile_init_irqs(i, controller)) { 315 if (tile_init_irqs(i, controller)) {
315 pr_err("PCI: Could not initialize IRQs\n"); 316 pr_err("PCI: Could not initialize IRQs\n");
@@ -327,9 +328,11 @@ int __init pcibios_init(void)
327 * This is inlined in linux/pci.h and calls into 328 * This is inlined in linux/pci.h and calls into
328 * pci_scan_bus_parented() in probe.c. 329 * pci_scan_bus_parented() in probe.c.
329 */ 330 */
330 bus = pci_scan_bus(0, controller->ops, controller); 331 pci_add_resource(&resources, &ioport_resource);
332 pci_add_resource(&resources, &iomem_resource);
333 bus = pci_scan_root_bus(NULL, 0, controller->ops, controller, &resources);
331 controller->root_bus = bus; 334 controller->root_bus = bus;
332 controller->last_busno = bus->subordinate; 335 controller->last_busno = bus->busn_res.end;
333 } 336 }
334 } 337 }
335 338
@@ -366,7 +369,7 @@ int __init pcibios_init(void)
366 */ 369 */
367 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI && 370 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
368 (PCI_SLOT(dev->devfn) == 0)) { 371 (PCI_SLOT(dev->devfn) == 0)) {
369 next_bus = dev->subordinate; 372 next_bus = dev->busn_res.end;
370 controllers[i].mem_resources[0] = 373 controllers[i].mem_resources[0] =
371 *next_bus->resource[0]; 374 *next_bus->resource[0];
372 controllers[i].mem_resources[1] = 375 controllers[i].mem_resources[1] =
diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h
index b3a531746026..b2652e95b3d7 100644
--- a/arch/x86/include/asm/pci_x86.h
+++ b/arch/x86/include/asm/pci_x86.h
@@ -100,6 +100,7 @@ struct pci_raw_ops {
100extern const struct pci_raw_ops *raw_pci_ops; 100extern const struct pci_raw_ops *raw_pci_ops;
101extern const struct pci_raw_ops *raw_pci_ext_ops; 101extern const struct pci_raw_ops *raw_pci_ext_ops;
102 102
103extern const struct pci_raw_ops pci_mmcfg;
103extern const struct pci_raw_ops pci_direct_conf1; 104extern const struct pci_raw_ops pci_direct_conf1;
104extern bool port_cf9_safe; 105extern bool port_cf9_safe;
105 106
@@ -135,6 +136,12 @@ struct pci_mmcfg_region {
135 136
136extern int __init pci_mmcfg_arch_init(void); 137extern int __init pci_mmcfg_arch_init(void);
137extern void __init pci_mmcfg_arch_free(void); 138extern void __init pci_mmcfg_arch_free(void);
139extern int __devinit pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg);
140extern void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg);
141extern int __devinit pci_mmconfig_insert(struct device *dev,
142 u16 seg, u8 start,
143 u8 end, phys_addr_t addr);
144extern int pci_mmconfig_delete(u16 seg, u8 start, u8 end);
138extern struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus); 145extern struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus);
139 146
140extern struct list_head pci_mmcfg_list; 147extern struct list_head pci_mmcfg_list;
diff --git a/arch/x86/kernel/quirks.c b/arch/x86/kernel/quirks.c
index 03920a15a632..1b27de563561 100644
--- a/arch/x86/kernel/quirks.c
+++ b/arch/x86/kernel/quirks.c
@@ -512,7 +512,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
512 512
513#if defined(CONFIG_PCI) && defined(CONFIG_NUMA) 513#if defined(CONFIG_PCI) && defined(CONFIG_NUMA)
514/* Set correct numa_node information for AMD NB functions */ 514/* Set correct numa_node information for AMD NB functions */
515static void __init quirk_amd_nb_node(struct pci_dev *dev) 515static void __devinit quirk_amd_nb_node(struct pci_dev *dev)
516{ 516{
517 struct pci_dev *nb_ht; 517 struct pci_dev *nb_ht;
518 unsigned int devfn; 518 unsigned int devfn;
diff --git a/arch/x86/pci/acpi.c b/arch/x86/pci/acpi.c
index fc09c2754e08..505acdd6d600 100644
--- a/arch/x86/pci/acpi.c
+++ b/arch/x86/pci/acpi.c
@@ -12,8 +12,13 @@ struct pci_root_info {
12 char name[16]; 12 char name[16];
13 unsigned int res_num; 13 unsigned int res_num;
14 struct resource *res; 14 struct resource *res;
15 int busnum;
16 struct pci_sysdata sd; 15 struct pci_sysdata sd;
16#ifdef CONFIG_PCI_MMCONFIG
17 bool mcfg_added;
18 u16 segment;
19 u8 start_bus;
20 u8 end_bus;
21#endif
17}; 22};
18 23
19static bool pci_use_crs = true; 24static bool pci_use_crs = true;
@@ -120,6 +125,81 @@ void __init pci_acpi_crs_quirks(void)
120 pci_use_crs ? "nocrs" : "use_crs"); 125 pci_use_crs ? "nocrs" : "use_crs");
121} 126}
122 127
128#ifdef CONFIG_PCI_MMCONFIG
129static int __devinit check_segment(u16 seg, struct device *dev, char *estr)
130{
131 if (seg) {
132 dev_err(dev,
133 "%s can't access PCI configuration "
134 "space under this host bridge.\n",
135 estr);
136 return -EIO;
137 }
138
139 /*
140 * Failure in adding MMCFG information is not fatal,
141 * just can't access extended configuration space of
142 * devices under this host bridge.
143 */
144 dev_warn(dev,
145 "%s can't access extended PCI configuration "
146 "space under this bridge.\n",
147 estr);
148
149 return 0;
150}
151
152static int __devinit setup_mcfg_map(struct pci_root_info *info,
153 u16 seg, u8 start, u8 end,
154 phys_addr_t addr)
155{
156 int result;
157 struct device *dev = &info->bridge->dev;
158
159 info->start_bus = start;
160 info->end_bus = end;
161 info->mcfg_added = false;
162
163 /* return success if MMCFG is not in use */
164 if (raw_pci_ext_ops && raw_pci_ext_ops != &pci_mmcfg)
165 return 0;
166
167 if (!(pci_probe & PCI_PROBE_MMCONF))
168 return check_segment(seg, dev, "MMCONFIG is disabled,");
169
170 result = pci_mmconfig_insert(dev, seg, start, end, addr);
171 if (result == 0) {
172 /* enable MMCFG if it hasn't been enabled yet */
173 if (raw_pci_ext_ops == NULL)
174 raw_pci_ext_ops = &pci_mmcfg;
175 info->mcfg_added = true;
176 } else if (result != -EEXIST)
177 return check_segment(seg, dev,
178 "fail to add MMCONFIG information,");
179
180 return 0;
181}
182
183static void teardown_mcfg_map(struct pci_root_info *info)
184{
185 if (info->mcfg_added) {
186 pci_mmconfig_delete(info->segment, info->start_bus,
187 info->end_bus);
188 info->mcfg_added = false;
189 }
190}
191#else
192static int __devinit setup_mcfg_map(struct pci_root_info *info,
193 u16 seg, u8 start, u8 end,
194 phys_addr_t addr)
195{
196 return 0;
197}
198static void teardown_mcfg_map(struct pci_root_info *info)
199{
200}
201#endif
202
123static acpi_status 203static acpi_status
124resource_to_addr(struct acpi_resource *resource, 204resource_to_addr(struct acpi_resource *resource,
125 struct acpi_resource_address64 *addr) 205 struct acpi_resource_address64 *addr)
@@ -234,13 +314,6 @@ setup_resource(struct acpi_resource *acpi_res, void *data)
234 } 314 }
235 315
236 info->res_num++; 316 info->res_num++;
237 if (addr.translation_offset)
238 dev_info(&info->bridge->dev, "host bridge window %pR "
239 "(PCI address [%#llx-%#llx])\n",
240 res, res->start - addr.translation_offset,
241 res->end - addr.translation_offset);
242 else
243 dev_info(&info->bridge->dev, "host bridge window %pR\n", res);
244 317
245 return AE_OK; 318 return AE_OK;
246} 319}
@@ -332,8 +405,11 @@ static void __release_pci_root_info(struct pci_root_info *info)
332 405
333 free_pci_root_info_res(info); 406 free_pci_root_info_res(info);
334 407
408 teardown_mcfg_map(info);
409
335 kfree(info); 410 kfree(info);
336} 411}
412
337static void release_pci_root_info(struct pci_host_bridge *bridge) 413static void release_pci_root_info(struct pci_host_bridge *bridge)
338{ 414{
339 struct pci_root_info *info = bridge->release_data; 415 struct pci_root_info *info = bridge->release_data;
@@ -347,7 +423,9 @@ probe_pci_root_info(struct pci_root_info *info, struct acpi_device *device,
347{ 423{
348 size_t size; 424 size_t size;
349 425
426 sprintf(info->name, "PCI Bus %04x:%02x", domain, busnum);
350 info->bridge = device; 427 info->bridge = device;
428
351 info->res_num = 0; 429 info->res_num = 0;
352 acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_resource, 430 acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_resource,
353 info); 431 info);
@@ -360,8 +438,6 @@ probe_pci_root_info(struct pci_root_info *info, struct acpi_device *device,
360 if (!info->res) 438 if (!info->res)
361 return; 439 return;
362 440
363 sprintf(info->name, "PCI Bus %04x:%02x", domain, busnum);
364
365 acpi_walk_resources(device->handle, METHOD_NAME__CRS, setup_resource, 441 acpi_walk_resources(device->handle, METHOD_NAME__CRS, setup_resource,
366 info); 442 info);
367} 443}
@@ -373,7 +449,7 @@ struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_pci_root *root)
373 int domain = root->segment; 449 int domain = root->segment;
374 int busnum = root->secondary.start; 450 int busnum = root->secondary.start;
375 LIST_HEAD(resources); 451 LIST_HEAD(resources);
376 struct pci_bus *bus; 452 struct pci_bus *bus = NULL;
377 struct pci_sysdata *sd; 453 struct pci_sysdata *sd;
378 int node; 454 int node;
379#ifdef CONFIG_ACPI_NUMA 455#ifdef CONFIG_ACPI_NUMA
@@ -426,6 +502,8 @@ struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_pci_root *root)
426 } else { 502 } else {
427 probe_pci_root_info(info, device, busnum, domain); 503 probe_pci_root_info(info, device, busnum, domain);
428 504
505 /* insert busn res at first */
506 pci_add_resource(&resources, &root->secondary);
429 /* 507 /*
430 * _CRS with no apertures is normal, so only fall back to 508 * _CRS with no apertures is normal, so only fall back to
431 * defaults or native bridge info if we're ignoring _CRS. 509 * defaults or native bridge info if we're ignoring _CRS.
@@ -437,10 +515,13 @@ struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_pci_root *root)
437 x86_pci_root_bus_resources(busnum, &resources); 515 x86_pci_root_bus_resources(busnum, &resources);
438 } 516 }
439 517
440 bus = pci_create_root_bus(NULL, busnum, &pci_root_ops, sd, 518 if (!setup_mcfg_map(info, domain, (u8)root->secondary.start,
441 &resources); 519 (u8)root->secondary.end, root->mcfg_addr))
520 bus = pci_create_root_bus(NULL, busnum, &pci_root_ops,
521 sd, &resources);
522
442 if (bus) { 523 if (bus) {
443 bus->subordinate = pci_scan_child_bus(bus); 524 pci_scan_child_bus(bus);
444 pci_set_host_bridge_release( 525 pci_set_host_bridge_release(
445 to_pci_host_bridge(bus->bridge), 526 to_pci_host_bridge(bus->bridge),
446 release_pci_root_info, info); 527 release_pci_root_info, info);
diff --git a/arch/x86/pci/amd_bus.c b/arch/x86/pci/amd_bus.c
index 5aed49bff058..e9e6ed5cdf94 100644
--- a/arch/x86/pci/amd_bus.c
+++ b/arch/x86/pci/amd_bus.c
@@ -121,7 +121,6 @@ static int __init early_fill_mp_bus_info(void)
121 link = (reg >> 8) & 0x03; 121 link = (reg >> 8) & 0x03;
122 122
123 info = alloc_pci_root_info(min_bus, max_bus, node, link); 123 info = alloc_pci_root_info(min_bus, max_bus, node, link);
124 sprintf(info->name, "PCI Bus #%02x", min_bus);
125 } 124 }
126 125
127 /* get the default node and link for left over res */ 126 /* get the default node and link for left over res */
@@ -300,9 +299,9 @@ static int __init early_fill_mp_bus_info(void)
300 int busnum; 299 int busnum;
301 struct pci_root_res *root_res; 300 struct pci_root_res *root_res;
302 301
303 busnum = info->bus_min; 302 busnum = info->busn.start;
304 printk(KERN_DEBUG "bus: [%02x, %02x] on node %x link %x\n", 303 printk(KERN_DEBUG "bus: %pR on node %x link %x\n",
305 info->bus_min, info->bus_max, info->node, info->link); 304 &info->busn, info->node, info->link);
306 list_for_each_entry(root_res, &info->resources, list) 305 list_for_each_entry(root_res, &info->resources, list)
307 printk(KERN_DEBUG "bus: %02x %pR\n", 306 printk(KERN_DEBUG "bus: %02x %pR\n",
308 busnum, &root_res->res); 307 busnum, &root_res->res);
diff --git a/arch/x86/pci/bus_numa.c b/arch/x86/pci/bus_numa.c
index 306579f7d0fd..d37e2fec97e5 100644
--- a/arch/x86/pci/bus_numa.c
+++ b/arch/x86/pci/bus_numa.c
@@ -14,7 +14,7 @@ static struct pci_root_info *x86_find_pci_root_info(int bus)
14 return NULL; 14 return NULL;
15 15
16 list_for_each_entry(info, &pci_root_infos, list) 16 list_for_each_entry(info, &pci_root_infos, list)
17 if (info->bus_min == bus) 17 if (info->busn.start == bus)
18 return info; 18 return info;
19 19
20 return NULL; 20 return NULL;
@@ -24,6 +24,8 @@ void x86_pci_root_bus_resources(int bus, struct list_head *resources)
24{ 24{
25 struct pci_root_info *info = x86_find_pci_root_info(bus); 25 struct pci_root_info *info = x86_find_pci_root_info(bus);
26 struct pci_root_res *root_res; 26 struct pci_root_res *root_res;
27 struct pci_host_bridge_window *window;
28 bool found = false;
27 29
28 if (!info) 30 if (!info)
29 goto default_resources; 31 goto default_resources;
@@ -31,6 +33,16 @@ void x86_pci_root_bus_resources(int bus, struct list_head *resources)
31 printk(KERN_DEBUG "PCI: root bus %02x: hardware-probed resources\n", 33 printk(KERN_DEBUG "PCI: root bus %02x: hardware-probed resources\n",
32 bus); 34 bus);
33 35
36 /* already added by acpi ? */
37 list_for_each_entry(window, resources, list)
38 if (window->res->flags & IORESOURCE_BUS) {
39 found = true;
40 break;
41 }
42
43 if (!found)
44 pci_add_resource(resources, &info->busn);
45
34 list_for_each_entry(root_res, &info->resources, list) { 46 list_for_each_entry(root_res, &info->resources, list) {
35 struct resource *res; 47 struct resource *res;
36 struct resource *root; 48 struct resource *root;
@@ -66,9 +78,13 @@ struct pci_root_info __init *alloc_pci_root_info(int bus_min, int bus_max,
66 if (!info) 78 if (!info)
67 return info; 79 return info;
68 80
81 sprintf(info->name, "PCI Bus #%02x", bus_min);
82
69 INIT_LIST_HEAD(&info->resources); 83 INIT_LIST_HEAD(&info->resources);
70 info->bus_min = bus_min; 84 info->busn.name = info->name;
71 info->bus_max = bus_max; 85 info->busn.start = bus_min;
86 info->busn.end = bus_max;
87 info->busn.flags = IORESOURCE_BUS;
72 info->node = node; 88 info->node = node;
73 info->link = link; 89 info->link = link;
74 90
diff --git a/arch/x86/pci/bus_numa.h b/arch/x86/pci/bus_numa.h
index 226a466b2b2b..ff8f65b04574 100644
--- a/arch/x86/pci/bus_numa.h
+++ b/arch/x86/pci/bus_numa.h
@@ -13,8 +13,7 @@ struct pci_root_info {
13 struct list_head list; 13 struct list_head list;
14 char name[12]; 14 char name[12];
15 struct list_head resources; 15 struct list_head resources;
16 int bus_min; 16 struct resource busn;
17 int bus_max;
18 int node; 17 int node;
19 int link; 18 int link;
20}; 19};
diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c
index 301e325992f6..937bcece7006 100644
--- a/arch/x86/pci/mmconfig-shared.c
+++ b/arch/x86/pci/mmconfig-shared.c
@@ -17,6 +17,8 @@
17#include <linux/bitmap.h> 17#include <linux/bitmap.h>
18#include <linux/dmi.h> 18#include <linux/dmi.h>
19#include <linux/slab.h> 19#include <linux/slab.h>
20#include <linux/mutex.h>
21#include <linux/rculist.h>
20#include <asm/e820.h> 22#include <asm/e820.h>
21#include <asm/pci_x86.h> 23#include <asm/pci_x86.h>
22#include <asm/acpi.h> 24#include <asm/acpi.h>
@@ -24,7 +26,9 @@
24#define PREFIX "PCI: " 26#define PREFIX "PCI: "
25 27
26/* Indicate if the mmcfg resources have been placed into the resource table. */ 28/* Indicate if the mmcfg resources have been placed into the resource table. */
27static int __initdata pci_mmcfg_resources_inserted; 29static bool pci_mmcfg_running_state;
30static bool pci_mmcfg_arch_init_failed;
31static DEFINE_MUTEX(pci_mmcfg_lock);
28 32
29LIST_HEAD(pci_mmcfg_list); 33LIST_HEAD(pci_mmcfg_list);
30 34
@@ -45,24 +49,25 @@ static __init void free_all_mmcfg(void)
45 pci_mmconfig_remove(cfg); 49 pci_mmconfig_remove(cfg);
46} 50}
47 51
48static __init void list_add_sorted(struct pci_mmcfg_region *new) 52static __devinit void list_add_sorted(struct pci_mmcfg_region *new)
49{ 53{
50 struct pci_mmcfg_region *cfg; 54 struct pci_mmcfg_region *cfg;
51 55
52 /* keep list sorted by segment and starting bus number */ 56 /* keep list sorted by segment and starting bus number */
53 list_for_each_entry(cfg, &pci_mmcfg_list, list) { 57 list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list) {
54 if (cfg->segment > new->segment || 58 if (cfg->segment > new->segment ||
55 (cfg->segment == new->segment && 59 (cfg->segment == new->segment &&
56 cfg->start_bus >= new->start_bus)) { 60 cfg->start_bus >= new->start_bus)) {
57 list_add_tail(&new->list, &cfg->list); 61 list_add_tail_rcu(&new->list, &cfg->list);
58 return; 62 return;
59 } 63 }
60 } 64 }
61 list_add_tail(&new->list, &pci_mmcfg_list); 65 list_add_tail_rcu(&new->list, &pci_mmcfg_list);
62} 66}
63 67
64static __init struct pci_mmcfg_region *pci_mmconfig_add(int segment, int start, 68static __devinit struct pci_mmcfg_region *pci_mmconfig_alloc(int segment,
65 int end, u64 addr) 69 int start,
70 int end, u64 addr)
66{ 71{
67 struct pci_mmcfg_region *new; 72 struct pci_mmcfg_region *new;
68 struct resource *res; 73 struct resource *res;
@@ -79,8 +84,6 @@ static __init struct pci_mmcfg_region *pci_mmconfig_add(int segment, int start,
79 new->start_bus = start; 84 new->start_bus = start;
80 new->end_bus = end; 85 new->end_bus = end;
81 86
82 list_add_sorted(new);
83
84 res = &new->res; 87 res = &new->res;
85 res->start = addr + PCI_MMCFG_BUS_OFFSET(start); 88 res->start = addr + PCI_MMCFG_BUS_OFFSET(start);
86 res->end = addr + PCI_MMCFG_BUS_OFFSET(end + 1) - 1; 89 res->end = addr + PCI_MMCFG_BUS_OFFSET(end + 1) - 1;
@@ -89,9 +92,25 @@ static __init struct pci_mmcfg_region *pci_mmconfig_add(int segment, int start,
89 "PCI MMCONFIG %04x [bus %02x-%02x]", segment, start, end); 92 "PCI MMCONFIG %04x [bus %02x-%02x]", segment, start, end);
90 res->name = new->name; 93 res->name = new->name;
91 94
92 printk(KERN_INFO PREFIX "MMCONFIG for domain %04x [bus %02x-%02x] at " 95 return new;
93 "%pR (base %#lx)\n", segment, start, end, &new->res, 96}
94 (unsigned long) addr); 97
98static __init struct pci_mmcfg_region *pci_mmconfig_add(int segment, int start,
99 int end, u64 addr)
100{
101 struct pci_mmcfg_region *new;
102
103 new = pci_mmconfig_alloc(segment, start, end, addr);
104 if (new) {
105 mutex_lock(&pci_mmcfg_lock);
106 list_add_sorted(new);
107 mutex_unlock(&pci_mmcfg_lock);
108
109 pr_info(PREFIX
110 "MMCONFIG for domain %04x [bus %02x-%02x] at %pR "
111 "(base %#lx)\n",
112 segment, start, end, &new->res, (unsigned long)addr);
113 }
95 114
96 return new; 115 return new;
97} 116}
@@ -100,7 +119,7 @@ struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus)
100{ 119{
101 struct pci_mmcfg_region *cfg; 120 struct pci_mmcfg_region *cfg;
102 121
103 list_for_each_entry(cfg, &pci_mmcfg_list, list) 122 list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list)
104 if (cfg->segment == segment && 123 if (cfg->segment == segment &&
105 cfg->start_bus <= bus && bus <= cfg->end_bus) 124 cfg->start_bus <= bus && bus <= cfg->end_bus)
106 return cfg; 125 return cfg;
@@ -343,8 +362,7 @@ static int __init pci_mmcfg_check_hostbridge(void)
343 name = pci_mmcfg_probes[i].probe(); 362 name = pci_mmcfg_probes[i].probe();
344 363
345 if (name) 364 if (name)
346 printk(KERN_INFO PREFIX "%s with MMCONFIG support\n", 365 pr_info(PREFIX "%s with MMCONFIG support\n", name);
347 name);
348 } 366 }
349 367
350 /* some end_bus_number is crazy, fix it */ 368 /* some end_bus_number is crazy, fix it */
@@ -353,19 +371,8 @@ static int __init pci_mmcfg_check_hostbridge(void)
353 return !list_empty(&pci_mmcfg_list); 371 return !list_empty(&pci_mmcfg_list);
354} 372}
355 373
356static void __init pci_mmcfg_insert_resources(void) 374static acpi_status __devinit check_mcfg_resource(struct acpi_resource *res,
357{ 375 void *data)
358 struct pci_mmcfg_region *cfg;
359
360 list_for_each_entry(cfg, &pci_mmcfg_list, list)
361 insert_resource(&iomem_resource, &cfg->res);
362
363 /* Mark that the resources have been inserted. */
364 pci_mmcfg_resources_inserted = 1;
365}
366
367static acpi_status __init check_mcfg_resource(struct acpi_resource *res,
368 void *data)
369{ 376{
370 struct resource *mcfg_res = data; 377 struct resource *mcfg_res = data;
371 struct acpi_resource_address64 address; 378 struct acpi_resource_address64 address;
@@ -401,8 +408,8 @@ static acpi_status __init check_mcfg_resource(struct acpi_resource *res,
401 return AE_OK; 408 return AE_OK;
402} 409}
403 410
404static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl, 411static acpi_status __devinit find_mboard_resource(acpi_handle handle, u32 lvl,
405 void *context, void **rv) 412 void *context, void **rv)
406{ 413{
407 struct resource *mcfg_res = context; 414 struct resource *mcfg_res = context;
408 415
@@ -415,7 +422,7 @@ static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl,
415 return AE_OK; 422 return AE_OK;
416} 423}
417 424
418static int __init is_acpi_reserved(u64 start, u64 end, unsigned not_used) 425static int __devinit is_acpi_reserved(u64 start, u64 end, unsigned not_used)
419{ 426{
420 struct resource mcfg_res; 427 struct resource mcfg_res;
421 428
@@ -434,13 +441,15 @@ static int __init is_acpi_reserved(u64 start, u64 end, unsigned not_used)
434 441
435typedef int (*check_reserved_t)(u64 start, u64 end, unsigned type); 442typedef int (*check_reserved_t)(u64 start, u64 end, unsigned type);
436 443
437static int __init is_mmconf_reserved(check_reserved_t is_reserved, 444static int __ref is_mmconf_reserved(check_reserved_t is_reserved,
438 struct pci_mmcfg_region *cfg, int with_e820) 445 struct pci_mmcfg_region *cfg,
446 struct device *dev, int with_e820)
439{ 447{
440 u64 addr = cfg->res.start; 448 u64 addr = cfg->res.start;
441 u64 size = resource_size(&cfg->res); 449 u64 size = resource_size(&cfg->res);
442 u64 old_size = size; 450 u64 old_size = size;
443 int valid = 0, num_buses; 451 int num_buses;
452 char *method = with_e820 ? "E820" : "ACPI motherboard resources";
444 453
445 while (!is_reserved(addr, addr + size, E820_RESERVED)) { 454 while (!is_reserved(addr, addr + size, E820_RESERVED)) {
446 size >>= 1; 455 size >>= 1;
@@ -448,30 +457,76 @@ static int __init is_mmconf_reserved(check_reserved_t is_reserved,
448 break; 457 break;
449 } 458 }
450 459
451 if (size >= (16UL<<20) || size == old_size) { 460 if (size < (16UL<<20) && size != old_size)
452 printk(KERN_INFO PREFIX "MMCONFIG at %pR reserved in %s\n", 461 return 0;
453 &cfg->res, 462
454 with_e820 ? "E820" : "ACPI motherboard resources"); 463 if (dev)
455 valid = 1; 464 dev_info(dev, "MMCONFIG at %pR reserved in %s\n",
456 465 &cfg->res, method);
457 if (old_size != size) { 466 else
458 /* update end_bus */ 467 pr_info(PREFIX "MMCONFIG at %pR reserved in %s\n",
459 cfg->end_bus = cfg->start_bus + ((size>>20) - 1); 468 &cfg->res, method);
460 num_buses = cfg->end_bus - cfg->start_bus + 1; 469
461 cfg->res.end = cfg->res.start + 470 if (old_size != size) {
462 PCI_MMCFG_BUS_OFFSET(num_buses) - 1; 471 /* update end_bus */
463 snprintf(cfg->name, PCI_MMCFG_RESOURCE_NAME_LEN, 472 cfg->end_bus = cfg->start_bus + ((size>>20) - 1);
464 "PCI MMCONFIG %04x [bus %02x-%02x]", 473 num_buses = cfg->end_bus - cfg->start_bus + 1;
465 cfg->segment, cfg->start_bus, cfg->end_bus); 474 cfg->res.end = cfg->res.start +
466 printk(KERN_INFO PREFIX 475 PCI_MMCFG_BUS_OFFSET(num_buses) - 1;
467 "MMCONFIG for %04x [bus%02x-%02x] " 476 snprintf(cfg->name, PCI_MMCFG_RESOURCE_NAME_LEN,
468 "at %pR (base %#lx) (size reduced!)\n", 477 "PCI MMCONFIG %04x [bus %02x-%02x]",
469 cfg->segment, cfg->start_bus, cfg->end_bus, 478 cfg->segment, cfg->start_bus, cfg->end_bus);
470 &cfg->res, (unsigned long) cfg->address); 479
471 } 480 if (dev)
481 dev_info(dev,
482 "MMCONFIG "
483 "at %pR (base %#lx) (size reduced!)\n",
484 &cfg->res, (unsigned long) cfg->address);
485 else
486 pr_info(PREFIX
487 "MMCONFIG for %04x [bus%02x-%02x] "
488 "at %pR (base %#lx) (size reduced!)\n",
489 cfg->segment, cfg->start_bus, cfg->end_bus,
490 &cfg->res, (unsigned long) cfg->address);
472 } 491 }
473 492
474 return valid; 493 return 1;
494}
495
496static int __ref pci_mmcfg_check_reserved(struct device *dev,
497 struct pci_mmcfg_region *cfg, int early)
498{
499 if (!early && !acpi_disabled) {
500 if (is_mmconf_reserved(is_acpi_reserved, cfg, dev, 0))
501 return 1;
502
503 if (dev)
504 dev_info(dev, FW_INFO
505 "MMCONFIG at %pR not reserved in "
506 "ACPI motherboard resources\n",
507 &cfg->res);
508 else
509 pr_info(FW_INFO PREFIX
510 "MMCONFIG at %pR not reserved in "
511 "ACPI motherboard resources\n",
512 &cfg->res);
513 }
514
515 /*
516 * e820_all_mapped() is marked as __init.
517 * All entries from ACPI MCFG table have been checked at boot time.
518 * For MCFG information constructed from hotpluggable host bridge's
519 * _CBA method, just assume it's reserved.
520 */
521 if (pci_mmcfg_running_state)
522 return 1;
523
524 /* Don't try to do this check unless configuration
525 type 1 is available. how about type 2 ?*/
526 if (raw_pci_ops)
527 return is_mmconf_reserved(e820_all_mapped, cfg, dev, 1);
528
529 return 0;
475} 530}
476 531
477static void __init pci_mmcfg_reject_broken(int early) 532static void __init pci_mmcfg_reject_broken(int early)
@@ -479,38 +534,14 @@ static void __init pci_mmcfg_reject_broken(int early)
479 struct pci_mmcfg_region *cfg; 534 struct pci_mmcfg_region *cfg;
480 535
481 list_for_each_entry(cfg, &pci_mmcfg_list, list) { 536 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
482 int valid = 0; 537 if (pci_mmcfg_check_reserved(NULL, cfg, early) == 0) {
483 538 pr_info(PREFIX "not using MMCONFIG\n");
484 if (!early && !acpi_disabled) { 539 free_all_mmcfg();
485 valid = is_mmconf_reserved(is_acpi_reserved, cfg, 0); 540 return;
486
487 if (valid)
488 continue;
489 else
490 printk(KERN_ERR FW_BUG PREFIX
491 "MMCONFIG at %pR not reserved in "
492 "ACPI motherboard resources\n",
493 &cfg->res);
494 } 541 }
495
496 /* Don't try to do this check unless configuration
497 type 1 is available. how about type 2 ?*/
498 if (raw_pci_ops)
499 valid = is_mmconf_reserved(e820_all_mapped, cfg, 1);
500
501 if (!valid)
502 goto reject;
503 } 542 }
504
505 return;
506
507reject:
508 printk(KERN_INFO PREFIX "not using MMCONFIG\n");
509 free_all_mmcfg();
510} 543}
511 544
512static int __initdata known_bridge;
513
514static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg, 545static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg,
515 struct acpi_mcfg_allocation *cfg) 546 struct acpi_mcfg_allocation *cfg)
516{ 547{
@@ -529,7 +560,7 @@ static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg,
529 return 0; 560 return 0;
530 } 561 }
531 562
532 printk(KERN_ERR PREFIX "MCFG region for %04x [bus %02x-%02x] at %#llx " 563 pr_err(PREFIX "MCFG region for %04x [bus %02x-%02x] at %#llx "
533 "is above 4GB, ignored\n", cfg->pci_segment, 564 "is above 4GB, ignored\n", cfg->pci_segment,
534 cfg->start_bus_number, cfg->end_bus_number, cfg->address); 565 cfg->start_bus_number, cfg->end_bus_number, cfg->address);
535 return -EINVAL; 566 return -EINVAL;
@@ -556,7 +587,7 @@ static int __init pci_parse_mcfg(struct acpi_table_header *header)
556 i -= sizeof(struct acpi_mcfg_allocation); 587 i -= sizeof(struct acpi_mcfg_allocation);
557 }; 588 };
558 if (entries == 0) { 589 if (entries == 0) {
559 printk(KERN_ERR PREFIX "MMCONFIG has no entries\n"); 590 pr_err(PREFIX "MMCONFIG has no entries\n");
560 return -ENODEV; 591 return -ENODEV;
561 } 592 }
562 593
@@ -570,8 +601,7 @@ static int __init pci_parse_mcfg(struct acpi_table_header *header)
570 601
571 if (pci_mmconfig_add(cfg->pci_segment, cfg->start_bus_number, 602 if (pci_mmconfig_add(cfg->pci_segment, cfg->start_bus_number,
572 cfg->end_bus_number, cfg->address) == NULL) { 603 cfg->end_bus_number, cfg->address) == NULL) {
573 printk(KERN_WARNING PREFIX 604 pr_warn(PREFIX "no memory for MCFG entries\n");
574 "no memory for MCFG entries\n");
575 free_all_mmcfg(); 605 free_all_mmcfg();
576 return -ENOMEM; 606 return -ENOMEM;
577 } 607 }
@@ -582,28 +612,7 @@ static int __init pci_parse_mcfg(struct acpi_table_header *header)
582 612
583static void __init __pci_mmcfg_init(int early) 613static void __init __pci_mmcfg_init(int early)
584{ 614{
585 /* MMCONFIG disabled */
586 if ((pci_probe & PCI_PROBE_MMCONF) == 0)
587 return;
588
589 /* MMCONFIG already enabled */
590 if (!early && !(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF))
591 return;
592
593 /* for late to exit */
594 if (known_bridge)
595 return;
596
597 if (early) {
598 if (pci_mmcfg_check_hostbridge())
599 known_bridge = 1;
600 }
601
602 if (!known_bridge)
603 acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
604
605 pci_mmcfg_reject_broken(early); 615 pci_mmcfg_reject_broken(early);
606
607 if (list_empty(&pci_mmcfg_list)) 616 if (list_empty(&pci_mmcfg_list))
608 return; 617 return;
609 618
@@ -620,33 +629,48 @@ static void __init __pci_mmcfg_init(int early)
620 if (pci_mmcfg_arch_init()) 629 if (pci_mmcfg_arch_init())
621 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF; 630 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
622 else { 631 else {
623 /* 632 free_all_mmcfg();
624 * Signal not to attempt to insert mmcfg resources because 633 pci_mmcfg_arch_init_failed = true;
625 * the architecture mmcfg setup could not initialize.
626 */
627 pci_mmcfg_resources_inserted = 1;
628 } 634 }
629} 635}
630 636
637static int __initdata known_bridge;
638
631void __init pci_mmcfg_early_init(void) 639void __init pci_mmcfg_early_init(void)
632{ 640{
633 __pci_mmcfg_init(1); 641 if (pci_probe & PCI_PROBE_MMCONF) {
642 if (pci_mmcfg_check_hostbridge())
643 known_bridge = 1;
644 else
645 acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
646 __pci_mmcfg_init(1);
647 }
634} 648}
635 649
636void __init pci_mmcfg_late_init(void) 650void __init pci_mmcfg_late_init(void)
637{ 651{
638 __pci_mmcfg_init(0); 652 /* MMCONFIG disabled */
653 if ((pci_probe & PCI_PROBE_MMCONF) == 0)
654 return;
655
656 if (known_bridge)
657 return;
658
659 /* MMCONFIG hasn't been enabled yet, try again */
660 if (pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF) {
661 acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
662 __pci_mmcfg_init(0);
663 }
639} 664}
640 665
641static int __init pci_mmcfg_late_insert_resources(void) 666static int __init pci_mmcfg_late_insert_resources(void)
642{ 667{
643 /* 668 struct pci_mmcfg_region *cfg;
644 * If resources are already inserted or we are not using MMCONFIG, 669
645 * don't insert the resources. 670 pci_mmcfg_running_state = true;
646 */ 671
647 if ((pci_mmcfg_resources_inserted == 1) || 672 /* If we are not using MMCONFIG, don't insert the resources. */
648 (pci_probe & PCI_PROBE_MMCONF) == 0 || 673 if ((pci_probe & PCI_PROBE_MMCONF) == 0)
649 list_empty(&pci_mmcfg_list))
650 return 1; 674 return 1;
651 675
652 /* 676 /*
@@ -654,7 +678,9 @@ static int __init pci_mmcfg_late_insert_resources(void)
654 * marked so it won't cause request errors when __request_region is 678 * marked so it won't cause request errors when __request_region is
655 * called. 679 * called.
656 */ 680 */
657 pci_mmcfg_insert_resources(); 681 list_for_each_entry(cfg, &pci_mmcfg_list, list)
682 if (!cfg->res.parent)
683 insert_resource(&iomem_resource, &cfg->res);
658 684
659 return 0; 685 return 0;
660} 686}
@@ -665,3 +691,101 @@ static int __init pci_mmcfg_late_insert_resources(void)
665 * with other system resources. 691 * with other system resources.
666 */ 692 */
667late_initcall(pci_mmcfg_late_insert_resources); 693late_initcall(pci_mmcfg_late_insert_resources);
694
695/* Add MMCFG information for host bridges */
696int __devinit pci_mmconfig_insert(struct device *dev,
697 u16 seg, u8 start, u8 end,
698 phys_addr_t addr)
699{
700 int rc;
701 struct resource *tmp = NULL;
702 struct pci_mmcfg_region *cfg;
703
704 if (!(pci_probe & PCI_PROBE_MMCONF) || pci_mmcfg_arch_init_failed)
705 return -ENODEV;
706
707 if (start > end)
708 return -EINVAL;
709
710 mutex_lock(&pci_mmcfg_lock);
711 cfg = pci_mmconfig_lookup(seg, start);
712 if (cfg) {
713 if (cfg->end_bus < end)
714 dev_info(dev, FW_INFO
715 "MMCONFIG for "
716 "domain %04x [bus %02x-%02x] "
717 "only partially covers this bridge\n",
718 cfg->segment, cfg->start_bus, cfg->end_bus);
719 mutex_unlock(&pci_mmcfg_lock);
720 return -EEXIST;
721 }
722
723 if (!addr) {
724 mutex_unlock(&pci_mmcfg_lock);
725 return -EINVAL;
726 }
727
728 rc = -EBUSY;
729 cfg = pci_mmconfig_alloc(seg, start, end, addr);
730 if (cfg == NULL) {
731 dev_warn(dev, "fail to add MMCONFIG (out of memory)\n");
732 rc = -ENOMEM;
733 } else if (!pci_mmcfg_check_reserved(dev, cfg, 0)) {
734 dev_warn(dev, FW_BUG "MMCONFIG %pR isn't reserved\n",
735 &cfg->res);
736 } else {
737 /* Insert resource if it's not in boot stage */
738 if (pci_mmcfg_running_state)
739 tmp = insert_resource_conflict(&iomem_resource,
740 &cfg->res);
741
742 if (tmp) {
743 dev_warn(dev,
744 "MMCONFIG %pR conflicts with "
745 "%s %pR\n",
746 &cfg->res, tmp->name, tmp);
747 } else if (pci_mmcfg_arch_map(cfg)) {
748 dev_warn(dev, "fail to map MMCONFIG %pR.\n",
749 &cfg->res);
750 } else {
751 list_add_sorted(cfg);
752 dev_info(dev, "MMCONFIG at %pR (base %#lx)\n",
753 &cfg->res, (unsigned long)addr);
754 cfg = NULL;
755 rc = 0;
756 }
757 }
758
759 if (cfg) {
760 if (cfg->res.parent)
761 release_resource(&cfg->res);
762 kfree(cfg);
763 }
764
765 mutex_unlock(&pci_mmcfg_lock);
766
767 return rc;
768}
769
770/* Delete MMCFG information for host bridges */
771int pci_mmconfig_delete(u16 seg, u8 start, u8 end)
772{
773 struct pci_mmcfg_region *cfg;
774
775 mutex_lock(&pci_mmcfg_lock);
776 list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list)
777 if (cfg->segment == seg && cfg->start_bus == start &&
778 cfg->end_bus == end) {
779 list_del_rcu(&cfg->list);
780 synchronize_rcu();
781 pci_mmcfg_arch_unmap(cfg);
782 if (cfg->res.parent)
783 release_resource(&cfg->res);
784 mutex_unlock(&pci_mmcfg_lock);
785 kfree(cfg);
786 return 0;
787 }
788 mutex_unlock(&pci_mmcfg_lock);
789
790 return -ENOENT;
791}
diff --git a/arch/x86/pci/mmconfig_32.c b/arch/x86/pci/mmconfig_32.c
index 5372e86834c0..db63ac23e3d9 100644
--- a/arch/x86/pci/mmconfig_32.c
+++ b/arch/x86/pci/mmconfig_32.c
@@ -11,6 +11,7 @@
11 11
12#include <linux/pci.h> 12#include <linux/pci.h>
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/rcupdate.h>
14#include <asm/e820.h> 15#include <asm/e820.h>
15#include <asm/pci_x86.h> 16#include <asm/pci_x86.h>
16#include <acpi/acpi.h> 17#include <acpi/acpi.h>
@@ -60,9 +61,12 @@ err: *value = -1;
60 return -EINVAL; 61 return -EINVAL;
61 } 62 }
62 63
64 rcu_read_lock();
63 base = get_base_addr(seg, bus, devfn); 65 base = get_base_addr(seg, bus, devfn);
64 if (!base) 66 if (!base) {
67 rcu_read_unlock();
65 goto err; 68 goto err;
69 }
66 70
67 raw_spin_lock_irqsave(&pci_config_lock, flags); 71 raw_spin_lock_irqsave(&pci_config_lock, flags);
68 72
@@ -80,6 +84,7 @@ err: *value = -1;
80 break; 84 break;
81 } 85 }
82 raw_spin_unlock_irqrestore(&pci_config_lock, flags); 86 raw_spin_unlock_irqrestore(&pci_config_lock, flags);
87 rcu_read_unlock();
83 88
84 return 0; 89 return 0;
85} 90}
@@ -93,9 +98,12 @@ static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
93 if ((bus > 255) || (devfn > 255) || (reg > 4095)) 98 if ((bus > 255) || (devfn > 255) || (reg > 4095))
94 return -EINVAL; 99 return -EINVAL;
95 100
101 rcu_read_lock();
96 base = get_base_addr(seg, bus, devfn); 102 base = get_base_addr(seg, bus, devfn);
97 if (!base) 103 if (!base) {
104 rcu_read_unlock();
98 return -EINVAL; 105 return -EINVAL;
106 }
99 107
100 raw_spin_lock_irqsave(&pci_config_lock, flags); 108 raw_spin_lock_irqsave(&pci_config_lock, flags);
101 109
@@ -113,11 +121,12 @@ static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
113 break; 121 break;
114 } 122 }
115 raw_spin_unlock_irqrestore(&pci_config_lock, flags); 123 raw_spin_unlock_irqrestore(&pci_config_lock, flags);
124 rcu_read_unlock();
116 125
117 return 0; 126 return 0;
118} 127}
119 128
120static const struct pci_raw_ops pci_mmcfg = { 129const struct pci_raw_ops pci_mmcfg = {
121 .read = pci_mmcfg_read, 130 .read = pci_mmcfg_read,
122 .write = pci_mmcfg_write, 131 .write = pci_mmcfg_write,
123}; 132};
@@ -132,3 +141,18 @@ int __init pci_mmcfg_arch_init(void)
132void __init pci_mmcfg_arch_free(void) 141void __init pci_mmcfg_arch_free(void)
133{ 142{
134} 143}
144
145int __devinit pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg)
146{
147 return 0;
148}
149
150void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg)
151{
152 unsigned long flags;
153
154 /* Invalidate the cached mmcfg map entry. */
155 raw_spin_lock_irqsave(&pci_config_lock, flags);
156 mmcfg_last_accessed_device = 0;
157 raw_spin_unlock_irqrestore(&pci_config_lock, flags);
158}
diff --git a/arch/x86/pci/mmconfig_64.c b/arch/x86/pci/mmconfig_64.c
index 915a493502cb..d4ebd07c306d 100644
--- a/arch/x86/pci/mmconfig_64.c
+++ b/arch/x86/pci/mmconfig_64.c
@@ -9,6 +9,7 @@
9#include <linux/init.h> 9#include <linux/init.h>
10#include <linux/acpi.h> 10#include <linux/acpi.h>
11#include <linux/bitmap.h> 11#include <linux/bitmap.h>
12#include <linux/rcupdate.h>
12#include <asm/e820.h> 13#include <asm/e820.h>
13#include <asm/pci_x86.h> 14#include <asm/pci_x86.h>
14 15
@@ -34,9 +35,12 @@ err: *value = -1;
34 return -EINVAL; 35 return -EINVAL;
35 } 36 }
36 37
38 rcu_read_lock();
37 addr = pci_dev_base(seg, bus, devfn); 39 addr = pci_dev_base(seg, bus, devfn);
38 if (!addr) 40 if (!addr) {
41 rcu_read_unlock();
39 goto err; 42 goto err;
43 }
40 44
41 switch (len) { 45 switch (len) {
42 case 1: 46 case 1:
@@ -49,6 +53,7 @@ err: *value = -1;
49 *value = mmio_config_readl(addr + reg); 53 *value = mmio_config_readl(addr + reg);
50 break; 54 break;
51 } 55 }
56 rcu_read_unlock();
52 57
53 return 0; 58 return 0;
54} 59}
@@ -62,9 +67,12 @@ static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
62 if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095))) 67 if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095)))
63 return -EINVAL; 68 return -EINVAL;
64 69
70 rcu_read_lock();
65 addr = pci_dev_base(seg, bus, devfn); 71 addr = pci_dev_base(seg, bus, devfn);
66 if (!addr) 72 if (!addr) {
73 rcu_read_unlock();
67 return -EINVAL; 74 return -EINVAL;
75 }
68 76
69 switch (len) { 77 switch (len) {
70 case 1: 78 case 1:
@@ -77,16 +85,17 @@ static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
77 mmio_config_writel(addr + reg, value); 85 mmio_config_writel(addr + reg, value);
78 break; 86 break;
79 } 87 }
88 rcu_read_unlock();
80 89
81 return 0; 90 return 0;
82} 91}
83 92
84static const struct pci_raw_ops pci_mmcfg = { 93const struct pci_raw_ops pci_mmcfg = {
85 .read = pci_mmcfg_read, 94 .read = pci_mmcfg_read,
86 .write = pci_mmcfg_write, 95 .write = pci_mmcfg_write,
87}; 96};
88 97
89static void __iomem * __init mcfg_ioremap(struct pci_mmcfg_region *cfg) 98static void __iomem * __devinit mcfg_ioremap(struct pci_mmcfg_region *cfg)
90{ 99{
91 void __iomem *addr; 100 void __iomem *addr;
92 u64 start, size; 101 u64 start, size;
@@ -105,16 +114,14 @@ int __init pci_mmcfg_arch_init(void)
105{ 114{
106 struct pci_mmcfg_region *cfg; 115 struct pci_mmcfg_region *cfg;
107 116
108 list_for_each_entry(cfg, &pci_mmcfg_list, list) { 117 list_for_each_entry(cfg, &pci_mmcfg_list, list)
109 cfg->virt = mcfg_ioremap(cfg); 118 if (pci_mmcfg_arch_map(cfg)) {
110 if (!cfg->virt) {
111 printk(KERN_ERR PREFIX "can't map MMCONFIG at %pR\n",
112 &cfg->res);
113 pci_mmcfg_arch_free(); 119 pci_mmcfg_arch_free();
114 return 0; 120 return 0;
115 } 121 }
116 } 122
117 raw_pci_ext_ops = &pci_mmcfg; 123 raw_pci_ext_ops = &pci_mmcfg;
124
118 return 1; 125 return 1;
119} 126}
120 127
@@ -122,10 +129,25 @@ void __init pci_mmcfg_arch_free(void)
122{ 129{
123 struct pci_mmcfg_region *cfg; 130 struct pci_mmcfg_region *cfg;
124 131
125 list_for_each_entry(cfg, &pci_mmcfg_list, list) { 132 list_for_each_entry(cfg, &pci_mmcfg_list, list)
126 if (cfg->virt) { 133 pci_mmcfg_arch_unmap(cfg);
127 iounmap(cfg->virt + PCI_MMCFG_BUS_OFFSET(cfg->start_bus)); 134}
128 cfg->virt = NULL; 135
129 } 136int __devinit pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg)
137{
138 cfg->virt = mcfg_ioremap(cfg);
139 if (!cfg->virt) {
140 pr_err(PREFIX "can't map MMCONFIG at %pR\n", &cfg->res);
141 return -ENOMEM;
142 }
143
144 return 0;
145}
146
147void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg)
148{
149 if (cfg && cfg->virt) {
150 iounmap(cfg->virt + PCI_MMCFG_BUS_OFFSET(cfg->start_bus));
151 cfg->virt = NULL;
130 } 152 }
131} 153}
diff --git a/arch/x86/pci/mrst.c b/arch/x86/pci/mrst.c
index 140942f66b31..e14a2ff708b5 100644
--- a/arch/x86/pci/mrst.c
+++ b/arch/x86/pci/mrst.c
@@ -264,7 +264,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_d3delay_fixup);
264 264
265static void __devinit mrst_power_off_unused_dev(struct pci_dev *dev) 265static void __devinit mrst_power_off_unused_dev(struct pci_dev *dev)
266{ 266{
267 pci_set_power_state(dev, PCI_D3cold); 267 pci_set_power_state(dev, PCI_D3hot);
268} 268}
269DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0801, mrst_power_off_unused_dev); 269DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0801, mrst_power_off_unused_dev);
270DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0809, mrst_power_off_unused_dev); 270DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0809, mrst_power_off_unused_dev);
diff --git a/arch/xtensa/kernel/pci.c b/arch/xtensa/kernel/pci.c
index 3a2cae4558b3..69759e9cb3ea 100644
--- a/arch/xtensa/kernel/pci.c
+++ b/arch/xtensa/kernel/pci.c
@@ -186,7 +186,7 @@ static int __init pcibios_init(void)
186 bus = pci_scan_root_bus(NULL, pci_ctrl->first_busno, 186 bus = pci_scan_root_bus(NULL, pci_ctrl->first_busno,
187 pci_ctrl->ops, pci_ctrl, &resources); 187 pci_ctrl->ops, pci_ctrl, &resources);
188 pci_ctrl->bus = bus; 188 pci_ctrl->bus = bus;
189 pci_ctrl->last_busno = bus->subordinate; 189 pci_ctrl->last_busno = bus->busn_res.end;
190 if (next_busno <= pci_ctrl->last_busno) 190 if (next_busno <= pci_ctrl->last_busno)
191 next_busno = pci_ctrl->last_busno+1; 191 next_busno = pci_ctrl->last_busno+1;
192 } 192 }
diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c
index 7aff6312ce7c..ec54014c321c 100644
--- a/drivers/acpi/pci_root.c
+++ b/drivers/acpi/pci_root.c
@@ -505,6 +505,8 @@ static int __devinit acpi_pci_root_add(struct acpi_device *device)
505 strcpy(acpi_device_class(device), ACPI_PCI_ROOT_CLASS); 505 strcpy(acpi_device_class(device), ACPI_PCI_ROOT_CLASS);
506 device->driver_data = root; 506 device->driver_data = root;
507 507
508 root->mcfg_addr = acpi_pci_root_get_mcfg_addr(device->handle);
509
508 /* 510 /*
509 * All supported architectures that use ACPI have support for 511 * All supported architectures that use ACPI have support for
510 * PCI domains, so we indicate this in _OSC support capabilities. 512 * PCI domains, so we indicate this in _OSC support capabilities.
diff --git a/drivers/acpi/sleep.c b/drivers/acpi/sleep.c
index 88561029cca8..1cc02ca2af2a 100644
--- a/drivers/acpi/sleep.c
+++ b/drivers/acpi/sleep.c
@@ -716,8 +716,9 @@ int acpi_suspend(u32 acpi_state)
716 * @dev: device to examine; its driver model wakeup flags control 716 * @dev: device to examine; its driver model wakeup flags control
717 * whether it should be able to wake up the system 717 * whether it should be able to wake up the system
718 * @d_min_p: used to store the upper limit of allowed states range 718 * @d_min_p: used to store the upper limit of allowed states range
719 * Return value: preferred power state of the device on success, -ENODEV on 719 * @d_max_in: specify the lowest allowed states
720 * failure (ie. if there's no 'struct acpi_device' for @dev) 720 * Return value: preferred power state of the device on success, -ENODEV
721 * (ie. if there's no 'struct acpi_device' for @dev) or -EINVAL on failure
721 * 722 *
722 * Find the lowest power (highest number) ACPI device power state that 723 * Find the lowest power (highest number) ACPI device power state that
723 * device @dev can be in while the system is in the sleep state represented 724 * device @dev can be in while the system is in the sleep state represented
@@ -732,13 +733,15 @@ int acpi_suspend(u32 acpi_state)
732 * via @wake. 733 * via @wake.
733 */ 734 */
734 735
735int acpi_pm_device_sleep_state(struct device *dev, int *d_min_p) 736int acpi_pm_device_sleep_state(struct device *dev, int *d_min_p, int d_max_in)
736{ 737{
737 acpi_handle handle = DEVICE_ACPI_HANDLE(dev); 738 acpi_handle handle = DEVICE_ACPI_HANDLE(dev);
738 struct acpi_device *adev; 739 struct acpi_device *adev;
739 char acpi_method[] = "_SxD"; 740 char acpi_method[] = "_SxD";
740 unsigned long long d_min, d_max; 741 unsigned long long d_min, d_max;
741 742
743 if (d_max_in < ACPI_STATE_D0 || d_max_in > ACPI_STATE_D3)
744 return -EINVAL;
742 if (!handle || ACPI_FAILURE(acpi_bus_get_device(handle, &adev))) { 745 if (!handle || ACPI_FAILURE(acpi_bus_get_device(handle, &adev))) {
743 printk(KERN_DEBUG "ACPI handle has no context!\n"); 746 printk(KERN_DEBUG "ACPI handle has no context!\n");
744 return -ENODEV; 747 return -ENODEV;
@@ -746,8 +749,10 @@ int acpi_pm_device_sleep_state(struct device *dev, int *d_min_p)
746 749
747 acpi_method[2] = '0' + acpi_target_sleep_state; 750 acpi_method[2] = '0' + acpi_target_sleep_state;
748 /* 751 /*
749 * If the sleep state is S0, we will return D3, but if the device has 752 * If the sleep state is S0, the lowest limit from ACPI is D3,
750 * _S0W, we will use the value from _S0W 753 * but if the device has _S0W, we will use the value from _S0W
754 * as the lowest limit from ACPI. Finally, we will constrain
755 * the lowest limit with the specified one.
751 */ 756 */
752 d_min = ACPI_STATE_D0; 757 d_min = ACPI_STATE_D0;
753 d_max = ACPI_STATE_D3; 758 d_max = ACPI_STATE_D3;
@@ -791,8 +796,17 @@ int acpi_pm_device_sleep_state(struct device *dev, int *d_min_p)
791 } 796 }
792 } 797 }
793 798
799 if (d_max_in < d_min)
800 return -EINVAL;
794 if (d_min_p) 801 if (d_min_p)
795 *d_min_p = d_min; 802 *d_min_p = d_min;
803 /* constrain d_max with specified lowest limit (max number) */
804 if (d_max > d_max_in) {
805 for (d_max = d_max_in; d_max > d_min; d_max--) {
806 if (adev->power.states[d_max].flags.valid)
807 break;
808 }
809 }
796 return d_max; 810 return d_max;
797} 811}
798#endif /* CONFIG_PM */ 812#endif /* CONFIG_PM */
diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
index b12af2ff8c54..2fb7d1598a68 100644
--- a/drivers/iommu/intel-iommu.c
+++ b/drivers/iommu/intel-iommu.c
@@ -661,7 +661,7 @@ static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn)
661 if (drhd->devices[i] && 661 if (drhd->devices[i] &&
662 drhd->devices[i]->subordinate && 662 drhd->devices[i]->subordinate &&
663 drhd->devices[i]->subordinate->number <= bus && 663 drhd->devices[i]->subordinate->number <= bus &&
664 drhd->devices[i]->subordinate->subordinate >= bus) 664 drhd->devices[i]->subordinate->busn_res.end >= bus)
665 return drhd->iommu; 665 return drhd->iommu;
666 } 666 }
667 667
diff --git a/drivers/misc/cb710/core.c b/drivers/misc/cb710/core.c
index 85cc7710193c..9d5eed754666 100644
--- a/drivers/misc/cb710/core.c
+++ b/drivers/misc/cb710/core.c
@@ -180,7 +180,7 @@ static int cb710_suspend(struct pci_dev *pdev, pm_message_t state)
180 pci_save_state(pdev); 180 pci_save_state(pdev);
181 pci_disable_device(pdev); 181 pci_disable_device(pdev);
182 if (state.event & PM_EVENT_SLEEP) 182 if (state.event & PM_EVENT_SLEEP)
183 pci_set_power_state(pdev, PCI_D3cold); 183 pci_set_power_state(pdev, PCI_D3hot);
184 return 0; 184 return 0;
185} 185}
186 186
diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c
index edeeb516807a..09fa3c687a1f 100644
--- a/drivers/net/ethernet/broadcom/tg3.c
+++ b/drivers/net/ethernet/broadcom/tg3.c
@@ -14168,7 +14168,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
14168 if (bridge->subordinate && 14168 if (bridge->subordinate &&
14169 (bridge->subordinate->number <= 14169 (bridge->subordinate->number <=
14170 tp->pdev->bus->number) && 14170 tp->pdev->bus->number) &&
14171 (bridge->subordinate->subordinate >= 14171 (bridge->subordinate->busn_res.end >=
14172 tp->pdev->bus->number)) { 14172 tp->pdev->bus->number)) {
14173 tg3_flag_set(tp, 5701_DMA_BUG); 14173 tg3_flag_set(tp, 5701_DMA_BUG);
14174 pci_dev_put(bridge); 14174 pci_dev_put(bridge);
@@ -14196,7 +14196,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
14196 if (bridge && bridge->subordinate && 14196 if (bridge && bridge->subordinate &&
14197 (bridge->subordinate->number <= 14197 (bridge->subordinate->number <=
14198 tp->pdev->bus->number) && 14198 tp->pdev->bus->number) &&
14199 (bridge->subordinate->subordinate >= 14199 (bridge->subordinate->busn_res.end >=
14200 tp->pdev->bus->number)) { 14200 tp->pdev->bus->number)) {
14201 tg3_flag_set(tp, 40BIT_DMA_BUG); 14201 tg3_flag_set(tp, 40BIT_DMA_BUG);
14202 pci_dev_put(bridge); 14202 pci_dev_put(bridge);
diff --git a/drivers/parisc/dino.c b/drivers/parisc/dino.c
index 432d4bbcc62a..ffddc4f64268 100644
--- a/drivers/parisc/dino.c
+++ b/drivers/parisc/dino.c
@@ -174,7 +174,7 @@ static int dino_cfg_read(struct pci_bus *bus, unsigned int devfn, int where,
174 int size, u32 *val) 174 int size, u32 *val)
175{ 175{
176 struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge)); 176 struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge));
177 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary; 177 u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
178 u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3); 178 u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3);
179 void __iomem *base_addr = d->hba.base_addr; 179 void __iomem *base_addr = d->hba.base_addr;
180 unsigned long flags; 180 unsigned long flags;
@@ -209,7 +209,7 @@ static int dino_cfg_write(struct pci_bus *bus, unsigned int devfn, int where,
209 int size, u32 val) 209 int size, u32 val)
210{ 210{
211 struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge)); 211 struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge));
212 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary; 212 u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
213 u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3); 213 u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3);
214 void __iomem *base_addr = d->hba.base_addr; 214 void __iomem *base_addr = d->hba.base_addr;
215 unsigned long flags; 215 unsigned long flags;
@@ -554,7 +554,7 @@ dino_fixup_bus(struct pci_bus *bus)
554 struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge)); 554 struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge));
555 555
556 DBG(KERN_WARNING "%s(0x%p) bus %d platform_data 0x%p\n", 556 DBG(KERN_WARNING "%s(0x%p) bus %d platform_data 0x%p\n",
557 __func__, bus, bus->secondary, 557 __func__, bus, bus->busn_res.start,
558 bus->bridge->platform_data); 558 bus->bridge->platform_data);
559 559
560 /* Firmware doesn't set up card-mode dino, so we have to */ 560 /* Firmware doesn't set up card-mode dino, so we have to */
@@ -898,6 +898,7 @@ static int __init dino_probe(struct parisc_device *dev)
898 LIST_HEAD(resources); 898 LIST_HEAD(resources);
899 struct pci_bus *bus; 899 struct pci_bus *bus;
900 unsigned long hpa = dev->hpa.start; 900 unsigned long hpa = dev->hpa.start;
901 int max;
901 902
902 name = "Dino"; 903 name = "Dino";
903 if (is_card_dino(&dev->id)) { 904 if (is_card_dino(&dev->id)) {
@@ -983,6 +984,10 @@ static int __init dino_probe(struct parisc_device *dev)
983 if (dino_dev->hba.gmmio_space.flags) 984 if (dino_dev->hba.gmmio_space.flags)
984 pci_add_resource(&resources, &dino_dev->hba.gmmio_space); 985 pci_add_resource(&resources, &dino_dev->hba.gmmio_space);
985 986
987 dino_dev->hba.bus_num.start = dino_current_bus;
988 dino_dev->hba.bus_num.end = 255;
989 dino_dev->hba.bus_num.flags = IORESOURCE_BUS;
990 pci_add_resource(&resources, &dino_dev->hba.bus_num);
986 /* 991 /*
987 ** It's not used to avoid chicken/egg problems 992 ** It's not used to avoid chicken/egg problems
988 ** with configuration accessor functions. 993 ** with configuration accessor functions.
@@ -998,12 +1003,13 @@ static int __init dino_probe(struct parisc_device *dev)
998 return 0; 1003 return 0;
999 } 1004 }
1000 1005
1001 bus->subordinate = pci_scan_child_bus(bus); 1006 max = pci_scan_child_bus(bus);
1007 pci_bus_update_busn_res_end(bus, max);
1002 1008
1003 /* This code *depends* on scanning being single threaded 1009 /* This code *depends* on scanning being single threaded
1004 * if it isn't, this global bus number count will fail 1010 * if it isn't, this global bus number count will fail
1005 */ 1011 */
1006 dino_current_bus = bus->subordinate + 1; 1012 dino_current_bus = max + 1;
1007 pci_bus_assign_resources(bus); 1013 pci_bus_assign_resources(bus);
1008 pci_bus_add_devices(bus); 1014 pci_bus_add_devices(bus);
1009 return 0; 1015 return 0;
diff --git a/drivers/parisc/iosapic.c b/drivers/parisc/iosapic.c
index 1f9e9fefb8e7..83380c8fcb6b 100644
--- a/drivers/parisc/iosapic.c
+++ b/drivers/parisc/iosapic.c
@@ -532,7 +532,7 @@ iosapic_xlate_pin(struct iosapic_info *isi, struct pci_dev *pcidev)
532 intr_slot = PCI_SLOT(pcidev->devfn); 532 intr_slot = PCI_SLOT(pcidev->devfn);
533 } 533 }
534 DBG_IRT("iosapic_xlate_pin: bus %d slot %d pin %d\n", 534 DBG_IRT("iosapic_xlate_pin: bus %d slot %d pin %d\n",
535 pcidev->bus->secondary, intr_slot, intr_pin); 535 pcidev->bus->busn_res.start, intr_slot, intr_pin);
536 536
537 return irt_find_irqline(isi, intr_slot, intr_pin); 537 return irt_find_irqline(isi, intr_slot, intr_pin);
538} 538}
diff --git a/drivers/parisc/lba_pci.c b/drivers/parisc/lba_pci.c
index 052fa230bc77..4f9cf2456f4e 100644
--- a/drivers/parisc/lba_pci.c
+++ b/drivers/parisc/lba_pci.c
@@ -189,8 +189,8 @@ lba_dump_res(struct resource *r, int d)
189 189
190static int lba_device_present(u8 bus, u8 dfn, struct lba_device *d) 190static int lba_device_present(u8 bus, u8 dfn, struct lba_device *d)
191{ 191{
192 u8 first_bus = d->hba.hba_bus->secondary; 192 u8 first_bus = d->hba.hba_bus->busn_res.start;
193 u8 last_sub_bus = d->hba.hba_bus->subordinate; 193 u8 last_sub_bus = d->hba.hba_bus->busn_res.end;
194 194
195 if ((bus < first_bus) || 195 if ((bus < first_bus) ||
196 (bus > last_sub_bus) || 196 (bus > last_sub_bus) ||
@@ -364,7 +364,7 @@ lba_rd_cfg(struct lba_device *d, u32 tok, u8 reg, u32 size)
364static int elroy_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data) 364static int elroy_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data)
365{ 365{
366 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge)); 366 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
367 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary; 367 u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
368 u32 tok = LBA_CFG_TOK(local_bus, devfn); 368 u32 tok = LBA_CFG_TOK(local_bus, devfn);
369 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; 369 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
370 370
@@ -380,7 +380,7 @@ static int elroy_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int
380 return 0; 380 return 0;
381 } 381 }
382 382
383 if (LBA_SKIP_PROBE(d) && !lba_device_present(bus->secondary, devfn, d)) { 383 if (LBA_SKIP_PROBE(d) && !lba_device_present(bus->busn_res.start, devfn, d)) {
384 DBG_CFG("%s(%x+%2x) -> -1 (b)\n", __func__, tok, pos); 384 DBG_CFG("%s(%x+%2x) -> -1 (b)\n", __func__, tok, pos);
385 /* either don't want to look or know device isn't present. */ 385 /* either don't want to look or know device isn't present. */
386 *data = ~0U; 386 *data = ~0U;
@@ -431,7 +431,7 @@ lba_wr_cfg(struct lba_device *d, u32 tok, u8 reg, u32 data, u32 size)
431static int elroy_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data) 431static int elroy_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data)
432{ 432{
433 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge)); 433 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
434 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary; 434 u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
435 u32 tok = LBA_CFG_TOK(local_bus,devfn); 435 u32 tok = LBA_CFG_TOK(local_bus,devfn);
436 436
437 if ((pos > 255) || (devfn > 255)) 437 if ((pos > 255) || (devfn > 255))
@@ -444,7 +444,7 @@ static int elroy_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int
444 return 0; 444 return 0;
445 } 445 }
446 446
447 if (LBA_SKIP_PROBE(d) && (!lba_device_present(bus->secondary, devfn, d))) { 447 if (LBA_SKIP_PROBE(d) && (!lba_device_present(bus->busn_res.start, devfn, d))) {
448 DBG_CFG("%s(%x+%2x) = 0x%x (b)\n", __func__, tok, pos,data); 448 DBG_CFG("%s(%x+%2x) = 0x%x (b)\n", __func__, tok, pos,data);
449 return 1; /* New Workaround */ 449 return 1; /* New Workaround */
450 } 450 }
@@ -481,7 +481,7 @@ static struct pci_ops elroy_cfg_ops = {
481static int mercury_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data) 481static int mercury_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data)
482{ 482{
483 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge)); 483 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
484 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary; 484 u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
485 u32 tok = LBA_CFG_TOK(local_bus, devfn); 485 u32 tok = LBA_CFG_TOK(local_bus, devfn);
486 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; 486 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
487 487
@@ -514,7 +514,7 @@ static int mercury_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, i
514{ 514{
515 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge)); 515 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
516 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; 516 void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
517 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary; 517 u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
518 u32 tok = LBA_CFG_TOK(local_bus,devfn); 518 u32 tok = LBA_CFG_TOK(local_bus,devfn);
519 519
520 if ((pos > 255) || (devfn > 255)) 520 if ((pos > 255) || (devfn > 255))
@@ -636,7 +636,7 @@ lba_fixup_bus(struct pci_bus *bus)
636 struct lba_device *ldev = LBA_DEV(parisc_walk_tree(bus->bridge)); 636 struct lba_device *ldev = LBA_DEV(parisc_walk_tree(bus->bridge));
637 637
638 DBG("lba_fixup_bus(0x%p) bus %d platform_data 0x%p\n", 638 DBG("lba_fixup_bus(0x%p) bus %d platform_data 0x%p\n",
639 bus, bus->secondary, bus->bridge->platform_data); 639 bus, (int)bus->busn_res.start, bus->bridge->platform_data);
640 640
641 /* 641 /*
642 ** Properly Setup MMIO resources for this bus. 642 ** Properly Setup MMIO resources for this bus.
@@ -989,6 +989,7 @@ lba_pat_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
989 case PAT_PBNUM: 989 case PAT_PBNUM:
990 lba_dev->hba.bus_num.start = p->start; 990 lba_dev->hba.bus_num.start = p->start;
991 lba_dev->hba.bus_num.end = p->end; 991 lba_dev->hba.bus_num.end = p->end;
992 lba_dev->hba.bus_num.flags = IORESOURCE_BUS;
992 break; 993 break;
993 994
994 case PAT_LMMIO: 995 case PAT_LMMIO:
@@ -1366,6 +1367,7 @@ lba_driver_probe(struct parisc_device *dev)
1366 void *tmp_obj; 1367 void *tmp_obj;
1367 char *version; 1368 char *version;
1368 void __iomem *addr = ioremap_nocache(dev->hpa.start, 4096); 1369 void __iomem *addr = ioremap_nocache(dev->hpa.start, 4096);
1370 int max;
1369 1371
1370 /* Read HW Rev First */ 1372 /* Read HW Rev First */
1371 func_class = READ_REG32(addr + LBA_FCLASS); 1373 func_class = READ_REG32(addr + LBA_FCLASS);
@@ -1502,6 +1504,8 @@ lba_driver_probe(struct parisc_device *dev)
1502 if (lba_dev->hba.gmmio_space.flags) 1504 if (lba_dev->hba.gmmio_space.flags)
1503 pci_add_resource(&resources, &lba_dev->hba.gmmio_space); 1505 pci_add_resource(&resources, &lba_dev->hba.gmmio_space);
1504 1506
1507 pci_add_resource(&resources, &lba_dev->hba.bus_num);
1508
1505 dev->dev.platform_data = lba_dev; 1509 dev->dev.platform_data = lba_dev;
1506 lba_bus = lba_dev->hba.hba_bus = 1510 lba_bus = lba_dev->hba.hba_bus =
1507 pci_create_root_bus(&dev->dev, lba_dev->hba.bus_num.start, 1511 pci_create_root_bus(&dev->dev, lba_dev->hba.bus_num.start,
@@ -1511,7 +1515,7 @@ lba_driver_probe(struct parisc_device *dev)
1511 return 0; 1515 return 0;
1512 } 1516 }
1513 1517
1514 lba_bus->subordinate = pci_scan_child_bus(lba_bus); 1518 max = pci_scan_child_bus(lba_bus);
1515 1519
1516 /* This is in lieu of calling pci_assign_unassigned_resources() */ 1520 /* This is in lieu of calling pci_assign_unassigned_resources() */
1517 if (is_pdc_pat()) { 1521 if (is_pdc_pat()) {
@@ -1541,7 +1545,7 @@ lba_driver_probe(struct parisc_device *dev)
1541 lba_dev->flags |= LBA_FLAG_SKIP_PROBE; 1545 lba_dev->flags |= LBA_FLAG_SKIP_PROBE;
1542 } 1546 }
1543 1547
1544 lba_next_bus = lba_bus->subordinate + 1; 1548 lba_next_bus = max + 1;
1545 pci_bus_add_devices(lba_bus); 1549 pci_bus_add_devices(lba_bus);
1546 1550
1547 /* Whew! Finally done! Tell services we got this one covered. */ 1551 /* Whew! Finally done! Tell services we got this one covered. */
diff --git a/drivers/pci/access.c b/drivers/pci/access.c
index 2a581642c237..ba91a7e17519 100644
--- a/drivers/pci/access.c
+++ b/drivers/pci/access.c
@@ -162,7 +162,8 @@ int pci_user_read_config_##size \
162 if (ret > 0) \ 162 if (ret > 0) \
163 ret = -EINVAL; \ 163 ret = -EINVAL; \
164 return ret; \ 164 return ret; \
165} 165} \
166EXPORT_SYMBOL_GPL(pci_user_read_config_##size);
166 167
167/* Returns 0 on success, negative values indicate error. */ 168/* Returns 0 on success, negative values indicate error. */
168#define PCI_USER_WRITE_CONFIG(size,type) \ 169#define PCI_USER_WRITE_CONFIG(size,type) \
@@ -181,7 +182,8 @@ int pci_user_write_config_##size \
181 if (ret > 0) \ 182 if (ret > 0) \
182 ret = -EINVAL; \ 183 ret = -EINVAL; \
183 return ret; \ 184 return ret; \
184} 185} \
186EXPORT_SYMBOL_GPL(pci_user_write_config_##size);
185 187
186PCI_USER_READ_CONFIG(byte, u8) 188PCI_USER_READ_CONFIG(byte, u8)
187PCI_USER_READ_CONFIG(word, u16) 189PCI_USER_READ_CONFIG(word, u16)
diff --git a/drivers/pci/hotplug-pci.c b/drivers/pci/hotplug-pci.c
index d3509cdeb554..6258dc260d9f 100644
--- a/drivers/pci/hotplug-pci.c
+++ b/drivers/pci/hotplug-pci.c
@@ -4,18 +4,26 @@
4#include <linux/export.h> 4#include <linux/export.h>
5#include "pci.h" 5#include "pci.h"
6 6
7 7int __ref pci_hp_add_bridge(struct pci_dev *dev)
8unsigned int __devinit pci_do_scan_bus(struct pci_bus *bus)
9{ 8{
10 unsigned int max; 9 struct pci_bus *parent = dev->bus;
11 10 int pass, busnr, start = parent->busn_res.start;
12 max = pci_scan_child_bus(bus); 11 int end = parent->busn_res.end;
13 12
14 /* 13 for (busnr = start; busnr <= end; busnr++) {
15 * Make the discovered devices available. 14 if (!pci_find_bus(pci_domain_nr(parent), busnr))
16 */ 15 break;
17 pci_bus_add_devices(bus); 16 }
17 if (busnr-- > end) {
18 printk(KERN_ERR "No bus number available for hot-added bridge %s\n",
19 pci_name(dev));
20 return -1;
21 }
22 for (pass = 0; pass < 2; pass++)
23 busnr = pci_scan_bridge(parent, dev, busnr, pass);
24 if (!dev->subordinate)
25 return -1;
18 26
19 return max; 27 return 0;
20} 28}
21EXPORT_SYMBOL(pci_do_scan_bus); 29EXPORT_SYMBOL_GPL(pci_hp_add_bridge);
diff --git a/drivers/pci/hotplug/acpiphp_glue.c b/drivers/pci/hotplug/acpiphp_glue.c
index 806c44fa645a..395c67d3d296 100644
--- a/drivers/pci/hotplug/acpiphp_glue.c
+++ b/drivers/pci/hotplug/acpiphp_glue.c
@@ -100,11 +100,11 @@ static int post_dock_fixups(struct notifier_block *nb, unsigned long val,
100 PCI_PRIMARY_BUS, 100 PCI_PRIMARY_BUS,
101 &buses); 101 &buses);
102 102
103 if (((buses >> 8) & 0xff) != bus->secondary) { 103 if (((buses >> 8) & 0xff) != bus->busn_res.start) {
104 buses = (buses & 0xff000000) 104 buses = (buses & 0xff000000)
105 | ((unsigned int)(bus->primary) << 0) 105 | ((unsigned int)(bus->primary) << 0)
106 | ((unsigned int)(bus->secondary) << 8) 106 | ((unsigned int)(bus->busn_res.start) << 8)
107 | ((unsigned int)(bus->subordinate) << 16); 107 | ((unsigned int)(bus->busn_res.end) << 16);
108 pci_write_config_dword(bus->self, PCI_PRIMARY_BUS, buses); 108 pci_write_config_dword(bus->self, PCI_PRIMARY_BUS, buses);
109 } 109 }
110 return NOTIFY_OK; 110 return NOTIFY_OK;
@@ -132,6 +132,15 @@ register_slot(acpi_handle handle, u32 lvl, void *context, void **rv)
132 if (!acpi_pci_check_ejectable(pbus, handle) && !is_dock_device(handle)) 132 if (!acpi_pci_check_ejectable(pbus, handle) && !is_dock_device(handle))
133 return AE_OK; 133 return AE_OK;
134 134
135 status = acpi_evaluate_integer(handle, "_ADR", NULL, &adr);
136 if (ACPI_FAILURE(status)) {
137 warn("can't evaluate _ADR (%#x)\n", status);
138 return AE_OK;
139 }
140
141 device = (adr >> 16) & 0xffff;
142 function = adr & 0xffff;
143
135 pdev = pbus->self; 144 pdev = pbus->self;
136 if (pdev && pci_is_pcie(pdev)) { 145 if (pdev && pci_is_pcie(pdev)) {
137 tmp = acpi_find_root_bridge_handle(pdev); 146 tmp = acpi_find_root_bridge_handle(pdev);
@@ -144,10 +153,6 @@ register_slot(acpi_handle handle, u32 lvl, void *context, void **rv)
144 } 153 }
145 } 154 }
146 155
147 acpi_evaluate_integer(handle, "_ADR", NULL, &adr);
148 device = (adr >> 16) & 0xffff;
149 function = adr & 0xffff;
150
151 newfunc = kzalloc(sizeof(struct acpiphp_func), GFP_KERNEL); 156 newfunc = kzalloc(sizeof(struct acpiphp_func), GFP_KERNEL);
152 if (!newfunc) 157 if (!newfunc)
153 return AE_NO_MEMORY; 158 return AE_NO_MEMORY;
@@ -692,7 +697,7 @@ static unsigned char acpiphp_max_busnr(struct pci_bus *bus)
692 * bus->subordinate value because it could have 697 * bus->subordinate value because it could have
693 * padding in it. 698 * padding in it.
694 */ 699 */
695 max = bus->secondary; 700 max = bus->busn_res.start;
696 701
697 list_for_each(tmp, &bus->children) { 702 list_for_each(tmp, &bus->children) {
698 n = pci_bus_max_busnr(pci_bus_b(tmp)); 703 n = pci_bus_max_busnr(pci_bus_b(tmp));
@@ -878,6 +883,24 @@ static void disable_bridges(struct pci_bus *bus)
878 } 883 }
879} 884}
880 885
886/* return first device in slot, acquiring a reference on it */
887static struct pci_dev *dev_in_slot(struct acpiphp_slot *slot)
888{
889 struct pci_bus *bus = slot->bridge->pci_bus;
890 struct pci_dev *dev;
891 struct pci_dev *ret = NULL;
892
893 down_read(&pci_bus_sem);
894 list_for_each_entry(dev, &bus->devices, bus_list)
895 if (PCI_SLOT(dev->devfn) == slot->device) {
896 ret = pci_dev_get(dev);
897 break;
898 }
899 up_read(&pci_bus_sem);
900
901 return ret;
902}
903
881/** 904/**
882 * disable_device - disable a slot 905 * disable_device - disable a slot
883 * @slot: ACPI PHP slot 906 * @slot: ACPI PHP slot
@@ -893,6 +916,7 @@ static int disable_device(struct acpiphp_slot *slot)
893 pdev = pci_get_slot(bus, PCI_DEVFN(slot->device, 0)); 916 pdev = pci_get_slot(bus, PCI_DEVFN(slot->device, 0));
894 if (!pdev) 917 if (!pdev)
895 goto err_exit; 918 goto err_exit;
919 pci_dev_put(pdev);
896 920
897 list_for_each_entry(func, &slot->funcs, sibling) { 921 list_for_each_entry(func, &slot->funcs, sibling) {
898 if (func->bridge) { 922 if (func->bridge) {
@@ -901,18 +925,22 @@ static int disable_device(struct acpiphp_slot *slot)
901 (u32)1, NULL, NULL); 925 (u32)1, NULL, NULL);
902 func->bridge = NULL; 926 func->bridge = NULL;
903 } 927 }
928 }
904 929
905 pdev = pci_get_slot(slot->bridge->pci_bus, 930 /*
906 PCI_DEVFN(slot->device, func->function)); 931 * enable_device() enumerates all functions in this device via
907 if (pdev) { 932 * pci_scan_slot(), whether they have associated ACPI hotplug
908 pci_stop_bus_device(pdev); 933 * methods (_EJ0, etc.) or not. Therefore, we remove all functions
909 if (pdev->subordinate) { 934 * here.
910 disable_bridges(pdev->subordinate); 935 */
911 pci_disable_device(pdev); 936 while ((pdev = dev_in_slot(slot))) {
912 } 937 pci_stop_bus_device(pdev);
913 __pci_remove_bus_device(pdev); 938 if (pdev->subordinate) {
914 pci_dev_put(pdev); 939 disable_bridges(pdev->subordinate);
940 pci_disable_device(pdev);
915 } 941 }
942 __pci_remove_bus_device(pdev);
943 pci_dev_put(pdev);
916 } 944 }
917 945
918 list_for_each_entry(func, &slot->funcs, sibling) { 946 list_for_each_entry(func, &slot->funcs, sibling) {
diff --git a/drivers/pci/hotplug/cpci_hotplug_pci.c b/drivers/pci/hotplug/cpci_hotplug_pci.c
index ae853ccd0cd5..dcc75c785443 100644
--- a/drivers/pci/hotplug/cpci_hotplug_pci.c
+++ b/drivers/pci/hotplug/cpci_hotplug_pci.c
@@ -285,42 +285,19 @@ int __ref cpci_configure_slot(struct slot *slot)
285 for (fn = 0; fn < 8; fn++) { 285 for (fn = 0; fn < 8; fn++) {
286 struct pci_dev *dev; 286 struct pci_dev *dev;
287 287
288 dev = pci_get_slot(parent, PCI_DEVFN(PCI_SLOT(slot->devfn), fn)); 288 dev = pci_get_slot(parent,
289 PCI_DEVFN(PCI_SLOT(slot->devfn), fn));
289 if (!dev) 290 if (!dev)
290 continue; 291 continue;
291 if ((dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) || 292 if ((dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) ||
292 (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)) { 293 (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS))
293 /* Find an unused bus number for the new bridge */ 294 pci_hp_add_bridge(dev);
294 struct pci_bus *child;
295 unsigned char busnr, start = parent->secondary;
296 unsigned char end = parent->subordinate;
297
298 for (busnr = start; busnr <= end; busnr++) {
299 if (!pci_find_bus(pci_domain_nr(parent),
300 busnr))
301 break;
302 }
303 if (busnr >= end) {
304 err("No free bus for hot-added bridge\n");
305 pci_dev_put(dev);
306 continue;
307 }
308 child = pci_add_new_bus(parent, dev, busnr);
309 if (!child) {
310 err("Cannot add new bus for %s\n",
311 pci_name(dev));
312 pci_dev_put(dev);
313 continue;
314 }
315 child->subordinate = pci_do_scan_bus(child);
316 pci_bus_size_bridges(child);
317 }
318 pci_dev_put(dev); 295 pci_dev_put(dev);
319 } 296 }
320 297
321 pci_bus_assign_resources(parent); 298 pci_assign_unassigned_bridge_resources(parent->self);
299
322 pci_bus_add_devices(parent); 300 pci_bus_add_devices(parent);
323 pci_enable_bridges(parent);
324 301
325 dbg("%s - exit", __func__); 302 dbg("%s - exit", __func__);
326 return 0; 303 return 0;
diff --git a/drivers/pci/hotplug/cpqphp_pci.c b/drivers/pci/hotplug/cpqphp_pci.c
index 1c8494021a42..09801c6945ce 100644
--- a/drivers/pci/hotplug/cpqphp_pci.c
+++ b/drivers/pci/hotplug/cpqphp_pci.c
@@ -83,7 +83,6 @@ static void __iomem *detect_HRT_floating_pointer(void __iomem *begin, void __iom
83 83
84int cpqhp_configure_device (struct controller* ctrl, struct pci_func* func) 84int cpqhp_configure_device (struct controller* ctrl, struct pci_func* func)
85{ 85{
86 unsigned char bus;
87 struct pci_bus *child; 86 struct pci_bus *child;
88 int num; 87 int num;
89 88
@@ -106,9 +105,10 @@ int cpqhp_configure_device (struct controller* ctrl, struct pci_func* func)
106 } 105 }
107 106
108 if (func->pci_dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { 107 if (func->pci_dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
109 pci_read_config_byte(func->pci_dev, PCI_SECONDARY_BUS, &bus); 108 pci_hp_add_bridge(func->pci_dev);
110 child = (struct pci_bus*) pci_add_new_bus(func->pci_dev->bus, (func->pci_dev), bus); 109 child = func->pci_dev->subordinate;
111 pci_do_scan_bus(child); 110 if (child)
111 pci_bus_add_devices(child);
112 } 112 }
113 113
114 pci_dev_put(func->pci_dev); 114 pci_dev_put(func->pci_dev);
diff --git a/drivers/pci/hotplug/ibmphp_core.c b/drivers/pci/hotplug/ibmphp_core.c
index 4fda7e6a86a7..7dccad5fc891 100644
--- a/drivers/pci/hotplug/ibmphp_core.c
+++ b/drivers/pci/hotplug/ibmphp_core.c
@@ -775,7 +775,6 @@ static u8 bus_structure_fixup(u8 busno)
775 775
776static int ibm_configure_device(struct pci_func *func) 776static int ibm_configure_device(struct pci_func *func)
777{ 777{
778 unsigned char bus;
779 struct pci_bus *child; 778 struct pci_bus *child;
780 int num; 779 int num;
781 int flag = 0; /* this is to make sure we don't double scan the bus, 780 int flag = 0; /* this is to make sure we don't double scan the bus,
@@ -805,9 +804,10 @@ static int ibm_configure_device(struct pci_func *func)
805 } 804 }
806 } 805 }
807 if (!(flag) && (func->dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)) { 806 if (!(flag) && (func->dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)) {
808 pci_read_config_byte(func->dev, PCI_SECONDARY_BUS, &bus); 807 pci_hp_add_bridge(func->dev);
809 child = pci_add_new_bus(func->dev->bus, func->dev, bus); 808 child = func->dev->subordinate;
810 pci_do_scan_bus(child); 809 if (child)
810 pci_bus_add_devices(child);
811 } 811 }
812 812
813 return 0; 813 return 0;
diff --git a/drivers/pci/hotplug/pciehp_pci.c b/drivers/pci/hotplug/pciehp_pci.c
index 47d9dc06b109..09cecaf450c5 100644
--- a/drivers/pci/hotplug/pciehp_pci.c
+++ b/drivers/pci/hotplug/pciehp_pci.c
@@ -34,29 +34,6 @@
34#include "../pci.h" 34#include "../pci.h"
35#include "pciehp.h" 35#include "pciehp.h"
36 36
37static int __ref pciehp_add_bridge(struct pci_dev *dev)
38{
39 struct pci_bus *parent = dev->bus;
40 int pass, busnr, start = parent->secondary;
41 int end = parent->subordinate;
42
43 for (busnr = start; busnr <= end; busnr++) {
44 if (!pci_find_bus(pci_domain_nr(parent), busnr))
45 break;
46 }
47 if (busnr-- > end) {
48 err("No bus number available for hot-added bridge %s\n",
49 pci_name(dev));
50 return -1;
51 }
52 for (pass = 0; pass < 2; pass++)
53 busnr = pci_scan_bridge(parent, dev, busnr, pass);
54 if (!dev->subordinate)
55 return -1;
56
57 return 0;
58}
59
60int pciehp_configure_device(struct slot *p_slot) 37int pciehp_configure_device(struct slot *p_slot)
61{ 38{
62 struct pci_dev *dev; 39 struct pci_dev *dev;
@@ -85,9 +62,8 @@ int pciehp_configure_device(struct slot *p_slot)
85 if (!dev) 62 if (!dev)
86 continue; 63 continue;
87 if ((dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) || 64 if ((dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) ||
88 (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)) { 65 (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS))
89 pciehp_add_bridge(dev); 66 pci_hp_add_bridge(dev);
90 }
91 pci_dev_put(dev); 67 pci_dev_put(dev);
92 } 68 }
93 69
diff --git a/drivers/pci/hotplug/sgi_hotplug.c b/drivers/pci/hotplug/sgi_hotplug.c
index de573113c102..f64ca92253da 100644
--- a/drivers/pci/hotplug/sgi_hotplug.c
+++ b/drivers/pci/hotplug/sgi_hotplug.c
@@ -397,13 +397,11 @@ static int enable_slot(struct hotplug_slot *bss_hotplug_slot)
397 else 397 else
398 sn_io_slot_fixup(dev); 398 sn_io_slot_fixup(dev);
399 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { 399 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
400 unsigned char sec_bus; 400 pci_hp_add_bridge(dev);
401 pci_read_config_byte(dev, PCI_SECONDARY_BUS, 401 if (dev->subordinate) {
402 &sec_bus); 402 new_bus = dev->subordinate;
403 new_bus = pci_add_new_bus(dev->bus, dev, 403 new_ppb = 1;
404 sec_bus); 404 }
405 pci_scan_child_bus(new_bus);
406 new_ppb = 1;
407 } 405 }
408 pci_dev_put(dev); 406 pci_dev_put(dev);
409 } 407 }
diff --git a/drivers/pci/hotplug/shpchp_ctrl.c b/drivers/pci/hotplug/shpchp_ctrl.c
index b00b09bdd38a..f9b5a52e4115 100644
--- a/drivers/pci/hotplug/shpchp_ctrl.c
+++ b/drivers/pci/hotplug/shpchp_ctrl.c
@@ -262,9 +262,6 @@ static int board_added(struct slot *p_slot)
262 } 262 }
263 263
264 if ((ctrl->pci_dev->vendor == 0x8086) && (ctrl->pci_dev->device == 0x0332)) { 264 if ((ctrl->pci_dev->vendor == 0x8086) && (ctrl->pci_dev->device == 0x0332)) {
265 if (slots_not_empty)
266 return WRONG_BUS_FREQUENCY;
267
268 if ((rc = p_slot->hpc_ops->set_bus_speed_mode(p_slot, PCI_SPEED_33MHz))) { 265 if ((rc = p_slot->hpc_ops->set_bus_speed_mode(p_slot, PCI_SPEED_33MHz))) {
269 ctrl_err(ctrl, "%s: Issue of set bus speed mode command" 266 ctrl_err(ctrl, "%s: Issue of set bus speed mode command"
270 " failed\n", __func__); 267 " failed\n", __func__);
diff --git a/drivers/pci/hotplug/shpchp_pci.c b/drivers/pci/hotplug/shpchp_pci.c
index df7e4bfadae3..c627ed9957d1 100644
--- a/drivers/pci/hotplug/shpchp_pci.c
+++ b/drivers/pci/hotplug/shpchp_pci.c
@@ -37,9 +37,10 @@
37int __ref shpchp_configure_device(struct slot *p_slot) 37int __ref shpchp_configure_device(struct slot *p_slot)
38{ 38{
39 struct pci_dev *dev; 39 struct pci_dev *dev;
40 struct pci_bus *parent = p_slot->ctrl->pci_dev->subordinate;
41 int num, fn;
42 struct controller *ctrl = p_slot->ctrl; 40 struct controller *ctrl = p_slot->ctrl;
41 struct pci_dev *bridge = ctrl->pci_dev;
42 struct pci_bus *parent = bridge->subordinate;
43 int num, fn;
43 44
44 dev = pci_get_slot(parent, PCI_DEVFN(p_slot->device, 0)); 45 dev = pci_get_slot(parent, PCI_DEVFN(p_slot->device, 0));
45 if (dev) { 46 if (dev) {
@@ -61,39 +62,23 @@ int __ref shpchp_configure_device(struct slot *p_slot)
61 if (!dev) 62 if (!dev)
62 continue; 63 continue;
63 if ((dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) || 64 if ((dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) ||
64 (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)) { 65 (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS))
65 /* Find an unused bus number for the new bridge */ 66 pci_hp_add_bridge(dev);
66 struct pci_bus *child; 67 pci_dev_put(dev);
67 unsigned char busnr, start = parent->secondary; 68 }
68 unsigned char end = parent->subordinate; 69
69 for (busnr = start; busnr <= end; busnr++) { 70 pci_assign_unassigned_bridge_resources(bridge);
70 if (!pci_find_bus(pci_domain_nr(parent), 71
71 busnr)) 72 for (fn = 0; fn < 8; fn++) {
72 break; 73 dev = pci_get_slot(parent, PCI_DEVFN(p_slot->device, fn));
73 } 74 if (!dev)
74 if (busnr > end) { 75 continue;
75 ctrl_err(ctrl,
76 "No free bus for hot-added bridge\n");
77 pci_dev_put(dev);
78 continue;
79 }
80 child = pci_add_new_bus(parent, dev, busnr);
81 if (!child) {
82 ctrl_err(ctrl, "Cannot add new bus for %s\n",
83 pci_name(dev));
84 pci_dev_put(dev);
85 continue;
86 }
87 child->subordinate = pci_do_scan_bus(child);
88 pci_bus_size_bridges(child);
89 }
90 pci_configure_slot(dev); 76 pci_configure_slot(dev);
91 pci_dev_put(dev); 77 pci_dev_put(dev);
92 } 78 }
93 79
94 pci_bus_assign_resources(parent);
95 pci_bus_add_devices(parent); 80 pci_bus_add_devices(parent);
96 pci_enable_bridges(parent); 81
97 return 0; 82 return 0;
98} 83}
99 84
diff --git a/drivers/pci/hotplug/shpchp_sysfs.c b/drivers/pci/hotplug/shpchp_sysfs.c
index efa30da1ae8f..eeb23ceae4a8 100644
--- a/drivers/pci/hotplug/shpchp_sysfs.c
+++ b/drivers/pci/hotplug/shpchp_sysfs.c
@@ -73,13 +73,13 @@ static ssize_t show_ctrl (struct device *dev, struct device_attribute *attr, cha
73 } 73 }
74 } 74 }
75 out += sprintf(out, "Free resources: bus numbers\n"); 75 out += sprintf(out, "Free resources: bus numbers\n");
76 for (busnr = bus->secondary; busnr <= bus->subordinate; busnr++) { 76 for (busnr = bus->busn_res.start; busnr <= bus->busn_res.end; busnr++) {
77 if (!pci_find_bus(pci_domain_nr(bus), busnr)) 77 if (!pci_find_bus(pci_domain_nr(bus), busnr))
78 break; 78 break;
79 } 79 }
80 if (busnr < bus->subordinate) 80 if (busnr < bus->busn_res.end)
81 out += sprintf(out, "start = %8.8x, length = %8.8x\n", 81 out += sprintf(out, "start = %8.8x, length = %8.8x\n",
82 busnr, (bus->subordinate - busnr)); 82 busnr, (int)(bus->busn_res.end - busnr));
83 83
84 return out - buf; 84 return out - buf;
85} 85}
diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c
index 6554e1a0f634..74bbaf82638d 100644
--- a/drivers/pci/iov.c
+++ b/drivers/pci/iov.c
@@ -47,7 +47,7 @@ static struct pci_bus *virtfn_add_bus(struct pci_bus *bus, int busnr)
47 if (!child) 47 if (!child)
48 return NULL; 48 return NULL;
49 49
50 child->subordinate = busnr; 50 pci_bus_insert_busn_res(child, busnr, busnr);
51 child->dev.parent = bus->bridge; 51 child->dev.parent = bus->bridge;
52 rc = pci_bus_add_child(child); 52 rc = pci_bus_add_child(child);
53 if (rc) { 53 if (rc) {
@@ -327,7 +327,7 @@ static int sriov_enable(struct pci_dev *dev, int nr_virtfn)
327 iov->offset = offset; 327 iov->offset = offset;
328 iov->stride = stride; 328 iov->stride = stride;
329 329
330 if (virtfn_bus(dev, nr_virtfn - 1) > dev->bus->subordinate) { 330 if (virtfn_bus(dev, nr_virtfn - 1) > dev->bus->busn_res.end) {
331 dev_err(&dev->dev, "SR-IOV: bus number out of range\n"); 331 dev_err(&dev->dev, "SR-IOV: bus number out of range\n");
332 return -ENOMEM; 332 return -ENOMEM;
333 } 333 }
diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c
index 61e2fefeedab..fbf7b26c7c8a 100644
--- a/drivers/pci/pci-acpi.c
+++ b/drivers/pci/pci-acpi.c
@@ -48,6 +48,12 @@ static void pci_acpi_wake_dev(acpi_handle handle, u32 event, void *context)
48 if (event != ACPI_NOTIFY_DEVICE_WAKE || !pci_dev) 48 if (event != ACPI_NOTIFY_DEVICE_WAKE || !pci_dev)
49 return; 49 return;
50 50
51 if (pci_dev->current_state == PCI_D3cold) {
52 pci_wakeup_event(pci_dev);
53 pm_runtime_resume(&pci_dev->dev);
54 return;
55 }
56
51 if (!pci_dev->pm_cap || !pci_dev->pme_support 57 if (!pci_dev->pm_cap || !pci_dev->pme_support
52 || pci_check_pme_status(pci_dev)) { 58 || pci_check_pme_status(pci_dev)) {
53 if (pci_dev->pme_poll) 59 if (pci_dev->pme_poll)
@@ -162,6 +168,20 @@ acpi_status pci_acpi_remove_pm_notifier(struct acpi_device *dev)
162 return remove_pm_notifier(dev, pci_acpi_wake_dev); 168 return remove_pm_notifier(dev, pci_acpi_wake_dev);
163} 169}
164 170
171phys_addr_t acpi_pci_root_get_mcfg_addr(acpi_handle handle)
172{
173 acpi_status status = AE_NOT_EXIST;
174 unsigned long long mcfg_addr;
175
176 if (handle)
177 status = acpi_evaluate_integer(handle, METHOD_NAME__CBA,
178 NULL, &mcfg_addr);
179 if (ACPI_FAILURE(status))
180 return 0;
181
182 return (phys_addr_t)mcfg_addr;
183}
184
165/* 185/*
166 * _SxD returns the D-state with the highest power 186 * _SxD returns the D-state with the highest power
167 * (lowest D-state number) supported in the S-state "x". 187 * (lowest D-state number) supported in the S-state "x".
@@ -187,9 +207,13 @@ acpi_status pci_acpi_remove_pm_notifier(struct acpi_device *dev)
187 207
188static pci_power_t acpi_pci_choose_state(struct pci_dev *pdev) 208static pci_power_t acpi_pci_choose_state(struct pci_dev *pdev)
189{ 209{
190 int acpi_state; 210 int acpi_state, d_max;
191 211
192 acpi_state = acpi_pm_device_sleep_state(&pdev->dev, NULL); 212 if (pdev->no_d3cold)
213 d_max = ACPI_STATE_D3_HOT;
214 else
215 d_max = ACPI_STATE_D3_COLD;
216 acpi_state = acpi_pm_device_sleep_state(&pdev->dev, NULL, d_max);
193 if (acpi_state < 0) 217 if (acpi_state < 0)
194 return PCI_POWER_ERROR; 218 return PCI_POWER_ERROR;
195 219
@@ -296,7 +320,13 @@ static void acpi_pci_propagate_run_wake(struct pci_bus *bus, bool enable)
296 320
297static int acpi_pci_run_wake(struct pci_dev *dev, bool enable) 321static int acpi_pci_run_wake(struct pci_dev *dev, bool enable)
298{ 322{
299 if (dev->pme_interrupt) 323 /*
324 * Per PCI Express Base Specification Revision 2.0 section
325 * 5.3.3.2 Link Wakeup, platform support is needed for D3cold
326 * waking up to power on the main link even if there is PME
327 * support for D3cold
328 */
329 if (dev->pme_interrupt && !dev->runtime_d3cold)
300 return 0; 330 return 0;
301 331
302 if (!acpi_pm_device_run_wake(&dev->dev, enable)) 332 if (!acpi_pm_device_run_wake(&dev->dev, enable))
diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c
index bf0cee629b60..ca2e4c79a588 100644
--- a/drivers/pci/pci-driver.c
+++ b/drivers/pci/pci-driver.c
@@ -1019,10 +1019,13 @@ static int pci_pm_runtime_suspend(struct device *dev)
1019 if (!pm || !pm->runtime_suspend) 1019 if (!pm || !pm->runtime_suspend)
1020 return -ENOSYS; 1020 return -ENOSYS;
1021 1021
1022 pci_dev->no_d3cold = false;
1022 error = pm->runtime_suspend(dev); 1023 error = pm->runtime_suspend(dev);
1023 suspend_report_result(pm->runtime_suspend, error); 1024 suspend_report_result(pm->runtime_suspend, error);
1024 if (error) 1025 if (error)
1025 return error; 1026 return error;
1027 if (!pci_dev->d3cold_allowed)
1028 pci_dev->no_d3cold = true;
1026 1029
1027 pci_fixup_device(pci_fixup_suspend, pci_dev); 1030 pci_fixup_device(pci_fixup_suspend, pci_dev);
1028 1031
@@ -1044,6 +1047,7 @@ static int pci_pm_runtime_suspend(struct device *dev)
1044 1047
1045static int pci_pm_runtime_resume(struct device *dev) 1048static int pci_pm_runtime_resume(struct device *dev)
1046{ 1049{
1050 int rc;
1047 struct pci_dev *pci_dev = to_pci_dev(dev); 1051 struct pci_dev *pci_dev = to_pci_dev(dev);
1048 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; 1052 const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
1049 1053
@@ -1054,7 +1058,11 @@ static int pci_pm_runtime_resume(struct device *dev)
1054 __pci_enable_wake(pci_dev, PCI_D0, true, false); 1058 __pci_enable_wake(pci_dev, PCI_D0, true, false);
1055 pci_fixup_device(pci_fixup_resume, pci_dev); 1059 pci_fixup_device(pci_fixup_resume, pci_dev);
1056 1060
1057 return pm->runtime_resume(dev); 1061 rc = pm->runtime_resume(dev);
1062
1063 pci_dev->runtime_d3cold = false;
1064
1065 return rc;
1058} 1066}
1059 1067
1060static int pci_pm_runtime_idle(struct device *dev) 1068static int pci_pm_runtime_idle(struct device *dev)
diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c
index 86c63fe45d11..6869009c7393 100644
--- a/drivers/pci/pci-sysfs.c
+++ b/drivers/pci/pci-sysfs.c
@@ -28,6 +28,7 @@
28#include <linux/pci-aspm.h> 28#include <linux/pci-aspm.h>
29#include <linux/slab.h> 29#include <linux/slab.h>
30#include <linux/vgaarb.h> 30#include <linux/vgaarb.h>
31#include <linux/pm_runtime.h>
31#include "pci.h" 32#include "pci.h"
32 33
33static int sysfs_initialized; /* = 0 */ 34static int sysfs_initialized; /* = 0 */
@@ -378,6 +379,31 @@ dev_bus_rescan_store(struct device *dev, struct device_attribute *attr,
378 379
379#endif 380#endif
380 381
382#if defined(CONFIG_PM_RUNTIME) && defined(CONFIG_ACPI)
383static ssize_t d3cold_allowed_store(struct device *dev,
384 struct device_attribute *attr,
385 const char *buf, size_t count)
386{
387 struct pci_dev *pdev = to_pci_dev(dev);
388 unsigned long val;
389
390 if (strict_strtoul(buf, 0, &val) < 0)
391 return -EINVAL;
392
393 pdev->d3cold_allowed = !!val;
394 pm_runtime_resume(dev);
395
396 return count;
397}
398
399static ssize_t d3cold_allowed_show(struct device *dev,
400 struct device_attribute *attr, char *buf)
401{
402 struct pci_dev *pdev = to_pci_dev(dev);
403 return sprintf (buf, "%u\n", pdev->d3cold_allowed);
404}
405#endif
406
381struct device_attribute pci_dev_attrs[] = { 407struct device_attribute pci_dev_attrs[] = {
382 __ATTR_RO(resource), 408 __ATTR_RO(resource),
383 __ATTR_RO(vendor), 409 __ATTR_RO(vendor),
@@ -402,6 +428,9 @@ struct device_attribute pci_dev_attrs[] = {
402 __ATTR(remove, (S_IWUSR|S_IWGRP), NULL, remove_store), 428 __ATTR(remove, (S_IWUSR|S_IWGRP), NULL, remove_store),
403 __ATTR(rescan, (S_IWUSR|S_IWGRP), NULL, dev_rescan_store), 429 __ATTR(rescan, (S_IWUSR|S_IWGRP), NULL, dev_rescan_store),
404#endif 430#endif
431#if defined(CONFIG_PM_RUNTIME) && defined(CONFIG_ACPI)
432 __ATTR(d3cold_allowed, 0644, d3cold_allowed_show, d3cold_allowed_store),
433#endif
405 __ATTR_NULL, 434 __ATTR_NULL,
406}; 435};
407 436
@@ -1112,7 +1141,7 @@ static struct bin_attribute pcie_config_attr = {
1112 .write = pci_write_config, 1141 .write = pci_write_config,
1113}; 1142};
1114 1143
1115int __attribute__ ((weak)) pcibios_add_platform_entries(struct pci_dev *dev) 1144int __weak pcibios_add_platform_entries(struct pci_dev *dev)
1116{ 1145{
1117 return 0; 1146 return 0;
1118} 1147}
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index c87d518acace..e091b0afdc8a 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -110,7 +110,7 @@ unsigned char pci_bus_max_busnr(struct pci_bus* bus)
110 struct list_head *tmp; 110 struct list_head *tmp;
111 unsigned char max, n; 111 unsigned char max, n;
112 112
113 max = bus->subordinate; 113 max = bus->busn_res.end;
114 list_for_each(tmp, &bus->children) { 114 list_for_each(tmp, &bus->children) {
115 n = pci_bus_max_busnr(pci_bus_b(tmp)); 115 n = pci_bus_max_busnr(pci_bus_b(tmp));
116 if(n > max) 116 if(n > max)
@@ -136,30 +136,6 @@ void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
136EXPORT_SYMBOL_GPL(pci_ioremap_bar); 136EXPORT_SYMBOL_GPL(pci_ioremap_bar);
137#endif 137#endif
138 138
139#if 0
140/**
141 * pci_max_busnr - returns maximum PCI bus number
142 *
143 * Returns the highest PCI bus number present in the system global list of
144 * PCI buses.
145 */
146unsigned char __devinit
147pci_max_busnr(void)
148{
149 struct pci_bus *bus = NULL;
150 unsigned char max, n;
151
152 max = 0;
153 while ((bus = pci_find_next_bus(bus)) != NULL) {
154 n = pci_bus_max_busnr(bus);
155 if(n > max)
156 max = n;
157 }
158 return max;
159}
160
161#endif /* 0 */
162
163#define PCI_FIND_CAP_TTL 48 139#define PCI_FIND_CAP_TTL 48
164 140
165static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, 141static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
@@ -278,6 +254,38 @@ int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
278} 254}
279 255
280/** 256/**
257 * pci_pcie_cap2 - query for devices' PCI_CAP_ID_EXP v2 capability structure
258 * @dev: PCI device to check
259 *
260 * Like pci_pcie_cap() but also checks that the PCIe capability version is
261 * >= 2. Note that v1 capability structures could be sparse in that not
262 * all register fields were required. v2 requires the entire structure to
263 * be present size wise, while still allowing for non-implemented registers
264 * to exist but they must be hardwired to 0.
265 *
266 * Due to the differences in the versions of capability structures, one
267 * must be careful not to try and access non-existant registers that may
268 * exist in early versions - v1 - of Express devices.
269 *
270 * Returns the offset of the PCIe capability structure as long as the
271 * capability version is >= 2; otherwise 0 is returned.
272 */
273static int pci_pcie_cap2(struct pci_dev *dev)
274{
275 u16 flags;
276 int pos;
277
278 pos = pci_pcie_cap(dev);
279 if (pos) {
280 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
281 if ((flags & PCI_EXP_FLAGS_VERS) < 2)
282 pos = 0;
283 }
284
285 return pos;
286}
287
288/**
281 * pci_find_ext_capability - Find an extended capability 289 * pci_find_ext_capability - Find an extended capability
282 * @dev: PCI device to query 290 * @dev: PCI device to query
283 * @cap: capability code 291 * @cap: capability code
@@ -329,49 +337,6 @@ int pci_find_ext_capability(struct pci_dev *dev, int cap)
329} 337}
330EXPORT_SYMBOL_GPL(pci_find_ext_capability); 338EXPORT_SYMBOL_GPL(pci_find_ext_capability);
331 339
332/**
333 * pci_bus_find_ext_capability - find an extended capability
334 * @bus: the PCI bus to query
335 * @devfn: PCI device to query
336 * @cap: capability code
337 *
338 * Like pci_find_ext_capability() but works for pci devices that do not have a
339 * pci_dev structure set up yet.
340 *
341 * Returns the address of the requested capability structure within the
342 * device's PCI configuration space or 0 in case the device does not
343 * support it.
344 */
345int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
346 int cap)
347{
348 u32 header;
349 int ttl;
350 int pos = PCI_CFG_SPACE_SIZE;
351
352 /* minimum 8 bytes per capability */
353 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
354
355 if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
356 return 0;
357 if (header == 0xffffffff || header == 0)
358 return 0;
359
360 while (ttl-- > 0) {
361 if (PCI_EXT_CAP_ID(header) == cap)
362 return pos;
363
364 pos = PCI_EXT_CAP_NEXT(header);
365 if (pos < PCI_CFG_SPACE_SIZE)
366 break;
367
368 if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
369 break;
370 }
371
372 return 0;
373}
374
375static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) 340static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
376{ 341{
377 int rc, ttl = PCI_FIND_CAP_TTL; 342 int rc, ttl = PCI_FIND_CAP_TTL;
@@ -622,7 +587,8 @@ static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
622 dev_info(&dev->dev, "Refused to change power state, " 587 dev_info(&dev->dev, "Refused to change power state, "
623 "currently in D%d\n", dev->current_state); 588 "currently in D%d\n", dev->current_state);
624 589
625 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT 590 /*
591 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
626 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning 592 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
627 * from D3hot to D0 _may_ perform an internal reset, thereby 593 * from D3hot to D0 _may_ perform an internal reset, thereby
628 * going to "D0 Uninitialized" rather than "D0 Initialized". 594 * going to "D0 Uninitialized" rather than "D0 Initialized".
@@ -654,6 +620,16 @@ void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
654 if (dev->pm_cap) { 620 if (dev->pm_cap) {
655 u16 pmcsr; 621 u16 pmcsr;
656 622
623 /*
624 * Configuration space is not accessible for device in
625 * D3cold, so just keep or set D3cold for safety
626 */
627 if (dev->current_state == PCI_D3cold)
628 return;
629 if (state == PCI_D3cold) {
630 dev->current_state = PCI_D3cold;
631 return;
632 }
657 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 633 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
658 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); 634 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
659 } else { 635 } else {
@@ -694,8 +670,50 @@ static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
694 */ 670 */
695static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state) 671static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
696{ 672{
697 if (state == PCI_D0) 673 if (state == PCI_D0) {
698 pci_platform_power_transition(dev, PCI_D0); 674 pci_platform_power_transition(dev, PCI_D0);
675 /*
676 * Mandatory power management transition delays, see
677 * PCI Express Base Specification Revision 2.0 Section
678 * 6.6.1: Conventional Reset. Do not delay for
679 * devices powered on/off by corresponding bridge,
680 * because have already delayed for the bridge.
681 */
682 if (dev->runtime_d3cold) {
683 msleep(dev->d3cold_delay);
684 /*
685 * When powering on a bridge from D3cold, the
686 * whole hierarchy may be powered on into
687 * D0uninitialized state, resume them to give
688 * them a chance to suspend again
689 */
690 pci_wakeup_bus(dev->subordinate);
691 }
692 }
693}
694
695/**
696 * __pci_dev_set_current_state - Set current state of a PCI device
697 * @dev: Device to handle
698 * @data: pointer to state to be set
699 */
700static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
701{
702 pci_power_t state = *(pci_power_t *)data;
703
704 dev->current_state = state;
705 return 0;
706}
707
708/**
709 * __pci_bus_set_current_state - Walk given bus and set current state of devices
710 * @bus: Top bus of the subtree to walk.
711 * @state: state to be set
712 */
713static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
714{
715 if (bus)
716 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
699} 717}
700 718
701/** 719/**
@@ -707,8 +725,15 @@ static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
707 */ 725 */
708int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state) 726int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
709{ 727{
710 return state >= PCI_D0 ? 728 int ret;
711 pci_platform_power_transition(dev, state) : -EINVAL; 729
730 if (state < PCI_D0)
731 return -EINVAL;
732 ret = pci_platform_power_transition(dev, state);
733 /* Power off the bridge may power off the whole hierarchy */
734 if (!ret && state == PCI_D3cold)
735 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
736 return ret;
712} 737}
713EXPORT_SYMBOL_GPL(__pci_complete_power_transition); 738EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
714 739
@@ -732,8 +757,8 @@ int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
732 int error; 757 int error;
733 758
734 /* bound the state we're entering */ 759 /* bound the state we're entering */
735 if (state > PCI_D3hot) 760 if (state > PCI_D3cold)
736 state = PCI_D3hot; 761 state = PCI_D3cold;
737 else if (state < PCI_D0) 762 else if (state < PCI_D0)
738 state = PCI_D0; 763 state = PCI_D0;
739 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) 764 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
@@ -748,10 +773,15 @@ int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
748 773
749 /* This device is quirked not to be put into D3, so 774 /* This device is quirked not to be put into D3, so
750 don't put it in D3 */ 775 don't put it in D3 */
751 if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) 776 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
752 return 0; 777 return 0;
753 778
754 error = pci_raw_set_power_state(dev, state); 779 /*
780 * To put device in D3cold, we put device into D3hot in native
781 * way, then put device into D3cold with platform ops
782 */
783 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
784 PCI_D3hot : state);
755 785
756 if (!__pci_complete_power_transition(dev, state)) 786 if (!__pci_complete_power_transition(dev, state))
757 error = 0; 787 error = 0;
@@ -822,12 +852,6 @@ EXPORT_SYMBOL(pci_choose_state);
822 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \ 852 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
823 (type == PCI_EXP_TYPE_ROOT_PORT || \ 853 (type == PCI_EXP_TYPE_ROOT_PORT || \
824 type == PCI_EXP_TYPE_RC_EC)) 854 type == PCI_EXP_TYPE_RC_EC))
825#define pcie_cap_has_devctl2(type, flags) \
826 ((flags & PCI_EXP_FLAGS_VERS) > 1)
827#define pcie_cap_has_lnkctl2(type, flags) \
828 ((flags & PCI_EXP_FLAGS_VERS) > 1)
829#define pcie_cap_has_sltctl2(type, flags) \
830 ((flags & PCI_EXP_FLAGS_VERS) > 1)
831 855
832static struct pci_cap_saved_state *pci_find_saved_cap( 856static struct pci_cap_saved_state *pci_find_saved_cap(
833 struct pci_dev *pci_dev, char cap) 857 struct pci_dev *pci_dev, char cap)
@@ -870,13 +894,14 @@ static int pci_save_pcie_state(struct pci_dev *dev)
870 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]); 894 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
871 if (pcie_cap_has_rtctl(dev->pcie_type, flags)) 895 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
872 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]); 896 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
873 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
874 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
875 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
876 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
877 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
878 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
879 897
898 pos = pci_pcie_cap2(dev);
899 if (!pos)
900 return 0;
901
902 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
903 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
904 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
880 return 0; 905 return 0;
881} 906}
882 907
@@ -903,12 +928,14 @@ static void pci_restore_pcie_state(struct pci_dev *dev)
903 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]); 928 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
904 if (pcie_cap_has_rtctl(dev->pcie_type, flags)) 929 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
905 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]); 930 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
906 if (pcie_cap_has_devctl2(dev->pcie_type, flags)) 931
907 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]); 932 pos = pci_pcie_cap2(dev);
908 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags)) 933 if (!pos)
909 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]); 934 return;
910 if (pcie_cap_has_sltctl2(dev->pcie_type, flags)) 935
911 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]); 936 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
937 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
938 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
912} 939}
913 940
914 941
@@ -1349,7 +1376,7 @@ void pcim_pin_device(struct pci_dev *pdev)
1349 * is the default implementation. Architecture implementations can 1376 * is the default implementation. Architecture implementations can
1350 * override this. 1377 * override this.
1351 */ 1378 */
1352void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {} 1379void __weak pcibios_disable_device (struct pci_dev *dev) {}
1353 1380
1354static void do_pci_disable_device(struct pci_dev *dev) 1381static void do_pci_disable_device(struct pci_dev *dev)
1355{ 1382{
@@ -1413,8 +1440,8 @@ pci_disable_device(struct pci_dev *dev)
1413 * Sets the PCIe reset state for the device. This is the default 1440 * Sets the PCIe reset state for the device. This is the default
1414 * implementation. Architecture implementations can override this. 1441 * implementation. Architecture implementations can override this.
1415 */ 1442 */
1416int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev, 1443int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1417 enum pcie_reset_state state) 1444 enum pcie_reset_state state)
1418{ 1445{
1419 return -EINVAL; 1446 return -EINVAL;
1420} 1447}
@@ -1498,6 +1525,28 @@ void pci_pme_wakeup_bus(struct pci_bus *bus)
1498} 1525}
1499 1526
1500/** 1527/**
1528 * pci_wakeup - Wake up a PCI device
1529 * @dev: Device to handle.
1530 * @ign: ignored parameter
1531 */
1532static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
1533{
1534 pci_wakeup_event(pci_dev);
1535 pm_request_resume(&pci_dev->dev);
1536 return 0;
1537}
1538
1539/**
1540 * pci_wakeup_bus - Walk given bus and wake up devices on it
1541 * @bus: Top bus of the subtree to walk.
1542 */
1543void pci_wakeup_bus(struct pci_bus *bus)
1544{
1545 if (bus)
1546 pci_walk_bus(bus, pci_wakeup, NULL);
1547}
1548
1549/**
1501 * pci_pme_capable - check the capability of PCI device to generate PME# 1550 * pci_pme_capable - check the capability of PCI device to generate PME#
1502 * @dev: PCI device to handle. 1551 * @dev: PCI device to handle.
1503 * @state: PCI state from which device will issue PME#. 1552 * @state: PCI state from which device will issue PME#.
@@ -1518,6 +1567,16 @@ static void pci_pme_list_scan(struct work_struct *work)
1518 if (!list_empty(&pci_pme_list)) { 1567 if (!list_empty(&pci_pme_list)) {
1519 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) { 1568 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1520 if (pme_dev->dev->pme_poll) { 1569 if (pme_dev->dev->pme_poll) {
1570 struct pci_dev *bridge;
1571
1572 bridge = pme_dev->dev->bus->self;
1573 /*
1574 * If bridge is in low power state, the
1575 * configuration space of subordinate devices
1576 * may be not accessible
1577 */
1578 if (bridge && bridge->current_state != PCI_D0)
1579 continue;
1521 pci_pme_wakeup(pme_dev->dev, NULL); 1580 pci_pme_wakeup(pme_dev->dev, NULL);
1522 } else { 1581 } else {
1523 list_del(&pme_dev->list); 1582 list_del(&pme_dev->list);
@@ -1744,6 +1803,10 @@ int pci_prepare_to_sleep(struct pci_dev *dev)
1744 if (target_state == PCI_POWER_ERROR) 1803 if (target_state == PCI_POWER_ERROR)
1745 return -EIO; 1804 return -EIO;
1746 1805
1806 /* D3cold during system suspend/hibernate is not supported */
1807 if (target_state > PCI_D3hot)
1808 target_state = PCI_D3hot;
1809
1747 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev)); 1810 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1748 1811
1749 error = pci_set_power_state(dev, target_state); 1812 error = pci_set_power_state(dev, target_state);
@@ -1781,12 +1844,16 @@ int pci_finish_runtime_suspend(struct pci_dev *dev)
1781 if (target_state == PCI_POWER_ERROR) 1844 if (target_state == PCI_POWER_ERROR)
1782 return -EIO; 1845 return -EIO;
1783 1846
1847 dev->runtime_d3cold = target_state == PCI_D3cold;
1848
1784 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev)); 1849 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1785 1850
1786 error = pci_set_power_state(dev, target_state); 1851 error = pci_set_power_state(dev, target_state);
1787 1852
1788 if (error) 1853 if (error) {
1789 __pci_enable_wake(dev, target_state, true, false); 1854 __pci_enable_wake(dev, target_state, true, false);
1855 dev->runtime_d3cold = false;
1856 }
1790 1857
1791 return error; 1858 return error;
1792} 1859}
@@ -1856,6 +1923,7 @@ void pci_pm_init(struct pci_dev *dev)
1856 1923
1857 dev->pm_cap = pm; 1924 dev->pm_cap = pm;
1858 dev->d3_delay = PCI_PM_D3_WAIT; 1925 dev->d3_delay = PCI_PM_D3_WAIT;
1926 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
1859 1927
1860 dev->d1_support = false; 1928 dev->d1_support = false;
1861 dev->d2_support = false; 1929 dev->d2_support = false;
@@ -1983,7 +2051,7 @@ void pci_enable_ari(struct pci_dev *dev)
1983{ 2051{
1984 int pos; 2052 int pos;
1985 u32 cap; 2053 u32 cap;
1986 u16 flags, ctrl; 2054 u16 ctrl;
1987 struct pci_dev *bridge; 2055 struct pci_dev *bridge;
1988 2056
1989 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn) 2057 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
@@ -1994,18 +2062,14 @@ void pci_enable_ari(struct pci_dev *dev)
1994 return; 2062 return;
1995 2063
1996 bridge = dev->bus->self; 2064 bridge = dev->bus->self;
1997 if (!bridge || !pci_is_pcie(bridge)) 2065 if (!bridge)
1998 return; 2066 return;
1999 2067
2000 pos = pci_pcie_cap(bridge); 2068 /* ARI is a PCIe cap v2 feature */
2069 pos = pci_pcie_cap2(bridge);
2001 if (!pos) 2070 if (!pos)
2002 return; 2071 return;
2003 2072
2004 /* ARI is a PCIe v2 feature */
2005 pci_read_config_word(bridge, pos + PCI_EXP_FLAGS, &flags);
2006 if ((flags & PCI_EXP_FLAGS_VERS) < 2)
2007 return;
2008
2009 pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap); 2073 pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
2010 if (!(cap & PCI_EXP_DEVCAP2_ARI)) 2074 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2011 return; 2075 return;
@@ -2018,7 +2082,7 @@ void pci_enable_ari(struct pci_dev *dev)
2018} 2082}
2019 2083
2020/** 2084/**
2021 * pci_enable_ido - enable ID-based ordering on a device 2085 * pci_enable_ido - enable ID-based Ordering on a device
2022 * @dev: the PCI device 2086 * @dev: the PCI device
2023 * @type: which types of IDO to enable 2087 * @type: which types of IDO to enable
2024 * 2088 *
@@ -2031,7 +2095,8 @@ void pci_enable_ido(struct pci_dev *dev, unsigned long type)
2031 int pos; 2095 int pos;
2032 u16 ctrl; 2096 u16 ctrl;
2033 2097
2034 pos = pci_pcie_cap(dev); 2098 /* ID-based Ordering is a PCIe cap v2 feature */
2099 pos = pci_pcie_cap2(dev);
2035 if (!pos) 2100 if (!pos)
2036 return; 2101 return;
2037 2102
@@ -2054,10 +2119,8 @@ void pci_disable_ido(struct pci_dev *dev, unsigned long type)
2054 int pos; 2119 int pos;
2055 u16 ctrl; 2120 u16 ctrl;
2056 2121
2057 if (!pci_is_pcie(dev)) 2122 /* ID-based Ordering is a PCIe cap v2 feature */
2058 return; 2123 pos = pci_pcie_cap2(dev);
2059
2060 pos = pci_pcie_cap(dev);
2061 if (!pos) 2124 if (!pos)
2062 return; 2125 return;
2063 2126
@@ -2096,10 +2159,8 @@ int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
2096 u16 ctrl; 2159 u16 ctrl;
2097 int ret; 2160 int ret;
2098 2161
2099 if (!pci_is_pcie(dev)) 2162 /* OBFF is a PCIe cap v2 feature */
2100 return -ENOTSUPP; 2163 pos = pci_pcie_cap2(dev);
2101
2102 pos = pci_pcie_cap(dev);
2103 if (!pos) 2164 if (!pos)
2104 return -ENOTSUPP; 2165 return -ENOTSUPP;
2105 2166
@@ -2108,7 +2169,7 @@ int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
2108 return -ENOTSUPP; /* no OBFF support at all */ 2169 return -ENOTSUPP; /* no OBFF support at all */
2109 2170
2110 /* Make sure the topology supports OBFF as well */ 2171 /* Make sure the topology supports OBFF as well */
2111 if (dev->bus) { 2172 if (dev->bus->self) {
2112 ret = pci_enable_obff(dev->bus->self, type); 2173 ret = pci_enable_obff(dev->bus->self, type);
2113 if (ret) 2174 if (ret)
2114 return ret; 2175 return ret;
@@ -2149,10 +2210,8 @@ void pci_disable_obff(struct pci_dev *dev)
2149 int pos; 2210 int pos;
2150 u16 ctrl; 2211 u16 ctrl;
2151 2212
2152 if (!pci_is_pcie(dev)) 2213 /* OBFF is a PCIe cap v2 feature */
2153 return; 2214 pos = pci_pcie_cap2(dev);
2154
2155 pos = pci_pcie_cap(dev);
2156 if (!pos) 2215 if (!pos)
2157 return; 2216 return;
2158 2217
@@ -2169,15 +2228,13 @@ EXPORT_SYMBOL(pci_disable_obff);
2169 * RETURNS: 2228 * RETURNS:
2170 * True if @dev supports latency tolerance reporting, false otherwise. 2229 * True if @dev supports latency tolerance reporting, false otherwise.
2171 */ 2230 */
2172bool pci_ltr_supported(struct pci_dev *dev) 2231static bool pci_ltr_supported(struct pci_dev *dev)
2173{ 2232{
2174 int pos; 2233 int pos;
2175 u32 cap; 2234 u32 cap;
2176 2235
2177 if (!pci_is_pcie(dev)) 2236 /* LTR is a PCIe cap v2 feature */
2178 return false; 2237 pos = pci_pcie_cap2(dev);
2179
2180 pos = pci_pcie_cap(dev);
2181 if (!pos) 2238 if (!pos)
2182 return false; 2239 return false;
2183 2240
@@ -2185,7 +2242,6 @@ bool pci_ltr_supported(struct pci_dev *dev)
2185 2242
2186 return cap & PCI_EXP_DEVCAP2_LTR; 2243 return cap & PCI_EXP_DEVCAP2_LTR;
2187} 2244}
2188EXPORT_SYMBOL(pci_ltr_supported);
2189 2245
2190/** 2246/**
2191 * pci_enable_ltr - enable latency tolerance reporting 2247 * pci_enable_ltr - enable latency tolerance reporting
@@ -2206,7 +2262,8 @@ int pci_enable_ltr(struct pci_dev *dev)
2206 if (!pci_ltr_supported(dev)) 2262 if (!pci_ltr_supported(dev))
2207 return -ENOTSUPP; 2263 return -ENOTSUPP;
2208 2264
2209 pos = pci_pcie_cap(dev); 2265 /* LTR is a PCIe cap v2 feature */
2266 pos = pci_pcie_cap2(dev);
2210 if (!pos) 2267 if (!pos)
2211 return -ENOTSUPP; 2268 return -ENOTSUPP;
2212 2269
@@ -2215,7 +2272,7 @@ int pci_enable_ltr(struct pci_dev *dev)
2215 return -EINVAL; 2272 return -EINVAL;
2216 2273
2217 /* Enable upstream ports first */ 2274 /* Enable upstream ports first */
2218 if (dev->bus) { 2275 if (dev->bus->self) {
2219 ret = pci_enable_ltr(dev->bus->self); 2276 ret = pci_enable_ltr(dev->bus->self);
2220 if (ret) 2277 if (ret)
2221 return ret; 2278 return ret;
@@ -2241,7 +2298,8 @@ void pci_disable_ltr(struct pci_dev *dev)
2241 if (!pci_ltr_supported(dev)) 2298 if (!pci_ltr_supported(dev))
2242 return; 2299 return;
2243 2300
2244 pos = pci_pcie_cap(dev); 2301 /* LTR is a PCIe cap v2 feature */
2302 pos = pci_pcie_cap2(dev);
2245 if (!pos) 2303 if (!pos)
2246 return; 2304 return;
2247 2305
@@ -2360,6 +2418,75 @@ void pci_enable_acs(struct pci_dev *dev)
2360} 2418}
2361 2419
2362/** 2420/**
2421 * pci_acs_enabled - test ACS against required flags for a given device
2422 * @pdev: device to test
2423 * @acs_flags: required PCI ACS flags
2424 *
2425 * Return true if the device supports the provided flags. Automatically
2426 * filters out flags that are not implemented on multifunction devices.
2427 */
2428bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2429{
2430 int pos, ret;
2431 u16 ctrl;
2432
2433 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
2434 if (ret >= 0)
2435 return ret > 0;
2436
2437 if (!pci_is_pcie(pdev))
2438 return false;
2439
2440 /* Filter out flags not applicable to multifunction */
2441 if (pdev->multifunction)
2442 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR |
2443 PCI_ACS_EC | PCI_ACS_DT);
2444
2445 if (pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM ||
2446 pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
2447 pdev->multifunction) {
2448 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
2449 if (!pos)
2450 return false;
2451
2452 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
2453 if ((ctrl & acs_flags) != acs_flags)
2454 return false;
2455 }
2456
2457 return true;
2458}
2459
2460/**
2461 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
2462 * @start: starting downstream device
2463 * @end: ending upstream device or NULL to search to the root bus
2464 * @acs_flags: required flags
2465 *
2466 * Walk up a device tree from start to end testing PCI ACS support. If
2467 * any step along the way does not support the required flags, return false.
2468 */
2469bool pci_acs_path_enabled(struct pci_dev *start,
2470 struct pci_dev *end, u16 acs_flags)
2471{
2472 struct pci_dev *pdev, *parent = start;
2473
2474 do {
2475 pdev = parent;
2476
2477 if (!pci_acs_enabled(pdev, acs_flags))
2478 return false;
2479
2480 if (pci_is_root_bus(pdev->bus))
2481 return (end == NULL);
2482
2483 parent = pdev->bus->self;
2484 } while (pdev != end);
2485
2486 return true;
2487}
2488
2489/**
2363 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge 2490 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2364 * @dev: the PCI device 2491 * @dev: the PCI device
2365 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD) 2492 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
@@ -2888,6 +3015,9 @@ bool pci_intx_mask_supported(struct pci_dev *dev)
2888 bool mask_supported = false; 3015 bool mask_supported = false;
2889 u16 orig, new; 3016 u16 orig, new;
2890 3017
3018 if (dev->broken_intx_masking)
3019 return false;
3020
2891 pci_cfg_access_lock(dev); 3021 pci_cfg_access_lock(dev);
2892 3022
2893 pci_read_config_word(dev, PCI_COMMAND, &orig); 3023 pci_read_config_word(dev, PCI_COMMAND, &orig);
@@ -3407,8 +3537,7 @@ int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
3407 3537
3408 o = (cmd & PCI_X_CMD_MAX_READ) >> 2; 3538 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
3409 if (o != v) { 3539 if (o != v) {
3410 if (v > o && dev->bus && 3540 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
3411 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
3412 return -EIO; 3541 return -EIO;
3413 3542
3414 cmd &= ~PCI_X_CMD_MAX_READ; 3543 cmd &= ~PCI_X_CMD_MAX_READ;
@@ -3863,7 +3992,7 @@ static void __devinit pci_no_domains(void)
3863 * greater than 0xff). This is the default implementation. Architecture 3992 * greater than 0xff). This is the default implementation. Architecture
3864 * implementations can override this. 3993 * implementations can override this.
3865 */ 3994 */
3866int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev) 3995int __weak pci_ext_cfg_avail(struct pci_dev *dev)
3867{ 3996{
3868 return 1; 3997 return 1;
3869} 3998}
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index e4943479b234..ec1512de4297 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -70,6 +70,7 @@ extern void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
70extern void pci_disable_enabled_device(struct pci_dev *dev); 70extern void pci_disable_enabled_device(struct pci_dev *dev);
71extern int pci_finish_runtime_suspend(struct pci_dev *dev); 71extern int pci_finish_runtime_suspend(struct pci_dev *dev);
72extern int __pci_pme_wakeup(struct pci_dev *dev, void *ign); 72extern int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
73extern void pci_wakeup_bus(struct pci_bus *bus);
73extern void pci_pm_init(struct pci_dev *dev); 74extern void pci_pm_init(struct pci_dev *dev);
74extern void platform_pci_wakeup_init(struct pci_dev *dev); 75extern void platform_pci_wakeup_init(struct pci_dev *dev);
75extern void pci_allocate_cap_save_buffers(struct pci_dev *dev); 76extern void pci_allocate_cap_save_buffers(struct pci_dev *dev);
@@ -86,13 +87,6 @@ static inline bool pci_is_bridge(struct pci_dev *pci_dev)
86 return !!(pci_dev->subordinate); 87 return !!(pci_dev->subordinate);
87} 88}
88 89
89extern int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
90extern int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
91extern int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
92extern int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
93extern int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
94extern int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
95
96struct pci_vpd_ops { 90struct pci_vpd_ops {
97 ssize_t (*read)(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 91 ssize_t (*read)(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
98 ssize_t (*write)(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 92 ssize_t (*write)(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
@@ -124,7 +118,7 @@ static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
124#endif 118#endif
125 119
126/* Functions for PCI Hotplug drivers to use */ 120/* Functions for PCI Hotplug drivers to use */
127extern unsigned int pci_do_scan_bus(struct pci_bus *bus); 121int pci_hp_add_bridge(struct pci_dev *dev);
128 122
129#ifdef HAVE_PCI_LEGACY 123#ifdef HAVE_PCI_LEGACY
130extern void pci_create_legacy_files(struct pci_bus *bus); 124extern void pci_create_legacy_files(struct pci_bus *bus);
diff --git a/drivers/pci/pcie/aer/aerdrv_acpi.c b/drivers/pci/pcie/aer/aerdrv_acpi.c
index 275bf158ffa7..124f20ff11b2 100644
--- a/drivers/pci/pcie/aer/aerdrv_acpi.c
+++ b/drivers/pci/pcie/aer/aerdrv_acpi.c
@@ -59,7 +59,7 @@ static int aer_hest_parse(struct acpi_hest_header *hest_hdr, void *data)
59 59
60 p = (struct acpi_hest_aer_common *)(hest_hdr + 1); 60 p = (struct acpi_hest_aer_common *)(hest_hdr + 1);
61 if (p->flags & ACPI_HEST_GLOBAL) { 61 if (p->flags & ACPI_HEST_GLOBAL) {
62 if ((info->pci_dev->is_pcie && 62 if ((pci_is_pcie(info->pci_dev) &&
63 info->pci_dev->pcie_type == pcie_type) || bridge) 63 info->pci_dev->pcie_type == pcie_type) || bridge)
64 ff = !!(p->flags & ACPI_HEST_FIRMWARE_FIRST); 64 ff = !!(p->flags & ACPI_HEST_FIRMWARE_FIRST);
65 } else 65 } else
diff --git a/drivers/pci/pcie/portdrv_pci.c b/drivers/pci/pcie/portdrv_pci.c
index e0610bda1dea..3a7eefcb270a 100644
--- a/drivers/pci/pcie/portdrv_pci.c
+++ b/drivers/pci/pcie/portdrv_pci.c
@@ -11,6 +11,7 @@
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/errno.h> 12#include <linux/errno.h>
13#include <linux/pm.h> 13#include <linux/pm.h>
14#include <linux/pm_runtime.h>
14#include <linux/init.h> 15#include <linux/init.h>
15#include <linux/pcieport_if.h> 16#include <linux/pcieport_if.h>
16#include <linux/aer.h> 17#include <linux/aer.h>
@@ -99,6 +100,51 @@ static int pcie_port_resume_noirq(struct device *dev)
99 return 0; 100 return 0;
100} 101}
101 102
103#ifdef CONFIG_PM_RUNTIME
104struct d3cold_info {
105 bool no_d3cold;
106 unsigned int d3cold_delay;
107};
108
109static int pci_dev_d3cold_info(struct pci_dev *pdev, void *data)
110{
111 struct d3cold_info *info = data;
112
113 info->d3cold_delay = max_t(unsigned int, pdev->d3cold_delay,
114 info->d3cold_delay);
115 if (pdev->no_d3cold)
116 info->no_d3cold = true;
117 return 0;
118}
119
120static int pcie_port_runtime_suspend(struct device *dev)
121{
122 struct pci_dev *pdev = to_pci_dev(dev);
123 struct d3cold_info d3cold_info = {
124 .no_d3cold = false,
125 .d3cold_delay = PCI_PM_D3_WAIT,
126 };
127
128 /*
129 * If any subordinate device disable D3cold, we should not put
130 * the port into D3cold. The D3cold delay of port should be
131 * the max of that of all subordinate devices.
132 */
133 pci_walk_bus(pdev->subordinate, pci_dev_d3cold_info, &d3cold_info);
134 pdev->no_d3cold = d3cold_info.no_d3cold;
135 pdev->d3cold_delay = d3cold_info.d3cold_delay;
136 return 0;
137}
138
139static int pcie_port_runtime_resume(struct device *dev)
140{
141 return 0;
142}
143#else
144#define pcie_port_runtime_suspend NULL
145#define pcie_port_runtime_resume NULL
146#endif
147
102static const struct dev_pm_ops pcie_portdrv_pm_ops = { 148static const struct dev_pm_ops pcie_portdrv_pm_ops = {
103 .suspend = pcie_port_device_suspend, 149 .suspend = pcie_port_device_suspend,
104 .resume = pcie_port_device_resume, 150 .resume = pcie_port_device_resume,
@@ -107,6 +153,8 @@ static const struct dev_pm_ops pcie_portdrv_pm_ops = {
107 .poweroff = pcie_port_device_suspend, 153 .poweroff = pcie_port_device_suspend,
108 .restore = pcie_port_device_resume, 154 .restore = pcie_port_device_resume,
109 .resume_noirq = pcie_port_resume_noirq, 155 .resume_noirq = pcie_port_resume_noirq,
156 .runtime_suspend = pcie_port_runtime_suspend,
157 .runtime_resume = pcie_port_runtime_resume,
110}; 158};
111 159
112#define PCIE_PORTDRV_PM_OPS (&pcie_portdrv_pm_ops) 160#define PCIE_PORTDRV_PM_OPS (&pcie_portdrv_pm_ops)
@@ -117,6 +165,14 @@ static const struct dev_pm_ops pcie_portdrv_pm_ops = {
117#endif /* !PM */ 165#endif /* !PM */
118 166
119/* 167/*
168 * PCIe port runtime suspend is broken for some chipsets, so use a
169 * black list to disable runtime PM for these chipsets.
170 */
171static const struct pci_device_id port_runtime_pm_black_list[] = {
172 { /* end: all zeroes */ }
173};
174
175/*
120 * pcie_portdrv_probe - Probe PCI-Express port devices 176 * pcie_portdrv_probe - Probe PCI-Express port devices
121 * @dev: PCI-Express port device being probed 177 * @dev: PCI-Express port device being probed
122 * 178 *
@@ -144,12 +200,16 @@ static int __devinit pcie_portdrv_probe(struct pci_dev *dev,
144 return status; 200 return status;
145 201
146 pci_save_state(dev); 202 pci_save_state(dev);
203 if (!pci_match_id(port_runtime_pm_black_list, dev))
204 pm_runtime_put_noidle(&dev->dev);
147 205
148 return 0; 206 return 0;
149} 207}
150 208
151static void pcie_portdrv_remove(struct pci_dev *dev) 209static void pcie_portdrv_remove(struct pci_dev *dev)
152{ 210{
211 if (!pci_match_id(port_runtime_pm_black_list, dev))
212 pm_runtime_get_noresume(&dev->dev);
153 pcie_port_device_remove(dev); 213 pcie_port_device_remove(dev);
154 pci_disable_device(dev); 214 pci_disable_device(dev);
155} 215}
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 658ac977cb56..cd06c8478267 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -16,10 +16,47 @@
16#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ 16#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
17#define CARDBUS_RESERVE_BUSNR 3 17#define CARDBUS_RESERVE_BUSNR 3
18 18
19struct resource busn_resource = {
20 .name = "PCI busn",
21 .start = 0,
22 .end = 255,
23 .flags = IORESOURCE_BUS,
24};
25
19/* Ugh. Need to stop exporting this to modules. */ 26/* Ugh. Need to stop exporting this to modules. */
20LIST_HEAD(pci_root_buses); 27LIST_HEAD(pci_root_buses);
21EXPORT_SYMBOL(pci_root_buses); 28EXPORT_SYMBOL(pci_root_buses);
22 29
30static LIST_HEAD(pci_domain_busn_res_list);
31
32struct pci_domain_busn_res {
33 struct list_head list;
34 struct resource res;
35 int domain_nr;
36};
37
38static struct resource *get_pci_domain_busn_res(int domain_nr)
39{
40 struct pci_domain_busn_res *r;
41
42 list_for_each_entry(r, &pci_domain_busn_res_list, list)
43 if (r->domain_nr == domain_nr)
44 return &r->res;
45
46 r = kzalloc(sizeof(*r), GFP_KERNEL);
47 if (!r)
48 return NULL;
49
50 r->domain_nr = domain_nr;
51 r->res.start = 0;
52 r->res.end = 0xff;
53 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
54
55 list_add_tail(&r->list, &pci_domain_busn_res_list);
56
57 return &r->res;
58}
59
23static int find_anything(struct device *dev, void *data) 60static int find_anything(struct device *dev, void *data)
24{ 61{
25 return 1; 62 return 1;
@@ -281,10 +318,11 @@ static void __devinit pci_read_bridge_io(struct pci_bus *child)
281 318
282 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { 319 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
283 u16 io_base_hi, io_limit_hi; 320 u16 io_base_hi, io_limit_hi;
321
284 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); 322 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
285 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); 323 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
286 base |= (io_base_hi << 16); 324 base |= ((unsigned long) io_base_hi << 16);
287 limit |= (io_limit_hi << 16); 325 limit |= ((unsigned long) io_limit_hi << 16);
288 } 326 }
289 327
290 if (base && base <= limit) { 328 if (base && base <= limit) {
@@ -312,8 +350,8 @@ static void __devinit pci_read_bridge_mmio(struct pci_bus *child)
312 res = child->resource[1]; 350 res = child->resource[1];
313 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); 351 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
314 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); 352 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
315 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; 353 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
316 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; 354 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
317 if (base && base <= limit) { 355 if (base && base <= limit) {
318 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; 356 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
319 region.start = base; 357 region.start = base;
@@ -334,11 +372,12 @@ static void __devinit pci_read_bridge_mmio_pref(struct pci_bus *child)
334 res = child->resource[2]; 372 res = child->resource[2];
335 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); 373 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
336 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); 374 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
337 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; 375 base = ((unsigned long) mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
338 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; 376 limit = ((unsigned long) mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
339 377
340 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 378 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
341 u32 mem_base_hi, mem_limit_hi; 379 u32 mem_base_hi, mem_limit_hi;
380
342 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); 381 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
343 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); 382 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
344 383
@@ -349,8 +388,8 @@ static void __devinit pci_read_bridge_mmio_pref(struct pci_bus *child)
349 */ 388 */
350 if (mem_base_hi <= mem_limit_hi) { 389 if (mem_base_hi <= mem_limit_hi) {
351#if BITS_PER_LONG == 64 390#if BITS_PER_LONG == 64
352 base |= ((long) mem_base_hi) << 32; 391 base |= ((unsigned long) mem_base_hi) << 32;
353 limit |= ((long) mem_limit_hi) << 32; 392 limit |= ((unsigned long) mem_limit_hi) << 32;
354#else 393#else
355 if (mem_base_hi || mem_limit_hi) { 394 if (mem_base_hi || mem_limit_hi) {
356 dev_err(&dev->dev, "can't handle 64-bit " 395 dev_err(&dev->dev, "can't handle 64-bit "
@@ -381,8 +420,8 @@ void __devinit pci_read_bridge_bases(struct pci_bus *child)
381 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */ 420 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
382 return; 421 return;
383 422
384 dev_info(&dev->dev, "PCI bridge to [bus %02x-%02x]%s\n", 423 dev_info(&dev->dev, "PCI bridge to %pR%s\n",
385 child->secondary, child->subordinate, 424 &child->busn_res,
386 dev->transparent ? " (subtractive decode)" : ""); 425 dev->transparent ? " (subtractive decode)" : "");
387 426
388 pci_bus_remove_resources(child); 427 pci_bus_remove_resources(child);
@@ -599,9 +638,9 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
599 * Set up the primary, secondary and subordinate 638 * Set up the primary, secondary and subordinate
600 * bus numbers. 639 * bus numbers.
601 */ 640 */
602 child->number = child->secondary = busnr; 641 child->number = child->busn_res.start = busnr;
603 child->primary = parent->secondary; 642 child->primary = parent->busn_res.start;
604 child->subordinate = 0xff; 643 child->busn_res.end = 0xff;
605 644
606 if (!bridge) 645 if (!bridge)
607 return child; 646 return child;
@@ -643,8 +682,8 @@ static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
643 if (!pcibios_assign_all_busses()) 682 if (!pcibios_assign_all_busses())
644 return; 683 return;
645 684
646 while (parent->parent && parent->subordinate < max) { 685 while (parent->parent && parent->busn_res.end < max) {
647 parent->subordinate = max; 686 parent->busn_res.end = max;
648 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max); 687 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
649 parent = parent->parent; 688 parent = parent->parent;
650 } 689 }
@@ -718,15 +757,15 @@ int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
718 if (!child) 757 if (!child)
719 goto out; 758 goto out;
720 child->primary = primary; 759 child->primary = primary;
721 child->subordinate = subordinate; 760 pci_bus_insert_busn_res(child, secondary, subordinate);
722 child->bridge_ctl = bctl; 761 child->bridge_ctl = bctl;
723 } 762 }
724 763
725 cmax = pci_scan_child_bus(child); 764 cmax = pci_scan_child_bus(child);
726 if (cmax > max) 765 if (cmax > max)
727 max = cmax; 766 max = cmax;
728 if (child->subordinate > max) 767 if (child->busn_res.end > max)
729 max = child->subordinate; 768 max = child->busn_res.end;
730 } else { 769 } else {
731 /* 770 /*
732 * We need to assign a number to this bus which we always 771 * We need to assign a number to this bus which we always
@@ -756,11 +795,12 @@ int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
756 child = pci_add_new_bus(bus, dev, ++max); 795 child = pci_add_new_bus(bus, dev, ++max);
757 if (!child) 796 if (!child)
758 goto out; 797 goto out;
798 pci_bus_insert_busn_res(child, max, 0xff);
759 } 799 }
760 buses = (buses & 0xff000000) 800 buses = (buses & 0xff000000)
761 | ((unsigned int)(child->primary) << 0) 801 | ((unsigned int)(child->primary) << 0)
762 | ((unsigned int)(child->secondary) << 8) 802 | ((unsigned int)(child->busn_res.start) << 8)
763 | ((unsigned int)(child->subordinate) << 16); 803 | ((unsigned int)(child->busn_res.end) << 16);
764 804
765 /* 805 /*
766 * yenta.c forces a secondary latency timer of 176. 806 * yenta.c forces a secondary latency timer of 176.
@@ -805,8 +845,8 @@ int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
805 break; 845 break;
806 while (parent->parent) { 846 while (parent->parent) {
807 if ((!pcibios_assign_all_busses()) && 847 if ((!pcibios_assign_all_busses()) &&
808 (parent->subordinate > max) && 848 (parent->busn_res.end > max) &&
809 (parent->subordinate <= max+i)) { 849 (parent->busn_res.end <= max+i)) {
810 j = 1; 850 j = 1;
811 } 851 }
812 parent = parent->parent; 852 parent = parent->parent;
@@ -827,7 +867,7 @@ int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
827 /* 867 /*
828 * Set the subordinate bus number to its real value. 868 * Set the subordinate bus number to its real value.
829 */ 869 */
830 child->subordinate = max; 870 pci_bus_update_busn_res_end(child, max);
831 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); 871 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
832 } 872 }
833 873
@@ -837,19 +877,19 @@ int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
837 877
838 /* Has only triggered on CardBus, fixup is in yenta_socket */ 878 /* Has only triggered on CardBus, fixup is in yenta_socket */
839 while (bus->parent) { 879 while (bus->parent) {
840 if ((child->subordinate > bus->subordinate) || 880 if ((child->busn_res.end > bus->busn_res.end) ||
841 (child->number > bus->subordinate) || 881 (child->number > bus->busn_res.end) ||
842 (child->number < bus->number) || 882 (child->number < bus->number) ||
843 (child->subordinate < bus->number)) { 883 (child->busn_res.end < bus->number)) {
844 dev_info(&child->dev, "[bus %02x-%02x] %s " 884 dev_info(&child->dev, "%pR %s "
845 "hidden behind%s bridge %s [bus %02x-%02x]\n", 885 "hidden behind%s bridge %s %pR\n",
846 child->number, child->subordinate, 886 &child->busn_res,
847 (bus->number > child->subordinate && 887 (bus->number > child->busn_res.end &&
848 bus->subordinate < child->number) ? 888 bus->busn_res.end < child->number) ?
849 "wholly" : "partially", 889 "wholly" : "partially",
850 bus->self->transparent ? " transparent" : "", 890 bus->self->transparent ? " transparent" : "",
851 dev_name(&bus->dev), 891 dev_name(&bus->dev),
852 bus->number, bus->subordinate); 892 &bus->busn_res);
853 } 893 }
854 bus = bus->parent; 894 bus = bus->parent;
855 } 895 }
@@ -1548,7 +1588,7 @@ EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
1548 1588
1549unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus) 1589unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
1550{ 1590{
1551 unsigned int devfn, pass, max = bus->secondary; 1591 unsigned int devfn, pass, max = bus->busn_res.start;
1552 struct pci_dev *dev; 1592 struct pci_dev *dev;
1553 1593
1554 dev_dbg(&bus->dev, "scanning bus\n"); 1594 dev_dbg(&bus->dev, "scanning bus\n");
@@ -1642,7 +1682,7 @@ struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1642 /* Create legacy_io and legacy_mem files for this bus */ 1682 /* Create legacy_io and legacy_mem files for this bus */
1643 pci_create_legacy_files(b); 1683 pci_create_legacy_files(b);
1644 1684
1645 b->number = b->secondary = bus; 1685 b->number = b->busn_res.start = bus;
1646 1686
1647 if (parent) 1687 if (parent)
1648 dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev)); 1688 dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev));
@@ -1654,7 +1694,10 @@ struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1654 list_move_tail(&window->list, &bridge->windows); 1694 list_move_tail(&window->list, &bridge->windows);
1655 res = window->res; 1695 res = window->res;
1656 offset = window->offset; 1696 offset = window->offset;
1657 pci_bus_add_resource(b, res, 0); 1697 if (res->flags & IORESOURCE_BUS)
1698 pci_bus_insert_busn_res(b, bus, res->end);
1699 else
1700 pci_bus_add_resource(b, res, 0);
1658 if (offset) { 1701 if (offset) {
1659 if (resource_type(res) == IORESOURCE_IO) 1702 if (resource_type(res) == IORESOURCE_IO)
1660 fmt = " (bus address [%#06llx-%#06llx])"; 1703 fmt = " (bus address [%#06llx-%#06llx])";
@@ -1684,16 +1727,104 @@ err_out:
1684 return NULL; 1727 return NULL;
1685} 1728}
1686 1729
1730int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
1731{
1732 struct resource *res = &b->busn_res;
1733 struct resource *parent_res, *conflict;
1734
1735 res->start = bus;
1736 res->end = bus_max;
1737 res->flags = IORESOURCE_BUS;
1738
1739 if (!pci_is_root_bus(b))
1740 parent_res = &b->parent->busn_res;
1741 else {
1742 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
1743 res->flags |= IORESOURCE_PCI_FIXED;
1744 }
1745
1746 conflict = insert_resource_conflict(parent_res, res);
1747
1748 if (conflict)
1749 dev_printk(KERN_DEBUG, &b->dev,
1750 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
1751 res, pci_is_root_bus(b) ? "domain " : "",
1752 parent_res, conflict->name, conflict);
1753 else
1754 dev_printk(KERN_DEBUG, &b->dev,
1755 "busn_res: %pR is inserted under %s%pR\n",
1756 res, pci_is_root_bus(b) ? "domain " : "",
1757 parent_res);
1758
1759 return conflict == NULL;
1760}
1761
1762int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
1763{
1764 struct resource *res = &b->busn_res;
1765 struct resource old_res = *res;
1766 resource_size_t size;
1767 int ret;
1768
1769 if (res->start > bus_max)
1770 return -EINVAL;
1771
1772 size = bus_max - res->start + 1;
1773 ret = adjust_resource(res, res->start, size);
1774 dev_printk(KERN_DEBUG, &b->dev,
1775 "busn_res: %pR end %s updated to %02x\n",
1776 &old_res, ret ? "can not be" : "is", bus_max);
1777
1778 if (!ret && !res->parent)
1779 pci_bus_insert_busn_res(b, res->start, res->end);
1780
1781 return ret;
1782}
1783
1784void pci_bus_release_busn_res(struct pci_bus *b)
1785{
1786 struct resource *res = &b->busn_res;
1787 int ret;
1788
1789 if (!res->flags || !res->parent)
1790 return;
1791
1792 ret = release_resource(res);
1793 dev_printk(KERN_DEBUG, &b->dev,
1794 "busn_res: %pR %s released\n",
1795 res, ret ? "can not be" : "is");
1796}
1797
1687struct pci_bus * __devinit pci_scan_root_bus(struct device *parent, int bus, 1798struct pci_bus * __devinit pci_scan_root_bus(struct device *parent, int bus,
1688 struct pci_ops *ops, void *sysdata, struct list_head *resources) 1799 struct pci_ops *ops, void *sysdata, struct list_head *resources)
1689{ 1800{
1801 struct pci_host_bridge_window *window;
1802 bool found = false;
1690 struct pci_bus *b; 1803 struct pci_bus *b;
1804 int max;
1805
1806 list_for_each_entry(window, resources, list)
1807 if (window->res->flags & IORESOURCE_BUS) {
1808 found = true;
1809 break;
1810 }
1691 1811
1692 b = pci_create_root_bus(parent, bus, ops, sysdata, resources); 1812 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
1693 if (!b) 1813 if (!b)
1694 return NULL; 1814 return NULL;
1695 1815
1696 b->subordinate = pci_scan_child_bus(b); 1816 if (!found) {
1817 dev_info(&b->dev,
1818 "No busn resource found for root bus, will use [bus %02x-ff]\n",
1819 bus);
1820 pci_bus_insert_busn_res(b, bus, 255);
1821 }
1822
1823 max = pci_scan_child_bus(b);
1824
1825 if (!found)
1826 pci_bus_update_busn_res_end(b, max);
1827
1697 pci_bus_add_devices(b); 1828 pci_bus_add_devices(b);
1698 return b; 1829 return b;
1699} 1830}
@@ -1708,9 +1839,10 @@ struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1708 1839
1709 pci_add_resource(&resources, &ioport_resource); 1840 pci_add_resource(&resources, &ioport_resource);
1710 pci_add_resource(&resources, &iomem_resource); 1841 pci_add_resource(&resources, &iomem_resource);
1842 pci_add_resource(&resources, &busn_resource);
1711 b = pci_create_root_bus(parent, bus, ops, sysdata, &resources); 1843 b = pci_create_root_bus(parent, bus, ops, sysdata, &resources);
1712 if (b) 1844 if (b)
1713 b->subordinate = pci_scan_child_bus(b); 1845 pci_scan_child_bus(b);
1714 else 1846 else
1715 pci_free_resource_list(&resources); 1847 pci_free_resource_list(&resources);
1716 return b; 1848 return b;
@@ -1725,9 +1857,10 @@ struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops,
1725 1857
1726 pci_add_resource(&resources, &ioport_resource); 1858 pci_add_resource(&resources, &ioport_resource);
1727 pci_add_resource(&resources, &iomem_resource); 1859 pci_add_resource(&resources, &iomem_resource);
1860 pci_add_resource(&resources, &busn_resource);
1728 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources); 1861 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
1729 if (b) { 1862 if (b) {
1730 b->subordinate = pci_scan_child_bus(b); 1863 pci_scan_child_bus(b);
1731 pci_bus_add_devices(b); 1864 pci_bus_add_devices(b);
1732 } else { 1865 } else {
1733 pci_free_resource_list(&resources); 1866 pci_free_resource_list(&resources);
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 2a7521677541..a2d9d330a01e 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -253,7 +253,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx)
253 * workaround applied too 253 * workaround applied too
254 * [Info kindly provided by ALi] 254 * [Info kindly provided by ALi]
255 */ 255 */
256static void __init quirk_alimagik(struct pci_dev *dev) 256static void __devinit quirk_alimagik(struct pci_dev *dev)
257{ 257{
258 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) { 258 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
259 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); 259 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
@@ -789,7 +789,7 @@ static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
789} 789}
790DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); 790DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
791 791
792static void __init quirk_ioapic_rmw(struct pci_dev *dev) 792static void __devinit quirk_ioapic_rmw(struct pci_dev *dev)
793{ 793{
794 if (dev->devfn == 0 && dev->bus->number == 0) 794 if (dev->devfn == 0 && dev->bus->number == 0)
795 sis_apic_bug = 1; 795 sis_apic_bug = 1;
@@ -801,7 +801,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
801 * Some settings of MMRBC can lead to data corruption so block changes. 801 * Some settings of MMRBC can lead to data corruption so block changes.
802 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide 802 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
803 */ 803 */
804static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev) 804static void __devinit quirk_amd_8131_mmrbc(struct pci_dev *dev)
805{ 805{
806 if (dev->subordinate && dev->revision <= 0x12) { 806 if (dev->subordinate && dev->revision <= 0x12) {
807 dev_info(&dev->dev, "AMD8131 rev %x detected; " 807 dev_info(&dev->dev, "AMD8131 rev %x detected; "
@@ -1082,7 +1082,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB
1082/* 1082/*
1083 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same 1083 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1084 */ 1084 */
1085static void __init quirk_ide_samemode(struct pci_dev *pdev) 1085static void __devinit quirk_ide_samemode(struct pci_dev *pdev)
1086{ 1086{
1087 u8 prog; 1087 u8 prog;
1088 1088
@@ -1121,7 +1121,7 @@ DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1121/* This was originally an Alpha specific thing, but it really fits here. 1121/* This was originally an Alpha specific thing, but it really fits here.
1122 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 1122 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1123 */ 1123 */
1124static void __init quirk_eisa_bridge(struct pci_dev *dev) 1124static void __devinit quirk_eisa_bridge(struct pci_dev *dev)
1125{ 1125{
1126 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 1126 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1127} 1127}
@@ -1155,7 +1155,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_e
1155 */ 1155 */
1156static int asus_hides_smbus; 1156static int asus_hides_smbus;
1157 1157
1158static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev) 1158static void __devinit asus_hides_smbus_hostbridge(struct pci_dev *dev)
1159{ 1159{
1160 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1160 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1161 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 1161 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
@@ -1538,7 +1538,7 @@ DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB3
1538#endif 1538#endif
1539 1539
1540#ifdef CONFIG_X86_IO_APIC 1540#ifdef CONFIG_X86_IO_APIC
1541static void __init quirk_alder_ioapic(struct pci_dev *pdev) 1541static void __devinit quirk_alder_ioapic(struct pci_dev *pdev)
1542{ 1542{
1543 int i; 1543 int i;
1544 1544
@@ -1777,7 +1777,7 @@ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, qui
1777 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. 1777 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1778 * Re-allocate the region if needed... 1778 * Re-allocate the region if needed...
1779 */ 1779 */
1780static void __init quirk_tc86c001_ide(struct pci_dev *dev) 1780static void __devinit quirk_tc86c001_ide(struct pci_dev *dev)
1781{ 1781{
1782 struct resource *r = &dev->resource[0]; 1782 struct resource *r = &dev->resource[0];
1783 1783
@@ -2169,7 +2169,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
2169 * aware of it. Instead of setting the flag on all busses in the 2169 * aware of it. Instead of setting the flag on all busses in the
2170 * machine, simply disable MSI globally. 2170 * machine, simply disable MSI globally.
2171 */ 2171 */
2172static void __init quirk_disable_all_msi(struct pci_dev *dev) 2172static void __devinit quirk_disable_all_msi(struct pci_dev *dev)
2173{ 2173{
2174 pci_no_msi(); 2174 pci_no_msi();
2175 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n"); 2175 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
@@ -2929,6 +2929,20 @@ static void __devinit disable_igfx_irq(struct pci_dev *dev)
2929DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq); 2929DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
2930DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); 2930DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
2931 2931
2932/*
2933 * Some devices may pass our check in pci_intx_mask_supported if
2934 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
2935 * support this feature.
2936 */
2937static void __devinit quirk_broken_intx_masking(struct pci_dev *dev)
2938{
2939 dev->broken_intx_masking = 1;
2940}
2941DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, 0x0030,
2942 quirk_broken_intx_masking);
2943DECLARE_PCI_FIXUP_HEADER(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
2944 quirk_broken_intx_masking);
2945
2932static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, 2946static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
2933 struct pci_fixup *end) 2947 struct pci_fixup *end)
2934{ 2948{
@@ -3179,3 +3193,87 @@ int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3179 3193
3180 return -ENOTTY; 3194 return -ENOTTY;
3181} 3195}
3196
3197static struct pci_dev *pci_func_0_dma_source(struct pci_dev *dev)
3198{
3199 if (!PCI_FUNC(dev->devfn))
3200 return pci_dev_get(dev);
3201
3202 return pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
3203}
3204
3205static const struct pci_dev_dma_source {
3206 u16 vendor;
3207 u16 device;
3208 struct pci_dev *(*dma_source)(struct pci_dev *dev);
3209} pci_dev_dma_source[] = {
3210 /*
3211 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
3212 *
3213 * Some Ricoh devices use the function 0 source ID for DMA on
3214 * other functions of a multifunction device. The DMA devices
3215 * is therefore function 0, which will have implications of the
3216 * iommu grouping of these devices.
3217 */
3218 { PCI_VENDOR_ID_RICOH, 0xe822, pci_func_0_dma_source },
3219 { PCI_VENDOR_ID_RICOH, 0xe230, pci_func_0_dma_source },
3220 { PCI_VENDOR_ID_RICOH, 0xe832, pci_func_0_dma_source },
3221 { PCI_VENDOR_ID_RICOH, 0xe476, pci_func_0_dma_source },
3222 { 0 }
3223};
3224
3225/*
3226 * IOMMUs with isolation capabilities need to be programmed with the
3227 * correct source ID of a device. In most cases, the source ID matches
3228 * the device doing the DMA, but sometimes hardware is broken and will
3229 * tag the DMA as being sourced from a different device. This function
3230 * allows that translation. Note that the reference count of the
3231 * returned device is incremented on all paths.
3232 */
3233struct pci_dev *pci_get_dma_source(struct pci_dev *dev)
3234{
3235 const struct pci_dev_dma_source *i;
3236
3237 for (i = pci_dev_dma_source; i->dma_source; i++) {
3238 if ((i->vendor == dev->vendor ||
3239 i->vendor == (u16)PCI_ANY_ID) &&
3240 (i->device == dev->device ||
3241 i->device == (u16)PCI_ANY_ID))
3242 return i->dma_source(dev);
3243 }
3244
3245 return pci_dev_get(dev);
3246}
3247
3248static const struct pci_dev_acs_enabled {
3249 u16 vendor;
3250 u16 device;
3251 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
3252} pci_dev_acs_enabled[] = {
3253 { 0 }
3254};
3255
3256int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
3257{
3258 const struct pci_dev_acs_enabled *i;
3259 int ret;
3260
3261 /*
3262 * Allow devices that do not expose standard PCIe ACS capabilities
3263 * or control to indicate their support here. Multi-function express
3264 * devices which do not allow internal peer-to-peer between functions,
3265 * but do not implement PCIe ACS may wish to return true here.
3266 */
3267 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
3268 if ((i->vendor == dev->vendor ||
3269 i->vendor == (u16)PCI_ANY_ID) &&
3270 (i->device == dev->device ||
3271 i->device == (u16)PCI_ANY_ID)) {
3272 ret = i->acs_enabled(dev, acs_flags);
3273 if (ret >= 0)
3274 return ret;
3275 }
3276 }
3277
3278 return -ENOTTY;
3279}
diff --git a/drivers/pci/remove.c b/drivers/pci/remove.c
index fd77e2bde2e8..04a4861b4749 100644
--- a/drivers/pci/remove.c
+++ b/drivers/pci/remove.c
@@ -68,6 +68,7 @@ void pci_remove_bus(struct pci_bus *pci_bus)
68 68
69 down_write(&pci_bus_sem); 69 down_write(&pci_bus_sem);
70 list_del(&pci_bus->node); 70 list_del(&pci_bus->node);
71 pci_bus_release_busn_res(pci_bus);
71 up_write(&pci_bus_sem); 72 up_write(&pci_bus_sem);
72 if (!pci_bus->is_added) 73 if (!pci_bus->is_added)
73 return; 74 return;
diff --git a/drivers/pci/search.c b/drivers/pci/search.c
index 9d75dc8ca602..993d4a0a2469 100644
--- a/drivers/pci/search.c
+++ b/drivers/pci/search.c
@@ -15,6 +15,8 @@
15#include "pci.h" 15#include "pci.h"
16 16
17DECLARE_RWSEM(pci_bus_sem); 17DECLARE_RWSEM(pci_bus_sem);
18EXPORT_SYMBOL_GPL(pci_bus_sem);
19
18/* 20/*
19 * find the upstream PCIe-to-PCI bridge of a PCI device 21 * find the upstream PCIe-to-PCI bridge of a PCI device
20 * if the device is PCIE, return NULL 22 * if the device is PCIE, return NULL
diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
index 8fa2d4be88de..561e41cf102d 100644
--- a/drivers/pci/setup-bus.c
+++ b/drivers/pci/setup-bus.c
@@ -265,7 +265,7 @@ out:
265 * assign_requested_resources_sorted() - satisfy resource requests 265 * assign_requested_resources_sorted() - satisfy resource requests
266 * 266 *
267 * @head : head of the list tracking requests for resources 267 * @head : head of the list tracking requests for resources
268 * @failed_list : head of the list tracking requests that could 268 * @fail_head : head of the list tracking requests that could
269 * not be allocated 269 * not be allocated
270 * 270 *
271 * Satisfy resource requests of each element in the list. Add 271 * Satisfy resource requests of each element in the list. Add
@@ -404,8 +404,8 @@ void pci_setup_cardbus(struct pci_bus *bus)
404 struct resource *res; 404 struct resource *res;
405 struct pci_bus_region region; 405 struct pci_bus_region region;
406 406
407 dev_info(&bridge->dev, "CardBus bridge to [bus %02x-%02x]\n", 407 dev_info(&bridge->dev, "CardBus bridge to %pR\n",
408 bus->secondary, bus->subordinate); 408 &bus->busn_res);
409 409
410 res = bus->resource[0]; 410 res = bus->resource[0];
411 pcibios_resource_to_bus(bridge, &region, res); 411 pcibios_resource_to_bus(bridge, &region, res);
@@ -553,8 +553,8 @@ static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
553{ 553{
554 struct pci_dev *bridge = bus->self; 554 struct pci_dev *bridge = bus->self;
555 555
556 dev_info(&bridge->dev, "PCI bridge to [bus %02x-%02x]\n", 556 dev_info(&bridge->dev, "PCI bridge to %pR\n",
557 bus->secondary, bus->subordinate); 557 &bus->busn_res);
558 558
559 if (type & IORESOURCE_IO) 559 if (type & IORESOURCE_IO)
560 pci_setup_bridge_io(bus); 560 pci_setup_bridge_io(bus);
@@ -745,8 +745,8 @@ static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
745 if (!size0 && !size1) { 745 if (!size0 && !size1) {
746 if (b_res->start || b_res->end) 746 if (b_res->start || b_res->end)
747 dev_info(&bus->self->dev, "disabling bridge window " 747 dev_info(&bus->self->dev, "disabling bridge window "
748 "%pR to [bus %02x-%02x] (unused)\n", b_res, 748 "%pR to %pR (unused)\n", b_res,
749 bus->secondary, bus->subordinate); 749 &bus->busn_res);
750 b_res->flags = 0; 750 b_res->flags = 0;
751 return; 751 return;
752 } 752 }
@@ -757,8 +757,8 @@ static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
757 if (size1 > size0 && realloc_head) { 757 if (size1 > size0 && realloc_head) {
758 add_to_list(realloc_head, bus->self, b_res, size1-size0, 4096); 758 add_to_list(realloc_head, bus->self, b_res, size1-size0, 4096);
759 dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window " 759 dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window "
760 "%pR to [bus %02x-%02x] add_size %lx\n", b_res, 760 "%pR to %pR add_size %lx\n", b_res,
761 bus->secondary, bus->subordinate, size1-size0); 761 &bus->busn_res, size1-size0);
762 } 762 }
763} 763}
764 764
@@ -863,8 +863,8 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
863 if (!size0 && !size1) { 863 if (!size0 && !size1) {
864 if (b_res->start || b_res->end) 864 if (b_res->start || b_res->end)
865 dev_info(&bus->self->dev, "disabling bridge window " 865 dev_info(&bus->self->dev, "disabling bridge window "
866 "%pR to [bus %02x-%02x] (unused)\n", b_res, 866 "%pR to %pR (unused)\n", b_res,
867 bus->secondary, bus->subordinate); 867 &bus->busn_res);
868 b_res->flags = 0; 868 b_res->flags = 0;
869 return 1; 869 return 1;
870 } 870 }
@@ -874,8 +874,8 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
874 if (size1 > size0 && realloc_head) { 874 if (size1 > size0 && realloc_head) {
875 add_to_list(realloc_head, bus->self, b_res, size1-size0, min_align); 875 add_to_list(realloc_head, bus->self, b_res, size1-size0, min_align);
876 dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window " 876 dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window "
877 "%pR to [bus %02x-%02x] add_size %llx\n", b_res, 877 "%pR to %pR add_size %llx\n", b_res,
878 bus->secondary, bus->subordinate, (unsigned long long)size1-size0); 878 &bus->busn_res, (unsigned long long)size1-size0);
879 } 879 }
880 return 1; 880 return 1;
881} 881}
diff --git a/drivers/pcmcia/cardbus.c b/drivers/pcmcia/cardbus.c
index 6e75153c5b4f..24caeaf50529 100644
--- a/drivers/pcmcia/cardbus.c
+++ b/drivers/pcmcia/cardbus.c
@@ -73,7 +73,7 @@ int __ref cb_alloc(struct pcmcia_socket *s)
73 s->functions = pci_scan_slot(bus, PCI_DEVFN(0, 0)); 73 s->functions = pci_scan_slot(bus, PCI_DEVFN(0, 0));
74 pci_fixup_cardbus(bus); 74 pci_fixup_cardbus(bus);
75 75
76 max = bus->secondary; 76 max = bus->busn_res.start;
77 for (pass = 0; pass < 2; pass++) 77 for (pass = 0; pass < 2; pass++)
78 list_for_each_entry(dev, &bus->devices, bus_list) 78 list_for_each_entry(dev, &bus->devices, bus_list)
79 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 79 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
diff --git a/drivers/pcmcia/yenta_socket.c b/drivers/pcmcia/yenta_socket.c
index d07f9ac8c41d..667678db1153 100644
--- a/drivers/pcmcia/yenta_socket.c
+++ b/drivers/pcmcia/yenta_socket.c
@@ -1048,8 +1048,8 @@ static void yenta_config_init(struct yenta_socket *socket)
1048 config_writeb(socket, PCI_LATENCY_TIMER, 168); 1048 config_writeb(socket, PCI_LATENCY_TIMER, 168);
1049 config_writel(socket, PCI_PRIMARY_BUS, 1049 config_writel(socket, PCI_PRIMARY_BUS,
1050 (176 << 24) | /* sec. latency timer */ 1050 (176 << 24) | /* sec. latency timer */
1051 (dev->subordinate->subordinate << 16) | /* subordinate bus */ 1051 ((unsigned int)dev->subordinate->busn_res.end << 16) | /* subordinate bus */
1052 (dev->subordinate->secondary << 8) | /* secondary bus */ 1052 ((unsigned int)dev->subordinate->busn_res.start << 8) | /* secondary bus */
1053 dev->subordinate->primary); /* primary bus */ 1053 dev->subordinate->primary); /* primary bus */
1054 1054
1055 /* 1055 /*
@@ -1086,14 +1086,14 @@ static void yenta_fixup_parent_bridge(struct pci_bus *cardbus_bridge)
1086 struct pci_bus *bridge_to_fix = cardbus_bridge->parent; 1086 struct pci_bus *bridge_to_fix = cardbus_bridge->parent;
1087 1087
1088 /* Check bus numbers are already set up correctly: */ 1088 /* Check bus numbers are already set up correctly: */
1089 if (bridge_to_fix->subordinate >= cardbus_bridge->subordinate) 1089 if (bridge_to_fix->busn_res.end >= cardbus_bridge->busn_res.end)
1090 return; /* The subordinate number is ok, nothing to do */ 1090 return; /* The subordinate number is ok, nothing to do */
1091 1091
1092 if (!bridge_to_fix->parent) 1092 if (!bridge_to_fix->parent)
1093 return; /* Root bridges are ok */ 1093 return; /* Root bridges are ok */
1094 1094
1095 /* stay within the limits of the bus range of the parent: */ 1095 /* stay within the limits of the bus range of the parent: */
1096 upper_limit = bridge_to_fix->parent->subordinate; 1096 upper_limit = bridge_to_fix->parent->busn_res.end;
1097 1097
1098 /* check the bus ranges of all silbling bridges to prevent overlap */ 1098 /* check the bus ranges of all silbling bridges to prevent overlap */
1099 list_for_each(tmp, &bridge_to_fix->parent->children) { 1099 list_for_each(tmp, &bridge_to_fix->parent->children) {
@@ -1104,36 +1104,36 @@ static void yenta_fixup_parent_bridge(struct pci_bus *cardbus_bridge)
1104 * current upper limit, set the new upper limit to 1104 * current upper limit, set the new upper limit to
1105 * the bus number below the silbling's range: 1105 * the bus number below the silbling's range:
1106 */ 1106 */
1107 if (silbling->secondary > bridge_to_fix->subordinate 1107 if (silbling->busn_res.start > bridge_to_fix->busn_res.end
1108 && silbling->secondary <= upper_limit) 1108 && silbling->busn_res.start <= upper_limit)
1109 upper_limit = silbling->secondary - 1; 1109 upper_limit = silbling->busn_res.start - 1;
1110 } 1110 }
1111 1111
1112 /* Show that the wanted subordinate number is not possible: */ 1112 /* Show that the wanted subordinate number is not possible: */
1113 if (cardbus_bridge->subordinate > upper_limit) 1113 if (cardbus_bridge->busn_res.end > upper_limit)
1114 dev_printk(KERN_WARNING, &cardbus_bridge->dev, 1114 dev_printk(KERN_WARNING, &cardbus_bridge->dev,
1115 "Upper limit for fixing this " 1115 "Upper limit for fixing this "
1116 "bridge's parent bridge: #%02x\n", upper_limit); 1116 "bridge's parent bridge: #%02x\n", upper_limit);
1117 1117
1118 /* If we have room to increase the bridge's subordinate number, */ 1118 /* If we have room to increase the bridge's subordinate number, */
1119 if (bridge_to_fix->subordinate < upper_limit) { 1119 if (bridge_to_fix->busn_res.end < upper_limit) {
1120 1120
1121 /* use the highest number of the hidden bus, within limits */ 1121 /* use the highest number of the hidden bus, within limits */
1122 unsigned char subordinate_to_assign = 1122 unsigned char subordinate_to_assign =
1123 min(cardbus_bridge->subordinate, upper_limit); 1123 min_t(int, cardbus_bridge->busn_res.end, upper_limit);
1124 1124
1125 dev_printk(KERN_INFO, &bridge_to_fix->dev, 1125 dev_printk(KERN_INFO, &bridge_to_fix->dev,
1126 "Raising subordinate bus# of parent " 1126 "Raising subordinate bus# of parent "
1127 "bus (#%02x) from #%02x to #%02x\n", 1127 "bus (#%02x) from #%02x to #%02x\n",
1128 bridge_to_fix->number, 1128 bridge_to_fix->number,
1129 bridge_to_fix->subordinate, subordinate_to_assign); 1129 (int)bridge_to_fix->busn_res.end, subordinate_to_assign);
1130 1130
1131 /* Save the new subordinate in the bus struct of the bridge */ 1131 /* Save the new subordinate in the bus struct of the bridge */
1132 bridge_to_fix->subordinate = subordinate_to_assign; 1132 bridge_to_fix->busn_res.end = subordinate_to_assign;
1133 1133
1134 /* and update the PCI config space with the new subordinate */ 1134 /* and update the PCI config space with the new subordinate */
1135 pci_write_config_byte(bridge_to_fix->self, 1135 pci_write_config_byte(bridge_to_fix->self,
1136 PCI_SUBORDINATE_BUS, bridge_to_fix->subordinate); 1136 PCI_SUBORDINATE_BUS, bridge_to_fix->busn_res.end);
1137 } 1137 }
1138} 1138}
1139 1139
diff --git a/drivers/pnp/pnpacpi/core.c b/drivers/pnp/pnpacpi/core.c
index d21e8f59c84e..507a8e2b9a4c 100644
--- a/drivers/pnp/pnpacpi/core.c
+++ b/drivers/pnp/pnpacpi/core.c
@@ -170,8 +170,8 @@ static int pnpacpi_suspend(struct pnp_dev *dev, pm_message_t state)
170 } 170 }
171 171
172 if (acpi_bus_power_manageable(handle)) { 172 if (acpi_bus_power_manageable(handle)) {
173 int power_state = acpi_pm_device_sleep_state(&dev->dev, NULL); 173 int power_state = acpi_pm_device_sleep_state(&dev->dev, NULL,
174 174 ACPI_STATE_D3);
175 if (power_state < 0) 175 if (power_state < 0)
176 power_state = (state.event == PM_EVENT_ON) ? 176 power_state = (state.event == PM_EVENT_ON) ?
177 ACPI_STATE_D0 : ACPI_STATE_D3; 177 ACPI_STATE_D0 : ACPI_STATE_D3;
diff --git a/drivers/xen/xen-pciback/conf_space.c b/drivers/xen/xen-pciback/conf_space.c
index 30d7be026c18..46ae0f9f02ad 100644
--- a/drivers/xen/xen-pciback/conf_space.c
+++ b/drivers/xen/xen-pciback/conf_space.c
@@ -124,7 +124,7 @@ static inline u32 merge_value(u32 val, u32 new_val, u32 new_val_mask,
124 return val; 124 return val;
125} 125}
126 126
127static int pcibios_err_to_errno(int err) 127static int xen_pcibios_err_to_errno(int err)
128{ 128{
129 switch (err) { 129 switch (err) {
130 case PCIBIOS_SUCCESSFUL: 130 case PCIBIOS_SUCCESSFUL:
@@ -202,7 +202,7 @@ out:
202 pci_name(dev), size, offset, value); 202 pci_name(dev), size, offset, value);
203 203
204 *ret_val = value; 204 *ret_val = value;
205 return pcibios_err_to_errno(err); 205 return xen_pcibios_err_to_errno(err);
206} 206}
207 207
208int xen_pcibk_config_write(struct pci_dev *dev, int offset, int size, u32 value) 208int xen_pcibk_config_write(struct pci_dev *dev, int offset, int size, u32 value)
@@ -290,7 +290,7 @@ int xen_pcibk_config_write(struct pci_dev *dev, int offset, int size, u32 value)
290 } 290 }
291 } 291 }
292 292
293 return pcibios_err_to_errno(err); 293 return xen_pcibios_err_to_errno(err);
294} 294}
295 295
296void xen_pcibk_config_free_dyn_fields(struct pci_dev *dev) 296void xen_pcibk_config_free_dyn_fields(struct pci_dev *dev)
diff --git a/include/acpi/acnames.h b/include/acpi/acnames.h
index 38f508816e4a..b177f97f53b6 100644
--- a/include/acpi/acnames.h
+++ b/include/acpi/acnames.h
@@ -62,6 +62,7 @@
62#define METHOD_NAME__AEI "_AEI" 62#define METHOD_NAME__AEI "_AEI"
63#define METHOD_NAME__PRW "_PRW" 63#define METHOD_NAME__PRW "_PRW"
64#define METHOD_NAME__SRS "_SRS" 64#define METHOD_NAME__SRS "_SRS"
65#define METHOD_NAME__CBA "_CBA"
65 66
66/* Method names - these methods must appear at the namespace root */ 67/* Method names - these methods must appear at the namespace root */
67 68
diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h
index 9e6e1c6eb60a..6a6c46e84ae3 100644
--- a/include/acpi/acpi_bus.h
+++ b/include/acpi/acpi_bus.h
@@ -401,6 +401,7 @@ struct acpi_pci_root {
401 401
402 u32 osc_support_set; /* _OSC state of support bits */ 402 u32 osc_support_set; /* _OSC state of support bits */
403 u32 osc_control_set; /* _OSC state of control bits */ 403 u32 osc_control_set; /* _OSC state of control bits */
404 phys_addr_t mcfg_addr;
404}; 405};
405 406
406/* helper */ 407/* helper */
@@ -414,13 +415,13 @@ int acpi_enable_wakeup_device_power(struct acpi_device *dev, int state);
414int acpi_disable_wakeup_device_power(struct acpi_device *dev); 415int acpi_disable_wakeup_device_power(struct acpi_device *dev);
415 416
416#ifdef CONFIG_PM 417#ifdef CONFIG_PM
417int acpi_pm_device_sleep_state(struct device *, int *); 418int acpi_pm_device_sleep_state(struct device *, int *, int);
418#else 419#else
419static inline int acpi_pm_device_sleep_state(struct device *d, int *p) 420static inline int acpi_pm_device_sleep_state(struct device *d, int *p, int m)
420{ 421{
421 if (p) 422 if (p)
422 *p = ACPI_STATE_D0; 423 *p = ACPI_STATE_D0;
423 return ACPI_STATE_D3; 424 return (m >= ACPI_STATE_D0 && m <= ACPI_STATE_D3) ? m : ACPI_STATE_D0;
424} 425}
425#endif 426#endif
426 427
diff --git a/include/linux/pci-acpi.h b/include/linux/pci-acpi.h
index 44623500f419..248fba2af98a 100644
--- a/include/linux/pci-acpi.h
+++ b/include/linux/pci-acpi.h
@@ -17,6 +17,7 @@ extern acpi_status pci_acpi_remove_bus_pm_notifier(struct acpi_device *dev);
17extern acpi_status pci_acpi_add_pm_notifier(struct acpi_device *dev, 17extern acpi_status pci_acpi_add_pm_notifier(struct acpi_device *dev,
18 struct pci_dev *pci_dev); 18 struct pci_dev *pci_dev);
19extern acpi_status pci_acpi_remove_pm_notifier(struct acpi_device *dev); 19extern acpi_status pci_acpi_remove_pm_notifier(struct acpi_device *dev);
20extern phys_addr_t acpi_pci_root_get_mcfg_addr(acpi_handle handle);
20 21
21static inline acpi_handle acpi_find_root_bridge_handle(struct pci_dev *pdev) 22static inline acpi_handle acpi_find_root_bridge_handle(struct pci_dev *pdev)
22{ 23{
diff --git a/include/linux/pci.h b/include/linux/pci.h
index f91143e86f85..85cffb823b4e 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -132,9 +132,10 @@ static inline const char *pci_power_name(pci_power_t state)
132 return pci_power_names[1 + (int) state]; 132 return pci_power_names[1 + (int) state];
133} 133}
134 134
135#define PCI_PM_D2_DELAY 200 135#define PCI_PM_D2_DELAY 200
136#define PCI_PM_D3_WAIT 10 136#define PCI_PM_D3_WAIT 10
137#define PCI_PM_BUS_WAIT 50 137#define PCI_PM_D3COLD_WAIT 100
138#define PCI_PM_BUS_WAIT 50
138 139
139/** The pci_channel state describes connectivity between the CPU and 140/** The pci_channel state describes connectivity between the CPU and
140 * the pci device. If some PCI bus between here and the pci device 141 * the pci device. If some PCI bus between here and the pci device
@@ -278,11 +279,18 @@ struct pci_dev {
278 unsigned int pme_poll:1; /* Poll device's PME status bit */ 279 unsigned int pme_poll:1; /* Poll device's PME status bit */
279 unsigned int d1_support:1; /* Low power state D1 is supported */ 280 unsigned int d1_support:1; /* Low power state D1 is supported */
280 unsigned int d2_support:1; /* Low power state D2 is supported */ 281 unsigned int d2_support:1; /* Low power state D2 is supported */
281 unsigned int no_d1d2:1; /* Only allow D0 and D3 */ 282 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
283 unsigned int no_d3cold:1; /* D3cold is forbidden */
284 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
282 unsigned int mmio_always_on:1; /* disallow turning off io/mem 285 unsigned int mmio_always_on:1; /* disallow turning off io/mem
283 decoding during bar sizing */ 286 decoding during bar sizing */
284 unsigned int wakeup_prepared:1; 287 unsigned int wakeup_prepared:1;
288 unsigned int runtime_d3cold:1; /* whether go through runtime
289 D3cold, not set for devices
290 powered on/off by the
291 corresponding bridge */
285 unsigned int d3_delay; /* D3->D0 transition time in ms */ 292 unsigned int d3_delay; /* D3->D0 transition time in ms */
293 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
286 294
287#ifdef CONFIG_PCIEASPM 295#ifdef CONFIG_PCIEASPM
288 struct pcie_link_state *link_state; /* ASPM link state. */ 296 struct pcie_link_state *link_state; /* ASPM link state. */
@@ -324,6 +332,7 @@ struct pci_dev {
324 unsigned int is_hotplug_bridge:1; 332 unsigned int is_hotplug_bridge:1;
325 unsigned int __aer_firmware_first_valid:1; 333 unsigned int __aer_firmware_first_valid:1;
326 unsigned int __aer_firmware_first:1; 334 unsigned int __aer_firmware_first:1;
335 unsigned int broken_intx_masking:1;
327 pci_dev_flags_t dev_flags; 336 pci_dev_flags_t dev_flags;
328 atomic_t enable_cnt; /* pci_enable_device has been called */ 337 atomic_t enable_cnt; /* pci_enable_device has been called */
329 338
@@ -368,6 +377,8 @@ static inline int pci_channel_offline(struct pci_dev *pdev)
368 return (pdev->error_state != pci_channel_io_normal); 377 return (pdev->error_state != pci_channel_io_normal);
369} 378}
370 379
380extern struct resource busn_resource;
381
371struct pci_host_bridge_window { 382struct pci_host_bridge_window {
372 struct list_head list; 383 struct list_head list;
373 struct resource *res; /* host bridge aperture (CPU address) */ 384 struct resource *res; /* host bridge aperture (CPU address) */
@@ -419,6 +430,7 @@ struct pci_bus {
419 struct list_head slots; /* list of slots on this bus */ 430 struct list_head slots; /* list of slots on this bus */
420 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 431 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
421 struct list_head resources; /* address space routed to this bus */ 432 struct list_head resources; /* address space routed to this bus */
433 struct resource busn_res; /* bus numbers routed to this bus */
422 434
423 struct pci_ops *ops; /* configuration access functions */ 435 struct pci_ops *ops; /* configuration access functions */
424 void *sysdata; /* hook for sys-specific extension */ 436 void *sysdata; /* hook for sys-specific extension */
@@ -426,8 +438,6 @@ struct pci_bus {
426 438
427 unsigned char number; /* bus number */ 439 unsigned char number; /* bus number */
428 unsigned char primary; /* number of primary bridge */ 440 unsigned char primary; /* number of primary bridge */
429 unsigned char secondary; /* number of secondary bridge */
430 unsigned char subordinate; /* max number of subordinate buses */
431 unsigned char max_bus_speed; /* enum pci_bus_speed */ 441 unsigned char max_bus_speed; /* enum pci_bus_speed */
432 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 442 unsigned char cur_bus_speed; /* enum pci_bus_speed */
433 443
@@ -474,6 +484,32 @@ static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false;
474#define PCIBIOS_SET_FAILED 0x88 484#define PCIBIOS_SET_FAILED 0x88
475#define PCIBIOS_BUFFER_TOO_SMALL 0x89 485#define PCIBIOS_BUFFER_TOO_SMALL 0x89
476 486
487/*
488 * Translate above to generic errno for passing back through non-pci.
489 */
490static inline int pcibios_err_to_errno(int err)
491{
492 if (err <= PCIBIOS_SUCCESSFUL)
493 return err; /* Assume already errno */
494
495 switch (err) {
496 case PCIBIOS_FUNC_NOT_SUPPORTED:
497 return -ENOENT;
498 case PCIBIOS_BAD_VENDOR_ID:
499 return -EINVAL;
500 case PCIBIOS_DEVICE_NOT_FOUND:
501 return -ENODEV;
502 case PCIBIOS_BAD_REGISTER_NUMBER:
503 return -EFAULT;
504 case PCIBIOS_SET_FAILED:
505 return -EIO;
506 case PCIBIOS_BUFFER_TOO_SMALL:
507 return -ENOSPC;
508 }
509
510 return -ENOTTY;
511}
512
477/* Low-level architecture-dependent routines */ 513/* Low-level architecture-dependent routines */
478 514
479struct pci_ops { 515struct pci_ops {
@@ -669,6 +705,9 @@ struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
669struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 705struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
670 struct pci_ops *ops, void *sysdata, 706 struct pci_ops *ops, void *sysdata,
671 struct list_head *resources); 707 struct list_head *resources);
708int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
709int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
710void pci_bus_release_busn_res(struct pci_bus *b);
672struct pci_bus * __devinit pci_scan_root_bus(struct device *parent, int bus, 711struct pci_bus * __devinit pci_scan_root_bus(struct device *parent, int bus,
673 struct pci_ops *ops, void *sysdata, 712 struct pci_ops *ops, void *sysdata,
674 struct list_head *resources); 713 struct list_head *resources);
@@ -715,8 +754,6 @@ enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
715int pci_find_capability(struct pci_dev *dev, int cap); 754int pci_find_capability(struct pci_dev *dev, int cap);
716int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 755int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
717int pci_find_ext_capability(struct pci_dev *dev, int cap); 756int pci_find_ext_capability(struct pci_dev *dev, int cap);
718int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
719 int cap);
720int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 757int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
721int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); 758int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
722struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 759struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
@@ -778,6 +815,14 @@ static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
778 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val); 815 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
779} 816}
780 817
818/* user-space driven config access */
819int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
820int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
821int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
822int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
823int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
824int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
825
781int __must_check pci_enable_device(struct pci_dev *dev); 826int __must_check pci_enable_device(struct pci_dev *dev);
782int __must_check pci_enable_device_io(struct pci_dev *dev); 827int __must_check pci_enable_device_io(struct pci_dev *dev);
783int __must_check pci_enable_device_mem(struct pci_dev *dev); 828int __must_check pci_enable_device_mem(struct pci_dev *dev);
@@ -876,7 +921,6 @@ enum pci_obff_signal_type {
876int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type); 921int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type);
877void pci_disable_obff(struct pci_dev *dev); 922void pci_disable_obff(struct pci_dev *dev);
878 923
879bool pci_ltr_supported(struct pci_dev *dev);
880int pci_enable_ltr(struct pci_dev *dev); 924int pci_enable_ltr(struct pci_dev *dev);
881void pci_disable_ltr(struct pci_dev *dev); 925void pci_disable_ltr(struct pci_dev *dev);
882int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns); 926int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns);
@@ -1333,6 +1377,9 @@ static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1333static inline int pci_domain_nr(struct pci_bus *bus) 1377static inline int pci_domain_nr(struct pci_bus *bus)
1334{ return 0; } 1378{ return 0; }
1335 1379
1380static inline struct pci_dev *pci_dev_get(struct pci_dev *dev)
1381{ return NULL; }
1382
1336#define dev_is_pci(d) (false) 1383#define dev_is_pci(d) (false)
1337#define dev_is_pf(d) (false) 1384#define dev_is_pf(d) (false)
1338#define dev_num_vf(d) (0) 1385#define dev_num_vf(d) (0)
@@ -1487,9 +1534,20 @@ enum pci_fixup_pass {
1487 1534
1488#ifdef CONFIG_PCI_QUIRKS 1535#ifdef CONFIG_PCI_QUIRKS
1489void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 1536void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1537struct pci_dev *pci_get_dma_source(struct pci_dev *dev);
1538int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1490#else 1539#else
1491static inline void pci_fixup_device(enum pci_fixup_pass pass, 1540static inline void pci_fixup_device(enum pci_fixup_pass pass,
1492 struct pci_dev *dev) {} 1541 struct pci_dev *dev) {}
1542static inline struct pci_dev *pci_get_dma_source(struct pci_dev *dev)
1543{
1544 return pci_dev_get(dev);
1545}
1546static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1547 u16 acs_flags)
1548{
1549 return -ENOTTY;
1550}
1493#endif 1551#endif
1494 1552
1495void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 1553void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
@@ -1592,7 +1650,9 @@ static inline bool pci_is_pcie(struct pci_dev *dev)
1592} 1650}
1593 1651
1594void pci_request_acs(void); 1652void pci_request_acs(void);
1595 1653bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
1654bool pci_acs_path_enabled(struct pci_dev *start,
1655 struct pci_dev *end, u16 acs_flags);
1596 1656
1597#define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 1657#define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1598#define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT) 1658#define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT)
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index 4b608f543412..80e8605b5f93 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -26,6 +26,7 @@
26 * Under PCI, each device has 256 bytes of configuration address space, 26 * Under PCI, each device has 256 bytes of configuration address space,
27 * of which the first 64 bytes are standardized as follows: 27 * of which the first 64 bytes are standardized as follows:
28 */ 28 */
29#define PCI_STD_HEADER_SIZEOF 64
29#define PCI_VENDOR_ID 0x00 /* 16 bits */ 30#define PCI_VENDOR_ID 0x00 /* 16 bits */
30#define PCI_DEVICE_ID 0x02 /* 16 bits */ 31#define PCI_DEVICE_ID 0x02 /* 16 bits */
31#define PCI_COMMAND 0x04 /* 16 bits */ 32#define PCI_COMMAND 0x04 /* 16 bits */
@@ -209,9 +210,12 @@
209#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ 210#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
210#define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */ 211#define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */
211#define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */ 212#define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */
213#define PCI_CAP_ID_SECDEV 0x0F /* Secure Device */
212#define PCI_CAP_ID_EXP 0x10 /* PCI Express */ 214#define PCI_CAP_ID_EXP 0x10 /* PCI Express */
213#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ 215#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
216#define PCI_CAP_ID_SATA 0x12 /* SATA Data/Index Conf. */
214#define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */ 217#define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */
218#define PCI_CAP_ID_MAX PCI_CAP_ID_AF
215#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ 219#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
216#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ 220#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
217#define PCI_CAP_SIZEOF 4 221#define PCI_CAP_SIZEOF 4
@@ -276,6 +280,7 @@
276#define PCI_VPD_ADDR_MASK 0x7fff /* Address mask */ 280#define PCI_VPD_ADDR_MASK 0x7fff /* Address mask */
277#define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */ 281#define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */
278#define PCI_VPD_DATA 4 /* 32-bits of data returned here */ 282#define PCI_VPD_DATA 4 /* 32-bits of data returned here */
283#define PCI_CAP_VPD_SIZEOF 8
279 284
280/* Slot Identification */ 285/* Slot Identification */
281 286
@@ -297,8 +302,10 @@
297#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ 302#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
298#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ 303#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
299#define PCI_MSI_MASK_32 12 /* Mask bits register for 32-bit devices */ 304#define PCI_MSI_MASK_32 12 /* Mask bits register for 32-bit devices */
305#define PCI_MSI_PENDING_32 16 /* Pending intrs for 32-bit devices */
300#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ 306#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
301#define PCI_MSI_MASK_64 16 /* Mask bits register for 64-bit devices */ 307#define PCI_MSI_MASK_64 16 /* Mask bits register for 64-bit devices */
308#define PCI_MSI_PENDING_64 20 /* Pending intrs for 64-bit devices */
302 309
303/* MSI-X registers */ 310/* MSI-X registers */
304#define PCI_MSIX_FLAGS 2 311#define PCI_MSIX_FLAGS 2
@@ -308,6 +315,7 @@
308#define PCI_MSIX_TABLE 4 315#define PCI_MSIX_TABLE 4
309#define PCI_MSIX_PBA 8 316#define PCI_MSIX_PBA 8
310#define PCI_MSIX_FLAGS_BIRMASK (7 << 0) 317#define PCI_MSIX_FLAGS_BIRMASK (7 << 0)
318#define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */
311 319
312/* MSI-X entry's format */ 320/* MSI-X entry's format */
313#define PCI_MSIX_ENTRY_SIZE 16 321#define PCI_MSIX_ENTRY_SIZE 16
@@ -338,6 +346,7 @@
338#define PCI_AF_CTRL_FLR 0x01 346#define PCI_AF_CTRL_FLR 0x01
339#define PCI_AF_STATUS 5 347#define PCI_AF_STATUS 5
340#define PCI_AF_STATUS_TP 0x01 348#define PCI_AF_STATUS_TP 0x01
349#define PCI_CAP_AF_SIZEOF 6 /* size of AF registers */
341 350
342/* PCI-X registers */ 351/* PCI-X registers */
343 352
@@ -374,6 +383,10 @@
374#define PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */ 383#define PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */
375#define PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */ 384#define PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */
376#define PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */ 385#define PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
386#define PCI_X_ECC_CSR 8 /* ECC control and status */
387#define PCI_CAP_PCIX_SIZEOF_V0 8 /* size of registers for Version 0 */
388#define PCI_CAP_PCIX_SIZEOF_V1 24 /* size for Version 1 */
389#define PCI_CAP_PCIX_SIZEOF_V2 PCI_CAP_PCIX_SIZEOF_V1 /* Same for v2 */
377 390
378/* PCI Bridge Subsystem ID registers */ 391/* PCI Bridge Subsystem ID registers */
379 392
@@ -462,6 +475,7 @@
462#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ 475#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
463#define PCI_EXP_LNKSTA_LBMS 0x4000 /* Link Bandwidth Management Status */ 476#define PCI_EXP_LNKSTA_LBMS 0x4000 /* Link Bandwidth Management Status */
464#define PCI_EXP_LNKSTA_LABS 0x8000 /* Link Autonomous Bandwidth Status */ 477#define PCI_EXP_LNKSTA_LABS 0x8000 /* Link Autonomous Bandwidth Status */
478#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 20 /* v1 endpoints end here */
465#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ 479#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
466#define PCI_EXP_SLTCAP_ABP 0x00000001 /* Attention Button Present */ 480#define PCI_EXP_SLTCAP_ABP 0x00000001 /* Attention Button Present */
467#define PCI_EXP_SLTCAP_PCP 0x00000002 /* Power Controller Present */ 481#define PCI_EXP_SLTCAP_PCP 0x00000002 /* Power Controller Present */
@@ -507,6 +521,12 @@
507#define PCI_EXP_RTSTA 32 /* Root Status */ 521#define PCI_EXP_RTSTA 32 /* Root Status */
508#define PCI_EXP_RTSTA_PME 0x10000 /* PME status */ 522#define PCI_EXP_RTSTA_PME 0x10000 /* PME status */
509#define PCI_EXP_RTSTA_PENDING 0x20000 /* PME pending */ 523#define PCI_EXP_RTSTA_PENDING 0x20000 /* PME pending */
524/*
525 * Note that the following PCI Express 'Capability Structure' registers
526 * were introduced with 'Capability Version' 0x2 (v2). These registers
527 * do not exist on devices with Capability Version 1. Use pci_pcie_cap2()
528 * to use these fields safely.
529 */
510#define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */ 530#define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */
511#define PCI_EXP_DEVCAP2_ARI 0x20 /* Alternative Routing-ID */ 531#define PCI_EXP_DEVCAP2_ARI 0x20 /* Alternative Routing-ID */
512#define PCI_EXP_DEVCAP2_LTR 0x800 /* Latency tolerance reporting */ 532#define PCI_EXP_DEVCAP2_LTR 0x800 /* Latency tolerance reporting */
@@ -521,6 +541,7 @@
521#define PCI_EXP_OBFF_MSGA_EN 0x2000 /* OBFF enable with Message type A */ 541#define PCI_EXP_OBFF_MSGA_EN 0x2000 /* OBFF enable with Message type A */
522#define PCI_EXP_OBFF_MSGB_EN 0x4000 /* OBFF enable with Message type B */ 542#define PCI_EXP_OBFF_MSGB_EN 0x4000 /* OBFF enable with Message type B */
523#define PCI_EXP_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */ 543#define PCI_EXP_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */
544#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 44 /* v2 endpoints end here */
524#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ 545#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
525#define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */ 546#define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */
526 547
@@ -529,23 +550,43 @@
529#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) 550#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
530#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) 551#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
531 552
532#define PCI_EXT_CAP_ID_ERR 1 553#define PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */
533#define PCI_EXT_CAP_ID_VC 2 554#define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel Capability */
534#define PCI_EXT_CAP_ID_DSN 3 555#define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
535#define PCI_EXT_CAP_ID_PWR 4 556#define PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */
536#define PCI_EXT_CAP_ID_VNDR 11 557#define PCI_EXT_CAP_ID_RCLD 0x05 /* Root Complex Link Declaration */
537#define PCI_EXT_CAP_ID_ACS 13 558#define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */
538#define PCI_EXT_CAP_ID_ARI 14 559#define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */
539#define PCI_EXT_CAP_ID_ATS 15 560#define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */
540#define PCI_EXT_CAP_ID_SRIOV 16 561#define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */
541#define PCI_EXT_CAP_ID_PRI 19 562#define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */
542#define PCI_EXT_CAP_ID_LTR 24 563#define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor Specific */
543#define PCI_EXT_CAP_ID_PASID 27 564#define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */
565#define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */
566#define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */
567#define PCI_EXT_CAP_ID_ATS 0x0F /* Address Translation Services */
568#define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */
569#define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */
570#define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */
571#define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */
572#define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* reserved for AMD */
573#define PCI_EXT_CAP_ID_REBAR 0x15 /* resizable BAR */
574#define PCI_EXT_CAP_ID_DPA 0x16 /* dynamic power alloc */
575#define PCI_EXT_CAP_ID_TPH 0x17 /* TPH request */
576#define PCI_EXT_CAP_ID_LTR 0x18 /* latency tolerance reporting */
577#define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe */
578#define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */
579#define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */
580#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PASID
581
582#define PCI_EXT_CAP_DSN_SIZEOF 12
583#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40
544 584
545/* Advanced Error Reporting */ 585/* Advanced Error Reporting */
546#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */ 586#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */
547#define PCI_ERR_UNC_TRAIN 0x00000001 /* Training */ 587#define PCI_ERR_UNC_TRAIN 0x00000001 /* Training */
548#define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */ 588#define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */
589#define PCI_ERR_UNC_SURPDN 0x00000020 /* Surprise Down */
549#define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */ 590#define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */
550#define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */ 591#define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */
551#define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */ 592#define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */
@@ -555,6 +596,11 @@
555#define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */ 596#define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */
556#define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */ 597#define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */
557#define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */ 598#define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */
599#define PCI_ERR_UNC_ACSV 0x00200000 /* ACS Violation */
600#define PCI_ERR_UNC_INTN 0x00400000 /* internal error */
601#define PCI_ERR_UNC_MCBTLP 0x00800000 /* MC blocked TLP */
602#define PCI_ERR_UNC_ATOMEG 0x01000000 /* Atomic egress blocked */
603#define PCI_ERR_UNC_TLPPRE 0x02000000 /* TLP prefix blocked */
558#define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */ 604#define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */
559 /* Same bits as above */ 605 /* Same bits as above */
560#define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */ 606#define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */
@@ -565,6 +611,9 @@
565#define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */ 611#define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */
566#define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */ 612#define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */
567#define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */ 613#define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */
614#define PCI_ERR_COR_ADV_NFAT 0x00002000 /* Advisory Non-Fatal */
615#define PCI_ERR_COR_INTERNAL 0x00004000 /* Corrected Internal */
616#define PCI_ERR_COR_LOG_OVER 0x00008000 /* Header Log Overflow */
568#define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */ 617#define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */
569 /* Same bits as above */ 618 /* Same bits as above */
570#define PCI_ERR_CAP 24 /* Advanced Error Capabilities */ 619#define PCI_ERR_CAP 24 /* Advanced Error Capabilities */
@@ -596,12 +645,18 @@
596 645
597/* Virtual Channel */ 646/* Virtual Channel */
598#define PCI_VC_PORT_REG1 4 647#define PCI_VC_PORT_REG1 4
648#define PCI_VC_REG1_EVCC 0x7 /* extended vc count */
599#define PCI_VC_PORT_REG2 8 649#define PCI_VC_PORT_REG2 8
650#define PCI_VC_REG2_32_PHASE 0x2
651#define PCI_VC_REG2_64_PHASE 0x4
652#define PCI_VC_REG2_128_PHASE 0x8
600#define PCI_VC_PORT_CTRL 12 653#define PCI_VC_PORT_CTRL 12
601#define PCI_VC_PORT_STATUS 14 654#define PCI_VC_PORT_STATUS 14
602#define PCI_VC_RES_CAP 16 655#define PCI_VC_RES_CAP 16
603#define PCI_VC_RES_CTRL 20 656#define PCI_VC_RES_CTRL 20
604#define PCI_VC_RES_STATUS 26 657#define PCI_VC_RES_STATUS 26
658#define PCI_CAP_VC_BASE_SIZEOF 0x10
659#define PCI_CAP_VC_PER_VC_SIZEOF 0x0C
605 660
606/* Power Budgeting */ 661/* Power Budgeting */
607#define PCI_PWR_DSR 4 /* Data Select Register */ 662#define PCI_PWR_DSR 4 /* Data Select Register */
@@ -614,6 +669,7 @@
614#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */ 669#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */
615#define PCI_PWR_CAP 12 /* Capability */ 670#define PCI_PWR_CAP 12 /* Capability */
616#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */ 671#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */
672#define PCI_EXT_CAP_PWR_SIZEOF 16
617 673
618/* 674/*
619 * Hypertransport sub capability types 675 * Hypertransport sub capability types
@@ -646,6 +702,8 @@
646#define HT_CAPTYPE_ERROR_RETRY 0xC0 /* Retry on error configuration */ 702#define HT_CAPTYPE_ERROR_RETRY 0xC0 /* Retry on error configuration */
647#define HT_CAPTYPE_GEN3 0xD0 /* Generation 3 hypertransport configuration */ 703#define HT_CAPTYPE_GEN3 0xD0 /* Generation 3 hypertransport configuration */
648#define HT_CAPTYPE_PM 0xE0 /* Hypertransport powermanagement configuration */ 704#define HT_CAPTYPE_PM 0xE0 /* Hypertransport powermanagement configuration */
705#define HT_CAP_SIZEOF_LONG 28 /* slave & primary */
706#define HT_CAP_SIZEOF_SHORT 24 /* host & secondary */
649 707
650/* Alternative Routing-ID Interpretation */ 708/* Alternative Routing-ID Interpretation */
651#define PCI_ARI_CAP 0x04 /* ARI Capability Register */ 709#define PCI_ARI_CAP 0x04 /* ARI Capability Register */
@@ -656,6 +714,7 @@
656#define PCI_ARI_CTRL_MFVC 0x0001 /* MFVC Function Groups Enable */ 714#define PCI_ARI_CTRL_MFVC 0x0001 /* MFVC Function Groups Enable */
657#define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */ 715#define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */
658#define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */ 716#define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */
717#define PCI_EXT_CAP_ARI_SIZEOF 8
659 718
660/* Address Translation Service */ 719/* Address Translation Service */
661#define PCI_ATS_CAP 0x04 /* ATS Capability Register */ 720#define PCI_ATS_CAP 0x04 /* ATS Capability Register */
@@ -665,6 +724,7 @@
665#define PCI_ATS_CTRL_ENABLE 0x8000 /* ATS Enable */ 724#define PCI_ATS_CTRL_ENABLE 0x8000 /* ATS Enable */
666#define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) /* Smallest Translation Unit */ 725#define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) /* Smallest Translation Unit */
667#define PCI_ATS_MIN_STU 12 /* shift of minimum STU block */ 726#define PCI_ATS_MIN_STU 12 /* shift of minimum STU block */
727#define PCI_EXT_CAP_ATS_SIZEOF 8
668 728
669/* Page Request Interface */ 729/* Page Request Interface */
670#define PCI_PRI_CTRL 0x04 /* PRI control register */ 730#define PCI_PRI_CTRL 0x04 /* PRI control register */
@@ -676,6 +736,7 @@
676#define PCI_PRI_STATUS_STOPPED 0x100 /* PRI Stopped */ 736#define PCI_PRI_STATUS_STOPPED 0x100 /* PRI Stopped */
677#define PCI_PRI_MAX_REQ 0x08 /* PRI max reqs supported */ 737#define PCI_PRI_MAX_REQ 0x08 /* PRI max reqs supported */
678#define PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */ 738#define PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */
739#define PCI_EXT_CAP_PRI_SIZEOF 16
679 740
680/* PASID capability */ 741/* PASID capability */
681#define PCI_PASID_CAP 0x04 /* PASID feature register */ 742#define PCI_PASID_CAP 0x04 /* PASID feature register */
@@ -685,6 +746,7 @@
685#define PCI_PASID_CTRL_ENABLE 0x01 /* Enable bit */ 746#define PCI_PASID_CTRL_ENABLE 0x01 /* Enable bit */
686#define PCI_PASID_CTRL_EXEC 0x02 /* Exec permissions Enable */ 747#define PCI_PASID_CTRL_EXEC 0x02 /* Exec permissions Enable */
687#define PCI_PASID_CTRL_PRIV 0x04 /* Priviledge Mode Enable */ 748#define PCI_PASID_CTRL_PRIV 0x04 /* Priviledge Mode Enable */
749#define PCI_EXT_CAP_PASID_SIZEOF 8
688 750
689/* Single Root I/O Virtualization */ 751/* Single Root I/O Virtualization */
690#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ 752#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
@@ -716,12 +778,14 @@
716#define PCI_SRIOV_VFM_MI 0x1 /* Dormant.MigrateIn */ 778#define PCI_SRIOV_VFM_MI 0x1 /* Dormant.MigrateIn */
717#define PCI_SRIOV_VFM_MO 0x2 /* Active.MigrateOut */ 779#define PCI_SRIOV_VFM_MO 0x2 /* Active.MigrateOut */
718#define PCI_SRIOV_VFM_AV 0x3 /* Active.Available */ 780#define PCI_SRIOV_VFM_AV 0x3 /* Active.Available */
781#define PCI_EXT_CAP_SRIOV_SIZEOF 64
719 782
720#define PCI_LTR_MAX_SNOOP_LAT 0x4 783#define PCI_LTR_MAX_SNOOP_LAT 0x4
721#define PCI_LTR_MAX_NOSNOOP_LAT 0x6 784#define PCI_LTR_MAX_NOSNOOP_LAT 0x6
722#define PCI_LTR_VALUE_MASK 0x000003ff 785#define PCI_LTR_VALUE_MASK 0x000003ff
723#define PCI_LTR_SCALE_MASK 0x00001c00 786#define PCI_LTR_SCALE_MASK 0x00001c00
724#define PCI_LTR_SCALE_SHIFT 10 787#define PCI_LTR_SCALE_SHIFT 10
788#define PCI_EXT_CAP_LTR_SIZEOF 8
725 789
726/* Access Control Service */ 790/* Access Control Service */
727#define PCI_ACS_CAP 0x04 /* ACS Capability Register */ 791#define PCI_ACS_CAP 0x04 /* ACS Capability Register */
@@ -732,7 +796,38 @@
732#define PCI_ACS_UF 0x10 /* Upstream Forwarding */ 796#define PCI_ACS_UF 0x10 /* Upstream Forwarding */
733#define PCI_ACS_EC 0x20 /* P2P Egress Control */ 797#define PCI_ACS_EC 0x20 /* P2P Egress Control */
734#define PCI_ACS_DT 0x40 /* Direct Translated P2P */ 798#define PCI_ACS_DT 0x40 /* Direct Translated P2P */
799#define PCI_ACS_EGRESS_BITS 0x05 /* ACS Egress Control Vector Size */
735#define PCI_ACS_CTRL 0x06 /* ACS Control Register */ 800#define PCI_ACS_CTRL 0x06 /* ACS Control Register */
736#define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */ 801#define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */
737 802
803#define PCI_VSEC_HDR 4 /* extended cap - vendor specific */
804#define PCI_VSEC_HDR_LEN_SHIFT 20 /* shift for length field */
805
806/* sata capability */
807#define PCI_SATA_REGS 4 /* SATA REGs specifier */
808#define PCI_SATA_REGS_MASK 0xF /* location - BAR#/inline */
809#define PCI_SATA_REGS_INLINE 0xF /* REGS in config space */
810#define PCI_SATA_SIZEOF_SHORT 8
811#define PCI_SATA_SIZEOF_LONG 16
812
813/* resizable BARs */
814#define PCI_REBAR_CTRL 8 /* control register */
815#define PCI_REBAR_CTRL_NBAR_MASK (7 << 5) /* mask for # bars */
816#define PCI_REBAR_CTRL_NBAR_SHIFT 5 /* shift for # bars */
817
818/* dynamic power allocation */
819#define PCI_DPA_CAP 4 /* capability register */
820#define PCI_DPA_CAP_SUBSTATE_MASK 0x1F /* # substates - 1 */
821#define PCI_DPA_BASE_SIZEOF 16 /* size with 0 substates */
822
823/* TPH Requester */
824#define PCI_TPH_CAP 4 /* capability register */
825#define PCI_TPH_CAP_LOC_MASK 0x600 /* location mask */
826#define PCI_TPH_LOC_NONE 0x000 /* no location */
827#define PCI_TPH_LOC_CAP 0x200 /* in capability */
828#define PCI_TPH_LOC_MSIX 0x400 /* in MSI-X */
829#define PCI_TPH_CAP_ST_MASK 0x07FF0000 /* st table mask */
830#define PCI_TPH_CAP_ST_SHIFT 16 /* st table shift */
831#define PCI_TPH_BASE_SIZEOF 12 /* size with no st table */
832
738#endif /* LINUX_PCI_REGS_H */ 833#endif /* LINUX_PCI_REGS_H */
diff --git a/include/linux/sfi_acpi.h b/include/linux/sfi_acpi.h
index c4a5a8cd4469..631af63af42d 100644
--- a/include/linux/sfi_acpi.h
+++ b/include/linux/sfi_acpi.h
@@ -66,7 +66,7 @@ extern int sfi_acpi_table_parse(char *signature, char *oem_id,
66 char *oem_table_id, 66 char *oem_table_id,
67 int (*handler)(struct acpi_table_header *)); 67 int (*handler)(struct acpi_table_header *));
68 68
69static inline int acpi_sfi_table_parse(char *signature, 69static inline int __init acpi_sfi_table_parse(char *signature,
70 int (*handler)(struct acpi_table_header *)) 70 int (*handler)(struct acpi_table_header *))
71{ 71{
72 if (!acpi_table_parse(signature, handler)) 72 if (!acpi_table_parse(signature, handler))
@@ -83,7 +83,7 @@ static inline int sfi_acpi_table_parse(char *signature, char *oem_id,
83 return -1; 83 return -1;
84} 84}
85 85
86static inline int acpi_sfi_table_parse(char *signature, 86static inline int __init acpi_sfi_table_parse(char *signature,
87 int (*handler)(struct acpi_table_header *)) 87 int (*handler)(struct acpi_table_header *))
88{ 88{
89 return acpi_table_parse(signature, handler); 89 return acpi_table_parse(signature, handler);
diff --git a/kernel/resource.c b/kernel/resource.c
index e1d2b8ee76d5..dc8b47764443 100644
--- a/kernel/resource.c
+++ b/kernel/resource.c
@@ -722,14 +722,12 @@ int adjust_resource(struct resource *res, resource_size_t start, resource_size_t
722 722
723 write_lock(&resource_lock); 723 write_lock(&resource_lock);
724 724
725 if (!parent)
726 goto skip;
727
725 if ((start < parent->start) || (end > parent->end)) 728 if ((start < parent->start) || (end > parent->end))
726 goto out; 729 goto out;
727 730
728 for (tmp = res->child; tmp; tmp = tmp->sibling) {
729 if ((tmp->start < start) || (tmp->end > end))
730 goto out;
731 }
732
733 if (res->sibling && (res->sibling->start <= end)) 731 if (res->sibling && (res->sibling->start <= end))
734 goto out; 732 goto out;
735 733
@@ -741,6 +739,11 @@ int adjust_resource(struct resource *res, resource_size_t start, resource_size_t
741 goto out; 739 goto out;
742 } 740 }
743 741
742skip:
743 for (tmp = res->child; tmp; tmp = tmp->sibling)
744 if ((tmp->start < start) || (tmp->end > end))
745 goto out;
746
744 res->start = start; 747 res->start = start;
745 res->end = end; 748 res->end = end;
746 result = 0; 749 result = 0;
diff --git a/scripts/mod/modpost.c b/scripts/mod/modpost.c
index 0f84bb38eb0d..68e9f5ed0a6f 100644
--- a/scripts/mod/modpost.c
+++ b/scripts/mod/modpost.c
@@ -865,6 +865,11 @@ static void check_section(const char *modname, struct elf_info *elf,
865#define ALL_EXIT_TEXT_SECTIONS \ 865#define ALL_EXIT_TEXT_SECTIONS \
866 ".exit.text$", ".devexit.text$", ".cpuexit.text$", ".memexit.text$" 866 ".exit.text$", ".devexit.text$", ".cpuexit.text$", ".memexit.text$"
867 867
868#define ALL_PCI_INIT_SECTIONS \
869 ".pci_fixup_early$", ".pci_fixup_header$", ".pci_fixup_final$", \
870 ".pci_fixup_enable$", ".pci_fixup_resume$", \
871 ".pci_fixup_resume_early$", ".pci_fixup_suspend$"
872
868#define ALL_XXXINIT_SECTIONS DEV_INIT_SECTIONS, CPU_INIT_SECTIONS, \ 873#define ALL_XXXINIT_SECTIONS DEV_INIT_SECTIONS, CPU_INIT_SECTIONS, \
869 MEM_INIT_SECTIONS 874 MEM_INIT_SECTIONS
870#define ALL_XXXEXIT_SECTIONS DEV_EXIT_SECTIONS, CPU_EXIT_SECTIONS, \ 875#define ALL_XXXEXIT_SECTIONS DEV_EXIT_SECTIONS, CPU_EXIT_SECTIONS, \
@@ -1027,6 +1032,12 @@ const struct sectioncheck sectioncheck[] = {
1027 .mismatch = ANY_EXIT_TO_ANY_INIT, 1032 .mismatch = ANY_EXIT_TO_ANY_INIT,
1028 .symbol_white_list = { DEFAULT_SYMBOL_WHITE_LIST, NULL }, 1033 .symbol_white_list = { DEFAULT_SYMBOL_WHITE_LIST, NULL },
1029}, 1034},
1035{
1036 .fromsec = { ALL_PCI_INIT_SECTIONS, NULL },
1037 .tosec = { INIT_SECTIONS, NULL },
1038 .mismatch = ANY_INIT_TO_ANY_EXIT,
1039 .symbol_white_list = { NULL },
1040},
1030/* Do not export init/exit functions or data */ 1041/* Do not export init/exit functions or data */
1031{ 1042{
1032 .fromsec = { "__ksymtab*", NULL }, 1043 .fromsec = { "__ksymtab*", NULL },
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-23 22:13:48 -0500