diff options
| -rw-r--r-- | drivers/clk/renesas/r8a7745-cpg-mssr.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/renesas/r8a7745-cpg-mssr.c b/drivers/clk/renesas/r8a7745-cpg-mssr.c index 87f5a3619e4f..4b0a9243b748 100644 --- a/drivers/clk/renesas/r8a7745-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7745-cpg-mssr.c | |||
| @@ -51,7 +51,6 @@ static const struct cpg_core_clk r8a7745_core_clks[] __initconst = { | |||
| 51 | DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), | 51 | DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), |
| 52 | 52 | ||
| 53 | /* Core Clock Outputs */ | 53 | /* Core Clock Outputs */ |
| 54 | DEF_BASE("lb", R8A7745_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1), | ||
| 55 | DEF_BASE("sdh", R8A7745_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1), | 54 | DEF_BASE("sdh", R8A7745_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1), |
| 56 | DEF_BASE("sd0", R8A7745_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1), | 55 | DEF_BASE("sd0", R8A7745_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1), |
| 57 | DEF_BASE("qspi", R8A7745_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2), | 56 | DEF_BASE("qspi", R8A7745_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2), |
| @@ -63,6 +62,7 @@ static const struct cpg_core_clk r8a7745_core_clks[] __initconst = { | |||
| 63 | DEF_FIXED("zs", R8A7745_CLK_ZS, CLK_PLL1, 6, 1), | 62 | DEF_FIXED("zs", R8A7745_CLK_ZS, CLK_PLL1, 6, 1), |
| 64 | DEF_FIXED("hp", R8A7745_CLK_HP, CLK_PLL1, 12, 1), | 63 | DEF_FIXED("hp", R8A7745_CLK_HP, CLK_PLL1, 12, 1), |
| 65 | DEF_FIXED("b", R8A7745_CLK_B, CLK_PLL1, 12, 1), | 64 | DEF_FIXED("b", R8A7745_CLK_B, CLK_PLL1, 12, 1), |
| 65 | DEF_FIXED("lb", R8A7745_CLK_LB, CLK_PLL1, 24, 1), | ||
| 66 | DEF_FIXED("p", R8A7745_CLK_P, CLK_PLL1, 24, 1), | 66 | DEF_FIXED("p", R8A7745_CLK_P, CLK_PLL1, 24, 1), |
| 67 | DEF_FIXED("cl", R8A7745_CLK_CL, CLK_PLL1, 48, 1), | 67 | DEF_FIXED("cl", R8A7745_CLK_CL, CLK_PLL1, 48, 1), |
| 68 | DEF_FIXED("cp", R8A7745_CLK_CP, CLK_PLL1, 48, 1), | 68 | DEF_FIXED("cp", R8A7745_CLK_CP, CLK_PLL1, 48, 1), |