2 files changed, 16 insertions, 1 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f11bb213ec07..7720569f2024 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2425,12 +2425,17 @@ enum i915_power_well_id {
 #define _3D_CHICKEN     _MMIO(0x2084)
 #define  _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB      (1 << 10)
 #define _3D_CHICKEN2    _MMIO(0x208c)
+
+#define FF_SLICE_CHICKEN        _MMIO(0x2088)
+#define  FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX       (1 << 1)
+
 /* Disables pipelining of read flushes past the SF-WIZ interface.
  * Required on all Ironlake steppings according to the B-Spec, but the
  * particular danger of not doing so is not specified.
  */
 # define _3D_CHICKEN2_WM_READ_PIPELINED                 (1 << 14)
 #define _3D_CHICKEN3    _MMIO(0x2090)
+#define  _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX            (1 << 12)
 #define  _3D_CHICKEN_SF_DISABLE_OBJEND_CULL             (1 << 10)
 #define  _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE        (1 << 5)
 #define  _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL          (1 << 5)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index f3968580e5e2..7c4c8fb1dae4 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1545,11 +1545,21 @@ static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
         /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */
         batch = gen8_emit_flush_coherentl3_wa(engine, batch);
 
+        *batch++ = MI_LOAD_REGISTER_IMM(3);
+
         /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */
-        *batch++ = MI_LOAD_REGISTER_IMM(1);
         *batch++ = i915_mmio_reg_offset(COMMON_SLICE_CHICKEN2);
         *batch++ = _MASKED_BIT_DISABLE(
                         GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE);
+
+        /* BSpec: 11391 */
+        *batch++ = i915_mmio_reg_offset(FF_SLICE_CHICKEN);
+        *batch++ = _MASKED_BIT_ENABLE(FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX);
+
+        /* BSpec: 11299 */
+        *batch++ = i915_mmio_reg_offset(_3D_CHICKEN3);
+        *batch++ = _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_PROVOKING_VERTEX_FIX);
+
         *batch++ = MI_NOOP;
 
         /* WaClearSlmSpaceAtContextSwitch:kbl */