1717 files changed, 48347 insertions, 23346 deletions

diff --git a/.gitignore b/.gitignore
index 705e09913dc2..1be78fd8163b 100644
--- a/.gitignore
+++ b/.gitignore
@@ -127,3 +127,7 @@ all.config
 
 # Kdevelop4
 *.kdev4
+
+#Automatically generated by ASN.1 compiler
+net/ipv4/netfilter/nf_nat_snmp_basic-asn1.c
+net/ipv4/netfilter/nf_nat_snmp_basic-asn1.h
diff --git a/Documentation/ABI/testing/sysfs-devices-platform-dock b/Documentation/ABI/testing/sysfs-devices-platform-dock
new file mode 100644
index 000000000000..1d8c18f905c7
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-devices-platform-dock
@@ -0,0 +1,39 @@
+What:           /sys/devices/platform/dock.N/docked
+Date:           Dec, 2006
+KernelVersion:  2.6.19
+Contact:        linux-acpi@vger.kernel.org
+Description:
+                (RO) Value 1 or 0 indicates whether the software believes the
+                laptop is docked in a docking station.
+
+What:           /sys/devices/platform/dock.N/undock
+Date:           Dec, 2006
+KernelVersion:  2.6.19
+Contact:        linux-acpi@vger.kernel.org
+Description:
+                (WO) Writing to this file causes the software to initiate an
+                undock request to the firmware.
+
+What:           /sys/devices/platform/dock.N/uid
+Date:           Feb, 2007
+KernelVersion:  v2.6.21
+Contact:        linux-acpi@vger.kernel.org
+Description:
+                (RO) Displays the docking station the laptop is docked to.
+
+What:           /sys/devices/platform/dock.N/flags
+Date:           May, 2007
+KernelVersion:  v2.6.21
+Contact:        linux-acpi@vger.kernel.org
+Description:
+                (RO) Show dock station flags, useful for checking if undock
+                request has been made by the user (from the immediate_undock
+                option).
+
+What:           /sys/devices/platform/dock.N/type
+Date:           Aug, 2008
+KernelVersion:  v2.6.27
+Contact:        linux-acpi@vger.kernel.org
+Description:
+                (RO) Display the dock station type- dock_station, ata_bay or
+                battery_bay.
diff --git a/Documentation/ABI/testing/sysfs-devices-system-cpu b/Documentation/ABI/testing/sysfs-devices-system-cpu
index bfd29bc8d37a..4ed63b6cfb15 100644
--- a/Documentation/ABI/testing/sysfs-devices-system-cpu
+++ b/Documentation/ABI/testing/sysfs-devices-system-cpu
@@ -108,6 +108,8 @@ Description:	CPU topology files that describe a logical CPU's relationship
 
 What:           /sys/devices/system/cpu/cpuidle/current_driver
                 /sys/devices/system/cpu/cpuidle/current_governer_ro
+                /sys/devices/system/cpu/cpuidle/available_governors
+                /sys/devices/system/cpu/cpuidle/current_governor
 Date:           September 2007
 Contact:        Linux kernel mailing list <linux-kernel@vger.kernel.org>
 Description:    Discover cpuidle policy and mechanism
@@ -119,13 +121,84 @@ Description:	Discover cpuidle policy and mechanism
                 Idle policy (governor) is differentiated from idle mechanism
                 (driver)
 
-                current_driver: displays current idle mechanism
+                current_driver: (RO) displays current idle mechanism
 
-                current_governor_ro: displays current idle policy
+                current_governor_ro: (RO) displays current idle policy
+
+                With the cpuidle_sysfs_switch boot option enabled (meant for
+                developer testing), the following three attributes are visible
+                instead:
+
+                current_driver: same as described above
+
+                available_governors: (RO) displays a space separated list of
+                available governors
+
+                current_governor: (RW) displays current idle policy. Users can
+                switch the governor at runtime by writing to this file.
 
                 See files in Documentation/cpuidle/ for more information.
 
 
+What:           /sys/devices/system/cpu/cpuX/cpuidle/stateN/name
+                /sys/devices/system/cpu/cpuX/cpuidle/stateN/latency
+                /sys/devices/system/cpu/cpuX/cpuidle/stateN/power
+                /sys/devices/system/cpu/cpuX/cpuidle/stateN/time
+                /sys/devices/system/cpu/cpuX/cpuidle/stateN/usage
+Date:           September 2007
+KernelVersion:  v2.6.24
+Contact:        Linux power management list <linux-pm@vger.kernel.org>
+Description:
+                The directory /sys/devices/system/cpu/cpuX/cpuidle contains per
+                logical CPU specific cpuidle information for each online cpu X.
+                The processor idle states which are available for use have the
+                following attributes:
+
+                name: (RO) Name of the idle state (string).
+
+                latency: (RO) The latency to exit out of this idle state (in
+                microseconds).
+
+                power: (RO) The power consumed while in this idle state (in
+                milliwatts).
+
+                time: (RO) The total time spent in this idle state (in microseconds).
+
+                usage: (RO) Number of times this state was entered (a count).
+
+
+What:           /sys/devices/system/cpu/cpuX/cpuidle/stateN/desc
+Date:           February 2008
+KernelVersion:  v2.6.25
+Contact:        Linux power management list <linux-pm@vger.kernel.org>
+Description:
+                (RO) A small description about the idle state (string).
+
+
+What:           /sys/devices/system/cpu/cpuX/cpuidle/stateN/disable
+Date:           March 2012
+KernelVersion:  v3.10
+Contact:        Linux power management list <linux-pm@vger.kernel.org>
+Description:
+                (RW) Option to disable this idle state (bool). The behavior and
+                the effect of the disable variable depends on the implementation
+                of a particular governor. In the ladder governor, for example,
+                it is not coherent, i.e. if one is disabling a light state, then
+                all deeper states are disabled as well, but the disable variable
+                does not reflect it. Likewise, if one enables a deep state but a
+                lighter state still is disabled, then this has no effect.
+
+
+What:           /sys/devices/system/cpu/cpuX/cpuidle/stateN/residency
+Date:           March 2014
+KernelVersion:  v3.15
+Contact:        Linux power management list <linux-pm@vger.kernel.org>
+Description:
+                (RO) Display the target residency i.e. the minimum amount of
+                time (in microseconds) this cpu should spend in this idle state
+                to make the transition worth the effort.
+
+
 What:           /sys/devices/system/cpu/cpu#/cpufreq/*
 Date:           pre-git history
 Contact:        linux-pm@vger.kernel.org
diff --git a/Documentation/ABI/testing/sysfs-platform-dptf b/Documentation/ABI/testing/sysfs-platform-dptf
new file mode 100644
index 000000000000..325dc0667dbb
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-platform-dptf
@@ -0,0 +1,40 @@
+What:           /sys/bus/platform/devices/INT3407:00/dptf_power/charger_type
+Date:           Jul, 2016
+KernelVersion:  v4.10
+Contact:        linux-acpi@vger.kernel.org
+Description:
+                (RO) The charger type - Traditional, Hybrid or NVDC.
+
+What:           /sys/bus/platform/devices/INT3407:00/dptf_power/adapter_rating_mw
+Date:           Jul, 2016
+KernelVersion:  v4.10
+Contact:        linux-acpi@vger.kernel.org
+Description:
+                (RO) Adapter rating in milliwatts (the maximum Adapter power).
+                Must be 0 if no AC Adaptor is plugged in.
+
+What:           /sys/bus/platform/devices/INT3407:00/dptf_power/max_platform_power_mw
+Date:           Jul, 2016
+KernelVersion:  v4.10
+Contact:        linux-acpi@vger.kernel.org
+Description:
+                (RO) Maximum platform power that can be supported by the battery
+                in milliwatts.
+
+What:           /sys/bus/platform/devices/INT3407:00/dptf_power/platform_power_source
+Date:           Jul, 2016
+KernelVersion:  v4.10
+Contact:        linux-acpi@vger.kernel.org
+Description:
+                (RO) Display the platform power source
+                0x00 = DC
+                0x01 = AC
+                0x02 = USB
+                0x03 = Wireless Charger
+
+What:           /sys/bus/platform/devices/INT3407:00/dptf_power/battery_steady_power
+Date:           Jul, 2016
+KernelVersion:  v4.10
+Contact:        linux-acpi@vger.kernel.org
+Description:
+                (RO) The maximum sustained power for battery in milliwatts.
diff --git a/Documentation/PCI/pci.txt b/Documentation/PCI/pci.txt
index 611a75e4366e..badb26ac33dc 100644
--- a/Documentation/PCI/pci.txt
+++ b/Documentation/PCI/pci.txt
@@ -570,7 +570,9 @@ your driver if they're helpful, or just use plain hex constants.
 The device IDs are arbitrary hex numbers (vendor controlled) and normally used
 only in a single location, the pci_device_id table.
 
-Please DO submit new vendor/device IDs to http://pciids.sourceforge.net/.
+Please DO submit new vendor/device IDs to http://pci-ids.ucw.cz/.
+There are mirrors of the pci.ids file at http://pciids.sourceforge.net/
+and https://github.com/pciutils/pciids.
 
 
 
diff --git a/Documentation/atomic_bitops.txt b/Documentation/atomic_bitops.txt
index 5550bfdcce5f..be70b32c95d9 100644
--- a/Documentation/atomic_bitops.txt
+++ b/Documentation/atomic_bitops.txt
@@ -58,7 +58,12 @@ Like with atomic_t, the rule of thumb is:
 
  - RMW operations that have a return value are fully ordered.
 
-Except for test_and_set_bit_lock() which has ACQUIRE semantics and
+ - RMW operations that are conditional are unordered on FAILURE,
+   otherwise the above rules apply. In the case of test_and_{}_bit() operations,
+   if the bit in memory is unchanged by the operation then it is deemed to have
+   failed.
+
+Except for a successful test_and_set_bit_lock() which has ACQUIRE semantics and
 clear_bit_unlock() which has RELEASE semantics.
 
 Since a platform only has a single means of achieving atomic operations
diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm750-smp b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm750-smp
new file mode 100644
index 000000000000..8e043301e28e
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm750-smp
@@ -0,0 +1,42 @@
+=========================================================
+Secondary CPU enable-method "nuvoton,npcm750-smp" binding
+=========================================================
+
+To apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be
+defined in the "cpus" node.
+
+Enable method name:     "nuvoton,npcm750-smp"
+Compatible machines:    "nuvoton,npcm750"
+Compatible CPUs:        "arm,cortex-a9"
+Related properties:     (none)
+
+Note:
+This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
+"nuvoton,npcm750-gcr".
+
+Example:
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                enable-method = "nuvoton,npcm750-smp";
+
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        clocks = <&clk NPCM7XX_CLK_CPU>;
+                        clock-names = "clk_cpu";
+                        reg = <0>;
+                        next-level-cache = <&L2>;
+                };
+
+                cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        clocks = <&clk NPCM7XX_CLK_CPU>;
+                        clock-names = "clk_cpu";
+                        reg = <1>;
+                        next-level-cache = <&L2>;
+                };
+        };
+
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index f4a777039f03..8b0328ff951d 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -185,6 +185,7 @@ described below.
                             "nvidia,tegra186-denver"
                             "qcom,krait"
                             "qcom,kryo"
+                            "qcom,kryo385"
                             "qcom,scorpion"
         - enable-method
                 Value type: <stringlist>
diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt
index 91d517849483..7d21ab37c19c 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek.txt
@@ -50,6 +50,15 @@ Supported boards:
 - Reference board variant 1 for MT7622:
     Required root node properties:
       - compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
+- Reference board for MT7623a with eMMC:
+    Required root node properties:
+      - compatible = "mediatek,mt7623a-rfb-emmc", "mediatek,mt7623";
+- Reference board for MT7623a with NAND:
+    Required root node properties:
+      - compatible = "mediatek,mt7623a-rfb-nand", "mediatek,mt7623";
+- Reference board for MT7623n with eMMC:
+    Required root node properties:
+      - compatible = "mediatek,mt7623n-rfb-emmc", "mediatek,mt7623";
 - Reference  board for MT7623n with NAND:
     Required root node properties:
       - compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623";
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
index 6cc7840ff37a..8f5335b480ac 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
@@ -9,6 +9,7 @@ Required Properties:
         - "mediatek,mt2701-ethsys", "syscon"
         - "mediatek,mt7622-ethsys", "syscon"
 - #clock-cells: Must be 1
+- #reset-cells: Must be 1
 
 The ethsys controller uses the common clk binding from
 Documentation/devicetree/bindings/clock/clock-bindings.txt
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
index d5d5f1227665..7fe5dc6097a6 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
@@ -8,6 +8,7 @@ Required Properties:
 - compatible: Should be:
         - "mediatek,mt7622-pciesys", "syscon"
 - #clock-cells: Must be 1
+- #reset-cells: Must be 1
 
 The PCIESYS controller uses the common clk binding from
 Documentation/devicetree/bindings/clock/clock-bindings.txt
@@ -19,4 +20,5 @@ pciesys: pciesys@1a100800 {
         compatible = "mediatek,mt7622-pciesys", "syscon";
         reg = <0 0x1a100800 0 0x1000>;
         #clock-cells = <1>;
+        #reset-cells = <1>;
 };
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
index 00760019da00..b8184da2508c 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
@@ -8,6 +8,7 @@ Required Properties:
 - compatible: Should be:
         - "mediatek,mt7622-ssusbsys", "syscon"
 - #clock-cells: Must be 1
+- #reset-cells: Must be 1
 
 The SSUSBSYS controller uses the common clk binding from
 Documentation/devicetree/bindings/clock/clock-bindings.txt
@@ -19,4 +20,5 @@ ssusbsys: ssusbsys@1a000000 {
         compatible = "mediatek,mt7622-ssusbsys", "syscon";
         reg = <0 0x1a000000 0 0x1000>;
         #clock-cells = <1>;
+        #reset-cells = <1>;
 };
diff --git a/Documentation/devicetree/bindings/arm/npcm/npcm.txt b/Documentation/devicetree/bindings/arm/npcm/npcm.txt
new file mode 100644
index 000000000000..2d87d9ecea85
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/npcm/npcm.txt
@@ -0,0 +1,6 @@
+NPCM Platforms Device Tree Bindings
+-----------------------------------
+NPCM750 SoC
+Required root node properties:
+        - compatible = "nuvoton,npcm750";
+
diff --git a/Documentation/devicetree/bindings/arm/omap/ctrl.txt b/Documentation/devicetree/bindings/arm/omap/ctrl.txt
index ce8dabf8c0f9..f35b77920786 100644
--- a/Documentation/devicetree/bindings/arm/omap/ctrl.txt
+++ b/Documentation/devicetree/bindings/arm/omap/ctrl.txt
@@ -25,6 +25,7 @@ Required properties:
                 "ti,omap4-scm-padconf-wkup"
                 "ti,omap5-scm-core"
                 "ti,omap5-scm-padconf-core"
+                "ti,omap5-scm-wkup-pad-conf"
                 "ti,dra7-scm-core"
 - reg:          Contains Control Module register address range
                 (base address and length)
diff --git a/Documentation/devicetree/bindings/arm/qcom.txt b/Documentation/devicetree/bindings/arm/qcom.txt
index 0ed4d39d7fe1..ee532e705d6c 100644
--- a/Documentation/devicetree/bindings/arm/qcom.txt
+++ b/Documentation/devicetree/bindings/arm/qcom.txt
@@ -26,6 +26,7 @@ The 'SoC' element must be one of the following strings:
         msm8996
         mdm9615
         ipq8074
+        sdm845
 
 The 'board' element must be one of the following strings:
 
diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
index 469ac98ecf8f..14510b215480 100644
--- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
@@ -9,7 +9,11 @@ Required root node properties:
         - "samsung,smdkv310"    - for Exynos4210-based Samsung SMDKV310 eval board.
         - "samsung,trats"       - for Exynos4210-based Tizen Reference board.
         - "samsung,universal_c210" - for Exynos4210-based Samsung board.
+        - "samsung,i9300"          - for Exynos4412-based Samsung GT-I9300 board.
+        - "samsung,i9305"          - for Exynos4412-based Samsung GT-I9305 board.
+        - "samsung,midas"       - for Exynos4412-based Samsung Midas board.
         - "samsung,smdk4412",   - for Exynos4412-based Samsung SMDK4412 eval board.
+        - "samsung,n710x"          - for Exynos4412-based Samsung GT-N7100/GT-N7105 board.
         - "samsung,trats2"      - for Exynos4412-based Tizen Reference board.
         - "samsung,smdk5250"    - for Exynos5250-based Samsung SMDK5250 eval board.
         - "samsung,xyref5260"   - for Exynos5260-based Samsung board.
diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index 5c3af7ef0761..d3d1df97834f 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -39,8 +39,12 @@ SoCs:
     compatible = "renesas,r8a7795"
   - R-Car M3-W (R8A77960)
     compatible = "renesas,r8a7796"
+  - R-Car M3-N (R8A77965)
+    compatible = "renesas,r8a77965"
   - R-Car V3M (R8A77970)
     compatible = "renesas,r8a77970"
+  - R-Car V3H (R8A77980)
+    compatible = "renesas,r8a77980"
   - R-Car D3 (R8A77995)
     compatible = "renesas,r8a77995"
 
@@ -52,11 +56,13 @@ Boards:
   - APE6-EVM
     compatible = "renesas,ape6evm", "renesas,r8a73a4"
   - Atmark Techno Armadillo-800 EVA
-    compatible = "renesas,armadillo800eva"
+    compatible = "renesas,armadillo800eva", "renesas,r8a7740"
   - Blanche (RTP0RC7792SEB00010S)
     compatible = "renesas,blanche", "renesas,r8a7792"
   - BOCK-W
     compatible = "renesas,bockw", "renesas,r8a7778"
+  - Condor (RTP0RC77980SEB0010SS/RTP0RC77980SEB0010SA01)
+    compatible = "renesas,condor", "renesas,r8a77980"
   - Draak (RTP0RC77995SEB0010S)
     compatible = "renesas,draak", "renesas,r8a77995"
   - Eagle (RTP0RC77970SEB0010S)
@@ -102,19 +108,25 @@ Boards:
     compatible = "renesas,salvator-x", "renesas,r8a7795"
   - Salvator-X (RTP0RC7796SIPB0011S)
     compatible = "renesas,salvator-x", "renesas,r8a7796"
+  - Salvator-X (RTP0RC7796SIPB0011S (M3N))
+    compatible = "renesas,salvator-x", "renesas,r8a77965"
   - Salvator-XS (Salvator-X 2nd version, RTP0RC7795SIPB0012S)
     compatible = "renesas,salvator-xs", "renesas,r8a7795"
   - Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012S)
     compatible = "renesas,salvator-xs", "renesas,r8a7796"
+  - Salvator-XS (Salvator-X 2nd version, RTP0RC77965SIPB012S)
+    compatible = "renesas,salvator-xs", "renesas,r8a77965"
   - SILK (RTP0RC7794LCB00011S)
     compatible = "renesas,silk", "renesas,r8a7794"
   - SK-RZG1E (YR8A77450S000BE)
     compatible = "renesas,sk-rzg1e", "renesas,r8a7745"
   - SK-RZG1M (YR8A77430S000BE)
     compatible = "renesas,sk-rzg1m", "renesas,r8a7743"
-  - V3MSK
+  - Stout (ADAS Starterkit, Y-R-CAR-ADAS-SKH2-BOARD)
+    compatible = "renesas,stout", "renesas,r8a7790"
+  - V3MSK (Y-ASK-RCAR-V3M-WS10)
     compatible = "renesas,v3msk", "renesas,r8a77970"
-  - Wheat
+  - Wheat (RTP0RC7792ASKB0000JE)
     compatible = "renesas,wheat", "renesas,r8a7792"
 
 
diff --git a/Documentation/devicetree/bindings/arm/stm32.txt b/Documentation/devicetree/bindings/arm/stm32.txt
index 05762b08a7bb..6808ed9ddfd5 100644
--- a/Documentation/devicetree/bindings/arm/stm32.txt
+++ b/Documentation/devicetree/bindings/arm/stm32.txt
@@ -7,3 +7,4 @@ using one of the following compatible strings:
   st,stm32f469
   st,stm32f746
   st,stm32h743
+  st,stm32mp157
diff --git a/Documentation/devicetree/bindings/arm/tegra.txt b/Documentation/devicetree/bindings/arm/tegra.txt
index 7f1411bbabf7..32f62bb7006d 100644
--- a/Documentation/devicetree/bindings/arm/tegra.txt
+++ b/Documentation/devicetree/bindings/arm/tegra.txt
@@ -9,6 +9,12 @@ following compatible values:
 
   nvidia,tegra20
   nvidia,tegra30
+  nvidia,tegra114
+  nvidia,tegra124
+  nvidia,tegra132
+  nvidia,tegra210
+  nvidia,tegra186
+  nvidia,tegra194
 
 Boards
 -------------------------------------------
@@ -26,8 +32,18 @@ board-specific compatible values:
   nvidia,cardhu
   nvidia,cardhu-a02
   nvidia,cardhu-a04
+  nvidia,dalmore
   nvidia,harmony
+  nvidia,jetson-tk1
+  nvidia,norrin
+  nvidia,p2371-0000
+  nvidia,p2371-2180
+  nvidia,p2571
+  nvidia,p2771-0000
+  nvidia,p2972-0000
+  nvidia,roth
   nvidia,seaboard
+  nvidia,tn7
   nvidia,ventana
   toradex,apalis_t30
   toradex,apalis_t30-eval
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt
index 078a58b0302f..5a3bf7c5a7a0 100644
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt
@@ -3,6 +3,7 @@ NVIDIA Tegra Power Management Controller (PMC)
 Required properties:
 - compatible: Should contain one of the following:
   - "nvidia,tegra186-pmc": for Tegra186
+  - "nvidia,tegra194-pmc": for Tegra194
 - reg: Must contain an (offset, length) pair of the register set for each
   entry in reg-names.
 - reg-names: Must include the following entries:
@@ -10,6 +11,7 @@ Required properties:
   - "wake"
   - "aotag"
   - "scratch"
+  - "misc" (Only for Tegra194)
 
 Optional properties:
 - nvidia,invert-interrupt: If present, inverts the PMU interrupt signal.
diff --git a/Documentation/devicetree/bindings/arm/xilinx.txt b/Documentation/devicetree/bindings/arm/xilinx.txt
index 1f7995357888..b9043bc35c14 100644
--- a/Documentation/devicetree/bindings/arm/xilinx.txt
+++ b/Documentation/devicetree/bindings/arm/xilinx.txt
@@ -5,3 +5,59 @@ shall have the following properties.
 
 Required root node properties:
     - compatible = "xlnx,zynq-7000";
+
+Additional compatible strings:
+
+- Xilinx internal board cc108
+  "xlnx,zynq-cc108"
+
+- Xilinx internal board zc770 with different FMC cards
+  "xlnx,zynq-zc770-xm010"
+  "xlnx,zynq-zc770-xm011"
+  "xlnx,zynq-zc770-xm012"
+  "xlnx,zynq-zc770-xm013"
+
+- Digilent Zybo Z7 board
+  "digilent,zynq-zybo-z7"
+
+---------------------------------------------------------------
+
+Xilinx Zynq UltraScale+ MPSoC Platforms Device Tree Bindings
+
+Boards with ZynqMP SOC based on an ARM Cortex A53 processor
+shall have the following properties.
+
+Required root node properties:
+    - compatible = "xlnx,zynqmp";
+
+
+Additional compatible strings:
+
+- Xilinx internal board zc1232
+  "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232"
+
+- Xilinx internal board zc1254
+  "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254"
+
+- Xilinx internal board zc1275
+  "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275"
+
+- Xilinx internal board zc1751
+  "xlnx,zynqmp-zc1751"
+
+- Xilinx 96boards compatible board zcu100
+  "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100"
+
+- Xilinx evaluation board zcu102
+  "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102"
+  "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102"
+  "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102"
+
+- Xilinx evaluation board zcu104
+  "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104"
+
+- Xilinx evaluation board zcu106
+  "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106"
+
+- Xilinx evaluation board zcu111
+  "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111"
diff --git a/Documentation/devicetree/bindings/misc/arm-charlcd.txt b/Documentation/devicetree/bindings/auxdisplay/arm-charlcd.txt
index e28e2aac47f1..e28e2aac47f1 100644
--- a/Documentation/devicetree/bindings/misc/arm-charlcd.txt
+++ b/Documentation/devicetree/bindings/auxdisplay/arm-charlcd.txt
diff --git a/Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt b/Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt
index 3e21eb822811..c1e70621799b 100644
--- a/Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt
+++ b/Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt
@@ -73,7 +73,7 @@ Example with two SJA1000 CAN controllers connected to the GMI bus. We wrap the
 controllers with a simple-bus node since they are all connected to the same
 chip-select (CS4), in this example external address decoding is provided:
 
-gmi@70090000 {
+gmi@70009000 {
         compatible = "nvidia,tegra20-gmi";
         reg = <0x70009000 0x1000>;
         #address-cells = <2>;
@@ -84,7 +84,6 @@ gmi@70090000 {
         reset-names = "gmi";
         ranges = <4 0 0xd0000000 0xfffffff>;
 
-
         bus@4,0 {
                 compatible = "simple-bus";
                 #address-cells = <1>;
@@ -109,7 +108,7 @@ gmi@70090000 {
 Example with one SJA1000 CAN controller connected to the GMI bus
 on CS4:
 
-gmi@70090000 {
+gmi@70009000 {
         compatible = "nvidia,tegra20-gmi";
         reg = <0x70009000 0x1000>;
         #address-cells = <2>;
@@ -120,7 +119,6 @@ gmi@70090000 {
         reset-names = "gmi";
         ranges = <4 0 0xd0000000 0xfffffff>;
 
-
         can@4,0 {
                 reg = <4 0 0x100>;
                 nvidia,snor-mux-mode;
diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt
index 76aec8a3724d..3c1f3a229eab 100644
--- a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt
+++ b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt
@@ -415,12 +415,27 @@ Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
         value type: <u32>
         Definition: LP register offset. default it is 0x34.
 
+   - clocks
+      Usage: optional, required if SNVS LP RTC requires explicit
+          enablement of clocks
+      Value type: <prop_encoded-array>
+      Definition:  a clock specifier describing the clock required for
+          enabling and disabling SNVS LP RTC.
+
+   - clock-names
+      Usage: optional, required if SNVS LP RTC requires explicit
+          enablement of clocks
+      Value type: <string>
+      Definition: clock name string should be "snvs-rtc".
+
 EXAMPLE
         sec_mon_rtc_lp@1 {
                 compatible = "fsl,sec-v4.0-mon-rtc-lp";
                 interrupts = <93 2>;
                 regmap = <&snvs>;
                 offset = <0x34>;
+                clocks = <&clks IMX7D_SNVS_CLK>;
+                clock-names = "snvs-rtc";
         };
 
 =====================================================================
@@ -543,6 +558,8 @@ FULL EXAMPLE
                         regmap = <&sec_mon>;
                         offset = <0x34>;
                         interrupts = <93 2>;
+                        clocks = <&clks IMX7D_SNVS_CLK>;
+                        clock-names = "snvs-rtc";
                 };
 
                 snvs-pwrkey@020cc000 {
diff --git a/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt b/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt
index baf9b34d20bf..b6a8cc0978cd 100644
--- a/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt
+++ b/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt
@@ -74,8 +74,8 @@ Example:
 
 bcm2835_i2s: i2s@7e203000 {
         compatible = "brcm,bcm2835-i2s";
-        reg = < 0x7e203000 0x20>,
-              < 0x7e101098 0x02>;
+        reg = < 0x7e203000 0x24>;
+        clocks = <&clocks BCM2835_CLOCK_PCM>;
 
         dmas = <&dma 2>,
                <&dma 3>;
diff --git a/Documentation/devicetree/bindings/eeprom/at24.txt b/Documentation/devicetree/bindings/eeprom/at24.txt
index 1812c848e369..abfae1beca2b 100644
--- a/Documentation/devicetree/bindings/eeprom/at24.txt
+++ b/Documentation/devicetree/bindings/eeprom/at24.txt
@@ -38,9 +38,9 @@ Required properties:
 
                 "catalyst",
                 "microchip",
+                "nxp",
                 "ramtron",
                 "renesas",
-                "nxp",
                 "st",
 
                 Some vendors use different model names for chips which are just
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
index ad876548ab5d..c1f65d1dac1d 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
@@ -10,6 +10,7 @@ Required properties:
     * And, optionally, one of the vendor specific compatible:
       + allwinner,sun4i-a10-mali
       + allwinner,sun7i-a20-mali
+      + allwinner,sun8i-h3-mali
       + allwinner,sun50i-h5-mali
       + amlogic,meson-gxbb-mali
       + amlogic,meson-gxl-mali
diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt
index 33c9a10fdc91..20f121daa910 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt
@@ -14,6 +14,7 @@ Required properties:
     - "renesas,irqc-r8a7794" (R-Car E2)
     - "renesas,intc-ex-r8a7795" (R-Car H3)
     - "renesas,intc-ex-r8a7796" (R-Car M3-W)
+    - "renesas,intc-ex-r8a77965" (R-Car M3-N)
     - "renesas,intc-ex-r8a77970" (R-Car V3M)
     - "renesas,intc-ex-r8a77995" (R-Car D3)
 - #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in
diff --git a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
index 621b41c79faa..44d71469c914 100644
--- a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
@@ -3,7 +3,9 @@
 EMIF - External Memory Interface - is an SDRAM controller used in
 TI SoCs. EMIF supports, based on the IP revision, one or more of
 DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
-of the EMIF IP and memory parts attached to it.
+of the EMIF IP and memory parts attached to it. Certain revisions
+of the EMIF controller also contain optional ECC support, which
+corrects one bit errors and detects two bit errors.
 
 Required properties:
 - compatible    : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
@@ -11,6 +13,8 @@ Required properties:
   compatible should be one of the following:
              "ti,emif-am3352"
              "ti,emif-am4372"
+             "ti,emif-dra7xx"
+             "ti,emif-keystone"
 
 - phy-type      : <u32> indicating the DDR phy type. Following are the
   allowed values
@@ -22,6 +26,7 @@ Required properties:
 - ti,hwmods     : For TI hwmods processing and omap device creation
   the value shall be "emif<n>" where <n> is the number of the EMIF
   instance with base 1.
+- interrupts    : interrupt used by the controller
 
 Required only for "ti,emif-am3352" and "ti,emif-am4372":
 - sram                  : Phandles for generic sram driver nodes,
@@ -71,3 +76,9 @@ emif: emif@4c000000 {
         sram = <&pm_sram_code
                 &pm_sram_data>;
 };
+
+emif1: emif@4c000000 {
+        compatible = "ti,emif-dra7xx";
+        reg = <0x4c000000 0x200>;
+        interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+};
diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt b/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt
index a9aa79fb90ed..1aa6f2674af5 100644
--- a/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt
@@ -21,7 +21,9 @@ Required properties :
    - timer: The timeout clock (clk_m). Present if phy_type == utmi.
    - utmi-pads: The clock needed to access the UTMI pad control registers.
      Present if phy_type == utmi.
-   - ulpi-link: The clock Tegra provides to the ULPI PHY (cdev2).
+   - ulpi-link: The clock Tegra provides to the ULPI PHY (usually pad DAP_MCLK2
+     with pad group aka "nvidia,pins" cdev2 and pin mux option config aka
+     "nvidia,function" pllp_out4).
      Present if phy_type == ulpi, and ULPI link mode is in use.
  - resets : Must contain an entry for each entry in reset-names.
    See ../reset/reset.txt for details.
diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
index 2c46f30b62c5..9a06e1fdbc42 100644
--- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
@@ -11,6 +11,7 @@ Required properies:
    "st,stm32f429-pinctrl"
    "st,stm32f469-pinctrl"
    "st,stm32f746-pinctrl"
+   "st,stm32f769-pinctrl"
    "st,stm32h743-pinctrl"
    "st,stm32mp157-pinctrl"
    "st,stm32mp157-z-pinctrl"
diff --git a/Documentation/devicetree/bindings/power/mti,mips-cpc.txt b/Documentation/devicetree/bindings/power/mti,mips-cpc.txt
new file mode 100644
index 000000000000..c6b82511ae8a
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/mti,mips-cpc.txt
@@ -0,0 +1,8 @@
+Binding for MIPS Cluster Power Controller (CPC).
+
+This binding allows a system to specify where the CPC registers are
+located.
+
+Required properties:
+compatible : Should be "mti,mips-cpc".
+regs: Should describe the address & size of the CPC register region.
diff --git a/Documentation/devicetree/bindings/power/wakeup-source.txt b/Documentation/devicetree/bindings/power/wakeup-source.txt
index 3c81f78b5c27..5d254ab13ebf 100644
--- a/Documentation/devicetree/bindings/power/wakeup-source.txt
+++ b/Documentation/devicetree/bindings/power/wakeup-source.txt
@@ -60,7 +60,7 @@ Examples
                 #size-cells = <0>;
 
                 button@1 {
-                        debounce_interval = <50>;
+                        debounce-interval = <50>;
                         wakeup-source;
                         linux,code = <116>;
                         label = "POWER";
diff --git a/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt b/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt
index 65783de0aedf..7bb0362828ec 100644
--- a/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt
@@ -2,9 +2,8 @@
 
 Required properties:
 - compatible: "brcm,bcm2835-i2s"
-- reg: A list of base address and size entries:
-        * The first entry should cover the PCM registers
-        * The second entry should cover the PCM clock registers
+- reg: Should contain PCM registers location and length.
+- clocks: the (PCM) clock to use
 - dmas: List of DMA controller phandle and DMA request line ordered pairs.
 - dma-names: Identifier string for each DMA request line in the dmas property.
   These strings correspond 1:1 with the ordered pairs in dmas.
@@ -16,8 +15,8 @@ Example:
 
 bcm2835_i2s: i2s@7e203000 {
         compatible = "brcm,bcm2835-i2s";
-        reg = <0x7e203000 0x20>,
-              <0x7e101098 0x02>;
+        reg = <0x7e203000 0x24>;
+        clocks = <&clocks BCM2835_CLOCK_PCM>;
 
         dmas = <&dma 2>,
                <&dma 3>;
diff --git a/Documentation/devicetree/bindings/thermal/imx-thermal.txt b/Documentation/devicetree/bindings/thermal/imx-thermal.txt
index 28be51afdb6a..379eb763073e 100644
--- a/Documentation/devicetree/bindings/thermal/imx-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/imx-thermal.txt
@@ -22,7 +22,32 @@ Optional properties:
 - clocks : thermal sensor's clock source.
 
 Example:
+ocotp: ocotp@21bc000 {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "fsl,imx6sx-ocotp", "syscon";
+        reg = <0x021bc000 0x4000>;
+        clocks = <&clks IMX6SX_CLK_OCOTP>;
 
+        tempmon_calib: calib@38 {
+                reg = <0x38 4>;
+        };
+
+        tempmon_temp_grade: temp-grade@20 {
+                reg = <0x20 4>;
+        };
+};
+
+tempmon: tempmon {
+        compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
+        interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+        fsl,tempmon = <&anatop>;
+        nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
+        nvmem-cell-names = "calib", "temp_grade";
+        clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
+};
+
+Legacy method (Deprecated):
 tempmon {
         compatible = "fsl,imx6q-tempmon";
         fsl,tempmon = <&anatop>;
diff --git a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
index 62dd5baad70e..04fc368d828f 100644
--- a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
@@ -2,8 +2,10 @@ Allwinner SoCs Watchdog timer
 
 Required properties:
 
-- compatible : should be either "allwinner,sun4i-a10-wdt" or
-               "allwinner,sun6i-a31-wdt"
+- compatible : should be one of
+        "allwinner,sun4i-a10-wdt"
+        "allwinner,sun6i-a31-wdt"
+        "allwinner,sun50i-a64-wdt","allwinner,sun6i-a31-wdt"
 - reg : Specifies base physical address and size of the registers.
 
 Example:
diff --git a/Documentation/features/sched/membarrier-sync-core/arch-support.txt b/Documentation/features/sched/membarrier-sync-core/arch-support.txt
new file mode 100644
index 000000000000..2c815a7f1ba7
--- /dev/null
+++ b/Documentation/features/sched/membarrier-sync-core/arch-support.txt
@@ -0,0 +1,62 @@
+#
+# Feature name:          membarrier-sync-core
+#         Kconfig:       ARCH_HAS_MEMBARRIER_SYNC_CORE
+#         description:   arch supports core serializing membarrier
+#
+# Architecture requirements
+#
+# * arm64
+#
+# Rely on eret context synchronization when returning from IPI handler, and
+# when returning to user-space.
+#
+# * x86
+#
+# x86-32 uses IRET as return from interrupt, which takes care of the IPI.
+# However, it uses both IRET and SYSEXIT to go back to user-space. The IRET
+# instruction is core serializing, but not SYSEXIT.
+#
+# x86-64 uses IRET as return from interrupt, which takes care of the IPI.
+# However, it can return to user-space through either SYSRETL (compat code),
+# SYSRETQ, or IRET.
+#
+# Given that neither SYSRET{L,Q}, nor SYSEXIT, are core serializing, we rely
+# instead on write_cr3() performed by switch_mm() to provide core serialization
+# after changing the current mm, and deal with the special case of kthread ->
+# uthread (temporarily keeping current mm into active_mm) by issuing a
+# sync_core_before_usermode() in that specific case.
+#
+    -----------------------
+    |         arch |status|
+    -----------------------
+    |       alpha: | TODO |
+    |         arc: | TODO |
+    |         arm: | TODO |
+    |       arm64: |  ok  |
+    |    blackfin: | TODO |
+    |         c6x: | TODO |
+    |        cris: | TODO |
+    |         frv: | TODO |
+    |       h8300: | TODO |
+    |     hexagon: | TODO |
+    |        ia64: | TODO |
+    |        m32r: | TODO |
+    |        m68k: | TODO |
+    |       metag: | TODO |
+    |  microblaze: | TODO |
+    |        mips: | TODO |
+    |     mn10300: | TODO |
+    |       nios2: | TODO |
+    |    openrisc: | TODO |
+    |      parisc: | TODO |
+    |     powerpc: | TODO |
+    |        s390: | TODO |
+    |       score: | TODO |
+    |          sh: | TODO |
+    |       sparc: | TODO |
+    |        tile: | TODO |
+    |          um: | TODO |
+    |   unicore32: | TODO |
+    |         x86: |  ok  |
+    |      xtensa: | TODO |
+    -----------------------
diff --git a/Documentation/gpu/tve200.rst b/Documentation/gpu/tve200.rst
index 69b17b324e12..152ea9398f7e 100644
--- a/Documentation/gpu/tve200.rst
+++ b/Documentation/gpu/tve200.rst
@@ -3,4 +3,4 @@
 ==================================
 
 .. kernel-doc:: drivers/gpu/drm/tve200/tve200_drv.c
-   :doc: Faraday TV Encoder 200
+   :doc: Faraday TV Encoder TVE200 DRM Driver
diff --git a/Documentation/i2c/busses/i2c-i801 b/Documentation/i2c/busses/i2c-i801
index d47702456926..65514c251318 100644
--- a/Documentation/i2c/busses/i2c-i801
+++ b/Documentation/i2c/busses/i2c-i801
@@ -28,8 +28,10 @@ Supported adapters:
   * Intel Wildcat Point (PCH)
   * Intel Wildcat Point-LP (PCH)
   * Intel BayTrail (SOC)
+  * Intel Braswell (SOC)
   * Intel Sunrise Point-H (PCH)
   * Intel Sunrise Point-LP (PCH)
+  * Intel Kaby Lake-H (PCH)
   * Intel DNV (SOC)
   * Intel Broxton (SOC)
   * Intel Lewisburg (PCH)
diff --git a/Documentation/locking/mutex-design.txt b/Documentation/locking/mutex-design.txt
index 60c482df1a38..818aca19612f 100644
--- a/Documentation/locking/mutex-design.txt
+++ b/Documentation/locking/mutex-design.txt
@@ -21,37 +21,23 @@ Implementation
 --------------
 
 Mutexes are represented by 'struct mutex', defined in include/linux/mutex.h
-and implemented in kernel/locking/mutex.c. These locks use a three
-state atomic counter (->count) to represent the different possible
-transitions that can occur during the lifetime of a lock:
-
-          1: unlocked
-          0: locked, no waiters
-   negative: locked, with potential waiters
-
-In its most basic form it also includes a wait-queue and a spinlock
-that serializes access to it. CONFIG_SMP systems can also include
-a pointer to the lock task owner (->owner) as well as a spinner MCS
-lock (->osq), both described below in (ii).
+and implemented in kernel/locking/mutex.c. These locks use an atomic variable
+(->owner) to keep track of the lock state during its lifetime.  Field owner
+actually contains 'struct task_struct *' to the current lock owner and it is
+therefore NULL if not currently owned. Since task_struct pointers are aligned
+at at least L1_CACHE_BYTES, low bits (3) are used to store extra state (e.g.,
+if waiter list is non-empty).  In its most basic form it also includes a
+wait-queue and a spinlock that serializes access to it. Furthermore,
+CONFIG_MUTEX_SPIN_ON_OWNER=y systems use a spinner MCS lock (->osq), described
+below in (ii).
 
 When acquiring a mutex, there are three possible paths that can be
 taken, depending on the state of the lock:
 
-(i) fastpath: tries to atomically acquire the lock by decrementing the
-    counter. If it was already taken by another task it goes to the next
-    possible path. This logic is architecture specific. On x86-64, the
-    locking fastpath is 2 instructions:
-
-    0000000000000e10 <mutex_lock>:
-    e21:   f0 ff 0b                lock decl (%rbx)
-    e24:   79 08                   jns    e2e <mutex_lock+0x1e>
-
-   the unlocking fastpath is equally tight:
-
-    0000000000000bc0 <mutex_unlock>:
-    bc8:   f0 ff 07                lock incl (%rdi)
-    bcb:   7f 0a                   jg     bd7 <mutex_unlock+0x17>
-
+(i) fastpath: tries to atomically acquire the lock by cmpxchg()ing the owner with
+    the current task. This only works in the uncontended case (cmpxchg() checks
+    against 0UL, so all 3 state bits above have to be 0). If the lock is
+    contended it goes to the next possible path.
 
 (ii) midpath: aka optimistic spinning, tries to spin for acquisition
      while the lock owner is running and there are no other tasks ready
@@ -143,11 +129,10 @@ Test if the mutex is taken:
 Disadvantages
 -------------
 
-Unlike its original design and purpose, 'struct mutex' is larger than
-most locks in the kernel. E.g: on x86-64 it is 40 bytes, almost twice
-as large as 'struct semaphore' (24 bytes) and tied, along with rwsems,
-for the largest lock in the kernel. Larger structure sizes mean more
-CPU cache and memory footprint.
+Unlike its original design and purpose, 'struct mutex' is among the largest
+locks in the kernel. E.g: on x86-64 it is 32 bytes, where 'struct semaphore'
+is 24 bytes and rw_semaphore is 40 bytes. Larger structure sizes mean more CPU
+cache and memory footprint.
 
 When to use mutexes
 -------------------
diff --git a/Documentation/media/dmx.h.rst.exceptions b/Documentation/media/dmx.h.rst.exceptions
index 63f55a9ae2b1..a8c4239ed95b 100644
--- a/Documentation/media/dmx.h.rst.exceptions
+++ b/Documentation/media/dmx.h.rst.exceptions
@@ -50,9 +50,15 @@ replace typedef dmx_filter_t :c:type:`dmx_filter`
 replace typedef dmx_pes_type_t :c:type:`dmx_pes_type`
 replace typedef dmx_input_t :c:type:`dmx_input`
 
-ignore symbol DMX_OUT_DECODER
-ignore symbol DMX_OUT_TAP
-ignore symbol DMX_OUT_TS_TAP
-ignore symbol DMX_OUT_TSDEMUX_TAP
+replace symbol DMX_BUFFER_FLAG_HAD_CRC32_DISCARD :c:type:`dmx_buffer_flags`
+replace symbol DMX_BUFFER_FLAG_TEI :c:type:`dmx_buffer_flags`
+replace symbol DMX_BUFFER_PKT_COUNTER_MISMATCH :c:type:`dmx_buffer_flags`
+replace symbol DMX_BUFFER_FLAG_DISCONTINUITY_DETECTED :c:type:`dmx_buffer_flags`
+replace symbol DMX_BUFFER_FLAG_DISCONTINUITY_INDICATOR :c:type:`dmx_buffer_flags`
+
+replace symbol DMX_OUT_DECODER :c:type:`dmx_output`
+replace symbol DMX_OUT_TAP :c:type:`dmx_output`
+replace symbol DMX_OUT_TS_TAP :c:type:`dmx_output`
+replace symbol DMX_OUT_TSDEMUX_TAP :c:type:`dmx_output`
 
 replace ioctl DMX_DQBUF dmx_qbuf
diff --git a/Documentation/media/uapi/dvb/dmx-qbuf.rst b/Documentation/media/uapi/dvb/dmx-qbuf.rst
index b48c4931658e..be5a4c6f1904 100644
--- a/Documentation/media/uapi/dvb/dmx-qbuf.rst
+++ b/Documentation/media/uapi/dvb/dmx-qbuf.rst
@@ -51,9 +51,10 @@ out to disk. Buffers remain locked until dequeued, until the
 the device is closed.
 
 Applications call the ``DMX_DQBUF`` ioctl to dequeue a filled
-(capturing) buffer from the driver's outgoing queue. They just set the ``reserved`` field array to zero. When ``DMX_DQBUF`` is called with a
-pointer to this structure, the driver fills the remaining fields or
-returns an error code.
+(capturing) buffer from the driver's outgoing queue.
+They just set the ``index`` field withe the buffer ID to be queued.
+When ``DMX_DQBUF`` is called with a pointer to struct :c:type:`dmx_buffer`,
+the driver fills the remaining fields or returns an error code.
 
 By default ``DMX_DQBUF`` blocks when no buffer is in the outgoing
 queue. When the ``O_NONBLOCK`` flag was given to the
diff --git a/Documentation/networking/segmentation-offloads.txt b/Documentation/networking/segmentation-offloads.txt
index 2f09455a993a..d47480b61ac6 100644
--- a/Documentation/networking/segmentation-offloads.txt
+++ b/Documentation/networking/segmentation-offloads.txt
@@ -13,6 +13,7 @@ The following technologies are described:
  * Generic Segmentation Offload - GSO
  * Generic Receive Offload - GRO
  * Partial Generic Segmentation Offload - GSO_PARTIAL
+ * SCTP accelleration with GSO - GSO_BY_FRAGS
 
 TCP Segmentation Offload
 ========================
@@ -49,6 +50,10 @@ datagram into multiple IPv4 fragments.  Many of the requirements for UDP
 fragmentation offload are the same as TSO.  However the IPv4 ID for
 fragments should not increment as a single IPv4 datagram is fragmented.
 
+UFO is deprecated: modern kernels will no longer generate UFO skbs, but can
+still receive them from tuntap and similar devices. Offload of UDP-based
+tunnel protocols is still supported.
+
 IPIP, SIT, GRE, UDP Tunnel, and Remote Checksum Offloads
 ========================================================
 
@@ -83,10 +88,10 @@ SKB_GSO_UDP_TUNNEL_CSUM.  These two additional tunnel types reflect the
 fact that the outer header also requests to have a non-zero checksum
 included in the outer header.
 
-Finally there is SKB_GSO_REMCSUM which indicates that a given tunnel header
-has requested a remote checksum offload.  In this case the inner headers
-will be left with a partial checksum and only the outer header checksum
-will be computed.
+Finally there is SKB_GSO_TUNNEL_REMCSUM which indicates that a given tunnel
+header has requested a remote checksum offload.  In this case the inner
+headers will be left with a partial checksum and only the outer header
+checksum will be computed.
 
 Generic Segmentation Offload
 ============================
@@ -128,3 +133,28 @@ values for if the header was simply duplicated.  The one exception to this
 is the outer IPv4 ID field.  It is up to the device drivers to guarantee
 that the IPv4 ID field is incremented in the case that a given header does
 not have the DF bit set.
+
+SCTP accelleration with GSO
+===========================
+
+SCTP - despite the lack of hardware support - can still take advantage of
+GSO to pass one large packet through the network stack, rather than
+multiple small packets.
+
+This requires a different approach to other offloads, as SCTP packets
+cannot be just segmented to (P)MTU. Rather, the chunks must be contained in
+IP segments, padding respected. So unlike regular GSO, SCTP can't just
+generate a big skb, set gso_size to the fragmentation point and deliver it
+to IP layer.
+
+Instead, the SCTP protocol layer builds an skb with the segments correctly
+padded and stored as chained skbs, and skb_segment() splits based on those.
+To signal this, gso_size is set to the special value GSO_BY_FRAGS.
+
+Therefore, any code in the core networking stack must be aware of the
+possibility that gso_size will be GSO_BY_FRAGS and handle that case
+appropriately. (For size checks, the skb_gso_validate_*_len family of
+helpers do this automatically.)
+
+This also affects drivers with the NETIF_F_FRAGLIST & NETIF_F_GSO_SCTP bits
+set. Note also that NETIF_F_GSO_SCTP is included in NETIF_F_GSO_SOFTWARE.
diff --git a/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/api.txt
index 792fa8717d13..d6b3ff51a14f 100644
--- a/Documentation/virtual/kvm/api.txt
+++ b/Documentation/virtual/kvm/api.txt
@@ -123,14 +123,15 @@ memory layout to fit in user mode), check KVM_CAP_MIPS_VZ and use the
 flag KVM_VM_MIPS_VZ.
 
 
-4.3 KVM_GET_MSR_INDEX_LIST
+4.3 KVM_GET_MSR_INDEX_LIST, KVM_GET_MSR_FEATURE_INDEX_LIST
 
-Capability: basic
+Capability: basic, KVM_CAP_GET_MSR_FEATURES for KVM_GET_MSR_FEATURE_INDEX_LIST
 Architectures: x86
-Type: system
+Type: system ioctl
 Parameters: struct kvm_msr_list (in/out)
 Returns: 0 on success; -1 on error
 Errors:
+  EFAULT:    the msr index list cannot be read from or written to
   E2BIG:     the msr index list is to be to fit in the array specified by
              the user.
 
@@ -139,16 +140,23 @@ struct kvm_msr_list {
         __u32 indices[0];
 };
 
-This ioctl returns the guest msrs that are supported.  The list varies
-by kvm version and host processor, but does not change otherwise.  The
-user fills in the size of the indices array in nmsrs, and in return
-kvm adjusts nmsrs to reflect the actual number of msrs and fills in
-the indices array with their numbers.
+The user fills in the size of the indices array in nmsrs, and in return
+kvm adjusts nmsrs to reflect the actual number of msrs and fills in the
+indices array with their numbers.
+
+KVM_GET_MSR_INDEX_LIST returns the guest msrs that are supported.  The list
+varies by kvm version and host processor, but does not change otherwise.
 
 Note: if kvm indicates supports MCE (KVM_CAP_MCE), then the MCE bank MSRs are
 not returned in the MSR list, as different vcpus can have a different number
 of banks, as set via the KVM_X86_SETUP_MCE ioctl.
 
+KVM_GET_MSR_FEATURE_INDEX_LIST returns the list of MSRs that can be passed
+to the KVM_GET_MSRS system ioctl.  This lets userspace probe host capabilities
+and processor features that are exposed via MSRs (e.g., VMX capabilities).
+This list also varies by kvm version and host processor, but does not change
+otherwise.
+
 
 4.4 KVM_CHECK_EXTENSION
 
@@ -475,14 +483,22 @@ Support for this has been removed.  Use KVM_SET_GUEST_DEBUG instead.
 
 4.18 KVM_GET_MSRS
 
-Capability: basic
+Capability: basic (vcpu), KVM_CAP_GET_MSR_FEATURES (system)
 Architectures: x86
-Type: vcpu ioctl
+Type: system ioctl, vcpu ioctl
 Parameters: struct kvm_msrs (in/out)
-Returns: 0 on success, -1 on error
+Returns: number of msrs successfully returned;
+        -1 on error
+
+When used as a system ioctl:
+Reads the values of MSR-based features that are available for the VM.  This
+is similar to KVM_GET_SUPPORTED_CPUID, but it returns MSR indices and values.
+The list of msr-based features can be obtained using KVM_GET_MSR_FEATURE_INDEX_LIST
+in a system ioctl.
 
+When used as a vcpu ioctl:
 Reads model-specific registers from the vcpu.  Supported msr indices can
-be obtained using KVM_GET_MSR_INDEX_LIST.
+be obtained using KVM_GET_MSR_INDEX_LIST in a system ioctl.
 
 struct kvm_msrs {
         __u32 nmsrs; /* number of msrs in entries */
diff --git a/Documentation/virtual/kvm/cpuid.txt b/Documentation/virtual/kvm/cpuid.txt
index dcab6dc11e3b..87a7506f31c2 100644
--- a/Documentation/virtual/kvm/cpuid.txt
+++ b/Documentation/virtual/kvm/cpuid.txt
@@ -58,6 +58,10 @@ KVM_FEATURE_PV_TLB_FLUSH           ||     9 || guest checks this feature bit
                                    ||       || before enabling paravirtualized
                                    ||       || tlb flush.
 ------------------------------------------------------------------------------
+KVM_FEATURE_ASYNC_PF_VMEXIT        ||    10 || paravirtualized async PF VM exit
+                                   ||       || can be enabled by setting bit 2
+                                   ||       || when writing to msr 0x4b564d02
+------------------------------------------------------------------------------
 KVM_FEATURE_CLOCKSOURCE_STABLE_BIT ||    24 || host will warn if no guest-side
                                    ||       || per-cpu warps are expected in
                                    ||       || kvmclock.
diff --git a/Documentation/virtual/kvm/msr.txt b/Documentation/virtual/kvm/msr.txt
index 1ebecc115dc6..f3f0d57ced8e 100644
--- a/Documentation/virtual/kvm/msr.txt
+++ b/Documentation/virtual/kvm/msr.txt
@@ -170,7 +170,8 @@ MSR_KVM_ASYNC_PF_EN: 0x4b564d02
         when asynchronous page faults are enabled on the vcpu 0 when
         disabled. Bit 1 is 1 if asynchronous page faults can be injected
         when vcpu is in cpl == 0. Bit 2 is 1 if asynchronous page faults
-        are delivered to L1 as #PF vmexits.
+        are delivered to L1 as #PF vmexits.  Bit 2 can be set only if
+        KVM_FEATURE_ASYNC_PF_VMEXIT is present in CPUID.
 
         First 4 byte of 64 byte memory location will be written to by
         the hypervisor at the time of asynchronous page fault (APF)
diff --git a/Documentation/x86/intel_rdt_ui.txt b/Documentation/x86/intel_rdt_ui.txt
index 756fd76b78a6..71c30984e94d 100644
--- a/Documentation/x86/intel_rdt_ui.txt
+++ b/Documentation/x86/intel_rdt_ui.txt
@@ -671,7 +671,7 @@ occupancy of the real time threads on these cores.
 # mkdir p1
 
 Move the cpus 4-7 over to p1
-# echo f0 > p0/cpus
+# echo f0 > p1/cpus
 
 View the llc occupancy snapshot
 
diff --git a/Documentation/x86/topology.txt b/Documentation/x86/topology.txt
index f3e9d7e9ed6c..2953e3ec9a02 100644
--- a/Documentation/x86/topology.txt
+++ b/Documentation/x86/topology.txt
@@ -108,7 +108,7 @@ The topology of a system is described in the units of:
 
     The number of online threads is also printed in /proc/cpuinfo "siblings."
 
-  - topology_sibling_mask():
+  - topology_sibling_cpumask():
 
     The cpumask contains all online threads in the core to which a thread
     belongs.
diff --git a/MAINTAINERS b/MAINTAINERS
index 3bdc260e36b7..94e6a62ca60b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1238,7 +1238,7 @@ F:	drivers/clk/at91
 
 ARM/ATMEL AT91RM9200, AT91SAM9 AND SAMA5 SOC SUPPORT
 M:      Nicolas Ferre <nicolas.ferre@microchip.com>
-M:      Alexandre Belloni <alexandre.belloni@free-electrons.com>
+M:      Alexandre Belloni <alexandre.belloni@bootlin.com>
 L:      linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 W:      http://www.linux4sam.org
 T:      git git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91.git
@@ -1590,7 +1590,7 @@ ARM/Marvell Dove/MV78xx0/Orion SOC support
 M:      Jason Cooper <jason@lakedaemon.net>
 M:      Andrew Lunn <andrew@lunn.ch>
 M:      Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
-M:      Gregory Clement <gregory.clement@free-electrons.com>
+M:      Gregory Clement <gregory.clement@bootlin.com>
 L:      linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:      Maintained
 F:      Documentation/devicetree/bindings/soc/dove/
@@ -1604,7 +1604,7 @@ F:	arch/arm/boot/dts/orion5x*
 ARM/Marvell Kirkwood and Armada 370, 375, 38x, 39x, XP, 3700, 7K/8K SOC support
 M:      Jason Cooper <jason@lakedaemon.net>
 M:      Andrew Lunn <andrew@lunn.ch>
-M:      Gregory Clement <gregory.clement@free-electrons.com>
+M:      Gregory Clement <gregory.clement@bootlin.com>
 M:      Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
 L:      linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:      Maintained
@@ -1863,7 +1863,6 @@ Q:	https://patchwork.kernel.org/project/linux-samsung-soc/list/
 S:      Maintained
 F:      arch/arm/boot/dts/s3c*
 F:      arch/arm/boot/dts/s5p*
-F:      arch/arm/boot/dts/samsung*
 F:      arch/arm/boot/dts/exynos*
 F:      arch/arm64/boot/dts/exynos/
 F:      arch/arm/plat-samsung/
@@ -1999,8 +1998,10 @@ M:	Maxime Coquelin <mcoquelin.stm32@gmail.com>
 M:      Alexandre Torgue <alexandre.torgue@st.com>
 L:      linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:      Maintained
-T:      git git://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/stm32.git
+T:      git git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32.git stm32-next
 N:      stm32
+F:      arch/arm/boot/dts/stm32*
+F:      arch/arm/mach-stm32/
 F:      drivers/clocksource/armv7m_systick.c
 
 ARM/TANGO ARCHITECTURE
@@ -7600,8 +7601,10 @@ F:	mm/kasan/
 F:      scripts/Makefile.kasan
 
 KCONFIG
+M:      Masahiro Yamada <yamada.masahiro@socionext.com>
+T:      git git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild.git kconfig
 L:      linux-kbuild@vger.kernel.org
-S:      Orphan
+S:      Maintained
 F:      Documentation/kbuild/kconfig-language.txt
 F:      scripts/kconfig/
 
@@ -7909,7 +7912,6 @@ S:	Maintained
 F:      scripts/leaking_addresses.pl
 
 LED SUBSYSTEM
-M:      Richard Purdie <rpurdie@rpsys.net>
 M:      Jacek Anaszewski <jacek.anaszewski@gmail.com>
 M:      Pavel Machek <pavel@ucw.cz>
 L:      linux-leds@vger.kernel.org
@@ -9206,6 +9208,7 @@ MIPS GENERIC PLATFORM
 M:      Paul Burton <paul.burton@mips.com>
 L:      linux-mips@linux-mips.org
 S:      Supported
+F:      Documentation/devicetree/bindings/power/mti,mips-cpc.txt
 F:      arch/mips/generic/
 F:      arch/mips/tools/generic-board-config.sh
 
@@ -9945,6 +9948,7 @@ F:	drivers/nfc/nxp-nci
 
 OBJTOOL
 M:      Josh Poimboeuf <jpoimboe@redhat.com>
+M:      Peter Zijlstra <peterz@infradead.org>
 S:      Supported
 F:      tools/objtool/
 
@@ -10925,6 +10929,17 @@ L:	linux-gpio@vger.kernel.org
 S:      Supported
 F:      drivers/pinctrl/pinctrl-at91-pio4.*
 
+PIN CONTROLLER - FREESCALE
+M:      Dong Aisheng <aisheng.dong@nxp.com>
+M:      Fabio Estevam <festevam@gmail.com>
+M:      Shawn Guo <shawnguo@kernel.org>
+M:      Stefan Agner <stefan@agner.ch>
+R:      Pengutronix Kernel Team <kernel@pengutronix.de>
+L:      linux-gpio@vger.kernel.org
+S:      Maintained
+F:      drivers/pinctrl/freescale/
+F:      Documentation/devicetree/bindings/pinctrl/fsl,*
+
 PIN CONTROLLER - INTEL
 M:      Mika Westerberg <mika.westerberg@linux.intel.com>
 M:      Heikki Krogerus <heikki.krogerus@linux.intel.com>
diff --git a/Makefile b/Makefile
index 79ad2bfa24b6..c4322dea3ca2 100644
--- a/Makefile
+++ b/Makefile
@@ -2,7 +2,7 @@
 VERSION = 4
 PATCHLEVEL = 16
 SUBLEVEL = 0
-EXTRAVERSION = -rc1
+EXTRAVERSION = -rc4
 NAME = Fearless Coyote
 
 # *DOCUMENTATION*
@@ -388,7 +388,7 @@ PYTHON		= python
 CHECK           = sparse
 
 CHECKFLAGS     := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \
-                  -Wbitwise -Wno-return-void $(CF)
+                  -Wbitwise -Wno-return-void -Wno-unknown-attribute $(CF)
 NOSTDINC_FLAGS  =
 CFLAGS_MODULE   =
 AFLAGS_MODULE   =
@@ -489,6 +489,11 @@ KBUILD_CFLAGS += $(CLANG_TARGET) $(CLANG_GCC_TC)
 KBUILD_AFLAGS += $(CLANG_TARGET) $(CLANG_GCC_TC)
 endif
 
+RETPOLINE_CFLAGS_GCC := -mindirect-branch=thunk-extern -mindirect-branch-register
+RETPOLINE_CFLAGS_CLANG := -mretpoline-external-thunk
+RETPOLINE_CFLAGS := $(call cc-option,$(RETPOLINE_CFLAGS_GCC),$(call cc-option,$(RETPOLINE_CFLAGS_CLANG)))
+export RETPOLINE_CFLAGS
+
 ifeq ($(config-targets),1)
 # ===========================================================================
 # *config targets only - make sure prerequisites are updated, and descend
@@ -579,10 +584,9 @@ ifeq ($(KBUILD_EXTMOD),)
 # To avoid any implicit rule to kick in, define an empty command
 $(KCONFIG_CONFIG) include/config/auto.conf.cmd: ;
 
-# If .config is newer than include/config/auto.conf, someone tinkered
-# with it and forgot to run make oldconfig.
-# if auto.conf.cmd is missing then we are probably in a cleaned tree so
-# we execute the config step to be sure to catch updated Kconfig files
+# The actual configuration files used during the build are stored in
+# include/generated/ and include/config/. Update them if .config is newer than
+# include/config/auto.conf (which mirrors .config).
 include/config/%.conf: $(KCONFIG_CONFIG) include/config/auto.conf.cmd
         $(Q)$(MAKE) -f $(srctree)/Makefile silentoldconfig
 else
@@ -857,8 +861,7 @@ KBUILD_AFLAGS   += $(ARCH_AFLAGS)   $(KAFLAGS)
 KBUILD_CFLAGS   += $(ARCH_CFLAGS)   $(KCFLAGS)
 
 # Use --build-id when available.
-LDFLAGS_BUILD_ID := $(patsubst -Wl$(comma)%,%,\
-                              $(call cc-ldoption, -Wl$(comma)--build-id,))
+LDFLAGS_BUILD_ID := $(call ld-option, --build-id)
 KBUILD_LDFLAGS_MODULE += $(LDFLAGS_BUILD_ID)
 LDFLAGS_vmlinux += $(LDFLAGS_BUILD_ID)
 
diff --git a/arch/alpha/include/asm/cmpxchg.h b/arch/alpha/include/asm/cmpxchg.h
index 46ebf14aed4e..8a2b331e43fe 100644
--- a/arch/alpha/include/asm/cmpxchg.h
+++ b/arch/alpha/include/asm/cmpxchg.h
@@ -6,7 +6,6 @@
  * Atomic exchange routines.
  */
 
-#define __ASM__MB
 #define ____xchg(type, args...)         __xchg ## type ## _local(args)
 #define ____cmpxchg(type, args...)      __cmpxchg ## type ## _local(args)
 #include <asm/xchg.h>
@@ -33,10 +32,6 @@
         cmpxchg_local((ptr), (o), (n));                                 \
 })
 
-#ifdef CONFIG_SMP
-#undef __ASM__MB
-#define __ASM__MB       "\tmb\n"
-#endif
 #undef ____xchg
 #undef ____cmpxchg
 #define ____xchg(type, args...)         __xchg ##type(args)
@@ -64,7 +59,6 @@
         cmpxchg((ptr), (o), (n));                                       \
 })
 
-#undef __ASM__MB
 #undef ____cmpxchg
 
 #endif /* _ALPHA_CMPXCHG_H */
diff --git a/arch/alpha/include/asm/xchg.h b/arch/alpha/include/asm/xchg.h
index 68dfb3cb7145..e2b59fac5257 100644
--- a/arch/alpha/include/asm/xchg.h
+++ b/arch/alpha/include/asm/xchg.h
@@ -12,6 +12,10 @@
  * Atomic exchange.
  * Since it can be used to implement critical sections
  * it must clobber "memory" (also for interrupts in UP).
+ *
+ * The leading and the trailing memory barriers guarantee that these
+ * operations are fully ordered.
+ *
  */
 
 static inline unsigned long
@@ -19,6 +23,7 @@ ____xchg(_u8, volatile char *m, unsigned long val)
 {
         unsigned long ret, tmp, addr64;
 
+        smp_mb();
         __asm__ __volatile__(
         "       andnot  %4,7,%3\n"
         "       insbl   %1,%4,%1\n"
@@ -28,12 +33,12 @@ ____xchg(_u8, volatile char *m, unsigned long val)
         "       or      %1,%2,%2\n"
         "       stq_c   %2,0(%3)\n"
         "       beq     %2,2f\n"
-                __ASM__MB
         ".subsection 2\n"
         "2:     br      1b\n"
         ".previous"
         : "=&r" (ret), "=&r" (val), "=&r" (tmp), "=&r" (addr64)
         : "r" ((long)m), "1" (val) : "memory");
+        smp_mb();
 
         return ret;
 }
@@ -43,6 +48,7 @@ ____xchg(_u16, volatile short *m, unsigned long val)
 {
         unsigned long ret, tmp, addr64;
 
+        smp_mb();
         __asm__ __volatile__(
         "       andnot  %4,7,%3\n"
         "       inswl   %1,%4,%1\n"
@@ -52,12 +58,12 @@ ____xchg(_u16, volatile short *m, unsigned long val)
         "       or      %1,%2,%2\n"
         "       stq_c   %2,0(%3)\n"
         "       beq     %2,2f\n"
-                __ASM__MB
         ".subsection 2\n"
         "2:     br      1b\n"
         ".previous"
         : "=&r" (ret), "=&r" (val), "=&r" (tmp), "=&r" (addr64)
         : "r" ((long)m), "1" (val) : "memory");
+        smp_mb();
 
         return ret;
 }
@@ -67,17 +73,18 @@ ____xchg(_u32, volatile int *m, unsigned long val)
 {
         unsigned long dummy;
 
+        smp_mb();
         __asm__ __volatile__(
         "1:     ldl_l %0,%4\n"
         "       bis $31,%3,%1\n"
         "       stl_c %1,%2\n"
         "       beq %1,2f\n"
-                __ASM__MB
         ".subsection 2\n"
         "2:     br 1b\n"
         ".previous"
         : "=&r" (val), "=&r" (dummy), "=m" (*m)
         : "rI" (val), "m" (*m) : "memory");
+        smp_mb();
 
         return val;
 }
@@ -87,17 +94,18 @@ ____xchg(_u64, volatile long *m, unsigned long val)
 {
         unsigned long dummy;
 
+        smp_mb();
         __asm__ __volatile__(
         "1:     ldq_l %0,%4\n"
         "       bis $31,%3,%1\n"
         "       stq_c %1,%2\n"
         "       beq %1,2f\n"
-                __ASM__MB
         ".subsection 2\n"
         "2:     br 1b\n"
         ".previous"
         : "=&r" (val), "=&r" (dummy), "=m" (*m)
         : "rI" (val), "m" (*m) : "memory");
+        smp_mb();
 
         return val;
 }
@@ -128,10 +136,12 @@ ____xchg(, volatile void *ptr, unsigned long x, int size)
  * store NEW in MEM.  Return the initial value in MEM.  Success is
  * indicated by comparing RETURN with OLD.
  *
- * The memory barrier should be placed in SMP only when we actually
- * make the change. If we don't change anything (so if the returned
- * prev is equal to old) then we aren't acquiring anything new and
- * we don't need any memory barrier as far I can tell.
+ * The leading and the trailing memory barriers guarantee that these
+ * operations are fully ordered.
+ *
+ * The trailing memory barrier is placed in SMP unconditionally, in
+ * order to guarantee that dependency ordering is preserved when a
+ * dependency is headed by an unsuccessful operation.
  */
 
 static inline unsigned long
@@ -139,6 +149,7 @@ ____cmpxchg(_u8, volatile char *m, unsigned char old, unsigned char new)
 {
         unsigned long prev, tmp, cmp, addr64;
 
+        smp_mb();
         __asm__ __volatile__(
         "       andnot  %5,7,%4\n"
         "       insbl   %1,%5,%1\n"
@@ -150,13 +161,13 @@ ____cmpxchg(_u8, volatile char *m, unsigned char old, unsigned char new)
         "       or      %1,%2,%2\n"
         "       stq_c   %2,0(%4)\n"
         "       beq     %2,3f\n"
-                __ASM__MB
         "2:\n"
         ".subsection 2\n"
         "3:     br      1b\n"
         ".previous"
         : "=&r" (prev), "=&r" (new), "=&r" (tmp), "=&r" (cmp), "=&r" (addr64)
         : "r" ((long)m), "Ir" (old), "1" (new) : "memory");
+        smp_mb();
 
         return prev;
 }
@@ -166,6 +177,7 @@ ____cmpxchg(_u16, volatile short *m, unsigned short old, unsigned short new)
 {
         unsigned long prev, tmp, cmp, addr64;
 
+        smp_mb();
         __asm__ __volatile__(
         "       andnot  %5,7,%4\n"
         "       inswl   %1,%5,%1\n"
@@ -177,13 +189,13 @@ ____cmpxchg(_u16, volatile short *m, unsigned short old, unsigned short new)
         "       or      %1,%2,%2\n"
         "       stq_c   %2,0(%4)\n"
         "       beq     %2,3f\n"
-                __ASM__MB
         "2:\n"
         ".subsection 2\n"
         "3:     br      1b\n"
         ".previous"
         : "=&r" (prev), "=&r" (new), "=&r" (tmp), "=&r" (cmp), "=&r" (addr64)
         : "r" ((long)m), "Ir" (old), "1" (new) : "memory");
+        smp_mb();
 
         return prev;
 }
@@ -193,6 +205,7 @@ ____cmpxchg(_u32, volatile int *m, int old, int new)
 {
         unsigned long prev, cmp;
 
+        smp_mb();
         __asm__ __volatile__(
         "1:     ldl_l %0,%5\n"
         "       cmpeq %0,%3,%1\n"
@@ -200,13 +213,13 @@ ____cmpxchg(_u32, volatile int *m, int old, int new)
         "       mov %4,%1\n"
         "       stl_c %1,%2\n"
         "       beq %1,3f\n"
-                __ASM__MB
         "2:\n"
         ".subsection 2\n"
         "3:     br 1b\n"
         ".previous"
         : "=&r"(prev), "=&r"(cmp), "=m"(*m)
         : "r"((long) old), "r"(new), "m"(*m) : "memory");
+        smp_mb();
 
         return prev;
 }
@@ -216,6 +229,7 @@ ____cmpxchg(_u64, volatile long *m, unsigned long old, unsigned long new)
 {
         unsigned long prev, cmp;
 
+        smp_mb();
         __asm__ __volatile__(
         "1:     ldq_l %0,%5\n"
         "       cmpeq %0,%3,%1\n"
@@ -223,13 +237,13 @@ ____cmpxchg(_u64, volatile long *m, unsigned long old, unsigned long new)
         "       mov %4,%1\n"
         "       stq_c %1,%2\n"
         "       beq %1,3f\n"
-                __ASM__MB
         "2:\n"
         ".subsection 2\n"
         "3:     br 1b\n"
         ".previous"
         : "=&r"(prev), "=&r"(cmp), "=m"(*m)
         : "r"((long) old), "r"(new), "m"(*m) : "memory");
+        smp_mb();
 
         return prev;
 }
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index f3a80cf164cc..d76bf4a83740 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -484,7 +484,6 @@ config ARC_CURR_IN_REG
 
 config ARC_EMUL_UNALIGNED
         bool "Emulate unaligned memory access (userspace only)"
-        default N
         select SYSCTL_ARCH_UNALIGN_NO_WARN
         select SYSCTL_ARCH_UNALIGN_ALLOW
         depends on ISA_ARCOMPACT
diff --git a/arch/arc/boot/dts/axs101.dts b/arch/arc/boot/dts/axs101.dts
index 70aec7d6ca60..626b694c7be7 100644
--- a/arch/arc/boot/dts/axs101.dts
+++ b/arch/arc/boot/dts/axs101.dts
@@ -17,6 +17,6 @@
         compatible = "snps,axs101", "snps,arc-sdp";
 
         chosen {
-                bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=tty0 console=ttyS3,115200n8 consoleblank=0 video=1280x720@60";
+                bootargs = "earlycon=uart8250,mmio32,0xe0022000,115200n8 console=tty0 console=ttyS3,115200n8 consoleblank=0 video=1280x720@60 print-fatal-signals=1";
         };
 };
diff --git a/arch/arc/boot/dts/axs10x_mb.dtsi b/arch/arc/boot/dts/axs10x_mb.dtsi
index 74d070cd3c13..47b74fbc403c 100644
--- a/arch/arc/boot/dts/axs10x_mb.dtsi
+++ b/arch/arc/boot/dts/axs10x_mb.dtsi
@@ -214,13 +214,13 @@
                         };
 
                         eeprom@0x54{
-                                compatible = "24c01";
+                                compatible = "atmel,24c01";
                                 reg = <0x54>;
                                 pagesize = <0x8>;
                         };
 
                         eeprom@0x57{
-                                compatible = "24c04";
+                                compatible = "atmel,24c04";
                                 reg = <0x57>;
                                 pagesize = <0x8>;
                         };
diff --git a/arch/arc/boot/dts/haps_hs_idu.dts b/arch/arc/boot/dts/haps_hs_idu.dts
index 215cddd0b63b..0c603308aeb3 100644
--- a/arch/arc/boot/dts/haps_hs_idu.dts
+++ b/arch/arc/boot/dts/haps_hs_idu.dts
@@ -22,7 +22,7 @@
         };
 
         chosen {
-                bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug";
+                bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
         };
 
         aliases {
diff --git a/arch/arc/boot/dts/nsim_700.dts b/arch/arc/boot/dts/nsim_700.dts
index 5ee96b067c08..ff2f2c70c545 100644
--- a/arch/arc/boot/dts/nsim_700.dts
+++ b/arch/arc/boot/dts/nsim_700.dts
@@ -17,7 +17,7 @@
         interrupt-parent = <&core_intc>;
 
         chosen {
-                bootargs = "earlycon=arc_uart,mmio32,0xc0fc1000,115200n8 console=ttyARC0,115200n8";
+                bootargs = "earlycon=arc_uart,mmio32,0xc0fc1000,115200n8 console=ttyARC0,115200n8 print-fatal-signals=1";
         };
 
         aliases {
diff --git a/arch/arc/boot/dts/nsim_hs.dts b/arch/arc/boot/dts/nsim_hs.dts
index 8d787b251f73..8e2489b16b0a 100644
--- a/arch/arc/boot/dts/nsim_hs.dts
+++ b/arch/arc/boot/dts/nsim_hs.dts
@@ -24,7 +24,7 @@
         };
 
         chosen {
-                bootargs = "earlycon=arc_uart,mmio32,0xc0fc1000,115200n8 console=ttyARC0,115200n8";
+                bootargs = "earlycon=arc_uart,mmio32,0xc0fc1000,115200n8 console=ttyARC0,115200n8 print-fatal-signals=1";
         };
 
         aliases {
diff --git a/arch/arc/boot/dts/nsim_hs_idu.dts b/arch/arc/boot/dts/nsim_hs_idu.dts
index 4f98ebf71fd8..ed12f494721d 100644
--- a/arch/arc/boot/dts/nsim_hs_idu.dts
+++ b/arch/arc/boot/dts/nsim_hs_idu.dts
@@ -15,7 +15,7 @@
         interrupt-parent = <&core_intc>;
 
         chosen {
-                bootargs = "earlycon=arc_uart,mmio32,0xc0fc1000,115200n8 console=ttyARC0,115200n8";
+                bootargs = "earlycon=arc_uart,mmio32,0xc0fc1000,115200n8 console=ttyARC0,115200n8 print-fatal-signals=1";
         };
 
         aliases {
diff --git a/arch/arc/boot/dts/nsimosci.dts b/arch/arc/boot/dts/nsimosci.dts
index 3c391ba565ed..7842e5eb4ab5 100644
--- a/arch/arc/boot/dts/nsimosci.dts
+++ b/arch/arc/boot/dts/nsimosci.dts
@@ -20,7 +20,7 @@
                 /* this is for console on PGU */
                 /* bootargs = "console=tty0 consoleblank=0"; */
                 /* this is for console on serial */
-                bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblank=0 debug video=640x480-24";
+                bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblank=0 debug video=640x480-24 print-fatal-signals=1";
         };
 
         aliases {
diff --git a/arch/arc/boot/dts/nsimosci_hs.dts b/arch/arc/boot/dts/nsimosci_hs.dts
index 14a727cbf4c9..b8838cf2b4ec 100644
--- a/arch/arc/boot/dts/nsimosci_hs.dts
+++ b/arch/arc/boot/dts/nsimosci_hs.dts
@@ -20,7 +20,7 @@
                 /* this is for console on PGU */
                 /* bootargs = "console=tty0 consoleblank=0"; */
                 /* this is for console on serial */
-                bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblank=0 debug video=640x480-24";
+                bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblank=0 debug video=640x480-24 print-fatal-signals=1";
         };
 
         aliases {
diff --git a/arch/arc/boot/dts/nsimosci_hs_idu.dts b/arch/arc/boot/dts/nsimosci_hs_idu.dts
index 5052917d4a99..72a2c723f1f7 100644
--- a/arch/arc/boot/dts/nsimosci_hs_idu.dts
+++ b/arch/arc/boot/dts/nsimosci_hs_idu.dts
@@ -18,7 +18,7 @@
 
         chosen {
                 /* this is for console on serial */
-                bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblan=0 debug video=640x480-24";
+                bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblan=0 debug video=640x480-24 print-fatal-signals=1";
         };
 
         aliases {
diff --git a/arch/arc/include/asm/bug.h b/arch/arc/include/asm/bug.h
index ea022d47896c..21ec82466d62 100644
--- a/arch/arc/include/asm/bug.h
+++ b/arch/arc/include/asm/bug.h
@@ -23,7 +23,8 @@ void die(const char *str, struct pt_regs *regs, unsigned long address);
 
 #define BUG()   do {                                                            \
         pr_warn("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __func__); \
-        dump_stack();                                                           \
+        barrier_before_unreachable();                                           \
+        __builtin_trap();                                                       \
 } while (0)
 
 #define HAVE_ARCH_BUG
diff --git a/arch/arc/include/asm/entry-arcv2.h b/arch/arc/include/asm/entry-arcv2.h
index 257a68f3c2fe..309f4e6721b3 100644
--- a/arch/arc/include/asm/entry-arcv2.h
+++ b/arch/arc/include/asm/entry-arcv2.h
@@ -184,7 +184,7 @@
 .macro FAKE_RET_FROM_EXCPN
         lr      r9, [status32]
         bic     r9, r9, (STATUS_U_MASK|STATUS_DE_MASK|STATUS_AE_MASK)
-        or      r9, r9, (STATUS_L_MASK|STATUS_IE_MASK)
+        or      r9, r9, STATUS_IE_MASK
         kflag   r9
 .endm
 
diff --git a/arch/arc/kernel/mcip.c b/arch/arc/kernel/mcip.c
index f61a52b01625..5fe84e481654 100644
--- a/arch/arc/kernel/mcip.c
+++ b/arch/arc/kernel/mcip.c
@@ -22,10 +22,79 @@ static DEFINE_RAW_SPINLOCK(mcip_lock);
 
 static char smp_cpuinfo_buf[128];
 
+/*
+ * Set mask to halt GFRC if any online core in SMP cluster is halted.
+ * Only works for ARC HS v3.0+, on earlier versions has no effect.
+ */
+static void mcip_update_gfrc_halt_mask(int cpu)
+{
+        struct bcr_generic gfrc;
+        unsigned long flags;
+        u32 gfrc_halt_mask;
+
+        READ_BCR(ARC_REG_GFRC_BUILD, gfrc);
+
+        /*
+         * CMD_GFRC_SET_CORE and CMD_GFRC_READ_CORE commands were added in
+         * GFRC 0x3 version.
+         */
+        if (gfrc.ver < 0x3)
+                return;
+
+        raw_spin_lock_irqsave(&mcip_lock, flags);
+
+        __mcip_cmd(CMD_GFRC_READ_CORE, 0);
+        gfrc_halt_mask = read_aux_reg(ARC_REG_MCIP_READBACK);
+        gfrc_halt_mask |= BIT(cpu);
+        __mcip_cmd_data(CMD_GFRC_SET_CORE, 0, gfrc_halt_mask);
+
+        raw_spin_unlock_irqrestore(&mcip_lock, flags);
+}
+
+static void mcip_update_debug_halt_mask(int cpu)
+{
+        u32 mcip_mask = 0;
+        unsigned long flags;
+
+        raw_spin_lock_irqsave(&mcip_lock, flags);
+
+        /*
+         * mcip_mask is same for CMD_DEBUG_SET_SELECT and CMD_DEBUG_SET_MASK
+         * commands. So read it once instead of reading both CMD_DEBUG_READ_MASK
+         * and CMD_DEBUG_READ_SELECT.
+         */
+        __mcip_cmd(CMD_DEBUG_READ_SELECT, 0);
+        mcip_mask = read_aux_reg(ARC_REG_MCIP_READBACK);
+
+        mcip_mask |= BIT(cpu);
+
+        __mcip_cmd_data(CMD_DEBUG_SET_SELECT, 0, mcip_mask);
+        /*
+         * Parameter specified halt cause:
+         * STATUS32[H]/actionpoint/breakpoint/self-halt
+         * We choose all of them (0xF).
+         */
+        __mcip_cmd_data(CMD_DEBUG_SET_MASK, 0xF, mcip_mask);
+
+        raw_spin_unlock_irqrestore(&mcip_lock, flags);
+}
+
 static void mcip_setup_per_cpu(int cpu)
 {
+        struct mcip_bcr mp;
+
+        READ_BCR(ARC_REG_MCIP_BCR, mp);
+
         smp_ipi_irq_setup(cpu, IPI_IRQ);
         smp_ipi_irq_setup(cpu, SOFTIRQ_IRQ);
+
+        /* Update GFRC halt mask as new CPU came online */
+        if (mp.gfrc)
+                mcip_update_gfrc_halt_mask(cpu);
+
+        /* Update MCIP debug mask as new CPU came online */
+        if (mp.dbg)
+                mcip_update_debug_halt_mask(cpu);
 }
 
 static void mcip_ipi_send(int cpu)
@@ -101,11 +170,6 @@ static void mcip_probe_n_setup(void)
                 IS_AVAIL1(mp.gfrc, "GFRC"));
 
         cpuinfo_arc700[0].extn.gfrc = mp.gfrc;
-
-        if (mp.dbg) {
-                __mcip_cmd_data(CMD_DEBUG_SET_SELECT, 0, 0xf);
-                __mcip_cmd_data(CMD_DEBUG_SET_MASK, 0xf, 0xf);
-        }
 }
 
 struct plat_smp_ops plat_smp_ops = {
diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c
index 9d27331fe69a..b2cae79a25d7 100644
--- a/arch/arc/kernel/setup.c
+++ b/arch/arc/kernel/setup.c
@@ -51,7 +51,7 @@ static const struct id_to_str arc_cpu_rel[] = {
         { 0x51, "R2.0" },
         { 0x52, "R2.1" },
         { 0x53, "R3.0" },
-        { 0x54, "R4.0" },
+        { 0x54, "R3.10a" },
 #endif
         { 0x00, NULL   }
 };
@@ -373,7 +373,7 @@ static void arc_chk_core_config(void)
 {
         struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
         int saved = 0, present = 0;
-        char *opt_nm = NULL;;
+        char *opt_nm = NULL;
 
         if (!cpu->extn.timer0)
                 panic("Timer0 is not present!\n");
diff --git a/arch/arc/kernel/smp.c b/arch/arc/kernel/smp.c
index efe8b4200a67..21d86c36692b 100644
--- a/arch/arc/kernel/smp.c
+++ b/arch/arc/kernel/smp.c
@@ -24,6 +24,7 @@
 #include <linux/reboot.h>
 #include <linux/irqdomain.h>
 #include <linux/export.h>
+#include <linux/of_fdt.h>
 
 #include <asm/processor.h>
 #include <asm/setup.h>
@@ -47,6 +48,42 @@ void __init smp_prepare_boot_cpu(void)
 {
 }
 
+static int __init arc_get_cpu_map(const char *name, struct cpumask *cpumask)
+{
+        unsigned long dt_root = of_get_flat_dt_root();
+        const char *buf;
+
+        buf = of_get_flat_dt_prop(dt_root, name, NULL);
+        if (!buf)
+                return -EINVAL;
+
+        if (cpulist_parse(buf, cpumask))
+                return -EINVAL;
+
+        return 0;
+}
+
+/*
+ * Read from DeviceTree and setup cpu possible mask. If there is no
+ * "possible-cpus" property in DeviceTree pretend all [0..NR_CPUS-1] exist.
+ */
+static void __init arc_init_cpu_possible(void)
+{
+        struct cpumask cpumask;
+
+        if (arc_get_cpu_map("possible-cpus", &cpumask)) {
+                pr_warn("Failed to get possible-cpus from dtb, pretending all %u cpus exist\n",
+                        NR_CPUS);
+
+                cpumask_setall(&cpumask);
+        }
+
+        if (!cpumask_test_cpu(0, &cpumask))
+                panic("Master cpu (cpu[0]) is missed in cpu possible mask!");
+
+        init_cpu_possible(&cpumask);
+}
+
 /*
  * Called from setup_arch() before calling setup_processor()
  *
@@ -58,10 +95,7 @@ void __init smp_prepare_boot_cpu(void)
  */
 void __init smp_init_cpus(void)
 {
-        unsigned int i;
-
-        for (i = 0; i < NR_CPUS; i++)
-                set_cpu_possible(i, true);
+        arc_init_cpu_possible();
 
         if (plat_smp_ops.init_early_smp)
                 plat_smp_ops.init_early_smp();
@@ -70,16 +104,12 @@ void __init smp_init_cpus(void)
 /* called from init ( ) =>  process 1 */
 void __init smp_prepare_cpus(unsigned int max_cpus)
 {
-        int i;
-
         /*
          * if platform didn't set the present map already, do it now
          * boot cpu is set to present already by init/main.c
          */
-        if (num_present_cpus() <= 1) {
-                for (i = 0; i < max_cpus; i++)
-                        set_cpu_present(i, true);
-        }
+        if (num_present_cpus() <= 1)
+                init_cpu_present(cpu_possible_mask);
 }
 
 void __init smp_cpus_done(unsigned int max_cpus)
diff --git a/arch/arc/kernel/unwind.c b/arch/arc/kernel/unwind.c
index 333daab7def0..183391d4d33a 100644
--- a/arch/arc/kernel/unwind.c
+++ b/arch/arc/kernel/unwind.c
@@ -366,7 +366,7 @@ static void init_unwind_hdr(struct unwind_table *table,
         return;
 
 ret_err:
-        panic("Attention !!! Dwarf FDE parsing errors\n");;
+        panic("Attention !!! Dwarf FDE parsing errors\n");
 }
 
 #ifdef CONFIG_MODULES
diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index eee924dfffa6..2072f3451e9c 100644
--- a/arch/arc/mm/cache.c
+++ b/arch/arc/mm/cache.c
@@ -780,7 +780,10 @@ noinline static void slc_entire_op(const int op)
 
         write_aux_reg(r, ctrl);
 
-        write_aux_reg(ARC_REG_SLC_INVALIDATE, 1);
+        if (op & OP_INV)        /* Inv or flush-n-inv use same cmd reg */
+                write_aux_reg(ARC_REG_SLC_INVALIDATE, 0x1);
+        else
+                write_aux_reg(ARC_REG_SLC_FLUSH, 0x1);
 
         /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */
         read_aux_reg(r);
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index ade7a38543dc..8164c1294226 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -163,7 +163,10 @@ dtb-$(CONFIG_ARCH_EXYNOS4) += \
         exynos4210-smdkv310.dtb \
         exynos4210-trats.dtb \
         exynos4210-universal_c210.dtb \
+        exynos4412-i9300.dtb \
+        exynos4412-i9305.dtb \
         exynos4412-itop-elite.dtb \
+        exynos4412-n710x.dtb \
         exynos4412-odroidu3.dtb \
         exynos4412-odroidx.dtb \
         exynos4412-odroidx2.dtb \
@@ -304,6 +307,8 @@ dtb-$(CONFIG_ARCH_LPC18XX) += \
 dtb-$(CONFIG_ARCH_LPC32XX) += \
         lpc3250-ea3250.dtb \
         lpc3250-phy3250.dtb
+dtb-$(CONFIG_ARCH_NPCM750) += \
+        nuvoton-npcm750-evb.dtb
 dtb-$(CONFIG_MACH_MESON6) += \
         meson6-atv1200.dtb
 dtb-$(CONFIG_MACH_MESON8) += \
@@ -396,6 +401,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
         imx6dl-icore-rqs.dtb \
         imx6dl-nit6xlite.dtb \
         imx6dl-nitrogen6x.dtb \
+        imx6dl-phytec-mira-rdk-nand.dtb \
         imx6dl-phytec-pbab01.dtb \
         imx6dl-rex-basic.dtb \
         imx6dl-riotboard.dtb \
@@ -435,6 +441,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
         imx6q-dfi-fs700-m60.dtb \
         imx6q-display5-tianma-tm070-1280x768.dtb \
         imx6q-dmo-edmqmx6.dtb \
+        imx6q-dms-ba16.dtb \
         imx6q-evi.dtb \
         imx6q-gk802.dtb \
         imx6q-gw51xx.dtb \
@@ -465,6 +472,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
         imx6q-nitrogen6_max.dtb \
         imx6q-nitrogen6_som2.dtb \
         imx6q-novena.dtb \
+        imx6q-phytec-mira-rdk-emmc.dtb \
+        imx6q-phytec-mira-rdk-nand.dtb \
         imx6q-phytec-pbab01.dtb \
         imx6q-pistachio.dtb \
         imx6q-rex-pro.dtb \
@@ -494,6 +503,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
         imx6q-zii-rdu2.dtb \
         imx6qp-nitrogen6_max.dtb \
         imx6qp-nitrogen6_som2.dtb \
+        imx6qp-phytec-mira-rdk-nand.dtb \
         imx6qp-sabreauto.dtb \
         imx6qp-sabresd.dtb \
         imx6qp-tx6qp-8037.dtb \
@@ -526,7 +536,9 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
         imx6ul-tx6ul-0010.dtb \
         imx6ul-tx6ul-0011.dtb \
         imx6ul-tx6ul-mainboard.dtb \
-        imx6ull-14x14-evk.dtb
+        imx6ull-14x14-evk.dtb \
+        imx6ull-colibri-eval-v3.dtb \
+        imx6ull-colibri-wifi-eval-v3.dtb
 dtb-$(CONFIG_SOC_IMX7D) += \
         imx7d-cl-som-imx7.dtb \
         imx7d-colibri-emmc-eval-v3.dtb \
@@ -673,6 +685,7 @@ dtb-$(CONFIG_SOC_AM33XX) += \
         am335x-lxm.dtb \
         am335x-moxa-uc-8100-me-t.dtb \
         am335x-nano.dtb \
+        am335x-pdu001.dtb \
         am335x-pepper.dtb \
         am335x-phycore-rdk.dtb \
         am335x-shc.dtb \
@@ -752,6 +765,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
         qcom-msm8960-cdp.dtb \
         qcom-msm8974-fairphone-fp2.dtb \
         qcom-msm8974-lge-nexus5-hammerhead.dtb \
+        qcom-msm8974-samsung-klte.dtb \
         qcom-msm8974-sony-xperia-castor.dtb \
         qcom-msm8974-sony-xperia-honami.dtb \
         qcom-mdm9615-wp8548-mangoh-green.dtb
@@ -784,6 +798,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
         r8a7778-bockw.dtb \
         r8a7779-marzen.dtb \
         r8a7790-lager.dtb \
+        r8a7790-stout.dtb \
         r8a7791-koelsch.dtb \
         r8a7791-porter.dtb \
         r8a7792-blanche.dtb \
@@ -863,7 +878,7 @@ dtb-$(CONFIG_ARCH_STI) += \
         stih410-b2120.dtb \
         stih410-b2260.dtb \
         stih418-b2199.dtb
-dtb-$(CONFIG_ARCH_STM32)+= \
+dtb-$(CONFIG_ARCH_STM32) += \
         stm32f429-disco.dtb \
         stm32f469-disco.dtb \
         stm32f746-disco.dtb \
@@ -871,7 +886,9 @@ dtb-$(CONFIG_ARCH_STM32)+= \
         stm32429i-eval.dtb \
         stm32746g-eval.dtb \
         stm32h743i-eval.dtb \
-        stm32h743i-disco.dtb
+        stm32h743i-disco.dtb \
+        stm32mp157c-ed1.dtb \
+        stm32mp157c-ev1.dtb
 dtb-$(CONFIG_MACH_SUN4I) += \
         sun4i-a10-a1000.dtb \
         sun4i-a10-ba10-tvbox.dtb \
@@ -942,6 +959,8 @@ dtb-$(CONFIG_MACH_SUN7I) += \
         sun7i-a20-m3.dtb \
         sun7i-a20-mk808c.dtb \
         sun7i-a20-olimex-som-evb.dtb \
+        sun7i-a20-olimex-som204-evb.dtb \
+        sun7i-a20-olimex-som204-evb-emmc.dtb \
         sun7i-a20-olinuxino-lime.dtb \
         sun7i-a20-olinuxino-lime2.dtb \
         sun7i-a20-olinuxino-lime2-emmc.dtb \
@@ -974,6 +993,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
         sun8i-a83t-cubietruck-plus.dtb \
         sun8i-a83t-tbs-a711.dtb \
         sun8i-h2-plus-orangepi-r1.dtb \
+        sun8i-h2-plus-bananapi-m2-zero.dtb \
         sun8i-h2-plus-orangepi-zero.dtb \
         sun8i-h3-bananapi-m2-plus.dtb \
         sun8i-h3-beelink-x2.dtb \
@@ -1022,6 +1042,7 @@ dtb-$(CONFIG_ARCH_TEGRA_114_SOC) += \
         tegra114-tn7.dtb
 dtb-$(CONFIG_ARCH_TEGRA_124_SOC) += \
         tegra124-apalis-eval.dtb \
+        tegra124-apalis-v1.2-eval.dtb \
         tegra124-jetson-tk1.dtb \
         tegra124-nyan-big.dtb \
         tegra124-nyan-blaze.dtb \
@@ -1047,6 +1068,7 @@ dtb-$(CONFIG_ARCH_UNIPHIER) += \
         uniphier-sld8-ref.dtb
 dtb-$(CONFIG_ARCH_VERSATILE) += \
         versatile-ab.dtb \
+        versatile-ab-ib2.dtb \
         versatile-pb.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += \
         vexpress-v2p-ca5s.dtb \
@@ -1062,12 +1084,18 @@ dtb-$(CONFIG_ARCH_VT8500) += \
         wm8750-apc8750.dtb \
         wm8850-w70v2.dtb
 dtb-$(CONFIG_ARCH_ZYNQ) += \
+        zynq-cc108.dtb \
         zynq-microzed.dtb \
         zynq-parallella.dtb \
         zynq-zc702.dtb \
         zynq-zc706.dtb \
+        zynq-zc770-xm010.dtb \
+        zynq-zc770-xm011.dtb \
+        zynq-zc770-xm012.dtb \
+        zynq-zc770-xm013.dtb \
         zynq-zed.dtb \
-        zynq-zybo.dtb
+        zynq-zybo.dtb \
+        zynq-zybo-z7.dtb
 dtb-$(CONFIG_MACH_ARMADA_370) += \
         armada-370-db.dtb \
         armada-370-dlink-dns327l.dtb \
@@ -1129,6 +1157,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
 dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
 dtb-$(CONFIG_ARCH_ASPEED) += \
         aspeed-ast2500-evb.dtb \
+        aspeed-bmc-arm-centriq2400-rep.dtb \
         aspeed-bmc-opp-palmetto.dtb \
         aspeed-bmc-opp-romulus.dtb \
         aspeed-bmc-opp-witherspoon.dtb \
diff --git a/arch/arm/boot/dts/am335x-boneblue.dts b/arch/arm/boot/dts/am335x-boneblue.dts
index 3f2480d05a3b..58baee158e64 100644
--- a/arch/arm/boot/dts/am335x-boneblue.dts
+++ b/arch/arm/boot/dts/am335x-boneblue.dts
@@ -342,7 +342,7 @@
         };
 
         baseboard_eeprom: baseboard_eeprom@50 {
-                compatible = "at,24c256";
+                compatible = "atmel,24c256";
                 reg = <0x50>;
 
                 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/am335x-pdu001.dts b/arch/arm/boot/dts/am335x-pdu001.dts
new file mode 100644
index 000000000000..1ad530a39a95
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-pdu001.dts
@@ -0,0 +1,595 @@
+/*
+ * pdu001.dts
+ *
+ * EETS GmbH PDU001 board device tree file
+ *
+ * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:  GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "am33xx.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/leds-pca9532.h>
+
+/ {
+        model = "EETS,PDU001";
+        compatible = "ti,am33xx";
+
+        chosen {
+                stdout-path = &uart3;
+        };
+
+        cpus {
+                cpu@0 {
+                        cpu0-supply = <&vdd1_reg>;
+                };
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x10000000>; /* 256 MB */
+        };
+
+        vbat: fixedregulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "vbat";
+                regulator-min-microvolt = <3600000>;
+                regulator-max-microvolt = <3600000>;
+                regulator-boot-on;
+        };
+
+        lis3_reg: fixedregulator@1 {
+                compatible = "regulator-fixed";
+                regulator-name = "lis3_reg";
+                regulator-boot-on;
+        };
+
+        panel {
+                compatible = "ti,tilcdc,panel";
+                status = "okay";
+                pinctrl-names = "default";
+                pinctrl-0 = <&lcd_pins_s0>;
+                panel-info {
+                        ac-bias           = <255>;
+                        ac-bias-intrpt    = <0>;
+                        dma-burst-sz      = <16>;
+                        bpp               = <16>;
+                        fdd               = <0x80>;
+                        sync-edge         = <0>;
+                        sync-ctrl         = <1>;
+                        raster-order      = <0>;
+                        fifo-th           = <0>;
+                };
+
+                display-timings {
+                        240x320p16 {
+                                clock-frequency = <6500000>;
+                                hactive = <240>;
+                                vactive = <320>;
+                                hfront-porch = <6>;
+                                hback-porch = <6>;
+                                hsync-len = <1>;
+                                vback-porch = <6>;
+                                vfront-porch = <6>;
+                                vsync-len = <1>;
+                                hsync-active = <0>;
+                                vsync-active = <0>;
+                                pixelclk-active = <1>;
+                                de-active = <0>;
+                        };
+                };
+        };
+};
+
+&am33xx_pinmux {
+        pinctrl-names = "default";
+        pinctrl-0 = <&clkout2_pin>;
+
+        i2c0_pins: pinmux_i2c0_pins {
+                pinctrl-single,pins = <
+                        AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)       /* i2c0_sda.i2c0_sda */
+                        AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)       /* i2c0_scl.i2c0_scl */
+                >;
+        };
+
+        i2c1_pins: pinmux_i2c1_pins {
+                pinctrl-single,pins = <
+                        AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE2)       /* spi0_d1.i2c1_sda */
+                        AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE2)       /* spi0_cs0.i2c1_scl */
+                >;
+        };
+
+        i2c2_pins: pinmux_i2c2_pins {
+                pinctrl-single,pins = <
+                        AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE2)       /* spi0_clk.i2c2_sda */
+                        AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE2)       /* spi0_d0.i2c2_scl */
+                >;
+        };
+
+        spi1_pins: pinmux_spi1_pins {
+                pinctrl-single,pins = <
+                        AM33XX_IOPAD(0x990, PIN_OUTPUT | MUX_MODE3)             /* mcasp0_aclkx.spi1_sclk */
+                        AM33XX_IOPAD(0x994, PIN_OUTPUT | MUX_MODE3)             /* mcasp0_fsx.spi1_d0 */
+                        AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE3)     /* mcasp0_axr0.spi1_d1 */
+                        AM33XX_IOPAD(0x99C, PIN_OUTPUT | MUX_MODE3)             /* mcasp0_ahclkr.spi1_cs0 */
+                >;
+        };
+
+        uart0_pins: pinmux_uart0_pins {
+                pinctrl-single,pins = <
+                        AM33XX_IOPAD(0x96C, PIN_OUTPUT | MUX_MODE7)             /* uart0_rtsn.gpio1_9 */
+                        AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart0_rxd.uart0_rxd */
+                        AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart0_txd.uart0_txd */
+                >;
+        };
+
+        uart1_pins: pinmux_uart1_pins {
+                pinctrl-single,pins = <
+                        AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart1_rxd.uart1_rxd */
+                        AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0)    /* uart1_txd.uart1_txd */
+                >;
+        };
+
+        uart3_pins: pinmux_uart3_pins {
+                pinctrl-single,pins = <
+                        AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE1)       /* spi0_cs1.uart3_rxd */
+                        AM33XX_IOPAD(0x964, PIN_OUTPUT_PULLDOWN | MUX_MODE1)    /* ecap0_in_pwm0_out.uart3_txd */
+                >;
+        };
+
+        clkout2_pin: pinmux_clkout2_pin {
+                pinctrl-single,pins = <
+                        AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3)    /* xdma_event_intr1.clkout2 */
+                >;
+        };
+
+        cpsw_default: cpsw_default {
+                pinctrl-single,pins = <
+                        /* Port 1 (emac0) */
+                        AM33XX_IOPAD(0x908, PIN_INPUT | MUX_MODE0)              /* mii1_col.mii1_col */
+                        AM33XX_IOPAD(0x90C, PIN_INPUT | MUX_MODE0)              /* mii1_crs.mii1_crs */
+                        AM33XX_IOPAD(0x910, PIN_INPUT | MUX_MODE0)              /* mii1_rxer.mii1_rxer */
+                        AM33XX_IOPAD(0x914, PIN_OUTPUT | MUX_MODE0)             /* mii1_txen.mii1_txen */
+                        AM33XX_IOPAD(0x918, PIN_INPUT | MUX_MODE0)              /* mii1_rxdv.mii1_rxdv */
+                        AM33XX_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE0)             /* mii1_txd3.mii1_txd3 */
+                        AM33XX_IOPAD(0x920, PIN_OUTPUT | MUX_MODE0)             /* mii1_txd2.mii1_txd2 */
+                        AM33XX_IOPAD(0x924, PIN_OUTPUT | MUX_MODE0)             /* mii1_txd1.mii1_txd1 */
+                        AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE0)             /* mii1_txd0.mii1_txd0 */
+                        AM33XX_IOPAD(0x92c, PIN_INPUT | MUX_MODE0)              /* mii1_txclk.mii1_txclk */
+                        AM33XX_IOPAD(0x930, PIN_INPUT | MUX_MODE0)              /* mii1_rxclk.mii1_rxclk */
+                        AM33XX_IOPAD(0x934, PIN_INPUT | MUX_MODE0)              /* mii1_rxd3.mii1_rxd3 */
+                        AM33XX_IOPAD(0x938, PIN_INPUT | MUX_MODE0)              /* mii1_rxd2.mii1_rxd2 */
+                        AM33XX_IOPAD(0x93c, PIN_INPUT | MUX_MODE0)              /* mii1_rxd1.mii1_rxd1 */
+                        AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE0)              /* mii1_rxd0.mii1_rxd0 */
+
+                        /* Port 2 (emac1) */
+                        AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE1)             /* mii2_txen.gpmc_a0 */
+                        AM33XX_IOPAD(0x844, PIN_INPUT | MUX_MODE1)              /* mii2_rxdv.gpmc_a1 */
+                        AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE1)             /* mii2_txd3.gpmc_a2 */
+                        AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE1)             /* mii2_txd2.gpmc_a3 */
+                        AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE1)             /* mii2_txd1.gpmc_a4 */
+                        AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE1)             /* mii2_txd0.gpmc_a5 */
+                        AM33XX_IOPAD(0x858, PIN_INPUT | MUX_MODE1)              /* mii2_txclk.gpmc_a6 */
+                        AM33XX_IOPAD(0x85c, PIN_INPUT | MUX_MODE1)              /* mii2_rxclk.gpmc_a7 */
+                        AM33XX_IOPAD(0x860, PIN_INPUT | MUX_MODE1)              /* mii2_rxd3.gpmc_a8 */
+                        AM33XX_IOPAD(0x864, PIN_INPUT | MUX_MODE1)              /* mii2_rxd2.gpmc_a9 */
+                        AM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE1)              /* mii2_rxd1.gpmc_a10 */
+                        AM33XX_IOPAD(0x86C, PIN_INPUT | MUX_MODE1)              /* mii2_rxd0.gpmc_a11 */
+                        AM33XX_IOPAD(0x870, PIN_INPUT | MUX_MODE1)              /* mii2_crs.gpmc_wait0 */
+                        AM33XX_IOPAD(0x874, PIN_INPUT | MUX_MODE1)              /* mii2_rxer.gpmc_wpn */
+                        AM33XX_IOPAD(0x878, PIN_INPUT | MUX_MODE1)              /* mii2_col.gpmc_ben1 */
+                >;
+        };
+
+        davinci_mdio_default: davinci_mdio_default {
+                pinctrl-single,pins = <
+                        AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)       /* mdio_data.mdio_data */
+                        AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)                      /* mdio_clk.mdio_clk */
+                >;
+        };
+
+        mmc1_pins: pinmux_mmc1_pins {
+                /* eMMC */
+                pinctrl-single,pins = <
+                        AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat3 */
+                        AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat2 */
+                        AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat1 */
+                        AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_dat0 */
+                        AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_clk */
+                        AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0)       /* mmc0_cmd */
+                >;
+        };
+
+        mmc2_pins: pinmux_mmc2_pins {
+                /* SD cardcage */
+                pinctrl-single,pins = <
+                        AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad3.mmc1_dat3 */
+                        AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad2.mmc1_dat2 */
+                        AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad1.mmc1_dat1 */
+                        AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1)       /* gpmc_ad0.mmc1_dat0 */
+                        AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2)       /* gpmc_csn1.mmc1_clk */
+                        AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2)       /* gpmc_csn2.mmc1_cmd */
+                        /* card change signal for frontpanel SD cardcage */
+                        AM33XX_IOPAD(0x890, PIN_INPUT | MUX_MODE7)              /* gpmc_advn_ale.gpio2_2 */
+                >;
+        };
+
+        lcd_pins_s0: lcd_pins_s0 {
+                pinctrl-single,pins = <
+                        AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0)             /* lcd_data0.lcd_data0 */
+                        AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0)             /* lcd_data1.lcd_data1 */
+                        AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0)             /* lcd_data2.lcd_data2 */
+                        AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0)             /* lcd_data3.lcd_data3 */
+                        AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0)             /* lcd_data4.lcd_data4 */
+                        AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0)             /* lcd_data5.lcd_data5 */
+                        AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0)             /* lcd_data6.lcd_data6 */
+                        AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0)             /* lcd_data7.lcd_data7 */
+                        AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0)             /* lcd_data8.lcd_data8 */
+                        AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0)             /* lcd_data9.lcd_data9 */
+                        AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0)             /* lcd_data10.lcd_data10 */
+                        AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0)             /* lcd_data11.lcd_data11 */
+                        AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0)             /* lcd_data12.lcd_data12 */
+                        AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0)             /* lcd_data13.lcd_data13 */
+                        AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0)             /* lcd_data14.lcd_data14 */
+                        AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0)             /* lcd_data15.lcd_data15 */
+                        AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0)             /* lcd_vsync.lcd_vsync */
+                        AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0)             /* lcd_hsync.lcd_hsync */
+                        AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0)             /* lcd_pclk.lcd_pclk */
+                        AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0)             /* lcd_ac_bias_en.lcd_ac_bias_en */
+                >;
+        };
+
+        dcan0_pins: pinmux_dcan0_pins {
+                pinctrl-single,pins = <
+                        AM33XX_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2)             /* uart1_ctsn.d_can0_tx */
+                        AM33XX_IOPAD(0x97c, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* uart1_rtsn.d_can0_rx */
+                >;
+        };
+};
+
+&uart0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart0_pins>;
+
+        rts-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+        rs485-rts-active-high;
+        rs485-rts-delay = <0 0>;
+        linux,rs485-enabled-at-boot-time;
+
+        status = "okay";
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart1_pins>;
+
+        status = "okay";
+};
+
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart3_pins>;
+
+        status = "okay";
+};
+
+&i2c0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c0_pins>;
+
+        status = "okay";
+        clock-frequency = <400000>;
+
+        tps: tps@2d {
+                reg = <0x2d>;
+        };
+
+        m2_eeprom: m2_eeprom@50 {
+                compatible = "atmel,24c256";
+                reg = <0x50>;
+                status = "okay";
+        };
+};
+
+&i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c1_pins>;
+
+        status = "okay";
+        clock-frequency = <100000>;
+
+        board_24aa025e48: board_24aa025e48@50 {
+                compatible = "atmel,24c02";
+                reg = <0x50>;
+        };
+
+        backplane_24aa025e48: backplane_24aa025e48@53 {
+                compatible = "atmel,24c02";
+                reg = <0x53>;
+        };
+
+        pca9532: pca9532@60 {
+                compatible = "nxp,pca9532";
+                reg = <0x60>;
+                psc0 = <0x97>;
+                pwm0 = <0x80>;
+                psc1 = <0x97>;
+                pwm1 = <0x10>;
+
+                run.red@0 {
+                        type = <PCA9532_TYPE_LED>;
+                };
+                run.green@1 {
+                        type = <PCA9532_TYPE_LED>;
+                        default-state = "on";
+                };
+                s2.red@2 {
+                        type = <PCA9532_TYPE_LED>;
+                };
+                s2.green@3 {
+                        type = <PCA9532_TYPE_LED>;
+                };
+                s1.yellow@4 {
+                        type = <PCA9532_TYPE_LED>;
+                };
+                s1.green@5 {
+                        type = <PCA9532_TYPE_LED>;
+                };
+        };
+
+        pca9530: pca9530@61 {
+                compatible = "nxp,pca9530";
+                reg = <0x61>;
+
+                tft-panel@0 {
+                        type = <PCA9532_TYPE_LED>;
+                        linux,default-trigger = "backlight";
+                        default-state = "on";
+                };
+        };
+
+        mcp79400: mcp79400@6f {
+                compatible = "microchip,mcp7940x";
+                reg = <0x6f>;
+        };
+};
+
+&i2c2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c2_pins>;
+
+        status = "okay";
+        clock-frequency = <100000>;
+};
+
+&spi1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&spi1_pins>;
+        ti,pindir-d0-out-d1-in;
+        status = "okay";
+
+        cfaf240320a032t {
+                compatible = "orisetech,otm3225a";
+                reg = <0>;
+                spi-max-frequency = <1000000>;
+                // SPI mode 3
+                spi-cpol;
+                spi-cpha;
+                status = "okay";
+        };
+};
+
+&usb {
+        status = "okay";
+};
+
+&usb_ctrl_mod {
+        status = "okay";
+};
+
+&usb0_phy {
+        status = "okay";
+};
+
+&usb1_phy {
+        status = "okay";
+};
+
+&usb0 {
+        status = "okay";
+};
+
+&usb1 {
+        status = "okay";
+};
+
+&cppi41dma  {
+        status = "okay";
+};
+
+/*
+ * Disable soc's rtc as we have no VBAT for it. This makes the board
+ * rtc (Microchip MCP79400) the default rtc device 'rtc0'.
+ */
+&rtc {
+        status = "disabled";
+};
+
+&lcdc {
+        status = "okay";
+};
+
+&elm {
+        status = "okay";
+};
+
+#include "tps65910.dtsi"
+
+&tps {
+        vcc1-supply = <&vbat>;
+        vcc2-supply = <&vbat>;
+        vcc3-supply = <&vbat>;
+        vcc4-supply = <&vbat>;
+        vcc5-supply = <&vbat>;
+        vcc6-supply = <&vbat>;
+        vcc7-supply = <&vbat>;
+        vccio-supply = <&vbat>;
+
+        regulators {
+                vrtc_reg: regulator@0 {
+                        regulator-name = "ldo_vrtc";
+                        regulator-always-on;
+                };
+
+                vio_reg: regulator@1 {
+                        regulator-name = "buck_vdd_ddr";
+                        regulator-always-on;
+                };
+
+                vdd1_reg: regulator@2 {
+                        /* VDD_MPU voltage limits */
+                        regulator-name = "buck_vdd_mpu";
+                        regulator-min-microvolt = <912500>;
+                        regulator-max-microvolt = <1312500>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+
+                vdd2_reg: regulator@3 {
+                        /* VDD_CORE voltage limits */
+                        regulator-name = "buck_vdd_core";
+                        regulator-min-microvolt = <912500>;
+                        regulator-max-microvolt = <1150000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+
+                vdd3_reg: regulator@4 {
+                        regulator-name = "boost_res";
+                        regulator-always-on;
+                };
+
+                vdig1_reg: regulator@5 {
+                        regulator-name = "ldo_vdig1";
+                        regulator-always-on;
+                };
+
+                vdig2_reg: regulator@6 {
+                        regulator-name = "ldo_vdig2";
+                        regulator-always-on;
+                };
+
+                vpll_reg: regulator@7 {
+                        regulator-name = "ldo_vpll";
+                        regulator-always-on;
+                };
+
+                vdac_reg: regulator@8 {
+                        regulator-name = "ldo_vdac";
+                        regulator-always-on;
+                };
+
+                vaux1_reg: regulator@9 {
+                        regulator-name = "ldo_vaux1";
+                        regulator-always-on;
+                };
+
+                vaux2_reg: regulator@10 {
+                        regulator-name = "ldo_vaux2";
+                        regulator-always-on;
+                };
+
+                vaux33_reg: regulator@11 {
+                        regulator-name = "ldo_vaux33";
+                        regulator-always-on;
+                };
+
+                vmmc_reg: regulator@12 {
+                        regulator-name = "ldo_vmmc";
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
+
+                vbb_reg: regulator@13 {
+                        regulator-name = "bat_vbb";
+                };
+        };
+};
+
+&mac {
+        pinctrl-names = "default";
+        pinctrl-0 = <&cpsw_default>;
+        dual_emac;                      /* no switch, two distinct MACs */
+        status = "okay";
+};
+
+&davinci_mdio {
+        pinctrl-names = "default";
+        pinctrl-0 = <&davinci_mdio_default>;
+        status = "okay";
+};
+
+&cpsw_emac0 {
+        phy_id = <&davinci_mdio>, <0>;
+        phy-mode = "mii";
+        dual_emac_res_vlan = <1>;
+};
+
+&cpsw_emac1 {
+        phy_id = <&davinci_mdio>, <1>;
+        phy-mode = "mii";
+        dual_emac_res_vlan = <2>;
+};
+
+&tscadc {
+        status = "okay";
+        tsc {
+                ti,wires = <4>;
+                ti,x-plate-resistance = <200>;
+                ti,coordinate-readouts = <5>;
+                ti,wire-config = <0x01 0x10 0x22 0x33>;
+                ti,charge-delay = <0x400>;
+        };
+
+        adc {
+                ti,adc-channels = <4 5 6 7>;
+        };
+};
+
+&mmc1 {
+        status = "okay";
+        vmmc-supply = <&vmmc_reg>;
+        bus-width = <4>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc1_pins>;
+        non-removable;
+};
+
+&mmc2 {
+        status = "okay";
+        vmmc-supply = <&vmmc_reg>;
+        bus-width = <4>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc2_pins>;
+        cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
+};
+
+&sham {
+        status = "okay";
+};
+
+&aes {
+        status = "okay";
+};
+
+&dcan0 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&dcan0_pins>;
+};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 628c77b0b386..9cd62bc2ca35 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -147,6 +147,8 @@
                 mpu {
                         compatible = "ti,omap3-mpu";
                         ti,hwmods = "mpu";
+                        pm-sram = <&pm_sram_code
+                                   &pm_sram_data>;
                 };
         };
 
@@ -905,6 +907,21 @@
                 ocmcram: ocmcram@40300000 {
                         compatible = "mmio-sram";
                         reg = <0x40300000 0x10000>; /* 64k */
+                        ranges = <0x0 0x40300000 0x10000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        pm_sram_code: pm-sram-code@0 {
+                                compatible = "ti,sram";
+                                reg = <0x0 0x1000>;
+                                protect-exec;
+                        };
+
+                        pm_sram_data: pm-sram-data@1000 {
+                                compatible = "ti,sram";
+                                reg = <0x1000 0x1000>;
+                                pool;
+                        };
                 };
 
                 elm: elm@48080000 {
@@ -945,6 +962,10 @@
                         compatible = "ti,emif-am3352";
                         reg = <0x4c000000 0x1000000>;
                         ti,hwmods = "emif";
+                        interrupts = <101>;
+                        sram = <&pm_sram_code
+                                &pm_sram_data>;
+                        ti,no-idle;
                 };
 
                 gpmc: gpmc@50000000 {
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 964f3ef79728..f0cbd86312dc 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -92,6 +92,16 @@
                 };
         };
 
+        soc {
+                compatible = "ti,omap-infra";
+                mpu {
+                        compatible = "ti,omap4-mpu";
+                        ti,hwmods = "mpu";
+                        pm-sram = <&pm_sram_code
+                                   &pm_sram_data>;
+                };
+        };
+
         gic: interrupt-controller@48241000 {
                 compatible = "arm,cortex-a9-gic";
                 interrupt-controller;
@@ -143,6 +153,7 @@
                 #size-cells = <1>;
                 ranges;
                 ti,hwmods = "l3_main";
+                ti,no-idle;
                 reg = <0x44000000 0x400000
                        0x44800000 0x400000>;
                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
@@ -237,6 +248,10 @@
                         compatible = "ti,emif-am4372";
                         reg = <0x4c000000 0x1000000>;
                         ti,hwmods = "emif";
+                        interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+                        ti,no-idle;
+                        sram = <&pm_sram_code
+                                &pm_sram_data>;
                 };
 
                 edma: edma@49000000 {
@@ -1141,6 +1156,21 @@
                 ocmcram: ocmcram@40300000 {
                         compatible = "mmio-sram";
                         reg = <0x40300000 0x40000>; /* 256k */
+                        ranges = <0x0 0x40300000 0x40000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        pm_sram_code: pm-sram-code@0 {
+                                compatible = "ti,sram";
+                                reg = <0x0 0x1000>;
+                                protect-exec;
+                        };
+
+                        pm_sram_data: pm-sram-data@1000 {
+                                compatible = "ti,sram";
+                                reg = <0x1000 0x1000>;
+                                pool;
+                        };
                 };
 
                 dcan0: can@481cc000 {
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
index c3b1a3fb5a2e..8fe95cd7232a 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -805,7 +805,7 @@
 };
 
 &usb1 {
-        dr_mode = "peripheral";
+        dr_mode = "otg";
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts
index 3fa3b226995d..4118802b7fea 100644
--- a/arch/arm/boot/dts/am437x-sk-evm.dts
+++ b/arch/arm/boot/dts/am437x-sk-evm.dts
@@ -600,7 +600,7 @@
 };
 
 &usb1 {
-        dr_mode = "peripheral";
+        dr_mode = "otg";
         status = "okay";
         pinctrl-names = "default";
         pinctrl-0 = <&usb1_pins>;
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index 00c3d1de384f..a66941885c11 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -856,7 +856,7 @@
 };
 
 &usb1 {
-        dr_mode = "peripheral";
+        dr_mode = "otg";
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/am571x-idk.dts b/arch/arm/boot/dts/am571x-idk.dts
index 6d3c83743156..a2555140babc 100644
--- a/arch/arm/boot/dts/am571x-idk.dts
+++ b/arch/arm/boot/dts/am571x-idk.dts
@@ -10,8 +10,8 @@
 #include "dra72x.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
-#include "am57xx-idk-common.dtsi"
 #include "dra72x-mmc-iodelay.dtsi"
+#include "am57xx-idk-common.dtsi"
 
 / {
         model = "TI AM5718 IDK";
diff --git a/arch/arm/boot/dts/am572x-idk.dts b/arch/arm/boot/dts/am572x-idk.dts
index 9ab0af5017df..3a02ed720957 100644
--- a/arch/arm/boot/dts/am572x-idk.dts
+++ b/arch/arm/boot/dts/am572x-idk.dts
@@ -9,9 +9,8 @@
 /dts-v1/;
 
 #include "dra74x.dtsi"
-#include "am572x-idk-common.dtsi"
-#include "am57xx-idk-common.dtsi"
 #include "dra74x-mmc-iodelay.dtsi"
+#include "am572x-idk-common.dtsi"
 
 / {
         model = "TI AM5728 IDK";
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
index ab60035bc50c..6204a266212a 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
+++ b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
@@ -442,6 +442,7 @@
         pinctrl-0 = <&mmc2_pins_default>;
 
         vmmc-supply = <&vdd_3v3>;
+        vqmmc-supply = <&vdd_3v3>;
         bus-width = <8>;
         ti,non-removable;
         cap-mmc-dual-data-rate;
diff --git a/arch/arm/boot/dts/am57xx-idk-common.dtsi b/arch/arm/boot/dts/am57xx-idk-common.dtsi
index 97aa8e6a56da..43cdf523a8a0 100644
--- a/arch/arm/boot/dts/am57xx-idk-common.dtsi
+++ b/arch/arm/boot/dts/am57xx-idk-common.dtsi
@@ -115,6 +115,17 @@
                         DRA7XX_CORE_IOPAD(0x37d4, MUX_MODE15 | PULL_UP) /* dcan1_rx.off */
                 >;
         };
+
+        mmc1_pins_default: mmc1_pins_default {
+                pinctrl-single,pins = <
+                        DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mmc1_clk.clk */
+                        DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+                        DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+                        DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+                        DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+                        DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+                >;
+        };
 };
 
 &i2c1 {
@@ -410,6 +421,7 @@
 &mmc2 {
         status = "okay";
         vmmc-supply = <&v3_3d>;
+        vqmmc-supply = <&v3_3d>;
         bus-width = <8>;
         ti,non-removable;
         max-frequency = <96000000>;
diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts
index b67a75179784..d7c841932701 100644
--- a/arch/arm/boot/dts/animeo_ip.dts
+++ b/arch/arm/boot/dts/animeo_ip.dts
@@ -24,7 +24,7 @@
         };
 
         chosen {
-                linux,stdout-path = &usart2;
+                stdout-path = &usart2;
         };
 
         memory {
diff --git a/arch/arm/boot/dts/arm-realview-eb.dtsi b/arch/arm/boot/dts/arm-realview-eb.dtsi
index e2e9599596e2..a917cf8825ca 100644
--- a/arch/arm/boot/dts/arm-realview-eb.dtsi
+++ b/arch/arm/boot/dts/arm-realview-eb.dtsi
@@ -143,6 +143,43 @@
                 port1-otg;
         };
 
+        bridge {
+                compatible = "ti,ths8134a", "ti,ths8134";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@0 {
+                                reg = <0>;
+
+                                vga_bridge_in: endpoint {
+                                        remote-endpoint = <&clcd_pads>;
+                                };
+                        };
+
+                        port@1 {
+                                reg = <1>;
+
+                                vga_bridge_out: endpoint {
+                                        remote-endpoint = <&vga_con_in>;
+                                };
+                        };
+                };
+        };
+
+        vga {
+                compatible = "vga-connector";
+
+                port {
+                        vga_con_in: endpoint {
+                                remote-endpoint = <&vga_bridge_out>;
+                        };
+                };
+        };
+
         /* These peripherals are inside the FPGA */
         fpga {
                 #address-cells = <1>;
@@ -409,36 +446,15 @@
                         interrupt-names = "combined";
                         clocks = <&oscclk0>, <&pclk>;
                         clock-names = "clcdclk", "apb_pclk";
+                        /* 1024x768 16bpp @65MHz works fine */
+                        max-memory-bandwidth = <95000000>;
 
                         port {
                                 clcd_pads: endpoint {
-                                        remote-endpoint = <&clcd_panel>;
+                                        remote-endpoint = <&vga_bridge_in>;
                                         arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
                                 };
                         };
-
-                        panel {
-                                compatible = "panel-dpi";
-
-                                port {
-                                        clcd_panel: endpoint {
-                                                remote-endpoint = <&clcd_pads>;
-                                        };
-                                };
-
-                                /* Standard 640x480 VGA timings */
-                                panel-timing {
-                                        clock-frequency = <25175000>;
-                                        hactive = <640>;
-                                        hback-porch = <48>;
-                                        hfront-porch = <16>;
-                                        hsync-len = <96>;
-                                        vactive = <480>;
-                                        vback-porch = <33>;
-                                        vfront-porch = <10>;
-                                        vsync-len = <2>;
-                                };
-                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/arm-realview-pb1176.dts b/arch/arm/boot/dts/arm-realview-pb1176.dts
index c789564f2803..f935b72d3d96 100644
--- a/arch/arm/boot/dts/arm-realview-pb1176.dts
+++ b/arch/arm/boot/dts/arm-realview-pb1176.dts
@@ -161,6 +161,43 @@
                 port1-otg;
         };
 
+        bridge {
+                compatible = "ti,ths8134a", "ti,ths8134";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@0 {
+                                reg = <0>;
+
+                                vga_bridge_in: endpoint {
+                                        remote-endpoint = <&clcd_pads>;
+                                };
+                        };
+
+                        port@1 {
+                                reg = <1>;
+
+                                vga_bridge_out: endpoint {
+                                        remote-endpoint = <&vga_con_in>;
+                                };
+                        };
+                };
+        };
+
+        vga {
+                compatible = "vga-connector";
+
+                port {
+                        vga_con_in: endpoint {
+                                remote-endpoint = <&vga_bridge_out>;
+                        };
+                };
+        };
+
         soc {
                 #address-cells = <1>;
                 #size-cells = <1>;
@@ -403,36 +440,15 @@
                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&oscclk0>, <&pclk>;
                         clock-names = "clcdclk", "apb_pclk";
+                        /* 1024x768 16bpp @65MHz works fine */
+                        max-memory-bandwidth = <95000000>;
 
                         port {
                                 clcd_pads: endpoint {
-                                        remote-endpoint = <&clcd_panel>;
+                                        remote-endpoint = <&vga_bridge_in>;
                                         arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
                                 };
                         };
-
-                        panel {
-                                compatible = "panel-dpi";
-
-                                port {
-                                        clcd_panel: endpoint {
-                                                remote-endpoint = <&clcd_pads>;
-                                        };
-                                };
-
-                                /* Standard 640x480 VGA timings */
-                                panel-timing {
-                                        clock-frequency = <25175000>;
-                                        hactive = <640>;
-                                        hback-porch = <48>;
-                                        hfront-porch = <16>;
-                                        hsync-len = <96>;
-                                        vactive = <480>;
-                                        vback-porch = <33>;
-                                        vfront-porch = <10>;
-                                        vsync-len = <2>;
-                                };
-                        };
                 };
         };
 
@@ -564,7 +580,5 @@
                         clocks = <&pclk>;
                         clock-names = "apb_pclk";
                 };
-
-
         };
 };
diff --git a/arch/arm/boot/dts/arm-realview-pb11mp.dts b/arch/arm/boot/dts/arm-realview-pb11mp.dts
index 3944765ac4b0..36203288de42 100644
--- a/arch/arm/boot/dts/arm-realview-pb11mp.dts
+++ b/arch/arm/boot/dts/arm-realview-pb11mp.dts
@@ -242,6 +242,49 @@
                 bank-width = <4>;
         };
 
+        bridge {
+                compatible = "ti,ths8134a", "ti,ths8134";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@0 {
+                                reg = <0>;
+
+                                vga_bridge_in: endpoint {
+                                        remote-endpoint = <&clcd_pads>;
+                                };
+                        };
+
+                        port@1 {
+                                reg = <1>;
+
+                                vga_bridge_out: endpoint {
+                                        remote-endpoint = <&vga_con_in>;
+                                };
+                        };
+                };
+        };
+
+        vga {
+                /*
+                 * This DDC I2C is connected directly to the DVI portions
+                 * of the connector, so it's not really working when the
+                 * monitor is connected to the VGA connector.
+                 */
+                compatible = "vga-connector";
+                ddc-i2c-bus = <&i2c1>;
+
+                port {
+                        vga_con_in: endpoint {
+                                remote-endpoint = <&vga_bridge_out>;
+                        };
+                };
+        };
+
         soc {
                 #address-cells = <1>;
                 #size-cells = <1>;
@@ -575,6 +618,13 @@
                         clock-names = "apb_pclk";
                 };
 
+                i2c1: i2c@10016000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "arm,versatile-i2c";
+                        reg = <0x10016000 0x1000>;
+                };
+
                 rtc: rtc@10017000 {
                         compatible = "arm,pl031", "arm,primecell";
                         reg = <0x10017000 0x1000>;
@@ -609,37 +659,15 @@
                         interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&oscclk4>, <&pclk>;
                         clock-names = "clcdclk", "apb_pclk";
-                        max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */
+                        /* 1024x768 16bpp @65MHz works fine */
+                        max-memory-bandwidth = <95000000>;
 
                         port {
                                 clcd_pads: endpoint {
-                                        remote-endpoint = <&clcd_panel>;
+                                        remote-endpoint = <&vga_bridge_in>;
                                         arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
                                 };
                         };
-
-                        panel {
-                                compatible = "panel-dpi";
-
-                                port {
-                                        clcd_panel: endpoint {
-                                                remote-endpoint = <&clcd_pads>;
-                                        };
-                                };
-
-                                /* Standard 640x480 VGA timings */
-                                panel-timing {
-                                        clock-frequency = <25175000>;
-                                        hactive = <640>;
-                                        hback-porch = <48>;
-                                        hfront-porch = <16>;
-                                        hsync-len = <96>;
-                                        vactive = <480>;
-                                        vback-porch = <33>;
-                                        vfront-porch = <10>;
-                                        vsync-len = <2>;
-                                };
-                        };
                 };
 
                 /*
diff --git a/arch/arm/boot/dts/arm-realview-pbx.dtsi b/arch/arm/boot/dts/arm-realview-pbx.dtsi
index aeb49c4bd773..10868ba3277f 100644
--- a/arch/arm/boot/dts/arm-realview-pbx.dtsi
+++ b/arch/arm/boot/dts/arm-realview-pbx.dtsi
@@ -34,7 +34,8 @@
                 serial1 = &serial1;
                 serial2 = &serial2;
                 serial3 = &serial3;
-                i2c0 = &i2c;
+                i2c0 = &i2c0;
+                i2c1 = &i2c1;
         };
 
         memory {
@@ -158,6 +159,49 @@
                 port1-otg;
         };
 
+        bridge {
+                compatible = "ti,ths8134a", "ti,ths8134";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@0 {
+                                reg = <0>;
+
+                                vga_bridge_in: endpoint {
+                                        remote-endpoint = <&clcd_pads>;
+                                };
+                        };
+
+                        port@1 {
+                                reg = <1>;
+
+                                vga_bridge_out: endpoint {
+                                        remote-endpoint = <&vga_con_in>;
+                                };
+                        };
+                };
+        };
+
+        vga {
+                /*
+                 * This DDC I2C is connected directly to the DVI portions
+                 * of the connector, so it's not really working when the
+                 * monitor is connected to the VGA connector.
+                 */
+                compatible = "vga-connector";
+                ddc-i2c-bus = <&i2c1>;
+
+                port {
+                        vga_con_in: endpoint {
+                                remote-endpoint = <&vga_bridge_out>;
+                        };
+                };
+        };
+
         soc: soc@0 {
                 compatible = "arm,realview-pbx-soc", "simple-bus";
                 #address-cells = <1>;
@@ -285,7 +329,7 @@
                                                <&timclk>;
                 };
 
-                i2c: i2c@10002000 {
+                i2c0: i2c@10002000 {
                         #address-cells = <1>;
                         #size-cells = <0>;
                         compatible = "arm,versatile-i2c";
@@ -396,7 +440,12 @@
                         clock-names = "apb_pclk";
                 };
 
-                /* DVI serial bus control is at 10016000 */
+                i2c1: i2c@10016000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "arm,versatile-i2c";
+                        reg = <0x10016000 0x1000>;
+                };
 
                 rtc: rtc@10017000 {
                         compatible = "arm,pl031", "arm,primecell";
@@ -506,36 +555,15 @@
                         interrupt-names = "combined";
                         clocks = <&oscclk4>, <&pclk>;
                         clock-names = "clcdclk", "apb_pclk";
+                        /* 1024x768 16bpp @65MHz works fine */
+                        max-memory-bandwidth = <95000000>;
 
                         port {
                                 clcd_pads: endpoint {
-                                        remote-endpoint = <&clcd_panel>;
+                                        remote-endpoint = <&vga_bridge_in>;
                                         arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
                                 };
                         };
-
-                        panel {
-                                compatible = "panel-dpi";
-
-                                port {
-                                        clcd_panel: endpoint {
-                                                remote-endpoint = <&clcd_pads>;
-                                        };
-                                };
-
-                                /* Standard 640x480 VGA timings */
-                                panel-timing {
-                                        clock-frequency = <25175000>;
-                                        hactive = <640>;
-                                        hback-porch = <48>;
-                                        hfront-porch = <16>;
-                                        hsync-len = <96>;
-                                        vactive = <480>;
-                                        vback-porch = <33>;
-                                        vfront-porch = <10>;
-                                        vsync-len = <2>;
-                                };
-                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/artpec6-devboard.dts b/arch/arm/boot/dts/artpec6-devboard.dts
index 9dfe845694cf..d20d95359b28 100644
--- a/arch/arm/boot/dts/artpec6-devboard.dts
+++ b/arch/arm/boot/dts/artpec6-devboard.dts
@@ -26,7 +26,7 @@
 
         memory {
                 device_type = "memory";
-                reg = <0x0 0x10000000>;
+                reg = <0x0 0x40000000>;
         };
 };
 
@@ -59,6 +59,7 @@
         mdio {
                 #address-cells = <0x1>;
                 #size-cells = <0x0>;
+                compatible = "snps,dwmac-mdio";
                 phy1: phy@0 {
                         compatible = "ethernet-phy-ieee802.3-c22";
                         device_type = "ethernet-phy";
diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm/boot/dts/artpec6.dtsi
index 2ed11773048d..3e4115c2cd75 100644
--- a/arch/arm/boot/dts/artpec6.dtsi
+++ b/arch/arm/boot/dts/artpec6.dtsi
@@ -41,6 +41,7 @@
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/dma/nbpfaxi.h>
 #include <dt-bindings/clock/axis,artpec6-clkctrl.h>
 #include "skeleton.dtsi"
 
@@ -98,7 +99,7 @@
                 clock-frequency = <125000000>;
         };
 
-        clkctrl: clkctrl@0xf8000000 {
+        clkctrl: clkctrl@f8000000 {
                 #clock-cells = <1>;
                 compatible = "axis,artpec6-clkctrl";
                 reg = <0xf8000000 0x48>;
@@ -153,6 +154,10 @@
                 interrupt-affinity = <&cpu0>, <&cpu1>;
         };
 
+        /*
+         * Both pci nodes cannot be enabled at the same time,
+         * leave the unwanted node as disabled.
+         */
         pcie: pcie@f8050000 {
                 compatible = "axis,artpec6-pcie", "snps,dw-pcie";
                 reg = <0xf8050000 0x2000
@@ -180,28 +185,146 @@
                 status = "disabled";
         };
 
+        pcie_ep: pcie_ep@f8050000 {
+                compatible = "axis,artpec6-pcie-ep", "snps,dw-pcie";
+                reg = <0xf8050000 0x2000
+                       0xf8051000 0x2000
+                       0xf8040000 0x1000
+                       0xc0000000 0x20000000>;
+                reg-names = "dbi", "dbi2", "phy", "addr_space";
+                num-ib-windows = <6>;
+                num-ob-windows = <2>;
+                num-lanes = <2>;
+                axis,syscon-pcie = <&syscon>;
+                status = "disabled";
+        };
+
+        pinctrl: pinctrl@f801d000 {
+                compatible = "axis,artpec6-pinctrl";
+                reg = <0xf801d000 0x400>;
+
+                pinctrl_uart0: uart0grp {
+                        function = "uart0";
+                        groups = "uart0grp2";
+                        bias-pull-up;
+                };
+                pinctrl_uart1: uart1grp {
+                        function = "uart1";
+                        groups = "uart1grp0";
+                        bias-pull-up;
+                };
+                pinctrl_uart2: uart2grp {
+                        function = "uart2";
+                        groups = "uart2grp1";
+                        bias-pull-up;
+                };
+                pinctrl_uart3: uart3grp {
+                        function = "uart3";
+                        groups = "uart3grp0";
+                        bias-pull-up;
+                };
+        };
+
         amba@0 {
                 compatible = "simple-bus";
                 #address-cells = <0x1>;
                 #size-cells = <0x1>;
                 ranges;
-                dma-ranges = <0x80000000 0x00000000 0x40000000>;
-                dma-coherent;
+                dma-ranges;
+
+                crypto@f4264000 {
+                        compatible = "axis,artpec6-crypto";
+                        reg = <0xf4264000 0x4000>;
+                        interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+                };
+
+                dma0: dma@f8019000 {
+                        compatible = "renesas,nbpfaxi64dmac8b16";
+                        reg = <0xf8019000 0x400>;
+                        interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* error */
+                                     <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "error",
+                                          "ch0", "ch1", "ch2", "ch3",
+                                          "ch4", "ch5", "ch6", "ch7",
+                                          "ch8", "ch9", "ch10", "ch12",
+                                          "ch12", "ch13", "ch14", "ch15";
+                        clocks = <&clkctrl ARTPEC6_CLK_DMA_ACLK>;
+                        #dma-cells = <2>;
+                        dma-channels = <8>;
+                        dma-requests = <8>;
+                };
+                dma1: dma@f8019400 {
+                        compatible = "renesas,nbpfaxi64dmac8b16";
+                        reg = <0xf8019400 0x400>;
+                        interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* error */
+                                     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "error",
+                                          "ch0", "ch1", "ch2", "ch3",
+                                          "ch4", "ch5", "ch6", "ch7",
+                                          "ch8", "ch9", "ch10", "ch12",
+                                          "ch12", "ch13", "ch14", "ch15";
+                        clocks = <&clkctrl ARTPEC6_CLK_DMA_ACLK>;
+                        #dma-cells = <2>;
+                        dma-channels = <8>;
+                        dma-requests = <8>;
+                };
 
                 ethernet: ethernet@f8010000 {
-                        clock-names = "phy_ref_clk", "apb_pclk";
-                        clocks = <&eth_phy_ref_clk>,
-                                <&clkctrl ARTPEC6_CLK_ETH_ACLK>;
-                        compatible = "snps,dwc-qos-ethernet-4.10";
-                        interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+                        clock-names = "stmmaceth", "ptp_ref";
+                        clocks = <&clkctrl ARTPEC6_CLK_ETH_ACLK>,
+                                <&clkctrl ARTPEC6_CLK_PTP_REF>;
+                        compatible = "snps,dwmac-4.10a", "snps,dwmac";
+                        interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "macirq", "eth_lpi";
                         reg = <0xf8010000 0x4000>;
 
-                        snps,write-requests = <2>;
-                        snps,read-requests = <16>;
+                        snps,axi-config = <&stmmac_axi_setup>;
+                        snps,mtl-rx-config = <&mtl_rx_setup>;
+                        snps,mtl-tx-config = <&mtl_tx_setup>;
+
                         snps,txpbl = <8>;
                         snps,rxpbl = <2>;
+                        snps,aal;
+                        snps,tso;
 
                         status = "disabled";
+
+                        stmmac_axi_setup: stmmac-axi-config {
+                                snps,wr_osr_lmt = <1>;
+                                snps,rd_osr_lmt = <15>;
+                                /* If FB is disabled, the AXI master chooses
+                                 * a burst length of any value less than the
+                                 * maximum enabled burst length
+                                 * (all lesser burst length enables are redundant).
+                                 */
+                                snps,blen = <0 0 0 0 16 0 0>;
+                        };
+
+                        mtl_rx_setup: rx-queues-config {
+                                snps,rx-queues-to-use = <1>;
+                                queue0 {};
+                        };
+
+                        mtl_tx_setup: tx-queues-config {
+                                snps,tx-queues-to-use = <2>;
+                                queue0 {};
+                                queue1 {};
+                        };
                 };
 
                 uart0: serial@f8036000 {
@@ -211,6 +334,11 @@
                         clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
                                 <&clkctrl ARTPEC6_CLK_UART_PCLK>;
                         clock-names = "uart_clk", "apb_pclk";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_uart0>;
+                        dmas = <&dma0 4 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>,
+                               <&dma0 5 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>;
+                        dma-names = "rx", "tx";
                         status = "disabled";
                 };
                 uart1: serial@f8037000 {
@@ -220,6 +348,11 @@
                         clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
                                 <&clkctrl ARTPEC6_CLK_UART_PCLK>;
                         clock-names = "uart_clk", "apb_pclk";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_uart1>;
+                        dmas = <&dma0 6 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>,
+                               <&dma0 7 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>;
+                        dma-names = "rx", "tx";
                         status = "disabled";
                 };
                 uart2: serial@f8038000 {
@@ -229,6 +362,11 @@
                         clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
                                 <&clkctrl ARTPEC6_CLK_UART_PCLK>;
                         clock-names = "uart_clk", "apb_pclk";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_uart2>;
+                        dmas = <&dma1 0 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>,
+                               <&dma1 1 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>;
+                        dma-names = "rx", "tx";
                         status = "disabled";
                 };
                 uart3: serial@f8039000 {
@@ -238,6 +376,11 @@
                         clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
                                 <&clkctrl ARTPEC6_CLK_UART_PCLK>;
                         clock-names = "uart_clk", "apb_pclk";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_uart3>;
+                        dmas = <&dma1 2 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>,
+                               <&dma1 3 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>;
+                        dma-names = "rx", "tx";
                         status = "disabled";
                 };
         };
diff --git a/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts b/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts
new file mode 100644
index 000000000000..df1227613d48
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-arm-centriq2400-rep.dts
@@ -0,0 +1,225 @@
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+
+#include "aspeed-g5.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+
+/ {
+        model = "Qualcomm Centriq 2400  REP AST2520";
+        compatible = "qualcomm,centriq2400-rep-bmc", "aspeed,ast2500";
+
+        chosen {
+                stdout-path = &uart5;
+                bootargs = "console=ttyS4,115200 earlyprintk";
+        };
+
+        memory {
+                reg = <0x80000000 0x40000000>;
+        };
+
+        iio-hwmon {
+                compatible = "iio-hwmon";
+                io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
+                        <&adc 4>, <&adc 5>, <&adc 6>, <&adc 8>;
+        };
+
+        iio-hwmon-battery {
+                compatible = "iio-hwmon";
+                io-channels = <&adc 7>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                uid_led {
+                        label = "UID_LED";
+                        gpios = <&gpio ASPEED_GPIO(Q, 5) GPIO_ACTIVE_LOW>;
+                };
+
+                ras_error_led {
+                        label = "RAS_ERROR_LED";
+                        gpios = <&gpio ASPEED_GPIO(F, 6) GPIO_ACTIVE_LOW>;
+                };
+
+                system_fault {
+                        label = "System_fault";
+                        gpios = <&gpio ASPEED_GPIO(A, 1) GPIO_ACTIVE_LOW>;
+                };
+        };
+};
+
+&fmc {
+        status = "okay";
+        flash@0 {
+                status = "okay";
+                m25p,fast-read;
+                label = "bmc";
+#include "openbmc-flash-layout.dtsi"
+        };
+};
+
+&spi1 {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_spi1_default>;
+        flash@0 {
+                status = "okay";
+        };
+};
+
+&spi2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_spi2ck_default
+                        &pinctrl_spi2miso_default
+                        &pinctrl_spi2mosi_default
+                        &pinctrl_spi2cs0_default>;
+};
+
+&uart3 {
+        status = "okay";
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>;
+        current-speed = <115200>;
+};
+
+&uart5 {
+        status = "okay";
+};
+
+&mac0 {
+        status = "okay";
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>;
+};
+
+&i2c0 {
+        status = "okay";
+};
+
+&i2c1 {
+        status = "okay";
+
+        tmp421@1e {
+                compatible = "ti,tmp421";
+                reg = <0x1e>;
+        };
+        tmp421@2a {
+                compatible = "ti,tmp421";
+                reg = <0x2a>;
+        };
+        tmp421@4e {
+                compatible = "ti,tmp421";
+                reg = <0x4e>;
+        };
+        tmp421@1c {
+                compatible = "ti,tmp421";
+                reg = <0x1c>;
+        };
+};
+
+&i2c2 {
+        status = "okay";
+};
+
+&i2c3 {
+        status = "okay";
+};
+
+&i2c4 {
+        status = "okay";
+};
+
+&i2c5 {
+        status = "okay";
+};
+
+&i2c6 {
+        status = "okay";
+
+        tmp421@1d {
+                compatible = "ti,tmp421";
+                reg = <0x1d>;
+        };
+        tmp421@1f {
+                compatible = "ti,tmp421";
+                reg = <0x1f>;
+        };
+        tmp421@4d {
+                compatible = "ti,tmp421";
+                reg = <0x4d>;
+        };
+        tmp421@4f {
+                compatible = "ti,tmp421";
+                reg = <0x4f>;
+        };
+        nvt210@4c {
+                compatible = "nvt210";
+                reg = <0x4c>;
+        };
+        eeprom@50 {
+                compatible = "atmel,24c128";
+                reg = <0x50>;
+                pagesize = <128>;
+        };
+};
+
+&i2c7 {
+        status = "okay";
+};
+
+&i2c8 {
+        status = "okay";
+
+        pca9641@70 {
+                compatible = "nxp,pca9641";
+                reg = <0x70>;
+                i2c-arb {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        tmp421@1d {
+                                compatible = "tmp421";
+                                reg = <0x1d>;
+                        };
+                        adm1278@12 {
+                                compatible = "adi,adm1278";
+                                reg = <0x12>;
+                                Rsense = <500>;
+                        };
+                        eeprom@50 {
+                                compatible = "atmel,24c02";
+                                reg = <0x50>;
+                        };
+                        ds1100@58 {
+                                compatible = "ds1100";
+                                reg = <0x58>;
+                        };
+                };
+        };
+};
+
+&i2c9 {
+        status = "okay";
+};
+
+&vuart {
+        status = "okay";
+};
+
+&gfx {
+        status = "okay";
+};
+
+&pinctrl {
+        aspeed,external-nodes = <&gfx &lhc>;
+};
+
+&gpio {
+        pin_gpio_c7 {
+                gpio-hog;
+                gpios = <ASPEED_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
+                output;
+                line-name = "BIOS_SPI_MUX_S";
+        };
+};
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
index 4379d09a261f..c7084a819dc6 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
@@ -2,6 +2,7 @@
 /dts-v1/;
 
 #include "aspeed-g4.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
 
 / {
         model = "Palmetto BMC";
@@ -26,6 +27,32 @@
                         reg = <0x5f000000 0x01000000>; /* 16M */
                 };
         };
+
+        leds {
+                compatible = "gpio-leds";
+
+                heartbeat {
+                        gpios = <&gpio ASPEED_GPIO(R, 4) GPIO_ACTIVE_LOW>;
+                };
+
+                power {
+                        gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_LOW>;
+                };
+
+                identify {
+                        gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>;
+                };
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+
+                checkstop {
+                        label = "checkstop";
+                        gpios = <&gpio ASPEED_GPIO(P, 5) GPIO_ACTIVE_LOW>;
+                        linux,code = <ASPEED_GPIO(P, 5)>;
+                };
+        };
 };
 
 &fmc {
@@ -40,6 +67,9 @@
 
 &spi {
         status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_spi1debug_default>;
+
         flash@0 {
                 status = "okay";
                 m25p,fast-read;
@@ -47,6 +77,29 @@
         };
 };
 
+&pinctrl {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_flbusy_default &pinctrl_flwp_default
+
+                        &pinctrl_vgahs_default &pinctrl_vgavs_default
+                        &pinctrl_ddcclk_default &pinctrl_ddcdat_default>;
+};
+
+&uart1 {
+        /* Rear RS-232 connector */
+        status = "okay";
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_txd1_default
+                        &pinctrl_rxd1_default
+                        &pinctrl_nrts1_default
+                        &pinctrl_ndtr1_default
+                        &pinctrl_ndsr1_default
+                        &pinctrl_ncts1_default
+                        &pinctrl_ndcd1_default
+                        &pinctrl_nri1_default>;
+};
+
 &uart5 {
         status = "okay";
 };
@@ -111,3 +164,156 @@
 &vuart {
         status = "okay";
 };
+
+&ibt {
+        status = "okay";
+};
+
+&gpio {
+        pin_func_mode0 {
+                gpio-hog;
+                gpios = <ASPEED_GPIO(C, 4) GPIO_ACTIVE_HIGH>;
+                output-low;
+                line-name = "func_mode0";
+        };
+
+        pin_func_mode1 {
+                gpio-hog;
+                gpios = <ASPEED_GPIO(C, 5)  GPIO_ACTIVE_HIGH>;
+                output-low;
+                line-name = "func_mode1";
+        };
+
+        pin_func_mode2 {
+                gpio-hog;
+                gpios = <ASPEED_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
+                output-low;
+                line-name = "func_mode2";
+        };
+
+        pin_gpio_a0 {
+                gpio-hog;
+                gpios = <ASPEED_GPIO(A, 0) GPIO_ACTIVE_HIGH>;
+                input;
+                line-name = "BMC_FAN_RESERVED_N";
+        };
+
+        pin_gpio_a1 {
+                gpio-hog;
+                gpios = <ASPEED_GPIO(A, 1) GPIO_ACTIVE_HIGH>;
+                output-high;
+                line-name = "APSS_WDT_N";
+        };
+
+        pin_gpio_b1 {
+                gpio-hog;
+                gpios = <ASPEED_GPIO(B, 1) GPIO_ACTIVE_HIGH>;
+                output-high;
+                line-name = "APSS_BOOT_MODE";
+        };
+
+        pin_gpio_b2 {
+                gpio-hog;
+                gpios = <ASPEED_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
+                output-high;
+                line-name = "APSS_RESET_N";
+        };
+
+        pin_gpio_b7 {
+                gpio-hog;
+                gpios = <ASPEED_GPIO(B, 7) GPIO_ACTIVE_HIGH>;
+                output-high;
+                line-name = "SPIVID_STBY_RESET_N";
+        };
+
+        pin_gpio_d1 {
+                gpio-hog;
+                gpios = <ASPEED_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
+                output-high;
+                line-name = "BMC_POWER_UP";
+        };
+
+        pin_gpio_f1 {
+                gpio-hog;
+                gpios = <ASPEED_GPIO(F, 1) GPIO_ACTIVE_HIGH>;
+                input;
+                line-name = "BMC_BATTERY_TEST";
+        };
+
+        pin_gpio_f4 {
+                gpio-hog;
+                gpios = <ASPEED_GPIO(F, 4) GPIO_ACTIVE_HIGH>;
+                input;
+                line-name = "AST_HW_FAULT_N";
+        };
+
+        pin_gpio_f5 {
+                gpio-hog;
+                gpios = <ASPEED_GPIO(F, 5) GPIO_ACTIVE_HIGH>;
+                input;
+                line-name = "AST_SYS_FAULT_N";
+        };
+
+        pin_gpio_f7 {
+                gpio-hog;
+                gpios = <ASPEED_GPIO(F, 7) GPIO_ACTIVE_HIGH>;
+                output-high;
+                line-name = "BMC_FULL_SPEED_N";
+        };
+
+        pin_gpio_g3 {
+                gpio-hog;
+                gpios = <ASPEED_GPIO(G, 3) GPIO_ACTIVE_HIGH>;
+                output-high;
+                line-name = "BMC_FAN_ERROR_N";
+        };
+
+        pin_gpio_g4 {
+                gpio-hog;
+                gpios = <ASPEED_GPIO(G, 4) GPIO_ACTIVE_HIGH>;
+                input;
+                line-name = "BMC_WDT_RST1_P";
+        };
+
+        pin_gpio_g5 {
+                gpio-hog;
+                gpios = <ASPEED_GPIO(G, 5) GPIO_ACTIVE_HIGH>;
+                input;
+                line-name = "BMC_WDT_RST2_P";
+        };
+
+        pin_gpio_h0 {
+                gpio-hog;
+                gpios = <ASPEED_GPIO(H, 0) GPIO_ACTIVE_HIGH>;
+                input;
+                line-name = "PE_SLOT_TEST_EN_N";
+        };
+
+        pin_gpio_h1 {
+                gpio-hog;
+                gpios = <ASPEED_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+                input;
+                line-name = "BMC_RTCRST_N";
+        };
+
+        pin_gpio_h2 {
+                gpio-hog;
+                gpios = <ASPEED_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+                output-high;
+                line-name = "SYS_PWROK_BMC";
+        };
+
+        pin_gpio_h6 {
+                gpio-hog;
+                gpios = <ASPEED_GPIO(H, 6) GPIO_ACTIVE_HIGH>;
+                output-high;
+                line-name = "SCM1_FSI0_DATA_EN";
+        };
+
+        pin_gpio_h7 {
+                gpio-hog;
+                gpios = <ASPEED_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
+                output-high;
+                line-name = "BMC_TPM_INT_N";
+        };
+};
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
index 623b6ab42021..51bc6a2e9dd5 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts
@@ -184,9 +184,9 @@
 &i2c12 {
         status = "okay";
 
-        max31785@52 {
-                compatible = "maxim,max31785";
-                reg = <0x52>;
+        w83773g@4c {
+                compatible = "nuvoton,w83773g";
+                reg = <0x4c>;
         };
 };
 
@@ -203,6 +203,12 @@
                 output-low;
                 line-name = "nic_func_mode1";
         };
+        seq_cont {
+                gpio-hog;
+                gpios = <ASPEED_GPIO(S, 7) GPIO_ACTIVE_HIGH>;
+                output-low;
+                line-name = "seq_cont";
+        };
 };
 
 &vuart {
@@ -257,3 +263,7 @@
                 aspeed,fan-tach-ch = /bits/ 8 <0x0e>;
         };
 };
+
+&ibt {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
index 5f9049d2c4c3..7056231cbee6 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts
@@ -546,3 +546,7 @@
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_wdtrst1_default>;
 };
+
+&ibt {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
index c881484a85cf..ebe726a0d311 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts
@@ -424,3 +424,7 @@
                 aspeed,fan-tach-ch = /bits/ 8 <0x03>;
         };
 };
+
+&ibt {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index b0d8431a3700..36ae23aa3b48 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -162,6 +162,7 @@
                                 reg-shift = <2>;
                                 interrupts = <9>;
                                 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
+                                resets = <&lpc_reset 4>;
                                 no-loopback-test;
                                 status = "disabled";
                         };
@@ -233,6 +234,7 @@
                                         lpc_ctrl: lpc-ctrl@0 {
                                                 compatible = "aspeed,ast2400-lpc-ctrl";
                                                 reg = <0x0 0x80>;
+                                                clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
                                                 status = "disabled";
                                         };
 
@@ -247,6 +249,19 @@
                                                 compatible = "aspeed,ast2400-lhc";
                                                 reg = <0x20 0x24 0x48 0x8>;
                                         };
+
+                                        lpc_reset: reset-controller@18 {
+                                                compatible = "aspeed,ast2400-lpc-reset";
+                                                reg = <0x18 0x4>;
+                                                #reset-cells = <1>;
+                                        };
+
+                                        ibt: ibt@c0  {
+                                                compatible = "aspeed,ast2400-ibt-bmc";
+                                                reg = <0xc0 0x18>;
+                                                interrupts = <8>;
+                                                status = "disabled";
+                                        };
                                 };
                         };
 
@@ -256,6 +271,7 @@
                                 reg-shift = <2>;
                                 interrupts = <32>;
                                 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
+                                resets = <&lpc_reset 5>;
                                 no-loopback-test;
                                 status = "disabled";
                         };
@@ -266,6 +282,7 @@
                                 reg-shift = <2>;
                                 interrupts = <33>;
                                 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
+                                resets = <&lpc_reset 6>;
                                 no-loopback-test;
                                 status = "disabled";
                         };
@@ -276,6 +293,7 @@
                                 reg-shift = <2>;
                                 interrupts = <34>;
                                 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
+                                resets = <&lpc_reset 7>;
                                 no-loopback-test;
                                 status = "disabled";
                         };
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 40de3b66c33f..17ee0fa33a14 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -205,6 +205,7 @@
                                 reg-shift = <2>;
                                 interrupts = <9>;
                                 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
+                                resets = <&lpc_reset 4>;
                                 no-loopback-test;
                                 status = "disabled";
                         };
@@ -264,7 +265,7 @@
 
                                 #address-cells = <1>;
                                 #size-cells = <1>;
-                                ranges = <0 0x1e789000 0x1000>;
+                                ranges = <0x0 0x1e789000 0x1000>;
 
                                 lpc_bmc: lpc-bmc@0 {
                                         compatible = "aspeed,ast2500-lpc-bmc";
@@ -274,16 +275,16 @@
                                 lpc_host: lpc-host@80 {
                                         compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
                                         reg = <0x80 0x1e0>;
+                                        reg-io-width = <4>;
 
                                         #address-cells = <1>;
                                         #size-cells = <1>;
-                                        ranges = <0 0x80 0x1e0>;
-
-                                        reg-io-width = <4>;
+                                        ranges = <0x0 0x80 0x1e0>;
 
                                         lpc_ctrl: lpc-ctrl@0 {
                                                 compatible = "aspeed,ast2500-lpc-ctrl";
                                                 reg = <0x0 0x80>;
+                                                clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
                                                 status = "disabled";
                                         };
 
@@ -298,6 +299,19 @@
                                                 compatible = "aspeed,ast2500-lhc";
                                                 reg = <0x20 0x24 0x48 0x8>;
                                         };
+
+                                        lpc_reset: reset-controller@18 {
+                                                compatible = "aspeed,ast2500-lpc-reset";
+                                                reg = <0x18 0x4>;
+                                                #reset-cells = <1>;
+                                        };
+
+                                        ibt: ibt@c0 {
+                                                compatible = "aspeed,ast2500-ibt-bmc";
+                                                reg = <0xc0 0x18>;
+                                                interrupts = <8>;
+                                                status = "disabled";
+                                        };
                                 };
                         };
 
@@ -307,6 +321,7 @@
                                 reg-shift = <2>;
                                 interrupts = <32>;
                                 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
+                                resets = <&lpc_reset 5>;
                                 no-loopback-test;
                                 status = "disabled";
                         };
@@ -317,6 +332,7 @@
                                 reg-shift = <2>;
                                 interrupts = <33>;
                                 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
+                                resets = <&lpc_reset 6>;
                                 no-loopback-test;
                                 status = "disabled";
                         };
@@ -327,6 +343,7 @@
                                 reg-shift = <2>;
                                 interrupts = <34>;
                                 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
+                                resets = <&lpc_reset 7>;
                                 no-loopback-test;
                                 status = "disabled";
                         };
diff --git a/arch/arm/boot/dts/at91-nattis-2-natte-2.dts b/arch/arm/boot/dts/at91-nattis-2-natte-2.dts
index 3ea1d26e1c68..af9f38456d04 100644
--- a/arch/arm/boot/dts/at91-nattis-2-natte-2.dts
+++ b/arch/arm/boot/dts/at91-nattis-2-natte-2.dts
@@ -109,7 +109,32 @@
 
                 port {
                         panel_input: endpoint {
-                                remote-endpoint = <&hlcdc_panel_output>;
+                                remote-endpoint = <&lvds_encoder_output>;
+                        };
+                };
+        };
+
+        lvds-encoder {
+                compatible = "lvds-encoder";
+
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@0 {
+                                reg = <0>;
+
+                                lvds_encoder_input: endpoint {
+                                        remote-endpoint = <&hlcdc_output>;
+                                };
+                        };
+
+                        port@1 {
+                                reg = <1>;
+
+                                lvds_encoder_output: endpoint {
+                                        remote-endpoint = <&panel_input>;
+                                };
                         };
                 };
         };
@@ -146,7 +171,7 @@
         };
 
         eeprom@50 {
-                compatible = "nxp,24c02";
+                compatible = "nxp,se97b", "atmel,24c02";
                 reg = <0x50>;
                 pagesize = <16>;
         };
@@ -176,8 +201,8 @@
                              &pinctrl_lcd_hipow0>;
 
                 port@0 {
-                        hlcdc_panel_output: endpoint {
-                                remote-endpoint = <&panel_input>;
+                        hlcdc_output: endpoint {
+                                remote-endpoint = <&lvds_encoder_input>;
                         };
                 };
         };
@@ -216,29 +241,34 @@
                         reg = <0x0 0x40000>;
                 };
 
-                bootloader@40000 {
-                        label = "bootloader";
-                        reg = <0x40000 0x80000>;
+                barebox@40000 {
+                        label = "barebox";
+                        reg = <0x40000 0x60000>;
+                };
+
+                bareboxenv@c0000 {
+                        label = "bareboxenv";
+                        reg = <0xc0000 0x40000>;
                 };
 
-                bootloaderenv@c0000 {
-                        label = "bootloader env";
-                        reg = <0xc0000 0xc0000>;
+                bareboxenv2@100000 {
+                        label = "bareboxenv2";
+                        reg = <0x100000 0x40000>;
                 };
 
-                dtb@180000 {
-                        label = "device tree";
-                        reg = <0x180000 0x80000>;
+                oftree@180000 {
+                        label = "oftree";
+                        reg = <0x180000 0x20000>;
                 };
 
                 kernel@200000 {
                         label = "kernel";
-                        reg = <0x200000 0x600000>;
+                        reg = <0x200000 0x500000>;
                 };
 
                 rootfs@800000 {
                         label = "rootfs";
-                        reg = <0x800000 0x0f800000>;
+                        reg = <0x800000 0x1f800000>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
index e603a267bdf1..b10dccd0958f 100644
--- a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
@@ -230,7 +230,7 @@
                                 status = "okay";
 
                                 at24@50 {
-                                        compatible = "24c02";
+                                        compatible = "atmel,24c02";
                                         reg = <0x50>;
                                         pagesize = <8>;
                                 };
diff --git a/arch/arm/boot/dts/at91-tse850-3.dts b/arch/arm/boot/dts/at91-tse850-3.dts
index 9b82cc8843e1..2fbec69d9cd6 100644
--- a/arch/arm/boot/dts/at91-tse850-3.dts
+++ b/arch/arm/boot/dts/at91-tse850-3.dts
@@ -234,6 +234,7 @@
                 compatible = "ti,pcm5142";
 
                 reg = <0x4c>;
+                #sound-dai-cells = <0>;
 
                 AVDD-supply = <&reg_3v3>;
                 DVDD-supply = <&reg_3v3>;
@@ -246,7 +247,7 @@
         };
 
         eeprom@50 {
-                compatible = "nxp,24c02", "atmel,24c02";
+                compatible = "nxp,se97b", "atmel,24c02";
                 reg = <0x50>;
                 pagesize = <16>;
         };
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index ba61893a02a0..2ad69a7fbc00 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -493,8 +493,8 @@
                                 uart0 {
                                         pinctrl_uart0: uart0-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA17 periph A */
-                                                         AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA18 periph A */
+                                                        <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE
+                                                         AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
                                         };
 
                                         pinctrl_uart0_cts: uart0_cts-0 {
@@ -511,8 +511,8 @@
                                 uart1 {
                                         pinctrl_uart1: uart1-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PB20 periph A with pullup */
-                                                         AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB21 periph A */
+                                                        <AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE
+                                                         AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
                                         };
 
                                         pinctrl_uart1_rts: uart1_rts-0 {
@@ -545,8 +545,8 @@
                                 uart2 {
                                         pinctrl_uart2: uart2-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA22 periph A */
-                                                         AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA23 periph A with pullup */
+                                                        <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+                                                         AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
                                         };
 
                                         pinctrl_uart2_rts: uart2_rts-0 {
@@ -563,8 +563,8 @@
                                 uart3 {
                                         pinctrl_uart3: uart3-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA5 periph B with pullup */
-                                                         AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PA6 periph B */
+                                                        <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE
+                                                         AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
                                         };
 
                                         pinctrl_uart3_rts: uart3_rts-0 {
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 655f06cd716a..9118e29b6d6a 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -434,8 +434,8 @@
                                 usart0 {
                                         pinctrl_usart0: usart0-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB4 periph A */
-                                                         AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB5 periph A */
+                                                        <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE
+                                                         AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
                                         };
 
                                         pinctrl_usart0_rts: usart0_rts-0 {
@@ -468,8 +468,8 @@
                                 usart1 {
                                         pinctrl_usart1: usart1-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */
-                                                         AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB7 periph A */
+                                                        <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE
+                                                         AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
                                         };
 
                                         pinctrl_usart1_rts: usart1_rts-0 {
@@ -486,8 +486,8 @@
                                 usart2 {
                                         pinctrl_usart2: usart2-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB8 periph A with pullup */
-                                                         AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB9 periph A */
+                                                        <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE
+                                                         AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
                                         };
 
                                         pinctrl_usart2_rts: usart2_rts-0 {
@@ -504,8 +504,8 @@
                                 usart3 {
                                         pinctrl_usart3: usart3-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PB10 periph A with pullup */
-                                                         AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */
+                                                        <AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE
+                                                         AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
                                         };
 
                                         pinctrl_usart3_rts: usart3_rts-0 {
@@ -522,16 +522,16 @@
                                 uart0 {
                                         pinctrl_uart0: uart0-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* PA31 periph B with pullup */
-                                                         AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */
+                                                        <AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_NONE
+                                                         AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
                                         };
                                 };
 
                                 uart1 {
                                         pinctrl_uart1: uart1-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PB12 periph A with pullup */
-                                                         AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB13 periph A */
+                                                        <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE
+                                                         AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
                                         };
                                 };
 
diff --git a/arch/arm/boot/dts/at91sam9260ek.dts b/arch/arm/boot/dts/at91sam9260ek.dts
index e16c706d91ef..d2b865f60293 100644
--- a/arch/arm/boot/dts/at91sam9260ek.dts
+++ b/arch/arm/boot/dts/at91sam9260ek.dts
@@ -201,7 +201,7 @@
                 status = "okay";
 
                 24c512@50 {
-                        compatible = "24c512";
+                        compatible = "atmel,24c512";
                         reg = <0x50>;
                 };
         };
diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi
index ddfc63b8fd4e..53c63d0a418a 100644
--- a/arch/arm/boot/dts/at91sam9261.dtsi
+++ b/arch/arm/boot/dts/at91sam9261.dtsi
@@ -328,8 +328,8 @@
                                 usart0 {
                                         pinctrl_usart0: usart0-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
-                                                        <AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                                        <AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
                                         };
 
                                         pinctrl_usart0_rts: usart0_rts-0 {
@@ -346,8 +346,8 @@
                                 usart1 {
                                         pinctrl_usart1: usart1-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
-                                                        <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                                        <AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
                                         };
 
                                         pinctrl_usart1_rts: usart1_rts-0 {
@@ -364,8 +364,8 @@
                                 usart2 {
                                         pinctrl_usart2: usart2-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
-                                                        <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                                        <AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
                                         };
 
                                         pinctrl_usart2_rts: usart2_rts-0 {
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index f2405671e3bd..87fb0660ab5d 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -437,8 +437,8 @@
                                 usart0 {
                                         pinctrl_usart0: usart0-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA26 periph A with pullup */
-                                                         AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA27 periph A */
+                                                        <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE
+                                                         AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
                                         };
 
                                         pinctrl_usart0_rts: usart0_rts-0 {
@@ -455,8 +455,8 @@
                                 usart1 {
                                         pinctrl_usart1: usart1-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A with pullup */
-                                                         AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PD1 periph A */
+                                                        <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE
+                                                         AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
                                         };
 
                                         pinctrl_usart1_rts: usart1_rts-0 {
@@ -473,8 +473,8 @@
                                 usart2 {
                                         pinctrl_usart2: usart2-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A with pullup */
-                                                         AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PD3 periph A */
+                                                        <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE
+                                                         AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
                                         };
 
                                         pinctrl_usart2_rts: usart2_rts-0 {
diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts
index e9a7c70830a8..727096f24f7c 100644
--- a/arch/arm/boot/dts/at91sam9263ek.dts
+++ b/arch/arm/boot/dts/at91sam9263ek.dts
@@ -250,7 +250,7 @@
                 status = "okay";
 
                 24c512@50 {
-                        compatible = "24c512";
+                        compatible = "atmel,24c512";
                         reg = <0x50>;
                         pagesize = <128>;
                 };
diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
index 50561b7b7939..71df3adfc7ca 100644
--- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
@@ -211,7 +211,7 @@
                 status = "okay";
 
                 24c512@50 {
-                        compatible = "24c512";
+                        compatible = "atmel,24c512";
                         reg = <0x50>;
                 };
 
diff --git a/arch/arm/boot/dts/at91sam9g25.dtsi b/arch/arm/boot/dts/at91sam9g25.dtsi
index a7da0dd0c98f..0898213f3bb2 100644
--- a/arch/arm/boot/dts/at91sam9g25.dtsi
+++ b/arch/arm/boot/dts/at91sam9g25.dtsi
@@ -21,7 +21,7 @@
                                 atmel,mux-mask = <
                                       /*    A         B          C     */
                                        0xffffffff 0xffe0399f 0xc000001c  /* pioA */
-                                       0x0007ffff 0x8000fe3f 0x00000000  /* pioB */
+                                       0x0007ffff 0x00047e3f 0x00000000  /* pioB */
                                        0x80000000 0x07c0ffff 0xb83fffff  /* pioC */
                                        0x003fffff 0x003f8000 0x00000000  /* pioD */
                                       >;
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 3a30eec7f508..1ee25a475be8 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -555,8 +555,8 @@
                                 usart0 {
                                         pinctrl_usart0: usart0-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PB19 periph A with pullup */
-                                                         AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */
+                                                        <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE
+                                                         AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
                                         };
 
                                         pinctrl_usart0_rts: usart0_rts-0 {
@@ -573,8 +573,8 @@
                                 uart1 {
                                         pinctrl_usart1: usart1-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB4 periph A with pullup */
-                                                         AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB5 periph A */
+                                                        <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE
+                                                         AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
                                         };
 
                                         pinctrl_usart1_rts: usart1_rts-0 {
@@ -591,8 +591,8 @@
                                 usart2 {
                                         pinctrl_usart2: usart2-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */
-                                                         AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB7 periph A */
+                                                        <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE
+                                                         AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
                                         };
 
                                         pinctrl_usart2_rts: usart2_rts-0 {
@@ -609,8 +609,8 @@
                                 usart3 {
                                         pinctrl_usart3: usart3-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB9 periph A with pullup */
-                                                         AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB8 periph A */
+                                                        <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE
+                                                         AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
                                         };
 
                                         pinctrl_usart3_rts: usart3_rts-0 {
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 4b62f4f963f6..37cb81f457b5 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -641,8 +641,8 @@
                                 uart1 {
                                         pinctrl_uart1: uart1-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_PULL_UP        /* PC17 periph C with pullup */
-                                                         AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC16 periph C */
+                                                        <AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_NONE
+                                                         AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>;
                                         };
                                 };
 
diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi
index 3cae687dccbd..bd001cca25a4 100644
--- a/arch/arm/boot/dts/at91sam9rl.dtsi
+++ b/arch/arm/boot/dts/at91sam9rl.dtsi
@@ -1,7 +1,8 @@
 /*
  * at91sam9rl.dtsi - Device Tree Include file for AT91SAM9RL family SoC
  *
- *  Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
+ *  Copyright (C) 2014 Microchip
+ *  Alexandre Belloni <alexandre.belloni@free-electrons.com>
  *
  * Licensed under GPLv2 or later.
  */
@@ -719,8 +720,8 @@
                                 usart1 {
                                         pinctrl_usart1: usart1-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
-                                                        <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                                        <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
                                         };
 
                                         pinctrl_usart1_rts: usart1_rts-0 {
@@ -742,8 +743,8 @@
                                 usart2 {
                                         pinctrl_usart2: usart2-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
-                                                        <AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                                        <AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
                                         };
 
                                         pinctrl_usart2_rts: usart2_rts-0 {
@@ -765,8 +766,8 @@
                                 usart3 {
                                         pinctrl_usart3: usart3-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
-                                                        <AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                                        <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
                                         };
 
                                         pinctrl_usart3_rts: usart3_rts-0 {
diff --git a/arch/arm/boot/dts/at91sam9rlek.dts b/arch/arm/boot/dts/at91sam9rlek.dts
index 4bde9f245e61..27d8a1f44233 100644
--- a/arch/arm/boot/dts/at91sam9rlek.dts
+++ b/arch/arm/boot/dts/at91sam9rlek.dts
@@ -1,7 +1,8 @@
 /*
  * at91sam9rlek.dts - Device Tree file for Atmel at91sam9rl reference board
  *
- *  Copyright (C) 2014  Alexandre Belloni <alexandre.belloni@free-electrons.com>
+ *  Copyright (C) 2014 Microchip
+ *  Alexandre Belloni <alexandre.belloni@free-electrons.com>
  *
  * Licensed under GPLv2 only
  */
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index fee4fe51a97e..a3c3c3128148 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -520,8 +520,8 @@
                                 usart0 {
                                         pinctrl_usart0: usart0-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA0 periph A with pullup */
-                                                         AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PA1 periph A */
+                                                        <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE
+                                                         AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
                                         };
 
                                         pinctrl_usart0_rts: usart0_rts-0 {
@@ -543,8 +543,8 @@
                                 usart1 {
                                         pinctrl_usart1: usart1-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA5 periph A with pullup */
-                                                         AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PA6 periph A */
+                                                        <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE
+                                                         AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
                                         };
 
                                         pinctrl_usart1_rts: usart1_rts-0 {
@@ -566,8 +566,8 @@
                                 usart2 {
                                         pinctrl_usart2: usart2-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
-                                                         AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PA8 periph A */
+                                                        <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE
+                                                         AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
                                         };
 
                                         pinctrl_usart2_rts: usart2_rts-0 {
diff --git a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
index 43bb5b51caa6..a32d12b406a3 100644
--- a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
@@ -21,8 +21,8 @@
                                 usart3 {
                                         pinctrl_usart3: usart3-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* PC22 periph B with pullup */
-                                                         AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>;         /* PC23 periph B */
+                                                        <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE
+                                                         AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
                                         };
 
                                         pinctrl_usart3_rts: usart3_rts-0 {
diff --git a/arch/arm/boot/dts/atlas7-evb.dts b/arch/arm/boot/dts/atlas7-evb.dts
index 1e9cd1a8508e..900e03b7a7b2 100644
--- a/arch/arm/boot/dts/atlas7-evb.dts
+++ b/arch/arm/boot/dts/atlas7-evb.dts
@@ -73,7 +73,7 @@
                 btm {
                         uart6: uart@11000000 {
                                 status = "okay";
-                                sirf,uart-has-rtscts;
+                                uart-has-rtscts;
                         };
                 };
 
diff --git a/arch/arm/boot/dts/axp209.dtsi b/arch/arm/boot/dts/axp209.dtsi
index 897103e0a79b..0d9ff12bdf28 100644
--- a/arch/arm/boot/dts/axp209.dtsi
+++ b/arch/arm/boot/dts/axp209.dtsi
@@ -58,6 +58,11 @@
                 status = "disabled";
         };
 
+        axp_adc: adc {
+                compatible = "x-powers,axp209-adc";
+                #io-channel-cells = <1>;
+        };
+
         axp_gpio: gpio {
                 compatible = "x-powers,axp209-gpio";
                 gpio-controller;
diff --git a/arch/arm/boot/dts/axp22x.dtsi b/arch/arm/boot/dts/axp22x.dtsi
index 87fb08e812ec..65a07a67aca9 100644
--- a/arch/arm/boot/dts/axp22x.dtsi
+++ b/arch/arm/boot/dts/axp22x.dtsi
@@ -57,6 +57,11 @@
                 status = "disabled";
         };
 
+        axp_adc: adc {
+                compatible = "x-powers,axp221-adc";
+                #io-channel-cells = <1>;
+        };
+
         battery_power_supply: battery-power-supply {
                 compatible = "x-powers,axp221-battery-power-supply";
                 status = "disabled";
diff --git a/arch/arm/boot/dts/axp81x.dtsi b/arch/arm/boot/dts/axp81x.dtsi
index fd55b896afa1..043c717dcef1 100644
--- a/arch/arm/boot/dts/axp81x.dtsi
+++ b/arch/arm/boot/dts/axp81x.dtsi
@@ -48,7 +48,12 @@
         interrupt-controller;
         #interrupt-cells = <1>;
 
-        axp_gpio: axp-gpio {
+        axp_adc: adc {
+                compatible = "x-powers,axp813-adc";
+                #io-channel-cells = <1>;
+        };
+
+        axp_gpio: gpio {
                 compatible = "x-powers,axp813-gpio";
                 gpio-controller;
                 #gpio-cells = <2>;
@@ -64,6 +69,11 @@
                 };
         };
 
+        battery_power_supply: battery-power-supply {
+                compatible = "x-powers,axp813-battery-power-supply";
+                status = "disabled";
+        };
+
         regulators {
                 /* Default work frequency for buck regulators */
                 x-powers,dcdc-freq = <3000>;
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
index 18045c38bcf1..db7cded1b7ad 100644
--- a/arch/arm/boot/dts/bcm11351.dtsi
+++ b/arch/arm/boot/dts/bcm11351.dtsi
@@ -55,7 +55,7 @@
                       <0x3ff00100 0x100>;
         };
 
-        smc@0x3404c000 {
+        smc@3404c000 {
                 compatible = "brcm,bcm11351-smc", "brcm,kona-smc";
                 reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */
         };
diff --git a/arch/arm/boot/dts/bcm21664.dtsi b/arch/arm/boot/dts/bcm21664.dtsi
index 6dde95f21cef..266f2611dc22 100644
--- a/arch/arm/boot/dts/bcm21664.dtsi
+++ b/arch/arm/boot/dts/bcm21664.dtsi
@@ -55,7 +55,7 @@
                       <0x3ff00100 0x100>;
         };
 
-        smc@0x3404e000 {
+        smc@3404e000 {
                 compatible = "brcm,bcm21664-smc", "brcm,kona-smc";
                 reg = <0x3404e000 0x400>; /* 1 KiB in SRAM */
         };
diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts
index b8565fc33eea..b7f79f1c431a 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts
@@ -12,7 +12,7 @@
 /dts-v1/;
 #include "bcm2835.dtsi"
 #include "bcm2835-rpi.dtsi"
-#include "bcm283x-rpi-usb-host.dtsi"
+#include "bcm283x-rpi-usb-otg.dtsi"
 
 / {
         compatible = "raspberrypi,model-zero-w", "brcm,bcm2835";
@@ -131,6 +131,18 @@
 
 &uart0 {
         pinctrl-names = "default";
-        pinctrl-0 = <&uart0_gpio14>;
+        pinctrl-0 = <&uart0_gpio32 &uart0_ctsrts_gpio30>;
+        status = "okay";
+
+        bluetooth {
+                compatible = "brcm,bcm43438-bt";
+                max-speed = <2000000>;
+                shutdown-gpios = <&gpio 45 GPIO_ACTIVE_HIGH>;
+        };
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart1_gpio14>;
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi
index e36c392a2b8f..0198bd46ef7c 100644
--- a/arch/arm/boot/dts/bcm2835-rpi.dtsi
+++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi
@@ -18,7 +18,9 @@
 
         soc {
                 firmware: firmware {
-                        compatible = "raspberrypi,bcm2835-firmware";
+                        compatible = "raspberrypi,bcm2835-firmware", "simple-bus";
+                        #address-cells = <0>;
+                        #size-cells = <0>;
                         mboxes = <&mailbox>;
                 };
 
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
index 0e3d2a5ff208..a5c3824c8056 100644
--- a/arch/arm/boot/dts/bcm2835.dtsi
+++ b/arch/arm/boot/dts/bcm2835.dtsi
@@ -18,10 +18,10 @@
         soc {
                 ranges = <0x7e000000 0x20000000 0x02000000>;
                 dma-ranges = <0x40000000 0x00000000 0x20000000>;
+        };
 
-                arm-pmu {
-                        compatible = "arm,arm1176-pmu";
-                };
+        arm-pmu {
+                compatible = "arm,arm1176-pmu";
         };
 };
 
diff --git a/arch/arm/boot/dts/bcm2836.dtsi b/arch/arm/boot/dts/bcm2836.dtsi
index 1dfd76442777..c933e8413884 100644
--- a/arch/arm/boot/dts/bcm2836.dtsi
+++ b/arch/arm/boot/dts/bcm2836.dtsi
@@ -9,19 +9,19 @@
                          <0x40000000 0x40000000 0x00001000>;
                 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
 
-                local_intc: local_intc {
+                local_intc: local_intc@40000000 {
                         compatible = "brcm,bcm2836-l1-intc";
                         reg = <0x40000000 0x100>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
                         interrupt-parent = <&local_intc>;
                 };
+        };
 
-                arm-pmu {
-                        compatible = "arm,cortex-a7-pmu";
-                        interrupt-parent = <&local_intc>;
-                        interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
-                };
+        arm-pmu {
+                compatible = "arm,cortex-a7-pmu";
+                interrupt-parent = <&local_intc>;
+                interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
         };
 
         timer {
diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
index 3e4ed7c5b0b3..0b31d995a066 100644
--- a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
+++ b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
@@ -25,6 +25,23 @@
         };
 };
 
+&firmware {
+        expgpio: gpio {
+                compatible = "raspberrypi,firmware-gpio";
+                gpio-controller;
+                #gpio-cells = <2>;
+                gpio-line-names = "BT_ON",
+                                  "WL_ON",
+                                  "STATUS_LED",
+                                  "LAN_RUN",
+                                  "HPD_N",
+                                  "CAM_GPIO0",
+                                  "CAM_GPIO1",
+                                  "PWR_LOW_N";
+                status = "okay";
+        };
+};
+
 /* uart0 communicates with the BT module */
 &uart0 {
         pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/bcm2837.dtsi b/arch/arm/boot/dts/bcm2837.dtsi
index efa7d3387ab2..7704bb029605 100644
--- a/arch/arm/boot/dts/bcm2837.dtsi
+++ b/arch/arm/boot/dts/bcm2837.dtsi
@@ -8,7 +8,7 @@
                          <0x40000000 0x40000000 0x00001000>;
                 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
 
-                local_intc: local_intc {
+                local_intc: local_intc@40000000 {
                         compatible = "brcm,bcm2836-l1-intc";
                         reg = <0x40000000 0x100>;
                         interrupt-controller;
diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi
index 18db25a5a66e..ac00e730f898 100644
--- a/arch/arm/boot/dts/bcm283x.dtsi
+++ b/arch/arm/boot/dts/bcm283x.dtsi
@@ -223,6 +223,7 @@
                         gpclk2_gpio43: gpclk2_gpio43 {
                                 brcm,pins = <43>;
                                 brcm,function = <BCM2835_FSEL_ALT0>;
+                                brcm,pull = <BCM2835_PUD_OFF>;
                         };
 
                         i2c0_gpio0: i2c0_gpio0 {
@@ -252,7 +253,7 @@
 
                         jtag_gpio4: jtag_gpio4 {
                                 brcm,pins = <4 5 6 12 13>;
-                                brcm,function = <BCM2835_FSEL_ALT4>;
+                                brcm,function = <BCM2835_FSEL_ALT5>;
                         };
                         jtag_gpio22: jtag_gpio22 {
                                 brcm,pins = <22 23 24 25 26 27>;
@@ -335,10 +336,12 @@
                         uart0_ctsrts_gpio30: uart0_ctsrts_gpio30 {
                                 brcm,pins = <30 31>;
                                 brcm,function = <BCM2835_FSEL_ALT3>;
+                                brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_OFF>;
                         };
                         uart0_gpio32: uart0_gpio32 {
                                 brcm,pins = <32 33>;
                                 brcm,function = <BCM2835_FSEL_ALT3>;
+                                brcm,pull = <BCM2835_PUD_OFF BCM2835_PUD_UP>;
                         };
                         uart0_gpio36: uart0_gpio36 {
                                 brcm,pins = <36 37>;
@@ -397,8 +400,8 @@
 
                 i2s: i2s@7e203000 {
                         compatible = "brcm,bcm2835-i2s";
-                        reg = <0x7e203000 0x20>,
-                              <0x7e101098 0x02>;
+                        reg = <0x7e203000 0x24>;
+                        clocks = <&clocks BCM2835_CLOCK_PCM>;
 
                         dmas = <&dma 2>,
                                <&dma 3>;
@@ -438,6 +441,17 @@
                         interrupts = <2 14>; /* pwa1 */
                 };
 
+                dpi: dpi@7e208000 {
+                        compatible = "brcm,bcm2835-dpi";
+                        reg = <0x7e208000 0x8c>;
+                        clocks = <&clocks BCM2835_CLOCK_VPU>,
+                                 <&clocks BCM2835_CLOCK_DPI>;
+                        clock-names = "core", "pixel";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
                 dsi0: dsi@7e209000 {
                         compatible = "brcm,bcm2835-dsi0";
                         reg = <0x7e209000 0x78>;
@@ -465,7 +479,7 @@
                         status = "disabled";
                 };
 
-                aux: aux@0x7e215000 {
+                aux: aux@7e215000 {
                         compatible = "brcm,bcm2835-aux";
                         #clock-cells = <1>;
                         reg = <0x7e215000 0x8>;
diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts
index 8bef6429feee..87ea6ba664f5 100644
--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts
+++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts
@@ -35,6 +35,74 @@
                        0x88000000 0x08000000>;
         };
 
+        spi {
+                compatible = "spi-gpio";
+                num-chipselects = <1>;
+                gpio-sck = <&chipcommon 7 0>;
+                gpio-mosi = <&chipcommon 4 0>;
+                cs-gpios = <&chipcommon 6 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                hc595: gpio_spi@0 {
+                        compatible = "fairchild,74hc595";
+                        reg = <0>;
+                        registers-number = <1>;
+                        spi-max-frequency = <100000>;
+
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                usb {
+                        label = "bcm53xx:green:usb";
+                        gpios = <&hc595 0 GPIO_ACTIVE_HIGH>;
+                };
+
+                power0 {
+                        label = "bcm53xx:green:power";
+                        gpios = <&hc595 1 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "default-on";
+                };
+
+                power1 {
+                        label = "bcm53xx:red:power";
+                        gpios = <&hc595 2 GPIO_ACTIVE_HIGH>;
+                };
+
+                router0 {
+                        label = "bcm53xx:green:router";
+                        gpios = <&hc595 3 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "default-on";
+                };
+
+                router1 {
+                        label = "bcm53xx:amber:router";
+                        gpios = <&hc595 4 GPIO_ACTIVE_HIGH>;
+                };
+
+                wan {
+                        label = "bcm53xx:green:wan";
+                        gpios = <&hc595 5 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "default-on";
+                };
+
+                wireless0 {
+                        label = "bcm53xx:green:wireless";
+                        gpios = <&hc595 6 GPIO_ACTIVE_HIGH>;
+                };
+
+                wireless1 {
+                        label = "bcm53xx:amber:wireless";
+                        gpios = <&hc595 7 GPIO_ACTIVE_HIGH>;
+                };
+        };
+
         gpio-keys {
                 compatible = "gpio-keys";
                 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/bcm958622hr.dts b/arch/arm/boot/dts/bcm958622hr.dts
index fd8b8c689ffe..ecd05e26c262 100644
--- a/arch/arm/boot/dts/bcm958622hr.dts
+++ b/arch/arm/boot/dts/bcm958622hr.dts
@@ -204,10 +204,10 @@
                         reg = <4>;
                 };
 
-                port@5 {
-                        ethernet = <&amac0>;
+                port@8 {
+                        ethernet = <&amac2>;
                         label = "cpu";
-                        reg = <5>;
+                        reg = <8>;
                         fixed-link {
                                 speed = <1000>;
                                 full-duplex;
diff --git a/arch/arm/boot/dts/bcm958623hr.dts b/arch/arm/boot/dts/bcm958623hr.dts
index b8bde13de90a..f5e85b301497 100644
--- a/arch/arm/boot/dts/bcm958623hr.dts
+++ b/arch/arm/boot/dts/bcm958623hr.dts
@@ -208,10 +208,10 @@
                         reg = <4>;
                 };
 
-                port@5 {
-                        ethernet = <&amac0>;
+                port@8 {
+                        ethernet = <&amac2>;
                         label = "cpu";
-                        reg = <5>;
+                        reg = <8>;
                         fixed-link {
                                 speed = <1000>;
                                 full-duplex;
diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts
index 6a44b8021702..ea3fc194f8f3 100644
--- a/arch/arm/boot/dts/bcm958625hr.dts
+++ b/arch/arm/boot/dts/bcm958625hr.dts
@@ -49,7 +49,7 @@
 
         memory {
                 device_type = "memory";
-                reg = <0x60000000 0x80000000>;
+                reg = <0x60000000 0x20000000>;
         };
 
         gpio-restart {
@@ -210,10 +210,10 @@
                         reg = <4>;
                 };
 
-                port@5 {
-                        ethernet = <&amac0>;
+                port@8 {
+                        ethernet = <&amac2>;
                         label = "cpu";
-                        reg = <5>;
+                        reg = <8>;
                         fixed-link {
                                 speed = <1000>;
                                 full-duplex;
diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts
index 2cf2392483b2..3ea5f739e90b 100644
--- a/arch/arm/boot/dts/bcm958625k.dts
+++ b/arch/arm/boot/dts/bcm958625k.dts
@@ -245,10 +245,10 @@
                         reg = <4>;
                 };
 
-                port@5 {
-                        ethernet = <&amac0>;
+                port@8 {
+                        ethernet = <&amac2>;
                         label = "cpu";
-                        reg = <5>;
+                        reg = <8>;
                         fixed-link {
                                 speed = <1000>;
                                 full-duplex;
diff --git a/arch/arm/boot/dts/bcm988312hr.dts b/arch/arm/boot/dts/bcm988312hr.dts
index bce251a68591..ea9a0806b446 100644
--- a/arch/arm/boot/dts/bcm988312hr.dts
+++ b/arch/arm/boot/dts/bcm988312hr.dts
@@ -216,10 +216,10 @@
                         reg = <4>;
                 };
 
-                port@5 {
-                        ethernet = <&amac0>;
+                port@8 {
+                        ethernet = <&amac2>;
                         label = "cpu";
-                        reg = <5>;
+                        reg = <8>;
                         fixed-link {
                                 speed = <1000>;
                                 full-duplex;
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
index c75507922f7d..3962fa4b07f5 100644
--- a/arch/arm/boot/dts/da850-evm.dts
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -15,11 +15,16 @@
         compatible = "ti,da850-evm", "ti,da850";
         model = "DA850/AM1808/OMAP-L138 EVM";
 
+        chosen {
+                stdout-path = &serial2;
+        };
+
         aliases {
                 serial0 = &serial0;
                 serial1 = &serial1;
                 serial2 = &serial2;
                 ethernet0 = &eth0;
+                spi0 = &spi1;
         };
 
         soc@1c00000 {
diff --git a/arch/arm/boot/dts/da850-lego-ev3.dts b/arch/arm/boot/dts/da850-lego-ev3.dts
index 81942ae83e1f..1ffd87796cac 100644
--- a/arch/arm/boot/dts/da850-lego-ev3.dts
+++ b/arch/arm/boot/dts/da850-lego-ev3.dts
@@ -184,6 +184,23 @@
                 io-channel-names = "voltage", "current";
                 rechargeable-gpios = <&gpio 136 GPIO_ACTIVE_LOW>;
         };
+
+        /* ARM local RAM */
+        memory@ffff0000 {
+                compatible = "syscon", "simple-mfd";
+                reg = <0xffff0000 0x2000>; /* 8k */
+
+                /*
+                 * The I2C bootloader looks for this magic value to either
+                 * boot normally or boot into a firmware update mode.
+                 */
+                reboot-mode {
+                        compatible = "syscon-reboot-mode";
+                        offset = <0x1ffc>;
+                        mode-normal = <0x00000000>;
+                        mode-loader = <0x5555aaaa>;
+                };
+        };
 };
 
 &pmx_core {
@@ -293,7 +310,7 @@
          * EEPROM contains the first stage bootloader, HW ID and Bluetooth MAC.
          */
         eeprom@50 {
-                compatible = "microchip,24c128";
+                compatible = "microchip,24c128", "atmel,24c128";
                 pagesize = <64>;
                 read-only;
                 reg = <0x50>;
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index a7385c338ee9..f1425b0f3a54 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -87,33 +87,6 @@
                         DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
                 >;
         };
-
-        mmc1_pins_default: mmc1_pins_default {
-                pinctrl-single,pins = <
-                        DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14)       /* mmc1sdcd.gpio219 */
-                        DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
-                        DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
-                        DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
-                        DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
-                        DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
-                        DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
-                >;
-        };
-
-        mmc2_pins_default: mmc2_pins_default {
-                pinctrl-single,pins = <
-                        DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
-                        DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
-                        DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
-                        DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
-                        DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
-                        DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
-                        DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
-                        DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
-                        DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
-                        DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
-                >;
-        };
 };
 
 &i2c1 {
@@ -350,6 +323,7 @@
 &mmc2 {
         status = "okay";
         vmmc-supply = <&evm_1v8_sw>;
+        vqmmc-supply = <&evm_1v8_sw>;
         bus-width = <8>;
         pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v", "hs200_1_8v-rev11", "hs200_1_8v";
         pinctrl-0 = <&mmc2_pins_default>;
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index e4a420f16800..f4ddd86f2c77 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -92,8 +92,6 @@
                         clock-latency = <300000>; /* From omap-cpufreq driver */
 
                         /* cooling options */
-                        cooling-min-level = <0>;
-                        cooling-max-level = <2>;
                         #cooling-cells = <2>; /* min followed by max */
 
                         vbb-supply = <&abb_mpu>;
diff --git a/arch/arm/boot/dts/dra71-evm.dts b/arch/arm/boot/dts/dra71-evm.dts
index 41c9132eb550..ebc4bbae981e 100644
--- a/arch/arm/boot/dts/dra71-evm.dts
+++ b/arch/arm/boot/dts/dra71-evm.dts
@@ -24,13 +24,13 @@
 
                 regulator-name = "vddshv8";
                 regulator-min-microvolt = <1800000>;
-                regulator-max-microvolt = <3000000>;
+                regulator-max-microvolt = <3300000>;
                 regulator-boot-on;
                 vin-supply = <&evm_5v0>;
 
                 gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
                 states = <1800000 0x0
-                          3000000 0x1>;
+                          3300000 0x1>;
         };
 
         evm_1v8_sw: fixedregulator-evm_1v8 {
@@ -50,6 +50,19 @@
         };
 };
 
+&dra7_pmx_core {
+        mmc1_pins_default: mmc1_pins_default {
+                pinctrl-single,pins = <
+                        DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mmc1_clk.clk */
+                        DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+                        DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+                        DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+                        DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+                        DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+                >;
+        };
+};
+
 &i2c1 {
         status = "okay";
         clock-frequency = <400000>;
diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts
index c4fe7f8ef72a..2deb96405d06 100644
--- a/arch/arm/boot/dts/dra76-evm.dts
+++ b/arch/arm/boot/dts/dra76-evm.dts
@@ -9,6 +9,7 @@
 
 #include "dra76x.dtsi"
 #include "dra7-evm-common.dtsi"
+#include "dra76x-mmc-iodelay.dtsi"
 #include <dt-bindings/net/ti-dp83867.h>
 
 / {
@@ -100,46 +101,6 @@
         };
 };
 
-&dra7_pmx_core {
-        mmc1_pins_default: mmc1_pins_default {
-                pinctrl-single,pins = <
-                        DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14)       /* mmc1sdcd.gpio219 */
-                        DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
-                        DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
-                        DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
-                        DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
-                        DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
-                        DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
-                >;
-        };
-
-        mmc1_pins_sdr12: pinmux_mmc1_sdr12_pins {
-                pinctrl-single,pins = <
-                        DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
-                        DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
-                        DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
-                        DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
-                        DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
-                        DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
-                >;
-        };
-
-        mmc2_pins_default: mmc2_pins_default {
-                pinctrl-single,pins = <
-                        DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
-                        DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
-                        DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
-                        DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
-                        DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
-                        DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
-                        DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
-                        DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
-                        DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
-                        DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
-                >;
-        };
-};
-
 &i2c1 {
         status = "okay";
         clock-frequency = <400000>;
@@ -353,16 +314,21 @@
          * is always hardwired.
          */
         cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
-        pinctrl-names = "default";
+        pinctrl-names = "default", "hs";
         pinctrl-0 = <&mmc1_pins_default>;
+        pinctrl-1 = <&mmc1_pins_hs>;
 };
 
 &mmc2 {
         status = "okay";
         vmmc-supply = <&vio_1v8>;
+        vqmmc-supply = <&vio_1v8>;
         bus-width = <8>;
-        pinctrl-names = "default";
+        pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
         pinctrl-0 = <&mmc2_pins_default>;
+        pinctrl-1 = <&mmc2_pins_default>;
+        pinctrl-2 = <&mmc2_pins_default>;
+        pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_conf>;
 };
 
 /* No RTC on this device */
diff --git a/arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi b/arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi
new file mode 100644
index 000000000000..baba7b00eca7
--- /dev/null
+++ b/arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi
@@ -0,0 +1,285 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018 Texas Instruments
+// MMC IOdelay values for TI's DRA76x and AM576x SoCs.
+// Author: Sekhar Nori <nsekhar@ti.com>
+
+/*
+ * Rules for modifying this file:
+ * a) Update of this file should typically correspond to a datamanual revision.
+ *    Datamanual revision that was used should be updated in comment below.
+ *    If there is no update to datamanual, do not update the values. If you
+ *    need to use values different from that recommended by the datamanual
+ *    for your design, then you should consider adding values to the device-
+ *    -tree file for your board directly.
+ * b) We keep the mode names as close to the datamanual as possible. So
+ *    if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v,
+ *    we follow that in code too.
+ * c) If the values change between multiple revisions of silicon, we add
+ *    a revision tag to both the new and old entry. Use 'rev11' for PG 1.1,
+ *    'rev20' for PG 2.0 and so on.
+ * d) The node name and node label should be the exact same string. This is
+ *    to curb naming creativity and achieve consistency.
+ *
+ * Datamanual Revisions:
+ *
+ * DRA76x Silicon Revision 1.0: SPRS993A, Revised July 2017
+ *
+ */
+
+&dra7_pmx_core {
+        mmc1_pins_default: mmc1_pins_default {
+                pinctrl-single,pins = <
+                        DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
+                        DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+                        DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+                        DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+                        DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+                        DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+                >;
+        };
+
+        mmc1_pins_hs: mmc1_pins_hs {
+                pinctrl-single,pins = <
+                        DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
+                        DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
+                        DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
+                        DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
+                        DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */
+                        DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */
+                >;
+        };
+
+        mmc1_pins_sdr50: mmc1_pins_sdr50 {
+                pinctrl-single,pins = <
+                        DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)    /* mmc1_clk.clk */
+                        DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)    /* mmc1_cmd.cmd */
+                        DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)    /* mmc1_dat0.dat0 */
+                        DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)    /* mmc1_dat1.dat1 */
+                        DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)    /* mmc1_dat2.dat2 */
+                        DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)    /* mmc1_dat3.dat3 */
+                >;
+        };
+
+        mmc1_pins_ddr50: mmc1_pins_ddr50 {
+                pinctrl-single,pins = <
+                        DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)   /* mmc1_clk.clk */
+                        DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)   /* mmc1_cmd.cmd */
+                        DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)   /* mmc1_dat0.dat0 */
+                        DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)   /* mmc1_dat1.dat1 */
+                        DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)   /* mmc1_dat2.dat2 */
+                        DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)   /* mmc1_dat3.dat3 */
+                >;
+        };
+
+        mmc2_pins_default: mmc2_pins_default {
+                pinctrl-single,pins = <
+                        DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+                        DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+                        DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+                        DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+                        DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+                        DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+                        DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+                        DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+                        DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+                        DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+                >;
+        };
+
+        mmc2_pins_hs200: mmc2_pins_hs200 {
+                pinctrl-single,pins = <
+                        DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+                        DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+                        DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+                        DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+                        DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+                        DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+                        DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+                        DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+                        DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+                        DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+                >;
+        };
+
+        mmc3_pins_default: mmc3_pins_default {
+                pinctrl-single,pins = <
+                        DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
+                        DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
+                        DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
+                        DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
+                        DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
+                        DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
+                >;
+        };
+
+        mmc4_pins_hs: mmc4_pins_hs {
+                pinctrl-single,pins = <
+                        DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
+                        DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
+                        DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
+                        DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
+                        DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
+                        DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
+                >;
+        };
+};
+
+&dra7_iodelay_core {
+
+        /* Corresponds to MMC1_DDR_MANUAL1 in datamanual */
+        mmc1_iodelay_ddr_conf: mmc1_iodelay_ddr_conf {
+                pinctrl-pin-array = <
+                        0x618 A_DELAY_PS(489) G_DELAY_PS(0)     /* CFG_MMC1_CLK_IN */
+                        0x624 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_CMD_IN */
+                        0x630 A_DELAY_PS(374) G_DELAY_PS(0)     /* CFG_MMC1_DAT0_IN */
+                        0x63c A_DELAY_PS(31) G_DELAY_PS(0)      /* CFG_MMC1_DAT1_IN */
+                        0x648 A_DELAY_PS(56) G_DELAY_PS(0)      /* CFG_MMC1_DAT2_IN */
+                        0x654 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT3_IN */
+                        0x620 A_DELAY_PS(1355) G_DELAY_PS(0)    /* CFG_MMC1_CLK_OUT */
+                        0x628 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_CMD_OEN */
+                        0x62c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_CMD_OUT */
+                        0x634 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT0_OEN */
+                        0x638 A_DELAY_PS(0) G_DELAY_PS(4)       /* CFG_MMC1_DAT0_OUT */
+                        0x640 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT1_OEN */
+                        0x644 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT1_OUT */
+                        0x64c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT2_OEN */
+                        0x650 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT2_OUT */
+                        0x658 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT3_OEN */
+                        0x65c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT3_OUT */
+                >;
+        };
+
+        /* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */
+        mmc1_iodelay_sdr104_conf: mmc1_iodelay_sdr104_conf {
+                pinctrl-pin-array = <
+                        0x620 A_DELAY_PS(892) G_DELAY_PS(0)     /* CFG_MMC1_CLK_OUT */
+                        0x628 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_CMD_OEN */
+                        0x62c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_CMD_OUT */
+                        0x634 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT0_OEN */
+                        0x638 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT0_OUT */
+                        0x640 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT1_OEN */
+                        0x644 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT1_OUT */
+                        0x64c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT2_OEN */
+                        0x650 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT2_OUT */
+                        0x658 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT3_OEN */
+                        0x65c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT3_OUT */
+                >;
+        };
+
+        /* Corresponds to MMC2_HS200_MANUAL1 in datamanual */
+        mmc2_iodelay_hs200_conf: mmc2_iodelay_hs200_conf {
+                pinctrl-pin-array = <
+                        0x190 A_DELAY_PS(384) G_DELAY_PS(0)       /* CFG_GPMC_A19_OEN */
+                        0x194 A_DELAY_PS(0) G_DELAY_PS(174)       /* CFG_GPMC_A19_OUT */
+                        0x1a8 A_DELAY_PS(410) G_DELAY_PS(0)       /* CFG_GPMC_A20_OEN */
+                        0x1ac A_DELAY_PS(85) G_DELAY_PS(0)        /* CFG_GPMC_A20_OUT */
+                        0x1b4 A_DELAY_PS(468) G_DELAY_PS(0)       /* CFG_GPMC_A21_OEN */
+                        0x1b8 A_DELAY_PS(139) G_DELAY_PS(0)       /* CFG_GPMC_A21_OUT */
+                        0x1c0 A_DELAY_PS(676) G_DELAY_PS(0)       /* CFG_GPMC_A22_OEN */
+                        0x1c4 A_DELAY_PS(69) G_DELAY_PS(0)        /* CFG_GPMC_A22_OUT */
+                        0x1d0 A_DELAY_PS(1062) G_DELAY_PS(154)    /* CFG_GPMC_A23_OUT */
+                        0x1d8 A_DELAY_PS(640) G_DELAY_PS(0)       /* CFG_GPMC_A24_OEN */
+                        0x1dc A_DELAY_PS(0) G_DELAY_PS(0)         /* CFG_GPMC_A24_OUT */
+                        0x1e4 A_DELAY_PS(356) G_DELAY_PS(0)       /* CFG_GPMC_A25_OEN */
+                        0x1e8 A_DELAY_PS(0) G_DELAY_PS(0)         /* CFG_GPMC_A25_OUT */
+                        0x1f0 A_DELAY_PS(579) G_DELAY_PS(0)       /* CFG_GPMC_A26_OEN */
+                        0x1f4 A_DELAY_PS(0) G_DELAY_PS(0)         /* CFG_GPMC_A26_OUT */
+                        0x1fc A_DELAY_PS(435) G_DELAY_PS(0)       /* CFG_GPMC_A27_OEN */
+                        0x200 A_DELAY_PS(36) G_DELAY_PS(0)        /* CFG_GPMC_A27_OUT */
+                        0x364 A_DELAY_PS(759) G_DELAY_PS(0)       /* CFG_GPMC_CS1_OEN */
+                        0x368 A_DELAY_PS(72) G_DELAY_PS(0)        /* CFG_GPMC_CS1_OUT */
+              >;
+        };
+
+        /* Corresponds to MMC3_MANUAL1 in datamanual */
+        mmc3_iodelay_manual1_conf: mmc3_iodelay_manual1_conf {
+                pinctrl-pin-array = <
+                        0x678 A_DELAY_PS(0) G_DELAY_PS(386)     /* CFG_MMC3_CLK_IN */
+                        0x680 A_DELAY_PS(605) G_DELAY_PS(0)     /* CFG_MMC3_CLK_OUT */
+                        0x684 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_CMD_IN */
+                        0x688 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_CMD_OEN */
+                        0x68c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_CMD_OUT */
+                        0x690 A_DELAY_PS(171) G_DELAY_PS(0)     /* CFG_MMC3_DAT0_IN */
+                        0x694 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT0_OEN */
+                        0x698 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT0_OUT */
+                        0x69c A_DELAY_PS(221) G_DELAY_PS(0)     /* CFG_MMC3_DAT1_IN */
+                        0x6a0 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT1_OEN */
+                        0x6a4 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT1_OUT */
+                        0x6a8 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT2_IN */
+                        0x6ac A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT2_OEN */
+                        0x6b0 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT2_OUT */
+                        0x6b4 A_DELAY_PS(474) G_DELAY_PS(0)     /* CFG_MMC3_DAT3_IN */
+                        0x6b8 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT3_OEN */
+                        0x6bc A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT3_OUT */
+                >;
+        };
+
+        /* Corresponds to MMC3_MANUAL2 in datamanual */
+        mmc3_iodelay_sdr50_conf: mmc3_iodelay_sdr50_conf {
+                pinctrl-pin-array = <
+                        0x678 A_DELAY_PS(852) G_DELAY_PS(0)     /* CFG_MMC3_CLK_IN */
+                        0x680 A_DELAY_PS(94) G_DELAY_PS(0)      /* CFG_MMC3_CLK_OUT */
+                        0x684 A_DELAY_PS(122) G_DELAY_PS(0)     /* CFG_MMC3_CMD_IN */
+                        0x688 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_CMD_OEN */
+                        0x68c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_CMD_OUT */
+                        0x690 A_DELAY_PS(91) G_DELAY_PS(0)      /* CFG_MMC3_DAT0_IN */
+                        0x694 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT0_OEN */
+                        0x698 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT0_OUT */
+                        0x69c A_DELAY_PS(57) G_DELAY_PS(0)      /* CFG_MMC3_DAT1_IN */
+                        0x6a0 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT1_OEN */
+                        0x6a4 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT1_OUT */
+                        0x6a8 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT2_IN */
+                        0x6ac A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT2_OEN */
+                        0x6b0 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT2_OUT */
+                        0x6b4 A_DELAY_PS(375) G_DELAY_PS(0)     /* CFG_MMC3_DAT3_IN */
+                        0x6b8 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT3_OEN */
+                        0x6bc A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT3_OUT */
+                >;
+        };
+
+        /* Corresponds to MMC4_MANUAL1 in datamanual */
+        mmc4_iodelay_manual1_conf: mmc4_iodelay_manual1_conf {
+                pinctrl-pin-array = <
+                        0x840 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART1_CTSN_IN */
+                        0x848 A_DELAY_PS(1147) G_DELAY_PS(0)    /* CFG_UART1_CTSN_OUT */
+                        0x84c A_DELAY_PS(1834) G_DELAY_PS(0)    /* CFG_UART1_RTSN_IN */
+                        0x850 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART1_RTSN_OEN */
+                        0x854 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART1_RTSN_OUT */
+                        0x870 A_DELAY_PS(2165) G_DELAY_PS(0)    /* CFG_UART2_CTSN_IN */
+                        0x874 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_CTSN_OEN */
+                        0x878 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_CTSN_OUT */
+                        0x87c A_DELAY_PS(1929) G_DELAY_PS(64)   /* CFG_UART2_RTSN_IN */
+                        0x880 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_RTSN_OEN */
+                        0x884 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_RTSN_OUT */
+                        0x888 A_DELAY_PS(1935) G_DELAY_PS(128)  /* CFG_UART2_RXD_IN */
+                        0x88c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_RXD_OEN */
+                        0x890 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_RXD_OUT */
+                        0x894 A_DELAY_PS(2172) G_DELAY_PS(44)   /* CFG_UART2_TXD_IN */
+                        0x898 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_TXD_OEN */
+                        0x89c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_TXD_OUT */
+                >;
+        };
+
+        /* Corresponds to MMC4_DS_MANUAL1 in datamanual */
+        mmc4_iodelay_default_conf: mmc4_iodelay_default_conf {
+                pinctrl-pin-array = <
+                        0x840 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART1_CTSN_IN */
+                        0x848 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART1_CTSN_OUT */
+                        0x84c A_DELAY_PS(307) G_DELAY_PS(0)     /* CFG_UART1_RTSN_IN */
+                        0x850 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART1_RTSN_OEN */
+                        0x854 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART1_RTSN_OUT */
+                        0x870 A_DELAY_PS(785) G_DELAY_PS(0)     /* CFG_UART2_CTSN_IN */
+                        0x874 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_CTSN_OEN */
+                        0x878 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_CTSN_OUT */
+                        0x87c A_DELAY_PS(613) G_DELAY_PS(0)     /* CFG_UART2_RTSN_IN */
+                        0x880 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_RTSN_OEN */
+                        0x884 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_RTSN_OUT */
+                        0x888 A_DELAY_PS(683) G_DELAY_PS(0)     /* CFG_UART2_RXD_IN */
+                        0x88c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_RXD_OEN */
+                        0x890 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_RXD_OUT */
+                        0x894 A_DELAY_PS(835) G_DELAY_PS(0)     /* CFG_UART2_TXD_IN */
+                        0x898 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_TXD_OEN */
+                        0x89c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_TXD_OUT */
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts
index 60d0a732833a..c238407133bf 100644
--- a/arch/arm/boot/dts/emev2-kzm9d.dts
+++ b/arch/arm/boot/dts/emev2-kzm9d.dts
@@ -38,28 +38,28 @@
                 #size-cells = <0>;
 
                 one {
-                        debounce_interval = <50>;
+                        debounce-interval = <50>;
                         wakeup-source;
                         label = "DSW2-1";
                         linux,code = <KEY_1>;
                         gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
                 };
                 two {
-                        debounce_interval = <50>;
+                        debounce-interval = <50>;
                         wakeup-source;
                         label = "DSW2-2";
                         linux,code = <KEY_2>;
                         gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
                 };
                 three {
-                        debounce_interval = <50>;
+                        debounce-interval = <50>;
                         wakeup-source;
                         label = "DSW2-3";
                         linux,code = <KEY_3>;
                         gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
                 };
                 four {
-                        debounce_interval = <50>;
+                        debounce-interval = <50>;
                         wakeup-source;
                         label = "DSW2-4";
                         linux,code = <KEY_4>;
diff --git a/arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi b/arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi
index 25186ac4188d..1dbf3bbff8d3 100644
--- a/arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi
+++ b/arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Samsung's Exynos SoC MFC (Video Codec) reserved memory common definition.
  *
  * Copyright (c) 2016 Samsung Electronics Co., Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 
 / {
diff --git a/arch/arm/boot/dts/exynos-syscon-restart.dtsi b/arch/arm/boot/dts/exynos-syscon-restart.dtsi
index 09a2040054ed..4b3dd0549a54 100644
--- a/arch/arm/boot/dts/exynos-syscon-restart.dtsi
+++ b/arch/arm/boot/dts/exynos-syscon-restart.dtsi
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Samsung's Exynos SoC syscon reboot/poweroff nodes common definition.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 
 / {
diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi
index 0aa577fe9f95..620b50c19ead 100644
--- a/arch/arm/boot/dts/exynos3250-artik5.dtsi
+++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi
@@ -245,6 +245,7 @@
                                 regulator-name = "VLDO23_1.8V";
                                 regulator-min-microvolt = <1800000>;
                                 regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
                         };
 
                         ldo24_reg: LDO24 {
@@ -316,6 +317,41 @@
         status = "okay";
 };
 
+&mshc_1 {
+        cap-sd-highspeed;
+        cap-sdio-irq;
+        disable-wp;
+        non-removable;
+        keep-power-in-suspend;
+        fifo-depth = <0x40>;
+        vqmmc-supply = <&ldo11_reg>;
+        /*
+         * Voltage negotiation is broken for the SDIO periph so we
+         * can't actually set the voltage here.
+         * vmmc-supply = <&ldo23_reg>;
+         */
+        card-detect-delay = <500>;
+        clock-frequency = <100000000>;
+        max-frequency = <100000000>;
+        samsung,dw-mshc-ciu-div = <3>;
+        samsung,dw-mshc-sdr-timing = <0 1>;
+        samsung,dw-mshc-ddr-timing = <1 2>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd1_cmd &sd1_clk &sd1_bus1 &sd1_bus4 &wlanen>;
+        bus-width = <4>;
+        status = "okay";
+};
+
+&pinctrl_1 {
+        wlanen: wlanen {
+                samsung,pins = "gpx2-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV3>;
+                samsung,pin-val = <1>;
+        };
+};
+
 &rtc {
         clocks = <&cmu CLK_RTC>, <&s2mps14_osc S2MPS11_CLK_AP>;
         clock-names = "rtc", "rtc_src";
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index b8fb94f5daa8..0a5f989d963b 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -161,34 +161,39 @@
                         syscon = <&pmu_system_controller>;
                 };
 
-                pd_cam: cam-power-domain@10023c00 {
+                pd_cam: power-domain@10023c00 {
                         compatible = "samsung,exynos4210-pd";
                         reg = <0x10023C00 0x20>;
                         #power-domain-cells = <0>;
+                        label = "CAM";
                 };
 
-                pd_mfc: mfc-power-domain@10023c40 {
+                pd_mfc: power-domain@10023c40 {
                         compatible = "samsung,exynos4210-pd";
                         reg = <0x10023C40 0x20>;
                         #power-domain-cells = <0>;
+                        label = "MFC";
                 };
 
-                pd_g3d: g3d-power-domain@10023c60 {
+                pd_g3d: power-domain@10023c60 {
                         compatible = "samsung,exynos4210-pd";
                         reg = <0x10023C60 0x20>;
                         #power-domain-cells = <0>;
+                        label = "G3D";
                 };
 
-                pd_lcd0: lcd0-power-domain@10023c80 {
+                pd_lcd0: power-domain@10023c80 {
                         compatible = "samsung,exynos4210-pd";
                         reg = <0x10023C80 0x20>;
                         #power-domain-cells = <0>;
+                        label = "LCD0";
                 };
 
-                pd_isp: isp-power-domain@10023ca0 {
+                pd_isp: power-domain@10023ca0 {
                         compatible = "samsung,exynos4210-pd";
                         reg = <0x10023CA0 0x20>;
                         #power-domain-cells = <0>;
+                        label = "ISP";
                 };
 
                 cmu: clock-controller@10030000 {
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 6d59cc827649..909a9f2bf5be 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -52,961 +52,976 @@
                 serial3 = &serial_3;
         };
 
-        clock_audss: clock-controller@3810000 {
-                compatible = "samsung,exynos4210-audss-clock";
-                reg = <0x03810000 0x0C>;
-                #clock-cells = <1>;
-                clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
-                         <&clock CLK_SCLK_AUDIO0>, <&clock CLK_SCLK_AUDIO0>;
-                clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
-        };
-
-        i2s0: i2s@3830000 {
-                compatible = "samsung,s5pv210-i2s";
-                reg = <0x03830000 0x100>;
-                clocks = <&clock_audss EXYNOS_I2S_BUS>,
-                         <&clock_audss EXYNOS_DOUT_AUD_BUS>,
-                         <&clock_audss EXYNOS_SCLK_I2S>;
-                clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
-                #clock-cells = <1>;
-                clock-output-names = "i2s_cdclk0";
-                dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>;
-                dma-names = "tx", "rx", "tx-sec";
-                samsung,idma-addr = <0x03000000>;
-                #sound-dai-cells = <1>;
-                status = "disabled";
-        };
+        soc: soc {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
 
-        chipid@10000000 {
-                compatible = "samsung,exynos4210-chipid";
-                reg = <0x10000000 0x100>;
-        };
+                clock_audss: clock-controller@3810000 {
+                        compatible = "samsung,exynos4210-audss-clock";
+                        reg = <0x03810000 0x0C>;
+                        #clock-cells = <1>;
+                        clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
+                                 <&clock CLK_SCLK_AUDIO0>,
+                                 <&clock CLK_SCLK_AUDIO0>;
+                        clock-names = "pll_ref", "pll_in", "sclk_audio",
+                                      "sclk_pcm_in";
+                };
 
-        scu: snoop-control-unit@10500000 {
-                compatible = "arm,cortex-a9-scu";
-                reg = <0x10500000 0x2000>;
-        };
+                i2s0: i2s@3830000 {
+                        compatible = "samsung,s5pv210-i2s";
+                        reg = <0x03830000 0x100>;
+                        clocks = <&clock_audss EXYNOS_I2S_BUS>,
+                                 <&clock_audss EXYNOS_DOUT_AUD_BUS>,
+                                 <&clock_audss EXYNOS_SCLK_I2S>;
+                        clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
+                        #clock-cells = <1>;
+                        clock-output-names = "i2s_cdclk0";
+                        dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>;
+                        dma-names = "tx", "rx", "tx-sec";
+                        samsung,idma-addr = <0x03000000>;
+                        #sound-dai-cells = <1>;
+                        status = "disabled";
+                };
 
-        memory-controller@12570000 {
-                compatible = "samsung,exynos4210-srom";
-                reg = <0x12570000 0x14>;
-        };
+                chipid@10000000 {
+                        compatible = "samsung,exynos4210-chipid";
+                        reg = <0x10000000 0x100>;
+                };
 
-        mipi_phy: video-phy {
-                compatible = "samsung,s5pv210-mipi-video-phy";
-                #phy-cells = <1>;
-                syscon = <&pmu_system_controller>;
-        };
+                scu: snoop-control-unit@10500000 {
+                        compatible = "arm,cortex-a9-scu";
+                        reg = <0x10500000 0x2000>;
+                };
 
-        pd_mfc: mfc-power-domain@10023c40 {
-                compatible = "samsung,exynos4210-pd";
-                reg = <0x10023C40 0x20>;
-                #power-domain-cells = <0>;
-                label = "MFC";
-        };
+                memory-controller@12570000 {
+                        compatible = "samsung,exynos4210-srom";
+                        reg = <0x12570000 0x14>;
+                };
 
-        pd_g3d: g3d-power-domain@10023c60 {
-                compatible = "samsung,exynos4210-pd";
-                reg = <0x10023C60 0x20>;
-                #power-domain-cells = <0>;
-                label = "G3D";
-        };
+                mipi_phy: video-phy {
+                        compatible = "samsung,s5pv210-mipi-video-phy";
+                        #phy-cells = <1>;
+                        syscon = <&pmu_system_controller>;
+                };
 
-        pd_lcd0: lcd0-power-domain@10023c80 {
-                compatible = "samsung,exynos4210-pd";
-                reg = <0x10023C80 0x20>;
-                #power-domain-cells = <0>;
-                label = "LCD0";
-        };
+                pd_mfc: mfc-power-domain@10023c40 {
+                        compatible = "samsung,exynos4210-pd";
+                        reg = <0x10023C40 0x20>;
+                        #power-domain-cells = <0>;
+                        label = "MFC";
+                };
 
-        pd_tv: tv-power-domain@10023c20 {
-                compatible = "samsung,exynos4210-pd";
-                reg = <0x10023C20 0x20>;
-                #power-domain-cells = <0>;
-                power-domains = <&pd_lcd0>;
-                label = "TV";
-        };
+                pd_g3d: g3d-power-domain@10023c60 {
+                        compatible = "samsung,exynos4210-pd";
+                        reg = <0x10023C60 0x20>;
+                        #power-domain-cells = <0>;
+                        label = "G3D";
+                };
 
-        pd_cam: cam-power-domain@10023c00 {
-                compatible = "samsung,exynos4210-pd";
-                reg = <0x10023C00 0x20>;
-                #power-domain-cells = <0>;
-                label = "CAM";
-        };
+                pd_lcd0: lcd0-power-domain@10023c80 {
+                        compatible = "samsung,exynos4210-pd";
+                        reg = <0x10023C80 0x20>;
+                        #power-domain-cells = <0>;
+                        label = "LCD0";
+                };
 
-        pd_gps: gps-power-domain@10023ce0 {
-                compatible = "samsung,exynos4210-pd";
-                reg = <0x10023CE0 0x20>;
-                #power-domain-cells = <0>;
-                label = "GPS";
-        };
+                pd_tv: tv-power-domain@10023c20 {
+                        compatible = "samsung,exynos4210-pd";
+                        reg = <0x10023C20 0x20>;
+                        #power-domain-cells = <0>;
+                        power-domains = <&pd_lcd0>;
+                        label = "TV";
+                };
 
-        pd_gps_alive: gps-alive-power-domain@10023d00 {
-                compatible = "samsung,exynos4210-pd";
-                reg = <0x10023D00 0x20>;
-                #power-domain-cells = <0>;
-                label = "GPS alive";
-        };
+                pd_cam: cam-power-domain@10023c00 {
+                        compatible = "samsung,exynos4210-pd";
+                        reg = <0x10023C00 0x20>;
+                        #power-domain-cells = <0>;
+                        label = "CAM";
+                };
 
-        gic: interrupt-controller@10490000 {
-                compatible = "arm,cortex-a9-gic";
-                #interrupt-cells = <3>;
-                interrupt-controller;
-                reg = <0x10490000 0x10000>, <0x10480000 0x10000>;
-        };
+                pd_gps: gps-power-domain@10023ce0 {
+                        compatible = "samsung,exynos4210-pd";
+                        reg = <0x10023CE0 0x20>;
+                        #power-domain-cells = <0>;
+                        label = "GPS";
+                };
 
-        combiner: interrupt-controller@10440000 {
-                compatible = "samsung,exynos4210-combiner";
-                #interrupt-cells = <2>;
-                interrupt-controller;
-                reg = <0x10440000 0x1000>;
-        };
+                pd_gps_alive: gps-alive-power-domain@10023d00 {
+                        compatible = "samsung,exynos4210-pd";
+                        reg = <0x10023D00 0x20>;
+                        #power-domain-cells = <0>;
+                        label = "GPS alive";
+                };
 
-        pmu {
-                compatible = "arm,cortex-a9-pmu";
-                interrupt-parent = <&combiner>;
-                interrupts = <2 2>, <3 2>;
-        };
+                gic: interrupt-controller@10490000 {
+                        compatible = "arm,cortex-a9-gic";
+                        #interrupt-cells = <3>;
+                        interrupt-controller;
+                        reg = <0x10490000 0x10000>, <0x10480000 0x10000>;
+                };
 
-        sys_reg: syscon@10010000 {
-                compatible = "samsung,exynos4-sysreg", "syscon";
-                reg = <0x10010000 0x400>;
-        };
+                combiner: interrupt-controller@10440000 {
+                        compatible = "samsung,exynos4210-combiner";
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        reg = <0x10440000 0x1000>;
+                };
 
-        pmu_system_controller: system-controller@10020000 {
-                compatible = "samsung,exynos4210-pmu", "syscon";
-                reg = <0x10020000 0x4000>;
-                interrupt-controller;
-                #interrupt-cells = <3>;
-                interrupt-parent = <&gic>;
-        };
+                pmu: pmu {
+                        compatible = "arm,cortex-a9-pmu";
+                        interrupt-parent = <&combiner>;
+                        interrupts = <2 2>, <3 2>;
+                };
 
-        dsi_0: dsi@11c80000 {
-                compatible = "samsung,exynos4210-mipi-dsi";
-                reg = <0x11C80000 0x10000>;
-                interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
-                power-domains = <&pd_lcd0>;
-                phys = <&mipi_phy 1>;
-                phy-names = "dsim";
-                clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
-                clock-names = "bus_clk", "sclk_mipi";
-                status = "disabled";
-                #address-cells = <1>;
-                #size-cells = <0>;
-        };
+                sys_reg: syscon@10010000 {
+                        compatible = "samsung,exynos4-sysreg", "syscon";
+                        reg = <0x10010000 0x400>;
+                };
 
-        camera {
-                compatible = "samsung,fimc", "simple-bus";
-                status = "disabled";
-                #address-cells = <1>;
-                #size-cells = <1>;
-                #clock-cells = <1>;
-                clock-output-names = "cam_a_clkout", "cam_b_clkout";
-                ranges;
+                pmu_system_controller: system-controller@10020000 {
+                        compatible = "samsung,exynos4210-pmu", "syscon";
+                        reg = <0x10020000 0x4000>;
+                        interrupt-controller;
+                        #interrupt-cells = <3>;
+                        interrupt-parent = <&gic>;
+                };
 
-                fimc_0: fimc@11800000 {
-                        compatible = "samsung,exynos4210-fimc";
-                        reg = <0x11800000 0x1000>;
-                        interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>;
-                        clock-names = "fimc", "sclk_fimc";
-                        power-domains = <&pd_cam>;
-                        samsung,sysreg = <&sys_reg>;
-                        iommus = <&sysmmu_fimc0>;
+                dsi_0: dsi@11c80000 {
+                        compatible = "samsung,exynos4210-mipi-dsi";
+                        reg = <0x11C80000 0x10000>;
+                        interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+                        power-domains = <&pd_lcd0>;
+                        phys = <&mipi_phy 1>;
+                        phy-names = "dsim";
+                        clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
+                        clock-names = "bus_clk", "sclk_mipi";
                         status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
                 };
 
-                fimc_1: fimc@11810000 {
-                        compatible = "samsung,exynos4210-fimc";
-                        reg = <0x11810000 0x1000>;
-                        interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>;
-                        clock-names = "fimc", "sclk_fimc";
-                        power-domains = <&pd_cam>;
-                        samsung,sysreg = <&sys_reg>;
-                        iommus = <&sysmmu_fimc1>;
+                camera: camera {
+                        compatible = "samsung,fimc", "simple-bus";
                         status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        #clock-cells = <1>;
+                        clock-output-names = "cam_a_clkout", "cam_b_clkout";
+                        ranges;
+
+                        fimc_0: fimc@11800000 {
+                                compatible = "samsung,exynos4210-fimc";
+                                reg = <0x11800000 0x1000>;
+                                interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clock CLK_FIMC0>,
+                                         <&clock CLK_SCLK_FIMC0>;
+                                clock-names = "fimc", "sclk_fimc";
+                                power-domains = <&pd_cam>;
+                                samsung,sysreg = <&sys_reg>;
+                                iommus = <&sysmmu_fimc0>;
+                                status = "disabled";
+                        };
+
+                        fimc_1: fimc@11810000 {
+                                compatible = "samsung,exynos4210-fimc";
+                                reg = <0x11810000 0x1000>;
+                                interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clock CLK_FIMC1>,
+                                         <&clock CLK_SCLK_FIMC1>;
+                                clock-names = "fimc", "sclk_fimc";
+                                power-domains = <&pd_cam>;
+                                samsung,sysreg = <&sys_reg>;
+                                iommus = <&sysmmu_fimc1>;
+                                status = "disabled";
+                        };
+
+                        fimc_2: fimc@11820000 {
+                                compatible = "samsung,exynos4210-fimc";
+                                reg = <0x11820000 0x1000>;
+                                interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clock CLK_FIMC2>,
+                                         <&clock CLK_SCLK_FIMC2>;
+                                clock-names = "fimc", "sclk_fimc";
+                                power-domains = <&pd_cam>;
+                                samsung,sysreg = <&sys_reg>;
+                                iommus = <&sysmmu_fimc2>;
+                                status = "disabled";
+                        };
+
+                        fimc_3: fimc@11830000 {
+                                compatible = "samsung,exynos4210-fimc";
+                                reg = <0x11830000 0x1000>;
+                                interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clock CLK_FIMC3>,
+                                         <&clock CLK_SCLK_FIMC3>;
+                                clock-names = "fimc", "sclk_fimc";
+                                power-domains = <&pd_cam>;
+                                samsung,sysreg = <&sys_reg>;
+                                iommus = <&sysmmu_fimc3>;
+                                status = "disabled";
+                        };
+
+                        csis_0: csis@11880000 {
+                                compatible = "samsung,exynos4210-csis";
+                                reg = <0x11880000 0x4000>;
+                                interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clock CLK_CSIS0>,
+                                         <&clock CLK_SCLK_CSIS0>;
+                                clock-names = "csis", "sclk_csis";
+                                bus-width = <4>;
+                                power-domains = <&pd_cam>;
+                                phys = <&mipi_phy 0>;
+                                phy-names = "csis";
+                                status = "disabled";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        csis_1: csis@11890000 {
+                                compatible = "samsung,exynos4210-csis";
+                                reg = <0x11890000 0x4000>;
+                                interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clock CLK_CSIS1>,
+                                         <&clock CLK_SCLK_CSIS1>;
+                                clock-names = "csis", "sclk_csis";
+                                bus-width = <2>;
+                                power-domains = <&pd_cam>;
+                                phys = <&mipi_phy 2>;
+                                phy-names = "csis";
+                                status = "disabled";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
                 };
 
-                fimc_2: fimc@11820000 {
-                        compatible = "samsung,exynos4210-fimc";
-                        reg = <0x11820000 0x1000>;
-                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>;
-                        clock-names = "fimc", "sclk_fimc";
-                        power-domains = <&pd_cam>;
-                        samsung,sysreg = <&sys_reg>;
-                        iommus = <&sysmmu_fimc2>;
+                rtc: rtc@10070000 {
+                        compatible = "samsung,s3c6410-rtc";
+                        reg = <0x10070000 0x100>;
+                        interrupt-parent = <&pmu_system_controller>;
+                        interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_RTC>;
+                        clock-names = "rtc";
                         status = "disabled";
                 };
 
-                fimc_3: fimc@11830000 {
-                        compatible = "samsung,exynos4210-fimc";
-                        reg = <0x11830000 0x1000>;
-                        interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>;
-                        clock-names = "fimc", "sclk_fimc";
-                        power-domains = <&pd_cam>;
-                        samsung,sysreg = <&sys_reg>;
-                        iommus = <&sysmmu_fimc3>;
+                keypad: keypad@100a0000 {
+                        compatible = "samsung,s5pv210-keypad";
+                        reg = <0x100A0000 0x100>;
+                        interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_KEYIF>;
+                        clock-names = "keypad";
                         status = "disabled";
                 };
 
-                csis_0: csis@11880000 {
-                        compatible = "samsung,exynos4210-csis";
-                        reg = <0x11880000 0x4000>;
-                        interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>;
-                        clock-names = "csis", "sclk_csis";
-                        bus-width = <4>;
-                        power-domains = <&pd_cam>;
-                        phys = <&mipi_phy 0>;
-                        phy-names = "csis";
+                sdhci_0: sdhci@12510000 {
+                        compatible = "samsung,exynos4210-sdhci";
+                        reg = <0x12510000 0x100>;
+                        interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
+                        clock-names = "hsmmc", "mmc_busclk.2";
                         status = "disabled";
-                        #address-cells = <1>;
-                        #size-cells = <0>;
                 };
 
-                csis_1: csis@11890000 {
-                        compatible = "samsung,exynos4210-csis";
-                        reg = <0x11890000 0x4000>;
-                        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>;
-                        clock-names = "csis", "sclk_csis";
-                        bus-width = <2>;
-                        power-domains = <&pd_cam>;
-                        phys = <&mipi_phy 2>;
-                        phy-names = "csis";
+                sdhci_1: sdhci@12520000 {
+                        compatible = "samsung,exynos4210-sdhci";
+                        reg = <0x12520000 0x100>;
+                        interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
+                        clock-names = "hsmmc", "mmc_busclk.2";
                         status = "disabled";
-                        #address-cells = <1>;
-                        #size-cells = <0>;
                 };
-        };
-
-        rtc: rtc@10070000 {
-                compatible = "samsung,s3c6410-rtc";
-                reg = <0x10070000 0x100>;
-                interrupt-parent = <&pmu_system_controller>;
-                interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_RTC>;
-                clock-names = "rtc";
-                status = "disabled";
-        };
-
-        keypad: keypad@100a0000 {
-                compatible = "samsung,s5pv210-keypad";
-                reg = <0x100A0000 0x100>;
-                interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_KEYIF>;
-                clock-names = "keypad";
-                status = "disabled";
-        };
-
-        sdhci_0: sdhci@12510000 {
-                compatible = "samsung,exynos4210-sdhci";
-                reg = <0x12510000 0x100>;
-                interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
-                clock-names = "hsmmc", "mmc_busclk.2";
-                status = "disabled";
-        };
 
-        sdhci_1: sdhci@12520000 {
-                compatible = "samsung,exynos4210-sdhci";
-                reg = <0x12520000 0x100>;
-                interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
-                clock-names = "hsmmc", "mmc_busclk.2";
-                status = "disabled";
-        };
-
-        sdhci_2: sdhci@12530000 {
-                compatible = "samsung,exynos4210-sdhci";
-                reg = <0x12530000 0x100>;
-                interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
-                clock-names = "hsmmc", "mmc_busclk.2";
-                status = "disabled";
-        };
-
-        sdhci_3: sdhci@12540000 {
-                compatible = "samsung,exynos4210-sdhci";
-                reg = <0x12540000 0x100>;
-                interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
-                clock-names = "hsmmc", "mmc_busclk.2";
-                status = "disabled";
-        };
-
-        exynos_usbphy: exynos-usbphy@125b0000 {
-                compatible = "samsung,exynos4210-usb2-phy";
-                reg = <0x125B0000 0x100>;
-                samsung,pmureg-phandle = <&pmu_system_controller>;
-                clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>;
-                clock-names = "phy", "ref";
-                #phy-cells = <1>;
-                status = "disabled";
-        };
-
-        hsotg: hsotg@12480000 {
-                compatible = "samsung,s3c6400-hsotg";
-                reg = <0x12480000 0x20000>;
-                interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_USB_DEVICE>;
-                clock-names = "otg";
-                phys = <&exynos_usbphy 0>;
-                phy-names = "usb2-phy";
-                status = "disabled";
-        };
+                sdhci_2: sdhci@12530000 {
+                        compatible = "samsung,exynos4210-sdhci";
+                        reg = <0x12530000 0x100>;
+                        interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
+                        clock-names = "hsmmc", "mmc_busclk.2";
+                        status = "disabled";
+                };
 
-        ehci: ehci@12580000 {
-                compatible = "samsung,exynos4210-ehci";
-                reg = <0x12580000 0x100>;
-                interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_USB_HOST>;
-                clock-names = "usbhost";
-                status = "disabled";
-                #address-cells = <1>;
-                #size-cells = <0>;
-                port@0 {
-                        reg = <0>;
-                        phys = <&exynos_usbphy 1>;
+                sdhci_3: sdhci@12540000 {
+                        compatible = "samsung,exynos4210-sdhci";
+                        reg = <0x12540000 0x100>;
+                        interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
+                        clock-names = "hsmmc", "mmc_busclk.2";
                         status = "disabled";
                 };
-                port@1 {
-                        reg = <1>;
-                        phys = <&exynos_usbphy 2>;
+
+                exynos_usbphy: exynos-usbphy@125b0000 {
+                        compatible = "samsung,exynos4210-usb2-phy";
+                        reg = <0x125B0000 0x100>;
+                        samsung,pmureg-phandle = <&pmu_system_controller>;
+                        clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>;
+                        clock-names = "phy", "ref";
+                        #phy-cells = <1>;
                         status = "disabled";
                 };
-                port@2 {
-                        reg = <2>;
-                        phys = <&exynos_usbphy 3>;
+
+                hsotg: hsotg@12480000 {
+                        compatible = "samsung,s3c6400-hsotg";
+                        reg = <0x12480000 0x20000>;
+                        interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_USB_DEVICE>;
+                        clock-names = "otg";
+                        phys = <&exynos_usbphy 0>;
+                        phy-names = "usb2-phy";
                         status = "disabled";
                 };
-        };
 
-        ohci: ohci@12590000 {
-                compatible = "samsung,exynos4210-ohci";
-                reg = <0x12590000 0x100>;
-                interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_USB_HOST>;
-                clock-names = "usbhost";
-                status = "disabled";
-                #address-cells = <1>;
-                #size-cells = <0>;
-                port@0 {
-                        reg = <0>;
-                        phys = <&exynos_usbphy 1>;
+                ehci: ehci@12580000 {
+                        compatible = "samsung,exynos4210-ehci";
+                        reg = <0x12580000 0x100>;
+                        interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_USB_HOST>;
+                        clock-names = "usbhost";
                         status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        port@0 {
+                                reg = <0>;
+                                phys = <&exynos_usbphy 1>;
+                                status = "disabled";
+                        };
+                        port@1 {
+                                reg = <1>;
+                                phys = <&exynos_usbphy 2>;
+                                status = "disabled";
+                        };
+                        port@2 {
+                                reg = <2>;
+                                phys = <&exynos_usbphy 3>;
+                                status = "disabled";
+                        };
                 };
-        };
 
-        i2s1: i2s@13960000 {
-                compatible = "samsung,s3c6410-i2s";
-                reg = <0x13960000 0x100>;
-                clocks = <&clock CLK_I2S1>;
-                clock-names = "iis";
-                #clock-cells = <1>;
-                clock-output-names = "i2s_cdclk1";
-                dmas = <&pdma1 12>, <&pdma1 11>;
-                dma-names = "tx", "rx";
-                #sound-dai-cells = <1>;
-                status = "disabled";
-        };
+                ohci: ohci@12590000 {
+                        compatible = "samsung,exynos4210-ohci";
+                        reg = <0x12590000 0x100>;
+                        interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_USB_HOST>;
+                        clock-names = "usbhost";
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        port@0 {
+                                reg = <0>;
+                                phys = <&exynos_usbphy 1>;
+                                status = "disabled";
+                        };
+                };
 
-        i2s2: i2s@13970000 {
-                compatible = "samsung,s3c6410-i2s";
-                reg = <0x13970000 0x100>;
-                clocks = <&clock CLK_I2S2>;
-                clock-names = "iis";
-                #clock-cells = <1>;
-                clock-output-names = "i2s_cdclk2";
-                dmas = <&pdma0 14>, <&pdma0 13>;
-                dma-names = "tx", "rx";
-                #sound-dai-cells = <1>;
-                status = "disabled";
-        };
+                i2s1: i2s@13960000 {
+                        compatible = "samsung,s3c6410-i2s";
+                        reg = <0x13960000 0x100>;
+                        clocks = <&clock CLK_I2S1>;
+                        clock-names = "iis";
+                        #clock-cells = <1>;
+                        clock-output-names = "i2s_cdclk1";
+                        dmas = <&pdma1 12>, <&pdma1 11>;
+                        dma-names = "tx", "rx";
+                        #sound-dai-cells = <1>;
+                        status = "disabled";
+                };
 
-        mfc: codec@13400000 {
-                compatible = "samsung,mfc-v5";
-                reg = <0x13400000 0x10000>;
-                interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
-                power-domains = <&pd_mfc>;
-                clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
-                clock-names = "mfc", "sclk_mfc";
-                iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
-                iommu-names = "left", "right";
-        };
+                i2s2: i2s@13970000 {
+                        compatible = "samsung,s3c6410-i2s";
+                        reg = <0x13970000 0x100>;
+                        clocks = <&clock CLK_I2S2>;
+                        clock-names = "iis";
+                        #clock-cells = <1>;
+                        clock-output-names = "i2s_cdclk2";
+                        dmas = <&pdma0 14>, <&pdma0 13>;
+                        dma-names = "tx", "rx";
+                        #sound-dai-cells = <1>;
+                        status = "disabled";
+                };
 
-        serial_0: serial@13800000 {
-                compatible = "samsung,exynos4210-uart";
-                reg = <0x13800000 0x100>;
-                interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
-                clock-names = "uart", "clk_uart_baud0";
-                dmas = <&pdma0 15>, <&pdma0 16>;
-                dma-names = "rx", "tx";
-                status = "disabled";
-        };
+                mfc: codec@13400000 {
+                        compatible = "samsung,mfc-v5";
+                        reg = <0x13400000 0x10000>;
+                        interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+                        power-domains = <&pd_mfc>;
+                        clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
+                        clock-names = "mfc", "sclk_mfc";
+                        iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
+                        iommu-names = "left", "right";
+                };
 
-        serial_1: serial@13810000 {
-                compatible = "samsung,exynos4210-uart";
-                reg = <0x13810000 0x100>;
-                interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
-                clock-names = "uart", "clk_uart_baud0";
-                dmas = <&pdma1 15>, <&pdma1 16>;
-                dma-names = "rx", "tx";
-                status = "disabled";
-        };
+                serial_0: serial@13800000 {
+                        compatible = "samsung,exynos4210-uart";
+                        reg = <0x13800000 0x100>;
+                        interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
+                        clock-names = "uart", "clk_uart_baud0";
+                        dmas = <&pdma0 15>, <&pdma0 16>;
+                        dma-names = "rx", "tx";
+                        status = "disabled";
+                };
 
-        serial_2: serial@13820000 {
-                compatible = "samsung,exynos4210-uart";
-                reg = <0x13820000 0x100>;
-                interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
-                clock-names = "uart", "clk_uart_baud0";
-                dmas = <&pdma0 17>, <&pdma0 18>;
-                dma-names = "rx", "tx";
-                status = "disabled";
-        };
+                serial_1: serial@13810000 {
+                        compatible = "samsung,exynos4210-uart";
+                        reg = <0x13810000 0x100>;
+                        interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
+                        clock-names = "uart", "clk_uart_baud0";
+                        dmas = <&pdma1 15>, <&pdma1 16>;
+                        dma-names = "rx", "tx";
+                        status = "disabled";
+                };
 
-        serial_3: serial@13830000 {
-                compatible = "samsung,exynos4210-uart";
-                reg = <0x13830000 0x100>;
-                interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
-                clock-names = "uart", "clk_uart_baud0";
-                dmas = <&pdma1 17>, <&pdma1 18>;
-                dma-names = "rx", "tx";
-                status = "disabled";
-        };
+                serial_2: serial@13820000 {
+                        compatible = "samsung,exynos4210-uart";
+                        reg = <0x13820000 0x100>;
+                        interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
+                        clock-names = "uart", "clk_uart_baud0";
+                        dmas = <&pdma0 17>, <&pdma0 18>;
+                        dma-names = "rx", "tx";
+                        status = "disabled";
+                };
 
-        i2c_0: i2c@13860000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "samsung,s3c2440-i2c";
-                reg = <0x13860000 0x100>;
-                interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_I2C0>;
-                clock-names = "i2c";
-                pinctrl-names = "default";
-                pinctrl-0 = <&i2c0_bus>;
-                status = "disabled";
-        };
+                serial_3: serial@13830000 {
+                        compatible = "samsung,exynos4210-uart";
+                        reg = <0x13830000 0x100>;
+                        interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
+                        clock-names = "uart", "clk_uart_baud0";
+                        dmas = <&pdma1 17>, <&pdma1 18>;
+                        dma-names = "rx", "tx";
+                        status = "disabled";
+                };
 
-        i2c_1: i2c@13870000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "samsung,s3c2440-i2c";
-                reg = <0x13870000 0x100>;
-                interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_I2C1>;
-                clock-names = "i2c";
-                pinctrl-names = "default";
-                pinctrl-0 = <&i2c1_bus>;
-                status = "disabled";
-        };
+                i2c_0: i2c@13860000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0x13860000 0x100>;
+                        interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_I2C0>;
+                        clock-names = "i2c";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_bus>;
+                        status = "disabled";
+                };
 
-        i2c_2: i2c@13880000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "samsung,s3c2440-i2c";
-                reg = <0x13880000 0x100>;
-                interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_I2C2>;
-                clock-names = "i2c";
-                pinctrl-names = "default";
-                pinctrl-0 = <&i2c2_bus>;
-                status = "disabled";
-        };
+                i2c_1: i2c@13870000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0x13870000 0x100>;
+                        interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_I2C1>;
+                        clock-names = "i2c";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c1_bus>;
+                        status = "disabled";
+                };
 
-        i2c_3: i2c@13890000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "samsung,s3c2440-i2c";
-                reg = <0x13890000 0x100>;
-                interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_I2C3>;
-                clock-names = "i2c";
-                pinctrl-names = "default";
-                pinctrl-0 = <&i2c3_bus>;
-                status = "disabled";
-        };
+                i2c_2: i2c@13880000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0x13880000 0x100>;
+                        interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_I2C2>;
+                        clock-names = "i2c";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c2_bus>;
+                        status = "disabled";
+                };
 
-        i2c_4: i2c@138a0000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "samsung,s3c2440-i2c";
-                reg = <0x138A0000 0x100>;
-                interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_I2C4>;
-                clock-names = "i2c";
-                pinctrl-names = "default";
-                pinctrl-0 = <&i2c4_bus>;
-                status = "disabled";
-        };
+                i2c_3: i2c@13890000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0x13890000 0x100>;
+                        interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_I2C3>;
+                        clock-names = "i2c";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c3_bus>;
+                        status = "disabled";
+                };
 
-        i2c_5: i2c@138b0000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "samsung,s3c2440-i2c";
-                reg = <0x138B0000 0x100>;
-                interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_I2C5>;
-                clock-names = "i2c";
-                pinctrl-names = "default";
-                pinctrl-0 = <&i2c5_bus>;
-                status = "disabled";
-        };
+                i2c_4: i2c@138a0000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0x138A0000 0x100>;
+                        interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_I2C4>;
+                        clock-names = "i2c";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c4_bus>;
+                        status = "disabled";
+                };
 
-        i2c_6: i2c@138c0000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "samsung,s3c2440-i2c";
-                reg = <0x138C0000 0x100>;
-                interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_I2C6>;
-                clock-names = "i2c";
-                pinctrl-names = "default";
-                pinctrl-0 = <&i2c6_bus>;
-                status = "disabled";
-        };
+                i2c_5: i2c@138b0000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0x138B0000 0x100>;
+                        interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_I2C5>;
+                        clock-names = "i2c";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c5_bus>;
+                        status = "disabled";
+                };
 
-        i2c_7: i2c@138d0000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "samsung,s3c2440-i2c";
-                reg = <0x138D0000 0x100>;
-                interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_I2C7>;
-                clock-names = "i2c";
-                pinctrl-names = "default";
-                pinctrl-0 = <&i2c7_bus>;
-                status = "disabled";
-        };
+                i2c_6: i2c@138c0000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0x138C0000 0x100>;
+                        interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_I2C6>;
+                        clock-names = "i2c";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c6_bus>;
+                        status = "disabled";
+                };
 
-        i2c_8: i2c@138e0000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "samsung,s3c2440-hdmiphy-i2c";
-                reg = <0x138E0000 0x100>;
-                interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_I2C_HDMI>;
-                clock-names = "i2c";
-                status = "disabled";
-
-                hdmi_i2c_phy: hdmiphy@38 {
-                        compatible = "exynos4210-hdmiphy";
-                        reg = <0x38>;
+                i2c_7: i2c@138d0000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0x138D0000 0x100>;
+                        interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_I2C7>;
+                        clock-names = "i2c";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c7_bus>;
+                        status = "disabled";
                 };
-        };
 
-        spi_0: spi@13920000 {
-                compatible = "samsung,exynos4210-spi";
-                reg = <0x13920000 0x100>;
-                interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
-                dmas = <&pdma0 7>, <&pdma0 6>;
-                dma-names = "tx", "rx";
-                #address-cells = <1>;
-                #size-cells = <0>;
-                clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
-                clock-names = "spi", "spi_busclk0";
-                pinctrl-names = "default";
-                pinctrl-0 = <&spi0_bus>;
-                status = "disabled";
-        };
+                i2c_8: i2c@138e0000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "samsung,s3c2440-hdmiphy-i2c";
+                        reg = <0x138E0000 0x100>;
+                        interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_I2C_HDMI>;
+                        clock-names = "i2c";
+                        status = "disabled";
 
-        spi_1: spi@13930000 {
-                compatible = "samsung,exynos4210-spi";
-                reg = <0x13930000 0x100>;
-                interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
-                dmas = <&pdma1 7>, <&pdma1 6>;
-                dma-names = "tx", "rx";
-                #address-cells = <1>;
-                #size-cells = <0>;
-                clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
-                clock-names = "spi", "spi_busclk0";
-                pinctrl-names = "default";
-                pinctrl-0 = <&spi1_bus>;
-                status = "disabled";
-        };
+                        hdmi_i2c_phy: hdmiphy@38 {
+                                compatible = "exynos4210-hdmiphy";
+                                reg = <0x38>;
+                        };
+                };
 
-        spi_2: spi@13940000 {
-                compatible = "samsung,exynos4210-spi";
-                reg = <0x13940000 0x100>;
-                interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
-                dmas = <&pdma0 9>, <&pdma0 8>;
-                dma-names = "tx", "rx";
-                #address-cells = <1>;
-                #size-cells = <0>;
-                clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
-                clock-names = "spi", "spi_busclk0";
-                pinctrl-names = "default";
-                pinctrl-0 = <&spi2_bus>;
-                status = "disabled";
-        };
+                spi_0: spi@13920000 {
+                        compatible = "samsung,exynos4210-spi";
+                        reg = <0x13920000 0x100>;
+                        interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+                        dmas = <&pdma0 7>, <&pdma0 6>;
+                        dma-names = "tx", "rx";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
+                        clock-names = "spi", "spi_busclk0";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&spi0_bus>;
+                        status = "disabled";
+                };
 
-        pwm: pwm@139d0000 {
-                compatible = "samsung,exynos4210-pwm";
-                reg = <0x139D0000 0x1000>;
-                interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_PWM>;
-                clock-names = "timers";
-                #pwm-cells = <3>;
-                status = "disabled";
-        };
+                spi_1: spi@13930000 {
+                        compatible = "samsung,exynos4210-spi";
+                        reg = <0x13930000 0x100>;
+                        interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+                        dmas = <&pdma1 7>, <&pdma1 6>;
+                        dma-names = "tx", "rx";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
+                        clock-names = "spi", "spi_busclk0";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&spi1_bus>;
+                        status = "disabled";
+                };
 
-        amba {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                compatible = "simple-bus";
-                interrupt-parent = <&gic>;
-                ranges;
+                spi_2: spi@13940000 {
+                        compatible = "samsung,exynos4210-spi";
+                        reg = <0x13940000 0x100>;
+                        interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+                        dmas = <&pdma0 9>, <&pdma0 8>;
+                        dma-names = "tx", "rx";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
+                        clock-names = "spi", "spi_busclk0";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&spi2_bus>;
+                        status = "disabled";
+                };
 
-                pdma0: pdma@12680000 {
-                        compatible = "arm,pl330", "arm,primecell";
-                        reg = <0x12680000 0x1000>;
-                        interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&clock CLK_PDMA0>;
-                        clock-names = "apb_pclk";
-                        #dma-cells = <1>;
-                        #dma-channels = <8>;
-                        #dma-requests = <32>;
-                };
-
-                pdma1: pdma@12690000 {
-                        compatible = "arm,pl330", "arm,primecell";
-                        reg = <0x12690000 0x1000>;
-                        interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&clock CLK_PDMA1>;
-                        clock-names = "apb_pclk";
-                        #dma-cells = <1>;
-                        #dma-channels = <8>;
-                        #dma-requests = <32>;
-                };
-
-                mdma1: mdma@12850000 {
-                        compatible = "arm,pl330", "arm,primecell";
-                        reg = <0x12850000 0x1000>;
-                        interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&clock CLK_MDMA>;
-                        clock-names = "apb_pclk";
-                        #dma-cells = <1>;
-                        #dma-channels = <8>;
-                        #dma-requests = <1>;
+                pwm: pwm@139d0000 {
+                        compatible = "samsung,exynos4210-pwm";
+                        reg = <0x139D0000 0x1000>;
+                        interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_PWM>;
+                        clock-names = "timers";
+                        #pwm-cells = <3>;
+                        status = "disabled";
                 };
-        };
 
-        fimd: fimd@11c00000 {
-                compatible = "samsung,exynos4210-fimd";
-                interrupt-parent = <&combiner>;
-                reg = <0x11c00000 0x20000>;
-                interrupt-names = "fifo", "vsync", "lcd_sys";
-                interrupts = <11 0>, <11 1>, <11 2>;
-                clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
-                clock-names = "sclk_fimd", "fimd";
-                power-domains = <&pd_lcd0>;
-                iommus = <&sysmmu_fimd0>;
-                samsung,sysreg = <&sys_reg>;
-                status = "disabled";
-        };
+                amba {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "simple-bus";
+                        interrupt-parent = <&gic>;
+                        ranges;
+
+                        pdma0: pdma@12680000 {
+                                compatible = "arm,pl330", "arm,primecell";
+                                reg = <0x12680000 0x1000>;
+                                interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clock CLK_PDMA0>;
+                                clock-names = "apb_pclk";
+                                #dma-cells = <1>;
+                                #dma-channels = <8>;
+                                #dma-requests = <32>;
+                        };
+
+                        pdma1: pdma@12690000 {
+                                compatible = "arm,pl330", "arm,primecell";
+                                reg = <0x12690000 0x1000>;
+                                interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clock CLK_PDMA1>;
+                                clock-names = "apb_pclk";
+                                #dma-cells = <1>;
+                                #dma-channels = <8>;
+                                #dma-requests = <32>;
+                        };
+
+                        mdma1: mdma@12850000 {
+                                compatible = "arm,pl330", "arm,primecell";
+                                reg = <0x12850000 0x1000>;
+                                interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clock CLK_MDMA>;
+                                clock-names = "apb_pclk";
+                                #dma-cells = <1>;
+                                #dma-channels = <8>;
+                                #dma-requests = <1>;
+                        };
+                };
 
-        tmu: tmu@100c0000 {
-                #include "exynos4412-tmu-sensor-conf.dtsi"
-        };
+                fimd: fimd@11c00000 {
+                        compatible = "samsung,exynos4210-fimd";
+                        interrupt-parent = <&combiner>;
+                        reg = <0x11c00000 0x20000>;
+                        interrupt-names = "fifo", "vsync", "lcd_sys";
+                        interrupts = <11 0>, <11 1>, <11 2>;
+                        clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
+                        clock-names = "sclk_fimd", "fimd";
+                        power-domains = <&pd_lcd0>;
+                        iommus = <&sysmmu_fimd0>;
+                        samsung,sysreg = <&sys_reg>;
+                        status = "disabled";
+                };
 
-        jpeg_codec: jpeg-codec@11840000 {
-                compatible = "samsung,exynos4210-jpeg";
-                reg = <0x11840000 0x1000>;
-                interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_JPEG>;
-                clock-names = "jpeg";
-                power-domains = <&pd_cam>;
-                iommus = <&sysmmu_jpeg>;
-        };
+                tmu: tmu@100c0000 {
+                        interrupt-parent = <&combiner>;
+                        reg = <0x100C0000 0x100>;
+                        interrupts = <2 4>;
+                        status = "disabled";
+                        #include "exynos4412-tmu-sensor-conf.dtsi"
+                };
 
-        rotator: rotator@12810000 {
-                compatible = "samsung,exynos4210-rotator";
-                reg = <0x12810000 0x64>;
-                interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_ROTATOR>;
-                clock-names = "rotator";
-                iommus = <&sysmmu_rotator>;
-        };
+                jpeg_codec: jpeg-codec@11840000 {
+                        compatible = "samsung,exynos4210-jpeg";
+                        reg = <0x11840000 0x1000>;
+                        interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_JPEG>;
+                        clock-names = "jpeg";
+                        power-domains = <&pd_cam>;
+                        iommus = <&sysmmu_jpeg>;
+                };
 
-        hdmi: hdmi@12d00000 {
-                compatible = "samsung,exynos4210-hdmi";
-                reg = <0x12D00000 0x70000>;
-                interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
-                clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy",
-                        "mout_hdmi";
-                clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
-                        <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
-                        <&clock CLK_MOUT_HDMI>;
-                phy = <&hdmi_i2c_phy>;
-                power-domains = <&pd_tv>;
-                samsung,syscon-phandle = <&pmu_system_controller>;
-                #sound-dai-cells = <0>;
-                status = "disabled";
-        };
+                rotator: rotator@12810000 {
+                        compatible = "samsung,exynos4210-rotator";
+                        reg = <0x12810000 0x64>;
+                        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_ROTATOR>;
+                        clock-names = "rotator";
+                        iommus = <&sysmmu_rotator>;
+                };
 
-        hdmicec: cec@100b0000 {
-                compatible = "samsung,s5p-cec";
-                reg = <0x100B0000 0x200>;
-                interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_HDMI_CEC>;
-                clock-names = "hdmicec";
-                samsung,syscon-phandle = <&pmu_system_controller>;
-                hdmi-phandle = <&hdmi>;
-                pinctrl-names = "default";
-                pinctrl-0 = <&hdmi_cec>;
-                status = "disabled";
-        };
+                hdmi: hdmi@12d00000 {
+                        compatible = "samsung,exynos4210-hdmi";
+                        reg = <0x12D00000 0x70000>;
+                        interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+                        clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
+                                      "sclk_hdmiphy", "mout_hdmi";
+                        clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
+                                 <&clock CLK_SCLK_PIXEL>,
+                                 <&clock CLK_SCLK_HDMIPHY>,
+                                 <&clock CLK_MOUT_HDMI>;
+                        phy = <&hdmi_i2c_phy>;
+                        power-domains = <&pd_tv>;
+                        samsung,syscon-phandle = <&pmu_system_controller>;
+                        #sound-dai-cells = <0>;
+                        status = "disabled";
+                };
 
-        mixer: mixer@12c10000 {
-                compatible = "samsung,exynos4210-mixer";
-                interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
-                reg = <0x12C10000 0x2100>, <0x12c00000 0x300>;
-                power-domains = <&pd_tv>;
-                iommus = <&sysmmu_tv>;
-                status = "disabled";
-        };
+                hdmicec: cec@100b0000 {
+                        compatible = "samsung,s5p-cec";
+                        reg = <0x100B0000 0x200>;
+                        interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_HDMI_CEC>;
+                        clock-names = "hdmicec";
+                        samsung,syscon-phandle = <&pmu_system_controller>;
+                        hdmi-phandle = <&hdmi>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&hdmi_cec>;
+                        status = "disabled";
+                };
 
-        ppmu_dmc0: ppmu_dmc0@106a0000 {
-                compatible = "samsung,exynos-ppmu";
-                reg = <0x106a0000 0x2000>;
-                clocks = <&clock CLK_PPMUDMC0>;
-                clock-names = "ppmu";
-                status = "disabled";
-        };
+                mixer: mixer@12c10000 {
+                        compatible = "samsung,exynos4210-mixer";
+                        interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+                        reg = <0x12C10000 0x2100>, <0x12c00000 0x300>;
+                        power-domains = <&pd_tv>;
+                        iommus = <&sysmmu_tv>;
+                        status = "disabled";
+                };
 
-        ppmu_dmc1: ppmu_dmc1@106b0000 {
-                compatible = "samsung,exynos-ppmu";
-                reg = <0x106b0000 0x2000>;
-                clocks = <&clock CLK_PPMUDMC1>;
-                clock-names = "ppmu";
-                status = "disabled";
-        };
+                ppmu_dmc0: ppmu_dmc0@106a0000 {
+                        compatible = "samsung,exynos-ppmu";
+                        reg = <0x106a0000 0x2000>;
+                        clocks = <&clock CLK_PPMUDMC0>;
+                        clock-names = "ppmu";
+                        status = "disabled";
+                };
 
-        ppmu_cpu: ppmu_cpu@106c0000 {
-                compatible = "samsung,exynos-ppmu";
-                reg = <0x106c0000 0x2000>;
-                clocks = <&clock CLK_PPMUCPU>;
-                clock-names = "ppmu";
-                status = "disabled";
-        };
+                ppmu_dmc1: ppmu_dmc1@106b0000 {
+                        compatible = "samsung,exynos-ppmu";
+                        reg = <0x106b0000 0x2000>;
+                        clocks = <&clock CLK_PPMUDMC1>;
+                        clock-names = "ppmu";
+                        status = "disabled";
+                };
 
-        ppmu_acp: ppmu_acp@10ae0000 {
-                compatible = "samsung,exynos-ppmu";
-                reg = <0x106e0000 0x2000>;
-                status = "disabled";
-        };
+                ppmu_cpu: ppmu_cpu@106c0000 {
+                        compatible = "samsung,exynos-ppmu";
+                        reg = <0x106c0000 0x2000>;
+                        clocks = <&clock CLK_PPMUCPU>;
+                        clock-names = "ppmu";
+                        status = "disabled";
+                };
 
-        ppmu_rightbus: ppmu_rightbus@112a0000 {
-                compatible = "samsung,exynos-ppmu";
-                reg = <0x112a0000 0x2000>;
-                clocks = <&clock CLK_PPMURIGHT>;
-                clock-names = "ppmu";
-                status = "disabled";
-        };
+                ppmu_rightbus: ppmu_rightbus@112a0000 {
+                        compatible = "samsung,exynos-ppmu";
+                        reg = <0x112a0000 0x2000>;
+                        clocks = <&clock CLK_PPMURIGHT>;
+                        clock-names = "ppmu";
+                        status = "disabled";
+                };
 
-        ppmu_leftbus: ppmu_leftbus0@116a0000 {
-                compatible = "samsung,exynos-ppmu";
-                reg = <0x116a0000 0x2000>;
-                clocks = <&clock CLK_PPMULEFT>;
-                clock-names = "ppmu";
-                status = "disabled";
-        };
+                ppmu_leftbus: ppmu_leftbus0@116a0000 {
+                        compatible = "samsung,exynos-ppmu";
+                        reg = <0x116a0000 0x2000>;
+                        clocks = <&clock CLK_PPMULEFT>;
+                        clock-names = "ppmu";
+                        status = "disabled";
+                };
 
-        ppmu_camif: ppmu_camif@11ac0000 {
-                compatible = "samsung,exynos-ppmu";
-                reg = <0x11ac0000 0x2000>;
-                clocks = <&clock CLK_PPMUCAMIF>;
-                clock-names = "ppmu";
-                status = "disabled";
-        };
+                ppmu_camif: ppmu_camif@11ac0000 {
+                        compatible = "samsung,exynos-ppmu";
+                        reg = <0x11ac0000 0x2000>;
+                        clocks = <&clock CLK_PPMUCAMIF>;
+                        clock-names = "ppmu";
+                        status = "disabled";
+                };
 
-        ppmu_lcd0: ppmu_lcd0@11e40000 {
-                compatible = "samsung,exynos-ppmu";
-                reg = <0x11e40000 0x2000>;
-                clocks = <&clock CLK_PPMULCD0>;
-                clock-names = "ppmu";
-                status = "disabled";
-        };
+                ppmu_lcd0: ppmu_lcd0@11e40000 {
+                        compatible = "samsung,exynos-ppmu";
+                        reg = <0x11e40000 0x2000>;
+                        clocks = <&clock CLK_PPMULCD0>;
+                        clock-names = "ppmu";
+                        status = "disabled";
+                };
 
-        ppmu_fsys: ppmu_g3d@12630000 {
-                compatible = "samsung,exynos-ppmu";
-                reg = <0x12630000 0x2000>;
-                status = "disabled";
-        };
+                ppmu_fsys: ppmu_g3d@12630000 {
+                        compatible = "samsung,exynos-ppmu";
+                        reg = <0x12630000 0x2000>;
+                        status = "disabled";
+                };
 
-        ppmu_image: ppmu_image@12aa0000 {
-                compatible = "samsung,exynos-ppmu";
-                reg = <0x12aa0000 0x2000>;
-                clocks = <&clock CLK_PPMUIMAGE>;
-                clock-names = "ppmu";
-                status = "disabled";
-        };
+                ppmu_image: ppmu_image@12aa0000 {
+                        compatible = "samsung,exynos-ppmu";
+                        reg = <0x12aa0000 0x2000>;
+                        clocks = <&clock CLK_PPMUIMAGE>;
+                        clock-names = "ppmu";
+                        status = "disabled";
+                };
 
-        ppmu_tv: ppmu_tv@12e40000 {
-                compatible = "samsung,exynos-ppmu";
-                reg = <0x12e40000 0x2000>;
-                clocks = <&clock CLK_PPMUTV>;
-                clock-names = "ppmu";
-                status = "disabled";
-        };
+                ppmu_tv: ppmu_tv@12e40000 {
+                        compatible = "samsung,exynos-ppmu";
+                        reg = <0x12e40000 0x2000>;
+                        clocks = <&clock CLK_PPMUTV>;
+                        clock-names = "ppmu";
+                        status = "disabled";
+                };
 
-        ppmu_g3d: ppmu_g3d@13220000 {
-                compatible = "samsung,exynos-ppmu";
-                reg = <0x13220000 0x2000>;
-                clocks = <&clock CLK_PPMUG3D>;
-                clock-names = "ppmu";
-                status = "disabled";
-        };
+                ppmu_g3d: ppmu_g3d@13220000 {
+                        compatible = "samsung,exynos-ppmu";
+                        reg = <0x13220000 0x2000>;
+                        clocks = <&clock CLK_PPMUG3D>;
+                        clock-names = "ppmu";
+                        status = "disabled";
+                };
 
-        ppmu_mfc_left: ppmu_mfc_left@13660000 {
-                compatible = "samsung,exynos-ppmu";
-                reg = <0x13660000 0x2000>;
-                clocks = <&clock CLK_PPMUMFC_L>;
-                clock-names = "ppmu";
-                status = "disabled";
-        };
+                ppmu_mfc_left: ppmu_mfc_left@13660000 {
+                        compatible = "samsung,exynos-ppmu";
+                        reg = <0x13660000 0x2000>;
+                        clocks = <&clock CLK_PPMUMFC_L>;
+                        clock-names = "ppmu";
+                        status = "disabled";
+                };
 
-        ppmu_mfc_right: ppmu_mfc_right@13670000 {
-                compatible = "samsung,exynos-ppmu";
-                reg = <0x13670000 0x2000>;
-                clocks = <&clock CLK_PPMUMFC_R>;
-                clock-names = "ppmu";
-                status = "disabled";
-        };
+                ppmu_mfc_right: ppmu_mfc_right@13670000 {
+                        compatible = "samsung,exynos-ppmu";
+                        reg = <0x13670000 0x2000>;
+                        clocks = <&clock CLK_PPMUMFC_R>;
+                        clock-names = "ppmu";
+                        status = "disabled";
+                };
 
-        sysmmu_mfc_l: sysmmu@13620000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x13620000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <5 5>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
-                power-domains = <&pd_mfc>;
-                #iommu-cells = <0>;
-        };
+                sysmmu_mfc_l: sysmmu@13620000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x13620000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <5 5>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
+                        power-domains = <&pd_mfc>;
+                        #iommu-cells = <0>;
+                };
 
-        sysmmu_mfc_r: sysmmu@13630000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x13630000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <5 6>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
-                power-domains = <&pd_mfc>;
-                #iommu-cells = <0>;
-        };
+                sysmmu_mfc_r: sysmmu@13630000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x13630000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <5 6>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
+                        power-domains = <&pd_mfc>;
+                        #iommu-cells = <0>;
+                };
 
-        sysmmu_tv: sysmmu@12e20000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x12E20000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <5 4>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
-                power-domains = <&pd_tv>;
-                #iommu-cells = <0>;
-        };
+                sysmmu_tv: sysmmu@12e20000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x12E20000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <5 4>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
+                        power-domains = <&pd_tv>;
+                        #iommu-cells = <0>;
+                };
 
-        sysmmu_fimc0: sysmmu@11a20000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x11A20000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <4 2>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_FIMC0>, <&clock CLK_FIMC0>;
-                power-domains = <&pd_cam>;
-                #iommu-cells = <0>;
-        };
+                sysmmu_fimc0: sysmmu@11a20000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x11A20000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <4 2>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_FIMC0>, <&clock CLK_FIMC0>;
+                        power-domains = <&pd_cam>;
+                        #iommu-cells = <0>;
+                };
 
-        sysmmu_fimc1: sysmmu@11a30000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x11A30000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <4 3>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_FIMC1>, <&clock CLK_FIMC1>;
-                power-domains = <&pd_cam>;
-                #iommu-cells = <0>;
-        };
+                sysmmu_fimc1: sysmmu@11a30000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x11A30000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <4 3>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_FIMC1>, <&clock CLK_FIMC1>;
+                        power-domains = <&pd_cam>;
+                        #iommu-cells = <0>;
+                };
 
-        sysmmu_fimc2: sysmmu@11a40000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x11A40000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <4 4>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_FIMC2>, <&clock CLK_FIMC2>;
-                power-domains = <&pd_cam>;
-                #iommu-cells = <0>;
-        };
+                sysmmu_fimc2: sysmmu@11a40000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x11A40000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <4 4>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_FIMC2>, <&clock CLK_FIMC2>;
+                        power-domains = <&pd_cam>;
+                        #iommu-cells = <0>;
+                };
 
-        sysmmu_fimc3: sysmmu@11a50000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x11A50000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <4 5>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_FIMC3>, <&clock CLK_FIMC3>;
-                power-domains = <&pd_cam>;
-                #iommu-cells = <0>;
-        };
+                sysmmu_fimc3: sysmmu@11a50000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x11A50000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <4 5>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_FIMC3>, <&clock CLK_FIMC3>;
+                        power-domains = <&pd_cam>;
+                        #iommu-cells = <0>;
+                };
 
-        sysmmu_jpeg: sysmmu@11a60000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x11A60000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <4 6>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
-                power-domains = <&pd_cam>;
-                #iommu-cells = <0>;
-        };
+                sysmmu_jpeg: sysmmu@11a60000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x11A60000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <4 6>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
+                        power-domains = <&pd_cam>;
+                        #iommu-cells = <0>;
+                };
 
-        sysmmu_rotator: sysmmu@12a30000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x12A30000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <5 0>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
-                #iommu-cells = <0>;
-        };
+                sysmmu_rotator: sysmmu@12a30000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x12A30000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <5 0>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_ROTATOR>,
+                                 <&clock CLK_ROTATOR>;
+                        #iommu-cells = <0>;
+                };
 
-        sysmmu_fimd0: sysmmu@11e20000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x11E20000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <5 2>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_FIMD0>, <&clock CLK_FIMD0>;
-                power-domains = <&pd_lcd0>;
-                #iommu-cells = <0>;
-        };
+                sysmmu_fimd0: sysmmu@11e20000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x11E20000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <5 2>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_FIMD0>, <&clock CLK_FIMD0>;
+                        power-domains = <&pd_lcd0>;
+                        #iommu-cells = <0>;
+                };
 
-        sss: sss@10830000 {
-                compatible = "samsung,exynos4210-secss";
-                reg = <0x10830000 0x300>;
-                interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_SSS>;
-                clock-names = "secss";
-        };
+                sss: sss@10830000 {
+                        compatible = "samsung,exynos4210-secss";
+                        reg = <0x10830000 0x300>;
+                        interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_SSS>;
+                        clock-names = "secss";
+                };
 
-        prng: rng@10830400 {
-                compatible = "samsung,exynos4-rng";
-                reg = <0x10830400 0x200>;
-                clocks = <&clock CLK_SSS>;
-                clock-names = "secss";
+                prng: rng@10830400 {
+                        compatible = "samsung,exynos4-rng";
+                        reg = <0x10830400 0x200>;
+                        clocks = <&clock CLK_SSS>;
+                        clock-names = "secss";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
index dbe6c052d8c1..520c5934a8d4 100644
--- a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
@@ -13,853 +13,851 @@
 
 #include <dt-bindings/pinctrl/samsung.h>
 
-/ {
-        pinctrl@11400000 {
-                gpa0: gpa0 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
+&pinctrl_0 {
+        gpa0: gpa0 {
+                gpio-controller;
+                #gpio-cells = <2>;
 
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpa1: gpa1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpb: gpb {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpc0: gpc0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpc1: gpc1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpd0: gpd0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpd1: gpd1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpe0: gpe0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpe1: gpe1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpe2: gpe2 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpe3: gpe3 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpe4: gpe4 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpf0: gpf0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpf1: gpf1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpf2: gpf2 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpf3: gpf3 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        uart0_data: uart0-data {
+                samsung,pins = "gpa0-0", "gpa0-1";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        uart0_fctl: uart0-fctl {
+                samsung,pins = "gpa0-2", "gpa0-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        uart1_data: uart1-data {
+                samsung,pins = "gpa0-4", "gpa0-5";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        uart1_fctl: uart1-fctl {
+                samsung,pins = "gpa0-6", "gpa0-7";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        i2c2_bus: i2c2-bus {
+                samsung,pins = "gpa0-6", "gpa0-7";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        uart2_data: uart2-data {
+                samsung,pins = "gpa1-0", "gpa1-1";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        uart2_fctl: uart2-fctl {
+                samsung,pins = "gpa1-2", "gpa1-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        uart_audio_a: uart-audio-a {
+                samsung,pins = "gpa1-0", "gpa1-1";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        i2c3_bus: i2c3-bus {
+                samsung,pins = "gpa1-2", "gpa1-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        uart3_data: uart3-data {
+                samsung,pins = "gpa1-4", "gpa1-5";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        uart_audio_b: uart-audio-b {
+                samsung,pins = "gpa1-4", "gpa1-5";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        spi0_bus: spi0-bus {
+                samsung,pins = "gpb-0", "gpb-2", "gpb-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        i2c4_bus: i2c4-bus {
+                samsung,pins = "gpb-2", "gpb-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        spi1_bus: spi1-bus {
+                samsung,pins = "gpb-4", "gpb-6", "gpb-7";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        i2c5_bus: i2c5-bus {
+                samsung,pins = "gpb-6", "gpb-7";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        i2s1_bus: i2s1-bus {
+                samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
+                                "gpc0-4";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        pcm1_bus: pcm1-bus {
+                samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
+                                "gpc0-4";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        ac97_bus: ac97-bus {
+                samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
+                                "gpc0-4";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        i2s2_bus: i2s2-bus {
+                samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
+                                "gpc1-4";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        pcm2_bus: pcm2-bus {
+                samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
+                                "gpc1-4";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        spdif_bus: spdif-bus {
+                samsung,pins = "gpc1-0", "gpc1-1";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        i2c6_bus: i2c6-bus {
+                samsung,pins = "gpc1-3", "gpc1-4";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        spi2_bus: spi2-bus {
+                samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_5>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        i2c7_bus: i2c7-bus {
+                samsung,pins = "gpd0-2", "gpd0-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        i2c0_bus: i2c0-bus {
+                samsung,pins = "gpd1-0", "gpd1-1";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        i2c1_bus: i2c1-bus {
+                samsung,pins = "gpd1-2", "gpd1-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        pwm0_out: pwm0-out {
+                samsung,pins = "gpd0-0";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        pwm1_out: pwm1-out {
+                samsung,pins = "gpd0-1";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        pwm2_out: pwm2-out {
+                samsung,pins = "gpd0-2";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        pwm3_out: pwm3-out {
+                samsung,pins = "gpd0-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        lcd_ctrl: lcd-ctrl {
+                samsung,pins = "gpd0-0", "gpd0-1";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        lcd_sync: lcd-sync {
+                samsung,pins = "gpf0-0", "gpf0-1";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        lcd_en: lcd-en {
+                samsung,pins = "gpe3-4";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        lcd_clk: lcd-clk {
+                samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        lcd_data16: lcd-data-width16 {
+                samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2",
+                                "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0",
+                                "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7",
+                                "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        lcd_data18: lcd-data-width18 {
+                samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1",
+                                "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7",
+                                "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
+                                "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1",
+                                "gpf3-2", "gpf3-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        lcd_data24: lcd-data-width24 {
+                samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7",
+                                "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3",
+                                "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7",
+                                "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
+                                "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7",
+                                "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+};
+
+&pinctrl_1 {
+        gpj0: gpj0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpj1: gpj1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpk0: gpk0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpk1: gpk1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpk2: gpk2 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpk3: gpk3 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpl0: gpl0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpl1: gpl1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpl2: gpl2 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpy0: gpy0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        gpy1: gpy1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        gpy2: gpy2 {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
 
-                gpa1: gpa1 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
+        gpy3: gpy3 {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        gpy4: gpy4 {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        gpy5: gpy5 {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        gpy6: gpy6 {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        gpx0: gpx0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                interrupt-parent = <&gic>;
+                interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+                #interrupt-cells = <2>;
+        };
+
+        gpx1: gpx1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                interrupt-parent = <&gic>;
+                interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+                #interrupt-cells = <2>;
+        };
+
+        gpx2: gpx2 {
+                gpio-controller;
+                #gpio-cells = <2>;
 
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpx3: gpx3 {
+                gpio-controller;
+                #gpio-cells = <2>;
 
-                gpb: gpb {
-                        gpio-controller;
-                        #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
 
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
+        sd0_clk: sd0-clk {
+                samsung,pins = "gpk0-0";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
 
-                gpc0: gpc0 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
+        sd0_cmd: sd0-cmd {
+                samsung,pins = "gpk0-1";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd0_cd: sd0-cd {
+                samsung,pins = "gpk0-2";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd0_bus1: sd0-bus-width1 {
+                samsung,pins = "gpk0-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd0_bus4: sd0-bus-width4 {
+                samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd0_bus8: sd0-bus-width8 {
+                samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd4_clk: sd4-clk {
+                samsung,pins = "gpk0-0";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd4_cmd: sd4-cmd {
+                samsung,pins = "gpk0-1";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd4_cd: sd4-cd {
+                samsung,pins = "gpk0-2";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd4_bus1: sd4-bus-width1 {
+                samsung,pins = "gpk0-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd4_bus4: sd4-bus-width4 {
+                samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd4_bus8: sd4-bus-width8 {
+                samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd1_clk: sd1-clk {
+                samsung,pins = "gpk1-0";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd1_cmd: sd1-cmd {
+                samsung,pins = "gpk1-1";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd1_cd: sd1-cd {
+                samsung,pins = "gpk1-2";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd1_bus1: sd1-bus-width1 {
+                samsung,pins = "gpk1-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd1_bus4: sd1-bus-width4 {
+                samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd2_clk: sd2-clk {
+                samsung,pins = "gpk2-0";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd2_cmd: sd2-cmd {
+                samsung,pins = "gpk2-1";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd2_cd: sd2-cd {
+                samsung,pins = "gpk2-2";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd2_bus1: sd2-bus-width1 {
+                samsung,pins = "gpk2-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd2_bus4: sd2-bus-width4 {
+                samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd2_bus8: sd2-bus-width8 {
+                samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd3_clk: sd3-clk {
+                samsung,pins = "gpk3-0";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd3_cmd: sd3-cmd {
+                samsung,pins = "gpk3-1";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd3_cd: sd3-cd {
+                samsung,pins = "gpk3-2";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd3_bus1: sd3-bus-width1 {
+                samsung,pins = "gpk3-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd3_bus4: sd3-bus-width4 {
+                samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        eint0: ext-int0 {
+                samsung,pins = "gpx0-0";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        eint8: ext-int8 {
+                samsung,pins = "gpx1-0";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        eint15: ext-int15 {
+                samsung,pins = "gpx1-7";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        eint16: ext-int16 {
+                samsung,pins = "gpx2-0";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        eint31: ext-int31 {
+                samsung,pins = "gpx3-7";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        cam_port_a_io: cam-port-a-io {
+                samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3",
+                                "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7",
+                                "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        cam_port_a_clk_active: cam-port-a-clk-active {
+                samsung,pins = "gpj1-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        cam_port_a_clk_idle: cam-port-a-clk-idle {
+                samsung,pins = "gpj1-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        hdmi_cec: hdmi-cec {
+                samsung,pins = "gpx3-6";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+};
+
+&pinctrl_2 {
+        gpz: gpz {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        i2s0_bus: i2s0-bus {
+                samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
+                                "gpz-4", "gpz-5", "gpz-6";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
 
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpc1: gpc1 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpd0: gpd0 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpd1: gpd1 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpe0: gpe0 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpe1: gpe1 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpe2: gpe2 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpe3: gpe3 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpe4: gpe4 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpf0: gpf0 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpf1: gpf1 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpf2: gpf2 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpf3: gpf3 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                uart0_data: uart0-data {
-                        samsung,pins = "gpa0-0", "gpa0-1";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                uart0_fctl: uart0-fctl {
-                        samsung,pins = "gpa0-2", "gpa0-3";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                uart1_data: uart1-data {
-                        samsung,pins = "gpa0-4", "gpa0-5";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                uart1_fctl: uart1-fctl {
-                        samsung,pins = "gpa0-6", "gpa0-7";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                i2c2_bus: i2c2-bus {
-                        samsung,pins = "gpa0-6", "gpa0-7";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                uart2_data: uart2-data {
-                        samsung,pins = "gpa1-0", "gpa1-1";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                uart2_fctl: uart2-fctl {
-                        samsung,pins = "gpa1-2", "gpa1-3";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                uart_audio_a: uart-audio-a {
-                        samsung,pins = "gpa1-0", "gpa1-1";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                i2c3_bus: i2c3-bus {
-                        samsung,pins = "gpa1-2", "gpa1-3";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                uart3_data: uart3-data {
-                        samsung,pins = "gpa1-4", "gpa1-5";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                uart_audio_b: uart-audio-b {
-                        samsung,pins = "gpa1-4", "gpa1-5";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                spi0_bus: spi0-bus {
-                        samsung,pins = "gpb-0", "gpb-2", "gpb-3";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                i2c4_bus: i2c4-bus {
-                        samsung,pins = "gpb-2", "gpb-3";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                spi1_bus: spi1-bus {
-                        samsung,pins = "gpb-4", "gpb-6", "gpb-7";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                i2c5_bus: i2c5-bus {
-                        samsung,pins = "gpb-6", "gpb-7";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                i2s1_bus: i2s1-bus {
-                        samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
-                                        "gpc0-4";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                pcm1_bus: pcm1-bus {
-                        samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
-                                        "gpc0-4";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                ac97_bus: ac97-bus {
-                        samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
-                                        "gpc0-4";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                i2s2_bus: i2s2-bus {
-                        samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
-                                        "gpc1-4";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                pcm2_bus: pcm2-bus {
-                        samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
-                                        "gpc1-4";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                spdif_bus: spdif-bus {
-                        samsung,pins = "gpc1-0", "gpc1-1";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                i2c6_bus: i2c6-bus {
-                        samsung,pins = "gpc1-3", "gpc1-4";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                spi2_bus: spi2-bus {
-                        samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_5>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                i2c7_bus: i2c7-bus {
-                        samsung,pins = "gpd0-2", "gpd0-3";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                i2c0_bus: i2c0-bus {
-                        samsung,pins = "gpd1-0", "gpd1-1";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                i2c1_bus: i2c1-bus {
-                        samsung,pins = "gpd1-2", "gpd1-3";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                pwm0_out: pwm0-out {
-                        samsung,pins = "gpd0-0";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                pwm1_out: pwm1-out {
-                        samsung,pins = "gpd0-1";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                pwm2_out: pwm2-out {
-                        samsung,pins = "gpd0-2";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                pwm3_out: pwm3-out {
-                        samsung,pins = "gpd0-3";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                lcd_ctrl: lcd-ctrl {
-                        samsung,pins = "gpd0-0", "gpd0-1";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                lcd_sync: lcd-sync {
-                        samsung,pins = "gpf0-0", "gpf0-1";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                lcd_en: lcd-en {
-                        samsung,pins = "gpe3-4";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                lcd_clk: lcd-clk {
-                        samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                lcd_data16: lcd-data-width16 {
-                        samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2",
-                                        "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0",
-                                        "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7",
-                                        "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                lcd_data18: lcd-data-width18 {
-                        samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1",
-                                        "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7",
-                                        "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
-                                        "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1",
-                                        "gpf3-2", "gpf3-3";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                lcd_data24: lcd-data-width24 {
-                        samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7",
-                                        "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3",
-                                        "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7",
-                                        "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
-                                        "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7",
-                                        "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-        };
-
-        pinctrl@11000000 {
-                gpj0: gpj0 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpj1: gpj1 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpk0: gpk0 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpk1: gpk1 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpk2: gpk2 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpk3: gpk3 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpl0: gpl0 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpl1: gpl1 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpl2: gpl2 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpy0: gpy0 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                };
-
-                gpy1: gpy1 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                };
-
-                gpy2: gpy2 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                };
-
-                gpy3: gpy3 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                };
-
-                gpy4: gpy4 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                };
-
-                gpy5: gpy5 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                };
-
-                gpy6: gpy6 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                };
-
-                gpx0: gpx0 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        interrupt-parent = <&gic>;
-                        interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
-                        #interrupt-cells = <2>;
-                };
-
-                gpx1: gpx1 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        interrupt-parent = <&gic>;
-                        interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
-                        #interrupt-cells = <2>;
-                };
-
-                gpx2: gpx2 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpx3: gpx3 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                sd0_clk: sd0-clk {
-                        samsung,pins = "gpk0-0";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd0_cmd: sd0-cmd {
-                        samsung,pins = "gpk0-1";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd0_cd: sd0-cd {
-                        samsung,pins = "gpk0-2";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd0_bus1: sd0-bus-width1 {
-                        samsung,pins = "gpk0-3";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd0_bus4: sd0-bus-width4 {
-                        samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd0_bus8: sd0-bus-width8 {
-                        samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd4_clk: sd4-clk {
-                        samsung,pins = "gpk0-0";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd4_cmd: sd4-cmd {
-                        samsung,pins = "gpk0-1";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd4_cd: sd4-cd {
-                        samsung,pins = "gpk0-2";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd4_bus1: sd4-bus-width1 {
-                        samsung,pins = "gpk0-3";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd4_bus4: sd4-bus-width4 {
-                        samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd4_bus8: sd4-bus-width8 {
-                        samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd1_clk: sd1-clk {
-                        samsung,pins = "gpk1-0";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd1_cmd: sd1-cmd {
-                        samsung,pins = "gpk1-1";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd1_cd: sd1-cd {
-                        samsung,pins = "gpk1-2";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd1_bus1: sd1-bus-width1 {
-                        samsung,pins = "gpk1-3";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd1_bus4: sd1-bus-width4 {
-                        samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd2_clk: sd2-clk {
-                        samsung,pins = "gpk2-0";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd2_cmd: sd2-cmd {
-                        samsung,pins = "gpk2-1";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd2_cd: sd2-cd {
-                        samsung,pins = "gpk2-2";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd2_bus1: sd2-bus-width1 {
-                        samsung,pins = "gpk2-3";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd2_bus4: sd2-bus-width4 {
-                        samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd2_bus8: sd2-bus-width8 {
-                        samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd3_clk: sd3-clk {
-                        samsung,pins = "gpk3-0";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd3_cmd: sd3-cmd {
-                        samsung,pins = "gpk3-1";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd3_cd: sd3-cd {
-                        samsung,pins = "gpk3-2";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd3_bus1: sd3-bus-width1 {
-                        samsung,pins = "gpk3-3";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd3_bus4: sd3-bus-width4 {
-                        samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                eint0: ext-int0 {
-                        samsung,pins = "gpx0-0";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                eint8: ext-int8 {
-                        samsung,pins = "gpx1-0";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                eint15: ext-int15 {
-                        samsung,pins = "gpx1-7";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                eint16: ext-int16 {
-                        samsung,pins = "gpx2-0";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                eint31: ext-int31 {
-                        samsung,pins = "gpx3-7";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                cam_port_a_io: cam-port-a-io {
-                        samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3",
-                                        "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7",
-                                        "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                cam_port_a_clk_active: cam-port-a-clk-active {
-                        samsung,pins = "gpj1-3";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                cam_port_a_clk_idle: cam-port-a-clk-idle {
-                        samsung,pins = "gpj1-3";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                hdmi_cec: hdmi-cec {
-                        samsung,pins = "gpx3-6";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-        };
-
-        pinctrl@3860000 {
-                gpz: gpz {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                };
-
-                i2s0_bus: i2s0-bus {
-                        samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
-                                        "gpz-4", "gpz-5", "gpz-6";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                pcm0_bus: pcm0-bus {
-                        samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
-                                        "gpz-4";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
+        pcm0_bus: pcm0-bus {
+                samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
+                                "gpz-4";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
         };
 };
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index aaade17b140e..eaeeb4f6b84a 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -148,43 +148,12 @@
                 };
         };
 
-        camera {
-                pinctrl-names = "default";
-                pinctrl-0 = <>;
-                status = "okay";
-
-                fimc_0: fimc@11800000 {
-                        status = "okay";
-                        assigned-clocks = <&clock CLK_MOUT_FIMC0>,
-                                        <&clock CLK_SCLK_FIMC0>;
-                        assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
-                        assigned-clock-rates = <0>, <160000000>;
-                };
-
-                fimc_1: fimc@11810000 {
-                        status = "okay";
-                        assigned-clocks = <&clock CLK_MOUT_FIMC1>,
-                                        <&clock CLK_SCLK_FIMC1>;
-                        assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
-                        assigned-clock-rates = <0>, <160000000>;
-                };
-
-                fimc_2: fimc@11820000 {
-                        status = "okay";
-                        assigned-clocks = <&clock CLK_MOUT_FIMC2>,
-                                        <&clock CLK_SCLK_FIMC2>;
-                        assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
-                        assigned-clock-rates = <0>, <160000000>;
-                };
+};
 
-                fimc_3: fimc@11830000 {
-                        status = "okay";
-                        assigned-clocks = <&clock CLK_MOUT_FIMC3>,
-                                        <&clock CLK_SCLK_FIMC3>;
-                        assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
-                        assigned-clock-rates = <0>, <160000000>;
-                };
-        };
+&camera {
+        pinctrl-names = "default";
+        pinctrl-0 = <>;
+        status = "okay";
 };
 
 &cpu0 {
@@ -234,6 +203,38 @@
         vbus-supply = <&safe1_sreg>;
 };
 
+&fimc_0 {
+        status = "okay";
+        assigned-clocks = <&clock CLK_MOUT_FIMC0>,
+                          <&clock CLK_SCLK_FIMC0>;
+        assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+        assigned-clock-rates = <0>, <160000000>;
+};
+
+&fimc_1 {
+        status = "okay";
+        assigned-clocks = <&clock CLK_MOUT_FIMC1>,
+                          <&clock CLK_SCLK_FIMC1>;
+        assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+        assigned-clock-rates = <0>, <160000000>;
+};
+
+&fimc_2 {
+        status = "okay";
+        assigned-clocks = <&clock CLK_MOUT_FIMC2>,
+                          <&clock CLK_SCLK_FIMC2>;
+        assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+                assigned-clock-rates = <0>, <160000000>;
+};
+
+&fimc_3 {
+        status = "okay";
+        assigned-clocks = <&clock CLK_MOUT_FIMC3>,
+                          <&clock CLK_SCLK_FIMC3>;
+        assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+        assigned-clock-rates = <0>, <160000000>;
+};
+
 &fimd {
         status = "okay";
 };
@@ -275,6 +276,7 @@
 
         max8997_pmic@66 {
                 compatible = "maxim,max8997-pmic";
+                interrupts-extended = <&gpx0 7 0>, <&gpx2 3 0>;
 
                 reg = <0x66>;
                 interrupt-parent = <&gpx0>;
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index 21fff7cd3aa4..4e6ff97e1ec4 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -28,24 +28,6 @@
                 stdout-path = &serial_2;
         };
 
-        sysram@2020000 {
-                smp-sysram@0 {
-                        status = "disabled";
-                };
-
-                smp-sysram@5000 {
-                        compatible = "samsung,exynos4210-sysram";
-                        reg = <0x5000 0x1000>;
-                };
-
-                smp-sysram@1f000 {
-                        status = "disabled";
-                };
-        };
-
-        mct@10050000 {
-                compatible = "none";
-        };
 
         fixed-rate-clocks {
                 xxti {
@@ -173,45 +155,6 @@
                 };
         };
 
-        camera {
-                status = "okay";
-
-                pinctrl-names = "default";
-                pinctrl-0 = <>;
-
-                fimc_0: fimc@11800000 {
-                        status = "okay";
-                        assigned-clocks = <&clock CLK_MOUT_FIMC0>,
-                                        <&clock CLK_SCLK_FIMC0>;
-                        assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
-                        assigned-clock-rates = <0>, <160000000>;
-                };
-
-                fimc_1: fimc@11810000 {
-                        status = "okay";
-                        assigned-clocks = <&clock CLK_MOUT_FIMC1>,
-                                        <&clock CLK_SCLK_FIMC1>;
-                        assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
-                        assigned-clock-rates = <0>, <160000000>;
-                };
-
-                fimc_2: fimc@11820000 {
-                        status = "okay";
-                        assigned-clocks = <&clock CLK_MOUT_FIMC2>,
-                                        <&clock CLK_SCLK_FIMC2>;
-                        assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
-                        assigned-clock-rates = <0>, <160000000>;
-                };
-
-                fimc_3: fimc@11830000 {
-                        status = "okay";
-                        assigned-clocks = <&clock CLK_MOUT_FIMC3>,
-                                        <&clock CLK_SCLK_FIMC3>;
-                        assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
-                        assigned-clock-rates = <0>, <160000000>;
-                };
-        };
-
         hdmi_en: voltage-regulator-hdmi-5v {
                 compatible = "regulator-fixed";
                 regulator-name = "HDMI_5V";
@@ -234,6 +177,13 @@
         };
 };
 
+&camera {
+        status = "okay";
+
+        pinctrl-names = "default";
+        pinctrl-0 = <>;
+};
+
 &cpu0 {
         cpu0-supply = <&vdd_arm_reg>;
 };
@@ -250,6 +200,38 @@
         vbus-supply = <&safeout1_reg>;
 };
 
+&fimc_0 {
+        status = "okay";
+        assigned-clocks = <&clock CLK_MOUT_FIMC0>,
+                          <&clock CLK_SCLK_FIMC0>;
+        assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+        assigned-clock-rates = <0>, <160000000>;
+};
+
+&fimc_1 {
+        status = "okay";
+        assigned-clocks = <&clock CLK_MOUT_FIMC1>,
+                          <&clock CLK_SCLK_FIMC1>;
+        assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+        assigned-clock-rates = <0>, <160000000>;
+};
+
+&fimc_2 {
+        status = "okay";
+        assigned-clocks = <&clock CLK_MOUT_FIMC2>,
+                          <&clock CLK_SCLK_FIMC2>;
+        assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+        assigned-clock-rates = <0>, <160000000>;
+};
+
+&fimc_3 {
+        status = "okay";
+        assigned-clocks = <&clock CLK_MOUT_FIMC3>,
+                          <&clock CLK_SCLK_FIMC3>;
+        assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
+        assigned-clock-rates = <0>, <160000000>;
+};
+
 &fimd {
         pinctrl-0 = <&lcd_clk>, <&lcd_data24>;
         pinctrl-names = "default";
@@ -501,6 +483,10 @@
         status = "okay";
 };
 
+&mct {
+        compatible = "none";
+};
+
 &mdma1 {
         reg = <0x12840000 0x1000>;
 };
@@ -579,3 +565,18 @@
         /delete-property/dmas;
         /delete-property/dma-names;
 };
+
+&sysram {
+        smp-sysram@0 {
+                status = "disabled";
+        };
+
+        smp-sysram@5000 {
+                compatible = "samsung,exynos4210-sysram";
+                reg = <0x5000 0x1000>;
+        };
+
+        smp-sysram@1f000 {
+                status = "disabled";
+        };
+};
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index cc978cf28267..88fb47cef9a8 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -17,7 +17,6 @@
  */
 
 #include "exynos4.dtsi"
-#include "exynos4210-pinctrl.dtsi"
 #include "exynos4-cpu-thermal.dtsi"
 
 / {
@@ -49,8 +48,6 @@
                                 400000  975000
                                 200000  950000
                         >;
-                        cooling-min-level = <4>;
-                        cooling-max-level = <2>;
                         #cooling-cells = <2>; /* min followed by max */
                 };
 
@@ -61,365 +58,323 @@
                 };
         };
 
-        sysram: sysram@2020000 {
-                compatible = "mmio-sram";
-                reg = <0x02020000 0x20000>;
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges = <0 0x02020000 0x20000>;
+        soc: soc {
+                sysram: sysram@2020000 {
+                        compatible = "mmio-sram";
+                        reg = <0x02020000 0x20000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x02020000 0x20000>;
 
-                smp-sysram@0 {
-                        compatible = "samsung,exynos4210-sysram";
-                        reg = <0x0 0x1000>;
-                };
+                        smp-sysram@0 {
+                                compatible = "samsung,exynos4210-sysram";
+                                reg = <0x0 0x1000>;
+                        };
 
-                smp-sysram@1f000 {
-                        compatible = "samsung,exynos4210-sysram-ns";
-                        reg = <0x1f000 0x1000>;
+                        smp-sysram@1f000 {
+                                compatible = "samsung,exynos4210-sysram-ns";
+                                reg = <0x1f000 0x1000>;
+                        };
                 };
-        };
 
-        pd_lcd1: lcd1-power-domain@10023ca0 {
-                compatible = "samsung,exynos4210-pd";
-                reg = <0x10023CA0 0x20>;
-                #power-domain-cells = <0>;
-                label = "LCD1";
-        };
+                pd_lcd1: lcd1-power-domain@10023ca0 {
+                        compatible = "samsung,exynos4210-pd";
+                        reg = <0x10023CA0 0x20>;
+                        #power-domain-cells = <0>;
+                        label = "LCD1";
+                };
 
-        l2c: l2-cache-controller@10502000 {
-                compatible = "arm,pl310-cache";
-                reg = <0x10502000 0x1000>;
-                cache-unified;
-                cache-level = <2>;
-                arm,tag-latency = <2 2 1>;
-                arm,data-latency = <2 2 1>;
-        };
+                l2c: l2-cache-controller@10502000 {
+                        compatible = "arm,pl310-cache";
+                        reg = <0x10502000 0x1000>;
+                        cache-unified;
+                        cache-level = <2>;
+                        arm,tag-latency = <2 2 1>;
+                        arm,data-latency = <2 2 1>;
+                };
 
-        mct: mct@10050000 {
-                compatible = "samsung,exynos4210-mct";
-                reg = <0x10050000 0x800>;
-                interrupt-parent = <&mct_map>;
-                interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
-                clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
-                clock-names = "fin_pll", "mct";
-
-                mct_map: mct-map {
-                        #interrupt-cells = <1>;
-                        #address-cells = <0>;
-                        #size-cells = <0>;
-                        interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
+                mct: mct@10050000 {
+                        compatible = "samsung,exynos4210-mct";
+                        reg = <0x10050000 0x800>;
+                        interrupt-parent = <&mct_map>;
+                        interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
+                        clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
+                        clock-names = "fin_pll", "mct";
+
+                        mct_map: mct-map {
+                                #interrupt-cells = <1>;
+                                #address-cells = <0>;
+                                #size-cells = <0>;
+                                interrupt-map =
+                                        <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
                                         <1 &gic 0 69 IRQ_TYPE_LEVEL_HIGH>,
                                         <2 &combiner 12 6>,
                                         <3 &combiner 12 7>,
                                         <4 &gic 0 42 IRQ_TYPE_LEVEL_HIGH>,
                                         <5 &gic 0 48 IRQ_TYPE_LEVEL_HIGH>;
+                        };
                 };
-        };
 
-        watchdog: watchdog@10060000 {
-                compatible = "samsung,s3c6410-wdt";
-                reg = <0x10060000 0x100>;
-                interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_WDT>;
-                clock-names = "watchdog";
-        };
-
-        clock: clock-controller@10030000 {
-                compatible = "samsung,exynos4210-clock";
-                reg = <0x10030000 0x20000>;
-                #clock-cells = <1>;
-        };
-
-        pinctrl_0: pinctrl@11400000 {
-                compatible = "samsung,exynos4210-pinctrl";
-                reg = <0x11400000 0x1000>;
-                interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
-        };
-
-        pinctrl_1: pinctrl@11000000 {
-                compatible = "samsung,exynos4210-pinctrl";
-                reg = <0x11000000 0x1000>;
-                interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
-
-                wakup_eint: wakeup-interrupt-controller {
-                        compatible = "samsung,exynos4210-wakeup-eint";
-                        interrupt-parent = <&gic>;
-                        interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+                watchdog: watchdog@10060000 {
+                        compatible = "samsung,s3c6410-wdt";
+                        reg = <0x10060000 0x100>;
+                        interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_WDT>;
+                        clock-names = "watchdog";
                 };
-        };
 
-        pinctrl_2: pinctrl@3860000 {
-                compatible = "samsung,exynos4210-pinctrl";
-                reg = <0x03860000 0x1000>;
-        };
+                clock: clock-controller@10030000 {
+                        compatible = "samsung,exynos4210-clock";
+                        reg = <0x10030000 0x20000>;
+                        #clock-cells = <1>;
+                };
 
-        tmu: tmu@100c0000 {
-                compatible = "samsung,exynos4210-tmu";
-                interrupt-parent = <&combiner>;
-                reg = <0x100C0000 0x100>;
-                interrupts = <2 4>;
-                clocks = <&clock CLK_TMU_APBIF>;
-                clock-names = "tmu_apbif";
-                samsung,tmu_gain = <15>;
-                samsung,tmu_reference_voltage = <7>;
-                status = "disabled";
-        };
+                pinctrl_0: pinctrl@11400000 {
+                        compatible = "samsung,exynos4210-pinctrl";
+                        reg = <0x11400000 0x1000>;
+                        interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+                };
 
-        thermal-zones {
-                cpu_thermal: cpu-thermal {
-                        polling-delay-passive = <0>;
-                        polling-delay = <0>;
-                        thermal-sensors = <&tmu 0>;
+                pinctrl_1: pinctrl@11000000 {
+                        compatible = "samsung,exynos4210-pinctrl";
+                        reg = <0x11000000 0x1000>;
+                        interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 
-                        trips {
-                              cpu_alert0: cpu-alert-0 {
-                                      temperature = <85000>; /* millicelsius */
-                              };
-                              cpu_alert1: cpu-alert-1 {
-                                      temperature = <100000>; /* millicelsius */
-                              };
-                              cpu_alert2: cpu-alert-2 {
-                                      temperature = <110000>; /* millicelsius */
-                              };
+                        wakup_eint: wakeup-interrupt-controller {
+                                compatible = "samsung,exynos4210-wakeup-eint";
+                                interrupt-parent = <&gic>;
+                                interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
                         };
                 };
-        };
-
-        g2d: g2d@12800000 {
-                compatible = "samsung,s5pv210-g2d";
-                reg = <0x12800000 0x1000>;
-                interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
-                clock-names = "sclk_fimg2d", "fimg2d";
-                power-domains = <&pd_lcd0>;
-                iommus = <&sysmmu_g2d>;
-        };
 
-        camera {
-                clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
-                         <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
-                clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
+                pinctrl_2: pinctrl@3860000 {
+                        compatible = "samsung,exynos4210-pinctrl";
+                        reg = <0x03860000 0x1000>;
+                };
 
-                fimc_0: fimc@11800000 {
-                        samsung,pix-limits = <4224 8192 1920 4224>;
-                        samsung,mainscaler-ext;
-                        samsung,cam-if;
+                g2d: g2d@12800000 {
+                        compatible = "samsung,s5pv210-g2d";
+                        reg = <0x12800000 0x1000>;
+                        interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
+                        clock-names = "sclk_fimg2d", "fimg2d";
+                        power-domains = <&pd_lcd0>;
+                        iommus = <&sysmmu_g2d>;
                 };
 
-                fimc_1: fimc@11810000 {
-                        samsung,pix-limits = <4224 8192 1920 4224>;
-                        samsung,mainscaler-ext;
-                        samsung,cam-if;
+                ppmu_acp: ppmu_acp@10ae0000 {
+                        compatible = "samsung,exynos-ppmu";
+                        reg = <0x10ae0000 0x2000>;
+                        status = "disabled";
                 };
 
-                fimc_2: fimc@11820000 {
-                        samsung,pix-limits = <4224 8192 1920 4224>;
-                        samsung,mainscaler-ext;
-                        samsung,lcd-wb;
+                ppmu_lcd1: ppmu_lcd1@12240000 {
+                        compatible = "samsung,exynos-ppmu";
+                        reg = <0x12240000 0x2000>;
+                        clocks = <&clock CLK_PPMULCD1>;
+                        clock-names = "ppmu";
+                        status = "disabled";
                 };
 
-                fimc_3: fimc@11830000 {
-                        samsung,pix-limits = <1920 8192 1366 1920>;
-                        samsung,rotators = <0>;
-                        samsung,mainscaler-ext;
-                        samsung,lcd-wb;
+                sysmmu_g2d: sysmmu@12a20000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x12A20000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <4 7>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
+                        power-domains = <&pd_lcd0>;
+                        #iommu-cells = <0>;
                 };
-        };
 
-        mixer: mixer@12c10000 {
-                clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
-                        "sclk_mixer";
-                clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
-                        <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>,
-                        <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
-        };
+                sysmmu_fimd1: sysmmu@12220000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        interrupt-parent = <&combiner>;
+                        reg = <0x12220000 0x1000>;
+                        interrupts = <5 3>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
+                        power-domains = <&pd_lcd1>;
+                        #iommu-cells = <0>;
+                };
 
-        ppmu_lcd1: ppmu_lcd1@12240000 {
-                compatible = "samsung,exynos-ppmu";
-                reg = <0x12240000 0x2000>;
-                clocks = <&clock CLK_PPMULCD1>;
-                clock-names = "ppmu";
-                status = "disabled";
-        };
+                bus_dmc: bus_dmc {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&clock CLK_DIV_DMC>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_dmc_opp_table>;
+                        status = "disabled";
+                };
 
-        sysmmu_g2d: sysmmu@12a20000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x12A20000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <4 7>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
-                power-domains = <&pd_lcd0>;
-                #iommu-cells = <0>;
-        };
+                bus_acp: bus_acp {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&clock CLK_DIV_ACP>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_acp_opp_table>;
+                        status = "disabled";
+                };
 
-        sysmmu_fimd1: sysmmu@12220000 {
-                compatible = "samsung,exynos-sysmmu";
-                interrupt-parent = <&combiner>;
-                reg = <0x12220000 0x1000>;
-                interrupts = <5 3>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
-                power-domains = <&pd_lcd1>;
-                #iommu-cells = <0>;
-        };
+                bus_peri: bus_peri {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&clock CLK_ACLK100>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_peri_opp_table>;
+                        status = "disabled";
+                };
 
-        bus_dmc: bus_dmc {
-                compatible = "samsung,exynos-bus";
-                clocks = <&clock CLK_DIV_DMC>;
-                clock-names = "bus";
-                operating-points-v2 = <&bus_dmc_opp_table>;
-                status = "disabled";
-        };
+                bus_fsys: bus_fsys {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&clock CLK_ACLK133>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_fsys_opp_table>;
+                        status = "disabled";
+                };
 
-        bus_acp: bus_acp {
-                compatible = "samsung,exynos-bus";
-                clocks = <&clock CLK_DIV_ACP>;
-                clock-names = "bus";
-                operating-points-v2 = <&bus_acp_opp_table>;
-                status = "disabled";
-        };
+                bus_display: bus_display {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&clock CLK_ACLK160>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_display_opp_table>;
+                        status = "disabled";
+                };
 
-        bus_peri: bus_peri {
-                compatible = "samsung,exynos-bus";
-                clocks = <&clock CLK_ACLK100>;
-                clock-names = "bus";
-                operating-points-v2 = <&bus_peri_opp_table>;
-                status = "disabled";
-        };
+                bus_lcd0: bus_lcd0 {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&clock CLK_ACLK200>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_leftbus_opp_table>;
+                        status = "disabled";
+                };
 
-        bus_fsys: bus_fsys {
-                compatible = "samsung,exynos-bus";
-                clocks = <&clock CLK_ACLK133>;
-                clock-names = "bus";
-                operating-points-v2 = <&bus_fsys_opp_table>;
-                status = "disabled";
-        };
+                bus_leftbus: bus_leftbus {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&clock CLK_DIV_GDL>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_leftbus_opp_table>;
+                        status = "disabled";
+                };
 
-        bus_display: bus_display {
-                compatible = "samsung,exynos-bus";
-                clocks = <&clock CLK_ACLK160>;
-                clock-names = "bus";
-                operating-points-v2 = <&bus_display_opp_table>;
-                status = "disabled";
-        };
+                bus_rightbus: bus_rightbus {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&clock CLK_DIV_GDR>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_leftbus_opp_table>;
+                        status = "disabled";
+                };
 
-        bus_lcd0: bus_lcd0 {
-                compatible = "samsung,exynos-bus";
-                clocks = <&clock CLK_ACLK200>;
-                clock-names = "bus";
-                operating-points-v2 = <&bus_leftbus_opp_table>;
-                status = "disabled";
-        };
+                bus_mfc: bus_mfc {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&clock CLK_SCLK_MFC>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_leftbus_opp_table>;
+                        status = "disabled";
+                };
 
-        bus_leftbus: bus_leftbus {
-                compatible = "samsung,exynos-bus";
-                clocks = <&clock CLK_DIV_GDL>;
-                clock-names = "bus";
-                operating-points-v2 = <&bus_leftbus_opp_table>;
-                status = "disabled";
-        };
+                bus_dmc_opp_table: opp_table1 {
+                        compatible = "operating-points-v2";
+                        opp-shared;
 
-        bus_rightbus: bus_rightbus {
-                compatible = "samsung,exynos-bus";
-                clocks = <&clock CLK_DIV_GDR>;
-                clock-names = "bus";
-                operating-points-v2 = <&bus_leftbus_opp_table>;
-                status = "disabled";
-        };
-
-        bus_mfc: bus_mfc {
-                compatible = "samsung,exynos-bus";
-                clocks = <&clock CLK_SCLK_MFC>;
-                clock-names = "bus";
-                operating-points-v2 = <&bus_leftbus_opp_table>;
-                status = "disabled";
-        };
+                        opp-134000000 {
+                                opp-hz = /bits/ 64 <134000000>;
+                                opp-microvolt = <1025000>;
+                        };
+                        opp-267000000 {
+                                opp-hz = /bits/ 64 <267000000>;
+                                opp-microvolt = <1050000>;
+                        };
+                        opp-400000000 {
+                                opp-hz = /bits/ 64 <400000000>;
+                                opp-microvolt = <1150000>;
+                        };
+                };
 
-        bus_dmc_opp_table: opp_table1 {
-                compatible = "operating-points-v2";
-                opp-shared;
+                bus_acp_opp_table: opp_table2 {
+                        compatible = "operating-points-v2";
+                        opp-shared;
 
-                opp-134000000 {
-                        opp-hz = /bits/ 64 <134000000>;
-                        opp-microvolt = <1025000>;
-                };
-                opp-267000000 {
-                        opp-hz = /bits/ 64 <267000000>;
-                        opp-microvolt = <1050000>;
-                };
-                opp-400000000 {
-                        opp-hz = /bits/ 64 <400000000>;
-                        opp-microvolt = <1150000>;
+                        opp-134000000 {
+                                opp-hz = /bits/ 64 <134000000>;
+                        };
+                        opp-160000000 {
+                                opp-hz = /bits/ 64 <160000000>;
+                        };
+                        opp-200000000 {
+                                opp-hz = /bits/ 64 <200000000>;
+                        };
                 };
-        };
 
-        bus_acp_opp_table: opp_table2 {
-                compatible = "operating-points-v2";
-                opp-shared;
+                bus_peri_opp_table: opp_table3 {
+                        compatible = "operating-points-v2";
+                        opp-shared;
 
-                opp-134000000 {
-                        opp-hz = /bits/ 64 <134000000>;
-                };
-                opp-160000000 {
-                        opp-hz = /bits/ 64 <160000000>;
-                };
-                opp-200000000 {
-                        opp-hz = /bits/ 64 <200000000>;
+                        opp-5000000 {
+                                opp-hz = /bits/ 64 <5000000>;
+                        };
+                        opp-100000000 {
+                                opp-hz = /bits/ 64 <100000000>;
+                        };
                 };
-        };
 
-        bus_peri_opp_table: opp_table3 {
-                compatible = "operating-points-v2";
-                opp-shared;
+                bus_fsys_opp_table: opp_table4 {
+                        compatible = "operating-points-v2";
+                        opp-shared;
 
-                opp-5000000 {
-                        opp-hz = /bits/ 64 <5000000>;
-                };
-                opp-100000000 {
-                        opp-hz = /bits/ 64 <100000000>;
+                        opp-10000000 {
+                                opp-hz = /bits/ 64 <10000000>;
+                        };
+                        opp-134000000 {
+                                opp-hz = /bits/ 64 <134000000>;
+                        };
                 };
-        };
 
-        bus_fsys_opp_table: opp_table4 {
-                compatible = "operating-points-v2";
-                opp-shared;
+                bus_display_opp_table: opp_table5 {
+                        compatible = "operating-points-v2";
+                        opp-shared;
 
-                opp-10000000 {
-                        opp-hz = /bits/ 64 <10000000>;
-                };
-                opp-134000000 {
-                        opp-hz = /bits/ 64 <134000000>;
+                        opp-100000000 {
+                                opp-hz = /bits/ 64 <100000000>;
+                        };
+                        opp-134000000 {
+                                opp-hz = /bits/ 64 <134000000>;
+                        };
+                        opp-160000000 {
+                                opp-hz = /bits/ 64 <160000000>;
+                        };
                 };
-        };
 
-        bus_display_opp_table: opp_table5 {
-                compatible = "operating-points-v2";
-                opp-shared;
+                bus_leftbus_opp_table: opp_table6 {
+                        compatible = "operating-points-v2";
+                        opp-shared;
 
-                opp-100000000 {
-                        opp-hz = /bits/ 64 <100000000>;
-                };
-                opp-134000000 {
-                        opp-hz = /bits/ 64 <134000000>;
-                };
-                opp-160000000 {
-                        opp-hz = /bits/ 64 <160000000>;
+                        opp-100000000 {
+                                opp-hz = /bits/ 64 <100000000>;
+                        };
+                        opp-160000000 {
+                                opp-hz = /bits/ 64 <160000000>;
+                        };
+                        opp-200000000 {
+                                opp-hz = /bits/ 64 <200000000>;
+                        };
                 };
         };
 
-        bus_leftbus_opp_table: opp_table6 {
-                compatible = "operating-points-v2";
-                opp-shared;
+        thermal-zones {
+                cpu_thermal: cpu-thermal {
+                        polling-delay-passive = <0>;
+                        polling-delay = <0>;
+                        thermal-sensors = <&tmu 0>;
 
-                opp-100000000 {
-                        opp-hz = /bits/ 64 <100000000>;
-                };
-                opp-160000000 {
-                        opp-hz = /bits/ 64 <160000000>;
-                };
-                opp-200000000 {
-                        opp-hz = /bits/ 64 <200000000>;
+                        trips {
+                                cpu_alert0: cpu-alert-0 {
+                                temperature = <85000>; /* millicelsius */
+                                };
+                                cpu_alert1: cpu-alert-1 {
+                                temperature = <100000>; /* millicelsius */
+                                };
+                                cpu_alert2: cpu-alert-2 {
+                                temperature = <110000>; /* millicelsius */
+                                };
+                        };
                 };
         };
 };
@@ -428,6 +383,12 @@
         cpu-offset = <0x8000>;
 };
 
+&camera {
+        clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
+                 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
+        clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
+};
+
 &combiner {
         samsung,combiner-nr = <16>;
         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
@@ -448,10 +409,43 @@
                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 };
 
+&fimc_0 {
+        samsung,pix-limits = <4224 8192 1920 4224>;
+        samsung,mainscaler-ext;
+        samsung,cam-if;
+};
+
+&fimc_1 {
+        samsung,pix-limits = <4224 8192 1920 4224>;
+        samsung,mainscaler-ext;
+        samsung,cam-if;
+};
+
+&fimc_2 {
+        samsung,pix-limits = <4224 8192 1920 4224>;
+        samsung,mainscaler-ext;
+        samsung,lcd-wb;
+};
+
+&fimc_3 {
+        samsung,pix-limits = <1920 8192 1366 1920>;
+        samsung,rotators = <0>;
+        samsung,mainscaler-ext;
+        samsung,lcd-wb;
+};
+
 &mdma1 {
         power-domains = <&pd_lcd0>;
 };
 
+&mixer {
+        clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
+                      "sclk_mixer";
+        clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
+                 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>,
+                 <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
+};
+
 &pmu_system_controller {
         clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
                         "clkout4", "clkout8", "clkout9";
@@ -468,3 +462,13 @@
 &sysmmu_rotator {
         power-domains = <&pd_lcd0>;
 };
+
+&tmu {
+        compatible = "samsung,exynos4210-tmu";
+        clocks = <&clock CLK_TMU_APBIF>;
+        clock-names = "tmu_apbif";
+        samsung,tmu_gain = <15>;
+        samsung,tmu_reference_voltage = <7>;
+};
+
+#include "exynos4210-pinctrl.dtsi"
diff --git a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi
new file mode 100644
index 000000000000..ee8e1f445370
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi
@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Samsung's Exynos4412 based Galaxy S3 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ */
+
+/dts-v1/;
+#include "exynos4412-midas.dtsi"
+
+/ {
+        aliases {
+                i2c9 = &i2c_ak8975;
+                i2c10 = &i2c_cm36651;
+        };
+
+        regulators {
+                lcd_vdd3_reg: voltage-regulator-2 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "LCD_VDD_2.2V";
+                        regulator-min-microvolt = <2200000>;
+                        regulator-max-microvolt = <2200000>;
+                        gpio = <&gpc0 1 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                };
+
+                ps_als_reg: voltage-regulator-5 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "LED_A_3.0V";
+                        regulator-min-microvolt = <3000000>;
+                        regulator-max-microvolt = <3000000>;
+                        gpio = <&gpj0 5 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                };
+        };
+
+        i2c_ak8975: i2c-gpio-0 {
+                compatible = "i2c-gpio";
+                gpios = <&gpy2 4 GPIO_ACTIVE_HIGH>, <&gpy2 5 GPIO_ACTIVE_HIGH>;
+                i2c-gpio,delay-us = <2>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "okay";
+
+                ak8975@c {
+                        compatible = "asahi-kasei,ak8975";
+                        reg = <0x0c>;
+                        gpios = <&gpj0 7 GPIO_ACTIVE_HIGH>;
+                };
+        };
+
+        i2c_cm36651: i2c-gpio-2 {
+                compatible = "i2c-gpio";
+                gpios = <&gpf0 0 GPIO_ACTIVE_LOW>, <&gpf0 1 GPIO_ACTIVE_LOW>;
+                i2c-gpio,delay-us = <2>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cm36651@18 {
+                        compatible = "capella,cm36651";
+                        reg = <0x18>;
+                        interrupt-parent = <&gpx0>;
+                        interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+                        vled-supply = <&ps_als_reg>;
+                };
+        };
+};
+
+&buck9_reg {
+        maxim,ena-gpios = <&gpm0 3 GPIO_ACTIVE_HIGH>;
+};
+
+&cam_af_reg {
+        gpio = <&gpm0 4 GPIO_ACTIVE_HIGH>;
+        status = "okay";
+};
+
+&cam_io_reg {
+        gpio = <&gpm0 2 GPIO_ACTIVE_HIGH>;
+        status = "okay";
+};
+
+&dsi_0 {
+        status = "okay";
+
+        panel@0 {
+                compatible = "samsung,s6e8aa0";
+                reg = <0>;
+                vdd3-supply = <&lcd_vdd3_reg>;
+                vci-supply = <&ldo25_reg>;
+                reset-gpios = <&gpf2 1 GPIO_ACTIVE_HIGH>;
+                power-on-delay= <50>;
+                reset-delay = <100>;
+                init-delay = <100>;
+                flip-horizontal;
+                flip-vertical;
+                panel-width-mm = <58>;
+                panel-height-mm = <103>;
+
+                display-timings {
+                        timing-0 {
+                                clock-frequency = <57153600>;
+                                hactive = <720>;
+                                vactive = <1280>;
+                                hfront-porch = <5>;
+                                hback-porch = <5>;
+                                hsync-len = <5>;
+                                vfront-porch = <13>;
+                                vback-porch = <1>;
+                                vsync-len = <2>;
+                        };
+                };
+        };
+};
+
+&i2c_3 {
+        mms114-touchscreen@48 {
+                compatible = "melfas,mms114";
+                reg = <0x48>;
+                interrupt-parent = <&gpm2>;
+                interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+                x-size = <720>;
+                y-size = <1280>;
+                avdd-supply = <&ldo23_reg>;
+                vdd-supply = <&ldo24_reg>;
+        };
+};
+
+&ldo25_reg {
+        regulator-name = "LCD_VCC_3.3V";
+        regulator-min-microvolt = <2800000>;
+        regulator-max-microvolt = <2800000>;
+};
+
+&s5c73m3 {
+        standby-gpios = <&gpm0 1 GPIO_ACTIVE_LOW>;   /* ISP_STANDBY */
+        vdda-supply = <&ldo17_reg>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/exynos4412-i9300.dts b/arch/arm/boot/dts/exynos4412-i9300.dts
new file mode 100644
index 000000000000..f8125a945f8d
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-i9300.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Samsung's Exynos4412 based M0 (GT-I9300) board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ */
+
+/dts-v1/;
+#include "exynos4412-galaxy-s3.dtsi"
+
+/ {
+        model = "Samsung Galaxy S3 (GT-I9300) based on Exynos4412";
+        compatible = "samsung,i9300", "samsung,midas", "samsung,exynos4412", "samsung,exynos4";
+
+        /* bootargs are passed in by bootloader */
+
+        memory@40000000 {
+                device_type = "memory";
+                reg =  <0x40000000 0x40000000>;
+        };
+};
diff --git a/arch/arm/boot/dts/exynos4412-i9305.dts b/arch/arm/boot/dts/exynos4412-i9305.dts
new file mode 100644
index 000000000000..54a2a55dbf70
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-i9305.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+#include "exynos4412-galaxy-s3.dtsi"
+
+/ {
+        model = "Samsung Galaxy S3 (GT-I9305) based on Exynos4412";
+        compatible = "samsung,i9305", "samsung,midas", "samsung,exynos4412", "samsung,exynos4";
+
+        /* bootargs are passed in by bootloader */
+
+        memory@40000000 {
+                device_type = "memory";
+                reg =  <0x40000000 0x80000000>;
+        };
+};
+
+&i2c0_bus {
+        /* SCL and SDA pins are swapped */
+        samsung,pins = "gpd1-1", "gpd1-0";
+};
diff --git a/arch/arm/boot/dts/exynos4412-itop-elite.dts b/arch/arm/boot/dts/exynos4412-itop-elite.dts
index a4cd4939fe9a..0dedeba89b5f 100644
--- a/arch/arm/boot/dts/exynos4412-itop-elite.dts
+++ b/arch/arm/boot/dts/exynos4412-itop-elite.dts
@@ -116,14 +116,6 @@
                 compatible = "pwm-beeper";
                 pwms = <&pwm 0 4000000 PWM_POLARITY_INVERTED>;
         };
-
-        camera: camera {
-                pinctrl-0 = <&cam_port_a_clk_active>;
-                pinctrl-names = "default";
-                status = "okay";
-                assigned-clocks = <&clock CLK_MOUT_CAM0>;
-                assigned-clock-parents = <&clock CLK_XUSBXTI>;
-        };
 };
 
 &adc {
@@ -131,6 +123,14 @@
         status = "okay";
 };
 
+&camera {
+        pinctrl-0 = <&cam_port_a_clk_active>;
+        pinctrl-names = "default";
+        status = "okay";
+        assigned-clocks = <&clock CLK_MOUT_CAM0>;
+        assigned-clock-parents = <&clock CLK_XUSBXTI>;
+};
+
 &clock_audss {
         assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
                         <&clock_audss EXYNOS_MOUT_I2S>,
diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi
new file mode 100644
index 000000000000..76f2b30f1731
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-midas.dtsi
@@ -0,0 +1,1308 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Samsung's Exynos4412 based Trats 2 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Device tree source file for Samsung's Trats 2 board which is based on
+ * Samsung's Exynos4412 SoC.
+ */
+
+/dts-v1/;
+#include "exynos4412.dtsi"
+#include "exynos4412-ppmu-common.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/maxim,max77686.h>
+#include <dt-bindings/pinctrl/samsung.h>
+
+/ {
+        compatible = "samsung,midas", "samsung,exynos4412", "samsung,exynos4";
+
+        aliases {
+                i2c11 = &i2c_max77693;
+                i2c12 = &i2c_max77693_fuel;
+        };
+
+        chosen {
+                stdout-path = &serial_2;
+        };
+
+        firmware@204f000 {
+                compatible = "samsung,secure-firmware";
+                reg = <0x0204F000 0x1000>;
+        };
+
+        fixed-rate-clocks {
+                xxti {
+                        compatible = "samsung,clock-xxti", "fixed-clock";
+                        clock-frequency = <0>;
+                };
+
+                xusbxti {
+                        compatible = "samsung,clock-xusbxti", "fixed-clock";
+                        clock-frequency = <24000000>;
+                };
+        };
+
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cam_io_reg: voltage-regulator-1 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "CAM_SENSOR_A";
+                        regulator-min-microvolt = <2800000>;
+                        regulator-max-microvolt = <2800000>;
+                        enable-active-high;
+                        status = "disabled";
+                };
+
+                cam_af_reg: voltage-regulator-3 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "CAM_AF";
+                        regulator-min-microvolt = <2800000>;
+                        regulator-max-microvolt = <2800000>;
+                        enable-active-high;
+                        status = "disabled";
+                };
+
+                vsil12: voltage-regulator-6 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "VSIL_1.2V";
+                        regulator-min-microvolt = <1200000>;
+                        regulator-max-microvolt = <1200000>;
+                        gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        vin-supply = <&buck7_reg>;
+                };
+
+                vcc33mhl: voltage-regulator-7 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "VCC_3.3_MHL";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                };
+
+                vcc18mhl: voltage-regulator-8 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "VCC_1.8_MHL";
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                        gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                };
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+
+                key-down {
+                        gpios = <&gpx3 3 GPIO_ACTIVE_LOW>;
+                        linux,code = <114>;
+                        label = "volume down";
+                        debounce-interval = <10>;
+                };
+
+                key-up {
+                        gpios = <&gpx2 2 GPIO_ACTIVE_LOW>;
+                        linux,code = <115>;
+                        label = "volume up";
+                        debounce-interval = <10>;
+                };
+
+                key-power {
+                        gpios = <&gpx2 7 GPIO_ACTIVE_LOW>;
+                        linux,code = <116>;
+                        label = "power";
+                        debounce-interval = <10>;
+                        wakeup-source;
+                };
+
+                key-ok {
+                        gpios = <&gpx0 1 GPIO_ACTIVE_LOW>;
+                        linux,code = <139>;
+                        label = "ok";
+                        debounce-interval = <10>;
+                        wakeup-source;
+                };
+        };
+
+        i2c_max77693: i2c-gpio-1 {
+                compatible = "i2c-gpio";
+                gpios = <&gpm2 0 GPIO_ACTIVE_HIGH>, <&gpm2 1 GPIO_ACTIVE_HIGH>;
+                i2c-gpio,delay-us = <2>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "okay";
+
+                max77693@66 {
+                        compatible = "maxim,max77693";
+                        interrupt-parent = <&gpx1>;
+                        interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
+                        reg = <0x66>;
+
+                        regulators {
+                                esafeout1_reg: ESAFEOUT1 {
+                                        regulator-name = "ESAFEOUT1";
+                                };
+                                esafeout2_reg: ESAFEOUT2 {
+                                        regulator-name = "ESAFEOUT2";
+                                };
+                                charger_reg: CHARGER {
+                                        regulator-name = "CHARGER";
+                                        regulator-min-microamp = <60000>;
+                                        regulator-max-microamp = <2580000>;
+                                };
+                        };
+
+                        max77693_haptic {
+                                compatible = "maxim,max77693-haptic";
+                                haptic-supply = <&ldo26_reg>;
+                                pwms = <&pwm 0 38022 0>;
+                        };
+
+                        charger {
+                                compatible = "maxim,max77693-charger";
+
+                                maxim,constant-microvolt = <4350000>;
+                                maxim,min-system-microvolt = <3600000>;
+                                maxim,thermal-regulation-celsius = <100>;
+                                maxim,battery-overcurrent-microamp = <3500000>;
+                                maxim,charge-input-threshold-microvolt = <4300000>;
+                        };
+                };
+        };
+
+        i2c_max77693_fuel: i2c-gpio-3 {
+                compatible = "i2c-gpio";
+                gpios = <&gpf1 5 GPIO_ACTIVE_HIGH>, <&gpf1 4 GPIO_ACTIVE_HIGH>;
+                i2c-gpio,delay-us = <2>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "okay";
+
+                max77693-fuel-gauge@36 {
+                        compatible = "maxim,max17047";
+                        interrupt-parent = <&gpx2>;
+                        interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+                        reg = <0x36>;
+
+                        maxim,over-heat-temp = <700>;
+                        maxim,over-volt = <4500>;
+                };
+        };
+
+        i2c-mhl {
+                compatible = "i2c-gpio";
+                gpios = <&gpf0 4 GPIO_ACTIVE_HIGH>, <&gpf0 6 GPIO_ACTIVE_HIGH>;
+                i2c-gpio,delay-us = <100>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                pinctrl-0 = <&i2c_mhl_bus>;
+                pinctrl-names = "default";
+                status = "okay";
+
+                sii9234: hdmi-bridge@39 {
+                        compatible = "sil,sii9234";
+                        avcc33-supply = <&vcc33mhl>;
+                        iovcc18-supply = <&vcc18mhl>;
+                        avcc12-supply = <&vsil12>;
+                        cvcc12-supply = <&vsil12>;
+                        reset-gpios = <&gpf3 4 GPIO_ACTIVE_LOW>;
+                        interrupt-parent = <&gpf3>;
+                        interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
+                        reg = <0x39>;
+
+                        port {
+                                mhl_to_hdmi: endpoint {
+                                        remote-endpoint = <&hdmi_to_mhl>;
+                                };
+                        };
+                };
+        };
+
+        wlan_pwrseq: sdhci3-pwrseq {
+                compatible = "mmc-pwrseq-simple";
+                reset-gpios = <&gpj0 0 GPIO_ACTIVE_LOW>;
+                clocks = <&max77686 MAX77686_CLK_PMIC>;
+                clock-names = "ext_clock";
+        };
+
+        sound {
+                compatible = "samsung,trats2-audio";
+                samsung,i2s-controller = <&i2s0>;
+                samsung,model = "Trats2";
+                samsung,audio-codec = <&wm1811>;
+                samsung,audio-routing =
+                        "SPK", "SPKOUTLN",
+                        "SPK", "SPKOUTLP",
+                        "SPK", "SPKOUTRN",
+                        "SPK", "SPKOUTRP";
+        };
+
+        thermistor-ap {
+                compatible = "murata,ncp15wb473";
+                pullup-uv = <1800000>;   /* VCC_1.8V_AP */
+                pullup-ohm = <100000>;   /* 100K */
+                pulldown-ohm = <100000>; /* 100K */
+                io-channels = <&adc 1>;  /* AP temperature */
+        };
+
+        thermistor-battery {
+                compatible = "murata,ncp15wb473";
+                pullup-uv = <1800000>;   /* VCC_1.8V_AP */
+                pullup-ohm = <100000>;   /* 100K */
+                pulldown-ohm = <100000>; /* 100K */
+                io-channels = <&adc 2>;  /* Battery temperature */
+        };
+
+        thermal-zones {
+                cpu_thermal: cpu-thermal {
+                        cooling-maps {
+                                map0 {
+                                     /* Corresponds to 800MHz at freq_table */
+                                     cooling-device = <&cpu0 7 7>;
+                                };
+                                map1 {
+                                     /* Corresponds to 200MHz at freq_table */
+                                     cooling-device = <&cpu0 13 13>;
+                               };
+                       };
+                };
+        };
+};
+
+&adc {
+        vdd-supply = <&ldo3_reg>;
+        status = "okay";
+};
+
+&bus_dmc {
+        devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
+        vdd-supply = <&buck1_reg>;
+        status = "okay";
+};
+
+&bus_acp {
+        devfreq = <&bus_dmc>;
+        status = "okay";
+};
+
+&bus_c2c {
+        devfreq = <&bus_dmc>;
+        status = "okay";
+};
+
+&bus_leftbus {
+        devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
+        vdd-supply = <&buck3_reg>;
+        status = "okay";
+};
+
+&bus_rightbus {
+        devfreq = <&bus_leftbus>;
+        status = "okay";
+};
+
+&bus_display {
+        devfreq = <&bus_leftbus>;
+        status = "okay";
+};
+
+&bus_fsys {
+        devfreq = <&bus_leftbus>;
+        status = "okay";
+};
+
+&bus_peri {
+        devfreq = <&bus_leftbus>;
+        status = "okay";
+};
+
+&bus_mfc {
+        devfreq = <&bus_leftbus>;
+        status = "okay";
+};
+
+&camera {
+        pinctrl-0 = <&cam_port_a_clk_active &cam_port_b_clk_active>;
+        pinctrl-names = "default";
+        status = "okay";
+        assigned-clocks = <&clock CLK_MOUT_CAM0>,
+                <&clock CLK_MOUT_CAM1>;
+        assigned-clock-parents = <&clock CLK_XUSBXTI>,
+                <&clock CLK_XUSBXTI>;
+};
+
+&cpu0 {
+        cpu0-supply = <&buck2_reg>;
+};
+
+&csis_0 {
+        status = "okay";
+        vddcore-supply = <&ldo8_reg>;
+        vddio-supply = <&ldo10_reg>;
+        assigned-clocks = <&clock CLK_MOUT_CSIS0>,
+                        <&clock CLK_SCLK_CSIS0>;
+        assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
+        assigned-clock-rates = <0>, <176000000>;
+
+        /* Camera C (3) MIPI CSI-2 (CSIS0) */
+        port@3 {
+                reg = <3>;
+                csis0_ep: endpoint {
+                        remote-endpoint = <&s5c73m3_ep>;
+                        data-lanes = <1 2 3 4>;
+                        samsung,csis-hs-settle = <12>;
+                };
+        };
+};
+
+&csis_1 {
+        status = "okay";
+        vddcore-supply = <&ldo8_reg>;
+        vddio-supply = <&ldo10_reg>;
+        assigned-clocks = <&clock CLK_MOUT_CSIS1>,
+                        <&clock CLK_SCLK_CSIS1>;
+        assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
+        assigned-clock-rates = <0>, <176000000>;
+
+        /* Camera D (4) MIPI CSI-2 (CSIS1) */
+        port@4 {
+                reg = <4>;
+                csis1_ep: endpoint {
+                        remote-endpoint = <&is_s5k6a3_ep>;
+                        data-lanes = <1>;
+                        samsung,csis-hs-settle = <18>;
+                        samsung,csis-wclk;
+                };
+        };
+};
+
+&dsi_0 {
+        vddcore-supply = <&ldo8_reg>;
+        vddio-supply = <&ldo10_reg>;
+        samsung,burst-clock-frequency = <500000000>;
+        samsung,esc-clock-frequency = <20000000>;
+        samsung,pll-clock-frequency = <24000000>;
+};
+
+&exynos_usbphy {
+        vbus-supply = <&esafeout1_reg>;
+        status = "okay";
+};
+
+&fimc_0 {
+        status = "okay";
+        assigned-clocks = <&clock CLK_MOUT_FIMC0>,
+                        <&clock CLK_SCLK_FIMC0>;
+        assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
+        assigned-clock-rates = <0>, <176000000>;
+};
+
+&fimc_1 {
+        status = "okay";
+        assigned-clocks = <&clock CLK_MOUT_FIMC1>,
+                        <&clock CLK_SCLK_FIMC1>;
+        assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
+        assigned-clock-rates = <0>, <176000000>;
+};
+
+&fimc_2 {
+        status = "okay";
+        assigned-clocks = <&clock CLK_MOUT_FIMC2>,
+                        <&clock CLK_SCLK_FIMC2>;
+        assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
+        assigned-clock-rates = <0>, <176000000>;
+};
+
+&fimc_3 {
+        status = "okay";
+        assigned-clocks = <&clock CLK_MOUT_FIMC3>,
+                        <&clock CLK_SCLK_FIMC3>;
+        assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
+        assigned-clock-rates = <0>, <176000000>;
+};
+
+&fimc_is {
+        pinctrl-0 = <&fimc_is_uart>;
+        pinctrl-names = "default";
+        status = "okay";
+
+        };
+
+&fimc_lite_0 {
+        status = "okay";
+};
+
+&fimc_lite_1 {
+        status = "okay";
+};
+
+&fimd {
+        status = "okay";
+};
+
+&hdmi {
+        hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&hdmi_hpd>;
+        vdd-supply = <&ldo3_reg>;
+        vdd_osc-supply = <&ldo4_reg>;
+        vdd_pll-supply = <&ldo3_reg>;
+        ddc = <&i2c_5>;
+        status = "okay";
+
+        ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                port@1 {
+                        reg = <1>;
+                        hdmi_to_mhl: endpoint {
+                                remote-endpoint = <&mhl_to_hdmi>;
+                        };
+                };
+        };
+};
+
+&hsotg {
+        vusb_d-supply = <&ldo15_reg>;
+        vusb_a-supply = <&ldo12_reg>;
+        dr_mode = "peripheral";
+        status = "okay";
+};
+
+&i2c_0 {
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-slave-addr = <0x10>;
+        samsung,i2c-max-bus-freq = <400000>;
+        pinctrl-0 = <&i2c0_bus>;
+        pinctrl-names = "default";
+        status = "okay";
+
+        s5c73m3: s5c73m3@3c {
+                compatible = "samsung,s5c73m3";
+                reg = <0x3c>;
+                xshutdown-gpios = <&gpf1 3 GPIO_ACTIVE_LOW>; /* ISP_RESET */
+                vdd-int-supply = <&buck9_reg>;
+                vddio-cis-supply = <&ldo9_reg>;
+                vddio-host-supply = <&ldo18_reg>;
+                vdd-af-supply = <&cam_af_reg>;
+                vdd-reg-supply = <&cam_io_reg>;
+                clock-frequency = <24000000>;
+                /* CAM_A_CLKOUT */
+                clocks = <&camera 0>;
+                clock-names = "cis_extclk";
+                status = "disabled";
+                port {
+                        s5c73m3_ep: endpoint {
+                                remote-endpoint = <&csis0_ep>;
+                                data-lanes = <1 2 3 4>;
+                        };
+                };
+        };
+};
+
+&i2c1_isp {
+        pinctrl-0 = <&fimc_is_i2c1>;
+        pinctrl-names = "default";
+
+        s5k6a3@10 {
+                compatible = "samsung,s5k6a3";
+                reg = <0x10>;
+                svdda-supply = <&cam_io_reg>;
+                svddio-supply = <&ldo19_reg>;
+                afvdd-supply = <&ldo19_reg>;
+                clock-frequency = <24000000>;
+                /* CAM_B_CLKOUT */
+                clocks = <&camera 1>;
+                clock-names = "extclk";
+                samsung,camclk-out = <1>;
+                gpios = <&gpm1 6 GPIO_ACTIVE_HIGH>;
+
+                port {
+                        is_s5k6a3_ep: endpoint {
+                                remote-endpoint = <&csis1_ep>;
+                                data-lanes = <1>;
+                        };
+                };
+        };
+};
+
+&i2c_3 {
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-slave-addr = <0x10>;
+        samsung,i2c-max-bus-freq = <400000>;
+        pinctrl-0 = <&i2c3_bus>;
+        pinctrl-names = "default";
+        status = "okay";
+};
+
+&i2c_4 {
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-slave-addr = <0x10>;
+        samsung,i2c-max-bus-freq = <100000>;
+        pinctrl-0 = <&i2c4_bus>;
+        pinctrl-names = "default";
+        status = "okay";
+
+        wm1811: wm1811@1a {
+                compatible = "wlf,wm1811";
+                reg = <0x1a>;
+                clocks = <&pmu_system_controller 0>;
+                clock-names = "MCLK1";
+                DCVDD-supply = <&ldo3_reg>;
+                DBVDD1-supply = <&ldo3_reg>;
+                wlf,ldo1ena = <&gpj0 4 0>;
+        };
+};
+
+&i2c_5 {
+        status = "okay";
+};
+
+&i2c_7 {
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-slave-addr = <0x10>;
+        samsung,i2c-max-bus-freq = <100000>;
+        pinctrl-0 = <&i2c7_bus>;
+        pinctrl-names = "default";
+        status = "okay";
+
+        max77686: max77686_pmic@9 {
+                compatible = "maxim,max77686";
+                interrupt-parent = <&gpx0>;
+                interrupts = <7 IRQ_TYPE_NONE>;
+                reg = <0x09>;
+                #clock-cells = <1>;
+
+                voltage-regulators {
+                        ldo1_reg: LDO1 {
+                                regulator-name = "VALIVE_1.0V_AP";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                        };
+
+                        ldo2_reg: LDO2 {
+                                regulator-name = "VM1M2_1.2V_AP";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                };
+                        };
+
+                        ldo3_reg: LDO3 {
+                                regulator-name = "VCC_1.8V_AP";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+
+                        ldo4_reg: LDO4 {
+                                regulator-name = "VCC_2.8V_AP";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                                regulator-always-on;
+                        };
+
+                        ldo5_reg: LDO5 {
+                                regulator-name = "VCC_1.8V_IO";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+
+                        ldo6_reg: LDO6 {
+                                regulator-name = "VMPLL_1.0V_AP";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                };
+                        };
+
+                        ldo7_reg: LDO7 {
+                                regulator-name = "VPLL_1.0V_AP";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                };
+                        };
+
+                        ldo8_reg: LDO8 {
+                                regulator-name = "VMIPI_1.0V";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        ldo9_reg: LDO9 {
+                                regulator-name = "CAM_ISP_MIPI_1.2V";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                        };
+
+                        ldo10_reg: LDO10 {
+                                regulator-name = "VMIPI_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        ldo11_reg: LDO11 {
+                                regulator-name = "VABB1_1.95V";
+                                regulator-min-microvolt = <1950000>;
+                                regulator-max-microvolt = <1950000>;
+                                regulator-always-on;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        ldo12_reg: LDO12 {
+                                regulator-name = "VUOTG_3.0V";
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        ldo13_reg: LDO13 {
+                                regulator-name = "NFC_AVDD_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
+
+                        ldo14_reg: LDO14 {
+                                regulator-name = "VABB2_1.95V";
+                                regulator-min-microvolt = <1950000>;
+                                regulator-max-microvolt = <1950000>;
+                                regulator-always-on;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        ldo15_reg: LDO15 {
+                                regulator-name = "VHSIC_1.0V";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                };
+                        };
+
+                        ldo16_reg: LDO16 {
+                                regulator-name = "VHSIC_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                };
+                        };
+
+                        ldo17_reg: LDO17 {
+                                regulator-name = "CAM_SENSOR_CORE_1.2V";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                        };
+
+                        ldo18_reg: LDO18 {
+                                regulator-name = "CAM_ISP_SEN_IO_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
+
+                        ldo19_reg: LDO19 {
+                                regulator-name = "VT_CAM_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
+
+                        ldo20_reg: LDO20 {
+                                regulator-name = "VDDQ_PRE_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
+
+                        ldo21_reg: LDO21 {
+                                regulator-name = "VTF_2.8V";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                                maxim,ena-gpios = <&gpy2 0 GPIO_ACTIVE_HIGH>;
+                        };
+
+                        ldo22_reg: LDO22 {
+                                regulator-name = "VMEM_VDD_2.8V";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                                maxim,ena-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>;
+                        };
+
+                        ldo23_reg: LDO23 {
+                                regulator-name = "TSP_AVDD_3.3V";
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                        };
+
+                        ldo24_reg: LDO24 {
+                                regulator-name = "TSP_VDD_1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
+
+                        ldo25_reg: LDO25 {
+                                regulator-name = "LDO25";
+                        };
+
+                        ldo26_reg: LDO26 {
+                                regulator-name = "MOTOR_VCC_3.0V";
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                        };
+
+                        buck1_reg: BUCK1 {
+                                regulator-name = "vdd_mif";
+                                regulator-min-microvolt = <850000>;
+                                regulator-max-microvolt = <1100000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        buck2_reg: BUCK2 {
+                                regulator-name = "vdd_arm";
+                                regulator-min-microvolt = <850000>;
+                                regulator-max-microvolt = <1500000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-state-mem {
+                                        regulator-on-in-suspend;
+                                };
+                        };
+
+                        buck3_reg: BUCK3 {
+                                regulator-name = "vdd_int";
+                                regulator-min-microvolt = <850000>;
+                                regulator-max-microvolt = <1150000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        buck4_reg: BUCK4 {
+                                regulator-name = "vdd_g3d";
+                                regulator-min-microvolt = <850000>;
+                                regulator-max-microvolt = <1150000>;
+                                regulator-boot-on;
+                                regulator-state-mem {
+                                        regulator-off-in-suspend;
+                                };
+                        };
+
+                        buck5_reg: BUCK5 {
+                                regulator-name = "VMEM_1.2V_AP";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+                        };
+
+                        buck6_reg: BUCK6 {
+                                regulator-name = "VCC_SUB_1.35V";
+                                regulator-min-microvolt = <1350000>;
+                                regulator-max-microvolt = <1350000>;
+                                regulator-always-on;
+                        };
+
+                        buck7_reg: BUCK7 {
+                                regulator-name = "VCC_SUB_2.0V";
+                                regulator-min-microvolt = <2000000>;
+                                regulator-max-microvolt = <2000000>;
+                                regulator-always-on;
+                        };
+
+                        buck8_reg: BUCK8 {
+                                regulator-name = "VMEM_VDDF_3.0V";
+                                regulator-min-microvolt = <2850000>;
+                                regulator-max-microvolt = <2850000>;
+                                maxim,ena-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>;
+                        };
+
+                        buck9_reg: BUCK9 {
+                                regulator-name = "CAM_ISP_CORE_1.2V";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1200000>;
+                        };
+                };
+        };
+};
+
+&i2c_8 {
+        status = "okay";
+};
+
+&i2s0 {
+        pinctrl-0 = <&i2s0_bus>;
+        pinctrl-names = "default";
+        status = "okay";
+};
+
+&mixer {
+        status = "okay";
+};
+
+&mshc_0 {
+        broken-cd;
+        non-removable;
+        card-detect-delay = <200>;
+        vmmc-supply = <&ldo22_reg>;
+        clock-frequency = <400000000>;
+        samsung,dw-mshc-ciu-div = <0>;
+        samsung,dw-mshc-sdr-timing = <2 3>;
+        samsung,dw-mshc-ddr-timing = <1 2>;
+        pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
+        pinctrl-names = "default";
+        status = "okay";
+        bus-width = <8>;
+        cap-mmc-highspeed;
+};
+
+&pmu_system_controller {
+        assigned-clocks = <&pmu_system_controller 0>;
+        assigned-clock-parents =  <&clock CLK_XUSBXTI>;
+};
+
+&pinctrl_0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&sleep0>;
+
+        mhl_int: mhl-int {
+                samsung,pins = "gpf3-5";
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+        };
+
+        i2c_mhl_bus: i2c-mhl-bus {
+                samsung,pins = "gpf0-4", "gpf0-6";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        sleep0: sleep-states {
+                PIN_SLP(gpa0-0, INPUT, NONE);
+                PIN_SLP(gpa0-1, OUT0, NONE);
+                PIN_SLP(gpa0-2, INPUT, NONE);
+                PIN_SLP(gpa0-3, INPUT, UP);
+                PIN_SLP(gpa0-4, INPUT, NONE);
+                PIN_SLP(gpa0-5, INPUT, DOWN);
+                PIN_SLP(gpa0-6, INPUT, DOWN);
+                PIN_SLP(gpa0-7, INPUT, UP);
+
+                PIN_SLP(gpa1-0, INPUT, DOWN);
+                PIN_SLP(gpa1-1, INPUT, DOWN);
+                PIN_SLP(gpa1-2, INPUT, DOWN);
+                PIN_SLP(gpa1-3, INPUT, DOWN);
+                PIN_SLP(gpa1-4, INPUT, DOWN);
+                PIN_SLP(gpa1-5, INPUT, DOWN);
+
+                PIN_SLP(gpb-0, INPUT, NONE);
+                PIN_SLP(gpb-1, INPUT, NONE);
+                PIN_SLP(gpb-2, INPUT, NONE);
+                PIN_SLP(gpb-3, INPUT, NONE);
+                PIN_SLP(gpb-4, INPUT, DOWN);
+                PIN_SLP(gpb-5, INPUT, UP);
+                PIN_SLP(gpb-6, INPUT, DOWN);
+                PIN_SLP(gpb-7, INPUT, DOWN);
+
+                PIN_SLP(gpc0-0, INPUT, DOWN);
+                PIN_SLP(gpc0-1, INPUT, DOWN);
+                PIN_SLP(gpc0-2, INPUT, DOWN);
+                PIN_SLP(gpc0-3, INPUT, DOWN);
+                PIN_SLP(gpc0-4, INPUT, DOWN);
+
+                PIN_SLP(gpc1-0, INPUT, NONE);
+                PIN_SLP(gpc1-1, PREV, NONE);
+                PIN_SLP(gpc1-2, INPUT, NONE);
+                PIN_SLP(gpc1-3, INPUT, NONE);
+                PIN_SLP(gpc1-4, INPUT, NONE);
+
+                PIN_SLP(gpd0-0, INPUT, DOWN);
+                PIN_SLP(gpd0-1, INPUT, DOWN);
+                PIN_SLP(gpd0-2, INPUT, NONE);
+                PIN_SLP(gpd0-3, INPUT, NONE);
+
+                PIN_SLP(gpd1-0, INPUT, DOWN);
+                PIN_SLP(gpd1-1, INPUT, DOWN);
+                PIN_SLP(gpd1-2, INPUT, NONE);
+                PIN_SLP(gpd1-3, INPUT, NONE);
+
+                PIN_SLP(gpf0-0, INPUT, NONE);
+                PIN_SLP(gpf0-1, INPUT, NONE);
+                PIN_SLP(gpf0-2, INPUT, DOWN);
+                PIN_SLP(gpf0-3, INPUT, DOWN);
+                PIN_SLP(gpf0-4, INPUT, NONE);
+                PIN_SLP(gpf0-5, INPUT, DOWN);
+                PIN_SLP(gpf0-6, INPUT, NONE);
+                PIN_SLP(gpf0-7, INPUT, DOWN);
+
+                PIN_SLP(gpf1-0, INPUT, DOWN);
+                PIN_SLP(gpf1-1, INPUT, DOWN);
+                PIN_SLP(gpf1-2, INPUT, DOWN);
+                PIN_SLP(gpf1-3, INPUT, DOWN);
+                PIN_SLP(gpf1-4, INPUT, NONE);
+                PIN_SLP(gpf1-5, INPUT, NONE);
+                PIN_SLP(gpf1-6, INPUT, DOWN);
+                PIN_SLP(gpf1-7, PREV, NONE);
+
+                PIN_SLP(gpf2-0, PREV, NONE);
+                PIN_SLP(gpf2-1, INPUT, DOWN);
+                PIN_SLP(gpf2-2, INPUT, DOWN);
+                PIN_SLP(gpf2-3, INPUT, DOWN);
+                PIN_SLP(gpf2-4, INPUT, DOWN);
+                PIN_SLP(gpf2-5, INPUT, DOWN);
+                PIN_SLP(gpf2-6, INPUT, NONE);
+                PIN_SLP(gpf2-7, INPUT, NONE);
+
+                PIN_SLP(gpf3-0, INPUT, NONE);
+                PIN_SLP(gpf3-1, PREV, NONE);
+                PIN_SLP(gpf3-2, PREV, NONE);
+                PIN_SLP(gpf3-3, PREV, NONE);
+                PIN_SLP(gpf3-4, OUT1, NONE);
+                PIN_SLP(gpf3-5, INPUT, DOWN);
+
+                PIN_SLP(gpj0-0, PREV, NONE);
+                PIN_SLP(gpj0-1, PREV, NONE);
+                PIN_SLP(gpj0-2, PREV, NONE);
+                PIN_SLP(gpj0-3, INPUT, DOWN);
+                PIN_SLP(gpj0-4, PREV, NONE);
+                PIN_SLP(gpj0-5, PREV, NONE);
+                PIN_SLP(gpj0-6, INPUT, DOWN);
+                PIN_SLP(gpj0-7, INPUT, DOWN);
+
+                PIN_SLP(gpj1-0, INPUT, DOWN);
+                PIN_SLP(gpj1-1, PREV, NONE);
+                PIN_SLP(gpj1-2, PREV, NONE);
+                PIN_SLP(gpj1-3, INPUT, DOWN);
+                PIN_SLP(gpj1-4, INPUT, DOWN);
+        };
+};
+
+&pinctrl_1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&sleep1>;
+
+        hdmi_hpd: hdmi-hpd {
+                samsung,pins = "gpx3-7";
+                samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+        };
+
+        sleep1: sleep-states {
+                PIN_SLP(gpk0-0, PREV, NONE);
+                PIN_SLP(gpk0-1, PREV, NONE);
+                PIN_SLP(gpk0-2, OUT0, NONE);
+                PIN_SLP(gpk0-3, PREV, NONE);
+                PIN_SLP(gpk0-4, PREV, NONE);
+                PIN_SLP(gpk0-5, PREV, NONE);
+                PIN_SLP(gpk0-6, PREV, NONE);
+
+                PIN_SLP(gpk1-0, INPUT, DOWN);
+                PIN_SLP(gpk1-1, INPUT, DOWN);
+                PIN_SLP(gpk1-2, INPUT, DOWN);
+                PIN_SLP(gpk1-3, PREV, NONE);
+                PIN_SLP(gpk1-4, PREV, NONE);
+                PIN_SLP(gpk1-5, PREV, NONE);
+                PIN_SLP(gpk1-6, PREV, NONE);
+
+                PIN_SLP(gpk2-0, INPUT, DOWN);
+                PIN_SLP(gpk2-1, INPUT, DOWN);
+                PIN_SLP(gpk2-2, INPUT, DOWN);
+                PIN_SLP(gpk2-3, INPUT, DOWN);
+                PIN_SLP(gpk2-4, INPUT, DOWN);
+                PIN_SLP(gpk2-5, INPUT, DOWN);
+                PIN_SLP(gpk2-6, INPUT, DOWN);
+
+                PIN_SLP(gpk3-0, OUT0, NONE);
+                PIN_SLP(gpk3-1, INPUT, NONE);
+                PIN_SLP(gpk3-2, INPUT, DOWN);
+                PIN_SLP(gpk3-3, INPUT, NONE);
+                PIN_SLP(gpk3-4, INPUT, NONE);
+                PIN_SLP(gpk3-5, INPUT, NONE);
+                PIN_SLP(gpk3-6, INPUT, NONE);
+
+                PIN_SLP(gpl0-0, INPUT, DOWN);
+                PIN_SLP(gpl0-1, INPUT, DOWN);
+                PIN_SLP(gpl0-2, INPUT, DOWN);
+                PIN_SLP(gpl0-3, INPUT, DOWN);
+                PIN_SLP(gpl0-4, PREV, NONE);
+                PIN_SLP(gpl0-6, PREV, NONE);
+
+                PIN_SLP(gpl1-0, INPUT, DOWN);
+                PIN_SLP(gpl1-1, INPUT, DOWN);
+                PIN_SLP(gpl2-0, INPUT, DOWN);
+                PIN_SLP(gpl2-1, INPUT, DOWN);
+                PIN_SLP(gpl2-2, INPUT, DOWN);
+                PIN_SLP(gpl2-3, INPUT, DOWN);
+                PIN_SLP(gpl2-4, INPUT, DOWN);
+                PIN_SLP(gpl2-5, INPUT, DOWN);
+                PIN_SLP(gpl2-6, PREV, NONE);
+                PIN_SLP(gpl2-7, INPUT, DOWN);
+
+                PIN_SLP(gpm0-0, INPUT, DOWN);
+                PIN_SLP(gpm0-1, INPUT, DOWN);
+                PIN_SLP(gpm0-2, INPUT, DOWN);
+                PIN_SLP(gpm0-3, INPUT, DOWN);
+                PIN_SLP(gpm0-4, INPUT, DOWN);
+                PIN_SLP(gpm0-5, INPUT, DOWN);
+                PIN_SLP(gpm0-6, INPUT, DOWN);
+                PIN_SLP(gpm0-7, INPUT, DOWN);
+
+                PIN_SLP(gpm1-0, INPUT, DOWN);
+                PIN_SLP(gpm1-1, INPUT, DOWN);
+                PIN_SLP(gpm1-2, INPUT, NONE);
+                PIN_SLP(gpm1-3, INPUT, NONE);
+                PIN_SLP(gpm1-4, INPUT, NONE);
+                PIN_SLP(gpm1-5, INPUT, NONE);
+                PIN_SLP(gpm1-6, INPUT, DOWN);
+
+                PIN_SLP(gpm2-0, INPUT, NONE);
+                PIN_SLP(gpm2-1, INPUT, NONE);
+                PIN_SLP(gpm2-2, INPUT, DOWN);
+                PIN_SLP(gpm2-3, INPUT, DOWN);
+                PIN_SLP(gpm2-4, INPUT, DOWN);
+
+                PIN_SLP(gpm3-0, PREV, NONE);
+                PIN_SLP(gpm3-1, PREV, NONE);
+                PIN_SLP(gpm3-2, PREV, NONE);
+                PIN_SLP(gpm3-3, OUT1, NONE);
+                PIN_SLP(gpm3-4, INPUT, DOWN);
+                PIN_SLP(gpm3-5, INPUT, DOWN);
+                PIN_SLP(gpm3-6, INPUT, DOWN);
+                PIN_SLP(gpm3-7, INPUT, DOWN);
+
+                PIN_SLP(gpm4-0, INPUT, DOWN);
+                PIN_SLP(gpm4-1, INPUT, DOWN);
+                PIN_SLP(gpm4-2, INPUT, DOWN);
+                PIN_SLP(gpm4-3, INPUT, DOWN);
+                PIN_SLP(gpm4-4, INPUT, DOWN);
+                PIN_SLP(gpm4-5, INPUT, DOWN);
+                PIN_SLP(gpm4-6, INPUT, DOWN);
+                PIN_SLP(gpm4-7, INPUT, DOWN);
+
+                PIN_SLP(gpy0-0, INPUT, DOWN);
+                PIN_SLP(gpy0-1, INPUT, DOWN);
+                PIN_SLP(gpy0-2, INPUT, DOWN);
+                PIN_SLP(gpy0-3, INPUT, DOWN);
+                PIN_SLP(gpy0-4, INPUT, DOWN);
+                PIN_SLP(gpy0-5, INPUT, DOWN);
+
+                PIN_SLP(gpy1-0, INPUT, DOWN);
+                PIN_SLP(gpy1-1, INPUT, DOWN);
+                PIN_SLP(gpy1-2, INPUT, DOWN);
+                PIN_SLP(gpy1-3, INPUT, DOWN);
+
+                PIN_SLP(gpy2-0, PREV, NONE);
+                PIN_SLP(gpy2-1, INPUT, DOWN);
+                PIN_SLP(gpy2-2, INPUT, NONE);
+                PIN_SLP(gpy2-3, INPUT, NONE);
+                PIN_SLP(gpy2-4, INPUT, NONE);
+                PIN_SLP(gpy2-5, INPUT, NONE);
+
+                PIN_SLP(gpy3-0, INPUT, DOWN);
+                PIN_SLP(gpy3-1, INPUT, DOWN);
+                PIN_SLP(gpy3-2, INPUT, DOWN);
+                PIN_SLP(gpy3-3, INPUT, DOWN);
+                PIN_SLP(gpy3-4, INPUT, DOWN);
+                PIN_SLP(gpy3-5, INPUT, DOWN);
+                PIN_SLP(gpy3-6, INPUT, DOWN);
+                PIN_SLP(gpy3-7, INPUT, DOWN);
+
+                PIN_SLP(gpy4-0, INPUT, DOWN);
+                PIN_SLP(gpy4-1, INPUT, DOWN);
+                PIN_SLP(gpy4-2, INPUT, DOWN);
+                PIN_SLP(gpy4-3, INPUT, DOWN);
+                PIN_SLP(gpy4-4, INPUT, DOWN);
+                PIN_SLP(gpy4-5, INPUT, DOWN);
+                PIN_SLP(gpy4-6, INPUT, DOWN);
+                PIN_SLP(gpy4-7, INPUT, DOWN);
+
+                PIN_SLP(gpy5-0, INPUT, DOWN);
+                PIN_SLP(gpy5-1, INPUT, DOWN);
+                PIN_SLP(gpy5-2, INPUT, DOWN);
+                PIN_SLP(gpy5-3, INPUT, DOWN);
+                PIN_SLP(gpy5-4, INPUT, DOWN);
+                PIN_SLP(gpy5-5, INPUT, DOWN);
+                PIN_SLP(gpy5-6, INPUT, DOWN);
+                PIN_SLP(gpy5-7, INPUT, DOWN);
+
+                PIN_SLP(gpy6-0, INPUT, DOWN);
+                PIN_SLP(gpy6-1, INPUT, DOWN);
+                PIN_SLP(gpy6-2, INPUT, DOWN);
+                PIN_SLP(gpy6-3, INPUT, DOWN);
+                PIN_SLP(gpy6-4, INPUT, DOWN);
+                PIN_SLP(gpy6-5, INPUT, DOWN);
+                PIN_SLP(gpy6-6, INPUT, DOWN);
+                PIN_SLP(gpy6-7, INPUT, DOWN);
+        };
+};
+
+&pinctrl_2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&sleep2>;
+
+        sleep2: sleep-states {
+                PIN_SLP(gpz-0, INPUT, DOWN);
+                PIN_SLP(gpz-1, INPUT, DOWN);
+                PIN_SLP(gpz-2, INPUT, DOWN);
+                PIN_SLP(gpz-3, INPUT, DOWN);
+                PIN_SLP(gpz-4, INPUT, DOWN);
+                PIN_SLP(gpz-5, INPUT, DOWN);
+                PIN_SLP(gpz-6, INPUT, DOWN);
+        };
+};
+
+&pinctrl_3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&sleep3>;
+
+        sleep3: sleep-states {
+                PIN_SLP(gpv0-0, INPUT, DOWN);
+                PIN_SLP(gpv0-1, INPUT, DOWN);
+                PIN_SLP(gpv0-2, INPUT, DOWN);
+                PIN_SLP(gpv0-3, INPUT, DOWN);
+                PIN_SLP(gpv0-4, INPUT, DOWN);
+                PIN_SLP(gpv0-5, INPUT, DOWN);
+                PIN_SLP(gpv0-6, INPUT, DOWN);
+                PIN_SLP(gpv0-7, INPUT, DOWN);
+
+                PIN_SLP(gpv1-0, INPUT, DOWN);
+                PIN_SLP(gpv1-1, INPUT, DOWN);
+                PIN_SLP(gpv1-2, INPUT, DOWN);
+                PIN_SLP(gpv1-3, INPUT, DOWN);
+                PIN_SLP(gpv1-4, INPUT, DOWN);
+                PIN_SLP(gpv1-5, INPUT, DOWN);
+                PIN_SLP(gpv1-6, INPUT, DOWN);
+                PIN_SLP(gpv1-7, INPUT, DOWN);
+
+                PIN_SLP(gpv2-0, INPUT, DOWN);
+                PIN_SLP(gpv2-1, INPUT, DOWN);
+                PIN_SLP(gpv2-2, INPUT, DOWN);
+                PIN_SLP(gpv2-3, INPUT, DOWN);
+                PIN_SLP(gpv2-4, INPUT, DOWN);
+                PIN_SLP(gpv2-5, INPUT, DOWN);
+                PIN_SLP(gpv2-6, INPUT, DOWN);
+                PIN_SLP(gpv2-7, INPUT, DOWN);
+
+                PIN_SLP(gpv3-0, INPUT, DOWN);
+                PIN_SLP(gpv3-1, INPUT, DOWN);
+                PIN_SLP(gpv3-2, INPUT, DOWN);
+                PIN_SLP(gpv3-3, INPUT, DOWN);
+                PIN_SLP(gpv3-4, INPUT, DOWN);
+                PIN_SLP(gpv3-5, INPUT, DOWN);
+                PIN_SLP(gpv3-6, INPUT, DOWN);
+                PIN_SLP(gpv3-7, INPUT, DOWN);
+
+                PIN_SLP(gpv4-0, INPUT, DOWN);
+        };
+};
+
+&pwm {
+        pinctrl-0 = <&pwm0_out>;
+        pinctrl-names = "default";
+        samsung,pwm-outputs = <0>;
+        status = "okay";
+};
+
+&rtc {
+        status = "okay";
+        clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>;
+        clock-names = "rtc", "rtc_src";
+};
+
+&sdhci_2 {
+        bus-width = <4>;
+        cd-gpios = <&gpx3 4 GPIO_ACTIVE_HIGH>;
+        cd-inverted;
+        pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>;
+        pinctrl-names = "default";
+        vmmc-supply = <&ldo21_reg>;
+        status = "okay";
+};
+
+&sdhci_3 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        non-removable;
+        bus-width = <4>;
+
+        mmc-pwrseq = <&wlan_pwrseq>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>;
+        status = "okay";
+
+        brcmf: wifi@1 {
+                reg = <1>;
+                compatible = "brcm,bcm4329-fmac";
+                interrupt-parent = <&gpx2>;
+                interrupts = <5 IRQ_TYPE_NONE>;
+                interrupt-names = "host-wake";
+        };
+};
+
+&serial_0 {
+        status = "okay";
+};
+
+&serial_1 {
+        status = "okay";
+};
+
+&serial_2 {
+        status = "okay";
+};
+
+&serial_3 {
+        status = "okay";
+};
+
+&spi_1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&spi1_bus>;
+        cs-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>;
+        status = "okay";
+
+        s5c73m3_spi: s5c73m3@0 {
+                compatible = "samsung,s5c73m3";
+                spi-max-frequency = <50000000>;
+                reg = <0>;
+                controller-data {
+                        samsung,spi-feedback-delay = <2>;
+                };
+        };
+};
+
+&tmu {
+        vtmu-supply = <&ldo10_reg>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/exynos4412-n710x.dts b/arch/arm/boot/dts/exynos4412-n710x.dts
new file mode 100644
index 000000000000..eb402a0d6651
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-n710x.dts
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+#include "exynos4412-midas.dtsi"
+
+/ {
+        compatible = "samsung,n710x", "samsung,midas", "samsung,exynos4412", "samsung,exynos4";
+        model = "Samsung Galaxy Note 2 (GT-N7100, GT-N7105) based on Exynos4412";
+
+        memory@40000000 {
+                device_type = "memory";
+                reg =  <0x40000000 0x80000000>;
+        };
+
+        /* bootargs are passed in by bootloader */
+
+        regulators {
+                cam_vdda_reg: voltage-regulator-9 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "CAM_SENSOR_CORE_1.2V";
+                        regulator-min-microvolt = <1200000>;
+                        regulator-max-microvolt = <1200000>;
+                        gpio = <&gpm4 1 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                };
+        };
+};
+
+&buck9_reg {
+        maxim,ena-gpios = <&gpm1 0 GPIO_ACTIVE_HIGH>;
+};
+
+&cam_af_reg {
+        gpio = <&gpm1 1 GPIO_ACTIVE_HIGH>;
+        status = "okay";
+};
+
+&cam_io_reg {
+        gpio = <&gpm0 7 GPIO_ACTIVE_HIGH>;
+        status = "okay";
+};
+
+&i2c_3 {
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-slave-addr = <0x10>;
+        samsung,i2c-max-bus-freq = <400000>;
+        pinctrl-0 = <&i2c3_bus>;
+        pinctrl-names = "default";
+        status = "okay";
+
+        mms152-touchscreen@48 {
+                compatible = "melfas,mms152";
+                reg = <0x48>;
+                interrupt-parent = <&gpm2>;
+                interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+                x-size = <720>;
+                y-size = <1280>;
+                avdd-supply = <&ldo23_reg>;
+                vdd-supply = <&ldo24_reg>;
+        };
+};
+
+&ldo13_reg {
+        regulator-name = "VCC_1.8V_LCD";
+        regulator-always-on;
+};
+
+&ldo25_reg {
+        regulator-name = "VCI_3.0V_LCD";
+        regulator-min-microvolt = <3000000>;
+        regulator-max-microvolt = <3000000>;
+};
+
+&s5c73m3 {
+        standby-gpios = <&gpm0 6 GPIO_ACTIVE_LOW>;   /* ISP_STANDBY */
+        vdda-supply = <&cam_vdda_reg>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index 556ea78b8e32..d7ad07fd48f9 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -61,12 +61,6 @@
                 reset-gpios = <&gpk1 2 GPIO_ACTIVE_LOW>;
         };
 
-        camera {
-                status = "okay";
-                pinctrl-names = "default";
-                pinctrl-0 = <>;
-        };
-
         fixed-rate-clocks {
                 xxti {
                         compatible = "samsung,clock-xxti";
@@ -142,6 +136,12 @@
         status = "okay";
 };
 
+&camera {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <>;
+};
+
 &clock_audss {
         assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
                         <&clock_audss EXYNOS_MOUT_I2S>,
diff --git a/arch/arm/boot/dts/exynos4412-pinctrl.dtsi b/arch/arm/boot/dts/exynos4412-pinctrl.dtsi
index e8dd5f2d976f..d7d5fdc230d8 100644
--- a/arch/arm/boot/dts/exynos4412-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4412-pinctrl.dtsi
@@ -18,964 +18,962 @@
                 samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_ ##_pull>;       \
         }
 
-/ {
-        pinctrl_0: pinctrl@11400000 {
-                gpa0: gpa0 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
+&pinctrl_0 {
+        gpa0: gpa0 {
+                gpio-controller;
+                #gpio-cells = <2>;
 
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpa1: gpa1 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpb: gpb {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpc0: gpc0 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpc1: gpc1 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpd0: gpd0 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpd1: gpd1 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpf0: gpf0 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpf1: gpf1 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpf2: gpf2 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpf3: gpf3 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpj0: gpj0 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpj1: gpj1 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                uart0_data: uart0-data {
-                        samsung,pins = "gpa0-0", "gpa0-1";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                uart0_fctl: uart0-fctl {
-                        samsung,pins = "gpa0-2", "gpa0-3";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                uart1_data: uart1-data {
-                        samsung,pins = "gpa0-4", "gpa0-5";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                uart1_fctl: uart1-fctl {
-                        samsung,pins = "gpa0-6", "gpa0-7";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                i2c2_bus: i2c2-bus {
-                        samsung,pins = "gpa0-6", "gpa0-7";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                uart2_data: uart2-data {
-                        samsung,pins = "gpa1-0", "gpa1-1";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                uart2_fctl: uart2-fctl {
-                        samsung,pins = "gpa1-2", "gpa1-3";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                uart_audio_a: uart-audio-a {
-                        samsung,pins = "gpa1-0", "gpa1-1";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                i2c3_bus: i2c3-bus {
-                        samsung,pins = "gpa1-2", "gpa1-3";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                uart3_data: uart3-data {
-                        samsung,pins = "gpa1-4", "gpa1-5";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                uart_audio_b: uart-audio-b {
-                        samsung,pins = "gpa1-4", "gpa1-5";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                spi0_bus: spi0-bus {
-                        samsung,pins = "gpb-0", "gpb-2", "gpb-3";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                i2c4_bus: i2c4-bus {
-                        samsung,pins = "gpb-0", "gpb-1";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                spi1_bus: spi1-bus {
-                        samsung,pins = "gpb-4", "gpb-6", "gpb-7";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                i2c5_bus: i2c5-bus {
-                        samsung,pins = "gpb-2", "gpb-3";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                i2s1_bus: i2s1-bus {
-                        samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
-                                        "gpc0-4";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                pcm1_bus: pcm1-bus {
-                        samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
-                                        "gpc0-4";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                ac97_bus: ac97-bus {
-                        samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
-                                        "gpc0-4";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                i2s2_bus: i2s2-bus {
-                        samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
-                                        "gpc1-4";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                pcm2_bus: pcm2-bus {
-                        samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
-                                        "gpc1-4";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                spdif_bus: spdif-bus {
-                        samsung,pins = "gpc1-0", "gpc1-1";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                i2c6_bus: i2c6-bus {
-                        samsung,pins = "gpc1-3", "gpc1-4";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                spi2_bus: spi2-bus {
-                        samsung,pins = "gpc1-1", "gpc1-3", "gpc1-4";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_5>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                pwm0_out: pwm0-out {
-                        samsung,pins = "gpd0-0";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                pwm1_out: pwm1-out {
-                        samsung,pins = "gpd0-1";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                lcd_ctrl: lcd-ctrl {
-                        samsung,pins = "gpd0-0", "gpd0-1";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                i2c7_bus: i2c7-bus {
-                        samsung,pins = "gpd0-2", "gpd0-3";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                pwm2_out: pwm2-out {
-                        samsung,pins = "gpd0-2";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                pwm3_out: pwm3-out {
-                        samsung,pins = "gpd0-3";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                i2c0_bus: i2c0-bus {
-                        samsung,pins = "gpd1-0", "gpd1-1";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                mipi0_clk: mipi0-clk {
-                        samsung,pins = "gpd1-0", "gpd1-1";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                i2c1_bus: i2c1-bus {
-                        samsung,pins = "gpd1-2", "gpd1-3";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                mipi1_clk: mipi1-clk {
-                        samsung,pins = "gpd1-2", "gpd1-3";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                lcd_clk: lcd-clk {
-                        samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                lcd_data16: lcd-data-width16 {
-                        samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2",
-                                        "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0",
-                                        "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7",
-                                        "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                lcd_data18: lcd-data-width18 {
-                        samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1",
-                                        "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7",
-                                        "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
-                                        "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1",
-                                        "gpf3-2", "gpf3-3";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                lcd_data24: lcd-data-width24 {
-                        samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7",
-                                        "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3",
-                                        "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7",
-                                        "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
-                                        "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7",
-                                        "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                lcd_ldi: lcd-ldi {
-                        samsung,pins = "gpf3-4";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                cam_port_a_io: cam-port-a-io {
-                        samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3",
-                                        "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7",
-                                        "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                cam_port_a_clk_active: cam-port-a-clk-active {
-                        samsung,pins = "gpj1-3";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                cam_port_a_clk_idle: cam-port-a-clk-idle {
-                        samsung,pins = "gpj1-3";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-        };
-
-        pinctrl_1: pinctrl@11000000 {
-                gpk0: gpk0 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpk1: gpk1 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpk2: gpk2 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpk3: gpk3 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpl0: gpl0 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpl1: gpl1 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpl2: gpl2 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpm0: gpm0 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpm1: gpm1 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpm2: gpm2 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpm3: gpm3 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpm4: gpm4 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpy0: gpy0 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                };
-
-                gpy1: gpy1 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                };
-
-                gpy2: gpy2 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                };
-
-                gpy3: gpy3 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                };
-
-                gpy4: gpy4 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                };
-
-                gpy5: gpy5 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                };
-
-                gpy6: gpy6 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                };
-
-                gpx0: gpx0 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        interrupt-parent = <&gic>;
-                        interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
-                        #interrupt-cells = <2>;
-                };
-
-                gpx1: gpx1 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        interrupt-parent = <&gic>;
-                        interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
-                        #interrupt-cells = <2>;
-                };
-
-                gpx2: gpx2 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpx3: gpx3 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                sd0_clk: sd0-clk {
-                        samsung,pins = "gpk0-0";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd0_cmd: sd0-cmd {
-                        samsung,pins = "gpk0-1";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd0_cd: sd0-cd {
-                        samsung,pins = "gpk0-2";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd0_bus1: sd0-bus-width1 {
-                        samsung,pins = "gpk0-3";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd0_bus4: sd0-bus-width4 {
-                        samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd0_bus8: sd0-bus-width8 {
-                        samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd4_clk: sd4-clk {
-                        samsung,pins = "gpk0-0";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd4_cmd: sd4-cmd {
-                        samsung,pins = "gpk0-1";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd4_cd: sd4-cd {
-                        samsung,pins = "gpk0-2";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd4_bus1: sd4-bus-width1 {
-                        samsung,pins = "gpk0-3";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd4_bus4: sd4-bus-width4 {
-                        samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd4_bus8: sd4-bus-width8 {
-                        samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd1_clk: sd1-clk {
-                        samsung,pins = "gpk1-0";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd1_cmd: sd1-cmd {
-                        samsung,pins = "gpk1-1";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd1_cd: sd1-cd {
-                        samsung,pins = "gpk1-2";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd1_bus1: sd1-bus-width1 {
-                        samsung,pins = "gpk1-3";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd1_bus4: sd1-bus-width4 {
-                        samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd2_clk: sd2-clk {
-                        samsung,pins = "gpk2-0";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd2_cmd: sd2-cmd {
-                        samsung,pins = "gpk2-1";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd2_cd: sd2-cd {
-                        samsung,pins = "gpk2-2";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd2_bus1: sd2-bus-width1 {
-                        samsung,pins = "gpk2-3";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd2_bus4: sd2-bus-width4 {
-                        samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd2_bus8: sd2-bus-width8 {
-                        samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd3_clk: sd3-clk {
-                        samsung,pins = "gpk3-0";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd3_cmd: sd3-cmd {
-                        samsung,pins = "gpk3-1";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd3_cd: sd3-cd {
-                        samsung,pins = "gpk3-2";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd3_bus1: sd3-bus-width1 {
-                        samsung,pins = "gpk3-3";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                sd3_bus4: sd3-bus-width4 {
-                        samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                cam_port_b_io: cam-port-b-io {
-                        samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3",
-                                        "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7",
-                                        "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                cam_port_b_clk_active: cam-port-b-clk-active {
-                        samsung,pins = "gpm2-2";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
-                };
-
-                cam_port_b_clk_idle: cam-port-b-clk-idle {
-                        samsung,pins = "gpm2-2";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                eint0: ext-int0 {
-                        samsung,pins = "gpx0-0";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                eint8: ext-int8 {
-                        samsung,pins = "gpx1-0";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                eint15: ext-int15 {
-                        samsung,pins = "gpx1-7";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                eint16: ext-int16 {
-                        samsung,pins = "gpx2-0";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                eint31: ext-int31 {
-                        samsung,pins = "gpx3-7";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                fimc_is_i2c0: fimc-is-i2c0 {
-                        samsung,pins = "gpm4-0", "gpm4-1";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                fimc_is_i2c1: fimc-is-i2c1 {
-                        samsung,pins = "gpm4-2", "gpm4-3";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                fimc_is_uart: fimc-is-uart {
-                        samsung,pins = "gpm3-5", "gpm3-7";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                hdmi_cec: hdmi-cec {
-                        samsung,pins = "gpx3-6";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-        };
-
-        pinctrl_2: pinctrl@3860000 {
-                gpz: gpz {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                i2s0_bus: i2s0-bus {
-                        samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
-                                        "gpz-4", "gpz-5", "gpz-6";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-
-                pcm0_bus: pcm0-bus {
-                        samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
-                                        "gpz-4";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
-        };
-
-        pinctrl_3: pinctrl@106e0000 {
-                gpv0: gpv0 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpv1: gpv1 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpv2: gpv2 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpv3: gpv3 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                gpv4: gpv4 {
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                };
-
-                c2c_bus: c2c-bus {
-                        samsung,pins = "gpv0-0", "gpv0-1", "gpv0-2", "gpv0-3",
-                                        "gpv0-4", "gpv0-5", "gpv0-6", "gpv0-7",
-                                        "gpv1-0", "gpv1-1", "gpv1-2", "gpv1-3",
-                                        "gpv1-4", "gpv1-5", "gpv1-6", "gpv1-7",
-                                        "gpv2-0", "gpv2-1", "gpv2-2", "gpv2-3",
-                                        "gpv2-4", "gpv2-5", "gpv2-6", "gpv2-7",
-                                        "gpv3-0", "gpv3-1", "gpv3-2", "gpv3-3",
-                                        "gpv3-4", "gpv3-5", "gpv3-6", "gpv3-7",
-                                        "gpv4-0", "gpv4-1";
-                        samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                        samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-                        samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-                };
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpa1: gpa1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpb: gpb {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpc0: gpc0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpc1: gpc1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpd0: gpd0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpd1: gpd1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpf0: gpf0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpf1: gpf1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpf2: gpf2 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpf3: gpf3 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpj0: gpj0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpj1: gpj1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        uart0_data: uart0-data {
+                samsung,pins = "gpa0-0", "gpa0-1";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        uart0_fctl: uart0-fctl {
+                samsung,pins = "gpa0-2", "gpa0-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        uart1_data: uart1-data {
+                samsung,pins = "gpa0-4", "gpa0-5";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        uart1_fctl: uart1-fctl {
+                samsung,pins = "gpa0-6", "gpa0-7";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        i2c2_bus: i2c2-bus {
+                samsung,pins = "gpa0-6", "gpa0-7";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        uart2_data: uart2-data {
+                samsung,pins = "gpa1-0", "gpa1-1";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        uart2_fctl: uart2-fctl {
+                samsung,pins = "gpa1-2", "gpa1-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        uart_audio_a: uart-audio-a {
+                samsung,pins = "gpa1-0", "gpa1-1";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        i2c3_bus: i2c3-bus {
+                samsung,pins = "gpa1-2", "gpa1-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        uart3_data: uart3-data {
+                samsung,pins = "gpa1-4", "gpa1-5";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        uart_audio_b: uart-audio-b {
+                samsung,pins = "gpa1-4", "gpa1-5";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        spi0_bus: spi0-bus {
+                samsung,pins = "gpb-0", "gpb-2", "gpb-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        i2c4_bus: i2c4-bus {
+                samsung,pins = "gpb-0", "gpb-1";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        spi1_bus: spi1-bus {
+                samsung,pins = "gpb-4", "gpb-6", "gpb-7";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        i2c5_bus: i2c5-bus {
+                samsung,pins = "gpb-2", "gpb-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        i2s1_bus: i2s1-bus {
+                samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
+                                "gpc0-4";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        pcm1_bus: pcm1-bus {
+                samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
+                                "gpc0-4";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        ac97_bus: ac97-bus {
+                samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
+                                "gpc0-4";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        i2s2_bus: i2s2-bus {
+                samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
+                                "gpc1-4";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        pcm2_bus: pcm2-bus {
+                samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
+                                "gpc1-4";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        spdif_bus: spdif-bus {
+                samsung,pins = "gpc1-0", "gpc1-1";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        i2c6_bus: i2c6-bus {
+                samsung,pins = "gpc1-3", "gpc1-4";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        spi2_bus: spi2-bus {
+                samsung,pins = "gpc1-1", "gpc1-3", "gpc1-4";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_5>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        pwm0_out: pwm0-out {
+                samsung,pins = "gpd0-0";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        pwm1_out: pwm1-out {
+                samsung,pins = "gpd0-1";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        lcd_ctrl: lcd-ctrl {
+                samsung,pins = "gpd0-0", "gpd0-1";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        i2c7_bus: i2c7-bus {
+                samsung,pins = "gpd0-2", "gpd0-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        pwm2_out: pwm2-out {
+                samsung,pins = "gpd0-2";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        pwm3_out: pwm3-out {
+                samsung,pins = "gpd0-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        i2c0_bus: i2c0-bus {
+                samsung,pins = "gpd1-0", "gpd1-1";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        mipi0_clk: mipi0-clk {
+                samsung,pins = "gpd1-0", "gpd1-1";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        i2c1_bus: i2c1-bus {
+                samsung,pins = "gpd1-2", "gpd1-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        mipi1_clk: mipi1-clk {
+                samsung,pins = "gpd1-2", "gpd1-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        lcd_clk: lcd-clk {
+                samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        lcd_data16: lcd-data-width16 {
+                samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2",
+                                "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0",
+                                "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7",
+                                "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        lcd_data18: lcd-data-width18 {
+                samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1",
+                                "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7",
+                                "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
+                                "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1",
+                                "gpf3-2", "gpf3-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        lcd_data24: lcd-data-width24 {
+                samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7",
+                                "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3",
+                                "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7",
+                                "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
+                                "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7",
+                                "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        lcd_ldi: lcd-ldi {
+                samsung,pins = "gpf3-4";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        cam_port_a_io: cam-port-a-io {
+                samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3",
+                                "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7",
+                                "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        cam_port_a_clk_active: cam-port-a-clk-active {
+                samsung,pins = "gpj1-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        cam_port_a_clk_idle: cam-port-a-clk-idle {
+                samsung,pins = "gpj1-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+};
+
+&pinctrl_1 {
+        gpk0: gpk0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpk1: gpk1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpk2: gpk2 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpk3: gpk3 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpl0: gpl0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpl1: gpl1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpl2: gpl2 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpm0: gpm0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpm1: gpm1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpm2: gpm2 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpm3: gpm3 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpm4: gpm4 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpy0: gpy0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        gpy1: gpy1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        gpy2: gpy2 {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        gpy3: gpy3 {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        gpy4: gpy4 {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        gpy5: gpy5 {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        gpy6: gpy6 {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        gpx0: gpx0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                interrupt-parent = <&gic>;
+                interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+                #interrupt-cells = <2>;
+        };
+
+        gpx1: gpx1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                interrupt-parent = <&gic>;
+                interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+                #interrupt-cells = <2>;
+        };
+
+        gpx2: gpx2 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpx3: gpx3 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        sd0_clk: sd0-clk {
+                samsung,pins = "gpk0-0";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd0_cmd: sd0-cmd {
+                samsung,pins = "gpk0-1";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd0_cd: sd0-cd {
+                samsung,pins = "gpk0-2";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd0_bus1: sd0-bus-width1 {
+                samsung,pins = "gpk0-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd0_bus4: sd0-bus-width4 {
+                samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd0_bus8: sd0-bus-width8 {
+                samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd4_clk: sd4-clk {
+                samsung,pins = "gpk0-0";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd4_cmd: sd4-cmd {
+                samsung,pins = "gpk0-1";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd4_cd: sd4-cd {
+                samsung,pins = "gpk0-2";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd4_bus1: sd4-bus-width1 {
+                samsung,pins = "gpk0-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd4_bus4: sd4-bus-width4 {
+                samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd4_bus8: sd4-bus-width8 {
+                samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd1_clk: sd1-clk {
+                samsung,pins = "gpk1-0";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd1_cmd: sd1-cmd {
+                samsung,pins = "gpk1-1";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd1_cd: sd1-cd {
+                samsung,pins = "gpk1-2";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd1_bus1: sd1-bus-width1 {
+                samsung,pins = "gpk1-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd1_bus4: sd1-bus-width4 {
+                samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd2_clk: sd2-clk {
+                samsung,pins = "gpk2-0";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd2_cmd: sd2-cmd {
+                samsung,pins = "gpk2-1";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd2_cd: sd2-cd {
+                samsung,pins = "gpk2-2";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd2_bus1: sd2-bus-width1 {
+                samsung,pins = "gpk2-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd2_bus4: sd2-bus-width4 {
+                samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd2_bus8: sd2-bus-width8 {
+                samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd3_clk: sd3-clk {
+                samsung,pins = "gpk3-0";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd3_cmd: sd3-cmd {
+                samsung,pins = "gpk3-1";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd3_cd: sd3-cd {
+                samsung,pins = "gpk3-2";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd3_bus1: sd3-bus-width1 {
+                samsung,pins = "gpk3-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        sd3_bus4: sd3-bus-width4 {
+                samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        cam_port_b_io: cam-port-b-io {
+                samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3",
+                                "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7",
+                                "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        cam_port_b_clk_active: cam-port-b-clk-active {
+                samsung,pins = "gpm2-2";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
+        };
+
+        cam_port_b_clk_idle: cam-port-b-clk-idle {
+                samsung,pins = "gpm2-2";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        eint0: ext-int0 {
+                samsung,pins = "gpx0-0";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        eint8: ext-int8 {
+                samsung,pins = "gpx1-0";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        eint15: ext-int15 {
+                samsung,pins = "gpx1-7";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        eint16: ext-int16 {
+                samsung,pins = "gpx2-0";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        eint31: ext-int31 {
+                samsung,pins = "gpx3-7";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        fimc_is_i2c0: fimc-is-i2c0 {
+                samsung,pins = "gpm4-0", "gpm4-1";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        fimc_is_i2c1: fimc-is-i2c1 {
+                samsung,pins = "gpm4-2", "gpm4-3";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        fimc_is_uart: fimc-is-uart {
+                samsung,pins = "gpm3-5", "gpm3-7";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        hdmi_cec: hdmi-cec {
+                samsung,pins = "gpx3-6";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+};
+
+&pinctrl_2 {
+        gpz: gpz {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        i2s0_bus: i2s0-bus {
+                samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
+                                "gpz-4", "gpz-5", "gpz-6";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+
+        pcm0_bus: pcm0-bus {
+                samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
+                                "gpz-4";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+        };
+};
+
+&pinctrl_3 {
+        gpv0: gpv0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpv1: gpv1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpv2: gpv2 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpv3: gpv3 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpv4: gpv4 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        c2c_bus: c2c-bus {
+                samsung,pins = "gpv0-0", "gpv0-1", "gpv0-2", "gpv0-3",
+                                "gpv0-4", "gpv0-5", "gpv0-6", "gpv0-7",
+                                "gpv1-0", "gpv1-1", "gpv1-2", "gpv1-3",
+                                "gpv1-4", "gpv1-5", "gpv1-6", "gpv1-7",
+                                "gpv2-0", "gpv2-1", "gpv2-2", "gpv2-3",
+                                "gpv2-4", "gpv2-5", "gpv2-6", "gpv2-7",
+                                "gpv3-0", "gpv3-1", "gpv3-2", "gpv3-3",
+                                "gpv3-4", "gpv3-5", "gpv3-6", "gpv3-7",
+                                "gpv4-0", "gpv4-1";
+                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
         };
 };
diff --git a/arch/arm/boot/dts/exynos4412-tiny4412.dts b/arch/arm/boot/dts/exynos4412-tiny4412.dts
index 5504398e6e37..01f37b5ac9c4 100644
--- a/arch/arm/boot/dts/exynos4412-tiny4412.dts
+++ b/arch/arm/boot/dts/exynos4412-tiny4412.dts
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * FriendlyARM's Exynos4412 based TINY4412 board device tree source
  *
@@ -5,11 +6,7 @@
  *
  * Device tree source file for FriendlyARM's TINY4412 board which is based on
  * Samsung's Exynos4412 SoC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
+ */
 
 /dts-v1/;
 #include "exynos4412.dtsi"
diff --git a/arch/arm/boot/dts/exynos4412-tmu-sensor-conf.dtsi b/arch/arm/boot/dts/exynos4412-tmu-sensor-conf.dtsi
index e3f7934d19d0..489b58c619ee 100644
--- a/arch/arm/boot/dts/exynos4412-tmu-sensor-conf.dtsi
+++ b/arch/arm/boot/dts/exynos4412-tmu-sensor-conf.dtsi
@@ -1,12 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Device tree sources for Exynos4412 TMU sensor configuration
  *
  * Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
  */
 
 #include <dt-bindings/thermal/thermal_exynos.h>
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
index f285790e8e04..327ee980d3a5 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Samsung's Exynos4412 based Trats 2 board device tree source
  *
@@ -6,30 +7,14 @@
  *
  * Device tree source file for Samsung's Trats 2 board which is based on
  * Samsung's Exynos4412 SoC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
+ */
 
 /dts-v1/;
-#include "exynos4412.dtsi"
-#include "exynos4412-ppmu-common.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/clock/maxim,max77686.h>
-#include <dt-bindings/pinctrl/samsung.h>
+#include "exynos4412-galaxy-s3.dtsi"
 
 / {
         model = "Samsung Trats 2 based on Exynos4412";
-        compatible = "samsung,trats2", "samsung,exynos4412", "samsung,exynos4";
-
-        aliases {
-                i2c9 = &i2c_ak8975;
-                i2c10 = &i2c_cm36651;
-                i2c11 = &i2c_max77693;
-                i2c12 = &i2c_max77693_fuel;
-        };
+        compatible = "samsung,trats2", "samsung,midas", "samsung,exynos4412", "samsung,exynos4";
 
         memory@40000000 {
                 device_type = "memory";
@@ -38,1378 +23,5 @@
 
         chosen {
                 bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rootwait earlyprintk panic=5";
-                stdout-path = &serial_2;
-        };
-
-        firmware@204f000 {
-                compatible = "samsung,secure-firmware";
-                reg = <0x0204F000 0x1000>;
-        };
-
-        fixed-rate-clocks {
-                xxti {
-                        compatible = "samsung,clock-xxti", "fixed-clock";
-                        clock-frequency = <0>;
-                };
-
-                xusbxti {
-                        compatible = "samsung,clock-xusbxti", "fixed-clock";
-                        clock-frequency = <24000000>;
-                };
-        };
-
-        regulators {
-                compatible = "simple-bus";
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                cam_io_reg: voltage-regulator-1 {
-                        compatible = "regulator-fixed";
-                        regulator-name = "CAM_SENSOR_A";
-                        regulator-min-microvolt = <2800000>;
-                        regulator-max-microvolt = <2800000>;
-                        gpio = <&gpm0 2 GPIO_ACTIVE_HIGH>;
-                        enable-active-high;
-                };
-
-                lcd_vdd3_reg: voltage-regulator-2 {
-                        compatible = "regulator-fixed";
-                        regulator-name = "LCD_VDD_2.2V";
-                        regulator-min-microvolt = <2200000>;
-                        regulator-max-microvolt = <2200000>;
-                        gpio = <&gpc0 1 GPIO_ACTIVE_HIGH>;
-                        enable-active-high;
-                };
-
-                cam_af_reg: voltage-regulator-3 {
-                        compatible = "regulator-fixed";
-                        regulator-name = "CAM_AF";
-                        regulator-min-microvolt = <2800000>;
-                        regulator-max-microvolt = <2800000>;
-                        gpio = <&gpm0 4 GPIO_ACTIVE_HIGH>;
-                        enable-active-high;
-                };
-
-                ps_als_reg: voltage-regulator-5 {
-                        compatible = "regulator-fixed";
-                        regulator-name = "LED_A_3.0V";
-                        regulator-min-microvolt = <3000000>;
-                        regulator-max-microvolt = <3000000>;
-                        gpio = <&gpj0 5 GPIO_ACTIVE_HIGH>;
-                        enable-active-high;
-                };
-
-                vsil12: voltage-regulator-6 {
-                        compatible = "regulator-fixed";
-                        regulator-name = "VSIL_1.2V";
-                        regulator-min-microvolt = <1200000>;
-                        regulator-max-microvolt = <1200000>;
-                        gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>;
-                        enable-active-high;
-                        vin-supply = <&buck7_reg>;
-                };
-
-                vcc33mhl: voltage-regulator-7 {
-                        compatible = "regulator-fixed";
-                        regulator-name = "VCC_3.3_MHL";
-                        regulator-min-microvolt = <3300000>;
-                        regulator-max-microvolt = <3300000>;
-                        gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>;
-                        enable-active-high;
-                };
-
-                vcc18mhl: voltage-regulator-8 {
-                        compatible = "regulator-fixed";
-                        regulator-name = "VCC_1.8_MHL";
-                        regulator-min-microvolt = <1800000>;
-                        regulator-max-microvolt = <1800000>;
-                        gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>;
-                        enable-active-high;
-                };
-        };
-
-        gpio-keys {
-                compatible = "gpio-keys";
-
-                key-down {
-                        gpios = <&gpx3 3 GPIO_ACTIVE_LOW>;
-                        linux,code = <114>;
-                        label = "volume down";
-                        debounce-interval = <10>;
-                };
-
-                key-up {
-                        gpios = <&gpx2 2 GPIO_ACTIVE_LOW>;
-                        linux,code = <115>;
-                        label = "volume up";
-                        debounce-interval = <10>;
-                };
-
-                key-power {
-                        gpios = <&gpx2 7 GPIO_ACTIVE_LOW>;
-                        linux,code = <116>;
-                        label = "power";
-                        debounce-interval = <10>;
-                        wakeup-source;
-                };
-
-                key-ok {
-                        gpios = <&gpx0 1 GPIO_ACTIVE_LOW>;
-                        linux,code = <139>;
-                        label = "ok";
-                        debounce-inteval = <10>;
-                        wakeup-source;
-                };
-        };
-
-        i2c_max77693: i2c-gpio-1 {
-                compatible = "i2c-gpio";
-                gpios = <&gpm2 0 GPIO_ACTIVE_HIGH>, <&gpm2 1 GPIO_ACTIVE_HIGH>;
-                i2c-gpio,delay-us = <2>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                status = "okay";
-
-                max77693@66 {
-                        compatible = "maxim,max77693";
-                        interrupt-parent = <&gpx1>;
-                        interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
-                        reg = <0x66>;
-
-                        regulators {
-                                esafeout1_reg: ESAFEOUT1 {
-                                        regulator-name = "ESAFEOUT1";
-                                };
-                                esafeout2_reg: ESAFEOUT2 {
-                                        regulator-name = "ESAFEOUT2";
-                                };
-                                charger_reg: CHARGER {
-                                        regulator-name = "CHARGER";
-                                        regulator-min-microamp = <60000>;
-                                        regulator-max-microamp = <2580000>;
-                                };
-                        };
-
-                        max77693_haptic {
-                                compatible = "maxim,max77693-haptic";
-                                haptic-supply = <&ldo26_reg>;
-                                pwms = <&pwm 0 38022 0>;
-                        };
-
-                        charger {
-                                compatible = "maxim,max77693-charger";
-
-                                maxim,constant-microvolt = <4350000>;
-                                maxim,min-system-microvolt = <3600000>;
-                                maxim,thermal-regulation-celsius = <100>;
-                                maxim,battery-overcurrent-microamp = <3500000>;
-                                maxim,charge-input-threshold-microvolt = <4300000>;
-                        };
-                };
-        };
-
-        i2c_max77693_fuel: i2c-gpio-3 {
-                compatible = "i2c-gpio";
-                gpios = <&gpf1 5 GPIO_ACTIVE_HIGH>, <&gpf1 4 GPIO_ACTIVE_HIGH>;
-                i2c-gpio,delay-us = <2>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                status = "okay";
-
-                max77693-fuel-gauge@36 {
-                        compatible = "maxim,max17047";
-                        interrupt-parent = <&gpx2>;
-                        interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
-                        reg = <0x36>;
-
-                        maxim,over-heat-temp = <700>;
-                        maxim,over-volt = <4500>;
-                };
-        };
-
-        i2c_ak8975: i2c-gpio-0 {
-                compatible = "i2c-gpio";
-                gpios = <&gpy2 4 GPIO_ACTIVE_HIGH>, <&gpy2 5 GPIO_ACTIVE_HIGH>;
-                i2c-gpio,delay-us = <2>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                status = "okay";
-
-                ak8975@c {
-                        compatible = "asahi-kasei,ak8975";
-                        reg = <0x0c>;
-                        gpios = <&gpj0 7 GPIO_ACTIVE_HIGH>;
-                };
-        };
-
-        i2c_cm36651: i2c-gpio-2 {
-                compatible = "i2c-gpio";
-                gpios = <&gpf0 0 GPIO_ACTIVE_LOW>, <&gpf0 1 GPIO_ACTIVE_LOW>;
-                i2c-gpio,delay-us = <2>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                cm36651@18 {
-                        compatible = "capella,cm36651";
-                        reg = <0x18>;
-                        interrupt-parent = <&gpx0>;
-                        interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
-                        vled-supply = <&ps_als_reg>;
-                };
-        };
-
-        i2c-mhl {
-                compatible = "i2c-gpio";
-                gpios = <&gpf0 4 GPIO_ACTIVE_HIGH>, <&gpf0 6 GPIO_ACTIVE_HIGH>;
-                i2c-gpio,delay-us = <100>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                pinctrl-0 = <&i2c_mhl_bus>;
-                pinctrl-names = "default";
-                status = "okay";
-
-                sii9234: hdmi-bridge@39 {
-                        compatible = "sil,sii9234";
-                        avcc33-supply = <&vcc33mhl>;
-                        iovcc18-supply = <&vcc18mhl>;
-                        avcc12-supply = <&vsil12>;
-                        cvcc12-supply = <&vsil12>;
-                        reset-gpios = <&gpf3 4 GPIO_ACTIVE_LOW>;
-                        interrupt-parent = <&gpf3>;
-                        interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
-                        reg = <0x39>;
-
-                        port {
-                                mhl_to_hdmi: endpoint {
-                                        remote-endpoint = <&hdmi_to_mhl>;
-                                };
-                        };
-                };
-        };
-
-        camera: camera {
-                pinctrl-0 = <&cam_port_a_clk_active &cam_port_b_clk_active>;
-                pinctrl-names = "default";
-                status = "okay";
-                assigned-clocks = <&clock CLK_MOUT_CAM0>,
-                                  <&clock CLK_MOUT_CAM1>;
-                assigned-clock-parents = <&clock CLK_XUSBXTI>,
-                                         <&clock CLK_XUSBXTI>;
-
-
-        };
-
-        wlan_pwrseq: sdhci3-pwrseq {
-                compatible = "mmc-pwrseq-simple";
-                reset-gpios = <&gpj0 0 GPIO_ACTIVE_LOW>;
-                clocks = <&max77686 MAX77686_CLK_PMIC>;
-                clock-names = "ext_clock";
-        };
-
-        sound {
-                compatible = "samsung,trats2-audio";
-                samsung,i2s-controller = <&i2s0>;
-                samsung,model = "Trats2";
-                samsung,audio-codec = <&wm1811>;
-                samsung,audio-routing =
-                        "SPK", "SPKOUTLN",
-                        "SPK", "SPKOUTLP",
-                        "SPK", "SPKOUTRN",
-                        "SPK", "SPKOUTRP";
-        };
-
-        thermistor-ap {
-                compatible = "murata,ncp15wb473";
-                pullup-uv = <1800000>;   /* VCC_1.8V_AP */
-                pullup-ohm = <100000>;   /* 100K */
-                pulldown-ohm = <100000>; /* 100K */
-                io-channels = <&adc 1>;  /* AP temperature */
-        };
-
-        thermistor-battery {
-                compatible = "murata,ncp15wb473";
-                pullup-uv = <1800000>;   /* VCC_1.8V_AP */
-                pullup-ohm = <100000>;   /* 100K */
-                pulldown-ohm = <100000>; /* 100K */
-                io-channels = <&adc 2>;  /* Battery temperature */
-        };
-
-        thermal-zones {
-                cpu_thermal: cpu-thermal {
-                        cooling-maps {
-                                map0 {
-                                     /* Corresponds to 800MHz at freq_table */
-                                     cooling-device = <&cpu0 7 7>;
-                                };
-                                map1 {
-                                     /* Corresponds to 200MHz at freq_table */
-                                     cooling-device = <&cpu0 13 13>;
-                               };
-                       };
-                };
-        };
-};
-
-&adc {
-        vdd-supply = <&ldo3_reg>;
-        status = "okay";
-};
-
-&bus_dmc {
-        devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
-        vdd-supply = <&buck1_reg>;
-        status = "okay";
-};
-
-&bus_acp {
-        devfreq = <&bus_dmc>;
-        status = "okay";
-};
-
-&bus_c2c {
-        devfreq = <&bus_dmc>;
-        status = "okay";
-};
-
-&bus_leftbus {
-        devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
-        vdd-supply = <&buck3_reg>;
-        status = "okay";
-};
-
-&bus_rightbus {
-        devfreq = <&bus_leftbus>;
-        status = "okay";
-};
-
-&bus_display {
-        devfreq = <&bus_leftbus>;
-        status = "okay";
-};
-
-&bus_fsys {
-        devfreq = <&bus_leftbus>;
-        status = "okay";
-};
-
-&bus_peri {
-        devfreq = <&bus_leftbus>;
-        status = "okay";
-};
-
-&bus_mfc {
-        devfreq = <&bus_leftbus>;
-        status = "okay";
-};
-
-&cpu0 {
-        cpu0-supply = <&buck2_reg>;
-};
-
-&csis_0 {
-        status = "okay";
-        vddcore-supply = <&ldo8_reg>;
-        vddio-supply = <&ldo10_reg>;
-        assigned-clocks = <&clock CLK_MOUT_CSIS0>,
-                        <&clock CLK_SCLK_CSIS0>;
-        assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
-        assigned-clock-rates = <0>, <176000000>;
-
-        /* Camera C (3) MIPI CSI-2 (CSIS0) */
-        port@3 {
-                reg = <3>;
-                csis0_ep: endpoint {
-                        remote-endpoint = <&s5c73m3_ep>;
-                        data-lanes = <1 2 3 4>;
-                        samsung,csis-hs-settle = <12>;
-                };
-        };
-};
-
-&csis_1 {
-        status = "okay";
-        vddcore-supply = <&ldo8_reg>;
-        vddio-supply = <&ldo10_reg>;
-        assigned-clocks = <&clock CLK_MOUT_CSIS1>,
-                        <&clock CLK_SCLK_CSIS1>;
-        assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
-        assigned-clock-rates = <0>, <176000000>;
-
-        /* Camera D (4) MIPI CSI-2 (CSIS1) */
-        port@4 {
-                reg = <4>;
-                csis1_ep: endpoint {
-                        remote-endpoint = <&is_s5k6a3_ep>;
-                        data-lanes = <1>;
-                        samsung,csis-hs-settle = <18>;
-                        samsung,csis-wclk;
-                };
-        };
-};
-
-&dsi_0 {
-        vddcore-supply = <&ldo8_reg>;
-        vddio-supply = <&ldo10_reg>;
-        samsung,burst-clock-frequency = <500000000>;
-        samsung,esc-clock-frequency = <20000000>;
-        samsung,pll-clock-frequency = <24000000>;
-        status = "okay";
-
-        panel@0 {
-                compatible = "samsung,s6e8aa0";
-                reg = <0>;
-                vdd3-supply = <&lcd_vdd3_reg>;
-                vci-supply = <&ldo25_reg>;
-                reset-gpios = <&gpf2 1 GPIO_ACTIVE_HIGH>;
-                power-on-delay= <50>;
-                reset-delay = <100>;
-                init-delay = <100>;
-                flip-horizontal;
-                flip-vertical;
-                panel-width-mm = <58>;
-                panel-height-mm = <103>;
-
-                display-timings {
-                        timing-0 {
-                                clock-frequency = <57153600>;
-                                hactive = <720>;
-                                vactive = <1280>;
-                                hfront-porch = <5>;
-                                hback-porch = <5>;
-                                hsync-len = <5>;
-                                vfront-porch = <13>;
-                                vback-porch = <1>;
-                                vsync-len = <2>;
-                        };
-                };
-        };
-};
-
-&exynos_usbphy {
-        vbus-supply = <&esafeout1_reg>;
-        status = "okay";
-};
-
-&fimc_0 {
-        status = "okay";
-        assigned-clocks = <&clock CLK_MOUT_FIMC0>,
-                        <&clock CLK_SCLK_FIMC0>;
-        assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
-        assigned-clock-rates = <0>, <176000000>;
-};
-
-&fimc_1 {
-        status = "okay";
-        assigned-clocks = <&clock CLK_MOUT_FIMC1>,
-                        <&clock CLK_SCLK_FIMC1>;
-        assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
-        assigned-clock-rates = <0>, <176000000>;
-};
-
-&fimc_2 {
-        status = "okay";
-        assigned-clocks = <&clock CLK_MOUT_FIMC2>,
-                        <&clock CLK_SCLK_FIMC2>;
-        assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
-        assigned-clock-rates = <0>, <176000000>;
-};
-
-&fimc_3 {
-        status = "okay";
-        assigned-clocks = <&clock CLK_MOUT_FIMC3>,
-                        <&clock CLK_SCLK_FIMC3>;
-        assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
-        assigned-clock-rates = <0>, <176000000>;
-};
-
-&fimc_is {
-        pinctrl-0 = <&fimc_is_uart>;
-        pinctrl-names = "default";
-        status = "okay";
-
-        i2c1_isp: i2c-isp@12140000 {
-                pinctrl-0 = <&fimc_is_i2c1>;
-                pinctrl-names = "default";
-
-                s5k6a3@10 {
-                        compatible = "samsung,s5k6a3";
-                        reg = <0x10>;
-                        svdda-supply = <&cam_io_reg>;
-                        svddio-supply = <&ldo19_reg>;
-                        afvdd-supply = <&ldo19_reg>;
-                        clock-frequency = <24000000>;
-                        /* CAM_B_CLKOUT */
-                        clocks = <&camera 1>;
-                        clock-names = "extclk";
-                        samsung,camclk-out = <1>;
-                        gpios = <&gpm1 6 GPIO_ACTIVE_HIGH>;
-
-                        port {
-                                is_s5k6a3_ep: endpoint {
-                                        remote-endpoint = <&csis1_ep>;
-                                        data-lanes = <1>;
-                                };
-                        };
-                };
-        };
-};
-
-&fimc_lite_0 {
-        status = "okay";
-};
-
-&fimc_lite_1 {
-        status = "okay";
-};
-
-&fimd {
-        status = "okay";
-};
-
-&hdmi {
-        hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>;
-        pinctrl-names = "default";
-        pinctrl-0 = <&hdmi_hpd>;
-        vdd-supply = <&ldo3_reg>;
-        vdd_osc-supply = <&ldo4_reg>;
-        vdd_pll-supply = <&ldo3_reg>;
-        ddc = <&i2c_5>;
-        status = "okay";
-
-        ports {
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                port@1 {
-                        reg = <1>;
-                        hdmi_to_mhl: endpoint {
-                                remote-endpoint = <&mhl_to_hdmi>;
-                        };
-                };
-        };
-};
-
-&hsotg {
-        vusb_d-supply = <&ldo15_reg>;
-        vusb_a-supply = <&ldo12_reg>;
-        dr_mode = "peripheral";
-        status = "okay";
-};
-
-&i2c_0 {
-        samsung,i2c-sda-delay = <100>;
-        samsung,i2c-slave-addr = <0x10>;
-        samsung,i2c-max-bus-freq = <400000>;
-        pinctrl-0 = <&i2c0_bus>;
-        pinctrl-names = "default";
-        status = "okay";
-
-        s5c73m3@3c {
-                compatible = "samsung,s5c73m3";
-                reg = <0x3c>;
-                standby-gpios = <&gpm0 1 GPIO_ACTIVE_LOW>;   /* ISP_STANDBY */
-                xshutdown-gpios = <&gpf1 3 GPIO_ACTIVE_LOW>; /* ISP_RESET */
-                vdd-int-supply = <&buck9_reg>;
-                vddio-cis-supply = <&ldo9_reg>;
-                vdda-supply = <&ldo17_reg>;
-                vddio-host-supply = <&ldo18_reg>;
-                vdd-af-supply = <&cam_af_reg>;
-                vdd-reg-supply = <&cam_io_reg>;
-                clock-frequency = <24000000>;
-                /* CAM_A_CLKOUT */
-                clocks = <&camera 0>;
-                clock-names = "cis_extclk";
-                port {
-                        s5c73m3_ep: endpoint {
-                                remote-endpoint = <&csis0_ep>;
-                                data-lanes = <1 2 3 4>;
-                        };
-                };
-        };
-};
-
-&i2c_3 {
-        samsung,i2c-sda-delay = <100>;
-        samsung,i2c-slave-addr = <0x10>;
-        samsung,i2c-max-bus-freq = <400000>;
-        pinctrl-0 = <&i2c3_bus>;
-        pinctrl-names = "default";
-        status = "okay";
-
-        mms114-touchscreen@48 {
-                compatible = "melfas,mms114";
-                reg = <0x48>;
-                interrupt-parent = <&gpm2>;
-                interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
-                x-size = <720>;
-                y-size = <1280>;
-                avdd-supply = <&ldo23_reg>;
-                vdd-supply = <&ldo24_reg>;
-        };
-};
-
-&i2c_4 {
-        samsung,i2c-sda-delay = <100>;
-        samsung,i2c-slave-addr = <0x10>;
-        samsung,i2c-max-bus-freq = <100000>;
-        pinctrl-0 = <&i2c4_bus>;
-        pinctrl-names = "default";
-        status = "okay";
-
-        wm1811: wm1811@1a {
-                compatible = "wlf,wm1811";
-                reg = <0x1a>;
-                clocks = <&pmu_system_controller 0>;
-                clock-names = "MCLK1";
-                DCVDD-supply = <&ldo3_reg>;
-                DBVDD1-supply = <&ldo3_reg>;
-                wlf,ldo1ena = <&gpj0 4 0>;
         };
 };
-
-&i2c_5 {
-        status = "okay";
-};
-
-&i2c_7 {
-        samsung,i2c-sda-delay = <100>;
-        samsung,i2c-slave-addr = <0x10>;
-        samsung,i2c-max-bus-freq = <100000>;
-        pinctrl-0 = <&i2c7_bus>;
-        pinctrl-names = "default";
-        status = "okay";
-
-        max77686: max77686_pmic@9 {
-                compatible = "maxim,max77686";
-                interrupt-parent = <&gpx0>;
-                interrupts = <7 IRQ_TYPE_NONE>;
-                reg = <0x09>;
-                #clock-cells = <1>;
-
-                voltage-regulators {
-                        ldo1_reg: LDO1 {
-                                regulator-name = "VALIVE_1.0V_AP";
-                                regulator-min-microvolt = <1000000>;
-                                regulator-max-microvolt = <1000000>;
-                                regulator-always-on;
-                        };
-
-                        ldo2_reg: LDO2 {
-                                regulator-name = "VM1M2_1.2V_AP";
-                                regulator-min-microvolt = <1200000>;
-                                regulator-max-microvolt = <1200000>;
-                                regulator-always-on;
-                                regulator-state-mem {
-                                        regulator-on-in-suspend;
-                                };
-                        };
-
-                        ldo3_reg: LDO3 {
-                                regulator-name = "VCC_1.8V_AP";
-                                regulator-min-microvolt = <1800000>;
-                                regulator-max-microvolt = <1800000>;
-                                regulator-always-on;
-                        };
-
-                        ldo4_reg: LDO4 {
-                                regulator-name = "VCC_2.8V_AP";
-                                regulator-min-microvolt = <2800000>;
-                                regulator-max-microvolt = <2800000>;
-                                regulator-always-on;
-                        };
-
-                        ldo5_reg: LDO5 {
-                                regulator-name = "VCC_1.8V_IO";
-                                regulator-min-microvolt = <1800000>;
-                                regulator-max-microvolt = <1800000>;
-                                regulator-always-on;
-                        };
-
-                        ldo6_reg: LDO6 {
-                                regulator-name = "VMPLL_1.0V_AP";
-                                regulator-min-microvolt = <1000000>;
-                                regulator-max-microvolt = <1000000>;
-                                regulator-always-on;
-                                regulator-state-mem {
-                                        regulator-on-in-suspend;
-                                };
-                        };
-
-                        ldo7_reg: LDO7 {
-                                regulator-name = "VPLL_1.0V_AP";
-                                regulator-min-microvolt = <1000000>;
-                                regulator-max-microvolt = <1000000>;
-                                regulator-always-on;
-                                regulator-state-mem {
-                                        regulator-on-in-suspend;
-                                };
-                        };
-
-                        ldo8_reg: LDO8 {
-                                regulator-name = "VMIPI_1.0V";
-                                regulator-min-microvolt = <1000000>;
-                                regulator-max-microvolt = <1000000>;
-                                regulator-state-mem {
-                                        regulator-off-in-suspend;
-                                };
-                        };
-
-                        ldo9_reg: LDO9 {
-                                regulator-name = "CAM_ISP_MIPI_1.2V";
-                                regulator-min-microvolt = <1200000>;
-                                regulator-max-microvolt = <1200000>;
-                        };
-
-                        ldo10_reg: LDO10 {
-                                regulator-name = "VMIPI_1.8V";
-                                regulator-min-microvolt = <1800000>;
-                                regulator-max-microvolt = <1800000>;
-                                regulator-state-mem {
-                                        regulator-off-in-suspend;
-                                };
-                        };
-
-                        ldo11_reg: LDO11 {
-                                regulator-name = "VABB1_1.95V";
-                                regulator-min-microvolt = <1950000>;
-                                regulator-max-microvolt = <1950000>;
-                                regulator-always-on;
-                                regulator-state-mem {
-                                        regulator-off-in-suspend;
-                                };
-                        };
-
-                        ldo12_reg: LDO12 {
-                                regulator-name = "VUOTG_3.0V";
-                                regulator-min-microvolt = <3000000>;
-                                regulator-max-microvolt = <3000000>;
-                                regulator-state-mem {
-                                        regulator-off-in-suspend;
-                                };
-                        };
-
-                        ldo13_reg: LDO13 {
-                                regulator-name = "NFC_AVDD_1.8V";
-                                regulator-min-microvolt = <1800000>;
-                                regulator-max-microvolt = <1800000>;
-                        };
-
-                        ldo14_reg: LDO14 {
-                                regulator-name = "VABB2_1.95V";
-                                regulator-min-microvolt = <1950000>;
-                                regulator-max-microvolt = <1950000>;
-                                regulator-always-on;
-                                regulator-state-mem {
-                                        regulator-off-in-suspend;
-                                };
-                        };
-
-                        ldo15_reg: LDO15 {
-                                regulator-name = "VHSIC_1.0V";
-                                regulator-min-microvolt = <1000000>;
-                                regulator-max-microvolt = <1000000>;
-                                regulator-state-mem {
-                                        regulator-on-in-suspend;
-                                };
-                        };
-
-                        ldo16_reg: LDO16 {
-                                regulator-name = "VHSIC_1.8V";
-                                regulator-min-microvolt = <1800000>;
-                                regulator-max-microvolt = <1800000>;
-                                regulator-state-mem {
-                                        regulator-on-in-suspend;
-                                };
-                        };
-
-                        ldo17_reg: LDO17 {
-                                regulator-name = "CAM_SENSOR_CORE_1.2V";
-                                regulator-min-microvolt = <1200000>;
-                                regulator-max-microvolt = <1200000>;
-                        };
-
-                        ldo18_reg: LDO18 {
-                                regulator-name = "CAM_ISP_SEN_IO_1.8V";
-                                regulator-min-microvolt = <1800000>;
-                                regulator-max-microvolt = <1800000>;
-                        };
-
-                        ldo19_reg: LDO19 {
-                                regulator-name = "VT_CAM_1.8V";
-                                regulator-min-microvolt = <1800000>;
-                                regulator-max-microvolt = <1800000>;
-                        };
-
-                        ldo20_reg: LDO20 {
-                                regulator-name = "VDDQ_PRE_1.8V";
-                                regulator-min-microvolt = <1800000>;
-                                regulator-max-microvolt = <1800000>;
-                        };
-
-                        ldo21_reg: LDO21 {
-                                regulator-name = "VTF_2.8V";
-                                regulator-min-microvolt = <2800000>;
-                                regulator-max-microvolt = <2800000>;
-                                maxim,ena-gpios = <&gpy2 0 GPIO_ACTIVE_HIGH>;
-                        };
-
-                        ldo22_reg: LDO22 {
-                                regulator-name = "VMEM_VDD_2.8V";
-                                regulator-min-microvolt = <2800000>;
-                                regulator-max-microvolt = <2800000>;
-                                maxim,ena-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>;
-                        };
-
-                        ldo23_reg: LDO23 {
-                                regulator-name = "TSP_AVDD_3.3V";
-                                regulator-min-microvolt = <3300000>;
-                                regulator-max-microvolt = <3300000>;
-                        };
-
-                        ldo24_reg: LDO24 {
-                                regulator-name = "TSP_VDD_1.8V";
-                                regulator-min-microvolt = <1800000>;
-                                regulator-max-microvolt = <1800000>;
-                        };
-
-                        ldo25_reg: LDO25 {
-                                regulator-name = "LCD_VCC_3.3V";
-                                regulator-min-microvolt = <2800000>;
-                                regulator-max-microvolt = <2800000>;
-                        };
-
-                        ldo26_reg: LDO26 {
-                                regulator-name = "MOTOR_VCC_3.0V";
-                                regulator-min-microvolt = <3000000>;
-                                regulator-max-microvolt = <3000000>;
-                        };
-
-                        buck1_reg: BUCK1 {
-                                regulator-name = "vdd_mif";
-                                regulator-min-microvolt = <850000>;
-                                regulator-max-microvolt = <1100000>;
-                                regulator-always-on;
-                                regulator-boot-on;
-                                regulator-state-mem {
-                                        regulator-off-in-suspend;
-                                };
-                        };
-
-                        buck2_reg: BUCK2 {
-                                regulator-name = "vdd_arm";
-                                regulator-min-microvolt = <850000>;
-                                regulator-max-microvolt = <1500000>;
-                                regulator-always-on;
-                                regulator-boot-on;
-                                regulator-state-mem {
-                                        regulator-on-in-suspend;
-                                };
-                        };
-
-                        buck3_reg: BUCK3 {
-                                regulator-name = "vdd_int";
-                                regulator-min-microvolt = <850000>;
-                                regulator-max-microvolt = <1150000>;
-                                regulator-always-on;
-                                regulator-boot-on;
-                                regulator-state-mem {
-                                        regulator-off-in-suspend;
-                                };
-                        };
-
-                        buck4_reg: BUCK4 {
-                                regulator-name = "vdd_g3d";
-                                regulator-min-microvolt = <850000>;
-                                regulator-max-microvolt = <1150000>;
-                                regulator-boot-on;
-                                regulator-state-mem {
-                                        regulator-off-in-suspend;
-                                };
-                        };
-
-                        buck5_reg: BUCK5 {
-                                regulator-name = "VMEM_1.2V_AP";
-                                regulator-min-microvolt = <1200000>;
-                                regulator-max-microvolt = <1200000>;
-                                regulator-always-on;
-                        };
-
-                        buck6_reg: BUCK6 {
-                                regulator-name = "VCC_SUB_1.35V";
-                                regulator-min-microvolt = <1350000>;
-                                regulator-max-microvolt = <1350000>;
-                                regulator-always-on;
-                        };
-
-                        buck7_reg: BUCK7 {
-                                regulator-name = "VCC_SUB_2.0V";
-                                regulator-min-microvolt = <2000000>;
-                                regulator-max-microvolt = <2000000>;
-                                regulator-always-on;
-                        };
-
-                        buck8_reg: BUCK8 {
-                                regulator-name = "VMEM_VDDF_3.0V";
-                                regulator-min-microvolt = <2850000>;
-                                regulator-max-microvolt = <2850000>;
-                                maxim,ena-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>;
-                        };
-
-                        buck9_reg: BUCK9 {
-                                regulator-name = "CAM_ISP_CORE_1.2V";
-                                regulator-min-microvolt = <1000000>;
-                                regulator-max-microvolt = <1200000>;
-                                maxim,ena-gpios = <&gpm0 3 GPIO_ACTIVE_HIGH>;
-                        };
-                };
-        };
-};
-
-&i2c_8 {
-        status = "okay";
-};
-
-&i2s0 {
-        pinctrl-0 = <&i2s0_bus>;
-        pinctrl-names = "default";
-        status = "okay";
-};
-
-&mixer {
-        status = "okay";
-};
-
-&mshc_0 {
-        broken-cd;
-        non-removable;
-        card-detect-delay = <200>;
-        vmmc-supply = <&ldo22_reg>;
-        clock-frequency = <400000000>;
-        samsung,dw-mshc-ciu-div = <0>;
-        samsung,dw-mshc-sdr-timing = <2 3>;
-        samsung,dw-mshc-ddr-timing = <1 2>;
-        pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
-        pinctrl-names = "default";
-        status = "okay";
-        bus-width = <8>;
-        cap-mmc-highspeed;
-};
-
-&pmu_system_controller {
-        assigned-clocks = <&pmu_system_controller 0>;
-        assigned-clock-parents =  <&clock CLK_XUSBXTI>;
-};
-
-&pinctrl_0 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&sleep0>;
-
-        mhl_int: mhl-int {
-                samsung,pins = "gpf3-5";
-                samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
-        };
-
-        i2c_mhl_bus: i2c-mhl-bus {
-                samsung,pins = "gpf0-4", "gpf0-6";
-                samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
-                samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
-                samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
-        };
-
-        sleep0: sleep-states {
-                PIN_SLP(gpa0-0, INPUT, NONE);
-                PIN_SLP(gpa0-1, OUT0, NONE);
-                PIN_SLP(gpa0-2, INPUT, NONE);
-                PIN_SLP(gpa0-3, INPUT, UP);
-                PIN_SLP(gpa0-4, INPUT, NONE);
-                PIN_SLP(gpa0-5, INPUT, DOWN);
-                PIN_SLP(gpa0-6, INPUT, DOWN);
-                PIN_SLP(gpa0-7, INPUT, UP);
-
-                PIN_SLP(gpa1-0, INPUT, DOWN);
-                PIN_SLP(gpa1-1, INPUT, DOWN);
-                PIN_SLP(gpa1-2, INPUT, DOWN);
-                PIN_SLP(gpa1-3, INPUT, DOWN);
-                PIN_SLP(gpa1-4, INPUT, DOWN);
-                PIN_SLP(gpa1-5, INPUT, DOWN);
-
-                PIN_SLP(gpb-0, INPUT, NONE);
-                PIN_SLP(gpb-1, INPUT, NONE);
-                PIN_SLP(gpb-2, INPUT, NONE);
-                PIN_SLP(gpb-3, INPUT, NONE);
-                PIN_SLP(gpb-4, INPUT, DOWN);
-                PIN_SLP(gpb-5, INPUT, UP);
-                PIN_SLP(gpb-6, INPUT, DOWN);
-                PIN_SLP(gpb-7, INPUT, DOWN);
-
-                PIN_SLP(gpc0-0, INPUT, DOWN);
-                PIN_SLP(gpc0-1, INPUT, DOWN);
-                PIN_SLP(gpc0-2, INPUT, DOWN);
-                PIN_SLP(gpc0-3, INPUT, DOWN);
-                PIN_SLP(gpc0-4, INPUT, DOWN);
-
-                PIN_SLP(gpc1-0, INPUT, NONE);
-                PIN_SLP(gpc1-1, PREV, NONE);
-                PIN_SLP(gpc1-2, INPUT, NONE);
-                PIN_SLP(gpc1-3, INPUT, NONE);
-                PIN_SLP(gpc1-4, INPUT, NONE);
-
-                PIN_SLP(gpd0-0, INPUT, DOWN);
-                PIN_SLP(gpd0-1, INPUT, DOWN);
-                PIN_SLP(gpd0-2, INPUT, NONE);
-                PIN_SLP(gpd0-3, INPUT, NONE);
-
-                PIN_SLP(gpd1-0, INPUT, DOWN);
-                PIN_SLP(gpd1-1, INPUT, DOWN);
-                PIN_SLP(gpd1-2, INPUT, NONE);
-                PIN_SLP(gpd1-3, INPUT, NONE);
-
-                PIN_SLP(gpf0-0, INPUT, NONE);
-                PIN_SLP(gpf0-1, INPUT, NONE);
-                PIN_SLP(gpf0-2, INPUT, DOWN);
-                PIN_SLP(gpf0-3, INPUT, DOWN);
-                PIN_SLP(gpf0-4, INPUT, NONE);
-                PIN_SLP(gpf0-5, INPUT, DOWN);
-                PIN_SLP(gpf0-6, INPUT, NONE);
-                PIN_SLP(gpf0-7, INPUT, DOWN);
-
-                PIN_SLP(gpf1-0, INPUT, DOWN);
-                PIN_SLP(gpf1-1, INPUT, DOWN);
-                PIN_SLP(gpf1-2, INPUT, DOWN);
-                PIN_SLP(gpf1-3, INPUT, DOWN);
-                PIN_SLP(gpf1-4, INPUT, NONE);
-                PIN_SLP(gpf1-5, INPUT, NONE);
-                PIN_SLP(gpf1-6, INPUT, DOWN);
-                PIN_SLP(gpf1-7, PREV, NONE);
-
-                PIN_SLP(gpf2-0, PREV, NONE);
-                PIN_SLP(gpf2-1, INPUT, DOWN);
-                PIN_SLP(gpf2-2, INPUT, DOWN);
-                PIN_SLP(gpf2-3, INPUT, DOWN);
-                PIN_SLP(gpf2-4, INPUT, DOWN);
-                PIN_SLP(gpf2-5, INPUT, DOWN);
-                PIN_SLP(gpf2-6, INPUT, NONE);
-                PIN_SLP(gpf2-7, INPUT, NONE);
-
-                PIN_SLP(gpf3-0, INPUT, NONE);
-                PIN_SLP(gpf3-1, PREV, NONE);
-                PIN_SLP(gpf3-2, PREV, NONE);
-                PIN_SLP(gpf3-3, PREV, NONE);
-                PIN_SLP(gpf3-4, OUT1, NONE);
-                PIN_SLP(gpf3-5, INPUT, DOWN);
-
-                PIN_SLP(gpj0-0, PREV, NONE);
-                PIN_SLP(gpj0-1, PREV, NONE);
-                PIN_SLP(gpj0-2, PREV, NONE);
-                PIN_SLP(gpj0-3, INPUT, DOWN);
-                PIN_SLP(gpj0-4, PREV, NONE);
-                PIN_SLP(gpj0-5, PREV, NONE);
-                PIN_SLP(gpj0-6, INPUT, DOWN);
-                PIN_SLP(gpj0-7, INPUT, DOWN);
-
-                PIN_SLP(gpj1-0, INPUT, DOWN);
-                PIN_SLP(gpj1-1, PREV, NONE);
-                PIN_SLP(gpj1-2, PREV, NONE);
-                PIN_SLP(gpj1-3, INPUT, DOWN);
-                PIN_SLP(gpj1-4, INPUT, DOWN);
-        };
-};
-
-&pinctrl_1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&sleep1>;
-
-        hdmi_hpd: hdmi-hpd {
-                samsung,pins = "gpx3-7";
-                samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
-        };
-
-        sleep1: sleep-states {
-                PIN_SLP(gpk0-0, PREV, NONE);
-                PIN_SLP(gpk0-1, PREV, NONE);
-                PIN_SLP(gpk0-2, OUT0, NONE);
-                PIN_SLP(gpk0-3, PREV, NONE);
-                PIN_SLP(gpk0-4, PREV, NONE);
-                PIN_SLP(gpk0-5, PREV, NONE);
-                PIN_SLP(gpk0-6, PREV, NONE);
-
-                PIN_SLP(gpk1-0, INPUT, DOWN);
-                PIN_SLP(gpk1-1, INPUT, DOWN);
-                PIN_SLP(gpk1-2, INPUT, DOWN);
-                PIN_SLP(gpk1-3, PREV, NONE);
-                PIN_SLP(gpk1-4, PREV, NONE);
-                PIN_SLP(gpk1-5, PREV, NONE);
-                PIN_SLP(gpk1-6, PREV, NONE);
-
-                PIN_SLP(gpk2-0, INPUT, DOWN);
-                PIN_SLP(gpk2-1, INPUT, DOWN);
-                PIN_SLP(gpk2-2, INPUT, DOWN);
-                PIN_SLP(gpk2-3, INPUT, DOWN);
-                PIN_SLP(gpk2-4, INPUT, DOWN);
-                PIN_SLP(gpk2-5, INPUT, DOWN);
-                PIN_SLP(gpk2-6, INPUT, DOWN);
-
-                PIN_SLP(gpk3-0, OUT0, NONE);
-                PIN_SLP(gpk3-1, INPUT, NONE);
-                PIN_SLP(gpk3-2, INPUT, DOWN);
-                PIN_SLP(gpk3-3, INPUT, NONE);
-                PIN_SLP(gpk3-4, INPUT, NONE);
-                PIN_SLP(gpk3-5, INPUT, NONE);
-                PIN_SLP(gpk3-6, INPUT, NONE);
-
-                PIN_SLP(gpl0-0, INPUT, DOWN);
-                PIN_SLP(gpl0-1, INPUT, DOWN);
-                PIN_SLP(gpl0-2, INPUT, DOWN);
-                PIN_SLP(gpl0-3, INPUT, DOWN);
-                PIN_SLP(gpl0-4, PREV, NONE);
-                PIN_SLP(gpl0-6, PREV, NONE);
-
-                PIN_SLP(gpl1-0, INPUT, DOWN);
-                PIN_SLP(gpl1-1, INPUT, DOWN);
-                PIN_SLP(gpl2-0, INPUT, DOWN);
-                PIN_SLP(gpl2-1, INPUT, DOWN);
-                PIN_SLP(gpl2-2, INPUT, DOWN);
-                PIN_SLP(gpl2-3, INPUT, DOWN);
-                PIN_SLP(gpl2-4, INPUT, DOWN);
-                PIN_SLP(gpl2-5, INPUT, DOWN);
-                PIN_SLP(gpl2-6, PREV, NONE);
-                PIN_SLP(gpl2-7, INPUT, DOWN);
-
-                PIN_SLP(gpm0-0, INPUT, DOWN);
-                PIN_SLP(gpm0-1, INPUT, DOWN);
-                PIN_SLP(gpm0-2, INPUT, DOWN);
-                PIN_SLP(gpm0-3, INPUT, DOWN);
-                PIN_SLP(gpm0-4, INPUT, DOWN);
-                PIN_SLP(gpm0-5, INPUT, DOWN);
-                PIN_SLP(gpm0-6, INPUT, DOWN);
-                PIN_SLP(gpm0-7, INPUT, DOWN);
-
-                PIN_SLP(gpm1-0, INPUT, DOWN);
-                PIN_SLP(gpm1-1, INPUT, DOWN);
-                PIN_SLP(gpm1-2, INPUT, NONE);
-                PIN_SLP(gpm1-3, INPUT, NONE);
-                PIN_SLP(gpm1-4, INPUT, NONE);
-                PIN_SLP(gpm1-5, INPUT, NONE);
-                PIN_SLP(gpm1-6, INPUT, DOWN);
-
-                PIN_SLP(gpm2-0, INPUT, NONE);
-                PIN_SLP(gpm2-1, INPUT, NONE);
-                PIN_SLP(gpm2-2, INPUT, DOWN);
-                PIN_SLP(gpm2-3, INPUT, DOWN);
-                PIN_SLP(gpm2-4, INPUT, DOWN);
-
-                PIN_SLP(gpm3-0, PREV, NONE);
-                PIN_SLP(gpm3-1, PREV, NONE);
-                PIN_SLP(gpm3-2, PREV, NONE);
-                PIN_SLP(gpm3-3, OUT1, NONE);
-                PIN_SLP(gpm3-4, INPUT, DOWN);
-                PIN_SLP(gpm3-5, INPUT, DOWN);
-                PIN_SLP(gpm3-6, INPUT, DOWN);
-                PIN_SLP(gpm3-7, INPUT, DOWN);
-
-                PIN_SLP(gpm4-0, INPUT, DOWN);
-                PIN_SLP(gpm4-1, INPUT, DOWN);
-                PIN_SLP(gpm4-2, INPUT, DOWN);
-                PIN_SLP(gpm4-3, INPUT, DOWN);
-                PIN_SLP(gpm4-4, INPUT, DOWN);
-                PIN_SLP(gpm4-5, INPUT, DOWN);
-                PIN_SLP(gpm4-6, INPUT, DOWN);
-                PIN_SLP(gpm4-7, INPUT, DOWN);
-
-                PIN_SLP(gpy0-0, INPUT, DOWN);
-                PIN_SLP(gpy0-1, INPUT, DOWN);
-                PIN_SLP(gpy0-2, INPUT, DOWN);
-                PIN_SLP(gpy0-3, INPUT, DOWN);
-                PIN_SLP(gpy0-4, INPUT, DOWN);
-                PIN_SLP(gpy0-5, INPUT, DOWN);
-
-                PIN_SLP(gpy1-0, INPUT, DOWN);
-                PIN_SLP(gpy1-1, INPUT, DOWN);
-                PIN_SLP(gpy1-2, INPUT, DOWN);
-                PIN_SLP(gpy1-3, INPUT, DOWN);
-
-                PIN_SLP(gpy2-0, PREV, NONE);
-                PIN_SLP(gpy2-1, INPUT, DOWN);
-                PIN_SLP(gpy2-2, INPUT, NONE);
-                PIN_SLP(gpy2-3, INPUT, NONE);
-                PIN_SLP(gpy2-4, INPUT, NONE);
-                PIN_SLP(gpy2-5, INPUT, NONE);
-
-                PIN_SLP(gpy3-0, INPUT, DOWN);
-                PIN_SLP(gpy3-1, INPUT, DOWN);
-                PIN_SLP(gpy3-2, INPUT, DOWN);
-                PIN_SLP(gpy3-3, INPUT, DOWN);
-                PIN_SLP(gpy3-4, INPUT, DOWN);
-                PIN_SLP(gpy3-5, INPUT, DOWN);
-                PIN_SLP(gpy3-6, INPUT, DOWN);
-                PIN_SLP(gpy3-7, INPUT, DOWN);
-
-                PIN_SLP(gpy4-0, INPUT, DOWN);
-                PIN_SLP(gpy4-1, INPUT, DOWN);
-                PIN_SLP(gpy4-2, INPUT, DOWN);
-                PIN_SLP(gpy4-3, INPUT, DOWN);
-                PIN_SLP(gpy4-4, INPUT, DOWN);
-                PIN_SLP(gpy4-5, INPUT, DOWN);
-                PIN_SLP(gpy4-6, INPUT, DOWN);
-                PIN_SLP(gpy4-7, INPUT, DOWN);
-
-                PIN_SLP(gpy5-0, INPUT, DOWN);
-                PIN_SLP(gpy5-1, INPUT, DOWN);
-                PIN_SLP(gpy5-2, INPUT, DOWN);
-                PIN_SLP(gpy5-3, INPUT, DOWN);
-                PIN_SLP(gpy5-4, INPUT, DOWN);
-                PIN_SLP(gpy5-5, INPUT, DOWN);
-                PIN_SLP(gpy5-6, INPUT, DOWN);
-                PIN_SLP(gpy5-7, INPUT, DOWN);
-
-                PIN_SLP(gpy6-0, INPUT, DOWN);
-                PIN_SLP(gpy6-1, INPUT, DOWN);
-                PIN_SLP(gpy6-2, INPUT, DOWN);
-                PIN_SLP(gpy6-3, INPUT, DOWN);
-                PIN_SLP(gpy6-4, INPUT, DOWN);
-                PIN_SLP(gpy6-5, INPUT, DOWN);
-                PIN_SLP(gpy6-6, INPUT, DOWN);
-                PIN_SLP(gpy6-7, INPUT, DOWN);
-        };
-};
-
-&pinctrl_2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&sleep2>;
-
-        sleep2: sleep-states {
-                PIN_SLP(gpz-0, INPUT, DOWN);
-                PIN_SLP(gpz-1, INPUT, DOWN);
-                PIN_SLP(gpz-2, INPUT, DOWN);
-                PIN_SLP(gpz-3, INPUT, DOWN);
-                PIN_SLP(gpz-4, INPUT, DOWN);
-                PIN_SLP(gpz-5, INPUT, DOWN);
-                PIN_SLP(gpz-6, INPUT, DOWN);
-        };
-};
-
-&pinctrl_3 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&sleep3>;
-
-        sleep3: sleep-states {
-                PIN_SLP(gpv0-0, INPUT, DOWN);
-                PIN_SLP(gpv0-1, INPUT, DOWN);
-                PIN_SLP(gpv0-2, INPUT, DOWN);
-                PIN_SLP(gpv0-3, INPUT, DOWN);
-                PIN_SLP(gpv0-4, INPUT, DOWN);
-                PIN_SLP(gpv0-5, INPUT, DOWN);
-                PIN_SLP(gpv0-6, INPUT, DOWN);
-                PIN_SLP(gpv0-7, INPUT, DOWN);
-
-                PIN_SLP(gpv1-0, INPUT, DOWN);
-                PIN_SLP(gpv1-1, INPUT, DOWN);
-                PIN_SLP(gpv1-2, INPUT, DOWN);
-                PIN_SLP(gpv1-3, INPUT, DOWN);
-                PIN_SLP(gpv1-4, INPUT, DOWN);
-                PIN_SLP(gpv1-5, INPUT, DOWN);
-                PIN_SLP(gpv1-6, INPUT, DOWN);
-                PIN_SLP(gpv1-7, INPUT, DOWN);
-
-                PIN_SLP(gpv2-0, INPUT, DOWN);
-                PIN_SLP(gpv2-1, INPUT, DOWN);
-                PIN_SLP(gpv2-2, INPUT, DOWN);
-                PIN_SLP(gpv2-3, INPUT, DOWN);
-                PIN_SLP(gpv2-4, INPUT, DOWN);
-                PIN_SLP(gpv2-5, INPUT, DOWN);
-                PIN_SLP(gpv2-6, INPUT, DOWN);
-                PIN_SLP(gpv2-7, INPUT, DOWN);
-
-                PIN_SLP(gpv3-0, INPUT, DOWN);
-                PIN_SLP(gpv3-1, INPUT, DOWN);
-                PIN_SLP(gpv3-2, INPUT, DOWN);
-                PIN_SLP(gpv3-3, INPUT, DOWN);
-                PIN_SLP(gpv3-4, INPUT, DOWN);
-                PIN_SLP(gpv3-5, INPUT, DOWN);
-                PIN_SLP(gpv3-6, INPUT, DOWN);
-                PIN_SLP(gpv3-7, INPUT, DOWN);
-
-                PIN_SLP(gpv4-0, INPUT, DOWN);
-        };
-};
-
-&pwm {
-        pinctrl-0 = <&pwm0_out>;
-        pinctrl-names = "default";
-        samsung,pwm-outputs = <0>;
-        status = "okay";
-};
-
-&rtc {
-        status = "okay";
-        clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>;
-        clock-names = "rtc", "rtc_src";
-};
-
-&sdhci_2 {
-        bus-width = <4>;
-        cd-gpios = <&gpx3 4 GPIO_ACTIVE_HIGH>;
-        cd-inverted;
-        pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>;
-        pinctrl-names = "default";
-        vmmc-supply = <&ldo21_reg>;
-        status = "okay";
-};
-
-&sdhci_3 {
-        #address-cells = <1>;
-        #size-cells = <0>;
-        non-removable;
-        bus-width = <4>;
-
-        mmc-pwrseq = <&wlan_pwrseq>;
-        pinctrl-names = "default";
-        pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>;
-        status = "okay";
-
-        brcmf: wifi@1 {
-                reg = <1>;
-                compatible = "brcm,bcm4329-fmac";
-                interrupt-parent = <&gpx2>;
-                interrupts = <5 IRQ_TYPE_NONE>;
-                interrupt-names = "host-wake";
-        };
-};
-
-&serial_0 {
-        status = "okay";
-};
-
-&serial_1 {
-        status = "okay";
-};
-
-&serial_2 {
-        status = "okay";
-};
-
-&serial_3 {
-        status = "okay";
-};
-
-&spi_1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&spi1_bus>;
-        cs-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>;
-        status = "okay";
-
-        s5c73m3_spi: s5c73m3@0 {
-                compatible = "samsung,s5c73m3";
-                spi-max-frequency = <50000000>;
-                reg = <0>;
-                controller-data {
-                        samsung,spi-feedback-delay = <2>;
-                };
-        };
-};
-
-&tmu {
-        vtmu-supply = <&ldo10_reg>;
-        status = "okay";
-};
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index e4ad2fc0329e..2ae1ab602f4b 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -15,7 +15,7 @@
  */
 
 #include "exynos4.dtsi"
-#include "exynos4412-pinctrl.dtsi"
+
 #include "exynos4-cpu-thermal.dtsi"
 
 / {
@@ -42,8 +42,6 @@
                         clocks = <&clock CLK_ARM_CLK>;
                         clock-names = "cpu";
                         operating-points-v2 = <&cpu0_opp_table>;
-                        cooling-min-level = <13>;
-                        cooling-max-level = <7>;
                         #cooling-cells = <2>; /* min followed by max */
                 };
 
@@ -147,463 +145,410 @@
                 };
         };
 
-        sysram@2020000 {
-                compatible = "mmio-sram";
-                reg = <0x02020000 0x40000>;
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges = <0 0x02020000 0x40000>;
 
-                smp-sysram@0 {
-                        compatible = "samsung,exynos4210-sysram";
-                        reg = <0x0 0x1000>;
-                };
+        soc: soc {
 
-                smp-sysram@2f000 {
-                        compatible = "samsung,exynos4210-sysram-ns";
-                        reg = <0x2f000 0x1000>;
+                pinctrl_0: pinctrl@11400000 {
+                        compatible = "samsung,exynos4x12-pinctrl";
+                        reg = <0x11400000 0x1000>;
+                        interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
                 };
-        };
-
-        pd_isp: isp-power-domain@10023ca0 {
-                compatible = "samsung,exynos4210-pd";
-                reg = <0x10023CA0 0x20>;
-                #power-domain-cells = <0>;
-                label = "ISP";
-        };
-
-        l2c: l2-cache-controller@10502000 {
-                compatible = "arm,pl310-cache";
-                reg = <0x10502000 0x1000>;
-                cache-unified;
-                cache-level = <2>;
-                arm,tag-latency = <2 2 1>;
-                arm,data-latency = <3 2 1>;
-                arm,double-linefill = <1>;
-                arm,double-linefill-incr = <0>;
-                arm,double-linefill-wrap = <1>;
-                arm,prefetch-drop = <1>;
-                arm,prefetch-offset = <7>;
-        };
 
-        clock: clock-controller@10030000 {
-                compatible = "samsung,exynos4412-clock";
-                reg = <0x10030000 0x18000>;
-                #clock-cells = <1>;
-        };
-
-        isp_clock: clock-controller@10048000 {
-                compatible = "samsung,exynos4412-isp-clock";
-                reg = <0x10048000 0x1000>;
-                #clock-cells = <1>;
-                power-domains = <&pd_isp>;
-                clocks = <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>;
-                clock-names = "aclk200", "aclk400_mcuisp";
-        };
+                pinctrl_1: pinctrl@11000000 {
+                        compatible = "samsung,exynos4x12-pinctrl";
+                        reg = <0x11000000 0x1000>;
+                        interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 
-        mct@10050000 {
-                compatible = "samsung,exynos4412-mct";
-                reg = <0x10050000 0x800>;
-                interrupt-parent = <&mct_map>;
-                interrupts = <0>, <1>, <2>, <3>, <4>;
-                clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
-                clock-names = "fin_pll", "mct";
-
-                mct_map: mct-map {
-                        #interrupt-cells = <1>;
-                        #address-cells = <0>;
-                        #size-cells = <0>;
-                        interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
-                                        <1 &combiner 12 5>,
-                                        <2 &combiner 12 6>,
-                                        <3 &combiner 12 7>,
-                                        <4 &gic 1 12 IRQ_TYPE_LEVEL_HIGH>;
+                        wakup_eint: wakeup-interrupt-controller {
+                                compatible = "samsung,exynos4210-wakeup-eint";
+                                interrupt-parent = <&gic>;
+                                interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+                        };
                 };
-        };
-
-        watchdog: watchdog@10060000 {
-                compatible = "samsung,exynos5250-wdt";
-                reg = <0x10060000 0x100>;
-                interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_WDT>;
-                clock-names = "watchdog";
-                samsung,syscon-phandle = <&pmu_system_controller>;
-        };
-
-        adc: adc@126c0000 {
-                compatible = "samsung,exynos-adc-v1";
-                reg = <0x126C0000 0x100>;
-                interrupt-parent = <&combiner>;
-                interrupts = <10 3>;
-                clocks = <&clock CLK_TSADC>;
-                clock-names = "adc";
-                #io-channel-cells = <1>;
-                io-channel-ranges;
-                samsung,syscon-phandle = <&pmu_system_controller>;
-                status = "disabled";
-        };
-
-        g2d: g2d@10800000 {
-                compatible = "samsung,exynos4212-g2d";
-                reg = <0x10800000 0x1000>;
-                interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
-                clock-names = "sclk_fimg2d", "fimg2d";
-                iommus = <&sysmmu_g2d>;
-        };
-
-        camera {
-                clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
-                         <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
-                clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
 
-                /* fimc_[0-3] are configured outside, under phandles */
-                fimc_lite_0: fimc-lite@12390000 {
-                        compatible = "samsung,exynos4212-fimc-lite";
-                        reg = <0x12390000 0x1000>;
-                        interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
-                        power-domains = <&pd_isp>;
-                        clocks = <&isp_clock CLK_ISP_FIMC_LITE0>;
-                        clock-names = "flite";
-                        iommus = <&sysmmu_fimc_lite0>;
-                        status = "disabled";
+                pinctrl_2: pinctrl@3860000 {
+                        compatible = "samsung,exynos4x12-pinctrl";
+                        reg = <0x03860000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <10 0>;
                 };
 
-                fimc_lite_1: fimc-lite@123a0000 {
-                        compatible = "samsung,exynos4212-fimc-lite";
-                        reg = <0x123A0000 0x1000>;
-                        interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
-                        power-domains = <&pd_isp>;
-                        clocks = <&isp_clock CLK_ISP_FIMC_LITE1>;
-                        clock-names = "flite";
-                        iommus = <&sysmmu_fimc_lite1>;
-                        status = "disabled";
+                pinctrl_3: pinctrl@106e0000 {
+                        compatible = "samsung,exynos4x12-pinctrl";
+                        reg = <0x106E0000 0x1000>;
+                        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
                 };
 
-                fimc_is: fimc-is@12000000 {
-                        compatible = "samsung,exynos4212-fimc-is";
-                        reg = <0x12000000 0x260000>;
-                        interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
-                        power-domains = <&pd_isp>;
-                        clocks = <&isp_clock CLK_ISP_FIMC_LITE0>,
-                                 <&isp_clock CLK_ISP_FIMC_LITE1>,
-                                 <&isp_clock CLK_ISP_PPMUISPX>,
-                                 <&isp_clock CLK_ISP_PPMUISPMX>,
-                                 <&isp_clock CLK_ISP_FIMC_ISP>,
-                                 <&isp_clock CLK_ISP_FIMC_DRC>,
-                                 <&isp_clock CLK_ISP_FIMC_FD>,
-                                 <&isp_clock CLK_ISP_MCUISP>,
-                                 <&isp_clock CLK_ISP_GICISP>,
-                                 <&isp_clock CLK_ISP_MCUCTL_ISP>,
-                                 <&isp_clock CLK_ISP_PWM_ISP>,
-                                 <&isp_clock CLK_ISP_DIV_ISP0>,
-                                 <&isp_clock CLK_ISP_DIV_ISP1>,
-                                 <&isp_clock CLK_ISP_DIV_MCUISP0>,
-                                 <&isp_clock CLK_ISP_DIV_MCUISP1>,
-                                 <&clock CLK_MOUT_MPLL_USER_T>,
-                                 <&clock CLK_ACLK200>,
-                                 <&clock CLK_ACLK400_MCUISP>,
-                                 <&clock CLK_DIV_ACLK200>,
-                                 <&clock CLK_DIV_ACLK400_MCUISP>,
-                                 <&clock CLK_UART_ISP_SCLK>;
-                        clock-names = "lite0", "lite1", "ppmuispx",
-                                      "ppmuispmx", "isp",
-                                      "drc", "fd", "mcuisp",
-                                      "gicisp", "mcuctl_isp", "pwm_isp",
-                                      "ispdiv0", "ispdiv1", "mcuispdiv0",
-                                      "mcuispdiv1", "mpll", "aclk200",
-                                      "aclk400mcuisp", "div_aclk200",
-                                      "div_aclk400mcuisp", "uart";
-                        iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>,
-                                 <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>;
-                        iommu-names = "isp", "drc", "fd", "mcuctl";
+                sysram@2020000 {
+                        compatible = "mmio-sram";
+                        reg = <0x02020000 0x40000>;
                         #address-cells = <1>;
                         #size-cells = <1>;
-                        ranges;
-                        status = "disabled";
+                        ranges = <0 0x02020000 0x40000>;
 
-                        pmu@10020000 {
-                                reg = <0x10020000 0x3000>;
+                        smp-sysram@0 {
+                                compatible = "samsung,exynos4210-sysram";
+                                reg = <0x0 0x1000>;
                         };
 
-                        i2c1_isp: i2c-isp@12140000 {
-                                compatible = "samsung,exynos4212-i2c-isp";
-                                reg = <0x12140000 0x100>;
-                                clocks = <&isp_clock CLK_ISP_I2C1_ISP>;
-                                clock-names = "i2c_isp";
-                                #address-cells = <1>;
-                                #size-cells = <0>;
+                        smp-sysram@2f000 {
+                                compatible = "samsung,exynos4210-sysram-ns";
+                                reg = <0x2f000 0x1000>;
                         };
                 };
-        };
-
-        mshc_0: mmc@12550000 {
-                compatible = "samsung,exynos4412-dw-mshc";
-                reg = <0x12550000 0x1000>;
-                interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                fifo-depth = <0x80>;
-                clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
-                clock-names = "biu", "ciu";
-                status = "disabled";
-        };
-
-        sysmmu_g2d: sysmmu@10A40000{
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x10A40000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <4 7>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
-                #iommu-cells = <0>;
-        };
-
-        sysmmu_fimc_isp: sysmmu@12260000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x12260000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <16 2>;
-                power-domains = <&pd_isp>;
-                clock-names = "sysmmu";
-                clocks = <&isp_clock CLK_ISP_SMMU_ISP>;
-                #iommu-cells = <0>;
-        };
-
-        sysmmu_fimc_drc: sysmmu@12270000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x12270000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <16 3>;
-                power-domains = <&pd_isp>;
-                clock-names = "sysmmu";
-                clocks = <&isp_clock CLK_ISP_SMMU_DRC>;
-                #iommu-cells = <0>;
-        };
-
-        sysmmu_fimc_fd: sysmmu@122a0000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x122A0000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <16 4>;
-                power-domains = <&pd_isp>;
-                clock-names = "sysmmu";
-                clocks = <&isp_clock CLK_ISP_SMMU_FD>;
-                #iommu-cells = <0>;
-        };
-
-        sysmmu_fimc_mcuctl: sysmmu@122b0000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x122B0000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <16 5>;
-                power-domains = <&pd_isp>;
-                clock-names = "sysmmu";
-                clocks = <&isp_clock CLK_ISP_SMMU_ISPCX>;
-                #iommu-cells = <0>;
-        };
 
-        sysmmu_fimc_lite0: sysmmu@123b0000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x123B0000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <16 0>;
-                power-domains = <&pd_isp>;
-                clock-names = "sysmmu", "master";
-                clocks = <&isp_clock CLK_ISP_SMMU_LITE0>,
-                         <&isp_clock CLK_ISP_FIMC_LITE0>;
-                #iommu-cells = <0>;
-        };
+                pd_isp: isp-power-domain@10023ca0 {
+                        compatible = "samsung,exynos4210-pd";
+                        reg = <0x10023CA0 0x20>;
+                        #power-domain-cells = <0>;
+                        label = "ISP";
+                };
 
-        sysmmu_fimc_lite1: sysmmu@123c0000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x123C0000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <16 1>;
-                power-domains = <&pd_isp>;
-                clock-names = "sysmmu", "master";
-                clocks = <&isp_clock CLK_ISP_SMMU_LITE1>,
-                         <&isp_clock CLK_ISP_FIMC_LITE1>;
-                #iommu-cells = <0>;
-        };
+                l2c: l2-cache-controller@10502000 {
+                        compatible = "arm,pl310-cache";
+                        reg = <0x10502000 0x1000>;
+                        cache-unified;
+                        cache-level = <2>;
+                        arm,tag-latency = <2 2 1>;
+                        arm,data-latency = <3 2 1>;
+                        arm,double-linefill = <1>;
+                        arm,double-linefill-incr = <0>;
+                        arm,double-linefill-wrap = <1>;
+                        arm,prefetch-drop = <1>;
+                        arm,prefetch-offset = <7>;
+                };
 
-        bus_dmc: bus_dmc {
-                compatible = "samsung,exynos-bus";
-                clocks = <&clock CLK_DIV_DMC>;
-                clock-names = "bus";
-                operating-points-v2 = <&bus_dmc_opp_table>;
-                status = "disabled";
-        };
+                clock: clock-controller@10030000 {
+                        compatible = "samsung,exynos4412-clock";
+                        reg = <0x10030000 0x18000>;
+                        #clock-cells = <1>;
+                };
 
-        bus_acp: bus_acp {
-                compatible = "samsung,exynos-bus";
-                clocks = <&clock CLK_DIV_ACP>;
-                clock-names = "bus";
-                operating-points-v2 = <&bus_acp_opp_table>;
-                status = "disabled";
-        };
+                isp_clock: clock-controller@10048000 {
+                        compatible = "samsung,exynos4412-isp-clock";
+                        reg = <0x10048000 0x1000>;
+                        #clock-cells = <1>;
+                        power-domains = <&pd_isp>;
+                        clocks = <&clock CLK_ACLK200>,
+                                 <&clock CLK_ACLK400_MCUISP>;
+                        clock-names = "aclk200", "aclk400_mcuisp";
+                };
+
+                mct@10050000 {
+                        compatible = "samsung,exynos4412-mct";
+                        reg = <0x10050000 0x800>;
+                        interrupt-parent = <&mct_map>;
+                        interrupts = <0>, <1>, <2>, <3>, <4>;
+                        clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
+                        clock-names = "fin_pll", "mct";
+
+                        mct_map: mct-map {
+                                #interrupt-cells = <1>;
+                                #address-cells = <0>;
+                                #size-cells = <0>;
+                                interrupt-map =
+                                        <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
+                                        <1 &combiner 12 5>,
+                                        <2 &combiner 12 6>,
+                                        <3 &combiner 12 7>,
+                                        <4 &gic 1 12 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+                };
 
-        bus_c2c: bus_c2c {
-                compatible = "samsung,exynos-bus";
-                clocks = <&clock CLK_DIV_C2C>;
-                clock-names = "bus";
-                operating-points-v2 = <&bus_dmc_opp_table>;
-                status = "disabled";
-        };
+                watchdog: watchdog@10060000 {
+                        compatible = "samsung,exynos5250-wdt";
+                        reg = <0x10060000 0x100>;
+                        interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_WDT>;
+                        clock-names = "watchdog";
+                        samsung,syscon-phandle = <&pmu_system_controller>;
+                };
+
+                adc: adc@126c0000 {
+                        compatible = "samsung,exynos-adc-v1";
+                        reg = <0x126C0000 0x100>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <10 3>;
+                        clocks = <&clock CLK_TSADC>;
+                        clock-names = "adc";
+                        #io-channel-cells = <1>;
+                        io-channel-ranges;
+                        samsung,syscon-phandle = <&pmu_system_controller>;
+                        status = "disabled";
+                };
 
-        bus_dmc_opp_table: opp_table1 {
-                compatible = "operating-points-v2";
-                opp-shared;
+                g2d: g2d@10800000 {
+                        compatible = "samsung,exynos4212-g2d";
+                        reg = <0x10800000 0x1000>;
+                        interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
+                        clock-names = "sclk_fimg2d", "fimg2d";
+                        iommus = <&sysmmu_g2d>;
+                };
 
-                opp-100000000 {
-                        opp-hz = /bits/ 64 <100000000>;
-                        opp-microvolt = <900000>;
+                mshc_0: mmc@12550000 {
+                        compatible = "samsung,exynos4412-dw-mshc";
+                        reg = <0x12550000 0x1000>;
+                        interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        fifo-depth = <0x80>;
+                        clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
+                        clock-names = "biu", "ciu";
+                        status = "disabled";
                 };
-                opp-134000000 {
-                        opp-hz = /bits/ 64 <134000000>;
-                        opp-microvolt = <900000>;
+
+                sysmmu_g2d: sysmmu@10A40000{
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x10A40000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <4 7>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
+                        #iommu-cells = <0>;
                 };
-                opp-160000000 {
-                        opp-hz = /bits/ 64 <160000000>;
-                        opp-microvolt = <900000>;
+
+                sysmmu_fimc_isp: sysmmu@12260000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x12260000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <16 2>;
+                        power-domains = <&pd_isp>;
+                        clock-names = "sysmmu";
+                        clocks = <&isp_clock CLK_ISP_SMMU_ISP>;
+                        #iommu-cells = <0>;
                 };
-                opp-267000000 {
-                        opp-hz = /bits/ 64 <267000000>;
-                        opp-microvolt = <950000>;
+
+                sysmmu_fimc_drc: sysmmu@12270000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x12270000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <16 3>;
+                        power-domains = <&pd_isp>;
+                        clock-names = "sysmmu";
+                        clocks = <&isp_clock CLK_ISP_SMMU_DRC>;
+                        #iommu-cells = <0>;
                 };
-                opp-400000000 {
-                        opp-hz = /bits/ 64 <400000000>;
-                        opp-microvolt = <1050000>;
+
+                sysmmu_fimc_fd: sysmmu@122a0000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x122A0000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <16 4>;
+                        power-domains = <&pd_isp>;
+                        clock-names = "sysmmu";
+                        clocks = <&isp_clock CLK_ISP_SMMU_FD>;
+                        #iommu-cells = <0>;
                 };
-        };
 
-        bus_acp_opp_table: opp_table2 {
-                compatible = "operating-points-v2";
-                opp-shared;
+                sysmmu_fimc_mcuctl: sysmmu@122b0000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x122B0000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <16 5>;
+                        power-domains = <&pd_isp>;
+                        clock-names = "sysmmu";
+                        clocks = <&isp_clock CLK_ISP_SMMU_ISPCX>;
+                        #iommu-cells = <0>;
+                };
 
-                opp-100000000 {
-                        opp-hz = /bits/ 64 <100000000>;
+                sysmmu_fimc_lite0: sysmmu@123b0000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x123B0000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <16 0>;
+                        power-domains = <&pd_isp>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&isp_clock CLK_ISP_SMMU_LITE0>,
+                                 <&isp_clock CLK_ISP_FIMC_LITE0>;
+                        #iommu-cells = <0>;
                 };
-                opp-134000000 {
-                        opp-hz = /bits/ 64 <134000000>;
+
+                sysmmu_fimc_lite1: sysmmu@123c0000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x123C0000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <16 1>;
+                        power-domains = <&pd_isp>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&isp_clock CLK_ISP_SMMU_LITE1>,
+                                 <&isp_clock CLK_ISP_FIMC_LITE1>;
+                        #iommu-cells = <0>;
                 };
-                opp-160000000 {
-                        opp-hz = /bits/ 64 <160000000>;
+
+                bus_dmc: bus_dmc {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&clock CLK_DIV_DMC>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_dmc_opp_table>;
+                        status = "disabled";
                 };
-                opp-267000000 {
-                        opp-hz = /bits/ 64 <267000000>;
+
+                bus_acp: bus_acp {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&clock CLK_DIV_ACP>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_acp_opp_table>;
+                        status = "disabled";
                 };
-        };
 
-        bus_leftbus: bus_leftbus {
-                compatible = "samsung,exynos-bus";
-                clocks = <&clock CLK_DIV_GDL>;
-                clock-names = "bus";
-                operating-points-v2 = <&bus_leftbus_opp_table>;
-                status = "disabled";
-        };
+                bus_c2c: bus_c2c {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&clock CLK_DIV_C2C>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_dmc_opp_table>;
+                        status = "disabled";
+                };
 
-        bus_rightbus: bus_rightbus {
-                compatible = "samsung,exynos-bus";
-                clocks = <&clock CLK_DIV_GDR>;
-                clock-names = "bus";
-                operating-points-v2 = <&bus_leftbus_opp_table>;
-                status = "disabled";
-        };
+                bus_dmc_opp_table: opp_table1 {
+                        compatible = "operating-points-v2";
+                        opp-shared;
 
-        bus_display: bus_display {
-                compatible = "samsung,exynos-bus";
-                clocks = <&clock CLK_ACLK160>;
-                clock-names = "bus";
-                operating-points-v2 = <&bus_display_opp_table>;
-                status = "disabled";
-        };
+                        opp-100000000 {
+                                opp-hz = /bits/ 64 <100000000>;
+                                opp-microvolt = <900000>;
+                        };
+                        opp-134000000 {
+                                opp-hz = /bits/ 64 <134000000>;
+                                opp-microvolt = <900000>;
+                        };
+                        opp-160000000 {
+                                opp-hz = /bits/ 64 <160000000>;
+                                opp-microvolt = <900000>;
+                        };
+                        opp-267000000 {
+                                opp-hz = /bits/ 64 <267000000>;
+                                opp-microvolt = <950000>;
+                        };
+                        opp-400000000 {
+                                opp-hz = /bits/ 64 <400000000>;
+                                opp-microvolt = <1050000>;
+                        };
+                };
 
-        bus_fsys: bus_fsys {
-                compatible = "samsung,exynos-bus";
-                clocks = <&clock CLK_ACLK133>;
-                clock-names = "bus";
-                operating-points-v2 = <&bus_fsys_opp_table>;
-                status = "disabled";
-        };
+                bus_acp_opp_table: opp_table2 {
+                        compatible = "operating-points-v2";
+                        opp-shared;
 
-        bus_peri: bus_peri {
-                compatible = "samsung,exynos-bus";
-                clocks = <&clock CLK_ACLK100>;
-                clock-names = "bus";
-                operating-points-v2 = <&bus_peri_opp_table>;
-                status = "disabled";
-        };
+                        opp-100000000 {
+                                opp-hz = /bits/ 64 <100000000>;
+                        };
+                        opp-134000000 {
+                                opp-hz = /bits/ 64 <134000000>;
+                        };
+                        opp-160000000 {
+                                opp-hz = /bits/ 64 <160000000>;
+                        };
+                        opp-267000000 {
+                                opp-hz = /bits/ 64 <267000000>;
+                        };
+                };
 
-        bus_mfc: bus_mfc {
-                compatible = "samsung,exynos-bus";
-                clocks = <&clock CLK_SCLK_MFC>;
-                clock-names = "bus";
-                operating-points-v2 = <&bus_leftbus_opp_table>;
-                status = "disabled";
-        };
+                bus_leftbus: bus_leftbus {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&clock CLK_DIV_GDL>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_leftbus_opp_table>;
+                        status = "disabled";
+                };
 
-        bus_leftbus_opp_table: opp_table3 {
-                compatible = "operating-points-v2";
-                opp-shared;
+                bus_rightbus: bus_rightbus {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&clock CLK_DIV_GDR>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_leftbus_opp_table>;
+                        status = "disabled";
+                };
 
-                opp-100000000 {
-                        opp-hz = /bits/ 64 <100000000>;
-                        opp-microvolt = <900000>;
+                bus_display: bus_display {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&clock CLK_ACLK160>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_display_opp_table>;
+                        status = "disabled";
                 };
-                opp-134000000 {
-                        opp-hz = /bits/ 64 <134000000>;
-                        opp-microvolt = <925000>;
+
+                bus_fsys: bus_fsys {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&clock CLK_ACLK133>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_fsys_opp_table>;
+                        status = "disabled";
                 };
-                opp-160000000 {
-                        opp-hz = /bits/ 64 <160000000>;
-                        opp-microvolt = <950000>;
+
+                bus_peri: bus_peri {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&clock CLK_ACLK100>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_peri_opp_table>;
+                        status = "disabled";
                 };
-                opp-200000000 {
-                        opp-hz = /bits/ 64 <200000000>;
-                        opp-microvolt = <1000000>;
+
+                bus_mfc: bus_mfc {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&clock CLK_SCLK_MFC>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_leftbus_opp_table>;
+                        status = "disabled";
                 };
-        };
 
-        bus_display_opp_table: opp_table4 {
-                compatible = "operating-points-v2";
-                opp-shared;
+                bus_leftbus_opp_table: opp_table3 {
+                        compatible = "operating-points-v2";
+                        opp-shared;
 
-                opp-160000000 {
-                        opp-hz = /bits/ 64 <160000000>;
-                };
-                opp-200000000 {
-                        opp-hz = /bits/ 64 <200000000>;
+                        opp-100000000 {
+                                opp-hz = /bits/ 64 <100000000>;
+                                opp-microvolt = <900000>;
+                        };
+                        opp-134000000 {
+                                opp-hz = /bits/ 64 <134000000>;
+                                opp-microvolt = <925000>;
+                        };
+                        opp-160000000 {
+                                opp-hz = /bits/ 64 <160000000>;
+                                opp-microvolt = <950000>;
+                        };
+                        opp-200000000 {
+                                opp-hz = /bits/ 64 <200000000>;
+                                opp-microvolt = <1000000>;
+                        };
                 };
-        };
 
-        bus_fsys_opp_table: opp_table5 {
-                compatible = "operating-points-v2";
-                opp-shared;
+                bus_display_opp_table: opp_table4 {
+                        compatible = "operating-points-v2";
+                        opp-shared;
 
-                opp-100000000 {
-                        opp-hz = /bits/ 64 <100000000>;
-                };
-                opp-134000000 {
-                        opp-hz = /bits/ 64 <134000000>;
+                        opp-160000000 {
+                                opp-hz = /bits/ 64 <160000000>;
+                        };
+                        opp-200000000 {
+                                opp-hz = /bits/ 64 <200000000>;
+                        };
                 };
-        };
 
-        bus_peri_opp_table: opp_table6 {
-                compatible = "operating-points-v2";
-                opp-shared;
+                bus_fsys_opp_table: opp_table5 {
+                        compatible = "operating-points-v2";
+                        opp-shared;
 
-                opp-50000000 {
-                        opp-hz = /bits/ 64 <50000000>;
-                };
-                opp-100000000 {
-                        opp-hz = /bits/ 64 <100000000>;
+                        opp-100000000 {
+                                opp-hz = /bits/ 64 <100000000>;
+                        };
+                        opp-134000000 {
+                                opp-hz = /bits/ 64 <134000000>;
+                        };
                 };
-        };
 
-        pmu {
-                interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
+                bus_peri_opp_table: opp_table6 {
+                        compatible = "operating-points-v2";
+                        opp-shared;
+
+                        opp-50000000 {
+                                opp-hz = /bits/ 64 <50000000>;
+                        };
+                        opp-100000000 {
+                                opp-hz = /bits/ 64 <100000000>;
+                        };
+                };
         };
 };
 
@@ -631,6 +576,92 @@
                      <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 };
 
+&camera {
+        clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
+                 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
+        clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
+
+        /* fimc_[0-3] are configured outside, under phandles */
+        fimc_lite_0: fimc-lite@12390000 {
+                compatible = "samsung,exynos4212-fimc-lite";
+                reg = <0x12390000 0x1000>;
+                interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+                power-domains = <&pd_isp>;
+                clocks = <&isp_clock CLK_ISP_FIMC_LITE0>;
+                clock-names = "flite";
+                iommus = <&sysmmu_fimc_lite0>;
+                status = "disabled";
+        };
+
+        fimc_lite_1: fimc-lite@123a0000 {
+                compatible = "samsung,exynos4212-fimc-lite";
+                reg = <0x123A0000 0x1000>;
+                interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+                power-domains = <&pd_isp>;
+                clocks = <&isp_clock CLK_ISP_FIMC_LITE1>;
+                clock-names = "flite";
+                iommus = <&sysmmu_fimc_lite1>;
+                status = "disabled";
+        };
+
+        fimc_is: fimc-is@12000000 {
+                compatible = "samsung,exynos4212-fimc-is";
+                reg = <0x12000000 0x260000>;
+                interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+                power-domains = <&pd_isp>;
+                clocks = <&isp_clock CLK_ISP_FIMC_LITE0>,
+                         <&isp_clock CLK_ISP_FIMC_LITE1>,
+                         <&isp_clock CLK_ISP_PPMUISPX>,
+                         <&isp_clock CLK_ISP_PPMUISPMX>,
+                         <&isp_clock CLK_ISP_FIMC_ISP>,
+                         <&isp_clock CLK_ISP_FIMC_DRC>,
+                         <&isp_clock CLK_ISP_FIMC_FD>,
+                         <&isp_clock CLK_ISP_MCUISP>,
+                         <&isp_clock CLK_ISP_GICISP>,
+                         <&isp_clock CLK_ISP_MCUCTL_ISP>,
+                         <&isp_clock CLK_ISP_PWM_ISP>,
+                         <&isp_clock CLK_ISP_DIV_ISP0>,
+                         <&isp_clock CLK_ISP_DIV_ISP1>,
+                         <&isp_clock CLK_ISP_DIV_MCUISP0>,
+                         <&isp_clock CLK_ISP_DIV_MCUISP1>,
+                         <&clock CLK_MOUT_MPLL_USER_T>,
+                         <&clock CLK_ACLK200>,
+                         <&clock CLK_ACLK400_MCUISP>,
+                         <&clock CLK_DIV_ACLK200>,
+                         <&clock CLK_DIV_ACLK400_MCUISP>,
+                         <&clock CLK_UART_ISP_SCLK>;
+                clock-names = "lite0", "lite1", "ppmuispx",
+                              "ppmuispmx", "isp",
+                              "drc", "fd", "mcuisp",
+                              "gicisp", "mcuctl_isp", "pwm_isp",
+                              "ispdiv0", "ispdiv1", "mcuispdiv0",
+                              "mcuispdiv1", "mpll", "aclk200",
+                              "aclk400mcuisp", "div_aclk200",
+                              "div_aclk400mcuisp", "uart";
+                iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>,
+                         <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>;
+                iommu-names = "isp", "drc", "fd", "mcuctl";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                status = "disabled";
+
+                pmu@10020000 {
+                        reg = <0x10020000 0x3000>;
+                };
+
+                i2c1_isp: i2c-isp@12140000 {
+                        compatible = "samsung,exynos4212-i2c-isp";
+                        reg = <0x12140000 0x100>;
+                        clocks = <&isp_clock CLK_ISP_I2C1_ISP>;
+                        clock-names = "i2c_isp";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+        };
+};
+
 &exynos_usbphy {
         compatible = "samsung,exynos4x12-usb2-phy";
         samsung,sysreg-phandle = <&sys_reg>;
@@ -693,35 +724,8 @@
                  <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>;
 };
 
-&pinctrl_0 {
-        compatible = "samsung,exynos4x12-pinctrl";
-        reg = <0x11400000 0x1000>;
-        interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&pinctrl_1 {
-        compatible = "samsung,exynos4x12-pinctrl";
-        reg = <0x11000000 0x1000>;
-        interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
-
-        wakup_eint: wakeup-interrupt-controller {
-                compatible = "samsung,exynos4210-wakeup-eint";
-                interrupt-parent = <&gic>;
-                interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-        };
-};
-
-&pinctrl_2 {
-        compatible = "samsung,exynos4x12-pinctrl";
-        reg = <0x03860000 0x1000>;
-        interrupt-parent = <&combiner>;
-        interrupts = <10 0>;
-};
-
-&pinctrl_3 {
-        compatible = "samsung,exynos4x12-pinctrl";
-        reg = <0x106E0000 0x1000>;
-        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+&pmu {
+        interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
 };
 
 &pmu_system_controller {
@@ -743,3 +747,5 @@
         clock-names = "tmu_apbif";
         status = "disabled";
 };
+
+#include "exynos4412-pinctrl.dtsi"
diff --git a/arch/arm/boot/dts/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/exynos5250-snow-common.dtsi
index 59cf1b202849..fd9226d3b207 100644
--- a/arch/arm/boot/dts/exynos5250-snow-common.dtsi
+++ b/arch/arm/boot/dts/exynos5250-snow-common.dtsi
@@ -9,6 +9,7 @@
 #include <dt-bindings/clock/maxim,max77686.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/sound/samsung-i2s.h>
 #include "exynos5250.dtsi"
 
 / {
@@ -225,6 +226,16 @@
         };
 };
 
+&clock {
+        assigned-clocks = <&clock CLK_FOUT_EPLL>;
+        assigned-clock-rates = <49152000>;
+};
+
+&clock_audss {
+        assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>;
+        assigned-clock-parents = <&clock CLK_FOUT_EPLL>;
+};
+
 &cpu0 {
         cpu0-supply = <&buck2_reg>;
 };
@@ -513,6 +524,8 @@
 };
 
 &i2s0 {
+        assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>;
+        assigned-clock-parents = <&clock_audss EXYNOS_I2S_BUS>;
         status = "okay";
 };
 
@@ -649,6 +662,11 @@
         };
 };
 
+&pmu_system_controller {
+        assigned-clocks = <&pmu_system_controller 0>;
+        assigned-clock-parents = <&clock CLK_FIN_PLL>;
+};
+
 &rtc {
         status = "okay";
         clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>;
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index 4827cb506fa3..75fdc5e6d423 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -18,6 +18,14 @@
 
                 samsung,model = "Snow-I2S-MAX98095";
                 samsung,audio-codec = <&max98095>;
+
+                cpu {
+                        sound-dai = <&i2s0 0>;
+                };
+
+                codec {
+                        sound-dai = <&max98095 0>, <&hdmi>;
+                };
         };
 };
 
@@ -27,6 +35,9 @@
                 reg = <0x11>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&max98095_en>;
+                clocks = <&pmu_system_controller 0>;
+                clock-names = "mclk";
+                #sound-dai-cells = <1>;
         };
 };
 
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 56626d1a4235..45283a6c5eee 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -77,8 +77,6 @@
                                  300000  937500
                                  200000  925000
                         >;
-                        cooling-min-level = <15>;
-                        cooling-max-level = <9>;
                         #cooling-cells = <2>; /* min followed by max */
                 };
                 cpu@1 {
@@ -500,6 +498,8 @@
                         pinctrl-names = "default";
                         pinctrl-0 = <&i2s0_bus>;
                         power-domains = <&pd_mau>;
+                        #clock-cells = <1>;
+                        #sound-dai-cells = <1>;
                 };
 
                 i2s1: i2s@12d60000 {
@@ -514,6 +514,7 @@
                         pinctrl-names = "default";
                         pinctrl-0 = <&i2s1_bus>;
                         power-domains = <&pd_mau>;
+                        #sound-dai-cells = <1>;
                 };
 
                 i2s2: i2s@12d70000 {
@@ -528,6 +529,7 @@
                         pinctrl-names = "default";
                         pinctrl-0 = <&i2s2_bus>;
                         power-domains = <&pd_mau>;
+                        #sound-dai-cells = <1>;
                 };
 
                 usb_dwc3 {
@@ -655,7 +657,7 @@
                         power-domains = <&pd_gsc>;
                         clocks = <&clock CLK_GSCL0>;
                         clock-names = "gscl";
-                        iommu = <&sysmmu_gsc0>;
+                        iommus = <&sysmmu_gsc0>;
                 };
 
                 gsc_1:  gsc@13e10000 {
@@ -665,7 +667,7 @@
                         power-domains = <&pd_gsc>;
                         clocks = <&clock CLK_GSCL1>;
                         clock-names = "gscl";
-                        iommu = <&sysmmu_gsc1>;
+                        iommus = <&sysmmu_gsc1>;
                 };
 
                 gsc_2:  gsc@13e20000 {
@@ -675,7 +677,7 @@
                         power-domains = <&pd_gsc>;
                         clocks = <&clock CLK_GSCL2>;
                         clock-names = "gscl";
-                        iommu = <&sysmmu_gsc2>;
+                        iommus = <&sysmmu_gsc2>;
                 };
 
                 gsc_3:  gsc@13e30000 {
@@ -685,7 +687,7 @@
                         power-domains = <&pd_gsc>;
                         clocks = <&clock CLK_GSCL3>;
                         clock-names = "gscl";
-                        iommu = <&sysmmu_gsc3>;
+                        iommus = <&sysmmu_gsc3>;
                 };
 
                 hdmi: hdmi@14530000 {
@@ -700,6 +702,7 @@
                                         "sclk_hdmiphy", "mout_hdmi";
                         samsung,syscon-phandle = <&pmu_system_controller>;
                         phy = <&hdmiphy>;
+                        #sound-dai-cells = <0>;
                         status = "disabled";
                 };
 
diff --git a/arch/arm/boot/dts/exynos5260-xyref5260.dts b/arch/arm/boot/dts/exynos5260-xyref5260.dts
index 442eb0353f29..fa19c59b2fb6 100644
--- a/arch/arm/boot/dts/exynos5260-xyref5260.dts
+++ b/arch/arm/boot/dts/exynos5260-xyref5260.dts
@@ -65,7 +65,6 @@
 &mmc_0 {
         status = "okay";
         broken-cd;
-        bypass-smu;
         cap-mmc-highspeed;
         supports-hs200-mode; /* 200 MHz */
         card-detect-delay = <200>;
diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
index 1886aa00b2db..55509c690328 100644
--- a/arch/arm/boot/dts/exynos5410.dtsi
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -11,7 +11,6 @@
  */
 
 #include "exynos54xx.dtsi"
-#include "exynos-syscon-restart.dtsi"
 #include <dt-bindings/clock/exynos5410.h>
 #include <dt-bindings/clock/exynos-audss-clk.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -197,9 +196,9 @@
                         interrupt-parent = <&gic>;
                         ranges;
 
-                        pdma0: pdma@12680000 {
+                        pdma0: pdma@121a0000 {
                                 compatible = "arm,pl330", "arm,primecell";
-                                reg = <0x121A0000 0x1000>;
+                                reg = <0x121a0000 0x1000>;
                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&clock CLK_PDMA0>;
                                 clock-names = "apb_pclk";
@@ -208,9 +207,9 @@
                                 #dma-requests = <32>;
                         };
 
-                        pdma1: pdma@12690000 {
+                        pdma1: pdma@121b0000 {
                                 compatible = "arm,pl330", "arm,primecell";
-                                reg = <0x121B0000 0x1000>;
+                                reg = <0x121b0000 0x1000>;
                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
                                 clocks = <&clock CLK_PDMA1>;
                                 clock-names = "apb_pclk";
diff --git a/arch/arm/boot/dts/exynos5420-cpus.dtsi b/arch/arm/boot/dts/exynos5420-cpus.dtsi
index 123f0cef658d..a8e449471304 100644
--- a/arch/arm/boot/dts/exynos5420-cpus.dtsi
+++ b/arch/arm/boot/dts/exynos5420-cpus.dtsi
@@ -30,8 +30,6 @@
                         clock-frequency = <1800000000>;
                         cci-control-port = <&cci_control1>;
                         operating-points-v2 = <&cluster_a15_opp_table>;
-                        cooling-min-level = <0>;
-                        cooling-max-level = <11>;
                         #cooling-cells = <2>; /* min followed by max */
                         capacity-dmips-mhz = <1024>;
                 };
@@ -43,8 +41,6 @@
                         clock-frequency = <1800000000>;
                         cci-control-port = <&cci_control1>;
                         operating-points-v2 = <&cluster_a15_opp_table>;
-                        cooling-min-level = <0>;
-                        cooling-max-level = <11>;
                         #cooling-cells = <2>; /* min followed by max */
                         capacity-dmips-mhz = <1024>;
                 };
@@ -56,8 +52,6 @@
                         clock-frequency = <1800000000>;
                         cci-control-port = <&cci_control1>;
                         operating-points-v2 = <&cluster_a15_opp_table>;
-                        cooling-min-level = <0>;
-                        cooling-max-level = <11>;
                         #cooling-cells = <2>; /* min followed by max */
                         capacity-dmips-mhz = <1024>;
                 };
@@ -69,8 +63,6 @@
                         clock-frequency = <1800000000>;
                         cci-control-port = <&cci_control1>;
                         operating-points-v2 = <&cluster_a15_opp_table>;
-                        cooling-min-level = <0>;
-                        cooling-max-level = <11>;
                         #cooling-cells = <2>; /* min followed by max */
                         capacity-dmips-mhz = <1024>;
                 };
@@ -83,8 +75,6 @@
                         clock-frequency = <1000000000>;
                         cci-control-port = <&cci_control0>;
                         operating-points-v2 = <&cluster_a7_opp_table>;
-                        cooling-min-level = <0>;
-                        cooling-max-level = <7>;
                         #cooling-cells = <2>; /* min followed by max */
                         capacity-dmips-mhz = <539>;
                 };
@@ -96,8 +86,6 @@
                         clock-frequency = <1000000000>;
                         cci-control-port = <&cci_control0>;
                         operating-points-v2 = <&cluster_a7_opp_table>;
-                        cooling-min-level = <0>;
-                        cooling-max-level = <7>;
                         #cooling-cells = <2>; /* min followed by max */
                         capacity-dmips-mhz = <539>;
                 };
@@ -109,8 +97,6 @@
                         clock-frequency = <1000000000>;
                         cci-control-port = <&cci_control0>;
                         operating-points-v2 = <&cluster_a7_opp_table>;
-                        cooling-min-level = <0>;
-                        cooling-max-level = <7>;
                         #cooling-cells = <2>; /* min followed by max */
                         capacity-dmips-mhz = <539>;
                 };
@@ -122,8 +108,6 @@
                         clock-frequency = <1000000000>;
                         cci-control-port = <&cci_control0>;
                         operating-points-v2 = <&cluster_a7_opp_table>;
-                        cooling-min-level = <0>;
-                        cooling-max-level = <7>;
                         #cooling-cells = <2>; /* min followed by max */
                         capacity-dmips-mhz = <539>;
                 };
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 5a76ed77dda1..244f0091c21f 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -11,6 +11,7 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/clock/maxim,max77802.h>
 #include <dt-bindings/regulator/maxim,max77802.h>
+#include <dt-bindings/sound/samsung-i2s.h>
 #include "exynos5420.dtsi"
 #include "exynos5420-cpus.dtsi"
 
@@ -86,6 +87,14 @@
                 samsung,model = "Peach-Pit-I2S-MAX98090";
                 samsung,i2s-controller = <&i2s0>;
                 samsung,audio-codec = <&max98090>;
+
+                cpu {
+                        sound-dai = <&i2s0 0>;
+                };
+
+                codec {
+                        sound-dai = <&max98090>, <&hdmi>;
+                };
         };
 
         usb300_vbus_reg: regulator-usb300 {
@@ -142,6 +151,11 @@
         vdd-supply = <&ldo9_reg>;
 };
 
+&clock_audss {
+        assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>;
+        assigned-clock-parents = <&clock CLK_FOUT_EPLL>;
+};
+
 &cpu0 {
         cpu-supply = <&buck2_reg>;
 };
@@ -606,6 +620,7 @@
                 pinctrl-0 = <&max98090_irq>;
                 clocks = <&pmu_system_controller 0>;
                 clock-names = "mclk";
+                #sound-dai-cells = <0>;
         };
 
         light-sensor@44 {
@@ -690,6 +705,8 @@
 };
 
 &i2s0 {
+        assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>;
+        assigned-clock-parents = <&clock_audss EXYNOS_I2S_BUS>;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi
index c593809c7f08..7c130a00d1a8 100644
--- a/arch/arm/boot/dts/exynos5422-cpus.dtsi
+++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi
@@ -29,8 +29,6 @@
                         clock-frequency = <1000000000>;
                         cci-control-port = <&cci_control0>;
                         operating-points-v2 = <&cluster_a7_opp_table>;
-                        cooling-min-level = <0>;
-                        cooling-max-level = <11>;
                         #cooling-cells = <2>; /* min followed by max */
                         capacity-dmips-mhz = <539>;
                 };
@@ -42,8 +40,6 @@
                         clock-frequency = <1000000000>;
                         cci-control-port = <&cci_control0>;
                         operating-points-v2 = <&cluster_a7_opp_table>;
-                        cooling-min-level = <0>;
-                        cooling-max-level = <11>;
                         #cooling-cells = <2>; /* min followed by max */
                         capacity-dmips-mhz = <539>;
                 };
@@ -55,8 +51,6 @@
                         clock-frequency = <1000000000>;
                         cci-control-port = <&cci_control0>;
                         operating-points-v2 = <&cluster_a7_opp_table>;
-                        cooling-min-level = <0>;
-                        cooling-max-level = <11>;
                         #cooling-cells = <2>; /* min followed by max */
                         capacity-dmips-mhz = <539>;
                 };
@@ -68,8 +62,6 @@
                         clock-frequency = <1000000000>;
                         cci-control-port = <&cci_control0>;
                         operating-points-v2 = <&cluster_a7_opp_table>;
-                        cooling-min-level = <0>;
-                        cooling-max-level = <11>;
                         #cooling-cells = <2>; /* min followed by max */
                         capacity-dmips-mhz = <539>;
                 };
@@ -82,8 +74,6 @@
                         clock-frequency = <1800000000>;
                         cci-control-port = <&cci_control1>;
                         operating-points-v2 = <&cluster_a15_opp_table>;
-                        cooling-min-level = <0>;
-                        cooling-max-level = <15>;
                         #cooling-cells = <2>; /* min followed by max */
                         capacity-dmips-mhz = <1024>;
                 };
@@ -95,8 +85,6 @@
                         clock-frequency = <1800000000>;
                         cci-control-port = <&cci_control1>;
                         operating-points-v2 = <&cluster_a15_opp_table>;
-                        cooling-min-level = <0>;
-                        cooling-max-level = <15>;
                         #cooling-cells = <2>; /* min followed by max */
                         capacity-dmips-mhz = <1024>;
                 };
@@ -108,8 +96,6 @@
                         clock-frequency = <1800000000>;
                         cci-control-port = <&cci_control1>;
                         operating-points-v2 = <&cluster_a15_opp_table>;
-                        cooling-min-level = <0>;
-                        cooling-max-level = <15>;
                         #cooling-cells = <2>; /* min followed by max */
                         capacity-dmips-mhz = <1024>;
                 };
@@ -121,8 +107,6 @@
                         clock-frequency = <1800000000>;
                         cci-control-port = <&cci_control1>;
                         operating-points-v2 = <&cluster_a15_opp_table>;
-                        cooling-min-level = <0>;
-                        cooling-max-level = <15>;
                         #cooling-cells = <2>; /* min followed by max */
                         capacity-dmips-mhz = <1024>;
                 };
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index fce9e26b5930..f3abecc44657 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -26,24 +26,6 @@
                 tmuctrl2 = &tmuctrl_2;
         };
 
-        clock: clock-controller@160000 {
-                compatible = "samsung,exynos5440-clock";
-                reg = <0x160000 0x1000>;
-                #clock-cells = <1>;
-        };
-
-        gic: interrupt-controller@2e0000 {
-                compatible = "arm,cortex-a15-gic";
-                #interrupt-cells = <3>;
-                interrupt-controller;
-                reg =   <0x2E1000 0x1000>,
-                        <0x2E2000 0x2000>,
-                        <0x2E4000 0x2000>,
-                        <0x2E6000 0x2000>;
-                interrupts = <GIC_PPI 9
-                                (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-        };
-
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -70,182 +52,290 @@
                 };
         };
 
-        arm-pmu {
-                compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
-                interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
-        };
+        soc: soc {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
 
-        timer {
-                compatible = "arm,cortex-a15-timer",
-                             "arm,armv7-timer";
-                interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-                             <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-                             <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-                             <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
-                clock-frequency = <50000000>;
-        };
+                clock: clock-controller@160000 {
+                        compatible = "samsung,exynos5440-clock";
+                        reg = <0x160000 0x1000>;
+                        #clock-cells = <1>;
+                };
 
-        cpufreq@160000 {
-                compatible = "samsung,exynos5440-cpufreq";
-                reg = <0x160000 0x1000>;
-                interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
-                operating-points = <
-                                /* KHz    uV */
-                                1500000 1100000
-                                1400000 1075000
-                                1300000 1050000
-                                1200000 1025000
-                                1100000 1000000
-                                1000000 975000
-                                900000  950000
-                                800000  925000
-                >;
-        };
+                gic: interrupt-controller@2e0000 {
+                        compatible = "arm,cortex-a15-gic";
+                        #interrupt-cells = <3>;
+                        interrupt-controller;
+                        reg =   <0x2E1000 0x1000>,
+                                <0x2E2000 0x2000>,
+                                <0x2E4000 0x2000>,
+                                <0x2E6000 0x2000>;
+                        interrupts = <GIC_PPI 9
+                                        (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+                };
 
-        serial_0: serial@b0000 {
-                compatible = "samsung,exynos4210-uart";
-                reg = <0xB0000 0x1000>;
-                interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
-                clock-names = "uart", "clk_uart_baud0";
-        };
 
-        serial_1: serial@c0000 {
-                compatible = "samsung,exynos4210-uart";
-                reg = <0xC0000 0x1000>;
-                interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
-                clock-names = "uart", "clk_uart_baud0";
-        };
+                arm-pmu {
+                        compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
+                        interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+                };
 
-        spi_0: spi@d0000 {
-                compatible = "samsung,exynos5440-spi";
-                reg = <0xD0000 0x100>;
-                interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                samsung,spi-src-clk = <0>;
-                num-cs = <1>;
-                clocks = <&clock CLK_B_125>, <&clock CLK_SPI_BAUD>;
-                clock-names = "spi", "spi_busclk0";
-        };
+                timer {
+                        compatible = "arm,cortex-a15-timer",
+                                     "arm,armv7-timer";
+                        interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                                     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                                     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                                     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+                        clock-frequency = <50000000>;
+                };
 
-        pin_ctrl: pinctrl@e0000 {
-                compatible = "samsung,exynos5440-pinctrl";
-                reg = <0xE0000 0x1000>;
-                interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
-                interrupt-controller;
-                #interrupt-cells = <2>;
-                #gpio-cells = <2>;
+                cpufreq@160000 {
+                        compatible = "samsung,exynos5440-cpufreq";
+                        reg = <0x160000 0x1000>;
+                        interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+                        operating-points = <
+                                        /* KHz    uV */
+                                        1500000 1100000
+                                        1400000 1075000
+                                        1300000 1050000
+                                        1200000 1025000
+                                        1100000 1000000
+                                        1000000 975000
+                                        900000  950000
+                                        800000  925000
+                        >;
+                };
 
-                fan: fan {
-                        samsung,exynos5440-pin-function = <1>;
+                serial_0: serial@b0000 {
+                        compatible = "samsung,exynos4210-uart";
+                        reg = <0xB0000 0x1000>;
+                        interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
+                        clock-names = "uart", "clk_uart_baud0";
                 };
 
-                hdd_led0: hdd_led0 {
-                        samsung,exynos5440-pin-function = <2>;
+                serial_1: serial@c0000 {
+                        compatible = "samsung,exynos4210-uart";
+                        reg = <0xC0000 0x1000>;
+                        interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
+                        clock-names = "uart", "clk_uart_baud0";
                 };
 
-                hdd_led1: hdd_led1 {
-                        samsung,exynos5440-pin-function = <3>;
+                spi_0: spi@d0000 {
+                        compatible = "samsung,exynos5440-spi";
+                        reg = <0xD0000 0x100>;
+                        interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        samsung,spi-src-clk = <0>;
+                        num-cs = <1>;
+                        clocks = <&clock CLK_B_125>, <&clock CLK_SPI_BAUD>;
+                        clock-names = "spi", "spi_busclk0";
                 };
 
-                uart1: uart1 {
-                        samsung,exynos5440-pin-function = <4>;
+                pin_ctrl: pinctrl@e0000 {
+                        compatible = "samsung,exynos5440-pinctrl";
+                        reg = <0xE0000 0x1000>;
+                        interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        #gpio-cells = <2>;
+
+                        fan: fan {
+                                samsung,exynos5440-pin-function = <1>;
+                        };
+
+                        hdd_led0: hdd_led0 {
+                                samsung,exynos5440-pin-function = <2>;
+                        };
+
+                        hdd_led1: hdd_led1 {
+                                samsung,exynos5440-pin-function = <3>;
+                        };
+
+                        uart1: uart1 {
+                                samsung,exynos5440-pin-function = <4>;
+                        };
                 };
-        };
 
-        i2c@f0000 {
-                compatible = "samsung,exynos5440-i2c";
-                reg = <0xF0000 0x1000>;
-                interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                clocks = <&clock CLK_B_125>;
-                clock-names = "i2c";
-        };
+                i2c@f0000 {
+                        compatible = "samsung,exynos5440-i2c";
+                        reg = <0xF0000 0x1000>;
+                        interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&clock CLK_B_125>;
+                        clock-names = "i2c";
+                };
 
-        i2c@100000 {
-                compatible = "samsung,exynos5440-i2c";
-                reg = <0x100000 0x1000>;
-                interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                clocks = <&clock CLK_B_125>;
-                clock-names = "i2c";
-        };
+                i2c@100000 {
+                        compatible = "samsung,exynos5440-i2c";
+                        reg = <0x100000 0x1000>;
+                        interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&clock CLK_B_125>;
+                        clock-names = "i2c";
+                };
 
-        watchdog@110000 {
-                compatible = "samsung,s3c6410-wdt";
-                reg = <0x110000 0x1000>;
-                interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_B_125>;
-                clock-names = "watchdog";
-        };
+                watchdog@110000 {
+                        compatible = "samsung,s3c6410-wdt";
+                        reg = <0x110000 0x1000>;
+                        interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_B_125>;
+                        clock-names = "watchdog";
+                };
 
-        gmac: ethernet@230000 {
-                compatible = "snps,dwmac-3.70a", "snps,dwmac";
-                reg = <0x00230000 0x8000>;
-                interrupt-parent = <&gic>;
-                interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
-                interrupt-names = "macirq";
-                phy-mode = "sgmii";
-                clocks = <&clock CLK_GMAC0>;
-                clock-names = "stmmaceth";
-        };
+                gmac: ethernet@230000 {
+                        compatible = "snps,dwmac-3.70a", "snps,dwmac";
+                        reg = <0x00230000 0x8000>;
+                        interrupt-parent = <&gic>;
+                        interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "macirq";
+                        phy-mode = "sgmii";
+                        clocks = <&clock CLK_GMAC0>;
+                        clock-names = "stmmaceth";
+                };
 
-        amba {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                compatible = "simple-bus";
-                interrupt-parent = <&gic>;
-                ranges;
-        };
+                amba {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "simple-bus";
+                        interrupt-parent = <&gic>;
+                        ranges;
+                };
 
-        rtc@130000 {
-                compatible = "samsung,s3c6410-rtc";
-                reg = <0x130000 0x1000>;
-                interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_B_125>;
-                clock-names = "rtc";
-        };
+                rtc@130000 {
+                        compatible = "samsung,s3c6410-rtc";
+                        reg = <0x130000 0x1000>;
+                        interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_B_125>;
+                        clock-names = "rtc";
+                };
 
-        tmuctrl_0: tmuctrl@160118 {
-                compatible = "samsung,exynos5440-tmu";
-                reg = <0x160118 0x230>, <0x160368 0x10>;
-                interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_B_125>;
-                clock-names = "tmu_apbif";
-                #include "exynos5440-tmu-sensor-conf.dtsi"
-        };
+                tmuctrl_0: tmuctrl@160118 {
+                        compatible = "samsung,exynos5440-tmu";
+                        reg = <0x160118 0x230>, <0x160368 0x10>;
+                        interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_B_125>;
+                        clock-names = "tmu_apbif";
+                        #include "exynos5440-tmu-sensor-conf.dtsi"
+                };
 
-        tmuctrl_1: tmuctrl@16011c {
-                compatible = "samsung,exynos5440-tmu";
-                reg = <0x16011C 0x230>, <0x160368 0x10>;
-                interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_B_125>;
-                clock-names = "tmu_apbif";
-                #include "exynos5440-tmu-sensor-conf.dtsi"
-        };
+                tmuctrl_1: tmuctrl@16011c {
+                        compatible = "samsung,exynos5440-tmu";
+                        reg = <0x16011C 0x230>, <0x160368 0x10>;
+                        interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_B_125>;
+                        clock-names = "tmu_apbif";
+                        #include "exynos5440-tmu-sensor-conf.dtsi"
+                };
+
+                tmuctrl_2: tmuctrl@160120 {
+                        compatible = "samsung,exynos5440-tmu";
+                        reg = <0x160120 0x230>, <0x160368 0x10>;
+                        interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_B_125>;
+                        clock-names = "tmu_apbif";
+                        #include "exynos5440-tmu-sensor-conf.dtsi"
+                };
 
-        tmuctrl_2: tmuctrl@160120 {
-                compatible = "samsung,exynos5440-tmu";
-                reg = <0x160120 0x230>, <0x160368 0x10>;
-                interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_B_125>;
-                clock-names = "tmu_apbif";
-                #include "exynos5440-tmu-sensor-conf.dtsi"
+                sata@210000 {
+                        compatible = "snps,exynos5440-ahci";
+                        reg = <0x210000 0x10000>;
+                        interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_SATA>;
+                        clock-names = "sata";
+                };
+
+                ohci@220000 {
+                        compatible = "samsung,exynos5440-ohci";
+                        reg = <0x220000 0x1000>;
+                        interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_USB>;
+                        clock-names = "usbhost";
+                };
+
+                ehci@221000 {
+                        compatible = "samsung,exynos5440-ehci";
+                        reg = <0x221000 0x1000>;
+                        interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_USB>;
+                        clock-names = "usbhost";
+                };
+
+                pcie_phy0: pcie-phy@270000 {
+                        #phy-cells = <0>;
+                        compatible = "samsung,exynos5440-pcie-phy";
+                        reg = <0x270000 0x1000>, <0x271000 0x40>;
+                };
+
+                pcie_phy1: pcie-phy@272000 {
+                        #phy-cells = <0>;
+                        compatible = "samsung,exynos5440-pcie-phy";
+                        reg = <0x272000 0x1000>, <0x271040 0x40>;
+                };
+
+                pcie_0: pcie@290000 {
+                        compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
+                        reg = <0x290000 0x1000>, <0x40000000 0x1000>;
+                        reg-names = "elbi", "config";
+                        interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>;
+                        clock-names = "pcie", "pcie_bus";
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        device_type = "pci";
+                        phys = <&pcie_phy0>;
+                        ranges = <0x81000000 0 0          0x40001000 0 0x00010000   /* downstream I/O */
+                                  0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
+                        bus-range = <0x00 0xff>;
+                        #interrupt-cells = <1>;
+                        interrupt-map-mask = <0 0 0 0>;
+                        interrupt-map = <0x0 0 &gic 53>;
+                        num-lanes = <4>;
+                        status = "disabled";
+                };
+
+                pcie_1: pcie@2a0000 {
+                        compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
+                        reg = <0x2a0000 0x1000>, <0x60000000 0x1000>;
+                        reg-names = "elbi", "config";
+                        interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>;
+                        clock-names = "pcie", "pcie_bus";
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        device_type = "pci";
+                        phys = <&pcie_phy1>;
+                        ranges = <0x81000000 0 0          0x60001000 0 0x00010000   /* downstream I/O */
+                                  0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
+                        bus-range = <0x00 0xff>;
+                        #interrupt-cells = <1>;
+                        interrupt-map-mask = <0 0 0 0>;
+                        interrupt-map = <0x0 0 &gic 56>;
+                        num-lanes = <4>;
+                        status = "disabled";
+                };
         };
 
         thermal-zones {
@@ -262,86 +352,4 @@
                        #include "exynos5440-trip-points.dtsi"
                 };
         };
-
-        sata@210000 {
-                compatible = "snps,exynos5440-ahci";
-                reg = <0x210000 0x10000>;
-                interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_SATA>;
-                clock-names = "sata";
-        };
-
-        ohci@220000 {
-                compatible = "samsung,exynos5440-ohci";
-                reg = <0x220000 0x1000>;
-                interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_USB>;
-                clock-names = "usbhost";
-        };
-
-        ehci@221000 {
-                compatible = "samsung,exynos5440-ehci";
-                reg = <0x221000 0x1000>;
-                interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_USB>;
-                clock-names = "usbhost";
-        };
-
-        pcie_phy0: pcie-phy@270000 {
-                #phy-cells = <0>;
-                compatible = "samsung,exynos5440-pcie-phy";
-                reg = <0x270000 0x1000>, <0x271000 0x40>;
-        };
-
-        pcie_phy1: pcie-phy@272000 {
-                #phy-cells = <0>;
-                compatible = "samsung,exynos5440-pcie-phy";
-                reg = <0x272000 0x1000>, <0x271040 0x40>;
-        };
-
-        pcie_0: pcie@290000 {
-                compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
-                reg = <0x290000 0x1000>, <0x40000000 0x1000>;
-                reg-names = "elbi", "config";
-                interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>;
-                clock-names = "pcie", "pcie_bus";
-                #address-cells = <3>;
-                #size-cells = <2>;
-                device_type = "pci";
-                phys = <&pcie_phy0>;
-                ranges = <0x81000000 0 0          0x40001000 0 0x00010000   /* downstream I/O */
-                          0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
-                bus-range = <0x00 0xff>;
-                #interrupt-cells = <1>;
-                interrupt-map-mask = <0 0 0 0>;
-                interrupt-map = <0x0 0 &gic 53>;
-                num-lanes = <4>;
-                status = "disabled";
-        };
-
-        pcie_1: pcie@2a0000 {
-                compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
-                reg = <0x2a0000 0x1000>, <0x60000000 0x1000>;
-                reg-names = "elbi", "config";
-                interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>;
-                clock-names = "pcie", "pcie_bus";
-                #address-cells = <3>;
-                #size-cells = <2>;
-                device_type = "pci";
-                phys = <&pcie_phy1>;
-                ranges = <0x81000000 0 0          0x60001000 0 0x00010000   /* downstream I/O */
-                          0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
-                bus-range = <0x00 0xff>;
-                #interrupt-cells = <1>;
-                interrupt-map-mask = <0 0 0 0>;
-                interrupt-map = <0x0 0 &gic 56>;
-                num-lanes = <4>;
-                status = "disabled";
-        };
 };
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 0029ec27819c..2f8df9244f72 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Google Peach Pi Rev 10+ board device tree source
  *
  * Copyright (c) 2014 Google, Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 
 /dts-v1/;
@@ -14,6 +11,7 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/clock/maxim,max77802.h>
 #include <dt-bindings/regulator/maxim,max77802.h>
+#include <dt-bindings/sound/samsung-i2s.h>
 #include "exynos5800.dtsi"
 #include "exynos5420-cpus.dtsi"
 
@@ -89,6 +87,14 @@
                 samsung,model = "Peach-Pi-I2S-MAX98091";
                 samsung,i2s-controller = <&i2s0>;
                 samsung,audio-codec = <&max98091>;
+
+                cpu {
+                        sound-dai = <&i2s0 0>;
+                };
+
+                codec {
+                        sound-dai = <&max98091>, <&hdmi>;
+                };
         };
 
         usb300_vbus_reg: regulator-usb300 {
@@ -145,6 +151,11 @@
         vdd-supply = <&ldo9_reg>;
 };
 
+&clock_audss {
+        assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>;
+        assigned-clock-parents = <&clock CLK_FOUT_EPLL>;
+};
+
 &cpu0 {
         cpu-supply = <&buck2_reg>;
 };
@@ -609,6 +620,7 @@
                 pinctrl-0 = <&max98091_irq>;
                 clocks = <&pmu_system_controller 0>;
                 clock-names = "mclk";
+                #sound-dai-cells = <0>;
         };
 
         light-sensor@44 {
@@ -661,6 +673,8 @@
 };
 
 &i2s0 {
+        assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>;
+        assigned-clock-parents = <&clock_audss EXYNOS_I2S_BUS>;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi
index 9ddb6bacac5a..57d3b319fd65 100644
--- a/arch/arm/boot/dts/exynos5800.dtsi
+++ b/arch/arm/boot/dts/exynos5800.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * SAMSUNG EXYNOS5800 SoC device tree source
  *
@@ -7,10 +8,6 @@
  * SAMSUNG EXYNOS5800 SoC device nodes are listed in this file.
  * EXYNOS5800 based board files can include this file and provide
  * values for board specfic bindings.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
  */
 
 #include "exynos5420.dtsi"
diff --git a/arch/arm/boot/dts/gemini-dlink-dns-313.dts b/arch/arm/boot/dts/gemini-dlink-dns-313.dts
index 08568ce24d06..403364a7aab9 100644
--- a/arch/arm/boot/dts/gemini-dlink-dns-313.dts
+++ b/arch/arm/boot/dts/gemini-dlink-dns-313.dts
@@ -78,8 +78,6 @@
                 gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>,
                         <&gpio0 12 GPIO_ACTIVE_HIGH>;
                 gpio-fan,speed-map = <0 0>, <3000 1>, <6000 2>;
-                cooling-min-level = <0>;
-                cooling-max-level = <2>;
                 #cooling-cells = <2>;
         };
 
@@ -269,7 +267,7 @@
 
                 sata: sata@46000000 {
                         /* The ROM uses this muxmode */
-                        cortina,gemini-ata-muxmode = <3>;
+                        cortina,gemini-ata-muxmode = <0>;
                         cortina,gemini-enable-sata-bridge;
                         status = "okay";
                 };
diff --git a/arch/arm/boot/dts/imx1-ads.dts b/arch/arm/boot/dts/imx1-ads.dts
index 5ea28ee07cf4..6354e4c87313 100644
--- a/arch/arm/boot/dts/imx1-ads.dts
+++ b/arch/arm/boot/dts/imx1-ads.dts
@@ -20,7 +20,7 @@
                 stdout-path = &uart1;
         };
 
-        memory {
+        memory@8000000 {
                 reg = <0x08000000 0x04000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx1-apf9328.dts b/arch/arm/boot/dts/imx1-apf9328.dts
index e8b4b52c2418..11515c0cb195 100644
--- a/arch/arm/boot/dts/imx1-apf9328.dts
+++ b/arch/arm/boot/dts/imx1-apf9328.dts
@@ -20,7 +20,7 @@
                 stdout-path = &uart1;
         };
 
-        memory {
+        memory@8000000 {
                 reg = <0x08000000 0x00800000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx1.dtsi b/arch/arm/boot/dts/imx1.dtsi
index 20f6565c337d..f7b9edf93f5e 100644
--- a/arch/arm/boot/dts/imx1.dtsi
+++ b/arch/arm/boot/dts/imx1.dtsi
@@ -25,7 +25,7 @@
          * Also for U-Boot there must be a pre-existing /memory node.
          */
         chosen {};
-        memory { device_type = "memory"; reg = <0 0>; };
+        memory { device_type = "memory"; };
 
         aliases {
                 gpio0 = &gpio1;
diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts
index 57e29977ba06..9d92ece82560 100644
--- a/arch/arm/boot/dts/imx23-evk.dts
+++ b/arch/arm/boot/dts/imx23-evk.dts
@@ -16,7 +16,7 @@
         model = "Freescale i.MX23 Evaluation Kit";
         compatible = "fsl,imx23-evk", "fsl,imx23";
 
-        memory {
+        memory@40000000 {
                 reg = <0x40000000 0x08000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts
index a8b1c53ebe46..e9351774c619 100644
--- a/arch/arm/boot/dts/imx23-olinuxino.dts
+++ b/arch/arm/boot/dts/imx23-olinuxino.dts
@@ -19,7 +19,7 @@
         model = "i.MX23 Olinuxino Low Cost Board";
         compatible = "olimex,imx23-olinuxino", "fsl,imx23";
 
-        memory {
+        memory@40000000 {
                 reg = <0x40000000 0x04000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx23-sansa.dts b/arch/arm/boot/dts/imx23-sansa.dts
index 221fd55e967e..67de7863ad79 100644
--- a/arch/arm/boot/dts/imx23-sansa.dts
+++ b/arch/arm/boot/dts/imx23-sansa.dts
@@ -49,7 +49,7 @@
         model = "SanDisk Sansa Fuze+";
         compatible = "sandisk,sansa_fuze_plus", "fsl,imx23";
 
-        memory {
+        memory@40000000 {
                 reg = <0x40000000 0x04000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx23-stmp378x_devb.dts b/arch/arm/boot/dts/imx23-stmp378x_devb.dts
index 455169e99d49..95c7b918f6d6 100644
--- a/arch/arm/boot/dts/imx23-stmp378x_devb.dts
+++ b/arch/arm/boot/dts/imx23-stmp378x_devb.dts
@@ -16,7 +16,7 @@
         model = "Freescale STMP378x Development Board";
         compatible = "fsl,stmp378x-devb", "fsl,imx23";
 
-        memory {
+        memory@40000000 {
                 reg = <0x40000000 0x04000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx23-xfi3.dts b/arch/arm/boot/dts/imx23-xfi3.dts
index 025cf949662d..9616e500b996 100644
--- a/arch/arm/boot/dts/imx23-xfi3.dts
+++ b/arch/arm/boot/dts/imx23-xfi3.dts
@@ -48,7 +48,7 @@
         model = "Creative ZEN X-Fi3";
         compatible = "creative,x-fi3", "fsl,imx23";
 
-        memory {
+        memory@40000000 {
                 reg = <0x40000000 0x04000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 10d57f9cbb42..cb0a3fe32718 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -23,7 +23,7 @@
          * Also for U-Boot there must be a pre-existing /memory node.
          */
         chosen {};
-        memory { device_type = "memory"; reg = <0 0>; };
+        memory { device_type = "memory"; };
 
         aliases {
                 gpio0 = &gpio0;
@@ -222,7 +222,8 @@
                                         fsl,pull-up = <MXS_PULL_DISABLE>;
                                 };
 
-                                gpmi_pins_fixup: gpmi-pins-fixup {
+                                gpmi_pins_fixup: gpmi-pins-fixup@0 {
+                                        reg = <0>;
                                         fsl,pinmux-ids = <
                                                 MX23_PAD_GPMI_WPN__GPMI_WPN
                                                 MX23_PAD_GPMI_WRN__GPMI_WRN
@@ -266,7 +267,8 @@
                                         fsl,pull-up = <MXS_PULL_ENABLE>;
                                 };
 
-                                mmc0_pins_fixup: mmc0-pins-fixup {
+                                mmc0_pins_fixup: mmc0-pins-fixup@0 {
+                                        reg = <0>;
                                         fsl,pinmux-ids = <
                                                 MX23_PAD_SSP1_DETECT__SSP1_DETECT
                                                 MX23_PAD_SSP1_SCK__SSP1_SCK
diff --git a/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi b/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi
index d6f27641c0ef..e316fe08837a 100644
--- a/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi
+++ b/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi
@@ -17,7 +17,7 @@
         model = "Eukrea CPUIMX25";
         compatible = "eukrea,cpuimx25", "fsl,imx25";
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x4000000>; /* 64M */
         };
 };
diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
index 0f053721d80f..6273a1f243ed 100644
--- a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
+++ b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
@@ -88,12 +88,12 @@
 
                 pinctrl_esdhc1: esdhc1grp {
                         fsl,pins = <
-                                MX25_PAD_SD1_CMD__SD1_CMD               0x400000c0
-                                MX25_PAD_SD1_CLK__SD1_CLK               0x400000c0
-                                MX25_PAD_SD1_DATA0__SD1_DATA0           0x400000c0
-                                MX25_PAD_SD1_DATA1__SD1_DATA1           0x400000c0
-                                MX25_PAD_SD1_DATA2__SD1_DATA2           0x400000c0
-                                MX25_PAD_SD1_DATA3__SD1_DATA3           0x400000c0
+                                MX25_PAD_SD1_CMD__ESDHC1_CMD            0x400000c0
+                                MX25_PAD_SD1_CLK__ESDHC1_CLK            0x400000c0
+                                MX25_PAD_SD1_DATA0__ESDHC1_DAT0         0x400000c0
+                                MX25_PAD_SD1_DATA1__ESDHC1_DAT1         0x400000c0
+                                MX25_PAD_SD1_DATA2__ESDHC1_DAT2         0x400000c0
+                                MX25_PAD_SD1_DATA3__ESDHC1_DAT3         0x400000c0
                         >;
                 };
 
diff --git a/arch/arm/boot/dts/imx25-karo-tx25.dts b/arch/arm/boot/dts/imx25-karo-tx25.dts
index 30a62d4be8d9..5cb6967866c0 100644
--- a/arch/arm/boot/dts/imx25-karo-tx25.dts
+++ b/arch/arm/boot/dts/imx25-karo-tx25.dts
@@ -36,7 +36,7 @@
                 };
         };
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x02000000 0x90000000 0x02000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts
index 2d15ce72d006..7f9bd052b84e 100644
--- a/arch/arm/boot/dts/imx25-pdk.dts
+++ b/arch/arm/boot/dts/imx25-pdk.dts
@@ -18,7 +18,7 @@
         model = "Freescale i.MX25 Product Development Kit";
         compatible = "fsl,imx25-pdk", "fsl,imx25";
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x4000000>;
         };
 
@@ -165,12 +165,12 @@
 
                 pinctrl_esdhc1: esdhc1grp {
                         fsl,pins = <
-                                MX25_PAD_SD1_CMD__SD1_CMD               0x80000000
-                                MX25_PAD_SD1_CLK__SD1_CLK               0x80000000
-                                MX25_PAD_SD1_DATA0__SD1_DATA0           0x80000000
-                                MX25_PAD_SD1_DATA1__SD1_DATA1           0x80000000
-                                MX25_PAD_SD1_DATA2__SD1_DATA2           0x80000000
-                                MX25_PAD_SD1_DATA3__SD1_DATA3           0x80000000
+                                MX25_PAD_SD1_CMD__ESDHC1_CMD            0x80000000
+                                MX25_PAD_SD1_CLK__ESDHC1_CLK            0x80000000
+                                MX25_PAD_SD1_DATA0__ESDHC1_DAT0         0x80000000
+                                MX25_PAD_SD1_DATA1__ESDHC1_DAT1         0x80000000
+                                MX25_PAD_SD1_DATA2__ESDHC1_DAT2         0x80000000
+                                MX25_PAD_SD1_DATA3__ESDHC1_DAT3         0x80000000
                                 MX25_PAD_A14__GPIO_2_0                  0x80000000
                                 MX25_PAD_A15__GPIO_2_1                  0x80000000
                         >;
diff --git a/arch/arm/boot/dts/imx25-pinfunc.h b/arch/arm/boot/dts/imx25-pinfunc.h
index 6c63dca1b9b8..a4807062a90f 100644
--- a/arch/arm/boot/dts/imx25-pinfunc.h
+++ b/arch/arm/boot/dts/imx25-pinfunc.h
@@ -151,21 +151,21 @@
 #define MX25_PAD_D15__D15                       0x088 0x280 0x000 0x00 0x000
 #define MX25_PAD_D15__LD16                      0x088 0x280 0x000 0x01 0x000
 #define MX25_PAD_D15__GPIO_4_5                  0x088 0x280 0x000 0x05 0x000
-#define MX25_PAD_D15__SDHC1_DAT7                0x088 0x280 0x4d8 0x06 0x000
+#define MX25_PAD_D15__ESDHC1_DAT7               0x088 0x280 0x4d8 0x06 0x000
 
 #define MX25_PAD_D14__D14                       0x08c 0x284 0x000 0x00 0x000
 #define MX25_PAD_D14__LD17                      0x08c 0x284 0x000 0x01 0x000
 #define MX25_PAD_D14__GPIO_4_6                  0x08c 0x284 0x000 0x05 0x000
-#define MX25_PAD_D14__SDHC1_DAT6                0x08c 0x284 0x4d4 0x06 0x000
+#define MX25_PAD_D14__ESDHC1_DAT6               0x08c 0x284 0x4d4 0x06 0x000
 
 #define MX25_PAD_D13__D13                       0x090 0x288 0x000 0x00 0x000
 #define MX25_PAD_D13__LD18                      0x090 0x288 0x000 0x01 0x000
 #define MX25_PAD_D13__GPIO_4_7                  0x090 0x288 0x000 0x05 0x000
-#define MX25_PAD_D13__SDHC1_DAT5                0x090 0x288 0x4d0 0x06 0x000
+#define MX25_PAD_D13__ESDHC1_DAT5               0x090 0x288 0x4d0 0x06 0x000
 
 #define MX25_PAD_D12__D12                       0x094 0x28c 0x000 0x00 0x000
 #define MX25_PAD_D12__GPIO_4_8                  0x094 0x28c 0x000 0x05 0x000
-#define MX25_PAD_D12__SDHC1_DAT4                0x094 0x28c 0x4cc 0x06 0x000
+#define MX25_PAD_D12__ESDHC1_DAT4               0x094 0x28c 0x4cc 0x06 0x000
 
 #define MX25_PAD_D11__D11                       0x098 0x290 0x000 0x00 0x000
 #define MX25_PAD_D11__GPIO_4_9                  0x098 0x290 0x000 0x05 0x000
@@ -236,12 +236,13 @@
 #define MX25_PAD_LD8__LD8                       0x0e8 0x2e0 0x000 0x00 0x000
 #define MX25_PAD_LD8__UART4_RXD                 0x0e8 0x2e0 0x570 0x02 0x000
 #define MX25_PAD_LD8__FEC_TX_ERR                0x0e8 0x2e0 0x000 0x05 0x000
-#define MX25_PAD_LD8__SDHC2_CMD                 0x0e8 0x2e0 0x4e0 0x06 0x000
+/* SION must be set; see the comment for MX25_PAD_SD1_CMD__ESDHC1_CMD. */
+#define MX25_PAD_LD8__ESDHC2_CMD                0x0e8 0x2e0 0x4e0 0x16 0x000
 
 #define MX25_PAD_LD9__LD9                       0x0ec 0x2e4 0x000 0x00 0x000
 #define MX25_PAD_LD9__UART4_TXD                 0x0ec 0x2e4 0x000 0x02 0x000
 #define MX25_PAD_LD9__FEC_COL                   0x0ec 0x2e4 0x504 0x05 0x001
-#define MX25_PAD_LD9__SDHC2_CLK                 0x0ec 0x2e4 0x4dc 0x06 0x000
+#define MX25_PAD_LD9__ESDHC2_CLK                0x0ec 0x2e4 0x4dc 0x06 0x000
 
 #define MX25_PAD_LD10__LD10                     0x0f0 0x2e8 0x000 0x00 0x000
 #define MX25_PAD_LD10__UART4_RTS                0x0f0 0x2e8 0x56c 0x02 0x000
@@ -250,7 +251,7 @@
 #define MX25_PAD_LD11__LD11                     0x0f4 0x2ec 0x000 0x00 0x000
 #define MX25_PAD_LD11__UART4_CTS                0x0f4 0x2ec 0x000 0x02 0x000
 #define MX25_PAD_LD11__FEC_RDATA2               0x0f4 0x2ec 0x50c 0x05 0x001
-#define MX25_PAD_LD11__SDHC2_DAT1               0x0f4 0x2ec 0x4e8 0x06 0x000
+#define MX25_PAD_LD11__ESDHC2_DAT1              0x0f4 0x2ec 0x4e8 0x06 0x000
 
 #define MX25_PAD_LD12__LD12                     0x0f8 0x2f0 0x000 0x00 0x000
 #define MX25_PAD_LD12__CSPI2_MOSI               0x0f8 0x2f0 0x4a0 0x02 0x000
@@ -316,12 +317,13 @@
 #define MX25_PAD_CSI_D5__CSPI3_RDY              0x12c 0x324 0x000 0x07 0x000
 
 #define MX25_PAD_CSI_D6__CSI_D6                 0x130 0x328 0x000 0x00 0x000
-#define MX25_PAD_CSI_D6__SDHC2_CMD              0x130 0x328 0x4e0 0x02 0x001
+/* SION must be set; see the comment for MX25_PAD_SD1_CMD__ESDHC1_CMD. */
+#define MX25_PAD_CSI_D6__ESDHC2_CMD             0x130 0x328 0x4e0 0x12 0x001
 #define MX25_PAD_CSI_D6__SIM1_PD0               0x130 0x328 0x000 0x04 0x000
 #define MX25_PAD_CSI_D6__GPIO_1_31              0x130 0x328 0x000 0x05 0x000
 
 #define MX25_PAD_CSI_D7__CSI_D7                 0x134 0x32c 0x000 0x00 0x000
-#define MX25_PAD_CSI_D7__SDHC2_DAT_CLK          0x134 0x32C 0x4dc 0x02 0x001
+#define MX25_PAD_CSI_D7__ESDHC2_CLK             0x134 0x32C 0x4dc 0x02 0x001
 #define MX25_PAD_CSI_D7__GPIO_1_6               0x134 0x32c 0x000 0x05 0x000
 
 #define MX25_PAD_CSI_D8__CSI_D8                 0x138 0x330 0x000 0x00 0x000
@@ -336,22 +338,22 @@
 
 #define MX25_PAD_CSI_MCLK__CSI_MCLK             0x140 0x338 0x000 0x00 0x000
 #define MX25_PAD_CSI_MCLK__AUD6_TXD             0x140 0x338 0x000 0x01 0x000
-#define MX25_PAD_CSI_MCLK__SDHC2_DAT0           0x140 0x338 0x4e4 0x02 0x001
+#define MX25_PAD_CSI_MCLK__ESDHC2_DAT0          0x140 0x338 0x4e4 0x02 0x001
 #define MX25_PAD_CSI_MCLK__GPIO_1_8             0x140 0x338 0x000 0x05 0x000
 
 #define MX25_PAD_CSI_VSYNC__CSI_VSYNC           0x144 0x33c 0x000 0x00 0x000
 #define MX25_PAD_CSI_VSYNC__AUD6_RXD            0x144 0x33c 0x000 0x01 0x000
-#define MX25_PAD_CSI_VSYNC__SDHC2_DAT1          0x144 0x33c 0x4e8 0x02 0x001
+#define MX25_PAD_CSI_VSYNC__ESDHC2_DAT1         0x144 0x33c 0x4e8 0x02 0x001
 #define MX25_PAD_CSI_VSYNC__GPIO_1_9            0x144 0x33c 0x000 0x05 0x000
 
 #define MX25_PAD_CSI_HSYNC__CSI_HSYNC           0x148 0x340 0x000 0x00 0x000
 #define MX25_PAD_CSI_HSYNC__AUD6_TXC            0x148 0x340 0x000 0x01 0x000
-#define MX25_PAD_CSI_HSYNC__SDHC2_DAT2          0x148 0x340 0x4ec 0x02 0x001
+#define MX25_PAD_CSI_HSYNC__ESDHC2_DAT2         0x148 0x340 0x4ec 0x02 0x001
 #define MX25_PAD_CSI_HSYNC__GPIO_1_10           0x148 0x340 0x000 0x05 0x000
 
 #define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK         0x14c 0x344 0x000 0x00 0x000
 #define MX25_PAD_CSI_PIXCLK__AUD6_TXFS          0x14c 0x344 0x000 0x01 0x000
-#define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3         0x14c 0x344 0x4f0 0x02 0x001
+#define MX25_PAD_CSI_PIXCLK__ESDHC2_DAT3        0x14c 0x344 0x4f0 0x02 0x001
 #define MX25_PAD_CSI_PIXCLK__GPIO_1_11          0x14c 0x344 0x000 0x05 0x000
 
 #define MX25_PAD_I2C1_CLK__I2C1_CLK             0x150 0x348 0x000 0x00 0x000
@@ -419,37 +421,37 @@
 #define MX25_PAD_UART2_CTS__GPIO_4_29           0x18c 0x384 0x000 0x05 0x000
 
 /*
- * Removing the SION bit from MX25_PAD_SD1_CMD__SD1_CMD breaks detecting an SD
+ * Removing the SION bit from MX25_PAD_*__ESDHCn_CMD breaks detecting an SD
  * card. According to the i.MX25 reference manual (e.g. Figure 23-2 in IMX25RM
  * Rev. 2 from 01/2011) this pin is bidirectional. So it seems to be a silicon
- * bug that configuring the SD1_CMD function doesn't enable the input path for
- * this pin.
+ * bug that configuring the ESDHCn_CMD function doesn't enable the input path
+ * for this pin.
  * This might have side effects for other hardware units that are connected to
  * that pin and use the respective function as input.
  */
-#define MX25_PAD_SD1_CMD__SD1_CMD               0x190 0x388 0x000 0x10 0x000
+#define MX25_PAD_SD1_CMD__ESDHC1_CMD            0x190 0x388 0x000 0x10 0x000
 #define MX25_PAD_SD1_CMD__CSPI2_MOSI            0x190 0x388 0x4a0 0x01 0x001
 #define MX25_PAD_SD1_CMD__FEC_RDATA2            0x190 0x388 0x50c 0x02 0x002
 #define MX25_PAD_SD1_CMD__GPIO_2_23             0x190 0x388 0x000 0x05 0x000
 
-#define MX25_PAD_SD1_CLK__SD1_CLK               0x194 0x38c 0x000 0x00 0x000
+#define MX25_PAD_SD1_CLK__ESDHC1_CLK            0x194 0x38c 0x000 0x00 0x000
 #define MX25_PAD_SD1_CLK__CSPI2_MISO            0x194 0x38c 0x49c 0x01 0x001
 #define MX25_PAD_SD1_CLK__FEC_RDATA3            0x194 0x38c 0x510 0x02 0x002
 #define MX25_PAD_SD1_CLK__GPIO_2_24             0x194 0x38c 0x000 0x05 0x000
 
-#define MX25_PAD_SD1_DATA0__SD1_DATA0           0x198 0x390 0x000 0x00 0x000
+#define MX25_PAD_SD1_DATA0__ESDHC1_DAT0         0x198 0x390 0x000 0x00 0x000
 #define MX25_PAD_SD1_DATA0__CSPI2_SCLK          0x198 0x390 0x494 0x01 0x001
 #define MX25_PAD_SD1_DATA0__GPIO_2_25           0x198 0x390 0x000 0x05 0x000
 
-#define MX25_PAD_SD1_DATA1__SD1_DATA1           0x19c 0x394 0x000 0x00 0x000
+#define MX25_PAD_SD1_DATA1__ESDHC1_DAT1         0x19c 0x394 0x000 0x00 0x000
 #define MX25_PAD_SD1_DATA1__AUD7_RXD            0x19c 0x394 0x478 0x03 0x000
 #define MX25_PAD_SD1_DATA1__GPIO_2_26           0x19c 0x394 0x000 0x05 0x000
 
-#define MX25_PAD_SD1_DATA2__SD1_DATA2           0x1a0 0x398 0x000 0x00 0x000
+#define MX25_PAD_SD1_DATA2__ESDHC1_DAT2         0x1a0 0x398 0x000 0x00 0x000
 #define MX25_PAD_SD1_DATA2__FEC_RX_CLK          0x1a0 0x398 0x514 0x02 0x002
 #define MX25_PAD_SD1_DATA2__GPIO_2_27           0x1a0 0x398 0x000 0x05 0x000
 
-#define MX25_PAD_SD1_DATA3__SD1_DATA3           0x1a4 0x39c 0x000 0x00 0x000
+#define MX25_PAD_SD1_DATA3__ESDHC1_DAT3         0x1a4 0x39c 0x000 0x00 0x000
 #define MX25_PAD_SD1_DATA3__FEC_CRS             0x1a4 0x39c 0x508 0x02 0x002
 #define MX25_PAD_SD1_DATA3__GPIO_2_28           0x1a4 0x39c 0x000 0x05 0x000
 
@@ -496,6 +498,8 @@
 #define MX25_PAD_KPP_COL3__GPIO_3_4             0x1c4 0x3bc 0x000 0x05 0x000
 
 #define MX25_PAD_FEC_MDC__FEC_MDC               0x1c8 0x3c0 0x000 0x00 0x000
+/* SION must be set; see the comment for MX25_PAD_SD1_CMD__ESDHC1_CMD. */
+#define MX25_PAD_FEC_MDC__ESDHC2_CMD            0x1c8 0x3c0 0x4e0 0x11 0x002
 #define MX25_PAD_FEC_MDC__AUD4_TXD              0x1c8 0x3c0 0x464 0x02 0x001
 #define MX25_PAD_FEC_MDC__GPIO_3_5              0x1c8 0x3c0 0x000 0x05 0x000
 
@@ -601,4 +605,28 @@
 #define MX25_PAD_BOOT_MODE1__BOOT_MODE1         0x228 0x000 0x000 0x00 0x000
 #define MX25_PAD_BOOT_MODE1__GPIO_4_31          0x228 0x000 0x000 0x05 0x000
 
+/*
+ * Compatibility defines for out-of-tree users. You should update if you make
+ * use of one of them.
+ */
+#define MX25_PAD_D15__SDHC1_DAT7                MX25_PAD_D15__ESDHC1_DAT7
+#define MX25_PAD_D14__SDHC1_DAT6                MX25_PAD_D14__ESDHC1_DAT6
+#define MX25_PAD_D13__SDHC1_DAT5                MX25_PAD_D13__ESDHC1_DAT5
+#define MX25_PAD_D12__SDHC1_DAT4                MX25_PAD_D12__ESDHC1_DAT4
+#define MX25_PAD_LD8__SDHC2_CMD                 MX25_PAD_LD8__ESDHC2_CMD
+#define MX25_PAD_LD9__SDHC2_CLK                 MX25_PAD_LD9__ESDHC2_CLK
+#define MX25_PAD_LD11__SDHC2_DAT1               MX25_PAD_LD11__ESDHC2_DAT1
+#define MX25_PAD_CSI_D6__SDHC2_CMD              MX25_PAD_CSI_D6__ESDHC2_CMD
+#define MX25_PAD_CSI_D7__SDHC2_DAT_CLK          MX25_PAD_CSI_D7__ESDHC2_CLK
+#define MX25_PAD_CSI_MCLK__SDHC2_DAT0           MX25_PAD_CSI_MCLK__ESDHC2_DAT0
+#define MX25_PAD_CSI_VSYNC__SDHC2_DAT1          MX25_PAD_CSI_VSYNC__ESDHC2_DAT1
+#define MX25_PAD_CSI_HSYNC__SDHC2_DAT2          MX25_PAD_CSI_HSYNC__ESDHC2_DAT2
+#define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3         MX25_PAD_CSI_PIXCLK__ESDHC2_DAT3
+#define MX25_PAD_SD1_CMD__SD1_CMD               MX25_PAD_SD1_CMD__ESDHC1_CMD
+#define MX25_PAD_SD1_CLK__SD1_CLK               MX25_PAD_SD1_CLK__ESDHC1_CLK
+#define MX25_PAD_SD1_DATA0__SD1_DATA0           MX25_PAD_SD1_DATA0__ESDHC1_DAT0
+#define MX25_PAD_SD1_DATA1__SD1_DATA1           MX25_PAD_SD1_DATA1__ESDHC1_DAT1
+#define MX25_PAD_SD1_DATA2__SD1_DATA2           MX25_PAD_SD1_DATA2__ESDHC1_DAT2
+#define MX25_PAD_SD1_DATA3__SD1_DATA3           MX25_PAD_SD1_DATA3__ESDHC1_DAT3
+
 #endif /* __DTS_IMX25_PINFUNC_H */
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index 9445f8e1473c..cf70df20b19c 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -22,7 +22,7 @@
          * Also for U-Boot there must be a pre-existing /memory node.
          */
         chosen {};
-        memory { device_type = "memory"; reg = <0 0>; };
+        memory { device_type = "memory"; };
 
         aliases {
                 ethernet0 = &fec;
@@ -269,6 +269,7 @@
                                 dmas = <&sdma 24 1 0>,
                                        <&sdma 25 1 0>;
                                 dma-names = "rx", "tx";
+                                fsl,fifo-depth = <15>;
                                 status = "disabled";
                         };
 
@@ -329,6 +330,7 @@
                                 dmas = <&sdma 28 1 0>,
                                        <&sdma 29 1 0>;
                                 dma-names = "rx", "tx";
+                                fsl,fifo-depth = <15>;
                                 status = "disabled";
                         };
 
diff --git a/arch/arm/boot/dts/imx27-apf27.dts b/arch/arm/boot/dts/imx27-apf27.dts
index 73aae4f5e539..66941cdbf244 100644
--- a/arch/arm/boot/dts/imx27-apf27.dts
+++ b/arch/arm/boot/dts/imx27-apf27.dts
@@ -19,7 +19,7 @@
         model = "Armadeus Systems APF27 module";
         compatible = "armadeus,imx27-apf27", "fsl,imx27";
 
-        memory {
+        memory@a0000000 {
                 reg = <0xa0000000 0x04000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi b/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi
index 2cf896c505f9..9c455dcbe6eb 100644
--- a/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi
+++ b/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi
@@ -16,21 +16,14 @@
         model = "Eukrea CPUIMX27";
         compatible = "eukrea,cpuimx27", "fsl,imx27";
 
-        memory {
+        memory@a0000000 {
                 reg = <0xa0000000 0x04000000>;
         };
 
-        clocks {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "simple-bus";
-
-                clk14745600: clock@0 {
-                        #clock-cells = <0>;
-                        compatible = "fixed-clock";
-                        clock-frequency = <14745600>;
-                        reg = <0>;
-                };
+        clk14745600: clk-uart {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <14745600>;
         };
 };
 
diff --git a/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts b/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts
index f56535768ee8..15145e7f9778 100644
--- a/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts
+++ b/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts
@@ -84,7 +84,7 @@
         cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
         status = "okay";
 
-        ads7846 {
+        ads7846@0 {
                 compatible = "ti,ads7846";
                 pinctrl-names = "default";
                 pinctrl-0 = <&pinctrl_touch>;
diff --git a/arch/arm/boot/dts/imx27-pdk.dts b/arch/arm/boot/dts/imx27-pdk.dts
index 2a140c8ae6d2..924b90c9985d 100644
--- a/arch/arm/boot/dts/imx27-pdk.dts
+++ b/arch/arm/boot/dts/imx27-pdk.dts
@@ -16,7 +16,7 @@
         model = "Freescale i.MX27 Product Development Kit";
         compatible = "fsl,imx27-pdk", "fsl,imx27";
 
-        memory {
+        memory@a0000000 {
                 reg = <0xa0000000 0x08000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi
index 0b8490b21a38..cbad7c88c58c 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi
+++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi
@@ -17,7 +17,7 @@
         model = "Phytec pca100";
         compatible = "phytec,imx27-pca100", "fsl,imx27";
 
-        memory {
+        memory@a0000000 {
                 reg = <0xa0000000 0x08000000>; /* 128MB */
         };
 };
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
index c9095b7654c6..ec466b4bfd41 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
@@ -16,7 +16,7 @@
         model = "Phytec pcm038";
         compatible = "phytec,imx27-pcm038", "fsl,imx27";
 
-        memory {
+        memory@a0000000 {
                 reg = <0xa0000000 0x08000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 15d85f1f85fd..6585b00c3917 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -26,7 +26,7 @@
          * Also for U-Boot there must be a pre-existing /memory node.
          */
         chosen {};
-        memory { device_type = "memory"; reg = <0 0>; };
+        memory { device_type = "memory"; };
 
         aliases {
                 ethernet0 = &fec;
diff --git a/arch/arm/boot/dts/imx28-apf28.dts b/arch/arm/boot/dts/imx28-apf28.dts
index 070e59cbdd8b..bab78346fa9f 100644
--- a/arch/arm/boot/dts/imx28-apf28.dts
+++ b/arch/arm/boot/dts/imx28-apf28.dts
@@ -16,7 +16,7 @@
         model = "Armadeus Systems APF28 module";
         compatible = "armadeus,imx28-apf28", "fsl,imx28";
 
-        memory {
+        memory@40000000 {
                 reg = <0x40000000 0x08000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts
index ae078341fb60..96faa53ba44c 100644
--- a/arch/arm/boot/dts/imx28-apx4devkit.dts
+++ b/arch/arm/boot/dts/imx28-apx4devkit.dts
@@ -6,7 +6,7 @@
         model = "Bluegiga APX4 Development Kit";
         compatible = "bluegiga,apx4devkit", "fsl,imx28";
 
-        memory {
+        memory@40000000 {
                 reg = <0x40000000 0x04000000>;
         };
 
@@ -82,7 +82,8 @@
                                         fsl,pull-up = <MXS_PULL_ENABLE>;
                                 };
 
-                                mmc2_sck_cfg_apx4: mmc2-sck-cfg-apx4 {
+                                mmc2_sck_cfg_apx4: mmc2-sck-cfg-apx4@0 {
+                                        reg = <0>;
                                         fsl,pinmux-ids = <
                                                 MX28_PAD_SSP0_DATA7__SSP2_SCK
                                         >;
@@ -146,6 +147,7 @@
                                 sgtl5000: codec@a {
                                         compatible = "fsl,sgtl5000";
                                         reg = <0x0a>;
+                                        #sound-dai-cells = <0>;
                                         VDDA-supply = <&reg_3p3v>;
                                         VDDIO-supply = <&reg_3p3v>;
                                         clocks = <&saif0>;
diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts
index 570aa339a05e..e54f5aba7091 100644
--- a/arch/arm/boot/dts/imx28-cfa10036.dts
+++ b/arch/arm/boot/dts/imx28-cfa10036.dts
@@ -16,7 +16,7 @@
         model = "Crystalfontz CFA-10036 Board";
         compatible = "crystalfontz,cfa10036", "fsl,imx28";
 
-        memory {
+        memory@40000000 {
                 reg = <0x40000000 0x08000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts
index 4cd52d53cf00..60e5c7fd5035 100644
--- a/arch/arm/boot/dts/imx28-cfa10049.dts
+++ b/arch/arm/boot/dts/imx28-cfa10049.dts
@@ -19,6 +19,71 @@
         model = "Crystalfontz CFA-10049 Board";
         compatible = "crystalfontz,cfa10049", "crystalfontz,cfa10036", "fsl,imx28";
 
+        i2cmux {
+                compatible = "i2c-mux-gpio";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2cmux_pins_cfa10049>;
+                mux-gpios = <&gpio1 22 0 &gpio1 23 0>;
+                i2c-parent = <&i2c1>;
+
+                i2c@0 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0>;
+
+                        adc0: nau7802@2a {
+                                compatible = "nuvoton,nau7802";
+                                reg = <0x2a>;
+                                nuvoton,vldo = <3000>;
+                        };
+                };
+
+                i2c@1 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <1>;
+
+                        adc1: nau7802@2a {
+                                compatible = "nuvoton,nau7802";
+                                reg = <0x2a>;
+                                nuvoton,vldo = <3000>;
+                        };
+                };
+
+                i2c@2 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <2>;
+
+                                adc2: nau7802@2a {
+                                compatible = "nuvoton,nau7802";
+                                reg = <0x2a>;
+                                nuvoton,vldo = <3000>;
+                        };
+                };
+
+                i2c@3 {
+                        reg = <3>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        pca9555: pca9555@20 {
+                                compatible = "nxp,pca9555";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pca_pins_cfa10049>;
+                                interrupt-parent = <&gpio2>;
+                                interrupts = <19 0x2>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x20>;
+                        };
+                };
+        };
+
         apb@80000000 {
                 apbh@80000000 {
                         pinctrl@80018000 {
@@ -219,71 +284,6 @@
                                 status = "okay";
                         };
 
-                        i2cmux {
-                                compatible = "i2c-mux-gpio";
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&i2cmux_pins_cfa10049>;
-                                mux-gpios = <&gpio1 22 0 &gpio1 23 0>;
-                                i2c-parent = <&i2c1>;
-
-                                i2c@0 {
-                                        #address-cells = <1>;
-                                        #size-cells = <0>;
-                                        reg = <0>;
-
-                                        adc0: nau7802@2a {
-                                                compatible = "nuvoton,nau7802";
-                                                reg = <0x2a>;
-                                                nuvoton,vldo = <3000>;
-                                        };
-                                };
-
-                                i2c@1 {
-                                        #address-cells = <1>;
-                                        #size-cells = <0>;
-                                        reg = <1>;
-
-                                        adc1: nau7802@2a {
-                                                compatible = "nuvoton,nau7802";
-                                                reg = <0x2a>;
-                                                nuvoton,vldo = <3000>;
-                                        };
-                                };
-
-                                i2c@2 {
-                                        #address-cells = <1>;
-                                        #size-cells = <0>;
-                                        reg = <2>;
-
-                                        adc2: nau7802@2a {
-                                                compatible = "nuvoton,nau7802";
-                                                reg = <0x2a>;
-                                                nuvoton,vldo = <3000>;
-                                        };
-                                };
-
-                                i2c@3 {
-                                        reg = <3>;
-                                        #address-cells = <1>;
-                                        #size-cells = <0>;
-
-                                        pca9555: pca9555@20 {
-                                                compatible = "nxp,pca9555";
-                                                pinctrl-names = "default";
-                                                pinctrl-0 = <&pca_pins_cfa10049>;
-                                                interrupt-parent = <&gpio2>;
-                                                interrupts = <19 0x2>;
-                                                gpio-controller;
-                                                #gpio-cells = <2>;
-                                                interrupt-controller;
-                                                #interrupt-cells = <2>;
-                                                reg = <0x20>;
-                                        };
-                                };
-                        };
-
                         usbphy1: usbphy@8007e000 {
                                 status = "okay";
                         };
diff --git a/arch/arm/boot/dts/imx28-duckbill-2-485.dts b/arch/arm/boot/dts/imx28-duckbill-2-485.dts
index bd3fd470f9c3..97084e463d7c 100644
--- a/arch/arm/boot/dts/imx28-duckbill-2-485.dts
+++ b/arch/arm/boot/dts/imx28-duckbill-2-485.dts
@@ -19,7 +19,7 @@
         model = "I2SE Duckbill 2 485";
         compatible = "i2se,duckbill-2-485", "i2se,duckbill-2", "fsl,imx28";
 
-        memory {
+        memory@40000000 {
                 reg = <0x40000000 0x08000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts b/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts
index 4450047885eb..7f8d40a9c67e 100644
--- a/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts
+++ b/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts
@@ -20,7 +20,7 @@
         model = "I2SE Duckbill 2 EnOcean";
         compatible = "i2se,duckbill-2-enocean", "i2se,duckbill-2", "fsl,imx28";
 
-        memory {
+        memory@40000000 {
                 reg = <0x40000000 0x08000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx28-duckbill-2-spi.dts b/arch/arm/boot/dts/imx28-duckbill-2-spi.dts
index 927732efca98..13e7b134da9e 100644
--- a/arch/arm/boot/dts/imx28-duckbill-2-spi.dts
+++ b/arch/arm/boot/dts/imx28-duckbill-2-spi.dts
@@ -23,7 +23,7 @@
                 ethernet1 = &qca7000;
         };
 
-        memory {
+        memory@40000000 {
                 reg = <0x40000000 0x08000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx28-duckbill-2.dts b/arch/arm/boot/dts/imx28-duckbill-2.dts
index 7fa3d759505c..88556c93b00f 100644
--- a/arch/arm/boot/dts/imx28-duckbill-2.dts
+++ b/arch/arm/boot/dts/imx28-duckbill-2.dts
@@ -19,7 +19,7 @@
         model = "I2SE Duckbill 2";
         compatible = "i2se,duckbill-2", "fsl,imx28";
 
-        memory {
+        memory@40000000 {
                 reg = <0x40000000 0x08000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx28-duckbill.dts b/arch/arm/boot/dts/imx28-duckbill.dts
index 3e4385d4ed78..f286bfe699be 100644
--- a/arch/arm/boot/dts/imx28-duckbill.dts
+++ b/arch/arm/boot/dts/imx28-duckbill.dts
@@ -18,7 +18,7 @@
         model = "I2SE Duckbill";
         compatible = "i2se,duckbill", "fsl,imx28";
 
-        memory {
+        memory@40000000 {
                 reg = <0x40000000 0x08000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts b/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts
index 7c1572c5a4fb..b70f3349c350 100644
--- a/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts
+++ b/arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dts
@@ -23,7 +23,7 @@
         model = "Eukrea Electromatique MBMX283LC";
         compatible = "eukrea,mbmx283lc", "eukrea,mbmx28lc", "fsl,imx28";
 
-        memory {
+        memory@40000000 {
                 reg = <0x40000000 0x04000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts b/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts
index b61fd61eb1c7..65efb78ac040 100644
--- a/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts
+++ b/arch/arm/boot/dts/imx28-eukrea-mbmx287lc.dts
@@ -22,7 +22,7 @@
         model = "Eukrea Electromatique MBMX287LC";
         compatible = "eukrea,mbmx287lc", "eukrea,mbmx283lc", "eukrea,mbmx28lc", "fsl,imx28";
 
-        memory {
+        memory@40000000 {
                 reg = <0x40000000 0x08000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi b/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi
index 49ab40838e69..ff1328ce7d37 100644
--- a/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi
+++ b/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi
@@ -151,6 +151,7 @@
         sgtl5000: codec@a {
                 compatible = "fsl,sgtl5000";
                 reg = <0x0a>;
+                #sound-dai-cells = <0>;
                 VDDA-supply = <&reg_3p3v>;
                 VDDIO-supply = <&reg_3p3v>;
                 clocks = <&saif0>;
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index 7f5b80402c54..b0d39654aeb3 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -16,7 +16,7 @@
         model = "Freescale i.MX28 Evaluation Kit";
         compatible = "fsl,imx28-evk", "fsl,imx28";
 
-        memory {
+        memory@40000000 {
                 reg = <0x40000000 0x08000000>;
         };
 
@@ -197,6 +197,7 @@
                                 sgtl5000: codec@a {
                                         compatible = "fsl,sgtl5000";
                                         reg = <0x0a>;
+                                        #sound-dai-cells = <0>;
                                         VDDA-supply = <&reg_3p3v>;
                                         VDDIO-supply = <&reg_3p3v>;
                                         clocks = <&saif0>;
diff --git a/arch/arm/boot/dts/imx28-m28.dtsi b/arch/arm/boot/dts/imx28-m28.dtsi
index a69856e41ba4..0ec415e1ff58 100644
--- a/arch/arm/boot/dts/imx28-m28.dtsi
+++ b/arch/arm/boot/dts/imx28-m28.dtsi
@@ -15,7 +15,7 @@
         model = "Aries/DENX M28";
         compatible = "aries,m28", "denx,m28", "fsl,imx28";
 
-        memory {
+        memory@40000000 {
                 reg = <0x40000000 0x08000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx28-m28cu3.dts b/arch/arm/boot/dts/imx28-m28cu3.dts
index 9d6c8fe28d74..3bb5ffc644d6 100644
--- a/arch/arm/boot/dts/imx28-m28cu3.dts
+++ b/arch/arm/boot/dts/imx28-m28cu3.dts
@@ -16,7 +16,7 @@
         model = "MSR M28CU3";
         compatible = "msr,m28cu3", "fsl,imx28";
 
-        memory {
+        memory@40000000 {
                 reg = <0x40000000 0x08000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts
index 22aa025cab1e..7d97a0ce74a3 100644
--- a/arch/arm/boot/dts/imx28-m28evk.dts
+++ b/arch/arm/boot/dts/imx28-m28evk.dts
@@ -140,6 +140,7 @@
                                 sgtl5000: codec@a {
                                         compatible = "fsl,sgtl5000";
                                         reg = <0x0a>;
+                                        #sound-dai-cells = <0>;
                                         VDDA-supply = <&reg_3p3v>;
                                         VDDIO-supply = <&reg_3p3v>;
                                         clocks = <&saif0>;
diff --git a/arch/arm/boot/dts/imx28-sps1.dts b/arch/arm/boot/dts/imx28-sps1.dts
index 0ce3cb8e7914..2393e83979e0 100644
--- a/arch/arm/boot/dts/imx28-sps1.dts
+++ b/arch/arm/boot/dts/imx28-sps1.dts
@@ -16,7 +16,7 @@
         model = "SchulerControl GmbH, SC SPS 1";
         compatible = "schulercontrol,imx28-sps1", "fsl,imx28";
 
-        memory {
+        memory@40000000 {
                 reg = <0x40000000 0x08000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx28-ts4600.dts b/arch/arm/boot/dts/imx28-ts4600.dts
index 1e391c9f1b7a..f8a09a8c2c36 100644
--- a/arch/arm/boot/dts/imx28-ts4600.dts
+++ b/arch/arm/boot/dts/imx28-ts4600.dts
@@ -19,7 +19,7 @@
         model = "Technologic Systems i.MX28 TS-4600";
         compatible = "technologic,imx28-ts4600", "fsl,imx28";
 
-        memory {
+        memory@40000000 {
                 reg = <0x40000000 0x10000000>;   /* 256MB */
         };
 
diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts
index 152621ea37db..687186358c18 100644
--- a/arch/arm/boot/dts/imx28-tx28.dts
+++ b/arch/arm/boot/dts/imx28-tx28.dts
@@ -65,8 +65,8 @@
                 usbotg = &usb0;
         };
 
-        memory {
-                reg = <0 0>; /* will be filled in by U-Boot */
+        memory@40000000 {
+                reg = <0x40000000 0>; /* will be filled in by U-Boot */
         };
 
         onewire {
@@ -531,7 +531,8 @@
                 fsl,pull-up = <MXS_PULL_DISABLE>;
         };
 
-        tx28_edt_ft5x06_pins: tx28-edt-ft5x06-pins {
+        tx28_edt_ft5x06_pins: tx28-edt-ft5x06-pins@0 {
+                reg = <0>;
                 fsl,pinmux-ids = <
                         MX28_PAD_SSP0_DATA6__GPIO_2_6 /* RESET */
                         MX28_PAD_SSP0_DATA5__GPIO_2_5 /* IRQ */
@@ -542,7 +543,8 @@
                 fsl,pull-up = <MXS_PULL_DISABLE>;
         };
 
-        tx28_flexcan_xcvr_pins: tx28-flexcan-xcvr-pins {
+        tx28_flexcan_xcvr_pins: tx28-flexcan-xcvr-pins@0 {
+                reg = <0>;
                 fsl,pinmux-ids = <
                         MX28_PAD_LCD_D00__GPIO_1_0
                 >;
@@ -551,7 +553,8 @@
                 fsl,pull-up = <MXS_PULL_DISABLE>;
         };
 
-        tx28_lcdif_23bit_pins: tx28-lcdif-23bit {
+        tx28_lcdif_23bit_pins: tx28-lcdif-23bit@0 {
+                reg = <0>;
                 fsl,pinmux-ids = <
                         /* LCD_D00 may be used as Flexcan Transceiver Enable on STK5-V5 */
                         MX28_PAD_LCD_D01__LCD_D1
@@ -583,7 +586,8 @@
                 fsl,pull-up = <MXS_PULL_DISABLE>;
         };
 
-        tx28_lcdif_ctrl_pins: tx28-lcdif-ctrl {
+        tx28_lcdif_ctrl_pins: tx28-lcdif-ctrl@0 {
+                reg = <0>;
                 fsl,pinmux-ids = <
                         MX28_PAD_LCD_ENABLE__GPIO_1_31 /* Enable */
                         MX28_PAD_LCD_RESET__GPIO_3_30  /* Reset */
@@ -593,7 +597,8 @@
                 fsl,pull-up = <MXS_PULL_DISABLE>;
         };
 
-        tx28_mac0_pins_gpio: tx28-mac0-gpio-pins {
+        tx28_mac0_pins_gpio: tx28-mac0-gpio-pins@0 {
+                reg = <0>;
                 fsl,pinmux-ids = <
                         MX28_PAD_ENET0_MDC__GPIO_4_0
                         MX28_PAD_ENET0_MDIO__GPIO_4_1
@@ -610,7 +615,8 @@
                 fsl,pull-up = <MXS_PULL_DISABLE>;
         };
 
-        tx28_pca9554_pins: tx28-pca9554-pins {
+        tx28_pca9554_pins: tx28-pca9554-pins@0 {
+                reg = <0>;
                 fsl,pinmux-ids = <
                         MX28_PAD_PWM3__GPIO_3_28
                 >;
@@ -619,7 +625,8 @@
                 fsl,pull-up = <MXS_PULL_DISABLE>;
         };
 
-        tx28_spi_gpio_pins: spi-gpiogrp {
+        tx28_spi_gpio_pins: spi-gpiogrp@0 {
+                reg = <0>;
                 fsl,pinmux-ids = <
                         MX28_PAD_AUART2_RX__GPIO_3_8
                         MX28_PAD_AUART2_TX__GPIO_3_9
@@ -633,7 +640,8 @@
                 fsl,pull-up = <MXS_PULL_DISABLE>;
         };
 
-        tx28_tsc2007_pins: tx28-tsc2007-pins {
+        tx28_tsc2007_pins: tx28-tsc2007-pins@0 {
+                reg = <0>;
                 fsl,pinmux-ids = <
                         MX28_PAD_SAIF0_MCLK__GPIO_3_20 /* TSC2007 IRQ */
                 >;
@@ -643,7 +651,8 @@
         };
 
 
-        tx28_usbphy0_pins: tx28-usbphy0-pins {
+        tx28_usbphy0_pins: tx28-usbphy0-pins@0 {
+                reg = <0>;
                 fsl,pinmux-ids = <
                         MX28_PAD_GPMI_CE2N__GPIO_0_18 /* USBOTG_VBUSEN */
                         MX28_PAD_GPMI_CE3N__GPIO_0_19 /* USBOTH_OC */
@@ -653,7 +662,8 @@
                 fsl,pull-up = <MXS_PULL_DISABLE>;
         };
 
-        tx28_usbphy1_pins: tx28-usbphy1-pins {
+        tx28_usbphy1_pins: tx28-usbphy1-pins@0 {
+                reg = <0>;
                 fsl,pinmux-ids = <
                         MX28_PAD_SPDIF__GPIO_3_27 /* USBH_VBUSEN */
                         MX28_PAD_JTAG_RTCK__GPIO_4_20 /* USBH_OC */
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index e52e05c0fe56..9ad8d3556859 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -24,7 +24,7 @@
          * Also for U-Boot there must be a pre-existing /memory node.
          */
         chosen {};
-        memory { device_type = "memory"; reg = <0 0>; };
+        memory { device_type = "memory"; };
 
         aliases {
                 ethernet0 = &mac0;
@@ -283,7 +283,8 @@
                                         fsl,pull-up = <MXS_PULL_DISABLE>;
                                 };
 
-                                gpmi_status_cfg: gpmi-status-cfg {
+                                gpmi_status_cfg: gpmi-status-cfg@0 {
+                                        reg = <0>;
                                         fsl,pinmux-ids = <
                                                 MX28_PAD_GPMI_RDN__GPMI_RDN
                                                 MX28_PAD_GPMI_WRN__GPMI_WRN
@@ -527,14 +528,16 @@
                                         fsl,pull-up = <MXS_PULL_ENABLE>;
                                 };
 
-                                mmc0_cd_cfg: mmc0-cd-cfg {
+                                mmc0_cd_cfg: mmc0-cd-cfg@0 {
+                                        reg = <0>;
                                         fsl,pinmux-ids = <
                                                 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
                                         >;
                                         fsl,pull-up = <MXS_PULL_DISABLE>;
                                 };
 
-                                mmc0_sck_cfg: mmc0-sck-cfg {
+                                mmc0_sck_cfg: mmc0-sck-cfg@0 {
+                                        reg = <0>;
                                         fsl,pinmux-ids = <
                                                 MX28_PAD_SSP0_SCK__SSP0_SCK
                                         >;
@@ -558,14 +561,16 @@
                                         fsl,pull-up = <MXS_PULL_ENABLE>;
                                 };
 
-                                mmc1_cd_cfg: mmc1-cd-cfg {
+                                mmc1_cd_cfg: mmc1-cd-cfg@0 {
+                                        reg = <0>;
                                         fsl,pinmux-ids = <
                                                 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
                                         >;
                                         fsl,pull-up = <MXS_PULL_DISABLE>;
                                 };
 
-                                mmc1_sck_cfg: mmc1-sck-cfg {
+                                mmc1_sck_cfg: mmc1-sck-cfg@0 {
+                                        reg = <0>;
                                         fsl,pinmux-ids = <
                                                 MX28_PAD_GPMI_WRN__SSP1_SCK
                                         >;
@@ -606,7 +611,8 @@
                                         fsl,pull-up = <MXS_PULL_ENABLE>;
                                 };
 
-                                mmc2_cd_cfg: mmc2-cd-cfg {
+                                mmc2_cd_cfg: mmc2-cd-cfg@0 {
+                                        reg = <0>;
                                         fsl,pinmux-ids = <
                                                 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
                                         >;
diff --git a/arch/arm/boot/dts/imx31-bug.dts b/arch/arm/boot/dts/imx31-bug.dts
index ae6cebbed84b..6ee4ff8e4e8f 100644
--- a/arch/arm/boot/dts/imx31-bug.dts
+++ b/arch/arm/boot/dts/imx31-bug.dts
@@ -16,7 +16,7 @@
         model = "Buglabs i.MX31 Bug 1.x";
         compatible = "buglabs,imx31-bug", "fsl,imx31";
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x8000000>; /* 128M */
         };
 };
diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi
index a72031407ebd..ebc3f2dbb6fd 100644
--- a/arch/arm/boot/dts/imx31.dtsi
+++ b/arch/arm/boot/dts/imx31.dtsi
@@ -19,7 +19,7 @@
          * Also for U-Boot there must be a pre-existing /memory node.
          */
         chosen {};
-        memory { device_type = "memory"; reg = <0 0>; };
+        memory { device_type = "memory"; };
 
         aliases {
                 serial0 = &uart1;
diff --git a/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi b/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi
index 9c2b715ab8bf..ba39d938f289 100644
--- a/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi
+++ b/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi
@@ -17,7 +17,7 @@
         model = "Eukrea CPUIMX35";
         compatible = "eukrea,cpuimx35", "fsl,imx35";
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x8000000>; /* 128M */
         };
 };
diff --git a/arch/arm/boot/dts/imx35-pdk.dts b/arch/arm/boot/dts/imx35-pdk.dts
index 9bb628f22502..646b1257bba2 100644
--- a/arch/arm/boot/dts/imx35-pdk.dts
+++ b/arch/arm/boot/dts/imx35-pdk.dts
@@ -17,7 +17,7 @@
         model = "Freescale i.MX35 Product Development Kit";
         compatible = "fsl,imx35-pdk", "fsl,imx35";
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x8000000>,
                       <0x90000000 0x8000000>;
         };
diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi
index e08c0c193767..bf343195697e 100644
--- a/arch/arm/boot/dts/imx35.dtsi
+++ b/arch/arm/boot/dts/imx35.dtsi
@@ -20,7 +20,7 @@
          * Also for U-Boot there must be a pre-existing /memory node.
          */
         chosen {};
-        memory { device_type = "memory"; reg = <0 0>; };
+        memory { device_type = "memory"; };
 
         aliases {
                 ethernet0 = &fec;
diff --git a/arch/arm/boot/dts/imx50-evk.dts b/arch/arm/boot/dts/imx50-evk.dts
index 98b5faa06e27..23f1833e23fa 100644
--- a/arch/arm/boot/dts/imx50-evk.dts
+++ b/arch/arm/boot/dts/imx50-evk.dts
@@ -18,7 +18,7 @@
         model = "Freescale i.MX50 Evaluation Kit";
         compatible = "fsl,imx50-evk", "fsl,imx50";
 
-        memory {
+        memory@70000000 {
                 reg = <0x70000000 0x80000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi
index 35955e63d6c5..7954e79d0a16 100644
--- a/arch/arm/boot/dts/imx50.dtsi
+++ b/arch/arm/boot/dts/imx50.dtsi
@@ -25,7 +25,7 @@
          * Also for U-Boot there must be a pre-existing /memory node.
          */
         chosen {};
-        memory { device_type = "memory"; reg = <0 0>; };
+        memory { device_type = "memory"; };
 
         aliases {
                 ethernet0 = &fec;
diff --git a/arch/arm/boot/dts/imx51-apf51.dts b/arch/arm/boot/dts/imx51-apf51.dts
index c83ac1600322..79d80036f74d 100644
--- a/arch/arm/boot/dts/imx51-apf51.dts
+++ b/arch/arm/boot/dts/imx51-apf51.dts
@@ -21,7 +21,7 @@
         model = "Armadeus Systems APF51 module";
         compatible = "armadeus,imx51-apf51", "fsl,imx51";
 
-        memory {
+        memory@90000000 {
                 reg = <0x90000000 0x20000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index 4ac5ab614a7f..cf7a1963df25 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -21,7 +21,7 @@
                 stdout-path = &uart1;
         };
 
-        memory {
+        memory@90000000 {
                 reg = <0x90000000 0x20000000>;
         };
 
@@ -369,6 +369,7 @@
         sgtl5000: codec@a {
                 compatible = "fsl,sgtl5000";
                 reg = <0x0a>;
+                #sound-dai-cells = <0>;
                 clocks = <&clk_audio>;
                 VDDA-supply = <&vdig_reg>;
                 VDDIO-supply = <&vvideo_reg>;
diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts b/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts
index 1db517d3d497..2967a748d859 100644
--- a/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts
+++ b/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts
@@ -17,7 +17,7 @@
                      "digi,connectcore-ccxmx51-som", "fsl,imx51";
 
         chosen {
-                linux,stdout-path = &uart1;
+                stdout-path = &uart1;
         };
 };
 
diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi
index b821066a0d2a..5761a66e8a0d 100644
--- a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi
+++ b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi
@@ -16,7 +16,7 @@
         model = "Digi ConnectCore CC(W)-MX51";
         compatible = "digi,connectcore-ccxmx51-som", "fsl,imx51";
 
-        memory {
+        memory@90000000 {
                 reg = <0x90000000 0x08000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi b/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi
index 63164266af83..f8902a338e49 100644
--- a/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi
+++ b/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi
@@ -22,7 +22,7 @@
         model = "Eukrea CPUIMX51";
         compatible = "eukrea,cpuimx51", "fsl,imx51";
 
-        memory {
+        memory@90000000 {
                 reg = <0x90000000 0x10000000>; /* 256M */
         };
 };
diff --git a/arch/arm/boot/dts/imx51-ts4800.dts b/arch/arm/boot/dts/imx51-ts4800.dts
index f59b02bae68d..39eb067904c3 100644
--- a/arch/arm/boot/dts/imx51-ts4800.dts
+++ b/arch/arm/boot/dts/imx51-ts4800.dts
@@ -17,7 +17,7 @@
                 stdout-path = &uart1;
         };
 
-        memory {
+        memory@90000000 {
                 reg = <0x90000000 0x10000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts
index 5306b78de0ca..0c99ac04ad08 100644
--- a/arch/arm/boot/dts/imx51-zii-rdu1.dts
+++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts
@@ -51,6 +51,11 @@
                 stdout-path = &uart1;
         };
 
+        /* Will be filled by the bootloader */
+        memory@90000000 {
+                reg = <0x90000000 0>;
+        };
+
         aliases {
                 mdio-gpio0 = &mdio_gpio;
                 rtc0 = &ds1341;
@@ -568,6 +573,15 @@
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart3>;
         status = "okay";
+
+        rave-sp {
+                compatible = "zii,rave-sp-rdu1";
+                current-speed = <38400>;
+
+                watchdog {
+                        compatible = "zii,rave-sp-watchdog";
+                };
+        };
 };
 
 &usbh1 {
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 00d30bd70068..5d390a64e976 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -26,7 +26,7 @@
          * Also for U-Boot there must be a pre-existing /memory node.
          */
         chosen {};
-        memory { device_type = "memory"; reg = <0 0>; };
+        memory { device_type = "memory"; };
 
         aliases {
                 ethernet0 = &fec;
diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts
index 4486bc47d140..80fc00705d92 100644
--- a/arch/arm/boot/dts/imx53-ard.dts
+++ b/arch/arm/boot/dts/imx53-ard.dts
@@ -17,7 +17,7 @@
         model = "Freescale i.MX53 Automotive Reference Design Board";
         compatible = "fsl,imx53-ard", "fsl,imx53";
 
-        memory {
+        memory@70000000 {
                 reg = <0x70000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx53-cx9020.dts b/arch/arm/boot/dts/imx53-cx9020.dts
index 5e67e43004e7..cf70ebc4399a 100644
--- a/arch/arm/boot/dts/imx53-cx9020.dts
+++ b/arch/arm/boot/dts/imx53-cx9020.dts
@@ -21,7 +21,7 @@
                 stdout-path = &uart2;
         };
 
-        memory {
+        memory@70000000 {
                 reg = <0x70000000 0x20000000>,
                       <0xb0000000 0x20000000>;
         };
diff --git a/arch/arm/boot/dts/imx53-m53.dtsi b/arch/arm/boot/dts/imx53-m53.dtsi
index 7ce69c63510c..3da6dd5edb79 100644
--- a/arch/arm/boot/dts/imx53-m53.dtsi
+++ b/arch/arm/boot/dts/imx53-m53.dtsi
@@ -15,7 +15,7 @@
         model = "Aries/DENX M53";
         compatible = "aries,imx53-m53", "denx,imx53-m53", "fsl,imx53";
 
-        memory {
+        memory@70000000 {
                 reg = <0x70000000 0x20000000>,
                       <0xb0000000 0x20000000>;
         };
diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/imx53-m53evk.dts
index e48525763b1b..3935fe6490ed 100644
--- a/arch/arm/boot/dts/imx53-m53evk.dts
+++ b/arch/arm/boot/dts/imx53-m53evk.dts
@@ -153,6 +153,7 @@
         sgtl5000: codec@a {
                 compatible = "fsl,sgtl5000";
                 reg = <0x0a>;
+                #sound-dai-cells = <0>;
                 VDDA-supply = <&reg_3p2v>;
                 VDDIO-supply = <&reg_3p2v>;
                 clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
diff --git a/arch/arm/boot/dts/imx53-ppd.dts b/arch/arm/boot/dts/imx53-ppd.dts
index cce959438a79..d5628af2e301 100644
--- a/arch/arm/boot/dts/imx53-ppd.dts
+++ b/arch/arm/boot/dts/imx53-ppd.dts
@@ -132,6 +132,14 @@
                 enable-active-high;
         };
 
+        reg_tsiref: regulator-tsiref {
+                compatible = "regulator-fixed";
+                regulator-name = "tsiref";
+                regulator-min-microvolt = <2500000>;
+                regulator-max-microvolt = <2500000>;
+                regulator-always-on;
+        };
+
         pwm_bl: backlight {
                 compatible = "pwm-backlight";
                 pwms = <&pwm2 0 50000>;
@@ -294,6 +302,8 @@
                 interrupt-parent = <&gpio3>;
                 interrupts = <12 0x8>;
                 spi-max-frequency = <1000000>;
+                dlg,tsi-as-adc;
+                tsiref-supply = <&reg_tsiref>;
 
                 regulators {
                         buck1_reg: buck1 {
@@ -436,6 +446,7 @@
                         sgtl5000: codec@a {
                                 compatible = "fsl,sgtl5000";
                                 reg = <0xa>;
+                                #sound-dai-cells = <0>;
                                 VDDA-supply = <&reg_sgtl5k>;
                                 VDDIO-supply = <&reg_sgtl5k>;
                                 clocks = <&cko2_11M>;
@@ -525,6 +536,7 @@
 
         touchscreen@4b {
                 compatible = "atmel,maxtouch";
+                reset-gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>;
                 reg = <0x4b>;
                 interrupt-parent = <&gpio5>;
                 interrupts = <4 0x8>;
diff --git a/arch/arm/boot/dts/imx53-qsb-common.dtsi b/arch/arm/boot/dts/imx53-qsb-common.dtsi
index 41a2e2a2b079..485a69d45e1c 100644
--- a/arch/arm/boot/dts/imx53-qsb-common.dtsi
+++ b/arch/arm/boot/dts/imx53-qsb-common.dtsi
@@ -17,7 +17,7 @@
                 stdout-path = &uart1;
         };
 
-        memory {
+        memory@70000000 {
                 reg = <0x70000000 0x20000000>,
                       <0xb0000000 0x20000000>;
         };
@@ -317,6 +317,7 @@
         sgtl5000: codec@a {
                 compatible = "fsl,sgtl5000";
                 reg = <0x0a>;
+                #sound-dai-cells = <0>;
                 VDDA-supply = <&reg_3p2v>;
                 VDDIO-supply = <&reg_3p2v>;
                 clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
index 51f4a42a55e2..fd030128666c 100644
--- a/arch/arm/boot/dts/imx53-smd.dts
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -17,7 +17,7 @@
         model = "Freescale i.MX53 Smart Mobile Reference Design Board";
         compatible = "fsl,imx53-smd", "fsl,imx53";
 
-        memory {
+        memory@70000000 {
                 reg = <0x70000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx53-tqma53.dtsi b/arch/arm/boot/dts/imx53-tqma53.dtsi
index eecdc1c55eef..a72b8981fc3b 100644
--- a/arch/arm/boot/dts/imx53-tqma53.dtsi
+++ b/arch/arm/boot/dts/imx53-tqma53.dtsi
@@ -16,7 +16,7 @@
         model = "TQ TQMa53";
         compatible = "tq,tqma53", "fsl,imx53";
 
-        memory {
+        memory@70000000 {
                 reg = <0x70000000 0x40000000>; /* Up to 1GiB */
         };
 
diff --git a/arch/arm/boot/dts/imx53-tx53-x03x.dts b/arch/arm/boot/dts/imx53-tx53-x03x.dts
index fe15c9555d6e..af8ec5e4417b 100644
--- a/arch/arm/boot/dts/imx53-tx53-x03x.dts
+++ b/arch/arm/boot/dts/imx53-tx53-x03x.dts
@@ -230,6 +230,7 @@
         sgtl5000: codec@a {
                 compatible = "fsl,sgtl5000";
                 reg = <0x0a>;
+                #sound-dai-cells = <0>;
                 VDDA-supply = <&reg_2v5>;
                 VDDIO-supply = <&reg_3v3>;
                 clocks = <&mclk>;
diff --git a/arch/arm/boot/dts/imx53-tx53-x13x.dts b/arch/arm/boot/dts/imx53-tx53-x13x.dts
index f2b2ad3ce9e5..6cdf2082c742 100644
--- a/arch/arm/boot/dts/imx53-tx53-x13x.dts
+++ b/arch/arm/boot/dts/imx53-tx53-x13x.dts
@@ -131,6 +131,7 @@
         sgtl5000: codec@a {
                 compatible = "fsl,sgtl5000";
                 reg = <0x0a>;
+                #sound-dai-cells = <0>;
                 VDDA-supply = <&reg_2v5>;
                 VDDIO-supply = <&reg_3v3>;
                 clocks = <&mclk>;
diff --git a/arch/arm/boot/dts/imx53-tx53.dtsi b/arch/arm/boot/dts/imx53-tx53.dtsi
index a22e461fc168..69a2af7d6c11 100644
--- a/arch/arm/boot/dts/imx53-tx53.dtsi
+++ b/arch/arm/boot/dts/imx53-tx53.dtsi
@@ -49,6 +49,11 @@
         model = "Ka-Ro electronics TX53 module";
         compatible = "karo,tx53", "fsl,imx53";
 
+        /* Will be filled by the bootloader */
+        memory@70000000 {
+                reg = <0x70000000 0>;
+        };
+
         aliases {
                 can0 = &can2; /* Make the can interface indices consistent with TX28/TX48 modules */
                 can1 = &can1;
diff --git a/arch/arm/boot/dts/imx53-usbarmory.dts b/arch/arm/boot/dts/imx53-usbarmory.dts
index 6782d7fc5961..f6268d0ded29 100644
--- a/arch/arm/boot/dts/imx53-usbarmory.dts
+++ b/arch/arm/boot/dts/imx53-usbarmory.dts
@@ -57,7 +57,7 @@
                 stdout-path = &uart1;
         };
 
-        memory {
+        memory@70000000 {
                 reg = <0x70000000 0x20000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx53-voipac-bsb.dts b/arch/arm/boot/dts/imx53-voipac-bsb.dts
index 25c78f19826c..957053755c3c 100644
--- a/arch/arm/boot/dts/imx53-voipac-bsb.dts
+++ b/arch/arm/boot/dts/imx53-voipac-bsb.dts
@@ -133,6 +133,7 @@
         sgtl5000: codec@a {
                 compatible = "fsl,sgtl5000";
                 reg = <0x0a>;
+                #sound-dai-cells = <0>;
                 VDDA-supply = <&reg_3p3v>;
                 VDDIO-supply = <&reg_3p3v>;
                 clocks = <&clks 150>;
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 1040251f2951..7d647d043f52 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -26,7 +26,7 @@
          * Also for U-Boot there must be a pre-existing /memory node.
          */
         chosen {};
-        memory { device_type = "memory"; reg = <0 0>; };
+        memory { device_type = "memory"; };
 
         aliases {
                 ethernet0 = &fec;
diff --git a/arch/arm/boot/dts/imx6dl-apf6dev.dts b/arch/arm/boot/dts/imx6dl-apf6dev.dts
index df26e542ab3a..4a7f86de6c39 100644
--- a/arch/arm/boot/dts/imx6dl-apf6dev.dts
+++ b/arch/arm/boot/dts/imx6dl-apf6dev.dts
@@ -54,7 +54,7 @@
         model = "Armadeus APF6 Solo Module on APF6Dev Board";
         compatible = "armadeus,imx6dl-apf6dev", "armadeus,imx6dl-apf6", "fsl,imx6dl";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x20000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts b/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts
index 5f0d196495d0..7128c76d5721 100644
--- a/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts
+++ b/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts
@@ -48,7 +48,7 @@
         model = "aristainetos2 i.MX6 Dual Lite Board 4";
         compatible = "fsl,imx6dl";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6dl-aristainetos2_7.dts b/arch/arm/boot/dts/imx6dl-aristainetos2_7.dts
index 805b1318b7f7..240f3661469f 100644
--- a/arch/arm/boot/dts/imx6dl-aristainetos2_7.dts
+++ b/arch/arm/boot/dts/imx6dl-aristainetos2_7.dts
@@ -48,7 +48,7 @@
         model = "aristainetos2 i.MX6 Dual Lite Board 7";
         compatible = "fsl,imx6dl";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts
index 3c9f4af9e9ff..ad7733662fe5 100644
--- a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts
+++ b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts
@@ -27,7 +27,7 @@
                 status = "okay";
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts
index 96cd835ccbf6..64ed84e3c512 100644
--- a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts
+++ b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts
@@ -16,7 +16,7 @@
         model = "aristainetos i.MX6 Dual Lite Board 7";
         compatible = "fsl,imx6dl";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
index dcf9206f3e0d..ea184d108491 100644
--- a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
@@ -53,6 +53,11 @@
         compatible = "toradex,colibri_imx6dl-eval-v3", "toradex,colibri_imx6dl",
                      "fsl,imx6dl";
 
+        /* Will be filled by the bootloader */
+        memory@10000000 {
+                reg = <0x10000000 0>;
+        };
+
         aliases {
                 i2c0 = &i2c2;
                 i2c1 = &i2c3;
@@ -63,6 +68,10 @@
                 rtc1 = &snvs_rtc;
         };
 
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+
         clocks {
                 /* Fixed crystal dedicated to mcp251x */
                 clk16m: clk@1 {
diff --git a/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts b/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts
index 994f96a3fb54..89384cb618f6 100644
--- a/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts
+++ b/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts
@@ -20,4 +20,9 @@
 / {
         model = "DFI FS700-M60-6DL i.MX6dl Q7 Board";
         compatible = "dfi,fs700-m60-6dl", "dfi,fs700e-m60", "fsl,imx6dl";
+
+        /* Will be filled by the bootloader */
+        memory@10000000 {
+                reg = <0x10000000 0>;
+        };
 };
diff --git a/arch/arm/boot/dts/imx6dl-icore-rqs.dts b/arch/arm/boot/dts/imx6dl-icore-rqs.dts
index cf42c2f5cdc7..1281bc39b7ab 100644
--- a/arch/arm/boot/dts/imx6dl-icore-rqs.dts
+++ b/arch/arm/boot/dts/imx6dl-icore-rqs.dts
@@ -42,7 +42,7 @@
 
 /dts-v1/;
 
-#include "imx6q.dtsi"
+#include "imx6dl.dtsi"
 #include "imx6qdl-icore-rqs.dtsi"
 
 / {
diff --git a/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts
new file mode 100644
index 000000000000..a8adcb2ec3fd
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-phytec-mira-rdk-nand.dts
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 PHYTEC Messtechnik GmbH
+ * Author: Christian Hemp <c.hemp@phytec.de>
+ */
+
+/dts-v1/;
+#include "imx6dl.dtsi"
+#include "imx6qdl-phytec-phycore-som.dtsi"
+#include "imx6qdl-phytec-mira.dtsi"
+
+/ {
+        model = "PHYTEC phyBOARD-Mira DualLite/Solo Carrier-Board with NAND";
+        compatible = "phytec,imx6dl-pbac06-nand", "phytec,imx6dl-pbac06",
+                     "phytec,imx6qdl-pcm058", "fsl,imx6dl";
+
+        chosen {
+                linux,stdout-path = &uart2;
+        };
+};
+
+&ethphy {
+        max-speed = <100>;
+};
+
+&fec {
+        status = "okay";
+};
+
+&gpmi {
+        status = "okay";
+};
+
+&hdmi {
+        status = "okay";
+};
+
+&i2c1 {
+        status = "okay";
+};
+
+&i2c2 {
+        status = "okay";
+};
+
+&i2c_rtc {
+        status = "okay";
+};
+
+&uart3 {
+        status = "okay";
+};
+
+&usbh1 {
+        status = "okay";
+};
+
+&usbotg {
+        status = "okay";
+};
+
+&usdhc1 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi
index 964bc2ad3c5d..7d9888937f12 100644
--- a/arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi
@@ -16,7 +16,7 @@
         model = "Phytec phyFLEX-i.MX6 DualLite/Solo";
         compatible = "phytec,imx6dl-pfla02", "fsl,imx6dl";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x20000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx6dl-rex-basic.dts b/arch/arm/boot/dts/imx6dl-rex-basic.dts
index c3a14a4330a2..3fb7f4ee2496 100644
--- a/arch/arm/boot/dts/imx6dl-rex-basic.dts
+++ b/arch/arm/boot/dts/imx6dl-rex-basic.dts
@@ -16,7 +16,7 @@
         model = "Rex Basic i.MX6 Dual Lite Board";
         compatible = "rex,imx6dl-rex-basic", "fsl,imx6dl";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x20000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts
index 23e108204e1e..2e98c92adff7 100644
--- a/arch/arm/boot/dts/imx6dl-riotboard.dts
+++ b/arch/arm/boot/dts/imx6dl-riotboard.dts
@@ -15,7 +15,7 @@
         model = "RIoTboard i.MX6S";
         compatible = "riot,imx6s-riotboard", "fsl,imx6dl";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6dl-ts4900.dts b/arch/arm/boot/dts/imx6dl-ts4900.dts
index 6ea0b780677d..cc01a7a22e30 100644
--- a/arch/arm/boot/dts/imx6dl-ts4900.dts
+++ b/arch/arm/boot/dts/imx6dl-ts4900.dts
@@ -46,4 +46,9 @@
 / {
         model = "Technologic Systems i.MX6 Solo/DualLite TS-4900 (Default Device Tree)";
         compatible = "technologic,imx6dl-ts4900", "fsl,imx6dl";
+
+        /* Will be filled by the bootloader */
+        memory@10000000 {
+                reg = <0x10000000 0>;
+        };
 };
diff --git a/arch/arm/boot/dts/imx6dl-ts7970.dts b/arch/arm/boot/dts/imx6dl-ts7970.dts
index d104daf305d9..82435d5bf33f 100644
--- a/arch/arm/boot/dts/imx6dl-ts7970.dts
+++ b/arch/arm/boot/dts/imx6dl-ts7970.dts
@@ -47,4 +47,9 @@
 / {
         model = "Technologic Systems i.MX6 Solo/DualLite TS-7970 (Default Device Tree)";
         compatible = "technologic,imx6dl-ts7970", "fsl,imx6dl";
+
+        /* Will be filled by the bootloader */
+        memory@10000000 {
+                reg = <0x10000000 0>;
+        };
 };
diff --git a/arch/arm/boot/dts/imx6dl-wandboard-revb1.dts b/arch/arm/boot/dts/imx6dl-wandboard-revb1.dts
index 8c314eee4fdd..5727fa48cfd5 100644
--- a/arch/arm/boot/dts/imx6dl-wandboard-revb1.dts
+++ b/arch/arm/boot/dts/imx6dl-wandboard-revb1.dts
@@ -16,7 +16,7 @@
         model = "Wandboard i.MX6 Dual Lite Board rev B1";
         compatible = "wand,imx6dl-wandboard", "fsl,imx6dl";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx6dl-wandboard-revd1.dts b/arch/arm/boot/dts/imx6dl-wandboard-revd1.dts
index aa4d4faaaec4..a72c07db7dda 100644
--- a/arch/arm/boot/dts/imx6dl-wandboard-revd1.dts
+++ b/arch/arm/boot/dts/imx6dl-wandboard-revd1.dts
@@ -16,7 +16,7 @@
         model = "Wandboard i.MX6 Dual Lite Board revD1";
         compatible = "wand,imx6dl-wandboard", "fsl,imx6dl";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx6dl-wandboard.dts b/arch/arm/boot/dts/imx6dl-wandboard.dts
index bbb616723097..a09f274cd1f4 100644
--- a/arch/arm/boot/dts/imx6dl-wandboard.dts
+++ b/arch/arm/boot/dts/imx6dl-wandboard.dts
@@ -16,7 +16,7 @@
         model = "Wandboard i.MX6 Dual Lite Board";
         compatible = "wand,imx6dl-wandboard", "fsl,imx6dl";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index c01674fa098a..558bce81209d 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -80,11 +80,6 @@
                                 reg = <0x020f4000 0x4000>;
                                 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
                         };
-
-                        lcdif: lcdif@20f8000 {
-                                reg = <0x020f8000 0x4000>;
-                                interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
-                        };
                 };
 
                 aips2: aips-bus@2100000 {
@@ -109,11 +104,6 @@
                 compatible = "fsl,imx-display-subsystem";
                 ports = <&ipu1_di0>, <&ipu1_di1>;
         };
-
-        gpu-subsystem {
-                compatible = "fsl,imx-gpu-subsystem";
-                cores = <&gpu_2d>, <&gpu_3d>;
-        };
 };
 
 &gpio1 {
diff --git a/arch/arm/boot/dts/imx6q-apf6dev.dts b/arch/arm/boot/dts/imx6q-apf6dev.dts
index 4e4de821d9e5..5e72f81cdf8b 100644
--- a/arch/arm/boot/dts/imx6q-apf6dev.dts
+++ b/arch/arm/boot/dts/imx6q-apf6dev.dts
@@ -54,7 +54,7 @@
         model = "Armadeus APF6 Quad / Dual Module on APF6Dev Board";
         compatible = "armadeus,imx6q-apf6dev", "armadeus,imx6q-apf6", "fsl,imx6q";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index 4989d0bff10f..953a5b5a8ea4 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -18,7 +18,7 @@
         model = "Freescale i.MX6 Quad Armadillo2 Board";
         compatible = "fsl,imx6q-arm2", "fsl,imx6q";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x80000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6q-ba16.dtsi b/arch/arm/boot/dts/imx6q-ba16.dtsi
index 5fcb0372d58b..bf4bdb385de9 100644
--- a/arch/arm/boot/dts/imx6q-ba16.dtsi
+++ b/arch/arm/boot/dts/imx6q-ba16.dtsi
@@ -46,7 +46,7 @@
 #include <dt-bindings/gpio/gpio.h>
 
 / {
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/imx6q-bx50v3.dtsi
index 916ea94d75ca..990e411cbca0 100644
--- a/arch/arm/boot/dts/imx6q-bx50v3.dtsi
+++ b/arch/arm/boot/dts/imx6q-bx50v3.dtsi
@@ -353,6 +353,14 @@
         };
 };
 
+&pmu {
+        secure-reg-access;
+};
+
+&usdhc2 {
+        status = "disabled";
+};
+
 &usdhc4 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_usdhc4>;
diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts
index bc7587c383f6..65ef4cacbc71 100644
--- a/arch/arm/boot/dts/imx6q-cm-fx6.dts
+++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts
@@ -50,7 +50,7 @@
         model = "CompuLab CM-FX6";
         compatible = "compulab,cm-fx6", "fsl,imx6q";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x80000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts b/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts
index fd0ad9a8866c..ad12d76bbb89 100644
--- a/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts
+++ b/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts
@@ -20,4 +20,9 @@
 / {
         model = "DFI FS700-M60-6QD i.MX6qd Q7 Board";
         compatible = "dfi,fs700-m60-6qd", "dfi,fs700e-m60", "fsl,imx6q";
+
+        /* Will be filled by the bootloader */
+        memory@10000000 {
+                reg = <0x10000000 0>;
+        };
 };
diff --git a/arch/arm/boot/dts/imx6q-display5.dtsi b/arch/arm/boot/dts/imx6q-display5.dtsi
index 09085fde3341..85232c7c36a0 100644
--- a/arch/arm/boot/dts/imx6q-display5.dtsi
+++ b/arch/arm/boot/dts/imx6q-display5.dtsi
@@ -47,7 +47,7 @@
         model = "Liebherr (LWN) display5 i.MX6 Quad Board";
         compatible = "lwn,display5", "fsl,imx6q";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
index f0316ea96898..b3c6a4a7897d 100644
--- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
+++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
@@ -29,7 +29,7 @@
                 stmpe-i2c1 = &stmpe2;
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x80000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6q-dms-ba16.dts b/arch/arm/boot/dts/imx6q-dms-ba16.dts
new file mode 100644
index 000000000000..57761f3172fa
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-dms-ba16.dts
@@ -0,0 +1,139 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include "imx6q-ba16.dtsi"
+
+/ {
+        model = "Advantech DMS-BA16";
+        compatible = "advantech,imx6q-dms-ba16", "advantech,imx6q-ba16", "fsl,imx6q";
+
+        reg_usb_otg_vbus: regulator-usbotgvbus {
+                compatible = "regulator-fixed";
+                regulator-name = "usb_otg_vbus";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_usbotgvbus>;
+                gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+        };
+
+        sys_mclk: clock-sys-mclk {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <22000000>;
+        };
+
+        sound {
+                compatible = "fsl,imx6q-ba16-sgtl5000",
+                             "fsl,imx-audio-sgtl5000";
+                model = "imx6q-ba16-sgtl5000";
+                ssi-controller = <&ssi1>;
+                audio-codec = <&sgtl5000>;
+                audio-routing =
+                        "MIC_IN", "Mic Jack",
+                        "Mic Jack", "Mic Bias",
+                        "Headphone Jack", "HP_OUT";
+                mux-int-port = <1>;
+                mux-ext-port = <4>;
+        };
+};
+
+&ecspi5 {
+        cs-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ecspi5>;
+        status = "okay";
+
+        m25_eeprom: m25p80@0 {
+                compatible = "atmel,at25256B", "atmel,at25";
+                spi-max-frequency = <20000000>;
+                size = <0x8000>;
+                pagesize = <64>;
+                reg = <0>;
+                address-width = <16>;
+        };
+};
+
+&iomuxc {
+        pinctrl_i2c1_gpio: i2c1gpiogrp {
+                fsl,pins = <
+                        MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26        0x1b0b0
+                        MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27        0x1b0b0
+                >;
+        };
+
+        pinctrl_i2c2_gpio: i2c2gpiogrp {
+                fsl,pins = <
+                        MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0
+                        MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0
+                >;
+        };
+
+        pinctrl_i2c3_gpio: i2c3gpiogrp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_3__GPIO1_IO03   0x1b0b0
+                        MX6QDL_PAD_GPIO_6__GPIO1_IO06   0x1b0b0
+                >;
+        };
+
+        pinctrl_usbotgvbus: usbotgvbusgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
+                        MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0
+                >;
+        };
+};
+
+&i2c1 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1>;
+        status = "okay";
+
+        sgtl5000: codec@a {
+                compatible = "fsl,sgtl5000";
+                reg = <0x0a>;
+                clocks = <&sys_mclk>;
+                lrclk-strength = <0x3>;
+                VDDA-supply = <&reg_1p8v>;
+                VDDIO-supply = <&reg_3p3v>;
+        };
+};
+
+&pwm2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm2>;
+        status = "okay";
+};
+
+&sata {
+        fsl,no-spread-spectrum;
+        fsl,transmit-atten-16ths = <12>;
+        fsl,transmit-boost-mdB = <3330>;
+        fsl,transmit-level-mV = <1133>;
+        fsl,receive-dpll-mode = <1>;
+        status = "okay";
+};
+
+&usbotg {
+        vbus-supply = <&reg_usb_otg_vbus>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbotg>;
+        dr_mode = "otg";
+        disable-over-current;
+        status = "okay";
+};
+
+&usdhc4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc4>;
+        bus-width = <8>;
+        cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
+        no-1-8-v;
+        keep-power-in-suspend;
+        wakeup-source;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts
index e0aea782c666..fcd257bc5ac3 100644
--- a/arch/arm/boot/dts/imx6q-evi.dts
+++ b/arch/arm/boot/dts/imx6q-evi.dts
@@ -50,7 +50,7 @@
         model = "Uniwest Evi";
         compatible = "uniwest,imx6q-evi", "fsl,imx6q";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6q-gk802.dts b/arch/arm/boot/dts/imx6q-gk802.dts
index b715deb4ea46..0be375611382 100644
--- a/arch/arm/boot/dts/imx6q-gk802.dts
+++ b/arch/arm/boot/dts/imx6q-gk802.dts
@@ -18,7 +18,7 @@
                 stdout-path = &uart4;
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts
index 29adaa7c72f8..a8f70b4266ef 100644
--- a/arch/arm/boot/dts/imx6q-gw5400-a.dts
+++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts
@@ -60,7 +60,7 @@
                 };
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6q-h100.dts b/arch/arm/boot/dts/imx6q-h100.dts
index 8a2ea6c58902..714e09e04dcb 100644
--- a/arch/arm/boot/dts/imx6q-h100.dts
+++ b/arch/arm/boot/dts/imx6q-h100.dts
@@ -49,6 +49,11 @@
         model = "Auvidea H100";
         compatible = "auvidea,h100", "fsl,imx6q";
 
+        /* Will be filled by the bootloader */
+        memory@10000000 {
+                reg = <0x10000000 0>;
+        };
+
         aliases {
                 rtc0 = &rtc;
                 rtc1 = &snvs_rtc;
@@ -161,7 +166,7 @@
         status = "okay";
 
         eeprom: 24c02@51 {
-                compatible = "microchip,24c02", "at24";
+                compatible = "microchip,24c02", "atmel,24c02";
                 reg = <0x51>;
         };
 
diff --git a/arch/arm/boot/dts/imx6q-marsboard.dts b/arch/arm/boot/dts/imx6q-marsboard.dts
index 432291bedcf1..dd763f205819 100644
--- a/arch/arm/boot/dts/imx6q-marsboard.dts
+++ b/arch/arm/boot/dts/imx6q-marsboard.dts
@@ -47,7 +47,7 @@
         model = "Embest MarS Board i.MX6Dual";
         compatible = "embest,imx6q-marsboard", "fsl,imx6q";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6q-mccmon6.dts b/arch/arm/boot/dts/imx6q-mccmon6.dts
index cab36f48d5f1..b7e9f38cec72 100644
--- a/arch/arm/boot/dts/imx6q-mccmon6.dts
+++ b/arch/arm/boot/dts/imx6q-mccmon6.dts
@@ -19,7 +19,7 @@
         model = "Liebherr (LWN) monitor6 i.MX6 Quad Board";
         compatible = "lwn,mccmon6", "fsl,imx6q";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x80000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6q-novena.dts b/arch/arm/boot/dts/imx6q-novena.dts
index 7d7dc59507cf..52f39371188d 100644
--- a/arch/arm/boot/dts/imx6q-novena.dts
+++ b/arch/arm/boot/dts/imx6q-novena.dts
@@ -55,6 +55,11 @@
         model = "Kosagi Novena Dual/Quad";
         compatible = "kosagi,imx6q-novena", "fsl,imx6q";
 
+        /* Will be filled by the bootloader */
+        memory@10000000 {
+                reg = <0x10000000 0>;
+        };
+
         chosen {
                 stdout-path = &uart2;
         };
diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts
new file mode 100644
index 000000000000..8fdce3c8e5fa
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-emmc.dts
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 PHYTEC Messtechnik GmbH
+ * Author: Christian Hemp <c.hemp@phytec.de>
+ */
+
+/dts-v1/;
+#include "imx6q.dtsi"
+#include "imx6qdl-phytec-phycore-som.dtsi"
+#include "imx6qdl-phytec-mira.dtsi"
+
+/ {
+        model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with eMMC";
+        compatible = "phytec,imx6q-pbac06-emmc", "phytec,imx6q-pbac06",
+                     "phytec,imx6qdl-pcm058", "fsl,imx6q";
+
+        chosen {
+                linux,stdout-path = &uart2;
+        };
+};
+
+&can1 {
+        status = "okay";
+};
+
+&fec {
+        status = "okay";
+};
+
+&hdmi {
+        status = "okay";
+};
+
+&i2c1 {
+        status = "okay";
+};
+
+&i2c2 {
+        status = "okay";
+};
+
+&i2c_rtc {
+        status = "okay";
+};
+
+&m25p80 {
+        status = "okay";
+};
+
+&pcie {
+        status = "okay";
+};
+
+&uart3 {
+        status = "okay";
+};
+
+&usbh1 {
+        status = "okay";
+};
+
+&usbotg {
+        status = "okay";
+};
+
+&usdhc1 {
+        status = "okay";
+};
+
+&usdhc4 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts
new file mode 100644
index 000000000000..8afa5ceb7d7c
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-phytec-mira-rdk-nand.dts
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 PHYTEC Messtechnik GmbH
+ * Author: Christian Hemp <c.hemp@phytec.de>
+ */
+
+/dts-v1/;
+#include "imx6q.dtsi"
+#include "imx6qdl-phytec-phycore-som.dtsi"
+#include "imx6qdl-phytec-mira.dtsi"
+
+/ {
+        model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with NAND";
+        compatible = "phytec,imx6q-pbac06-nand", "phytec,imx6q-pbac06",
+                     "phytec,imx6qdl-pcm058", "fsl,imx6q";
+
+        chosen {
+                linux,stdout-path = &uart2;
+        };
+};
+
+&can1 {
+        status = "okay";
+};
+
+&fec {
+        status = "okay";
+};
+
+&gpmi {
+        status = "okay";
+};
+
+&hdmi {
+        status = "okay";
+};
+
+&i2c1 {
+        status = "okay";
+};
+
+&i2c2 {
+        status = "okay";
+};
+
+&i2c_rtc {
+        status = "okay";
+};
+
+&m25p80 {
+        status = "okay";
+};
+
+&pcie {
+        status = "okay";
+};
+
+&uart3 {
+        status = "okay";
+};
+
+&usbh1 {
+        status = "okay";
+};
+
+&usbotg {
+        status = "okay";
+};
+
+&usdhc1 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
index cd20d0a948de..fad858c30fe9 100644
--- a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
@@ -16,7 +16,7 @@
         model = "Phytec phyFLEX-i.MX6 Quad";
         compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x80000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx6q-pistachio.dts b/arch/arm/boot/dts/imx6q-pistachio.dts
index 1effb58f304c..bd57b3b74db7 100644
--- a/arch/arm/boot/dts/imx6q-pistachio.dts
+++ b/arch/arm/boot/dts/imx6q-pistachio.dts
@@ -56,7 +56,7 @@
                 stdout-path = &uart4;
         };
 
-        memory: memory {
+        memory@10000000 {
                 reg = <0x10000000 0x80000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6q-rex-pro.dts b/arch/arm/boot/dts/imx6q-rex-pro.dts
index 90ea61ae04e9..d6cae73b1927 100644
--- a/arch/arm/boot/dts/imx6q-rex-pro.dts
+++ b/arch/arm/boot/dts/imx6q-rex-pro.dts
@@ -16,7 +16,7 @@
         model = "Rex Pro i.MX6 Quad Board";
         compatible = "rex,imx6q-rex-pro", "fsl,imx6q";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x80000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx6q-sbc6x.dts b/arch/arm/boot/dts/imx6q-sbc6x.dts
index 255733063ea4..b7aa2f0b9f53 100644
--- a/arch/arm/boot/dts/imx6q-sbc6x.dts
+++ b/arch/arm/boot/dts/imx6q-sbc6x.dts
@@ -12,7 +12,7 @@
         model = "MicroSys sbc6x board";
         compatible = "microsys,sbc6x", "fsl,imx6q";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x80000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx6q-tbs2910.dts b/arch/arm/boot/dts/imx6q-tbs2910.dts
index a3cd7afac20a..505cba776a2d 100644
--- a/arch/arm/boot/dts/imx6q-tbs2910.dts
+++ b/arch/arm/boot/dts/imx6q-tbs2910.dts
@@ -59,7 +59,7 @@
                 stdout-path = &uart1;
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x80000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6q-ts4900.dts b/arch/arm/boot/dts/imx6q-ts4900.dts
index fab76f8cd076..e655107edc56 100644
--- a/arch/arm/boot/dts/imx6q-ts4900.dts
+++ b/arch/arm/boot/dts/imx6q-ts4900.dts
@@ -46,6 +46,11 @@
 / {
         model = "Technologic Systems i.MX6 Quad TS-4900 (Default Device Tree)";
         compatible = "technologic,imx6q-ts4900", "fsl,imx6q";
+
+        /* Will be filled by the bootloader */
+        memory@10000000 {
+                reg = <0x10000000 0>;
+        };
 };
 
 &sata {
diff --git a/arch/arm/boot/dts/imx6q-ts7970.dts b/arch/arm/boot/dts/imx6q-ts7970.dts
index f19e18995e68..c615ac4feede 100644
--- a/arch/arm/boot/dts/imx6q-ts7970.dts
+++ b/arch/arm/boot/dts/imx6q-ts7970.dts
@@ -47,6 +47,11 @@
 / {
         model = "Technologic Systems i.MX6 Quad TS-7970 (Default Device Tree)";
         compatible = "technologic,imx6q-ts7970", "fsl,imx6q";
+
+        /* Will be filled by the bootloader */
+        memory@10000000 {
+                reg = <0x10000000 0>;
+        };
 };
 
 &sata {
diff --git a/arch/arm/boot/dts/imx6q-wandboard-revb1.dts b/arch/arm/boot/dts/imx6q-wandboard-revb1.dts
index 9207d80f9cfb..b763352cddae 100644
--- a/arch/arm/boot/dts/imx6q-wandboard-revb1.dts
+++ b/arch/arm/boot/dts/imx6q-wandboard-revb1.dts
@@ -16,7 +16,7 @@
         model = "Wandboard i.MX6 Quad Board rev B1";
         compatible = "wand,imx6q-wandboard", "fsl,imx6q";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x80000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx6q-wandboard-revd1.dts b/arch/arm/boot/dts/imx6q-wandboard-revd1.dts
index e87ddb168669..8691fab21058 100644
--- a/arch/arm/boot/dts/imx6q-wandboard-revd1.dts
+++ b/arch/arm/boot/dts/imx6q-wandboard-revd1.dts
@@ -16,7 +16,7 @@
         model = "Wandboard i.MX6 Quad Board revD1";
         compatible = "wand,imx6q-wandboard", "fsl,imx6q";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x80000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx6q-wandboard.dts b/arch/arm/boot/dts/imx6q-wandboard.dts
index 4a8a6ee13e9f..2a3d98c1489a 100644
--- a/arch/arm/boot/dts/imx6q-wandboard.dts
+++ b/arch/arm/boot/dts/imx6q-wandboard.dts
@@ -16,7 +16,7 @@
         model = "Wandboard i.MX6 Quad Board";
         compatible = "wand,imx6q-wandboard", "fsl,imx6q";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x80000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx6q-zii-rdu2.dts b/arch/arm/boot/dts/imx6q-zii-rdu2.dts
index 6be8a1eea895..7da6dde9c857 100644
--- a/arch/arm/boot/dts/imx6q-zii-rdu2.dts
+++ b/arch/arm/boot/dts/imx6q-zii-rdu2.dts
@@ -47,4 +47,9 @@
 / {
         model = "ZII RDU2 Board";
         compatible = "zii,imx6q-zii-rdu2", "fsl,imx6q";
+
+        /* Will be filled by the bootloader */
+        memory@10000000 {
+                reg = <0x10000000 0>;
+        };
 };
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index bc581aa5cf17..ae7b3f107893 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -215,11 +215,6 @@
                 compatible = "fsl,imx-display-subsystem";
                 ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
         };
-
-        gpu-subsystem {
-                compatible = "fsl,imx-gpu-subsystem";
-                cores = <&gpu_2d>, <&gpu_3d>, <&gpu_vg>;
-        };
 };
 
 &gpio1 {
diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
index 4e776e036cbc..8206683172d2 100644
--- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
@@ -47,6 +47,11 @@
         model = "Toradex Apalis iMX6Q/D Module";
         compatible = "toradex,apalis_imx6q", "fsl,imx6q";
 
+        /* Will be filled by the bootloader */
+        memory@10000000 {
+                reg = <0x10000000 0>;
+        };
+
         backlight: backlight {
                 compatible = "pwm-backlight";
                 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
index d1cfdc264126..9332a31e6c8b 100644
--- a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
@@ -42,6 +42,11 @@
 #include <dt-bindings/gpio/gpio.h>
 
 / {
+        /* Will be filled by the bootloader */
+        memory@10000000 {
+                reg = <0x10000000 0>;
+        };
+
         ir_recv: ir-receiver {
                 compatible = "gpio-ir-receiver";
                 gpios = <&gpio3 9 1>;
diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
index dea8fc43c692..17a7b9c083d0 100644
--- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
@@ -44,7 +44,7 @@
                 };
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x20000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
index 363a44394dad..b8044681006c 100644
--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
@@ -59,7 +59,7 @@
                 };
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x20000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
index c75385c0cad0..629908fbaa32 100644
--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
@@ -59,7 +59,7 @@
                 };
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
index eab75f3dbaf3..a1a6fb5541e1 100644
--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
@@ -59,7 +59,7 @@
                 };
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
index 30d4662d4480..4e21b3849394 100644
--- a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
@@ -74,7 +74,7 @@
                 };
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x20000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
index c67c10605070..81dae5b5bc87 100644
--- a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
@@ -51,7 +51,7 @@
                 };
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x20000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6qdl-gw553x.dtsi b/arch/arm/boot/dts/imx6qdl-gw553x.dtsi
index 1a0faa1a14c8..c5d95e8d2e09 100644
--- a/arch/arm/boot/dts/imx6qdl-gw553x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw553x.dtsi
@@ -80,7 +80,7 @@
                 };
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x20000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6qdl-gw560x.dtsi b/arch/arm/boot/dts/imx6qdl-gw560x.dtsi
index d894dde6e85d..b5986efe1090 100644
--- a/arch/arm/boot/dts/imx6qdl-gw560x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw560x.dtsi
@@ -288,6 +288,7 @@
         sgtl5000: codec@a {
                 compatible = "fsl,sgtl5000";
                 reg = <0x0a>;
+                #sound-dai-cells = <0>;
                 clocks = <&clks IMX6QDL_CLK_CKO>;
                 VDDA-supply = <&reg_1p8v>;
                 VDDIO-supply = <&reg_3p3v>;
diff --git a/arch/arm/boot/dts/imx6qdl-gw5903.dtsi b/arch/arm/boot/dts/imx6qdl-gw5903.dtsi
index 444425153fc7..368132274a91 100644
--- a/arch/arm/boot/dts/imx6qdl-gw5903.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw5903.dtsi
@@ -83,7 +83,7 @@
                 };
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6qdl-gw5904.dtsi b/arch/arm/boot/dts/imx6qdl-gw5904.dtsi
index fd4b68be9fe9..58124adfd65b 100644
--- a/arch/arm/boot/dts/imx6qdl-gw5904.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw5904.dtsi
@@ -93,7 +93,7 @@
                 };
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi
index 92583238ca4a..7e20b47de839 100644
--- a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi
@@ -40,6 +40,11 @@
  */
 
 / {
+        /* Will be filled by the bootloader */
+        memory@10000000 {
+                reg = <0x10000000 0>;
+        };
+
         chosen {
                 stdout-path = &uart1;
         };
@@ -239,10 +244,9 @@
 
                 pinctrl_hummingboard_usbotg_id: hummingboard-usbotg-id {
                         /*
-                         * Similar to pinctrl_usbotg_2, but we want it
-                         * pulled down for a fixed host connection.
+                         * We want it pulled down for a fixed host connection.
                          */
-                        fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
+                        fsl,pins = <MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x13059>;
                 };
 
                 pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus {
diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi
index dffbc92e0023..98241acb08a6 100644
--- a/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi
@@ -40,6 +40,11 @@
  */
 
 / {
+        /* Will be filled by the bootloader */
+        memory@10000000 {
+                reg = <0x10000000 0>;
+        };
+
         chosen {
                 stdout-path = &uart1;
         };
@@ -191,6 +196,7 @@
         sgtl5000: codec@a {
                 clocks = <&clks IMX6QDL_CLK_CKO>;
                 compatible = "fsl,sgtl5000";
+                #sound-dai-cells = <0>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&pinctrl_hummingboard2_sgtl5000>;
                 reg = <0x0a>;
@@ -409,8 +415,7 @@
 
                 pinctrl_hummingboard2_usbotg_id: hummingboard2-usbotg-id {
                         /*
-                         * Similar to pinctrl_usbotg_2, but we want it
-                         * pulled down for a fixed host connection.
+                         * We want it pulled down for a fixed host connection.
                          */
                         fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
                 };
diff --git a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
index b6220d62f6de..acc3b11fba2a 100644
--- a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
@@ -44,7 +44,7 @@
 #include <dt-bindings/sound/fsl-imx-audmux.h>
 
 / {
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x80000000>;
         };
 
@@ -200,7 +200,11 @@
         status = "okay";
 
         mdio {
-                eth_phy: ethernet-phy {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                eth_phy: ethernet-phy@0 {
+                        reg = <0x0>;
                         rxc-skew-ps = <1140>;
                         txc-skew-ps = <1140>;
                         txen-skew-ps = <600>;
diff --git a/arch/arm/boot/dts/imx6qdl-icore.dtsi b/arch/arm/boot/dts/imx6qdl-icore.dtsi
index a1b469c142f1..b3a463a5908b 100644
--- a/arch/arm/boot/dts/imx6qdl-icore.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-icore.dtsi
@@ -45,7 +45,7 @@
 #include <dt-bindings/sound/fsl-imx-audmux.h>
 
 / {
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x80000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
index 4cc4e23cf99c..aab088f318e8 100644
--- a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
@@ -46,7 +46,7 @@
                 stdout-path = &uart2;
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x20000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
index fd05f7caa472..87ca6ead4098 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
@@ -46,7 +46,7 @@
                 stdout-path = &uart2;
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0xF0000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
index 40942d6b94b3..f5b763d39285 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
@@ -46,7 +46,7 @@
                 stdout-path = &uart2;
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
index 919b6b7619a4..596866b0a0d2 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
@@ -48,7 +48,7 @@
                 stdout-path = &uart2;
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi
new file mode 100644
index 000000000000..9ebd438dce7d
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi
@@ -0,0 +1,390 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 PHYTEC Messtechnik GmbH
+ * Author: Christian Hemp <c.hemp@phytec.de>
+ */
+
+
+/ {
+        aliases {
+                rtc0 = &i2c_rtc;
+        };
+
+        backlight: backlight {
+                compatible = "pwm-backlight";
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <7>;
+                power-supply = <&reg_backlight>;
+                pwms = <&pwm1 0 5000000>;
+                status = "okay";
+        };
+
+        gpio_leds: leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_gpioleds>;
+                status = "disabled";
+
+                red {
+                        label = "phyboard-mira:red";
+                        gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>;
+                };
+
+                green {
+                        label = "phyboard-mira:green";
+                        gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>;
+                };
+
+                blue {
+                        label = "phyboard-mira:blue";
+                        gpios = <&gpio5 24 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "mmc0";
+                };
+        };
+
+        reg_backlight: regulator-backlight {
+                compatible = "regulator-fixed";
+                regulator-name = "backlight_3v3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+        };
+
+        reg_en_switch: regulator-en-switch {
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_en_switch>;
+                regulator-name = "Enable Switch";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                enable-active-high;
+                gpio = <&gpio3 4 GPIO_ACTIVE_HIGH>;
+                regulator-always-on;
+        };
+
+        reg_flexcan1: regulator-flexcan1 {
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_flexcan1_en>;
+                regulator-name = "flexcan1-reg";
+                regulator-min-microvolt = <1500000>;
+                regulator-max-microvolt = <1500000>;
+                gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+        };
+
+        reg_panel: regulator-panel {
+                compatible = "regulator-fixed";
+                regulator-name = "panel-power-supply";
+                regulator-min-microvolt = <12000000>;
+                regulator-max-microvolt = <12000000>;
+                regulator-always-on;
+        };
+
+        reg_pcie: regulator-pcie {
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_pcie_reg>;
+                regulator-name = "mPCIe_1V5";
+                regulator-min-microvolt = <1500000>;
+                regulator-max-microvolt = <1500000>;
+                gpio = <&gpio3 0 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+        };
+
+        reg_usb_h1_vbus: usb-h1-vbus {
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_usbh1_vbus>;
+                regulator-name = "usb_h1_vbus";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                gpio = <&gpio2 18 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+        };
+
+        reg_usbotg_vbus: usbotg-vbus {
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_usbotg_vbus>;
+                regulator-name = "usb_otg_vbus";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+        };
+
+        panel {
+                compatible = "auo,g104sn02";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_panel_en>;
+                power-supply = <&reg_panel>;
+                enable-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
+                backlight = <&backlight>;
+
+                port {
+                        panel_in: endpoint {
+                                remote-endpoint = <&lvds0_out>;
+                        };
+                };
+        };
+};
+
+&can1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_flexcan1>;
+        xceiver-supply = <&reg_flexcan1>;
+        status = "disabled";
+};
+
+&hdmi {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hdmicec>;
+        ddc-i2c-bus = <&i2c2>;
+        status = "disabled";
+};
+
+&i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1>;
+        clock-frequency = <400000>;
+        status = "disabled";
+
+        stmpe: touchctrl@44 {
+                compatible = "st,stmpe811";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_stmpe>;
+                reg = <0x44>;
+                interrupt-parent = <&gpio7>;
+                interrupts = <12 IRQ_TYPE_NONE>;
+                status = "disabled";
+
+                stmpe_touchscreen {
+                        compatible = "st,stmpe-ts";
+                        st,sample-time = <4>;
+                        st,mod-12b = <1>;
+                        st,ref-sel = <0>;
+                        st,adc-freq = <1>;
+                        st,ave-ctrl = <1>;
+                        st,touch-det-delay = <2>;
+                        st,settling = <2>;
+                        st,fraction-z = <7>;
+                        st,i-drive = <1>;
+                };
+        };
+
+        i2c_rtc: rtc@68 {
+                compatible = "microcrystal,rv4162";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_rtc_int>;
+                reg = <0x68>;
+                interrupt-parent = <&gpio7>;
+                interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+        };
+};
+
+&i2c2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2>;
+        clock-frequency = <100000>;
+        status = "disabled";
+};
+
+&ldb {
+        status = "okay";
+
+        lvds-channel@0 {
+                fsl,data-mapping = "spwg";
+                fsl,data-width = <24>;
+                status = "disabled";
+
+                port@4 {
+                        reg = <4>;
+
+                        lvds0_out: endpoint {
+                                remote-endpoint = <&panel_in>;
+                        };
+                };
+        };
+};
+
+&pcie {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pcie>;
+        reset-gpio = <&gpio2 25 GPIO_ACTIVE_LOW>;
+        vpcie-supply = <&reg_pcie>;
+        status = "disabled";
+};
+
+&pwm1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm1>;
+        status = "okay";
+};
+
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        status = "okay";
+};
+
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart3>;
+        uart-has-rtscts;
+        status = "disabled";
+};
+
+&usbh1 {
+        vbus-supply = <&reg_usb_h1_vbus>;
+        disable-over-current;
+        status = "disabled";
+};
+
+&usbotg {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbotg>;
+        vbus-supply = <&reg_usbotg_vbus>;
+        disable-over-current;
+        status = "disabled";
+};
+
+&usdhc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc1>;
+        cd-gpios = <&gpio6 31 GPIO_ACTIVE_LOW>;
+        no-1-8-v;
+        status = "disabled";
+};
+
+&iomuxc {
+        pinctrl_panel_en: panelen1grp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_EB0__GPIO2_IO28          0xb0b1
+                >;
+        };
+
+        pinctrl_en_switch: enswitchgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_DA4__GPIO3_IO04          0xb0b1
+                >;
+        };
+
+        pinctrl_flexcan1: flexcan1grp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_7__FLEXCAN1_TX          0x1b0b0
+                        MX6QDL_PAD_GPIO_8__FLEXCAN1_RX          0x1b0b0
+                >;
+        };
+
+        pinctrl_flexcan1_en: flexcan1engrp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_A18__GPIO2_IO20          0xb0b1
+                >;
+        };
+
+        pinctrl_gpioleds: gpioledsgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22        0x1b0b0
+                        MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23        0x1b0b0
+                        MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24        0x1b0b0
+                >;
+        };
+
+        pinctrl_hdmicec: hdmicecgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE   0x1f8b0
+                >;
+        };
+
+        pinctrl_i2c2: i2c2grp {
+                fsl,pins = <
+                        MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
+                        MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
+                >;
+        };
+
+        pinctrl_i2c1: i2c1grp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
+                        MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
+                >;
+        };
+
+        pinctrl_pcie: pciegrp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_OE__GPIO2_IO25           0xb0b1
+                >;
+        };
+
+        pinctrl_pcie_reg: pciereggrp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_DA0__GPIO3_IO00          0xb0b1
+                >;
+        };
+
+        pinctrl_pwm1: pwm1grp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_9__PWM1_OUT             0x1b0b1
+                >;
+        };
+
+        pinctrl_rtc_int: rtcintgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_SD3_RST__GPIO7_IO08          0x1b0b0
+                >;
+        };
+
+        pinctrl_stmpe: stmpegrp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x1b0b0
+                >;
+        };
+
+        pinctrl_uart2: uart2grp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_D26__UART2_TX_DATA       0x1b0b1
+                        MX6QDL_PAD_EIM_D27__UART2_RX_DATA       0x1b0b1
+                >;
+        };
+
+        pinctrl_uart3: uart3grp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_EB3__UART3_CTS_B         0x1b0b1
+                        MX6QDL_PAD_EIM_D23__UART3_RTS_B         0x1b0b1
+                        MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
+                        MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
+                >;
+        };
+
+        pinctrl_usbh1_vbus: usbh1vbusgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_A20__GPIO2_IO18          0xb0b1
+                >;
+        };
+
+        pinctrl_usbotg: usbotggrp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
+                >;
+        };
+
+        pinctrl_usbotg_vbus: usbotgvbusgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_A19__GPIO2_IO19          0xb0b1
+                >;
+        };
+
+        pinctrl_usdhc1: usdhc1grp {
+                fsl,pins = <
+                        MX6QDL_PAD_SD1_CMD__SD1_CMD             0x170f9
+                        MX6QDL_PAD_SD1_CLK__SD1_CLK             0x100f9
+                        MX6QDL_PAD_SD1_DAT0__SD1_DATA0          0x170f9
+                        MX6QDL_PAD_SD1_DAT1__SD1_DATA1          0x170f9
+                        MX6QDL_PAD_SD1_DAT2__SD1_DATA2          0x170f9
+                        MX6QDL_PAD_SD1_DAT3__SD1_DATA3          0x170f9
+                        MX6QDL_PAD_EIM_BCLK__GPIO6_IO31         0xb0b1  /* CD */
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
index 585b4f6986c1..7ba317ae899b 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
@@ -13,7 +13,7 @@
 
 / {
         chosen {
-                linux,stdout-path = &uart4;
+                stdout-path = &uart4;
         };
 
         regulators {
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
index d81b0078a100..c58f3443d55d 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
@@ -15,7 +15,7 @@
         model = "Phytec phyFLEX-i.MX6 Quad";
         compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x80000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
new file mode 100644
index 000000000000..6486df3e2942
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
@@ -0,0 +1,279 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 PHYTEC Messtechnik GmbH
+ * Author: Christian Hemp <c.hemp@phytec.de>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+        aliases {
+                rtc1 = &da9062_rtc;
+                rtc2 = &snvs_rtc;
+        };
+
+        /*
+         * Set the minimum memory size here and
+         * let the bootloader set the real size.
+         */
+        memory@10000000 {
+                device_type = "memory";
+                reg = <0x10000000 0x8000000>;
+        };
+
+        gpio_leds_som: somleds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_gpioleds_som>;
+
+                som-led-green {
+                        label = "phycore:green";
+                        gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+};
+
+&ecspi1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ecspi1>;
+        cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
+        status = "okay";
+
+        m25p80: flash@0 {
+                compatible = "jedec,spi-nor";
+                spi-max-frequency = <20000000>;
+                reg = <0>;
+                status = "disabled";
+        };
+};
+
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet>;
+        phy-handle = <&ethphy>;
+        phy-mode = "rgmii";
+        phy-supply = <&vdd_eth_io>;
+        phy-reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+        status = "disabled";
+
+        mdio {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                ethphy: ethernet-phy@3 {
+                        reg = <3>;
+                        txc-skew-ps = <1680>;
+                        rxc-skew-ps = <1860>;
+                };
+        };
+};
+
+&gpmi {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_gpmi_nand>;
+        nand-on-flash-bbt;
+        status = "disabled";
+};
+
+&i2c3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c3>;
+        clock-frequency = <400000>;
+        status = "okay";
+
+        eeprom@50 {
+                compatible = "atmel,24c32";
+                reg = <0x50>;
+        };
+
+        pmic@58 {
+                compatible = "dlg,da9062";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_pmic>;
+                reg = <0x58>;
+                interrupt-parent = <&gpio1>;
+                interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+                interrupt-controller;
+
+                da9062_rtc: rtc {
+                        compatible = "dlg,da9062-rtc";
+                };
+
+                watchdog {
+                        compatible = "dlg,da9062-watchdog";
+                };
+
+                regulators {
+                        vdd_arm: buck1 {
+                                regulator-name = "vdd_arm";
+                                regulator-min-microvolt = <730000>;
+                                regulator-max-microvolt = <1380000>;
+                                regulator-always-on;
+                        };
+
+                        vdd_soc: buck2 {
+                                regulator-name = "vdd_soc";
+                                regulator-min-microvolt = <730000>;
+                                regulator-max-microvolt = <1380000>;
+                                regulator-always-on;
+                        };
+
+                        vdd_ddr3_1p5: buck3 {
+                                regulator-name = "vdd_ddr3";
+                                regulator-min-microvolt = <1500000>;
+                                regulator-max-microvolt = <1500000>;
+                                regulator-always-on;
+                        };
+
+                        vdd_eth_1p2: buck4 {
+                                regulator-name = "vdd_eth";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+                        };
+
+                        vdd_snvs: ldo1 {
+                                regulator-name = "vdd_snvs";
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-always-on;
+                        };
+
+                        vdd_high: ldo2 {
+                                regulator-name = "vdd_high";
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-always-on;
+                        };
+
+                        vdd_eth_io: ldo3 {
+                                regulator-name = "vdd_eth_io";
+                                regulator-min-microvolt = <2500000>;
+                                regulator-max-microvolt = <2500000>;
+                        };
+
+                        vdd_emmc_1p8: ldo4 {
+                                regulator-name = "vdd_emmc";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
+                };
+        };
+};
+
+&reg_arm {
+        vin-supply = <&vdd_arm>;
+};
+
+&reg_pu {
+        vin-supply = <&vdd_soc>;
+};
+
+&reg_soc {
+        vin-supply = <&vdd_soc>;
+};
+
+&snvs_poweroff {
+        status = "okay";
+};
+
+&usdhc4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc4>;
+        bus-width = <8>;
+        non-removable;
+        vmmc-supply = <&vdd_emmc_1p8>;
+        status = "disabled";
+};
+
+&iomuxc {
+        pinctrl_enet: enetgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
+                        MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
+                        MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
+                        MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
+                        MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
+                        MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
+                        MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
+                        MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
+                        MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
+                        MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
+                        MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
+                        MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
+                        MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
+                        MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
+                        MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
+                        MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
+                        MX6QDL_PAD_SD2_DAT1__GPIO1_IO14         0x1b0b0
+                >;
+        };
+
+        pinctrl_gpioleds_som: gpioledssomgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x1b0b0
+                >;
+        };
+
+        pinctrl_gpmi_nand: gpminandgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
+                        MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
+                        MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
+                        MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
+                        MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
+                        MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
+                        MX6QDL_PAD_NANDF_CS2__NAND_CE2_B        0xb0b1
+                        MX6QDL_PAD_NANDF_CS3__NAND_CE3_B        0xb0b1
+                        MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
+                        MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
+                        MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
+                        MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
+                        MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
+                        MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
+                        MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
+                        MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
+                        MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
+                        MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
+                        MX6QDL_PAD_SD4_DAT0__NAND_DQS           0x00b1
+                >;
+        };
+
+        pinctrl_i2c3: i2c3grp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
+                        MX6QDL_PAD_GPIO_5__I2C3_SCL             0x4001b8b1
+                >;
+        };
+
+        pinctrl_ecspi1: ecspi1grp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
+                        MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
+                        MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
+                        MX6QDL_PAD_EIM_D19__GPIO3_IO19          0x1b0b0
+                >;
+        };
+
+        pinctrl_pmic: pmicgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x1b0b0
+                >;
+        };
+
+        pinctrl_usdhc4: usdhc4grp {
+                fsl,pins = <
+                        MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
+                        MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
+                        MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
+                        MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
+                        MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
+                        MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
+                        MX6QDL_PAD_SD4_DAT4__SD4_DATA4          0x17059
+                        MX6QDL_PAD_SD4_DAT5__SD4_DATA5          0x17059
+                        MX6QDL_PAD_SD4_DAT6__SD4_DATA6          0x17059
+                        MX6QDL_PAD_SD4_DAT7__SD4_DATA7          0x17059
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/imx6qdl-rex.dtsi b/arch/arm/boot/dts/imx6qdl-rex.dtsi
index 6e9549ff11da..039e3b8306c4 100644
--- a/arch/arm/boot/dts/imx6qdl-rex.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-rex.dtsi
@@ -137,7 +137,7 @@
         status = "okay";
 
         eeprom@57 {
-                compatible = "at,24c02";
+                compatible = "atmel,24c02";
                 reg = <0x57>;
         };
 };
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index 82d6ccb46982..54b0139e978d 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -13,7 +13,7 @@
 #include <dt-bindings/gpio/gpio.h>
 
 / {
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x80000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
index 35de7adc997b..18b65052553d 100644
--- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
@@ -49,7 +49,7 @@
                 stdout-path = &uart2;
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index 0a50705b9c18..f019f9900369 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -19,7 +19,7 @@
                 stdout-path = &uart1;
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/imx6qdl-tx6.dtsi
index 6abb66cd7d4a..f015e2d1cf35 100644
--- a/arch/arm/boot/dts/imx6qdl-tx6.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-tx6.dtsi
@@ -61,8 +61,8 @@
                 sdhc1 = &usdhc2;
         };
 
-        memory {
-                reg = <0 0>; /* will be filled by U-Boot */
+        memory@10000000 {
+                reg = <0x10000000 0>; /* will be filled by U-Boot */
         };
 
         clocks {
diff --git a/arch/arm/boot/dts/imx6qdl-udoo.dtsi b/arch/arm/boot/dts/imx6qdl-udoo.dtsi
index 4161b7d4323a..906387915dc5 100644
--- a/arch/arm/boot/dts/imx6qdl-udoo.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-udoo.dtsi
@@ -35,7 +35,7 @@
                 pinctrl-names = "default";
         };
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6qdl-var-dart.dtsi b/arch/arm/boot/dts/imx6qdl-var-dart.dtsi
index 421d6f527609..38080c1dfaec 100644
--- a/arch/arm/boot/dts/imx6qdl-var-dart.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-var-dart.dtsi
@@ -10,7 +10,7 @@
 #include <dt-bindings/sound/fsl-imx-audmux.h>
 
 / {
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
index 72f52fcecee1..911f7f0e3cea 100644
--- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
@@ -305,6 +305,15 @@
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart4>;
         status = "okay";
+
+        rave-sp {
+                compatible = "zii,rave-sp-rdu2";
+                current-speed = <1000000>;
+
+                watchdog {
+                        compatible = "zii,rave-sp-watchdog";
+                };
+        };
 };
 
 &ecspi1 {
@@ -498,7 +507,7 @@
         };
 
         eeprom@54 {
-                compatible = "at,24c128";
+                compatible = "atmel,24c128";
                 reg = <0x54>;
         };
 
@@ -602,6 +611,8 @@
         wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
         vmmc-supply = <&reg_3p3v_sd>;
         vqmmc-supply = <&reg_3p3v>;
+        no-1-8-v;
+        no-sdio;
         status = "okay";
 };
 
@@ -613,6 +624,8 @@
         wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
         vmmc-supply = <&reg_3p3v_sd>;
         vqmmc-supply = <&reg_3p3v>;
+        no-1-8-v;
+        no-sdio;
         status = "okay";
 };
 
@@ -622,7 +635,10 @@
         bus-width = <8>;
         vmmc-supply = <&reg_3p3v>;
         vqmmc-supply = <&reg_3p3v>;
+        no-1-8-v;
         non-removable;
+        no-sdio;
+        no-sd;
         status = "okay";
 };
 
@@ -805,6 +821,10 @@
         };
 };
 
+&wdog1 {
+        status = "disabled";
+};
+
 &iomuxc {
         pinctrl_accel: accelgrp {
                 fsl,pins = <
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 59ff86695a14..c003e62bf290 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -23,7 +23,7 @@
          * Also for U-Boot there must be a pre-existing /memory node.
          */
         chosen {};
-        memory { device_type = "memory"; reg = <0 0>; };
+        memory { device_type = "memory"; };
 
         aliases {
                 ethernet0 = &fec;
@@ -143,7 +143,7 @@
                 };
         };
 
-        pmu {
+        pmu: pmu {
                 compatible = "arm,cortex-a9-pmu";
                 interrupt-parent = <&gpc>;
                 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts b/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts
new file mode 100644
index 000000000000..3618e5316bf4
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qp-phytec-mira-rdk-nand.dts
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 PHYTEC Messtechnik GmbH
+ * Author: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
+ */
+
+/dts-v1/;
+#include "imx6qp.dtsi"
+#include "imx6qdl-phytec-phycore-som.dtsi"
+#include "imx6qdl-phytec-mira.dtsi"
+
+/ {
+        model = "PHYTEC phyBOARD-Mira QuadPlus Carrier-Board with NAND";
+        compatible = "phytec,imx6qp-pbac06-nand", "phytec,imx6qp-pbac06",
+                     "phytec,imx6qdl-pcm058", "fsl,imx6qp";
+
+        chosen {
+                linux,stdout-path = &uart2;
+        };
+};
+
+&can1 {
+        status = "okay";
+};
+
+&fec {
+        status = "okay";
+};
+
+&gpmi {
+        status = "okay";
+};
+
+&hdmi {
+        status = "okay";
+};
+
+&i2c1 {
+        status = "okay";
+};
+
+&i2c2 {
+        status = "okay";
+};
+
+&i2c_rtc {
+        status = "okay";
+};
+
+&m25p80 {
+        status = "okay";
+};
+
+&pcie {
+        status = "okay";
+};
+
+&uart3 {
+        status = "okay";
+};
+
+&usbh1 {
+        status = "okay";
+};
+
+&usbotg {
+        status = "okay";
+};
+
+&usdhc1 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6qp-wandboard-revd1.dts b/arch/arm/boot/dts/imx6qp-wandboard-revd1.dts
index f7badd82ce8a..907ba0c74ba6 100644
--- a/arch/arm/boot/dts/imx6qp-wandboard-revd1.dts
+++ b/arch/arm/boot/dts/imx6qp-wandboard-revd1.dts
@@ -16,7 +16,7 @@
         model = "Wandboard i.MX6 QuadPlus Board revD1";
         compatible = "wand,imx6qp-wandboard", "fsl,imx6qp";
 
-        memory {
+        memory@10000000 {
                 reg = <0x10000000 0x80000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx6qp-zii-rdu2.dts b/arch/arm/boot/dts/imx6qp-zii-rdu2.dts
index 547a76677ab3..de5b50df833c 100644
--- a/arch/arm/boot/dts/imx6qp-zii-rdu2.dts
+++ b/arch/arm/boot/dts/imx6qp-zii-rdu2.dts
@@ -47,4 +47,9 @@
 / {
         model = "ZII RDU2+ Board";
         compatible = "zii,imx6qp-zii-rdu2", "fsl,imx6qp";
+
+        /* Will be filled by the bootloader */
+        memory@10000000 {
+                reg = <0x10000000 0>;
+        };
 };
diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts
index 2844ab541759..37e792fdc160 100644
--- a/arch/arm/boot/dts/imx6sl-evk.dts
+++ b/arch/arm/boot/dts/imx6sl-evk.dts
@@ -16,7 +16,7 @@
         model = "Freescale i.MX6 SoloLite EVK Board";
         compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6sl-warp.dts b/arch/arm/boot/dts/imx6sl-warp.dts
index 72c7745f51d3..404e602e6781 100644
--- a/arch/arm/boot/dts/imx6sl-warp.dts
+++ b/arch/arm/boot/dts/imx6sl-warp.dts
@@ -54,7 +54,7 @@
         model = "WaRP Board";
         compatible = "warp,imx6sl-warp", "fsl,imx6sl";
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x20000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index ae8df3cf687e..ab6a7e2e7e8f 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -21,7 +21,7 @@
          * Also for U-Boot there must be a pre-existing /memory node.
          */
         chosen {};
-        memory { device_type = "memory"; reg = <0 0>; };
+        memory { device_type = "memory"; };
 
         aliases {
                 ethernet0 = &fec;
diff --git a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts
index f9d40ee14982..b58f770c40d9 100644
--- a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts
+++ b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts
@@ -52,7 +52,7 @@
                 t_lcd = &t_lcd;
         };
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts b/arch/arm/boot/dts/imx6sx-sabreauto.dts
index 240a2864d044..72da5acf35a2 100644
--- a/arch/arm/boot/dts/imx6sx-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts
@@ -14,7 +14,7 @@
         model = "Freescale i.MX6 SoloX Sabre Auto Board";
         compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx";
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x80000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/imx6sx-sdb.dtsi
index d35aa858f9db..f8f31872fa14 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dtsi
+++ b/arch/arm/boot/dts/imx6sx-sdb.dtsi
@@ -20,7 +20,7 @@
                 stdout-path = &uart1;
         };
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts b/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts
index 4d8c6521845f..252175b59247 100644
--- a/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts
+++ b/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts
@@ -20,7 +20,7 @@
                 stdout-path = &uart1;
         };
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts b/arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts
index 0c1fc1a8f913..40ccdf43dffc 100644
--- a/arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts
+++ b/arch/arm/boot/dts/imx6sx-udoo-neo-basic.dts
@@ -48,7 +48,7 @@
         model = "UDOO Neo Basic";
         compatible = "udoo,neobasic", "fsl,imx6sx";
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x20000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts b/arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts
index 5d6c2274ee2b..42bfc8f8f7f6 100644
--- a/arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts
+++ b/arch/arm/boot/dts/imx6sx-udoo-neo-extended.dts
@@ -48,7 +48,7 @@
         model = "UDOO Neo Extended";
         compatible = "udoo,neoextended", "fsl,imx6sx";
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x40000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo-full.dts b/arch/arm/boot/dts/imx6sx-udoo-neo-full.dts
index 653ceb29e28b..c84c877f09d4 100644
--- a/arch/arm/boot/dts/imx6sx-udoo-neo-full.dts
+++ b/arch/arm/boot/dts/imx6sx-udoo-neo-full.dts
@@ -48,7 +48,7 @@
         model = "UDOO Neo Full";
         compatible = "udoo,neofull", "fsl,imx6sx";
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x40000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index fd7879342d0d..49c7205b8db8 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -22,7 +22,7 @@
          * Also for U-Boot there must be a pre-existing /memory node.
          */
         chosen {};
-        memory { device_type = "memory"; reg = <0 0>; };
+        memory { device_type = "memory"; };
 
         aliases {
                 can0 = &flexcan1;
@@ -188,6 +188,7 @@
                                  <&clks IMX6SX_CLK_GPU>,
                                  <&clks IMX6SX_CLK_GPU>;
                         clock-names = "bus", "core", "shader";
+                        power-domains = <&pd_pu>;
                 };
 
                 dma_apbh: dma-apbh@1804000 {
@@ -767,6 +768,18 @@
                                         #address-cells = <1>;
                                         #size-cells = <0>;
 
+                                        power-domain@0 {
+                                                reg = <0>;
+                                                #power-domain-cells = <0>;
+                                        };
+
+                                        pd_pu: power-domain@1 {
+                                                reg = <1>;
+                                                #power-domain-cells = <0>;
+                                                power-supply = <&reg_soc>;
+                                                clocks = <&clks IMX6SX_CLK_GPU>;
+                                        };
+
                                         pd_pci: power-domain@3 {
                                                 reg = <3>;
                                                 #power-domain-cells = <0>;
@@ -1355,9 +1368,4 @@
                         status = "disabled";
                 };
         };
-
-        gpu-subsystem {
-                compatible = "fsl,imx-gpu-subsystem";
-                cores = <&gpu>;
-        };
 };
diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dts b/arch/arm/boot/dts/imx6ul-14x14-evk.dts
index 18fdb088ba1e..6d720b20e7ed 100644
--- a/arch/arm/boot/dts/imx6ul-14x14-evk.dts
+++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dts
@@ -9,487 +9,9 @@
 /dts-v1/;
 
 #include "imx6ul.dtsi"
+#include "imx6ul-14x14-evk.dtsi"
 
 / {
         model = "Freescale i.MX6 UltraLite 14x14 EVK Board";
         compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul";
-
-        chosen {
-                stdout-path = &uart1;
-        };
-
-        memory {
-                reg = <0x80000000 0x20000000>;
-        };
-
-        backlight_display: backlight-display {
-                compatible = "pwm-backlight";
-                pwms = <&pwm1 0 5000000>;
-                brightness-levels = <0 4 8 16 32 64 128 255>;
-                default-brightness-level = <6>;
-                status = "okay";
-        };
-
-
-        reg_sd1_vmmc: regulator-sd1-vmmc {
-                compatible = "regulator-fixed";
-                regulator-name = "VSD_3V3";
-                regulator-min-microvolt = <3300000>;
-                regulator-max-microvolt = <3300000>;
-                gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
-                enable-active-high;
-        };
-
-        sound {
-                compatible = "simple-audio-card";
-                simple-audio-card,name = "mx6ul-wm8960";
-                simple-audio-card,format = "i2s";
-                simple-audio-card,bitclock-master = <&dailink_master>;
-                simple-audio-card,frame-master = <&dailink_master>;
-                simple-audio-card,widgets =
-                        "Microphone", "Mic Jack",
-                        "Line", "Line In",
-                        "Line", "Line Out",
-                        "Speaker", "Speaker",
-                        "Headphone", "Headphone Jack";
-                simple-audio-card,routing =
-                        "Headphone Jack", "HP_L",
-                        "Headphone Jack", "HP_R",
-                        "Speaker", "SPK_LP",
-                        "Speaker", "SPK_LN",
-                        "Speaker", "SPK_RP",
-                        "Speaker", "SPK_RN",
-                        "LINPUT1", "Mic Jack",
-                        "LINPUT3", "Mic Jack",
-                        "RINPUT1", "Mic Jack",
-                        "RINPUT2", "Mic Jack";
-
-                simple-audio-card,cpu {
-                        sound-dai = <&sai2>;
-                };
-
-                dailink_master: simple-audio-card,codec {
-                        sound-dai = <&codec>;
-                        clocks = <&clks IMX6UL_CLK_SAI2>;
-                };
-        };
-
-        panel {
-                compatible = "innolux,at043tn24";
-                backlight = <&backlight_display>;
-
-                port {
-                        panel_in: endpoint {
-                                remote-endpoint = <&display_out>;
-                        };
-                };
-        };
-};
-
-&clks {
-        assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
-        assigned-clock-rates = <786432000>;
-};
-
-&i2c2 {
-        clock_frequency = <100000>;
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_i2c2>;
-        status = "okay";
-
-        codec: wm8960@1a {
-                #sound-dai-cells = <0>;
-                compatible = "wlf,wm8960";
-                reg = <0x1a>;
-                wlf,shared-lrclk;
-        };
-};
-
-&fec1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_enet1>;
-        phy-mode = "rmii";
-        phy-handle = <&ethphy0>;
-        status = "okay";
-};
-
-&fec2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_enet2>;
-        phy-mode = "rmii";
-        phy-handle = <&ethphy1>;
-        status = "okay";
-
-        mdio {
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                ethphy0: ethernet-phy@2 {
-                        reg = <2>;
-                        micrel,led-mode = <1>;
-                        clocks = <&clks IMX6UL_CLK_ENET_REF>;
-                        clock-names = "rmii-ref";
-                };
-
-                ethphy1: ethernet-phy@1 {
-                        reg = <1>;
-                        micrel,led-mode = <1>;
-                        clocks = <&clks IMX6UL_CLK_ENET2_REF>;
-                        clock-names = "rmii-ref";
-                };
-        };
-};
-
-
-&lcdif {
-        assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>;
-        assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>;
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_lcdif_dat
-                     &pinctrl_lcdif_ctrl>;
-        status = "okay";
-
-        port {
-                display_out: endpoint {
-                        remote-endpoint = <&panel_in>;
-                };
-        };
-};
-
-&pwm1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_pwm1>;
-        status = "okay";
-};
-
-&qspi {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_qspi>;
-        status = "okay";
-
-        flash0: n25q256a@0 {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                compatible = "micron,n25q256a";
-                spi-max-frequency = <29000000>;
-                reg = <0>;
-        };
-};
-
-&sai2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_sai2>;
-        assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
-                          <&clks IMX6UL_CLK_SAI2>;
-        assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
-        assigned-clock-rates = <0>, <12288000>;
-        fsl,sai-mclk-direction-output;
-        status = "okay";
-};
-
-&snvs_poweroff {
-        status = "okay";
-};
-
-&tsc {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_tsc>;
-        xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
-        measure-delay-time = <0xffff>;
-        pre-charge-time = <0xfff>;
-        status = "okay";
-};
-
-&uart1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart1>;
-        status = "okay";
-};
-
-&uart2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart2>;
-        uart-has-rtscts;
-        status = "okay";
-};
-
-&usbotg1 {
-        dr_mode = "otg";
-        status = "okay";
-};
-
-&usbotg2 {
-        dr_mode = "host";
-        disable-over-current;
-        status = "okay";
-};
-
-&usbphy1 {
-        fsl,tx-d-cal = <106>;
-};
-
-&usbphy2 {
-        fsl,tx-d-cal = <106>;
-};
-
-&usdhc1 {
-        pinctrl-names = "default", "state_100mhz", "state_200mhz";
-        pinctrl-0 = <&pinctrl_usdhc1>;
-        pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
-        pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
-        cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
-        keep-power-in-suspend;
-        wakeup-source;
-        vmmc-supply = <&reg_sd1_vmmc>;
-        status = "okay";
-};
-
-&usdhc2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usdhc2>;
-        no-1-8-v;
-        keep-power-in-suspend;
-        wakeup-source;
-        status = "okay";
-};
-
-&wdog1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_wdog>;
-        fsl,ext-reset-output;
-};
-
-&iomuxc {
-        pinctrl-names = "default";
-
-        pinctrl_csi1: csi1grp {
-                fsl,pins = <
-                        MX6UL_PAD_CSI_MCLK__CSI_MCLK            0x1b088
-                        MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK        0x1b088
-                        MX6UL_PAD_CSI_VSYNC__CSI_VSYNC          0x1b088
-                        MX6UL_PAD_CSI_HSYNC__CSI_HSYNC          0x1b088
-                        MX6UL_PAD_CSI_DATA00__CSI_DATA02        0x1b088
-                        MX6UL_PAD_CSI_DATA01__CSI_DATA03        0x1b088
-                        MX6UL_PAD_CSI_DATA02__CSI_DATA04        0x1b088
-                        MX6UL_PAD_CSI_DATA03__CSI_DATA05        0x1b088
-                        MX6UL_PAD_CSI_DATA04__CSI_DATA06        0x1b088
-                        MX6UL_PAD_CSI_DATA05__CSI_DATA07        0x1b088
-                        MX6UL_PAD_CSI_DATA06__CSI_DATA08        0x1b088
-                        MX6UL_PAD_CSI_DATA07__CSI_DATA09        0x1b088
-                >;
-        };
-
-        pinctrl_enet1: enet1grp {
-                fsl,pins = <
-                        MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
-                        MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x1b0b0
-                        MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
-                        MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
-                        MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
-                        MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
-                        MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
-                        MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b031
-                >;
-        };
-
-        pinctrl_enet2: enet2grp {
-                fsl,pins = <
-                        MX6UL_PAD_GPIO1_IO07__ENET2_MDC         0x1b0b0
-                        MX6UL_PAD_GPIO1_IO06__ENET2_MDIO        0x1b0b0
-                        MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x1b0b0
-                        MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x1b0b0
-                        MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
-                        MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
-                        MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x1b0b0
-                        MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
-                        MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
-                        MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x4001b031
-                >;
-        };
-
-        pinctrl_flexcan1: flexcan1grp{
-                fsl,pins = <
-                        MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX      0x1b020
-                        MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX      0x1b020
-                >;
-        };
-
-        pinctrl_flexcan2: flexcan2grp{
-                fsl,pins = <
-                        MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX      0x1b020
-                        MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX      0x1b020
-                >;
-        };
-
-        pinctrl_i2c1: i2c1grp {
-                fsl,pins = <
-                        MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
-                        MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
-                >;
-        };
-
-        pinctrl_i2c2: i2c2grp {
-                fsl,pins = <
-                        MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
-                        MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
-                >;
-        };
-
-        pinctrl_lcdif_dat: lcdifdatgrp {
-                fsl,pins = <
-                        MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x79
-                        MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x79
-                        MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x79
-                        MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x79
-                        MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x79
-                        MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x79
-                        MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x79
-                        MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x79
-                        MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x79
-                        MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x79
-                        MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x79
-                        MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x79
-                        MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x79
-                        MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x79
-                        MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x79
-                        MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x79
-                        MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x79
-                        MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x79
-                        MX6UL_PAD_LCD_DATA18__LCDIF_DATA18  0x79
-                        MX6UL_PAD_LCD_DATA19__LCDIF_DATA19  0x79
-                        MX6UL_PAD_LCD_DATA20__LCDIF_DATA20  0x79
-                        MX6UL_PAD_LCD_DATA21__LCDIF_DATA21  0x79
-                        MX6UL_PAD_LCD_DATA22__LCDIF_DATA22  0x79
-                        MX6UL_PAD_LCD_DATA23__LCDIF_DATA23  0x79
-                >;
-        };
-
-        pinctrl_lcdif_ctrl: lcdifctrlgrp {
-                fsl,pins = <
-                        MX6UL_PAD_LCD_CLK__LCDIF_CLK        0x79
-                        MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x79
-                        MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x79
-                        MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x79
-                        /* used for lcd reset */
-                        MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09  0x79
-                >;
-        };
-
-        pinctrl_qspi: qspigrp {
-                fsl,pins = <
-                        MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK        0x70a1
-                        MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00   0x70a1
-                        MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01     0x70a1
-                        MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02     0x70a1
-                        MX6UL_PAD_NAND_CLE__QSPI_A_DATA03       0x70a1
-                        MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B        0x70a1
-                >;
-        };
-
-        pinctrl_sai2: sai2grp {
-                fsl,pins = <
-                        MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK        0x17088
-                        MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC        0x17088
-                        MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA     0x11088
-                        MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA        0x11088
-                        MX6UL_PAD_JTAG_TMS__SAI2_MCLK           0x17088
-                        MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04      0x17059
-                >;
-        };
-
-        pinctrl_pwm1: pwm1grp {
-                fsl,pins = <
-                        MX6UL_PAD_GPIO1_IO08__PWM1_OUT   0x110b0
-                >;
-        };
-
-        pinctrl_sim2: sim2grp {
-                fsl,pins = <
-                        MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD             0xb808
-                        MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK            0x31
-                        MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B          0xb808
-                        MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN           0xb808
-                        MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD           0xb809
-                        MX6UL_PAD_CSI_DATA02__GPIO4_IO23                0x3008
-                >;
-        };
-
-        pinctrl_tsc: tscgrp {
-                fsl,pins = <
-                        MX6UL_PAD_GPIO1_IO01__GPIO1_IO01                0xb0
-                        MX6UL_PAD_GPIO1_IO02__GPIO1_IO02                0xb0
-                        MX6UL_PAD_GPIO1_IO03__GPIO1_IO03                0xb0
-                        MX6UL_PAD_GPIO1_IO04__GPIO1_IO04                0xb0
-                >;
-        };
-
-        pinctrl_uart1: uart1grp {
-                fsl,pins = <
-                        MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
-                        MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
-                >;
-        };
-
-        pinctrl_uart2: uart2grp {
-                fsl,pins = <
-                        MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x1b0b1
-                        MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x1b0b1
-                        MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS  0x1b0b1
-                        MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS  0x1b0b1
-                >;
-        };
-
-        pinctrl_usdhc1: usdhc1grp {
-                fsl,pins = <
-                        MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x17059
-                        MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x10059
-                        MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x17059
-                        MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x17059
-                        MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x17059
-                        MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x17059
-                        MX6UL_PAD_UART1_RTS_B__GPIO1_IO19       0x17059 /* SD1 CD */
-                        MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT    0x17059 /* SD1 VSELECT */
-                        MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059 /* SD1 RESET */
-                >;
-        };
-
-        pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
-                fsl,pins = <
-                        MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
-                        MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
-                        MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
-                        MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
-                        MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
-                        MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
-
-                >;
-        };
-
-        pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
-                fsl,pins = <
-                        MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
-                        MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
-                        MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
-                        MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
-                        MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
-                        MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
-                >;
-        };
-
-        pinctrl_usdhc2: usdhc2grp {
-                fsl,pins = <
-                        MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x17059
-                        MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
-                        MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
-                        MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
-                        MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
-                        MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
-                >;
-        };
-
-        pinctrl_wdog: wdoggrp {
-                fsl,pins = <
-                        MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY    0x30b0
-                >;
-        };
 };
diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
new file mode 100644
index 000000000000..32a07232c034
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
@@ -0,0 +1,499 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/ {
+        chosen {
+                stdout-path = &uart1;
+        };
+
+        memory@80000000 {
+                reg = <0x80000000 0x20000000>;
+        };
+
+        backlight_display: backlight-display {
+                compatible = "pwm-backlight";
+                pwms = <&pwm1 0 5000000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+                status = "okay";
+        };
+
+
+        reg_sd1_vmmc: regulator-sd1-vmmc {
+                compatible = "regulator-fixed";
+                regulator-name = "VSD_3V3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+        };
+
+        sound {
+                compatible = "simple-audio-card";
+                simple-audio-card,name = "mx6ul-wm8960";
+                simple-audio-card,format = "i2s";
+                simple-audio-card,bitclock-master = <&dailink_master>;
+                simple-audio-card,frame-master = <&dailink_master>;
+                simple-audio-card,widgets =
+                        "Microphone", "Mic Jack",
+                        "Line", "Line In",
+                        "Line", "Line Out",
+                        "Speaker", "Speaker",
+                        "Headphone", "Headphone Jack";
+                simple-audio-card,routing =
+                        "Headphone Jack", "HP_L",
+                        "Headphone Jack", "HP_R",
+                        "Speaker", "SPK_LP",
+                        "Speaker", "SPK_LN",
+                        "Speaker", "SPK_RP",
+                        "Speaker", "SPK_RN",
+                        "LINPUT1", "Mic Jack",
+                        "LINPUT3", "Mic Jack",
+                        "RINPUT1", "Mic Jack",
+                        "RINPUT2", "Mic Jack";
+
+                simple-audio-card,cpu {
+                        sound-dai = <&sai2>;
+                };
+
+                dailink_master: simple-audio-card,codec {
+                        sound-dai = <&codec>;
+                        clocks = <&clks IMX6UL_CLK_SAI2>;
+                };
+        };
+
+        panel {
+                compatible = "innolux,at043tn24";
+                backlight = <&backlight_display>;
+
+                port {
+                        panel_in: endpoint {
+                                remote-endpoint = <&display_out>;
+                        };
+                };
+        };
+};
+
+&clks {
+        assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+        assigned-clock-rates = <786432000>;
+};
+
+&i2c2 {
+        clock_frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2>;
+        status = "okay";
+
+        codec: wm8960@1a {
+                #sound-dai-cells = <0>;
+                compatible = "wlf,wm8960";
+                reg = <0x1a>;
+                wlf,shared-lrclk;
+        };
+};
+
+&fec1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet1>;
+        phy-mode = "rmii";
+        phy-handle = <&ethphy0>;
+        status = "okay";
+};
+
+&fec2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet2>;
+        phy-mode = "rmii";
+        phy-handle = <&ethphy1>;
+        status = "okay";
+
+        mdio {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                ethphy0: ethernet-phy@2 {
+                        reg = <2>;
+                        micrel,led-mode = <1>;
+                        clocks = <&clks IMX6UL_CLK_ENET_REF>;
+                        clock-names = "rmii-ref";
+                };
+
+                ethphy1: ethernet-phy@1 {
+                        reg = <1>;
+                        micrel,led-mode = <1>;
+                        clocks = <&clks IMX6UL_CLK_ENET2_REF>;
+                        clock-names = "rmii-ref";
+                };
+        };
+};
+
+&i2c1 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1>;
+        status = "okay";
+
+        mag3110@e {
+                compatible = "fsl,mag3110";
+                reg = <0x0e>;
+        };
+};
+
+&lcdif {
+        assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>;
+        assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_lcdif_dat
+                     &pinctrl_lcdif_ctrl>;
+        status = "okay";
+
+        port {
+                display_out: endpoint {
+                        remote-endpoint = <&panel_in>;
+                };
+        };
+};
+
+&pwm1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm1>;
+        status = "okay";
+};
+
+&qspi {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_qspi>;
+        status = "okay";
+
+        flash0: n25q256a@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "micron,n25q256a";
+                spi-max-frequency = <29000000>;
+                reg = <0>;
+        };
+};
+
+&sai2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_sai2>;
+        assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
+                          <&clks IMX6UL_CLK_SAI2>;
+        assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+        assigned-clock-rates = <0>, <12288000>;
+        fsl,sai-mclk-direction-output;
+        status = "okay";
+};
+
+&snvs_poweroff {
+        status = "okay";
+};
+
+&tsc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_tsc>;
+        xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
+        measure-delay-time = <0xffff>;
+        pre-charge-time = <0xfff>;
+        status = "okay";
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        status = "okay";
+};
+
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        uart-has-rtscts;
+        status = "okay";
+};
+
+&usbotg1 {
+        dr_mode = "otg";
+        status = "okay";
+};
+
+&usbotg2 {
+        dr_mode = "host";
+        disable-over-current;
+        status = "okay";
+};
+
+&usbphy1 {
+        fsl,tx-d-cal = <106>;
+};
+
+&usbphy2 {
+        fsl,tx-d-cal = <106>;
+};
+
+&usdhc1 {
+        pinctrl-names = "default", "state_100mhz", "state_200mhz";
+        pinctrl-0 = <&pinctrl_usdhc1>;
+        pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+        pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+        cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+        keep-power-in-suspend;
+        wakeup-source;
+        vmmc-supply = <&reg_sd1_vmmc>;
+        status = "okay";
+};
+
+&usdhc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc2>;
+        no-1-8-v;
+        keep-power-in-suspend;
+        wakeup-source;
+        status = "okay";
+};
+
+&wdog1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_wdog>;
+        fsl,ext-reset-output;
+};
+
+&iomuxc {
+        pinctrl-names = "default";
+
+        pinctrl_csi1: csi1grp {
+                fsl,pins = <
+                        MX6UL_PAD_CSI_MCLK__CSI_MCLK            0x1b088
+                        MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK        0x1b088
+                        MX6UL_PAD_CSI_VSYNC__CSI_VSYNC          0x1b088
+                        MX6UL_PAD_CSI_HSYNC__CSI_HSYNC          0x1b088
+                        MX6UL_PAD_CSI_DATA00__CSI_DATA02        0x1b088
+                        MX6UL_PAD_CSI_DATA01__CSI_DATA03        0x1b088
+                        MX6UL_PAD_CSI_DATA02__CSI_DATA04        0x1b088
+                        MX6UL_PAD_CSI_DATA03__CSI_DATA05        0x1b088
+                        MX6UL_PAD_CSI_DATA04__CSI_DATA06        0x1b088
+                        MX6UL_PAD_CSI_DATA05__CSI_DATA07        0x1b088
+                        MX6UL_PAD_CSI_DATA06__CSI_DATA08        0x1b088
+                        MX6UL_PAD_CSI_DATA07__CSI_DATA09        0x1b088
+                >;
+        };
+
+        pinctrl_enet1: enet1grp {
+                fsl,pins = <
+                        MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
+                        MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x1b0b0
+                        MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
+                        MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
+                        MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
+                        MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
+                        MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
+                        MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b031
+                >;
+        };
+
+        pinctrl_enet2: enet2grp {
+                fsl,pins = <
+                        MX6UL_PAD_GPIO1_IO07__ENET2_MDC         0x1b0b0
+                        MX6UL_PAD_GPIO1_IO06__ENET2_MDIO        0x1b0b0
+                        MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x1b0b0
+                        MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x1b0b0
+                        MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
+                        MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
+                        MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x1b0b0
+                        MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
+                        MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
+                        MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x4001b031
+                >;
+        };
+
+        pinctrl_flexcan1: flexcan1grp{
+                fsl,pins = <
+                        MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX      0x1b020
+                        MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX      0x1b020
+                >;
+        };
+
+        pinctrl_flexcan2: flexcan2grp{
+                fsl,pins = <
+                        MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX      0x1b020
+                        MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX      0x1b020
+                >;
+        };
+
+        pinctrl_i2c1: i2c1grp {
+                fsl,pins = <
+                        MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
+                        MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
+                >;
+        };
+
+        pinctrl_i2c2: i2c2grp {
+                fsl,pins = <
+                        MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
+                        MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
+                >;
+        };
+
+        pinctrl_lcdif_dat: lcdifdatgrp {
+                fsl,pins = <
+                        MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x79
+                        MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x79
+                        MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x79
+                        MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x79
+                        MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x79
+                        MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x79
+                        MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x79
+                        MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x79
+                        MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x79
+                        MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x79
+                        MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x79
+                        MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x79
+                        MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x79
+                        MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x79
+                        MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x79
+                        MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x79
+                        MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x79
+                        MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x79
+                        MX6UL_PAD_LCD_DATA18__LCDIF_DATA18  0x79
+                        MX6UL_PAD_LCD_DATA19__LCDIF_DATA19  0x79
+                        MX6UL_PAD_LCD_DATA20__LCDIF_DATA20  0x79
+                        MX6UL_PAD_LCD_DATA21__LCDIF_DATA21  0x79
+                        MX6UL_PAD_LCD_DATA22__LCDIF_DATA22  0x79
+                        MX6UL_PAD_LCD_DATA23__LCDIF_DATA23  0x79
+                >;
+        };
+
+        pinctrl_lcdif_ctrl: lcdifctrlgrp {
+                fsl,pins = <
+                        MX6UL_PAD_LCD_CLK__LCDIF_CLK        0x79
+                        MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x79
+                        MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x79
+                        MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x79
+                        /* used for lcd reset */
+                        MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09  0x79
+                >;
+        };
+
+        pinctrl_qspi: qspigrp {
+                fsl,pins = <
+                        MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK        0x70a1
+                        MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00   0x70a1
+                        MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01     0x70a1
+                        MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02     0x70a1
+                        MX6UL_PAD_NAND_CLE__QSPI_A_DATA03       0x70a1
+                        MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B        0x70a1
+                >;
+        };
+
+        pinctrl_sai2: sai2grp {
+                fsl,pins = <
+                        MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK        0x17088
+                        MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC        0x17088
+                        MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA     0x11088
+                        MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA        0x11088
+                        MX6UL_PAD_JTAG_TMS__SAI2_MCLK           0x17088
+                        MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04      0x17059
+                >;
+        };
+
+        pinctrl_pwm1: pwm1grp {
+                fsl,pins = <
+                        MX6UL_PAD_GPIO1_IO08__PWM1_OUT   0x110b0
+                >;
+        };
+
+        pinctrl_sim2: sim2grp {
+                fsl,pins = <
+                        MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD             0xb808
+                        MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK            0x31
+                        MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B          0xb808
+                        MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN           0xb808
+                        MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD           0xb809
+                        MX6UL_PAD_CSI_DATA02__GPIO4_IO23                0x3008
+                >;
+        };
+
+        pinctrl_tsc: tscgrp {
+                fsl,pins = <
+                        MX6UL_PAD_GPIO1_IO01__GPIO1_IO01                0xb0
+                        MX6UL_PAD_GPIO1_IO02__GPIO1_IO02                0xb0
+                        MX6UL_PAD_GPIO1_IO03__GPIO1_IO03                0xb0
+                        MX6UL_PAD_GPIO1_IO04__GPIO1_IO04                0xb0
+                >;
+        };
+
+        pinctrl_uart1: uart1grp {
+                fsl,pins = <
+                        MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+                        MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+                >;
+        };
+
+        pinctrl_uart2: uart2grp {
+                fsl,pins = <
+                        MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x1b0b1
+                        MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x1b0b1
+                        MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS  0x1b0b1
+                        MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS  0x1b0b1
+                >;
+        };
+
+        pinctrl_usdhc1: usdhc1grp {
+                fsl,pins = <
+                        MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x17059
+                        MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x10059
+                        MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x17059
+                        MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x17059
+                        MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x17059
+                        MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x17059
+                        MX6UL_PAD_UART1_RTS_B__GPIO1_IO19       0x17059 /* SD1 CD */
+                        MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT    0x17059 /* SD1 VSELECT */
+                        MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059 /* SD1 RESET */
+                >;
+        };
+
+        pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+                fsl,pins = <
+                        MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
+                        MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
+                        MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
+                        MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
+                        MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
+                        MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
+
+                >;
+        };
+
+        pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+                fsl,pins = <
+                        MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
+                        MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
+                        MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
+                        MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
+                        MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
+                        MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
+                >;
+        };
+
+        pinctrl_usdhc2: usdhc2grp {
+                fsl,pins = <
+                        MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x17059
+                        MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
+                        MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+                        MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+                        MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+                        MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+                >;
+        };
+
+        pinctrl_wdog: wdoggrp {
+                fsl,pins = <
+                        MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY    0x30b0
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/imx6ul-geam.dts b/arch/arm/boot/dts/imx6ul-geam.dts
index 571eea7f1c6b..d81d20f8fc8d 100644
--- a/arch/arm/boot/dts/imx6ul-geam.dts
+++ b/arch/arm/boot/dts/imx6ul-geam.dts
@@ -50,7 +50,7 @@
         model = "Engicam GEAM6UL Starter Kit";
         compatible = "engicam,imx6ul-geam", "fsl,imx6ul";
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x08000000>;
         };
 
@@ -181,6 +181,7 @@
         sgtl5000: codec@a {
                 compatible = "fsl,sgtl5000";
                 reg = <0x0a>;
+                #sound-dai-cells = <0>;
                 clocks = <&clks IMX6UL_CLK_OSC>;
                 clock-names = "mclk";
                 VDDA-supply = <&reg_3p3v>;
diff --git a/arch/arm/boot/dts/imx6ul-isiot.dtsi b/arch/arm/boot/dts/imx6ul-isiot.dtsi
index 950fb28b630a..b0ecebb512b3 100644
--- a/arch/arm/boot/dts/imx6ul-isiot.dtsi
+++ b/arch/arm/boot/dts/imx6ul-isiot.dtsi
@@ -45,7 +45,7 @@
 #include "imx6ul.dtsi"
 
 / {
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x20000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6ul-litesom.dtsi b/arch/arm/boot/dts/imx6ul-litesom.dtsi
index 039721d3dcb4..8f775f6974d1 100644
--- a/arch/arm/boot/dts/imx6ul-litesom.dtsi
+++ b/arch/arm/boot/dts/imx6ul-litesom.dtsi
@@ -47,7 +47,7 @@
         model = "Grinn i.MX6UL liteSOM";
         compatible = "grinn,imx6ul-litesom", "fsl,imx6ul";
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x20000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx6ul-opos6ul.dtsi b/arch/arm/boot/dts/imx6ul-opos6ul.dtsi
index aec5ccce0321..a031bee311df 100644
--- a/arch/arm/boot/dts/imx6ul-opos6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul-opos6ul.dtsi
@@ -48,7 +48,7 @@
 #include "imx6ul.dtsi"
 
 / {
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0>; /* will be filled by U-Boot */
         };
 
diff --git a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts
index 3bf26ebd4df9..47682b8c023c 100644
--- a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts
+++ b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts
@@ -51,7 +51,7 @@
         model = "Technexion Pico i.MX6UL Board";
         compatible = "technexion,imx6ul-pico-hobbit", "fsl,imx6ul";
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x10000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx6ul-pinfunc.h b/arch/arm/boot/dts/imx6ul-pinfunc.h
index 0034eeb84542..7b9a4dc38456 100644
--- a/arch/arm/boot/dts/imx6ul-pinfunc.h
+++ b/arch/arm/boot/dts/imx6ul-pinfunc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright 2014 - 2015 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -34,14 +34,14 @@
 #define MX6UL_PAD_JTAG_MOD__ENET1_REF_CLK_25M           0x0044 0x02d0 0x0000 3 0
 #define MX6UL_PAD_JTAG_MOD__CCM_PMIC_RDY                0x0044 0x02d0 0x04c0 4 0
 #define MX6UL_PAD_JTAG_MOD__GPIO1_IO10                  0x0044 0x02d0 0x0000 5 0
-#define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00            0x0044 0x02d0 0x0000 6 0
+#define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00            0x0044 0x02d0 0x0610 6 0
 #define MX6UL_PAD_JTAG_TMS__SJC_TMS                     0x0048 0x02d4 0x0000 0 0
 #define MX6UL_PAD_JTAG_TMS__GPT2_CAPTURE1               0x0048 0x02d4 0x0598 1 0
-#define MX6UL_PAD_JTAG_TMS__SAI2_MCLK                   0x0048 0x02d4 0x0000 2 0
+#define MX6UL_PAD_JTAG_TMS__SAI2_MCLK                   0x0048 0x02d4 0x05f0 2 0
 #define MX6UL_PAD_JTAG_TMS__CCM_CLKO1                   0x0048 0x02d4 0x0000 3 0
 #define MX6UL_PAD_JTAG_TMS__CCM_WAIT                    0x0048 0x02d4 0x0000 4 0
 #define MX6UL_PAD_JTAG_TMS__GPIO1_IO11                  0x0048 0x02d4 0x0000 5 0
-#define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01            0x0048 0x02d4 0x0000 6 0
+#define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01            0x0048 0x02d4 0x0614 6 0
 #define MX6UL_PAD_JTAG_TMS__EPIT1_OUT                   0x0048 0x02d4 0x0000 8 0
 #define MX6UL_PAD_JTAG_TDO__SJC_TDO                     0x004c 0x02d8 0x0000 0 0
 #define MX6UL_PAD_JTAG_TDO__GPT2_CAPTURE2               0x004c 0x02d8 0x059c 1 0
@@ -63,12 +63,14 @@
 #define MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA                0x0054 0x02e0 0x05f4 2 0
 #define MX6UL_PAD_JTAG_TCK__PWM7_OUT                    0x0054 0x02e0 0x0000 4 0
 #define MX6UL_PAD_JTAG_TCK__GPIO1_IO14                  0x0054 0x02e0 0x0000 5 0
+#define MX6UL_PAD_JTAG_TCK__OSC32K_32K_OUT                      0x0054 0x02e0 0x0000 6 0
 #define MX6UL_PAD_JTAG_TCK__SIM2_POWER_FAIL             0x0054 0x02e0 0x0000 8 0
 #define MX6UL_PAD_JTAG_TRST_B__SJC_TRSTB                0x0058 0x02e4 0x0000 0 0
 #define MX6UL_PAD_JTAG_TRST_B__GPT2_COMPARE3            0x0058 0x02e4 0x0000 1 0
 #define MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA             0x0058 0x02e4 0x0000 2 0
 #define MX6UL_PAD_JTAG_TRST_B__PWM8_OUT                 0x0058 0x02e4 0x0000 4 0
 #define MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15               0x0058 0x02e4 0x0000 5 0
+#define MX6UL_PAD_JTAG_TRST_B__REF_CLK_24M              0x0058 0x02e4 0x0000 6 0
 #define MX6UL_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS         0x0058 0x02e4 0x0000 8 0
 #define MX6UL_PAD_GPIO1_IO00__I2C2_SCL                  0x005c 0x02e8 0x05ac 0 1
 #define MX6UL_PAD_GPIO1_IO00__GPT1_CAPTURE1             0x005c 0x02e8 0x058c 1 0
@@ -94,22 +96,24 @@
 #define MX6UL_PAD_GPIO1_IO02__ENET1_REF_CLK_25M         0x0064 0x02f0 0x0000 3 0
 #define MX6UL_PAD_GPIO1_IO02__USDHC1_WP                 0x0064 0x02f0 0x066c 4 0
 #define MX6UL_PAD_GPIO1_IO02__GPIO1_IO02                0x0064 0x02f0 0x0000 5 0
-#define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00          0x0064 0x02f0 0x0000 6 0
+#define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00          0x0064 0x02f0 0x0610 6 1
 #define MX6UL_PAD_GPIO1_IO02__SRC_ANY_PU_RESET          0x0064 0x02f0 0x0000 7 0
 #define MX6UL_PAD_GPIO1_IO02__UART1_DCE_TX              0x0064 0x02f0 0x0000 8 0
 #define MX6UL_PAD_GPIO1_IO02__UART1_DTE_RX              0x0064 0x02f0 0x0624 8 0
 #define MX6UL_PAD_GPIO1_IO03__I2C1_SDA                  0x0068 0x02f4 0x05a8 0 1
 #define MX6UL_PAD_GPIO1_IO03__GPT1_COMPARE3             0x0068 0x02f4 0x0000 1 0
 #define MX6UL_PAD_GPIO1_IO03__USB_OTG2_OC               0x0068 0x02f4 0x0660 2 0
+#define MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT            0x0068 0x02f4 0x0000 3 0
 #define MX6UL_PAD_GPIO1_IO03__USDHC1_CD_B               0x0068 0x02f4 0x0668 4 0
 #define MX6UL_PAD_GPIO1_IO03__GPIO1_IO03                0x0068 0x02f4 0x0000 5 0
-#define MX6UL_PAD_GPIO1_IO03__CCM_DI0_eXT_CLK           0x0068 0x02f4 0x0000 6 0
+#define MX6UL_PAD_GPIO1_IO03__CCM_DI0_EXT_CLK           0x0068 0x02f4 0x0000 6 0
 #define MX6UL_PAD_GPIO1_IO03__SRC_TESTER_ACK            0x0068 0x02f4 0x0000 7 0
-#define MX6UL_PAD_GPIO1_IO03__UART1_DTE_TX              0x0068 0x02f4 0x0000 8 0
 #define MX6UL_PAD_GPIO1_IO03__UART1_DCE_RX              0x0068 0x02f4 0x0624 8 1
+#define MX6UL_PAD_GPIO1_IO03__UART1_DTE_TX              0x0068 0x02f4 0x0000 8 0
 #define MX6UL_PAD_GPIO1_IO04__ENET1_REF_CLK1            0x006c 0x02f8 0x0574 0 1
 #define MX6UL_PAD_GPIO1_IO04__PWM3_OUT                  0x006c 0x02f8 0x0000 1 0
 #define MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR              0x006c 0x02f8 0x0000 2 0
+#define MX6UL_PAD_GPIO1_IO04__REF_CLK_24M               0x006c 0x02f8 0x0000 3 0
 #define MX6UL_PAD_GPIO1_IO04__USDHC1_RESET_B            0x006c 0x02f8 0x0000 4 0
 #define MX6UL_PAD_GPIO1_IO04__GPIO1_IO04                0x006c 0x02f8 0x0000 5 0
 #define MX6UL_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN      0x006c 0x02f8 0x0000 6 0
@@ -200,7 +204,7 @@
 #define MX6UL_PAD_UART2_TX_DATA__CSI_DATA06             0x0094 0x0320 0x04dc 3 0
 #define MX6UL_PAD_UART2_TX_DATA__GPT1_CAPTURE1          0x0094 0x0320 0x058c 4 1
 #define MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20             0x0094 0x0320 0x0000 5 0
-#define MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0             0x0094 0x0320 0x0000 8 0
+#define MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0             0x0094 0x0320 0x0560 8 0
 #define MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX           0x0098 0x0324 0x062c 0 1
 #define MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX           0x0098 0x0324 0x0000 0 0
 #define MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03          0x0098 0x0324 0x0000 1 0
@@ -232,7 +236,7 @@
 #define MX6UL_PAD_UART3_TX_DATA__UART3_DTE_RX           0x00a4 0x0330 0x0634 0 0
 #define MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02          0x00a4 0x0330 0x0000 1 0
 #define MX6UL_PAD_UART3_TX_DATA__SIM1_PORT0_PD          0x00a4 0x0330 0x0000 2 0
-#define MX6UL_PAD_UART3_TX_DATA__CSI_DATA01             0x00a4 0x0330 0x0000 3 0
+#define MX6UL_PAD_UART3_TX_DATA__CSI_DATA01             0x00a4 0x0330 0x04d4 3 0
 #define MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS          0x00a4 0x0330 0x0000 4 0
 #define MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS          0x00a4 0x0330 0x0628 4 2
 #define MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24             0x00a4 0x0330 0x0000 5 0
@@ -242,7 +246,7 @@
 #define MX6UL_PAD_UART3_RX_DATA__UART3_DTE_TX           0x00a8 0x0334 0x0000 0 0
 #define MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03          0x00a8 0x0334 0x0000 1 0
 #define MX6UL_PAD_UART3_RX_DATA__SIM2_PORT0_PD          0x00a8 0x0334 0x0000 2 0
-#define MX6UL_PAD_UART3_RX_DATA__CSI_DATA00             0x00a8 0x0334 0x0000 3 0
+#define MX6UL_PAD_UART3_RX_DATA__CSI_DATA00             0x00a8 0x0334 0x04d0 3 0
 #define MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS          0x00a8 0x0334 0x0628 4 3
 #define MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS          0x00a8 0x0334 0x0000 4 0
 #define MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25             0x00a8 0x0334 0x0000 5 0
@@ -251,7 +255,7 @@
 #define MX6UL_PAD_UART3_CTS_B__UART3_DTE_RTS            0x00ac 0x0338 0x0630 0 0
 #define MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK             0x00ac 0x0338 0x0000 1 0
 #define MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX              0x00ac 0x0338 0x0000 2 0
-#define MX6UL_PAD_UART3_CTS_B__CSI_DATA10               0x00ac 0x0338 0x0000 3 0
+#define MX6UL_PAD_UART3_CTS_B__CSI_DATA10               0x00ac 0x0338 0x04ec 3 0
 #define MX6UL_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN     0x00ac 0x0338 0x0000 4 0
 #define MX6UL_PAD_UART3_CTS_B__GPIO1_IO26               0x00ac 0x0338 0x0000 5 0
 #define MX6UL_PAD_UART3_CTS_B__EPIT2_OUT                0x00ac 0x0338 0x0000 8 0
@@ -259,7 +263,7 @@
 #define MX6UL_PAD_UART3_RTS_B__UART3_DTE_CTS            0x00b0 0x033c 0x0000 0 0
 #define MX6UL_PAD_UART3_RTS_B__ENET2_TX_ER              0x00b0 0x033c 0x0000 1 0
 #define MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX              0x00b0 0x033c 0x0584 2 0
-#define MX6UL_PAD_UART3_RTS_B__CSI_DATA11               0x00b0 0x033c 0x0000 3 0
+#define MX6UL_PAD_UART3_RTS_B__CSI_DATA11               0x00b0 0x033c 0x04f0 3 0
 #define MX6UL_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT    0x00b0 0x033c 0x0000 4 0
 #define MX6UL_PAD_UART3_RTS_B__GPIO1_IO27               0x00b0 0x033c 0x0000 5 0
 #define MX6UL_PAD_UART3_RTS_B__WDOG1_WDOG_B             0x00b0 0x033c 0x0000 8 0
@@ -267,7 +271,7 @@
 #define MX6UL_PAD_UART4_TX_DATA__UART4_DTE_RX           0x00b4 0x0340 0x063c 0 0
 #define MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02          0x00b4 0x0340 0x0000 1 0
 #define MX6UL_PAD_UART4_TX_DATA__I2C1_SCL               0x00b4 0x0340 0x05a4 2 1
-#define MX6UL_PAD_UART4_TX_DATA__CSI_DATA12             0x00b4 0x0340 0x0000 3 0
+#define MX6UL_PAD_UART4_TX_DATA__CSI_DATA12             0x00b4 0x0340 0x04f4 3 0
 #define MX6UL_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02    0x00b4 0x0340 0x0000 4 0
 #define MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28             0x00b4 0x0340 0x0000 5 0
 #define MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK            0x00b4 0x0340 0x0544 8 1
@@ -275,23 +279,23 @@
 #define MX6UL_PAD_UART4_RX_DATA__UART4_DTE_TX           0x00b8 0x0344 0x0000 0 0
 #define MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03          0x00b8 0x0344 0x0000 1 0
 #define MX6UL_PAD_UART4_RX_DATA__I2C1_SDA               0x00b8 0x0344 0x05a8 2 2
-#define MX6UL_PAD_UART4_RX_DATA__CSI_DATA13             0x00b8 0x0344 0x0000 3 0
+#define MX6UL_PAD_UART4_RX_DATA__CSI_DATA13             0x00b8 0x0344 0x04f8 3 0
 #define MX6UL_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01    0x00b8 0x0344 0x0000 4 0
 #define MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29             0x00b8 0x0344 0x0000 5 0
-#define MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0             0x00b8 0x0344 0x0000 8 0
+#define MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0             0x00b8 0x0344 0x0550 8 1
 #define MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30             0x00bc 0x0348 0x0000 5 0
 #define MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI            0x00bc 0x0348 0x054c 8 0
 #define MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX           0x00bc 0x0348 0x0000 0 0
 #define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX           0x00bc 0x0348 0x0644 0 4
 #define MX6UL_PAD_UART5_TX_DATA__ENET2_CRS              0x00bc 0x0348 0x0000 1 0
 #define MX6UL_PAD_UART5_TX_DATA__I2C2_SCL               0x00bc 0x0348 0x05ac 2 2
-#define MX6UL_PAD_UART5_TX_DATA__CSI_DATA14             0x00bc 0x0348 0x0000 3 0
+#define MX6UL_PAD_UART5_TX_DATA__CSI_DATA14             0x00bc 0x0348 0x04fc 3 0
 #define MX6UL_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00    0x00bc 0x0348 0x0000 4 0
 #define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX           0x00c0 0x034c 0x0644 0 5
 #define MX6UL_PAD_UART5_RX_DATA__UART5_DTE_TX           0x00c0 0x034c 0x0000 0 0
 #define MX6UL_PAD_UART5_RX_DATA__ENET2_COL              0x00c0 0x034c 0x0000 1 0
 #define MX6UL_PAD_UART5_RX_DATA__I2C2_SDA               0x00c0 0x034c 0x05b0 2 2
-#define MX6UL_PAD_UART5_RX_DATA__CSI_DATA15             0x00c0 0x034c 0x0000 3 0
+#define MX6UL_PAD_UART5_RX_DATA__CSI_DATA15             0x00c0 0x034c 0x0500 3 0
 #define MX6UL_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB        0x00c0 0x034c 0x0000 4 0
 #define MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31             0x00c0 0x034c 0x0000 5 0
 #define MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO            0x00c0 0x034c 0x0548 8 1
@@ -299,59 +303,61 @@
 #define MX6UL_PAD_ENET1_RX_DATA0__UART4_DCE_RTS         0x00c4 0x0350 0x0638 1 0
 #define MX6UL_PAD_ENET1_RX_DATA0__UART4_DTE_CTS         0x00c4 0x0350 0x0000 1 0
 #define MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT              0x00c4 0x0350 0x0000 2 0
-#define MX6UL_PAD_ENET1_RX_DATA0__CSI_DATA16            0x00c4 0x0350 0x0000 3 0
+#define MX6UL_PAD_ENET1_RX_DATA0__CSI_DATA16            0x00c4 0x0350 0x0504 3 0
 #define MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX           0x00c4 0x0350 0x0000 4 0
 #define MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00            0x00c4 0x0350 0x0000 5 0
-#define MX6UL_PAD_ENET1_RX_DATA0__KPP_ROW00             0x00c4 0x0350 0x0000 6 0
+#define MX6UL_PAD_ENET1_RX_DATA0__KPP_ROW00             0x00c4 0x0350 0x05d0 6 0
 #define MX6UL_PAD_ENET1_RX_DATA0__USDHC1_LCTL           0x00c4 0x0350 0x0000 8 0
 #define MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01         0x00c8 0x0354 0x0000 0 0
 #define MX6UL_PAD_ENET1_RX_DATA1__UART4_DCE_CTS         0x00c8 0x0354 0x0000 1 0
 #define MX6UL_PAD_ENET1_RX_DATA1__UART4_DTE_RTS         0x00c8 0x0354 0x0638 1 1
 #define MX6UL_PAD_ENET1_RX_DATA1__PWM2_OUT              0x00c8 0x0354 0x0000 2 0
-#define MX6UL_PAD_ENET1_RX_DATA1__CSI_DATA17            0x00c8 0x0354 0x0000 3 0
+#define MX6UL_PAD_ENET1_RX_DATA1__CSI_DATA17            0x00c8 0x0354 0x0508 3 0
 #define MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX           0x00c8 0x0354 0x0584 4 1
 #define MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01            0x00c8 0x0354 0x0000 5 0
-#define MX6UL_PAD_ENET1_RX_DATA1__KPP_COL00             0x00c8 0x0354 0x0000 6 0
+#define MX6UL_PAD_ENET1_RX_DATA1__KPP_COL00             0x00c8 0x0354 0x05c4 6 0
 #define MX6UL_PAD_ENET1_RX_DATA1__USDHC2_LCTL           0x00c8 0x0354 0x0000 8 0
 #define MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN              0x00cc 0x0358 0x0000 0 0
 #define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS            0x00cc 0x0358 0x0640 1 3
 #define MX6UL_PAD_ENET1_RX_EN__UART5_DTE_CTS            0x00cc 0x0358 0x0000 1 0
-#define MX6UL_PAD_ENET1_RX_EN__CSI_DATA18               0x00cc 0x0358 0x0000 3 0
+#define MX6UL_PAD_ENET1_RX_EN__OSC32K_32K_OUT           0x00cc 0x0358 0x0000 2 0
+#define MX6UL_PAD_ENET1_RX_EN__CSI_DATA18               0x00cc 0x0358 0x050c 3 0
 #define MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX              0x00cc 0x0358 0x0000 4 0
 #define MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02               0x00cc 0x0358 0x0000 5 0
-#define MX6UL_PAD_ENET1_RX_EN__KPP_ROW01                0x00cc 0x0358 0x0000 6 0
+#define MX6UL_PAD_ENET1_RX_EN__KPP_ROW01                0x00cc 0x0358 0x05d4 6 0
 #define MX6UL_PAD_ENET1_RX_EN__USDHC1_VSELECT           0x00cc 0x0358 0x0000 8 0
 #define MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00         0x00d0 0x035c 0x0000 0 0
 #define MX6UL_PAD_ENET1_TX_DATA0__UART5_DCE_CTS         0x00d0 0x035c 0x0000 1 0
 #define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS         0x00d0 0x035c 0x0640 1 4
-#define MX6UL_PAD_ENET1_TX_DATA0__CSI_DATA19            0x00d0 0x035c 0x0000 3 0
+#define MX6UL_PAD_ENET1_TX_DATA0__REF_CLK_24M           0x00d0 0x035c 0x0000 2 0
+#define MX6UL_PAD_ENET1_TX_DATA0__CSI_DATA19            0x00d0 0x035c 0x0510 3 0
 #define MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX           0x00d0 0x035c 0x0588 4 1
 #define MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03            0x00d0 0x035c 0x0000 5 0
-#define MX6UL_PAD_ENET1_TX_DATA0__KPP_COL01             0x00d0 0x035c 0x0000 6 0
+#define MX6UL_PAD_ENET1_TX_DATA0__KPP_COL01             0x00d0 0x035c 0x05c8 6 0
 #define MX6UL_PAD_ENET1_TX_DATA0__USDHC2_VSELECT        0x00d0 0x035c 0x0000 8 0
 #define MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01         0x00d4 0x0360 0x0000 0 0
 #define MX6UL_PAD_ENET1_TX_DATA1__UART6_DCE_CTS         0x00d4 0x0360 0x0000 1 0
 #define MX6UL_PAD_ENET1_TX_DATA1__UART6_DTE_RTS         0x00d4 0x0360 0x0648 1 2
 #define MX6UL_PAD_ENET1_TX_DATA1__PWM5_OUT              0x00d4 0x0360 0x0000 2 0
-#define MX6UL_PAD_ENET1_TX_DATA1__CSI_DATA20            0x00d4 0x0360 0x0000 3 0
+#define MX6UL_PAD_ENET1_TX_DATA1__CSI_DATA20            0x00d4 0x0360 0x0514 3 0
 #define MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO            0x00d4 0x0360 0x0580 4 1
 #define MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04            0x00d4 0x0360 0x0000 5 0
-#define MX6UL_PAD_ENET1_TX_DATA1__KPP_ROW02             0x00d4 0x0360 0x0000 6 0
+#define MX6UL_PAD_ENET1_TX_DATA1__KPP_ROW02             0x00d4 0x0360 0x05d8 6 0
 #define MX6UL_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB  0x00d4 0x0360 0x0000 8 0
 #define MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN              0x00d8 0x0364 0x0000 0 0
 #define MX6UL_PAD_ENET1_TX_EN__UART6_DCE_RTS            0x00d8 0x0364 0x0648 1 3
 #define MX6UL_PAD_ENET1_TX_EN__UART6_DTE_CTS            0x00d8 0x0364 0x0000 1 0
 #define MX6UL_PAD_ENET1_TX_EN__PWM6_OUT                 0x00d8 0x0364 0x0000 2 0
-#define MX6UL_PAD_ENET1_TX_EN__CSI_DATA21               0x00d8 0x0364 0x0000 3 0
+#define MX6UL_PAD_ENET1_TX_EN__CSI_DATA21               0x00d8 0x0364 0x0518 3 0
 #define MX6UL_PAD_ENET1_TX_EN__ENET2_MDC                0x00d8 0x0364 0x0000 4 0
 #define MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05               0x00d8 0x0364 0x0000 5 0
-#define MX6UL_PAD_ENET1_TX_EN__KPP_COL02                0x00d8 0x0364 0x0000 6 0
+#define MX6UL_PAD_ENET1_TX_EN__KPP_COL02                0x00d8 0x0364 0x05cc 6 0
 #define MX6UL_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB     0x00d8 0x0364 0x0000 8 0
 #define MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK            0x00dc 0x0368 0x0000 0 0
 #define MX6UL_PAD_ENET1_TX_CLK__UART7_DCE_CTS           0x00dc 0x0368 0x0000 1 0
 #define MX6UL_PAD_ENET1_TX_CLK__UART7_DTE_RTS           0x00dc 0x0368 0x0650 1 0
 #define MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT                0x00dc 0x0368 0x0000 2 0
-#define MX6UL_PAD_ENET1_TX_CLK__CSI_DATA22              0x00dc 0x0368 0x0000 3 0
+#define MX6UL_PAD_ENET1_TX_CLK__CSI_DATA22              0x00dc 0x0368 0x051c 3 0
 #define MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1          0x00dc 0x0368 0x0574 4 2
 #define MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06              0x00dc 0x0368 0x0000 5 0
 #define MX6UL_PAD_ENET1_TX_CLK__KPP_ROW03               0x00dc 0x0368 0x0000 6 0
@@ -360,7 +366,7 @@
 #define MX6UL_PAD_ENET1_RX_ER__UART7_DCE_RTS            0x00e0 0x036c 0x0650 1 1
 #define MX6UL_PAD_ENET1_RX_ER__UART7_DTE_CTS            0x00e0 0x036c 0x0000 1 0
 #define MX6UL_PAD_ENET1_RX_ER__PWM8_OUT                 0x00e0 0x036c 0x0000 2 0
-#define MX6UL_PAD_ENET1_RX_ER__CSI_DATA23               0x00e0 0x036c 0x0000 3 0
+#define MX6UL_PAD_ENET1_RX_ER__CSI_DATA23               0x00e0 0x036c 0x0520 3 0
 #define MX6UL_PAD_ENET1_RX_ER__EIM_CRE                  0x00e0 0x036c 0x0000 4 0
 #define MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07               0x00e0 0x036c 0x0000 5 0
 #define MX6UL_PAD_ENET1_RX_ER__KPP_COL03                0x00e0 0x036c 0x0000 6 0
@@ -377,7 +383,7 @@
 #define MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01         0x00e8 0x0374 0x0000 0 0
 #define MX6UL_PAD_ENET2_RX_DATA1__UART6_DCE_RX          0x00e8 0x0374 0x064c 1 2
 #define MX6UL_PAD_ENET2_RX_DATA1__UART6_DTE_TX          0x00e8 0x0374 0x0000 1 0
-#define MX6UL_PAD_ENET2_RX_DATA1__SIM1_PORT0_cLK        0x00e8 0x0374 0x0000 2 0
+#define MX6UL_PAD_ENET2_RX_DATA1__SIM1_PORT0_CLK        0x00e8 0x0374 0x0000 2 0
 #define MX6UL_PAD_ENET2_RX_DATA1__I2C3_SDA              0x00e8 0x0374 0x05b8 3 1
 #define MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC             0x00e8 0x0374 0x0000 4 0
 #define MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09            0x00e8 0x0374 0x0000 5 0
@@ -400,6 +406,7 @@
 #define MX6UL_PAD_ENET2_TX_DATA0__EIM_EB_B02            0x00f0 0x037c 0x0000 4 0
 #define MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11            0x00f0 0x037c 0x0000 5 0
 #define MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05             0x00f0 0x037c 0x0000 6 0
+#define MX6UL_PAD_ENET2_TX_DATA0__REF_CLK_24M           0x00f0 0x037c 0x0000 8 0
 #define MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01         0x00f4 0x0380 0x0000 0 0
 #define MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX          0x00f4 0x0380 0x0000 1 0
 #define MX6UL_PAD_ENET2_TX_DATA1__UART8_DTE_RX          0x00f4 0x0380 0x065c 1 0
@@ -412,7 +419,7 @@
 #define MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN              0x00f8 0x0384 0x0000 0 0
 #define MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX             0x00f8 0x0384 0x065c 1 1
 #define MX6UL_PAD_ENET2_TX_EN__UART8_DTE_TX             0x00f8 0x0384 0x0000 1 0
-#define MX6UL_PAD_ENET2_TX_EN__SIM2_PORT0_cLK           0x00f8 0x0384 0x0000 2 0
+#define MX6UL_PAD_ENET2_TX_EN__SIM2_PORT0_CLK           0x00f8 0x0384 0x0000 2 0
 #define MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI              0x00f8 0x0384 0x056c 3 0
 #define MX6UL_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN         0x00f8 0x0384 0x0000 4 0
 #define MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13               0x00f8 0x0384 0x0000 5 0
@@ -431,7 +438,7 @@
 #define MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS            0x0100 0x038c 0x0658 1 1
 #define MX6UL_PAD_ENET2_RX_ER__UART8_DTE_CTS            0x0100 0x038c 0x0000 1 0
 #define MX6UL_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN          0x0100 0x038c 0x0000 2 0
-#define MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0               0x0100 0x038c 0x0000 3 0
+#define MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0               0x0100 0x038c 0x0570 3 0
 #define MX6UL_PAD_ENET2_RX_ER__EIM_ADDR25               0x0100 0x038c 0x0000 4 0
 #define MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15               0x0100 0x038c 0x0000 5 0
 #define MX6UL_PAD_ENET2_RX_ER__KPP_COL07                0x0100 0x038c 0x0000 6 0
@@ -440,7 +447,7 @@
 #define MX6UL_PAD_LCD_CLK__LCDIF_WR_RWN                 0x0104 0x0390 0x0000 1 0
 #define MX6UL_PAD_LCD_CLK__UART4_DCE_TX                 0x0104 0x0390 0x0000 2 0
 #define MX6UL_PAD_LCD_CLK__UART4_DTE_RX                 0x0104 0x0390 0x063c 2 2
-#define MX6UL_PAD_LCD_CLK__SAI3_MCLK                    0x0104 0x0390 0x0000 3 0
+#define MX6UL_PAD_LCD_CLK__SAI3_MCLK                    0x0104 0x0390 0x0600 3 0
 #define MX6UL_PAD_LCD_CLK__EIM_CS2_B                    0x0104 0x0390 0x0000 4 0
 #define MX6UL_PAD_LCD_CLK__GPIO3_IO00                   0x0104 0x0390 0x0000 5 0
 #define MX6UL_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB         0x0104 0x0390 0x0000 8 0
@@ -464,7 +471,7 @@
 #define MX6UL_PAD_LCD_VSYNC__LCDIF_BUSY                 0x0110 0x039c 0x05dc 1 1
 #define MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS              0x0110 0x039c 0x0638 2 3
 #define MX6UL_PAD_LCD_VSYNC__UART4_DTE_CTS              0x0110 0x039c 0x0000 2 0
-#define MX6UL_PAD_LCD_VSYNC__SAI3_RX_DATA               0x0110 0x039c 0x0000 3 0
+#define MX6UL_PAD_LCD_VSYNC__SAI3_RX_DATA               0x0110 0x039c 0x0604 3 0
 #define MX6UL_PAD_LCD_VSYNC__WDOG2_WDOG_B               0x0110 0x039c 0x0000 4 0
 #define MX6UL_PAD_LCD_VSYNC__GPIO3_IO03                 0x0110 0x039c 0x0000 5 0
 #define MX6UL_PAD_LCD_VSYNC__ECSPI2_SS2                 0x0110 0x039c 0x0000 8 0
@@ -477,13 +484,15 @@
 #define MX6UL_PAD_LCD_RESET__ECSPI2_SS3                 0x0114 0x03a0 0x0000 8 0
 #define MX6UL_PAD_LCD_DATA00__LCDIF_DATA00              0x0118 0x03a4 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA00__PWM1_OUT                  0x0118 0x03a4 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA00__CA7_MX6UL_TRACE0          0x0118 0x03a4 0x0000 2 0
 #define MX6UL_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN      0x0118 0x03a4 0x0000 3 0
 #define MX6UL_PAD_LCD_DATA00__I2C3_SDA                  0x0118 0x03a4 0x05b8 4 2
 #define MX6UL_PAD_LCD_DATA00__GPIO3_IO05                0x0118 0x03a4 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA00__SRC_BT_CFG00              0x0118 0x03a4 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA00__SAI1_MCLK                 0x0118 0x03a4 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA00__SAI1_MCLK                 0x0118 0x03a4 0x05e0 8 1
 #define MX6UL_PAD_LCD_DATA01__LCDIF_DATA01              0x011c 0x03a8 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA01__PWM2_OUT                  0x011c 0x03a8 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA01__CA7_MX6UL_TRACE1          0x011c 0x03a8 0x0000 2 0
 #define MX6UL_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT     0x011c 0x03a8 0x0000 3 0
 #define MX6UL_PAD_LCD_DATA01__I2C3_SCL                  0x011c 0x03a8 0x05b4 4 2
 #define MX6UL_PAD_LCD_DATA01__GPIO3_IO06                0x011c 0x03a8 0x0000 5 0
@@ -491,6 +500,7 @@
 #define MX6UL_PAD_LCD_DATA01__SAI1_TX_SYNC              0x011c 0x03a8 0x05ec 8 0
 #define MX6UL_PAD_LCD_DATA02__LCDIF_DATA02              0x0120 0x03ac 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA02__PWM3_OUT                  0x0120 0x03ac 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA02__CA7_MX6UL_TRACE2          0x0120 0x03ac 0x0000 2 0
 #define MX6UL_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN      0x0120 0x03ac 0x0000 3 0
 #define MX6UL_PAD_LCD_DATA02__I2C4_SDA                  0x0120 0x03ac 0x05c0 4 2
 #define MX6UL_PAD_LCD_DATA02__GPIO3_IO07                0x0120 0x03ac 0x0000 5 0
@@ -498,14 +508,16 @@
 #define MX6UL_PAD_LCD_DATA02__SAI1_TX_BCLK              0x0120 0x03ac 0x05e8 8 0
 #define MX6UL_PAD_LCD_DATA03__LCDIF_DATA03              0x0124 0x03b0 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA03__PWM4_OUT                  0x0124 0x03b0 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA03__CA7_MX6UL_TRACE3          0x0124 0x03b0 0x0000 2 0
 #define MX6UL_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT     0x0124 0x03b0 0x0000 3 0
 #define MX6UL_PAD_LCD_DATA03__I2C4_SCL                  0x0124 0x03b0 0x05bc 4 2
 #define MX6UL_PAD_LCD_DATA03__GPIO3_IO08                0x0124 0x03b0 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA03__SRC_BT_CFG03              0x0124 0x03b0 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA              0x0124 0x03b0 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA              0x0124 0x03b0 0x05e4 8 0
 #define MX6UL_PAD_LCD_DATA04__LCDIF_DATA04              0x0128 0x03b4 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA04__UART8_DCE_CTS             0x0128 0x03b4 0x0000 1 0
 #define MX6UL_PAD_LCD_DATA04__UART8_DTE_RTS             0x0128 0x03b4 0x0658 1 2
+#define MX6UL_PAD_LCD_DATA04__CA7_MX6UL_TRACE4          0x0128 0x03b4 0x0000 2 0
 #define MX6UL_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN      0x0128 0x03b4 0x0000 3 0
 #define MX6UL_PAD_LCD_DATA04__SPDIF_SR_CLK              0x0128 0x03b4 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA04__GPIO3_IO09                0x0128 0x03b4 0x0000 5 0
@@ -514,6 +526,7 @@
 #define MX6UL_PAD_LCD_DATA05__LCDIF_DATA05              0x012c 0x03b8 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA05__UART8_DCE_RTS             0x012c 0x03b8 0x0658 1 3
 #define MX6UL_PAD_LCD_DATA05__UART8_DTE_CTS             0x012c 0x03b8 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA05__CA7_MX6UL_TRACE5          0x012c 0x03b8 0x0000 2 0
 #define MX6UL_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT     0x012c 0x03b8 0x0000 3 0
 #define MX6UL_PAD_LCD_DATA05__SPDIF_OUT                 0x012c 0x03b8 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA05__GPIO3_IO10                0x012c 0x03b8 0x0000 5 0
@@ -522,6 +535,7 @@
 #define MX6UL_PAD_LCD_DATA06__LCDIF_DATA06              0x0130 0x03bc 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA06__UART7_DCE_CTS             0x0130 0x03bc 0x0000 1 0
 #define MX6UL_PAD_LCD_DATA06__UART7_DTE_RTS             0x0130 0x03bc 0x0650 1 2
+#define MX6UL_PAD_LCD_DATA06__CA7_MX6UL_TRACE6          0x0130 0x03bc 0x0000 2 0
 #define MX6UL_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN      0x0130 0x03bc 0x0000 3 0
 #define MX6UL_PAD_LCD_DATA06__SPDIF_LOCK                0x0130 0x03bc 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA06__GPIO3_IO11                0x0130 0x03bc 0x0000 5 0
@@ -530,6 +544,7 @@
 #define MX6UL_PAD_LCD_DATA07__LCDIF_DATA07              0x0134 0x03c0 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA07__UART7_DCE_RTS             0x0134 0x03c0 0x0650 1 3
 #define MX6UL_PAD_LCD_DATA07__UART7_DTE_CTS             0x0134 0x03c0 0x0000 1 0
+#define MX6UL_PAD_LCD_DATA07__CA7_MX6UL_TRACE7          0x0134 0x03c0 0x0000 2 0
 #define MX6UL_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT     0x0134 0x03c0 0x0000 3 0
 #define MX6UL_PAD_LCD_DATA07__SPDIF_EXT_CLK             0x0134 0x03c0 0x061c 4 0
 #define MX6UL_PAD_LCD_DATA07__GPIO3_IO12                0x0134 0x03c0 0x0000 5 0
@@ -537,56 +552,64 @@
 #define MX6UL_PAD_LCD_DATA07__ECSPI1_SS3                0x0134 0x03c0 0x0000 8 0
 #define MX6UL_PAD_LCD_DATA08__LCDIF_DATA08              0x0138 0x03c4 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA08__SPDIF_IN                  0x0138 0x03c4 0x0618 1 2
-#define MX6UL_PAD_LCD_DATA08__CSI_DATA16                0x0138 0x03c4 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA08__CA7_MX6UL_TRACE8          0x0138 0x03c4 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA08__CSI_DATA16                0x0138 0x03c4 0x0504 3 1
 #define MX6UL_PAD_LCD_DATA08__EIM_DATA00                0x0138 0x03c4 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA08__GPIO3_IO13                0x0138 0x03c4 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA08__SRC_BT_CFG08              0x0138 0x03c4 0x0000 6 0
 #define MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX               0x0138 0x03c4 0x0000 8 0
 #define MX6UL_PAD_LCD_DATA09__LCDIF_DATA09              0x013c 0x03c8 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA09__SAI3_MCLK                 0x013c 0x03c8 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA09__CSI_DATA17                0x013c 0x03c8 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA09__SAI3_MCLK                 0x013c 0x03c8 0x0600 1 1
+#define MX6UL_PAD_LCD_DATA09__CA7_MX6UL_TRACE9          0x013c 0x03c8 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA09__CSI_DATA17                0x013c 0x03c8 0x0508 3 1
 #define MX6UL_PAD_LCD_DATA09__EIM_DATA01                0x013c 0x03c8 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA09__GPIO3_IO14                0x013c 0x03c8 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA09__SRC_BT_CFG09              0x013c 0x03c8 0x0000 6 0
 #define MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX               0x013c 0x03c8 0x0584 8 2
 #define MX6UL_PAD_LCD_DATA10__LCDIF_DATA10              0x0140 0x03cc 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA10__SAI3_RX_SYNC              0x0140 0x03cc 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA10__CSI_DATA18                0x0140 0x03cc 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA10__CA7_MX6UL_TRACE10         0x0140 0x03cc 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA10__CSI_DATA18                0x0140 0x03cc 0x050c 3 1
 #define MX6UL_PAD_LCD_DATA10__EIM_DATA02                0x0140 0x03cc 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA10__GPIO3_IO15                0x0140 0x03cc 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA10__SRC_BT_CFG10              0x0140 0x03cc 0x0000 6 0
 #define MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX               0x0140 0x03cc 0x0000 8 0
 #define MX6UL_PAD_LCD_DATA11__LCDIF_DATA11              0x0144 0x03d0 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA11__SAI3_RX_BCLK              0x0144 0x03d0 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA11__CSI_DATA19                0x0144 0x03d0 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA11__CA7_MX6UL_TRACE11         0x0144 0x03d0 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA11__CSI_DATA19                0x0144 0x03d0 0x0510 3 1
 #define MX6UL_PAD_LCD_DATA11__EIM_DATA03                0x0144 0x03d0 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA11__GPIO3_IO16                0x0144 0x03d0 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA11__SRC_BT_CFG11              0x0144 0x03d0 0x0000 6 0
 #define MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX               0x0144 0x03d0 0x0588 8 2
 #define MX6UL_PAD_LCD_DATA12__LCDIF_DATA12              0x0148 0x03d4 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA12__SAI3_TX_SYNC              0x0148 0x03d4 0x060c 1 1
-#define MX6UL_PAD_LCD_DATA12__CSI_DATA20                0x0148 0x03d4 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA12__CA7_MX6UL_TRACE12         0x0148 0x03d4 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA12__CSI_DATA20                0x0148 0x03d4 0x0514 3 1
 #define MX6UL_PAD_LCD_DATA12__EIM_DATA04                0x0148 0x03d4 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA12__GPIO3_IO17                0x0148 0x03d4 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA12__SRC_BT_CFG12              0x0148 0x03d4 0x0000 6 0
 #define MX6UL_PAD_LCD_DATA12__ECSPI1_RDY                0x0148 0x03d4 0x0000 8 0
 #define MX6UL_PAD_LCD_DATA13__LCDIF_DATA13              0x014c 0x03d8 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA13__SAI3_TX_BCLK              0x014c 0x03d8 0x0608 1 1
-#define MX6UL_PAD_LCD_DATA13__CSI_DATA21                0x014c 0x03d8 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA13__CA7_MX6UL_TRACE13         0x014c 0x03d8 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA13__CSI_DATA21                0x014c 0x03d8 0x0518 3 1
 #define MX6UL_PAD_LCD_DATA13__EIM_DATA05                0x014c 0x03d8 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA13__GPIO3_IO18                0x014c 0x03d8 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA13__SRC_BT_CFG13              0x014c 0x03d8 0x0000 6 0
 #define MX6UL_PAD_LCD_DATA13__USDHC2_RESET_B            0x014c 0x03d8 0x0000 8 0
 #define MX6UL_PAD_LCD_DATA14__LCDIF_DATA14              0x0150 0x03dc 0x0000 0 0
-#define MX6UL_PAD_LCD_DATA14__SAI3_RX_DATA              0x0150 0x03dc 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA14__CSI_DATA22                0x0150 0x03dc 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA14__SAI3_RX_DATA              0x0150 0x03dc 0x0604 1 1
+#define MX6UL_PAD_LCD_DATA14__CA7_MX6UL_TRACE14         0x0150 0x03dc 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA14__CSI_DATA22                0x0150 0x03dc 0x051c 3 1
 #define MX6UL_PAD_LCD_DATA14__EIM_DATA06                0x0150 0x03dc 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA14__GPIO3_IO19                0x0150 0x03dc 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA14__SRC_BT_CFG14              0x0150 0x03dc 0x0000 6 0
 #define MX6UL_PAD_LCD_DATA14__USDHC2_DATA4              0x0150 0x03dc 0x068c 8 0
 #define MX6UL_PAD_LCD_DATA15__LCDIF_DATA15              0x0154 0x03e0 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA15__SAI3_TX_DATA              0x0154 0x03e0 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA15__CSI_DATA23                0x0154 0x03e0 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA15__CA7_MX6UL_TRACE15         0x0154 0x03e0 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA15__CSI_DATA23                0x0154 0x03e0 0x0520 3 1
 #define MX6UL_PAD_LCD_DATA15__EIM_DATA07                0x0154 0x03e0 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA15__GPIO3_IO20                0x0154 0x03e0 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA15__SRC_BT_CFG15              0x0154 0x03e0 0x0000 6 0
@@ -594,7 +617,8 @@
 #define MX6UL_PAD_LCD_DATA16__LCDIF_DATA16              0x0158 0x03e4 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA16__UART7_DCE_TX              0x0158 0x03e4 0x0000 1 0
 #define MX6UL_PAD_LCD_DATA16__UART7_DTE_RX              0x0158 0x03e4 0x0654 1 2
-#define MX6UL_PAD_LCD_DATA16__CSI_DATA01                0x0158 0x03e4 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA16__CA7_MX6UL_TRACE_CLK       0x0158 0x03e4 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA16__CSI_DATA01                0x0158 0x03e4 0x04d4 3 1
 #define MX6UL_PAD_LCD_DATA16__EIM_DATA08                0x0158 0x03e4 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA16__GPIO3_IO21                0x0158 0x03e4 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA16__SRC_BT_CFG24              0x0158 0x03e4 0x0000 6 0
@@ -602,7 +626,8 @@
 #define MX6UL_PAD_LCD_DATA17__LCDIF_DATA17              0x015c 0x03e8 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA17__UART7_DCE_RX              0x015c 0x03e8 0x0654 1 3
 #define MX6UL_PAD_LCD_DATA17__UART7_DTE_TX              0x015c 0x03e8 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA17__CSI_DATA00                0x015c 0x03e8 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA17__CA7_MX6UL_TRACE_CTL       0x015c 0x03e8 0x0000 2 0
+#define MX6UL_PAD_LCD_DATA17__CSI_DATA00                0x015c 0x03e8 0x04d0 3 1
 #define MX6UL_PAD_LCD_DATA17__EIM_DATA09                0x015c 0x03e8 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA17__GPIO3_IO22                0x015c 0x03e8 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA17__SRC_BT_CFG25              0x015c 0x03e8 0x0000 6 0
@@ -610,7 +635,7 @@
 #define MX6UL_PAD_LCD_DATA18__LCDIF_DATA18              0x0160 0x03ec 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA18__PWM5_OUT                  0x0160 0x03ec 0x0000 1 0
 #define MX6UL_PAD_LCD_DATA18__CA7_MX6UL_EVENTO          0x0160 0x03ec 0x0000 2 0
-#define MX6UL_PAD_LCD_DATA18__CSI_DATA10                0x0160 0x03ec 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA18__CSI_DATA10                0x0160 0x03ec 0x04ec 3 1
 #define MX6UL_PAD_LCD_DATA18__EIM_DATA10                0x0160 0x03ec 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA18__GPIO3_IO23                0x0160 0x03ec 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA18__SRC_BT_CFG26              0x0160 0x03ec 0x0000 6 0
@@ -622,7 +647,7 @@
 #define MX6UL_PAD_LCD_DATA19__LCDIF_DATA19              0x0164 0x03f0 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA19__PWM6_OUT                  0x0164 0x03f0 0x0000 1 0
 #define MX6UL_PAD_LCD_DATA19__WDOG1_WDOG_ANY            0x0164 0x03f0 0x0000 2 0
-#define MX6UL_PAD_LCD_DATA19__CSI_DATA11                0x0164 0x03f0 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA19__CSI_DATA11                0x0164 0x03f0 0x04f0 3 1
 #define MX6UL_PAD_LCD_DATA20__EIM_DATA12                0x0168 0x03f4 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA20__GPIO3_IO25                0x0168 0x03f4 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA20__SRC_BT_CFG28              0x0168 0x03f4 0x0000 6 0
@@ -631,12 +656,12 @@
 #define MX6UL_PAD_LCD_DATA20__UART8_DCE_TX              0x0168 0x03f4 0x0000 1 0
 #define MX6UL_PAD_LCD_DATA20__UART8_DTE_RX              0x0168 0x03f4 0x065c 1 2
 #define MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK               0x0168 0x03f4 0x0534 2 0
-#define MX6UL_PAD_LCD_DATA20__CSI_DATA12                0x0168 0x03f4 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA20__CSI_DATA12                0x0168 0x03f4 0x04f4 3 1
 #define MX6UL_PAD_LCD_DATA21__LCDIF_DATA21              0x016c 0x03f8 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA21__UART8_DCE_RX              0x016c 0x03f8 0x065c 1 3
 #define MX6UL_PAD_LCD_DATA21__UART8_DTE_TX              0x016c 0x03f8 0x0000 1 0
-#define MX6UL_PAD_LCD_DATA21__ECSPI1_SS0                0x016c 0x03f8 0x0000 2 0
-#define MX6UL_PAD_LCD_DATA21__CSI_DATA13                0x016c 0x03f8 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA21__ECSPI1_SS0                0x016c 0x03f8 0x0540 2 0
+#define MX6UL_PAD_LCD_DATA21__CSI_DATA13                0x016c 0x03f8 0x04f8 3 1
 #define MX6UL_PAD_LCD_DATA21__EIM_DATA13                0x016c 0x03f8 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA21__GPIO3_IO26                0x016c 0x03f8 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA21__SRC_BT_CFG29              0x016c 0x03f8 0x0000 6 0
@@ -644,7 +669,7 @@
 #define MX6UL_PAD_LCD_DATA22__LCDIF_DATA22              0x0170 0x03fc 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA22__MQS_RIGHT                 0x0170 0x03fc 0x0000 1 0
 #define MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI               0x0170 0x03fc 0x053c 2 0
-#define MX6UL_PAD_LCD_DATA22__CSI_DATA14                0x0170 0x03fc 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA22__CSI_DATA14                0x0170 0x03fc 0x04fc 3 1
 #define MX6UL_PAD_LCD_DATA22__EIM_DATA14                0x0170 0x03fc 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA22__GPIO3_IO27                0x0170 0x03fc 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA22__SRC_BT_CFG30              0x0170 0x03fc 0x0000 6 0
@@ -652,7 +677,7 @@
 #define MX6UL_PAD_LCD_DATA23__LCDIF_DATA23              0x0174 0x0400 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA23__MQS_LEFT                  0x0174 0x0400 0x0000 1 0
 #define MX6UL_PAD_LCD_DATA23__ECSPI1_MISO               0x0174 0x0400 0x0538 2 0
-#define MX6UL_PAD_LCD_DATA23__CSI_DATA15                0x0174 0x0400 0x0000 3 0
+#define MX6UL_PAD_LCD_DATA23__CSI_DATA15                0x0174 0x0400 0x0500 3 1
 #define MX6UL_PAD_LCD_DATA23__EIM_DATA15                0x0174 0x0400 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA23__GPIO3_IO28                0x0174 0x0400 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA23__SRC_BT_CFG31              0x0174 0x0400 0x0000 6 0
@@ -660,42 +685,42 @@
 #define MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B               0x0178 0x0404 0x0000 0 0
 #define MX6UL_PAD_NAND_RE_B__USDHC2_CLK                 0x0178 0x0404 0x0670 1 2
 #define MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK                0x0178 0x0404 0x0000 2 0
-#define MX6UL_PAD_NAND_RE_B__KPP_ROW00                  0x0178 0x0404 0x0000 3 0
+#define MX6UL_PAD_NAND_RE_B__KPP_ROW00                  0x0178 0x0404 0x05d0 3 1
 #define MX6UL_PAD_NAND_RE_B__EIM_EB_B00                 0x0178 0x0404 0x0000 4 0
 #define MX6UL_PAD_NAND_RE_B__GPIO4_IO00                 0x0178 0x0404 0x0000 5 0
 #define MX6UL_PAD_NAND_RE_B__ECSPI3_SS2                 0x0178 0x0404 0x0000 8 0
 #define MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B               0x017c 0x0408 0x0000 0 0
 #define MX6UL_PAD_NAND_WE_B__USDHC2_CMD                 0x017c 0x0408 0x0678 1 2
 #define MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B               0x017c 0x0408 0x0000 2 0
-#define MX6UL_PAD_NAND_WE_B__KPP_COL00                  0x017c 0x0408 0x0000 3 0
+#define MX6UL_PAD_NAND_WE_B__KPP_COL00                  0x017c 0x0408 0x05c4 3 1
 #define MX6UL_PAD_NAND_WE_B__EIM_EB_B01                 0x017c 0x0408 0x0000 4 0
 #define MX6UL_PAD_NAND_WE_B__GPIO4_IO01                 0x017c 0x0408 0x0000 5 0
 #define MX6UL_PAD_NAND_WE_B__ECSPI3_SS3                 0x017c 0x0408 0x0000 8 0
 #define MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00           0x0180 0x040c 0x0000 0 0
 #define MX6UL_PAD_NAND_DATA00__USDHC2_DATA0             0x0180 0x040c 0x067c 1 2
 #define MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B             0x0180 0x040c 0x0000 2 0
-#define MX6UL_PAD_NAND_DATA00__KPP_ROW01                0x0180 0x040c 0x0000 3 0
+#define MX6UL_PAD_NAND_DATA00__KPP_ROW01                0x0180 0x040c 0x05d4 3 1
 #define MX6UL_PAD_NAND_DATA00__EIM_AD08                 0x0180 0x040c 0x0000 4 0
 #define MX6UL_PAD_NAND_DATA00__GPIO4_IO02               0x0180 0x040c 0x0000 5 0
 #define MX6UL_PAD_NAND_DATA00__ECSPI4_RDY               0x0180 0x040c 0x0000 8 0
 #define MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01           0x0184 0x0410 0x0000 0 0
 #define MX6UL_PAD_NAND_DATA01__USDHC2_DATA1             0x0184 0x0410 0x0680 1 2
 #define MX6UL_PAD_NAND_DATA01__QSPI_B_DQS               0x0184 0x0410 0x0000 2 0
-#define MX6UL_PAD_NAND_DATA01__KPP_COL01                0x0184 0x0410 0x0000 3 0
+#define MX6UL_PAD_NAND_DATA01__KPP_COL01                0x0184 0x0410 0x05c8 3 1
 #define MX6UL_PAD_NAND_DATA01__EIM_AD09                 0x0184 0x0410 0x0000 4 0
 #define MX6UL_PAD_NAND_DATA01__GPIO4_IO03               0x0184 0x0410 0x0000 5 0
 #define MX6UL_PAD_NAND_DATA01__ECSPI4_SS1               0x0184 0x0410 0x0000 8 0
 #define MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02           0x0188 0x0414 0x0000 0 0
 #define MX6UL_PAD_NAND_DATA02__USDHC2_DATA2             0x0188 0x0414 0x0684 1 1
 #define MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00            0x0188 0x0414 0x0000 2 0
-#define MX6UL_PAD_NAND_DATA02__KPP_ROW02                0x0188 0x0414 0x0000 3 0
+#define MX6UL_PAD_NAND_DATA02__KPP_ROW02                0x0188 0x0414 0x05d8 3 1
 #define MX6UL_PAD_NAND_DATA02__EIM_AD10                 0x0188 0x0414 0x0000 4 0
 #define MX6UL_PAD_NAND_DATA02__GPIO4_IO04               0x0188 0x0414 0x0000 5 0
 #define MX6UL_PAD_NAND_DATA02__ECSPI4_SS2               0x0188 0x0414 0x0000 8 0
 #define MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03           0x018c 0x0418 0x0000 0 0
 #define MX6UL_PAD_NAND_DATA03__USDHC2_DATA3             0x018c 0x0418 0x0688 1 2
 #define MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01            0x018c 0x0418 0x0000 2 0
-#define MX6UL_PAD_NAND_DATA03__KPP_COL02                0x018c 0x0418 0x0000 3 0
+#define MX6UL_PAD_NAND_DATA03__KPP_COL02                0x018c 0x0418 0x05cc 3 1
 #define MX6UL_PAD_NAND_DATA03__EIM_AD11                 0x018c 0x0418 0x0000 4 0
 #define MX6UL_PAD_NAND_DATA03__GPIO4_IO05               0x018c 0x0418 0x0000 5 0
 #define MX6UL_PAD_NAND_DATA03__ECSPI4_SS3               0x018c 0x0418 0x0000 8 0
@@ -726,7 +751,7 @@
 #define MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07           0x019c 0x0428 0x0000 0 0
 #define MX6UL_PAD_NAND_DATA07__USDHC2_DATA7             0x019c 0x0428 0x0698 1 1
 #define MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B             0x019c 0x0428 0x0000 2 0
-#define MX6UL_PAD_NAND_DATA07__ECSPI4_SS0               0x019c 0x0428 0x0000 3 0
+#define MX6UL_PAD_NAND_DATA07__ECSPI4_SS0               0x019c 0x0428 0x0570 3 1
 #define MX6UL_PAD_NAND_DATA07__EIM_AD15                 0x019c 0x0428 0x0000 4 0
 #define MX6UL_PAD_NAND_DATA07__GPIO4_IO09               0x019c 0x0428 0x0000 5 0
 #define MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS            0x019c 0x0428 0x0628 8 5
@@ -748,7 +773,7 @@
 #define MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B         0x01a8 0x0434 0x0000 0 0
 #define MX6UL_PAD_NAND_READY_B__USDHC1_DATA4            0x01a8 0x0434 0x0000 1 0
 #define MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00           0x01a8 0x0434 0x0000 2 0
-#define MX6UL_PAD_NAND_READY_B__ECSPI3_SS0              0x01a8 0x0434 0x0000 3 0
+#define MX6UL_PAD_NAND_READY_B__ECSPI3_SS0              0x01a8 0x0434 0x0560 3 1
 #define MX6UL_PAD_NAND_READY_B__EIM_CS1_B               0x01a8 0x0434 0x0000 4 0
 #define MX6UL_PAD_NAND_READY_B__GPIO4_IO12              0x01a8 0x0434 0x0000 5 0
 #define MX6UL_PAD_NAND_READY_B__UART3_DCE_TX            0x01a8 0x0434 0x0000 8 0
@@ -783,7 +808,7 @@
 #define MX6UL_PAD_NAND_DQS__PWM5_OUT                    0x01b8 0x0444 0x0000 3 0
 #define MX6UL_PAD_NAND_DQS__EIM_WAIT                    0x01b8 0x0444 0x0000 4 0
 #define MX6UL_PAD_NAND_DQS__GPIO4_IO16                  0x01b8 0x0444 0x0000 5 0
-#define MX6UL_PAD_NAND_DQS__SDMA_EXT_EVENT01            0x01b8 0x0444 0x0000 6 0
+#define MX6UL_PAD_NAND_DQS__SDMA_EXT_EVENT01            0x01b8 0x0444 0x0614 6 1
 #define MX6UL_PAD_NAND_DQS__SPDIF_EXT_CLK               0x01b8 0x0444 0x061c 8 1
 #define MX6UL_PAD_SD1_CMD__USDHC1_CMD                   0x01bc 0x0448 0x0000 0 0
 #define MX6UL_PAD_SD1_CMD__GPT2_COMPARE1                0x01bc 0x0448 0x0000 1 0
@@ -791,11 +816,11 @@
 #define MX6UL_PAD_SD1_CMD__SPDIF_OUT                    0x01bc 0x0448 0x0000 3 0
 #define MX6UL_PAD_SD1_CMD__EIM_ADDR19                   0x01bc 0x0448 0x0000 4 0
 #define MX6UL_PAD_SD1_CMD__GPIO2_IO16                   0x01bc 0x0448 0x0000 5 0
-#define MX6UL_PAD_SD1_CMD__SDMA_EXT_EVENT00             0x01bc 0x0448 0x0000 6 0
+#define MX6UL_PAD_SD1_CMD__SDMA_EXT_EVENT00             0x01bc 0x0448 0x0610 6 2
 #define MX6UL_PAD_SD1_CMD__USB_OTG1_PWR                 0x01bc 0x0448 0x0000 8 0
 #define MX6UL_PAD_SD1_CLK__USDHC1_CLK                   0x01c0 0x044c 0x0000 0 0
 #define MX6UL_PAD_SD1_CLK__GPT2_COMPARE2                0x01c0 0x044c 0x0000 1 0
-#define MX6UL_PAD_SD1_CLK__SAI2_MCLK                    0x01c0 0x044c 0x0000 2 0
+#define MX6UL_PAD_SD1_CLK__SAI2_MCLK                    0x01c0 0x044c 0x05f0 2 1
 #define MX6UL_PAD_SD1_CLK__SPDIF_IN                     0x01c0 0x044c 0x0618 3 3
 #define MX6UL_PAD_SD1_CLK__EIM_ADDR20                   0x01c0 0x044c 0x0000 4 0
 #define MX6UL_PAD_SD1_CLK__GPIO2_IO17                   0x01c0 0x044c 0x0000 5 0
@@ -878,10 +903,10 @@
 #define MX6UL_PAD_CSI_DATA01__CSI_DATA03                0x01e8 0x0474 0x04c8 0 0
 #define MX6UL_PAD_CSI_DATA01__USDHC2_DATA1              0x01e8 0x0474 0x0680 1 0
 #define MX6UL_PAD_CSI_DATA01__SIM1_PORT1_SVEN           0x01e8 0x0474 0x0000 2 0
-#define MX6UL_PAD_CSI_DATA01__ECSPI2_SS0                0x01e8 0x0474 0x0000 3 0
+#define MX6UL_PAD_CSI_DATA01__ECSPI2_SS0                0x01e8 0x0474 0x0550 3 0
 #define MX6UL_PAD_CSI_DATA01__EIM_AD01                  0x01e8 0x0474 0x0000 4 0
 #define MX6UL_PAD_CSI_DATA01__GPIO4_IO22                0x01e8 0x0474 0x0000 5 0
-#define MX6UL_PAD_CSI_DATA01__SAI1_MCLK                 0x01e8 0x0474 0x0000 6 0
+#define MX6UL_PAD_CSI_DATA01__SAI1_MCLK                 0x01e8 0x0474 0x05e0 6 0
 #define MX6UL_PAD_CSI_DATA01__UART5_DCE_RX              0x01e8 0x0474 0x0644 8 1
 #define MX6UL_PAD_CSI_DATA01__UART5_DTE_TX              0x01e8 0x0474 0x0000 8 0
 #define MX6UL_PAD_CSI_DATA02__CSI_DATA04                0x01ec 0x0478 0x04d8 0 1
@@ -913,7 +938,7 @@
 #define MX6UL_PAD_CSI_DATA05__CSI_DATA07                0x01f8 0x0484 0x04e0 0 1
 #define MX6UL_PAD_CSI_DATA05__USDHC2_DATA5              0x01f8 0x0484 0x0690 1 2
 #define MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B          0x01f8 0x0484 0x0000 2 0
-#define MX6UL_PAD_CSI_DATA05__ECSPI1_SS0                0x01f8 0x0484 0x0000 3 0
+#define MX6UL_PAD_CSI_DATA05__ECSPI1_SS0                0x01f8 0x0484 0x0540 3 1
 #define MX6UL_PAD_CSI_DATA05__EIM_AD05                  0x01f8 0x0484 0x0000 4 0
 #define MX6UL_PAD_CSI_DATA05__GPIO4_IO26                0x01f8 0x0484 0x0000 5 0
 #define MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK              0x01f8 0x0484 0x05e8 6 1
@@ -924,7 +949,7 @@
 #define MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI               0x01fc 0x0488 0x053c 3 1
 #define MX6UL_PAD_CSI_DATA06__EIM_AD06                  0x01fc 0x0488 0x0000 4 0
 #define MX6UL_PAD_CSI_DATA06__GPIO4_IO27                0x01fc 0x0488 0x0000 5 0
-#define MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA              0x01fc 0x0488 0x0000 6 0
+#define MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA              0x01fc 0x0488 0x05e4 6 1
 #define MX6UL_PAD_CSI_DATA06__USDHC1_RESET_B            0x01fc 0x0488 0x0000 8 0
 #define MX6UL_PAD_CSI_DATA07__CSI_DATA09                0x0200 0x048c 0x04e8 0 1
 #define MX6UL_PAD_CSI_DATA07__USDHC2_DATA7              0x0200 0x048c 0x0698 1 2
diff --git a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi
index 65111f9843f4..f678d18ad44a 100644
--- a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi
@@ -70,8 +70,8 @@
                 stdout-path = &uart1;
         };
 
-        memory {
-                reg = <0 0>; /* will be filled by U-Boot */
+        memory@80000000 {
+                reg = <0x80000000 0>; /* will be filled by U-Boot */
         };
 
         clocks {
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index 5d6c3ba36cd1..1241972b16ba 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -22,7 +22,7 @@
          * Also for U-Boot there must be a pre-existing /memory node.
          */
         chosen {};
-        memory { device_type = "memory"; reg = <0 0>; };
+        memory { device_type = "memory"; };
 
         aliases {
                 ethernet0 = &fec1;
@@ -86,15 +86,10 @@
                                  <&clks IMX6UL_CA7_SECONDARY_SEL>,
                                  <&clks IMX6UL_CLK_STEP>,
                                  <&clks IMX6UL_CLK_PLL1_SW>,
-                                 <&clks IMX6UL_CLK_PLL1_SYS>,
-                                 <&clks IMX6UL_PLL1_BYPASS>,
-                                 <&clks IMX6UL_CLK_PLL1>,
-                                 <&clks IMX6UL_PLL1_BYPASS_SRC>,
-                                 <&clks IMX6UL_CLK_OSC>;
+                                 <&clks IMX6UL_CLK_PLL1_SYS>;
                         clock-names = "arm", "pll2_bus",  "pll2_pfd2_396m",
                                       "secondary_sel", "step", "pll1_sw",
-                                      "pll1_sys", "pll1_bypass", "pll1",
-                                      "pll1_bypass_src", "osc";
+                                      "pll1_sys";
                         arm-supply = <&reg_arm>;
                         soc-supply = <&reg_soc>;
                 };
@@ -102,14 +97,26 @@
 
         intc: interrupt-controller@a01000 {
                 compatible = "arm,gic-400", "arm,cortex-a7-gic";
+                interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
                 #interrupt-cells = <3>;
                 interrupt-controller;
+                interrupt-parent = <&intc>;
                 reg = <0x00a01000 0x1000>,
                       <0x00a02000 0x2000>,
                       <0x00a04000 0x2000>,
                       <0x00a06000 0x2000>;
         };
 
+        timer {
+                compatible = "arm,armv7-timer";
+                interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+                interrupt-parent = <&intc>;
+                status = "disabled";
+        };
+
         ckil: clock-cli {
                 compatible = "fixed-clock";
                 #clock-cells = <0>;
@@ -924,6 +931,14 @@
                                 status = "disabled";
                         };
 
+                        wdog3: wdog@21e4000 {
+                                compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
+                                reg = <0x021e4000 0x4000>;
+                                interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX6UL_CLK_WDOG3>;
+                                status = "disabled";
+                        };
+
                         uart2: serial@21e8000 {
                                 compatible = "fsl,imx6ul-uart",
                                              "fsl,imx6q-uart";
diff --git a/arch/arm/boot/dts/imx6ull-14x14-evk.dts b/arch/arm/boot/dts/imx6ull-14x14-evk.dts
index 4741871434dd..30ef60344af3 100644
--- a/arch/arm/boot/dts/imx6ull-14x14-evk.dts
+++ b/arch/arm/boot/dts/imx6ull-14x14-evk.dts
@@ -39,7 +39,10 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-#include "imx6ul-14x14-evk.dts"
+/dts-v1/;
+
+#include "imx6ull.dtsi"
+#include "imx6ul-14x14-evk.dtsi"
 
 / {
         model = "Freescale i.MX6 UlltraLite 14x14 EVK Board";
diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts
new file mode 100644
index 000000000000..08669a18349e
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2018 Toradex AG
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-nonwifi.dtsi"
+#include "imx6ull-colibri-eval-v3.dtsi"
+
+/ {
+        model = "Toradex Colibri iMX6ULL 256MB on Colibri Evaluation Board V3";
+        compatible = "toradex,colibri-imx6ull-eval", "fsl,imx6ull";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
new file mode 100644
index 000000000000..006690ea98c0
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2017 Toradex AG
+ */
+
+/ {
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+
+        /* fixed crystal dedicated to mcp2515 */
+        clk16m: clk16m {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <16000000>;
+        };
+
+        panel: panel {
+                compatible = "edt,et057090dhu";
+                backlight = <&bl>;
+                power-supply = <&reg_3v3>;
+
+                port {
+                        panel_in: endpoint {
+                                remote-endpoint = <&lcdif_out>;
+                        };
+                };
+        };
+
+        reg_3v3: regulator-3v3 {
+                compatible = "regulator-fixed";
+                regulator-name = "3.3V";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
+
+        reg_5v0: regulator-5v0 {
+                compatible = "regulator-fixed";
+                regulator-name = "5V";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+        };
+
+        reg_usbh_vbus: regulator-usbh-vbus {
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_usbh_reg>;
+                regulator-name = "VCC_USB[1-4]";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
+                vin-supply = <&reg_5v0>;
+        };
+};
+
+&adc1 {
+        status = "okay";
+};
+
+&bl {
+        brightness-levels = <0 4 8 16 32 64 128 255>;
+        default-brightness-level = <6>;
+        power-supply = <&reg_3v3>;
+        pwms = <&pwm4 0 5000000 1>;
+        status = "okay";
+};
+
+&ecspi1 {
+        status = "okay";
+
+        mcp2515: can@0 {
+                compatible = "microchip,mcp2515";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_can_int>;
+                reg = <0>;
+                clocks = <&clk16m>;
+                interrupt-parent = <&gpio2>;
+                interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
+                spi-max-frequency = <10000000>;
+                vdd-supply = <&reg_3v3>;
+                xceiver-supply = <&reg_5v0>;
+                status = "okay";
+        };
+};
+
+&i2c1 {
+        status = "okay";
+
+        /* M41T0M6 real time clock on carrier board */
+        m41t0m6: rtc@68 {
+                compatible = "st,m41t0";
+                reg = <0x68>;
+        };
+};
+
+&lcdif {
+        status = "okay";
+
+        port {
+                lcdif_out: endpoint {
+                        remote-endpoint = <&panel_in>;
+                };
+        };
+};
+
+/* PWM <A> */
+&pwm4 {
+        status = "okay";
+};
+
+/* PWM <B> */
+&pwm5 {
+        status = "okay";
+};
+
+/* PWM <C> */
+&pwm6 {
+        status = "okay";
+};
+
+/* PWM <D> */
+&pwm7 {
+        status = "okay";
+};
+
+&uart1 {
+        status = "okay";
+};
+
+&uart2 {
+        status = "okay";
+};
+
+&uart5 {
+        status = "okay";
+};
+
+&usbotg1 {
+        status = "okay";
+};
+
+&usbotg2 {
+        vbus-supply = <&reg_usbh_vbus>;
+        status = "okay";
+};
+
+&usdhc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>;
+        no-1-8-v;
+        cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+        disable-wp;
+        wakeup-source;
+        keep-power-in-suspend;
+        vmmc-supply = <&reg_3v3>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi
new file mode 100644
index 000000000000..10ab4697950f
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2018 Toradex AG
+ */
+
+#include "imx6ull-colibri.dtsi"
+
+/ {
+        memory@80000000 {
+                reg = <0x80000000 0x10000000>;
+        };
+};
+
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3
+                &pinctrl_gpio4 &pinctrl_gpio5 &pinctrl_gpio6>;
+};
+
+&iomuxc_snvs {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio2 &pinctrl_snvs_gpio3>;
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts
new file mode 100644
index 000000000000..df72ce1ae2cb
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2018 Toradex AG
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-wifi.dtsi"
+#include "imx6ull-colibri-eval-v3.dtsi"
+
+/ {
+        model = "Toradex Colibri iMX6ULL 512MB on Colibri Evaluation Board V3";
+        compatible = "toradex,colibri-imx6ull-wifi-eval", "fsl,imx6ull";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi
new file mode 100644
index 000000000000..3dffbcd50bf6
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2018 Toradex AG
+ */
+
+#include "imx6ull-colibri.dtsi"
+
+/ {
+        memory@80000000 {
+                reg = <0x80000000 0x20000000>;
+        };
+
+        wifi_pwrseq: sdio-pwrseq {
+                compatible = "mmc-pwrseq-simple";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_snvs_wifi_pdn>;
+                reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
+        };
+};
+
+&cpu0 {
+        clock-frequency = <792000000>;
+        operating-points = <
+                /* kHz  uV */
+                792000  1225000
+                528000  1175000
+                396000  1025000
+                198000  950000
+        >;
+        fsl,soc-operating-points = <
+                /* KHz  uV */
+                792000  1175000
+                528000  1175000
+                396000  1175000
+                198000  1175000
+        >;
+};
+
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3
+                &pinctrl_gpio4 &pinctrl_gpio5>;
+
+};
+
+&iomuxc_snvs {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio2>;
+};
+
+&usdhc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc2>;
+        assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
+        assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
+        assigned-clock-rates = <0>, <198000000>;
+        cap-power-off-card;
+        keep-power-in-suspend;
+        mmc-pwrseq = <&wifi_pwrseq>;
+        no-1-8-v;
+        non-removable;
+        vmmc-supply = <&reg_module_3v3>;
+        wakeup-source;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi
new file mode 100644
index 000000000000..6c63a7384611
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi
@@ -0,0 +1,553 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2018 Toradex AG
+ */
+
+#include "imx6ull.dtsi"
+
+/ {
+        aliases {
+                ethernet0 = &fec2;
+                ethernet1 = &fec1;
+        };
+
+        bl: backlight {
+                compatible = "pwm-backlight";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_gpio_bl_on>;
+                enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+                status = "disabled";
+        };
+
+        reg_module_3v3: regulator-module-3v3 {
+                compatible = "regulator-fixed";
+                regulator-always-on;
+                regulator-name = "+V3.3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
+
+        reg_module_3v3_avdd: regulator-module-3v3-avdd {
+                compatible = "regulator-fixed";
+                regulator-always-on;
+                regulator-name = "+V3.3_AVDD_AUDIO";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
+
+        reg_sd1_vmmc: regulator-sd1-vmmc {
+                compatible = "regulator-gpio";
+                gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_snvs_reg_sd>;
+                regulator-always-on;
+                regulator-name = "+V3.3_1.8_SD";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <3300000>;
+                states = <1800000 0x1 3300000 0x0>;
+                vin-supply = <&reg_module_3v3>;
+        };
+};
+
+&adc1 {
+        num-channels = <10>;
+        vref-supply = <&reg_module_3v3_avdd>;
+};
+
+/* Colibri SPI */
+&ecspi1 {
+        cs-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
+};
+
+&fec2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet2>;
+        phy-mode = "rmii";
+        phy-handle = <&ethphy1>;
+        status = "okay";
+
+        mdio {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                ethphy1: ethernet-phy@2 {
+                        compatible = "ethernet-phy-ieee802.3-c22";
+                        max-speed = <100>;
+                        reg = <2>;
+                };
+        };
+};
+
+&gpmi {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_gpmi_nand>;
+        nand-on-flash-bbt;
+        nand-ecc-mode = "hw";
+        nand-ecc-strength = <8>;
+        nand-ecc-step-size = <512>;
+        status = "okay";
+};
+
+&i2c1 {
+        pinctrl-names = "default", "gpio";
+        pinctrl-0 = <&pinctrl_i2c1>;
+        pinctrl-1 = <&pinctrl_i2c1_gpio>;
+        sda-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
+        scl-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
+};
+
+&i2c2 {
+        pinctrl-names = "default", "gpio";
+        pinctrl-0 = <&pinctrl_i2c2>;
+        pinctrl-1 = <&pinctrl_i2c2_gpio>;
+        sda-gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
+        scl-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+        status = "okay";
+
+        ad7879@2c {
+                compatible = "adi,ad7879-1";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_snvs_ad7879_int>;
+                reg = <0x2c>;
+                interrupt-parent = <&gpio5>;
+                interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
+                touchscreen-max-pressure = <4096>;
+                adi,resistance-plate-x = <120>;
+                adi,first-conversion-delay = /bits/ 8 <3>;
+                adi,acquisition-time = /bits/ 8 <1>;
+                adi,median-filter-size = /bits/ 8 <2>;
+                adi,averaging = /bits/ 8 <1>;
+                adi,conversion-interval = /bits/ 8 <255>;
+        };
+};
+
+&lcdif {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_lcdif_dat
+                     &pinctrl_lcdif_ctrl>;
+};
+
+&pwm4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm4>;
+        #pwm-cells = <3>;
+};
+
+&pwm5 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm5>;
+        #pwm-cells = <3>;
+};
+
+&pwm6 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm6>;
+        #pwm-cells = <3>;
+};
+
+&pwm7 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm7>;
+        #pwm-cells = <3>;
+};
+
+&sdma {
+        status = "okay";
+};
+
+&snvs_pwrkey {
+        status = "disabled";
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>;
+        uart-has-rtscts;
+        fsl,dte-mode;
+};
+
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        uart-has-rtscts;
+        fsl,dte-mode;
+};
+
+&uart5 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart5>;
+        fsl,dte-mode;
+};
+
+&usbotg1 {
+        dr_mode = "otg";
+        srp-disable;
+        hnp-disable;
+        adp-disable;
+};
+
+&usbotg2 {
+        dr_mode = "host";
+};
+
+&usdhc1 {
+        assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>;
+        assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
+        assigned-clock-rates = <0>, <198000000>;
+};
+
+&iomuxc {
+        pinctrl_can_int: canint-grp {
+                fsl,pins = <
+                        MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04    0X14 /* SODIMM 73 */
+                >;
+        };
+
+        pinctrl_enet2: enet2-grp {
+                fsl,pins = <
+                        MX6UL_PAD_GPIO1_IO06__ENET2_MDIO        0x1b0b0
+                        MX6UL_PAD_GPIO1_IO07__ENET2_MDC         0x1b0b0
+                        MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
+                        MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
+                        MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x1b0b0
+                        MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x1b0b0
+                        MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x4001b031
+                        MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
+                        MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
+                        MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x1b0b0
+                >;
+        };
+
+        pinctrl_ecspi1_cs: ecspi1-cs-grp {
+                fsl,pins = <
+                        MX6UL_PAD_LCD_DATA21__GPIO3_IO26        0x000a0
+                >;
+        };
+
+        pinctrl_ecspi1: ecspi1-grp {
+                fsl,pins = <
+                        MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK       0x000a0
+                        MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI       0x000a0
+                        MX6UL_PAD_LCD_DATA23__ECSPI1_MISO       0x100a0
+                >;
+        };
+
+        pinctrl_flexcan2: flexcan2-grp {
+                fsl,pins = <
+                        MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX   0x1b020
+                        MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX      0x1b020
+                >;
+        };
+
+        pinctrl_gpio_bl_on: gpio-bl-on-grp {
+                fsl,pins = <
+                        MX6UL_PAD_JTAG_TMS__GPIO1_IO11          0x000a0
+                >;
+        };
+
+        pinctrl_gpio1: gpio1-grp {
+                fsl,pins = <
+                        MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00    0x74 /* SODIMM 55 */
+                        MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01    0x74 /* SODIMM 63 */
+                        MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25     0X14 /* SODIMM 77 */
+                        MX6UL_PAD_JTAG_TCK__GPIO1_IO14          0x14 /* SODIMM 99 */
+                        MX6UL_PAD_NAND_CE1_B__GPIO4_IO14        0x14 /* SODIMM 133 */
+                        MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24     0x14 /* SODIMM 135 */
+                        MX6UL_PAD_UART3_CTS_B__GPIO1_IO26       0x14 /* SODIMM 100 */
+                        MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15       0x14 /* SODIMM 102 */
+                        MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07       0x14 /* SODIMM 104 */
+                        MX6UL_PAD_UART3_RTS_B__GPIO1_IO27       0x14 /* SODIMM 186 */
+                >;
+        };
+
+        pinctrl_gpio2: gpio2-grp { /* Camera */
+                fsl,pins = <
+                        MX6UL_PAD_CSI_DATA04__GPIO4_IO25        0x74 /* SODIMM 69 */
+                        MX6UL_PAD_CSI_MCLK__GPIO4_IO17          0x14 /* SODIMM 75 */
+                        MX6UL_PAD_CSI_DATA06__GPIO4_IO27        0x14 /* SODIMM 85 */
+                        MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18        0x14 /* SODIMM 96 */
+                        MX6UL_PAD_CSI_DATA05__GPIO4_IO26        0x14 /* SODIMM 98 */
+                >;
+        };
+
+        pinctrl_gpio3: gpio3-grp { /* CAN2 */
+                fsl,pins = <
+                        MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02       0x14 /* SODIMM 178 */
+                        MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03    0x14 /* SODIMM 188 */
+                >;
+        };
+
+        pinctrl_gpio4: gpio4-grp {
+                fsl,pins = <
+                        MX6UL_PAD_CSI_DATA07__GPIO4_IO28        0x74 /* SODIMM 65 */
+                >;
+        };
+
+        pinctrl_gpio5: gpio5-grp { /* ATMEL MXT TOUCH */
+                fsl,pins = <
+                        MX6UL_PAD_JTAG_MOD__GPIO1_IO10          0x74 /* SODIMM 106 */
+                >;
+        };
+
+        pinctrl_gpio6: gpio6-grp { /* Wifi pins */
+                fsl,pins = <
+                        MX6UL_PAD_GPIO1_IO03__GPIO1_IO03        0x14 /* SODIMM 89 */
+                        MX6UL_PAD_CSI_DATA02__GPIO4_IO23        0x14 /* SODIMM 79 */
+                        MX6UL_PAD_CSI_VSYNC__GPIO4_IO19         0x14 /* SODIMM 81 */
+                        MX6UL_PAD_CSI_DATA03__GPIO4_IO24        0x14 /* SODIMM 97 */
+                        MX6UL_PAD_CSI_DATA00__GPIO4_IO21        0x14 /* SODIMM 101 */
+                        MX6UL_PAD_CSI_DATA01__GPIO4_IO22        0x14 /* SODIMM 103 */
+                        MX6UL_PAD_CSI_HSYNC__GPIO4_IO20         0x14 /* SODIMM 94 */
+                >;
+        };
+
+        pinctrl_gpmi_nand: gpmi-nand-grp {
+                fsl,pins = <
+                        MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0x100a9
+                        MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0x100a9
+                        MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0x100a9
+                        MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0x100a9
+                        MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0x100a9
+                        MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0x100a9
+                        MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0x100a9
+                        MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0x100a9
+                        MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0x100a9
+                        MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0x100a9
+                        MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0x100a9
+                        MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0x100a9
+                        MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0x100a9
+                        MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x100a9
+                >;
+        };
+
+        pinctrl_i2c1: i2c1-grp {
+                fsl,pins = <
+                        MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
+                        MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
+                >;
+        };
+
+        pinctrl_i2c1_gpio: i2c1-gpio-grp {
+                fsl,pins = <
+                        MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0
+                        MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0
+                >;
+        };
+
+        pinctrl_i2c2: i2c2-grp {
+                fsl,pins = <
+                        MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
+                        MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
+                >;
+        };
+
+        pinctrl_i2c2_gpio: i2c2-gpio-grp {
+                fsl,pins = <
+                        MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0
+                        MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0
+                >;
+        };
+
+        pinctrl_lcdif_dat: lcdif-dat-grp {
+                fsl,pins = <
+                        MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x00079
+                        MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x00079
+                        MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x00079
+                        MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x00079
+                        MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x00079
+                        MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x00079
+                        MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x00079
+                        MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x00079
+                        MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x00079
+                        MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x00079
+                        MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x00079
+                        MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x00079
+                        MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x00079
+                        MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x00079
+                        MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x00079
+                        MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x00079
+                        MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x00079
+                        MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x00079
+                >;
+        };
+
+        pinctrl_lcdif_ctrl: lcdif-ctrl-grp {
+                fsl,pins = <
+                        MX6UL_PAD_LCD_CLK__LCDIF_CLK        0x00079
+                        MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x00079
+                        MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x00079
+                        MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x00079
+                >;
+        };
+
+        pinctrl_pwm4: pwm4-grp {
+                fsl,pins = <
+                        MX6UL_PAD_NAND_WP_B__PWM4_OUT   0x00079
+                >;
+        };
+
+        pinctrl_pwm5: pwm5-grp {
+                fsl,pins = <
+                        MX6UL_PAD_NAND_DQS__PWM5_OUT    0x00079
+                >;
+        };
+
+        pinctrl_pwm6: pwm6-grp {
+                fsl,pins = <
+                        MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079
+                >;
+        };
+
+        pinctrl_pwm7: pwm7-grp {
+                fsl,pins = <
+                        MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT        0x00079
+                >;
+        };
+
+        pinctrl_uart1: uart1-grp {
+                fsl,pins = <
+                        MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX   0x1b0b1
+                        MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX   0x1b0b1
+                        MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS    0x1b0b1
+                        MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS    0x1b0b1
+                >;
+        };
+
+        pinctrl_uart1_ctrl1: uart1-ctrl1-grp { /* Additional DTR, DCD */
+                fsl,pins = <
+                        MX6UL_PAD_JTAG_TDI__GPIO1_IO13          0x1b0b1 /* DCD */
+                        MX6UL_PAD_LCD_DATA18__GPIO3_IO23        0x1b0b1 /* DSR */
+                        MX6UL_PAD_JTAG_TDO__GPIO1_IO12          0x1b0b1 /* DTR */
+                        MX6UL_PAD_LCD_DATA19__GPIO3_IO24        0x1b0b1 /* RI */
+                >;
+        };
+
+        pinctrl_uart2: uart2-grp {
+                fsl,pins = <
+                        MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX   0x1b0b1
+                        MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX   0x1b0b1
+                        MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS    0x1b0b1
+                        MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS    0x1b0b1
+                >;
+        };
+        pinctrl_uart5: uart5-grp {
+                fsl,pins = <
+                        MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX      0x1b0b1
+                        MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX      0x1b0b1
+                >;
+        };
+
+        pinctrl_usbh_reg: gpio-usbh-reg {
+                fsl,pins = <
+                        MX6UL_PAD_GPIO1_IO02__GPIO1_IO02        0x1b0b1 /* SODIMM 129 USBH PEN */
+                >;
+        };
+
+        pinctrl_usdhc1: usdhc1-grp {
+                fsl,pins = <
+                        MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x17059
+                        MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x10059
+                        MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x17059
+                        MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x17059
+                        MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x17059
+                        MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x17059
+                >;
+        };
+
+        pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
+                fsl,pins = <
+                        MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x170b9
+                        MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x100b9
+                        MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x170b9
+                        MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x170b9
+                        MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x170b9
+                        MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x170b9
+                >;
+        };
+
+        pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
+                fsl,pins = <
+                        MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x170f9
+                        MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x100f9
+                        MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x170b9
+                        MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x170b9
+                        MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x170b9
+                        MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x170b9
+                >;
+        };
+
+        pinctrl_usdhc2: usdhc2-grp {
+                fsl,pins = <
+                        MX6UL_PAD_CSI_DATA00__USDHC2_DATA0      0x17059
+                        MX6UL_PAD_CSI_DATA01__USDHC2_DATA1      0x17059
+                        MX6UL_PAD_CSI_DATA02__USDHC2_DATA2      0x17059
+                        MX6UL_PAD_CSI_DATA03__USDHC2_DATA3      0x17059
+                        MX6UL_PAD_CSI_HSYNC__USDHC2_CMD         0x17059
+                        MX6UL_PAD_CSI_VSYNC__USDHC2_CLK         0x17059
+
+                        MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT    0x14
+                >;
+        };
+};
+
+&iomuxc_snvs {
+        pinctrl_snvs_gpio1: snvs-gpio1-grp {
+                fsl,pins = <
+                        MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06     0x14 /* SODIMM 93 */
+                        MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03     0x14 /* SODIMM 95 */
+                        MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10       0x74 /* SODIMM 105 */
+                        MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05     0x14 /* SODIMM 131 USBH OC */
+                        MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08     0x74 /* SODIMM 138 */
+                >;
+        };
+
+        pinctrl_snvs_gpio2: snvs-gpio2-grp { /* ATMEL MXT TOUCH */
+                fsl,pins = <
+                        MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04     0x74 /* SODIMM 107 */
+                >;
+        };
+
+        pinctrl_snvs_gpio3: snvs-gpio3-grp { /* Wifi pins */
+                fsl,pins = <
+                        MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11       0x14 /* SODIMM 127 */
+                >;
+        };
+
+        pinctrl_snvs_ad7879_int: snvs-ad7879-int-grp { /* TOUCH Interrupt */
+                fsl,pins = <
+                        MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07     0x1b0b0
+                >;
+        };
+
+        pinctrl_snvs_reg_sd: snvs-reg-sd-grp {
+                fsl,pins = <
+                        MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09     0x4001b8b0
+                >;
+        };
+
+        pinctrl_snvs_usbc_det: snvs-usbc-det-grp {
+                fsl,pins = <
+                        MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02     0x1b0b0
+                >;
+        };
+
+        pinctrl_snvs_gpiokeys: snvs-gpiokeys-grp {
+                fsl,pins = <
+                        MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01     0x130b0
+                >;
+        };
+
+        pinctrl_snvs_usdhc1_cd: snvs-usdhc1-cd-grp {
+                fsl,pins = <
+                        MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00     0x1b0b0 /* CD */
+                >;
+        };
+
+        pinctrl_snvs_wifi_pdn: snvs-wifi-pdn-grp {
+                fsl,pins = <
+                        MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11       0x14
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/imx6ull-pinfunc-snvs.h b/arch/arm/boot/dts/imx6ull-pinfunc-snvs.h
new file mode 100644
index 000000000000..f6fb6783c193
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-pinfunc-snvs.h
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright (C) 2017 NXP
+ */
+
+#ifndef __DTS_IMX6ULL_PINFUNC_SNVS_H
+#define __DTS_IMX6ULL_PINFUNC_SNVS_H
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10                          0x0000 0x0044 0x0000 0x5 0x0
+#define MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11                          0x0004 0x0048 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00                        0x0008 0x004C 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01                        0x000C 0x0050 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02                        0x0010 0x0054 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03                        0x0014 0x0058 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04                        0x0018 0x005C 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05                        0x001C 0x0060 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06                        0x0020 0x0064 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07                        0x0024 0x0068 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08                        0x0028 0x006C 0x0000 0x5 0x0
+#define MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09                        0x002C 0x0070 0x0000 0x5 0x0
+
+#endif /* __DTS_IMX6ULL_PINFUNC_SNVS_H */
diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi
index 0c182917b863..571ddd71cdba 100644
--- a/arch/arm/boot/dts/imx6ull.dtsi
+++ b/arch/arm/boot/dts/imx6ull.dtsi
@@ -41,3 +41,35 @@
 
 #include "imx6ul.dtsi"
 #include "imx6ull-pinfunc.h"
+#include "imx6ull-pinfunc-snvs.h"
+
+/* Delete UART8 in AIPS-1 (i.MX6UL specific) */
+/delete-node/ &uart8;
+
+/ {
+        soc {
+                aips3: aips-bus@2200000 {
+                        compatible = "fsl,aips-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x02200000 0x100000>;
+                        ranges;
+
+                        iomuxc_snvs: iomuxc-snvs@2290000 {
+                                compatible = "fsl,imx6ull-iomuxc-snvs";
+                                reg = <0x02290000 0x4000>;
+                        };
+
+                        uart8: serial@2288000 {
+                                compatible = "fsl,imx6ul-uart",
+                                             "fsl,imx6q-uart";
+                                reg = <0x02288000 0x4000>;
+                                interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX6UL_CLK_UART8_IPG>,
+                                         <&clks IMX6UL_CLK_UART8_SERIAL>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
index ae45af1ad062..7f645683f53b 100644
--- a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
+++ b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
@@ -18,7 +18,7 @@
         model = "CompuLab CL-SOM-iMX7";
         compatible = "compulab,cl-som-imx7", "fsl,imx7d";
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x10000000>; /* 256 MB - minimal configuration */
         };
 
@@ -213,37 +213,37 @@
 &iomuxc {
         pinctrl_enet1: enet1grp {
                 fsl,pins = <
-                        MX7D_PAD_SD2_CD_B__ENET1_MDIO                   0x3
-                        MX7D_PAD_SD2_WP__ENET1_MDC                      0x3
-                        MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC       0x1
-                        MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0       0x1
-                        MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1       0x1
-                        MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2       0x1
-                        MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3       0x1
-                        MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
-                        MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC       0x1
-                        MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0       0x1
-                        MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1       0x1
-                        MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2       0x1
-                        MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3       0x1
-                        MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
+                        MX7D_PAD_SD2_CD_B__ENET1_MDIO                   0x30
+                        MX7D_PAD_SD2_WP__ENET1_MDC                      0x30
+                        MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC       0x11
+                        MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0       0x11
+                        MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1       0x11
+                        MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2       0x11
+                        MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3       0x11
+                        MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x11
+                        MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC       0x11
+                        MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0       0x11
+                        MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1       0x11
+                        MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2       0x11
+                        MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3       0x11
+                        MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x11
                 >;
         };
 
         pinctrl_enet2: enet2grp {
                 fsl,pins = <
-                        MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC             0x1
-                        MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0            0x1
-                        MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1            0x1
-                        MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2            0x1
-                        MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3             0x1
-                        MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL          0x1
-                        MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC            0x1
-                        MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0            0x1
-                        MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1             0x1
-                        MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2             0x1
-                        MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3            0x1
-                        MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL         0x1
+                        MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC             0x11
+                        MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0            0x11
+                        MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1            0x11
+                        MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2            0x11
+                        MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3             0x11
+                        MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL          0x11
+                        MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC            0x11
+                        MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0            0x11
+                        MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1             0x11
+                        MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2             0x11
+                        MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3            0x11
+                        MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL         0x11
                 >;
         };
 
diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi b/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi
index 9b63b9c89e4b..04d24ee17b14 100644
--- a/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi
+++ b/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi
@@ -7,7 +7,7 @@
 #include "imx7-colibri.dtsi"
 
 / {
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x40000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx7d-colibri.dtsi b/arch/arm/boot/dts/imx7d-colibri.dtsi
index 6f2bb70c1fbd..d9f8fb69511b 100644
--- a/arch/arm/boot/dts/imx7d-colibri.dtsi
+++ b/arch/arm/boot/dts/imx7d-colibri.dtsi
@@ -44,7 +44,7 @@
 #include "imx7-colibri.dtsi"
 
 / {
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x20000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx7d-nitrogen7.dts b/arch/arm/boot/dts/imx7d-nitrogen7.dts
index 2b05898bb3f6..52167298984d 100644
--- a/arch/arm/boot/dts/imx7d-nitrogen7.dts
+++ b/arch/arm/boot/dts/imx7d-nitrogen7.dts
@@ -53,7 +53,7 @@
                 t_lcd = &t_lcd;
         };
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x40000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx7d-pico.dtsi b/arch/arm/boot/dts/imx7d-pico.dtsi
index e307462a48ec..21973eb55671 100644
--- a/arch/arm/boot/dts/imx7d-pico.dtsi
+++ b/arch/arm/boot/dts/imx7d-pico.dtsi
@@ -48,7 +48,7 @@
         model = "Technexion Pico i.MX7D Board";
         compatible = "technexion,imx7d-pico", "fsl,imx7d";
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x80000000>;
         };
 
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index a7a5dc7b2700..7f241afc15ea 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -48,7 +48,7 @@
         model = "Freescale i.MX7 SabreSD Board";
         compatible = "fsl,imx7d-sdb", "fsl,imx7d";
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x80000000>;
         };
 
@@ -336,6 +336,11 @@
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_i2c2>;
         status = "okay";
+
+        mpl3115@60 {
+                compatible = "fsl,mpl3115";
+                reg = <0x60>;
+        };
 };
 
 &i2c3 {
diff --git a/arch/arm/boot/dts/imx7s-colibri.dtsi b/arch/arm/boot/dts/imx7s-colibri.dtsi
index b81013455b21..fe8344cee864 100644
--- a/arch/arm/boot/dts/imx7s-colibri.dtsi
+++ b/arch/arm/boot/dts/imx7s-colibri.dtsi
@@ -44,7 +44,7 @@
 #include "imx7-colibri.dtsi"
 
 / {
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x10000000>;
         };
 };
diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts
index 9bdf121f7e43..8a30b148534d 100644
--- a/arch/arm/boot/dts/imx7s-warp.dts
+++ b/arch/arm/boot/dts/imx7s-warp.dts
@@ -50,7 +50,7 @@
         model = "Warp i.MX7 Board";
         compatible = "warp,imx7s-warp", "fsl,imx7s";
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x20000000>;
         };
 
@@ -271,6 +271,15 @@
         status = "okay";
 };
 
+&uart6 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart6>;
+        assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
+        assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+        fsl,dte-mode;
+        status = "okay";
+};
+
 &usbotg1 {
         dr_mode = "peripheral";
         status = "okay";
@@ -379,6 +388,13 @@
                 >;
         };
 
+        pinctrl_uart6: uart6grp {
+                fsl,pins = <
+                        MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX      0x79
+                        MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX      0x79
+                >;
+        };
+
         pinctrl_usdhc1: usdhc1grp {
                 fsl,pins = <
                         MX7D_PAD_SD1_CMD__SD1_CMD       0x59
diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
index 9aa2bb998552..4d42335c0dee 100644
--- a/arch/arm/boot/dts/imx7s.dtsi
+++ b/arch/arm/boot/dts/imx7s.dtsi
@@ -58,7 +58,7 @@
          * Also for U-Boot there must be a pre-existing /memory node.
          */
         chosen {};
-        memory { device_type = "memory"; reg = <0 0>; };
+        memory { device_type = "memory"; };
 
         aliases {
                 gpio0 = &gpio1;
@@ -130,6 +130,12 @@
                 #phy-cells = <0>;
         };
 
+        pmu {
+                compatible = "arm,cortex-a7-pmu";
+                interrupt-parent = <&gpc>;
+                interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-affinity = <&cpu0>;
+        };
 
         replicator {
                 /*
@@ -499,6 +505,14 @@
                                 status = "disabled";
                         };
 
+                        kpp: kpp@30320000 {
+                                compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp";
+                                reg = <0x30320000 0x10000>;
+                                interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_KPP_ROOT_CLK>;
+                                status = "disabled";
+                        };
+
                         iomuxc: iomuxc@30330000 {
                                 compatible = "fsl,imx7d-iomuxc";
                                 reg = <0x30330000 0x10000>;
@@ -511,9 +525,29 @@
                         };
 
                         ocotp: ocotp-ctrl@30350000 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
                                 compatible = "fsl,imx7d-ocotp", "syscon";
                                 reg = <0x30350000 0x10000>;
                                 clocks = <&clks IMX7D_OCOTP_CLK>;
+
+                                tempmon_calib: calib@3c {
+                                        reg = <0x3c 0x4>;
+                                };
+
+                                tempmon_temp_grade: temp-grade@10 {
+                                        reg = <0x10 0x4>;
+                                };
+                        };
+
+                        tempmon: tempmon {
+                                compatible = "fsl,imx7d-tempmon";
+                                interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+                                fsl,tempmon =<&anatop>;
+                                nvmem-cells = <&tempmon_calib>,
+                                        <&tempmon_temp_grade>;
+                                nvmem-cell-names = "calib", "temp_grade";
+                                clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
                         };
 
                         anatop: anatop@30360000 {
@@ -551,6 +585,8 @@
                                         offset = <0x34>;
                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+                                        clocks = <&clks IMX7D_SNVS_CLK>;
+                                        clock-names = "snvs-rtc";
                                 };
 
                                 snvs_poweroff: snvs-poweroff {
@@ -708,118 +744,156 @@
                         reg = <0x30800000 0x400000>;
                         ranges;
 
-                        ecspi1: ecspi@30820000 {
+                        spba-bus@30800000 {
+                                compatible = "fsl,spba-bus", "simple-bus";
                                 #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
-                                reg = <0x30820000 0x10000>;
-                                interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
-                                        <&clks IMX7D_ECSPI1_ROOT_CLK>;
-                                clock-names = "ipg", "per";
-                                status = "disabled";
-                        };
+                                #size-cells = <1>;
+                                reg = <0x30800000 0x100000>;
+                                ranges;
 
-                        ecspi2: ecspi@30830000 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
-                                reg = <0x30830000 0x10000>;
-                                interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
-                                        <&clks IMX7D_ECSPI2_ROOT_CLK>;
-                                clock-names = "ipg", "per";
-                                status = "disabled";
-                        };
+                                ecspi1: ecspi@30820000 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
+                                        reg = <0x30820000 0x10000>;
+                                        interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+                                        clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
+                                                <&clks IMX7D_ECSPI1_ROOT_CLK>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
 
-                        ecspi3: ecspi@30840000 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
-                                reg = <0x30840000 0x10000>;
-                                interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
-                                        <&clks IMX7D_ECSPI3_ROOT_CLK>;
-                                clock-names = "ipg", "per";
-                                status = "disabled";
-                        };
+                                ecspi2: ecspi@30830000 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
+                                        reg = <0x30830000 0x10000>;
+                                        interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+                                        clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
+                                                <&clks IMX7D_ECSPI2_ROOT_CLK>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
 
-                        uart1: serial@30860000 {
-                                compatible = "fsl,imx7d-uart",
-                                             "fsl,imx6q-uart";
-                                reg = <0x30860000 0x10000>;
-                                interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_UART1_ROOT_CLK>,
-                                        <&clks IMX7D_UART1_ROOT_CLK>;
-                                clock-names = "ipg", "per";
-                                status = "disabled";
-                        };
+                                ecspi3: ecspi@30840000 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
+                                        reg = <0x30840000 0x10000>;
+                                        interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+                                        clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
+                                                <&clks IMX7D_ECSPI3_ROOT_CLK>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
 
-                        uart2: serial@30890000 {
-                                compatible = "fsl,imx7d-uart",
-                                             "fsl,imx6q-uart";
-                                reg = <0x30890000 0x10000>;
-                                interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_UART2_ROOT_CLK>,
-                                        <&clks IMX7D_UART2_ROOT_CLK>;
-                                clock-names = "ipg", "per";
-                                status = "disabled";
-                        };
+                                uart1: serial@30860000 {
+                                        compatible = "fsl,imx7d-uart",
+                                                     "fsl,imx6q-uart";
+                                        reg = <0x30860000 0x10000>;
+                                        interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+                                        clocks = <&clks IMX7D_UART1_ROOT_CLK>,
+                                                <&clks IMX7D_UART1_ROOT_CLK>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
 
-                        uart3: serial@30880000 {
-                                compatible = "fsl,imx7d-uart",
-                                             "fsl,imx6q-uart";
-                                reg = <0x30880000 0x10000>;
-                                interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_UART3_ROOT_CLK>,
-                                        <&clks IMX7D_UART3_ROOT_CLK>;
-                                clock-names = "ipg", "per";
-                                status = "disabled";
-                        };
+                                uart2: serial@30890000 {
+                                        compatible = "fsl,imx7d-uart",
+                                                     "fsl,imx6q-uart";
+                                        reg = <0x30890000 0x10000>;
+                                        interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+                                        clocks = <&clks IMX7D_UART2_ROOT_CLK>,
+                                                <&clks IMX7D_UART2_ROOT_CLK>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
 
-                        sai1: sai@308a0000 {
-                                #sound-dai-cells = <0>;
-                                compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
-                                reg = <0x308a0000 0x10000>;
-                                interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_SAI1_IPG_CLK>,
-                                         <&clks IMX7D_SAI1_ROOT_CLK>,
-                                         <&clks IMX7D_CLK_DUMMY>,
-                                         <&clks IMX7D_CLK_DUMMY>;
-                                clock-names = "bus", "mclk1", "mclk2", "mclk3";
-                                dma-names = "rx", "tx";
-                                dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
-                                status = "disabled";
-                        };
+                                uart3: serial@30880000 {
+                                        compatible = "fsl,imx7d-uart",
+                                                     "fsl,imx6q-uart";
+                                        reg = <0x30880000 0x10000>;
+                                        interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+                                        clocks = <&clks IMX7D_UART3_ROOT_CLK>,
+                                                <&clks IMX7D_UART3_ROOT_CLK>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
 
-                        sai2: sai@308b0000 {
-                                #sound-dai-cells = <0>;
-                                compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
-                                reg = <0x308b0000 0x10000>;
-                                interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_SAI2_IPG_CLK>,
-                                         <&clks IMX7D_SAI2_ROOT_CLK>,
-                                         <&clks IMX7D_CLK_DUMMY>,
-                                         <&clks IMX7D_CLK_DUMMY>;
-                                clock-names = "bus", "mclk1", "mclk2", "mclk3";
-                                dma-names = "rx", "tx";
-                                dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
-                                status = "disabled";
+                                sai1: sai@308a0000 {
+                                        #sound-dai-cells = <0>;
+                                        compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
+                                        reg = <0x308a0000 0x10000>;
+                                        interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+                                        clocks = <&clks IMX7D_SAI1_IPG_CLK>,
+                                                 <&clks IMX7D_SAI1_ROOT_CLK>,
+                                                 <&clks IMX7D_CLK_DUMMY>,
+                                                 <&clks IMX7D_CLK_DUMMY>;
+                                        clock-names = "bus", "mclk1", "mclk2", "mclk3";
+                                        dma-names = "rx", "tx";
+                                        dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
+                                        status = "disabled";
+                                };
+
+                                sai2: sai@308b0000 {
+                                        #sound-dai-cells = <0>;
+                                        compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
+                                        reg = <0x308b0000 0x10000>;
+                                        interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+                                        clocks = <&clks IMX7D_SAI2_IPG_CLK>,
+                                                 <&clks IMX7D_SAI2_ROOT_CLK>,
+                                                 <&clks IMX7D_CLK_DUMMY>,
+                                                 <&clks IMX7D_CLK_DUMMY>;
+                                        clock-names = "bus", "mclk1", "mclk2", "mclk3";
+                                        dma-names = "rx", "tx";
+                                        dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
+                                        status = "disabled";
+                                };
+
+                                sai3: sai@308c0000 {
+                                        #sound-dai-cells = <0>;
+                                        compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
+                                        reg = <0x308c0000 0x10000>;
+                                        interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+                                        clocks = <&clks IMX7D_SAI3_IPG_CLK>,
+                                                 <&clks IMX7D_SAI3_ROOT_CLK>,
+                                                 <&clks IMX7D_CLK_DUMMY>,
+                                                 <&clks IMX7D_CLK_DUMMY>;
+                                        clock-names = "bus", "mclk1", "mclk2", "mclk3";
+                                        dma-names = "rx", "tx";
+                                        dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
+                                        status = "disabled";
+                                };
                         };
 
-                        sai3: sai@308c0000 {
-                                #sound-dai-cells = <0>;
-                                compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
-                                reg = <0x308c0000 0x10000>;
-                                interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_SAI3_IPG_CLK>,
-                                         <&clks IMX7D_SAI3_ROOT_CLK>,
-                                         <&clks IMX7D_CLK_DUMMY>,
-                                         <&clks IMX7D_CLK_DUMMY>;
-                                clock-names = "bus", "mclk1", "mclk2", "mclk3";
-                                dma-names = "rx", "tx";
-                                dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
-                                status = "disabled";
+                        crypto: caam@30900000 {
+                                compatible = "fsl,sec-v4.0";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <0x30900000 0x40000>;
+                                ranges = <0 0x30900000 0x40000>;
+                                interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_CAAM_CLK>,
+                                         <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
+                                clock-names = "ipg", "aclk";
+
+                                sec_jr0: jr0@1000 {
+                                        compatible = "fsl,sec-v4.0-job-ring";
+                                        reg = <0x1000 0x1000>;
+                                        interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+                                };
+
+                                sec_jr1: jr1@2000 {
+                                        compatible = "fsl,sec-v4.0-job-ring";
+                                        reg = <0x2000 0x1000>;
+                                        interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+                                };
+
+                                sec_jr2: jr1@3000 {
+                                        compatible = "fsl,sec-v4.0-job-ring";
+                                        reg = <0x3000 0x1000>;
+                                        interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+                                };
                         };
 
                         flexcan1: can@30a00000 {
diff --git a/arch/arm/boot/dts/keystone-k2e-clocks.dtsi b/arch/arm/boot/dts/keystone-k2e-clocks.dtsi
index 5e0e7d232161..f7592155a740 100644
--- a/arch/arm/boot/dts/keystone-k2e-clocks.dtsi
+++ b/arch/arm/boot/dts/keystone-k2e-clocks.dtsi
@@ -42,7 +42,7 @@ clocks {
                 domain-id = <0>;
         };
 
-        clkhyperlink0: clkhyperlink02350030 {
+        clkhyperlink0: clkhyperlink0@2350030 {
                 #clock-cells = <0>;
                 compatible = "ti,keystone,psc-clock";
                 clocks = <&chipclk12>;
diff --git a/arch/arm/boot/dts/keystone-k2e.dtsi b/arch/arm/boot/dts/keystone-k2e.dtsi
index 0bcd3f8a9c45..085e7326ea8e 100644
--- a/arch/arm/boot/dts/keystone-k2e.dtsi
+++ b/arch/arm/boot/dts/keystone-k2e.dtsi
@@ -109,11 +109,14 @@
                         };
                 };
 
-                dspgpio0: keystone_dsp_gpio@2620240 {
-                        compatible = "ti,keystone-dsp-gpio";
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                        gpio,syscon-dev = <&devctrl 0x240>;
+                devctrl: device-state-control@2620000 {
+                        dspgpio0: keystone_dsp_gpio@240 {
+                                compatible = "ti,keystone-dsp-gpio";
+                                reg = <0x240 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                gpio,syscon-dev = <&devctrl 0x240>;
+                        };
                 };
 
                 dsp0: dsp@10800000 {
diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi
index fd061718dc0a..da78c0034427 100644
--- a/arch/arm/boot/dts/keystone-k2g.dtsi
+++ b/arch/arm/boot/dts/keystone-k2g.dtsi
@@ -69,6 +69,24 @@
                 interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
         };
 
+        usbphy {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "simple-bus";
+
+                usb0_phy: usb-phy@0 {
+                        compatible = "usb-nop-xceiv";
+                        reg = <0>;
+                        status = "disabled";
+                };
+
+                usb1_phy: usb-phy@1 {
+                        compatible = "usb-nop-xceiv";
+                        reg = <1>;
+                        status = "disabled";
+                };
+        };
+
         soc0: soc@0 {
                 #address-cells = <1>;
                 #size-cells = <1>;
@@ -97,8 +115,28 @@
                 };
 
                 devctrl: device-state-control@2620000 {
-                        compatible = "ti,keystone-devctrl", "syscon";
+                        compatible = "ti,keystone-devctrl", "syscon", "simple-mfd";
                         reg = <0x02620000 0x1000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x0 0x02620000 0x1000>;
+
+                        kirq0: keystone_irq@2a0 {
+                                compatible = "ti,keystone-irq";
+                                reg = <0x2a0 0x10>;
+                                interrupts = <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                ti,syscon-dev = <&devctrl 0x2a0>;
+                        };
+
+                        dspgpio0: keystone_dsp_gpio@240 {
+                                compatible = "ti,keystone-dsp-gpio";
+                                reg = <0x240 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                gpio,syscon-dev = <&devctrl 0x240>;
+                        };
                 };
 
                 uart0: serial@2530c00 {
@@ -113,7 +151,7 @@
                         status = "disabled";
                 };
 
-                uart1: serial@02531000 {
+                uart1: serial@2531000 {
                         compatible = "ti,da830-uart", "ns16550a";
                         current-speed = <115200>;
                         reg-shift = <2>;
@@ -125,7 +163,7 @@
                         status = "disabled";
                 };
 
-                uart2: serial@02531400 {
+                uart2: serial@2531400 {
                         compatible = "ti,da830-uart", "ns16550a";
                         current-speed = <115200>;
                         reg-shift = <2>;
@@ -188,21 +226,6 @@
                         status = "disabled";
                 };
 
-                kirq0: keystone_irq@26202a0 {
-                        compatible = "ti,keystone-irq";
-                        interrupts = <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>;
-                        interrupt-controller;
-                        #interrupt-cells = <1>;
-                        ti,syscon-dev = <&devctrl 0x2a0>;
-                };
-
-                dspgpio0: keystone_dsp_gpio@2620240 {
-                        compatible = "ti,keystone-dsp-gpio";
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                        gpio,syscon-dev = <&devctrl 0x240>;
-                };
-
                 dsp0: dsp@10800000 {
                         compatible = "ti,k2g-dsp";
                         reg = <0x10800000 0x00100000>,
@@ -460,11 +483,6 @@
                         status = "disabled";
                 };
 
-                usb0_phy: usb-phy@0 {
-                        compatible = "usb-nop-xceiv";
-                        status = "disabled";
-                };
-
                 keystone_usb0: keystone-dwc3@2680000 {
                         compatible = "ti,keystone-dwc3";
                         #address-cells = <1>;
@@ -488,11 +506,6 @@
                         };
                 };
 
-                usb1_phy: usb-phy@1 {
-                        compatible = "usb-nop-xceiv";
-                        status = "disabled";
-                };
-
                 keystone_usb1: keystone-dwc3@2580000 {
                         compatible = "ti,keystone-dwc3";
                         #address-cells = <1>;
@@ -583,5 +596,18 @@
                         power-domains = <&k2g_pds 0x0013>;
                         clocks = <&k2g_clks 0x0013 0>;
                 };
+
+                wdt: wdt@02250000 {
+                        compatible = "ti,keystone-wdt", "ti,davinci-wdt";
+                        reg = <0x02250000 0x80>;
+                        power-domains = <&k2g_pds 0x22>;
+                        clocks = <&k2g_clks 0x22 0>;
+                };
+
+                emif: emif@21010000 {
+                        compatible = "ti,emif-keystone";
+                        reg = <0x21010000 0x200>;
+                        interrupts = <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/keystone-k2hk.dtsi b/arch/arm/boot/dts/keystone-k2hk.dtsi
index ed59474522cb..ca0f198ba627 100644
--- a/arch/arm/boot/dts/keystone-k2hk.dtsi
+++ b/arch/arm/boot/dts/keystone-k2hk.dtsi
@@ -87,60 +87,70 @@
                         };
                 };
 
-                dspgpio0: keystone_dsp_gpio@2620240 {
-                        compatible = "ti,keystone-dsp-gpio";
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                        gpio,syscon-dev = <&devctrl 0x240>;
-                };
+                devctrl: device-state-control@2620000 {
+                        dspgpio0: keystone_dsp_gpio@240 {
+                                compatible = "ti,keystone-dsp-gpio";
+                                reg = <0x240 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                gpio,syscon-dev = <&devctrl 0x240>;
+                        };
 
-                dspgpio1: keystone_dsp_gpio@2620244 {
-                        compatible = "ti,keystone-dsp-gpio";
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                        gpio,syscon-dev = <&devctrl 0x244>;
-                };
+                        dspgpio1: keystone_dsp_gpio@244 {
+                                compatible = "ti,keystone-dsp-gpio";
+                                reg = <0x244 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                gpio,syscon-dev = <&devctrl 0x244>;
+                        };
 
-                dspgpio2: keystone_dsp_gpio@2620248 {
-                        compatible = "ti,keystone-dsp-gpio";
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                        gpio,syscon-dev = <&devctrl 0x248>;
-                };
+                        dspgpio2: keystone_dsp_gpio@248 {
+                                compatible = "ti,keystone-dsp-gpio";
+                                reg = <0x248 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                gpio,syscon-dev = <&devctrl 0x248>;
+                        };
 
-                dspgpio3: keystone_dsp_gpio@262024c {
-                        compatible = "ti,keystone-dsp-gpio";
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                        gpio,syscon-dev = <&devctrl 0x24c>;
-                };
+                        dspgpio3: keystone_dsp_gpio@24c {
+                                compatible = "ti,keystone-dsp-gpio";
+                                reg = <0x24c 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                gpio,syscon-dev = <&devctrl 0x24c>;
+                        };
 
-                dspgpio4: keystone_dsp_gpio@2620250 {
-                        compatible = "ti,keystone-dsp-gpio";
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                        gpio,syscon-dev = <&devctrl 0x250>;
-                };
+                        dspgpio4: keystone_dsp_gpio@250 {
+                                compatible = "ti,keystone-dsp-gpio";
+                                reg = <0x250 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                gpio,syscon-dev = <&devctrl 0x250>;
+                        };
 
-                dspgpio5: keystone_dsp_gpio@2620254 {
-                        compatible = "ti,keystone-dsp-gpio";
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                        gpio,syscon-dev = <&devctrl 0x254>;
-                };
+                        dspgpio5: keystone_dsp_gpio@254 {
+                                compatible = "ti,keystone-dsp-gpio";
+                                reg = <0x254 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                gpio,syscon-dev = <&devctrl 0x254>;
+                        };
 
-                dspgpio6: keystone_dsp_gpio@2620258 {
-                        compatible = "ti,keystone-dsp-gpio";
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                        gpio,syscon-dev = <&devctrl 0x258>;
-                };
+                        dspgpio6: keystone_dsp_gpio@258 {
+                                compatible = "ti,keystone-dsp-gpio";
+                                reg = <0x258 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                gpio,syscon-dev = <&devctrl 0x258>;
+                        };
 
-                dspgpio7: keystone_dsp_gpio@262025c {
-                        compatible = "ti,keystone-dsp-gpio";
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                        gpio,syscon-dev = <&devctrl 0x25c>;
+                        dspgpio7: keystone_dsp_gpio@25c {
+                                compatible = "ti,keystone-dsp-gpio";
+                                reg = <0x25c 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                gpio,syscon-dev = <&devctrl 0x25c>;
+                        };
                 };
 
                 dsp0: dsp@10800000 {
diff --git a/arch/arm/boot/dts/keystone-k2l.dtsi b/arch/arm/boot/dts/keystone-k2l.dtsi
index b61a830f4a4d..374c80124c4e 100644
--- a/arch/arm/boot/dts/keystone-k2l.dtsi
+++ b/arch/arm/boot/dts/keystone-k2l.dtsi
@@ -289,32 +289,38 @@
                         clocks = <&clkosr>;
                 };
 
-                dspgpio0: keystone_dsp_gpio@2620240 {
-                        compatible = "ti,keystone-dsp-gpio";
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                        gpio,syscon-dev = <&devctrl 0x240>;
-                };
+                devctrl: device-state-control@2620000 {
+                        dspgpio0: keystone_dsp_gpio@240 {
+                                compatible = "ti,keystone-dsp-gpio";
+                                reg = <0x240 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                gpio,syscon-dev = <&devctrl 0x240>;
+                        };
 
-                dspgpio1: keystone_dsp_gpio@2620244 {
-                        compatible = "ti,keystone-dsp-gpio";
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                        gpio,syscon-dev = <&devctrl 0x244>;
-                };
+                        dspgpio1: keystone_dsp_gpio@244 {
+                                compatible = "ti,keystone-dsp-gpio";
+                                reg = <0x244 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                gpio,syscon-dev = <&devctrl 0x244>;
+                        };
 
-                dspgpio2: keystone_dsp_gpio@2620248 {
-                        compatible = "ti,keystone-dsp-gpio";
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                        gpio,syscon-dev = <&devctrl 0x248>;
-                };
+                        dspgpio2: keystone_dsp_gpio@248 {
+                                compatible = "ti,keystone-dsp-gpio";
+                                reg = <0x248 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                gpio,syscon-dev = <&devctrl 0x248>;
+                        };
 
-                dspgpio3: keystone_dsp_gpio@262024c {
-                        compatible = "ti,keystone-dsp-gpio";
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                        gpio,syscon-dev = <&devctrl 0x24c>;
+                        dspgpio3: keystone_dsp_gpio@24c {
+                                compatible = "ti,keystone-dsp-gpio";
+                                reg = <0x24c 0x4>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                gpio,syscon-dev = <&devctrl 0x24c>;
+                        };
                 };
 
                 dsp0: dsp@10800000 {
diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi
index 93ea5c69ea77..c298675a29a5 100644
--- a/arch/arm/boot/dts/keystone.dtsi
+++ b/arch/arm/boot/dts/keystone.dtsi
@@ -87,15 +87,28 @@
                 };
 
                 devctrl: device-state-control@2620000 {
-                        compatible = "ti,keystone-devctrl", "syscon";
+                        compatible = "ti,keystone-devctrl", "syscon", "simple-mfd";
                         reg = <0x02620000 0x1000>;
-                };
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x0 0x02620000 0x1000>;
+
+                        kirq0: keystone_irq@2a0 {
+                                compatible = "ti,keystone-irq";
+                                reg = <0x2a0 0x4>;
+                                interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                ti,syscon-dev = <&devctrl 0x2a0>;
+                        };
 
-                rstctrl: reset-controller {
-                        compatible = "ti,keystone-reset";
-                        ti,syscon-pll = <&pllctrl 0xe4>;
-                        ti,syscon-dev = <&devctrl 0x328>;
-                        ti,wdt-list = <0>;
+                        rstctrl: reset-controller@328 {
+                                compatible = "ti,keystone-reset";
+                                reg = <0x328 0x10>;
+                                ti,syscon-pll = <&pllctrl 0xe4>;
+                                ti,syscon-dev = <&devctrl 0x328>;
+                                ti,wdt-list = <0>;
+                        };
                 };
 
                 /include/ "keystone-clocks.dtsi"
@@ -282,14 +295,6 @@
                                   1 0 0x21000A00 0x00000100>;
                 };
 
-                kirq0: keystone_irq@26202a0 {
-                        compatible = "ti,keystone-irq";
-                        interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
-                        interrupt-controller;
-                        #interrupt-cells = <1>;
-                        ti,syscon-dev = <&devctrl 0x2a0>;
-                };
-
                 pcie0: pcie@21800000 {
                         compatible = "ti,keystone-pcie", "snps,dw-pcie";
                         clocks = <&clkpcie>;
@@ -338,5 +343,12 @@
                                         <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
                         };
                 };
+
+                emif: emif@21010000 {
+                        compatible = "ti,emif-keystone";
+                        reg = <0x21010000 0x200>;
+                        interrupts = <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>;
+                        interrupt-parent = <&gic>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/logicpd-som-lv.dtsi b/arch/arm/boot/dts/logicpd-som-lv.dtsi
index c1aa7a4518fb..b47cac23a04b 100644
--- a/arch/arm/boot/dts/logicpd-som-lv.dtsi
+++ b/arch/arm/boot/dts/logicpd-som-lv.dtsi
@@ -71,6 +71,8 @@
 };
 
 &i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c1_pins>;
         clock-frequency = <2600000>;
 
         twl: twl@48 {
@@ -86,10 +88,14 @@
 };
 
 &i2c2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c2_pins>;
         clock-frequency = <400000>;
 };
 
 &i2c3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c3_pins>;
         clock-frequency = <400000>;
 };
 
@@ -189,7 +195,12 @@
                 >;
         };
 
-
+        i2c1_pins: pinmux_i2c1_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0)        /* i2c1_scl.i2c1_scl */
+                        OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0)        /* i2c1_sda.i2c1_sda */
+                >;
+        };
 };
 
 &omap3_pmx_wkup {
@@ -206,6 +217,18 @@
                         OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4)        /* sys_boot1.gpio_3 */
                 >;
         };
+        i2c2_pins: pinmux_i2c2_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0)        /* i2c2_scl */
+                        OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0)        /* i2c2_sda */
+                >;
+        };
+        i2c3_pins: pinmux_i2c3_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0)        /* i2c3_scl */
+                        OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0)        /* i2c3_sda */
+                >;
+        };
 };
 
 &omap3_pmx_core2 {
diff --git a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi
index b50b796e15c7..3e174e474d3d 100644
--- a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi
+++ b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi
@@ -66,6 +66,8 @@
 };
 
 &i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c1_pins>;
         clock-frequency = <2600000>;
 
         twl: twl@48 {
@@ -81,10 +83,14 @@
 };
 
 &i2c2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c2_pins>;
         clock-frequency = <400000>;
 };
 
 &i2c3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c3_pins>;
         clock-frequency = <400000>;
         at24@50 {
                 compatible = "atmel,24c64";
@@ -136,6 +142,24 @@
                         OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0)        /* hsusb0_data7.hsusb0_data7 */
                 >;
         };
+        i2c1_pins: pinmux_i2c1_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0)        /* i2c1_scl.i2c1_scl */
+                        OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0)        /* i2c1_sda.i2c1_sda */
+                >;
+        };
+        i2c2_pins: pinmux_i2c2_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0)        /* i2c2_scl */
+                        OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0)        /* i2c2_sda */
+                >;
+        };
+        i2c3_pins: pinmux_i2c3_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0)        /* i2c3_scl */
+                        OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0)        /* i2c3_sda */
+                >;
+        };
 };
 
 &uart2 {
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index c31dad98f989..fbd2897566c3 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -788,5 +788,21 @@
                         clock-names = "ipg", "per";
                         big-endian;
                 };
+
+                ocram1: sram@10000000 {
+                        compatible = "mmio-sram";
+                        reg = <0x0 0x10000000 0x0 0x10000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x0 0x0 0x10000000 0x10000>;
+                };
+
+                ocram2: sram@10010000 {
+                        compatible = "mmio-sram";
+                        reg = <0x0 0x10010000 0x0 0x10000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x0 0x0 0x10010000 0x10000>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index d2e3eeaa1a5f..dcc9292d2ffa 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -46,6 +46,7 @@
 #include <dt-bindings/clock/meson8b-clkc.h>
 #include <dt-bindings/gpio/meson8-gpio.h>
 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
+#include <dt-bindings/reset/amlogic,meson8b-reset.h>
 #include "meson.dtsi"
 
 / {
@@ -187,6 +188,12 @@
                 reg = <0x8000 0x4>, <0x4000 0x460>;
         };
 
+        reset: reset-controller@4404 {
+                compatible = "amlogic,meson8b-reset";
+                reg = <0x4404 0x9c>;
+                #reset-cells = <1>;
+        };
+
         analog_top: analog-top@81a8 {
                 compatible = "amlogic,meson8-analog-top", "syscon";
                 reg = <0x81a8 0x14>;
@@ -383,10 +390,12 @@
         compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
         clock-names = "usb_general", "usb";
+        resets = <&reset RESET_USB_OTG>;
 };
 
 &usb1_phy {
         compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
         clock-names = "usb_general", "usb";
+        resets = <&reset RESET_USB_OTG>;
 };
diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts
index 9ff6ca4e20d0..3a5603d95b70 100644
--- a/arch/arm/boot/dts/meson8b-odroidc1.dts
+++ b/arch/arm/boot/dts/meson8b-odroidc1.dts
@@ -54,6 +54,7 @@
 
         aliases {
                 serial0 = &uart_AO;
+                mmc0 = &sd_card_slot;
         };
 
         memory {
@@ -69,6 +70,37 @@
                         default-state = "off";
                 };
         };
+
+        tflash_vdd: regulator-tflash_vdd {
+                /*
+                 * signal name from schematics: TFLASH_VDD_EN
+                 */
+                compatible = "regulator-fixed";
+
+                regulator-name = "TFLASH_VDD";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+
+                gpio = <&gpio GPIOY_12 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+        };
+
+        tf_io: gpio-regulator-tf_io {
+                compatible = "regulator-gpio";
+
+                regulator-name = "TF_IO";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <3300000>;
+
+                /*
+                 * signal name from schematics: TF_3V3N_1V8_EN
+                 */
+                gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
+                gpios-states = <0>;
+
+                states = <3300000 0
+                          1800000 1>;
+        };
 };
 
 &uart_AO {
@@ -99,3 +131,59 @@
 &usb1 {
         status = "okay";
 };
+
+&sdio {
+        status = "okay";
+
+        pinctrl-0 = <&sd_b_pins>;
+        pinctrl-names = "default";
+
+        /* SD card */
+        sd_card_slot: slot@1 {
+                compatible = "mmc-slot";
+                reg = <1>;
+                status = "okay";
+
+                bus-width = <4>;
+                no-sdio;
+                cap-mmc-highspeed;
+                cap-sd-highspeed;
+                disable-wp;
+
+                cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
+                cd-inverted;
+
+                vmmc-supply = <&tflash_vdd>;
+                vqmmc-supply = <&tf_io>;
+        };
+};
+
+&ethmac {
+        status = "okay";
+
+        snps,reset-gpio = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH>;
+        snps,reset-active-low;
+        snps,reset-delays-us = <0 10000 30000>;
+
+        pinctrl-0 = <&eth_rgmii_pins>;
+        pinctrl-names = "default";
+
+        phy-mode = "rgmii";
+        phy-handle = <&eth_phy>;
+        amlogic,tx-delay-ns = <4>;
+
+        mdio {
+                compatible = "snps,dwmac-mdio";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                /* Realtek RTL8211F (0x001cc916) */
+                eth_phy: ethernet-phy@0 {
+                        reg = <0>;
+                        eee-broken-1000t;
+                        interrupt-parent = <&gpio_intc>;
+                        /* GPIOH_3 */
+                        interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 7cd03ed3742e..553b82174604 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -152,7 +152,7 @@
 
         reset: reset-controller@4404 {
                 compatible = "amlogic,meson8b-reset";
-                reg = <0x4404 0x20>;
+                reg = <0x4404 0x9c>;
                 #reset-cells = <1>;
         };
 
@@ -183,7 +183,36 @@
                         reg-names = "mux", "pull", "pull-enable", "gpio";
                         gpio-controller;
                         #gpio-cells = <2>;
-                        gpio-ranges = <&pinctrl_cbus 0 0 130>;
+                        gpio-ranges = <&pinctrl_cbus 0 0 83>;
+                };
+
+                eth_rgmii_pins: eth-rgmii {
+                        mux {
+                                groups = "eth_tx_clk",
+                                         "eth_tx_en",
+                                         "eth_txd1_0",
+                                         "eth_txd1_1",
+                                         "eth_txd0_0",
+                                         "eth_txd0_1",
+                                         "eth_rx_clk",
+                                         "eth_rx_dv",
+                                         "eth_rxd1",
+                                         "eth_rxd0",
+                                         "eth_mdio_en",
+                                         "eth_mdc",
+                                         "eth_ref_clk",
+                                         "eth_txd2",
+                                         "eth_txd3";
+                                function = "ethernet";
+                        };
+                };
+
+                sd_b_pins: sd-b {
+                        mux {
+                                groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
+                                        "sd_d3_b", "sd_clk_b", "sd_cmd_b";
+                                function = "sd_b";
+                        };
                 };
         };
 };
@@ -203,8 +232,18 @@
 };
 
 &ethmac {
-        clocks = <&clkc CLKID_ETH>;
-        clock-names = "stmmaceth";
+        compatible = "amlogic,meson8b-dwmac", "snps,dwmac-3.70a", "snps,dwmac";
+
+        reg = <0xc9410000 0x10000
+               0xc1108140 0x4>;
+
+        clocks = <&clkc CLKID_ETH>,
+                 <&clkc CLKID_MPLL2>,
+                 <&clkc CLKID_MPLL2>;
+        clock-names = "stmmaceth", "clkin0", "clkin1";
+
+        resets = <&reset RESET_ETHERNET>;
+        reset-names = "stmmaceth";
 };
 
 &gpio_intc {
@@ -219,6 +258,18 @@
         clock-names = "core";
 };
 
+&i2c_AO {
+        clocks = <&clkc CLKID_CLK81>;
+};
+
+&i2c_A {
+        clocks = <&clkc CLKID_I2C>;
+};
+
+&i2c_B {
+        clocks = <&clkc CLKID_I2C>;
+};
+
 &L2 {
         arm,data-latency = <3 3 3>;
         arm,tag-latency = <2 2 2>;
diff --git a/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi b/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi
index 4d61e5b1334a..ddc7a7bb33c0 100644
--- a/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi
+++ b/arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi
@@ -68,6 +68,19 @@
                         };
                 };
 
+                cpcap_audio: audio-codec {
+                        #sound-dai-cells = <1>;
+
+                        port@0 {
+                                cpcap_audio_codec0: endpoint {
+                                };
+                        };
+                        port@1 {
+                                cpcap_audio_codec1: endpoint {
+                                };
+                        };
+                };
+
                 cpcap_rtc: rtc {
                         compatible = "motorola,cpcap-rtc";
 
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
index b750da5362f7..ead9e1c1184a 100644
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -28,7 +28,7 @@
         compatible = "mediatek,mt7623";
         interrupt-parent = <&sysirq>;
 
-        cpu_opp_table: opp_table {
+        cpu_opp_table: opp-table {
                 compatible = "operating-points-v2";
                 opp-shared;
 
@@ -96,6 +96,9 @@
                         device_type = "cpu";
                         compatible = "arm,cortex-a7";
                         reg = <0x1>;
+                        clocks = <&infracfg CLK_INFRA_CPUSEL>,
+                                 <&apmixedsys CLK_APMIXED_MAINPLL>;
+                        clock-names = "cpu", "intermediate";
                         operating-points-v2 = <&cpu_opp_table>;
                         clock-frequency = <1300000000>;
                 };
@@ -104,6 +107,9 @@
                         device_type = "cpu";
                         compatible = "arm,cortex-a7";
                         reg = <0x2>;
+                        clocks = <&infracfg CLK_INFRA_CPUSEL>,
+                                 <&apmixedsys CLK_APMIXED_MAINPLL>;
+                        clock-names = "cpu", "intermediate";
                         operating-points-v2 = <&cpu_opp_table>;
                         clock-frequency = <1300000000>;
                 };
@@ -112,6 +118,9 @@
                         device_type = "cpu";
                         compatible = "arm,cortex-a7";
                         reg = <0x3>;
+                        clocks = <&infracfg CLK_INFRA_CPUSEL>,
+                                 <&apmixedsys CLK_APMIXED_MAINPLL>;
+                        clock-names = "cpu", "intermediate";
                         operating-points-v2 = <&cpu_opp_table>;
                         clock-frequency = <1300000000>;
                 };
@@ -138,32 +147,32 @@
         };
 
         thermal-zones {
-                        cpu_thermal: cpu_thermal {
+                        cpu_thermal: cpu-thermal {
                                 polling-delay-passive = <1000>;
                                 polling-delay = <1000>;
 
                                 thermal-sensors = <&thermal 0>;
 
                                 trips {
-                                        cpu_passive: cpu_passive {
+                                        cpu_passive: cpu-passive {
                                                 temperature = <47000>;
                                                 hysteresis = <2000>;
                                                 type = "passive";
                                         };
 
-                                        cpu_active: cpu_active {
+                                        cpu_active: cpu-active {
                                                 temperature = <67000>;
                                                 hysteresis = <2000>;
                                                 type = "active";
                                         };
 
-                                        cpu_hot: cpu_hot {
+                                        cpu_hot: cpu-hot {
                                                 temperature = <87000>;
                                                 hysteresis = <2000>;
                                                 type = "hot";
                                         };
 
-                                        cpu_crit {
+                                        cpu-crit {
                                                 temperature = <107000>;
                                                 hysteresis = <2000>;
                                                 type = "critical";
@@ -670,6 +679,111 @@
                 #reset-cells = <1>;
         };
 
+        pcie: pcie@1a140000 {
+                compatible = "mediatek,mt7623-pcie";
+                device_type = "pci";
+                reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
+                      <0 0x1a142000 0 0x1000>, /* Port0 registers */
+                      <0 0x1a143000 0 0x1000>, /* Port1 registers */
+                      <0 0x1a144000 0 0x1000>; /* Port2 registers */
+                reg-names = "subsys", "port0", "port1", "port2";
+                #address-cells = <3>;
+                #size-cells = <2>;
+                #interrupt-cells = <1>;
+                interrupt-map-mask = <0xf800 0 0 0>;
+                interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
+                                <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
+                                <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
+                clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
+                         <&hifsys CLK_HIFSYS_PCIE0>,
+                         <&hifsys CLK_HIFSYS_PCIE1>,
+                         <&hifsys CLK_HIFSYS_PCIE2>;
+                clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
+                resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
+                         <&hifsys MT2701_HIFSYS_PCIE1_RST>,
+                         <&hifsys MT2701_HIFSYS_PCIE2_RST>;
+                reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
+                phys = <&pcie0_port PHY_TYPE_PCIE>,
+                       <&pcie1_port PHY_TYPE_PCIE>,
+                       <&u3port1 PHY_TYPE_PCIE>;
+                phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
+                power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
+                bus-range = <0x00 0xff>;
+                status = "disabled";
+                ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000
+                          0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>;
+
+                pcie@0,0 {
+                        reg = <0x0000 0 0 0 0>;
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        #interrupt-cells = <1>;
+                        interrupt-map-mask = <0 0 0 0>;
+                        interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
+                        ranges;
+                        num-lanes = <1>;
+                        status = "disabled";
+                };
+
+                pcie@1,0 {
+                        reg = <0x0800 0 0 0 0>;
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        #interrupt-cells = <1>;
+                        interrupt-map-mask = <0 0 0 0>;
+                        interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
+                        ranges;
+                        num-lanes = <1>;
+                        status = "disabled";
+                };
+
+                pcie@2,0 {
+                        reg = <0x1000 0 0 0 0>;
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        #interrupt-cells = <1>;
+                        interrupt-map-mask = <0 0 0 0>;
+                        interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
+                        ranges;
+                        num-lanes = <1>;
+                        status = "disabled";
+                };
+        };
+
+        pcie0_phy: pcie-phy@1a149000 {
+                compatible = "mediatek,generic-tphy-v1";
+                reg = <0 0x1a149000 0 0x0700>;
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
+                status = "disabled";
+
+                pcie0_port: pcie-phy@1a149900 {
+                        reg = <0 0x1a149900 0 0x0700>;
+                        clocks = <&clk26m>;
+                        clock-names = "ref";
+                        #phy-cells = <1>;
+                        status = "okay";
+                };
+        };
+
+        pcie1_phy: pcie-phy@1a14a000 {
+                compatible = "mediatek,generic-tphy-v1";
+                reg = <0 0x1a14a000 0 0x0700>;
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
+                status = "disabled";
+
+                pcie1_port: pcie-phy@1a14a900 {
+                        reg = <0 0x1a14a900 0 0x0700>;
+                        clocks = <&clk26m>;
+                        clock-names = "ref";
+                        #phy-cells = <1>;
+                        status = "okay";
+                };
+        };
+
         usb1: usb@1a1c0000 {
                 compatible = "mediatek,mt7623-xhci",
                              "mediatek,mt8173-xhci";
diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
index 7bf5aa2237c9..bbf56f855e46 100644
--- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
@@ -39,7 +39,34 @@
                 };
         };
 
-        gpio_keys {
+        reg_1p8v: regulator-1p8v {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-1.8V";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                regulator-boot-on;
+                regulator-always-on;
+        };
+
+        reg_3p3v: regulator-3p3v {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-3.3V";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-boot-on;
+                regulator-always-on;
+        };
+
+        reg_5v: regulator-5v {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-5V";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-boot-on;
+                regulator-always-on;
+        };
+
+        gpio-keys {
                 compatible = "gpio-keys";
                 pinctrl-names = "default";
                 pinctrl-0 = <&key_pins_a>;
@@ -120,7 +147,6 @@
                         #address-cells = <1>;
                         #size-cells = <0>;
                         reg = <0>;
-                        pinctrl-names = "default";
                         reset-gpios = <&pio 33 0>;
                         core-supply = <&mt6323_vpa_reg>;
                         io-supply = <&mt6323_vemc3v3_reg>;
@@ -191,8 +217,8 @@
         bus-width = <8>;
         max-frequency = <50000000>;
         cap-mmc-highspeed;
-        vmmc-supply = <&mt6323_vemc3v3_reg>;
-        vqmmc-supply = <&mt6323_vio18_reg>;
+        vmmc-supply = <&reg_3p3v>;
+        vqmmc-supply = <&reg_1p8v>;
         non-removable;
 };
 
@@ -205,20 +231,42 @@
         max-frequency = <50000000>;
         cap-sd-highspeed;
         cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>;
-        vmmc-supply = <&mt6323_vmch_reg>;
-        vqmmc-supply = <&mt6323_vio18_reg>;
+        vmmc-supply = <&reg_3p3v>;
+        vqmmc-supply = <&reg_3p3v>;
+};
+
+&pcie {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pcie_default>;
+        status = "okay";
+
+        pcie@0,0 {
+                status = "okay";
+        };
+
+        pcie@1,0 {
+                status = "okay";
+        };
+};
+
+&pcie0_phy {
+        status = "okay";
+};
+
+&pcie1_phy {
+        status = "okay";
 };
 
 &pio {
         cir_pins_a:cir@0 {
-                pins_cir {
+                pins-cir {
                         pinmux = <MT7623_PIN_46_IR_FUNC_IR>;
                         bias-disable;
                 };
         };
 
         i2c0_pins_a: i2c@0 {
-                pins_i2c0 {
+                pins-i2c0 {
                         pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>,
                                  <MT7623_PIN_76_SCL0_FUNC_SCL0>;
                         bias-disable;
@@ -226,7 +274,7 @@
         };
 
         i2c1_pins_a: i2c@1 {
-                pin_i2c1 {
+                pin-i2c1 {
                         pinmux = <MT7623_PIN_57_SDA1_FUNC_SDA1>,
                                  <MT7623_PIN_58_SCL1_FUNC_SCL1>;
                         bias-disable;
@@ -234,7 +282,7 @@
         };
 
         i2s0_pins_a: i2s@0 {
-                pin_i2s0 {
+                pin-i2s0 {
                         pinmux = <MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA>,
                                  <MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN>,
                                  <MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK>,
@@ -246,7 +294,7 @@
         };
 
         i2s1_pins_a: i2s@1 {
-                pin_i2s1 {
+                pin-i2s1 {
                         pinmux = <MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA>,
                                  <MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN>,
                                  <MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK>,
@@ -258,7 +306,7 @@
         };
 
         key_pins_a: keys@0 {
-                pins_keys {
+                pins-keys {
                         pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>,
                                  <MT7623_PIN_257_GPIO257_FUNC_GPIO257> ;
                         input-enable;
@@ -266,7 +314,7 @@
         };
 
         led_pins_a: leds@0 {
-                pins_leds {
+                pins-leds {
                         pinmux = <MT7623_PIN_239_EXT_SDIO0_FUNC_GPIO239>,
                                  <MT7623_PIN_240_EXT_XCS_FUNC_GPIO240>,
                                  <MT7623_PIN_241_EXT_SCK_FUNC_GPIO241>;
@@ -274,7 +322,7 @@
         };
 
         mmc0_pins_default: mmc0default {
-                pins_cmd_dat {
+                pins-cmd-dat {
                         pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
                                  <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
                                  <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
@@ -288,19 +336,19 @@
                         bias-pull-up;
                 };
 
-                pins_clk {
+                pins-clk {
                         pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
                         bias-pull-down;
                 };
 
-                pins_rst {
+                pins-rst {
                         pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
                         bias-pull-up;
                 };
         };
 
         mmc0_pins_uhs: mmc0 {
-                pins_cmd_dat {
+                pins-cmd-dat {
                         pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
                                  <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
                                  <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
@@ -315,20 +363,20 @@
                         bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
                 };
 
-                pins_clk {
+                pins-clk {
                         pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
                         drive-strength = <MTK_DRIVE_2mA>;
                         bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
                 };
 
-                pins_rst {
+                pins-rst {
                         pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
                         bias-pull-up;
                 };
         };
 
         mmc1_pins_default: mmc1default {
-                pins_cmd_dat {
+                pins-cmd-dat {
                         pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
                                  <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
                                  <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
@@ -339,26 +387,26 @@
                         bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
                 };
 
-                pins_clk {
+                pins-clk {
                         pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
                         bias-pull-down;
                         drive-strength = <MTK_DRIVE_4mA>;
                 };
 
-                pins_wp {
+                pins-wp {
                         pinmux = <MT7623_PIN_29_EINT7_FUNC_MSDC1_WP>;
                         input-enable;
                         bias-pull-up;
                 };
 
-                pins_insert {
+                pins-insert {
                         pinmux = <MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261>;
                         bias-pull-up;
                 };
         };
 
         mmc1_pins_uhs: mmc1 {
-                pins_cmd_dat {
+                pins-cmd-dat {
                         pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
                                  <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
                                  <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
@@ -369,15 +417,23 @@
                         bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
                 };
 
-                pins_clk {
+                pins-clk {
                         pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
                         drive-strength = <MTK_DRIVE_4mA>;
                         bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
                 };
         };
 
+        pcie_default: pcie_pin_default {
+                pins_cmd_dat {
+                        pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>,
+                                 <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>;
+                        bias-disable;
+                };
+        };
+
         pwm_pins_a: pwm@0 {
-                pins_pwm {
+                pins-pwm {
                         pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>,
                                  <MT7623_PIN_204_PWM1_FUNC_PWM1>,
                                  <MT7623_PIN_205_PWM2_FUNC_PWM2>,
@@ -387,7 +443,7 @@
         };
 
         spi0_pins_a: spi@0 {
-                pins_spi {
+                pins-spi {
                         pinmux = <MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS>,
                                 <MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK>,
                                 <MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI>,
@@ -397,18 +453,25 @@
         };
 
         uart0_pins_a: uart@0 {
-                pins_dat {
+                pins-dat {
                         pinmux = <MT7623_PIN_79_URXD0_FUNC_URXD0>,
                                  <MT7623_PIN_80_UTXD0_FUNC_UTXD0>;
                 };
         };
 
         uart1_pins_a: uart@1 {
-                pins_dat {
+                pins-dat {
                         pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>,
                                  <MT7623_PIN_82_UTXD1_FUNC_UTXD1>;
                 };
         };
+
+        uart2_pins_a: uart@2 {
+                pins-dat {
+                        pinmux = <MT7623_PIN_14_GPIO14_FUNC_URXD2>,
+                                 <MT7623_PIN_15_GPIO15_FUNC_UTXD2>;
+                };
+        };
 };
 
 &pwm {
@@ -454,26 +517,30 @@
 &uart0 {
         pinctrl-names = "default";
         pinctrl-0 = <&uart0_pins_a>;
-        status = "disabled";
+        status = "okay";
 };
 
 &uart1 {
         pinctrl-names = "default";
         pinctrl-0 = <&uart1_pins_a>;
-        status = "disabled";
+        status = "okay";
 };
 
 &uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart2_pins_a>;
         status = "okay";
 };
 
 &usb1 {
-        vusb33-supply = <&mt6323_vusb_reg>;
+        vusb33-supply = <&reg_3p3v>;
+        vbus-supply = <&reg_5v>;
         status = "okay";
 };
 
 &usb2 {
-        vusb33-supply = <&mt6323_vusb_reg>;
+        vusb33-supply = <&reg_3p3v>;
+        vbus-supply = <&reg_5v>;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/mt7623n-rfb-nand.dts b/arch/arm/boot/dts/mt7623n-rfb-nand.dts
index e66de8611650..f729c718aba1 100644
--- a/arch/arm/boot/dts/mt7623n-rfb-nand.dts
+++ b/arch/arm/boot/dts/mt7623n-rfb-nand.dts
@@ -81,13 +81,13 @@
 
 &pio {
         nand_pins_default: nanddefault {
-                pins_ale {
+                pins-ale {
                         pinmux = <MT7623_PIN_116_MSDC0_CMD_FUNC_NALE>;
                         drive-strength = <MTK_DRIVE_8mA>;
                         bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
                 };
 
-                pins_dat {
+                pins-dat {
                         pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_NLD7>,
                                  <MT7623_PIN_112_MSDC0_DAT6_FUNC_NLD6>,
                                  <MT7623_PIN_114_MSDC0_DAT4_FUNC_NLD4>,
@@ -102,7 +102,7 @@
                         bias-pull-up;
                 };
 
-                pins_we {
+                pins-we {
                         pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB>;
                         drive-strength = <MTK_DRIVE_8mA>;
                         bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
diff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
new file mode 100644
index 000000000000..cabde3d5be8a
--- /dev/null
+++ b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018 Nuvoton Technology corporation.
+// Copyright 2018 Google, Inc.
+
+/dts-v1/;
+#include "nuvoton-npcm750.dtsi"
+
+/ {
+        model = "Nuvoton npcm750 Development Board (Device Tree)";
+        compatible = "nuvoton,npcm750";
+
+        chosen {
+                stdout-path = &serial3;
+        };
+
+        memory {
+                reg = <0 0x40000000>;
+        };
+};
+
+&serial0 {
+        status = "okay";
+};
+
+&serial1 {
+        status = "okay";
+};
+
+&serial2 {
+        status = "okay";
+};
+
+&serial3 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
new file mode 100644
index 000000000000..839e45cfd695
--- /dev/null
+++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
@@ -0,0 +1,165 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018 Nuvoton Technology corporation.
+// Copyright 2018 Google, Inc.
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        interrupt-parent = <&gic>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                enable-method = "nuvoton,npcm750-smp";
+
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        clocks = <&clk 10>;
+                        clock-names = "clk_cpu";
+                        reg = <0>;
+                        next-level-cache = <&l2>;
+                };
+
+                cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        clocks = <&clk 10>;
+                        clock-names = "clk_cpu";
+                        reg = <1>;
+                        next-level-cache = <&l2>;
+                };
+        };
+
+        /* external clock signal rg1refck, supplied by the phy */
+        clk-rg1refck {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <125000000>;
+        };
+
+        /* external clock signal rg2refck, supplied by the phy */
+        clk-rg2refck {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <125000000>;
+        };
+
+        clk-xin {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <50000000>;
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                interrupt-parent = <&gic>;
+                ranges = <0x0 0xf0000000 0x00900000>;
+
+                gcr: gcr@800000 {
+                        compatible = "nuvoton,npcm750-gcr", "syscon",
+                                "simple-mfd";
+                        reg = <0x800000 0x1000>;
+                };
+
+                scu: scu@3fe000 {
+                        compatible = "arm,cortex-a9-scu";
+                        reg = <0x3fe000 0x1000>;
+                };
+
+                l2: cache-controller@3fc000 {
+                        compatible = "arm,pl310-cache";
+                        reg = <0x3fc000 0x1000>;
+                        interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+                        cache-unified;
+                        cache-level = <2>;
+                        clocks = <&clk 22>;
+                        arm,shared-override;
+                };
+
+                gic: interrupt-controller@3ff000 {
+                        compatible = "arm,cortex-a9-gic";
+                        interrupt-controller;
+                        #interrupt-cells = <3>;
+                        reg = <0x3ff000 0x1000>,
+                            <0x3fe100 0x100>;
+                };
+
+                timer@3fe600 {
+                        compatible = "arm,cortex-a9-twd-timer";
+                        reg = <0x3fe600 0x20>;
+                        interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+                                                  IRQ_TYPE_LEVEL_HIGH)>;
+                        clocks = <&clk 15>;
+                };
+        };
+
+        ahb {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                interrupt-parent = <&gic>;
+                ranges;
+
+                clk: clock-controller@f0801000 {
+                        compatible = "nuvoton,npcm750-clk";
+                        #clock-cells = <1>;
+                        reg = <0xf0801000 0x1000>;
+                };
+
+                apb {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "simple-bus";
+                        interrupt-parent = <&gic>;
+                        ranges = <0x0 0xf0000000 0x00300000>;
+
+                        timer0: timer@8000 {
+                                compatible = "nuvoton,npcm750-timer";
+                                interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+                                reg = <0x8000 0x1000>;
+                                clocks = <&clk 15>;
+                        };
+
+                        serial0: serial@1000 {
+                                compatible = "ns16550a";
+                                reg = <0x1000 0x1000>;
+                                clocks = <&clk 14>;
+                                interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+                                reg-shift = <2>;
+                                status = "disabled";
+                        };
+
+                        serial1: serial@2000 {
+                                compatible = "ns16550a";
+                                reg = <0x2000 0x1000>;
+                                clocks = <&clk 14>;
+                                interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+                                reg-shift = <2>;
+                                status = "disabled";
+                        };
+
+                        serial2: serial@3000 {
+                                compatible = "ns16550a";
+                                reg = <0x3000 0x1000>;
+                                clocks = <&clk 14>;
+                                interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+                                reg-shift = <2>;
+                                status = "disabled";
+                        };
+
+                        serial3: serial@4000 {
+                                compatible = "ns16550a";
+                                reg = <0x4000 0x1000>;
+                                clocks = <&clk 14>;
+                                interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+                                reg-shift = <2>;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-n9.dts b/arch/arm/boot/dts/omap3-n9.dts
index e44d93fc644c..ded5fcf084eb 100644
--- a/arch/arm/boot/dts/omap3-n9.dts
+++ b/arch/arm/boot/dts/omap3-n9.dts
@@ -39,6 +39,13 @@
         };
 };
 
+&i2c3 {
+        ak8975@0f {
+                compatible = "asahi-kasei,ak8975";
+                reg = <0x0f>;
+        };
+};
+
 &isp {
         vdd-csiphy1-supply = <&vaux2>;
         vdd-csiphy2-supply = <&vaux2>;
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index a005802cd52b..4043ecb38016 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -557,6 +557,7 @@
                         dma-names = "tx", "rx";
                         clocks = <&mcbsp4_fck>;
                         clock-names = "fck";
+                        #sound-dai-cells = <0>;
                         status = "disabled";
                 };
 
diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/omap4-droid4-xt894.dts
index b21084da490b..bdf73cbcec3a 100644
--- a/arch/arm/boot/dts/omap4-droid4-xt894.dts
+++ b/arch/arm/boot/dts/omap4-droid4-xt894.dts
@@ -70,8 +70,30 @@
                 regulator-always-on;
         };
 
-        /* HS USB Host PHY on PORT 1 */
-        hsusb1_phy: hsusb1_phy {
+        /* FS USB Host PHY on port 1 for mdm6600 */
+        fsusb1_phy: usb-phy@1 {
+                compatible = "motorola,mapphone-mdm6600";
+                pinctrl-0 = <&usb_mdm6600_pins>;
+                pinctrl-names = "default";
+                enable-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;     /* gpio_95 */
+                power-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;     /* gpio_54 */
+                reset-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;     /* gpio_49 */
+                /* mode: gpio_148 gpio_149 */
+                motorola,mode-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>,
+                                      <&gpio5 21 GPIO_ACTIVE_HIGH>;
+                /* cmd: gpio_103 gpio_104 gpio_142 */
+                motorola,cmd-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>,
+                                     <&gpio4 8 GPIO_ACTIVE_HIGH>,
+                                     <&gpio5 14 GPIO_ACTIVE_HIGH>;
+                /* status: gpio_52 gpio_53 gpio_55 */
+                motorola,status-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>,
+                                        <&gpio2 21 GPIO_ACTIVE_HIGH>,
+                                        <&gpio2 23 GPIO_ACTIVE_HIGH>;
+                #phy-cells = <0>;
+        };
+
+        /* HS USB host TLL nop-phy on port 2 for w3glte */
+        hsusb2_phy: usb-phy@2 {
                 compatible = "usb-nop-xceiv";
                 #phy-cells = <0>;
         };
@@ -117,6 +139,26 @@
 
                 };
         };
+
+        soundcard {
+                compatible = "audio-graph-card";
+                label = "Droid 4 Audio";
+
+                simple-graph-card,widgets =
+                        "Speaker", "Earpiece",
+                        "Speaker", "Loudspeaker",
+                        "Headphone", "Headphone Jack",
+                        "Microphone", "Internal Mic";
+
+                simple-graph-card,routing =
+                        "Earpiece", "EP",
+                        "Loudspeaker", "SPKR",
+                        "Headphone Jack", "HSL",
+                        "Headphone Jack", "HSR",
+                        "MICR", "Internal Mic";
+
+                dais = <&mcbsp2_port>, <&mcbsp3_port>;
+        };
 };
 
 &dss {
@@ -124,13 +166,6 @@
 };
 
 &gpio6 {
-        touchscreen_reset {
-                gpio-hog;
-                gpios = <13 0>;
-                output-high;
-                line-name = "touchscreen-reset";
-        };
-
         pwm8: dmtimer-pwm-8 {
                 pinctrl-names = "default";
                 pinctrl-0 = <&vibrator_direction_pin>;
@@ -362,22 +397,18 @@
         };
 };
 
-/*
- * REVISIT: Add gpio173 reset pin handling to the driver, see gpio-hog above.
- * If the GPIO reset is used, we probably need to have /lib/firmware/maxtouch.fw
- * available. See "mxt-app" and "droid4-touchscreen-firmware" tools for more
- * information.
- */
 &i2c2 {
-        tsp@4a {
+        touchscreen@4a {
                 compatible = "atmel,maxtouch";
                 reg = <0x4a>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&touchscreen_pins>;
 
+                reset-gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; /* gpio173 */
+
                 /* gpio_183 with sys_nirq2 pad as wakeup */
-                interrupts-extended = <&gpio6 23 IRQ_TYPE_EDGE_FALLING
-                                       &omap4_pmx_core 0x160>;
+                interrupts-extended = <&gpio6 23 IRQ_TYPE_EDGE_FALLING>,
+                                      <&omap4_pmx_core 0x160>;
                 interrupt-names = "irq", "wakeup";
                 wakeup-source;
         };
@@ -435,6 +466,7 @@
 
         touchscreen_pins: pinmux_touchscreen_pins {
                 pinctrl-single,pins = <
+                OMAP4_IOPAD(0x180, PIN_OUTPUT | MUX_MODE3)
                 OMAP4_IOPAD(0x1a0, PIN_INPUT_PULLUP | MUX_MODE3)
                 >;
         };
@@ -445,6 +477,43 @@
                 >;
         };
 
+        usb_mdm6600_pins: pinmux_usb_mdm6600_pins {
+                pinctrl-single,pins = <
+                /* enable 0x4a1000d8 usbb1_ulpitll_dat7.gpio_95 ag16 */
+                OMAP4_IOPAD(0x0d8, PIN_INPUT | MUX_MODE3)
+
+                /* power 0x4a10007c gpmc_nwp.gpio_54 c25 */
+                OMAP4_IOPAD(0x07c, PIN_OUTPUT | MUX_MODE3)
+
+                /* reset 0x4a100072 gpmc_a25.gpio_49 d20 */
+                OMAP4_IOPAD(0x072, PIN_OUTPUT | MUX_MODE3)
+
+                /* mode0/bpwake 0x4a10014e sdmmc5_dat1.gpio_148 af4 */
+                OMAP4_IOPAD(0x14e, PIN_OUTPUT | MUX_MODE3)
+
+                /* mode1/apwake 0x4a100150 sdmmc5_dat2.gpio_149 ag3 */
+                OMAP4_IOPAD(0x150, PIN_OFF_OUTPUT_LOW | PIN_INPUT | MUX_MODE3)
+
+                /* status0 0x4a10007e gpmc_clk.gpio_55 b22 */
+                OMAP4_IOPAD(0x07e, PIN_INPUT | MUX_MODE3)
+
+                /* status1 0x4a10007a gpmc_ncs3.gpio_53 c22 */
+                OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3)
+
+                /* status2 0x4a100078 gpmc_ncs2.gpio_52 d21 */
+                OMAP4_IOPAD(0x078, PIN_INPUT | MUX_MODE3)
+
+                /* cmd0 0x4a100094 gpmc_ncs6.gpio_103 c24 */
+                OMAP4_IOPAD(0x094, PIN_OUTPUT | MUX_MODE3)
+
+                /* cmd1 0x4a100096 gpmc_ncs7.gpio_104 d24 */
+                OMAP4_IOPAD(0x096, PIN_OUTPUT | MUX_MODE3)
+
+                /* cmd2 0x4a100142 uart3_rts_sd.gpio_142 f28 */
+                OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE3)
+                >;
+        };
+
         usb_ulpi_pins: pinmux_usb_ulpi_pins {
                 pinctrl-single,pins = <
                 OMAP4_IOPAD(0x196, MUX_MODE7)
@@ -484,6 +553,28 @@
                 >;
         };
 
+        /*
+         * Note that the v3.0.8 stock userspace dynamically remuxes uart1
+         * rts pin probably for PM purposes to PIN_INPUT_PULLUP | MUX_MODE7
+         * when not used. If needed, we can add rts pin remux later based
+         * on power measurements.
+         */
+        uart1_pins: pinmux_uart1_pins {
+                pinctrl-single,pins = <
+                /* 0x4a10013c mcspi1_cs2.uart1_cts ag23 */
+                OMAP4_IOPAD(0x13c, PIN_INPUT_PULLUP | MUX_MODE1)
+
+                /* 0x4a10013e mcspi1_cs3.uart1_rts ah23 */
+                OMAP4_IOPAD(0x13e, MUX_MODE1)
+
+                /* 0x4a100140 uart3_cts_rctx.uart1_tx f27 */
+                OMAP4_IOPAD(0x140, PIN_OUTPUT | MUX_MODE1)
+
+                /* 0x4a1001ca dpm_emu14.uart1_rx aa3 */
+                OMAP4_IOPAD(0x1ca, PIN_INPUT_PULLUP | MUX_MODE2)
+                >;
+        };
+
         /* uart3_tx_irtx and uart3_rx_irrx */
         uart3_pins: pinmux_uart3_pins {
                 pinctrl-single,pins = <
@@ -512,6 +603,24 @@
                 OMAP4_IOPAD(0x112, PIN_OUTPUT_PULLUP | MUX_MODE5)       /* uart4_rts */
                 >;
         };
+
+        mcbsp2_pins: pinmux_mcbsp2_pins {
+                pinctrl-single,pins = <
+                OMAP4_IOPAD(0x0f6, PIN_INPUT | MUX_MODE0)       /* abe_mcbsp2_clkx */
+                OMAP4_IOPAD(0x0f8, PIN_INPUT | MUX_MODE0)       /* abe_mcbsp2_dr */
+                OMAP4_IOPAD(0x0fa, PIN_OUTPUT | MUX_MODE0)      /* abe_mcbsp2_dx */
+                OMAP4_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0)       /* abe_mcbsp2_fsx */
+                >;
+        };
+
+        mcbsp3_pins: pinmux_mcbsp3_pins {
+                pinctrl-single,pins = <
+                OMAP4_IOPAD(0x106, PIN_INPUT | MUX_MODE1)       /* abe_mcbsp3_dr */
+                OMAP4_IOPAD(0x108, PIN_OUTPUT | MUX_MODE1)      /* abe_mcbsp3_dx */
+                OMAP4_IOPAD(0x10a, PIN_INPUT | MUX_MODE1)       /* abe_mcbsp3_clkx */
+                OMAP4_IOPAD(0x10c, PIN_INPUT | MUX_MODE1)       /* abe_mcbsp3_fsx */
+                >;
+        };
 };
 
 &omap4_pmx_wkup {
@@ -535,6 +644,17 @@
         };
 };
 
+/*
+ * As uart1 is wired to mdm6600 with rts and cts, we can use the cts pin for
+ * uart1 wakeirq.
+ */
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart1_pins>;
+        interrupts-extended = <&wakeupgen GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH
+                               &omap4_pmx_core 0xfc>;
+};
+
 &uart3 {
         interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
                                &omap4_pmx_core 0x17c>;
@@ -551,8 +671,13 @@
         };
 };
 
+&usbhsohci {
+        phys = <&fsusb1_phy>;
+        phy-names = "usb";
+};
+
 &usbhsehci {
-        phys = <&hsusb1_phy>;
+        phys = <&hsusb2_phy>;
 };
 
 &usbhshost {
@@ -597,3 +722,43 @@
                                   "0", "0", "1";
         };
 };
+
+&mcbsp2 {
+        #sound-dai-cells = <0>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&mcbsp2_pins>;
+        status = "okay";
+
+        mcbsp2_port: port {
+                cpu_dai2: endpoint {
+                        dai-format = "i2s";
+                        remote-endpoint = <&cpcap_audio_codec0>;
+                        frame-master = <&cpcap_audio_codec0>;
+                        bitclock-master = <&cpcap_audio_codec0>;
+                };
+        };
+};
+
+&mcbsp3 {
+        #sound-dai-cells = <0>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&mcbsp3_pins>;
+        status = "okay";
+
+        mcbsp3_port: port {
+                cpu_dai3: endpoint {
+                        dai-format = "dsp_a";
+                        frame-master = <&cpcap_audio_codec1>;
+                        bitclock-master = <&cpcap_audio_codec1>;
+                        remote-endpoint = <&cpcap_audio_codec1>;
+                };
+        };
+};
+
+&cpcap_audio_codec0 {
+        remote-endpoint = <&cpu_dai2>;
+};
+
+&cpcap_audio_codec1 {
+        remote-endpoint = <&cpu_dai3>;
+};
diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi
index 03c8ad91ddac..cbcdcb4e7d1c 100644
--- a/arch/arm/boot/dts/omap443x.dtsi
+++ b/arch/arm/boot/dts/omap443x.dtsi
@@ -24,8 +24,6 @@
                         clock-latency = <300000>; /* From legacy driver */
 
                         /* cooling options */
-                        cooling-min-level = <0>;
-                        cooling-max-level = <3>;
                         #cooling-cells = <2>; /* min followed by max */
                 };
         };
diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
index c43f2a2d0a1e..ad97493e4e46 100644
--- a/arch/arm/boot/dts/omap4460.dtsi
+++ b/arch/arm/boot/dts/omap4460.dtsi
@@ -22,8 +22,6 @@
                         clock-latency = <300000>; /* From legacy driver */
 
                         /* cooling options */
-                        cooling-min-level = <0>;
-                        cooling-max-level = <2>;
                         #cooling-cells = <2>; /* min followed by max */
                 };
         };
diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi b/arch/arm/boot/dts/omap5-board-common.dtsi
index 1b20838bb9a4..3b2244560c28 100644
--- a/arch/arm/boot/dts/omap5-board-common.dtsi
+++ b/arch/arm/boot/dts/omap5-board-common.dtsi
@@ -659,8 +659,8 @@
                 v2v1-supply = <&smps9_reg>;
                 enable-active-high;
 
-                clocks = <&clk32kgaudio>;
-                clock-names = "clk32k";
+                clocks = <&clk32kgaudio>, <&fref_xtal_ck>;
+                clock-names = "clk32k", "mclk";
         };
 };
 
diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
index ec2c8baef62a..592e17fd4eeb 100644
--- a/arch/arm/boot/dts/omap5-uevm.dts
+++ b/arch/arm/boot/dts/omap5-uevm.dts
@@ -47,7 +47,7 @@
                         gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;    /* gpio3_83 */
                         wakeup-source;
                         autorepeat;
-                        debounce_interval = <50>;
+                        debounce-interval = <50>;
                 };
         };
 
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 35d4298da83d..732b61a0e990 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -55,8 +55,6 @@
                         clock-latency = <300000>; /* From omap-cpufreq driver */
 
                         /* cooling options */
-                        cooling-min-level = <0>;
-                        cooling-max-level = <2>;
                         #cooling-cells = <2>; /* min followed by max */
                 };
                 cpu@1 {
@@ -289,6 +287,28 @@
                                 pinctrl-single,register-width = <16>;
                                 pinctrl-single,function-mask = <0x7fff>;
                         };
+
+                        omap5_scm_wkup_pad_conf: omap5_scm_wkup_pad_conf@cda0 {
+                                compatible = "ti,omap5-scm-wkup-pad-conf",
+                                             "simple-bus";
+                                reg = <0xcda0 0x60>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0 0xcda0 0x60>;
+
+                                scm_wkup_pad_conf: scm_conf@0 {
+                                        compatible = "syscon", "simple-bus";
+                                        reg = <0x0 0x60>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        ranges = <0 0x0 0x60>;
+
+                                        scm_wkup_pad_conf_clocks: clocks@0 {
+                                                #address-cells = <1>;
+                                                #size-cells = <0>;
+                                        };
+                                };
+                        };
                 };
 
                 ocmcram: ocmcram@40300000 {
diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi
index 9619a746d657..ecc5573d264c 100644
--- a/arch/arm/boot/dts/omap54xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi
@@ -1179,3 +1179,13 @@
                 };
         };
 };
+
+&scm_wkup_pad_conf_clocks {
+        fref_xtal_ck: fref_xtal_ck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_clkin>;
+                ti,bit-shift = <28>;
+                reg = <0x14>;
+        };
+};
diff --git a/arch/arm/boot/dts/orion5x-lacie-d2-network.dts b/arch/arm/boot/dts/orion5x-lacie-d2-network.dts
index c701e8d16bbb..8c2449da6f00 100644
--- a/arch/arm/boot/dts/orion5x-lacie-d2-network.dts
+++ b/arch/arm/boot/dts/orion5x-lacie-d2-network.dts
@@ -24,7 +24,7 @@
 
         chosen {
                 bootargs = "console=ttyS0,115200n8 earlyprintk";
-                linux,stdout-path = &uart0;
+                stdout-path = &uart0;
         };
 
         soc {
diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
index 89ff404a528c..b545d0f228a5 100644
--- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
+++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
@@ -30,7 +30,7 @@
 
         chosen {
                 bootargs = "console=ttyS0,115200n8 earlyprintk";
-                linux,stdout-path = &uart0;
+                stdout-path = &uart0;
         };
 
         soc {
diff --git a/arch/arm/boot/dts/orion5x-linkstation.dtsi b/arch/arm/boot/dts/orion5x-linkstation.dtsi
index e9991c83d7b7..ebd93df5d07a 100644
--- a/arch/arm/boot/dts/orion5x-linkstation.dtsi
+++ b/arch/arm/boot/dts/orion5x-linkstation.dtsi
@@ -48,7 +48,7 @@
 / {
         chosen {
                 bootargs = "console=ttyS0,115200n8 earlyprintk";
-                linux,stdout-path = &uart0;
+                stdout-path = &uart0;
         };
 
         soc {
diff --git a/arch/arm/boot/dts/orion5x-lswsgl.dts b/arch/arm/boot/dts/orion5x-lswsgl.dts
index ea966ec03dd0..0d97ded66257 100644
--- a/arch/arm/boot/dts/orion5x-lswsgl.dts
+++ b/arch/arm/boot/dts/orion5x-lswsgl.dts
@@ -60,7 +60,7 @@
 
         chosen {
                 bootargs = "console=ttyS0,115200 earlyprintk";
-                linux,stdout-path = &uart0;
+                stdout-path = &uart0;
         };
 
         soc {
diff --git a/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts b/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts
index ff3484904294..0324cb54939d 100644
--- a/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts
+++ b/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts
@@ -24,7 +24,7 @@
 
         chosen {
                 bootargs = "console=ttyS0,115200n8 earlyprintk";
-                linux,stdout-path = &uart0;
+                stdout-path = &uart0;
         };
 
         soc {
diff --git a/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts b/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts
index 6fb052507b36..d1817af53e0b 100644
--- a/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts
+++ b/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts
@@ -21,7 +21,7 @@
 
         chosen {
                 bootargs = "console=ttyS0,115200n8 earlyprintk";
-                linux,stdout-path = &uart0;
+                stdout-path = &uart0;
         };
 
         soc {
diff --git a/arch/arm/boot/dts/picoxcell-pc7302-pc3x2.dts b/arch/arm/boot/dts/picoxcell-pc7302-pc3x2.dts
index 1297414dd649..0c9729306089 100644
--- a/arch/arm/boot/dts/picoxcell-pc7302-pc3x2.dts
+++ b/arch/arm/boot/dts/picoxcell-pc7302-pc3x2.dts
@@ -23,7 +23,7 @@
         };
 
         chosen {
-                linux,stdout-path = &uart0;
+                stdout-path = &uart0;
         };
 
         clocks {
diff --git a/arch/arm/boot/dts/picoxcell-pc7302-pc3x3.dts b/arch/arm/boot/dts/picoxcell-pc7302-pc3x3.dts
index 9e317a4f431c..86f26715b619 100644
--- a/arch/arm/boot/dts/picoxcell-pc7302-pc3x3.dts
+++ b/arch/arm/boot/dts/picoxcell-pc7302-pc3x3.dts
@@ -23,7 +23,7 @@
         };
 
         chosen {
-                linux,stdout-path = &uart0;
+                stdout-path = &uart0;
         };
 
         clocks {
diff --git a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
index b818ebce0978..209eb21cea00 100644
--- a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
@@ -133,7 +133,7 @@
                                 clock-frequency = <200000>;
 
                                 eeprom@50 {
-                                        compatible = "24c02";
+                                        compatible = "atmel,24c02";
                                         reg = <0x50>;
                                         pagesize = <32>;
                                 };
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 3ca96e361878..5341a39c0392 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -316,6 +316,23 @@
                 };
         };
 
+
+        /*
+         * These channels from the ADC are simply hardware monitors.
+         * That is why the ADC is referred to as "HKADC" - HouseKeeping
+         * ADC.
+         */
+        iio-hwmon {
+                compatible = "iio-hwmon";
+                io-channels = <&xoadc 0x00 0x01>, /* Battery */
+                            <&xoadc 0x00 0x02>, /* DC in (charger) */
+                            <&xoadc 0x00 0x04>, /* VPH the main system voltage */
+                            <&xoadc 0x00 0x0b>, /* Die temperature */
+                            <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
+                            <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
+                            <&xoadc 0x00 0x0e>; /* Charger temperature */
+        };
+
         soc: soc {
                 #address-cells = <1>;
                 #size-cells = <1>;
@@ -770,6 +787,52 @@
                                         debounce = <15625>;
                                         pull-up;
                                 };
+
+                                xoadc: xoadc@197 {
+                                        compatible = "qcom,pm8921-adc";
+                                        reg = <197>;
+                                        interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>;
+                                        #address-cells = <2>;
+                                        #size-cells = <0>;
+                                        #io-channel-cells = <2>;
+
+                                        vcoin: adc-channel@00 {
+                                                reg = <0x00 0x00>;
+                                        };
+                                        vbat: adc-channel@01 {
+                                                reg = <0x00 0x01>;
+                                        };
+                                        dcin: adc-channel@02 {
+                                                reg = <0x00 0x02>;
+                                        };
+                                        vph_pwr: adc-channel@04 {
+                                                reg = <0x00 0x04>;
+                                        };
+                                        batt_therm: adc-channel@08 {
+                                                reg = <0x00 0x08>;
+                                        };
+                                        batt_id: adc-channel@09 {
+                                                reg = <0x00 0x09>;
+                                        };
+                                        usb_vbus: adc-channel@0a {
+                                                reg = <0x00 0x0a>;
+                                        };
+                                        die_temp: adc-channel@0b {
+                                                reg = <0x00 0x0b>;
+                                        };
+                                        ref_625mv: adc-channel@0c {
+                                                reg = <0x00 0x0c>;
+                                        };
+                                        ref_1250mv: adc-channel@0d {
+                                                reg = <0x00 0x0d>;
+                                        };
+                                        chg_temp: adc-channel@0e {
+                                                reg = <0x00 0x0e>;
+                                        };
+                                        ref_muxoff: adc-channel@0f {
+                                                reg = <0x00 0x0f>;
+                                        };
+                                };
                         };
                 };
 
diff --git a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts
new file mode 100644
index 000000000000..eaa1001d0a46
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "qcom-msm8974pro.dtsi"
+#include "qcom-pm8841.dtsi"
+#include "qcom-pm8941.dtsi"
+
+/ {
+        model = "Samsung Galaxy S5";
+        compatible = "samsung,klte", "qcom,msm8974";
+
+        aliases {
+                serial0 = &blsp1_uart1;
+        };
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+};
+
+&soc {
+        serial@f991e000 {
+                status = "ok";
+        };
+
+};
diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts
index e87f2c99060d..701b396719c7 100644
--- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts
+++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-castor.dts
@@ -491,7 +491,7 @@
                 pinctrl-0 = <&i2c8_pins>;
 
                 synaptics@2c {
-                        compatible = "syna,rmi-i2c";
+                        compatible = "syna,rmi4-i2c";
                         reg = <0x2c>;
 
                         interrupt-parent = <&msmgpio>;
@@ -506,6 +506,8 @@
                         pinctrl-names = "default";
                         pinctrl-0 = <&ts_int_pin>;
 
+                        syna,startup-delay-ms = <10>;
+
                         rmi-f01@1 {
                                 reg = <0x1>;
                                 syna,nosleep = <1>;
diff --git a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
index 75a8ca571846..1d3e9503c5bd 100644
--- a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
+++ b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
@@ -34,6 +34,10 @@
         };
 };
 
+&cmt0 {
+        status = "okay";
+};
+
 &extal_clk {
         clock-frequency = <20000000>;
 };
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index 0b74c6c7d21d..1d9073ba0ce0 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -141,29 +141,6 @@
                 #size-cells = <2>;
                 ranges;
 
-                apmu@e6152000 {
-                        compatible = "renesas,r8a7743-apmu", "renesas,apmu";
-                        reg = <0 0xe6152000 0 0x188>;
-                        cpus = <&cpu0 &cpu1>;
-                };
-
-                gic: interrupt-controller@f1001000 {
-                        compatible = "arm,gic-400";
-                        #interrupt-cells = <3>;
-                        #address-cells = <0>;
-                        interrupt-controller;
-                        reg = <0 0xf1001000 0 0x1000>,
-                              <0 0xf1002000 0 0x2000>,
-                              <0 0xf1004000 0 0x2000>,
-                              <0 0xf1006000 0 0x2000>;
-                        interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
-                                                 IRQ_TYPE_LEVEL_HIGH)>;
-                        clocks = <&cpg CPG_MOD 408>;
-                        clock-names = "clk";
-                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
-                        resets = <&cpg 408>;
-                };
-
                 gpio0: gpio@e6050000 {
                         compatible = "renesas,gpio-r8a7743",
                                      "renesas,rcar-gen2-gpio";
@@ -284,6 +261,48 @@
                         resets = <&cpg 904>;
                 };
 
+                pfc: pin-controller@e6060000 {
+                        compatible = "renesas,pfc-r8a7743";
+                        reg = <0 0xe6060000 0 0x250>;
+                };
+
+                tpu: pwm@e60f0000 {
+                        compatible = "renesas,tpu-r8a7743", "renesas,tpu";
+                        reg = <0 0xe60f0000 0 0x148>;
+                        clocks = <&cpg CPG_MOD 304>;
+                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 304>;
+                        #pwm-cells = <3>;
+                        status = "disabled";
+                };
+
+                cpg: clock-controller@e6150000 {
+                        compatible = "renesas,r8a7743-cpg-mssr";
+                        reg = <0 0xe6150000 0 0x1000>;
+                        clocks = <&extal_clk>, <&usb_extal_clk>;
+                        clock-names = "extal", "usb_extal";
+                        #clock-cells = <2>;
+                        #power-domain-cells = <0>;
+                        #reset-cells = <1>;
+                };
+
+                apmu@e6152000 {
+                        compatible = "renesas,r8a7743-apmu", "renesas,apmu";
+                        reg = <0 0xe6152000 0 0x188>;
+                        cpus = <&cpu0 &cpu1>;
+                };
+
+                rst: reset-controller@e6160000 {
+                        compatible = "renesas,r8a7743-rst";
+                        reg = <0 0xe6160000 0 0x100>;
+                };
+
+                sysc: system-controller@e6180000 {
+                        compatible = "renesas,r8a7743-sysc";
+                        reg = <0 0xe6180000 0 0x200>;
+                        #power-domain-cells = <1>;
+                };
+
                 irqc: interrupt-controller@e61c0000 {
                         compatible = "renesas,irqc-r8a7743", "renesas,irqc";
                         #interrupt-cells = <2>;
@@ -316,227 +335,89 @@
                         #thermal-sensor-cells = <0>;
                 };
 
-                cmt0: timer@ffca0000 {
-                        compatible = "renesas,r8a7743-cmt0",
-                                     "renesas,rcar-gen2-cmt0";
-                        reg = <0 0xffca0000 0 0x1004>;
-                        interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 124>;
-                        clock-names = "fck";
-                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
-                        resets = <&cpg 124>;
+                ipmmu_sy0: mmu@e6280000 {
+                        compatible = "renesas,ipmmu-r8a7743",
+                                     "renesas,ipmmu-vmsa";
+                        reg = <0 0xe6280000 0 0x1000>;
+                        interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+                        #iommu-cells = <1>;
                         status = "disabled";
                 };
 
-                cmt1: timer@e6130000 {
-                        compatible = "renesas,r8a7743-cmt1",
-                                     "renesas,rcar-gen2-cmt1";
-                        reg = <0 0xe6130000 0 0x1004>;
-                        interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 329>;
-                        clock-names = "fck";
-                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
-                        resets = <&cpg 329>;
+                ipmmu_sy1: mmu@e6290000 {
+                        compatible = "renesas,ipmmu-r8a7743",
+                                     "renesas,ipmmu-vmsa";
+                        reg = <0 0xe6290000 0 0x1000>;
+                        interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+                        #iommu-cells = <1>;
                         status = "disabled";
                 };
 
-                cpg: clock-controller@e6150000 {
-                        compatible = "renesas,r8a7743-cpg-mssr";
-                        reg = <0 0xe6150000 0 0x1000>;
-                        clocks = <&extal_clk>, <&usb_extal_clk>;
-                        clock-names = "extal", "usb_extal";
-                        #clock-cells = <2>;
-                        #power-domain-cells = <0>;
-                        #reset-cells = <1>;
-                };
-
-                prr: chipid@ff000044 {
-                        compatible = "renesas,prr";
-                        reg = <0 0xff000044 0 4>;
-                };
-
-                rst: reset-controller@e6160000 {
-                        compatible = "renesas,r8a7743-rst";
-                        reg = <0 0xe6160000 0 0x100>;
-                };
-
-                sysc: system-controller@e6180000 {
-                        compatible = "renesas,r8a7743-sysc";
-                        reg = <0 0xe6180000 0 0x200>;
-                        #power-domain-cells = <1>;
+                ipmmu_ds: mmu@e6740000 {
+                        compatible = "renesas,ipmmu-r8a7743",
+                                     "renesas,ipmmu-vmsa";
+                        reg = <0 0xe6740000 0 0x1000>;
+                        interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+                        #iommu-cells = <1>;
+                        status = "disabled";
                 };
 
-                pfc: pin-controller@e6060000 {
-                        compatible = "renesas,pfc-r8a7743";
-                        reg = <0 0xe6060000 0 0x250>;
+                ipmmu_mp: mmu@ec680000 {
+                        compatible = "renesas,ipmmu-r8a7743",
+                                     "renesas,ipmmu-vmsa";
+                        reg = <0 0xec680000 0 0x1000>;
+                        interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+                        #iommu-cells = <1>;
+                        status = "disabled";
                 };
 
-                dmac0: dma-controller@e6700000 {
-                        compatible = "renesas,dmac-r8a7743",
-                                     "renesas,rcar-dmac";
-                        reg = <0 0xe6700000 0 0x20000>;
-                        interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
-                        interrupt-names = "error",
-                                        "ch0", "ch1", "ch2", "ch3",
-                                        "ch4", "ch5", "ch6", "ch7",
-                                        "ch8", "ch9", "ch10", "ch11",
-                                        "ch12", "ch13", "ch14";
-                        clocks = <&cpg CPG_MOD 219>;
-                        clock-names = "fck";
-                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
-                        resets = <&cpg 219>;
-                        #dma-cells = <1>;
-                        dma-channels = <15>;
+                ipmmu_mx: mmu@fe951000 {
+                        compatible = "renesas,ipmmu-r8a7743",
+                                     "renesas,ipmmu-vmsa";
+                        reg = <0 0xfe951000 0 0x1000>;
+                        interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+                        #iommu-cells = <1>;
+                        status = "disabled";
                 };
 
-                dmac1: dma-controller@e6720000 {
-                        compatible = "renesas,dmac-r8a7743",
-                                     "renesas,rcar-dmac";
-                        reg = <0 0xe6720000 0 0x20000>;
-                        interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
-                        interrupt-names = "error",
-                                        "ch0", "ch1", "ch2", "ch3",
-                                        "ch4", "ch5", "ch6", "ch7",
-                                        "ch8", "ch9", "ch10", "ch11",
-                                        "ch12", "ch13", "ch14";
-                        clocks = <&cpg CPG_MOD 218>;
-                        clock-names = "fck";
-                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
-                        resets = <&cpg 218>;
-                        #dma-cells = <1>;
-                        dma-channels = <15>;
+                ipmmu_gp: mmu@e62a0000 {
+                        compatible = "renesas,ipmmu-r8a7743",
+                                     "renesas,ipmmu-vmsa";
+                        reg = <0 0xe62a0000 0 0x1000>;
+                        interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+                        #iommu-cells = <1>;
+                        status = "disabled";
                 };
 
-                audma0: dma-controller@ec700000 {
-                        compatible = "renesas,dmac-r8a7743",
-                                     "renesas,rcar-dmac";
-                        reg = <0 0xec700000 0 0x10000>;
-                        interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
-                        interrupt-names = "error",
-                                          "ch0", "ch1", "ch2", "ch3",
-                                          "ch4", "ch5", "ch6", "ch7",
-                                          "ch8", "ch9", "ch10", "ch11",
-                                          "ch12";
-                        clocks = <&cpg CPG_MOD 502>;
-                        clock-names = "fck";
-                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
-                        resets = <&cpg 502>;
-                        #dma-cells = <1>;
-                        dma-channels = <13>;
+                icram0: sram@e63a0000 {
+                        compatible = "mmio-sram";
+                        reg = <0 0xe63a0000 0 0x12000>;
                 };
 
-                audma1: dma-controller@ec720000 {
-                        compatible = "renesas,dmac-r8a7743",
-                                     "renesas,rcar-dmac";
-                        reg = <0 0xec720000 0 0x10000>;
-                        interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
-                        interrupt-names = "error",
-                                          "ch0", "ch1", "ch2", "ch3",
-                                          "ch4", "ch5", "ch6", "ch7",
-                                          "ch8", "ch9", "ch10", "ch11",
-                                          "ch12";
-                        clocks = <&cpg CPG_MOD 501>;
-                        clock-names = "fck";
-                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
-                        resets = <&cpg 501>;
-                        #dma-cells = <1>;
-                        dma-channels = <13>;
-                };
+                icram1: sram@e63c0000 {
+                        compatible = "mmio-sram";
+                        reg = <0 0xe63c0000 0 0x1000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0 0xe63c0000 0x1000>;
 
-                usb_dmac0: dma-controller@e65a0000 {
-                        compatible = "renesas,r8a7743-usb-dmac",
-                                     "renesas,usb-dmac";
-                        reg = <0 0xe65a0000 0 0x100>;
-                        interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
-                        interrupt-names = "ch0", "ch1";
-                        clocks = <&cpg CPG_MOD 330>;
-                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
-                        resets = <&cpg 330>;
-                        #dma-cells = <1>;
-                        dma-channels = <2>;
+                        smp-sram@0 {
+                                compatible = "renesas,smp-sram";
+                                reg = <0 0x10>;
+                        };
                 };
 
-                usb_dmac1: dma-controller@e65b0000 {
-                        compatible = "renesas,r8a7743-usb-dmac",
-                                     "renesas,usb-dmac";
-                        reg = <0 0xe65b0000 0 0x100>;
-                        interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-                        interrupt-names = "ch0", "ch1";
-                        clocks = <&cpg CPG_MOD 331>;
-                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
-                        resets = <&cpg 331>;
-                        #dma-cells = <1>;
-                        dma-channels = <2>;
+                icram2: sram@e6300000 {
+                        compatible = "mmio-sram";
+                        reg = <0 0xe6300000 0 0x40000>;
                 };
 
-                /* The memory map in the User's Manual maps the cores to bus
-                 *  numbers
+                /* The memory map in the User's Manual maps the cores to
+                 * bus numbers
                  */
                 i2c0: i2c@e6508000 {
                         #address-cells = <1>;
@@ -675,6 +556,168 @@
                         status = "disabled";
                 };
 
+                hsusb: usb@e6590000 {
+                        compatible = "renesas,usbhs-r8a7743",
+                                     "renesas,rcar-gen2-usbhs";
+                        reg = <0 0xe6590000 0 0x100>;
+                        interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 704>;
+                        dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
+                               <&usb_dmac1 0>, <&usb_dmac1 1>;
+                        dma-names = "ch0", "ch1", "ch2", "ch3";
+                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 704>;
+                        renesas,buswait = <4>;
+                        phys = <&usb0 1>;
+                        phy-names = "usb";
+                        status = "disabled";
+                };
+
+                usbphy: usb-phy@e6590100 {
+                        compatible = "renesas,usb-phy-r8a7743",
+                                     "renesas,rcar-gen2-usb-phy";
+                        reg = <0 0xe6590100 0 0x100>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&cpg CPG_MOD 704>;
+                        clock-names = "usbhs";
+                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 704>;
+                        status = "disabled";
+
+                        usb0: usb-channel@0 {
+                                reg = <0>;
+                                #phy-cells = <1>;
+                        };
+                        usb2: usb-channel@2 {
+                                reg = <2>;
+                                #phy-cells = <1>;
+                        };
+                };
+
+                usb_dmac0: dma-controller@e65a0000 {
+                        compatible = "renesas,r8a7743-usb-dmac",
+                                     "renesas,usb-dmac";
+                        reg = <0 0xe65a0000 0 0x100>;
+                        interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "ch0", "ch1";
+                        clocks = <&cpg CPG_MOD 330>;
+                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 330>;
+                        #dma-cells = <1>;
+                        dma-channels = <2>;
+                };
+
+                usb_dmac1: dma-controller@e65b0000 {
+                        compatible = "renesas,r8a7743-usb-dmac",
+                                     "renesas,usb-dmac";
+                        reg = <0 0xe65b0000 0 0x100>;
+                        interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "ch0", "ch1";
+                        clocks = <&cpg CPG_MOD 331>;
+                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 331>;
+                        #dma-cells = <1>;
+                        dma-channels = <2>;
+                };
+
+                dmac0: dma-controller@e6700000 {
+                        compatible = "renesas,dmac-r8a7743",
+                                     "renesas,rcar-dmac";
+                        reg = <0 0xe6700000 0 0x20000>;
+                        interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "error",
+                                          "ch0", "ch1", "ch2", "ch3",
+                                          "ch4", "ch5", "ch6", "ch7",
+                                          "ch8", "ch9", "ch10", "ch11",
+                                          "ch12", "ch13", "ch14";
+                        clocks = <&cpg CPG_MOD 219>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 219>;
+                        #dma-cells = <1>;
+                        dma-channels = <15>;
+                };
+
+                dmac1: dma-controller@e6720000 {
+                        compatible = "renesas,dmac-r8a7743",
+                                     "renesas,rcar-dmac";
+                        reg = <0 0xe6720000 0 0x20000>;
+                        interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "error",
+                                          "ch0", "ch1", "ch2", "ch3",
+                                          "ch4", "ch5", "ch6", "ch7",
+                                          "ch8", "ch9", "ch10", "ch11",
+                                          "ch12", "ch13", "ch14";
+                        clocks = <&cpg CPG_MOD 218>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 218>;
+                        #dma-cells = <1>;
+                        dma-channels = <15>;
+                };
+
+                avb: ethernet@e6800000 {
+                        compatible = "renesas,etheravb-r8a7743",
+                                     "renesas,etheravb-rcar-gen2";
+                        reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
+                        interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 812>;
+                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 812>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                qspi: spi@e6b10000 {
+                        compatible = "renesas,qspi-r8a7743", "renesas,qspi";
+                        reg = <0 0xe6b10000 0 0x2c>;
+                        interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 917>;
+                        dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+                               <&dmac1 0x17>, <&dmac1 0x18>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        num-cs = <1>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        resets = <&cpg 917>;
+                        status = "disabled";
+                };
+
                 scifa0: serial@e6c40000 {
                         compatible = "renesas,scifa-r8a7743",
                                      "renesas,rcar-gen2-scifa", "renesas,scifa";
@@ -954,88 +997,6 @@
                         status = "disabled";
                 };
 
-                icram2: sram@e6300000 {
-                        compatible = "mmio-sram";
-                        reg = <0 0xe6300000 0 0x40000>;
-                };
-
-                icram0: sram@e63a0000 {
-                        compatible = "mmio-sram";
-                        reg = <0 0xe63a0000 0 0x12000>;
-                };
-
-                icram1: sram@e63c0000 {
-                        compatible = "mmio-sram";
-                        reg = <0 0xe63c0000 0 0x1000>;
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        ranges = <0 0 0xe63c0000 0x1000>;
-
-                        smp-sram@0 {
-                                compatible = "renesas,smp-sram";
-                                reg = <0 0x10>;
-                        };
-                };
-
-                ether: ethernet@ee700000 {
-                        compatible = "renesas,ether-r8a7743",
-                                     "renesas,rcar-gen2-ether";
-                        reg = <0 0xee700000 0 0x400>;
-                        interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 813>;
-                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
-                        resets = <&cpg 813>;
-                        phy-mode = "rmii";
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        status = "disabled";
-                };
-
-                avb: ethernet@e6800000 {
-                        compatible = "renesas,etheravb-r8a7743",
-                                     "renesas,etheravb-rcar-gen2";
-                        reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
-                        interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 812>;
-                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
-                        resets = <&cpg 812>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        status = "disabled";
-                };
-
-                mmcif0: mmc@ee200000 {
-                        compatible = "renesas,mmcif-r8a7743",
-                                     "renesas,sh-mmcif";
-                        reg = <0 0xee200000 0 0x80>;
-                        interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 315>;
-                        dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
-                               <&dmac1 0xd1>, <&dmac1 0xd2>;
-                        dma-names = "tx", "rx", "tx", "rx";
-                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
-                        resets = <&cpg 315>;
-                        reg-io-width = <4>;
-                        max-frequency = <97500000>;
-                        status = "disabled";
-                };
-
-                qspi: spi@e6b10000 {
-                        compatible = "renesas,qspi-r8a7743", "renesas,qspi";
-                        reg = <0 0xe6b10000 0 0x2c>;
-                        interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 917>;
-                        dmas = <&dmac0 0x17>, <&dmac0 0x18>,
-                               <&dmac1 0x17>, <&dmac1 0x18>;
-                        dma-names = "tx", "rx", "tx", "rx";
-                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
-                        num-cs = <1>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        resets = <&cpg 917>;
-                        status = "disabled";
-                };
-
                 msiof0: spi@e6e20000 {
                         compatible = "renesas,msiof-r8a7743",
                                      "renesas,rcar-gen2-msiof";
@@ -1084,26 +1045,6 @@
                         status = "disabled";
                 };
 
-                /*
-                 * pci1 and xhci share the same phy, therefore only one of them
-                 * can be active at any one time. If both of them are enabled,
-                 * a race condition will determine who'll control the phy.
-                 * A firmware file is needed by the xhci driver in order for
-                 * USB 3.0 to work properly.
-                 */
-                xhci: usb@ee000000 {
-                        compatible = "renesas,xhci-r8a7743",
-                                     "renesas,rcar-gen2-xhci";
-                        reg = <0 0xee000000 0 0xc00>;
-                        interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 328>;
-                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
-                        resets = <&cpg 328>;
-                        phys = <&usb2 1>;
-                        phy-names = "usb";
-                        status = "disabled";
-                };
-
                 pwm0: pwm@e6e30000 {
                         compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar";
                         reg = <0 0xe6e30000 0 0x8>;
@@ -1174,98 +1115,32 @@
                         status = "disabled";
                 };
 
-                tpu: pwm@e60f0000 {
-                        compatible = "renesas,tpu-r8a7743", "renesas,tpu";
-                        reg = <0 0xe60f0000 0 0x148>;
-                        clocks = <&cpg CPG_MOD 304>;
-                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
-                        resets = <&cpg 304>;
-                        #pwm-cells = <3>;
-                        status = "disabled";
-                };
-
-                sdhi0: sd@ee100000 {
-                        compatible = "renesas,sdhi-r8a7743",
-                                     "renesas,rcar-gen2-sdhi";
-                        reg = <0 0xee100000 0 0x328>;
-                        interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 314>;
-                        dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
-                               <&dmac1 0xcd>, <&dmac1 0xce>;
-                        dma-names = "tx", "rx", "tx", "rx";
-                        max-frequency = <195000000>;
-                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
-                        resets = <&cpg 314>;
-                        status = "disabled";
-                };
-
-                sdhi1: sd@ee140000 {
-                        compatible = "renesas,sdhi-r8a7743",
-                                     "renesas,rcar-gen2-sdhi";
-                        reg = <0 0xee140000 0 0x100>;
-                        interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 312>;
-                        dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
-                               <&dmac1 0xc1>, <&dmac1 0xc2>;
-                        dma-names = "tx", "rx", "tx", "rx";
-                        max-frequency = <97500000>;
-                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
-                        resets = <&cpg 312>;
-                        status = "disabled";
-                };
-
-                sdhi2: sd@ee160000 {
-                        compatible = "renesas,sdhi-r8a7743",
-                                     "renesas,rcar-gen2-sdhi";
-                        reg = <0 0xee160000 0 0x100>;
-                        interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 311>;
-                        dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
-                               <&dmac1 0xd3>, <&dmac1 0xd4>;
-                        dma-names = "tx", "rx", "tx", "rx";
-                        max-frequency = <97500000>;
-                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
-                        resets = <&cpg 311>;
-                        status = "disabled";
-                };
-
-                hsusb: usb@e6590000 {
-                        compatible = "renesas,usbhs-r8a7743",
-                                     "renesas,rcar-gen2-usbhs";
-                        reg = <0 0xe6590000 0 0x100>;
-                        interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 704>;
-                        dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
-                               <&usb_dmac1 0>, <&usb_dmac1 1>;
-                        dma-names = "ch0", "ch1", "ch2", "ch3";
+                can0: can@e6e80000 {
+                        compatible = "renesas,can-r8a7743",
+                                     "renesas,rcar-gen2-can";
+                        reg = <0 0xe6e80000 0 0x1000>;
+                        interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 916>,
+                                 <&cpg CPG_CORE R8A7743_CLK_RCAN>,
+                                 <&can_clk>;
+                        clock-names = "clkp1", "clkp2", "can_clk";
                         power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
-                        resets = <&cpg 704>;
-                        renesas,buswait = <4>;
-                        phys = <&usb0 1>;
-                        phy-names = "usb";
+                        resets = <&cpg 916>;
                         status = "disabled";
                 };
 
-                usbphy: usb-phy@e6590100 {
-                        compatible = "renesas,usb-phy-r8a7743",
-                                     "renesas,rcar-gen2-usb-phy";
-                        reg = <0 0xe6590100 0 0x100>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        clocks = <&cpg CPG_MOD 704>;
-                        clock-names = "usbhs";
+                can1: can@e6e88000 {
+                        compatible = "renesas,can-r8a7743",
+                                     "renesas,rcar-gen2-can";
+                        reg = <0 0xe6e88000 0 0x1000>;
+                        interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 915>,
+                                 <&cpg CPG_CORE R8A7743_CLK_RCAN>,
+                                 <&can_clk>;
+                        clock-names = "clkp1", "clkp2", "can_clk";
                         power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
-                        resets = <&cpg 704>;
+                        resets = <&cpg 915>;
                         status = "disabled";
-
-                        usb0: usb-channel@0 {
-                                reg = <0>;
-                                #phy-cells = <1>;
-                        };
-                        usb2: usb-channel@2 {
-                                reg = <2>;
-                                #phy-cells = <1>;
-                        };
                 };
 
                 vin0: video@e6ef0000 {
@@ -1301,162 +1176,6 @@
                         status = "disabled";
                 };
 
-                du: display@feb00000 {
-                        compatible = "renesas,du-r8a7743";
-                        reg = <0 0xfeb00000 0 0x40000>,
-                              <0 0xfeb90000 0 0x1c>;
-                        reg-names = "du", "lvds.0";
-                        interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 724>,
-                                 <&cpg CPG_MOD 723>,
-                                 <&cpg CPG_MOD 726>;
-                        clock-names = "du.0", "du.1", "lvds.0";
-                        status = "disabled";
-
-                        ports {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-
-                                port@0 {
-                                        reg = <0>;
-                                        du_out_rgb: endpoint {
-                                        };
-                                };
-                                port@1 {
-                                        reg = <1>;
-                                        du_out_lvds0: endpoint {
-                                        };
-                                };
-                        };
-                };
-
-                can0: can@e6e80000 {
-                        compatible = "renesas,can-r8a7743",
-                                     "renesas,rcar-gen2-can";
-                        reg = <0 0xe6e80000 0 0x1000>;
-                        interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 916>,
-                                 <&cpg CPG_CORE R8A7743_CLK_RCAN>,
-                                 <&can_clk>;
-                        clock-names = "clkp1", "clkp2", "can_clk";
-                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
-                        resets = <&cpg 916>;
-                        status = "disabled";
-                };
-
-                can1: can@e6e88000 {
-                        compatible = "renesas,can-r8a7743",
-                                     "renesas,rcar-gen2-can";
-                        reg = <0 0xe6e88000 0 0x1000>;
-                        interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 915>,
-                                 <&cpg CPG_CORE R8A7743_CLK_RCAN>,
-                                 <&can_clk>;
-                        clock-names = "clkp1", "clkp2", "can_clk";
-                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
-                        resets = <&cpg 915>;
-                        status = "disabled";
-                };
-
-                pci0: pci@ee090000 {
-                        compatible = "renesas,pci-r8a7743",
-                                     "renesas,pci-rcar-gen2";
-                        device_type = "pci";
-                        reg = <0 0xee090000 0 0xc00>,
-                              <0 0xee080000 0 0x1100>;
-                        interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 703>;
-                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
-                        resets = <&cpg 703>;
-                        status = "disabled";
-
-                        bus-range = <0 0>;
-                        #address-cells = <3>;
-                        #size-cells = <2>;
-                        #interrupt-cells = <1>;
-                        ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
-                        interrupt-map-mask = <0xff00 0 0 0x7>;
-                        interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
-                                         0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
-                                         0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-
-                        usb@1,0 {
-                                reg = <0x800 0 0 0 0>;
-                                phys = <&usb0 0>;
-                                phy-names = "usb";
-                        };
-
-                        usb@2,0 {
-                                reg = <0x1000 0 0 0 0>;
-                                phys = <&usb0 0>;
-                                phy-names = "usb";
-                        };
-                };
-
-                pci1: pci@ee0d0000 {
-                        compatible = "renesas,pci-r8a7743",
-                                     "renesas,pci-rcar-gen2";
-                        device_type = "pci";
-                        reg = <0 0xee0d0000 0 0xc00>,
-                              <0 0xee0c0000 0 0x1100>;
-                        interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 703>;
-                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
-                        resets = <&cpg 703>;
-                        status = "disabled";
-
-                        bus-range = <1 1>;
-                        #address-cells = <3>;
-                        #size-cells = <2>;
-                        #interrupt-cells = <1>;
-                        ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
-                        interrupt-map-mask = <0xff00 0 0 0x7>;
-                        interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
-                                         0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
-                                         0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
-
-                        usb@1,0 {
-                                reg = <0x10800 0 0 0 0>;
-                                phys = <&usb2 0>;
-                                phy-names = "usb";
-                        };
-
-                        usb@2,0 {
-                                reg = <0x11000 0 0 0 0>;
-                                phys = <&usb2 0>;
-                                phy-names = "usb";
-                        };
-                };
-
-                pciec: pcie@fe000000 {
-                        compatible = "renesas,pcie-r8a7743",
-                                     "renesas,pcie-rcar-gen2";
-                        reg = <0 0xfe000000 0 0x80000>;
-                        #address-cells = <3>;
-                        #size-cells = <2>;
-                        bus-range = <0x00 0xff>;
-                        device_type = "pci";
-                        ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
-                                  0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
-                                  0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
-                                  0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
-                        /* Map all possible DDR as inbound ranges */
-                        dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
-                                      0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
-                        interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
-                        #interrupt-cells = <1>;
-                        interrupt-map-mask = <0 0 0 0>;
-                        interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
-                        clock-names = "pcie", "pcie_bus";
-                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
-                        resets = <&cpg 319>;
-                        status = "disabled";
-                };
-
                 rcar_sound: sound@ec500000 {
                         /*
                          * #sound-dai-cells is required
@@ -1641,6 +1360,369 @@
                                 };
                         };
                 };
+
+                audma0: dma-controller@ec700000 {
+                        compatible = "renesas,dmac-r8a7743",
+                                     "renesas,rcar-dmac";
+                        reg = <0 0xec700000 0 0x10000>;
+                        interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "error",
+                                          "ch0", "ch1", "ch2", "ch3",
+                                          "ch4", "ch5", "ch6", "ch7",
+                                          "ch8", "ch9", "ch10", "ch11",
+                                          "ch12";
+                        clocks = <&cpg CPG_MOD 502>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 502>;
+                        #dma-cells = <1>;
+                        dma-channels = <13>;
+                };
+
+                audma1: dma-controller@ec720000 {
+                        compatible = "renesas,dmac-r8a7743",
+                                     "renesas,rcar-dmac";
+                        reg = <0 0xec720000 0 0x10000>;
+                        interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "error",
+                                          "ch0", "ch1", "ch2", "ch3",
+                                          "ch4", "ch5", "ch6", "ch7",
+                                          "ch8", "ch9", "ch10", "ch11",
+                                          "ch12";
+                        clocks = <&cpg CPG_MOD 501>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 501>;
+                        #dma-cells = <1>;
+                        dma-channels = <13>;
+                };
+
+                /*
+                 * pci1 and xhci share the same phy, therefore only one of them
+                 * can be active at any one time. If both of them are enabled,
+                 * a race condition will determine who'll control the phy.
+                 * A firmware file is needed by the xhci driver in order for
+                 * USB 3.0 to work properly.
+                 */
+                xhci: usb@ee000000 {
+                        compatible = "renesas,xhci-r8a7743",
+                                     "renesas,rcar-gen2-xhci";
+                        reg = <0 0xee000000 0 0xc00>;
+                        interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 328>;
+                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 328>;
+                        phys = <&usb2 1>;
+                        phy-names = "usb";
+                        status = "disabled";
+                };
+
+                pci0: pci@ee090000 {
+                        compatible = "renesas,pci-r8a7743",
+                                     "renesas,pci-rcar-gen2";
+                        device_type = "pci";
+                        reg = <0 0xee090000 0 0xc00>,
+                              <0 0xee080000 0 0x1100>;
+                        interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 703>;
+                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 703>;
+                        status = "disabled";
+
+                        bus-range = <0 0>;
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        #interrupt-cells = <1>;
+                        ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
+                        interrupt-map-mask = <0xff00 0 0 0x7>;
+                        interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+                                         0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+                                         0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+
+                        usb@1,0 {
+                                reg = <0x800 0 0 0 0>;
+                                phys = <&usb0 0>;
+                                phy-names = "usb";
+                        };
+
+                        usb@2,0 {
+                                reg = <0x1000 0 0 0 0>;
+                                phys = <&usb0 0>;
+                                phy-names = "usb";
+                        };
+                };
+
+                pci1: pci@ee0d0000 {
+                        compatible = "renesas,pci-r8a7743",
+                                     "renesas,pci-rcar-gen2";
+                        device_type = "pci";
+                        reg = <0 0xee0d0000 0 0xc00>,
+                              <0 0xee0c0000 0 0x1100>;
+                        interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 703>;
+                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 703>;
+                        status = "disabled";
+
+                        bus-range = <1 1>;
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        #interrupt-cells = <1>;
+                        ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
+                        interrupt-map-mask = <0xff00 0 0 0x7>;
+                        interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+                                         0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+                                         0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+
+                        usb@1,0 {
+                                reg = <0x10800 0 0 0 0>;
+                                phys = <&usb2 0>;
+                                phy-names = "usb";
+                        };
+
+                        usb@2,0 {
+                                reg = <0x11000 0 0 0 0>;
+                                phys = <&usb2 0>;
+                                phy-names = "usb";
+                        };
+                };
+
+                sdhi0: sd@ee100000 {
+                        compatible = "renesas,sdhi-r8a7743",
+                                     "renesas,rcar-gen2-sdhi";
+                        reg = <0 0xee100000 0 0x328>;
+                        interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 314>;
+                        dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+                               <&dmac1 0xcd>, <&dmac1 0xce>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        max-frequency = <195000000>;
+                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 314>;
+                        status = "disabled";
+                };
+
+                sdhi1: sd@ee140000 {
+                        compatible = "renesas,sdhi-r8a7743",
+                                     "renesas,rcar-gen2-sdhi";
+                        reg = <0 0xee140000 0 0x100>;
+                        interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 312>;
+                        dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+                               <&dmac1 0xc1>, <&dmac1 0xc2>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        max-frequency = <97500000>;
+                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 312>;
+                        status = "disabled";
+                };
+
+                sdhi2: sd@ee160000 {
+                        compatible = "renesas,sdhi-r8a7743",
+                                     "renesas,rcar-gen2-sdhi";
+                        reg = <0 0xee160000 0 0x100>;
+                        interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 311>;
+                        dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+                               <&dmac1 0xd3>, <&dmac1 0xd4>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        max-frequency = <97500000>;
+                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 311>;
+                        status = "disabled";
+                };
+
+                mmcif0: mmc@ee200000 {
+                        compatible = "renesas,mmcif-r8a7743",
+                                     "renesas,sh-mmcif";
+                        reg = <0 0xee200000 0 0x80>;
+                        interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 315>;
+                        dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+                               <&dmac1 0xd1>, <&dmac1 0xd2>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 315>;
+                        reg-io-width = <4>;
+                        max-frequency = <97500000>;
+                        status = "disabled";
+                };
+
+                ether: ethernet@ee700000 {
+                        compatible = "renesas,ether-r8a7743",
+                                     "renesas,rcar-gen2-ether";
+                        reg = <0 0xee700000 0 0x400>;
+                        interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 813>;
+                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 813>;
+                        phy-mode = "rmii";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                gic: interrupt-controller@f1001000 {
+                        compatible = "arm,gic-400";
+                        #interrupt-cells = <3>;
+                        #address-cells = <0>;
+                        interrupt-controller;
+                        reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
+                              <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
+                        interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+                        clocks = <&cpg CPG_MOD 408>;
+                        clock-names = "clk";
+                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 408>;
+                };
+
+                pciec: pcie@fe000000 {
+                        compatible = "renesas,pcie-r8a7743",
+                                     "renesas,pcie-rcar-gen2";
+                        reg = <0 0xfe000000 0 0x80000>;
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        bus-range = <0x00 0xff>;
+                        device_type = "pci";
+                        ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
+                                  0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
+                                  0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
+                                  0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+                        /* Map all possible DDR as inbound ranges */
+                        dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
+                                      0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
+                        interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+                        #interrupt-cells = <1>;
+                        interrupt-map-mask = <0 0 0 0>;
+                        interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
+                        clock-names = "pcie", "pcie_bus";
+                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 319>;
+                        status = "disabled";
+                };
+
+                vsp@fe928000 {
+                        compatible = "renesas,vsp1";
+                        reg = <0 0xfe928000 0 0x8000>;
+                        interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 131>;
+                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 131>;
+                };
+
+                vsp@fe930000 {
+                        compatible = "renesas,vsp1";
+                        reg = <0 0xfe930000 0 0x8000>;
+                        interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 128>;
+                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 128>;
+                };
+
+                vsp@fe938000 {
+                        compatible = "renesas,vsp1";
+                        reg = <0 0xfe938000 0 0x8000>;
+                        interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 127>;
+                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 127>;
+                };
+
+                du: display@feb00000 {
+                        compatible = "renesas,du-r8a7743";
+                        reg = <0 0xfeb00000 0 0x40000>,
+                              <0 0xfeb90000 0 0x1c>;
+                        reg-names = "du", "lvds.0";
+                        interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 724>,
+                                 <&cpg CPG_MOD 723>,
+                                 <&cpg CPG_MOD 726>;
+                        clock-names = "du.0", "du.1", "lvds.0";
+                        status = "disabled";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@0 {
+                                        reg = <0>;
+                                        du_out_rgb: endpoint {
+                                        };
+                                };
+                                port@1 {
+                                        reg = <1>;
+                                        du_out_lvds0: endpoint {
+                                        };
+                                };
+                        };
+                };
+
+                prr: chipid@ff000044 {
+                        compatible = "renesas,prr";
+                        reg = <0 0xff000044 0 4>;
+                };
+
+                cmt0: timer@ffca0000 {
+                        compatible = "renesas,r8a7743-cmt0",
+                                     "renesas,rcar-gen2-cmt0";
+                        reg = <0 0xffca0000 0 0x1004>;
+                        interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 124>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 124>;
+                        status = "disabled";
+                };
+
+                cmt1: timer@e6130000 {
+                        compatible = "renesas,r8a7743-cmt1",
+                                     "renesas,rcar-gen2-cmt1";
+                        reg = <0 0xe6130000 0 0x1004>;
+                        interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 329>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                        resets = <&cpg 329>;
+                        status = "disabled";
+                };
         };
 
         thermal-zones {
diff --git a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
index ed9a8cf3fe36..8d0a392b6811 100644
--- a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
+++ b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi
@@ -29,6 +29,10 @@
         };
 };
 
+&cmt0 {
+        status = "okay";
+};
+
 &extal_clk {
         clock-frequency = <20000000>;
 };
diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index ae918e9cce21..dd49a8b48f3e 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -121,29 +121,6 @@
                 #size-cells = <2>;
                 ranges;
 
-                apmu@e6151000 {
-                        compatible = "renesas,r8a7745-apmu", "renesas,apmu";
-                        reg = <0 0xe6151000 0 0x188>;
-                        cpus = <&cpu0 &cpu1>;
-                };
-
-                gic: interrupt-controller@f1001000 {
-                        compatible = "arm,gic-400";
-                        #interrupt-cells = <3>;
-                        #address-cells = <0>;
-                        interrupt-controller;
-                        reg = <0 0xf1001000 0 0x1000>,
-                              <0 0xf1002000 0 0x2000>,
-                              <0 0xf1004000 0 0x2000>,
-                              <0 0xf1006000 0 0x2000>;
-                        interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
-                                                 IRQ_TYPE_LEVEL_HIGH)>;
-                        clocks = <&cpg CPG_MOD 408>;
-                        clock-names = "clk";
-                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
-                        resets = <&cpg 408>;
-                };
-
                 gpio0: gpio@e6050000 {
                         compatible = "renesas,gpio-r8a7745",
                                      "renesas,rcar-gen2-gpio";
@@ -249,6 +226,48 @@
                         resets = <&cpg 905>;
                 };
 
+                pfc: pin-controller@e6060000 {
+                        compatible = "renesas,pfc-r8a7745";
+                        reg = <0 0xe6060000 0 0x11c>;
+                };
+
+                tpu: pwm@e60f0000 {
+                        compatible = "renesas,tpu-r8a7745", "renesas,tpu";
+                        reg = <0 0xe60f0000 0 0x148>;
+                        clocks = <&cpg CPG_MOD 304>;
+                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 304>;
+                        #pwm-cells = <3>;
+                        status = "disabled";
+                };
+
+                cpg: clock-controller@e6150000 {
+                        compatible = "renesas,r8a7745-cpg-mssr";
+                        reg = <0 0xe6150000 0 0x1000>;
+                        clocks = <&extal_clk>, <&usb_extal_clk>;
+                        clock-names = "extal", "usb_extal";
+                        #clock-cells = <2>;
+                        #power-domain-cells = <0>;
+                        #reset-cells = <1>;
+                };
+
+                apmu@e6151000 {
+                        compatible = "renesas,r8a7745-apmu", "renesas,apmu";
+                        reg = <0 0xe6151000 0 0x188>;
+                        cpus = <&cpu0 &cpu1>;
+                };
+
+                rst: reset-controller@e6160000 {
+                        compatible = "renesas,r8a7745-rst";
+                        reg = <0 0xe6160000 0 0x100>;
+                };
+
+                sysc: system-controller@e6180000 {
+                        compatible = "renesas,r8a7745-sysc";
+                        reg = <0 0xe6180000 0 0x200>;
+                        #power-domain-cells = <1>;
+                };
+
                 irqc: interrupt-controller@e61c0000 {
                         compatible = "renesas,irqc-r8a7745", "renesas,irqc";
                         #interrupt-cells = <2>;
@@ -269,67 +288,269 @@
                         resets = <&cpg 407>;
                 };
 
-                cmt0: timer@ffca0000 {
-                        compatible = "renesas,r8a7745-cmt0",
-                                     "renesas,rcar-gen2-cmt0";
-                        reg = <0 0xffca0000 0 0x1004>;
-                        interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 124>;
-                        clock-names = "fck";
+                ipmmu_sy0: mmu@e6280000 {
+                        compatible = "renesas,ipmmu-r8a7745",
+                                     "renesas,ipmmu-vmsa";
+                        reg = <0 0xe6280000 0 0x1000>;
+                        interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+                        #iommu-cells = <1>;
+                        status = "disabled";
+                };
+
+                ipmmu_sy1: mmu@e6290000 {
+                        compatible = "renesas,ipmmu-r8a7745",
+                                     "renesas,ipmmu-vmsa";
+                        reg = <0 0xe6290000 0 0x1000>;
+                        interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+                        #iommu-cells = <1>;
+                        status = "disabled";
+                };
+
+                ipmmu_ds: mmu@e6740000 {
+                        compatible = "renesas,ipmmu-r8a7745",
+                                     "renesas,ipmmu-vmsa";
+                        reg = <0 0xe6740000 0 0x1000>;
+                        interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+                        #iommu-cells = <1>;
+                        status = "disabled";
+                };
+
+                ipmmu_mp: mmu@ec680000 {
+                        compatible = "renesas,ipmmu-r8a7745",
+                                     "renesas,ipmmu-vmsa";
+                        reg = <0 0xec680000 0 0x1000>;
+                        interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+                        #iommu-cells = <1>;
+                        status = "disabled";
+                };
+
+                ipmmu_mx: mmu@fe951000 {
+                        compatible = "renesas,ipmmu-r8a7745",
+                                     "renesas,ipmmu-vmsa";
+                        reg = <0 0xfe951000 0 0x1000>;
+                        interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+                        #iommu-cells = <1>;
+                        status = "disabled";
+                };
+
+                ipmmu_gp: mmu@e62a0000 {
+                        compatible = "renesas,ipmmu-r8a7745",
+                                     "renesas,ipmmu-vmsa";
+                        reg = <0 0xe62a0000 0 0x1000>;
+                        interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+                        #iommu-cells = <1>;
+                        status = "disabled";
+                };
+
+                icram0: sram@e63a0000 {
+                        compatible = "mmio-sram";
+                        reg = <0 0xe63a0000 0 0x12000>;
+                };
+
+                icram1: sram@e63c0000 {
+                        compatible = "mmio-sram";
+                        reg = <0 0xe63c0000 0 0x1000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0 0xe63c0000 0x1000>;
+
+                        smp-sram@0 {
+                                compatible = "renesas,smp-sram";
+                                reg = <0 0x10>;
+                        };
+                };
+
+                icram2: sram@e6300000 {
+                        compatible = "mmio-sram";
+                        reg = <0 0xe6300000 0 0x40000>;
+                };
+                i2c0: i2c@e6508000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a7745",
+                                     "renesas,rcar-gen2-i2c";
+                        reg = <0 0xe6508000 0 0x40>;
+                        interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 931>;
                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
-                        resets = <&cpg 124>;
+                        resets = <&cpg 931>;
+                        i2c-scl-internal-delay-ns = <6>;
                         status = "disabled";
                 };
 
-                cmt1: timer@e6130000 {
-                        compatible = "renesas,r8a7745-cmt1",
-                                     "renesas,rcar-gen2-cmt1";
-                        reg = <0 0xe6130000 0 0x1004>;
-                        interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 329>;
-                        clock-names = "fck";
+                i2c1: i2c@e6518000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a7745",
+                                     "renesas,rcar-gen2-i2c";
+                        reg = <0 0xe6518000 0 0x40>;
+                        interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 930>;
                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
-                        resets = <&cpg 329>;
+                        resets = <&cpg 930>;
+                        i2c-scl-internal-delay-ns = <6>;
                         status = "disabled";
                 };
 
-                cpg: clock-controller@e6150000 {
-                        compatible = "renesas,r8a7745-cpg-mssr";
-                        reg = <0 0xe6150000 0 0x1000>;
-                        clocks = <&extal_clk>, <&usb_extal_clk>;
-                        clock-names = "extal", "usb_extal";
-                        #clock-cells = <2>;
-                        #power-domain-cells = <0>;
-                        #reset-cells = <1>;
+                i2c2: i2c@e6530000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a7745",
+                                     "renesas,rcar-gen2-i2c";
+                        reg = <0 0xe6530000 0 0x40>;
+                        interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 929>;
+                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 929>;
+                        i2c-scl-internal-delay-ns = <6>;
+                        status = "disabled";
                 };
 
-                prr: chipid@ff000044 {
-                        compatible = "renesas,prr";
-                        reg = <0 0xff000044 0 4>;
+                i2c3: i2c@e6540000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a7745",
+                                     "renesas,rcar-gen2-i2c";
+                        reg = <0 0xe6540000 0 0x40>;
+                        interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 928>;
+                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 928>;
+                        i2c-scl-internal-delay-ns = <6>;
+                        status = "disabled";
                 };
 
-                rst: reset-controller@e6160000 {
-                        compatible = "renesas,r8a7745-rst";
-                        reg = <0 0xe6160000 0 0x100>;
+                i2c4: i2c@e6520000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a7745",
+                                     "renesas,rcar-gen2-i2c";
+                        reg = <0 0xe6520000 0 0x40>;
+                        interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 927>;
+                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 927>;
+                        i2c-scl-internal-delay-ns = <6>;
+                        status = "disabled";
                 };
 
-                sysc: system-controller@e6180000 {
-                        compatible = "renesas,r8a7745-sysc";
-                        reg = <0 0xe6180000 0 0x200>;
-                        #power-domain-cells = <1>;
+                i2c5: i2c@e6528000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a7745",
+                                     "renesas,rcar-gen2-i2c";
+                        reg = <0 0xe6528000 0 0x40>;
+                        interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 925>;
+                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 925>;
+                        i2c-scl-internal-delay-ns = <6>;
+                        status = "disabled";
                 };
 
-                pfc: pin-controller@e6060000 {
-                        compatible = "renesas,pfc-r8a7745";
-                        reg = <0 0xe6060000 0 0x11c>;
+                iic0: i2c@e6500000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,iic-r8a7745",
+                                     "renesas,rcar-gen2-iic",
+                                     "renesas,rmobile-iic";
+                        reg = <0 0xe6500000 0 0x425>;
+                        interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 318>;
+                        dmas = <&dmac0 0x61>, <&dmac0 0x62>,
+                               <&dmac1 0x61>, <&dmac1 0x62>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 318>;
+                        status = "disabled";
+                };
+
+                iic1: i2c@e6510000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,iic-r8a7745",
+                                     "renesas,rcar-gen2-iic",
+                                     "renesas,rmobile-iic";
+                        reg = <0 0xe6510000 0 0x425>;
+                        interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 323>;
+                        dmas = <&dmac0 0x65>, <&dmac0 0x66>,
+                               <&dmac1 0x65>, <&dmac1 0x66>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 323>;
+                        status = "disabled";
+                };
+
+                hsusb: usb@e6590000 {
+                        compatible = "renesas,usbhs-r8a7745",
+                                     "renesas,rcar-gen2-usbhs";
+                        reg = <0 0xe6590000 0 0x100>;
+                        interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 704>;
+                        dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
+                               <&usb_dmac1 0>, <&usb_dmac1 1>;
+                        dma-names = "ch0", "ch1", "ch2", "ch3";
+                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 704>;
+                        renesas,buswait = <4>;
+                        phys = <&usb0 1>;
+                        phy-names = "usb";
+                        status = "disabled";
+                };
+
+                usbphy: usb-phy@e6590100 {
+                        compatible = "renesas,usb-phy-r8a7745",
+                                     "renesas,rcar-gen2-usb-phy";
+                        reg = <0 0xe6590100 0 0x100>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&cpg CPG_MOD 704>;
+                        clock-names = "usbhs";
+                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 704>;
+                        status = "disabled";
+
+                        usb0: usb-channel@0 {
+                                reg = <0>;
+                                #phy-cells = <1>;
+                        };
+                        usb2: usb-channel@2 {
+                                reg = <2>;
+                                #phy-cells = <1>;
+                        };
+                };
+
+                usb_dmac0: dma-controller@e65a0000 {
+                        compatible = "renesas,r8a7745-usb-dmac",
+                                     "renesas,usb-dmac";
+                        reg = <0 0xe65a0000 0 0x100>;
+                        interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "ch0", "ch1";
+                        clocks = <&cpg CPG_MOD 330>;
+                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 330>;
+                        #dma-cells = <1>;
+                        dma-channels = <2>;
+                };
+
+                usb_dmac1: dma-controller@e65b0000 {
+                        compatible = "renesas,r8a7745-usb-dmac",
+                                     "renesas,usb-dmac";
+                        reg = <0 0xe65b0000 0 0x100>;
+                        interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "ch0", "ch1";
+                        clocks = <&cpg CPG_MOD 331>;
+                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 331>;
+                        #dma-cells = <1>;
+                        dma-channels = <2>;
                 };
 
                 dmac0: dma-controller@e6700000 {
@@ -353,10 +574,10 @@
                                       GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
                                       GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-names = "error",
-                                        "ch0", "ch1", "ch2", "ch3",
-                                        "ch4", "ch5", "ch6", "ch7",
-                                        "ch8", "ch9", "ch10", "ch11",
-                                        "ch12", "ch13", "ch14";
+                                          "ch0", "ch1", "ch2", "ch3",
+                                          "ch4", "ch5", "ch6", "ch7",
+                                          "ch8", "ch9", "ch10", "ch11",
+                                          "ch12", "ch13", "ch14";
                         clocks = <&cpg CPG_MOD 219>;
                         clock-names = "fck";
                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
@@ -386,75 +607,45 @@
                                       GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
                                       GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-names = "error",
-                                        "ch0", "ch1", "ch2", "ch3",
-                                        "ch4", "ch5", "ch6", "ch7",
-                                        "ch8", "ch9", "ch10", "ch11",
-                                        "ch12", "ch13", "ch14";
-                        clocks = <&cpg CPG_MOD 218>;
-                        clock-names = "fck";
-                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
-                        resets = <&cpg 218>;
-                        #dma-cells = <1>;
-                        dma-channels = <15>;
-                };
-
-                audma0: dma-controller@ec700000 {
-                        compatible = "renesas,dmac-r8a7745",
-                                     "renesas,rcar-dmac";
-                        reg = <0 0xec700000 0 0x10000>;
-                        interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
-                        interrupt-names = "error",
                                           "ch0", "ch1", "ch2", "ch3",
                                           "ch4", "ch5", "ch6", "ch7",
                                           "ch8", "ch9", "ch10", "ch11",
-                                          "ch12";
-                        clocks = <&cpg CPG_MOD 502>;
+                                          "ch12", "ch13", "ch14";
+                        clocks = <&cpg CPG_MOD 218>;
                         clock-names = "fck";
                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
-                        resets = <&cpg 502>;
+                        resets = <&cpg 218>;
                         #dma-cells = <1>;
-                        dma-channels = <13>;
+                        dma-channels = <15>;
                 };
 
-                usb_dmac0: dma-controller@e65a0000 {
-                        compatible = "renesas,r8a7745-usb-dmac",
-                                     "renesas,usb-dmac";
-                        reg = <0 0xe65a0000 0 0x100>;
-                        interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
-                        interrupt-names = "ch0", "ch1";
-                        clocks = <&cpg CPG_MOD 330>;
+                avb: ethernet@e6800000 {
+                        compatible = "renesas,etheravb-r8a7745",
+                                     "renesas,etheravb-rcar-gen2";
+                        reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
+                        interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 812>;
                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
-                        resets = <&cpg 330>;
-                        #dma-cells = <1>;
-                        dma-channels = <2>;
+                        resets = <&cpg 812>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
                 };
 
-                usb_dmac1: dma-controller@e65b0000 {
-                        compatible = "renesas,r8a7745-usb-dmac",
-                                     "renesas,usb-dmac";
-                        reg = <0 0xe65b0000 0 0x100>;
-                        interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
-                                      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-                        interrupt-names = "ch0", "ch1";
-                        clocks = <&cpg CPG_MOD 331>;
+                qspi: spi@e6b10000 {
+                        compatible = "renesas,qspi-r8a7745", "renesas,qspi";
+                        reg = <0 0xe6b10000 0 0x2c>;
+                        interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 917>;
+                        dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+                               <&dmac1 0x17>, <&dmac1 0x18>;
+                        dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
-                        resets = <&cpg 331>;
-                        #dma-cells = <1>;
-                        dma-channels = <2>;
+                        num-cs = <1>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        resets = <&cpg 917>;
+                        status = "disabled";
                 };
 
                 scifa0: serial@e6c40000 {
@@ -736,255 +927,6 @@
                         status = "disabled";
                 };
 
-                icram2: sram@e6300000 {
-                        compatible = "mmio-sram";
-                        reg = <0 0xe6300000 0 0x40000>;
-                };
-
-                icram0: sram@e63a0000 {
-                        compatible = "mmio-sram";
-                        reg = <0 0xe63a0000 0 0x12000>;
-                };
-
-                icram1: sram@e63c0000 {
-                        compatible = "mmio-sram";
-                        reg = <0 0xe63c0000 0 0x1000>;
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        ranges = <0 0 0xe63c0000 0x1000>;
-
-                        smp-sram@0 {
-                                compatible = "renesas,smp-sram";
-                                reg = <0 0x10>;
-                        };
-                };
-
-                ether: ethernet@ee700000 {
-                        compatible = "renesas,ether-r8a7745",
-                                     "renesas,rcar-gen2-ether";
-                        reg = <0 0xee700000 0 0x400>;
-                        interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 813>;
-                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
-                        resets = <&cpg 813>;
-                        phy-mode = "rmii";
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        status = "disabled";
-                };
-
-                avb: ethernet@e6800000 {
-                        compatible = "renesas,etheravb-r8a7745",
-                                     "renesas,etheravb-rcar-gen2";
-                        reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
-                        interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 812>;
-                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
-                        resets = <&cpg 812>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        status = "disabled";
-                };
-
-                i2c0: i2c@e6508000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "renesas,i2c-r8a7745",
-                                     "renesas,rcar-gen2-i2c";
-                        reg = <0 0xe6508000 0 0x40>;
-                        interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 931>;
-                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
-                        resets = <&cpg 931>;
-                        i2c-scl-internal-delay-ns = <6>;
-                        status = "disabled";
-                };
-
-                i2c1: i2c@e6518000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "renesas,i2c-r8a7745",
-                                     "renesas,rcar-gen2-i2c";
-                        reg = <0 0xe6518000 0 0x40>;
-                        interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 930>;
-                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
-                        resets = <&cpg 930>;
-                        i2c-scl-internal-delay-ns = <6>;
-                        status = "disabled";
-                };
-
-                i2c2: i2c@e6530000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "renesas,i2c-r8a7745",
-                                     "renesas,rcar-gen2-i2c";
-                        reg = <0 0xe6530000 0 0x40>;
-                        interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 929>;
-                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
-                        resets = <&cpg 929>;
-                        i2c-scl-internal-delay-ns = <6>;
-                        status = "disabled";
-                };
-
-                i2c3: i2c@e6540000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "renesas,i2c-r8a7745",
-                                     "renesas,rcar-gen2-i2c";
-                        reg = <0 0xe6540000 0 0x40>;
-                        interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 928>;
-                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
-                        resets = <&cpg 928>;
-                        i2c-scl-internal-delay-ns = <6>;
-                        status = "disabled";
-                };
-
-                i2c4: i2c@e6520000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "renesas,i2c-r8a7745",
-                                     "renesas,rcar-gen2-i2c";
-                        reg = <0 0xe6520000 0 0x40>;
-                        interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 927>;
-                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
-                        resets = <&cpg 927>;
-                        i2c-scl-internal-delay-ns = <6>;
-                        status = "disabled";
-                };
-
-                i2c5: i2c@e6528000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "renesas,i2c-r8a7745",
-                                     "renesas,rcar-gen2-i2c";
-                        reg = <0 0xe6528000 0 0x40>;
-                        interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 925>;
-                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
-                        resets = <&cpg 925>;
-                        i2c-scl-internal-delay-ns = <6>;
-                        status = "disabled";
-                };
-
-                iic0: i2c@e6500000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "renesas,iic-r8a7745",
-                                     "renesas,rcar-gen2-iic",
-                                     "renesas,rmobile-iic";
-                        reg = <0 0xe6500000 0 0x425>;
-                        interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 318>;
-                        dmas = <&dmac0 0x61>, <&dmac0 0x62>,
-                               <&dmac1 0x61>, <&dmac1 0x62>;
-                        dma-names = "tx", "rx", "tx", "rx";
-                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
-                        resets = <&cpg 318>;
-                        status = "disabled";
-                };
-
-                iic1: i2c@e6510000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "renesas,iic-r8a7745",
-                                     "renesas,rcar-gen2-iic",
-                                     "renesas,rmobile-iic";
-                        reg = <0 0xe6510000 0 0x425>;
-                        interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 323>;
-                        dmas = <&dmac0 0x65>, <&dmac0 0x66>,
-                               <&dmac1 0x65>, <&dmac1 0x66>;
-                        dma-names = "tx", "rx", "tx", "rx";
-                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
-                        resets = <&cpg 323>;
-                        status = "disabled";
-                };
-
-                mmcif0: mmc@ee200000 {
-                        compatible = "renesas,mmcif-r8a7745",
-                                     "renesas,sh-mmcif";
-                        reg = <0 0xee200000 0 0x80>;
-                        interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 315>;
-                        dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
-                               <&dmac1 0xd1>, <&dmac1 0xd2>;
-                        dma-names = "tx", "rx", "tx", "rx";
-                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
-                        resets = <&cpg 315>;
-                        reg-io-width = <4>;
-                        max-frequency = <97500000>;
-                        status = "disabled";
-                };
-
-                qspi: spi@e6b10000 {
-                        compatible = "renesas,qspi-r8a7745", "renesas,qspi";
-                        reg = <0 0xe6b10000 0 0x2c>;
-                        interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 917>;
-                        dmas = <&dmac0 0x17>, <&dmac0 0x18>,
-                               <&dmac1 0x17>, <&dmac1 0x18>;
-                        dma-names = "tx", "rx", "tx", "rx";
-                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
-                        num-cs = <1>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        resets = <&cpg 917>;
-                        status = "disabled";
-                };
-
-                vin0: video@e6ef0000 {
-                        compatible = "renesas,vin-r8a7745",
-                                     "renesas,rcar-gen2-vin";
-                        reg = <0 0xe6ef0000 0 0x1000>;
-                        interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 811>;
-                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
-                        resets = <&cpg 811>;
-                        status = "disabled";
-                };
-
-                vin1: video@e6ef1000 {
-                        compatible = "renesas,vin-r8a7745",
-                                     "renesas,rcar-gen2-vin";
-                        reg = <0 0xe6ef1000 0 0x1000>;
-                        interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 810>;
-                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
-                        resets = <&cpg 810>;
-                        status = "disabled";
-                };
-
-                du: display@feb00000 {
-                        compatible = "renesas,du-r8a7745";
-                        reg = <0 0xfeb00000 0 0x40000>;
-                        reg-names = "du";
-                        interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
-                        clock-names = "du.0", "du.1";
-                        status = "disabled";
-
-                        ports {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-
-                                port@0 {
-                                        reg = <0>;
-                                        du_out_rgb0: endpoint {
-                                        };
-                                };
-                                port@1 {
-                                        reg = <1>;
-                                        du_out_rgb1: endpoint {
-                                        };
-                                };
-                        };
-                };
-
                 msiof0: spi@e6e20000 {
                         compatible = "renesas,msiof-r8a7745",
                                      "renesas,rcar-gen2-msiof";
@@ -1103,170 +1045,6 @@
                         status = "disabled";
                 };
 
-                tpu: pwm@e60f0000 {
-                        compatible = "renesas,tpu-r8a7745", "renesas,tpu";
-                        reg = <0 0xe60f0000 0 0x148>;
-                        clocks = <&cpg CPG_MOD 304>;
-                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
-                        resets = <&cpg 304>;
-                        #pwm-cells = <3>;
-                        status = "disabled";
-                };
-
-                sdhi0: sd@ee100000 {
-                        compatible = "renesas,sdhi-r8a7745",
-                                     "renesas,rcar-gen2-sdhi";
-                        reg = <0 0xee100000 0 0x328>;
-                        interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 314>;
-                        dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
-                               <&dmac1 0xcd>, <&dmac1 0xce>;
-                        dma-names = "tx", "rx", "tx", "rx";
-                        max-frequency = <195000000>;
-                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
-                        resets = <&cpg 314>;
-                        status = "disabled";
-                };
-
-                sdhi1: sd@ee140000 {
-                        compatible = "renesas,sdhi-r8a7745",
-                                     "renesas,rcar-gen2-sdhi";
-                        reg = <0 0xee140000 0 0x100>;
-                        interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 312>;
-                        dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
-                               <&dmac1 0xc1>, <&dmac1 0xc2>;
-                        dma-names = "tx", "rx", "tx", "rx";
-                        max-frequency = <97500000>;
-                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
-                        resets = <&cpg 312>;
-                        status = "disabled";
-                };
-
-                sdhi2: sd@ee160000 {
-                        compatible = "renesas,sdhi-r8a7745",
-                                     "renesas,rcar-gen2-sdhi";
-                        reg = <0 0xee160000 0 0x100>;
-                        interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 311>;
-                        dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
-                               <&dmac1 0xd3>, <&dmac1 0xd4>;
-                        dma-names = "tx", "rx", "tx", "rx";
-                        max-frequency = <97500000>;
-                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
-                        resets = <&cpg 311>;
-                        status = "disabled";
-                };
-
-                pci0: pci@ee090000 {
-                        compatible = "renesas,pci-r8a7745",
-                                     "renesas,pci-rcar-gen2";
-                        device_type = "pci";
-                        reg = <0 0xee090000 0 0xc00>,
-                              <0 0xee080000 0 0x1100>;
-                        interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 703>;
-                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
-                        resets = <&cpg 703>;
-                        status = "disabled";
-
-                        bus-range = <0 0>;
-                        #address-cells = <3>;
-                        #size-cells = <2>;
-                        #interrupt-cells = <1>;
-                        ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
-                        interrupt-map-mask = <0xff00 0 0 0x7>;
-                        interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
-                                         0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
-                                         0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-
-                        usb@1,0 {
-                                reg = <0x800 0 0 0 0>;
-                                phys = <&usb0 0>;
-                                phy-names = "usb";
-                        };
-
-                        usb@2,0 {
-                                reg = <0x1000 0 0 0 0>;
-                                phys = <&usb0 0>;
-                                phy-names = "usb";
-                        };
-                };
-
-                pci1: pci@ee0d0000 {
-                        compatible = "renesas,pci-r8a7745",
-                                     "renesas,pci-rcar-gen2";
-                        device_type = "pci";
-                        reg = <0 0xee0d0000 0 0xc00>,
-                              <0 0xee0c0000 0 0x1100>;
-                        interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 703>;
-                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
-                        resets = <&cpg 703>;
-                        status = "disabled";
-
-                        bus-range = <1 1>;
-                        #address-cells = <3>;
-                        #size-cells = <2>;
-                        #interrupt-cells = <1>;
-                        ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
-                        interrupt-map-mask = <0xff00 0 0 0x7>;
-                        interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
-                                         0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
-                                         0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
-
-                        usb@1,0 {
-                                reg = <0x10800 0 0 0 0>;
-                                phys = <&usb2 0>;
-                                phy-names = "usb";
-                        };
-
-                        usb@2,0 {
-                                reg = <0x11000 0 0 0 0>;
-                                phys = <&usb2 0>;
-                                phy-names = "usb";
-                        };
-                };
-
-                hsusb: usb@e6590000 {
-                        compatible = "renesas,usbhs-r8a7745",
-                                     "renesas,rcar-gen2-usbhs";
-                        reg = <0 0xe6590000 0 0x100>;
-                        interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 704>;
-                        dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
-                               <&usb_dmac1 0>, <&usb_dmac1 1>;
-                        dma-names = "ch0", "ch1", "ch2", "ch3";
-                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
-                        resets = <&cpg 704>;
-                        renesas,buswait = <4>;
-                        phys = <&usb0 1>;
-                        phy-names = "usb";
-                        status = "disabled";
-                };
-
-                usbphy: usb-phy@e6590100 {
-                        compatible = "renesas,usb-phy-r8a7745",
-                                     "renesas,rcar-gen2-usb-phy";
-                        reg = <0 0xe6590100 0 0x100>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        clocks = <&cpg CPG_MOD 704>;
-                        clock-names = "usbhs";
-                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
-                        resets = <&cpg 704>;
-                        status = "disabled";
-
-                        usb0: usb-channel@0 {
-                                reg = <0>;
-                                #phy-cells = <1>;
-                        };
-                        usb2: usb-channel@2 {
-                                reg = <2>;
-                                #phy-cells = <1>;
-                        };
-                };
-
                 can0: can@e6e80000 {
                         compatible = "renesas,can-r8a7745",
                                      "renesas,rcar-gen2-can";
@@ -1295,6 +1073,28 @@
                         status = "disabled";
                 };
 
+                vin0: video@e6ef0000 {
+                        compatible = "renesas,vin-r8a7745",
+                                     "renesas,rcar-gen2-vin";
+                        reg = <0 0xe6ef0000 0 0x1000>;
+                        interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 811>;
+                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 811>;
+                        status = "disabled";
+                };
+
+                vin1: video@e6ef1000 {
+                        compatible = "renesas,vin-r8a7745",
+                                     "renesas,rcar-gen2-vin";
+                        reg = <0 0xe6ef1000 0 0x1000>;
+                        interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 810>;
+                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 810>;
+                        status = "disabled";
+                };
+
                 rcar_sound: sound@ec500000 {
                         /*
                          * #sound-dai-cells is required
@@ -1474,6 +1274,278 @@
                                 };
                         };
                 };
+
+                audma0: dma-controller@ec700000 {
+                        compatible = "renesas,dmac-r8a7745",
+                                     "renesas,rcar-dmac";
+                        reg = <0 0xec700000 0 0x10000>;
+                        interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "error",
+                                          "ch0", "ch1", "ch2", "ch3",
+                                          "ch4", "ch5", "ch6", "ch7",
+                                          "ch8", "ch9", "ch10", "ch11",
+                                          "ch12";
+                        clocks = <&cpg CPG_MOD 502>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 502>;
+                        #dma-cells = <1>;
+                        dma-channels = <13>;
+                };
+
+                pci0: pci@ee090000 {
+                        compatible = "renesas,pci-r8a7745",
+                                     "renesas,pci-rcar-gen2";
+                        device_type = "pci";
+                        reg = <0 0xee090000 0 0xc00>,
+                              <0 0xee080000 0 0x1100>;
+                        interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 703>;
+                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 703>;
+                        status = "disabled";
+
+                        bus-range = <0 0>;
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        #interrupt-cells = <1>;
+                        ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
+                        interrupt-map-mask = <0xff00 0 0 0x7>;
+                        interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+                                         0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+                                         0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+
+                        usb@1,0 {
+                                reg = <0x800 0 0 0 0>;
+                                phys = <&usb0 0>;
+                                phy-names = "usb";
+                        };
+
+                        usb@2,0 {
+                                reg = <0x1000 0 0 0 0>;
+                                phys = <&usb0 0>;
+                                phy-names = "usb";
+                        };
+                };
+
+                pci1: pci@ee0d0000 {
+                        compatible = "renesas,pci-r8a7745",
+                                     "renesas,pci-rcar-gen2";
+                        device_type = "pci";
+                        reg = <0 0xee0d0000 0 0xc00>,
+                              <0 0xee0c0000 0 0x1100>;
+                        interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 703>;
+                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 703>;
+                        status = "disabled";
+
+                        bus-range = <1 1>;
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        #interrupt-cells = <1>;
+                        ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
+                        interrupt-map-mask = <0xff00 0 0 0x7>;
+                        interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+                                         0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+                                         0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+
+                        usb@1,0 {
+                                reg = <0x10800 0 0 0 0>;
+                                phys = <&usb2 0>;
+                                phy-names = "usb";
+                        };
+
+                        usb@2,0 {
+                                reg = <0x11000 0 0 0 0>;
+                                phys = <&usb2 0>;
+                                phy-names = "usb";
+                        };
+                };
+
+                sdhi0: sd@ee100000 {
+                        compatible = "renesas,sdhi-r8a7745",
+                                     "renesas,rcar-gen2-sdhi";
+                        reg = <0 0xee100000 0 0x328>;
+                        interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 314>;
+                        dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+                               <&dmac1 0xcd>, <&dmac1 0xce>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        max-frequency = <195000000>;
+                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 314>;
+                        status = "disabled";
+                };
+
+                sdhi1: sd@ee140000 {
+                        compatible = "renesas,sdhi-r8a7745",
+                                     "renesas,rcar-gen2-sdhi";
+                        reg = <0 0xee140000 0 0x100>;
+                        interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 312>;
+                        dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+                               <&dmac1 0xc1>, <&dmac1 0xc2>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        max-frequency = <97500000>;
+                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 312>;
+                        status = "disabled";
+                };
+
+                sdhi2: sd@ee160000 {
+                        compatible = "renesas,sdhi-r8a7745",
+                                     "renesas,rcar-gen2-sdhi";
+                        reg = <0 0xee160000 0 0x100>;
+                        interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 311>;
+                        dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+                               <&dmac1 0xd3>, <&dmac1 0xd4>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        max-frequency = <97500000>;
+                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 311>;
+                        status = "disabled";
+                };
+
+                mmcif0: mmc@ee200000 {
+                        compatible = "renesas,mmcif-r8a7745",
+                                     "renesas,sh-mmcif";
+                        reg = <0 0xee200000 0 0x80>;
+                        interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 315>;
+                        dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+                               <&dmac1 0xd1>, <&dmac1 0xd2>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 315>;
+                        reg-io-width = <4>;
+                        max-frequency = <97500000>;
+                        status = "disabled";
+                };
+
+                ether: ethernet@ee700000 {
+                        compatible = "renesas,ether-r8a7745",
+                                     "renesas,rcar-gen2-ether";
+                        reg = <0 0xee700000 0 0x400>;
+                        interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 813>;
+                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 813>;
+                        phy-mode = "rmii";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                gic: interrupt-controller@f1001000 {
+                        compatible = "arm,gic-400";
+                        #interrupt-cells = <3>;
+                        #address-cells = <0>;
+                        interrupt-controller;
+                        reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
+                              <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
+                        interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+                        clocks = <&cpg CPG_MOD 408>;
+                        clock-names = "clk";
+                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 408>;
+                };
+
+                vsp@fe928000 {
+                        compatible = "renesas,vsp1";
+                        reg = <0 0xfe928000 0 0x8000>;
+                        interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 131>;
+                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 131>;
+                };
+
+                vsp@fe930000 {
+                        compatible = "renesas,vsp1";
+                        reg = <0 0xfe930000 0 0x8000>;
+                        interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 128>;
+                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 128>;
+                };
+
+                du: display@feb00000 {
+                        compatible = "renesas,du-r8a7745";
+                        reg = <0 0xfeb00000 0 0x40000>;
+                        reg-names = "du";
+                        interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
+                        clock-names = "du.0", "du.1";
+                        status = "disabled";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@0 {
+                                        reg = <0>;
+                                        du_out_rgb0: endpoint {
+                                        };
+                                };
+                                port@1 {
+                                        reg = <1>;
+                                        du_out_rgb1: endpoint {
+                                        };
+                                };
+                        };
+                };
+
+                prr: chipid@ff000044 {
+                        compatible = "renesas,prr";
+                        reg = <0 0xff000044 0 4>;
+                };
+
+                cmt0: timer@ffca0000 {
+                        compatible = "renesas,r8a7745-cmt0",
+                                     "renesas,rcar-gen2-cmt0";
+                        reg = <0 0xffca0000 0 0x1004>;
+                        interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 124>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 124>;
+                        status = "disabled";
+                };
+
+                cmt1: timer@e6130000 {
+                        compatible = "renesas,r8a7745-cmt1",
+                                     "renesas,rcar-gen2-cmt1";
+                        reg = <0 0xe6130000 0 0x1004>;
+                        interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 329>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+                        resets = <&cpg 329>;
+                        status = "disabled";
+                };
         };
 
         timer {
diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
index 9412a86f9b30..4b9006bac3cb 100644
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -42,6 +42,19 @@
                 regulator-always-on;
         };
 
+        vccq_sdhi0: regulator-vccq-sdhi0 {
+                compatible = "regulator-gpio";
+
+                regulator-name = "SDHI0 VccQ";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <3300000>;
+
+                gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
+                gpios-states = <1>;
+                states = <3300000 1
+                          1800000 0>;
+        };
+
         ethernet@18000000 {
                 compatible = "smsc,lan9220", "smsc,lan9115";
                 reg = <0x18000000 0x100>;
@@ -243,6 +256,7 @@
         pinctrl-names = "default";
 
         vmmc-supply = <&fixedregulator3v3>;
+        vqmmc-supply = <&vccq_sdhi0>;
         bus-width = <4>;
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index f2ea632381e7..063fdb65dc60 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -51,8 +51,11 @@
                 serial0 = &scif0;
                 serial1 = &scifa1;
                 i2c8 = &gpioi2c1;
+                i2c9 = &gpioi2c2;
                 i2c10 = &i2cexio0;
                 i2c11 = &i2cexio1;
+                i2c12 = &i2chdmi;
+                i2c13 = &i2cpwr;
         };
 
         chosen {
@@ -244,6 +247,12 @@
                 };
         };
 
+        cec_clock: cec-clock {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <12000000>;
+        };
+
         hdmi-out {
                 compatible = "hdmi-connector";
                 type = "a";
@@ -272,8 +281,18 @@
                 #size-cells = <0>;
                 compatible = "i2c-gpio";
                 status = "disabled";
-                sda-gpios = <&gpio1 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
                 scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+                sda-gpios = <&gpio1 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+                i2c-gpio,delay-us = <5>;
+        };
+
+        gpioi2c2: i2c-9 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "i2c-gpio";
+                status = "disabled";
+                scl-gpios = <&gpio5 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+                sda-gpios = <&gpio5 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
                 i2c-gpio,delay-us = <5>;
         };
 
@@ -308,6 +327,138 @@
                 #address-cells = <1>;
                 #size-cells = <0>;
         };
+
+        /*
+         * IIC2 and I2C2 may be switched using pinmux.
+         * A fallback to GPIO is also provided.
+         */
+        i2chdmi: i2c-12 {
+                compatible = "i2c-demux-pinctrl";
+                i2c-parent = <&iic2>, <&i2c2>, <&gpioi2c2>;
+                i2c-bus-name = "i2c-hdmi";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                ak4643: codec@12 {
+                        compatible = "asahi-kasei,ak4643";
+                        #sound-dai-cells = <0>;
+                        reg = <0x12>;
+                };
+
+                composite-in@20 {
+                        compatible = "adi,adv7180";
+                        reg = <0x20>;
+                        remote = <&vin1>;
+
+                        port {
+                                adv7180: endpoint {
+                                        bus-width = <8>;
+                                        remote-endpoint = <&vin1ep0>;
+                                };
+                        };
+                };
+
+                hdmi@39 {
+                        compatible = "adi,adv7511w";
+                        reg = <0x39>;
+                        interrupt-parent = <&gpio1>;
+                        interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
+                        clocks = <&cec_clock>;
+                        clock-names = "cec";
+
+                        adi,input-depth = <8>;
+                        adi,input-colorspace = "rgb";
+                        adi,input-clock = "1x";
+                        adi,input-style = <1>;
+                        adi,input-justification = "evenly";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@0 {
+                                        reg = <0>;
+                                        adv7511_in: endpoint {
+                                                remote-endpoint = <&du_out_lvds0>;
+                                        };
+                                };
+
+                                port@1 {
+                                        reg = <1>;
+                                        adv7511_out: endpoint {
+                                                remote-endpoint = <&hdmi_con_out>;
+                                        };
+                                };
+                        };
+                };
+
+                hdmi-in@4c {
+                        compatible = "adi,adv7612";
+                        reg = <0x4c>;
+                        interrupt-parent = <&gpio1>;
+                        interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
+                        default-input = <0>;
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@0 {
+                                        reg = <0>;
+                                        adv7612_in: endpoint {
+                                                remote-endpoint = <&hdmi_con_in>;
+                                        };
+                                };
+
+                                port@2 {
+                                        reg = <2>;
+                                        adv7612_out: endpoint {
+                                                remote-endpoint = <&vin0ep2>;
+                                        };
+                                };
+                        };
+                };
+        };
+
+        /*
+         * IIC3 and I2C3 may be switched using pinmux.
+         * IIC3/I2C3 does not appear to support fallback to GPIO.
+         */
+        i2cpwr: i2c-13 {
+                compatible = "i2c-demux-pinctrl";
+                i2c-parent = <&iic3>, <&i2c3>;
+                i2c-bus-name = "i2c-pwr";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                pmic@58 {
+                        compatible = "dlg,da9063";
+                        reg = <0x58>;
+                        interrupt-parent = <&irqc0>;
+                        interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+                        interrupt-controller;
+
+                        rtc {
+                                compatible = "dlg,da9063-rtc";
+                        };
+
+                        wdt {
+                                compatible = "dlg,da9063-watchdog";
+                        };
+                };
+
+                vdd_dvfs: regulator@68 {
+                        compatible = "dlg,da9210";
+                        reg = <0x68>;
+                        interrupt-parent = <&irqc0>;
+                        interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+
+                        regulator-min-microvolt = <1000000>;
+                        regulator-max-microvolt = <1000000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+        };
 };
 
 &du {
@@ -437,11 +588,21 @@
                 function = "iic1";
         };
 
+        i2c2_pins: i2c2 {
+                groups = "i2c2";
+                function = "i2c2";
+        };
+
         iic2_pins: iic2 {
                 groups = "iic2";
                 function = "iic2";
         };
 
+        i2c3_pins: i2c3 {
+                groups = "i2c3";
+                function = "i2c3";
+        };
+
         iic3_pins: iic3 {
                 groups = "iic3";
                 function = "iic3";
@@ -643,124 +804,28 @@
         pinctrl-names = "i2c-exio1";
 };
 
-&iic2   {
-        status = "okay";
-        pinctrl-0 = <&iic2_pins>;
-        pinctrl-names = "default";
+&i2c2   {
+        pinctrl-0 = <&i2c2_pins>;
+        pinctrl-names = "i2c-hdmi";
 
         clock-frequency = <100000>;
+};
 
-        ak4643: codec@12 {
-                compatible = "asahi-kasei,ak4643";
-                #sound-dai-cells = <0>;
-                reg = <0x12>;
-        };
-
-        composite-in@20 {
-                compatible = "adi,adv7180";
-                reg = <0x20>;
-                remote = <&vin1>;
-
-                port {
-                        adv7180: endpoint {
-                                bus-width = <8>;
-                                remote-endpoint = <&vin1ep0>;
-                        };
-                };
-        };
-
-        hdmi@39 {
-                compatible = "adi,adv7511w";
-                reg = <0x39>;
-                interrupt-parent = <&gpio1>;
-                interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
-
-                adi,input-depth = <8>;
-                adi,input-colorspace = "rgb";
-                adi,input-clock = "1x";
-                adi,input-style = <1>;
-                adi,input-justification = "evenly";
-
-                ports {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-
-                        port@0 {
-                                reg = <0>;
-                                adv7511_in: endpoint {
-                                        remote-endpoint = <&du_out_lvds0>;
-                                };
-                        };
-
-                        port@1 {
-                                reg = <1>;
-                                adv7511_out: endpoint {
-                                        remote-endpoint = <&hdmi_con_out>;
-                                };
-                        };
-                };
-        };
-
-        hdmi-in@4c {
-                compatible = "adi,adv7612";
-                reg = <0x4c>;
-                interrupt-parent = <&gpio1>;
-                interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
-                default-input = <0>;
-
-                ports {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
+&iic2   {
+        pinctrl-0 = <&iic2_pins>;
+        pinctrl-names = "i2c-hdmi";
 
-                        port@0 {
-                                reg = <0>;
-                                adv7612_in: endpoint {
-                                        remote-endpoint = <&hdmi_con_in>;
-                                };
-                        };
+        clock-frequency = <100000>;
+};
 
-                        port@2 {
-                                reg = <2>;
-                                adv7612_out: endpoint {
-                                        remote-endpoint = <&vin0ep2>;
-                                };
-                        };
-                };
-        };
+&i2c3   {
+        pinctrl-0 = <&i2c3_pins>;
+        pinctrl-names = "i2c-pwr";
 };
 
-&iic3 {
-        pinctrl-names = "default";
+&iic3   {
         pinctrl-0 = <&iic3_pins>;
-        status = "okay";
-
-        pmic@58 {
-                compatible = "dlg,da9063";
-                reg = <0x58>;
-                interrupt-parent = <&irqc0>;
-                interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
-                interrupt-controller;
-
-                rtc {
-                        compatible = "dlg,da9063-rtc";
-                };
-
-                wdt {
-                        compatible = "dlg,da9063-watchdog";
-                };
-        };
-
-        vdd_dvfs: regulator@68 {
-                compatible = "dlg,da9210";
-                reg = <0x68>;
-                interrupt-parent = <&irqc0>;
-                interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
-
-                regulator-min-microvolt = <1000000>;
-                regulator-max-microvolt = <1000000>;
-                regulator-boot-on;
-                regulator-always-on;
-        };
+        pinctrl-names = "i2c-pwr";
 };
 
 &pci0 {
diff --git a/arch/arm/boot/dts/r8a7790-stout.dts b/arch/arm/boot/dts/r8a7790-stout.dts
new file mode 100644
index 000000000000..a13a92c26645
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7790-stout.dts
@@ -0,0 +1,363 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the Stout board
+ *
+ * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
+ */
+
+/dts-v1/;
+#include "r8a7790.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+        model = "Stout";
+        compatible = "renesas,stout", "renesas,r8a7790";
+
+        aliases {
+                serial0 = &scifa0;
+        };
+
+        chosen {
+                bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+                stdout-path = "serial0:115200n8";
+        };
+
+        memory@40000000 {
+                device_type = "memory";
+                reg = <0 0x40000000 0 0x40000000>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                led1 {
+                        gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+                };
+                led2 {
+                        gpios = <&gpio4 23 GPIO_ACTIVE_LOW>;
+                };
+                led3 {
+                        gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
+                };
+                led5 {
+                        gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
+                };
+        };
+
+        fixedregulator3v3: regulator-3v3 {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-3.3V";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-boot-on;
+                regulator-always-on;
+        };
+
+        vcc_sdhi0: regulator-vcc-sdhi0 {
+                compatible = "regulator-fixed";
+
+                regulator-name = "SDHI0 Vcc";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+
+                gpio = <&gpio5 24 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+        };
+
+        hdmi-out {
+                compatible = "hdmi-connector";
+                type = "a";
+
+                port {
+                        hdmi_con_out: endpoint {
+                                remote-endpoint = <&adv7511_out>;
+                        };
+                };
+        };
+
+        osc1_clk: osc1-clock {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <148500000>;
+        };
+
+        osc4_clk: osc4-clock {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <12000000>;
+        };
+};
+
+&du {
+        pinctrl-0 = <&du_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+
+        clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>,
+                 <&cpg CPG_MOD 726>, <&cpg CPG_MOD 725>,
+                 <&osc1_clk>;
+        clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1", "dclkin.0";
+
+        ports {
+                port@0 {
+                        endpoint {
+                                remote-endpoint = <&adv7511_in>;
+                        };
+                };
+                port@1 {
+                        lvds_connector0: endpoint {
+                        };
+                };
+                port@2 {
+                        lvds_connector1: endpoint {
+                        };
+                };
+        };
+};
+
+&extal_clk {
+        clock-frequency = <20000000>;
+};
+
+&pfc {
+
+        pinctrl-0 = <&scif_clk_pins>;
+        pinctrl-names = "default";
+
+        du_pins: du {
+                groups = "du_rgb888", "du_sync_1", "du_clk_out_0";
+                function = "du";
+        };
+
+        scifa0_pins: scifa0 {
+                groups = "scifa0_data_b";
+                function = "scifa0";
+        };
+
+        scif_clk_pins: scif_clk {
+                groups = "scif_clk";
+                function = "scif_clk";
+        };
+
+        ether_pins: ether {
+                groups = "eth_link", "eth_mdio", "eth_rmii";
+                function = "eth";
+        };
+
+        phy1_pins: phy1 {
+                groups = "intc_irq1";
+                function = "intc";
+        };
+
+        sdhi0_pins: sd0 {
+                groups = "sdhi0_data4", "sdhi0_ctrl";
+                function = "sdhi0";
+                power-source = <3300>;
+        };
+
+        qspi_pins: qspi {
+                groups = "qspi_ctrl", "qspi_data4";
+                function = "qspi";
+        };
+
+        iic2_pins: iic2 {
+                groups = "iic2_b";
+                function = "iic2";
+        };
+
+        iic3_pins: iic3 {
+                groups = "iic3";
+                function = "iic3";
+        };
+
+        usb0_pins: usb0 {
+                groups = "usb0";
+                function = "usb0";
+        };
+};
+
+&ether {
+        pinctrl-0 = <&ether_pins &phy1_pins>;
+        pinctrl-names = "default";
+
+        phy-handle = <&phy1>;
+        renesas,ether-link-active-low;
+        status = "okay";
+
+        phy1: ethernet-phy@1 {
+                reg = <1>;
+                interrupt-parent = <&irqc0>;
+                interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+                micrel,led-mode = <1>;
+        };
+};
+
+&cmt0 {
+        status = "okay";
+};
+
+&qspi {
+        pinctrl-0 = <&qspi_pins>;
+        pinctrl-names = "default";
+
+        status = "okay";
+
+        flash: flash@0 {
+                compatible = "spansion,s25fl512s", "jedec,spi-nor";
+                reg = <0>;
+                spi-max-frequency = <30000000>;
+                spi-tx-bus-width = <4>;
+                spi-rx-bus-width = <4>;
+                spi-cpha;
+                spi-cpol;
+                m25p,fast-read;
+
+                partitions {
+                        compatible = "fixed-partitions";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        partition@0 {
+                                label = "loader";
+                                reg = <0x00000000 0x00080000>;
+                                read-only;
+                        };
+                        partition@80000 {
+                                label = "uboot";
+                                reg = <0x00080000 0x00040000>;
+                                read-only;
+                        };
+                        partition@c0000 {
+                                label = "uboot-env";
+                                reg = <0x000c0000 0x00040000>;
+                                read-only;
+                        };
+                        partition@100000 {
+                                label = "flash";
+                                reg = <0x00100000 0x03f00000>;
+                        };
+                };
+        };
+};
+
+&scifa0 {
+        pinctrl-0 = <&scifa0_pins>;
+        pinctrl-names = "default";
+
+        status = "okay";
+};
+
+&scif_clk {
+        clock-frequency = <14745600>;
+};
+
+&sdhi0 {
+        pinctrl-0 = <&sdhi0_pins>;
+        pinctrl-names = "default";
+
+        vmmc-supply = <&vcc_sdhi0>;
+        cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
+        status = "okay";
+};
+
+&cpu0 {
+        cpu0-supply = <&vdd_dvfs>;
+};
+
+&iic2   {
+        status = "okay";
+        pinctrl-0 = <&iic2_pins>;
+        pinctrl-names = "default";
+
+        clock-frequency = <100000>;
+
+        hdmi@39 {
+                compatible = "adi,adv7511w";
+                reg = <0x39>;
+                interrupt-parent = <&gpio1>;
+                interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
+                clocks = <&osc4_clk>;
+                clock-names = "cec";
+
+                adi,input-depth = <8>;
+                adi,input-colorspace = "rgb";
+                adi,input-clock = "1x";
+                adi,input-style = <1>;
+                adi,input-justification = "evenly";
+
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@0 {
+                                reg = <0>;
+                                adv7511_in: endpoint {
+                                        remote-endpoint = <&du_out_rgb>;
+                                };
+                        };
+
+                        port@1 {
+                                reg = <1>;
+                                adv7511_out: endpoint {
+                                        remote-endpoint = <&hdmi_con_out>;
+                                };
+                        };
+                };
+        };
+};
+
+&iic3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&iic3_pins>;
+        status = "okay";
+
+        pmic@58 {
+                compatible = "dlg,da9063";
+                reg = <0x58>;
+                interrupt-parent = <&irqc0>;
+                interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+                interrupt-controller;
+
+                rtc {
+                        compatible = "dlg,da9063-rtc";
+                };
+
+                wdt {
+                        compatible = "dlg,da9063-watchdog";
+                };
+        };
+
+        vdd_dvfs: regulator@68 {
+                compatible = "dlg,da9210";
+                reg = <0x68>;
+                interrupt-parent = <&irqc0>;
+                interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+
+                regulator-min-microvolt = <1000000>;
+                regulator-max-microvolt = <1000000>;
+                regulator-boot-on;
+                regulator-always-on;
+        };
+
+        vdd: regulator@70 {
+                compatible = "dlg,da9210";
+                reg = <0x70>;
+                interrupt-parent = <&irqc0>;
+                interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+
+                regulator-min-microvolt = <1000000>;
+                regulator-max-microvolt = <1000000>;
+                regulator-boot-on;
+                regulator-always-on;
+        };
+};
+
+&pci0 {
+        status = "okay";
+        pinctrl-0 = <&usb0_pins>;
+        pinctrl-names = "default";
+};
+
+&usbphy {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index ed9a68538a55..e4367cecad18 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -17,7 +17,6 @@
 
 / {
         compatible = "renesas,r8a7790";
-        interrupt-parent = <&gic>;
         #address-cells = <2>;
         #size-cells = <2>;
 
@@ -41,6 +40,35 @@
                 vin3 = &vin3;
         };
 
+        /*
+         * The external audio clocks are configured as 0 Hz fixed frequency
+         * clocks by default.
+         * Boards that provide audio clocks should override them.
+         */
+        audio_clk_a: audio_clk_a {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+        audio_clk_b: audio_clk_b {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+        audio_clk_c: audio_clk_c {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+
+        /* External CAN clock */
+        can_clk: can {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                /* This value must be overridden by the board. */
+                clock-frequency = <0>;
+        };
+
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -159,1510 +187,1553 @@
                 };
         };
 
-        thermal-zones {
-                cpu_thermal: cpu-thermal {
-                        polling-delay-passive   = <0>;
-                        polling-delay           = <0>;
-
-                        thermal-sensors = <&thermal>;
-
-                        trips {
-                                cpu-crit {
-                                        temperature     = <95000>;
-                                        hysteresis      = <0>;
-                                        type            = "critical";
-                                };
-                        };
-                        cooling-maps {
-                        };
-                };
+        /* External root clock */
+        extal_clk: extal {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                /* This value must be overridden by the board. */
+                clock-frequency = <0>;
         };
 
-        apmu@e6151000 {
-                compatible = "renesas,r8a7790-apmu", "renesas,apmu";
-                reg = <0 0xe6151000 0 0x188>;
-                cpus = <&cpu4 &cpu5 &cpu6 &cpu7>;
+        /* External PCIe clock - can be overridden by the board */
+        pcie_bus_clk: pcie_bus {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
         };
 
-        apmu@e6152000 {
-                compatible = "renesas,r8a7790-apmu", "renesas,apmu";
-                reg = <0 0xe6152000 0 0x188>;
-                cpus = <&cpu0 &cpu1 &cpu2 &cpu3>;
+        /* External SCIF clock */
+        scif_clk: scif {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                /* This value must be overridden by the board. */
+                clock-frequency = <0>;
         };
 
-        gic: interrupt-controller@f1001000 {
-                compatible = "arm,gic-400";
-                #interrupt-cells = <3>;
-                #address-cells = <0>;
-                interrupt-controller;
-                reg = <0 0xf1001000 0 0x1000>,
-                        <0 0xf1002000 0 0x2000>,
-                        <0 0xf1004000 0 0x2000>,
-                        <0 0xf1006000 0 0x2000>;
-                interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-                clocks = <&cpg CPG_MOD 408>;
-                clock-names = "clk";
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 408>;
-        };
+        soc {
+                compatible = "simple-bus";
+                interrupt-parent = <&gic>;
 
-        gpio0: gpio@e6050000 {
-                compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
-                reg = <0 0xe6050000 0 0x50>;
-                interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
-                #gpio-cells = <2>;
-                gpio-controller;
-                gpio-ranges = <&pfc 0 0 32>;
-                #interrupt-cells = <2>;
-                interrupt-controller;
-                clocks = <&cpg CPG_MOD 912>;
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 912>;
-        };
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
+
+                gpio0: gpio@e6050000 {
+                        compatible = "renesas,gpio-r8a7790",
+                                     "renesas,rcar-gen2-gpio";
+                        reg = <0 0xe6050000 0 0x50>;
+                        interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 0 32>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 912>;
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 912>;
+                };
 
-        gpio1: gpio@e6051000 {
-                compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
-                reg = <0 0xe6051000 0 0x50>;
-                interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
-                #gpio-cells = <2>;
-                gpio-controller;
-                gpio-ranges = <&pfc 0 32 30>;
-                #interrupt-cells = <2>;
-                interrupt-controller;
-                clocks = <&cpg CPG_MOD 911>;
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 911>;
-        };
+                gpio1: gpio@e6051000 {
+                        compatible = "renesas,gpio-r8a7790",
+                                     "renesas,rcar-gen2-gpio";
+                        reg = <0 0xe6051000 0 0x50>;
+                        interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 32 30>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 911>;
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 911>;
+                };
 
-        gpio2: gpio@e6052000 {
-                compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
-                reg = <0 0xe6052000 0 0x50>;
-                interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
-                #gpio-cells = <2>;
-                gpio-controller;
-                gpio-ranges = <&pfc 0 64 30>;
-                #interrupt-cells = <2>;
-                interrupt-controller;
-                clocks = <&cpg CPG_MOD 910>;
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 910>;
-        };
+                gpio2: gpio@e6052000 {
+                        compatible = "renesas,gpio-r8a7790",
+                                     "renesas,rcar-gen2-gpio";
+                        reg = <0 0xe6052000 0 0x50>;
+                        interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 64 30>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 910>;
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 910>;
+                };
 
-        gpio3: gpio@e6053000 {
-                compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
-                reg = <0 0xe6053000 0 0x50>;
-                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
-                #gpio-cells = <2>;
-                gpio-controller;
-                gpio-ranges = <&pfc 0 96 32>;
-                #interrupt-cells = <2>;
-                interrupt-controller;
-                clocks = <&cpg CPG_MOD 909>;
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 909>;
-        };
+                gpio3: gpio@e6053000 {
+                        compatible = "renesas,gpio-r8a7790",
+                                     "renesas,rcar-gen2-gpio";
+                        reg = <0 0xe6053000 0 0x50>;
+                        interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 96 32>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 909>;
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 909>;
+                };
 
-        gpio4: gpio@e6054000 {
-                compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
-                reg = <0 0xe6054000 0 0x50>;
-                interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
-                #gpio-cells = <2>;
-                gpio-controller;
-                gpio-ranges = <&pfc 0 128 32>;
-                #interrupt-cells = <2>;
-                interrupt-controller;
-                clocks = <&cpg CPG_MOD 908>;
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 908>;
-        };
+                gpio4: gpio@e6054000 {
+                        compatible = "renesas,gpio-r8a7790",
+                                     "renesas,rcar-gen2-gpio";
+                        reg = <0 0xe6054000 0 0x50>;
+                        interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 128 32>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 908>;
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 908>;
+                };
 
-        gpio5: gpio@e6055000 {
-                compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio";
-                reg = <0 0xe6055000 0 0x50>;
-                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
-                #gpio-cells = <2>;
-                gpio-controller;
-                gpio-ranges = <&pfc 0 160 32>;
-                #interrupt-cells = <2>;
-                interrupt-controller;
-                clocks = <&cpg CPG_MOD 907>;
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 907>;
-        };
+                gpio5: gpio@e6055000 {
+                        compatible = "renesas,gpio-r8a7790",
+                                     "renesas,rcar-gen2-gpio";
+                        reg = <0 0xe6055000 0 0x50>;
+                        interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 160 32>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 907>;
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 907>;
+                };
 
-        thermal: thermal@e61f0000 {
-                compatible =    "renesas,thermal-r8a7790",
-                                "renesas,rcar-gen2-thermal",
-                                "renesas,rcar-thermal";
-                reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
-                interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 522>;
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 522>;
-                #thermal-sensor-cells = <0>;
-        };
+                pfc: pin-controller@e6060000 {
+                        compatible = "renesas,pfc-r8a7790";
+                        reg = <0 0xe6060000 0 0x250>;
+                };
 
-        timer {
-                compatible = "arm,armv7-timer";
-                interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-                             <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-                             <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-                             <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
-        };
+                cpg: clock-controller@e6150000 {
+                        compatible = "renesas,r8a7790-cpg-mssr";
+                        reg = <0 0xe6150000 0 0x1000>;
+                        clocks = <&extal_clk>, <&usb_extal_clk>;
+                        clock-names = "extal", "usb_extal";
+                        #clock-cells = <2>;
+                        #power-domain-cells = <0>;
+                        #reset-cells = <1>;
+                };
 
-        cmt0: timer@ffca0000 {
-                compatible = "renesas,r8a7790-cmt0", "renesas,rcar-gen2-cmt0";
-                reg = <0 0xffca0000 0 0x1004>;
-                interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 124>;
-                clock-names = "fck";
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 124>;
-
-                status = "disabled";
-        };
+                apmu@e6151000 {
+                        compatible = "renesas,r8a7790-apmu", "renesas,apmu";
+                        reg = <0 0xe6151000 0 0x188>;
+                        cpus = <&cpu4 &cpu5 &cpu6 &cpu7>;
+                };
 
-        cmt1: timer@e6130000 {
-                compatible = "renesas,r8a7790-cmt1", "renesas,rcar-gen2-cmt1";
-                reg = <0 0xe6130000 0 0x1004>;
-                interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 329>;
-                clock-names = "fck";
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 329>;
-
-                status = "disabled";
-        };
+                apmu@e6152000 {
+                        compatible = "renesas,r8a7790-apmu", "renesas,apmu";
+                        reg = <0 0xe6152000 0 0x188>;
+                        cpus = <&cpu0 &cpu1 &cpu2 &cpu3>;
+                };
 
-        irqc0: interrupt-controller@e61c0000 {
-                compatible = "renesas,irqc-r8a7790", "renesas,irqc";
-                #interrupt-cells = <2>;
-                interrupt-controller;
-                reg = <0 0xe61c0000 0 0x200>;
-                interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 407>;
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 407>;
-        };
+                rst: reset-controller@e6160000 {
+                        compatible = "renesas,r8a7790-rst";
+                        reg = <0 0xe6160000 0 0x0100>;
+                };
 
-        dmac0: dma-controller@e6700000 {
-                compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
-                reg = <0 0xe6700000 0 0x20000>;
-                interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
-                interrupt-names = "error",
-                                "ch0", "ch1", "ch2", "ch3",
-                                "ch4", "ch5", "ch6", "ch7",
-                                "ch8", "ch9", "ch10", "ch11",
-                                "ch12", "ch13", "ch14";
-                clocks = <&cpg CPG_MOD 219>;
-                clock-names = "fck";
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 219>;
-                #dma-cells = <1>;
-                dma-channels = <15>;
-        };
+                sysc: system-controller@e6180000 {
+                        compatible = "renesas,r8a7790-sysc";
+                        reg = <0 0xe6180000 0 0x0200>;
+                        #power-domain-cells = <1>;
+                };
 
-        dmac1: dma-controller@e6720000 {
-                compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
-                reg = <0 0xe6720000 0 0x20000>;
-                interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
-                interrupt-names = "error",
-                                "ch0", "ch1", "ch2", "ch3",
-                                "ch4", "ch5", "ch6", "ch7",
-                                "ch8", "ch9", "ch10", "ch11",
-                                "ch12", "ch13", "ch14";
-                clocks = <&cpg CPG_MOD 218>;
-                clock-names = "fck";
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 218>;
-                #dma-cells = <1>;
-                dma-channels = <15>;
-        };
+                irqc0: interrupt-controller@e61c0000 {
+                        compatible = "renesas,irqc-r8a7790", "renesas,irqc";
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        reg = <0 0xe61c0000 0 0x200>;
+                        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 407>;
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 407>;
+                };
 
-        audma0: dma-controller@ec700000 {
-                compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
-                reg = <0 0xec700000 0 0x10000>;
-                interrupts =    <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
-                interrupt-names = "error",
-                                "ch0", "ch1", "ch2", "ch3",
-                                "ch4", "ch5", "ch6", "ch7",
-                                "ch8", "ch9", "ch10", "ch11",
-                                "ch12";
-                clocks = <&cpg CPG_MOD 502>;
-                clock-names = "fck";
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 502>;
-                #dma-cells = <1>;
-                dma-channels = <13>;
-        };
+                thermal: thermal@e61f0000 {
+                        compatible = "renesas,thermal-r8a7790",
+                                     "renesas,rcar-gen2-thermal",
+                                     "renesas,rcar-thermal";
+                        reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
+                        interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 522>;
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 522>;
+                        #thermal-sensor-cells = <0>;
+                };
 
-        audma1: dma-controller@ec720000 {
-                compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
-                reg = <0 0xec720000 0 0x10000>;
-                interrupts =    <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
-                interrupt-names = "error",
-                                "ch0", "ch1", "ch2", "ch3",
-                                "ch4", "ch5", "ch6", "ch7",
-                                "ch8", "ch9", "ch10", "ch11",
-                                "ch12";
-                clocks = <&cpg CPG_MOD 501>;
-                clock-names = "fck";
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 501>;
-                #dma-cells = <1>;
-                dma-channels = <13>;
-        };
+                ipmmu_sy0: mmu@e6280000 {
+                        compatible = "renesas,ipmmu-r8a7790",
+                                     "renesas,ipmmu-vmsa";
+                        reg = <0 0xe6280000 0 0x1000>;
+                        interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+                        #iommu-cells = <1>;
+                        status = "disabled";
+                };
 
-        usb_dmac0: dma-controller@e65a0000 {
-                compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
-                reg = <0 0xe65a0000 0 0x100>;
-                interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
-                interrupt-names = "ch0", "ch1";
-                clocks = <&cpg CPG_MOD 330>;
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 330>;
-                #dma-cells = <1>;
-                dma-channels = <2>;
-        };
+                ipmmu_sy1: mmu@e6290000 {
+                        compatible = "renesas,ipmmu-r8a7790",
+                                     "renesas,ipmmu-vmsa";
+                        reg = <0 0xe6290000 0 0x1000>;
+                        interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+                        #iommu-cells = <1>;
+                        status = "disabled";
+                };
 
-        usb_dmac1: dma-controller@e65b0000 {
-                compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
-                reg = <0 0xe65b0000 0 0x100>;
-                interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-                interrupt-names = "ch0", "ch1";
-                clocks = <&cpg CPG_MOD 331>;
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 331>;
-                #dma-cells = <1>;
-                dma-channels = <2>;
-        };
+                ipmmu_ds: mmu@e6740000 {
+                        compatible = "renesas,ipmmu-r8a7790",
+                                     "renesas,ipmmu-vmsa";
+                        reg = <0 0xe6740000 0 0x1000>;
+                        interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+                        #iommu-cells = <1>;
+                        status = "disabled";
+                };
 
-        i2c0: i2c@e6508000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c";
-                reg = <0 0xe6508000 0 0x40>;
-                interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 931>;
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 931>;
-                i2c-scl-internal-delay-ns = <110>;
-                status = "disabled";
-        };
+                ipmmu_mp: mmu@ec680000 {
+                        compatible = "renesas,ipmmu-r8a7790",
+                                     "renesas,ipmmu-vmsa";
+                        reg = <0 0xec680000 0 0x1000>;
+                        interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+                        #iommu-cells = <1>;
+                        status = "disabled";
+                };
 
-        i2c1: i2c@e6518000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c";
-                reg = <0 0xe6518000 0 0x40>;
-                interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 930>;
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 930>;
-                i2c-scl-internal-delay-ns = <6>;
-                status = "disabled";
-        };
+                ipmmu_mx: mmu@fe951000 {
+                        compatible = "renesas,ipmmu-r8a7790",
+                                     "renesas,ipmmu-vmsa";
+                        reg = <0 0xfe951000 0 0x1000>;
+                        interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+                        #iommu-cells = <1>;
+                        status = "disabled";
+                };
 
-        i2c2: i2c@e6530000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c";
-                reg = <0 0xe6530000 0 0x40>;
-                interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 929>;
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 929>;
-                i2c-scl-internal-delay-ns = <6>;
-                status = "disabled";
-        };
+                ipmmu_rt: mmu@ffc80000 {
+                        compatible = "renesas,ipmmu-r8a7790",
+                                     "renesas,ipmmu-vmsa";
+                        reg = <0 0xffc80000 0 0x1000>;
+                        interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
+                        #iommu-cells = <1>;
+                        status = "disabled";
+                };
 
-        i2c3: i2c@e6540000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c";
-                reg = <0 0xe6540000 0 0x40>;
-                interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 928>;
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 928>;
-                i2c-scl-internal-delay-ns = <110>;
-                status = "disabled";
-        };
+                icram0: sram@e63a0000 {
+                        compatible = "mmio-sram";
+                        reg = <0 0xe63a0000 0 0x12000>;
+                };
 
-        iic0: i2c@e6500000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic",
-                             "renesas,rmobile-iic";
-                reg = <0 0xe6500000 0 0x425>;
-                interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 318>;
-                dmas = <&dmac0 0x61>, <&dmac0 0x62>,
-                       <&dmac1 0x61>, <&dmac1 0x62>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 318>;
-                status = "disabled";
-        };
+                icram1: sram@e63c0000 {
+                        compatible = "mmio-sram";
+                        reg = <0 0xe63c0000 0 0x1000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0 0xe63c0000 0x1000>;
 
-        iic1: i2c@e6510000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic",
-                             "renesas,rmobile-iic";
-                reg = <0 0xe6510000 0 0x425>;
-                interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 323>;
-                dmas = <&dmac0 0x65>, <&dmac0 0x66>,
-                       <&dmac1 0x65>, <&dmac1 0x66>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 323>;
-                status = "disabled";
-        };
+                        smp-sram@0 {
+                                compatible = "renesas,smp-sram";
+                                reg = <0 0x10>;
+                        };
+                };
 
-        iic2: i2c@e6520000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic",
-                             "renesas,rmobile-iic";
-                reg = <0 0xe6520000 0 0x425>;
-                interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 300>;
-                dmas = <&dmac0 0x69>, <&dmac0 0x6a>,
-                       <&dmac1 0x69>, <&dmac1 0x6a>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 300>;
-                status = "disabled";
-        };
+                i2c0: i2c@e6508000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a7790",
+                                     "renesas,rcar-gen2-i2c";
+                        reg = <0 0xe6508000 0 0x40>;
+                        interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 931>;
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 931>;
+                        i2c-scl-internal-delay-ns = <110>;
+                        status = "disabled";
+                };
 
-        iic3: i2c@e60b0000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic",
-                             "renesas,rmobile-iic";
-                reg = <0 0xe60b0000 0 0x425>;
-                interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 926>;
-                dmas = <&dmac0 0x77>, <&dmac0 0x78>,
-                       <&dmac1 0x77>, <&dmac1 0x78>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 926>;
-                status = "disabled";
-        };
+                i2c1: i2c@e6518000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a7790",
+                                     "renesas,rcar-gen2-i2c";
+                        reg = <0 0xe6518000 0 0x40>;
+                        interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 930>;
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 930>;
+                        i2c-scl-internal-delay-ns = <6>;
+                        status = "disabled";
+                };
 
-        mmcif0: mmc@ee200000 {
-                compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
-                reg = <0 0xee200000 0 0x80>;
-                interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 315>;
-                dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
-                       <&dmac1 0xd1>, <&dmac1 0xd2>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 315>;
-                reg-io-width = <4>;
-                status = "disabled";
-                max-frequency = <97500000>;
-        };
+                i2c2: i2c@e6530000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a7790",
+                                     "renesas,rcar-gen2-i2c";
+                        reg = <0 0xe6530000 0 0x40>;
+                        interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 929>;
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 929>;
+                        i2c-scl-internal-delay-ns = <6>;
+                        status = "disabled";
+                };
 
-        mmcif1: mmc@ee220000 {
-                compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
-                reg = <0 0xee220000 0 0x80>;
-                interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 305>;
-                dmas = <&dmac0 0xe1>, <&dmac0 0xe2>,
-                       <&dmac1 0xe1>, <&dmac1 0xe2>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 305>;
-                reg-io-width = <4>;
-                status = "disabled";
-                max-frequency = <97500000>;
-        };
+                i2c3: i2c@e6540000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a7790",
+                                     "renesas,rcar-gen2-i2c";
+                        reg = <0 0xe6540000 0 0x40>;
+                        interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 928>;
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 928>;
+                        i2c-scl-internal-delay-ns = <110>;
+                        status = "disabled";
+                };
 
-        pfc: pin-controller@e6060000 {
-                compatible = "renesas,pfc-r8a7790";
-                reg = <0 0xe6060000 0 0x250>;
-        };
+                iic0: i2c@e6500000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,iic-r8a7790",
+                                     "renesas,rcar-gen2-iic",
+                                     "renesas,rmobile-iic";
+                        reg = <0 0xe6500000 0 0x425>;
+                        interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 318>;
+                        dmas = <&dmac0 0x61>, <&dmac0 0x62>,
+                               <&dmac1 0x61>, <&dmac1 0x62>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 318>;
+                        status = "disabled";
+                };
 
-        sdhi0: sd@ee100000 {
-                compatible = "renesas,sdhi-r8a7790",
-                             "renesas,rcar-gen2-sdhi";
-                reg = <0 0xee100000 0 0x328>;
-                interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 314>;
-                dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
-                       <&dmac1 0xcd>, <&dmac1 0xce>;
-                dma-names = "tx", "rx", "tx", "rx";
-                max-frequency = <195000000>;
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 314>;
-                status = "disabled";
-        };
+                iic1: i2c@e6510000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,iic-r8a7790",
+                                     "renesas,rcar-gen2-iic",
+                                     "renesas,rmobile-iic";
+                        reg = <0 0xe6510000 0 0x425>;
+                        interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 323>;
+                        dmas = <&dmac0 0x65>, <&dmac0 0x66>,
+                               <&dmac1 0x65>, <&dmac1 0x66>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 323>;
+                        status = "disabled";
+                };
 
-        sdhi1: sd@ee120000 {
-                compatible = "renesas,sdhi-r8a7790",
-                             "renesas,rcar-gen2-sdhi";
-                reg = <0 0xee120000 0 0x328>;
-                interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 313>;
-                dmas = <&dmac0 0xc9>, <&dmac0 0xca>,
-                       <&dmac1 0xc9>, <&dmac1 0xca>;
-                dma-names = "tx", "rx", "tx", "rx";
-                max-frequency = <195000000>;
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 313>;
-                status = "disabled";
-        };
+                iic2: i2c@e6520000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,iic-r8a7790",
+                                     "renesas,rcar-gen2-iic",
+                                     "renesas,rmobile-iic";
+                        reg = <0 0xe6520000 0 0x425>;
+                        interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 300>;
+                        dmas = <&dmac0 0x69>, <&dmac0 0x6a>,
+                               <&dmac1 0x69>, <&dmac1 0x6a>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 300>;
+                        status = "disabled";
+                };
 
-        sdhi2: sd@ee140000 {
-                compatible = "renesas,sdhi-r8a7790",
-                             "renesas,rcar-gen2-sdhi";
-                reg = <0 0xee140000 0 0x100>;
-                interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 312>;
-                dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
-                       <&dmac1 0xc1>, <&dmac1 0xc2>;
-                dma-names = "tx", "rx", "tx", "rx";
-                max-frequency = <97500000>;
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 312>;
-                status = "disabled";
-        };
+                iic3: i2c@e60b0000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,iic-r8a7790",
+                                     "renesas,rcar-gen2-iic",
+                                     "renesas,rmobile-iic";
+                        reg = <0 0xe60b0000 0 0x425>;
+                        interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 926>;
+                        dmas = <&dmac0 0x77>, <&dmac0 0x78>,
+                               <&dmac1 0x77>, <&dmac1 0x78>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 926>;
+                        status = "disabled";
+                };
 
-        sdhi3: sd@ee160000 {
-                compatible = "renesas,sdhi-r8a7790",
-                             "renesas,rcar-gen2-sdhi";
-                reg = <0 0xee160000 0 0x100>;
-                interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 311>;
-                dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
-                       <&dmac1 0xd3>, <&dmac1 0xd4>;
-                dma-names = "tx", "rx", "tx", "rx";
-                max-frequency = <97500000>;
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 311>;
-                status = "disabled";
-        };
+                hsusb: usb@e6590000 {
+                        compatible = "renesas,usbhs-r8a7790",
+                                     "renesas,rcar-gen2-usbhs";
+                        reg = <0 0xe6590000 0 0x100>;
+                        interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 704>;
+                        dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
+                               <&usb_dmac1 0>, <&usb_dmac1 1>;
+                        dma-names = "ch0", "ch1", "ch2", "ch3";
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 704>;
+                        renesas,buswait = <4>;
+                        phys = <&usb0 1>;
+                        phy-names = "usb";
+                        status = "disabled";
+                };
 
-        scifa0: serial@e6c40000 {
-                compatible = "renesas,scifa-r8a7790",
-                             "renesas,rcar-gen2-scifa", "renesas,scifa";
-                reg = <0 0xe6c40000 0 64>;
-                interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 204>;
-                clock-names = "fck";
-                dmas = <&dmac0 0x21>, <&dmac0 0x22>,
-                       <&dmac1 0x21>, <&dmac1 0x22>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 204>;
-                status = "disabled";
-        };
+                usbphy: usb-phy@e6590100 {
+                        compatible = "renesas,usb-phy-r8a7790",
+                                     "renesas,rcar-gen2-usb-phy";
+                        reg = <0 0xe6590100 0 0x100>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&cpg CPG_MOD 704>;
+                        clock-names = "usbhs";
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 704>;
+                        status = "disabled";
 
-        scifa1: serial@e6c50000 {
-                compatible = "renesas,scifa-r8a7790",
-                             "renesas,rcar-gen2-scifa", "renesas,scifa";
-                reg = <0 0xe6c50000 0 64>;
-                interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 203>;
-                clock-names = "fck";
-                dmas = <&dmac0 0x25>, <&dmac0 0x26>,
-                       <&dmac1 0x25>, <&dmac1 0x26>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 203>;
-                status = "disabled";
-        };
+                        usb0: usb-channel@0 {
+                                reg = <0>;
+                                #phy-cells = <1>;
+                        };
+                        usb2: usb-channel@2 {
+                                reg = <2>;
+                                #phy-cells = <1>;
+                        };
+                };
 
-        scifa2: serial@e6c60000 {
-                compatible = "renesas,scifa-r8a7790",
-                             "renesas,rcar-gen2-scifa", "renesas,scifa";
-                reg = <0 0xe6c60000 0 64>;
-                interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 202>;
-                clock-names = "fck";
-                dmas = <&dmac0 0x27>, <&dmac0 0x28>,
-                       <&dmac1 0x27>, <&dmac1 0x28>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 202>;
-                status = "disabled";
-        };
+                usb_dmac0: dma-controller@e65a0000 {
+                        compatible = "renesas,r8a7790-usb-dmac",
+                                     "renesas,usb-dmac";
+                        reg = <0 0xe65a0000 0 0x100>;
+                        interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "ch0", "ch1";
+                        clocks = <&cpg CPG_MOD 330>;
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 330>;
+                        #dma-cells = <1>;
+                        dma-channels = <2>;
+                };
 
-        scifb0: serial@e6c20000 {
-                compatible = "renesas,scifb-r8a7790",
-                             "renesas,rcar-gen2-scifb", "renesas,scifb";
-                reg = <0 0xe6c20000 0 0x100>;
-                interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 206>;
-                clock-names = "fck";
-                dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
-                       <&dmac1 0x3d>, <&dmac1 0x3e>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 206>;
-                status = "disabled";
-        };
+                usb_dmac1: dma-controller@e65b0000 {
+                        compatible = "renesas,r8a7790-usb-dmac",
+                                     "renesas,usb-dmac";
+                        reg = <0 0xe65b0000 0 0x100>;
+                        interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "ch0", "ch1";
+                        clocks = <&cpg CPG_MOD 331>;
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 331>;
+                        #dma-cells = <1>;
+                        dma-channels = <2>;
+                };
 
-        scifb1: serial@e6c30000 {
-                compatible = "renesas,scifb-r8a7790",
-                             "renesas,rcar-gen2-scifb", "renesas,scifb";
-                reg = <0 0xe6c30000 0 0x100>;
-                interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 207>;
-                clock-names = "fck";
-                dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
-                       <&dmac1 0x19>, <&dmac1 0x1a>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 207>;
-                status = "disabled";
-        };
+                dmac0: dma-controller@e6700000 {
+                        compatible = "renesas,dmac-r8a7790",
+                                     "renesas,rcar-dmac";
+                        reg = <0 0xe6700000 0 0x20000>;
+                        interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "error",
+                                          "ch0", "ch1", "ch2", "ch3",
+                                          "ch4", "ch5", "ch6", "ch7",
+                                          "ch8", "ch9", "ch10", "ch11",
+                                          "ch12", "ch13", "ch14";
+                        clocks = <&cpg CPG_MOD 219>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 219>;
+                        #dma-cells = <1>;
+                        dma-channels = <15>;
+                };
 
-        scifb2: serial@e6ce0000 {
-                compatible = "renesas,scifb-r8a7790",
-                             "renesas,rcar-gen2-scifb", "renesas,scifb";
-                reg = <0 0xe6ce0000 0 0x100>;
-                interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 216>;
-                clock-names = "fck";
-                dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
-                       <&dmac1 0x1d>, <&dmac1 0x1e>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 216>;
-                status = "disabled";
-        };
+                dmac1: dma-controller@e6720000 {
+                        compatible = "renesas,dmac-r8a7790",
+                                     "renesas,rcar-dmac";
+                        reg = <0 0xe6720000 0 0x20000>;
+                        interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "error",
+                                          "ch0", "ch1", "ch2", "ch3",
+                                          "ch4", "ch5", "ch6", "ch7",
+                                          "ch8", "ch9", "ch10", "ch11",
+                                          "ch12", "ch13", "ch14";
+                        clocks = <&cpg CPG_MOD 218>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 218>;
+                        #dma-cells = <1>;
+                        dma-channels = <15>;
+                };
 
-        scif0: serial@e6e60000 {
-                compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
-                             "renesas,scif";
-                reg = <0 0xe6e60000 0 64>;
-                interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7790_CLK_ZS>,
-                         <&scif_clk>;
-                clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
-                       <&dmac1 0x29>, <&dmac1 0x2a>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 721>;
-                status = "disabled";
-        };
+                avb: ethernet@e6800000 {
+                        compatible = "renesas,etheravb-r8a7790",
+                                     "renesas,etheravb-rcar-gen2";
+                        reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
+                        interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 812>;
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 812>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
 
-        scif1: serial@e6e68000 {
-                compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
-                             "renesas,scif";
-                reg = <0 0xe6e68000 0 64>;
-                interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7790_CLK_ZS>,
-                         <&scif_clk>;
-                clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
-                       <&dmac1 0x2d>, <&dmac1 0x2e>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 720>;
-                status = "disabled";
-        };
+                qspi: spi@e6b10000 {
+                        compatible = "renesas,qspi-r8a7790", "renesas,qspi";
+                        reg = <0 0xe6b10000 0 0x2c>;
+                        interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 917>;
+                        dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+                               <&dmac1 0x17>, <&dmac1 0x18>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 917>;
+                        num-cs = <1>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
 
-        scif2: serial@e6e56000 {
-                compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
-                             "renesas,scif";
-                reg = <0 0xe6e56000 0 64>;
-                interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 310>, <&cpg CPG_CORE R8A7790_CLK_ZS>,
-                         <&scif_clk>;
-                clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
-                       <&dmac1 0x2b>, <&dmac1 0x2c>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 310>;
-                status = "disabled";
-        };
+                scifa0: serial@e6c40000 {
+                        compatible = "renesas,scifa-r8a7790",
+                                     "renesas,rcar-gen2-scifa", "renesas,scifa";
+                        reg = <0 0xe6c40000 0 64>;
+                        interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 204>;
+                        clock-names = "fck";
+                        dmas = <&dmac0 0x21>, <&dmac0 0x22>,
+                               <&dmac1 0x21>, <&dmac1 0x22>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 204>;
+                        status = "disabled";
+                };
 
-        hscif0: serial@e62c0000 {
-                compatible = "renesas,hscif-r8a7790",
-                             "renesas,rcar-gen2-hscif", "renesas,hscif";
-                reg = <0 0xe62c0000 0 96>;
-                interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7790_CLK_ZS>,
-                         <&scif_clk>;
-                clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
-                       <&dmac1 0x39>, <&dmac1 0x3a>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 717>;
-                status = "disabled";
-        };
+                scifa1: serial@e6c50000 {
+                        compatible = "renesas,scifa-r8a7790",
+                                     "renesas,rcar-gen2-scifa", "renesas,scifa";
+                        reg = <0 0xe6c50000 0 64>;
+                        interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 203>;
+                        clock-names = "fck";
+                        dmas = <&dmac0 0x25>, <&dmac0 0x26>,
+                               <&dmac1 0x25>, <&dmac1 0x26>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 203>;
+                        status = "disabled";
+                };
 
-        hscif1: serial@e62c8000 {
-                compatible = "renesas,hscif-r8a7790",
-                             "renesas,rcar-gen2-hscif", "renesas,hscif";
-                reg = <0 0xe62c8000 0 96>;
-                interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7790_CLK_ZS>,
-                         <&scif_clk>;
-                clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
-                       <&dmac1 0x4d>, <&dmac1 0x4e>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 716>;
-                status = "disabled";
-        };
+                scifa2: serial@e6c60000 {
+                        compatible = "renesas,scifa-r8a7790",
+                                     "renesas,rcar-gen2-scifa", "renesas,scifa";
+                        reg = <0 0xe6c60000 0 64>;
+                        interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 202>;
+                        clock-names = "fck";
+                        dmas = <&dmac0 0x27>, <&dmac0 0x28>,
+                               <&dmac1 0x27>, <&dmac1 0x28>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 202>;
+                        status = "disabled";
+                };
 
-        icram0: sram@e63a0000 {
-                compatible = "mmio-sram";
-                reg = <0 0xe63a0000 0 0x12000>;
-        };
+                scifb0: serial@e6c20000 {
+                        compatible = "renesas,scifb-r8a7790",
+                                     "renesas,rcar-gen2-scifb", "renesas,scifb";
+                        reg = <0 0xe6c20000 0 0x100>;
+                        interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 206>;
+                        clock-names = "fck";
+                        dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
+                               <&dmac1 0x3d>, <&dmac1 0x3e>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 206>;
+                        status = "disabled";
+                };
 
-        icram1: sram@e63c0000 {
-                compatible = "mmio-sram";
-                reg = <0 0xe63c0000 0 0x1000>;
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges = <0 0 0xe63c0000 0x1000>;
+                scifb1: serial@e6c30000 {
+                        compatible = "renesas,scifb-r8a7790",
+                                     "renesas,rcar-gen2-scifb", "renesas,scifb";
+                        reg = <0 0xe6c30000 0 0x100>;
+                        interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 207>;
+                        clock-names = "fck";
+                        dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
+                               <&dmac1 0x19>, <&dmac1 0x1a>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 207>;
+                        status = "disabled";
+                };
 
-                smp-sram@0 {
-                        compatible = "renesas,smp-sram";
-                        reg = <0 0x10>;
+                scifb2: serial@e6ce0000 {
+                        compatible = "renesas,scifb-r8a7790",
+                                     "renesas,rcar-gen2-scifb", "renesas,scifb";
+                        reg = <0 0xe6ce0000 0 0x100>;
+                        interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 216>;
+                        clock-names = "fck";
+                        dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
+                               <&dmac1 0x1d>, <&dmac1 0x1e>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 216>;
+                        status = "disabled";
                 };
-        };
 
-        ether: ethernet@ee700000 {
-                compatible = "renesas,ether-r8a7790",
-                             "renesas,rcar-gen2-ether";
-                reg = <0 0xee700000 0 0x400>;
-                interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 813>;
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 813>;
-                phy-mode = "rmii";
-                #address-cells = <1>;
-                #size-cells = <0>;
-                status = "disabled";
-        };
+                scif0: serial@e6e60000 {
+                        compatible = "renesas,scif-r8a7790",
+                                     "renesas,rcar-gen2-scif",
+                                     "renesas,scif";
+                        reg = <0 0xe6e60000 0 64>;
+                        interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 721>,
+                                 <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+                               <&dmac1 0x29>, <&dmac1 0x2a>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 721>;
+                        status = "disabled";
+                };
 
-        avb: ethernet@e6800000 {
-                compatible = "renesas,etheravb-r8a7790",
-                             "renesas,etheravb-rcar-gen2";
-                reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
-                interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 812>;
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 812>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                status = "disabled";
-        };
+                scif1: serial@e6e68000 {
+                        compatible = "renesas,scif-r8a7790",
+                                     "renesas,rcar-gen2-scif",
+                                     "renesas,scif";
+                        reg = <0 0xe6e68000 0 64>;
+                        interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 720>,
+                                 <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+                               <&dmac1 0x2d>, <&dmac1 0x2e>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 720>;
+                        status = "disabled";
+                };
 
-        sata0: sata@ee300000 {
-                compatible = "renesas,sata-r8a7790", "renesas,rcar-gen2-sata";
-                reg = <0 0xee300000 0 0x2000>;
-                interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 815>;
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 815>;
-                status = "disabled";
-        };
+                scif2: serial@e6e56000 {
+                        compatible = "renesas,scif-r8a7790",
+                                     "renesas,rcar-gen2-scif",
+                                     "renesas,scif";
+                        reg = <0 0xe6e56000 0 64>;
+                        interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 310>,
+                                 <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+                               <&dmac1 0x2b>, <&dmac1 0x2c>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 310>;
+                        status = "disabled";
+                };
 
-        sata1: sata@ee500000 {
-                compatible = "renesas,sata-r8a7790", "renesas,rcar-gen2-sata";
-                reg = <0 0xee500000 0 0x2000>;
-                interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 814>;
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 814>;
-                status = "disabled";
-        };
+                hscif0: serial@e62c0000 {
+                        compatible = "renesas,hscif-r8a7790",
+                                     "renesas,rcar-gen2-hscif", "renesas,hscif";
+                        reg = <0 0xe62c0000 0 96>;
+                        interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 717>,
+                                 <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+                               <&dmac1 0x39>, <&dmac1 0x3a>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 717>;
+                        status = "disabled";
+                };
 
-        hsusb: usb@e6590000 {
-                compatible = "renesas,usbhs-r8a7790", "renesas,rcar-gen2-usbhs";
-                reg = <0 0xe6590000 0 0x100>;
-                interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 704>;
-                dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
-                       <&usb_dmac1 0>, <&usb_dmac1 1>;
-                dma-names = "ch0", "ch1", "ch2", "ch3";
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 704>;
-                renesas,buswait = <4>;
-                phys = <&usb0 1>;
-                phy-names = "usb";
-                status = "disabled";
-        };
+                hscif1: serial@e62c8000 {
+                        compatible = "renesas,hscif-r8a7790",
+                                     "renesas,rcar-gen2-hscif", "renesas,hscif";
+                        reg = <0 0xe62c8000 0 96>;
+                        interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 716>,
+                                 <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+                               <&dmac1 0x4d>, <&dmac1 0x4e>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 716>;
+                        status = "disabled";
+                };
 
-        usbphy: usb-phy@e6590100 {
-                compatible = "renesas,usb-phy-r8a7790",
-                             "renesas,rcar-gen2-usb-phy";
-                reg = <0 0xe6590100 0 0x100>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                clocks = <&cpg CPG_MOD 704>;
-                clock-names = "usbhs";
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 704>;
-                status = "disabled";
+                msiof0: spi@e6e20000 {
+                        compatible = "renesas,msiof-r8a7790",
+                                     "renesas,rcar-gen2-msiof";
+                        reg = <0 0xe6e20000 0 0x0064>;
+                        interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 0>;
+                        dmas = <&dmac0 0x51>, <&dmac0 0x52>,
+                               <&dmac1 0x51>, <&dmac1 0x52>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
 
-                usb0: usb-channel@0 {
-                        reg = <0>;
-                        #phy-cells = <1>;
+                msiof1: spi@e6e10000 {
+                        compatible = "renesas,msiof-r8a7790",
+                                     "renesas,rcar-gen2-msiof";
+                        reg = <0 0xe6e10000 0 0x0064>;
+                        interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 208>;
+                        dmas = <&dmac0 0x55>, <&dmac0 0x56>,
+                               <&dmac1 0x55>, <&dmac1 0x56>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 208>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
                 };
-                usb2: usb-channel@2 {
-                        reg = <2>;
-                        #phy-cells = <1>;
+
+                msiof2: spi@e6e00000 {
+                        compatible = "renesas,msiof-r8a7790",
+                                     "renesas,rcar-gen2-msiof";
+                        reg = <0 0xe6e00000 0 0x0064>;
+                        interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 205>;
+                        dmas = <&dmac0 0x41>, <&dmac0 0x42>,
+                               <&dmac1 0x41>, <&dmac1 0x42>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 205>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
                 };
-        };
 
-        vin0: video@e6ef0000 {
-                compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
-                reg = <0 0xe6ef0000 0 0x1000>;
-                interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 811>;
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 811>;
-                status = "disabled";
-        };
+                msiof3: spi@e6c90000 {
+                        compatible = "renesas,msiof-r8a7790",
+                                     "renesas,rcar-gen2-msiof";
+                        reg = <0 0xe6c90000 0 0x0064>;
+                        interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 215>;
+                        dmas = <&dmac0 0x45>, <&dmac0 0x46>,
+                               <&dmac1 0x45>, <&dmac1 0x46>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 215>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
 
-        vin1: video@e6ef1000 {
-                compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
-                reg = <0 0xe6ef1000 0 0x1000>;
-                interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 810>;
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 810>;
-                status = "disabled";
-        };
+                can0: can@e6e80000 {
+                        compatible = "renesas,can-r8a7790",
+                                     "renesas,rcar-gen2-can";
+                        reg = <0 0xe6e80000 0 0x1000>;
+                        interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 916>,
+                                 <&cpg CPG_CORE R8A7790_CLK_RCAN>, <&can_clk>;
+                        clock-names = "clkp1", "clkp2", "can_clk";
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 916>;
+                        status = "disabled";
+                };
 
-        vin2: video@e6ef2000 {
-                compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
-                reg = <0 0xe6ef2000 0 0x1000>;
-                interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 809>;
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 809>;
-                status = "disabled";
-        };
+                can1: can@e6e88000 {
+                        compatible = "renesas,can-r8a7790",
+                                     "renesas,rcar-gen2-can";
+                        reg = <0 0xe6e88000 0 0x1000>;
+                        interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 915>,
+                                 <&cpg CPG_CORE R8A7790_CLK_RCAN>, <&can_clk>;
+                        clock-names = "clkp1", "clkp2", "can_clk";
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 915>;
+                        status = "disabled";
+                };
 
-        vin3: video@e6ef3000 {
-                compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
-                reg = <0 0xe6ef3000 0 0x1000>;
-                interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 808>;
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 808>;
-                status = "disabled";
-        };
+                vin0: video@e6ef0000 {
+                        compatible = "renesas,vin-r8a7790",
+                                     "renesas,rcar-gen2-vin";
+                        reg = <0 0xe6ef0000 0 0x1000>;
+                        interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 811>;
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 811>;
+                        status = "disabled";
+                };
 
-        vsp@fe920000 {
-                compatible = "renesas,vsp1";
-                reg = <0 0xfe920000 0 0x8000>;
-                interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 130>;
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 130>;
-        };
+                vin1: video@e6ef1000 {
+                        compatible = "renesas,vin-r8a7790",
+                                     "renesas,rcar-gen2-vin";
+                        reg = <0 0xe6ef1000 0 0x1000>;
+                        interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 810>;
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 810>;
+                        status = "disabled";
+                };
 
-        vsp@fe928000 {
-                compatible = "renesas,vsp1";
-                reg = <0 0xfe928000 0 0x8000>;
-                interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 131>;
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 131>;
-        };
+                vin2: video@e6ef2000 {
+                        compatible = "renesas,vin-r8a7790",
+                                     "renesas,rcar-gen2-vin";
+                        reg = <0 0xe6ef2000 0 0x1000>;
+                        interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 809>;
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 809>;
+                        status = "disabled";
+                };
 
-        vsp@fe930000 {
-                compatible = "renesas,vsp1";
-                reg = <0 0xfe930000 0 0x8000>;
-                interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 128>;
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 128>;
-        };
+                vin3: video@e6ef3000 {
+                        compatible = "renesas,vin-r8a7790",
+                                     "renesas,rcar-gen2-vin";
+                        reg = <0 0xe6ef3000 0 0x1000>;
+                        interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 808>;
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 808>;
+                        status = "disabled";
+                };
 
-        vsp@fe938000 {
-                compatible = "renesas,vsp1";
-                reg = <0 0xfe938000 0 0x8000>;
-                interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 127>;
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 127>;
-        };
+                rcar_sound: sound@ec500000 {
+                        /*
+                         * #sound-dai-cells is required
+                         *
+                         * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
+                         * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
+                         */
+                        compatible = "renesas,rcar_sound-r8a7790",
+                                     "renesas,rcar_sound-gen2";
+                        reg = <0 0xec500000 0 0x1000>, /* SCU */
+                              <0 0xec5a0000 0 0x100>,  /* ADG */
+                              <0 0xec540000 0 0x1000>, /* SSIU */
+                              <0 0xec541000 0 0x280>,  /* SSI */
+                              <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
+                        reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+                        clocks = <&cpg CPG_MOD 1005>,
+                                 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+                                 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+                                 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+                                 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+                                 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+                                 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+                                 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+                                 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+                                 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+                                 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+                                 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
+                                 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
+                                 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+                                 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
+                                 <&cpg CPG_CORE R8A7790_CLK_M2>;
+                        clock-names = "ssi-all",
+                                      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+                                      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+                                      "ssi.1", "ssi.0",
+                                      "src.9", "src.8", "src.7", "src.6",
+                                      "src.5", "src.4", "src.3", "src.2",
+                                      "src.1", "src.0",
+                                      "ctu.0", "ctu.1",
+                                      "mix.0", "mix.1",
+                                      "dvc.0", "dvc.1",
+                                      "clk_a", "clk_b", "clk_c", "clk_i";
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 1005>,
+                                 <&cpg 1006>, <&cpg 1007>,
+                                 <&cpg 1008>, <&cpg 1009>,
+                                 <&cpg 1010>, <&cpg 1011>,
+                                 <&cpg 1012>, <&cpg 1013>,
+                                 <&cpg 1014>, <&cpg 1015>;
+                        reset-names = "ssi-all",
+                                      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+                                      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+                                      "ssi.1", "ssi.0";
+
+                        status = "disabled";
+
+                        rcar_sound,dvc {
+                                dvc0: dvc-0 {
+                                        dmas = <&audma1 0xbc>;
+                                        dma-names = "tx";
+                                };
+                                dvc1: dvc-1 {
+                                        dmas = <&audma1 0xbe>;
+                                        dma-names = "tx";
+                                };
+                        };
 
-        du: display@feb00000 {
-                compatible = "renesas,du-r8a7790";
-                reg = <0 0xfeb00000 0 0x70000>,
-                      <0 0xfeb90000 0 0x1c>,
-                      <0 0xfeb94000 0 0x1c>;
-                reg-names = "du", "lvds.0", "lvds.1";
-                interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
-                         <&cpg CPG_MOD 722>, <&cpg CPG_MOD 726>,
-                         <&cpg CPG_MOD 725>;
-                clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
-                status = "disabled";
-
-                ports {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
+                        rcar_sound,mix {
+                                mix0: mix-0 { };
+                                mix1: mix-1 { };
+                        };
 
-                        port@0 {
-                                reg = <0>;
-                                du_out_rgb: endpoint {
-                                };
+                        rcar_sound,ctu {
+                                ctu00: ctu-0 { };
+                                ctu01: ctu-1 { };
+                                ctu02: ctu-2 { };
+                                ctu03: ctu-3 { };
+                                ctu10: ctu-4 { };
+                                ctu11: ctu-5 { };
+                                ctu12: ctu-6 { };
+                                ctu13: ctu-7 { };
                         };
-                        port@1 {
-                                reg = <1>;
-                                du_out_lvds0: endpoint {
+
+                        rcar_sound,src {
+                                src0: src-0 {
+                                        interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x85>, <&audma1 0x9a>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src1: src-1 {
+                                        interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x87>, <&audma1 0x9c>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src2: src-2 {
+                                        interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x89>, <&audma1 0x9e>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src3: src-3 {
+                                        interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x8b>, <&audma1 0xa0>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src4: src-4 {
+                                        interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x8d>, <&audma1 0xb0>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src5: src-5 {
+                                        interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x8f>, <&audma1 0xb2>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src6: src-6 {
+                                        interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x91>, <&audma1 0xb4>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src7: src-7 {
+                                        interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x93>, <&audma1 0xb6>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src8: src-8 {
+                                        interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x95>, <&audma1 0xb8>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src9: src-9 {
+                                        interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x97>, <&audma1 0xba>;
+                                        dma-names = "rx", "tx";
                                 };
                         };
-                        port@2 {
-                                reg = <2>;
-                                du_out_lvds1: endpoint {
+
+                        rcar_sound,ssi {
+                                ssi0: ssi-0 {
+                                        interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x01>, <&audma1 0x02>,
+                                               <&audma0 0x15>, <&audma1 0x16>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi1: ssi-1 {
+                                         interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x03>, <&audma1 0x04>,
+                                               <&audma0 0x49>, <&audma1 0x4a>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi2: ssi-2 {
+                                        interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x05>, <&audma1 0x06>,
+                                               <&audma0 0x63>, <&audma1 0x64>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi3: ssi-3 {
+                                        interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x07>, <&audma1 0x08>,
+                                               <&audma0 0x6f>, <&audma1 0x70>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi4: ssi-4 {
+                                        interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x09>, <&audma1 0x0a>,
+                                               <&audma0 0x71>, <&audma1 0x72>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi5: ssi-5 {
+                                        interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x0b>, <&audma1 0x0c>,
+                                               <&audma0 0x73>, <&audma1 0x74>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi6: ssi-6 {
+                                        interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x0d>, <&audma1 0x0e>,
+                                               <&audma0 0x75>, <&audma1 0x76>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi7: ssi-7 {
+                                        interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x0f>, <&audma1 0x10>,
+                                               <&audma0 0x79>, <&audma1 0x7a>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi8: ssi-8 {
+                                        interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x11>, <&audma1 0x12>,
+                                               <&audma0 0x7b>, <&audma1 0x7c>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi9: ssi-9 {
+                                        interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x13>, <&audma1 0x14>,
+                                               <&audma0 0x7d>, <&audma1 0x7e>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
                                 };
                         };
                 };
-        };
 
-        can0: can@e6e80000 {
-                compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can";
-                reg = <0 0xe6e80000 0 0x1000>;
-                interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7790_CLK_RCAN>,
-                         <&can_clk>;
-                clock-names = "clkp1", "clkp2", "can_clk";
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 916>;
-                status = "disabled";
-        };
-
-        can1: can@e6e88000 {
-                compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can";
-                reg = <0 0xe6e88000 0 0x1000>;
-                interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7790_CLK_RCAN>,
-                         <&can_clk>;
-                clock-names = "clkp1", "clkp2", "can_clk";
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 915>;
-                status = "disabled";
-        };
-
-        jpu: jpeg-codec@fe980000 {
-                compatible = "renesas,jpu-r8a7790", "renesas,rcar-gen2-jpu";
-                reg = <0 0xfe980000 0 0x10300>;
-                interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 106>;
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 106>;
-        };
-
-        /* External root clock */
-        extal_clk: extal {
-                compatible = "fixed-clock";
-                #clock-cells = <0>;
-                /* This value must be overridden by the board. */
-                clock-frequency = <0>;
-        };
-
-        /* External PCIe clock - can be overridden by the board */
-        pcie_bus_clk: pcie_bus {
-                compatible = "fixed-clock";
-                #clock-cells = <0>;
-                clock-frequency = <0>;
-        };
+                audma0: dma-controller@ec700000 {
+                        compatible = "renesas,dmac-r8a7790",
+                                     "renesas,rcar-dmac";
+                        reg = <0 0xec700000 0 0x10000>;
+                        interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "error",
+                                          "ch0", "ch1", "ch2", "ch3",
+                                          "ch4", "ch5", "ch6", "ch7",
+                                          "ch8", "ch9", "ch10", "ch11",
+                                          "ch12";
+                        clocks = <&cpg CPG_MOD 502>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 502>;
+                        #dma-cells = <1>;
+                        dma-channels = <13>;
+                };
 
-        /*
-         * The external audio clocks are configured as 0 Hz fixed frequency
-         * clocks by default.
-         * Boards that provide audio clocks should override them.
-         */
-        audio_clk_a: audio_clk_a {
-                compatible = "fixed-clock";
-                #clock-cells = <0>;
-                clock-frequency = <0>;
-        };
-        audio_clk_b: audio_clk_b {
-                compatible = "fixed-clock";
-                #clock-cells = <0>;
-                clock-frequency = <0>;
-        };
-        audio_clk_c: audio_clk_c {
-                compatible = "fixed-clock";
-                #clock-cells = <0>;
-                clock-frequency = <0>;
-        };
+                audma1: dma-controller@ec720000 {
+                        compatible = "renesas,dmac-r8a7790",
+                                     "renesas,rcar-dmac";
+                        reg = <0 0xec720000 0 0x10000>;
+                        interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "error",
+                                          "ch0", "ch1", "ch2", "ch3",
+                                          "ch4", "ch5", "ch6", "ch7",
+                                          "ch8", "ch9", "ch10", "ch11",
+                                          "ch12";
+                        clocks = <&cpg CPG_MOD 501>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 501>;
+                        #dma-cells = <1>;
+                        dma-channels = <13>;
+                };
 
-        /* External SCIF clock */
-        scif_clk: scif {
-                compatible = "fixed-clock";
-                #clock-cells = <0>;
-                /* This value must be overridden by the board. */
-                clock-frequency = <0>;
-        };
+                xhci: usb@ee000000 {
+                        compatible = "renesas,xhci-r8a7790",
+                                     "renesas,rcar-gen2-xhci";
+                        reg = <0 0xee000000 0 0xc00>;
+                        interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 328>;
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 328>;
+                        phys = <&usb2 1>;
+                        phy-names = "usb";
+                        status = "disabled";
+                };
 
-        /* External USB clock - can be overridden by the board */
-        usb_extal_clk: usb_extal {
-                compatible = "fixed-clock";
-                #clock-cells = <0>;
-                clock-frequency = <48000000>;
-        };
+                pci0: pci@ee090000 {
+                        compatible = "renesas,pci-r8a7790",
+                                     "renesas,pci-rcar-gen2";
+                        device_type = "pci";
+                        reg = <0 0xee090000 0 0xc00>,
+                              <0 0xee080000 0 0x1100>;
+                        interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 703>;
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 703>;
+                        status = "disabled";
+
+                        bus-range = <0 0>;
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        #interrupt-cells = <1>;
+                        ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
+                        interrupt-map-mask = <0xff00 0 0 0x7>;
+                        interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+                                         0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+                                         0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+
+                        usb@1,0 {
+                                reg = <0x800 0 0 0 0>;
+                                phys = <&usb0 0>;
+                                phy-names = "usb";
+                        };
 
-        /* External CAN clock */
-        can_clk: can {
-                compatible = "fixed-clock";
-                #clock-cells = <0>;
-                /* This value must be overridden by the board. */
-                clock-frequency = <0>;
-        };
+                        usb@2,0 {
+                                reg = <0x1000 0 0 0 0>;
+                                phys = <&usb0 0>;
+                                phy-names = "usb";
+                        };
+                };
 
-        cpg: clock-controller@e6150000 {
-                compatible = "renesas,r8a7790-cpg-mssr";
-                reg = <0 0xe6150000 0 0x1000>;
-                clocks = <&extal_clk>, <&usb_extal_clk>;
-                clock-names = "extal", "usb_extal";
-                #clock-cells = <2>;
-                #power-domain-cells = <0>;
-                #reset-cells = <1>;
-        };
+                pci1: pci@ee0b0000 {
+                        compatible = "renesas,pci-r8a7790",
+                                     "renesas,pci-rcar-gen2";
+                        device_type = "pci";
+                        reg = <0 0xee0b0000 0 0xc00>,
+                              <0 0xee0a0000 0 0x1100>;
+                        interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 703>;
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 703>;
+                        status = "disabled";
+
+                        bus-range = <1 1>;
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        #interrupt-cells = <1>;
+                        ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
+                        interrupt-map-mask = <0xff00 0 0 0x7>;
+                        interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
+                                         0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
+                                         0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+                };
 
-        prr: chipid@ff000044 {
-                compatible = "renesas,prr";
-                reg = <0 0xff000044 0 4>;
-        };
+                pci2: pci@ee0d0000 {
+                        compatible = "renesas,pci-r8a7790",
+                                     "renesas,pci-rcar-gen2";
+                        device_type = "pci";
+                        clocks = <&cpg CPG_MOD 703>;
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 703>;
+                        reg = <0 0xee0d0000 0 0xc00>,
+                              <0 0xee0c0000 0 0x1100>;
+                        interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+                        status = "disabled";
+
+                        bus-range = <2 2>;
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        #interrupt-cells = <1>;
+                        ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
+                        interrupt-map-mask = <0xff00 0 0 0x7>;
+                        interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+                                         0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+                                         0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+
+                        usb@1,0 {
+                                reg = <0x20800 0 0 0 0>;
+                                phys = <&usb2 0>;
+                                phy-names = "usb";
+                        };
 
-        rst: reset-controller@e6160000 {
-                compatible = "renesas,r8a7790-rst";
-                reg = <0 0xe6160000 0 0x0100>;
-        };
+                        usb@2,0 {
+                                reg = <0x21000 0 0 0 0>;
+                                phys = <&usb2 0>;
+                                phy-names = "usb";
+                        };
+                };
 
-        sysc: system-controller@e6180000 {
-                compatible = "renesas,r8a7790-sysc";
-                reg = <0 0xe6180000 0 0x0200>;
-                #power-domain-cells = <1>;
-        };
+                sdhi0: sd@ee100000 {
+                        compatible = "renesas,sdhi-r8a7790",
+                                     "renesas,rcar-gen2-sdhi";
+                        reg = <0 0xee100000 0 0x328>;
+                        interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 314>;
+                        dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+                               <&dmac1 0xcd>, <&dmac1 0xce>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        max-frequency = <195000000>;
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 314>;
+                        status = "disabled";
+                };
 
-        qspi: spi@e6b10000 {
-                compatible = "renesas,qspi-r8a7790", "renesas,qspi";
-                reg = <0 0xe6b10000 0 0x2c>;
-                interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 917>;
-                dmas = <&dmac0 0x17>, <&dmac0 0x18>,
-                       <&dmac1 0x17>, <&dmac1 0x18>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 917>;
-                num-cs = <1>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                status = "disabled";
-        };
+                sdhi1: sd@ee120000 {
+                        compatible = "renesas,sdhi-r8a7790",
+                                     "renesas,rcar-gen2-sdhi";
+                        reg = <0 0xee120000 0 0x328>;
+                        interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 313>;
+                        dmas = <&dmac0 0xc9>, <&dmac0 0xca>,
+                               <&dmac1 0xc9>, <&dmac1 0xca>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        max-frequency = <195000000>;
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 313>;
+                        status = "disabled";
+                };
 
-        msiof0: spi@e6e20000 {
-                compatible = "renesas,msiof-r8a7790",
-                             "renesas,rcar-gen2-msiof";
-                reg = <0 0xe6e20000 0 0x0064>;
-                interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 0>;
-                dmas = <&dmac0 0x51>, <&dmac0 0x52>,
-                       <&dmac1 0x51>, <&dmac1 0x52>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                status = "disabled";
-        };
+                sdhi2: sd@ee140000 {
+                        compatible = "renesas,sdhi-r8a7790",
+                                     "renesas,rcar-gen2-sdhi";
+                        reg = <0 0xee140000 0 0x100>;
+                        interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 312>;
+                        dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+                               <&dmac1 0xc1>, <&dmac1 0xc2>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        max-frequency = <97500000>;
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 312>;
+                        status = "disabled";
+                };
 
-        msiof1: spi@e6e10000 {
-                compatible = "renesas,msiof-r8a7790",
-                             "renesas,rcar-gen2-msiof";
-                reg = <0 0xe6e10000 0 0x0064>;
-                interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 208>;
-                dmas = <&dmac0 0x55>, <&dmac0 0x56>,
-                       <&dmac1 0x55>, <&dmac1 0x56>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 208>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                status = "disabled";
-        };
+                sdhi3: sd@ee160000 {
+                        compatible = "renesas,sdhi-r8a7790",
+                                     "renesas,rcar-gen2-sdhi";
+                        reg = <0 0xee160000 0 0x100>;
+                        interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 311>;
+                        dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+                               <&dmac1 0xd3>, <&dmac1 0xd4>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        max-frequency = <97500000>;
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 311>;
+                        status = "disabled";
+                };
 
-        msiof2: spi@e6e00000 {
-                compatible = "renesas,msiof-r8a7790",
-                             "renesas,rcar-gen2-msiof";
-                reg = <0 0xe6e00000 0 0x0064>;
-                interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 205>;
-                dmas = <&dmac0 0x41>, <&dmac0 0x42>,
-                       <&dmac1 0x41>, <&dmac1 0x42>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 205>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                status = "disabled";
-        };
+                mmcif0: mmc@ee200000 {
+                        compatible = "renesas,mmcif-r8a7790",
+                                     "renesas,sh-mmcif";
+                        reg = <0 0xee200000 0 0x80>;
+                        interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 315>;
+                        dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+                               <&dmac1 0xd1>, <&dmac1 0xd2>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 315>;
+                        reg-io-width = <4>;
+                        status = "disabled";
+                        max-frequency = <97500000>;
+                };
 
-        msiof3: spi@e6c90000 {
-                compatible = "renesas,msiof-r8a7790",
-                             "renesas,rcar-gen2-msiof";
-                reg = <0 0xe6c90000 0 0x0064>;
-                interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 215>;
-                dmas = <&dmac0 0x45>, <&dmac0 0x46>,
-                       <&dmac1 0x45>, <&dmac1 0x46>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 215>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                status = "disabled";
-        };
+                mmcif1: mmc@ee220000 {
+                        compatible = "renesas,mmcif-r8a7790",
+                                     "renesas,sh-mmcif";
+                        reg = <0 0xee220000 0 0x80>;
+                        interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 305>;
+                        dmas = <&dmac0 0xe1>, <&dmac0 0xe2>,
+                               <&dmac1 0xe1>, <&dmac1 0xe2>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 305>;
+                        reg-io-width = <4>;
+                        status = "disabled";
+                        max-frequency = <97500000>;
+                };
 
-        xhci: usb@ee000000 {
-                compatible = "renesas,xhci-r8a7790", "renesas,rcar-gen2-xhci";
-                reg = <0 0xee000000 0 0xc00>;
-                interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 328>;
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 328>;
-                phys = <&usb2 1>;
-                phy-names = "usb";
-                status = "disabled";
-        };
+                sata0: sata@ee300000 {
+                        compatible = "renesas,sata-r8a7790",
+                                     "renesas,rcar-gen2-sata";
+                        reg = <0 0xee300000 0 0x2000>;
+                        interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 815>;
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 815>;
+                        status = "disabled";
+                };
 
-        pci0: pci@ee090000 {
-                compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
-                device_type = "pci";
-                reg = <0 0xee090000 0 0xc00>,
-                      <0 0xee080000 0 0x1100>;
-                interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 703>;
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 703>;
-                status = "disabled";
-
-                bus-range = <0 0>;
-                #address-cells = <3>;
-                #size-cells = <2>;
-                #interrupt-cells = <1>;
-                ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
-                interrupt-map-mask = <0xff00 0 0 0x7>;
-                interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
-                                 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
-                                 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-
-                usb@1,0 {
-                        reg = <0x800 0 0 0 0>;
-                        phys = <&usb0 0>;
-                        phy-names = "usb";
+                sata1: sata@ee500000 {
+                        compatible = "renesas,sata-r8a7790",
+                                     "renesas,rcar-gen2-sata";
+                        reg = <0 0xee500000 0 0x2000>;
+                        interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 814>;
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 814>;
+                        status = "disabled";
                 };
 
-                usb@2,0 {
-                        reg = <0x1000 0 0 0 0>;
-                        phys = <&usb0 0>;
-                        phy-names = "usb";
+                ether: ethernet@ee700000 {
+                        compatible = "renesas,ether-r8a7790",
+                                     "renesas,rcar-gen2-ether";
+                        reg = <0 0xee700000 0 0x400>;
+                        interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 813>;
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 813>;
+                        phy-mode = "rmii";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
                 };
-        };
 
-        pci1: pci@ee0b0000 {
-                compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
-                device_type = "pci";
-                reg = <0 0xee0b0000 0 0xc00>,
-                      <0 0xee0a0000 0 0x1100>;
-                interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 703>;
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 703>;
-                status = "disabled";
-
-                bus-range = <1 1>;
-                #address-cells = <3>;
-                #size-cells = <2>;
-                #interrupt-cells = <1>;
-                ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
-                interrupt-map-mask = <0xff00 0 0 0x7>;
-                interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
-                                 0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
-                                 0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
-        };
+                gic: interrupt-controller@f1001000 {
+                        compatible = "arm,gic-400";
+                        #interrupt-cells = <3>;
+                        #address-cells = <0>;
+                        interrupt-controller;
+                        reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
+                              <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
+                        interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+                        clocks = <&cpg CPG_MOD 408>;
+                        clock-names = "clk";
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 408>;
+                };
 
-        pci2: pci@ee0d0000 {
-                compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
-                device_type = "pci";
-                clocks = <&cpg CPG_MOD 703>;
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 703>;
-                reg = <0 0xee0d0000 0 0xc00>,
-                      <0 0xee0c0000 0 0x1100>;
-                interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
-                status = "disabled";
-
-                bus-range = <2 2>;
-                #address-cells = <3>;
-                #size-cells = <2>;
-                #interrupt-cells = <1>;
-                ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
-                interrupt-map-mask = <0xff00 0 0 0x7>;
-                interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
-                                 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
-                                 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
-
-                usb@1,0 {
-                        reg = <0x20800 0 0 0 0>;
-                        phys = <&usb2 0>;
-                        phy-names = "usb";
+                pciec: pcie@fe000000 {
+                        compatible = "renesas,pcie-r8a7790",
+                                     "renesas,pcie-rcar-gen2";
+                        reg = <0 0xfe000000 0 0x80000>;
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        bus-range = <0x00 0xff>;
+                        device_type = "pci";
+                        ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
+                                  0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
+                                  0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
+                                  0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+                        /* Map all possible DDR as inbound ranges */
+                        dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
+                                      0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
+                        interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+                        #interrupt-cells = <1>;
+                        interrupt-map-mask = <0 0 0 0>;
+                        interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
+                        clock-names = "pcie", "pcie_bus";
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 319>;
+                        status = "disabled";
                 };
 
-                usb@2,0 {
-                        reg = <0x21000 0 0 0 0>;
-                        phys = <&usb2 0>;
-                        phy-names = "usb";
+                vsp@fe920000 {
+                        compatible = "renesas,vsp1";
+                        reg = <0 0xfe920000 0 0x8000>;
+                        interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 130>;
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 130>;
                 };
-        };
 
-        pciec: pcie@fe000000 {
-                compatible = "renesas,pcie-r8a7790", "renesas,pcie-rcar-gen2";
-                reg = <0 0xfe000000 0 0x80000>;
-                #address-cells = <3>;
-                #size-cells = <2>;
-                bus-range = <0x00 0xff>;
-                device_type = "pci";
-                ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
-                          0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
-                          0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
-                          0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
-                /* Map all possible DDR as inbound ranges */
-                dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
-                              0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
-                interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
-                #interrupt-cells = <1>;
-                interrupt-map-mask = <0 0 0 0>;
-                interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
-                clock-names = "pcie", "pcie_bus";
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 319>;
-                status = "disabled";
-        };
+                vsp@fe928000 {
+                        compatible = "renesas,vsp1";
+                        reg = <0 0xfe928000 0 0x8000>;
+                        interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 131>;
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 131>;
+                };
 
-        rcar_sound: sound@ec500000 {
-                /*
-                 * #sound-dai-cells is required
-                 *
-                 * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
-                 * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
-                 */
-                compatible =  "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2";
-                reg =   <0 0xec500000 0 0x1000>, /* SCU */
-                        <0 0xec5a0000 0 0x100>,  /* ADG */
-                        <0 0xec540000 0 0x1000>, /* SSIU */
-                        <0 0xec541000 0 0x280>,  /* SSI */
-                        <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
-                reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
-
-                clocks = <&cpg CPG_MOD 1005>,
-                         <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
-                         <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
-                         <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
-                         <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
-                         <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
-                         <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
-                         <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
-                         <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
-                         <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
-                         <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
-                         <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
-                         <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
-                         <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
-                         <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
-                         <&cpg CPG_CORE R8A7790_CLK_M2>;
-                clock-names = "ssi-all",
-                                "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
-                                "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
-                                "src.9", "src.8", "src.7", "src.6", "src.5",
-                                "src.4", "src.3", "src.2", "src.1", "src.0",
-                                "ctu.0", "ctu.1",
-                                "mix.0", "mix.1",
-                                "dvc.0", "dvc.1",
-                                "clk_a", "clk_b", "clk_c", "clk_i";
-                power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
-                resets = <&cpg 1005>,
-                         <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>,
-                         <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>,
-                         <&cpg 1014>, <&cpg 1015>;
-                reset-names = "ssi-all",
-                              "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
-                              "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0";
-
-                status = "disabled";
-
-                rcar_sound,dvc {
-                        dvc0: dvc-0 {
-                                dmas = <&audma1 0xbc>;
-                                dma-names = "tx";
-                        };
-                        dvc1: dvc-1 {
-                                dmas = <&audma1 0xbe>;
-                                dma-names = "tx";
-                        };
+                vsp@fe930000 {
+                        compatible = "renesas,vsp1";
+                        reg = <0 0xfe930000 0 0x8000>;
+                        interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 128>;
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 128>;
                 };
 
-                rcar_sound,mix {
-                        mix0: mix-0 { };
-                        mix1: mix-1 { };
+                vsp@fe938000 {
+                        compatible = "renesas,vsp1";
+                        reg = <0 0xfe938000 0 0x8000>;
+                        interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 127>;
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 127>;
                 };
 
-                rcar_sound,ctu {
-                        ctu00: ctu-0 { };
-                        ctu01: ctu-1 { };
-                        ctu02: ctu-2 { };
-                        ctu03: ctu-3 { };
-                        ctu10: ctu-4 { };
-                        ctu11: ctu-5 { };
-                        ctu12: ctu-6 { };
-                        ctu13: ctu-7 { };
+                jpu: jpeg-codec@fe980000 {
+                        compatible = "renesas,jpu-r8a7790",
+                                     "renesas,rcar-gen2-jpu";
+                        reg = <0 0xfe980000 0 0x10300>;
+                        interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 106>;
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 106>;
                 };
 
-                rcar_sound,src {
-                        src0: src-0 {
-                                interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x85>, <&audma1 0x9a>;
-                                dma-names = "rx", "tx";
-                        };
-                        src1: src-1 {
-                                interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x87>, <&audma1 0x9c>;
-                                dma-names = "rx", "tx";
-                        };
-                        src2: src-2 {
-                                interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x89>, <&audma1 0x9e>;
-                                dma-names = "rx", "tx";
-                        };
-                        src3: src-3 {
-                                interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x8b>, <&audma1 0xa0>;
-                                dma-names = "rx", "tx";
-                        };
-                        src4: src-4 {
-                                interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x8d>, <&audma1 0xb0>;
-                                dma-names = "rx", "tx";
-                        };
-                        src5: src-5 {
-                                interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x8f>, <&audma1 0xb2>;
-                                dma-names = "rx", "tx";
-                        };
-                        src6: src-6 {
-                                interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x91>, <&audma1 0xb4>;
-                                dma-names = "rx", "tx";
-                        };
-                        src7: src-7 {
-                                interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x93>, <&audma1 0xb6>;
-                                dma-names = "rx", "tx";
-                        };
-                        src8: src-8 {
-                                interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x95>, <&audma1 0xb8>;
-                                dma-names = "rx", "tx";
-                        };
-                        src9: src-9 {
-                                interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x97>, <&audma1 0xba>;
-                                dma-names = "rx", "tx";
+                du: display@feb00000 {
+                        compatible = "renesas,du-r8a7790";
+                        reg = <0 0xfeb00000 0 0x70000>,
+                              <0 0xfeb90000 0 0x1c>,
+                              <0 0xfeb94000 0 0x1c>;
+                        reg-names = "du", "lvds.0", "lvds.1";
+                        interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
+                                 <&cpg CPG_MOD 722>, <&cpg CPG_MOD 726>,
+                                 <&cpg CPG_MOD 725>;
+                        clock-names = "du.0", "du.1", "du.2", "lvds.0",
+                                      "lvds.1";
+                        status = "disabled";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@0 {
+                                        reg = <0>;
+                                        du_out_rgb: endpoint {
+                                        };
+                                };
+                                port@1 {
+                                        reg = <1>;
+                                        du_out_lvds0: endpoint {
+                                        };
+                                };
+                                port@2 {
+                                        reg = <2>;
+                                        du_out_lvds1: endpoint {
+                                        };
+                                };
                         };
                 };
 
-                rcar_sound,ssi {
-                        ssi0: ssi-0 {
-                                interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
-                                dma-names = "rx", "tx", "rxu", "txu";
-                        };
-                        ssi1: ssi-1 {
-                                 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
-                                dma-names = "rx", "tx", "rxu", "txu";
-                        };
-                        ssi2: ssi-2 {
-                                interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
-                                dma-names = "rx", "tx", "rxu", "txu";
-                        };
-                        ssi3: ssi-3 {
-                                interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
-                                dma-names = "rx", "tx", "rxu", "txu";
-                        };
-                        ssi4: ssi-4 {
-                                interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
-                                dma-names = "rx", "tx", "rxu", "txu";
-                        };
-                        ssi5: ssi-5 {
-                                interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
-                                dma-names = "rx", "tx", "rxu", "txu";
-                        };
-                        ssi6: ssi-6 {
-                                interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
-                                dma-names = "rx", "tx", "rxu", "txu";
-                        };
-                        ssi7: ssi-7 {
-                                interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
-                                dma-names = "rx", "tx", "rxu", "txu";
-                        };
-                        ssi8: ssi-8 {
-                                interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
-                                dma-names = "rx", "tx", "rxu", "txu";
-                        };
-                        ssi9: ssi-9 {
-                                interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
-                                dma-names = "rx", "tx", "rxu", "txu";
-                        };
+                prr: chipid@ff000044 {
+                        compatible = "renesas,prr";
+                        reg = <0 0xff000044 0 4>;
                 };
-        };
 
-        ipmmu_sy0: mmu@e6280000 {
-                compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
-                reg = <0 0xe6280000 0 0x1000>;
-                interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
-                #iommu-cells = <1>;
-                status = "disabled";
-        };
+                cmt0: timer@ffca0000 {
+                        compatible = "renesas,r8a7790-cmt0",
+                                     "renesas,rcar-gen2-cmt0";
+                        reg = <0 0xffca0000 0 0x1004>;
+                        interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 124>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 124>;
+
+                        status = "disabled";
+                };
 
-        ipmmu_sy1: mmu@e6290000 {
-                compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
-                reg = <0 0xe6290000 0 0x1000>;
-                interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
-                #iommu-cells = <1>;
-                status = "disabled";
+                cmt1: timer@e6130000 {
+                        compatible = "renesas,r8a7790-cmt1",
+                                     "renesas,rcar-gen2-cmt1";
+                        reg = <0 0xe6130000 0 0x1004>;
+                        interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 329>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+                        resets = <&cpg 329>;
+
+                        status = "disabled";
+                };
         };
 
-        ipmmu_ds: mmu@e6740000 {
-                compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
-                reg = <0 0xe6740000 0 0x1000>;
-                interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
-                #iommu-cells = <1>;
-                status = "disabled";
-        };
+        thermal-zones {
+                cpu_thermal: cpu-thermal {
+                        polling-delay-passive = <0>;
+                        polling-delay = <0>;
 
-        ipmmu_mp: mmu@ec680000 {
-                compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
-                reg = <0 0xec680000 0 0x1000>;
-                interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
-                #iommu-cells = <1>;
-                status = "disabled";
+                        thermal-sensors = <&thermal>;
+
+                        trips {
+                                cpu-crit {
+                                        temperature = <95000>;
+                                        hysteresis = <0>;
+                                        type = "critical";
+                                };
+                        };
+                        cooling-maps {
+                        };
+                };
         };
 
-        ipmmu_mx: mmu@fe951000 {
-                compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
-                reg = <0 0xfe951000 0 0x1000>;
-                interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
-                #iommu-cells = <1>;
-                status = "disabled";
+        timer {
+                compatible = "arm,armv7-timer";
+                interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                                      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                                      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                                      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
         };
 
-        ipmmu_rt: mmu@ffc80000 {
-                compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
-                reg = <0 0xffc80000 0 0x1000>;
-                interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
-                #iommu-cells = <1>;
-                status = "disabled";
+        /* External USB clock - can be overridden by the board */
+        usb_extal_clk: usb_extal {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <48000000>;
         };
 };
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index a50924d12b6f..f40321a1c917 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -51,7 +51,11 @@
                 serial0 = &scif0;
                 serial1 = &scif1;
                 i2c9 = &gpioi2c1;
+                i2c10 = &gpioi2c2;
+                i2c11 = &gpioi2c4;
                 i2c12 = &i2cexio1;
+                i2c13 = &i2chdmi;
+                i2c14 = &i2cexio4;
         };
 
         chosen {
@@ -312,8 +316,28 @@
                 #size-cells = <0>;
                 compatible = "i2c-gpio";
                 status = "disabled";
-                sda-gpios = <&gpio7 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
                 scl-gpios = <&gpio7 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+                sda-gpios = <&gpio7 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+                i2c-gpio,delay-us = <5>;
+        };
+
+        gpioi2c2: i2c-10 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "i2c-gpio";
+                status = "disabled";
+                scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+                sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+                i2c-gpio,delay-us = <5>;
+        };
+
+        gpioi2c4: i2c-11 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "i2c-gpio";
+                status = "disabled";
+                scl-gpios = <&gpio7 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+                sda-gpios = <&gpio7 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
                 i2c-gpio,delay-us = <5>;
         };
 
@@ -328,6 +352,115 @@
                 #address-cells = <1>;
                 #size-cells = <0>;
         };
+
+        /*
+         * A fallback to GPIO is provided for I2C2.
+         */
+        i2chdmi: i2c-13 {
+                compatible = "i2c-demux-pinctrl";
+                i2c-parent = <&i2c2>, <&gpioi2c2>;
+                i2c-bus-name = "i2c-hdmi";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                ak4643: codec@12 {
+                        compatible = "asahi-kasei,ak4643";
+                        #sound-dai-cells = <0>;
+                        reg = <0x12>;
+                };
+
+                composite-in@20 {
+                        compatible = "adi,adv7180";
+                        reg = <0x20>;
+                        remote = <&vin1>;
+
+                        port {
+                                adv7180: endpoint {
+                                        bus-width = <8>;
+                                        remote-endpoint = <&vin1ep>;
+                                };
+                        };
+                };
+
+                hdmi@39 {
+                        compatible = "adi,adv7511w";
+                        reg = <0x39>;
+                        interrupt-parent = <&gpio3>;
+                        interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
+                        clocks = <&cec_clock>;
+                        clock-names = "cec";
+
+                        adi,input-depth = <8>;
+                        adi,input-colorspace = "rgb";
+                        adi,input-clock = "1x";
+                        adi,input-style = <1>;
+                        adi,input-justification = "evenly";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@0 {
+                                        reg = <0>;
+                                        adv7511_in: endpoint {
+                                                remote-endpoint = <&du_out_rgb>;
+                                        };
+                                };
+
+                                port@1 {
+                                        reg = <1>;
+                                        adv7511_out: endpoint {
+                                                remote-endpoint = <&hdmi_con_out>;
+                                        };
+                                };
+                        };
+                };
+
+                hdmi-in@4c {
+                        compatible = "adi,adv7612";
+                        reg = <0x4c>;
+                        interrupt-parent = <&gpio4>;
+                        interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+                        default-input = <0>;
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@0 {
+                                        reg = <0>;
+                                        adv7612_in: endpoint {
+                                                remote-endpoint = <&hdmi_con_in>;
+                                        };
+                                };
+
+                                port@2 {
+                                        reg = <2>;
+                                        adv7612_out: endpoint {
+                                                remote-endpoint = <&vin0ep2>;
+                                        };
+                                };
+                        };
+                };
+
+                eeprom@50 {
+                        compatible = "renesas,r1ex24002", "atmel,24c02";
+                        reg = <0x50>;
+                        pagesize = <16>;
+                };
+        };
+
+        /*
+         * I2C4 is routed to EXIO connector E, pins 37 (SCL) + 39 (SDA).
+         * A fallback to GPIO is provided.
+         */
+        i2cexio4: i2c-14 {
+                compatible = "i2c-demux-pinctrl";
+                i2c-parent = <&i2c4>, <&gpioi2c4>;
+                i2c-bus-name = "i2c-exio4";
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
 };
 
 &du {
@@ -371,6 +504,11 @@
                 function = "i2c2";
         };
 
+        i2c4_pins: i2c4 {
+                groups = "i2c4_c";
+                function = "i2c4";
+        };
+
         du_pins: du {
                 groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
                 function = "du";
@@ -621,96 +759,14 @@
 
 &i2c2 {
         pinctrl-0 = <&i2c2_pins>;
-        pinctrl-names = "default";
+        pinctrl-names = "i2c-hdmi";
 
-        status = "okay";
         clock-frequency = <100000>;
+};
 
-        ak4643: codec@12 {
-                compatible = "asahi-kasei,ak4643";
-                #sound-dai-cells = <0>;
-                reg = <0x12>;
-        };
-
-        composite-in@20 {
-                compatible = "adi,adv7180";
-                reg = <0x20>;
-                remote = <&vin1>;
-
-                port {
-                        adv7180: endpoint {
-                                bus-width = <8>;
-                                remote-endpoint = <&vin1ep>;
-                        };
-                };
-        };
-
-        hdmi@39 {
-                compatible = "adi,adv7511w";
-                reg = <0x39>;
-                interrupt-parent = <&gpio3>;
-                interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
-                clocks = <&cec_clock>;
-                clock-names = "cec";
-
-                adi,input-depth = <8>;
-                adi,input-colorspace = "rgb";
-                adi,input-clock = "1x";
-                adi,input-style = <1>;
-                adi,input-justification = "evenly";
-
-                ports {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-
-                        port@0 {
-                                reg = <0>;
-                                adv7511_in: endpoint {
-                                        remote-endpoint = <&du_out_rgb>;
-                                };
-                        };
-
-                        port@1 {
-                                reg = <1>;
-                                adv7511_out: endpoint {
-                                        remote-endpoint = <&hdmi_con_out>;
-                                };
-                        };
-                };
-        };
-
-        hdmi-in@4c {
-                compatible = "adi,adv7612";
-                reg = <0x4c>;
-                interrupt-parent = <&gpio4>;
-                interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
-                default-input = <0>;
-
-                ports {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-
-                        port@0 {
-                                reg = <0>;
-                                adv7612_in: endpoint {
-                                        remote-endpoint = <&hdmi_con_in>;
-                                };
-                        };
-
-                        port@2 {
-                                reg = <2>;
-                                adv7612_out: endpoint {
-                                        remote-endpoint = <&vin0ep2>;
-                                };
-                        };
-                };
-        };
-
-        eeprom@50 {
-                compatible = "renesas,r1ex24002", "atmel,24c02";
-                reg = <0x50>;
-                pagesize = <16>;
-        };
+&i2c4 {
+        pinctrl-0 = <&i2c4_pins>;
+        pinctrl-names = "i2c-exio4";
 };
 
 &i2c6 {
diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts
index eb374956294f..c14e6fe9e4f6 100644
--- a/arch/arm/boot/dts/r8a7791-porter.dts
+++ b/arch/arm/boot/dts/r8a7791-porter.dts
@@ -29,6 +29,8 @@
 
         aliases {
                 serial0 = &scif0;
+                i2c9 = &gpioi2c2;
+                i2c10 = &i2chdmi;
         };
 
         chosen {
@@ -135,6 +137,78 @@
                         clocks = <&x14_clk>;
                 };
         };
+
+        gpioi2c2: i2c-9 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "i2c-gpio";
+                status = "disabled";
+                scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+                sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+                i2c-gpio,delay-us = <5>;
+        };
+
+        /*
+         * A fallback to GPIO is provided for I2C2.
+         */
+        i2chdmi: i2c-10 {
+                compatible = "i2c-demux-pinctrl";
+                i2c-parent = <&i2c2>, <&gpioi2c2>;
+                i2c-bus-name = "i2c-hdmi";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                ak4642: codec@12 {
+                        compatible = "asahi-kasei,ak4642";
+                        #sound-dai-cells = <0>;
+                        reg = <0x12>;
+                };
+
+                composite-in@20 {
+                        compatible = "adi,adv7180";
+                        reg = <0x20>;
+                        remote = <&vin0>;
+
+                        port {
+                                adv7180: endpoint {
+                                        bus-width = <8>;
+                                        remote-endpoint = <&vin0ep>;
+                                };
+                        };
+                };
+
+                hdmi@39 {
+                        compatible = "adi,adv7511w";
+                        reg = <0x39>;
+                        interrupt-parent = <&gpio3>;
+                        interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
+
+                        adi,input-depth = <8>;
+                        adi,input-colorspace = "rgb";
+                        adi,input-clock = "1x";
+                        adi,input-style = <1>;
+                        adi,input-justification = "evenly";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@0 {
+                                        reg = <0>;
+                                        adv7511_in: endpoint {
+                                                remote-endpoint = <&du_out_rgb>;
+                                        };
+                                };
+
+                                port@1 {
+                                        reg = <1>;
+                                        adv7511_out: endpoint {
+                                                remote-endpoint = <&hdmi_con>;
+                                        };
+                                };
+                        };
+                };
+        };
 };
 
 &extal_clk {
@@ -296,61 +370,9 @@
 
 &i2c2 {
         pinctrl-0 = <&i2c2_pins>;
-        pinctrl-names = "default";
+        pinctrl-names = "i2c-hdmi";
 
-        status = "okay";
         clock-frequency = <400000>;
-
-        ak4642: codec@12 {
-                compatible = "asahi-kasei,ak4642";
-                #sound-dai-cells = <0>;
-                reg = <0x12>;
-        };
-
-        composite-in@20 {
-                compatible = "adi,adv7180";
-                reg = <0x20>;
-                remote = <&vin0>;
-
-                port {
-                        adv7180: endpoint {
-                                bus-width = <8>;
-                                remote-endpoint = <&vin0ep>;
-                        };
-                };
-        };
-
-        hdmi@39 {
-                compatible = "adi,adv7511w";
-                reg = <0x39>;
-                interrupt-parent = <&gpio3>;
-                interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
-
-                adi,input-depth = <8>;
-                adi,input-colorspace = "rgb";
-                adi,input-clock = "1x";
-                adi,input-style = <1>;
-                adi,input-justification = "evenly";
-
-                ports {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-
-                        port@0 {
-                                reg = <0>;
-                                adv7511_in: endpoint {
-                                        remote-endpoint = <&du_out_rgb>;
-                                };
-                        };
-
-                        port@1 {
-                                reg = <1>;
-                                adv7511_out: endpoint {
-                                        remote-endpoint = <&hdmi_con>;
-                                };
-                        };
-                };
-        };
 };
 
 &sata0 {
@@ -425,7 +447,7 @@
                       "dclkin.0", "dclkin.1";
 
         ports {
-                port@1 {
+                port@0 {
                         endpoint {
                                 remote-endpoint = <&adv7511_in>;
                         };
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 008a260f86a5..f11dab71b03a 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -17,7 +17,6 @@
 
 / {
         compatible = "renesas,r8a7791";
-        interrupt-parent = <&gic>;
         #address-cells = <2>;
         #size-cells = <2>;
 
@@ -40,6 +39,35 @@
                 vin2 = &vin2;
         };
 
+        /*
+         * The external audio clocks are configured as 0 Hz fixed frequency
+         * clocks by default.
+         * Boards that provide audio clocks should override them.
+         */
+        audio_clk_a: audio_clk_a {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+        audio_clk_b: audio_clk_b {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+        audio_clk_c: audio_clk_c {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+
+        /* External CAN clock */
+        can_clk: can {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                /* This value must be overridden by the board. */
+                clock-frequency = <0>;
+        };
+
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -83,1585 +111,1627 @@
                 };
         };
 
-        thermal-zones {
-                cpu_thermal: cpu-thermal {
-                        polling-delay-passive   = <0>;
-                        polling-delay           = <0>;
-
-                        thermal-sensors = <&thermal>;
-
-                        trips {
-                                cpu-crit {
-                                        temperature     = <95000>;
-                                        hysteresis      = <0>;
-                                        type            = "critical";
-                                };
-                        };
-                        cooling-maps {
-                        };
-                };
-        };
-
-        apmu@e6152000 {
-                compatible = "renesas,r8a7791-apmu", "renesas,apmu";
-                reg = <0 0xe6152000 0 0x188>;
-                cpus = <&cpu0 &cpu1>;
-        };
-
-        gic: interrupt-controller@f1001000 {
-                compatible = "arm,gic-400";
-                #interrupt-cells = <3>;
-                #address-cells = <0>;
-                interrupt-controller;
-                reg = <0 0xf1001000 0 0x1000>,
-                        <0 0xf1002000 0 0x2000>,
-                        <0 0xf1004000 0 0x2000>,
-                        <0 0xf1006000 0 0x2000>;
-                interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
-                clocks = <&cpg CPG_MOD 408>;
-                clock-names = "clk";
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 408>;
-        };
-
-        gpio0: gpio@e6050000 {
-                compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
-                reg = <0 0xe6050000 0 0x50>;
-                interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
-                #gpio-cells = <2>;
-                gpio-controller;
-                gpio-ranges = <&pfc 0 0 32>;
-                #interrupt-cells = <2>;
-                interrupt-controller;
-                clocks = <&cpg CPG_MOD 912>;
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 912>;
-        };
-
-        gpio1: gpio@e6051000 {
-                compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
-                reg = <0 0xe6051000 0 0x50>;
-                interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
-                #gpio-cells = <2>;
-                gpio-controller;
-                gpio-ranges = <&pfc 0 32 26>;
-                #interrupt-cells = <2>;
-                interrupt-controller;
-                clocks = <&cpg CPG_MOD 911>;
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 911>;
-        };
-
-        gpio2: gpio@e6052000 {
-                compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
-                reg = <0 0xe6052000 0 0x50>;
-                interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
-                #gpio-cells = <2>;
-                gpio-controller;
-                gpio-ranges = <&pfc 0 64 32>;
-                #interrupt-cells = <2>;
-                interrupt-controller;
-                clocks = <&cpg CPG_MOD 910>;
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 910>;
+        /* External root clock */
+        extal_clk: extal {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                /* This value must be overridden by the board. */
+                clock-frequency = <0>;
         };
 
-        gpio3: gpio@e6053000 {
-                compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
-                reg = <0 0xe6053000 0 0x50>;
-                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
-                #gpio-cells = <2>;
-                gpio-controller;
-                gpio-ranges = <&pfc 0 96 32>;
-                #interrupt-cells = <2>;
-                interrupt-controller;
-                clocks = <&cpg CPG_MOD 909>;
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 909>;
+        /* External PCIe clock - can be overridden by the board */
+        pcie_bus_clk: pcie_bus {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
         };
 
-        gpio4: gpio@e6054000 {
-                compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
-                reg = <0 0xe6054000 0 0x50>;
-                interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
-                #gpio-cells = <2>;
-                gpio-controller;
-                gpio-ranges = <&pfc 0 128 32>;
-                #interrupt-cells = <2>;
-                interrupt-controller;
-                clocks = <&cpg CPG_MOD 908>;
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 908>;
+        /* External SCIF clock */
+        scif_clk: scif {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                /* This value must be overridden by the board. */
+                clock-frequency = <0>;
         };
 
-        gpio5: gpio@e6055000 {
-                compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
-                reg = <0 0xe6055000 0 0x50>;
-                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
-                #gpio-cells = <2>;
-                gpio-controller;
-                gpio-ranges = <&pfc 0 160 32>;
-                #interrupt-cells = <2>;
-                interrupt-controller;
-                clocks = <&cpg CPG_MOD 907>;
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 907>;
-        };
+        soc {
+                compatible = "simple-bus";
+                interrupt-parent = <&gic>;
 
-        gpio6: gpio@e6055400 {
-                compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
-                reg = <0 0xe6055400 0 0x50>;
-                interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-                #gpio-cells = <2>;
-                gpio-controller;
-                gpio-ranges = <&pfc 0 192 32>;
-                #interrupt-cells = <2>;
-                interrupt-controller;
-                clocks = <&cpg CPG_MOD 905>;
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 905>;
-        };
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
+
+                gpio0: gpio@e6050000 {
+                        compatible = "renesas,gpio-r8a7791",
+                                     "renesas,rcar-gen2-gpio";
+                        reg = <0 0xe6050000 0 0x50>;
+                        interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 0 32>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 912>;
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 912>;
+                };
 
-        gpio7: gpio@e6055800 {
-                compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio";
-                reg = <0 0xe6055800 0 0x50>;
-                interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
-                #gpio-cells = <2>;
-                gpio-controller;
-                gpio-ranges = <&pfc 0 224 26>;
-                #interrupt-cells = <2>;
-                interrupt-controller;
-                clocks = <&cpg CPG_MOD 904>;
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 904>;
-        };
+                gpio1: gpio@e6051000 {
+                        compatible = "renesas,gpio-r8a7791",
+                                     "renesas,rcar-gen2-gpio";
+                        reg = <0 0xe6051000 0 0x50>;
+                        interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 32 26>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 911>;
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 911>;
+                };
 
-        thermal: thermal@e61f0000 {
-                compatible =    "renesas,thermal-r8a7791",
-                                "renesas,rcar-gen2-thermal",
-                                "renesas,rcar-thermal";
-                reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
-                interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 522>;
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 522>;
-                #thermal-sensor-cells = <0>;
-        };
+                gpio2: gpio@e6052000 {
+                        compatible = "renesas,gpio-r8a7791",
+                                     "renesas,rcar-gen2-gpio";
+                        reg = <0 0xe6052000 0 0x50>;
+                        interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 64 32>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 910>;
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 910>;
+                };
 
-        timer {
-                compatible = "arm,armv7-timer";
-                interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-                             <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-                             <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-                             <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
-        };
+                gpio3: gpio@e6053000 {
+                        compatible = "renesas,gpio-r8a7791",
+                                     "renesas,rcar-gen2-gpio";
+                        reg = <0 0xe6053000 0 0x50>;
+                        interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 96 32>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 909>;
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 909>;
+                };
 
-        cmt0: timer@ffca0000 {
-                compatible = "renesas,r8a7791-cmt0", "renesas,rcar-gen2-cmt0";
-                reg = <0 0xffca0000 0 0x1004>;
-                interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 124>;
-                clock-names = "fck";
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 124>;
-
-                status = "disabled";
-        };
+                gpio4: gpio@e6054000 {
+                        compatible = "renesas,gpio-r8a7791",
+                                     "renesas,rcar-gen2-gpio";
+                        reg = <0 0xe6054000 0 0x50>;
+                        interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 128 32>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 908>;
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 908>;
+                };
 
-        cmt1: timer@e6130000 {
-                compatible = "renesas,r8a7791-cmt1", "renesas,rcar-gen2-cmt1";
-                reg = <0 0xe6130000 0 0x1004>;
-                interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 329>;
-                clock-names = "fck";
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 329>;
-
-                status = "disabled";
-        };
+                gpio5: gpio@e6055000 {
+                        compatible = "renesas,gpio-r8a7791",
+                                     "renesas,rcar-gen2-gpio";
+                        reg = <0 0xe6055000 0 0x50>;
+                        interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 160 32>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 907>;
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 907>;
+                };
 
-        irqc0: interrupt-controller@e61c0000 {
-                compatible = "renesas,irqc-r8a7791", "renesas,irqc";
-                #interrupt-cells = <2>;
-                interrupt-controller;
-                reg = <0 0xe61c0000 0 0x200>;
-                interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 407>;
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 407>;
-        };
+                gpio6: gpio@e6055400 {
+                        compatible = "renesas,gpio-r8a7791",
+                                     "renesas,rcar-gen2-gpio";
+                        reg = <0 0xe6055400 0 0x50>;
+                        interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 192 32>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 905>;
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 905>;
+                };
 
-        dmac0: dma-controller@e6700000 {
-                compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
-                reg = <0 0xe6700000 0 0x20000>;
-                interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
-                interrupt-names = "error",
-                                "ch0", "ch1", "ch2", "ch3",
-                                "ch4", "ch5", "ch6", "ch7",
-                                "ch8", "ch9", "ch10", "ch11",
-                                "ch12", "ch13", "ch14";
-                clocks = <&cpg CPG_MOD 219>;
-                clock-names = "fck";
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 219>;
-                #dma-cells = <1>;
-                dma-channels = <15>;
-        };
+                gpio7: gpio@e6055800 {
+                        compatible = "renesas,gpio-r8a7791",
+                                     "renesas,rcar-gen2-gpio";
+                        reg = <0 0xe6055800 0 0x50>;
+                        interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 224 26>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 904>;
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 904>;
+                };
 
-        dmac1: dma-controller@e6720000 {
-                compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
-                reg = <0 0xe6720000 0 0x20000>;
-                interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
-                interrupt-names = "error",
-                                "ch0", "ch1", "ch2", "ch3",
-                                "ch4", "ch5", "ch6", "ch7",
-                                "ch8", "ch9", "ch10", "ch11",
-                                "ch12", "ch13", "ch14";
-                clocks = <&cpg CPG_MOD 218>;
-                clock-names = "fck";
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 218>;
-                #dma-cells = <1>;
-                dma-channels = <15>;
-        };
+                pfc: pin-controller@e6060000 {
+                        compatible = "renesas,pfc-r8a7791";
+                        reg = <0 0xe6060000 0 0x250>;
+                };
 
-        audma0: dma-controller@ec700000 {
-                compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
-                reg = <0 0xec700000 0 0x10000>;
-                interrupts =    <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
-                interrupt-names = "error",
-                                "ch0", "ch1", "ch2", "ch3",
-                                "ch4", "ch5", "ch6", "ch7",
-                                "ch8", "ch9", "ch10", "ch11",
-                                "ch12";
-                clocks = <&cpg CPG_MOD 502>;
-                clock-names = "fck";
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 502>;
-                #dma-cells = <1>;
-                dma-channels = <13>;
-        };
+                cpg: clock-controller@e6150000 {
+                        compatible = "renesas,r8a7791-cpg-mssr";
+                        reg = <0 0xe6150000 0 0x1000>;
+                        clocks = <&extal_clk>, <&usb_extal_clk>;
+                        clock-names = "extal", "usb_extal";
+                        #clock-cells = <2>;
+                        #power-domain-cells = <0>;
+                        #reset-cells = <1>;
+                };
 
-        audma1: dma-controller@ec720000 {
-                compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac";
-                reg = <0 0xec720000 0 0x10000>;
-                interrupts =    <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
-                interrupt-names = "error",
-                                "ch0", "ch1", "ch2", "ch3",
-                                "ch4", "ch5", "ch6", "ch7",
-                                "ch8", "ch9", "ch10", "ch11",
-                                "ch12";
-                clocks = <&cpg CPG_MOD 501>;
-                clock-names = "fck";
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 501>;
-                #dma-cells = <1>;
-                dma-channels = <13>;
-        };
+                apmu@e6152000 {
+                        compatible = "renesas,r8a7791-apmu", "renesas,apmu";
+                        reg = <0 0xe6152000 0 0x188>;
+                        cpus = <&cpu0 &cpu1>;
+                };
 
-        usb_dmac0: dma-controller@e65a0000 {
-                compatible = "renesas,r8a7791-usb-dmac", "renesas,usb-dmac";
-                reg = <0 0xe65a0000 0 0x100>;
-                interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
-                interrupt-names = "ch0", "ch1";
-                clocks = <&cpg CPG_MOD 330>;
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 330>;
-                #dma-cells = <1>;
-                dma-channels = <2>;
-        };
+                rst: reset-controller@e6160000 {
+                        compatible = "renesas,r8a7791-rst";
+                        reg = <0 0xe6160000 0 0x0100>;
+                };
 
-        usb_dmac1: dma-controller@e65b0000 {
-                compatible = "renesas,r8a7791-usb-dmac", "renesas,usb-dmac";
-                reg = <0 0xe65b0000 0 0x100>;
-                interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-                interrupt-names = "ch0", "ch1";
-                clocks = <&cpg CPG_MOD 331>;
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 331>;
-                #dma-cells = <1>;
-                dma-channels = <2>;
-        };
+                sysc: system-controller@e6180000 {
+                        compatible = "renesas,r8a7791-sysc";
+                        reg = <0 0xe6180000 0 0x0200>;
+                        #power-domain-cells = <1>;
+                };
 
-        /* The memory map in the User's Manual maps the cores to bus numbers */
-        i2c0: i2c@e6508000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
-                reg = <0 0xe6508000 0 0x40>;
-                interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 931>;
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 931>;
-                i2c-scl-internal-delay-ns = <6>;
-                status = "disabled";
-        };
+                irqc0: interrupt-controller@e61c0000 {
+                        compatible = "renesas,irqc-r8a7791", "renesas,irqc";
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        reg = <0 0xe61c0000 0 0x200>;
+                        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 407>;
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 407>;
+                };
 
-        i2c1: i2c@e6518000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
-                reg = <0 0xe6518000 0 0x40>;
-                interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 930>;
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 930>;
-                i2c-scl-internal-delay-ns = <6>;
-                status = "disabled";
-        };
+                thermal: thermal@e61f0000 {
+                        compatible = "renesas,thermal-r8a7791",
+                                     "renesas,rcar-gen2-thermal",
+                                     "renesas,rcar-thermal";
+                        reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
+                        interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 522>;
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 522>;
+                        #thermal-sensor-cells = <0>;
+                };
 
-        i2c2: i2c@e6530000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
-                reg = <0 0xe6530000 0 0x40>;
-                interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 929>;
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 929>;
-                i2c-scl-internal-delay-ns = <6>;
-                status = "disabled";
-        };
+                ipmmu_sy0: mmu@e6280000 {
+                        compatible = "renesas,ipmmu-r8a7791",
+                                     "renesas,ipmmu-vmsa";
+                        reg = <0 0xe6280000 0 0x1000>;
+                        interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+                        #iommu-cells = <1>;
+                        status = "disabled";
+                };
 
-        i2c3: i2c@e6540000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
-                reg = <0 0xe6540000 0 0x40>;
-                interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 928>;
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 928>;
-                i2c-scl-internal-delay-ns = <6>;
-                status = "disabled";
-        };
+                ipmmu_sy1: mmu@e6290000 {
+                        compatible = "renesas,ipmmu-r8a7791",
+                                     "renesas,ipmmu-vmsa";
+                        reg = <0 0xe6290000 0 0x1000>;
+                        interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+                        #iommu-cells = <1>;
+                        status = "disabled";
+                };
 
-        i2c4: i2c@e6520000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
-                reg = <0 0xe6520000 0 0x40>;
-                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 927>;
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 927>;
-                i2c-scl-internal-delay-ns = <6>;
-                status = "disabled";
-        };
+                ipmmu_ds: mmu@e6740000 {
+                        compatible = "renesas,ipmmu-r8a7791",
+                                     "renesas,ipmmu-vmsa";
+                        reg = <0 0xe6740000 0 0x1000>;
+                        interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+                        #iommu-cells = <1>;
+                        status = "disabled";
+                };
 
-        i2c5: i2c@e6528000 {
-                /* doesn't need pinmux */
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
-                reg = <0 0xe6528000 0 0x40>;
-                interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 925>;
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 925>;
-                i2c-scl-internal-delay-ns = <110>;
-                status = "disabled";
-        };
+                ipmmu_mp: mmu@ec680000 {
+                        compatible = "renesas,ipmmu-r8a7791",
+                                     "renesas,ipmmu-vmsa";
+                        reg = <0 0xec680000 0 0x1000>;
+                        interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+                        #iommu-cells = <1>;
+                        status = "disabled";
+                };
 
-        i2c6: i2c@e60b0000 {
-                /* doesn't need pinmux */
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "renesas,iic-r8a7791", "renesas,rcar-gen2-iic",
-                             "renesas,rmobile-iic";
-                reg = <0 0xe60b0000 0 0x425>;
-                interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 926>;
-                dmas = <&dmac0 0x77>, <&dmac0 0x78>,
-                       <&dmac1 0x77>, <&dmac1 0x78>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 926>;
-                status = "disabled";
-        };
+                ipmmu_mx: mmu@fe951000 {
+                        compatible = "renesas,ipmmu-r8a7791",
+                                     "renesas,ipmmu-vmsa";
+                        reg = <0 0xfe951000 0 0x1000>;
+                        interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+                        #iommu-cells = <1>;
+                        status = "disabled";
+                };
 
-        i2c7: i2c@e6500000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "renesas,iic-r8a7791", "renesas,rcar-gen2-iic",
-                             "renesas,rmobile-iic";
-                reg = <0 0xe6500000 0 0x425>;
-                interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 318>;
-                dmas = <&dmac0 0x61>, <&dmac0 0x62>,
-                       <&dmac1 0x61>, <&dmac1 0x62>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 318>;
-                status = "disabled";
-        };
+                ipmmu_rt: mmu@ffc80000 {
+                        compatible = "renesas,ipmmu-r8a7791",
+                                     "renesas,ipmmu-vmsa";
+                        reg = <0 0xffc80000 0 0x1000>;
+                        interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
+                        #iommu-cells = <1>;
+                        status = "disabled";
+                };
 
-        i2c8: i2c@e6510000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "renesas,iic-r8a7791", "renesas,rcar-gen2-iic",
-                             "renesas,rmobile-iic";
-                reg = <0 0xe6510000 0 0x425>;
-                interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 323>;
-                dmas = <&dmac0 0x65>, <&dmac0 0x66>,
-                       <&dmac1 0x65>, <&dmac1 0x66>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 323>;
-                status = "disabled";
-        };
+                ipmmu_gp: mmu@e62a0000 {
+                        compatible = "renesas,ipmmu-r8a7791",
+                                     "renesas,ipmmu-vmsa";
+                        reg = <0 0xe62a0000 0 0x1000>;
+                        interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+                        #iommu-cells = <1>;
+                        status = "disabled";
+                };
 
-        pfc: pin-controller@e6060000 {
-                compatible = "renesas,pfc-r8a7791";
-                reg = <0 0xe6060000 0 0x250>;
-        };
+                icram0: sram@e63a0000 {
+                        compatible = "mmio-sram";
+                        reg = <0 0xe63a0000 0 0x12000>;
+                };
 
-        mmcif0: mmc@ee200000 {
-                compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif";
-                reg = <0 0xee200000 0 0x80>;
-                interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 315>;
-                dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
-                       <&dmac1 0xd1>, <&dmac1 0xd2>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 315>;
-                reg-io-width = <4>;
-                status = "disabled";
-                max-frequency = <97500000>;
-        };
+                icram1: sram@e63c0000 {
+                        compatible = "mmio-sram";
+                        reg = <0 0xe63c0000 0 0x1000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0 0xe63c0000 0x1000>;
 
-        sdhi0: sd@ee100000 {
-                compatible = "renesas,sdhi-r8a7791",
-                             "renesas,rcar-gen2-sdhi";
-                reg = <0 0xee100000 0 0x328>;
-                interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 314>;
-                dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
-                       <&dmac1 0xcd>, <&dmac1 0xce>;
-                dma-names = "tx", "rx", "tx", "rx";
-                max-frequency = <195000000>;
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 314>;
-                status = "disabled";
-        };
+                        smp-sram@0 {
+                                compatible = "renesas,smp-sram";
+                                reg = <0 0x10>;
+                        };
+                };
 
-        sdhi1: sd@ee140000 {
-                compatible = "renesas,sdhi-r8a7791",
-                             "renesas,rcar-gen2-sdhi";
-                reg = <0 0xee140000 0 0x100>;
-                interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 312>;
-                dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
-                       <&dmac1 0xc1>, <&dmac1 0xc2>;
-                dma-names = "tx", "rx", "tx", "rx";
-                max-frequency = <97500000>;
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 312>;
-                status = "disabled";
-        };
+                /* The memory map in the User's Manual maps the cores to
+                 * bus numbers
+                 */
+                i2c0: i2c@e6508000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a7791",
+                                     "renesas,rcar-gen2-i2c";
+                        reg = <0 0xe6508000 0 0x40>;
+                        interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 931>;
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 931>;
+                        i2c-scl-internal-delay-ns = <6>;
+                        status = "disabled";
+                };
 
-        sdhi2: sd@ee160000 {
-                compatible = "renesas,sdhi-r8a7791",
-                             "renesas,rcar-gen2-sdhi";
-                reg = <0 0xee160000 0 0x100>;
-                interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 311>;
-                dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
-                       <&dmac1 0xd3>, <&dmac1 0xd4>;
-                dma-names = "tx", "rx", "tx", "rx";
-                max-frequency = <97500000>;
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 311>;
-                status = "disabled";
-        };
+                i2c1: i2c@e6518000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a7791",
+                                     "renesas,rcar-gen2-i2c";
+                        reg = <0 0xe6518000 0 0x40>;
+                        interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 930>;
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 930>;
+                        i2c-scl-internal-delay-ns = <6>;
+                        status = "disabled";
+                };
 
-        scifa0: serial@e6c40000 {
-                compatible = "renesas,scifa-r8a7791",
-                             "renesas,rcar-gen2-scifa", "renesas,scifa";
-                reg = <0 0xe6c40000 0 64>;
-                interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 204>;
-                clock-names = "fck";
-                dmas = <&dmac0 0x21>, <&dmac0 0x22>,
-                       <&dmac1 0x21>, <&dmac1 0x22>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 204>;
-                status = "disabled";
-        };
+                i2c2: i2c@e6530000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a7791",
+                                     "renesas,rcar-gen2-i2c";
+                        reg = <0 0xe6530000 0 0x40>;
+                        interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 929>;
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 929>;
+                        i2c-scl-internal-delay-ns = <6>;
+                        status = "disabled";
+                };
 
-        scifa1: serial@e6c50000 {
-                compatible = "renesas,scifa-r8a7791",
-                             "renesas,rcar-gen2-scifa", "renesas,scifa";
-                reg = <0 0xe6c50000 0 64>;
-                interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 203>;
-                clock-names = "fck";
-                dmas = <&dmac0 0x25>, <&dmac0 0x26>,
-                       <&dmac1 0x25>, <&dmac1 0x26>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 203>;
-                status = "disabled";
-        };
+                i2c3: i2c@e6540000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a7791",
+                                     "renesas,rcar-gen2-i2c";
+                        reg = <0 0xe6540000 0 0x40>;
+                        interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 928>;
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 928>;
+                        i2c-scl-internal-delay-ns = <6>;
+                        status = "disabled";
+                };
 
-        scifa2: serial@e6c60000 {
-                compatible = "renesas,scifa-r8a7791",
-                             "renesas,rcar-gen2-scifa", "renesas,scifa";
-                reg = <0 0xe6c60000 0 64>;
-                interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 202>;
-                clock-names = "fck";
-                dmas = <&dmac0 0x27>, <&dmac0 0x28>,
-                       <&dmac1 0x27>, <&dmac1 0x28>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 202>;
-                status = "disabled";
-        };
+                i2c4: i2c@e6520000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a7791",
+                                     "renesas,rcar-gen2-i2c";
+                        reg = <0 0xe6520000 0 0x40>;
+                        interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 927>;
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 927>;
+                        i2c-scl-internal-delay-ns = <6>;
+                        status = "disabled";
+                };
 
-        scifa3: serial@e6c70000 {
-                compatible = "renesas,scifa-r8a7791",
-                             "renesas,rcar-gen2-scifa", "renesas,scifa";
-                reg = <0 0xe6c70000 0 64>;
-                interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 1106>;
-                clock-names = "fck";
-                dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
-                       <&dmac1 0x1b>, <&dmac1 0x1c>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 1106>;
-                status = "disabled";
-        };
+                i2c5: i2c@e6528000 {
+                        /* doesn't need pinmux */
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a7791",
+                                     "renesas,rcar-gen2-i2c";
+                        reg = <0 0xe6528000 0 0x40>;
+                        interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 925>;
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 925>;
+                        i2c-scl-internal-delay-ns = <110>;
+                        status = "disabled";
+                };
 
-        scifa4: serial@e6c78000 {
-                compatible = "renesas,scifa-r8a7791",
-                             "renesas,rcar-gen2-scifa", "renesas,scifa";
-                reg = <0 0xe6c78000 0 64>;
-                interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 1107>;
-                clock-names = "fck";
-                dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
-                       <&dmac1 0x1f>, <&dmac1 0x20>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 1107>;
-                status = "disabled";
-        };
+                i2c6: i2c@e60b0000 {
+                        /* doesn't need pinmux */
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,iic-r8a7791",
+                                     "renesas,rcar-gen2-iic",
+                                     "renesas,rmobile-iic";
+                        reg = <0 0xe60b0000 0 0x425>;
+                        interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 926>;
+                        dmas = <&dmac0 0x77>, <&dmac0 0x78>,
+                               <&dmac1 0x77>, <&dmac1 0x78>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 926>;
+                        status = "disabled";
+                };
 
-        scifa5: serial@e6c80000 {
-                compatible = "renesas,scifa-r8a7791",
-                             "renesas,rcar-gen2-scifa", "renesas,scifa";
-                reg = <0 0xe6c80000 0 64>;
-                interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 1108>;
-                clock-names = "fck";
-                dmas = <&dmac0 0x23>, <&dmac0 0x24>,
-                       <&dmac1 0x23>, <&dmac1 0x24>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 1108>;
-                status = "disabled";
-        };
+                i2c7: i2c@e6500000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,iic-r8a7791",
+                                     "renesas,rcar-gen2-iic",
+                                     "renesas,rmobile-iic";
+                        reg = <0 0xe6500000 0 0x425>;
+                        interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 318>;
+                        dmas = <&dmac0 0x61>, <&dmac0 0x62>,
+                               <&dmac1 0x61>, <&dmac1 0x62>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 318>;
+                        status = "disabled";
+                };
 
-        scifb0: serial@e6c20000 {
-                compatible = "renesas,scifb-r8a7791",
-                             "renesas,rcar-gen2-scifb", "renesas,scifb";
-                reg = <0 0xe6c20000 0 0x100>;
-                interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 206>;
-                clock-names = "fck";
-                dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
-                       <&dmac1 0x3d>, <&dmac1 0x3e>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 206>;
-                status = "disabled";
-        };
+                i2c8: i2c@e6510000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,iic-r8a7791",
+                                     "renesas,rcar-gen2-iic",
+                                     "renesas,rmobile-iic";
+                        reg = <0 0xe6510000 0 0x425>;
+                        interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 323>;
+                        dmas = <&dmac0 0x65>, <&dmac0 0x66>,
+                               <&dmac1 0x65>, <&dmac1 0x66>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 323>;
+                        status = "disabled";
+                };
 
-        scifb1: serial@e6c30000 {
-                compatible = "renesas,scifb-r8a7791",
-                             "renesas,rcar-gen2-scifb", "renesas,scifb";
-                reg = <0 0xe6c30000 0 0x100>;
-                interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 207>;
-                clock-names = "fck";
-                dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
-                       <&dmac1 0x19>, <&dmac1 0x1a>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 207>;
-                status = "disabled";
-        };
+                hsusb: usb@e6590000 {
+                        compatible = "renesas,usbhs-r8a7791",
+                                     "renesas,rcar-gen2-usbhs";
+                        reg = <0 0xe6590000 0 0x100>;
+                        interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 704>;
+                        dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
+                               <&usb_dmac1 0>, <&usb_dmac1 1>;
+                        dma-names = "ch0", "ch1", "ch2", "ch3";
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 704>;
+                        renesas,buswait = <4>;
+                        phys = <&usb0 1>;
+                        phy-names = "usb";
+                        status = "disabled";
+                };
 
-        scifb2: serial@e6ce0000 {
-                compatible = "renesas,scifb-r8a7791",
-                             "renesas,rcar-gen2-scifb", "renesas,scifb";
-                reg = <0 0xe6ce0000 0 0x100>;
-                interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 216>;
-                clock-names = "fck";
-                dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
-                       <&dmac1 0x1d>, <&dmac1 0x1e>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 216>;
-                status = "disabled";
-        };
+                usbphy: usb-phy@e6590100 {
+                        compatible = "renesas,usb-phy-r8a7791",
+                                     "renesas,rcar-gen2-usb-phy";
+                        reg = <0 0xe6590100 0 0x100>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&cpg CPG_MOD 704>;
+                        clock-names = "usbhs";
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 704>;
+                        status = "disabled";
 
-        scif0: serial@e6e60000 {
-                compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
-                             "renesas,scif";
-                reg = <0 0xe6e60000 0 64>;
-                interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
-                         <&scif_clk>;
-                clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
-                       <&dmac1 0x29>, <&dmac1 0x2a>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 721>;
-                status = "disabled";
-        };
+                        usb0: usb-channel@0 {
+                                reg = <0>;
+                                #phy-cells = <1>;
+                        };
+                        usb2: usb-channel@2 {
+                                reg = <2>;
+                                #phy-cells = <1>;
+                        };
+                };
 
-        scif1: serial@e6e68000 {
-                compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
-                             "renesas,scif";
-                reg = <0 0xe6e68000 0 64>;
-                interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
-                         <&scif_clk>;
-                clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
-                       <&dmac1 0x2d>, <&dmac1 0x2e>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 720>;
-                status = "disabled";
-        };
+                usb_dmac0: dma-controller@e65a0000 {
+                        compatible = "renesas,r8a7791-usb-dmac",
+                                     "renesas,usb-dmac";
+                        reg = <0 0xe65a0000 0 0x100>;
+                        interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "ch0", "ch1";
+                        clocks = <&cpg CPG_MOD 330>;
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 330>;
+                        #dma-cells = <1>;
+                        dma-channels = <2>;
+                };
 
-        adc: adc@e6e54000 {
-                compatible = "renesas,r8a7791-gyroadc", "renesas,rcar-gyroadc";
-                reg = <0 0xe6e54000 0 64>;
-                clocks = <&cpg CPG_MOD 901>;
-                clock-names = "fck";
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 901>;
-                status = "disabled";
-        };
+                usb_dmac1: dma-controller@e65b0000 {
+                        compatible = "renesas,r8a7791-usb-dmac",
+                                     "renesas,usb-dmac";
+                        reg = <0 0xe65b0000 0 0x100>;
+                        interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "ch0", "ch1";
+                        clocks = <&cpg CPG_MOD 331>;
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 331>;
+                        #dma-cells = <1>;
+                        dma-channels = <2>;
+                };
 
-        scif2: serial@e6e58000 {
-                compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
-                             "renesas,scif";
-                reg = <0 0xe6e58000 0 64>;
-                interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
-                         <&scif_clk>;
-                clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
-                       <&dmac1 0x2b>, <&dmac1 0x2c>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 719>;
-                status = "disabled";
-        };
+                dmac0: dma-controller@e6700000 {
+                        compatible = "renesas,dmac-r8a7791",
+                                     "renesas,rcar-dmac";
+                        reg = <0 0xe6700000 0 0x20000>;
+                        interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "error",
+                                          "ch0", "ch1", "ch2", "ch3",
+                                          "ch4", "ch5", "ch6", "ch7",
+                                          "ch8", "ch9", "ch10", "ch11",
+                                          "ch12", "ch13", "ch14";
+                        clocks = <&cpg CPG_MOD 219>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 219>;
+                        #dma-cells = <1>;
+                        dma-channels = <15>;
+                };
 
-        scif3: serial@e6ea8000 {
-                compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
-                             "renesas,scif";
-                reg = <0 0xe6ea8000 0 64>;
-                interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
-                         <&scif_clk>;
-                clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
-                       <&dmac1 0x2f>, <&dmac1 0x30>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 718>;
-                status = "disabled";
-        };
+                dmac1: dma-controller@e6720000 {
+                        compatible = "renesas,dmac-r8a7791",
+                                     "renesas,rcar-dmac";
+                        reg = <0 0xe6720000 0 0x20000>;
+                        interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "error",
+                                          "ch0", "ch1", "ch2", "ch3",
+                                          "ch4", "ch5", "ch6", "ch7",
+                                          "ch8", "ch9", "ch10", "ch11",
+                                          "ch12", "ch13", "ch14";
+                        clocks = <&cpg CPG_MOD 218>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 218>;
+                        #dma-cells = <1>;
+                        dma-channels = <15>;
+                };
 
-        scif4: serial@e6ee0000 {
-                compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
-                             "renesas,scif";
-                reg = <0 0xe6ee0000 0 64>;
-                interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
-                         <&scif_clk>;
-                clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
-                       <&dmac1 0xfb>, <&dmac1 0xfc>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 715>;
-                status = "disabled";
-        };
+                avb: ethernet@e6800000 {
+                        compatible = "renesas,etheravb-r8a7791",
+                                     "renesas,etheravb-rcar-gen2";
+                        reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
+                        interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 812>;
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 812>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
 
-        scif5: serial@e6ee8000 {
-                compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
-                             "renesas,scif";
-                reg = <0 0xe6ee8000 0 64>;
-                interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
-                         <&scif_clk>;
-                clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
-                       <&dmac1 0xfd>, <&dmac1 0xfe>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 714>;
-                status = "disabled";
-        };
+                qspi: spi@e6b10000 {
+                        compatible = "renesas,qspi-r8a7791", "renesas,qspi";
+                        reg = <0 0xe6b10000 0 0x2c>;
+                        interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 917>;
+                        dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+                               <&dmac1 0x17>, <&dmac1 0x18>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 917>;
+                        num-cs = <1>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
 
-        hscif0: serial@e62c0000 {
-                compatible = "renesas,hscif-r8a7791",
-                             "renesas,rcar-gen2-hscif", "renesas,hscif";
-                reg = <0 0xe62c0000 0 96>;
-                interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
-                         <&scif_clk>;
-                clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
-                       <&dmac1 0x39>, <&dmac1 0x3a>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 717>;
-                status = "disabled";
-        };
+                scifa0: serial@e6c40000 {
+                        compatible = "renesas,scifa-r8a7791",
+                                     "renesas,rcar-gen2-scifa", "renesas,scifa";
+                        reg = <0 0xe6c40000 0 64>;
+                        interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 204>;
+                        clock-names = "fck";
+                        dmas = <&dmac0 0x21>, <&dmac0 0x22>,
+                               <&dmac1 0x21>, <&dmac1 0x22>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 204>;
+                        status = "disabled";
+                };
 
-        hscif1: serial@e62c8000 {
-                compatible = "renesas,hscif-r8a7791",
-                             "renesas,rcar-gen2-hscif", "renesas,hscif";
-                reg = <0 0xe62c8000 0 96>;
-                interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
-                         <&scif_clk>;
-                clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
-                       <&dmac1 0x4d>, <&dmac1 0x4e>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 716>;
-                status = "disabled";
-        };
+                scifa1: serial@e6c50000 {
+                        compatible = "renesas,scifa-r8a7791",
+                                     "renesas,rcar-gen2-scifa", "renesas,scifa";
+                        reg = <0 0xe6c50000 0 64>;
+                        interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 203>;
+                        clock-names = "fck";
+                        dmas = <&dmac0 0x25>, <&dmac0 0x26>,
+                               <&dmac1 0x25>, <&dmac1 0x26>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 203>;
+                        status = "disabled";
+                };
 
-        hscif2: serial@e62d0000 {
-                compatible = "renesas,hscif-r8a7791",
-                             "renesas,rcar-gen2-hscif", "renesas,hscif";
-                reg = <0 0xe62d0000 0 96>;
-                interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
-                         <&scif_clk>;
-                clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
-                       <&dmac1 0x3b>, <&dmac1 0x3c>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 713>;
-                status = "disabled";
-        };
+                scifa2: serial@e6c60000 {
+                        compatible = "renesas,scifa-r8a7791",
+                                     "renesas,rcar-gen2-scifa", "renesas,scifa";
+                        reg = <0 0xe6c60000 0 64>;
+                        interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 202>;
+                        clock-names = "fck";
+                        dmas = <&dmac0 0x27>, <&dmac0 0x28>,
+                               <&dmac1 0x27>, <&dmac1 0x28>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 202>;
+                        status = "disabled";
+                };
 
-        icram0: sram@e63a0000 {
-                compatible = "mmio-sram";
-                reg = <0 0xe63a0000 0 0x12000>;
-        };
+                scifa3: serial@e6c70000 {
+                        compatible = "renesas,scifa-r8a7791",
+                                     "renesas,rcar-gen2-scifa", "renesas,scifa";
+                        reg = <0 0xe6c70000 0 64>;
+                        interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 1106>;
+                        clock-names = "fck";
+                        dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
+                               <&dmac1 0x1b>, <&dmac1 0x1c>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 1106>;
+                        status = "disabled";
+                };
 
-        icram1: sram@e63c0000 {
-                compatible = "mmio-sram";
-                reg = <0 0xe63c0000 0 0x1000>;
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges = <0 0 0xe63c0000 0x1000>;
+                scifa4: serial@e6c78000 {
+                        compatible = "renesas,scifa-r8a7791",
+                                     "renesas,rcar-gen2-scifa", "renesas,scifa";
+                        reg = <0 0xe6c78000 0 64>;
+                        interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 1107>;
+                        clock-names = "fck";
+                        dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
+                               <&dmac1 0x1f>, <&dmac1 0x20>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 1107>;
+                        status = "disabled";
+                };
 
-                smp-sram@0 {
-                        compatible = "renesas,smp-sram";
-                        reg = <0 0x10>;
+                scifa5: serial@e6c80000 {
+                        compatible = "renesas,scifa-r8a7791",
+                                     "renesas,rcar-gen2-scifa", "renesas,scifa";
+                        reg = <0 0xe6c80000 0 64>;
+                        interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 1108>;
+                        clock-names = "fck";
+                        dmas = <&dmac0 0x23>, <&dmac0 0x24>,
+                               <&dmac1 0x23>, <&dmac1 0x24>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 1108>;
+                        status = "disabled";
                 };
-        };
 
-        ether: ethernet@ee700000 {
-                compatible = "renesas,ether-r8a7791",
-                             "renesas,rcar-gen2-ether";
-                reg = <0 0xee700000 0 0x400>;
-                interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 813>;
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 813>;
-                phy-mode = "rmii";
-                #address-cells = <1>;
-                #size-cells = <0>;
-                status = "disabled";
-        };
+                scifb0: serial@e6c20000 {
+                        compatible = "renesas,scifb-r8a7791",
+                                     "renesas,rcar-gen2-scifb", "renesas,scifb";
+                        reg = <0 0xe6c20000 0 0x100>;
+                        interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 206>;
+                        clock-names = "fck";
+                        dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
+                               <&dmac1 0x3d>, <&dmac1 0x3e>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 206>;
+                        status = "disabled";
+                };
 
-        avb: ethernet@e6800000 {
-                compatible = "renesas,etheravb-r8a7791",
-                             "renesas,etheravb-rcar-gen2";
-                reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
-                interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 812>;
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 812>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                status = "disabled";
-        };
+                scifb1: serial@e6c30000 {
+                        compatible = "renesas,scifb-r8a7791",
+                                     "renesas,rcar-gen2-scifb", "renesas,scifb";
+                        reg = <0 0xe6c30000 0 0x100>;
+                        interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 207>;
+                        clock-names = "fck";
+                        dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
+                               <&dmac1 0x19>, <&dmac1 0x1a>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 207>;
+                        status = "disabled";
+                };
 
-        sata0: sata@ee300000 {
-                compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata";
-                reg = <0 0xee300000 0 0x2000>;
-                interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 815>;
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 815>;
-                status = "disabled";
-        };
+                scifb2: serial@e6ce0000 {
+                        compatible = "renesas,scifb-r8a7791",
+                                     "renesas,rcar-gen2-scifb", "renesas,scifb";
+                        reg = <0 0xe6ce0000 0 0x100>;
+                        interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 216>;
+                        clock-names = "fck";
+                        dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
+                               <&dmac1 0x1d>, <&dmac1 0x1e>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 216>;
+                        status = "disabled";
+                };
 
-        sata1: sata@ee500000 {
-                compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata";
-                reg = <0 0xee500000 0 0x2000>;
-                interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 814>;
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 814>;
-                status = "disabled";
-        };
+                scif0: serial@e6e60000 {
+                        compatible = "renesas,scif-r8a7791",
+                                     "renesas,rcar-gen2-scif", "renesas,scif";
+                        reg = <0 0xe6e60000 0 64>;
+                        interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+                               <&dmac1 0x29>, <&dmac1 0x2a>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 721>;
+                        status = "disabled";
+                };
 
-        hsusb: usb@e6590000 {
-                compatible = "renesas,usbhs-r8a7791", "renesas,rcar-gen2-usbhs";
-                reg = <0 0xe6590000 0 0x100>;
-                interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 704>;
-                dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
-                       <&usb_dmac1 0>, <&usb_dmac1 1>;
-                dma-names = "ch0", "ch1", "ch2", "ch3";
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 704>;
-                renesas,buswait = <4>;
-                phys = <&usb0 1>;
-                phy-names = "usb";
-                status = "disabled";
-        };
+                scif1: serial@e6e68000 {
+                        compatible = "renesas,scif-r8a7791",
+                                     "renesas,rcar-gen2-scif", "renesas,scif";
+                        reg = <0 0xe6e68000 0 64>;
+                        interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+                               <&dmac1 0x2d>, <&dmac1 0x2e>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 720>;
+                        status = "disabled";
+                };
 
-        usbphy: usb-phy@e6590100 {
-                compatible = "renesas,usb-phy-r8a7791",
-                             "renesas,rcar-gen2-usb-phy";
-                reg = <0 0xe6590100 0 0x100>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                clocks = <&cpg CPG_MOD 704>;
-                clock-names = "usbhs";
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 704>;
-                status = "disabled";
+                scif2: serial@e6e58000 {
+                        compatible = "renesas,scif-r8a7791",
+                                     "renesas,rcar-gen2-scif", "renesas,scif";
+                        reg = <0 0xe6e58000 0 64>;
+                        interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+                               <&dmac1 0x2b>, <&dmac1 0x2c>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 719>;
+                        status = "disabled";
+                };
 
-                usb0: usb-channel@0 {
-                        reg = <0>;
-                        #phy-cells = <1>;
+                scif3: serial@e6ea8000 {
+                        compatible = "renesas,scif-r8a7791",
+                                     "renesas,rcar-gen2-scif", "renesas,scif";
+                        reg = <0 0xe6ea8000 0 64>;
+                        interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
+                               <&dmac1 0x2f>, <&dmac1 0x30>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 718>;
+                        status = "disabled";
                 };
-                usb2: usb-channel@2 {
-                        reg = <2>;
-                        #phy-cells = <1>;
+
+                scif4: serial@e6ee0000 {
+                        compatible = "renesas,scif-r8a7791",
+                                     "renesas,rcar-gen2-scif", "renesas,scif";
+                        reg = <0 0xe6ee0000 0 64>;
+                        interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
+                               <&dmac1 0xfb>, <&dmac1 0xfc>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 715>;
+                        status = "disabled";
                 };
-        };
 
-        vin0: video@e6ef0000 {
-                compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin";
-                reg = <0 0xe6ef0000 0 0x1000>;
-                interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 811>;
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 811>;
-                status = "disabled";
-        };
+                scif5: serial@e6ee8000 {
+                        compatible = "renesas,scif-r8a7791",
+                                     "renesas,rcar-gen2-scif", "renesas,scif";
+                        reg = <0 0xe6ee8000 0 64>;
+                        interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
+                               <&dmac1 0xfd>, <&dmac1 0xfe>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 714>;
+                        status = "disabled";
+                };
 
-        vin1: video@e6ef1000 {
-                compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin";
-                reg = <0 0xe6ef1000 0 0x1000>;
-                interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 810>;
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 810>;
-                status = "disabled";
-        };
+                hscif0: serial@e62c0000 {
+                        compatible = "renesas,hscif-r8a7791",
+                                     "renesas,rcar-gen2-hscif", "renesas,hscif";
+                        reg = <0 0xe62c0000 0 96>;
+                        interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+                               <&dmac1 0x39>, <&dmac1 0x3a>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 717>;
+                        status = "disabled";
+                };
 
-        vin2: video@e6ef2000 {
-                compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin";
-                reg = <0 0xe6ef2000 0 0x1000>;
-                interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 809>;
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 809>;
-                status = "disabled";
-        };
+                hscif1: serial@e62c8000 {
+                        compatible = "renesas,hscif-r8a7791",
+                                     "renesas,rcar-gen2-hscif", "renesas,hscif";
+                        reg = <0 0xe62c8000 0 96>;
+                        interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+                               <&dmac1 0x4d>, <&dmac1 0x4e>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 716>;
+                        status = "disabled";
+                };
 
-        vsp@fe928000 {
-                compatible = "renesas,vsp1";
-                reg = <0 0xfe928000 0 0x8000>;
-                interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 131>;
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 131>;
-        };
+                hscif2: serial@e62d0000 {
+                        compatible = "renesas,hscif-r8a7791",
+                                     "renesas,rcar-gen2-hscif", "renesas,hscif";
+                        reg = <0 0xe62d0000 0 96>;
+                        interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
+                               <&dmac1 0x3b>, <&dmac1 0x3c>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 713>;
+                        status = "disabled";
+                };
 
-        vsp@fe930000 {
-                compatible = "renesas,vsp1";
-                reg = <0 0xfe930000 0 0x8000>;
-                interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 128>;
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 128>;
-        };
+                msiof0: spi@e6e20000 {
+                        compatible = "renesas,msiof-r8a7791",
+                                     "renesas,rcar-gen2-msiof";
+                        reg = <0 0xe6e20000 0 0x0064>;
+                        interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 000>;
+                        dmas = <&dmac0 0x51>, <&dmac0 0x52>,
+                               <&dmac1 0x51>, <&dmac1 0x52>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
 
-        vsp@fe938000 {
-                compatible = "renesas,vsp1";
-                reg = <0 0xfe938000 0 0x8000>;
-                interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 127>;
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 127>;
-        };
+                msiof1: spi@e6e10000 {
+                        compatible = "renesas,msiof-r8a7791",
+                                     "renesas,rcar-gen2-msiof";
+                        reg = <0 0xe6e10000 0 0x0064>;
+                        interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 208>;
+                        dmas = <&dmac0 0x55>, <&dmac0 0x56>,
+                               <&dmac1 0x55>, <&dmac1 0x56>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 208>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
 
-        du: display@feb00000 {
-                compatible = "renesas,du-r8a7791";
-                reg = <0 0xfeb00000 0 0x40000>,
-                      <0 0xfeb90000 0 0x1c>;
-                reg-names = "du", "lvds.0";
-                interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 724>,
-                         <&cpg CPG_MOD 723>,
-                         <&cpg CPG_MOD 726>;
-                clock-names = "du.0", "du.1", "lvds.0";
-                status = "disabled";
-
-                ports {
+                msiof2: spi@e6e00000 {
+                        compatible = "renesas,msiof-r8a7791",
+                                     "renesas,rcar-gen2-msiof";
+                        reg = <0 0xe6e00000 0 0x0064>;
+                        interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 205>;
+                        dmas = <&dmac0 0x41>, <&dmac0 0x42>,
+                               <&dmac1 0x41>, <&dmac1 0x42>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 205>;
                         #address-cells = <1>;
                         #size-cells = <0>;
+                        status = "disabled";
+                };
 
-                        port@0 {
-                                reg = <0>;
-                                du_out_rgb: endpoint {
-                                };
-                        };
-                        port@1 {
-                                reg = <1>;
-                                du_out_lvds0: endpoint {
-                                };
-                        };
+                adc: adc@e6e54000 {
+                        compatible = "renesas,r8a7791-gyroadc",
+                                     "renesas,rcar-gyroadc";
+                        reg = <0 0xe6e54000 0 64>;
+                        clocks = <&cpg CPG_MOD 901>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 901>;
+                        status = "disabled";
                 };
-        };
 
-        can0: can@e6e80000 {
-                compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";
-                reg = <0 0xe6e80000 0 0x1000>;
-                interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7791_CLK_RCAN>,
-                         <&can_clk>;
-                clock-names = "clkp1", "clkp2", "can_clk";
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 916>;
-                status = "disabled";
-        };
+                can0: can@e6e80000 {
+                        compatible = "renesas,can-r8a7791",
+                                     "renesas,rcar-gen2-can";
+                        reg = <0 0xe6e80000 0 0x1000>;
+                        interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 916>,
+                                 <&cpg CPG_CORE R8A7791_CLK_RCAN>, <&can_clk>;
+                        clock-names = "clkp1", "clkp2", "can_clk";
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 916>;
+                        status = "disabled";
+                };
 
-        can1: can@e6e88000 {
-                compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";
-                reg = <0 0xe6e88000 0 0x1000>;
-                interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7791_CLK_RCAN>,
-                         <&can_clk>;
-                clock-names = "clkp1", "clkp2", "can_clk";
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 915>;
-                status = "disabled";
-        };
+                can1: can@e6e88000 {
+                        compatible = "renesas,can-r8a7791",
+                                     "renesas,rcar-gen2-can";
+                        reg = <0 0xe6e88000 0 0x1000>;
+                        interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 915>,
+                                 <&cpg CPG_CORE R8A7791_CLK_RCAN>, <&can_clk>;
+                        clock-names = "clkp1", "clkp2", "can_clk";
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 915>;
+                        status = "disabled";
+                };
 
-        jpu: jpeg-codec@fe980000 {
-                compatible = "renesas,jpu-r8a7791", "renesas,rcar-gen2-jpu";
-                reg = <0 0xfe980000 0 0x10300>;
-                interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 106>;
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 106>;
-        };
+                vin0: video@e6ef0000 {
+                        compatible = "renesas,vin-r8a7791",
+                                     "renesas,rcar-gen2-vin";
+                        reg = <0 0xe6ef0000 0 0x1000>;
+                        interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 811>;
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 811>;
+                        status = "disabled";
+                };
 
-        /* External root clock */
-        extal_clk: extal {
-                compatible = "fixed-clock";
-                #clock-cells = <0>;
-                /* This value must be overridden by the board. */
-                clock-frequency = <0>;
-        };
+                vin1: video@e6ef1000 {
+                        compatible = "renesas,vin-r8a7791",
+                                     "renesas,rcar-gen2-vin";
+                        reg = <0 0xe6ef1000 0 0x1000>;
+                        interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 810>;
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 810>;
+                        status = "disabled";
+                };
 
-        /*
-         * The external audio clocks are configured as 0 Hz fixed frequency
-         * clocks by default.
-         * Boards that provide audio clocks should override them.
-         */
-        audio_clk_a: audio_clk_a {
-                compatible = "fixed-clock";
-                #clock-cells = <0>;
-                clock-frequency = <0>;
-        };
-        audio_clk_b: audio_clk_b {
-                compatible = "fixed-clock";
-                #clock-cells = <0>;
-                clock-frequency = <0>;
-        };
-        audio_clk_c: audio_clk_c {
-                compatible = "fixed-clock";
-                #clock-cells = <0>;
-                clock-frequency = <0>;
-        };
+                vin2: video@e6ef2000 {
+                        compatible = "renesas,vin-r8a7791",
+                                     "renesas,rcar-gen2-vin";
+                        reg = <0 0xe6ef2000 0 0x1000>;
+                        interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 809>;
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 809>;
+                        status = "disabled";
+                };
 
-        /* External PCIe clock - can be overridden by the board */
-        pcie_bus_clk: pcie_bus {
-                compatible = "fixed-clock";
-                #clock-cells = <0>;
-                clock-frequency = <0>;
-        };
+                rcar_sound: sound@ec500000 {
+                        /*
+                         * #sound-dai-cells is required
+                         *
+                         * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
+                         * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
+                         */
+                        compatible = "renesas,rcar_sound-r8a7791",
+                                     "renesas,rcar_sound-gen2";
+                        reg = <0 0xec500000 0 0x1000>, /* SCU */
+                              <0 0xec5a0000 0 0x100>,  /* ADG */
+                              <0 0xec540000 0 0x1000>, /* SSIU */
+                              <0 0xec541000 0 0x280>,  /* SSI */
+                              <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
+                        reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+                        clocks = <&cpg CPG_MOD 1005>,
+                                 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+                                 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+                                 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+                                 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+                                 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+                                 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+                                 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+                                 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+                                 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+                                 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+                                 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
+                                 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
+                                 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+                                 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
+                                 <&cpg CPG_CORE R8A7791_CLK_M2>;
+                        clock-names = "ssi-all",
+                                      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+                                      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+                                      "ssi.1", "ssi.0", "src.9", "src.8",
+                                      "src.7", "src.6", "src.5", "src.4",
+                                      "src.3", "src.2", "src.1", "src.0",
+                                      "ctu.0", "ctu.1",
+                                      "mix.0", "mix.1",
+                                      "dvc.0", "dvc.1",
+                                      "clk_a", "clk_b", "clk_c", "clk_i";
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 1005>,
+                                 <&cpg 1006>, <&cpg 1007>,
+                                 <&cpg 1008>, <&cpg 1009>,
+                                 <&cpg 1010>, <&cpg 1011>,
+                                 <&cpg 1012>, <&cpg 1013>,
+                                 <&cpg 1014>, <&cpg 1015>;
+                        reset-names = "ssi-all",
+                                      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+                                      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+                                      "ssi.1", "ssi.0";
+
+                        status = "disabled";
+
+                        rcar_sound,dvc {
+                                dvc0: dvc-0 {
+                                        dmas = <&audma1 0xbc>;
+                                        dma-names = "tx";
+                                };
+                                dvc1: dvc-1 {
+                                        dmas = <&audma1 0xbe>;
+                                        dma-names = "tx";
+                                };
+                        };
 
-        /* External SCIF clock */
-        scif_clk: scif {
-                compatible = "fixed-clock";
-                #clock-cells = <0>;
-                /* This value must be overridden by the board. */
-                clock-frequency = <0>;
-        };
+                        rcar_sound,mix {
+                                mix0: mix-0 { };
+                                mix1: mix-1 { };
+                        };
 
-        /* External USB clock - can be overridden by the board */
-        usb_extal_clk: usb_extal {
-                compatible = "fixed-clock";
-                #clock-cells = <0>;
-                clock-frequency = <48000000>;
-        };
+                        rcar_sound,ctu {
+                                ctu00: ctu-0 { };
+                                ctu01: ctu-1 { };
+                                ctu02: ctu-2 { };
+                                ctu03: ctu-3 { };
+                                ctu10: ctu-4 { };
+                                ctu11: ctu-5 { };
+                                ctu12: ctu-6 { };
+                                ctu13: ctu-7 { };
+                        };
 
-        /* External CAN clock */
-        can_clk: can {
-                compatible = "fixed-clock";
-                #clock-cells = <0>;
-                /* This value must be overridden by the board. */
-                clock-frequency = <0>;
-        };
+                        rcar_sound,src {
+                                src0: src-0 {
+                                        interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x85>, <&audma1 0x9a>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src1: src-1 {
+                                        interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x87>, <&audma1 0x9c>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src2: src-2 {
+                                        interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x89>, <&audma1 0x9e>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src3: src-3 {
+                                        interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x8b>, <&audma1 0xa0>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src4: src-4 {
+                                        interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x8d>, <&audma1 0xb0>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src5: src-5 {
+                                        interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x8f>, <&audma1 0xb2>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src6: src-6 {
+                                        interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x91>, <&audma1 0xb4>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src7: src-7 {
+                                        interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x93>, <&audma1 0xb6>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src8: src-8 {
+                                        interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x95>, <&audma1 0xb8>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src9: src-9 {
+                                        interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x97>, <&audma1 0xba>;
+                                        dma-names = "rx", "tx";
+                                };
+                        };
 
-        cpg: clock-controller@e6150000 {
-                compatible = "renesas,r8a7791-cpg-mssr";
-                reg = <0 0xe6150000 0 0x1000>;
-                clocks = <&extal_clk>, <&usb_extal_clk>;
-                clock-names = "extal", "usb_extal";
-                #clock-cells = <2>;
-                #power-domain-cells = <0>;
-                #reset-cells = <1>;
-        };
+                        rcar_sound,ssi {
+                                ssi0: ssi-0 {
+                                        interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x01>, <&audma1 0x02>,
+                                               <&audma0 0x15>, <&audma1 0x16>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi1: ssi-1 {
+                                         interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x03>, <&audma1 0x04>,
+                                               <&audma0 0x49>, <&audma1 0x4a>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi2: ssi-2 {
+                                        interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x05>, <&audma1 0x06>,
+                                               <&audma0 0x63>, <&audma1 0x64>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi3: ssi-3 {
+                                        interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x07>, <&audma1 0x08>,
+                                               <&audma0 0x6f>, <&audma1 0x70>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi4: ssi-4 {
+                                        interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x09>, <&audma1 0x0a>,
+                                               <&audma0 0x71>, <&audma1 0x72>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi5: ssi-5 {
+                                        interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x0b>, <&audma1 0x0c>,
+                                               <&audma0 0x73>, <&audma1 0x74>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi6: ssi-6 {
+                                        interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x0d>, <&audma1 0x0e>,
+                                               <&audma0 0x75>, <&audma1 0x76>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi7: ssi-7 {
+                                        interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x0f>, <&audma1 0x10>,
+                                               <&audma0 0x79>, <&audma1 0x7a>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi8: ssi-8 {
+                                        interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x11>, <&audma1 0x12>,
+                                               <&audma0 0x7b>, <&audma1 0x7c>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi9: ssi-9 {
+                                        interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x13>, <&audma1 0x14>,
+                                               <&audma0 0x7d>, <&audma1 0x7e>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                        };
+                };
 
-        rst: reset-controller@e6160000 {
-                compatible = "renesas,r8a7791-rst";
-                reg = <0 0xe6160000 0 0x0100>;
-        };
+                audma0: dma-controller@ec700000 {
+                        compatible = "renesas,dmac-r8a7791",
+                                     "renesas,rcar-dmac";
+                        reg = <0 0xec700000 0 0x10000>;
+                        interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "error",
+                                          "ch0", "ch1", "ch2", "ch3",
+                                          "ch4", "ch5", "ch6", "ch7",
+                                          "ch8", "ch9", "ch10", "ch11",
+                                          "ch12";
+                        clocks = <&cpg CPG_MOD 502>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 502>;
+                        #dma-cells = <1>;
+                        dma-channels = <13>;
+                };
 
-        prr: chipid@ff000044 {
-                compatible = "renesas,prr";
-                reg = <0 0xff000044 0 4>;
-        };
+                audma1: dma-controller@ec720000 {
+                        compatible = "renesas,dmac-r8a7791",
+                                     "renesas,rcar-dmac";
+                        reg = <0 0xec720000 0 0x10000>;
+                        interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "error",
+                                          "ch0", "ch1", "ch2", "ch3",
+                                          "ch4", "ch5", "ch6", "ch7",
+                                          "ch8", "ch9", "ch10", "ch11",
+                                          "ch12";
+                        clocks = <&cpg CPG_MOD 501>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 501>;
+                        #dma-cells = <1>;
+                        dma-channels = <13>;
+                };
 
-        sysc: system-controller@e6180000 {
-                compatible = "renesas,r8a7791-sysc";
-                reg = <0 0xe6180000 0 0x0200>;
-                #power-domain-cells = <1>;
-        };
+                xhci: usb@ee000000 {
+                        compatible = "renesas,xhci-r8a7791",
+                                     "renesas,rcar-gen2-xhci";
+                        reg = <0 0xee000000 0 0xc00>;
+                        interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 328>;
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 328>;
+                        phys = <&usb2 1>;
+                        phy-names = "usb";
+                        status = "disabled";
+                };
 
-        qspi: spi@e6b10000 {
-                compatible = "renesas,qspi-r8a7791", "renesas,qspi";
-                reg = <0 0xe6b10000 0 0x2c>;
-                interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 917>;
-                dmas = <&dmac0 0x17>, <&dmac0 0x18>,
-                       <&dmac1 0x17>, <&dmac1 0x18>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 917>;
-                num-cs = <1>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                status = "disabled";
-        };
+                pci0: pci@ee090000 {
+                        compatible = "renesas,pci-r8a7791",
+                                     "renesas,pci-rcar-gen2";
+                        device_type = "pci";
+                        reg = <0 0xee090000 0 0xc00>,
+                              <0 0xee080000 0 0x1100>;
+                        interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 703>;
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 703>;
+                        status = "disabled";
+
+                        bus-range = <0 0>;
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        #interrupt-cells = <1>;
+                        ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
+                        interrupt-map-mask = <0xff00 0 0 0x7>;
+                        interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+                                         0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+                                         0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+
+                        usb@1,0 {
+                                reg = <0x800 0 0 0 0>;
+                                phys = <&usb0 0>;
+                                phy-names = "usb";
+                        };
 
-        msiof0: spi@e6e20000 {
-                compatible = "renesas,msiof-r8a7791",
-                             "renesas,rcar-gen2-msiof";
-                reg = <0 0xe6e20000 0 0x0064>;
-                interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 000>;
-                dmas = <&dmac0 0x51>, <&dmac0 0x52>,
-                       <&dmac1 0x51>, <&dmac1 0x52>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                status = "disabled";
-        };
+                        usb@2,0 {
+                                reg = <0x1000 0 0 0 0>;
+                                phys = <&usb0 0>;
+                                phy-names = "usb";
+                        };
+                };
 
-        msiof1: spi@e6e10000 {
-                compatible = "renesas,msiof-r8a7791",
-                             "renesas,rcar-gen2-msiof";
-                reg = <0 0xe6e10000 0 0x0064>;
-                interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 208>;
-                dmas = <&dmac0 0x55>, <&dmac0 0x56>,
-                       <&dmac1 0x55>, <&dmac1 0x56>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 208>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                status = "disabled";
-        };
+                pci1: pci@ee0d0000 {
+                        compatible = "renesas,pci-r8a7791",
+                                     "renesas,pci-rcar-gen2";
+                        device_type = "pci";
+                        reg = <0 0xee0d0000 0 0xc00>,
+                              <0 0xee0c0000 0 0x1100>;
+                        interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 703>;
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 703>;
+                        status = "disabled";
+
+                        bus-range = <1 1>;
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        #interrupt-cells = <1>;
+                        ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
+                        interrupt-map-mask = <0xff00 0 0 0x7>;
+                        interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+                                         0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+                                         0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+
+                        usb@1,0 {
+                                reg = <0x10800 0 0 0 0>;
+                                phys = <&usb2 0>;
+                                phy-names = "usb";
+                        };
 
-        msiof2: spi@e6e00000 {
-                compatible = "renesas,msiof-r8a7791",
-                             "renesas,rcar-gen2-msiof";
-                reg = <0 0xe6e00000 0 0x0064>;
-                interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 205>;
-                dmas = <&dmac0 0x41>, <&dmac0 0x42>,
-                       <&dmac1 0x41>, <&dmac1 0x42>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 205>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                status = "disabled";
-        };
+                        usb@2,0 {
+                                reg = <0x11000 0 0 0 0>;
+                                phys = <&usb2 0>;
+                                phy-names = "usb";
+                        };
+                };
 
-        xhci: usb@ee000000 {
-                compatible = "renesas,xhci-r8a7791", "renesas,rcar-gen2-xhci";
-                reg = <0 0xee000000 0 0xc00>;
-                interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 328>;
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 328>;
-                phys = <&usb2 1>;
-                phy-names = "usb";
-                status = "disabled";
-        };
+                sdhi0: sd@ee100000 {
+                        compatible = "renesas,sdhi-r8a7791",
+                                     "renesas,rcar-gen2-sdhi";
+                        reg = <0 0xee100000 0 0x328>;
+                        interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 314>;
+                        dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+                               <&dmac1 0xcd>, <&dmac1 0xce>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        max-frequency = <195000000>;
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 314>;
+                        status = "disabled";
+                };
 
-        pci0: pci@ee090000 {
-                compatible = "renesas,pci-r8a7791", "renesas,pci-rcar-gen2";
-                device_type = "pci";
-                reg = <0 0xee090000 0 0xc00>,
-                      <0 0xee080000 0 0x1100>;
-                interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 703>;
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 703>;
-                status = "disabled";
-
-                bus-range = <0 0>;
-                #address-cells = <3>;
-                #size-cells = <2>;
-                #interrupt-cells = <1>;
-                ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
-                interrupt-map-mask = <0xff00 0 0 0x7>;
-                interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
-                                 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
-                                 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-
-                usb@1,0 {
-                        reg = <0x800 0 0 0 0>;
-                        phys = <&usb0 0>;
-                        phy-names = "usb";
+                sdhi1: sd@ee140000 {
+                        compatible = "renesas,sdhi-r8a7791",
+                                     "renesas,rcar-gen2-sdhi";
+                        reg = <0 0xee140000 0 0x100>;
+                        interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 312>;
+                        dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+                               <&dmac1 0xc1>, <&dmac1 0xc2>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        max-frequency = <97500000>;
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 312>;
+                        status = "disabled";
                 };
 
-                usb@2,0 {
-                        reg = <0x1000 0 0 0 0>;
-                        phys = <&usb0 0>;
-                        phy-names = "usb";
+                sdhi2: sd@ee160000 {
+                        compatible = "renesas,sdhi-r8a7791",
+                                     "renesas,rcar-gen2-sdhi";
+                        reg = <0 0xee160000 0 0x100>;
+                        interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 311>;
+                        dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+                               <&dmac1 0xd3>, <&dmac1 0xd4>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        max-frequency = <97500000>;
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 311>;
+                        status = "disabled";
                 };
-        };
 
-        pci1: pci@ee0d0000 {
-                compatible = "renesas,pci-r8a7791", "renesas,pci-rcar-gen2";
-                device_type = "pci";
-                reg = <0 0xee0d0000 0 0xc00>,
-                      <0 0xee0c0000 0 0x1100>;
-                interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 703>;
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 703>;
-                status = "disabled";
-
-                bus-range = <1 1>;
-                #address-cells = <3>;
-                #size-cells = <2>;
-                #interrupt-cells = <1>;
-                ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
-                interrupt-map-mask = <0xff00 0 0 0x7>;
-                interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
-                                 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
-                                 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
-
-                usb@1,0 {
-                        reg = <0x10800 0 0 0 0>;
-                        phys = <&usb2 0>;
-                        phy-names = "usb";
+                mmcif0: mmc@ee200000 {
+                        compatible = "renesas,mmcif-r8a7791",
+                                     "renesas,sh-mmcif";
+                        reg = <0 0xee200000 0 0x80>;
+                        interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 315>;
+                        dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+                               <&dmac1 0xd1>, <&dmac1 0xd2>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 315>;
+                        reg-io-width = <4>;
+                        status = "disabled";
+                        max-frequency = <97500000>;
                 };
 
-                usb@2,0 {
-                        reg = <0x11000 0 0 0 0>;
-                        phys = <&usb2 0>;
-                        phy-names = "usb";
+                sata0: sata@ee300000 {
+                        compatible = "renesas,sata-r8a7791",
+                                     "renesas,rcar-gen2-sata";
+                        reg = <0 0xee300000 0 0x2000>;
+                        interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 815>;
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 815>;
+                        status = "disabled";
                 };
-        };
 
-        pciec: pcie@fe000000 {
-                compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
-                reg = <0 0xfe000000 0 0x80000>;
-                #address-cells = <3>;
-                #size-cells = <2>;
-                bus-range = <0x00 0xff>;
-                device_type = "pci";
-                ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
-                          0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
-                          0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
-                          0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
-                /* Map all possible DDR as inbound ranges */
-                dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
-                              0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
-                interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
-                #interrupt-cells = <1>;
-                interrupt-map-mask = <0 0 0 0>;
-                interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
-                clock-names = "pcie", "pcie_bus";
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 319>;
-                status = "disabled";
-        };
+                sata1: sata@ee500000 {
+                        compatible = "renesas,sata-r8a7791",
+                                     "renesas,rcar-gen2-sata";
+                        reg = <0 0xee500000 0 0x2000>;
+                        interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 814>;
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 814>;
+                        status = "disabled";
+                };
 
-        ipmmu_sy0: mmu@e6280000 {
-                compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
-                reg = <0 0xe6280000 0 0x1000>;
-                interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
-                #iommu-cells = <1>;
-                status = "disabled";
-        };
+                ether: ethernet@ee700000 {
+                        compatible = "renesas,ether-r8a7791",
+                                     "renesas,rcar-gen2-ether";
+                        reg = <0 0xee700000 0 0x400>;
+                        interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 813>;
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 813>;
+                        phy-mode = "rmii";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
 
-        ipmmu_sy1: mmu@e6290000 {
-                compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
-                reg = <0 0xe6290000 0 0x1000>;
-                interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
-                #iommu-cells = <1>;
-                status = "disabled";
-        };
+                gic: interrupt-controller@f1001000 {
+                        compatible = "arm,gic-400";
+                        #interrupt-cells = <3>;
+                        #address-cells = <0>;
+                        interrupt-controller;
+                        reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
+                              <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
+                        interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+                        clocks = <&cpg CPG_MOD 408>;
+                        clock-names = "clk";
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 408>;
+                };
 
-        ipmmu_ds: mmu@e6740000 {
-                compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
-                reg = <0 0xe6740000 0 0x1000>;
-                interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
-                #iommu-cells = <1>;
-                status = "disabled";
-        };
+                pciec: pcie@fe000000 {
+                        compatible = "renesas,pcie-r8a7791",
+                                     "renesas,pcie-rcar-gen2";
+                        reg = <0 0xfe000000 0 0x80000>;
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        bus-range = <0x00 0xff>;
+                        device_type = "pci";
+                        ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
+                                  0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
+                                  0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
+                                  0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+                        /* Map all possible DDR as inbound ranges */
+                        dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
+                                      0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
+                        interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+                        #interrupt-cells = <1>;
+                        interrupt-map-mask = <0 0 0 0>;
+                        interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
+                        clock-names = "pcie", "pcie_bus";
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 319>;
+                        status = "disabled";
+                };
 
-        ipmmu_mp: mmu@ec680000 {
-                compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
-                reg = <0 0xec680000 0 0x1000>;
-                interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
-                #iommu-cells = <1>;
-                status = "disabled";
-        };
+                vsp@fe928000 {
+                        compatible = "renesas,vsp1";
+                        reg = <0 0xfe928000 0 0x8000>;
+                        interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 131>;
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 131>;
+                };
 
-        ipmmu_mx: mmu@fe951000 {
-                compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
-                reg = <0 0xfe951000 0 0x1000>;
-                interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
-                #iommu-cells = <1>;
-                status = "disabled";
-        };
+                vsp@fe930000 {
+                        compatible = "renesas,vsp1";
+                        reg = <0 0xfe930000 0 0x8000>;
+                        interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 128>;
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 128>;
+                };
 
-        ipmmu_rt: mmu@ffc80000 {
-                compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
-                reg = <0 0xffc80000 0 0x1000>;
-                interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
-                #iommu-cells = <1>;
-                status = "disabled";
-        };
+                vsp@fe938000 {
+                        compatible = "renesas,vsp1";
+                        reg = <0 0xfe938000 0 0x8000>;
+                        interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 127>;
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 127>;
+                };
 
-        ipmmu_gp: mmu@e62a0000 {
-                compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
-                reg = <0 0xe62a0000 0 0x1000>;
-                interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
-                #iommu-cells = <1>;
-                status = "disabled";
-        };
+                jpu: jpeg-codec@fe980000 {
+                        compatible = "renesas,jpu-r8a7791",
+                                     "renesas,rcar-gen2-jpu";
+                        reg = <0 0xfe980000 0 0x10300>;
+                        interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 106>;
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 106>;
+                };
 
-        rcar_sound: sound@ec500000 {
-                /*
-                 * #sound-dai-cells is required
-                 *
-                 * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
-                 * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
-                 */
-                compatible =  "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2";
-                reg =   <0 0xec500000 0 0x1000>, /* SCU */
-                        <0 0xec5a0000 0 0x100>,  /* ADG */
-                        <0 0xec540000 0 0x1000>, /* SSIU */
-                        <0 0xec541000 0 0x280>,  /* SSI */
-                        <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
-                reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
-
-                clocks = <&cpg CPG_MOD 1005>,
-                         <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
-                         <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
-                         <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
-                         <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
-                         <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
-                         <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
-                         <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
-                         <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
-                         <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
-                         <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
-                         <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
-                         <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
-                         <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
-                         <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
-                         <&cpg CPG_CORE R8A7791_CLK_M2>;
-                clock-names = "ssi-all",
-                                "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
-                                "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
-                                "src.9", "src.8", "src.7", "src.6", "src.5",
-                                "src.4", "src.3", "src.2", "src.1", "src.0",
-                                "ctu.0", "ctu.1",
-                                "mix.0", "mix.1",
-                                "dvc.0", "dvc.1",
-                                "clk_a", "clk_b", "clk_c", "clk_i";
-                power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
-                resets = <&cpg 1005>,
-                         <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>,
-                         <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>,
-                         <&cpg 1014>, <&cpg 1015>;
-                reset-names = "ssi-all",
-                              "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
-                              "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0";
-
-                status = "disabled";
-
-                rcar_sound,dvc {
-                        dvc0: dvc-0 {
-                                dmas = <&audma1 0xbc>;
-                                dma-names = "tx";
-                        };
-                        dvc1: dvc-1 {
-                                dmas = <&audma1 0xbe>;
-                                dma-names = "tx";
+                du: display@feb00000 {
+                        compatible = "renesas,du-r8a7791";
+                        reg = <0 0xfeb00000 0 0x40000>,
+                              <0 0xfeb90000 0 0x1c>;
+                        reg-names = "du", "lvds.0";
+                        interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 724>,
+                                 <&cpg CPG_MOD 723>,
+                                 <&cpg CPG_MOD 726>;
+                        clock-names = "du.0", "du.1", "lvds.0";
+                        status = "disabled";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@0 {
+                                        reg = <0>;
+                                        du_out_rgb: endpoint {
+                                        };
+                                };
+                                port@1 {
+                                        reg = <1>;
+                                        du_out_lvds0: endpoint {
+                                        };
+                                };
                         };
                 };
 
-                rcar_sound,mix {
-                        mix0: mix-0 { };
-                        mix1: mix-1 { };
+                prr: chipid@ff000044 {
+                        compatible = "renesas,prr";
+                        reg = <0 0xff000044 0 4>;
                 };
 
-                rcar_sound,ctu {
-                        ctu00: ctu-0 { };
-                        ctu01: ctu-1 { };
-                        ctu02: ctu-2 { };
-                        ctu03: ctu-3 { };
-                        ctu10: ctu-4 { };
-                        ctu11: ctu-5 { };
-                        ctu12: ctu-6 { };
-                        ctu13: ctu-7 { };
+                cmt0: timer@ffca0000 {
+                        compatible = "renesas,r8a7791-cmt0",
+                                     "renesas,rcar-gen2-cmt0";
+                        reg = <0 0xffca0000 0 0x1004>;
+                        interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 124>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 124>;
+
+                        status = "disabled";
                 };
 
-                rcar_sound,src {
-                        src0: src-0 {
-                                interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x85>, <&audma1 0x9a>;
-                                dma-names = "rx", "tx";
-                        };
-                        src1: src-1 {
-                                interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x87>, <&audma1 0x9c>;
-                                dma-names = "rx", "tx";
-                        };
-                        src2: src-2 {
-                                interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x89>, <&audma1 0x9e>;
-                                dma-names = "rx", "tx";
-                        };
-                        src3: src-3 {
-                                interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x8b>, <&audma1 0xa0>;
-                                dma-names = "rx", "tx";
-                        };
-                        src4: src-4 {
-                                interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x8d>, <&audma1 0xb0>;
-                                dma-names = "rx", "tx";
-                        };
-                        src5: src-5 {
-                                interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x8f>, <&audma1 0xb2>;
-                                dma-names = "rx", "tx";
-                        };
-                        src6: src-6 {
-                                interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x91>, <&audma1 0xb4>;
-                                dma-names = "rx", "tx";
-                        };
-                        src7: src-7 {
-                                interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x93>, <&audma1 0xb6>;
-                                dma-names = "rx", "tx";
-                        };
-                        src8: src-8 {
-                                interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x95>, <&audma1 0xb8>;
-                                dma-names = "rx", "tx";
-                        };
-                        src9: src-9 {
-                                interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x97>, <&audma1 0xba>;
-                                dma-names = "rx", "tx";
-                        };
+                cmt1: timer@e6130000 {
+                        compatible = "renesas,r8a7791-cmt1",
+                                     "renesas,rcar-gen2-cmt1";
+                        reg = <0 0xe6130000 0 0x1004>;
+                        interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 329>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                        resets = <&cpg 329>;
+
+                        status = "disabled";
                 };
+        };
 
-                rcar_sound,ssi {
-                        ssi0: ssi-0 {
-                                interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
-                                dma-names = "rx", "tx", "rxu", "txu";
-                        };
-                        ssi1: ssi-1 {
-                                 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
-                                dma-names = "rx", "tx", "rxu", "txu";
-                        };
-                        ssi2: ssi-2 {
-                                interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
-                                dma-names = "rx", "tx", "rxu", "txu";
-                        };
-                        ssi3: ssi-3 {
-                                interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
-                                dma-names = "rx", "tx", "rxu", "txu";
-                        };
-                        ssi4: ssi-4 {
-                                interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
-                                dma-names = "rx", "tx", "rxu", "txu";
-                        };
-                        ssi5: ssi-5 {
-                                interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
-                                dma-names = "rx", "tx", "rxu", "txu";
-                        };
-                        ssi6: ssi-6 {
-                                interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
-                                dma-names = "rx", "tx", "rxu", "txu";
-                        };
-                        ssi7: ssi-7 {
-                                interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
-                                dma-names = "rx", "tx", "rxu", "txu";
-                        };
-                        ssi8: ssi-8 {
-                                interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
-                                dma-names = "rx", "tx", "rxu", "txu";
+        thermal-zones {
+                cpu_thermal: cpu-thermal {
+                        polling-delay-passive = <0>;
+                        polling-delay = <0>;
+
+                        thermal-sensors = <&thermal>;
+
+                        trips {
+                                cpu-crit {
+                                        temperature = <95000>;
+                                        hysteresis = <0>;
+                                        type = "critical";
+                                };
                         };
-                        ssi9: ssi-9 {
-                                interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
-                                dma-names = "rx", "tx", "rxu", "txu";
+                        cooling-maps {
                         };
                 };
         };
+
+        timer {
+                compatible = "arm,armv7-timer";
+                interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                                      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                                      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                                      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+        };
+
+        /* External USB clock - can be overridden by the board */
+        usb_extal_clk: usb_extal {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <48000000>;
+        };
 };
diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
index 3be15a158bad..268987ff0201 100644
--- a/arch/arm/boot/dts/r8a7792.dtsi
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -101,63 +101,6 @@
                 #size-cells = <2>;
                 ranges;
 
-                apmu@e6152000 {
-                        compatible = "renesas,r8a7792-apmu", "renesas,apmu";
-                        reg = <0 0xe6152000 0 0x188>;
-                        cpus = <&cpu0 &cpu1>;
-                };
-
-                gic: interrupt-controller@f1001000 {
-                        compatible = "arm,gic-400";
-                        #interrupt-cells = <3>;
-                        interrupt-controller;
-                        reg = <0 0xf1001000 0 0x1000>,
-                              <0 0xf1002000 0 0x2000>,
-                              <0 0xf1004000 0 0x2000>,
-                              <0 0xf1006000 0 0x2000>;
-                        interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
-                                      IRQ_TYPE_LEVEL_HIGH)>;
-                        clocks = <&cpg CPG_MOD 408>;
-                        clock-names = "clk";
-                        power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
-                        resets = <&cpg 408>;
-                };
-
-                irqc: interrupt-controller@e61c0000 {
-                        compatible = "renesas,irqc-r8a7792", "renesas,irqc";
-                        #interrupt-cells = <2>;
-                        interrupt-controller;
-                        reg = <0 0xe61c0000 0 0x200>;
-                        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 407>;
-                        power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
-                        resets = <&cpg 407>;
-                };
-
-                rst: reset-controller@e6160000 {
-                        compatible = "renesas,r8a7792-rst";
-                        reg = <0 0xe6160000 0 0x0100>;
-                };
-
-                prr: chipid@ff000044 {
-                        compatible = "renesas,prr";
-                        reg = <0 0xff000044 0 4>;
-                };
-
-                sysc: system-controller@e6180000 {
-                        compatible = "renesas,r8a7792-sysc";
-                        reg = <0 0xe6180000 0 0x0200>;
-                        #power-domain-cells = <1>;
-                };
-
-                pfc: pin-controller@e6060000 {
-                        compatible = "renesas,pfc-r8a7792";
-                        reg = <0 0xe6060000 0 0x144>;
-                };
-
                 gpio0: gpio@e6050000 {
                         compatible = "renesas,gpio-r8a7792",
                                      "renesas,rcar-gen2-gpio";
@@ -338,6 +281,155 @@
                         resets = <&cpg 913>;
                 };
 
+                pfc: pin-controller@e6060000 {
+                        compatible = "renesas,pfc-r8a7792";
+                        reg = <0 0xe6060000 0 0x144>;
+                };
+
+                cpg: clock-controller@e6150000 {
+                        compatible = "renesas,r8a7792-cpg-mssr";
+                        reg = <0 0xe6150000 0 0x1000>;
+                        clocks = <&extal_clk>;
+                        clock-names = "extal";
+                        #clock-cells = <2>;
+                        #power-domain-cells = <0>;
+                        #reset-cells = <1>;
+                };
+
+                apmu@e6152000 {
+                        compatible = "renesas,r8a7792-apmu", "renesas,apmu";
+                        reg = <0 0xe6152000 0 0x188>;
+                        cpus = <&cpu0 &cpu1>;
+                };
+
+                rst: reset-controller@e6160000 {
+                        compatible = "renesas,r8a7792-rst";
+                        reg = <0 0xe6160000 0 0x0100>;
+                };
+
+                sysc: system-controller@e6180000 {
+                        compatible = "renesas,r8a7792-sysc";
+                        reg = <0 0xe6180000 0 0x0200>;
+                        #power-domain-cells = <1>;
+                };
+
+                irqc: interrupt-controller@e61c0000 {
+                        compatible = "renesas,irqc-r8a7792", "renesas,irqc";
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        reg = <0 0xe61c0000 0 0x200>;
+                        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 407>;
+                        power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+                        resets = <&cpg 407>;
+                };
+
+                icram0: sram@e63a0000 {
+                        compatible = "mmio-sram";
+                        reg = <0 0xe63a0000 0 0x12000>;
+                };
+
+                icram1: sram@e63c0000 {
+                        compatible = "mmio-sram";
+                        reg = <0 0xe63c0000 0 0x1000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0 0xe63c0000 0x1000>;
+
+                        smp-sram@0 {
+                                compatible = "renesas,smp-sram";
+                                reg = <0 0x10>;
+                        };
+                };
+
+                /* I2C doesn't need pinmux */
+                i2c0: i2c@e6508000 {
+                        compatible = "renesas,i2c-r8a7792",
+                                     "renesas,rcar-gen2-i2c";
+                        reg = <0 0xe6508000 0 0x40>;
+                        interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 931>;
+                        power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+                        resets = <&cpg 931>;
+                        i2c-scl-internal-delay-ns = <6>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                i2c1: i2c@e6518000 {
+                        compatible = "renesas,i2c-r8a7792",
+                                     "renesas,rcar-gen2-i2c";
+                        reg = <0 0xe6518000 0 0x40>;
+                        interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 930>;
+                        power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+                        resets = <&cpg 930>;
+                        i2c-scl-internal-delay-ns = <6>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                i2c2: i2c@e6530000 {
+                        compatible = "renesas,i2c-r8a7792",
+                                     "renesas,rcar-gen2-i2c";
+                        reg = <0 0xe6530000 0 0x40>;
+                        interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 929>;
+                        power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+                        resets = <&cpg 929>;
+                        i2c-scl-internal-delay-ns = <6>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                i2c3: i2c@e6540000 {
+                        compatible = "renesas,i2c-r8a7792",
+                                     "renesas,rcar-gen2-i2c";
+                        reg = <0 0xe6540000 0 0x40>;
+                        interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 928>;
+                        power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+                        resets = <&cpg 928>;
+                        i2c-scl-internal-delay-ns = <6>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                i2c4: i2c@e6520000 {
+                        compatible = "renesas,i2c-r8a7792",
+                                     "renesas,rcar-gen2-i2c";
+                        reg = <0 0xe6520000 0 0x40>;
+                        interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 927>;
+                        power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+                        resets = <&cpg 927>;
+                        i2c-scl-internal-delay-ns = <6>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                i2c5: i2c@e6528000 {
+                        compatible = "renesas,i2c-r8a7792",
+                                     "renesas,rcar-gen2-i2c";
+                        reg = <0 0xe6528000 0 0x40>;
+                        interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 925>;
+                        power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+                        resets = <&cpg 925>;
+                        i2c-scl-internal-delay-ns = <110>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
                 dmac0: dma-controller@e6700000 {
                         compatible = "renesas,dmac-r8a7792",
                                      "renesas,rcar-dmac";
@@ -404,6 +496,35 @@
                         dma-channels = <15>;
                 };
 
+                avb: ethernet@e6800000 {
+                        compatible = "renesas,etheravb-r8a7792",
+                                     "renesas,etheravb-rcar-gen2";
+                        reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
+                        interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 812>;
+                        power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+                        resets = <&cpg 812>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                qspi: spi@e6b10000 {
+                        compatible = "renesas,qspi-r8a7792", "renesas,qspi";
+                        reg = <0 0xe6b10000 0 0x2c>;
+                        interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 917>;
+                        dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+                               <&dmac1 0x17>, <&dmac1 0x18>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+                        resets = <&cpg 917>;
+                        num-cs = <1>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
                 scif0: serial@e6e60000 {
                         compatible = "renesas,scif-r8a7792",
                                      "renesas,rcar-gen2-scif", "renesas,scif";
@@ -500,162 +621,6 @@
                         status = "disabled";
                 };
 
-                icram0: sram@e63a0000 {
-                        compatible = "mmio-sram";
-                        reg = <0 0xe63a0000 0 0x12000>;
-                };
-
-                icram1: sram@e63c0000 {
-                        compatible = "mmio-sram";
-                        reg = <0 0xe63c0000 0 0x1000>;
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        ranges = <0 0 0xe63c0000 0x1000>;
-
-                        smp-sram@0 {
-                                compatible = "renesas,smp-sram";
-                                reg = <0 0x10>;
-                        };
-                };
-
-                sdhi0: sd@ee100000 {
-                        compatible = "renesas,sdhi-r8a7792",
-                                     "renesas,rcar-gen2-sdhi";
-                        reg = <0 0xee100000 0 0x328>;
-                        interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
-                        dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
-                               <&dmac1 0xcd>, <&dmac1 0xce>;
-                        dma-names = "tx", "rx", "tx", "rx";
-                        clocks = <&cpg CPG_MOD 314>;
-                        power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
-                        resets = <&cpg 314>;
-                        status = "disabled";
-                };
-
-                jpu: jpeg-codec@fe980000 {
-                        compatible = "renesas,jpu-r8a7792",
-                                     "renesas,rcar-gen2-jpu";
-                        reg = <0 0xfe980000 0 0x10300>;
-                        interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 106>;
-                        power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
-                        resets = <&cpg 106>;
-                };
-
-                avb: ethernet@e6800000 {
-                        compatible = "renesas,etheravb-r8a7792",
-                                     "renesas,etheravb-rcar-gen2";
-                        reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
-                        interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 812>;
-                        power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
-                        resets = <&cpg 812>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        status = "disabled";
-                };
-
-                /* I2C doesn't need pinmux */
-                i2c0: i2c@e6508000 {
-                        compatible = "renesas,i2c-r8a7792",
-                                     "renesas,rcar-gen2-i2c";
-                        reg = <0 0xe6508000 0 0x40>;
-                        interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 931>;
-                        power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
-                        resets = <&cpg 931>;
-                        i2c-scl-internal-delay-ns = <6>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        status = "disabled";
-                };
-
-                i2c1: i2c@e6518000 {
-                        compatible = "renesas,i2c-r8a7792",
-                                     "renesas,rcar-gen2-i2c";
-                        reg = <0 0xe6518000 0 0x40>;
-                        interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 930>;
-                        power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
-                        resets = <&cpg 930>;
-                        i2c-scl-internal-delay-ns = <6>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        status = "disabled";
-                };
-
-                i2c2: i2c@e6530000 {
-                        compatible = "renesas,i2c-r8a7792",
-                                     "renesas,rcar-gen2-i2c";
-                        reg = <0 0xe6530000 0 0x40>;
-                        interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 929>;
-                        power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
-                        resets = <&cpg 929>;
-                        i2c-scl-internal-delay-ns = <6>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        status = "disabled";
-                };
-
-                i2c3: i2c@e6540000 {
-                        compatible = "renesas,i2c-r8a7792",
-                                     "renesas,rcar-gen2-i2c";
-                        reg = <0 0xe6540000 0 0x40>;
-                        interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 928>;
-                        power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
-                        resets = <&cpg 928>;
-                        i2c-scl-internal-delay-ns = <6>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        status = "disabled";
-                };
-
-                i2c4: i2c@e6520000 {
-                        compatible = "renesas,i2c-r8a7792",
-                                     "renesas,rcar-gen2-i2c";
-                        reg = <0 0xe6520000 0 0x40>;
-                        interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 927>;
-                        power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
-                        resets = <&cpg 927>;
-                        i2c-scl-internal-delay-ns = <6>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        status = "disabled";
-                };
-
-                i2c5: i2c@e6528000 {
-                        compatible = "renesas,i2c-r8a7792",
-                                     "renesas,rcar-gen2-i2c";
-                        reg = <0 0xe6528000 0 0x40>;
-                        interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 925>;
-                        power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
-                        resets = <&cpg 925>;
-                        i2c-scl-internal-delay-ns = <110>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        status = "disabled";
-                };
-
-                qspi: spi@e6b10000 {
-                        compatible = "renesas,qspi-r8a7792", "renesas,qspi";
-                        reg = <0 0xe6b10000 0 0x2c>;
-                        interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 917>;
-                        dmas = <&dmac0 0x17>, <&dmac0 0x18>,
-                               <&dmac1 0x17>, <&dmac1 0x18>;
-                        dma-names = "tx", "rx", "tx", "rx";
-                        power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
-                        resets = <&cpg 917>;
-                        num-cs = <1>;
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        status = "disabled";
-                };
-
                 msiof0: spi@e6e20000 {
                         compatible = "renesas,msiof-r8a7792",
                                      "renesas,rcar-gen2-msiof";
@@ -688,34 +653,6 @@
                         status = "disabled";
                 };
 
-                du: display@feb00000 {
-                        compatible = "renesas,du-r8a7792";
-                        reg = <0 0xfeb00000 0 0x40000>;
-                        reg-names = "du";
-                        interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
-                                     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&cpg CPG_MOD 724>,
-                                 <&cpg CPG_MOD 723>;
-                        clock-names = "du.0", "du.1";
-                        status = "disabled";
-
-                        ports {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-
-                                port@0 {
-                                        reg = <0>;
-                                        du_out_rgb0: endpoint {
-                                        };
-                                };
-                                port@1 {
-                                        reg = <1>;
-                                        du_out_rgb1: endpoint {
-                                        };
-                                };
-                        };
-                };
-
                 can0: can@e6e80000 {
                         compatible = "renesas,can-r8a7792",
                                      "renesas,rcar-gen2-can";
@@ -808,6 +745,36 @@
                         status = "disabled";
                 };
 
+                sdhi0: sd@ee100000 {
+                        compatible = "renesas,sdhi-r8a7792",
+                                     "renesas,rcar-gen2-sdhi";
+                        reg = <0 0xee100000 0 0x328>;
+                        interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
+                        dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+                               <&dmac1 0xcd>, <&dmac1 0xce>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        clocks = <&cpg CPG_MOD 314>;
+                        power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+                        resets = <&cpg 314>;
+                        status = "disabled";
+                };
+
+                gic: interrupt-controller@f1001000 {
+                        compatible = "arm,gic-400";
+                        #interrupt-cells = <3>;
+                        interrupt-controller;
+                        reg = <0 0xf1001000 0 0x1000>,
+                              <0 0xf1002000 0 0x2000>,
+                              <0 0xf1004000 0 0x2000>,
+                              <0 0xf1006000 0 0x2000>;
+                        interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
+                                      IRQ_TYPE_LEVEL_HIGH)>;
+                        clocks = <&cpg CPG_MOD 408>;
+                        clock-names = "clk";
+                        power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+                        resets = <&cpg 408>;
+                };
+
                 vsp@fe928000 {
                         compatible = "renesas,vsp1";
                         reg = <0 0xfe928000 0 0x8000>;
@@ -835,14 +802,47 @@
                         resets = <&cpg 127>;
                 };
 
-                cpg: clock-controller@e6150000 {
-                        compatible = "renesas,r8a7792-cpg-mssr";
-                        reg = <0 0xe6150000 0 0x1000>;
-                        clocks = <&extal_clk>;
-                        clock-names = "extal";
-                        #clock-cells = <2>;
-                        #power-domain-cells = <0>;
-                        #reset-cells = <1>;
+                jpu: jpeg-codec@fe980000 {
+                        compatible = "renesas,jpu-r8a7792",
+                                     "renesas,rcar-gen2-jpu";
+                        reg = <0 0xfe980000 0 0x10300>;
+                        interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 106>;
+                        power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+                        resets = <&cpg 106>;
+                };
+
+                du: display@feb00000 {
+                        compatible = "renesas,du-r8a7792";
+                        reg = <0 0xfeb00000 0 0x40000>;
+                        reg-names = "du";
+                        interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 724>,
+                                 <&cpg CPG_MOD 723>;
+                        clock-names = "du.0", "du.1";
+                        status = "disabled";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@0 {
+                                        reg = <0>;
+                                        du_out_rgb0: endpoint {
+                                        };
+                                };
+                                port@1 {
+                                        reg = <1>;
+                                        du_out_rgb1: endpoint {
+                                        };
+                                };
+                        };
+                };
+
+                prr: chipid@ff000044 {
+                        compatible = "renesas,prr";
+                        reg = <0 0xff000044 0 4>;
                 };
         };
 
diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts
index 51b3ffac8efa..9ed6961f2d9a 100644
--- a/arch/arm/boot/dts/r8a7793-gose.dts
+++ b/arch/arm/boot/dts/r8a7793-gose.dts
@@ -48,6 +48,10 @@
         aliases {
                 serial0 = &scif0;
                 serial1 = &scif1;
+                i2c9 = &gpioi2c2;
+                i2c10 = &gpioi2c4;
+                i2c11 = &i2chdmi;
+                i2c12 = &i2cexio4;
         };
 
         chosen {
@@ -296,6 +300,146 @@
                 #clock-cells = <0>;
                 clock-frequency = <148500000>;
         };
+
+        gpioi2c2: i2c-9 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "i2c-gpio";
+                status = "disabled";
+                scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+                sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+                i2c-gpio,delay-us = <5>;
+        };
+
+        gpioi2c4: i2c-10 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "i2c-gpio";
+                status = "disabled";
+                scl-gpios = <&gpio7 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+                sda-gpios = <&gpio7 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+                i2c-gpio,delay-us = <5>;
+        };
+
+        /*
+         * A fallback to GPIO is provided for I2C2.
+         */
+        i2chdmi: i2c-11 {
+                compatible = "i2c-demux-pinctrl";
+                i2c-parent = <&i2c2>, <&gpioi2c2>;
+                i2c-bus-name = "i2c-hdmi";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                ak4643: codec@12 {
+                        compatible = "asahi-kasei,ak4643";
+                        #sound-dai-cells = <0>;
+                        reg = <0x12>;
+                };
+
+                composite-in@20 {
+                        compatible = "adi,adv7180cp";
+                        reg = <0x20>;
+                        remote = <&vin1>;
+
+                        port {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@0 {
+                                        reg = <0>;
+                                        adv7180_in: endpoint {
+                                                remote-endpoint = <&composite_con_in>;
+                                        };
+                                };
+
+                                port@3 {
+                                        reg = <3>;
+                                        adv7180_out: endpoint {
+                                                bus-width = <8>;
+                                                remote-endpoint = <&vin1ep>;
+                                        };
+                                };
+                        };
+                };
+
+                hdmi@39 {
+                        compatible = "adi,adv7511w";
+                        reg = <0x39>;
+                        interrupt-parent = <&gpio3>;
+                        interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
+
+                        adi,input-depth = <8>;
+                        adi,input-colorspace = "rgb";
+                        adi,input-clock = "1x";
+                        adi,input-style = <1>;
+                        adi,input-justification = "evenly";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@0 {
+                                        reg = <0>;
+                                        adv7511_in: endpoint {
+                                                remote-endpoint = <&du_out_rgb>;
+                                        };
+                                };
+
+                                port@1 {
+                                        reg = <1>;
+                                        adv7511_out: endpoint {
+                                                remote-endpoint = <&hdmi_con_out>;
+                                        };
+                                };
+                        };
+                };
+
+                hdmi-in@4c {
+                        compatible = "adi,adv7612";
+                        reg = <0x4c>;
+                        interrupt-parent = <&gpio4>;
+                        interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+                        default-input = <0>;
+
+                        port {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@0 {
+                                        reg = <0>;
+                                        adv7612_in: endpoint {
+                                                remote-endpoint = <&hdmi_con_in>;
+                                        };
+                                };
+
+                                port@2 {
+                                        reg = <2>;
+                                        adv7612_out: endpoint {
+                                                remote-endpoint = <&vin0ep2>;
+                                        };
+                                };
+                        };
+                };
+
+                eeprom@50 {
+                        compatible = "renesas,r1ex24002", "atmel,24c02";
+                        reg = <0x50>;
+                        pagesize = <16>;
+                };
+        };
+
+        /*
+         * I2C4 is routed to EXIO connector E, pins 37 (SCL) + 39 (SDA).
+         * A fallback to GPIO is provided.
+         */
+        i2cexio4: i2c-12 {
+                compatible = "i2c-demux-pinctrl";
+                i2c-parent = <&i2c4>, <&gpioi2c4>;
+                i2c-bus-name = "i2c-exio4";
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
 };
 
 &du {
@@ -334,6 +478,11 @@
                 function = "i2c2";
         };
 
+        i2c4_pins: i2c4 {
+                groups = "i2c4_c";
+                function = "i2c4";
+        };
+
         du_pins: du {
                 groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
                 function = "du";
@@ -544,107 +693,11 @@
 
 &i2c2 {
         pinctrl-0 = <&i2c2_pins>;
-        pinctrl-names = "default";
+        pinctrl-names = "i2c-hdmi";
 
         status = "okay";
         clock-frequency = <100000>;
 
-        ak4643: codec@12 {
-                compatible = "asahi-kasei,ak4643";
-                #sound-dai-cells = <0>;
-                reg = <0x12>;
-        };
-
-        composite-in@20 {
-                compatible = "adi,adv7180cp";
-                reg = <0x20>;
-                remote = <&vin1>;
-
-                port {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-
-                        port@0 {
-                                reg = <0>;
-                                adv7180_in: endpoint {
-                                        remote-endpoint = <&composite_con_in>;
-                                };
-                        };
-
-                        port@3 {
-                                reg = <3>;
-                                adv7180_out: endpoint {
-                                        bus-width = <8>;
-                                        remote-endpoint = <&vin1ep>;
-                                };
-                        };
-                };
-        };
-
-        hdmi@39 {
-                compatible = "adi,adv7511w";
-                reg = <0x39>;
-                interrupt-parent = <&gpio3>;
-                interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
-
-                adi,input-depth = <8>;
-                adi,input-colorspace = "rgb";
-                adi,input-clock = "1x";
-                adi,input-style = <1>;
-                adi,input-justification = "evenly";
-
-                ports {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-
-                        port@0 {
-                                reg = <0>;
-                                adv7511_in: endpoint {
-                                        remote-endpoint = <&du_out_rgb>;
-                                };
-                        };
-
-                        port@1 {
-                                reg = <1>;
-                                adv7511_out: endpoint {
-                                        remote-endpoint = <&hdmi_con_out>;
-                                };
-                        };
-                };
-        };
-
-        hdmi-in@4c {
-                compatible = "adi,adv7612";
-                reg = <0x4c>;
-                interrupt-parent = <&gpio4>;
-                interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
-                default-input = <0>;
-
-                port {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-
-                        port@0 {
-                                reg = <0>;
-                                adv7612_in: endpoint {
-                                        remote-endpoint = <&hdmi_con_in>;
-                                };
-                        };
-
-                        port@2 {
-                                reg = <2>;
-                                adv7612_out: endpoint {
-                                        remote-endpoint = <&vin0ep2>;
-                                };
-                        };
-                };
-        };
-
-        eeprom@50 {
-                compatible = "renesas,r1ex24002", "atmel,24c02";
-                reg = <0x50>;
-                pagesize = <16>;
-        };
 };
 
 &i2c6 {
@@ -668,6 +721,11 @@
         };
 };
 
+&i2c4 {
+        pinctrl-0 = <&i2c4_pins>;
+        pinctrl-names = "i2c-exio4";
+};
+
 &rcar_sound {
         pinctrl-0 = <&sound_pins &sound_clk_pins>;
         pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 039b22517526..f9c5a557107d 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -15,7 +15,6 @@
 
 / {
         compatible = "renesas,r8a7793";
-        interrupt-parent = <&gic>;
         #address-cells = <2>;
         #size-cells = <2>;
 
@@ -32,6 +31,35 @@
                 spi0 = &qspi;
         };
 
+        /*
+         * The external audio clocks are configured as 0 Hz fixed frequency
+         * clocks by default.
+         * Boards that provide audio clocks should override them.
+         */
+        audio_clk_a: audio_clk_a {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+        audio_clk_b: audio_clk_b {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+        audio_clk_c: audio_clk_c {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+
+        /* External CAN clock */
+        can_clk: can {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                /* This value must be overridden by the board. */
+                clock-frequency = <0>;
+        };
+
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -74,1261 +102,1295 @@
                 };
         };
 
-        apmu@e6152000 {
-                compatible = "renesas,r8a7793-apmu", "renesas,apmu";
-                reg = <0 0xe6152000 0 0x188>;
-                cpus = <&cpu0 &cpu1>;
+        /* External root clock */
+        extal_clk: extal {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                /* This value must be overridden by the board. */
+                clock-frequency = <0>;
         };
 
-        thermal-zones {
-                cpu_thermal: cpu-thermal {
-                        polling-delay-passive   = <0>;
-                        polling-delay           = <0>;
+        /* External SCIF clock */
+        scif_clk: scif {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                /* This value must be overridden by the board. */
+                clock-frequency = <0>;
+        };
 
-                        thermal-sensors = <&thermal>;
+        soc {
+                compatible = "simple-bus";
+                interrupt-parent = <&gic>;
+
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
+
+                gpio0: gpio@e6050000 {
+                        compatible = "renesas,gpio-r8a7793",
+                                     "renesas,rcar-gen2-gpio";
+                        reg = <0 0xe6050000 0 0x50>;
+                        interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 0 32>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 912>;
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 912>;
+                };
 
-                        trips {
-                                cpu-crit {
-                                        temperature     = <95000>;
-                                        hysteresis      = <0>;
-                                        type            = "critical";
-                                };
-                        };
-                        cooling-maps {
-                        };
+                gpio1: gpio@e6051000 {
+                        compatible = "renesas,gpio-r8a7793",
+                                     "renesas,rcar-gen2-gpio";
+                        reg = <0 0xe6051000 0 0x50>;
+                        interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 32 26>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 911>;
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 911>;
                 };
-        };
 
-        gic: interrupt-controller@f1001000 {
-                compatible = "arm,gic-400";
-                #interrupt-cells = <3>;
-                #address-cells = <0>;
-                interrupt-controller;
-                reg = <0 0xf1001000 0 0x1000>,
-                        <0 0xf1002000 0 0x2000>,
-                        <0 0xf1004000 0 0x2000>,
-                        <0 0xf1006000 0 0x2000>;
-                interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
-                clocks = <&cpg CPG_MOD 408>;
-                clock-names = "clk";
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 408>;
-        };
+                gpio2: gpio@e6052000 {
+                        compatible = "renesas,gpio-r8a7793",
+                                     "renesas,rcar-gen2-gpio";
+                        reg = <0 0xe6052000 0 0x50>;
+                        interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 64 32>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 910>;
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 910>;
+                };
 
-        gpio0: gpio@e6050000 {
-                compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
-                reg = <0 0xe6050000 0 0x50>;
-                interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
-                #gpio-cells = <2>;
-                gpio-controller;
-                gpio-ranges = <&pfc 0 0 32>;
-                #interrupt-cells = <2>;
-                interrupt-controller;
-                clocks = <&cpg CPG_MOD 912>;
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 912>;
-        };
+                gpio3: gpio@e6053000 {
+                        compatible = "renesas,gpio-r8a7793",
+                                     "renesas,rcar-gen2-gpio";
+                        reg = <0 0xe6053000 0 0x50>;
+                        interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 96 32>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 909>;
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 909>;
+                };
 
-        gpio1: gpio@e6051000 {
-                compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
-                reg = <0 0xe6051000 0 0x50>;
-                interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
-                #gpio-cells = <2>;
-                gpio-controller;
-                gpio-ranges = <&pfc 0 32 26>;
-                #interrupt-cells = <2>;
-                interrupt-controller;
-                clocks = <&cpg CPG_MOD 911>;
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 911>;
-        };
+                gpio4: gpio@e6054000 {
+                        compatible = "renesas,gpio-r8a7793",
+                                     "renesas,rcar-gen2-gpio";
+                        reg = <0 0xe6054000 0 0x50>;
+                        interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 128 32>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 908>;
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 908>;
+                };
 
-        gpio2: gpio@e6052000 {
-                compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
-                reg = <0 0xe6052000 0 0x50>;
-                interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
-                #gpio-cells = <2>;
-                gpio-controller;
-                gpio-ranges = <&pfc 0 64 32>;
-                #interrupt-cells = <2>;
-                interrupt-controller;
-                clocks = <&cpg CPG_MOD 910>;
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 910>;
-        };
+                gpio5: gpio@e6055000 {
+                        compatible = "renesas,gpio-r8a7793",
+                                     "renesas,rcar-gen2-gpio";
+                        reg = <0 0xe6055000 0 0x50>;
+                        interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 160 32>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 907>;
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 907>;
+                };
 
-        gpio3: gpio@e6053000 {
-                compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
-                reg = <0 0xe6053000 0 0x50>;
-                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
-                #gpio-cells = <2>;
-                gpio-controller;
-                gpio-ranges = <&pfc 0 96 32>;
-                #interrupt-cells = <2>;
-                interrupt-controller;
-                clocks = <&cpg CPG_MOD 909>;
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 909>;
-        };
+                gpio6: gpio@e6055400 {
+                        compatible = "renesas,gpio-r8a7793",
+                                     "renesas,rcar-gen2-gpio";
+                        reg = <0 0xe6055400 0 0x50>;
+                        interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 192 32>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 905>;
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 905>;
+                };
 
-        gpio4: gpio@e6054000 {
-                compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
-                reg = <0 0xe6054000 0 0x50>;
-                interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
-                #gpio-cells = <2>;
-                gpio-controller;
-                gpio-ranges = <&pfc 0 128 32>;
-                #interrupt-cells = <2>;
-                interrupt-controller;
-                clocks = <&cpg CPG_MOD 908>;
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 908>;
-        };
+                gpio7: gpio@e6055800 {
+                        compatible = "renesas,gpio-r8a7793",
+                                     "renesas,rcar-gen2-gpio";
+                        reg = <0 0xe6055800 0 0x50>;
+                        interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 224 26>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 904>;
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 904>;
+                };
 
-        gpio5: gpio@e6055000 {
-                compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
-                reg = <0 0xe6055000 0 0x50>;
-                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
-                #gpio-cells = <2>;
-                gpio-controller;
-                gpio-ranges = <&pfc 0 160 32>;
-                #interrupt-cells = <2>;
-                interrupt-controller;
-                clocks = <&cpg CPG_MOD 907>;
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 907>;
-        };
+                pfc: pin-controller@e6060000 {
+                        compatible = "renesas,pfc-r8a7793";
+                        reg = <0 0xe6060000 0 0x250>;
+                };
 
-        gpio6: gpio@e6055400 {
-                compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
-                reg = <0 0xe6055400 0 0x50>;
-                interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-                #gpio-cells = <2>;
-                gpio-controller;
-                gpio-ranges = <&pfc 0 192 32>;
-                #interrupt-cells = <2>;
-                interrupt-controller;
-                clocks = <&cpg CPG_MOD 905>;
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 905>;
-        };
+                /* Special CPG clocks */
+                cpg: clock-controller@e6150000 {
+                        compatible = "renesas,r8a7793-cpg-mssr";
+                        reg = <0 0xe6150000 0 0x1000>;
+                        clocks = <&extal_clk>, <&usb_extal_clk>;
+                        clock-names = "extal", "usb_extal";
+                        #clock-cells = <2>;
+                        #power-domain-cells = <0>;
+                        #reset-cells = <1>;
+                };
 
-        gpio7: gpio@e6055800 {
-                compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio";
-                reg = <0 0xe6055800 0 0x50>;
-                interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
-                #gpio-cells = <2>;
-                gpio-controller;
-                gpio-ranges = <&pfc 0 224 26>;
-                #interrupt-cells = <2>;
-                interrupt-controller;
-                clocks = <&cpg CPG_MOD 904>;
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 904>;
-        };
+                apmu@e6152000 {
+                        compatible = "renesas,r8a7793-apmu", "renesas,apmu";
+                        reg = <0 0xe6152000 0 0x188>;
+                        cpus = <&cpu0 &cpu1>;
+                };
 
-        thermal: thermal@e61f0000 {
-                compatible =    "renesas,thermal-r8a7793",
-                                "renesas,rcar-gen2-thermal",
-                                "renesas,rcar-thermal";
-                reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
-                interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 522>;
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 522>;
-                #thermal-sensor-cells = <0>;
-        };
+                rst: reset-controller@e6160000 {
+                        compatible = "renesas,r8a7793-rst";
+                        reg = <0 0xe6160000 0 0x0100>;
+                };
 
-        timer {
-                compatible = "arm,armv7-timer";
-                interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-                             <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-                             <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-                             <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
-        };
+                sysc: system-controller@e6180000 {
+                        compatible = "renesas,r8a7793-sysc";
+                        reg = <0 0xe6180000 0 0x0200>;
+                        #power-domain-cells = <1>;
+                };
 
-        cmt0: timer@ffca0000 {
-                compatible = "renesas,r8a7793-cmt0", "renesas,rcar-gen2-cmt0";
-                reg = <0 0xffca0000 0 0x1004>;
-                interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 124>;
-                clock-names = "fck";
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 124>;
-
-                status = "disabled";
-        };
+                irqc0: interrupt-controller@e61c0000 {
+                        compatible = "renesas,irqc-r8a7793", "renesas,irqc";
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        reg = <0 0xe61c0000 0 0x200>;
+                        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 407>;
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 407>;
+                };
 
-        cmt1: timer@e6130000 {
-                compatible = "renesas,r8a7793-cmt1", "renesas,rcar-gen2-cmt1";
-                reg = <0 0xe6130000 0 0x1004>;
-                interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 329>;
-                clock-names = "fck";
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 329>;
-
-                status = "disabled";
-        };
+                thermal: thermal@e61f0000 {
+                        compatible = "renesas,thermal-r8a7793",
+                                     "renesas,rcar-gen2-thermal",
+                                     "renesas,rcar-thermal";
+                        reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
+                        interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 522>;
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 522>;
+                        #thermal-sensor-cells = <0>;
+                };
 
-        irqc0: interrupt-controller@e61c0000 {
-                compatible = "renesas,irqc-r8a7793", "renesas,irqc";
-                #interrupt-cells = <2>;
-                interrupt-controller;
-                reg = <0 0xe61c0000 0 0x200>;
-                interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 407>;
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 407>;
-        };
+                ipmmu_sy0: mmu@e6280000 {
+                        compatible = "renesas,ipmmu-r8a7793",
+                                     "renesas,ipmmu-vmsa";
+                        reg = <0 0xe6280000 0 0x1000>;
+                        interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+                        #iommu-cells = <1>;
+                        status = "disabled";
+                };
 
-        dmac0: dma-controller@e6700000 {
-                compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
-                reg = <0 0xe6700000 0 0x20000>;
-                interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
-                interrupt-names = "error",
-                                "ch0", "ch1", "ch2", "ch3",
-                                "ch4", "ch5", "ch6", "ch7",
-                                "ch8", "ch9", "ch10", "ch11",
-                                "ch12", "ch13", "ch14";
-                clocks = <&cpg CPG_MOD 219>;
-                clock-names = "fck";
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 219>;
-                #dma-cells = <1>;
-                dma-channels = <15>;
-        };
+                ipmmu_sy1: mmu@e6290000 {
+                        compatible = "renesas,ipmmu-r8a7793",
+                                     "renesas,ipmmu-vmsa";
+                        reg = <0 0xe6290000 0 0x1000>;
+                        interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+                        #iommu-cells = <1>;
+                        status = "disabled";
+                };
 
-        dmac1: dma-controller@e6720000 {
-                compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
-                reg = <0 0xe6720000 0 0x20000>;
-                interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
-                interrupt-names = "error",
-                                "ch0", "ch1", "ch2", "ch3",
-                                "ch4", "ch5", "ch6", "ch7",
-                                "ch8", "ch9", "ch10", "ch11",
-                                "ch12", "ch13", "ch14";
-                clocks = <&cpg CPG_MOD 218>;
-                clock-names = "fck";
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 218>;
-                #dma-cells = <1>;
-                dma-channels = <15>;
-        };
+                ipmmu_ds: mmu@e6740000 {
+                        compatible = "renesas,ipmmu-r8a7793",
+                                     "renesas,ipmmu-vmsa";
+                        reg = <0 0xe6740000 0 0x1000>;
+                        interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+                        #iommu-cells = <1>;
+                        status = "disabled";
+                };
 
-        audma0: dma-controller@ec700000 {
-                compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
-                reg = <0 0xec700000 0 0x10000>;
-                interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
-                interrupt-names = "error",
-                                "ch0", "ch1", "ch2", "ch3",
-                                "ch4", "ch5", "ch6", "ch7",
-                                "ch8", "ch9", "ch10", "ch11",
-                                "ch12";
-                clocks = <&cpg CPG_MOD 502>;
-                clock-names = "fck";
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 502>;
-                #dma-cells = <1>;
-                dma-channels = <13>;
-        };
+                ipmmu_mp: mmu@ec680000 {
+                        compatible = "renesas,ipmmu-r8a7793",
+                                     "renesas,ipmmu-vmsa";
+                        reg = <0 0xec680000 0 0x1000>;
+                        interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+                        #iommu-cells = <1>;
+                        status = "disabled";
+                };
 
-        audma1: dma-controller@ec720000 {
-                compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
-                reg = <0 0xec720000 0 0x10000>;
-                interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
-                interrupt-names = "error",
-                                "ch0", "ch1", "ch2", "ch3",
-                                "ch4", "ch5", "ch6", "ch7",
-                                "ch8", "ch9", "ch10", "ch11",
-                                "ch12";
-                clocks = <&cpg CPG_MOD 501>;
-                clock-names = "fck";
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 501>;
-                #dma-cells = <1>;
-                dma-channels = <13>;
-        };
+                ipmmu_mx: mmu@fe951000 {
+                        compatible = "renesas,ipmmu-r8a7793",
+                                     "renesas,ipmmu-vmsa";
+                        reg = <0 0xfe951000 0 0x1000>;
+                        interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+                        #iommu-cells = <1>;
+                        status = "disabled";
+                };
 
-        /* The memory map in the User's Manual maps the cores to bus numbers */
-        i2c0: i2c@e6508000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
-                reg = <0 0xe6508000 0 0x40>;
-                interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 931>;
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 931>;
-                i2c-scl-internal-delay-ns = <6>;
-                status = "disabled";
-        };
+                ipmmu_rt: mmu@ffc80000 {
+                        compatible = "renesas,ipmmu-r8a7793",
+                                     "renesas,ipmmu-vmsa";
+                        reg = <0 0xffc80000 0 0x1000>;
+                        interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
+                        #iommu-cells = <1>;
+                        status = "disabled";
+                };
 
-        i2c1: i2c@e6518000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
-                reg = <0 0xe6518000 0 0x40>;
-                interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 930>;
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 930>;
-                i2c-scl-internal-delay-ns = <6>;
-                status = "disabled";
-        };
+                ipmmu_gp: mmu@e62a0000 {
+                        compatible = "renesas,ipmmu-r8a7793",
+                                     "renesas,ipmmu-vmsa";
+                        reg = <0 0xe62a0000 0 0x1000>;
+                        interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+                        #iommu-cells = <1>;
+                        status = "disabled";
+                };
 
-        i2c2: i2c@e6530000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
-                reg = <0 0xe6530000 0 0x40>;
-                interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 929>;
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 929>;
-                i2c-scl-internal-delay-ns = <6>;
-                status = "disabled";
-        };
+                icram0: sram@e63a0000 {
+                        compatible = "mmio-sram";
+                        reg = <0 0xe63a0000 0 0x12000>;
+                };
 
-        i2c3: i2c@e6540000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
-                reg = <0 0xe6540000 0 0x40>;
-                interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 928>;
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 928>;
-                i2c-scl-internal-delay-ns = <6>;
-                status = "disabled";
-        };
+                icram1: sram@e63c0000 {
+                        compatible = "mmio-sram";
+                        reg = <0 0xe63c0000 0 0x1000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0 0xe63c0000 0x1000>;
 
-        i2c4: i2c@e6520000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
-                reg = <0 0xe6520000 0 0x40>;
-                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 927>;
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 927>;
-                i2c-scl-internal-delay-ns = <6>;
-                status = "disabled";
-        };
+                        smp-sram@0 {
+                                compatible = "renesas,smp-sram";
+                                reg = <0 0x10>;
+                        };
+                };
 
-        i2c5: i2c@e6528000 {
-                /* doesn't need pinmux */
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c";
-                reg = <0 0xe6528000 0 0x40>;
-                interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 925>;
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 925>;
-                i2c-scl-internal-delay-ns = <110>;
-                status = "disabled";
-        };
+                /* The memory map in the User's Manual maps the cores to
+                 * bus numbers
+                 */
+                i2c0: i2c@e6508000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a7793",
+                                     "renesas,rcar-gen2-i2c";
+                        reg = <0 0xe6508000 0 0x40>;
+                        interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 931>;
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 931>;
+                        i2c-scl-internal-delay-ns = <6>;
+                        status = "disabled";
+                };
 
-        i2c6: i2c@e60b0000 {
-                /* doesn't need pinmux */
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "renesas,iic-r8a7793", "renesas,rcar-gen2-iic",
-                             "renesas,rmobile-iic";
-                reg = <0 0xe60b0000 0 0x425>;
-                interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 926>;
-                dmas = <&dmac0 0x77>, <&dmac0 0x78>,
-                       <&dmac1 0x77>, <&dmac1 0x78>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 926>;
-                status = "disabled";
-        };
+                i2c1: i2c@e6518000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a7793",
+                                     "renesas,rcar-gen2-i2c";
+                        reg = <0 0xe6518000 0 0x40>;
+                        interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 930>;
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 930>;
+                        i2c-scl-internal-delay-ns = <6>;
+                        status = "disabled";
+                };
 
-        i2c7: i2c@e6500000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "renesas,iic-r8a7793", "renesas,rcar-gen2-iic",
-                             "renesas,rmobile-iic";
-                reg = <0 0xe6500000 0 0x425>;
-                interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 318>;
-                dmas = <&dmac0 0x61>, <&dmac0 0x62>,
-                       <&dmac1 0x61>, <&dmac1 0x62>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 318>;
-                status = "disabled";
-        };
+                i2c2: i2c@e6530000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a7793",
+                                     "renesas,rcar-gen2-i2c";
+                        reg = <0 0xe6530000 0 0x40>;
+                        interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 929>;
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 929>;
+                        i2c-scl-internal-delay-ns = <6>;
+                        status = "disabled";
+                };
 
-        i2c8: i2c@e6510000 {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                compatible = "renesas,iic-r8a7793", "renesas,rcar-gen2-iic",
-                             "renesas,rmobile-iic";
-                reg = <0 0xe6510000 0 0x425>;
-                interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 323>;
-                dmas = <&dmac0 0x65>, <&dmac0 0x66>,
-                       <&dmac1 0x65>, <&dmac1 0x66>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 323>;
-                status = "disabled";
-        };
+                i2c3: i2c@e6540000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a7793",
+                                     "renesas,rcar-gen2-i2c";
+                        reg = <0 0xe6540000 0 0x40>;
+                        interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 928>;
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 928>;
+                        i2c-scl-internal-delay-ns = <6>;
+                        status = "disabled";
+                };
 
-        pfc: pin-controller@e6060000 {
-                compatible = "renesas,pfc-r8a7793";
-                reg = <0 0xe6060000 0 0x250>;
-        };
+                i2c4: i2c@e6520000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a7793",
+                                     "renesas,rcar-gen2-i2c";
+                        reg = <0 0xe6520000 0 0x40>;
+                        interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 927>;
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 927>;
+                        i2c-scl-internal-delay-ns = <6>;
+                        status = "disabled";
+                };
 
-        sdhi0: sd@ee100000 {
-                compatible = "renesas,sdhi-r8a7793",
-                             "renesas,rcar-gen2-sdhi";
-                reg = <0 0xee100000 0 0x328>;
-                interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 314>;
-                dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
-                       <&dmac1 0xcd>, <&dmac1 0xce>;
-                dma-names = "tx", "rx", "tx", "rx";
-                max-frequency = <195000000>;
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 314>;
-                status = "disabled";
-        };
+                i2c5: i2c@e6528000 {
+                        /* doesn't need pinmux */
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a7793",
+                                     "renesas,rcar-gen2-i2c";
+                        reg = <0 0xe6528000 0 0x40>;
+                        interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 925>;
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 925>;
+                        i2c-scl-internal-delay-ns = <110>;
+                        status = "disabled";
+                };
 
-        sdhi1: sd@ee140000 {
-                compatible = "renesas,sdhi-r8a7793",
-                             "renesas,rcar-gen2-sdhi";
-                reg = <0 0xee140000 0 0x100>;
-                interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 312>;
-                dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
-                       <&dmac1 0xc1>, <&dmac1 0xc2>;
-                dma-names = "tx", "rx", "tx", "rx";
-                max-frequency = <97500000>;
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 312>;
-                status = "disabled";
-        };
+                i2c6: i2c@e60b0000 {
+                        /* doesn't need pinmux */
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,iic-r8a7793",
+                                     "renesas,rcar-gen2-iic",
+                                     "renesas,rmobile-iic";
+                        reg = <0 0xe60b0000 0 0x425>;
+                        interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 926>;
+                        dmas = <&dmac0 0x77>, <&dmac0 0x78>,
+                               <&dmac1 0x77>, <&dmac1 0x78>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 926>;
+                        status = "disabled";
+                };
 
-        sdhi2: sd@ee160000 {
-                compatible = "renesas,sdhi-r8a7793",
-                             "renesas,rcar-gen2-sdhi";
-                reg = <0 0xee160000 0 0x100>;
-                interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 311>;
-                dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
-                       <&dmac1 0xd3>, <&dmac1 0xd4>;
-                dma-names = "tx", "rx", "tx", "rx";
-                max-frequency = <97500000>;
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 311>;
-                status = "disabled";
-        };
+                i2c7: i2c@e6500000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,iic-r8a7793",
+                                     "renesas,rcar-gen2-iic",
+                                     "renesas,rmobile-iic";
+                        reg = <0 0xe6500000 0 0x425>;
+                        interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 318>;
+                        dmas = <&dmac0 0x61>, <&dmac0 0x62>,
+                               <&dmac1 0x61>, <&dmac1 0x62>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 318>;
+                        status = "disabled";
+                };
 
-        mmcif0: mmc@ee200000 {
-                compatible = "renesas,mmcif-r8a7793", "renesas,sh-mmcif";
-                reg = <0 0xee200000 0 0x80>;
-                interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 315>;
-                dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
-                       <&dmac1 0xd1>, <&dmac1 0xd2>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 315>;
-                reg-io-width = <4>;
-                status = "disabled";
-                max-frequency = <97500000>;
-        };
+                i2c8: i2c@e6510000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,iic-r8a7793",
+                                     "renesas,rcar-gen2-iic",
+                                     "renesas,rmobile-iic";
+                        reg = <0 0xe6510000 0 0x425>;
+                        interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 323>;
+                        dmas = <&dmac0 0x65>, <&dmac0 0x66>,
+                               <&dmac1 0x65>, <&dmac1 0x66>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 323>;
+                        status = "disabled";
+                };
 
-        scifa0: serial@e6c40000 {
-                compatible = "renesas,scifa-r8a7793",
-                             "renesas,rcar-gen2-scifa", "renesas,scifa";
-                reg = <0 0xe6c40000 0 64>;
-                interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 204>;
-                clock-names = "fck";
-                dmas = <&dmac0 0x21>, <&dmac0 0x22>,
-                       <&dmac1 0x21>, <&dmac1 0x22>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 204>;
-                status = "disabled";
-        };
+                dmac0: dma-controller@e6700000 {
+                        compatible = "renesas,dmac-r8a7793",
+                                     "renesas,rcar-dmac";
+                        reg = <0 0xe6700000 0 0x20000>;
+                        interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "error",
+                                          "ch0", "ch1", "ch2", "ch3",
+                                          "ch4", "ch5", "ch6", "ch7",
+                                          "ch8", "ch9", "ch10", "ch11",
+                                          "ch12", "ch13", "ch14";
+                        clocks = <&cpg CPG_MOD 219>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 219>;
+                        #dma-cells = <1>;
+                        dma-channels = <15>;
+                };
 
-        scifa1: serial@e6c50000 {
-                compatible = "renesas,scifa-r8a7793",
-                             "renesas,rcar-gen2-scifa", "renesas,scifa";
-                reg = <0 0xe6c50000 0 64>;
-                interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 203>;
-                clock-names = "fck";
-                dmas = <&dmac0 0x25>, <&dmac0 0x26>,
-                       <&dmac1 0x25>, <&dmac1 0x26>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 203>;
-                status = "disabled";
-        };
+                dmac1: dma-controller@e6720000 {
+                        compatible = "renesas,dmac-r8a7793",
+                                     "renesas,rcar-dmac";
+                        reg = <0 0xe6720000 0 0x20000>;
+                        interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "error",
+                                          "ch0", "ch1", "ch2", "ch3",
+                                          "ch4", "ch5", "ch6", "ch7",
+                                          "ch8", "ch9", "ch10", "ch11",
+                                          "ch12", "ch13", "ch14";
+                        clocks = <&cpg CPG_MOD 218>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 218>;
+                        #dma-cells = <1>;
+                        dma-channels = <15>;
+                };
 
-        scifa2: serial@e6c60000 {
-                compatible = "renesas,scifa-r8a7793",
-                             "renesas,rcar-gen2-scifa", "renesas,scifa";
-                reg = <0 0xe6c60000 0 64>;
-                interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 202>;
-                clock-names = "fck";
-                dmas = <&dmac0 0x27>, <&dmac0 0x28>,
-                       <&dmac1 0x27>, <&dmac1 0x28>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 202>;
-                status = "disabled";
-        };
+                qspi: spi@e6b10000 {
+                        compatible = "renesas,qspi-r8a7793", "renesas,qspi";
+                        reg = <0 0xe6b10000 0 0x2c>;
+                        interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 917>;
+                        dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+                               <&dmac1 0x17>, <&dmac1 0x18>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 917>;
+                        num-cs = <1>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
 
-        scifa3: serial@e6c70000 {
-                compatible = "renesas,scifa-r8a7793",
-                             "renesas,rcar-gen2-scifa", "renesas,scifa";
-                reg = <0 0xe6c70000 0 64>;
-                interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 1106>;
-                clock-names = "fck";
-                dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
-                       <&dmac1 0x1b>, <&dmac1 0x1c>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 1106>;
-                status = "disabled";
-        };
+                scifa0: serial@e6c40000 {
+                        compatible = "renesas,scifa-r8a7793",
+                                     "renesas,rcar-gen2-scifa", "renesas,scifa";
+                        reg = <0 0xe6c40000 0 64>;
+                        interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 204>;
+                        clock-names = "fck";
+                        dmas = <&dmac0 0x21>, <&dmac0 0x22>,
+                               <&dmac1 0x21>, <&dmac1 0x22>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 204>;
+                        status = "disabled";
+                };
 
-        scifa4: serial@e6c78000 {
-                compatible = "renesas,scifa-r8a7793",
-                             "renesas,rcar-gen2-scifa", "renesas,scifa";
-                reg = <0 0xe6c78000 0 64>;
-                interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 1107>;
-                clock-names = "fck";
-                dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
-                       <&dmac1 0x1f>, <&dmac1 0x20>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 1107>;
-                status = "disabled";
-        };
+                scifa1: serial@e6c50000 {
+                        compatible = "renesas,scifa-r8a7793",
+                                     "renesas,rcar-gen2-scifa", "renesas,scifa";
+                        reg = <0 0xe6c50000 0 64>;
+                        interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 203>;
+                        clock-names = "fck";
+                        dmas = <&dmac0 0x25>, <&dmac0 0x26>,
+                               <&dmac1 0x25>, <&dmac1 0x26>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 203>;
+                        status = "disabled";
+                };
 
-        scifa5: serial@e6c80000 {
-                compatible = "renesas,scifa-r8a7793",
-                             "renesas,rcar-gen2-scifa", "renesas,scifa";
-                reg = <0 0xe6c80000 0 64>;
-                interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 1108>;
-                clock-names = "fck";
-                dmas = <&dmac0 0x23>, <&dmac0 0x24>,
-                       <&dmac1 0x23>, <&dmac1 0x24>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 1108>;
-                status = "disabled";
-        };
+                scifa2: serial@e6c60000 {
+                        compatible = "renesas,scifa-r8a7793",
+                                     "renesas,rcar-gen2-scifa", "renesas,scifa";
+                        reg = <0 0xe6c60000 0 64>;
+                        interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 202>;
+                        clock-names = "fck";
+                        dmas = <&dmac0 0x27>, <&dmac0 0x28>,
+                               <&dmac1 0x27>, <&dmac1 0x28>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 202>;
+                        status = "disabled";
+                };
 
-        scifb0: serial@e6c20000 {
-                compatible = "renesas,scifb-r8a7793",
-                             "renesas,rcar-gen2-scifb", "renesas,scifb";
-                reg = <0 0xe6c20000 0 0x100>;
-                interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 206>;
-                clock-names = "fck";
-                dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
-                       <&dmac1 0x3d>, <&dmac1 0x3e>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 206>;
-                status = "disabled";
-        };
+                scifa3: serial@e6c70000 {
+                        compatible = "renesas,scifa-r8a7793",
+                                     "renesas,rcar-gen2-scifa", "renesas,scifa";
+                        reg = <0 0xe6c70000 0 64>;
+                        interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 1106>;
+                        clock-names = "fck";
+                        dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
+                               <&dmac1 0x1b>, <&dmac1 0x1c>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 1106>;
+                        status = "disabled";
+                };
 
-        scifb1: serial@e6c30000 {
-                compatible = "renesas,scifb-r8a7793",
-                             "renesas,rcar-gen2-scifb", "renesas,scifb";
-                reg = <0 0xe6c30000 0 0x100>;
-                interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 207>;
-                clock-names = "fck";
-                dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
-                       <&dmac1 0x19>, <&dmac1 0x1a>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 207>;
-                status = "disabled";
-        };
+                scifa4: serial@e6c78000 {
+                        compatible = "renesas,scifa-r8a7793",
+                                     "renesas,rcar-gen2-scifa", "renesas,scifa";
+                        reg = <0 0xe6c78000 0 64>;
+                        interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 1107>;
+                        clock-names = "fck";
+                        dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
+                               <&dmac1 0x1f>, <&dmac1 0x20>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 1107>;
+                        status = "disabled";
+                };
 
-        scifb2: serial@e6ce0000 {
-                compatible = "renesas,scifb-r8a7793",
-                             "renesas,rcar-gen2-scifb", "renesas,scifb";
-                reg = <0 0xe6ce0000 0 0x100>;
-                interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 216>;
-                clock-names = "fck";
-                dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
-                       <&dmac1 0x1d>, <&dmac1 0x1e>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 216>;
-                status = "disabled";
-        };
+                scifa5: serial@e6c80000 {
+                        compatible = "renesas,scifa-r8a7793",
+                                     "renesas,rcar-gen2-scifa", "renesas,scifa";
+                        reg = <0 0xe6c80000 0 64>;
+                        interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 1108>;
+                        clock-names = "fck";
+                        dmas = <&dmac0 0x23>, <&dmac0 0x24>,
+                               <&dmac1 0x23>, <&dmac1 0x24>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 1108>;
+                        status = "disabled";
+                };
 
-        scif0: serial@e6e60000 {
-                compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
-                             "renesas,scif";
-                reg = <0 0xe6e60000 0 64>;
-                interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
-                         <&scif_clk>;
-                clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
-                       <&dmac1 0x29>, <&dmac1 0x2a>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 721>;
-                status = "disabled";
-        };
+                scifb0: serial@e6c20000 {
+                        compatible = "renesas,scifb-r8a7793",
+                                     "renesas,rcar-gen2-scifb", "renesas,scifb";
+                        reg = <0 0xe6c20000 0 0x100>;
+                        interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 206>;
+                        clock-names = "fck";
+                        dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
+                               <&dmac1 0x3d>, <&dmac1 0x3e>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 206>;
+                        status = "disabled";
+                };
 
-        scif1: serial@e6e68000 {
-                compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
-                             "renesas,scif";
-                reg = <0 0xe6e68000 0 64>;
-                interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
-                         <&scif_clk>;
-                clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
-                       <&dmac1 0x2d>, <&dmac1 0x2e>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 720>;
-                status = "disabled";
-        };
+                scifb1: serial@e6c30000 {
+                        compatible = "renesas,scifb-r8a7793",
+                                     "renesas,rcar-gen2-scifb", "renesas,scifb";
+                        reg = <0 0xe6c30000 0 0x100>;
+                        interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 207>;
+                        clock-names = "fck";
+                        dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
+                               <&dmac1 0x19>, <&dmac1 0x1a>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 207>;
+                        status = "disabled";
+                };
 
-        scif2: serial@e6e58000 {
-                compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
-                             "renesas,scif";
-                reg = <0 0xe6e58000 0 64>;
-                interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
-                         <&scif_clk>;
-                clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
-                       <&dmac1 0x2b>, <&dmac1 0x2c>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 719>;
-                status = "disabled";
-        };
+                scifb2: serial@e6ce0000 {
+                        compatible = "renesas,scifb-r8a7793",
+                                     "renesas,rcar-gen2-scifb", "renesas,scifb";
+                        reg = <0 0xe6ce0000 0 0x100>;
+                        interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 216>;
+                        clock-names = "fck";
+                        dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
+                               <&dmac1 0x1d>, <&dmac1 0x1e>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 216>;
+                        status = "disabled";
+                };
 
-        scif3: serial@e6ea8000 {
-                compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
-                             "renesas,scif";
-                reg = <0 0xe6ea8000 0 64>;
-                interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
-                         <&scif_clk>;
-                clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
-                       <&dmac1 0x2f>, <&dmac1 0x30>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 718>;
-                status = "disabled";
-        };
+                scif0: serial@e6e60000 {
+                        compatible = "renesas,scif-r8a7793",
+                                     "renesas,rcar-gen2-scif", "renesas,scif";
+                        reg = <0 0xe6e60000 0 64>;
+                        interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+                               <&dmac1 0x29>, <&dmac1 0x2a>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 721>;
+                        status = "disabled";
+                };
 
-        scif4: serial@e6ee0000 {
-                compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
-                             "renesas,scif";
-                reg = <0 0xe6ee0000 0 64>;
-                interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
-                         <&scif_clk>;
-                clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
-                       <&dmac1 0xfb>, <&dmac1 0xfc>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 715>;
-                status = "disabled";
-        };
+                scif1: serial@e6e68000 {
+                        compatible = "renesas,scif-r8a7793",
+                                     "renesas,rcar-gen2-scif", "renesas,scif";
+                        reg = <0 0xe6e68000 0 64>;
+                        interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+                               <&dmac1 0x2d>, <&dmac1 0x2e>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 720>;
+                        status = "disabled";
+                };
 
-        scif5: serial@e6ee8000 {
-                compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
-                             "renesas,scif";
-                reg = <0 0xe6ee8000 0 64>;
-                interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
-                         <&scif_clk>;
-                clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
-                       <&dmac1 0xfd>, <&dmac1 0xfe>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 714>;
-                status = "disabled";
-        };
+                scif2: serial@e6e58000 {
+                        compatible = "renesas,scif-r8a7793",
+                                     "renesas,rcar-gen2-scif", "renesas,scif";
+                        reg = <0 0xe6e58000 0 64>;
+                        interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+                               <&dmac1 0x2b>, <&dmac1 0x2c>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 719>;
+                        status = "disabled";
+                };
 
-        hscif0: serial@e62c0000 {
-                compatible = "renesas,hscif-r8a7793",
-                             "renesas,rcar-gen2-hscif", "renesas,hscif";
-                reg = <0 0xe62c0000 0 96>;
-                interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
-                         <&scif_clk>;
-                clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
-                       <&dmac1 0x39>, <&dmac1 0x3a>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 717>;
-                status = "disabled";
-        };
+                scif3: serial@e6ea8000 {
+                        compatible = "renesas,scif-r8a7793",
+                                     "renesas,rcar-gen2-scif", "renesas,scif";
+                        reg = <0 0xe6ea8000 0 64>;
+                        interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
+                               <&dmac1 0x2f>, <&dmac1 0x30>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 718>;
+                        status = "disabled";
+                };
 
-        hscif1: serial@e62c8000 {
-                compatible = "renesas,hscif-r8a7793",
-                             "renesas,rcar-gen2-hscif", "renesas,hscif";
-                reg = <0 0xe62c8000 0 96>;
-                interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
-                         <&scif_clk>;
-                clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
-                       <&dmac1 0x4d>, <&dmac1 0x4e>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 716>;
-                status = "disabled";
-        };
+                scif4: serial@e6ee0000 {
+                        compatible = "renesas,scif-r8a7793",
+                                     "renesas,rcar-gen2-scif", "renesas,scif";
+                        reg = <0 0xe6ee0000 0 64>;
+                        interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
+                               <&dmac1 0xfb>, <&dmac1 0xfc>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 715>;
+                        status = "disabled";
+                };
 
-        hscif2: serial@e62d0000 {
-                compatible = "renesas,hscif-r8a7793",
-                             "renesas,rcar-gen2-hscif", "renesas,hscif";
-                reg = <0 0xe62d0000 0 96>;
-                interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
-                         <&scif_clk>;
-                clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
-                       <&dmac1 0x3b>, <&dmac1 0x3c>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 713>;
-                status = "disabled";
-        };
+                scif5: serial@e6ee8000 {
+                        compatible = "renesas,scif-r8a7793",
+                                     "renesas,rcar-gen2-scif", "renesas,scif";
+                        reg = <0 0xe6ee8000 0 64>;
+                        interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
+                               <&dmac1 0xfd>, <&dmac1 0xfe>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 714>;
+                        status = "disabled";
+                };
 
-        icram0: sram@e63a0000 {
-                compatible = "mmio-sram";
-                reg = <0 0xe63a0000 0 0x12000>;
-        };
+                hscif0: serial@e62c0000 {
+                        compatible = "renesas,hscif-r8a7793",
+                                     "renesas,rcar-gen2-hscif", "renesas,hscif";
+                        reg = <0 0xe62c0000 0 96>;
+                        interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+                               <&dmac1 0x39>, <&dmac1 0x3a>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 717>;
+                        status = "disabled";
+                };
 
-        icram1: sram@e63c0000 {
-                compatible = "mmio-sram";
-                reg = <0 0xe63c0000 0 0x1000>;
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges = <0 0 0xe63c0000 0x1000>;
+                hscif1: serial@e62c8000 {
+                        compatible = "renesas,hscif-r8a7793",
+                                     "renesas,rcar-gen2-hscif", "renesas,hscif";
+                        reg = <0 0xe62c8000 0 96>;
+                        interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+                               <&dmac1 0x4d>, <&dmac1 0x4e>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 716>;
+                        status = "disabled";
+                };
 
-                smp-sram@0 {
-                        compatible = "renesas,smp-sram";
-                        reg = <0 0x10>;
+                hscif2: serial@e62d0000 {
+                        compatible = "renesas,hscif-r8a7793",
+                                     "renesas,rcar-gen2-hscif", "renesas,hscif";
+                        reg = <0 0xe62d0000 0 96>;
+                        interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7793_CLK_ZS>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
+                               <&dmac1 0x3b>, <&dmac1 0x3c>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 713>;
+                        status = "disabled";
                 };
-        };
 
-        ether: ethernet@ee700000 {
-                compatible = "renesas,ether-r8a7793",
-                             "renesas,rcar-gen2-ether";
-                reg = <0 0xee700000 0 0x400>;
-                interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 813>;
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 813>;
-                phy-mode = "rmii";
-                #address-cells = <1>;
-                #size-cells = <0>;
-                status = "disabled";
-        };
+                can0: can@e6e80000 {
+                        compatible = "renesas,can-r8a7793",
+                                     "renesas,rcar-gen2-can";
+                        reg = <0 0xe6e80000 0 0x1000>;
+                        interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7793_CLK_RCAN>,
+                                 <&can_clk>;
+                        clock-names = "clkp1", "clkp2", "can_clk";
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 916>;
+                        status = "disabled";
+                };
 
-        vin0: video@e6ef0000 {
-                compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin";
-                reg = <0 0xe6ef0000 0 0x1000>;
-                interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 811>;
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 811>;
-                status = "disabled";
-        };
+                can1: can@e6e88000 {
+                        compatible = "renesas,can-r8a7793",
+                                     "renesas,rcar-gen2-can";
+                        reg = <0 0xe6e88000 0 0x1000>;
+                        interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7793_CLK_RCAN>,
+                                 <&can_clk>;
+                        clock-names = "clkp1", "clkp2", "can_clk";
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 915>;
+                        status = "disabled";
+                };
 
-        vin1: video@e6ef1000 {
-                compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin";
-                reg = <0 0xe6ef1000 0 0x1000>;
-                interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 810>;
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 810>;
-                status = "disabled";
-        };
+                vin0: video@e6ef0000 {
+                        compatible = "renesas,vin-r8a7793",
+                                     "renesas,rcar-gen2-vin";
+                        reg = <0 0xe6ef0000 0 0x1000>;
+                        interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 811>;
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 811>;
+                        status = "disabled";
+                };
 
-        vin2: video@e6ef2000 {
-                compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin";
-                reg = <0 0xe6ef2000 0 0x1000>;
-                interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 809>;
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 809>;
-                status = "disabled";
-        };
+                vin1: video@e6ef1000 {
+                        compatible = "renesas,vin-r8a7793",
+                                     "renesas,rcar-gen2-vin";
+                        reg = <0 0xe6ef1000 0 0x1000>;
+                        interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 810>;
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 810>;
+                        status = "disabled";
+                };
 
-        qspi: spi@e6b10000 {
-                compatible = "renesas,qspi-r8a7793", "renesas,qspi";
-                reg = <0 0xe6b10000 0 0x2c>;
-                interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 917>;
-                dmas = <&dmac0 0x17>, <&dmac0 0x18>,
-                       <&dmac1 0x17>, <&dmac1 0x18>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 917>;
-                num-cs = <1>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                status = "disabled";
-        };
+                vin2: video@e6ef2000 {
+                        compatible = "renesas,vin-r8a7793",
+                                     "renesas,rcar-gen2-vin";
+                        reg = <0 0xe6ef2000 0 0x1000>;
+                        interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 809>;
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 809>;
+                        status = "disabled";
+                };
 
-        du: display@feb00000 {
-                compatible = "renesas,du-r8a7793";
-                reg = <0 0xfeb00000 0 0x40000>,
-                      <0 0xfeb90000 0 0x1c>;
-                reg-names = "du", "lvds.0";
-                interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 724>,
-                         <&cpg CPG_MOD 723>,
-                         <&cpg CPG_MOD 726>;
-                clock-names = "du.0", "du.1", "lvds.0";
-                status = "disabled";
-
-                ports {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
+                rcar_sound: sound@ec500000 {
+                        /*
+                         * #sound-dai-cells is required
+                         *
+                         * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
+                         * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
+                         */
+                        compatible = "renesas,rcar_sound-r8a7793",
+                                     "renesas,rcar_sound-gen2";
+                        reg = <0 0xec500000 0 0x1000>, /* SCU */
+                              <0 0xec5a0000 0 0x100>,  /* ADG */
+                              <0 0xec540000 0 0x1000>, /* SSIU */
+                              <0 0xec541000 0 0x280>,  /* SSI */
+                              <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
+                        reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+                        clocks = <&cpg CPG_MOD 1005>,
+                                 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+                                 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+                                 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+                                 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+                                 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+                                 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+                                 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+                                 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+                                 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+                                 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+                                 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+                                 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
+                                 <&cpg CPG_CORE R8A7793_CLK_M2>;
+                        clock-names = "ssi-all",
+                                      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+                                      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+                                      "ssi.1", "ssi.0",
+                                      "src.9", "src.8", "src.7", "src.6",
+                                      "src.5", "src.4", "src.3", "src.2",
+                                      "src.1", "src.0",
+                                      "dvc.0", "dvc.1",
+                                      "clk_a", "clk_b", "clk_c", "clk_i";
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 1005>,
+                                 <&cpg 1006>, <&cpg 1007>,
+                                 <&cpg 1008>, <&cpg 1009>,
+                                 <&cpg 1010>, <&cpg 1011>,
+                                 <&cpg 1012>, <&cpg 1013>,
+                                 <&cpg 1014>, <&cpg 1015>;
+                        reset-names = "ssi-all",
+                                      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+                                      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+                                      "ssi.1", "ssi.0";
+
+                        status = "disabled";
+
+                        rcar_sound,dvc {
+                                dvc0: dvc-0 {
+                                        dmas = <&audma1 0xbc>;
+                                        dma-names = "tx";
+                                };
+                                dvc1: dvc-1 {
+                                        dmas = <&audma1 0xbe>;
+                                        dma-names = "tx";
+                                };
+                        };
 
-                        port@0 {
-                                reg = <0>;
-                                du_out_rgb: endpoint {
+                        rcar_sound,src {
+                                src0: src-0 {
+                                        interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x85>, <&audma1 0x9a>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src1: src-1 {
+                                        interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x87>, <&audma1 0x9c>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src2: src-2 {
+                                        interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x89>, <&audma1 0x9e>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src3: src-3 {
+                                        interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x8b>, <&audma1 0xa0>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src4: src-4 {
+                                        interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x8d>, <&audma1 0xb0>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src5: src-5 {
+                                        interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x8f>, <&audma1 0xb2>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src6: src-6 {
+                                        interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x91>, <&audma1 0xb4>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src7: src-7 {
+                                        interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x93>, <&audma1 0xb6>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src8: src-8 {
+                                        interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x95>, <&audma1 0xb8>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src9: src-9 {
+                                        interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x97>, <&audma1 0xba>;
+                                        dma-names = "rx", "tx";
                                 };
                         };
-                        port@1 {
-                                reg = <1>;
-                                du_out_lvds0: endpoint {
+
+                        rcar_sound,ssi {
+                                ssi0: ssi-0 {
+                                        interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x01>, <&audma1 0x02>,
+                                               <&audma0 0x15>, <&audma1 0x16>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi1: ssi-1 {
+                                         interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x03>, <&audma1 0x04>,
+                                               <&audma0 0x49>, <&audma1 0x4a>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi2: ssi-2 {
+                                        interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x05>, <&audma1 0x06>,
+                                               <&audma0 0x63>, <&audma1 0x64>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi3: ssi-3 {
+                                        interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x07>, <&audma1 0x08>,
+                                               <&audma0 0x6f>, <&audma1 0x70>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi4: ssi-4 {
+                                        interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x09>, <&audma1 0x0a>,
+                                               <&audma0 0x71>, <&audma1 0x72>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi5: ssi-5 {
+                                        interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x0b>, <&audma1 0x0c>,
+                                               <&audma0 0x73>, <&audma1 0x74>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi6: ssi-6 {
+                                        interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x0d>, <&audma1 0x0e>,
+                                               <&audma0 0x75>, <&audma1 0x76>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi7: ssi-7 {
+                                        interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x0f>, <&audma1 0x10>,
+                                               <&audma0 0x79>, <&audma1 0x7a>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi8: ssi-8 {
+                                        interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x11>, <&audma1 0x12>,
+                                               <&audma0 0x7b>, <&audma1 0x7c>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi9: ssi-9 {
+                                        interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x13>, <&audma1 0x14>,
+                                               <&audma0 0x7d>, <&audma1 0x7e>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
                                 };
                         };
                 };
-        };
 
-        can0: can@e6e80000 {
-                compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can";
-                reg = <0 0xe6e80000 0 0x1000>;
-                interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7793_CLK_RCAN>,
-                         <&can_clk>;
-                clock-names = "clkp1", "clkp2", "can_clk";
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 916>;
-                status = "disabled";
-        };
-
-        can1: can@e6e88000 {
-                compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can";
-                reg = <0 0xe6e88000 0 0x1000>;
-                interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7793_CLK_RCAN>,
-                         <&can_clk>;
-                clock-names = "clkp1", "clkp2", "can_clk";
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 915>;
-                status = "disabled";
-        };
-
-        /* External root clock */
-        extal_clk: extal {
-                compatible = "fixed-clock";
-                #clock-cells = <0>;
-                /* This value must be overridden by the board. */
-                clock-frequency = <0>;
-        };
-
-        /*
-         * The external audio clocks are configured as 0 Hz fixed frequency
-         * clocks by default.
-         * Boards that provide audio clocks should override them.
-         */
-        audio_clk_a: audio_clk_a {
-                compatible = "fixed-clock";
-                #clock-cells = <0>;
-                clock-frequency = <0>;
-        };
-        audio_clk_b: audio_clk_b {
-                compatible = "fixed-clock";
-                #clock-cells = <0>;
-                clock-frequency = <0>;
-        };
-        audio_clk_c: audio_clk_c {
-                compatible = "fixed-clock";
-                #clock-cells = <0>;
-                clock-frequency = <0>;
-        };
-
-        /* External USB clock - can be overridden by the board */
-        usb_extal_clk: usb_extal {
-                compatible = "fixed-clock";
-                #clock-cells = <0>;
-                clock-frequency = <48000000>;
-        };
+                audma0: dma-controller@ec700000 {
+                        compatible = "renesas,dmac-r8a7793",
+                                     "renesas,rcar-dmac";
+                        reg = <0 0xec700000 0 0x10000>;
+                        interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "error",
+                                          "ch0", "ch1", "ch2", "ch3",
+                                          "ch4", "ch5", "ch6", "ch7",
+                                          "ch8", "ch9", "ch10", "ch11",
+                                          "ch12";
+                        clocks = <&cpg CPG_MOD 502>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 502>;
+                        #dma-cells = <1>;
+                        dma-channels = <13>;
+                };
 
-        /* External CAN clock */
-        can_clk: can {
-                compatible = "fixed-clock";
-                #clock-cells = <0>;
-                /* This value must be overridden by the board. */
-                clock-frequency = <0>;
-        };
+                audma1: dma-controller@ec720000 {
+                        compatible = "renesas,dmac-r8a7793",
+                                     "renesas,rcar-dmac";
+                        reg = <0 0xec720000 0 0x10000>;
+                        interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "error",
+                                          "ch0", "ch1", "ch2", "ch3",
+                                          "ch4", "ch5", "ch6", "ch7",
+                                          "ch8", "ch9", "ch10", "ch11",
+                                          "ch12";
+                        clocks = <&cpg CPG_MOD 501>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 501>;
+                        #dma-cells = <1>;
+                        dma-channels = <13>;
+                };
 
-        /* External SCIF clock */
-        scif_clk: scif {
-                compatible = "fixed-clock";
-                #clock-cells = <0>;
-                /* This value must be overridden by the board. */
-                clock-frequency = <0>;
-        };
+                sdhi0: sd@ee100000 {
+                        compatible = "renesas,sdhi-r8a7793",
+                                     "renesas,rcar-gen2-sdhi";
+                        reg = <0 0xee100000 0 0x328>;
+                        interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 314>;
+                        dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+                               <&dmac1 0xcd>, <&dmac1 0xce>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        max-frequency = <195000000>;
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 314>;
+                        status = "disabled";
+                };
 
-        /* Special CPG clocks */
-        cpg: clock-controller@e6150000 {
-                compatible = "renesas,r8a7793-cpg-mssr";
-                reg = <0 0xe6150000 0 0x1000>;
-                clocks = <&extal_clk>, <&usb_extal_clk>;
-                clock-names = "extal", "usb_extal";
-                #clock-cells = <2>;
-                #power-domain-cells = <0>;
-                #reset-cells = <1>;
-        };
+                sdhi1: sd@ee140000 {
+                        compatible = "renesas,sdhi-r8a7793",
+                                     "renesas,rcar-gen2-sdhi";
+                        reg = <0 0xee140000 0 0x100>;
+                        interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 312>;
+                        dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+                               <&dmac1 0xc1>, <&dmac1 0xc2>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        max-frequency = <97500000>;
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 312>;
+                        status = "disabled";
+                };
 
-        rst: reset-controller@e6160000 {
-                compatible = "renesas,r8a7793-rst";
-                reg = <0 0xe6160000 0 0x0100>;
-        };
+                sdhi2: sd@ee160000 {
+                        compatible = "renesas,sdhi-r8a7793",
+                                     "renesas,rcar-gen2-sdhi";
+                        reg = <0 0xee160000 0 0x100>;
+                        interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 311>;
+                        dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+                               <&dmac1 0xd3>, <&dmac1 0xd4>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        max-frequency = <97500000>;
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 311>;
+                        status = "disabled";
+                };
 
-        prr: chipid@ff000044 {
-                compatible = "renesas,prr";
-                reg = <0 0xff000044 0 4>;
-        };
+                mmcif0: mmc@ee200000 {
+                        compatible = "renesas,mmcif-r8a7793",
+                                     "renesas,sh-mmcif";
+                        reg = <0 0xee200000 0 0x80>;
+                        interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 315>;
+                        dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+                               <&dmac1 0xd1>, <&dmac1 0xd2>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 315>;
+                        reg-io-width = <4>;
+                        status = "disabled";
+                        max-frequency = <97500000>;
+                };
 
-        sysc: system-controller@e6180000 {
-                compatible = "renesas,r8a7793-sysc";
-                reg = <0 0xe6180000 0 0x0200>;
-                #power-domain-cells = <1>;
-        };
+                ether: ethernet@ee700000 {
+                        compatible = "renesas,ether-r8a7793",
+                                     "renesas,rcar-gen2-ether";
+                        reg = <0 0xee700000 0 0x400>;
+                        interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 813>;
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 813>;
+                        phy-mode = "rmii";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
 
-        ipmmu_sy0: mmu@e6280000 {
-                compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
-                reg = <0 0xe6280000 0 0x1000>;
-                interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
-                #iommu-cells = <1>;
-                status = "disabled";
-        };
+                gic: interrupt-controller@f1001000 {
+                        compatible = "arm,gic-400";
+                        #interrupt-cells = <3>;
+                        #address-cells = <0>;
+                        interrupt-controller;
+                        reg = <0 0xf1001000 0 0x1000>,
+                                <0 0xf1002000 0 0x2000>,
+                                <0 0xf1004000 0 0x2000>,
+                                <0 0xf1006000 0 0x2000>;
+                        interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+                        clocks = <&cpg CPG_MOD 408>;
+                        clock-names = "clk";
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 408>;
+                };
 
-        ipmmu_sy1: mmu@e6290000 {
-                compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
-                reg = <0 0xe6290000 0 0x1000>;
-                interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
-                #iommu-cells = <1>;
-                status = "disabled";
-        };
+                du: display@feb00000 {
+                        compatible = "renesas,du-r8a7793";
+                        reg = <0 0xfeb00000 0 0x40000>,
+                              <0 0xfeb90000 0 0x1c>;
+                        reg-names = "du", "lvds.0";
+                        interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 724>,
+                                 <&cpg CPG_MOD 723>,
+                                 <&cpg CPG_MOD 726>;
+                        clock-names = "du.0", "du.1", "lvds.0";
+                        status = "disabled";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@0 {
+                                        reg = <0>;
+                                        du_out_rgb: endpoint {
+                                        };
+                                };
+                                port@1 {
+                                        reg = <1>;
+                                        du_out_lvds0: endpoint {
+                                        };
+                                };
+                        };
+                };
 
-        ipmmu_ds: mmu@e6740000 {
-                compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
-                reg = <0 0xe6740000 0 0x1000>;
-                interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
-                #iommu-cells = <1>;
-                status = "disabled";
-        };
+                prr: chipid@ff000044 {
+                        compatible = "renesas,prr";
+                        reg = <0 0xff000044 0 4>;
+                };
 
-        ipmmu_mp: mmu@ec680000 {
-                compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
-                reg = <0 0xec680000 0 0x1000>;
-                interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
-                #iommu-cells = <1>;
-                status = "disabled";
-        };
+                cmt0: timer@ffca0000 {
+                        compatible = "renesas,r8a7793-cmt0",
+                                     "renesas,rcar-gen2-cmt0";
+                        reg = <0 0xffca0000 0 0x1004>;
+                        interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 124>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 124>;
+
+                        status = "disabled";
+                };
 
-        ipmmu_mx: mmu@fe951000 {
-                compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
-                reg = <0 0xfe951000 0 0x1000>;
-                interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
-                #iommu-cells = <1>;
-                status = "disabled";
+                cmt1: timer@e6130000 {
+                        compatible = "renesas,r8a7793-cmt1",
+                                     "renesas,rcar-gen2-cmt1";
+                        reg = <0 0xe6130000 0 0x1004>;
+                        interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 329>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                        resets = <&cpg 329>;
+
+                        status = "disabled";
+                };
         };
 
-        ipmmu_rt: mmu@ffc80000 {
-                compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
-                reg = <0 0xffc80000 0 0x1000>;
-                interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
-                #iommu-cells = <1>;
-                status = "disabled";
-        };
+        thermal-zones {
+                cpu_thermal: cpu-thermal {
+                        polling-delay-passive = <0>;
+                        polling-delay = <0>;
 
-        ipmmu_gp: mmu@e62a0000 {
-                compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
-                reg = <0 0xe62a0000 0 0x1000>;
-                interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
-                #iommu-cells = <1>;
-                status = "disabled";
-        };
+                        thermal-sensors = <&thermal>;
 
-        rcar_sound: sound@ec500000 {
-                /*
-                 * #sound-dai-cells is required
-                 *
-                 * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
-                 * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
-                 */
-                compatible =  "renesas,rcar_sound-r8a7793", "renesas,rcar_sound-gen2";
-                reg =   <0 0xec500000 0 0x1000>, /* SCU */
-                        <0 0xec5a0000 0 0x100>,  /* ADG */
-                        <0 0xec540000 0 0x1000>, /* SSIU */
-                        <0 0xec541000 0 0x280>,  /* SSI */
-                        <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
-                reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
-
-                clocks = <&cpg CPG_MOD 1005>,
-                         <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
-                         <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
-                         <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
-                         <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
-                         <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
-                         <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
-                         <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
-                         <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
-                         <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
-                         <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
-                         <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
-                         <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
-                         <&cpg CPG_CORE R8A7793_CLK_M2>;
-                clock-names = "ssi-all",
-                                "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
-                                "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
-                                "src.9", "src.8", "src.7", "src.6", "src.5",
-                                "src.4", "src.3", "src.2", "src.1", "src.0",
-                                "dvc.0", "dvc.1",
-                                "clk_a", "clk_b", "clk_c", "clk_i";
-                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
-                resets = <&cpg 1005>,
-                         <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>,
-                         <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>,
-                         <&cpg 1014>, <&cpg 1015>;
-                reset-names = "ssi-all",
-                              "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
-                              "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0";
-
-                status = "disabled";
-
-                rcar_sound,dvc {
-                        dvc0: dvc-0 {
-                                dmas = <&audma1 0xbc>;
-                                dma-names = "tx";
+                        trips {
+                                cpu-crit {
+                                        temperature = <95000>;
+                                        hysteresis = <0>;
+                                        type = "critical";
+                                };
                         };
-                        dvc1: dvc-1 {
-                                dmas = <&audma1 0xbe>;
-                                dma-names = "tx";
+                        cooling-maps {
                         };
                 };
+        };
 
-                rcar_sound,src {
-                        src0: src-0 {
-                                interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x85>, <&audma1 0x9a>;
-                                dma-names = "rx", "tx";
-                        };
-                        src1: src-1 {
-                                interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x87>, <&audma1 0x9c>;
-                                dma-names = "rx", "tx";
-                        };
-                        src2: src-2 {
-                                interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x89>, <&audma1 0x9e>;
-                                dma-names = "rx", "tx";
-                        };
-                        src3: src-3 {
-                                interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x8b>, <&audma1 0xa0>;
-                                dma-names = "rx", "tx";
-                        };
-                        src4: src-4 {
-                                interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x8d>, <&audma1 0xb0>;
-                                dma-names = "rx", "tx";
-                        };
-                        src5: src-5 {
-                                interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x8f>, <&audma1 0xb2>;
-                                dma-names = "rx", "tx";
-                        };
-                        src6: src-6 {
-                                interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x91>, <&audma1 0xb4>;
-                                dma-names = "rx", "tx";
-                        };
-                        src7: src-7 {
-                                interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x93>, <&audma1 0xb6>;
-                                dma-names = "rx", "tx";
-                        };
-                        src8: src-8 {
-                                interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x95>, <&audma1 0xb8>;
-                                dma-names = "rx", "tx";
-                        };
-                        src9: src-9 {
-                                interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x97>, <&audma1 0xba>;
-                                dma-names = "rx", "tx";
-                        };
-                };
+        timer {
+                compatible = "arm,armv7-timer";
+                interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                                      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                                      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                                      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+        };
 
-                rcar_sound,ssi {
-                        ssi0: ssi-0 {
-                                interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
-                                dma-names = "rx", "tx", "rxu", "txu";
-                        };
-                        ssi1: ssi-1 {
-                                 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
-                                dma-names = "rx", "tx", "rxu", "txu";
-                        };
-                        ssi2: ssi-2 {
-                                interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
-                                dma-names = "rx", "tx", "rxu", "txu";
-                        };
-                        ssi3: ssi-3 {
-                                interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
-                                dma-names = "rx", "tx", "rxu", "txu";
-                        };
-                        ssi4: ssi-4 {
-                                interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
-                                dma-names = "rx", "tx", "rxu", "txu";
-                        };
-                        ssi5: ssi-5 {
-                                interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
-                                dma-names = "rx", "tx", "rxu", "txu";
-                        };
-                        ssi6: ssi-6 {
-                                interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
-                                dma-names = "rx", "tx", "rxu", "txu";
-                        };
-                        ssi7: ssi-7 {
-                                interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
-                                dma-names = "rx", "tx", "rxu", "txu";
-                        };
-                        ssi8: ssi-8 {
-                                interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
-                                dma-names = "rx", "tx", "rxu", "txu";
-                        };
-                        ssi9: ssi-9 {
-                                interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
-                                dma-names = "rx", "tx", "rxu", "txu";
-                        };
-                };
+        /* External USB clock - can be overridden by the board */
+        usb_extal_clk: usb_extal {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <48000000>;
         };
 };
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
index 60c6515c4996..26a883484ea8 100644
--- a/arch/arm/boot/dts/r8a7794-alt.dts
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -18,7 +18,9 @@
 
         aliases {
                 serial0 = &scif2;
+                i2c9 = &gpioi2c1;
                 i2c10 = &gpioi2c4;
+                i2c11 = &i2chdmi;
                 i2c12 = &i2cexio4;
         };
 
@@ -138,17 +140,50 @@
                 clock-frequency = <148500000>;
         };
 
+        gpioi2c1: i2c-9 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "i2c-gpio";
+                status = "disabled";
+                scl-gpios = <&gpio4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+                sda-gpios = <&gpio4 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+        };
+
         gpioi2c4: i2c-10 {
                 #address-cells = <1>;
                 #size-cells = <0>;
                 compatible = "i2c-gpio";
                 status = "disabled";
-                sda-gpios = <&gpio4 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
                 scl-gpios = <&gpio4 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+                sda-gpios = <&gpio4 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
                 i2c-gpio,delay-us = <5>;
         };
 
         /*
+         * A fallback to GPIO is provided for I2C1.
+         */
+        i2chdmi: i2c-11 {
+                compatible = "i2c-demux-pinctrl";
+                i2c-parent = <&i2c1>, <&gpioi2c1>;
+                i2c-bus-name = "i2c-hdmi";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                composite-in@20 {
+                        compatible = "adi,adv7180";
+                        reg = <0x20>;
+                        remote = <&vin0>;
+
+                        port {
+                                adv7180: endpoint {
+                                        bus-width = <8>;
+                                        remote-endpoint = <&vin0ep>;
+                                };
+                        };
+                };
+        };
+
+        /*
          * I2C4 is routed to EXIO connector B, pins 73 (SCL) + 74 (SDA).
          * A fallback to GPIO is provided.
          */
@@ -324,23 +359,9 @@
 
 &i2c1 {
         pinctrl-0 = <&i2c1_pins>;
-        pinctrl-names = "default";
+        pinctrl-names = "i2c-hdmi";
 
-        status = "okay";
         clock-frequency = <400000>;
-
-        composite-in@20 {
-                compatible = "adi,adv7180";
-                reg = <0x20>;
-                remote = <&vin0>;
-
-                port {
-                        adv7180: endpoint {
-                                bus-width = <8>;
-                                remote-endpoint = <&vin0ep>;
-                        };
-                };
-        };
 };
 
 &i2c4 {
diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts
index edfad0e5ac53..351cb3b3d966 100644
--- a/arch/arm/boot/dts/r8a7794-silk.dts
+++ b/arch/arm/boot/dts/r8a7794-silk.dts
@@ -24,6 +24,7 @@
 /dts-v1/;
 #include "r8a7794.dtsi"
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
 
 / {
         model = "SILK";
@@ -31,6 +32,8 @@
 
         aliases {
                 serial0 = &scif2;
+                i2c9 = &gpioi2c1;
+                i2c10 = &i2chdmi;
         };
 
         chosen {
@@ -43,6 +46,60 @@
                 reg = <0 0x40000000 0 0x40000000>;
         };
 
+        gpio-keys {
+                compatible = "gpio-keys";
+
+                key-3 {
+                        gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_3>;
+                        label = "SW3";
+                        wakeup-source;
+                        debounce-interval = <20>;
+                };
+                key-4 {
+                        gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_4>;
+                        label = "SW4";
+                        wakeup-source;
+                        debounce-interval = <20>;
+                };
+                key-6 {
+                        gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_6>;
+                        label = "SW6";
+                        wakeup-source;
+                        debounce-interval = <20>;
+                };
+                key-a {
+                        gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_A>;
+                        label = "SW12-1";
+                        wakeup-source;
+                        debounce-interval = <20>;
+                };
+                key-b {
+                        gpios = <&gpio3 10 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_B>;
+                        label = "SW12-2";
+                        wakeup-source;
+                        debounce-interval = <20>;
+                };
+                key-c {
+                        gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_C>;
+                        label = "SW12-3";
+                        wakeup-source;
+                        debounce-interval = <20>;
+                };
+                key-d {
+                        gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_D>;
+                        label = "SW12-4";
+                        wakeup-source;
+                        debounce-interval = <20>;
+                };
+        };
+
         d3_3v: regulator-d3-3v {
                 compatible = "regulator-fixed";
                 regulator-name = "D3.3V";
@@ -153,6 +210,84 @@
                         clocks = <&x9_clk>;
                 };
         };
+
+        gpioi2c1: i2c-9 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "i2c-gpio";
+                status = "disabled";
+                scl-gpios = <&gpio4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+                sda-gpios = <&gpio4 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+                i2c-gpio,delay-us = <5>;
+        };
+
+        /*
+         * A fallback to GPIO is provided for I2C1.
+         */
+        i2chdmi: i2c-10 {
+                compatible = "i2c-demux-pinctrl";
+                i2c-parent = <&i2c1>, <&gpioi2c1>;
+                i2c-bus-name = "i2c-hdmi";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                ak4643: codec@12 {
+                        compatible = "asahi-kasei,ak4643";
+                        #sound-dai-cells = <0>;
+                        reg = <0x12>;
+                };
+
+                composite-in@20 {
+                        compatible = "adi,adv7180";
+                        reg = <0x20>;
+                        remote = <&vin0>;
+
+                        port {
+                                adv7180: endpoint {
+                                        bus-width = <8>;
+                                        remote-endpoint = <&vin0ep>;
+                                };
+                        };
+                };
+
+                hdmi@39 {
+                        compatible = "adi,adv7511w";
+                        reg = <0x39>;
+                        interrupt-parent = <&gpio5>;
+                        interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
+
+                        adi,input-depth = <8>;
+                        adi,input-colorspace = "rgb";
+                        adi,input-clock = "1x";
+                        adi,input-style = <1>;
+                        adi,input-justification = "evenly";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@0 {
+                                        reg = <0>;
+                                        adv7511_in: endpoint {
+                                                remote-endpoint = <&du_out_rgb0>;
+                                        };
+                                };
+
+                                port@1 {
+                                        reg = <1>;
+                                        adv7511_out: endpoint {
+                                                remote-endpoint = <&hdmi_con>;
+                                        };
+                                };
+                        };
+                };
+
+                eeprom@50 {
+                        compatible = "renesas,r1ex24002", "atmel,24c02";
+                        reg = <0x50>;
+                        pagesize = <16>;
+                };
+        };
 };
 
 &extal_clk {
@@ -268,61 +403,9 @@
 
 &i2c1 {
         pinctrl-0 = <&i2c1_pins>;
-        pinctrl-names = "default";
+        pinctrl-names = "i2c-hdmi";
 
-        status = "okay";
         clock-frequency = <400000>;
-
-        ak4643: codec@12 {
-                compatible = "asahi-kasei,ak4643";
-                #sound-dai-cells = <0>;
-                reg = <0x12>;
-        };
-
-        composite-in@20 {
-                compatible = "adi,adv7180";
-                reg = <0x20>;
-                remote = <&vin0>;
-
-                port {
-                        adv7180: endpoint {
-                                bus-width = <8>;
-                                remote-endpoint = <&vin0ep>;
-                        };
-                };
-        };
-
-        hdmi@39 {
-                compatible = "adi,adv7511w";
-                reg = <0x39>;
-                interrupt-parent = <&gpio5>;
-                interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
-
-                adi,input-depth = <8>;
-                adi,input-colorspace = "rgb";
-                adi,input-clock = "1x";
-                adi,input-style = <1>;
-                adi,input-justification = "evenly";
-
-                ports {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-
-                        port@0 {
-                                reg = <0>;
-                                adv7511_in: endpoint {
-                                        remote-endpoint = <&du_out_rgb0>;
-                                };
-                        };
-
-                        port@1 {
-                                reg = <1>;
-                                adv7511_out: endpoint {
-                                        remote-endpoint = <&hdmi_con>;
-                                };
-                        };
-                };
-        };
 };
 
 &mmcif0 {
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 106b4e1649ff..d588efa6aeaa 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -16,7 +16,6 @@
 
 / {
         compatible = "renesas,r8a7794";
-        interrupt-parent = <&gic>;
         #address-cells = <2>;
         #size-cells = <2>;
 
@@ -34,6 +33,35 @@
                 vin1 = &vin1;
         };
 
+        /*
+         * The external audio clocks are configured as 0 Hz fixed frequency
+         * clocks by default.
+         * Boards that provide audio clocks should override them.
+         */
+        audio_clka: audio_clka {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+        audio_clkb: audio_clkb {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+        audio_clkc: audio_clkc {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+
+        /* External CAN clock */
+        can_clk: can {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                /* This value must be overridden by the board. */
+                clock-frequency = <0>;
+        };
+
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -67,1290 +95,1313 @@
                 };
         };
 
-        apmu@e6151000 {
-                compatible = "renesas,r8a7794-apmu", "renesas,apmu";
-                reg = <0 0xe6151000 0 0x188>;
-                cpus = <&cpu0 &cpu1>;
-        };
-
-        gic: interrupt-controller@f1001000 {
-                compatible = "arm,gic-400";
-                #interrupt-cells = <3>;
-                #address-cells = <0>;
-                interrupt-controller;
-                reg = <0 0xf1001000 0 0x1000>,
-                        <0 0xf1002000 0 0x2000>,
-                        <0 0xf1004000 0 0x2000>,
-                        <0 0xf1006000 0 0x2000>;
-                interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
-                clocks = <&cpg CPG_MOD 408>;
-                clock-names = "clk";
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 408>;
+        /* External root clock */
+        extal_clk: extal {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                /* This value must be overridden by the board. */
+                clock-frequency = <0>;
         };
 
-        gpio0: gpio@e6050000 {
-                compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
-                reg = <0 0xe6050000 0 0x50>;
-                interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
-                #gpio-cells = <2>;
-                gpio-controller;
-                gpio-ranges = <&pfc 0 0 32>;
-                #interrupt-cells = <2>;
-                interrupt-controller;
-                clocks = <&cpg CPG_MOD 912>;
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 912>;
+        /* External SCIF clock */
+        scif_clk: scif {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                /* This value must be overridden by the board. */
+                clock-frequency = <0>;
         };
 
-        gpio1: gpio@e6051000 {
-                compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
-                reg = <0 0xe6051000 0 0x50>;
-                interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
-                #gpio-cells = <2>;
-                gpio-controller;
-                gpio-ranges = <&pfc 0 32 26>;
-                #interrupt-cells = <2>;
-                interrupt-controller;
-                clocks = <&cpg CPG_MOD 911>;
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 911>;
-        };
+        soc {
+                compatible = "simple-bus";
+                interrupt-parent = <&gic>;
 
-        gpio2: gpio@e6052000 {
-                compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
-                reg = <0 0xe6052000 0 0x50>;
-                interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
-                #gpio-cells = <2>;
-                gpio-controller;
-                gpio-ranges = <&pfc 0 64 32>;
-                #interrupt-cells = <2>;
-                interrupt-controller;
-                clocks = <&cpg CPG_MOD 910>;
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 910>;
-        };
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
+
+                gpio0: gpio@e6050000 {
+                        compatible = "renesas,gpio-r8a7794",
+                                     "renesas,rcar-gen2-gpio";
+                        reg = <0 0xe6050000 0 0x50>;
+                        interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 0 32>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 912>;
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 912>;
+                };
 
-        gpio3: gpio@e6053000 {
-                compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
-                reg = <0 0xe6053000 0 0x50>;
-                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
-                #gpio-cells = <2>;
-                gpio-controller;
-                gpio-ranges = <&pfc 0 96 32>;
-                #interrupt-cells = <2>;
-                interrupt-controller;
-                clocks = <&cpg CPG_MOD 909>;
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 909>;
-        };
+                gpio1: gpio@e6051000 {
+                        compatible = "renesas,gpio-r8a7794",
+                                     "renesas,rcar-gen2-gpio";
+                        reg = <0 0xe6051000 0 0x50>;
+                        interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 32 26>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 911>;
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 911>;
+                };
 
-        gpio4: gpio@e6054000 {
-                compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
-                reg = <0 0xe6054000 0 0x50>;
-                interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
-                #gpio-cells = <2>;
-                gpio-controller;
-                gpio-ranges = <&pfc 0 128 32>;
-                #interrupt-cells = <2>;
-                interrupt-controller;
-                clocks = <&cpg CPG_MOD 908>;
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 908>;
-        };
+                gpio2: gpio@e6052000 {
+                        compatible = "renesas,gpio-r8a7794",
+                                     "renesas,rcar-gen2-gpio";
+                        reg = <0 0xe6052000 0 0x50>;
+                        interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 64 32>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 910>;
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 910>;
+                };
 
-        gpio5: gpio@e6055000 {
-                compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
-                reg = <0 0xe6055000 0 0x50>;
-                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
-                #gpio-cells = <2>;
-                gpio-controller;
-                gpio-ranges = <&pfc 0 160 28>;
-                #interrupt-cells = <2>;
-                interrupt-controller;
-                clocks = <&cpg CPG_MOD 907>;
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 907>;
-        };
+                gpio3: gpio@e6053000 {
+                        compatible = "renesas,gpio-r8a7794",
+                                     "renesas,rcar-gen2-gpio";
+                        reg = <0 0xe6053000 0 0x50>;
+                        interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 96 32>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 909>;
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 909>;
+                };
 
-        gpio6: gpio@e6055400 {
-                compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio";
-                reg = <0 0xe6055400 0 0x50>;
-                interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-                #gpio-cells = <2>;
-                gpio-controller;
-                gpio-ranges = <&pfc 0 192 26>;
-                #interrupt-cells = <2>;
-                interrupt-controller;
-                clocks = <&cpg CPG_MOD 905>;
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 905>;
-        };
+                gpio4: gpio@e6054000 {
+                        compatible = "renesas,gpio-r8a7794",
+                                     "renesas,rcar-gen2-gpio";
+                        reg = <0 0xe6054000 0 0x50>;
+                        interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 128 32>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 908>;
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 908>;
+                };
 
-        cmt0: timer@ffca0000 {
-                compatible = "renesas,r8a7794-cmt0", "renesas,rcar-gen2-cmt0";
-                reg = <0 0xffca0000 0 0x1004>;
-                interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 124>;
-                clock-names = "fck";
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 124>;
-
-                status = "disabled";
-        };
+                gpio5: gpio@e6055000 {
+                        compatible = "renesas,gpio-r8a7794",
+                                     "renesas,rcar-gen2-gpio";
+                        reg = <0 0xe6055000 0 0x50>;
+                        interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 160 28>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 907>;
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 907>;
+                };
 
-        cmt1: timer@e6130000 {
-                compatible = "renesas,r8a7794-cmt1", "renesas,rcar-gen2-cmt1";
-                reg = <0 0xe6130000 0 0x1004>;
-                interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 329>;
-                clock-names = "fck";
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 329>;
-
-                status = "disabled";
-        };
+                gpio6: gpio@e6055400 {
+                        compatible = "renesas,gpio-r8a7794",
+                                     "renesas,rcar-gen2-gpio";
+                        reg = <0 0xe6055400 0 0x50>;
+                        interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 192 26>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 905>;
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 905>;
+                };
 
-        timer {
-                compatible = "arm,armv7-timer";
-                interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-                             <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-                             <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-                             <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
-        };
+                pfc: pin-controller@e6060000 {
+                        compatible = "renesas,pfc-r8a7794";
+                        reg = <0 0xe6060000 0 0x11c>;
+                };
 
-        irqc0: interrupt-controller@e61c0000 {
-                compatible = "renesas,irqc-r8a7794", "renesas,irqc";
-                #interrupt-cells = <2>;
-                interrupt-controller;
-                reg = <0 0xe61c0000 0 0x200>;
-                interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 407>;
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 407>;
-        };
+                cpg: clock-controller@e6150000 {
+                        compatible = "renesas,r8a7794-cpg-mssr";
+                        reg = <0 0xe6150000 0 0x1000>;
+                        clocks = <&extal_clk>, <&usb_extal_clk>;
+                        clock-names = "extal", "usb_extal";
+                        #clock-cells = <2>;
+                        #power-domain-cells = <0>;
+                        #reset-cells = <1>;
+                };
 
-        pfc: pin-controller@e6060000 {
-                compatible = "renesas,pfc-r8a7794";
-                reg = <0 0xe6060000 0 0x11c>;
-        };
+                apmu@e6151000 {
+                        compatible = "renesas,r8a7794-apmu", "renesas,apmu";
+                        reg = <0 0xe6151000 0 0x188>;
+                        cpus = <&cpu0 &cpu1>;
+                };
 
-        dmac0: dma-controller@e6700000 {
-                compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
-                reg = <0 0xe6700000 0 0x20000>;
-                interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
-                interrupt-names = "error",
-                                "ch0", "ch1", "ch2", "ch3",
-                                "ch4", "ch5", "ch6", "ch7",
-                                "ch8", "ch9", "ch10", "ch11",
-                                "ch12", "ch13", "ch14";
-                clocks = <&cpg CPG_MOD 219>;
-                clock-names = "fck";
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 219>;
-                #dma-cells = <1>;
-                dma-channels = <15>;
-        };
+                rst: reset-controller@e6160000 {
+                        compatible = "renesas,r8a7794-rst";
+                        reg = <0 0xe6160000 0 0x0100>;
+                };
 
-        dmac1: dma-controller@e6720000 {
-                compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
-                reg = <0 0xe6720000 0 0x20000>;
-                interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
-                              GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
-                interrupt-names = "error",
-                                "ch0", "ch1", "ch2", "ch3",
-                                "ch4", "ch5", "ch6", "ch7",
-                                "ch8", "ch9", "ch10", "ch11",
-                                "ch12", "ch13", "ch14";
-                clocks = <&cpg CPG_MOD 218>;
-                clock-names = "fck";
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 218>;
-                #dma-cells = <1>;
-                dma-channels = <15>;
-        };
+                sysc: system-controller@e6180000 {
+                        compatible = "renesas,r8a7794-sysc";
+                        reg = <0 0xe6180000 0 0x0200>;
+                        #power-domain-cells = <1>;
+                };
 
-        audma0: dma-controller@ec700000 {
-                compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
-                reg = <0 0xec700000 0 0x10000>;
-                interrupts =    <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
-                                 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
-                interrupt-names = "error",
-                                  "ch0", "ch1", "ch2", "ch3", "ch4", "ch5",
-                                  "ch6", "ch7", "ch8", "ch9", "ch10", "ch11",
-                                  "ch12";
-                clocks = <&cpg CPG_MOD 502>;
-                clock-names = "fck";
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 502>;
-                #dma-cells = <1>;
-                dma-channels = <13>;
-        };
+                irqc0: interrupt-controller@e61c0000 {
+                        compatible = "renesas,irqc-r8a7794", "renesas,irqc";
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        reg = <0 0xe61c0000 0 0x200>;
+                        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 407>;
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 407>;
+                };
 
-        scifa0: serial@e6c40000 {
-                compatible = "renesas,scifa-r8a7794",
-                             "renesas,rcar-gen2-scifa", "renesas,scifa";
-                reg = <0 0xe6c40000 0 64>;
-                interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 204>;
-                clock-names = "fck";
-                dmas = <&dmac0 0x21>, <&dmac0 0x22>,
-                       <&dmac1 0x21>, <&dmac1 0x22>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 204>;
-                status = "disabled";
-        };
+                ipmmu_sy0: mmu@e6280000 {
+                        compatible = "renesas,ipmmu-r8a7794",
+                                     "renesas,ipmmu-vmsa";
+                        reg = <0 0xe6280000 0 0x1000>;
+                        interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+                        #iommu-cells = <1>;
+                        status = "disabled";
+                };
 
-        scifa1: serial@e6c50000 {
-                compatible = "renesas,scifa-r8a7794",
-                             "renesas,rcar-gen2-scifa", "renesas,scifa";
-                reg = <0 0xe6c50000 0 64>;
-                interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 203>;
-                clock-names = "fck";
-                dmas = <&dmac0 0x25>, <&dmac0 0x26>,
-                       <&dmac1 0x25>, <&dmac1 0x26>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 203>;
-                status = "disabled";
-        };
+                ipmmu_sy1: mmu@e6290000 {
+                        compatible = "renesas,ipmmu-r8a7794",
+                                     "renesas,ipmmu-vmsa";
+                        reg = <0 0xe6290000 0 0x1000>;
+                        interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+                        #iommu-cells = <1>;
+                        status = "disabled";
+                };
 
-        scifa2: serial@e6c60000 {
-                compatible = "renesas,scifa-r8a7794",
-                             "renesas,rcar-gen2-scifa", "renesas,scifa";
-                reg = <0 0xe6c60000 0 64>;
-                interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 202>;
-                clock-names = "fck";
-                dmas = <&dmac0 0x27>, <&dmac0 0x28>,
-                       <&dmac1 0x27>, <&dmac1 0x28>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 202>;
-                status = "disabled";
-        };
+                ipmmu_ds: mmu@e6740000 {
+                        compatible = "renesas,ipmmu-r8a7794",
+                                     "renesas,ipmmu-vmsa";
+                        reg = <0 0xe6740000 0 0x1000>;
+                        interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+                        #iommu-cells = <1>;
+                        status = "disabled";
+                };
 
-        scifa3: serial@e6c70000 {
-                compatible = "renesas,scifa-r8a7794",
-                             "renesas,rcar-gen2-scifa", "renesas,scifa";
-                reg = <0 0xe6c70000 0 64>;
-                interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 1106>;
-                clock-names = "fck";
-                dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
-                       <&dmac1 0x1b>, <&dmac1 0x1c>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 1106>;
-                status = "disabled";
-        };
+                ipmmu_mp: mmu@ec680000 {
+                        compatible = "renesas,ipmmu-r8a7794",
+                                     "renesas,ipmmu-vmsa";
+                        reg = <0 0xec680000 0 0x1000>;
+                        interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+                        #iommu-cells = <1>;
+                        status = "disabled";
+                };
 
-        scifa4: serial@e6c78000 {
-                compatible = "renesas,scifa-r8a7794",
-                             "renesas,rcar-gen2-scifa", "renesas,scifa";
-                reg = <0 0xe6c78000 0 64>;
-                interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 1107>;
-                clock-names = "fck";
-                dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
-                       <&dmac1 0x1f>, <&dmac1 0x20>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 1107>;
-                status = "disabled";
-        };
+                ipmmu_mx: mmu@fe951000 {
+                        compatible = "renesas,ipmmu-r8a7794",
+                                     "renesas,ipmmu-vmsa";
+                        reg = <0 0xfe951000 0 0x1000>;
+                        interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+                        #iommu-cells = <1>;
+                        status = "disabled";
+                };
 
-        scifa5: serial@e6c80000 {
-                compatible = "renesas,scifa-r8a7794",
-                             "renesas,rcar-gen2-scifa", "renesas,scifa";
-                reg = <0 0xe6c80000 0 64>;
-                interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 1108>;
-                clock-names = "fck";
-                dmas = <&dmac0 0x23>, <&dmac0 0x24>,
-                       <&dmac1 0x23>, <&dmac1 0x24>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 1108>;
-                status = "disabled";
-        };
+                ipmmu_gp: mmu@e62a0000 {
+                        compatible = "renesas,ipmmu-r8a7794",
+                                     "renesas,ipmmu-vmsa";
+                        reg = <0 0xe62a0000 0 0x1000>;
+                        interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+                        #iommu-cells = <1>;
+                        status = "disabled";
+                };
 
-        scifb0: serial@e6c20000 {
-                compatible = "renesas,scifb-r8a7794",
-                             "renesas,rcar-gen2-scifb", "renesas,scifb";
-                reg = <0 0xe6c20000 0 0x100>;
-                interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 206>;
-                clock-names = "fck";
-                dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
-                       <&dmac1 0x3d>, <&dmac1 0x3e>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 206>;
-                status = "disabled";
-        };
+                icram0: sram@e63a0000 {
+                        compatible = "mmio-sram";
+                        reg = <0 0xe63a0000 0 0x12000>;
+                };
 
-        scifb1: serial@e6c30000 {
-                compatible = "renesas,scifb-r8a7794",
-                             "renesas,rcar-gen2-scifb", "renesas,scifb";
-                reg = <0 0xe6c30000 0 0x100>;
-                interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 207>;
-                clock-names = "fck";
-                dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
-                       <&dmac1 0x19>, <&dmac1 0x1a>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 207>;
-                status = "disabled";
-        };
+                icram1: sram@e63c0000 {
+                        compatible = "mmio-sram";
+                        reg = <0 0xe63c0000 0 0x1000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0 0xe63c0000 0x1000>;
 
-        scifb2: serial@e6ce0000 {
-                compatible = "renesas,scifb-r8a7794",
-                             "renesas,rcar-gen2-scifb", "renesas,scifb";
-                reg = <0 0xe6ce0000 0 0x100>;
-                interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 216>;
-                clock-names = "fck";
-                dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
-                       <&dmac1 0x1d>, <&dmac1 0x1e>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 216>;
-                status = "disabled";
-        };
+                        smp-sram@0 {
+                                compatible = "renesas,smp-sram";
+                                reg = <0 0x10>;
+                        };
+                };
 
-        scif0: serial@e6e60000 {
-                compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
-                             "renesas,scif";
-                reg = <0 0xe6e60000 0 64>;
-                interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
-                         <&scif_clk>;
-                clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
-                       <&dmac1 0x29>, <&dmac1 0x2a>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 721>;
-                status = "disabled";
-        };
+                /* The memory map in the User's Manual maps the cores to
+                 * bus numbers
+                 */
+                i2c0: i2c@e6508000 {
+                        compatible = "renesas,i2c-r8a7794",
+                                     "renesas,rcar-gen2-i2c";
+                        reg = <0 0xe6508000 0 0x40>;
+                        interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 931>;
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 931>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        i2c-scl-internal-delay-ns = <6>;
+                        status = "disabled";
+                };
 
-        scif1: serial@e6e68000 {
-                compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
-                             "renesas,scif";
-                reg = <0 0xe6e68000 0 64>;
-                interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
-                         <&scif_clk>;
-                clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
-                       <&dmac1 0x2d>, <&dmac1 0x2e>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 720>;
-                status = "disabled";
-        };
+                i2c1: i2c@e6518000 {
+                        compatible = "renesas,i2c-r8a7794",
+                                     "renesas,rcar-gen2-i2c";
+                        reg = <0 0xe6518000 0 0x40>;
+                        interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 930>;
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 930>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        i2c-scl-internal-delay-ns = <6>;
+                        status = "disabled";
+                };
 
-        scif2: serial@e6e58000 {
-                compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
-                             "renesas,scif";
-                reg = <0 0xe6e58000 0 64>;
-                interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
-                         <&scif_clk>;
-                clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
-                       <&dmac1 0x2b>, <&dmac1 0x2c>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 719>;
-                status = "disabled";
-        };
+                i2c2: i2c@e6530000 {
+                        compatible = "renesas,i2c-r8a7794",
+                                     "renesas,rcar-gen2-i2c";
+                        reg = <0 0xe6530000 0 0x40>;
+                        interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 929>;
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 929>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        i2c-scl-internal-delay-ns = <6>;
+                        status = "disabled";
+                };
 
-        scif3: serial@e6ea8000 {
-                compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
-                             "renesas,scif";
-                reg = <0 0xe6ea8000 0 64>;
-                interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
-                         <&scif_clk>;
-                clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
-                       <&dmac1 0x2f>, <&dmac1 0x30>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 718>;
-                status = "disabled";
-        };
+                i2c3: i2c@e6540000 {
+                        compatible = "renesas,i2c-r8a7794",
+                                     "renesas,rcar-gen2-i2c";
+                        reg = <0 0xe6540000 0 0x40>;
+                        interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 928>;
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 928>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        i2c-scl-internal-delay-ns = <6>;
+                        status = "disabled";
+                };
 
-        scif4: serial@e6ee0000 {
-                compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
-                             "renesas,scif";
-                reg = <0 0xe6ee0000 0 64>;
-                interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
-                         <&scif_clk>;
-                clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
-                       <&dmac1 0xfb>, <&dmac1 0xfc>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 715>;
-                status = "disabled";
-        };
+                i2c4: i2c@e6520000 {
+                        compatible = "renesas,i2c-r8a7794",
+                                     "renesas,rcar-gen2-i2c";
+                        reg = <0 0xe6520000 0 0x40>;
+                        interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 927>;
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 927>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        i2c-scl-internal-delay-ns = <6>;
+                        status = "disabled";
+                };
 
-        scif5: serial@e6ee8000 {
-                compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
-                             "renesas,scif";
-                reg = <0 0xe6ee8000 0 64>;
-                interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
-                         <&scif_clk>;
-                clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
-                       <&dmac1 0xfd>, <&dmac1 0xfe>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 714>;
-                status = "disabled";
-        };
+                i2c5: i2c@e6528000 {
+                        compatible = "renesas,i2c-r8a7794",
+                                     "renesas,rcar-gen2-i2c";
+                        reg = <0 0xe6528000 0 0x40>;
+                        interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 925>;
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 925>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        i2c-scl-internal-delay-ns = <6>;
+                        status = "disabled";
+                };
 
-        hscif0: serial@e62c0000 {
-                compatible = "renesas,hscif-r8a7794",
-                             "renesas,rcar-gen2-hscif", "renesas,hscif";
-                reg = <0 0xe62c0000 0 96>;
-                interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
-                         <&scif_clk>;
-                clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
-                       <&dmac1 0x39>, <&dmac1 0x3a>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 717>;
-                status = "disabled";
-        };
+                i2c6: i2c@e6500000 {
+                        compatible = "renesas,iic-r8a7794",
+                                     "renesas,rcar-gen2-iic",
+                                     "renesas,rmobile-iic";
+                        reg = <0 0xe6500000 0 0x425>;
+                        interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 318>;
+                        dmas = <&dmac0 0x61>, <&dmac0 0x62>,
+                               <&dmac1 0x61>, <&dmac1 0x62>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 318>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
 
-        hscif1: serial@e62c8000 {
-                compatible = "renesas,hscif-r8a7794",
-                             "renesas,rcar-gen2-hscif", "renesas,hscif";
-                reg = <0 0xe62c8000 0 96>;
-                interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
-                         <&scif_clk>;
-                clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
-                       <&dmac1 0x4d>, <&dmac1 0x4e>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 716>;
-                status = "disabled";
-        };
+                i2c7: i2c@e6510000 {
+                        compatible = "renesas,iic-r8a7794",
+                                     "renesas,rcar-gen2-iic",
+                                     "renesas,rmobile-iic";
+                        reg = <0 0xe6510000 0 0x425>;
+                        interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 323>;
+                        dmas = <&dmac0 0x65>, <&dmac0 0x66>,
+                               <&dmac1 0x65>, <&dmac1 0x66>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 323>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
 
-        hscif2: serial@e62d0000 {
-                compatible = "renesas,hscif-r8a7794",
-                             "renesas,rcar-gen2-hscif", "renesas,hscif";
-                reg = <0 0xe62d0000 0 96>;
-                interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
-                         <&scif_clk>;
-                clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
-                       <&dmac1 0x3b>, <&dmac1 0x3c>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 713>;
-                status = "disabled";
-        };
+                hsusb: usb@e6590000 {
+                        compatible = "renesas,usbhs-r8a7794",
+                                     "renesas,rcar-gen2-usbhs";
+                        reg = <0 0xe6590000 0 0x100>;
+                        interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 704>;
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 704>;
+                        renesas,buswait = <4>;
+                        phys = <&usb0 1>;
+                        phy-names = "usb";
+                        status = "disabled";
+                };
 
-        icram0: sram@e63a0000 {
-                compatible = "mmio-sram";
-                reg = <0 0xe63a0000 0 0x12000>;
-        };
+                usbphy: usb-phy@e6590100 {
+                        compatible = "renesas,usb-phy-r8a7794",
+                                     "renesas,rcar-gen2-usb-phy";
+                        reg = <0 0xe6590100 0 0x100>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&cpg CPG_MOD 704>;
+                        clock-names = "usbhs";
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 704>;
+                        status = "disabled";
 
-        icram1: sram@e63c0000 {
-                compatible = "mmio-sram";
-                reg = <0 0xe63c0000 0 0x1000>;
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges = <0 0 0xe63c0000 0x1000>;
+                        usb0: usb-channel@0 {
+                                reg = <0>;
+                                #phy-cells = <1>;
+                        };
+                        usb2: usb-channel@2 {
+                                reg = <2>;
+                                #phy-cells = <1>;
+                        };
+                };
 
-                smp-sram@0 {
-                        compatible = "renesas,smp-sram";
-                        reg = <0 0x10>;
+                dmac0: dma-controller@e6700000 {
+                        compatible = "renesas,dmac-r8a7794",
+                                     "renesas,rcar-dmac";
+                        reg = <0 0xe6700000 0 0x20000>;
+                        interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "error",
+                                          "ch0", "ch1", "ch2", "ch3",
+                                          "ch4", "ch5", "ch6", "ch7",
+                                          "ch8", "ch9", "ch10", "ch11",
+                                          "ch12", "ch13", "ch14";
+                        clocks = <&cpg CPG_MOD 219>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 219>;
+                        #dma-cells = <1>;
+                        dma-channels = <15>;
                 };
-        };
 
-        ether: ethernet@ee700000 {
-                compatible = "renesas,ether-r8a7794",
-                             "renesas,rcar-gen2-ether";
-                reg = <0 0xee700000 0 0x400>;
-                interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 813>;
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 813>;
-                phy-mode = "rmii";
-                #address-cells = <1>;
-                #size-cells = <0>;
-                status = "disabled";
-        };
+                dmac1: dma-controller@e6720000 {
+                        compatible = "renesas,dmac-r8a7794",
+                                     "renesas,rcar-dmac";
+                        reg = <0 0xe6720000 0 0x20000>;
+                        interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "error",
+                                          "ch0", "ch1", "ch2", "ch3",
+                                          "ch4", "ch5", "ch6", "ch7",
+                                          "ch8", "ch9", "ch10", "ch11",
+                                          "ch12", "ch13", "ch14";
+                        clocks = <&cpg CPG_MOD 218>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 218>;
+                        #dma-cells = <1>;
+                        dma-channels = <15>;
+                };
 
-        avb: ethernet@e6800000 {
-                compatible = "renesas,etheravb-r8a7794",
-                             "renesas,etheravb-rcar-gen2";
-                reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
-                interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 812>;
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 812>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                status = "disabled";
-        };
+                avb: ethernet@e6800000 {
+                        compatible = "renesas,etheravb-r8a7794",
+                                     "renesas,etheravb-rcar-gen2";
+                        reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
+                        interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 812>;
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 812>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
 
-        /* The memory map in the User's Manual maps the cores to bus numbers */
-        i2c0: i2c@e6508000 {
-                compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
-                reg = <0 0xe6508000 0 0x40>;
-                interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 931>;
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 931>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                i2c-scl-internal-delay-ns = <6>;
-                status = "disabled";
-        };
+                qspi: spi@e6b10000 {
+                        compatible = "renesas,qspi-r8a7794", "renesas,qspi";
+                        reg = <0 0xe6b10000 0 0x2c>;
+                        interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 917>;
+                        dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+                               <&dmac1 0x17>, <&dmac1 0x18>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 917>;
+                        num-cs = <1>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
 
-        i2c1: i2c@e6518000 {
-                compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
-                reg = <0 0xe6518000 0 0x40>;
-                interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 930>;
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 930>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                i2c-scl-internal-delay-ns = <6>;
-                status = "disabled";
-        };
+                scifa0: serial@e6c40000 {
+                        compatible = "renesas,scifa-r8a7794",
+                                     "renesas,rcar-gen2-scifa", "renesas,scifa";
+                        reg = <0 0xe6c40000 0 64>;
+                        interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 204>;
+                        clock-names = "fck";
+                        dmas = <&dmac0 0x21>, <&dmac0 0x22>,
+                               <&dmac1 0x21>, <&dmac1 0x22>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 204>;
+                        status = "disabled";
+                };
 
-        i2c2: i2c@e6530000 {
-                compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
-                reg = <0 0xe6530000 0 0x40>;
-                interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 929>;
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 929>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                i2c-scl-internal-delay-ns = <6>;
-                status = "disabled";
-        };
+                scifa1: serial@e6c50000 {
+                        compatible = "renesas,scifa-r8a7794",
+                                     "renesas,rcar-gen2-scifa", "renesas,scifa";
+                        reg = <0 0xe6c50000 0 64>;
+                        interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 203>;
+                        clock-names = "fck";
+                        dmas = <&dmac0 0x25>, <&dmac0 0x26>,
+                               <&dmac1 0x25>, <&dmac1 0x26>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 203>;
+                        status = "disabled";
+                };
 
-        i2c3: i2c@e6540000 {
-                compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
-                reg = <0 0xe6540000 0 0x40>;
-                interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 928>;
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 928>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                i2c-scl-internal-delay-ns = <6>;
-                status = "disabled";
-        };
+                scifa2: serial@e6c60000 {
+                        compatible = "renesas,scifa-r8a7794",
+                                     "renesas,rcar-gen2-scifa", "renesas,scifa";
+                        reg = <0 0xe6c60000 0 64>;
+                        interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 202>;
+                        clock-names = "fck";
+                        dmas = <&dmac0 0x27>, <&dmac0 0x28>,
+                               <&dmac1 0x27>, <&dmac1 0x28>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 202>;
+                        status = "disabled";
+                };
 
-        i2c4: i2c@e6520000 {
-                compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
-                reg = <0 0xe6520000 0 0x40>;
-                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 927>;
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 927>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                i2c-scl-internal-delay-ns = <6>;
-                status = "disabled";
-        };
+                scifa3: serial@e6c70000 {
+                        compatible = "renesas,scifa-r8a7794",
+                                     "renesas,rcar-gen2-scifa", "renesas,scifa";
+                        reg = <0 0xe6c70000 0 64>;
+                        interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 1106>;
+                        clock-names = "fck";
+                        dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
+                               <&dmac1 0x1b>, <&dmac1 0x1c>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 1106>;
+                        status = "disabled";
+                };
 
-        i2c5: i2c@e6528000 {
-                compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c";
-                reg = <0 0xe6528000 0 0x40>;
-                interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 925>;
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 925>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                i2c-scl-internal-delay-ns = <6>;
-                status = "disabled";
-        };
+                scifa4: serial@e6c78000 {
+                        compatible = "renesas,scifa-r8a7794",
+                                     "renesas,rcar-gen2-scifa", "renesas,scifa";
+                        reg = <0 0xe6c78000 0 64>;
+                        interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 1107>;
+                        clock-names = "fck";
+                        dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
+                               <&dmac1 0x1f>, <&dmac1 0x20>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 1107>;
+                        status = "disabled";
+                };
 
-        i2c6: i2c@e6500000 {
-                compatible = "renesas,iic-r8a7794", "renesas,rcar-gen2-iic",
-                             "renesas,rmobile-iic";
-                reg = <0 0xe6500000 0 0x425>;
-                interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 318>;
-                dmas = <&dmac0 0x61>, <&dmac0 0x62>,
-                       <&dmac1 0x61>, <&dmac1 0x62>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 318>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                status = "disabled";
-        };
+                scifa5: serial@e6c80000 {
+                        compatible = "renesas,scifa-r8a7794",
+                                     "renesas,rcar-gen2-scifa", "renesas,scifa";
+                        reg = <0 0xe6c80000 0 64>;
+                        interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 1108>;
+                        clock-names = "fck";
+                        dmas = <&dmac0 0x23>, <&dmac0 0x24>,
+                               <&dmac1 0x23>, <&dmac1 0x24>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 1108>;
+                        status = "disabled";
+                };
 
-        i2c7: i2c@e6510000 {
-                compatible = "renesas,iic-r8a7794", "renesas,rcar-gen2-iic",
-                             "renesas,rmobile-iic";
-                reg = <0 0xe6510000 0 0x425>;
-                interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 323>;
-                dmas = <&dmac0 0x65>, <&dmac0 0x66>,
-                       <&dmac1 0x65>, <&dmac1 0x66>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 323>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                status = "disabled";
-        };
+                scifb0: serial@e6c20000 {
+                        compatible = "renesas,scifb-r8a7794",
+                                     "renesas,rcar-gen2-scifb", "renesas,scifb";
+                        reg = <0 0xe6c20000 0 0x100>;
+                        interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 206>;
+                        clock-names = "fck";
+                        dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
+                               <&dmac1 0x3d>, <&dmac1 0x3e>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 206>;
+                        status = "disabled";
+                };
 
-        mmcif0: mmc@ee200000 {
-                compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif";
-                reg = <0 0xee200000 0 0x80>;
-                interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 315>;
-                dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
-                       <&dmac1 0xd1>, <&dmac1 0xd2>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 315>;
-                reg-io-width = <4>;
-                status = "disabled";
-        };
+                scifb1: serial@e6c30000 {
+                        compatible = "renesas,scifb-r8a7794",
+                                     "renesas,rcar-gen2-scifb", "renesas,scifb";
+                        reg = <0 0xe6c30000 0 0x100>;
+                        interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 207>;
+                        clock-names = "fck";
+                        dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
+                               <&dmac1 0x19>, <&dmac1 0x1a>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 207>;
+                        status = "disabled";
+                };
 
-        sdhi0: sd@ee100000 {
-                compatible = "renesas,sdhi-r8a7794",
-                             "renesas,rcar-gen2-sdhi";
-                reg = <0 0xee100000 0 0x328>;
-                interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 314>;
-                dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
-                       <&dmac1 0xcd>, <&dmac1 0xce>;
-                dma-names = "tx", "rx", "tx", "rx";
-                max-frequency = <195000000>;
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 314>;
-                status = "disabled";
-        };
+                scifb2: serial@e6ce0000 {
+                        compatible = "renesas,scifb-r8a7794",
+                                     "renesas,rcar-gen2-scifb", "renesas,scifb";
+                        reg = <0 0xe6ce0000 0 0x100>;
+                        interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 216>;
+                        clock-names = "fck";
+                        dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
+                               <&dmac1 0x1d>, <&dmac1 0x1e>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 216>;
+                        status = "disabled";
+                };
 
-        sdhi1: sd@ee140000 {
-                compatible = "renesas,sdhi-r8a7794",
-                             "renesas,rcar-gen2-sdhi";
-                reg = <0 0xee140000 0 0x100>;
-                interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 312>;
-                dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
-                       <&dmac1 0xc1>, <&dmac1 0xc2>;
-                dma-names = "tx", "rx", "tx", "rx";
-                max-frequency = <97500000>;
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 312>;
-                status = "disabled";
-        };
+                scif0: serial@e6e60000 {
+                        compatible = "renesas,scif-r8a7794",
+                                     "renesas,rcar-gen2-scif",
+                                     "renesas,scif";
+                        reg = <0 0xe6e60000 0 64>;
+                        interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+                               <&dmac1 0x29>, <&dmac1 0x2a>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 721>;
+                        status = "disabled";
+                };
 
-        sdhi2: sd@ee160000 {
-                compatible = "renesas,sdhi-r8a7794",
-                             "renesas,rcar-gen2-sdhi";
-                reg = <0 0xee160000 0 0x100>;
-                interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 311>;
-                dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
-                       <&dmac1 0xd3>, <&dmac1 0xd4>;
-                dma-names = "tx", "rx", "tx", "rx";
-                max-frequency = <97500000>;
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 311>;
-                status = "disabled";
-        };
+                scif1: serial@e6e68000 {
+                        compatible = "renesas,scif-r8a7794",
+                                     "renesas,rcar-gen2-scif",
+                                     "renesas,scif";
+                        reg = <0 0xe6e68000 0 64>;
+                        interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+                               <&dmac1 0x2d>, <&dmac1 0x2e>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 720>;
+                        status = "disabled";
+                };
 
-        qspi: spi@e6b10000 {
-                compatible = "renesas,qspi-r8a7794", "renesas,qspi";
-                reg = <0 0xe6b10000 0 0x2c>;
-                interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 917>;
-                dmas = <&dmac0 0x17>, <&dmac0 0x18>,
-                       <&dmac1 0x17>, <&dmac1 0x18>;
-                dma-names = "tx", "rx", "tx", "rx";
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 917>;
-                num-cs = <1>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                status = "disabled";
-        };
+                scif2: serial@e6e58000 {
+                        compatible = "renesas,scif-r8a7794",
+                                     "renesas,rcar-gen2-scif", "renesas,scif";
+                        reg = <0 0xe6e58000 0 64>;
+                        interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+                               <&dmac1 0x2b>, <&dmac1 0x2c>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 719>;
+                        status = "disabled";
+                };
 
-        vin0: video@e6ef0000 {
-                compatible = "renesas,vin-r8a7794", "renesas,rcar-gen2-vin";
-                reg = <0 0xe6ef0000 0 0x1000>;
-                interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 811>;
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 811>;
-                status = "disabled";
-        };
+                scif3: serial@e6ea8000 {
+                        compatible = "renesas,scif-r8a7794",
+                                     "renesas,rcar-gen2-scif", "renesas,scif";
+                        reg = <0 0xe6ea8000 0 64>;
+                        interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
+                               <&dmac1 0x2f>, <&dmac1 0x30>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 718>;
+                        status = "disabled";
+                };
 
-        vin1: video@e6ef1000 {
-                compatible = "renesas,vin-r8a7794", "renesas,rcar-gen2-vin";
-                reg = <0 0xe6ef1000 0 0x1000>;
-                interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 810>;
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 810>;
-                status = "disabled";
-        };
+                scif4: serial@e6ee0000 {
+                        compatible = "renesas,scif-r8a7794",
+                                     "renesas,rcar-gen2-scif", "renesas,scif";
+                        reg = <0 0xe6ee0000 0 64>;
+                        interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
+                               <&dmac1 0xfb>, <&dmac1 0xfc>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 715>;
+                        status = "disabled";
+                };
 
-        pci0: pci@ee090000 {
-                compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
-                device_type = "pci";
-                reg = <0 0xee090000 0 0xc00>,
-                      <0 0xee080000 0 0x1100>;
-                interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 703>;
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 703>;
-                status = "disabled";
-
-                bus-range = <0 0>;
-                #address-cells = <3>;
-                #size-cells = <2>;
-                #interrupt-cells = <1>;
-                ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
-                interrupt-map-mask = <0xff00 0 0 0x7>;
-                interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
-                                 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
-                                 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-
-                usb@1,0 {
-                        reg = <0x800 0 0 0 0>;
-                        phys = <&usb0 0>;
-                        phy-names = "usb";
+                scif5: serial@e6ee8000 {
+                        compatible = "renesas,scif-r8a7794",
+                                     "renesas,rcar-gen2-scif", "renesas,scif";
+                        reg = <0 0xe6ee8000 0 64>;
+                        interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
+                               <&dmac1 0xfd>, <&dmac1 0xfe>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 714>;
+                        status = "disabled";
                 };
 
-                usb@2,0 {
-                        reg = <0x1000 0 0 0 0>;
-                        phys = <&usb0 0>;
-                        phy-names = "usb";
+                hscif0: serial@e62c0000 {
+                        compatible = "renesas,hscif-r8a7794",
+                                     "renesas,rcar-gen2-hscif", "renesas,hscif";
+                        reg = <0 0xe62c0000 0 96>;
+                        interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 717>,
+                                 <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+                               <&dmac1 0x39>, <&dmac1 0x3a>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 717>;
+                        status = "disabled";
                 };
-        };
 
-        pci1: pci@ee0d0000 {
-                compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
-                device_type = "pci";
-                reg = <0 0xee0d0000 0 0xc00>,
-                      <0 0xee0c0000 0 0x1100>;
-                interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 703>;
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 703>;
-                status = "disabled";
-
-                bus-range = <1 1>;
-                #address-cells = <3>;
-                #size-cells = <2>;
-                #interrupt-cells = <1>;
-                ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
-                interrupt-map-mask = <0xff00 0 0 0x7>;
-                interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
-                                 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
-                                 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
-
-                usb@1,0 {
-                        reg = <0x10800 0 0 0 0>;
-                        phys = <&usb2 0>;
-                        phy-names = "usb";
+                hscif1: serial@e62c8000 {
+                        compatible = "renesas,hscif-r8a7794",
+                                     "renesas,rcar-gen2-hscif", "renesas,hscif";
+                        reg = <0 0xe62c8000 0 96>;
+                        interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 716>,
+                                 <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+                               <&dmac1 0x4d>, <&dmac1 0x4e>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 716>;
+                        status = "disabled";
                 };
 
-                usb@2,0 {
-                        reg = <0x11000 0 0 0 0>;
-                        phys = <&usb2 0>;
-                        phy-names = "usb";
+                hscif2: serial@e62d0000 {
+                        compatible = "renesas,hscif-r8a7794",
+                                     "renesas,rcar-gen2-hscif", "renesas,hscif";
+                        reg = <0 0xe62d0000 0 96>;
+                        interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
+                               <&dmac1 0x3b>, <&dmac1 0x3c>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 713>;
+                        status = "disabled";
                 };
-        };
 
-        hsusb: usb@e6590000 {
-                compatible = "renesas,usbhs-r8a7794", "renesas,rcar-gen2-usbhs";
-                reg = <0 0xe6590000 0 0x100>;
-                interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 704>;
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 704>;
-                renesas,buswait = <4>;
-                phys = <&usb0 1>;
-                phy-names = "usb";
-                status = "disabled";
-        };
+                can0: can@e6e80000 {
+                        compatible = "renesas,can-r8a7794",
+                                     "renesas,rcar-gen2-can";
+                        reg = <0 0xe6e80000 0 0x1000>;
+                        interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7794_CLK_RCAN>,
+                                 <&can_clk>;
+                        clock-names = "clkp1", "clkp2", "can_clk";
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 916>;
+                        status = "disabled";
+                };
 
-        usbphy: usb-phy@e6590100 {
-                compatible = "renesas,usb-phy-r8a7794",
-                             "renesas,rcar-gen2-usb-phy";
-                reg = <0 0xe6590100 0 0x100>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                clocks = <&cpg CPG_MOD 704>;
-                clock-names = "usbhs";
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 704>;
-                status = "disabled";
+                can1: can@e6e88000 {
+                        compatible = "renesas,can-r8a7794",
+                                     "renesas,rcar-gen2-can";
+                        reg = <0 0xe6e88000 0 0x1000>;
+                        interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7794_CLK_RCAN>,
+                                 <&can_clk>;
+                        clock-names = "clkp1", "clkp2", "can_clk";
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 915>;
+                        status = "disabled";
+                };
 
-                usb0: usb-channel@0 {
-                        reg = <0>;
-                        #phy-cells = <1>;
+                vin0: video@e6ef0000 {
+                        compatible = "renesas,vin-r8a7794",
+                                     "renesas,rcar-gen2-vin";
+                        reg = <0 0xe6ef0000 0 0x1000>;
+                        interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 811>;
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 811>;
+                        status = "disabled";
                 };
-                usb2: usb-channel@2 {
-                        reg = <2>;
-                        #phy-cells = <1>;
+
+                vin1: video@e6ef1000 {
+                        compatible = "renesas,vin-r8a7794",
+                                     "renesas,rcar-gen2-vin";
+                        reg = <0 0xe6ef1000 0 0x1000>;
+                        interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 810>;
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 810>;
+                        status = "disabled";
                 };
-        };
 
-        vsp@fe928000 {
-                compatible = "renesas,vsp1";
-                reg = <0 0xfe928000 0 0x8000>;
-                interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 131>;
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 131>;
-        };
+                rcar_sound: sound@ec500000 {
+                        /*
+                         * #sound-dai-cells is required
+                         *
+                         * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
+                         * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
+                         */
+                        compatible = "renesas,rcar_sound-r8a7794",
+                                     "renesas,rcar_sound-gen2";
+                        reg = <0 0xec500000 0 0x1000>, /* SCU */
+                              <0 0xec5a0000 0 0x100>,  /* ADG */
+                              <0 0xec540000 0 0x1000>, /* SSIU */
+                              <0 0xec541000 0 0x280>,  /* SSI */
+                              <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri */
+                        reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+                        clocks = <&cpg CPG_MOD 1005>,
+                                 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+                                 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+                                 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+                                 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+                                 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+                                 <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>,
+                                 <&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>,
+                                 <&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>,
+                                 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
+                                 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
+                                 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+                                 <&audio_clka>, <&audio_clkb>, <&audio_clkc>,
+                                 <&cpg CPG_CORE R8A7794_CLK_M2>;
+                        clock-names = "ssi-all",
+                                      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+                                      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+                                      "ssi.1", "ssi.0",
+                                      "src.6", "src.5", "src.4", "src.3",
+                                      "src.2", "src.1",
+                                      "ctu.0", "ctu.1",
+                                      "mix.0", "mix.1",
+                                      "dvc.0", "dvc.1",
+                                      "clk_a", "clk_b", "clk_c", "clk_i";
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 1005>,
+                                 <&cpg 1006>, <&cpg 1007>,
+                                 <&cpg 1008>, <&cpg 1009>,
+                                 <&cpg 1010>, <&cpg 1011>,
+                                 <&cpg 1012>, <&cpg 1013>,
+                                 <&cpg 1014>, <&cpg 1015>;
+                        reset-names = "ssi-all",
+                                      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+                                      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+                                      "ssi.1", "ssi.0";
+
+                        status = "disabled";
+
+                        rcar_sound,dvc {
+                                dvc0: dvc-0 {
+                                        dmas = <&audma0 0xbc>;
+                                        dma-names = "tx";
+                                };
+                                dvc1: dvc-1 {
+                                        dmas = <&audma0 0xbe>;
+                                        dma-names = "tx";
+                                };
+                        };
 
-        vsp@fe930000 {
-                compatible = "renesas,vsp1";
-                reg = <0 0xfe930000 0 0x8000>;
-                interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 128>;
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 128>;
-        };
+                        rcar_sound,mix {
+                                mix0: mix-0 { };
+                                mix1: mix-1 { };
+                        };
 
-        du: display@feb00000 {
-                compatible = "renesas,du-r8a7794";
-                reg = <0 0xfeb00000 0 0x40000>;
-                reg-names = "du";
-                interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
-                clock-names = "du.0", "du.1";
-                status = "disabled";
-
-                ports {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
+                        rcar_sound,ctu {
+                                ctu00: ctu-0 { };
+                                ctu01: ctu-1 { };
+                                ctu02: ctu-2 { };
+                                ctu03: ctu-3 { };
+                                ctu10: ctu-4 { };
+                                ctu11: ctu-5 { };
+                                ctu12: ctu-6 { };
+                                ctu13: ctu-7 { };
+                        };
 
-                        port@0 {
-                                reg = <0>;
-                                du_out_rgb0: endpoint {
+                        rcar_sound,src {
+                                src-0 {
+                                        status = "disabled";
+                                };
+                                src1: src-1 {
+                                        interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x87>, <&audma0 0x9c>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src2: src-2 {
+                                        interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x89>, <&audma0 0x9e>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src3: src-3 {
+                                        interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x8b>, <&audma0 0xa0>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src4: src-4 {
+                                        interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x8d>, <&audma0 0xb0>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src5: src-5 {
+                                        interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x8f>, <&audma0 0xb2>;
+                                        dma-names = "rx", "tx";
+                                };
+                                src6: src-6 {
+                                        interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x91>, <&audma0 0xb4>;
+                                        dma-names = "rx", "tx";
                                 };
                         };
-                        port@1 {
-                                reg = <1>;
-                                du_out_rgb1: endpoint {
+
+                        rcar_sound,ssi {
+                                ssi0: ssi-0 {
+                                        interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x01>, <&audma0 0x02>,
+                                               <&audma0 0x15>, <&audma0 0x16>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi1: ssi-1 {
+                                        interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x03>, <&audma0 0x04>,
+                                               <&audma0 0x49>, <&audma0 0x4a>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi2: ssi-2 {
+                                        interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x05>, <&audma0 0x06>,
+                                               <&audma0 0x63>, <&audma0 0x64>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi3: ssi-3 {
+                                        interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x07>, <&audma0 0x08>,
+                                               <&audma0 0x6f>, <&audma0 0x70>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi4: ssi-4 {
+                                        interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x09>, <&audma0 0x0a>,
+                                               <&audma0 0x71>, <&audma0 0x72>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi5: ssi-5 {
+                                        interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x0b>, <&audma0 0x0c>,
+                                               <&audma0 0x73>, <&audma0 0x74>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi6: ssi-6 {
+                                        interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x0d>, <&audma0 0x0e>,
+                                               <&audma0 0x75>, <&audma0 0x76>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi7: ssi-7 {
+                                        interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x0f>, <&audma0 0x10>,
+                                               <&audma0 0x79>, <&audma0 0x7a>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi8: ssi-8 {
+                                        interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x11>, <&audma0 0x12>,
+                                               <&audma0 0x7b>, <&audma0 0x7c>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
+                                };
+                                ssi9: ssi-9 {
+                                        interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+                                        dmas = <&audma0 0x13>, <&audma0 0x14>,
+                                               <&audma0 0x7d>, <&audma0 0x7e>;
+                                        dma-names = "rx", "tx", "rxu", "txu";
                                 };
                         };
                 };
-        };
-
-        can0: can@e6e80000 {
-                compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
-                reg = <0 0xe6e80000 0 0x1000>;
-                interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7794_CLK_RCAN>,
-                         <&can_clk>;
-                clock-names = "clkp1", "clkp2", "can_clk";
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 916>;
-                status = "disabled";
-        };
 
-        can1: can@e6e88000 {
-                compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
-                reg = <0 0xe6e88000 0 0x1000>;
-                interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7794_CLK_RCAN>,
-                         <&can_clk>;
-                clock-names = "clkp1", "clkp2", "can_clk";
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 915>;
-                status = "disabled";
-        };
-
-        /* External root clock */
-        extal_clk: extal {
-                compatible = "fixed-clock";
-                #clock-cells = <0>;
-                /* This value must be overridden by the board. */
-                clock-frequency = <0>;
-        };
-
-        /* External USB clock - can be overridden by the board */
-        usb_extal_clk: usb_extal {
-                compatible = "fixed-clock";
-                #clock-cells = <0>;
-                clock-frequency = <48000000>;
-        };
-
-        /* External CAN clock */
-        can_clk: can {
-                compatible = "fixed-clock";
-                #clock-cells = <0>;
-                /* This value must be overridden by the board. */
-                clock-frequency = <0>;
-        };
+                audma0: dma-controller@ec700000 {
+                        compatible = "renesas,dmac-r8a7794",
+                                     "renesas,rcar-dmac";
+                        reg = <0 0xec700000 0 0x10000>;
+                        interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "error",
+                                          "ch0", "ch1", "ch2", "ch3", "ch4",
+                                          "ch5", "ch6", "ch7", "ch8", "ch9",
+                                          "ch10", "ch11",
+                                          "ch12";
+                        clocks = <&cpg CPG_MOD 502>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 502>;
+                        #dma-cells = <1>;
+                        dma-channels = <13>;
+                };
 
-        /* External SCIF clock */
-        scif_clk: scif {
-                compatible = "fixed-clock";
-                #clock-cells = <0>;
-                /* This value must be overridden by the board. */
-                clock-frequency = <0>;
-        };
+                pci0: pci@ee090000 {
+                        compatible = "renesas,pci-r8a7794",
+                                     "renesas,pci-rcar-gen2";
+                        device_type = "pci";
+                        reg = <0 0xee090000 0 0xc00>,
+                              <0 0xee080000 0 0x1100>;
+                        interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 703>;
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 703>;
+                        status = "disabled";
+
+                        bus-range = <0 0>;
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        #interrupt-cells = <1>;
+                        ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
+                        interrupt-map-mask = <0xff00 0 0 0x7>;
+                        interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+                                         0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
+                                         0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+
+                        usb@1,0 {
+                                reg = <0x800 0 0 0 0>;
+                                phys = <&usb0 0>;
+                                phy-names = "usb";
+                        };
 
-        /*
-         * The external audio clocks are configured  as 0 Hz fixed
-         * frequency clocks by default.  Boards that provide audio
-         * clocks should override them.
-         */
-        audio_clka: audio_clka {
-                compatible = "fixed-clock";
-                #clock-cells = <0>;
-                clock-frequency = <0>;
-        };
-        audio_clkb: audio_clkb {
-                compatible = "fixed-clock";
-                #clock-cells = <0>;
-                clock-frequency = <0>;
-        };
-        audio_clkc: audio_clkc {
-                compatible = "fixed-clock";
-                #clock-cells = <0>;
-                clock-frequency = <0>;
-        };
+                        usb@2,0 {
+                                reg = <0x1000 0 0 0 0>;
+                                phys = <&usb0 0>;
+                                phy-names = "usb";
+                        };
+                };
 
-        cpg: clock-controller@e6150000 {
-                compatible = "renesas,r8a7794-cpg-mssr";
-                reg = <0 0xe6150000 0 0x1000>;
-                clocks = <&extal_clk>, <&usb_extal_clk>;
-                clock-names = "extal", "usb_extal";
-                #clock-cells = <2>;
-                #power-domain-cells = <0>;
-                #reset-cells = <1>;
-        };
+                pci1: pci@ee0d0000 {
+                        compatible = "renesas,pci-r8a7794",
+                                     "renesas,pci-rcar-gen2";
+                        device_type = "pci";
+                        reg = <0 0xee0d0000 0 0xc00>,
+                              <0 0xee0c0000 0 0x1100>;
+                        interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 703>;
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 703>;
+                        status = "disabled";
+
+                        bus-range = <1 1>;
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        #interrupt-cells = <1>;
+                        ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
+                        interrupt-map-mask = <0xff00 0 0 0x7>;
+                        interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+                                         0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
+                                         0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+
+                        usb@1,0 {
+                                reg = <0x10800 0 0 0 0>;
+                                phys = <&usb2 0>;
+                                phy-names = "usb";
+                        };
 
-        rst: reset-controller@e6160000 {
-                compatible = "renesas,r8a7794-rst";
-                reg = <0 0xe6160000 0 0x0100>;
-        };
+                        usb@2,0 {
+                                reg = <0x11000 0 0 0 0>;
+                                phys = <&usb2 0>;
+                                phy-names = "usb";
+                        };
+                };
 
-        prr: chipid@ff000044 {
-                compatible = "renesas,prr";
-                reg = <0 0xff000044 0 4>;
-        };
+                sdhi0: sd@ee100000 {
+                        compatible = "renesas,sdhi-r8a7794",
+                                     "renesas,rcar-gen2-sdhi";
+                        reg = <0 0xee100000 0 0x328>;
+                        interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 314>;
+                        dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+                               <&dmac1 0xcd>, <&dmac1 0xce>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        max-frequency = <195000000>;
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 314>;
+                        status = "disabled";
+                };
 
-        sysc: system-controller@e6180000 {
-                compatible = "renesas,r8a7794-sysc";
-                reg = <0 0xe6180000 0 0x0200>;
-                #power-domain-cells = <1>;
-        };
+                sdhi1: sd@ee140000 {
+                        compatible = "renesas,sdhi-r8a7794",
+                                     "renesas,rcar-gen2-sdhi";
+                        reg = <0 0xee140000 0 0x100>;
+                        interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 312>;
+                        dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+                               <&dmac1 0xc1>, <&dmac1 0xc2>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        max-frequency = <97500000>;
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 312>;
+                        status = "disabled";
+                };
 
-        ipmmu_sy0: mmu@e6280000 {
-                compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
-                reg = <0 0xe6280000 0 0x1000>;
-                interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
-                #iommu-cells = <1>;
-                status = "disabled";
-        };
+                sdhi2: sd@ee160000 {
+                        compatible = "renesas,sdhi-r8a7794",
+                                     "renesas,rcar-gen2-sdhi";
+                        reg = <0 0xee160000 0 0x100>;
+                        interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 311>;
+                        dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+                               <&dmac1 0xd3>, <&dmac1 0xd4>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        max-frequency = <97500000>;
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 311>;
+                        status = "disabled";
+                };
 
-        ipmmu_sy1: mmu@e6290000 {
-                compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
-                reg = <0 0xe6290000 0 0x1000>;
-                interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
-                #iommu-cells = <1>;
-                status = "disabled";
-        };
+                mmcif0: mmc@ee200000 {
+                        compatible = "renesas,mmcif-r8a7794",
+                                     "renesas,sh-mmcif";
+                        reg = <0 0xee200000 0 0x80>;
+                        interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 315>;
+                        dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+                               <&dmac1 0xd1>, <&dmac1 0xd2>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 315>;
+                        reg-io-width = <4>;
+                        status = "disabled";
+                };
 
-        ipmmu_ds: mmu@e6740000 {
-                compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
-                reg = <0 0xe6740000 0 0x1000>;
-                interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
-                #iommu-cells = <1>;
-                status = "disabled";
-        };
+                ether: ethernet@ee700000 {
+                        compatible = "renesas,ether-r8a7794",
+                                     "renesas,rcar-gen2-ether";
+                        reg = <0 0xee700000 0 0x400>;
+                        interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 813>;
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 813>;
+                        phy-mode = "rmii";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
 
-        ipmmu_mp: mmu@ec680000 {
-                compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
-                reg = <0 0xec680000 0 0x1000>;
-                interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
-                #iommu-cells = <1>;
-                status = "disabled";
-        };
+                gic: interrupt-controller@f1001000 {
+                        compatible = "arm,gic-400";
+                        #interrupt-cells = <3>;
+                        #address-cells = <0>;
+                        interrupt-controller;
+                        reg = <0 0xf1001000 0 0x1000>,
+                              <0 0xf1002000 0 0x2000>,
+                              <0 0xf1004000 0 0x2000>,
+                              <0 0xf1006000 0 0x2000>;
+                        interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+                        clocks = <&cpg CPG_MOD 408>;
+                        clock-names = "clk";
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 408>;
+                };
 
-        ipmmu_mx: mmu@fe951000 {
-                compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
-                reg = <0 0xfe951000 0 0x1000>;
-                interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
-                #iommu-cells = <1>;
-                status = "disabled";
-        };
+                vsp@fe928000 {
+                        compatible = "renesas,vsp1";
+                        reg = <0 0xfe928000 0 0x8000>;
+                        interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 131>;
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 131>;
+                };
 
-        ipmmu_gp: mmu@e62a0000 {
-                compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
-                reg = <0 0xe62a0000 0 0x1000>;
-                interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
-                             <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
-                #iommu-cells = <1>;
-                status = "disabled";
-        };
+                vsp@fe930000 {
+                        compatible = "renesas,vsp1";
+                        reg = <0 0xfe930000 0 0x8000>;
+                        interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 128>;
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 128>;
+                };
 
-        rcar_sound: sound@ec500000 {
-                /*
-                 * #sound-dai-cells is required
-                 *
-                 * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
-                 * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
-                 */
-                compatible = "renesas,rcar_sound-r8a7794",
-                             "renesas,rcar_sound-gen2";
-                reg =   <0 0xec500000 0 0x1000>, /* SCU */
-                        <0 0xec5a0000 0 0x100>,  /* ADG */
-                        <0 0xec540000 0 0x1000>, /* SSIU */
-                        <0 0xec541000 0 0x280>,  /* SSI */
-                        <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri */
-                reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
-
-                clocks = <&cpg CPG_MOD 1005>,
-                         <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
-                         <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
-                         <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
-                         <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
-                         <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
-                         <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>,
-                         <&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>,
-                         <&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>,
-                         <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
-                         <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
-                         <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
-                         <&audio_clka>, <&audio_clkb>, <&audio_clkc>,
-                         <&cpg CPG_CORE R8A7794_CLK_M2>;
-                clock-names = "ssi-all",
-                              "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
-                              "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
-                              "src.6", "src.5", "src.4", "src.3", "src.2",
-                              "src.1",
-                              "ctu.0", "ctu.1",
-                              "mix.0", "mix.1",
-                              "dvc.0", "dvc.1",
-                              "clk_a", "clk_b", "clk_c", "clk_i";
-                power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
-                resets = <&cpg 1005>,
-                         <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>,
-                         <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>,
-                         <&cpg 1014>, <&cpg 1015>;
-                reset-names = "ssi-all",
-                              "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
-                              "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0";
-
-                status = "disabled";
-
-                rcar_sound,dvc {
-                        dvc0: dvc-0 {
-                                dmas = <&audma0 0xbc>;
-                                dma-names = "tx";
-                        };
-                        dvc1: dvc-1 {
-                                dmas = <&audma0 0xbe>;
-                                dma-names = "tx";
+                du: display@feb00000 {
+                        compatible = "renesas,du-r8a7794";
+                        reg = <0 0xfeb00000 0 0x40000>;
+                        reg-names = "du";
+                        interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
+                        clock-names = "du.0", "du.1";
+                        status = "disabled";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@0 {
+                                        reg = <0>;
+                                        du_out_rgb0: endpoint {
+                                        };
+                                };
+                                port@1 {
+                                        reg = <1>;
+                                        du_out_rgb1: endpoint {
+                                        };
+                                };
                         };
                 };
 
-                rcar_sound,mix {
-                        mix0: mix-0 { };
-                        mix1: mix-1 { };
+                prr: chipid@ff000044 {
+                        compatible = "renesas,prr";
+                        reg = <0 0xff000044 0 4>;
                 };
 
-                rcar_sound,ctu {
-                        ctu00: ctu-0 { };
-                        ctu01: ctu-1 { };
-                        ctu02: ctu-2 { };
-                        ctu03: ctu-3 { };
-                        ctu10: ctu-4 { };
-                        ctu11: ctu-5 { };
-                        ctu12: ctu-6 { };
-                        ctu13: ctu-7 { };
+                cmt0: timer@ffca0000 {
+                        compatible = "renesas,r8a7794-cmt0",
+                                     "renesas,rcar-gen2-cmt0";
+                        reg = <0 0xffca0000 0 0x1004>;
+                        interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 124>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 124>;
+
+                        status = "disabled";
                 };
 
-                rcar_sound,src {
-                        src-0 {
-                                status = "disabled";
-                        };
-                        src1: src-1 {
-                                interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x87>, <&audma0 0x9c>;
-                                dma-names = "rx", "tx";
-                        };
-                        src2: src-2 {
-                                interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x89>, <&audma0 0x9e>;
-                                dma-names = "rx", "tx";
-                        };
-                        src3: src-3 {
-                                interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x8b>, <&audma0 0xa0>;
-                                dma-names = "rx", "tx";
-                        };
-                        src4: src-4 {
-                                interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x8d>, <&audma0 0xb0>;
-                                dma-names = "rx", "tx";
-                        };
-                        src5: src-5 {
-                                interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x8f>, <&audma0 0xb2>;
-                                dma-names = "rx", "tx";
-                        };
-                        src6: src-6 {
-                                interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x91>, <&audma0 0xb4>;
-                                dma-names = "rx", "tx";
-                        };
+                cmt1: timer@e6130000 {
+                        compatible = "renesas,r8a7794-cmt1",
+                                     "renesas,rcar-gen2-cmt1";
+                        reg = <0 0xe6130000 0 0x1004>;
+                        interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 329>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
+                        resets = <&cpg 329>;
+
+                        status = "disabled";
                 };
+        };
 
-                rcar_sound,ssi {
-                        ssi0: ssi-0 {
-                                interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x01>, <&audma0 0x02>,
-                                       <&audma0 0x15>, <&audma0 0x16>;
-                                dma-names = "rx", "tx", "rxu", "txu";
-                        };
-                        ssi1: ssi-1 {
-                                interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x03>, <&audma0 0x04>,
-                                       <&audma0 0x49>, <&audma0 0x4a>;
-                                dma-names = "rx", "tx", "rxu", "txu";
-                        };
-                        ssi2: ssi-2 {
-                                interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x05>, <&audma0 0x06>,
-                                       <&audma0 0x63>, <&audma0 0x64>;
-                                dma-names = "rx", "tx", "rxu", "txu";
-                        };
-                        ssi3: ssi-3 {
-                                interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x07>, <&audma0 0x08>,
-                                       <&audma0 0x6f>, <&audma0 0x70>;
-                                dma-names = "rx", "tx", "rxu", "txu";
-                        };
-                        ssi4: ssi-4 {
-                                interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x09>, <&audma0 0x0a>,
-                                       <&audma0 0x71>, <&audma0 0x72>;
-                                dma-names = "rx", "tx", "rxu", "txu";
-                        };
-                        ssi5: ssi-5 {
-                                interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x0b>, <&audma0 0x0c>,
-                                       <&audma0 0x73>, <&audma0 0x74>;
-                                dma-names = "rx", "tx", "rxu", "txu";
-                        };
-                        ssi6: ssi-6 {
-                                interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x0d>, <&audma0 0x0e>,
-                                       <&audma0 0x75>, <&audma0 0x76>;
-                                dma-names = "rx", "tx", "rxu", "txu";
-                        };
-                        ssi7: ssi-7 {
-                                interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x0f>, <&audma0 0x10>,
-                                       <&audma0 0x79>, <&audma0 0x7a>;
-                                dma-names = "rx", "tx", "rxu", "txu";
-                        };
-                        ssi8: ssi-8 {
-                                interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x11>, <&audma0 0x12>,
-                                       <&audma0 0x7b>, <&audma0 0x7c>;
-                                dma-names = "rx", "tx", "rxu", "txu";
-                        };
-                        ssi9: ssi-9 {
-                                interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
-                                dmas = <&audma0 0x13>, <&audma0 0x14>,
-                                       <&audma0 0x7d>, <&audma0 0x7e>;
-                                dma-names = "rx", "tx", "rxu", "txu";
-                        };
-                };
+        timer {
+                compatible = "arm,armv7-timer";
+                interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                                      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                                      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                                      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+        };
+
+        /* External USB clock - can be overridden by the board */
+        usb_extal_clk: usb_extal {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <48000000>;
         };
 };
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index 3b704cfed69a..a97458112ff6 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -280,7 +280,7 @@
                 max-frequency = <37500000>;
                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
-                clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+                clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
                 fifo-depth = <0x100>;
                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
                 resets = <&cru SRST_SDIO>;
@@ -298,7 +298,7 @@
                 max-frequency = <37500000>;
                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
-                clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+                clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
                 default-sample-phase = <158>;
                 disable-wp;
                 dmas = <&pdma 12>;
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index 780ec3a99b21..341deaf62ff6 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -621,7 +621,7 @@
                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
-                clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+                clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
                 fifo-depth = <0x100>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
@@ -634,7 +634,7 @@
                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
-                clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+                clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
                 fifo-depth = <0x100>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
@@ -649,7 +649,7 @@
                 max-frequency = <37500000>;
                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
-                clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+                clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
                 bus-width = <8>;
                 default-sample-phase = <158>;
                 fifo-depth = <0x100>;
diff --git a/arch/arm/boot/dts/rk3288-phycore-som.dtsi b/arch/arm/boot/dts/rk3288-phycore-som.dtsi
index 99cfae875e12..5eae4776ffde 100644
--- a/arch/arm/boot/dts/rk3288-phycore-som.dtsi
+++ b/arch/arm/boot/dts/rk3288-phycore-som.dtsi
@@ -110,26 +110,6 @@
         };
 };
 
-&cpu0 {
-        cpu0-supply = <&vdd_cpu>;
-        operating-points = <
-                /* KHz    uV */
-                1800000 1400000
-                1608000 1350000
-                1512000 1300000
-                1416000 1200000
-                1200000 1100000
-                1008000 1050000
-                 816000 1000000
-                 696000  950000
-                 600000  900000
-                 408000  900000
-                 312000  900000
-                 216000  900000
-                 126000  900000
-        >;
-};
-
 &emmc {
         status = "okay";
         bus-width = <8>;
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index b9c05b57735e..eae5e1ee9cd8 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -861,24 +861,24 @@
                                 uart0 {
                                         pinctrl_uart0: uart0-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE   /* conflicts with PWMFI2, ISI_D8 */
-                                                         AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* conflicts with ISI_PCK */
+                                                        <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* conflicts with PWMFI2, ISI_D8 */
+                                                         AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with ISI_PCK */
                                         };
                                 };
 
                                 uart1 {
                                         pinctrl_uart1: uart1-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE   /* conflicts with TWD0, ISI_VSYNC */
-                                                         AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;      /* conflicts with TWCK0, ISI_HSYNC */
+                                                        <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* conflicts with TWD0, ISI_VSYNC */
+                                                         AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with TWCK0, ISI_HSYNC */
                                         };
                                 };
 
                                 usart0 {
                                         pinctrl_usart0: usart0-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD17 periph A */
-                                                         AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PD18 periph A with pullup */
+                                                        <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+                                                         AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE>;
                                         };
 
                                         pinctrl_usart0_rts_cts: usart0_rts_cts-0 {
@@ -891,8 +891,8 @@
                                 usart1 {
                                         pinctrl_usart1: usart1-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB28 periph A */
-                                                         AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PB29 periph A with pullup */
+                                                        <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+                                                         AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
                                         };
 
                                         pinctrl_usart1_rts_cts: usart1_rts_cts-0 {
@@ -905,8 +905,8 @@
                                 usart2 {
                                         pinctrl_usart2: usart2-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOE 25 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PE25 periph B, conflicts with A25 */
-                                                         AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;      /* PE26 periph B with pullup, conflicts NCS0 */
+                                                        <AT91_PIOE 25 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* conflicts with A25 */
+                                                         AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts NCS0 */
                                         };
 
                                         pinctrl_usart2_rts_cts: usart2_rts_cts-0 {
@@ -919,8 +919,8 @@
                                 usart3 {
                                         pinctrl_usart3: usart3-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PE18 periph B, conflicts with A18 */
-                                                         AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;      /* PE19 periph B with pullup, conflicts with A19 */
+                                                        <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* conflicts with A18 */
+                                                         AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with A19 */
                                         };
 
                                         pinctrl_usart3_rts_cts: usart3_rts_cts-0 {
diff --git a/arch/arm/boot/dts/sama5d34ek.dts b/arch/arm/boot/dts/sama5d34ek.dts
index c8b8449fdc3e..15d5c46013a4 100644
--- a/arch/arm/boot/dts/sama5d34ek.dts
+++ b/arch/arm/boot/dts/sama5d34ek.dts
@@ -38,7 +38,7 @@
                                 status = "okay";
 
                                 24c256@50 {
-                                        compatible = "24c256";
+                                        compatible = "atmel,24c256";
                                         reg = <0x50>;
                                         pagesize = <64>;
                                 };
diff --git a/arch/arm/boot/dts/sama5d3_uart.dtsi b/arch/arm/boot/dts/sama5d3_uart.dtsi
index 186377d41c91..f599f8a5f664 100644
--- a/arch/arm/boot/dts/sama5d3_uart.dtsi
+++ b/arch/arm/boot/dts/sama5d3_uart.dtsi
@@ -23,16 +23,16 @@
                                 uart0 {
                                         pinctrl_uart0: uart0-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */
-                                                         AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PC30 periph A with pullup, conflicts with ISI_PCK */
+                                                        <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* conflicts with PWMFI2, ISI_D8 */
+                                                         AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with ISI_PCK */
                                         };
                                 };
 
                                 uart1 {
                                         pinctrl_uart1: uart1-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */
-                                                         AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;      /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */
+                                                        <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* conflicts with TWD0, ISI_VSYNC */
+                                                         AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with TWCK0, ISI_HSYNC */
                                         };
                                 };
                         };
diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
index 373b3621b536..0cf9beddd556 100644
--- a/arch/arm/boot/dts/sama5d4.dtsi
+++ b/arch/arm/boot/dts/sama5d4.dtsi
@@ -1379,7 +1379,7 @@
                         pinctrl@fc06a000 {
                                 #address-cells = <1>;
                                 #size-cells = <1>;
-                                compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
+                                compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus";
                                 ranges = <0xfc068000 0xfc068000 0x100
                                           0xfc06a000 0xfc06a000 0x4000>;
                                 /* WARNING: revisit as pin spec has changed */
@@ -1926,8 +1926,8 @@
                                 uart0 {
                                         pinctrl_uart0: uart0-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOE 29 AT91_PERIPH_B AT91_PINCTRL_NONE           /* RXD */
-                                                         AT91_PIOE 30 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* TXD */
+                                                        <AT91_PIOE 29 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* RXD */
+                                                         AT91_PIOE 30 AT91_PERIPH_B AT91_PINCTRL_NONE           /* TXD */
                                                         >;
                                         };
                                 };
@@ -1935,8 +1935,8 @@
                                 uart1 {
                                         pinctrl_uart1: uart1-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOC 25 AT91_PERIPH_C AT91_PINCTRL_NONE           /* RXD */
-                                                         AT91_PIOC 26 AT91_PERIPH_C AT91_PINCTRL_PULL_UP        /* TXD */
+                                                        <AT91_PIOC 25 AT91_PERIPH_C AT91_PINCTRL_PULL_UP        /* RXD */
+                                                         AT91_PIOC 26 AT91_PERIPH_C AT91_PINCTRL_NONE           /* TXD */
                                                         >;
                                         };
                                 };
@@ -1944,8 +1944,8 @@
                                 usart0 {
                                         pinctrl_usart0: usart0-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE           /* RXD */
-                                                         AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* TXD */
+                                                        <AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* RXD */
+                                                         AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE           /* TXD */
                                                         >;
                                         };
                                         pinctrl_usart0_rts: usart0_rts-0 {
@@ -1959,8 +1959,8 @@
                                 usart1 {
                                         pinctrl_usart1: usart1-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE           /* RXD */
-                                                         AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* TXD */
+                                                        <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* RXD */
+                                                         AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE           /* TXD */
                                                         >;
                                         };
                                         pinctrl_usart1_rts: usart1_rts-0 {
@@ -1974,8 +1974,8 @@
                                 usart2 {
                                         pinctrl_usart2: usart2-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE            /* RXD - conflicts with G0_CRS, ISI_HSYNC */
-                                                         AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP         /* TXD - conflicts with G0_COL, PCK2 */
+                                                        <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP         /* RXD - conflicts with G0_CRS, ISI_HSYNC */
+                                                         AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE            /* TXD - conflicts with G0_COL, PCK2 */
                                                         >;
                                         };
                                         pinctrl_usart2_rts: usart2_rts-0 {
@@ -1989,8 +1989,8 @@
                                 usart3 {
                                         pinctrl_usart3: usart3-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE           /* RXD */
-                                                         AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* TXD */
+                                                        <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* RXD */
+                                                         AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE           /* TXD */
                                                         >;
                                         };
                                 };
@@ -1998,8 +1998,8 @@
                                 usart4 {
                                         pinctrl_usart4: usart4-0 {
                                                 atmel,pins =
-                                                        <AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_NONE           /* RXD */
-                                                         AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* TXD */
+                                                        <AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* RXD */
+                                                         AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_NONE           /* TXD */
                                                         >;
                                         };
                                         pinctrl_usart4_rts: usart4_rts-0 {
diff --git a/arch/arm/boot/dts/samsung_k3pe0e000b.dtsi b/arch/arm/boot/dts/samsung_k3pe0e000b.dtsi
deleted file mode 100644
index dbdda36179ee..000000000000
--- a/arch/arm/boot/dts/samsung_k3pe0e000b.dtsi
+++ /dev/null
@@ -1,68 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Timings and Geometry for Samsung K3PE0E000B memory part
- */
-
-/ {
-        samsung_K3PE0E000B: lpddr2 {
-                compatible      = "Samsung,K3PE0E000B","jedec,lpddr2-s4";
-                density         = <4096>;
-                io-width        = <32>;
-
-                tRPab-min-tck   = <3>;
-                tRCD-min-tck    = <3>;
-                tWR-min-tck     = <3>;
-                tRASmin-min-tck = <3>;
-                tRRD-min-tck    = <2>;
-                tWTR-min-tck    = <2>;
-                tXP-min-tck     = <2>;
-                tRTP-min-tck    = <2>;
-                tCKE-min-tck    = <3>;
-                tCKESR-min-tck  = <3>;
-                tFAW-min-tck    = <8>;
-
-                timings_samsung_K3PE0E000B_533MHz: lpddr2-timings@0 {
-                        compatible      = "jedec,lpddr2-timings";
-                        min-freq        = <10000000>;
-                        max-freq        = <533333333>;
-                        tRPab           = <21000>;
-                        tRCD            = <18000>;
-                        tWR             = <15000>;
-                        tRAS-min        = <42000>;
-                        tRRD            = <10000>;
-                        tWTR            = <7500>;
-                        tXP             = <7500>;
-                        tRTP            = <7500>;
-                        tCKESR          = <15000>;
-                        tDQSCK-max      = <5500>;
-                        tFAW            = <50000>;
-                        tZQCS           = <90000>;
-                        tZQCL           = <360000>;
-                        tZQinit         = <1000000>;
-                        tRAS-max-ns     = <70000>;
-                        tDQSCK-max-derated = <6000>;
-                };
-
-                timings_samsung_K3PE0E000B_266MHz: lpddr2-timings@1 {
-                        compatible      = "jedec,lpddr2-timings";
-                        min-freq        = <10000000>;
-                        max-freq        = <266666666>;
-                        tRPab           = <21000>;
-                        tRCD            = <18000>;
-                        tWR             = <15000>;
-                        tRAS-min        = <42000>;
-                        tRRD            = <10000>;
-                        tWTR            = <7500>;
-                        tXP             = <7500>;
-                        tRTP            = <7500>;
-                        tCKESR          = <15000>;
-                        tDQSCK-max      = <5500>;
-                        tFAW            = <50000>;
-                        tZQCS           = <90000>;
-                        tZQCL           = <360000>;
-                        tZQinit         = <1000000>;
-                        tRAS-max-ns     = <70000>;
-                        tDQSCK-max-derated = <6000>;
-                };
-        };
-};
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index c42ca7022e8c..486d4e7433ed 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -831,7 +831,7 @@
                 timer@fffec600 {
                         compatible = "arm,cortex-a9-twd-timer";
                         reg = <0xfffec600 0x100>;
-                        interrupts = <1 13 0xf04>;
+                        interrupts = <1 13 0xf01>;
                         clocks = <&mpu_periph_clk>;
                 };
 
diff --git a/arch/arm/boot/dts/stih407-b2120.dts b/arch/arm/boot/dts/stih407-b2120.dts
index c8ad905d0309..de3c8bf129b5 100644
--- a/arch/arm/boot/dts/stih407-b2120.dts
+++ b/arch/arm/boot/dts/stih407-b2120.dts
@@ -15,10 +15,10 @@
 
         chosen {
                 bootargs = "console=ttyAS0,115200 clk_ignore_unused";
-                linux,stdout-path = &sbc_serial0;
+                stdout-path = &sbc_serial0;
         };
 
-        memory {
+        memory@40000000 {
                 device_type = "memory";
                 reg = <0x40000000 0x80000000>;
         };
diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi
index d0a24d9e517a..ea7833489832 100644
--- a/arch/arm/boot/dts/stih407-clock.dtsi
+++ b/arch/arm/boot/dts/stih407-clock.dtsi
@@ -7,33 +7,27 @@
  */
 #include <dt-bindings/clock/stih407-clks.h>
 / {
+        /*
+         * Fixed 30MHz oscillator inputs to SoC
+         */
+        clk_sysin: clk-sysin {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <30000000>;
+        };
+
+        clk_tmdsout_hdmi: clk-tmdsout-hdmi {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
         clocks {
                 #address-cells = <1>;
                 #size-cells = <1>;
                 ranges;
 
                 /*
-                 * Fixed 30MHz oscillator inputs to SoC
-                 */
-                clk_sysin: clk-sysin {
-                        #clock-cells = <0>;
-                        compatible = "fixed-clock";
-                        clock-frequency = <30000000>;
-                };
-
-                /*
-                 * ARM Peripheral clock for timers
-                 */
-                arm_periph_clk: clk-m-a9-periphs {
-                        #clock-cells = <0>;
-                        compatible = "fixed-factor-clock";
-
-                        clocks = <&clk_m_a9>;
-                        clock-div = <2>;
-                        clock-mult = <1>;
-                };
-
-                /*
                  * A9 PLL.
                  */
                 clockgen-a9@92b0000 {
@@ -62,32 +56,19 @@
                                  <&clockgen_a9_pll 0>,
                                  <&clk_s_c0_flexgen 13>,
                                  <&clk_m_a9_ext2f_div2>;
-                };
 
-                /*
-                 * ARM Peripheral clock for timers
-                 */
-                clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
-                        #clock-cells = <0>;
-                        compatible = "fixed-factor-clock";
-
-                        clocks = <&clk_s_c0_flexgen 13>;
-
-                        clock-output-names = "clk-m-a9-ext2f-div2";
 
-                        clock-div = <2>;
-                        clock-mult = <1>;
-                };
+                        /*
+                         * ARM Peripheral clock for timers
+                         */
+                        arm_periph_clk: clk-m-a9-periphs {
+                                #clock-cells = <0>;
+                                compatible = "fixed-factor-clock";
 
-                /*
-                 * Bootloader initialized system infrastructure clock for
-                 * serial devices.
-                 */
-                clk_ext2f_a9: clockgen-c0@13 {
-                        #clock-cells = <0>;
-                        compatible = "fixed-clock";
-                        clock-frequency = <200000000>;
-                        clock-output-names = "clk-s-icn-reg-0";
+                                clocks = <&clk_m_a9>;
+                                clock-div = <2>;
+                                clock-mult = <1>;
+                        };
                 };
 
                 clockgen-a@90ff000 {
@@ -204,6 +185,21 @@
                                                  <CLK_EXT2F_A9>,
                                                  <CLK_ICN_LMI>,
                                                  <CLK_ICN_SBC>;
+
+                                /*
+                                 * ARM Peripheral clock for timers
+                                 */
+                                clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
+                                        #clock-cells = <0>;
+                                        compatible = "fixed-factor-clock";
+
+                                        clocks = <&clk_s_c0_flexgen 13>;
+
+                                        clock-output-names = "clk-m-a9-ext2f-div2";
+
+                                        clock-div = <2>;
+                                        clock-mult = <1>;
+                                };
                         };
                 };
 
@@ -254,13 +250,7 @@
                                              "clk-s-d2-fs0-ch3";
                 };
 
-                clk_tmdsout_hdmi: clk-tmdsout-hdmi {
-                        #clock-cells = <0>;
-                        compatible = "fixed-clock";
-                        clock-frequency = <0>;
-                };
-
-                clockgen-d2@x9106000 {
+                clockgen-d2@9106000 {
                         compatible = "st,clkgen-c32";
                         reg = <0x9106000 0x1000>;
 
diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
index cf3756976c39..f7362c31de29 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -92,7 +92,7 @@
                 clocks = <&arm_periph_clk>;
         };
 
-        l2: cache-controller {
+        l2: cache-controller@8762000 {
                 compatible = "arm,pl310-cache";
                 reg = <0x08762000 0x1000>;
                 arm,data-latency = <3 3 3>;
@@ -125,24 +125,28 @@
                 ranges;
                 compatible = "simple-bus";
 
-                restart {
+                restart: restart-controller@0 {
                         compatible = "st,stih407-restart";
+                        reg = <0 0>;
                         st,syscfg = <&syscfg_sbc_reg>;
                         status = "okay";
                 };
 
-                powerdown: powerdown-controller {
+                powerdown: powerdown-controller@0 {
                         compatible = "st,stih407-powerdown";
+                        reg = <0 0>;
                         #reset-cells = <1>;
                 };
 
-                softreset: softreset-controller {
+                softreset: softreset-controller@0 {
                         compatible = "st,stih407-softreset";
+                        reg = <0 0>;
                         #reset-cells = <1>;
                 };
 
-                picophyreset: picophyreset-controller {
+                picophyreset: picophyreset-controller@0 {
                         compatible = "st,stih407-picophyreset";
+                        reg = <0 0>;
                         #reset-cells = <1>;
                 };
 
@@ -174,6 +178,13 @@
                 syscfg_core: core-syscfg@92b0000 {
                         compatible = "st,stih407-core-syscfg", "syscon";
                         reg = <0x92b0000 0x1000>;
+
+                        sti_sasg_codec: sti-sasg-codec {
+                                compatible = "st,stih407-sas-codec";
+                                #sound-dai-cells = <1>;
+                                status = "disabled";
+                                st,syscfg = <&syscfg_core>;
+                        };
                 };
 
                 syscfg_lpm: lpm-syscfg@94b5100 {
@@ -181,8 +192,9 @@
                         reg = <0x94b5100 0x1000>;
                 };
 
-                irq-syscfg {
+                irq-syscfg@0 {
                         compatible    = "st,stih407-irq-syscfg";
+                        reg = <0 0>;
                         st,syscfg     = <&syscfg_core>;
                         st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
                                         <ST_IRQ_SYSCFG_PMU_1>;
@@ -380,8 +392,9 @@
                         status = "disabled";
                 };
 
-                usb2_picophy0: phy1 {
+                usb2_picophy0: phy1@0 {
                         compatible = "st,stih407-usb2-phy";
+                        reg = <0 0>;
                         #phy-cells = <0>;
                         st,syscfg = <&syscfg_core 0x100 0xf4>;
                         resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
@@ -389,12 +402,13 @@
                         reset-names = "global", "port";
                 };
 
-                miphy28lp_phy: miphy28lp@9b22000 {
+                miphy28lp_phy: miphy28lp@0 {
                         compatible = "st,miphy28lp-phy";
                         st,syscfg = <&syscfg_core>;
                         #address-cells  = <1>;
                         #size-cells     = <1>;
                         ranges;
+                        reg = <0 0>;
 
                         phy_port0: port@9b22000 {
                                 reg = <0x9b22000 0xff>,
@@ -805,6 +819,7 @@
 
                 st231_gp0: st231-gp0@0 {
                         compatible      = "st,st231-rproc";
+                        reg             = <0 0>;
                         memory-region   = <&gp0_reserved>;
                         resets          = <&softreset STIH407_ST231_GP0_SOFTRESET>;
                         reset-names     = "sw_reset";
@@ -818,6 +833,7 @@
 
                 st231_delta: st231-delta@0 {
                         compatible      = "st,st231-rproc";
+                        reg             = <0 0>;
                         memory-region   = <&delta_reserved>;
                         resets          = <&softreset STIH407_ST231_DMU_SOFTRESET>;
                         reset-names     = "sw_reset";
@@ -885,13 +901,6 @@
                         status = "disabled";
                 };
 
-                sti_sasg_codec: sti-sasg-codec {
-                        compatible = "st,stih407-sas-codec";
-                        #sound-dai-cells = <1>;
-                        status = "disabled";
-                        st,syscfg = <&syscfg_core>;
-                };
-
                 sti_uni_player0: sti-uni-player@8d80000 {
                         compatible = "st,stih407-uni-player-hdmi";
                         #sound-dai-cells = <0>;
@@ -980,8 +989,9 @@
                         status = "disabled";
                 };
 
-                delta0 {
+                delta0@0 {
                         compatible = "st,st-delta";
+                        reg = <0 0>;
                         clock-names = "delta",
                                       "delta-st231",
                                       "delta-flash-promip";
diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi
index a29090077fdf..53c6888d1fc0 100644
--- a/arch/arm/boot/dts/stih407-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi
@@ -45,7 +45,7 @@
         };
 
         soc {
-                pin-controller-sbc {
+                pin-controller-sbc@961f080 {
                         #address-cells = <1>;
                         #size-cells = <1>;
                         compatible = "st,stih407-sbc-pinctrl";
@@ -369,7 +369,7 @@
                         };
                 };
 
-                pin-controller-front0 {
+                pin-controller-front0@920f080 {
                         #address-cells = <1>;
                         #size-cells = <1>;
                         compatible = "st,stih407-front-pinctrl";
@@ -929,7 +929,7 @@
                         };
                 };
 
-                pin-controller-front1 {
+                pin-controller-front1@921f080 {
                         #address-cells = <1>;
                         #size-cells = <1>;
                         compatible = "st,stih407-front-pinctrl";
@@ -962,7 +962,7 @@
                         };
                 };
 
-                pin-controller-rear {
+                pin-controller-rear@922f080 {
                         #address-cells = <1>;
                         #size-cells = <1>;
                         compatible = "st,stih407-rear-pinctrl";
@@ -1157,7 +1157,7 @@
                         };
                 };
 
-                pin-controller-flash {
+                pin-controller-flash@923f080 {
                         #address-cells = <1>;
                         #size-cells = <1>;
                         compatible = "st,stih407-flash-pinctrl";
diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi
index 11fdecd9312e..57efc87dec2b 100644
--- a/arch/arm/boot/dts/stih407.dtsi
+++ b/arch/arm/boot/dts/stih407.dtsi
@@ -11,11 +11,11 @@
 #include <dt-bindings/gpio/gpio.h>
 / {
         soc {
-                sti-display-subsystem {
+                sti-display-subsystem@0 {
                         compatible = "st,sti-display-subsystem";
                         #address-cells = <1>;
                         #size-cells = <1>;
-
+                        reg = <0 0>;
                         assigned-clocks = <&clk_s_d2_quadfs 0>,
                                           <&clk_s_d2_quadfs 1>,
                                           <&clk_s_c0_pll1 0>,
@@ -107,6 +107,7 @@
                                 compatible = "st,stih407-hdmi";
                                 reg = <0x8d04000 0x1000>;
                                 reg-names = "hdmi-reg";
+                                #sound-dai-cells = <0>;
                                 interrupts = <GIC_SPI 106 IRQ_TYPE_NONE>;
                                 interrupt-names = "irq";
                                 clock-names = "pix",
diff --git a/arch/arm/boot/dts/stih410-b2120.dts b/arch/arm/boot/dts/stih410-b2120.dts
index 9830be577433..0a59b7b0f4b2 100644
--- a/arch/arm/boot/dts/stih410-b2120.dts
+++ b/arch/arm/boot/dts/stih410-b2120.dts
@@ -15,10 +15,10 @@
 
         chosen {
                 bootargs = "console=ttyAS0,115200 clk_ignore_unused";
-                linux,stdout-path = &sbc_serial0;
+                stdout-path = &sbc_serial0;
         };
 
-        memory {
+        memory@40000000 {
                 device_type = "memory";
                 reg = <0x40000000 0x80000000>;
         };
@@ -37,11 +37,11 @@
                         sd-uhs-ddr50;
                 };
 
-                usb2_picophy1: phy2 {
+                usb2_picophy1: phy2@0 {
                         status = "okay";
                 };
 
-                usb2_picophy2: phy3 {
+                usb2_picophy2: phy3@0 {
                         status = "okay";
                 };
 
@@ -61,7 +61,7 @@
                         status = "okay";
                 };
 
-                sti-display-subsystem {
+                sti-display-subsystem@0 {
                         sti-hda@8d02000 {
                                 status = "okay";
                         };
diff --git a/arch/arm/boot/dts/stih410-b2260.dts b/arch/arm/boot/dts/stih410-b2260.dts
index c663b70c43a7..feb8834478fa 100644
--- a/arch/arm/boot/dts/stih410-b2260.dts
+++ b/arch/arm/boot/dts/stih410-b2260.dts
@@ -16,10 +16,10 @@
 
         chosen {
                 bootargs = "console=ttyAS1,115200 clk_ignore_unused";
-                linux,stdout-path = &uart1;
+                stdout-path = &uart1;
         };
 
-        memory {
+        memory@40000000 {
                 device_type = "memory";
                 reg = <0x40000000 0x40000000>;
         };
@@ -29,36 +29,54 @@
                 ethernet0 = &ethernet0;
         };
 
-        soc {
+        leds {
+                compatible = "gpio-leds";
+                user_green_1 {
+                        label = "User_green_1";
+                        gpios = <&pio1 3 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "heartbeat";
+                        default-state = "off";
+                };
 
-                leds {
-                        compatible = "gpio-leds";
-                        user_green_1 {
-                                label = "User_green_1";
-                                gpios = <&pio1 3 GPIO_ACTIVE_LOW>;
-                                linux,default-trigger = "heartbeat";
-                                default-state = "off";
-                        };
+                user_green_2 {
+                        label = "User_green_2";
+                        gpios = <&pio4 1 GPIO_ACTIVE_LOW>;
+                        default-state = "off";
+                };
 
-                        user_green_2 {
-                                label = "User_green_2";
-                                gpios = <&pio4 1 GPIO_ACTIVE_LOW>;
-                                default-state = "off";
-                        };
+                user_green_3 {
+                        label = "User_green_3";
+                        gpios = <&pio2 1 GPIO_ACTIVE_LOW>;
+                        default-state = "off";
+                };
+
+                user_green_4 {
+                        label = "User_green_4";
+                        gpios = <&pio2 5 GPIO_ACTIVE_LOW>;
+                        default-state = "off";
+                };
+        };
 
-                        user_green_3 {
-                                label = "User_green_3";
-                                gpios = <&pio2 1 GPIO_ACTIVE_LOW>;
-                                default-state = "off";
+        sound: sound {
+                compatible = "simple-audio-card";
+                simple-audio-card,name = "STI-B2260";
+                status = "okay";
+
+                simple-audio-card,dai-link0 {
+                        /* DAC */
+                        format = "i2s";
+                        mclk-fs = <128>;
+                        cpu {
+                                sound-dai = <&sti_uni_player0>;
                         };
 
-                        user_green_4 {
-                                label = "User_green_4";
-                                gpios = <&pio2 5 GPIO_ACTIVE_LOW>;
-                                default-state = "off";
+                        codec {
+                                sound-dai = <&sti_hdmi>;
                         };
                 };
+        };
 
+        soc {
                 /* Low speed expansion connector */
                 uart0: serial@9830000 {
                         label = "LS-UART0";
@@ -128,11 +146,11 @@
                         status = "okay";
                 };
 
-                usb2_picophy1: phy2 {
+                usb2_picophy1: phy2@0 {
                         status = "okay";
                 };
 
-                usb2_picophy2: phy3 {
+                usb2_picophy2: phy3@0 {
                         status = "okay";
                 };
 
@@ -182,26 +200,7 @@
                         status = "okay";
                 };
 
-                sound {
-                        compatible = "simple-audio-card";
-                        simple-audio-card,name = "STI-B2260";
-                        status = "okay";
-
-                        simple-audio-card,dai-link@0 {
-                                /* DAC */
-                                format = "i2s";
-                                mclk-fs = <128>;
-                                cpu {
-                                        sound-dai = <&sti_uni_player0>;
-                                };
-
-                                codec {
-                                        sound-dai = <&sti_hdmi>;
-                                };
-                        };
-                };
-
-                miphy28lp_phy: miphy28lp@9b22000 {
+                miphy28lp_phy: miphy28lp@0 {
 
                         phy_port1: port@9b2a000 {
                                 st,osc-force-ext;
diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih410-clock.dtsi
index fde5df17f575..5f11d09cb030 100644
--- a/arch/arm/boot/dts/stih410-clock.dtsi
+++ b/arch/arm/boot/dts/stih410-clock.dtsi
@@ -7,6 +7,22 @@
  */
 #include <dt-bindings/clock/stih410-clks.h>
 / {
+        /*
+         * Fixed 30MHz oscillator inputs to SoC
+         */
+        clk_sysin: clk-sysin {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <30000000>;
+                clock-output-names = "CLK_SYSIN";
+        };
+
+        clk_tmdsout_hdmi: clk-tmdsout-hdmi {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
         clocks {
                 #address-cells = <1>;
                 #size-cells = <1>;
@@ -15,27 +31,6 @@
                 compatible = "st,stih410-clk", "simple-bus";
 
                 /*
-                 * Fixed 30MHz oscillator inputs to SoC
-                 */
-                clk_sysin: clk-sysin {
-                        #clock-cells = <0>;
-                        compatible = "fixed-clock";
-                        clock-frequency = <30000000>;
-                        clock-output-names = "CLK_SYSIN";
-                };
-
-                /*
-                 * ARM Peripheral clock for timers
-                 */
-                arm_periph_clk: clk-m-a9-periphs {
-                        #clock-cells = <0>;
-                        compatible = "fixed-factor-clock";
-                        clocks = <&clk_m_a9>;
-                        clock-div = <2>;
-                        clock-mult = <1>;
-                };
-
-                /*
                  * A9 PLL.
                  */
                 clockgen-a9@92b0000 {
@@ -64,32 +59,16 @@
                                  <&clockgen_a9_pll 0>,
                                  <&clk_s_c0_flexgen 13>,
                                  <&clk_m_a9_ext2f_div2>;
-                };
-
-                /*
-                 * ARM Peripheral clock for timers
-                 */
-                clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
-                        #clock-cells = <0>;
-                        compatible = "fixed-factor-clock";
-
-                        clocks = <&clk_s_c0_flexgen 13>;
-
-                        clock-output-names = "clk-m-a9-ext2f-div2";
-
-                        clock-div = <2>;
-                        clock-mult = <1>;
-                };
-
-                /*
-                 * Bootloader initialized system infrastructure clock for
-                 * serial devices.
-                 */
-                clk_ext2f_a9: clockgen-c0@13 {
-                        #clock-cells = <0>;
-                        compatible = "fixed-clock";
-                        clock-frequency = <200000000>;
-                        clock-output-names = "clk-s-icn-reg-0";
+                        /*
+                         * ARM Peripheral clock for timers
+                         */
+                        arm_periph_clk: clk-m-a9-periphs {
+                                #clock-cells = <0>;
+                                compatible = "fixed-factor-clock";
+                                clocks = <&clk_m_a9>;
+                                clock-div = <2>;
+                                clock-mult = <1>;
+                        };
                 };
 
                 clockgen-a@90ff000 {
@@ -214,6 +193,21 @@
                                                  <CLK_EXT2F_A9>,
                                                  <CLK_ICN_LMI>,
                                                  <CLK_ICN_SBC>;
+
+                                /*
+                                 * ARM Peripheral clock for timers
+                                 */
+                                clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
+                                        #clock-cells = <0>;
+                                        compatible = "fixed-factor-clock";
+
+                                        clocks = <&clk_s_c0_flexgen 13>;
+
+                                        clock-output-names = "clk-m-a9-ext2f-div2";
+
+                                        clock-div = <2>;
+                                        clock-mult = <1>;
+                                };
                         };
                 };
 
@@ -266,13 +260,7 @@
                                              "clk-s-d2-fs0-ch3";
                 };
 
-                clk_tmdsout_hdmi: clk-tmdsout-hdmi {
-                        #clock-cells = <0>;
-                        compatible = "fixed-clock";
-                        clock-frequency = <0>;
-                };
-
-                clockgen-d2@x9106000 {
+                clockgen-d2@9106000 {
                         compatible = "st,clkgen-c32";
                         reg = <0x9106000 0x1000>;
 
diff --git a/arch/arm/boot/dts/stih410-pinctrl.dtsi b/arch/arm/boot/dts/stih410-pinctrl.dtsi
index b3e9dfc81c07..5ae1fd66c0b8 100644
--- a/arch/arm/boot/dts/stih410-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih410-pinctrl.dtsi
@@ -10,7 +10,7 @@
 / {
 
         soc {
-                pin-controller-rear {
+                pin-controller-rear@922f080 {
 
                         usb0 {
                                 pinctrl_usb0: usb2-0 {
diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi
index 68b5ff91d6a7..3313005ee15c 100644
--- a/arch/arm/boot/dts/stih410.dtsi
+++ b/arch/arm/boot/dts/stih410.dtsi
@@ -16,8 +16,9 @@
         };
 
         soc {
-                usb2_picophy1: phy2 {
+                usb2_picophy1: phy2@0 {
                         compatible = "st,stih407-usb2-phy";
+                        reg = <0 0>;
                         #phy-cells = <0>;
                         st,syscfg = <&syscfg_core 0xf8 0xf4>;
                         resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
@@ -27,8 +28,9 @@
                         status = "disabled";
                 };
 
-                usb2_picophy2: phy3 {
+                usb2_picophy2: phy3@0 {
                         compatible = "st,stih407-usb2-phy";
+                        reg = <0 0>;
                         #phy-cells = <0>;
                         st,syscfg = <&syscfg_core 0xfc 0xf4>;
                         resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
@@ -102,11 +104,12 @@
                         status = "disabled";
                 };
 
-                sti-display-subsystem {
+                sti-display-subsystem@0 {
                         compatible = "st,sti-display-subsystem";
                         #address-cells = <1>;
                         #size-cells = <1>;
 
+                        reg = <0 0>;
                         assigned-clocks = <&clk_s_d2_quadfs 0>,
                                           <&clk_s_d2_quadfs 1>,
                                           <&clk_s_c0_pll1 0>,
@@ -198,6 +201,7 @@
                                 compatible = "st,stih407-hdmi";
                                 reg = <0x8d04000 0x1000>;
                                 reg-names = "hdmi-reg";
+                                #sound-dai-cells = <0>;
                                 interrupts = <GIC_SPI 106 IRQ_TYPE_NONE>;
                                 interrupt-names = "irq";
                                 clock-names = "pix",
@@ -235,7 +239,7 @@
                                          <&clk_s_d2_quadfs 1>;
                         };
 
-                        sti-hqvdp@9c000000 {
+                        sti-hqvdp@9c00000 {
                                 compatible = "st,stih407-hqvdp";
                                 reg = <0x9C00000 0x100000>;
                                 clock-names = "hqvdp", "pix_main";
@@ -273,7 +277,7 @@
                         interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
                 };
 
-                delta0 {
+                delta0@0 {
                         compatible = "st,st-delta";
                         clock-names = "delta",
                                       "delta-st231",
diff --git a/arch/arm/boot/dts/stih418-b2199.dts b/arch/arm/boot/dts/stih418-b2199.dts
index 4e6d915c85ff..39b4db2e3507 100644
--- a/arch/arm/boot/dts/stih418-b2199.dts
+++ b/arch/arm/boot/dts/stih418-b2199.dts
@@ -15,10 +15,10 @@
 
         chosen {
                 bootargs = "console=ttyAS0,115200 clk_ignore_unused";
-                linux,stdout-path = &sbc_serial0;
+                stdout-path = &sbc_serial0;
         };
 
-        memory {
+        memory@40000000 {
                 device_type = "memory";
                 reg = <0x40000000 0xc0000000>;
         };
@@ -28,24 +28,24 @@
                 ethernet0 = &ethernet0;
         };
 
+        leds {
+                compatible = "gpio-leds";
+                red {
+                        label = "Front Panel LED";
+                        gpios = <&pio4 1 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "heartbeat";
+                };
+                green {
+                        gpios = <&pio1 3 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+        };
+
         soc {
                 sbc_serial0: serial@9530000 {
                         status = "okay";
                 };
 
-                leds {
-                        compatible = "gpio-leds";
-                        red {
-                                label = "Front Panel LED";
-                                gpios = <&pio4 1 GPIO_ACTIVE_HIGH>;
-                                linux,default-trigger = "heartbeat";
-                        };
-                        green {
-                                gpios = <&pio1 3 GPIO_ACTIVE_HIGH>;
-                                default-state = "off";
-                        };
-                };
-
                 i2c@9842000 {
                         status = "okay";
                 };
@@ -88,7 +88,7 @@
                         non-removable;
                 };
 
-                miphy28lp_phy: miphy28lp@9b22000 {
+                miphy28lp_phy: miphy28lp@0 {
 
                         phy_port0: port@9b22000 {
                                 st,osc-rdy;
diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih418-clock.dtsi
index 9a157c1a99b1..13fb8db52fc1 100644
--- a/arch/arm/boot/dts/stih418-clock.dtsi
+++ b/arch/arm/boot/dts/stih418-clock.dtsi
@@ -7,6 +7,22 @@
  */
 #include <dt-bindings/clock/stih418-clks.h>
 / {
+        /*
+         * Fixed 30MHz oscillator inputs to SoC
+         */
+        clk_sysin: clk-sysin {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <30000000>;
+                clock-output-names = "CLK_SYSIN";
+        };
+
+        clk_tmdsout_hdmi: clk-tmdsout-hdmi {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
         clocks {
                 #address-cells = <1>;
                 #size-cells = <1>;
@@ -15,27 +31,6 @@
                 compatible = "st,stih418-clk", "simple-bus";
 
                 /*
-                 * Fixed 30MHz oscillator inputs to SoC
-                 */
-                clk_sysin: clk-sysin {
-                        #clock-cells = <0>;
-                        compatible = "fixed-clock";
-                        clock-frequency = <30000000>;
-                        clock-output-names = "CLK_SYSIN";
-                };
-
-                /*
-                 * ARM Peripheral clock for timers
-                 */
-                arm_periph_clk: clk-m-a9-periphs {
-                        #clock-cells = <0>;
-                        compatible = "fixed-factor-clock";
-                        clocks = <&clk_m_a9>;
-                        clock-div = <2>;
-                        clock-mult = <1>;
-                };
-
-                /*
                  * A9 PLL.
                  */
                 clockgen-a9@92b0000 {
@@ -64,32 +59,17 @@
                                  <&clockgen_a9_pll 0>,
                                  <&clk_s_c0_flexgen 13>,
                                  <&clk_m_a9_ext2f_div2>;
-                };
-
-                /*
-                 * ARM Peripheral clock for timers
-                 */
-                clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
-                        #clock-cells = <0>;
-                        compatible = "fixed-factor-clock";
-
-                        clocks = <&clk_s_c0_flexgen 13>;
 
-                        clock-output-names = "clk-m-a9-ext2f-div2";
-
-                        clock-div = <2>;
-                        clock-mult = <1>;
-                };
-
-                /*
-                 * Bootloader initialized system infrastructure clock for
-                 * serial devices.
-                 */
-                clk_ext2f_a9: clockgen-c0@13 {
-                        #clock-cells = <0>;
-                        compatible = "fixed-clock";
-                        clock-frequency = <200000000>;
-                        clock-output-names = "clk-s-icn-reg-0";
+                        /*
+                         * ARM Peripheral clock for timers
+                         */
+                        arm_periph_clk: clk-m-a9-periphs {
+                                #clock-cells = <0>;
+                                compatible = "fixed-factor-clock";
+                                clocks = <&clk_m_a9>;
+                                clock-div = <2>;
+                                clock-mult = <1>;
+                        };
                 };
 
                 clockgen-a@90ff000 {
@@ -207,6 +187,21 @@
                                                      "clk-proc-mixer",
                                                      "clk-proc-sc",
                                                      "clk-avsp-hevc";
+
+                                /*
+                                 * ARM Peripheral clock for timers
+                                 */
+                                clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
+                                        #clock-cells = <0>;
+                                        compatible = "fixed-factor-clock";
+
+                                        clocks = <&clk_s_c0_flexgen 13>;
+
+                                        clock-output-names = "clk-m-a9-ext2f-div2";
+
+                                        clock-div = <2>;
+                                        clock-mult = <1>;
+                                };
                         };
                 };
 
@@ -259,13 +254,7 @@
                                              "clk-s-d2-fs0-ch3";
                 };
 
-                clk_tmdsout_hdmi: clk-tmdsout-hdmi {
-                        #clock-cells = <0>;
-                        compatible = "fixed-clock";
-                        clock-frequency = <0>;
-                };
-
-                clockgen-d2@x9106000 {
+                clockgen-d2@9106000 {
                         compatible = "st,clkgen-c32";
                         reg = <0x9106000 0x1000>;
 
diff --git a/arch/arm/boot/dts/stih418.dtsi b/arch/arm/boot/dts/stih418.dtsi
index e6525ab4d9bb..0efb3cd6a86e 100644
--- a/arch/arm/boot/dts/stih418.dtsi
+++ b/arch/arm/boot/dts/stih418.dtsi
@@ -30,8 +30,9 @@
         };
 
         soc {
-                usb2_picophy1: phy2 {
+                usb2_picophy1: phy2@0 {
                         compatible = "st,stih407-usb2-phy";
+                        reg = <0 0>;
                         #phy-cells = <0>;
                         st,syscfg = <&syscfg_core 0xf8 0xf4>;
                         resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
@@ -39,8 +40,9 @@
                         reset-names = "global", "port";
                 };
 
-                usb2_picophy2: phy3 {
+                usb2_picophy2: phy3@0 {
                         compatible = "st,stih407-usb2-phy";
+                        reg = <0 0>;
                         #phy-cells = <0>;
                         st,syscfg = <&syscfg_core 0xfc 0xf4>;
                         resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi
index 7f80c2c414c8..c67edb1a8121 100644
--- a/arch/arm/boot/dts/stihxxx-b2120.dtsi
+++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi
@@ -10,23 +10,69 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/media/c8sectpfe.h>
 / {
-        soc {
-                sbc_serial0: serial@9530000 {
-                        status = "okay";
+        leds {
+                compatible = "gpio-leds";
+                red {
+                        label = "Front Panel LED";
+                        gpios = <&pio4 1 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "heartbeat";
+                };
+                green {
+                        gpios = <&pio1 3 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                };
+        };
+
+        sound: sound {
+                compatible = "simple-audio-card";
+                simple-audio-card,name = "STI-B2120";
+                status = "okay";
+
+                simple-audio-card,dai-link0 {
+                        /* HDMI */
+                        format = "i2s";
+                        mclk-fs = <128>;
+                        cpu {
+                                sound-dai = <&sti_uni_player0>;
+                        };
+
+                        codec {
+                                sound-dai = <&sti_hdmi>;
+                        };
+                };
+
+                simple-audio-card,dai-link1 {
+                        /* DAC */
+                        format = "i2s";
+                        mclk-fs = <256>;
+                        frame-inversion = <1>;
+                        cpu {
+                                sound-dai = <&sti_uni_player2>;
+                        };
+
+                        codec {
+                                sound-dai = <&sti_sasg_codec 1>;
+                        };
                 };
 
-                leds {
-                        compatible = "gpio-leds";
-                        red {
-                                label = "Front Panel LED";
-                                gpios = <&pio4 1 GPIO_ACTIVE_HIGH>;
-                                linux,default-trigger = "heartbeat";
+                simple-audio-card,dai-link2 {
+                        /* SPDIF */
+                        format = "left_j";
+                        mclk-fs = <128>;
+                        cpu {
+                                sound-dai = <&sti_uni_player3>;
                         };
-                        green {
-                                gpios = <&pio1 3 GPIO_ACTIVE_HIGH>;
-                                default-state = "off";
+
+                        codec {
+                                sound-dai = <&sti_sasg_codec 0>;
                         };
                 };
+        };
+
+        soc {
+                sbc_serial0: serial@9530000 {
+                        status = "okay";
+                };
 
                 pwm0: pwm@9810000 {
                         status = "okay";
@@ -80,7 +126,7 @@
                         st,i2c-min-sda-pulse-width-us = <5>;
                 };
 
-                miphy28lp_phy: miphy28lp@9b22000 {
+                miphy28lp_phy: miphy28lp@0 {
 
                         phy_port0: port@9b22000 {
                                 st,osc-rdy;
@@ -126,7 +172,7 @@
                         clock-names     = "c8sectpfe";
 
                         /* tsin0 is TSA on NIMA */
-                        tsin0: port@0 {
+                        tsin0: port {
                                 tsin-num        = <0>;
                                 serial-not-parallel;
                                 i2c-bus         = <&ssc2>;
@@ -147,53 +193,11 @@
                         status = "okay";
                 };
 
-                sti_sasg_codec: sti-sasg-codec {
-                        status = "okay";
-                        pinctrl-names = "default";
-                        pinctrl-0 = <&pinctrl_spdif_out>;
-                };
-
-                sound {
-                        compatible = "simple-audio-card";
-                        simple-audio-card,name = "STI-B2120";
-                        status = "okay";
-
-                        simple-audio-card,dai-link@0 {
-                                /* HDMI */
-                                format = "i2s";
-                                mclk-fs = <128>;
-                                cpu {
-                                        sound-dai = <&sti_uni_player0>;
-                                };
-
-                                codec {
-                                        sound-dai = <&sti_hdmi>;
-                                };
-                        };
-                        simple-audio-card,dai-link@1 {
-                                /* DAC */
-                                format = "i2s";
-                                mclk-fs = <256>;
-                                frame-inversion = <1>;
-                                cpu {
-                                        sound-dai = <&sti_uni_player2>;
-                                };
-
-                                codec {
-                                        sound-dai = <&sti_sasg_codec 1>;
-                                };
-                        };
-                        simple-audio-card,dai-link@2 {
-                                /* SPDIF */
-                                format = "left_j";
-                                mclk-fs = <128>;
-                                cpu {
-                                        sound-dai = <&sti_uni_player3>;
-                                };
-
-                                codec {
-                                        sound-dai = <&sti_sasg_codec 0>;
-                                };
+                syscfg_core: core-syscfg@92b0000 {
+                        sti_sasg_codec: sti-sasg-codec {
+                                status = "okay";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_spdif_out>;
                         };
                 };
         };
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts
index 293ecb957227..7eb786a2d624 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -144,6 +144,13 @@
                         };
                 };
         };
+
+        mmc_vcard: mmc_vcard {
+                compatible = "regulator-fixed";
+                regulator-name = "mmc_vcard";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
 };
 
 &adc {
@@ -254,6 +261,18 @@
         status = "okay";
 };
 
+&sdio {
+        status = "okay";
+        vmmc-supply = <&mmc_vcard>;
+        cd-gpios = <&stmpegpio 15 GPIO_ACTIVE_HIGH>;
+        cd-inverted;
+        pinctrl-names = "default", "opendrain";
+        pinctrl-0 = <&sdio_pins>;
+        pinctrl-1 = <&sdio_pins_od>;
+        bus-width = <4>;
+        max-frequency = <12500000>;
+};
+
 &timers1 {
         status = "okay";
 
diff --git a/arch/arm/boot/dts/stm32746g-eval.dts b/arch/arm/boot/dts/stm32746g-eval.dts
index 2d4e71717694..8c081eaf20fe 100644
--- a/arch/arm/boot/dts/stm32746g-eval.dts
+++ b/arch/arm/boot/dts/stm32746g-eval.dts
@@ -42,6 +42,7 @@
 
 /dts-v1/;
 #include "stm32f746.dtsi"
+#include "stm32f746-pinctrl.dtsi"
 #include <dt-bindings/input/input.h>
 
 / {
@@ -90,6 +91,13 @@
                 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
                 clock-names = "main_clk";
         };
+
+        mmc_vcard: mmc_vcard {
+                compatible = "regulator-fixed";
+                regulator-name = "mmc_vcard";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
 };
 
 &clk_hse {
@@ -112,6 +120,16 @@
         status = "okay";
 };
 
+&sdio1 {
+        status = "okay";
+        vmmc-supply = <&mmc_vcard>;
+        broken-cd;
+        pinctrl-names = "default", "opendrain";
+        pinctrl-0 = <&sdio_pins_a>;
+        pinctrl-1 = <&sdio_pins_od_a>;
+        bus-width = <4>;
+};
+
 &usart1 {
         pinctrl-0 = <&usart1_pins_a>;
         pinctrl-names = "default";
@@ -119,7 +137,7 @@
 };
 
 &usbotg_hs {
-        dr_mode = "host";
+        dr_mode = "otg";
         phys = <&usbotg_hs_phy>;
         phy-names = "usb2-phy";
         pinctrl-0 = <&usbotg_hs_pins_a>;
diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
index ae94d86c53c4..35202896c093 100644
--- a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
@@ -338,6 +338,37 @@
                                         slew-rate = <3>;
                                 };
                         };
+
+                        sdio_pins: sdio_pins@0 {
+                                pins {
+                                        pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
+                                                 <STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
+                                                 <STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */
+                                                 <STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */
+                                                 <STM32_PINMUX('C', 12, AF12)>, /* SDIO_CK */
+                                                 <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */
+                                        drive-push-pull;
+                                        slew-rate = <2>;
+                                };
+                        };
+
+                        sdio_pins_od: sdio_pins_od@0 {
+                                pins1 {
+                                        pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
+                                                 <STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
+                                                 <STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */
+                                                 <STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */
+                                                 <STM32_PINMUX('C', 12, AF12)>; /* SDIO_CK */
+                                        drive-push-pull;
+                                        slew-rate = <2>;
+                                };
+
+                                pins2 {
+                                        pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */
+                                        drive-open-drain;
+                                        slew-rate = <2>;
+                                };
+                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 10099df8b73e..ede77e0f1c41 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -511,6 +511,17 @@
                         };
                 };
 
+                sdio: sdio@40012c00 {
+                        compatible = "arm,pl180", "arm,primecell";
+                        arm,primecell-periphid = <0x00880180>;
+                        reg = <0x40012c00 0x400>;
+                        clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
+                        clock-names = "apb_pclk";
+                        interrupts = <49>;
+                        max-frequency = <48000000>;
+                        status = "disabled";
+                };
+
                 syscfg: system-config@40013800 {
                         compatible = "syscon";
                         reg = <0x40013800 0x400>;
diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts
index c18acbe4cf4e..2f76726bf335 100644
--- a/arch/arm/boot/dts/stm32f469-disco.dts
+++ b/arch/arm/boot/dts/stm32f469-disco.dts
@@ -48,6 +48,8 @@
 /dts-v1/;
 #include "stm32f429.dtsi"
 #include "stm32f469-pinctrl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
 
 / {
         model = "STMicroelectronics STM32F469i-DISCO board";
@@ -66,10 +68,46 @@
                 serial0 = &usart3;
         };
 
+        mmc_vcard: mmc_vcard {
+                compatible = "regulator-fixed";
+                regulator-name = "mmc_vcard";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
+
         soc {
                 dma-ranges = <0xc0000000 0x0 0x10000000>;
         };
 
+        leds {
+                compatible = "gpio-leds";
+                green {
+                        gpios = <&gpiog 6 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "heartbeat";
+                };
+                orange {
+                        gpios = <&gpiod 4 GPIO_ACTIVE_LOW>;
+                };
+                red {
+                        gpios = <&gpiod 5 GPIO_ACTIVE_LOW>;
+                };
+                blue {
+                        gpios = <&gpiok 3 GPIO_ACTIVE_LOW>;
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                autorepeat;
+                button@0 {
+                        label = "User";
+                        linux,code = <KEY_WAKEUP>;
+                        gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
+                };
+        };
+
         /* This turns on vbus for otg for host mode (dwc2) */
         vcc5v_otg: vcc5v-otg-regulator {
                 compatible = "regulator-fixed";
@@ -120,6 +158,18 @@
         };
 };
 
+&sdio {
+        status = "okay";
+        vmmc-supply = <&mmc_vcard>;
+        cd-gpios = <&gpiog 2 GPIO_ACTIVE_HIGH>;
+        cd-inverted;
+        broken-cd;
+        pinctrl-names = "default", "opendrain";
+        pinctrl-0 = <&sdio_pins>;
+        pinctrl-1 = <&sdio_pins_od>;
+        bus-width = <4>;
+};
+
 &usart3 {
         pinctrl-0 = <&usart3_pins_a>;
         pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi
new file mode 100644
index 000000000000..9314128df185
--- /dev/null
+++ b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi
@@ -0,0 +1,289 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Alexandre Torgue  <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+#include <dt-bindings/pinctrl/stm32-pinfunc.h>
+#include <dt-bindings/mfd/stm32f7-rcc.h>
+
+/ {
+        soc {
+                pinctrl: pin-controller {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x40020000 0x3000>;
+                        interrupt-parent = <&exti>;
+                        st,syscfg = <&syscfg 0x8>;
+                        pins-are-numbered;
+
+                        gpioa: gpio@40020000 {
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x0 0x400>;
+                                clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
+                                st,bank-name = "GPIOA";
+                        };
+
+                        gpiob: gpio@40020400 {
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x400 0x400>;
+                                clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
+                                st,bank-name = "GPIOB";
+                        };
+
+                        gpioc: gpio@40020800 {
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x800 0x400>;
+                                clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
+                                st,bank-name = "GPIOC";
+                        };
+
+                        gpiod: gpio@40020c00 {
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0xc00 0x400>;
+                                clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
+                                st,bank-name = "GPIOD";
+                        };
+
+                        gpioe: gpio@40021000 {
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x1000 0x400>;
+                                clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
+                                st,bank-name = "GPIOE";
+                        };
+
+                        gpiof: gpio@40021400 {
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x1400 0x400>;
+                                clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
+                                st,bank-name = "GPIOF";
+                        };
+
+                        gpiog: gpio@40021800 {
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x1800 0x400>;
+                                clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
+                                st,bank-name = "GPIOG";
+                        };
+
+                        gpioh: gpio@40021c00 {
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x1c00 0x400>;
+                                clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
+                                st,bank-name = "GPIOH";
+                        };
+
+                        gpioi: gpio@40022000 {
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x2000 0x400>;
+                                clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
+                                st,bank-name = "GPIOI";
+                        };
+
+                        gpioj: gpio@40022400 {
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x2400 0x400>;
+                                clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
+                                st,bank-name = "GPIOJ";
+                        };
+
+                        gpiok: gpio@40022800 {
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x2800 0x400>;
+                                clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
+                                st,bank-name = "GPIOK";
+                        };
+
+                        cec_pins_a: cec@0 {
+                                pins {
+                                        pinmux = <STM32_PINMUX('A', 15, AF4)>; /* HDMI CEC */
+                                        slew-rate = <0>;
+                                        drive-open-drain;
+                                        bias-disable;
+                                };
+                        };
+
+                        usart1_pins_a: usart1@0 {
+                                pins1 {
+                                        pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
+                                        bias-disable;
+                                        drive-push-pull;
+                                        slew-rate = <0>;
+                                };
+                                pins2 {
+                                        pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
+                                        bias-disable;
+                                };
+                        };
+
+                        usart1_pins_b: usart1@1 {
+                                pins1 {
+                                        pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
+                                        bias-disable;
+                                        drive-push-pull;
+                                        slew-rate = <0>;
+                                };
+                                pins2 {
+                                        pinmux = <STM32_PINMUX('B', 7, AF7)>; /* USART1_RX */
+                                        bias-disable;
+                                };
+                        };
+
+                        i2c1_pins_b: i2c1@0 {
+                                pins {
+                                        pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1 SDA */
+                                                 <STM32_PINMUX('B', 8, AF4)>; /* I2C1 SCL */
+                                        bias-disable;
+                                        drive-open-drain;
+                                        slew-rate = <0>;
+                                };
+                        };
+
+                        usbotg_hs_pins_a: usbotg-hs@0 {
+                                pins {
+                                        pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
+                                                 <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
+                                                 <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
+                                                 <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
+                                                 <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
+                                                 <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
+                                                 <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
+                                                 <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
+                                                 <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
+                                                 <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
+                                                 <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
+                                                 <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
+                                        bias-disable;
+                                        drive-push-pull;
+                                        slew-rate = <2>;
+                                };
+                        };
+
+                        usbotg_hs_pins_b: usbotg-hs@1 {
+                                pins {
+                                        pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
+                                                 <STM32_PINMUX('C', 2, AF10)>, /* OTG_HS_ULPI_DIR */
+                                                 <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
+                                                 <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
+                                                 <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
+                                                 <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
+                                                 <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
+                                                 <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
+                                                 <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
+                                                 <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
+                                                 <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
+                                                 <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
+                                        bias-disable;
+                                        drive-push-pull;
+                                        slew-rate = <2>;
+                                };
+                        };
+
+                        usbotg_fs_pins_a: usbotg-fs@0 {
+                                pins {
+                                        pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
+                                                 <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
+                                                 <STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
+                                        bias-disable;
+                                        drive-push-pull;
+                                        slew-rate = <2>;
+                                };
+                        };
+
+                        sdio_pins_a: sdio_pins_a@0 {
+                                pins {
+                                        pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
+                                                 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
+                                                 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
+                                                 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
+                                                 <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1 CLK */
+                                                 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
+                                        drive-push-pull;
+                                        slew-rate = <2>;
+                                };
+                        };
+
+                        sdio_pins_od_a: sdio_pins_od_a@0 {
+                                pins1 {
+                                        pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
+                                                 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
+                                                 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
+                                                 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
+                                                 <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1 CLK */
+                                        drive-push-pull;
+                                        slew-rate = <2>;
+                                };
+
+                                pins2 {
+                                        pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
+                                        drive-open-drain;
+                                        slew-rate = <2>;
+                                };
+                        };
+
+                        sdio_pins_b: sdio_pins_b@0 {
+                                pins {
+                                        pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
+                                                 <STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
+                                                 <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */
+                                                 <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */
+                                                 <STM32_PINMUX('D', 6, AF11)>, /* SDMMC2 CLK */
+                                                 <STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
+                                        drive-push-pull;
+                                        slew-rate = <2>;
+                                };
+                        };
+
+                        sdio_pins_od_b: sdio_pins_od_b@0 {
+                                pins1 {
+                                        pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
+                                                 <STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
+                                                 <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */
+                                                 <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */
+                                                 <STM32_PINMUX('D', 6, AF11)>; /* SDMMC2 CLK */
+                                        drive-push-pull;
+                                        slew-rate = <2>;
+                                };
+
+                                pins2 {
+                                        pinmux = <STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
+                                        drive-open-drain;
+                                        slew-rate = <2>;
+                                };
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/stm32f746-disco.dts b/arch/arm/boot/dts/stm32f746-disco.dts
index 4d85dba59e1d..be94c6ad7e94 100644
--- a/arch/arm/boot/dts/stm32f746-disco.dts
+++ b/arch/arm/boot/dts/stm32f746-disco.dts
@@ -42,7 +42,9 @@
 
 /dts-v1/;
 #include "stm32f746.dtsi"
+#include "stm32f746-pinctrl.dtsi"
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
 
 / {
         model = "STMicroelectronics STM32F746-DISCO board";
@@ -75,12 +77,30 @@
                 regulator-name = "vcc5_host1";
                 regulator-always-on;
         };
+
+        mmc_vcard: mmc_vcard {
+                compatible = "regulator-fixed";
+                regulator-name = "mmc_vcard";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
 };
 
 &clk_hse {
         clock-frequency = <25000000>;
 };
 
+&sdio1 {
+        status = "okay";
+        vmmc-supply = <&mmc_vcard>;
+        cd-gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
+        cd-inverted;
+        pinctrl-names = "default", "opendrain";
+        pinctrl-0 = <&sdio_pins_a>;
+        pinctrl-1 = <&sdio_pins_od_a>;
+        bus-width = <4>;
+};
+
 &usart1 {
         pinctrl-0 = <&usart1_pins_b>;
         pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/stm32f746-pinctrl.dtsi b/arch/arm/boot/dts/stm32f746-pinctrl.dtsi
new file mode 100644
index 000000000000..fcfd2ac7239b
--- /dev/null
+++ b/arch/arm/boot/dts/stm32f746-pinctrl.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Alexandre Torgue  <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+#include "stm32f7-pinctrl.dtsi"
+
+&pinctrl{
+        compatible = "st,stm32f746-pinctrl";
+};
diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi
index 5f66d151eedb..4be2ee575b19 100644
--- a/arch/arm/boot/dts/stm32f746.dtsi
+++ b/arch/arm/boot/dts/stm32f746.dtsi
@@ -42,7 +42,6 @@
 
 #include "skeleton.dtsi"
 #include "armv7-m.dtsi"
-#include <dt-bindings/pinctrl/stm32-pinfunc.h>
 #include <dt-bindings/clock/stm32fx-clock.h>
 #include <dt-bindings/mfd/stm32f7-rcc.h>
 
@@ -429,6 +428,28 @@
                         status = "disabled";
                 };
 
+                sdio2: sdio2@40011c00 {
+                        compatible = "arm,pl180", "arm,primecell";
+                        arm,primecell-periphid = <0x00880180>;
+                        reg = <0x40011c00 0x400>;
+                        clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
+                        clock-names = "apb_pclk";
+                        interrupts = <103>;
+                        max-frequency = <48000000>;
+                        status = "disabled";
+                };
+
+                sdio1: sdio1@40012c00 {
+                        compatible = "arm,pl180", "arm,primecell";
+                        arm,primecell-periphid = <0x00880180>;
+                        reg = <0x40012c00 0x400>;
+                        clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
+                        clock-names = "apb_pclk";
+                        interrupts = <49>;
+                        max-frequency = <48000000>;
+                        status = "disabled";
+                };
+
                 syscfg: system-config@40013800 {
                         compatible = "syscon";
                         reg = <0x40013800 0x400>;
@@ -498,222 +519,6 @@
                         reg = <0x40007000 0x400>;
                 };
 
-                pin-controller {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "st,stm32f746-pinctrl";
-                        ranges = <0 0x40020000 0x3000>;
-                        interrupt-parent = <&exti>;
-                        st,syscfg = <&syscfg 0x8>;
-                        pins-are-numbered;
-
-                        gpioa: gpio@40020000 {
-                                gpio-controller;
-                                #gpio-cells = <2>;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                                reg = <0x0 0x400>;
-                                clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
-                                st,bank-name = "GPIOA";
-                        };
-
-                        gpiob: gpio@40020400 {
-                                gpio-controller;
-                                #gpio-cells = <2>;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                                reg = <0x400 0x400>;
-                                clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
-                                st,bank-name = "GPIOB";
-                        };
-
-                        gpioc: gpio@40020800 {
-                                gpio-controller;
-                                #gpio-cells = <2>;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                                reg = <0x800 0x400>;
-                                clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
-                                st,bank-name = "GPIOC";
-                        };
-
-                        gpiod: gpio@40020c00 {
-                                gpio-controller;
-                                #gpio-cells = <2>;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                                reg = <0xc00 0x400>;
-                                clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
-                                st,bank-name = "GPIOD";
-                        };
-
-                        gpioe: gpio@40021000 {
-                                gpio-controller;
-                                #gpio-cells = <2>;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                                reg = <0x1000 0x400>;
-                                clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
-                                st,bank-name = "GPIOE";
-                        };
-
-                        gpiof: gpio@40021400 {
-                                gpio-controller;
-                                #gpio-cells = <2>;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                                reg = <0x1400 0x400>;
-                                clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
-                                st,bank-name = "GPIOF";
-                        };
-
-                        gpiog: gpio@40021800 {
-                                gpio-controller;
-                                #gpio-cells = <2>;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                                reg = <0x1800 0x400>;
-                                clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
-                                st,bank-name = "GPIOG";
-                        };
-
-                        gpioh: gpio@40021c00 {
-                                gpio-controller;
-                                #gpio-cells = <2>;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                                reg = <0x1c00 0x400>;
-                                clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
-                                st,bank-name = "GPIOH";
-                        };
-
-                        gpioi: gpio@40022000 {
-                                gpio-controller;
-                                #gpio-cells = <2>;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                                reg = <0x2000 0x400>;
-                                clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
-                                st,bank-name = "GPIOI";
-                        };
-
-                        gpioj: gpio@40022400 {
-                                gpio-controller;
-                                #gpio-cells = <2>;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                                reg = <0x2400 0x400>;
-                                clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
-                                st,bank-name = "GPIOJ";
-                        };
-
-                        gpiok: gpio@40022800 {
-                                gpio-controller;
-                                #gpio-cells = <2>;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                                reg = <0x2800 0x400>;
-                                clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
-                                st,bank-name = "GPIOK";
-                        };
-
-                        cec_pins_a: cec@0 {
-                                pins {
-                                        pinmux = <STM32_PINMUX('A', 15, AF4)>; /* HDMI CEC */
-                                        slew-rate = <0>;
-                                        drive-open-drain;
-                                        bias-disable;
-                                };
-                        };
-
-                        usart1_pins_a: usart1@0 {
-                                pins1 {
-                                        pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
-                                        bias-disable;
-                                        drive-push-pull;
-                                        slew-rate = <0>;
-                                };
-                                pins2 {
-                                        pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
-                                        bias-disable;
-                                };
-                        };
-
-                        usart1_pins_b: usart1@1 {
-                                pins1 {
-                                        pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
-                                        bias-disable;
-                                        drive-push-pull;
-                                        slew-rate = <0>;
-                                };
-                                pins2 {
-                                        pinmux = <STM32_PINMUX('B', 7, AF7)>; /* USART1_RX */
-                                        bias-disable;
-                                };
-                        };
-
-                        i2c1_pins_b: i2c1@0 {
-                                pins {
-                                        pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1 SDA */
-                                                 <STM32_PINMUX('B', 8, AF4)>; /* I2C1 SCL */
-                                        bias-disable;
-                                        drive-open-drain;
-                                        slew-rate = <0>;
-                                };
-                        };
-
-                        usbotg_hs_pins_a: usbotg-hs@0 {
-                                pins {
-                                        pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
-                                                 <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
-                                                 <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
-                                                 <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
-                                                 <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
-                                                 <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
-                                                 <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
-                                                 <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
-                                                 <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
-                                                 <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
-                                                 <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
-                                                 <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
-                                        bias-disable;
-                                        drive-push-pull;
-                                        slew-rate = <2>;
-                                };
-                        };
-
-                        usbotg_hs_pins_b: usbotg-hs@1 {
-                                pins {
-                                        pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
-                                                 <STM32_PINMUX('C', 2, AF10)>, /* OTG_HS_ULPI_DIR */
-                                                 <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
-                                                 <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
-                                                 <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
-                                                 <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
-                                                 <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
-                                                 <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
-                                                 <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
-                                                 <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
-                                                 <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
-                                                 <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
-                                        bias-disable;
-                                        drive-push-pull;
-                                        slew-rate = <2>;
-                                };
-                        };
-
-                        usbotg_fs_pins_a: usbotg-fs@0 {
-                                pins {
-                                        pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
-                                                 <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
-                                                 <STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
-                                        bias-disable;
-                                        drive-push-pull;
-                                        slew-rate = <2>;
-                                };
-                        };
-                };
-
                 crc: crc@40023000 {
                         compatible = "st,stm32f7-crc";
                         reg = <0x40023000 0x400>;
@@ -771,6 +576,9 @@
                         interrupts = <77>;
                         clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
                         clock-names = "otg";
+                        g-rx-fifo-size = <256>;
+                        g-np-tx-fifo-size = <32>;
+                        g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
                         status = "disabled";
                 };
 
diff --git a/arch/arm/boot/dts/stm32f769-disco.dts b/arch/arm/boot/dts/stm32f769-disco.dts
index 4463ca13a740..2241eecdabfe 100644
--- a/arch/arm/boot/dts/stm32f769-disco.dts
+++ b/arch/arm/boot/dts/stm32f769-disco.dts
@@ -42,11 +42,13 @@
 
 /dts-v1/;
 #include "stm32f746.dtsi"
+#include "stm32f769-pinctrl.dtsi"
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
 
 / {
         model = "STMicroelectronics STM32F769-DISCO board";
-        compatible = "st,stm32f769-disco", "st,stm32f7";
+        compatible = "st,stm32f769-disco", "st,stm32f769";
 
         chosen {
                 bootargs = "root=/dev/ram";
@@ -61,6 +63,42 @@
                 serial0 = &usart1;
         };
 
+        leds {
+                compatible = "gpio-leds";
+                green {
+                        gpios = <&gpioj 5 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "heartbeat";
+                };
+                red {
+                        gpios = <&gpioj 13 GPIO_ACTIVE_HIGH>;
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                autorepeat;
+                button@0 {
+                        label = "User";
+                        linux,code = <KEY_HOME>;
+                        gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
+                };
+        };
+
+        usbotg_hs_phy: usb-phy {
+                #phy-cells = <0>;
+                compatible = "usb-nop-xceiv";
+                clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
+                clock-names = "main_clk";
+        };
+
+        mmc_vcard: mmc_vcard {
+                compatible = "regulator-fixed";
+                regulator-name = "mmc_vcard";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
 };
 
 &cec {
@@ -73,8 +111,33 @@
         clock-frequency = <25000000>;
 };
 
+&rtc {
+        status = "okay";
+};
+
+&sdio2 {
+        status = "okay";
+        vmmc-supply = <&mmc_vcard>;
+        cd-gpios = <&gpioi 15 GPIO_ACTIVE_HIGH>;
+        cd-inverted;
+        broken-cd;
+        pinctrl-names = "default", "opendrain";
+        pinctrl-0 = <&sdio_pins_b>;
+        pinctrl-1 = <&sdio_pins_od_b>;
+        bus-width = <4>;
+};
+
 &usart1 {
         pinctrl-0 = <&usart1_pins_a>;
         pinctrl-names = "default";
         status = "okay";
 };
+
+&usbotg_hs {
+        dr_mode = "otg";
+        phys = <&usbotg_hs_phy>;
+        phy-names = "usb2-phy";
+        pinctrl-0 = <&usbotg_hs_pins_a>;
+        pinctrl-names = "default";
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/stm32f769-pinctrl.dtsi b/arch/arm/boot/dts/stm32f769-pinctrl.dtsi
new file mode 100644
index 000000000000..31005dd9929c
--- /dev/null
+++ b/arch/arm/boot/dts/stm32f769-pinctrl.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Alexandre Torgue  <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+#include "stm32f7-pinctrl.dtsi"
+
+&pinctrl{
+        compatible = "st,stm32f769-pinctrl";
+};
diff --git a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
index 65c1cd043987..0f15dfb98381 100644
--- a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
@@ -49,6 +49,8 @@
                         #size-cells = <1>;
                         compatible = "st,stm32h743-pinctrl";
                         ranges = <0 0x58020000 0x3000>;
+                        interrupt-parent = <&exti>;
+                        st,syscfg = <&syscfg 0x8>;
                         pins-are-numbered;
 
                         gpioa: gpio@58020000 {
@@ -57,6 +59,8 @@
                                 reg = <0x0 0x400>;
                                 clocks = <&rcc GPIOA_CK>;
                                 st,bank-name = "GPIOA";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                         };
 
                         gpiob: gpio@58020400 {
@@ -65,6 +69,8 @@
                                 reg = <0x400 0x400>;
                                 clocks = <&rcc GPIOB_CK>;
                                 st,bank-name = "GPIOB";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                         };
 
                         gpioc: gpio@58020800 {
@@ -73,6 +79,8 @@
                                 reg = <0x800 0x400>;
                                 clocks = <&rcc GPIOC_CK>;
                                 st,bank-name = "GPIOC";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                         };
 
                         gpiod: gpio@58020c00 {
@@ -81,6 +89,8 @@
                                 reg = <0xc00 0x400>;
                                 clocks = <&rcc GPIOD_CK>;
                                 st,bank-name = "GPIOD";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                         };
 
                         gpioe: gpio@58021000 {
@@ -89,6 +99,8 @@
                                 reg = <0x1000 0x400>;
                                 clocks = <&rcc GPIOE_CK>;
                                 st,bank-name = "GPIOE";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                         };
 
                         gpiof: gpio@58021400 {
@@ -97,6 +109,8 @@
                                 reg = <0x1400 0x400>;
                                 clocks = <&rcc GPIOF_CK>;
                                 st,bank-name = "GPIOF";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                         };
 
                         gpiog: gpio@58021800 {
@@ -105,6 +119,8 @@
                                 reg = <0x1800 0x400>;
                                 clocks = <&rcc GPIOG_CK>;
                                 st,bank-name = "GPIOG";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                         };
 
                         gpioh: gpio@58021c00 {
@@ -113,6 +129,8 @@
                                 reg = <0x1c00 0x400>;
                                 clocks = <&rcc GPIOH_CK>;
                                 st,bank-name = "GPIOH";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                         };
 
                         gpioi: gpio@58022000 {
@@ -121,6 +139,8 @@
                                 reg = <0x2000 0x400>;
                                 clocks = <&rcc GPIOI_CK>;
                                 st,bank-name = "GPIOI";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                         };
 
                         gpioj: gpio@58022400 {
@@ -129,6 +149,8 @@
                                 reg = <0x2400 0x400>;
                                 clocks = <&rcc GPIOJ_CK>;
                                 st,bank-name = "GPIOJ";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                         };
 
                         gpiok: gpio@58022800 {
@@ -137,6 +159,8 @@
                                 reg = <0x2800 0x400>;
                                 clocks = <&rcc GPIOK_CK>;
                                 st,bank-name = "GPIOK";
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
                         };
 
                         usart1_pins: usart1@0 {
@@ -164,6 +188,26 @@
                                         bias-disable;
                                 };
                         };
+
+                        usbotg_hs_pins_a: usbotg-hs@0 {
+                                pins {
+                                        pinmux = <STM32_PINMUX('H', 4, AF10)>,  /* ULPI_NXT */
+                                                         <STM32_PINMUX('I', 11, AF10)>, /* ULPI_DIR> */
+                                                         <STM32_PINMUX('C', 0, AF10)>,  /* ULPI_STP> */
+                                                         <STM32_PINMUX('A', 5, AF10)>,  /* ULPI_CK> */
+                                                         <STM32_PINMUX('A', 3, AF10)>,  /* ULPI_D0> */
+                                                         <STM32_PINMUX('B', 0, AF10)>,  /* ULPI_D1> */
+                                                         <STM32_PINMUX('B', 1, AF10)>,  /* ULPI_D2> */
+                                                         <STM32_PINMUX('B', 10, AF10)>, /* ULPI_D3> */
+                                                         <STM32_PINMUX('B', 11, AF10)>, /* ULPI_D4> */
+                                                         <STM32_PINMUX('B', 12, AF10)>, /* ULPI_D5> */
+                                                         <STM32_PINMUX('B', 13, AF10)>, /* ULPI_D6> */
+                                                         <STM32_PINMUX('B', 5, AF10)>;  /* ULPI_D7> */
+                                        bias-disable;
+                                        drive-push-pull;
+                                        slew-rate = <2>;
+                                };
+                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi
index bbfcbaca0b36..2bb103e1194d 100644
--- a/arch/arm/boot/dts/stm32h743.dtsi
+++ b/arch/arm/boot/dts/stm32h743.dtsi
@@ -44,6 +44,7 @@
 #include "armv7-m.dtsi"
 #include <dt-bindings/clock/stm32h7-clks.h>
 #include <dt-bindings/mfd/stm32h7-rcc.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
         clocks {
@@ -100,6 +101,27 @@
                         };
                 };
 
+                spi2: spi@40003800 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "st,stm32h7-spi";
+                        reg = <0x40003800 0x400>;
+                        interrupts = <36>;
+                        clocks = <&rcc SPI2_CK>;
+                        status = "disabled";
+
+                };
+
+                spi3: spi@40003c00 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "st,stm32h7-spi";
+                        reg = <0x40003c00 0x400>;
+                        interrupts = <51>;
+                        clocks = <&rcc SPI3_CK>;
+                        status = "disabled";
+                };
+
                 usart2: serial@40004400 {
                         compatible = "st,stm32f7-uart";
                         reg = <0x40004400 0x400>;
@@ -140,6 +162,36 @@
                         clocks = <&rcc USART1_CK>;
                 };
 
+                spi1: spi@40013000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "st,stm32h7-spi";
+                        reg = <0x40013000 0x400>;
+                        interrupts = <35>;
+                        clocks = <&rcc SPI1_CK>;
+                        status = "disabled";
+                };
+
+                spi4: spi@40013400 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "st,stm32h7-spi";
+                        reg = <0x40013400 0x400>;
+                        interrupts = <84>;
+                        clocks = <&rcc SPI4_CK>;
+                        status = "disabled";
+                };
+
+                spi5: spi@40015000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "st,stm32h7-spi";
+                        reg = <0x40015000 0x400>;
+                        interrupts = <85>;
+                        clocks = <&rcc SPI5_CK>;
+                        status = "disabled";
+                };
+
                 dma1: dma@40020000 {
                         compatible = "st,stm32-dma";
                         reg = <0x40020000 0x400>;
@@ -217,6 +269,27 @@
                         };
                 };
 
+                usbotg_hs: usb@40040000 {
+                        compatible = "st,stm32f7-hsotg";
+                        reg = <0x40040000 0x40000>;
+                        interrupts = <77>;
+                        clocks = <&rcc USB1OTG_CK>;
+                        clock-names = "otg";
+                        g-rx-fifo-size = <256>;
+                        g-np-tx-fifo-size = <32>;
+                        g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
+                        status = "disabled";
+                };
+
+                usbotg_fs: usb@40080000 {
+                        compatible = "st,stm32f4x9-fsotg";
+                        reg = <0x40080000 0x40000>;
+                        interrupts = <101>;
+                        clocks = <&rcc USB2OTG_CK>;
+                        clock-names = "otg";
+                        status = "disabled";
+                };
+
                 mdma1: dma@52000000 {
                         compatible = "st,stm32h7-mdma";
                         reg = <0x52000000 0x1000>;
@@ -227,6 +300,29 @@
                         dma-requests = <32>;
                 };
 
+                exti: interrupt-controller@58000000 {
+                        compatible = "st,stm32h7-exti";
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        reg = <0x58000000 0x400>;
+                        interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <62>, <76>;
+                };
+
+                syscfg: system-config@58000400 {
+                        compatible = "syscon";
+                        reg = <0x58000400 0x400>;
+                };
+
+                spi6: spi@58001400 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "st,stm32h7-spi";
+                        reg = <0x58001400 0x400>;
+                        interrupts = <86>;
+                        clocks = <&rcc SPI6_CK>;
+                        status = "disabled";
+                };
+
                 lptimer2: timer@58002400 {
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -304,7 +400,7 @@
                         };
                 };
 
-                vrefbuf: regulator@58003C00 {
+                vrefbuf: regulator@58003c00 {
                         compatible = "st,stm32-vrefbuf";
                         reg = <0x58003C00 0x8>;
                         clocks = <&rcc VREF_CK>;
@@ -313,6 +409,20 @@
                         status = "disabled";
                 };
 
+                rtc: rtc@58004000 {
+                        compatible = "st,stm32h7-rtc";
+                        reg = <0x58004000 0x400>;
+                        clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>;
+                        clock-names = "pclk", "rtc_ck";
+                        assigned-clocks = <&rcc RTC_CK>;
+                        assigned-clock-parents = <&rcc LSE_CK>;
+                        interrupt-parent = <&exti>;
+                        interrupts = <17 IRQ_TYPE_EDGE_RISING>;
+                        interrupt-names = "alarm";
+                        st,syscfg = <&pwrcfg>;
+                        status = "disabled";
+                };
+
                 rcc: reset-clock-controller@58024400 {
                         compatible = "st,stm32h743-rcc", "st,stm32-rcc";
                         reg = <0x58024400 0x400>;
diff --git a/arch/arm/boot/dts/stm32h743i-disco.dts b/arch/arm/boot/dts/stm32h743i-disco.dts
index 79e841d94079..45e088c55741 100644
--- a/arch/arm/boot/dts/stm32h743i-disco.dts
+++ b/arch/arm/boot/dts/stm32h743i-disco.dts
@@ -63,7 +63,7 @@
 };
 
 &clk_hse {
-        clock-frequency = <125000000>;
+        clock-frequency = <25000000>;
 };
 
 &usart2 {
diff --git a/arch/arm/boot/dts/stm32h743i-eval.dts b/arch/arm/boot/dts/stm32h743i-eval.dts
index 9f0e72c67219..c7187e18ea16 100644
--- a/arch/arm/boot/dts/stm32h743i-eval.dts
+++ b/arch/arm/boot/dts/stm32h743i-eval.dts
@@ -68,6 +68,14 @@
                 regulator-max-microvolt = <3300000>;
                 regulator-always-on;
         };
+
+        usbotg_hs_phy: usb-phy {
+                #phy-cells = <0>;
+                compatible = "usb-nop-xceiv";
+                clocks = <&rcc USB1ULPI_CK>;
+                clock-names = "main_clk";
+        };
+
 };
 
 &adc_12 {
@@ -84,9 +92,21 @@
         clock-frequency = <25000000>;
 };
 
+&rtc {
+        status = "okay";
+};
+
 &usart1 {
         pinctrl-0 = <&usart1_pins>;
         pinctrl-names = "default";
         status = "okay";
 };
 
+&usbotg_hs {
+        pinctrl-0 = <&usbotg_hs_pins_a>;
+        pinctrl-names = "default";
+        phys = <&usbotg_hs_phy>;
+        phy-names = "usb2-phy";
+        dr_mode = "otg";
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
new file mode 100644
index 000000000000..c0743305f31b
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
@@ -0,0 +1,185 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
+ */
+#include <dt-bindings/pinctrl/stm32-pinfunc.h>
+
+/ {
+        soc {
+                pinctrl: pin-controller {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "st,stm32mp157-pinctrl";
+                        ranges = <0 0x50002000 0xa400>;
+                        pins-are-numbered;
+
+                        gpioa: gpio@50002000 {
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x0 0x400>;
+                                clocks = <&clk_pll3_p>;
+                                st,bank-name = "GPIOA";
+                                ngpios = <16>;
+                                gpio-ranges = <&pinctrl 0 0 16>;
+                        };
+
+                        gpiob: gpio@50003000 {
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x1000 0x400>;
+                                clocks = <&clk_pll3_p>;
+                                st,bank-name = "GPIOB";
+                                ngpios = <16>;
+                                gpio-ranges = <&pinctrl 0 16 16>;
+                        };
+
+                        gpioc: gpio@50004000 {
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x2000 0x400>;
+                                clocks = <&clk_pll3_p>;
+                                st,bank-name = "GPIOC";
+                                ngpios = <16>;
+                                gpio-ranges = <&pinctrl 0 32 16>;
+                        };
+
+                        gpiod: gpio@50005000 {
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x3000 0x400>;
+                                clocks = <&clk_pll3_p>;
+                                st,bank-name = "GPIOD";
+                                ngpios = <16>;
+                                gpio-ranges = <&pinctrl 0 48 16>;
+                        };
+
+                        gpioe: gpio@50006000 {
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x4000 0x400>;
+                                clocks = <&clk_pll3_p>;
+                                st,bank-name = "GPIOE";
+                                ngpios = <16>;
+                                gpio-ranges = <&pinctrl 0 64 16>;
+                        };
+
+                        gpiof: gpio@50007000 {
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x5000 0x400>;
+                                clocks = <&clk_pll3_p>;
+                                st,bank-name = "GPIOF";
+                                ngpios = <16>;
+                                gpio-ranges = <&pinctrl 0 80 16>;
+                        };
+
+                        gpiog: gpio@50008000 {
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x6000 0x400>;
+                                clocks = <&clk_pll3_p>;
+                                st,bank-name = "GPIOG";
+                                ngpios = <16>;
+                                gpio-ranges = <&pinctrl 0 96 16>;
+                        };
+
+                        gpioh: gpio@50009000 {
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x7000 0x400>;
+                                clocks = <&clk_pll3_p>;
+                                st,bank-name = "GPIOH";
+                                ngpios = <16>;
+                                gpio-ranges = <&pinctrl 0 112 16>;
+                        };
+
+                        gpioi: gpio@5000a000 {
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x8000 0x400>;
+                                clocks = <&clk_pll3_p>;
+                                st,bank-name = "GPIOI";
+                                ngpios = <16>;
+                                gpio-ranges = <&pinctrl 0 128 16>;
+                        };
+
+                        gpioj: gpio@5000b000 {
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x9000 0x400>;
+                                clocks = <&clk_pll3_p>;
+                                st,bank-name = "GPIOJ";
+                                ngpios = <16>;
+                                gpio-ranges = <&pinctrl 0 144 16>;
+                        };
+
+                        gpiok: gpio@5000c000 {
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0xa000 0x400>;
+                                clocks = <&clk_pll3_p>;
+                                st,bank-name = "GPIOK";
+                                ngpios = <8>;
+                                gpio-ranges = <&pinctrl 0 160 8>;
+                        };
+
+                        uart4_pins_a: uart4@0 {
+                                pins1 {
+                                        pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
+                                        bias-disable;
+                                        drive-push-pull;
+                                        slew-rate = <0>;
+                                };
+                                pins2 {
+                                        pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
+                                        bias-disable;
+                                };
+                        };
+                };
+
+                pinctrl_z: pin-controller-z {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "st,stm32mp157-z-pinctrl";
+                        ranges = <0 0x54004000 0x400>;
+                        pins-are-numbered;
+                        status = "disabled";
+
+                        gpioz: gpio@54004000 {
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0 0x400>;
+                                clocks = <&clk_pll2_p>;
+                                st,bank-name = "GPIOZ";
+                                st,bank-ioport = <11>;
+                                ngpios = <8>;
+                                gpio-ranges = <&pinctrl_z 0 400 8>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts
new file mode 100644
index 000000000000..9f90337a22e3
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
+ */
+/dts-v1/;
+
+#include "stm32mp157c.dtsi"
+#include "stm32mp157-pinctrl.dtsi"
+
+/ {
+        model = "STMicroelectronics STM32MP157C eval daughter";
+        compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+
+        memory {
+                reg = <0xC0000000 0x40000000>;
+        };
+
+        aliases {
+                serial0 = &uart4;
+        };
+};
+
+&uart4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart4_pins_a>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts
new file mode 100644
index 000000000000..57e6dbc52e09
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
+ */
+/dts-v1/;
+
+#include "stm32mp157c-ed1.dts"
+
+/ {
+        model = "STMicroelectronics STM32MP157C eval daughter on eval mother";
+        compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157";
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+
+        aliases {
+                serial0 = &uart4;
+        };
+};
diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi
new file mode 100644
index 000000000000..9e17e42b02b2
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157c.dtsi
@@ -0,0 +1,194 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
+ */
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu0: cpu@0 {
+                        compatible = "arm,cortex-a7";
+                        device_type = "cpu";
+                        reg = <0>;
+                };
+
+                cpu1: cpu@1 {
+                        compatible = "arm,cortex-a7";
+                        device_type = "cpu";
+                        reg = <1>;
+                };
+        };
+
+        psci {
+                compatible = "arm,psci";
+                method = "smc";
+                cpu_off = <0x84000002>;
+                cpu_on = <0x84000003>;
+        };
+
+        aliases {
+                gpio0 = &gpioa;
+                gpio1 = &gpiob;
+                gpio2 = &gpioc;
+                gpio3 = &gpiod;
+                gpio4 = &gpioe;
+                gpio5 = &gpiof;
+                gpio6 = &gpiog;
+                gpio7 = &gpioh;
+                gpio8 = &gpioi;
+                gpio9 = &gpioj;
+                gpio10 = &gpiok;
+        };
+
+        intc: interrupt-controller@a0021000 {
+                compatible = "arm,cortex-a7-gic";
+                #interrupt-cells = <3>;
+                interrupt-controller;
+                reg = <0xa0021000 0x1000>,
+                      <0xa0022000 0x2000>;
+        };
+
+        timer {
+                compatible = "arm,armv7-timer";
+                interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+                interrupt-parent = <&intc>;
+        };
+
+        clocks {
+                clk_hse: clk-hse {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <24000000>;
+                };
+
+                clk_pll_per: clk-pll-per {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <64000000>;
+                };
+
+                clk_hsi: clk-hsi {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <64000000>;
+                };
+
+                clk_lse: clk-lse {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <32768>;
+                };
+
+                clk_lsi: clk-lsi {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <32000>;
+                };
+
+                clk_csi: clk-csi {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <4000000>;
+                };
+
+                clk_pclk1: clk-pclk1 {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <86000000>;
+                };
+
+                clk_pll3_p: clk-pll3_p {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <172000000>;
+                };
+
+                clk_pll2_p: clk-pll2_p {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <264000000>;
+                };
+        };
+
+        soc {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                interrupt-parent = <&intc>;
+                ranges;
+
+                usart2: serial@4000e000 {
+                        compatible = "st,stm32h7-uart";
+                        reg = <0x4000e000 0x400>;
+                        interrupts = <GIC_SPI 38 IRQ_TYPE_NONE>;
+                        clocks = <&clk_pclk1>;
+                        status = "disabled";
+                };
+
+                usart3: serial@4000f000 {
+                        compatible = "st,stm32h7-uart";
+                        reg = <0x4000f000 0x400>;
+                        interrupts = <GIC_SPI 39 IRQ_TYPE_NONE>;
+                        clocks = <&clk_pclk1>;
+                        status = "disabled";
+                };
+
+                uart4: serial@40010000 {
+                        compatible = "st,stm32h7-uart";
+                        reg = <0x40010000 0x400>;
+                        interrupts = <GIC_SPI 52 IRQ_TYPE_NONE>;
+                        clocks = <&clk_pclk1>;
+                        status = "disabled";
+                };
+
+                uart5: serial@40011000 {
+                        compatible = "st,stm32h7-uart";
+                        reg = <0x40011000 0x400>;
+                        interrupts = <GIC_SPI 53 IRQ_TYPE_NONE>;
+                        clocks = <&clk_pclk1>;
+                        status = "disabled";
+                };
+
+                uart7: serial@40018000 {
+                        compatible = "st,stm32h7-uart";
+                        reg = <0x40018000 0x400>;
+                        interrupts = <GIC_SPI 82 IRQ_TYPE_NONE>;
+                        clocks = <&clk_pclk1>;
+                        status = "disabled";
+                };
+
+                uart8: serial@40019000 {
+                        compatible = "st,stm32h7-uart";
+                        reg = <0x40019000 0x400>;
+                        interrupts = <GIC_SPI 83 IRQ_TYPE_NONE>;
+                        clocks = <&clk_pclk1>;
+                        status = "disabled";
+                };
+
+                usart6: serial@44003000 {
+                        compatible = "st,stm32h7-uart";
+                        reg = <0x44003000 0x400>;
+                        interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
+                        clocks = <&clk_pclk1>;
+                        status = "disabled";
+                };
+
+                usart1: serial@5c000000 {
+                        compatible = "st,stm32h7-uart";
+                        reg = <0x5c000000 0x400>;
+                        interrupts = <GIC_SPI 37 IRQ_TYPE_NONE>;
+                        clocks = <&clk_pclk1>;
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts
index 09e909576c61..6c254ec4c85b 100644
--- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
@@ -164,8 +164,7 @@
 &mmc0 {
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-        cd-inverted;
+        cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts
index 39ba4ccb9e2e..38a2c4134952 100644
--- a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts
+++ b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts
@@ -106,8 +106,7 @@
 &mmc0 {
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-        cd-inverted;
+        cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts b/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts
index dfc88aee4fe3..cf7b392dff31 100644
--- a/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts
+++ b/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts
@@ -123,8 +123,7 @@
 &mmc0 {
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-        cd-inverted;
+        cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index 1982c8c238c5..197a1f2b75ff 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -162,8 +162,7 @@
 &mmc0 {
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-        cd-inverted;
+        cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts b/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts
index 147cbc5e08ac..896e27a08727 100644
--- a/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts
+++ b/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts
@@ -150,8 +150,7 @@
 &mmc0 {
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-        cd-inverted;
+        cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts b/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts
index 41ca8bded89f..ea7a59dcf8f9 100644
--- a/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts
+++ b/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts
@@ -141,8 +141,7 @@
 &mmc0 {
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH01 */
-        cd-inverted;
+        cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH01 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
index f33e42d6ce8b..cc988ccd5ca7 100644
--- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts
+++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
@@ -106,8 +106,7 @@
 &mmc0 {
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-        cd-inverted;
+        cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts b/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts
index 35c57d065dd8..f63767cddd8e 100644
--- a/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts
+++ b/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts
@@ -78,8 +78,7 @@
 &mmc0 {
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-        cd-inverted;
+        cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun4i-a10-inet1.dts b/arch/arm/boot/dts/sun4i-a10-inet1.dts
index 9482e831a9a1..26d0c1d6a02b 100644
--- a/arch/arm/boot/dts/sun4i-a10-inet1.dts
+++ b/arch/arm/boot/dts/sun4i-a10-inet1.dts
@@ -152,8 +152,7 @@
 &mmc0 {
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-        cd-inverted;
+        cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
index 4b5c91c8e85b..5d096528e75a 100644
--- a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
+++ b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
@@ -142,8 +142,7 @@
 &mmc0 {
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-        cd-inverted;
+        cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts b/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts
index 13224f5ac166..221acd10f6c8 100644
--- a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts
+++ b/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts
@@ -300,8 +300,7 @@
 &mmc0 {
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-        cd-inverted;
+        cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts b/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts
index d22bd79562d8..80ecd78247ac 100644
--- a/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts
+++ b/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts
@@ -106,8 +106,7 @@
         pinctrl-0 = <&mmc0_pins>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-        cd-inverted;
+        cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts b/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts
index 879141ca6027..247fa27ef717 100644
--- a/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts
+++ b/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts
@@ -133,8 +133,7 @@
 &mmc0 {
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-        cd-inverted;
+        cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun4i-a10-marsboard.dts b/arch/arm/boot/dts/sun4i-a10-marsboard.dts
index 435c551aef0f..0dbf69576512 100644
--- a/arch/arm/boot/dts/sun4i-a10-marsboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-marsboard.dts
@@ -132,8 +132,7 @@
 &mmc0 {
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-        cd-inverted;
+        cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
index 1b639e5f9172..f9d74e21031d 100644
--- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
+++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
@@ -96,8 +96,7 @@
 &mmc0 {
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-        cd-inverted;
+        cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun4i-a10-mk802.dts b/arch/arm/boot/dts/sun4i-a10-mk802.dts
index 7198b34e2e50..059fe9c5d024 100644
--- a/arch/arm/boot/dts/sun4i-a10-mk802.dts
+++ b/arch/arm/boot/dts/sun4i-a10-mk802.dts
@@ -56,12 +56,27 @@
         chosen {
                 stdout-path = "serial0:115200n8";
         };
+
+        hdmi-connector {
+                compatible = "hdmi-connector";
+                type = "a";
+
+                port {
+                        hdmi_con_in: endpoint {
+                                remote-endpoint = <&hdmi_out_con>;
+                        };
+                };
+        };
 };
 
 &codec {
         status = "okay";
 };
 
+&de {
+        status = "okay";
+};
+
 &ehci0 {
         status = "okay";
 };
@@ -70,11 +85,20 @@
         status = "okay";
 };
 
+&hdmi {
+        status = "okay";
+};
+
+&hdmi_out {
+        hdmi_out_con: endpoint {
+                remote-endpoint = <&hdmi_con_in>;
+        };
+};
+
 &mmc0 {
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-        cd-inverted;
+        cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun4i-a10-mk802ii.dts b/arch/arm/boot/dts/sun4i-a10-mk802ii.dts
index e460da2eb139..17dcdf031118 100644
--- a/arch/arm/boot/dts/sun4i-a10-mk802ii.dts
+++ b/arch/arm/boot/dts/sun4i-a10-mk802ii.dts
@@ -82,8 +82,7 @@
 &mmc0 {
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-        cd-inverted;
+        cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
index 49247fbe6acd..b74a61496537 100644
--- a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
+++ b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
@@ -97,7 +97,6 @@
                 864000  1300000
                 624000  1250000
                 >;
-        cooling-max-level = <2>;
 };
 
 &de {
@@ -165,8 +164,7 @@
 &mmc0 {
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-        cd-inverted;
+        cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
index 6e140547b638..b97a0f2f20b9 100644
--- a/arch/arm/boot/dts/sun4i-a10-pcduino.dts
+++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
@@ -140,8 +140,7 @@
 &mmc0 {
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-        cd-inverted;
+        cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts b/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts
index 5081303f79e7..84b25be1ac94 100644
--- a/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts
+++ b/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts
@@ -138,8 +138,7 @@
 &mmc0 {
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-        cd-inverted;
+        cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 4f2f2eea0755..77e8436beed4 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -123,8 +123,6 @@
                                 624000  1250000
                                 >;
                         #cooling-cells = <2>;
-                        cooling-min-level = <0>;
-                        cooling-max-level = <3>;
                 };
         };
 
diff --git a/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts b/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts
index d2dee8d434bf..39504d720efc 100644
--- a/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-auxtek-t003.dts
@@ -93,8 +93,7 @@
         pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_t003>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
-        cd-inverted;
+        cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts b/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts
index 16f839df4227..8d4fb9331212 100644
--- a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts
@@ -104,8 +104,7 @@
         pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_t004>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
-        cd-inverted;
+        cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun5i-a10s-mk802.dts b/arch/arm/boot/dts/sun5i-a10s-mk802.dts
index 020aa9d6c31d..dd7fd5c3d76f 100644
--- a/arch/arm/boot/dts/sun5i-a10s-mk802.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-mk802.dts
@@ -92,8 +92,7 @@
         pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_mk802>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
-        cd-inverted;
+        cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
index da95118af4dc..2c902ed2c87a 100644
--- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
@@ -201,8 +201,7 @@
         pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino_micro>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
-        cd-inverted;
+        cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */
         status = "okay";
 };
 
@@ -211,8 +210,7 @@
         pinctrl-0 = <&mmc1_pins_a>, <&mmc1_cd_pin_olinuxino_micro>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */
-        cd-inverted;
+        cd-gpios = <&pio 6 13 GPIO_ACTIVE_LOW>; /* PG13 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts
index 262b3669f04d..034853d1c08f 100644
--- a/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts
@@ -80,8 +80,7 @@
         pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_r7>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
-        cd-inverted;
+        cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts b/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts
index 5482be174e12..3f68ef5d92a0 100644
--- a/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts
@@ -130,8 +130,7 @@
         pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_wobo_i5>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
-        cd-inverted;
+        cd-gpios = <&pio 1 3 GPIO_ACTIVE_LOW>; /* PB3 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts
index 3dbb0d7c2f8c..378214d8316e 100644
--- a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts
+++ b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts
@@ -125,8 +125,7 @@
         pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_d709>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
-        cd-inverted;
+        cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts
index 584fa579ded2..7ee0c3f6d7a1 100644
--- a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts
+++ b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts
@@ -120,8 +120,7 @@
         pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_h702>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
-        cd-inverted;
+        cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
index 3a831eaf1dfc..aa4b34fd9126 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
@@ -99,8 +99,7 @@
         pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxinom>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
-        cd-inverted;
+        cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index 4b9af423c6d5..437ad913a373 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -194,8 +194,7 @@
         pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
-        cd-inverted;
+        cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 4e830f5cb7f1..b1d827765530 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -116,8 +116,6 @@
                 432000  1200000
                 >;
         #cooling-cells = <2>;
-        cooling-min-level = <0>;
-        cooling-max-level = <5>;
 };
 
 &pio {
diff --git a/arch/arm/boot/dts/sun5i-gr8-evb.dts b/arch/arm/boot/dts/sun5i-gr8-evb.dts
index 558c16a30543..5f0adc0f7bb4 100644
--- a/arch/arm/boot/dts/sun5i-gr8-evb.dts
+++ b/arch/arm/boot/dts/sun5i-gr8-evb.dts
@@ -236,8 +236,7 @@
         pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_gr8_evb>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
-        cd-inverted;
+        cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi
index 49229b3d5492..8acbaab14fe5 100644
--- a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi
+++ b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi
@@ -127,8 +127,7 @@
         pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
         vmmc-supply = <&reg_vcc3v0>;
         bus-width = <4>;
-        cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
-        cd-inverted;
+        cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts b/arch/arm/boot/dts/sun6i-a31-colombus.dts
index 85eff0307ca4..939c497a6f70 100644
--- a/arch/arm/boot/dts/sun6i-a31-colombus.dts
+++ b/arch/arm/boot/dts/sun6i-a31-colombus.dts
@@ -117,8 +117,7 @@
         pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_colombus>;
         vmmc-supply = <&reg_vcc3v0>;
         bus-width = <4>;
-        cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */
-        cd-inverted;
+        cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
index 19e382a11297..ce4f9e9834bf 100644
--- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
+++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
@@ -218,8 +218,7 @@
         pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_hummingbird>;
         vmmc-supply = <&reg_dcdc1>;
         bus-width = <4>;
-        cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */
-        cd-inverted;
+        cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun6i-a31-i7.dts b/arch/arm/boot/dts/sun6i-a31-i7.dts
index 010a84c7c012..d659be9dbc50 100644
--- a/arch/arm/boot/dts/sun6i-a31-i7.dts
+++ b/arch/arm/boot/dts/sun6i-a31-i7.dts
@@ -58,6 +58,17 @@
                 stdout-path = "serial0:115200n8";
         };
 
+        hdmi-connector {
+                compatible = "hdmi-connector";
+                type = "a";
+
+                port {
+                        hdmi_con_in: endpoint {
+                                remote-endpoint = <&hdmi_out_con>;
+                        };
+                };
+        };
+
         leds {
                 compatible = "gpio-leds";
                 pinctrl-names = "default";
@@ -93,6 +104,10 @@
         status = "okay";
 };
 
+&de {
+        status = "okay";
+};
+
 &ehci0 {
         status = "okay";
 };
@@ -113,6 +128,16 @@
         };
 };
 
+&hdmi {
+        status = "okay";
+};
+
+&hdmi_out {
+        hdmi_out_con: endpoint {
+                remote-endpoint = <&hdmi_con_in>;
+        };
+};
+
 &ir {
         pinctrl-names = "default";
         pinctrl-0 = <&ir_pins_a>;
@@ -124,8 +149,7 @@
         pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_i7>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */
-        cd-inverted;
+        cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */
         status = "okay";
 };
 
@@ -161,6 +185,10 @@
         status = "okay";
 };
 
+&tcon0 {
+        status = "okay";
+};
+
 &uart0 {
         pinctrl-names = "default";
         pinctrl-0 = <&uart0_pins_a>;
diff --git a/arch/arm/boot/dts/sun6i-a31-m9.dts b/arch/arm/boot/dts/sun6i-a31-m9.dts
index 50605fd4449e..9698f6d38d03 100644
--- a/arch/arm/boot/dts/sun6i-a31-m9.dts
+++ b/arch/arm/boot/dts/sun6i-a31-m9.dts
@@ -107,8 +107,7 @@
         pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_m9>;
         vmmc-supply = <&reg_dcdc1>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */
-        cd-inverted;
+        cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts b/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts
index 5219556e9f73..bb14b171b160 100644
--- a/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts
+++ b/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts
@@ -107,8 +107,7 @@
         pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_m9>;
         vmmc-supply = <&reg_dcdc1>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */
-        cd-inverted;
+        cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 72d3fe44ecaf..c72992556a86 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -113,8 +113,6 @@
                                 480000  1000000
                                 >;
                         #cooling-cells = <2>;
-                        cooling-min-level = <0>;
-                        cooling-max-level = <3>;
                 };
 
                 cpu@1 {
diff --git a/arch/arm/boot/dts/sun6i-a31s-primo81.dts b/arch/arm/boot/dts/sun6i-a31s-primo81.dts
index 0cdb38ab3377..4cb9664cdb29 100644
--- a/arch/arm/boot/dts/sun6i-a31s-primo81.dts
+++ b/arch/arm/boot/dts/sun6i-a31s-primo81.dts
@@ -151,8 +151,7 @@
         pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_primo81>;
         vmmc-supply = <&reg_dcdc1>;
         bus-width = <4>;
-        cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */
-        cd-inverted;
+        cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts
index 298476485bb4..da0ccf5a2c44 100644
--- a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts
+++ b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts
@@ -167,8 +167,7 @@
         pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_sina31s>;
         vmmc-supply = <&reg_dcdc1>;
         bus-width = <4>;
-        cd-gpios = <&pio 0 4 GPIO_ACTIVE_HIGH>; /* PA4 */
-        cd-inverted;
+        cd-gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
index 51e6f1d21c32..3077e8ec9cd9 100644
--- a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
+++ b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
@@ -120,8 +120,7 @@
         pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bpi_m2>;
         vmmc-supply = <&reg_vcc3v0>;
         bus-width = <4>;
-        cd-gpios = <&pio 0 4 GPIO_ACTIVE_HIGH>; /* PA4 */
-        cd-inverted;
+        cd-gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts b/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts
index f3edf9ca435c..aab6c1720ef7 100644
--- a/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts
+++ b/arch/arm/boot/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts
@@ -102,8 +102,7 @@
         pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bs1078v2>;
         vmmc-supply = <&reg_vcc3v0>;
         bus-width = <4>;
-        cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */
-        cd-inverted;
+        cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi
index 3cc4046b904a..4e72e4f3ef96 100644
--- a/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi
+++ b/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi
@@ -69,8 +69,7 @@
         pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_e708_q1>;
         vmmc-supply = <&reg_dcdc1>;
         bus-width = <4>;
-        cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */
-        cd-inverted;
+        cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts
index 4ed3162e3e5a..763cb03033c4 100644
--- a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts
+++ b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts
@@ -184,8 +184,7 @@
         pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bpi_m1p>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
-        cd-inverted;
+        cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi.dts b/arch/arm/boot/dts/sun7i-a20-bananapi.dts
index 88a1c2363c6c..70dfc4ac0bb5 100644
--- a/arch/arm/boot/dts/sun7i-a20-bananapi.dts
+++ b/arch/arm/boot/dts/sun7i-a20-bananapi.dts
@@ -63,6 +63,17 @@
                 stdout-path = "serial0:115200n8";
         };
 
+        hdmi-connector {
+                compatible = "hdmi-connector";
+                type = "a";
+
+                port {
+                        hdmi_con_in: endpoint {
+                                remote-endpoint = <&hdmi_out_con>;
+                        };
+                };
+        };
+
         leds {
                 compatible = "gpio-leds";
                 pinctrl-names = "default";
@@ -109,6 +120,10 @@
                 >;
 };
 
+&de {
+        status = "okay";
+};
+
 &ehci0 {
         status = "okay";
 };
@@ -130,6 +145,16 @@
         };
 };
 
+&hdmi {
+        status = "okay";
+};
+
+&hdmi_out {
+        hdmi_out_con: endpoint {
+                remote-endpoint = <&hdmi_con_in>;
+        };
+};
+
 &i2c0 {
         pinctrl-names = "default";
         pinctrl-0 = <&i2c0_pins_a>;
@@ -159,8 +184,7 @@
         pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bananapi>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
-        cd-inverted;
+        cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun7i-a20-bananapro.dts b/arch/arm/boot/dts/sun7i-a20-bananapro.dts
index e7af1b7c33d5..0898eb6162f5 100644
--- a/arch/arm/boot/dts/sun7i-a20-bananapro.dts
+++ b/arch/arm/boot/dts/sun7i-a20-bananapro.dts
@@ -158,8 +158,7 @@
         pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bananapro>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
-        cd-inverted;
+        cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
index 39f43e4eb742..942ac9dfd4a5 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
@@ -165,8 +165,7 @@
         pinctrl-0 = <&mmc0_pins_a>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-        cd-inverted;
+        cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index 8c9bedc602ec..5649161de1d7 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
@@ -206,8 +206,7 @@
         pinctrl-0 = <&mmc0_pins_a>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-        cd-inverted;
+        cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun7i-a20-hummingbird.dts b/arch/arm/boot/dts/sun7i-a20-hummingbird.dts
index 6e6264cd69f8..1f0e5ecbf0c4 100644
--- a/arch/arm/boot/dts/sun7i-a20-hummingbird.dts
+++ b/arch/arm/boot/dts/sun7i-a20-hummingbird.dts
@@ -163,8 +163,7 @@
         pinctrl-0 = <&mmc0_pins_a>;
         vmmc-supply = <&reg_vcc3v0>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-        cd-inverted;
+        cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
index 55809973a568..2e3f2f29d124 100644
--- a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
+++ b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
@@ -160,8 +160,7 @@
         pinctrl-0 = <&mmc0_pins_a>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-        cd-inverted;
+        cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts b/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts
index 794e7617f545..926fa194eb1b 100644
--- a/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts
+++ b/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts
@@ -107,8 +107,7 @@
         pinctrl-0 = <&mmc0_pins_a>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 8 5 GPIO_ACTIVE_HIGH>; /* PI5 */
-        cd-inverted;
+        cd-gpios = <&pio 8 5 GPIO_ACTIVE_LOW>; /* PI5 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts b/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts
index 8a8a6dbcd414..1b05ba466e7d 100644
--- a/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts
+++ b/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts
@@ -124,8 +124,7 @@
         pinctrl-0 = <&mmc0_pins_a>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-        cd-inverted;
+        cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts
index 442f3c755f36..b1ab7c1c33e3 100644
--- a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts
+++ b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts
@@ -227,8 +227,7 @@
         pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_lamobo_r1>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
-        cd-inverted;
+        cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun7i-a20-m3.dts b/arch/arm/boot/dts/sun7i-a20-m3.dts
index 43c94787ef07..e91a209850bc 100644
--- a/arch/arm/boot/dts/sun7i-a20-m3.dts
+++ b/arch/arm/boot/dts/sun7i-a20-m3.dts
@@ -120,8 +120,7 @@
         pinctrl-0 = <&mmc0_pins_a>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-        cd-inverted;
+        cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun7i-a20-mk808c.dts b/arch/arm/boot/dts/sun7i-a20-mk808c.dts
index f7413094183c..6109f794a9c1 100644
--- a/arch/arm/boot/dts/sun7i-a20-mk808c.dts
+++ b/arch/arm/boot/dts/sun7i-a20-mk808c.dts
@@ -66,12 +66,27 @@
         chosen {
                 stdout-path = "serial0:115200n8";
         };
+
+        hdmi-connector {
+                compatible = "hdmi-connector";
+                type = "a";
+
+                port {
+                        hdmi_con_in: endpoint {
+                                remote-endpoint = <&hdmi_out_con>;
+                        };
+                };
+        };
 };
 
 &codec {
         status = "okay";
 };
 
+&de {
+        status = "okay";
+};
+
 &ehci0 {
         status = "okay";
 };
@@ -80,6 +95,16 @@
         status = "okay";
 };
 
+&hdmi {
+        status = "okay";
+};
+
+&hdmi_out {
+        hdmi_out_con: endpoint {
+        remote-endpoint = <&hdmi_con_in>;
+        };
+};
+
 &i2c0 {
         pinctrl-names = "default";
         pinctrl-0 = <&i2c0_pins_a>;
@@ -112,8 +137,7 @@
         pinctrl-0 = <&mmc0_pins_a>;
         vmmc-supply = <&reg_vcc3v0>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-        cd-inverted;
+        cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts
index 64c8ef9a2756..f080f82b58ef 100644
--- a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts
@@ -61,6 +61,17 @@
                 stdout-path = "serial0:115200n8";
         };
 
+        hdmi-connector {
+                compatible = "hdmi-connector";
+                type = "a";
+
+                port {
+                        hdmi_con_in: endpoint {
+                                remote-endpoint = <&hdmi_out_con>;
+                        };
+                };
+        };
+
         leds {
                 compatible = "gpio-leds";
                 pinctrl-names = "default";
@@ -79,6 +90,10 @@
         status = "okay";
 };
 
+&de {
+        status = "okay";
+};
+
 &ehci0 {
         status = "okay";
 };
@@ -107,6 +122,16 @@
         };
 };
 
+&hdmi {
+        status = "okay";
+};
+
+&hdmi_out {
+        hdmi_out_con: endpoint {
+                remote-endpoint = <&hdmi_con_in>;
+        };
+};
+
 &i2c0 {
         pinctrl-names = "default";
         pinctrl-0 = <&i2c0_pins_a>;
@@ -190,8 +215,7 @@
         pinctrl-0 = <&mmc0_pins_a>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-        cd-inverted;
+        cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
         status = "okay";
 };
 
@@ -200,8 +224,7 @@
         pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_olimex_som_evb>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 0 GPIO_ACTIVE_HIGH>; /* PH0 */
-        cd-inverted;
+        cd-gpios = <&pio 7 0 GPIO_ACTIVE_LOW>; /* PH0 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb-emmc.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb-emmc.dts
new file mode 100644
index 000000000000..c56620a8fb20
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb-emmc.dts
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree Source for A20-SOM204-EVB-eMMC Board
+ *
+ * Copyright (C) 2018 Olimex Ltd.
+ *   Author: Stefan Mavrodiev <stefan@olimex.com>
+ */
+
+/dts-v1/;
+#include "sun7i-a20-olimex-som204-evb.dts"
+
+/ {
+        model = "Olimex A20-SOM204-EVB-eMMC";
+        compatible = "olimex,a20-olimex-som204-evb-emmc", "allwinner,sun7i-a20";
+
+        mmc2_pwrseq: mmc2_pwrseq {
+                compatible = "mmc-pwrseq-emmc";
+                reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>;
+        };
+};
+
+&mmc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc2_pins_a>;
+        vmmc-supply = <&reg_vcc3v3>;
+        mmc-pwrseq = <&mmc2_pwrseq>;
+        bus-width = <4>;
+        non-removable;
+        status = "okay";
+
+        emmc: emmc@0 {
+                reg = <0>;
+                compatible = "mmc-card";
+                broken-hpi;
+        };
+};
diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts
new file mode 100644
index 000000000000..eae8e267b9ef
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-olimex-som204-evb.dts
@@ -0,0 +1,335 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree Source for A20-SOM204-EVB Board
+ *
+ * Copyright (C) 2018 Olimex Ltd.
+ *   Author: Stefan Mavrodiev <stefan@olimex.com>
+ */
+
+/dts-v1/;
+#include "sun7i-a20.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+        model = "Olimex A20-SOM204-EVB";
+        compatible = "olimex,a20-olimex-som204-evb", "allwinner,sun7i-a20";
+
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart4;
+                serial2 = &uart7;
+                spi0 = &spi1;
+                spi1 = &spi2;
+                ethernet1 = &rtl8723bs;
+        };
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+
+        hdmi-connector {
+                compatible = "hdmi-connector";
+                type = "a";
+
+                port {
+                        hdmi_con_in: endpoint {
+                                remote-endpoint = <&hdmi_out_con>;
+                        };
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                stat {
+                        label = "a20-som204-evb:green:stat";
+                        gpios = <&pio 8 0 GPIO_ACTIVE_HIGH>;
+                        default-state = "on";
+                };
+
+                led1 {
+                        label = "a20-som204-evb:green:led1";
+                        gpios = <&pio 8 10 GPIO_ACTIVE_HIGH>;
+                        default-state = "on";
+                };
+
+                led2 {
+                        label = "a20-som204-evb:yellow:led2";
+                        gpios = <&pio 8 11 GPIO_ACTIVE_HIGH>;
+                        default-state = "on";
+                };
+        };
+
+        rtl_pwrseq: rtl_pwrseq {
+                compatible = "mmc-pwrseq-simple";
+                reset-gpios = <&pio 6 9 GPIO_ACTIVE_LOW>;
+        };
+};
+
+&ahci {
+        target-supply = <&reg_ahci_5v>;
+        status = "okay";
+};
+
+&can0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&can0_pins_a>;
+        status = "okay";
+};
+
+&codec {
+        status = "okay";
+};
+
+&cpu0 {
+        cpu-supply = <&reg_dcdc2>;
+};
+
+&de {
+        status = "okay";
+};
+
+&ehci0 {
+        status = "okay";
+};
+
+&ehci1 {
+        status = "okay";
+};
+
+&gmac {
+        pinctrl-names = "default";
+        pinctrl-0 = <&gmac_pins_rgmii_a>;
+        phy = <&phy3>;
+        phy-mode = "rgmii";
+        phy-supply = <&reg_vcc3v3>;
+
+        snps,reset-gpio = <&pio 0 17 GPIO_ACTIVE_HIGH>;
+        snps,reset-active-low;
+        snps,reset-delays-us = <0 10000 1000000>;
+        status = "okay";
+
+        phy3: ethernet-phy@3 {
+                reg = <3>;
+        };
+};
+
+&hdmi {
+        status = "okay";
+};
+
+&hdmi_out {
+        hdmi_out_con: endpoint {
+                remote-endpoint = <&hdmi_con_in>;
+        };
+};
+
+&i2c0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c0_pins_a>;
+        status = "okay";
+
+        axp209: pmic@34 {
+                reg = <0x34>;
+                interrupt-parent = <&nmi_intc>;
+                interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+        };
+};
+
+/* Exposed to UEXT1 */
+&i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c1_pins_a>;
+        status = "okay";
+
+        eeprom: eeprom@50 {
+                compatible = "atmel,24c16";
+                reg = <0x50>;
+                pagesize = <16>;
+        };
+};
+
+/* Exposed to UEXT2 */
+&i2c2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c2_pins_a>;
+        status = "okay";
+};
+
+&ir0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&ir0_rx_pins_a>;
+        status = "okay";
+};
+
+&mmc0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc0_pins_a>;
+        vmmc-supply = <&reg_vcc3v3>;
+        bus-width = <4>;
+        cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>;
+        cd-inverted;
+        status = "okay";
+};
+
+&mmc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc3_pins_a>;
+        vmmc-supply = <&reg_vcc3v3>;
+        mmc-pwrseq = <&rtl_pwrseq>;
+        bus-width = <4>;
+        non-removable;
+        status = "okay";
+
+        rtl8723bs: sdio_wifi@1 {
+                reg = <1>;
+        };
+};
+
+&ohci0 {
+        status = "okay";
+};
+
+&ohci1 {
+        status = "okay";
+};
+
+&otg_sram {
+        status = "okay";
+};
+
+&pio {
+        bt_uart_pins: bt_uart_pins@0 {
+                pins = "PG6", "PG7", "PG8";
+                function = "uart3";
+        };
+};
+
+#include "axp209.dtsi"
+
+&ac_power_supply {
+        status = "okay";
+};
+
+&battery_power_supply {
+        status = "okay";
+};
+
+&reg_ahci_5v {
+        gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>;
+        status = "okay";
+};
+
+&reg_dcdc2 {
+        regulator-always-on;
+        regulator-min-microvolt = <1000000>;
+        regulator-max-microvolt = <1400000>;
+        regulator-name = "vdd-cpu";
+};
+
+&reg_dcdc3 {
+        regulator-always-on;
+        regulator-min-microvolt = <1000000>;
+        regulator-max-microvolt = <1400000>;
+        regulator-name = "vdd-int-dll";
+};
+
+&reg_ldo1 {
+        regulator-always-on;
+        regulator-min-microvolt = <1300000>;
+        regulator-max-microvolt = <1300000>;
+        regulator-name = "vdd-rtc";
+};
+
+&reg_ldo2 {
+        regulator-always-on;
+        regulator-min-microvolt = <3000000>;
+        regulator-max-microvolt = <3000000>;
+        regulator-name = "avcc";
+};
+
+&reg_ldo4 {
+        regulator-min-microvolt = <3300000>;
+        regulator-max-microvolt = <3300000>;
+        regulator-name = "vcc-pg";
+};
+
+&reg_usb0_vbus {
+        gpio = <&pio 2 17 GPIO_ACTIVE_HIGH>;
+        status = "okay";
+};
+
+&reg_usb1_vbus {
+        status = "okay";
+};
+
+&reg_usb2_vbus {
+        status = "okay";
+};
+
+/* Exposed to UEXT1 */
+&spi1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&spi1_pins_a>,
+                    <&spi1_cs0_pins_a>;
+        status = "okay";
+};
+
+/* Exposed to UEXT2 */
+&spi2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&spi2_pins_a>,
+                    <&spi2_cs0_pins_a>;
+        status = "okay";
+};
+
+&uart0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart0_pins_a>;
+        status = "okay";
+};
+
+/* Used for RTL8723BS bluetooth */
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&bt_uart_pins>;
+        status = "okay";
+};
+
+/* Exposed to UEXT1 */
+&uart4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart4_pins_a>;
+        status = "okay";
+};
+
+/* Exposed to UEXT2 */
+&uart7 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart7_pins_a>;
+        status = "okay";
+};
+
+&usb_otg {
+        dr_mode = "otg";
+        status = "okay";
+};
+
+&usb_power_supply {
+        status = "okay";
+};
+
+&usbphy {
+        usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+        usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+        usb0_vbus_power-supply = <&usb_power_supply>;
+        usb0_vbus-supply = <&reg_usb0_vbus>;
+        usb1_vbus-supply = <&reg_usb1_vbus>;
+        usb2_vbus-supply = <&reg_usb2_vbus>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
index edf9c3c6c0d7..d20fd03596e9 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
@@ -158,8 +158,7 @@
         pinctrl-0 = <&mmc0_pins_a>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-        cd-inverted;
+        cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
index ba250189d07f..b828677f331d 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
@@ -159,8 +159,7 @@
         pinctrl-0 = <&mmc0_pins_a>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-        cd-inverted;
+        cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
index dffbaa24b3ee..866d230593be 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
@@ -226,8 +226,7 @@
         pinctrl-0 = <&mmc0_pins_a>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-        cd-inverted;
+        cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
         status = "okay";
 };
 
@@ -236,8 +235,7 @@
         pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_olinuxinom>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */
-        cd-inverted;
+        cd-gpios = <&pio 7 11 GPIO_ACTIVE_LOW>; /* PH11 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts b/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts
index 7af4c8fc1865..f5c7178eb063 100644
--- a/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts
+++ b/arch/arm/boot/dts/sun7i-a20-orangepi-mini.dts
@@ -61,6 +61,17 @@
                 stdout-path = "serial0:115200n8";
         };
 
+        hdmi-connector {
+                compatible = "hdmi-connector";
+                type = "a";
+
+                port {
+                        hdmi_con_in: endpoint {
+                                remote-endpoint = <&hdmi_out_con>;
+                        };
+                };
+        };
+
         leds {
                 compatible = "gpio-leds";
                 pinctrl-names = "default";
@@ -98,6 +109,10 @@
         status = "okay";
 };
 
+&de {
+        status = "okay";
+};
+
 &ehci0 {
         status = "okay";
 };
@@ -119,6 +134,16 @@
         };
 };
 
+&hdmi {
+        status = "okay";
+};
+
+&hdmi_out {
+        hdmi_out_con: endpoint {
+                remote-endpoint = <&hdmi_con_in>;
+        };
+};
+
 &i2c0 {
         pinctrl-names = "default";
         pinctrl-0 = <&i2c0_pins_a>;
@@ -144,8 +169,7 @@
         pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_orangepi>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
-        cd-inverted;
+        cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */
         status = "okay";
 };
 
@@ -154,8 +178,7 @@
         pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_orangepi>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */
-        cd-inverted;
+        cd-gpios = <&pio 7 11 GPIO_ACTIVE_LOW>; /* PH11 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun7i-a20-orangepi.dts b/arch/arm/boot/dts/sun7i-a20-orangepi.dts
index 0a8d4a05e8a0..7a4244e57589 100644
--- a/arch/arm/boot/dts/sun7i-a20-orangepi.dts
+++ b/arch/arm/boot/dts/sun7i-a20-orangepi.dts
@@ -135,8 +135,7 @@
         pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_orangepi>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
-        cd-inverted;
+        cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
index fb591f32252c..bfca960b03e0 100644
--- a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
+++ b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
@@ -158,8 +158,7 @@
         pinctrl-0 = <&mmc0_pins_a>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-        cd-inverted;
+        cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
index 777152a3df0f..c576f101fbde 100644
--- a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
+++ b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
@@ -159,8 +159,7 @@
         pinctrl-0 = <&mmc0_pins_a>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-        cd-inverted;
+        cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts b/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts
index f8d0aafb9f88..8202c87ca6a3 100644
--- a/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts
+++ b/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts
@@ -154,8 +154,7 @@
         pinctrl-0 = <&mmc0_pins_a>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-        cd-inverted;
+        cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts b/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts
index 7f8405a0dd0f..ff5c1086585c 100644
--- a/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts
+++ b/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts
@@ -123,8 +123,7 @@
         pinctrl-0 = <&mmc0_pins_a>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
-        cd-inverted;
+        cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index bd0cd3204273..e529e4ff2174 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -47,7 +47,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/thermal/thermal.h>
 #include <dt-bindings/dma/sun4i-a10.h>
-#include <dt-bindings/clock/sun4i-a10-ccu.h>
+#include <dt-bindings/clock/sun7i-a20-ccu.h>
 #include <dt-bindings/reset/sun4i-a10-ccu.h>
 
 / {
@@ -116,8 +116,6 @@
                                 144000  1000000
                                 >;
                         #cooling-cells = <2>;
-                        cooling-min-level = <0>;
-                        cooling-max-level = <6>;
                 };
 
                 cpu@1 {
@@ -1217,6 +1215,31 @@
                         #size-cells = <0>;
                 };
 
+                mali: gpu@1c40000 {
+                        compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
+                        reg = <0x01c40000 0x10000>;
+                        interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "gp",
+                                          "gpmmu",
+                                          "pp0",
+                                          "ppmmu0",
+                                          "pp1",
+                                          "ppmmu1",
+                                          "pmu";
+                        clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
+                        clock-names = "bus", "core";
+                        resets = <&ccu RST_GPU>;
+
+                        assigned-clocks = <&ccu CLK_GPU>;
+                        assigned-clock-rates = <384000000>;
+                };
+
                 gmac: ethernet@1c50000 {
                         compatible = "allwinner,sun7i-a20-gmac";
                         reg = <0x01c50000 0x10000>;
diff --git a/arch/arm/boot/dts/sun8i-a23-evb.dts b/arch/arm/boot/dts/sun8i-a23-evb.dts
index 87289a60c520..8a93697df3a5 100644
--- a/arch/arm/boot/dts/sun8i-a23-evb.dts
+++ b/arch/arm/boot/dts/sun8i-a23-evb.dts
@@ -107,8 +107,7 @@
         pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_evb>;
         vmmc-supply = <&reg_vcc3v0>;
         bus-width = <4>;
-        cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
-        cd-inverted;
+        cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun8i-a33-olinuxino.dts b/arch/arm/boot/dts/sun8i-a33-olinuxino.dts
index be9a6b8d7a1e..a1a1eb64caeb 100644
--- a/arch/arm/boot/dts/sun8i-a33-olinuxino.dts
+++ b/arch/arm/boot/dts/sun8i-a33-olinuxino.dts
@@ -43,7 +43,6 @@
 
 /dts-v1/;
 #include "sun8i-a33.dtsi"
-#include "sunxi-common-regulators.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
@@ -62,8 +61,6 @@
 
         leds {
                 compatible = "gpio-leds";
-                pinctrl-names = "default";
-                pinctrl-0 = <&led_pin_olinuxino>;
 
                 green {
                         label = "a33-olinuxino:green:usr";
@@ -72,17 +69,24 @@
         };
 };
 
+&codec {
+        status = "okay";
+};
+
+&dai {
+        status = "okay";
+};
+
 &ehci0 {
         status = "okay";
 };
 
 &mmc0 {
         pinctrl-names = "default";
-        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino>;
+        pinctrl-0 = <&mmc0_pins_a>;
         vmmc-supply = <&reg_dcdc1>;
         bus-width = <4>;
-        cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
-        cd-inverted;
+        cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */
         status = "okay";
 };
 
@@ -90,23 +94,6 @@
         status = "okay";
 };
 
-&pio {
-        led_pin_olinuxino: led_pins@0 {
-                pins = "PB7";
-                function = "gpio_out";
-        };
-
-        mmc0_cd_pin_olinuxino: mmc0_cd_pin@0 {
-                pins = "PB4";
-                function = "gpio_in";
-        };
-
-        usb0_id_detect_pin: usb0_id_detect_pin@0 {
-                pins = "PB3";
-                function = "gpio_in";
-        };
-};
-
 &r_rsb {
         status = "okay";
 
@@ -122,6 +109,14 @@
 
 #include "axp223.dtsi"
 
+&ac_power_supply {
+        status = "okay";
+};
+
+&battery_power_supply {
+        status = "okay";
+};
+
 &reg_aldo1 {
         regulator-always-on;
         regulator-min-microvolt = <3300000>;
@@ -195,6 +190,21 @@
         vcc-lcd-supply = <&reg_dc1sw>;
 };
 
+&sound {
+        /* Board level jack widgets */
+        simple-audio-card,widgets = "Microphone", "Microphone Jack",
+                                    "Headphone", "Headphone Jack";
+        /* Board level routing. First 2 routes copied from SoC level */
+        simple-audio-card,routing =
+                "Left DAC", "AIF1 Slot 0 Left",
+                "Right DAC", "AIF1 Slot 0 Right",
+                "HP", "HPCOM",
+                "Headphone Jack", "HP",
+                "MIC1", "Microphone Jack",
+                "Microphone Jack", "MBIAS";
+        status = "okay";
+};
+
 &uart0 {
         pinctrl-names = "default";
         pinctrl-0 = <&uart0_pins_b>;
@@ -211,8 +221,6 @@
 };
 
 &usbphy {
-        pinctrl-names = "default";
-        pinctrl-0 = <&usb0_id_detect_pin>;
         usb0_id_det-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
         usb0_vbus_power-supply = <&usb_power_supply>;
         usb0_vbus-supply = <&reg_drivevbus>;
diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
index 433cf2a2a9a2..541acb4d2b91 100644
--- a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
+++ b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
@@ -144,8 +144,7 @@
         pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_sina33>;
         vmmc-supply = <&reg_dcdc1>;
         bus-width = <4>;
-        cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
-        cd-inverted;
+        cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi
index 50eb84fa246a..a21f2ed07a52 100644
--- a/arch/arm/boot/dts/sun8i-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a33.dtsi
@@ -289,7 +289,6 @@
                         clock-names = "ahb", "mod",
                                       "ram";
                         resets = <&ccu RST_BUS_DE_FE>;
-                        status = "disabled";
 
                         ports {
                                 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
index 5091cecbcd1e..36ecebaff3c0 100644
--- a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
@@ -87,9 +87,8 @@
         pinctrl-names = "default";
         pinctrl-0 = <&mmc0_pins>;
         vmmc-supply = <&reg_dcdc1>;
-        cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+        cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
         bus-width = <4>;
-        cd-inverted;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
index 6550bf0e594b..3b579d7567c8 100644
--- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
@@ -60,6 +60,31 @@
                 stdout-path = "serial0:115200n8";
         };
 
+        connector {
+                compatible = "hdmi-connector";
+                type = "a";
+
+                port {
+                        hdmi_con_in: endpoint {
+                                remote-endpoint = <&hdmi_out_con>;
+                        };
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                blue {
+                        label = "bananapi-m3:blue:usr";
+                        gpios = <&axp_gpio 1 GPIO_ACTIVE_HIGH>;
+                };
+
+                green {
+                        label = "bananapi-m3:green:usr";
+                        gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>;
+                };
+        };
+
         reg_usb1_vbus: reg-usb1-vbus {
                 compatible = "regulator-fixed";
                 regulator-name = "usb1-vbus";
@@ -82,6 +107,10 @@
         };
 };
 
+&de {
+        status = "okay";
+};
+
 &ehci0 {
         /* Terminus Tech FE 1.1s 4-port USB 2.0 hub here */
         status = "okay";
@@ -100,6 +129,16 @@
         status = "okay";
 };
 
+&hdmi {
+        status = "okay";
+};
+
+&hdmi_out {
+        hdmi_out_con: endpoint {
+                remote-endpoint = <&hdmi_con_in>;
+        };
+};
+
 &mdio {
         rgmii_phy: ethernet-phy@1 {
                 compatible = "ethernet-phy-ieee802.3-c22";
@@ -112,8 +151,7 @@
         pinctrl-0 = <&mmc0_pins>;
         vmmc-supply = <&reg_dcdc1>;
         bus-width = <4>;
-        cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
-        cd-inverted;
+        cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
index 6da08cd0e107..88decb0747ac 100644
--- a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
@@ -176,8 +176,7 @@
         pinctrl-0 = <&mmc0_pins>;
         vmmc-supply = <&reg_dcdc1>;
         bus-width = <4>;
-        cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
-        cd-inverted;
+        cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index 511fca491fe8..1537ce148cc1 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -128,6 +128,14 @@
         };
 };
 
+&cpu0 {
+        cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu100 {
+        cpu-supply = <&reg_dcdc3>;
+};
+
 &de {
         status = "okay";
 };
@@ -231,6 +239,10 @@
 
 #include "axp81x.dtsi"
 
+&battery_power_supply {
+        status = "okay";
+};
+
 &reg_aldo1 {
         regulator-min-microvolt = <1800000>;
         regulator-max-microvolt = <1800000>;
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 7f4955a5fab7..568307639be8 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -60,51 +60,63 @@
                 #address-cells = <1>;
                 #size-cells = <0>;
 
-                cpu@0 {
+                cpu0: cpu@0 {
+                        clocks = <&ccu CLK_C0CPUX>;
+                        clock-names = "cpu";
                         compatible = "arm,cortex-a7";
                         device_type = "cpu";
+                        operating-points-v2 = <&cpu0_opp_table>;
                         reg = <0>;
                 };
 
                 cpu@1 {
                         compatible = "arm,cortex-a7";
                         device_type = "cpu";
+                        operating-points-v2 = <&cpu0_opp_table>;
                         reg = <1>;
                 };
 
                 cpu@2 {
                         compatible = "arm,cortex-a7";
                         device_type = "cpu";
+                        operating-points-v2 = <&cpu0_opp_table>;
                         reg = <2>;
                 };
 
                 cpu@3 {
                         compatible = "arm,cortex-a7";
                         device_type = "cpu";
+                        operating-points-v2 = <&cpu0_opp_table>;
                         reg = <3>;
                 };
 
-                cpu@100 {
+                cpu100: cpu@100 {
+                        clocks = <&ccu CLK_C1CPUX>;
+                        clock-names = "cpu";
                         compatible = "arm,cortex-a7";
                         device_type = "cpu";
+                        operating-points-v2 = <&cpu1_opp_table>;
                         reg = <0x100>;
                 };
 
                 cpu@101 {
                         compatible = "arm,cortex-a7";
                         device_type = "cpu";
+                        operating-points-v2 = <&cpu1_opp_table>;
                         reg = <0x101>;
                 };
 
                 cpu@102 {
                         compatible = "arm,cortex-a7";
                         device_type = "cpu";
+                        operating-points-v2 = <&cpu1_opp_table>;
                         reg = <0x102>;
                 };
 
                 cpu@103 {
                         compatible = "arm,cortex-a7";
                         device_type = "cpu";
+                        operating-points-v2 = <&cpu1_opp_table>;
                         reg = <0x103>;
                 };
         };
@@ -155,7 +167,7 @@
 
         de: display-engine {
                 compatible = "allwinner,sun8i-a83t-display-engine";
-                allwinner,pipelines = <&mixer0>;
+                allwinner,pipelines = <&mixer0>, <&mixer1>;
                 status = "disabled";
         };
 
@@ -164,6 +176,112 @@
                 device_type = "memory";
         };
 
+        cpu0_opp_table: opp_table0 {
+                compatible = "operating-points-v2";
+                opp-shared;
+
+                opp-480000000 {
+                        opp-hz = /bits/ 64 <480000000>;
+                        opp-microvolt = <840000>;
+                        clock-latency-ns = <244144>; /* 8 32k periods */
+                };
+
+                opp-600000000 {
+                        opp-hz = /bits/ 64 <600000000>;
+                        opp-microvolt = <840000>;
+                        clock-latency-ns = <244144>; /* 8 32k periods */
+                };
+
+                opp-720000000 {
+                        opp-hz = /bits/ 64 <720000000>;
+                        opp-microvolt = <840000>;
+                        clock-latency-ns = <244144>; /* 8 32k periods */
+                };
+
+                opp-864000000 {
+                        opp-hz = /bits/ 64 <864000000>;
+                        opp-microvolt = <840000>;
+                        clock-latency-ns = <244144>; /* 8 32k periods */
+                };
+
+                opp-912000000 {
+                        opp-hz = /bits/ 64 <912000000>;
+                        opp-microvolt = <840000>;
+                        clock-latency-ns = <244144>; /* 8 32k periods */
+                };
+
+                opp-1008000000 {
+                        opp-hz = /bits/ 64 <1008000000>;
+                        opp-microvolt = <840000>;
+                        clock-latency-ns = <244144>; /* 8 32k periods */
+                };
+
+                opp-1128000000 {
+                        opp-hz = /bits/ 64 <1128000000>;
+                        opp-microvolt = <840000>;
+                        clock-latency-ns = <244144>; /* 8 32k periods */
+                };
+
+                opp-1200000000 {
+                        opp-hz = /bits/ 64 <1200000000>;
+                        opp-microvolt = <840000>;
+                        clock-latency-ns = <244144>; /* 8 32k periods */
+                };
+        };
+
+        cpu1_opp_table: opp_table1 {
+                compatible = "operating-points-v2";
+                opp-shared;
+
+                opp-480000000 {
+                        opp-hz = /bits/ 64 <480000000>;
+                        opp-microvolt = <840000>;
+                        clock-latency-ns = <244144>; /* 8 32k periods */
+                };
+
+                opp-600000000 {
+                        opp-hz = /bits/ 64 <600000000>;
+                        opp-microvolt = <840000>;
+                        clock-latency-ns = <244144>; /* 8 32k periods */
+                };
+
+                opp-720000000 {
+                        opp-hz = /bits/ 64 <720000000>;
+                        opp-microvolt = <840000>;
+                        clock-latency-ns = <244144>; /* 8 32k periods */
+                };
+
+                opp-864000000 {
+                        opp-hz = /bits/ 64 <864000000>;
+                        opp-microvolt = <840000>;
+                        clock-latency-ns = <244144>; /* 8 32k periods */
+                };
+
+                opp-912000000 {
+                        opp-hz = /bits/ 64 <912000000>;
+                        opp-microvolt = <840000>;
+                        clock-latency-ns = <244144>; /* 8 32k periods */
+                };
+
+                opp-1008000000 {
+                        opp-hz = /bits/ 64 <1008000000>;
+                        opp-microvolt = <840000>;
+                        clock-latency-ns = <244144>; /* 8 32k periods */
+                };
+
+                opp-1128000000 {
+                        opp-hz = /bits/ 64 <1128000000>;
+                        opp-microvolt = <840000>;
+                        clock-latency-ns = <244144>; /* 8 32k periods */
+                };
+
+                opp-1200000000 {
+                        opp-hz = /bits/ 64 <1200000000>;
+                        opp-microvolt = <840000>;
+                        clock-latency-ns = <244144>; /* 8 32k periods */
+                };
+        };
+
         soc {
                 compatible = "simple-bus";
                 #address-cells = <1>;
@@ -208,6 +326,29 @@
                         };
                 };
 
+                mixer1: mixer@1200000 {
+                        compatible = "allwinner,sun8i-a83t-de2-mixer-1";
+                        reg = <0x01200000 0x100000>;
+                        clocks = <&display_clocks CLK_BUS_MIXER1>,
+                                 <&display_clocks CLK_MIXER1>;
+                        clock-names = "bus",
+                                      "mod";
+                        resets = <&display_clocks RST_WB>;
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                mixer1_out: port@1 {
+                                        reg = <1>;
+
+                                        mixer1_out_tcon1: endpoint {
+                                                remote-endpoint = <&tcon1_in_mixer1>;
+                                        };
+                                };
+                        };
+                };
+
                 syscon: syscon@1c00000 {
                         compatible = "allwinner,sun8i-a83t-system-controller",
                                 "syscon";
@@ -256,6 +397,40 @@
                         };
                 };
 
+                tcon1: lcd-controller@1c0d000 {
+                        compatible = "allwinner,sun8i-a83t-tcon-tv";
+                        reg = <0x01c0d000 0x1000>;
+                        interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
+                        clock-names = "ahb", "tcon-ch1";
+                        resets = <&ccu RST_BUS_TCON1>;
+                        reset-names = "lcd";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                tcon1_in: port@0 {
+                                        reg = <0>;
+
+                                        tcon1_in_mixer1: endpoint {
+                                                remote-endpoint = <&mixer1_out_tcon1>;
+                                        };
+                                };
+
+                                tcon1_out: port@1 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <1>;
+
+                                        tcon1_out_hdmi: endpoint@1 {
+                                                reg = <1>;
+                                                remote-endpoint = <&hdmi_in_tcon1>;
+                                        };
+                                };
+                        };
+                };
+
                 mmc0: mmc@1c0f000 {
                         compatible = "allwinner,sun8i-a83t-mmc",
                                      "allwinner,sun7i-a20-mmc";
@@ -427,6 +602,11 @@
                                 drive-strength = <40>;
                         };
 
+                        hdmi_pins: hdmi-pins {
+                                pins = "PH6", "PH7", "PH8";
+                                function = "hdmi";
+                        };
+
                         i2c0_pins: i2c0-pins {
                                 pins = "PH0", "PH1";
                                 function = "i2c0";
@@ -685,6 +865,50 @@
                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
                 };
 
+                hdmi: hdmi@1ee0000 {
+                        compatible = "allwinner,sun8i-a83t-dw-hdmi";
+                        reg = <0x01ee0000 0x10000>;
+                        reg-io-width = <1>;
+                        interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
+                                 <&ccu CLK_HDMI>;
+                        clock-names = "iahb", "isfr", "tmds";
+                        resets = <&ccu RST_BUS_HDMI1>;
+                        reset-names = "ctrl";
+                        phys = <&hdmi_phy>;
+                        phy-names = "hdmi-phy";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&hdmi_pins>;
+                        status = "disabled";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                hdmi_in: port@0 {
+                                        reg = <0>;
+
+                                        hdmi_in_tcon1: endpoint {
+                                                remote-endpoint = <&tcon1_out_hdmi>;
+                                        };
+                                };
+
+                                hdmi_out: port@1 {
+                                        reg = <1>;
+                                };
+                        };
+                };
+
+                hdmi_phy: hdmi-phy@1ef0000 {
+                        compatible = "allwinner,sun8i-a83t-hdmi-phy";
+                        reg = <0x01ef0000 0x10000>;
+                        clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
+                        clock-names = "bus", "mod";
+                        resets = <&ccu RST_BUS_HDMI0>;
+                        reset-names = "phy";
+                        #phy-cells = <0>;
+                };
+
                 r_intc: interrupt-controller@1f00c00 {
                         compatible = "allwinner,sun8i-a83t-r-intc",
                                      "allwinner,sun6i-a31-r-intc";
diff --git a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts
new file mode 100644
index 000000000000..7d01f9322658
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * Based on sun8i-h3-bananapi-m2-plus.dts, which is:
+ *   Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
+ */
+
+/dts-v1/;
+#include "sun8i-h3.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+        model = "Banana Pi BPI-M2-Zero";
+        compatible = "sinovoip,bpi-m2-zero", "allwinner,sun8i-h2-plus";
+
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+        };
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+
+                pwr_led {
+                        label = "bananapi-m2-zero:red:pwr";
+                        gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
+                        default-state = "on";
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                pinctrl-names = "default";
+
+                sw4 {
+                        label = "power";
+                        linux,code = <BTN_0>;
+                        gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+                };
+        };
+
+        wifi_pwrseq: wifi_pwrseq {
+                compatible = "mmc-pwrseq-simple";
+                pinctrl-names = "default";
+                reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
+        };
+};
+
+&ehci0 {
+        status = "okay";
+};
+
+&mmc0 {
+        vmmc-supply = <&reg_vcc3v3>;
+        bus-width = <4>;
+        /*
+         * On the production batch of this board the card detect GPIO is
+         * high active (card inserted), although on the early samples it's
+         * low active.
+         */
+        cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+        status = "okay";
+};
+
+&mmc1 {
+        vmmc-supply = <&reg_vcc3v3>;
+        vqmmc-supply = <&reg_vcc3v3>;
+        mmc-pwrseq = <&wifi_pwrseq>;
+        bus-width = <4>;
+        non-removable;
+        status = "okay";
+
+        brcmf: wifi@1 {
+                reg = <1>;
+                compatible = "brcm,bcm4329-fmac";
+                interrupt-parent = <&pio>;
+                interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */
+                interrupt-names = "host-wake";
+        };
+};
+
+&ohci0 {
+        status = "okay";
+};
+
+&uart0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart0_pins_a>;
+        status = "okay";
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+        status = "okay";
+};
+
+&usb_otg {
+        dr_mode = "otg";
+        status = "okay";
+};
+
+&usbphy {
+        usb0_id_det-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
+        /*
+         * There're two micro-USB connectors, one is power-only and another is
+         * OTG. The Vbus of these two connectors are connected together, so
+         * the external USB device will be powered just by the power input
+         * from the power-only USB port.
+         */
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts
index 112f09c67d67..3356f4210d45 100644
--- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts
+++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-r1.dts
@@ -68,6 +68,14 @@
         };
 };
 
+&spi0 {
+        status = "okay";
+
+        flash@0 {
+                compatible = "mxicy,mx25l12805d", "jedec,spi-nor";
+        };
+};
+
 &ohci1 {
         /*
          * RTL8152B USB-Ethernet adapter is connected to USB1,
diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
index 6713d0f2b3f4..0bc031fe4c56 100644
--- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
+++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
@@ -112,18 +112,13 @@
 };
 
 &mmc0 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mmc0_pins_a>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
-        cd-inverted;
+        cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
         status = "okay";
 };
 
 &mmc1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mmc1_pins_a>;
         vmmc-supply = <&reg_vcc_wifi>;
         mmc-pwrseq = <&wifi_pwrseq>;
         bus-width = <4>;
@@ -139,10 +134,6 @@
         };
 };
 
-&mmc1_pins_a {
-        bias-pull-up;
-};
-
 &ohci0 {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
index f1c3f1cc4d97..30540dc8e0c5 100644
--- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
@@ -61,6 +61,17 @@
                 stdout-path = "serial0:115200n8";
         };
 
+        connector {
+                compatible = "hdmi-connector";
+                type = "a";
+
+                port {
+                        hdmi_con_in: endpoint {
+                                remote-endpoint = <&hdmi_out_con>;
+                        };
+                };
+        };
+
         leds {
                 compatible = "gpio-leds";
                 pinctrl-names = "default";
@@ -100,6 +111,10 @@
         };
 };
 
+&de {
+        status = "okay";
+};
+
 &ehci0 {
         status = "okay";
 };
@@ -129,6 +144,16 @@
         };
 };
 
+&hdmi {
+        status = "okay";
+};
+
+&hdmi_out {
+        hdmi_out_con: endpoint {
+                remote-endpoint = <&hdmi_con_in>;
+        };
+};
+
 &ir {
         pinctrl-names = "default";
         pinctrl-0 = <&ir_pins_a>;
@@ -136,18 +161,13 @@
 };
 
 &mmc0 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
-        cd-inverted;
+        cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
         status = "okay";
 };
 
 &mmc1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mmc1_pins_a>;
         vmmc-supply = <&reg_vcc3v3>;
         vqmmc-supply = <&reg_vcc3v3>;
         mmc-pwrseq = <&wifi_pwrseq>;
diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
index 10da56e86ab8..cf1f970b0c6f 100644
--- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
@@ -61,6 +61,17 @@
                 stdout-path = "serial0:115200n8";
         };
 
+        connector {
+                compatible = "hdmi-connector";
+                type = "a";
+
+                port {
+                        hdmi_con_in: endpoint {
+                                remote-endpoint = <&hdmi_out_con>;
+                        };
+                };
+        };
+
         leds {
                 compatible = "gpio-leds";
 
@@ -100,6 +111,10 @@
         };
 };
 
+&de {
+        status = "okay";
+};
+
 &ehci0 {
         status = "okay";
 };
@@ -108,6 +123,16 @@
         status = "okay";
 };
 
+&hdmi {
+        status = "okay";
+};
+
+&hdmi_out {
+        hdmi_out_con: endpoint {
+                remote-endpoint = <&hdmi_con_in>;
+        };
+};
+
 &ir {
         pinctrl-names = "default";
         pinctrl-0 = <&ir_pins_a>;
@@ -115,18 +140,13 @@
 };
 
 &mmc0 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
-        cd-inverted;
+        cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
         status = "okay";
 };
 
 &mmc1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mmc1_pins_a>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
         non-removable;
diff --git a/arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts b/arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts
index d406571a0dd6..b20a710da7bc 100644
--- a/arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts
+++ b/arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts
@@ -23,6 +23,17 @@
                 stdout-path = "serial0:115200n8";
         };
 
+        connector {
+                compatible = "hdmi-connector";
+                type = "a";
+
+                port {
+                        hdmi_con_in: endpoint {
+                                remote-endpoint = <&hdmi_out_con>;
+                        };
+                };
+        };
+
         leds {
                 compatible = "gpio-leds";
 
@@ -120,6 +131,10 @@
         status = "okay";
 };
 
+&de {
+        status = "okay";
+};
+
 &ehci0 {
         status = "okay";
 };
@@ -143,6 +158,16 @@
         status = "okay";
 };
 
+&hdmi {
+        status = "okay";
+};
+
+&hdmi_out {
+        hdmi_out_con: endpoint {
+                remote-endpoint = <&hdmi_con_in>;
+        };
+};
+
 &ir {
         pinctrl-names = "default";
         pinctrl-0 = <&ir_pins_a>;
@@ -150,12 +175,9 @@
 };
 
 &mmc0 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mmc0_pins_a>;
         vmmc-supply = <&reg_vcc_io>;
         bus-width = <4>;
-        cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
-        cd-inverted;
+        cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
index a6e61915d648..65cba1050802 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
@@ -101,8 +101,6 @@
 };
 
 &mmc1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mmc1_pins_a>;
         vmmc-supply = <&reg_vcc3v3>;
         vqmmc-supply = <&reg_vcc3v3>;
         mmc-pwrseq = <&wifi_pwrseq>;
@@ -119,6 +117,16 @@
         };
 };
 
+&mmc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc2_8bit_pins>;
+        vmmc-supply = <&reg_vcc3v3>;
+        vqmmc-supply = <&reg_vcc3v3>;
+        bus-width = <8>;
+        non-removable;
+        status = "okay";
+};
+
 &ohci1 {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts
index c77fbca4f227..9412668bb888 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts
@@ -49,6 +49,21 @@
         aliases {
                 ethernet0 = &emac;
         };
+
+        connector {
+                compatible = "hdmi-connector";
+                type = "a";
+
+                port {
+                        hdmi_con_in: endpoint {
+                                remote-endpoint = <&hdmi_out_con>;
+                        };
+                };
+        };
+};
+
+&de {
+        status = "okay";
 };
 
 &ehci1 {
@@ -66,6 +81,16 @@
         status = "okay";
 };
 
+&hdmi {
+        status = "okay";
+};
+
+&hdmi_out {
+        hdmi_out_con: endpoint {
+                remote-endpoint = <&hdmi_con_in>;
+        };
+};
+
 &ir {
         pinctrl-names = "default";
         pinctrl-0 = <&ir_pins_a>;
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts
index 03ff6f8b93ff..6246d3eff39d 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts
@@ -72,16 +72,35 @@
                         gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */
                 };
         };
+
+        wifi_pwrseq: wifi_pwrseq {
+                compatible = "mmc-pwrseq-simple";
+                reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
+        };
 };
 
 &mmc0 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
-        cd-inverted;
+        cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+        status = "okay";
+};
+
+&mmc1 {
+        vmmc-supply = <&reg_vcc3v3>;
+        vqmmc-supply = <&reg_vcc3v3>;
+        mmc-pwrseq = <&wifi_pwrseq>;
+        bus-width = <4>;
+        non-removable;
         status = "okay";
+
+        brcmf: bcrmf@1 {
+                reg = <1>;
+                compatible = "brcm,bcm4329-fmac";
+                interrupt-parent = <&pio>;
+                interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */
+                interrupt-names = "host-wake";
+        };
 };
 
 &uart0 {
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi
index 7646e331bd29..f110ee382239 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi
@@ -95,10 +95,7 @@
 
 &mmc0 {
         bus-width = <4>;
-        cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
-        cd-inverted;
-        pinctrl-names = "default";
-        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+        cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
         status = "okay";
         vmmc-supply = <&reg_vcc3v3>;
 };
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
index b20be95b49d5..f1fc6bdca8be 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
@@ -62,6 +62,17 @@
                 stdout-path = "serial0:115200n8";
         };
 
+        connector {
+                compatible = "hdmi-connector";
+                type = "a";
+
+                port {
+                        hdmi_con_in: endpoint {
+                                remote-endpoint = <&hdmi_out_con>;
+                        };
+                };
+        };
+
         leds {
                 compatible = "gpio-leds";
                 pinctrl-names = "default";
@@ -114,6 +125,10 @@
         status = "okay";
 };
 
+&de {
+        status = "okay";
+};
+
 &ehci1 {
         status = "okay";
 };
@@ -125,6 +140,16 @@
         status = "okay";
 };
 
+&hdmi {
+        status = "okay";
+};
+
+&hdmi_out {
+        hdmi_out_con: endpoint {
+                remote-endpoint = <&hdmi_con_in>;
+        };
+};
+
 &ir {
         pinctrl-names = "default";
         pinctrl-0 = <&ir_pins_a>;
@@ -132,18 +157,13 @@
 };
 
 &mmc0 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
-        cd-inverted;
+        cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
         status = "okay";
 };
 
 &mmc1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mmc1_pins_a>;
         vmmc-supply = <&reg_vcc3v3>;
         mmc-pwrseq = <&wifi_pwrseq>;
         bus-width = <4>;
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts
index a70a1daf4e2c..476ae8e387ca 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts
@@ -61,6 +61,17 @@
                 stdout-path = "serial0:115200n8";
         };
 
+        connector {
+                compatible = "hdmi-connector";
+                type = "a";
+
+                port {
+                        hdmi_con_in: endpoint {
+                                remote-endpoint = <&hdmi_out_con>;
+                        };
+                };
+        };
+
         leds {
                 compatible = "gpio-leds";
                 pinctrl-names = "default";
@@ -91,6 +102,10 @@
         };
 };
 
+&de {
+        status = "okay";
+};
+
 &ehci1 {
         status = "okay";
 };
@@ -99,6 +114,16 @@
         status = "okay";
 };
 
+&hdmi {
+        status = "okay";
+};
+
+&hdmi_out {
+        hdmi_out_con: endpoint {
+                remote-endpoint = <&hdmi_con_in>;
+        };
+};
+
 &ir {
         pinctrl-names = "default";
         pinctrl-0 = <&ir_pins_a>;
@@ -106,18 +131,13 @@
 };
 
 &mmc0 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
-        cd-inverted;
+        cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
         status = "okay";
 };
 
 &mmc1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mmc1_pins_a>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
         non-removable;
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
index 82e5d28cd698..3328fe583c9b 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
@@ -60,6 +60,17 @@
                 stdout-path = "serial0:115200n8";
         };
 
+        connector {
+                compatible = "hdmi-connector";
+                type = "a";
+
+                port {
+                        hdmi_con_in: endpoint {
+                                remote-endpoint = <&hdmi_out_con>;
+                        };
+                };
+        };
+
         leds {
                 compatible = "gpio-leds";
                 pinctrl-names = "default";
@@ -90,6 +101,10 @@
         };
 };
 
+&de {
+        status = "okay";
+};
+
 &ehci0 {
         status = "okay";
 };
@@ -102,16 +117,22 @@
         phy-handle = <&int_mii_phy>;
         phy-mode = "mii";
         allwinner,leds-active-low;
+};
+
+&hdmi {
         status = "okay";
 };
 
+&hdmi_out {
+        hdmi_out_con: endpoint {
+                remote-endpoint = <&hdmi_con_in>;
+        };
+};
+
 &mmc0 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
-        cd-inverted;
+        cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
index a10281b455f5..71fb73208939 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
@@ -59,8 +59,6 @@
 };
 
 &mmc1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mmc1_pins_a>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
         non-removable;
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
index d22546df1b82..cea4d647ecbf 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
@@ -60,6 +60,17 @@
                 stdout-path = "serial0:115200n8";
         };
 
+        connector {
+                compatible = "hdmi-connector";
+                type = "a";
+
+                port {
+                        hdmi_con_in: endpoint {
+                                remote-endpoint = <&hdmi_out_con>;
+                        };
+                };
+        };
+
         leds {
                 compatible = "gpio-leds";
                 pinctrl-names = "default";
@@ -98,6 +109,10 @@
         status = "okay";
 };
 
+&de {
+        status = "okay";
+};
+
 &ehci0 {
         status = "okay";
 };
@@ -121,6 +136,16 @@
         status = "okay";
 };
 
+&hdmi {
+        status = "okay";
+};
+
+&hdmi_out {
+        hdmi_out_con: endpoint {
+                remote-endpoint = <&hdmi_con_in>;
+        };
+};
+
 &ir {
         pinctrl-names = "default";
         pinctrl-0 = <&ir_pins_a>;
@@ -128,12 +153,9 @@
 };
 
 &mmc0 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
-        cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
-        cd-inverted;
+        cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 8495deecedad..10da8ed7db81 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -79,6 +79,33 @@
                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
         };
+
+        soc {
+                mali: gpu@1c40000 {
+                        compatible = "allwinner,sun8i-h3-mali", "arm,mali-400";
+                        reg = <0x01c40000 0x10000>;
+                        interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "gp",
+                                          "gpmmu",
+                                          "pp0",
+                                          "ppmmu0",
+                                          "pp1",
+                                          "ppmmu1",
+                                          "pmu";
+                        clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
+                        clock-names = "bus", "core";
+                        resets = <&ccu RST_BUS_GPU>;
+
+                        assigned-clocks = <&ccu CLK_GPU>;
+                        assigned-clock-rates = <384000000>;
+                };
+        };
 };
 
 &ccu {
diff --git a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts
index eaf09666720d..0dbdb29a8fff 100644
--- a/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts
+++ b/arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts
@@ -150,8 +150,7 @@
         pinctrl-0 = <&mmc0_pins_a>;
         vmmc-supply = <&reg_dcdc1>;
         bus-width = <4>;
-        cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
-        cd-inverted;
+        cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
index 8c5efe2a9881..27d9ccd0ef2f 100644
--- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
+++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
@@ -164,8 +164,7 @@
 &mmc0 {
         vmmc-supply = <&reg_dcdc1>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; /* PH13 */
-        cd-inverted;
+        cd-gpios = <&pio 7 13 GPIO_ACTIVE_LOW>; /* PH13 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi
index d6bd15898db6..880096c7e252 100644
--- a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi
+++ b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi
@@ -85,8 +85,7 @@
         pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
         vmmc-supply = <&reg_dcdc1>;
         bus-width = <4>;
-        cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
-        cd-inverted;
+        cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */
         status = "okay";
 };
 
@@ -125,6 +124,14 @@
 
 #include "axp223.dtsi"
 
+&ac_power_supply {
+        status = "okay";
+};
+
+&battery_power_supply {
+        status = "okay";
+};
+
 &reg_aldo1 {
         regulator-always-on;
         regulator-min-microvolt = <3000000>;
diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
index fe16fc0eb518..a26d72c3f9b5 100644
--- a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
+++ b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts
@@ -150,8 +150,7 @@
 &mmc0 {
         vmmc-supply = <&reg_dcdc1>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; /* PH13 */
-        cd-inverted;
+        cd-gpios = <&pio 7 13 GPIO_ACTIVE_LOW>; /* PH13 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
index 4024639aa005..85da85faf869 100644
--- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
+++ b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
@@ -74,6 +74,52 @@
                 };
         };
 
+        vga-connector {
+                compatible = "vga-connector";
+                label = "vga";
+                ddc-i2c-bus = <&i2c3>;
+
+                port {
+                        vga_con_in: endpoint {
+                                remote-endpoint = <&vga_dac_out>;
+                        };
+                };
+        };
+
+        vga-dac {
+                compatible = "corpro,gm7123", "adi,adv7123", "dumb-vga-dac";
+                vdd-supply = <&reg_dcdc1>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@0 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                reg = <0>;
+
+                                vga_dac_in: endpoint@0 {
+                                        reg = <0>;
+                                        remote-endpoint = <&tcon0_out_vga>;
+                                };
+                        };
+
+                        port@1 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                reg = <1>;
+
+                                vga_dac_out: endpoint@0 {
+                                        reg = <0>;
+                                        remote-endpoint = <&vga_con_in>;
+                                };
+                        };
+                };
+        };
+
         wifi_pwrseq: wifi-pwrseq {
                 compatible = "mmc-pwrseq-simple";
                 clocks = <&ac100_rtc 1>;
@@ -83,13 +129,22 @@
         };
 };
 
+&de {
+        status = "okay";
+};
+
+&i2c3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c3_pins>;
+        status = "okay";
+};
+
 &mmc0 {
         pinctrl-names = "default";
         pinctrl-0 = <&mmc0_pins>;
         vmmc-supply = <&reg_dcdc1>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 18 GPIO_ACTIVE_HIGH>; /* PH18 */
-        cd-inverted;
+        cd-gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; /* PH18 */
         status = "okay";
 };
 
@@ -403,6 +458,18 @@
 
 #include "axp809.dtsi"
 
+&tcon0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&lcd0_rgb888_pins>;
+};
+
+&tcon0_out {
+        tcon0_out_vga: endpoint@0 {
+                reg = <0>;
+                remote-endpoint = <&vga_dac_in>;
+        };
+};
+
 &uart0 {
         pinctrl-names = "default";
         pinctrl-0 = <&uart0_ph_pins>;
diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts
index a9b807be99a0..58a199b0e494 100644
--- a/arch/arm/boot/dts/sun9i-a80-optimus.dts
+++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts
@@ -125,8 +125,7 @@
         pinctrl-0 = <&mmc0_pins>;
         vmmc-supply = <&reg_dcdc1>;
         bus-width = <4>;
-        cd-gpios = <&pio 7 18 GPIO_ACTIVE_HIGH>; /* PH8 */
-        cd-inverted;
+        cd-gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; /* PH8 */
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index 90eac0b2a193..25591d6883ef 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -63,48 +63,72 @@
                 cpu0: cpu@0 {
                         compatible = "arm,cortex-a7";
                         device_type = "cpu";
+                        cci-control-port = <&cci_control0>;
+                        clock-frequency = <12000000>;
+                        enable-method = "allwinner,sun9i-a80-smp";
                         reg = <0x0>;
                 };
 
                 cpu1: cpu@1 {
                         compatible = "arm,cortex-a7";
                         device_type = "cpu";
+                        cci-control-port = <&cci_control0>;
+                        clock-frequency = <12000000>;
+                        enable-method = "allwinner,sun9i-a80-smp";
                         reg = <0x1>;
                 };
 
                 cpu2: cpu@2 {
                         compatible = "arm,cortex-a7";
                         device_type = "cpu";
+                        cci-control-port = <&cci_control0>;
+                        clock-frequency = <12000000>;
+                        enable-method = "allwinner,sun9i-a80-smp";
                         reg = <0x2>;
                 };
 
                 cpu3: cpu@3 {
                         compatible = "arm,cortex-a7";
                         device_type = "cpu";
+                        cci-control-port = <&cci_control0>;
+                        clock-frequency = <12000000>;
+                        enable-method = "allwinner,sun9i-a80-smp";
                         reg = <0x3>;
                 };
 
                 cpu4: cpu@100 {
                         compatible = "arm,cortex-a15";
                         device_type = "cpu";
+                        cci-control-port = <&cci_control1>;
+                        clock-frequency = <18000000>;
+                        enable-method = "allwinner,sun9i-a80-smp";
                         reg = <0x100>;
                 };
 
                 cpu5: cpu@101 {
                         compatible = "arm,cortex-a15";
                         device_type = "cpu";
+                        cci-control-port = <&cci_control1>;
+                        clock-frequency = <18000000>;
+                        enable-method = "allwinner,sun9i-a80-smp";
                         reg = <0x101>;
                 };
 
                 cpu6: cpu@102 {
                         compatible = "arm,cortex-a15";
                         device_type = "cpu";
+                        cci-control-port = <&cci_control1>;
+                        clock-frequency = <18000000>;
+                        enable-method = "allwinner,sun9i-a80-smp";
                         reg = <0x102>;
                 };
 
                 cpu7: cpu@103 {
                         compatible = "arm,cortex-a15";
                         device_type = "cpu";
+                        cci-control-port = <&cci_control1>;
+                        clock-frequency = <18000000>;
+                        enable-method = "allwinner,sun9i-a80-smp";
                         reg = <0x103>;
                 };
         };
@@ -224,6 +248,12 @@
                 };
         };
 
+        de: display-engine {
+                compatible = "allwinner,sun9i-a80-display-engine";
+                allwinner,pipelines = <&fe0>, <&fe1>;
+                status = "disabled";
+        };
+
         soc {
                 compatible = "simple-bus";
                 #address-cells = <1>;
@@ -234,6 +264,25 @@
                  */
                 ranges = <0 0 0 0x20000000>;
 
+                sram_b: sram@20000 {
+                        /* 256 KiB secure SRAM at 0x20000 */
+                        compatible = "mmio-sram";
+                        reg = <0x00020000 0x40000>;
+
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x00020000 0x40000>;
+
+                        smp-sram@1000 {
+                                /*
+                                 * This is checked by BROM to determine if
+                                 * cpu0 should jump to SMP entry vector
+                                 */
+                                compatible = "allwinner,sun9i-a80-smp-sram";
+                                reg = <0x1000 0x8>;
+                        };
+                };
+
                 ehci0: usb@a00000 {
                         compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
                         reg = <0x00a00000 0x100>;
@@ -347,6 +396,11 @@
                         #reset-cells = <1>;
                 };
 
+                cpucfg@1700000 {
+                        compatible = "allwinner,sun9i-a80-cpucfg";
+                        reg = <0x01700000 0x100>;
+                };
+
                 mmc0: mmc@1c0f000 {
                         compatible = "allwinner,sun9i-a80-mmc";
                         reg = <0x01c0f000 0x1000>;
@@ -431,6 +485,36 @@
                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
                 };
 
+                cci: cci@1c90000 {
+                        compatible = "arm,cci-400";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x01c90000 0x1000>;
+                        ranges = <0x0 0x01c90000 0x10000>;
+
+                        cci_control0: slave-if@4000 {
+                                compatible = "arm,cci-400-ctrl-if";
+                                interface-type = "ace";
+                                reg = <0x4000 0x1000>;
+                        };
+
+                        cci_control1: slave-if@5000 {
+                                compatible = "arm,cci-400-ctrl-if";
+                                interface-type = "ace";
+                                reg = <0x5000 0x1000>;
+                        };
+
+                        pmu@9000 {
+                                 compatible = "arm,cci-400-pmu,r1";
+                                 reg = <0x9000 0x5000>;
+                                 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+                                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+                                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+                                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+                                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+                };
+
                 de_clocks: clock@3000000 {
                         compatible = "allwinner,sun9i-a80-de-clks";
                         reg = <0x03000000 0x30>;
@@ -445,6 +529,381 @@
                         #reset-cells = <1>;
                 };
 
+                fe0: display-frontend@3100000 {
+                        compatible = "allwinner,sun9i-a80-display-frontend";
+                        reg = <0x03100000 0x40000>;
+                        interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&de_clocks CLK_BUS_FE0>, <&de_clocks CLK_FE0>,
+                                 <&de_clocks CLK_DRAM_FE0>;
+                        clock-names = "ahb", "mod",
+                                      "ram";
+                        resets = <&de_clocks RST_FE0>;
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                fe0_out: port@1 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <1>;
+
+                                        fe0_out_deu0: endpoint@0 {
+                                                reg = <0>;
+                                                remote-endpoint = <&deu0_in_fe0>;
+                                        };
+                                };
+                        };
+                };
+
+                fe1: display-frontend@3140000 {
+                        compatible = "allwinner,sun9i-a80-display-frontend";
+                        reg = <0x03140000 0x40000>;
+                        interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&de_clocks CLK_BUS_FE1>, <&de_clocks CLK_FE1>,
+                                 <&de_clocks CLK_DRAM_FE1>;
+                        clock-names = "ahb", "mod",
+                                      "ram";
+                        resets = <&de_clocks RST_FE0>;
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                fe1_out: port@1 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <1>;
+
+                                        fe1_out_deu1: endpoint@0 {
+                                                reg = <0>;
+                                                remote-endpoint = <&deu1_in_fe1>;
+                                        };
+                                };
+                        };
+                };
+
+                be0: display-backend@3200000 {
+                        compatible = "allwinner,sun9i-a80-display-backend";
+                        reg = <0x03200000 0x40000>;
+                        interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&de_clocks CLK_BUS_BE0>, <&de_clocks CLK_BE0>,
+                                 <&de_clocks CLK_DRAM_BE0>;
+                        clock-names = "ahb", "mod",
+                                      "ram";
+                        resets = <&de_clocks RST_BE0>;
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                be0_in: port@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <0>;
+
+                                        be0_in_deu0: endpoint@0 {
+                                                reg = <0>;
+                                                remote-endpoint = <&deu0_out_be0>;
+                                        };
+
+                                        be0_in_deu1: endpoint@1 {
+                                                reg = <1>;
+                                                remote-endpoint = <&deu1_out_be0>;
+                                        };
+                                };
+
+                                be0_out: port@1 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <1>;
+
+                                        be0_out_drc0: endpoint@0 {
+                                                reg = <0>;
+                                                remote-endpoint = <&drc0_in_be0>;
+                                        };
+                                };
+                        };
+                };
+
+                be1: display-backend@3240000 {
+                        compatible = "allwinner,sun9i-a80-display-backend";
+                        reg = <0x03240000 0x40000>;
+                        interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&de_clocks CLK_BUS_BE1>, <&de_clocks CLK_BE1>,
+                                 <&de_clocks CLK_DRAM_BE1>;
+                        clock-names = "ahb", "mod",
+                                      "ram";
+                        resets = <&de_clocks RST_BE1>;
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                be1_in: port@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <0>;
+
+                                        be1_in_deu0: endpoint@0 {
+                                                reg = <0>;
+                                                remote-endpoint = <&deu0_out_be1>;
+                                        };
+
+                                        be1_in_deu1: endpoint@1 {
+                                                reg = <1>;
+                                                remote-endpoint = <&deu1_out_be1>;
+                                        };
+                                };
+
+                                be1_out: port@1 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <1>;
+
+                                        be1_out_drc1: endpoint@0 {
+                                                reg = <0>;
+                                                remote-endpoint = <&drc1_in_be1>;
+                                        };
+                                };
+                        };
+                };
+
+                deu0: deu@3300000 {
+                        compatible = "allwinner,sun9i-a80-deu";
+                        reg = <0x03300000 0x40000>;
+                        interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&de_clocks CLK_BUS_DEU0>,
+                                 <&de_clocks CLK_IEP_DEU0>,
+                                 <&de_clocks CLK_DRAM_DEU0>;
+                        clock-names = "ahb",
+                                      "mod",
+                                      "ram";
+                        resets = <&de_clocks RST_DEU0>;
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                deu0_in: port@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <0>;
+
+                                        deu0_in_fe0: endpoint@0 {
+                                                reg = <0>;
+                                                remote-endpoint = <&fe0_out_deu0>;
+                                        };
+                                };
+
+                                deu0_out: port@1 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <1>;
+
+                                        deu0_out_be0: endpoint@0 {
+                                                reg = <0>;
+                                                remote-endpoint = <&be0_in_deu0>;
+                                        };
+
+                                        deu0_out_be1: endpoint@1 {
+                                                reg = <1>;
+                                                remote-endpoint = <&be1_in_deu0>;
+                                        };
+                                };
+                        };
+                };
+
+                deu1: deu@3340000 {
+                        compatible = "allwinner,sun9i-a80-deu";
+                        reg = <0x03340000 0x40000>;
+                        interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&de_clocks CLK_BUS_DEU1>,
+                                 <&de_clocks CLK_IEP_DEU1>,
+                                 <&de_clocks CLK_DRAM_DEU1>;
+                        clock-names = "ahb",
+                                      "mod",
+                                      "ram";
+                        resets = <&de_clocks RST_DEU1>;
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                deu1_in: port@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <0>;
+
+                                        deu1_in_fe1: endpoint@0 {
+                                                reg = <0>;
+                                                remote-endpoint = <&fe1_out_deu1>;
+                                        };
+                                };
+
+                                deu1_out: port@1 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <1>;
+
+                                        deu1_out_be0: endpoint@0 {
+                                                reg = <0>;
+                                                remote-endpoint = <&be0_in_deu1>;
+                                        };
+
+                                        deu1_out_be1: endpoint@1 {
+                                                reg = <1>;
+                                                remote-endpoint = <&be1_in_deu1>;
+                                        };
+                                };
+                        };
+                };
+
+                drc0: drc@3400000 {
+                        compatible = "allwinner,sun9i-a80-drc";
+                        reg = <0x03400000 0x40000>;
+                        interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&de_clocks CLK_BUS_DRC0>,
+                                 <&de_clocks CLK_IEP_DRC0>,
+                                 <&de_clocks CLK_DRAM_DRC0>;
+                        clock-names = "ahb",
+                                      "mod",
+                                      "ram";
+                        resets = <&de_clocks RST_DRC0>;
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                drc0_in: port@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <0>;
+
+                                        drc0_in_be0: endpoint@0 {
+                                                reg = <0>;
+                                                remote-endpoint = <&be0_out_drc0>;
+                                        };
+                                };
+
+                                drc0_out: port@1 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <1>;
+
+                                        drc0_out_tcon0: endpoint@0 {
+                                                reg = <0>;
+                                                remote-endpoint = <&tcon0_in_drc0>;
+                                        };
+                                };
+                        };
+                };
+
+                drc1: drc@3440000 {
+                        compatible = "allwinner,sun9i-a80-drc";
+                        reg = <0x03440000 0x40000>;
+                        interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&de_clocks CLK_BUS_DRC1>,
+                                 <&de_clocks CLK_IEP_DRC1>,
+                                 <&de_clocks CLK_DRAM_DRC1>;
+                        clock-names = "ahb",
+                                      "mod",
+                                      "ram";
+                        resets = <&de_clocks RST_DRC1>;
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                drc1_in: port@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <0>;
+
+                                        drc1_in_be1: endpoint@0 {
+                                                reg = <0>;
+                                                remote-endpoint = <&be1_out_drc1>;
+                                        };
+                                };
+
+                                drc1_out: port@1 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <1>;
+
+                                        drc1_out_tcon1: endpoint@0 {
+                                                reg = <0>;
+                                                remote-endpoint = <&tcon1_in_drc1>;
+                                        };
+                                };
+                        };
+                };
+
+                tcon0: lcd-controller@3c00000 {
+                        compatible = "allwinner,sun9i-a80-tcon-lcd";
+                        reg = <0x03c00000 0x10000>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&ccu CLK_BUS_LCD0>, <&ccu CLK_LCD0>;
+                        clock-names = "ahb", "tcon-ch0";
+                        resets = <&ccu RST_BUS_LCD0>, <&ccu RST_BUS_EDP>;
+                        reset-names = "lcd", "edp";
+                        clock-output-names = "tcon0-pixel-clock";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                tcon0_in: port@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <0>;
+
+                                        tcon0_in_drc0: endpoint@0 {
+                                                reg = <0>;
+                                                remote-endpoint = <&drc0_out_tcon0>;
+                                        };
+                                };
+
+                                tcon0_out: port@1 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <1>;
+                                };
+                        };
+                };
+
+                tcon1: lcd-controller@3c10000 {
+                        compatible = "allwinner,sun9i-a80-tcon-tv";
+                        reg = <0x03c10000 0x10000>;
+                        interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&ccu CLK_BUS_LCD1>, <&ccu CLK_LCD1>;
+                        clock-names = "ahb", "tcon-ch1";
+                        resets = <&ccu RST_BUS_LCD1>, <&ccu RST_BUS_EDP>;
+                        reset-names = "lcd", "edp";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                tcon1_in: port@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <0>;
+
+                                        tcon1_in_drc1: endpoint@0 {
+                                                reg = <0>;
+                                                remote-endpoint = <&drc1_out_tcon1>;
+                                        };
+                                };
+
+                                tcon1_out: port@1 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <1>;
+                                };
+                        };
+                };
+
                 ccu: clock@6000000 {
                         compatible = "allwinner,sun9i-a80-ccu";
                         reg = <0x06000000 0x800>;
@@ -494,6 +953,17 @@
                                 function = "i2c3";
                         };
 
+                        lcd0_rgb888_pins: lcd0-rgb888-pins {
+                                pins = "PD0", "PD1", "PD2", "PD3",
+                                       "PD4", "PD5", "PD6", "PD7",
+                                       "PD8", "PD9", "PD10", "PD11",
+                                       "PD12", "PD13", "PD14", "PD15",
+                                       "PD16", "PD17", "PD18", "PD19",
+                                       "PD20", "PD21", "PD22", "PD23",
+                                       "PD24", "PD25", "PD26", "PD27";
+                                function = "lcd0";
+                        };
+
                         mmc0_pins: mmc0-pins {
                                 pins = "PF0", "PF1" ,"PF2", "PF3",
                                        "PF4", "PF5";
@@ -658,6 +1128,11 @@
                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
                 };
 
+                prcm@8001400 {
+                        compatible = "allwinner,sun9i-a80-prcm";
+                        reg = <0x08001400 0x200>;
+                };
+
                 apbs_rst: reset@80014b0 {
                         reg = <0x080014b0 0x4>;
                         compatible = "allwinner,sun6i-a31-clock-reset";
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 7a83b15225c7..1be1a02d6df2 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -105,6 +105,12 @@
                 };
         };
 
+        de: display-engine {
+                compatible = "allwinner,sun8i-h3-display-engine";
+                allwinner,pipelines = <&mixer0>;
+                status = "disabled";
+        };
+
         soc {
                 compatible = "simple-bus";
                 #address-cells = <1>;
@@ -123,6 +129,29 @@
                         #reset-cells = <1>;
                 };
 
+                mixer0: mixer@1100000 {
+                        compatible = "allwinner,sun8i-h3-de2-mixer-0";
+                        reg = <0x01100000 0x100000>;
+                        clocks = <&display_clocks CLK_BUS_MIXER0>,
+                                 <&display_clocks CLK_MIXER0>;
+                        clock-names = "bus",
+                                      "mod";
+                        resets = <&display_clocks RST_MIXER0>;
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                mixer0_out: port@1 {
+                                        reg = <1>;
+
+                                        mixer0_out_tcon0: endpoint {
+                                                remote-endpoint = <&tcon0_in_mixer0>;
+                                        };
+                                };
+                        };
+                };
+
                 syscon: syscon@1c00000 {
                         compatible = "allwinner,sun8i-h3-system-controller",
                                 "syscon";
@@ -138,9 +167,46 @@
                         #dma-cells = <1>;
                 };
 
+                tcon0: lcd-controller@1c0c000 {
+                        compatible = "allwinner,sun8i-h3-tcon-tv",
+                                     "allwinner,sun8i-a83t-tcon-tv";
+                        reg = <0x01c0c000 0x1000>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
+                        clock-names = "ahb", "tcon-ch1";
+                        resets = <&ccu RST_BUS_TCON0>;
+                        reset-names = "lcd";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                tcon0_in: port@0 {
+                                        reg = <0>;
+
+                                        tcon0_in_mixer0: endpoint {
+                                                remote-endpoint = <&mixer0_out_tcon0>;
+                                        };
+                                };
+
+                                tcon0_out: port@1 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <1>;
+
+                                        tcon0_out_hdmi: endpoint@1 {
+                                                reg = <1>;
+                                                remote-endpoint = <&hdmi_in_tcon0>;
+                                        };
+                                };
+                        };
+                };
+
                 mmc0: mmc@1c0f000 {
                         /* compatible and clocks are in per SoC .dtsi file */
                         reg = <0x01c0f000 0x1000>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmc0_pins>;
                         resets = <&ccu RST_BUS_MMC0>;
                         reset-names = "ahb";
                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
@@ -152,6 +218,8 @@
                 mmc1: mmc@1c10000 {
                         /* compatible and clocks are in per SoC .dtsi file */
                         reg = <0x01c10000 0x1000>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmc1_pins>;
                         resets = <&ccu RST_BUS_MMC1>;
                         reset-names = "ahb";
                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
@@ -348,7 +416,7 @@
                                 function = "i2c2";
                         };
 
-                        mmc0_pins_a: mmc0 {
+                        mmc0_pins: mmc0 {
                                 pins = "PF0", "PF1", "PF2", "PF3",
                                        "PF4", "PF5";
                                 function = "mmc0";
@@ -356,13 +424,7 @@
                                 bias-pull-up;
                         };
 
-                        mmc0_cd_pin: mmc0_cd_pin {
-                                pins = "PF6";
-                                function = "gpio_in";
-                                bias-pull-up;
-                        };
-
-                        mmc1_pins_a: mmc1 {
+                        mmc1_pins: mmc1 {
                                 pins = "PG0", "PG1", "PG2", "PG3",
                                        "PG4", "PG5";
                                 function = "mmc1";
@@ -684,6 +746,50 @@
                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
                 };
 
+                hdmi: hdmi@1ee0000 {
+                        compatible = "allwinner,sun8i-h3-dw-hdmi",
+                                     "allwinner,sun8i-a83t-dw-hdmi";
+                        reg = <0x01ee0000 0x10000>;
+                        reg-io-width = <1>;
+                        interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
+                                 <&ccu CLK_HDMI>;
+                        clock-names = "iahb", "isfr", "tmds";
+                        resets = <&ccu RST_BUS_HDMI1>;
+                        reset-names = "ctrl";
+                        phys = <&hdmi_phy>;
+                        phy-names = "hdmi-phy";
+                        status = "disabled";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                hdmi_in: port@0 {
+                                        reg = <0>;
+
+                                        hdmi_in_tcon0: endpoint {
+                                                remote-endpoint = <&tcon0_out_hdmi>;
+                                        };
+                                };
+
+                                hdmi_out: port@1 {
+                                        reg = <1>;
+                                };
+                        };
+                };
+
+                hdmi_phy: hdmi-phy@1ef0000 {
+                        compatible = "allwinner,sun8i-h3-hdmi-phy";
+                        reg = <0x01ef0000 0x10000>;
+                        clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
+                                 <&ccu 6>;
+                        clock-names = "bus", "mod", "pll-0";
+                        resets = <&ccu RST_BUS_HDMI0>;
+                        reset-names = "phy";
+                        #phy-cells = <0>;
+                };
+
                 rtc: rtc@1f00000 {
                         compatible = "allwinner,sun6i-a31-rtc";
                         reg = <0x01f00000 0x54>;
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index acd6cf51b15b..eafff16765b4 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -780,7 +780,7 @@
                         compatible = "realtek,rt5640";
                         reg = <0x1c>;
                         interrupt-parent = <&gpio>;
-                        interrupts = <TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>;
+                        interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_FALLING>;
                         realtek,ldo1-en-gpios =
                                 <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
                 };
diff --git a/arch/arm/boot/dts/tegra124-apalis-eval.dts b/arch/arm/boot/dts/tegra124-apalis-eval.dts
index ecffcd115fa7..a6ad759dddb4 100644
--- a/arch/arm/boot/dts/tegra124-apalis-eval.dts
+++ b/arch/arm/boot/dts/tegra124-apalis-eval.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright 2016 Toradex AG
+ * Copyright 2016-2018 Toradex AG
  *
  * This file is dual-licensed: you can use it either under the terms
  * of the GPL or the X11 license, at your option. Note that this dual
@@ -105,7 +105,7 @@
          */
         i2c@7000c000 {
                 status = "okay";
-                clock-frequency = <100000>;
+                clock-frequency = <400000>;
 
                 pcie-switch@58 {
                         compatible = "plx,pex8605";
@@ -114,7 +114,7 @@
 
                 /* M41T0M6 real time clock on carrier board */
                 rtc@68 {
-                        compatible = "st,m41t00";
+                        compatible = "st,m41t0";
                         reg = <0x68>;
                 };
         };
@@ -124,7 +124,6 @@
          */
         hdmi_ddc: i2c@7000c400 {
                 status = "okay";
-                clock-frequency = <100000>;
         };
 
         /*
@@ -133,7 +132,7 @@
          */
         i2c@7000c500 {
                 status = "okay";
-                clock-frequency = <100000>;
+                clock-frequency = <400000>;
         };
 
         /* I2C4 (DDC): unused */
@@ -226,9 +225,7 @@
 
         backlight: backlight {
                 compatible = "pwm-backlight";
-
-                /* BKL1_PWM */
-                pwms = <&pwm 3 5000000>;
+                pwms = <&pwm 3 5000000>; /* BKL1_PWM */
                 brightness-levels = <255 231 223 207 191 159 127 0>;
                 default-brightness-level = <6>;
                 /* BKL1_ON */
@@ -276,3 +273,13 @@
                 vin-supply = <&reg_5v0>;
         };
 };
+
+&gpio {
+        /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */
+        pex_perst_n {
+                gpio-hog;
+                gpios = <TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
+                output-high;
+                line-name = "PEX_PERST_N";
+        };
+};
diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts
new file mode 100644
index 000000000000..8a8d5fa0ecd1
--- /dev/null
+++ b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts
@@ -0,0 +1,250 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2016-2018 Toradex AG
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "tegra124-apalis-v1.2.dtsi"
+
+/ {
+        model = "Toradex Apalis TK1 on Apalis Evaluation Board";
+        compatible = "toradex,apalis-tk1-v1.2-eval", "toradex,apalis-tk1-eval",
+                     "toradex,apalis-tk1", "nvidia,tegra124";
+
+        aliases {
+                rtc0 = "/i2c@7000c000/rtc@68";
+                rtc1 = "/i2c@7000d000/pmic@40";
+                rtc2 = "/rtc@7000e000";
+                serial0 = &uarta;
+                serial1 = &uartb;
+                serial2 = &uartc;
+                serial3 = &uartd;
+        };
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+
+        pcie@1003000 {
+                pci@1,0 {
+                        status = "okay";
+                };
+        };
+
+        host1x@50000000 {
+                hdmi@54280000 {
+                        status = "okay";
+                };
+        };
+
+        /* Apalis UART1 */
+        serial@70006000 {
+                status = "okay";
+        };
+
+        /* Apalis UART2 */
+        serial@70006040 {
+                status = "okay";
+        };
+
+        /* Apalis UART3 */
+        serial@70006200 {
+                status = "okay";
+        };
+
+        /* Apalis UART4 */
+        serial@70006300 {
+                status = "okay";
+        };
+
+        pwm@7000a000 {
+                status = "okay";
+        };
+
+        /*
+         * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier
+         * board)
+         */
+        i2c@7000c000 {
+                status = "okay";
+                clock-frequency = <400000>;
+
+                pcie-switch@58 {
+                        compatible = "plx,pex8605";
+                        reg = <0x58>;
+                };
+
+                /* M41T0M6 real time clock on carrier board */
+                rtc@68 {
+                        compatible = "st,m41t0";
+                        reg = <0x68>;
+                };
+        };
+
+        /* GEN2_I2C: unused */
+
+        /*
+         * CAM_I2C: I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor
+         * on carrier board)
+         */
+        i2c@7000c500 {
+                status = "okay";
+                clock-frequency = <400000>;
+        };
+
+        /*
+         * I2C4 (DDC): I2C4_SDA/SCL (DDC) on MXM3 pin 205/207
+         * (e.g. display EDID)
+         */
+        hdmi_ddc: i2c@7000c700 {
+                status = "okay";
+        };
+
+        /* SPI1: Apalis SPI1 */
+        spi@7000d400 {
+                status = "okay";
+                spi-max-frequency = <50000000>;
+
+                spidev0: spidev@0 {
+                        compatible = "spidev";
+                        reg = <0>;
+                        spi-max-frequency = <50000000>;
+                };
+        };
+
+        /* SPI4: Apalis SPI2 */
+        spi@7000da00 {
+                status = "okay";
+                spi-max-frequency = <50000000>;
+
+                spidev1: spidev@0 {
+                        compatible = "spidev";
+                        reg = <0>;
+                        spi-max-frequency = <50000000>;
+                };
+        };
+
+        /* Apalis Serial ATA */
+        sata@70020000 {
+                status = "okay";
+        };
+
+        hda@70030000 {
+                status = "okay";
+        };
+
+        usb@70090000 {
+                status = "okay";
+        };
+
+        /* Apalis MMC1 */
+        sdhci@700b0000 {
+                status = "okay";
+                /* MMC1_CD# */
+                cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
+                bus-width = <4>;
+                vqmmc-supply = <&vddio_sdmmc1>;
+        };
+
+        /* Apalis SD1 */
+        sdhci@700b0400 {
+                status = "okay";
+                /* SD1_CD# */
+                cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
+                bus-width = <4>;
+                vqmmc-supply = <&vddio_sdmmc3>;
+        };
+
+        /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */
+        usb@7d000000 {
+                status = "okay";
+                dr_mode = "otg";
+        };
+
+        usb-phy@7d000000 {
+                status = "okay";
+                vbus-supply = <&reg_usbo1_vbus>;
+        };
+
+        /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */
+        usb@7d004000 {
+                status = "okay";
+        };
+
+        usb-phy@7d004000 {
+                status = "okay";
+                vbus-supply = <&reg_usbh_vbus>;
+        };
+
+        /* EHCI instance 2: USB3_DP/N -> USBH4_DP/N */
+        usb@7d008000 {
+                status = "okay";
+        };
+
+        usb-phy@7d008000 {
+                status = "okay";
+                vbus-supply = <&reg_usbh_vbus>;
+        };
+
+        backlight: backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm 3 5000000>; /* BKL1_PWM */
+                brightness-levels = <255 231 223 207 191 159 127 0>;
+                default-brightness-level = <6>;
+                /* BKL1_ON */
+                enable-gpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_HIGH>;
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+
+                wakeup {
+                        label = "WAKE1_MICO";
+                        gpios = <&gpio TEGRA_GPIO(DD, 3) GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_WAKEUP>;
+                        debounce-interval = <10>;
+                        wakeup-source;
+                };
+        };
+
+        reg_5v0: regulator-5v0 {
+                compatible = "regulator-fixed";
+                regulator-name = "5V_SW";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+        };
+
+        /* USBO1_EN */
+        reg_usbo1_vbus: regulator-usbo1-vbus {
+                compatible = "regulator-fixed";
+                regulator-name = "VCC_USBO1";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+                vin-supply = <&reg_5v0>;
+        };
+
+        /* USBH_EN */
+        reg_usbh_vbus: regulator-usbh-vbus {
+                compatible = "regulator-fixed";
+                regulator-name = "VCC_USBH(2A|2C|2D|3|4)";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                gpio = <&gpio TEGRA_GPIO(T, 6) GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+                vin-supply = <&reg_5v0>;
+        };
+};
+
+&gpio {
+        /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */
+        pex_perst_n {
+                gpio-hog;
+                gpios = <TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
+                output-high;
+                line-name = "PEX_PERST_N";
+        };
+};
diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
new file mode 100644
index 000000000000..bb67edb016c5
--- /dev/null
+++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
@@ -0,0 +1,2052 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2016-2018 Toradex AG
+ */
+
+#include "tegra124.dtsi"
+#include "tegra124-apalis-emc.dtsi"
+
+/*
+ * Toradex Apalis TK1 Module Device Tree
+ * Compatible for Revisions 2GB: V1.2A
+ */
+/ {
+        model = "Toradex Apalis TK1";
+        compatible = "toradex,apalis-tk1-v1.2", "toradex,apalis-tk1",
+                     "nvidia,tegra124";
+
+        memory {
+                reg = <0x0 0x80000000 0x0 0x80000000>;
+        };
+
+        pcie@1003000 {
+                status = "okay";
+                avddio-pex-supply = <&vdd_1v05>;
+                avdd-pex-pll-supply = <&vdd_1v05>;
+                avdd-pll-erefe-supply = <&avdd_1v05>;
+                dvddio-pex-supply = <&vdd_1v05>;
+                hvdd-pex-pll-e-supply = <&reg_3v3>;
+                hvdd-pex-supply = <&reg_3v3>;
+                vddio-pex-ctl-supply = <&reg_3v3>;
+
+                /* Apalis PCIe (additional lane Apalis type specific) */
+                pci@1,0 {
+                        /* PCIE1_RX/TX and TS_DIFF1/2 */
+                        phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>,
+                               <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>;
+                        phy-names = "pcie-0", "pcie-1";
+                };
+
+                /* I210 Gigabit Ethernet Controller (On-module) */
+                pci@2,0 {
+                        phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
+                        phy-names = "pcie-0";
+                        status = "okay";
+                };
+        };
+
+        host1x@50000000 {
+                hdmi@54280000 {
+                        pll-supply = <&reg_1v05_avdd_hdmi_pll>;
+                        vdd-supply = <&reg_3v3_avdd_hdmi>;
+                        nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+                        nvidia,hpd-gpio =
+                                <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
+                };
+        };
+
+        gpu@0,57000000 {
+                /*
+                 * Node left disabled on purpose - the bootloader will enable
+                 * it after having set the VPR up
+                 */
+                vdd-supply = <&vdd_gpu>;
+        };
+
+        pinmux: pinmux@70000868 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&state_default>;
+
+                state_default: pinmux {
+                        /* Analogue Audio (On-module) */
+                        dap3_fs_pp0 {
+                                nvidia,pins = "dap3_fs_pp0";
+                                nvidia,function = "i2s2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap3_din_pp1 {
+                                nvidia,pins = "dap3_din_pp1";
+                                nvidia,function = "i2s2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap3_dout_pp2 {
+                                nvidia,pins = "dap3_dout_pp2";
+                                nvidia,function = "i2s2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap3_sclk_pp3 {
+                                nvidia,pins = "dap3_sclk_pp3";
+                                nvidia,function = "i2s2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap_mclk1_pw4 {
+                                nvidia,pins = "dap_mclk1_pw4";
+                                nvidia,function = "extperiph1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis BKL1_ON */
+                        pbb5 {
+                                nvidia,pins = "pbb5";
+                                nvidia,function = "vgp5";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis BKL1_PWM */
+                        pu6 {
+                                nvidia,pins = "pu6";
+                                nvidia,function = "pwm3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis CAM1_MCLK */
+                        cam_mclk_pcc0 {
+                                nvidia,pins = "cam_mclk_pcc0";
+                                nvidia,function = "vi_alt3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis Digital Audio */
+                        dap2_fs_pa2 {
+                                nvidia,pins = "dap2_fs_pa2";
+                                nvidia,function = "hda";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap2_sclk_pa3 {
+                                nvidia,pins = "dap2_sclk_pa3";
+                                nvidia,function = "hda";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap2_din_pa4 {
+                                nvidia,pins = "dap2_din_pa4";
+                                nvidia,function = "hda";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap2_dout_pa5 {
+                                nvidia,pins = "dap2_dout_pa5";
+                                nvidia,function = "hda";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pbb3 { /* DAP1_RESET */
+                                nvidia,pins = "pbb3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        clk3_out_pee0 {
+                                nvidia,pins = "clk3_out_pee0";
+                                nvidia,function = "extperiph3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis GPIO */
+                        usb_vbus_en0_pn4 {
+                                nvidia,pins = "usb_vbus_en0_pn4";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+                        usb_vbus_en1_pn5 {
+                                nvidia,pins = "usb_vbus_en1_pn5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+                        pex_l0_rst_n_pdd1 {
+                                nvidia,pins = "pex_l0_rst_n_pdd1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pex_l0_clkreq_n_pdd2 {
+                                nvidia,pins = "pex_l0_clkreq_n_pdd2";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pex_l1_rst_n_pdd5 {
+                                nvidia,pins = "pex_l1_rst_n_pdd5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pex_l1_clkreq_n_pdd6 {
+                                nvidia,pins = "pex_l1_clkreq_n_pdd6";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dp_hpd_pff0 {
+                                nvidia,pins = "dp_hpd_pff0";
+                                nvidia,function = "dp";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pff2 {
+                                nvidia,pins = "pff2";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        owr { /* PEX_L1_CLKREQ_N multiplexed GPIO6 */
+                                nvidia,pins = "owr";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis HDMI1_CEC */
+                        hdmi_cec_pee3 {
+                                nvidia,pins = "hdmi_cec_pee3";
+                                nvidia,function = "cec";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis HDMI1_HPD */
+                        hdmi_int_pn7 {
+                                nvidia,pins = "hdmi_int_pn7";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis I2C1 */
+                        gen1_i2c_scl_pc4 {
+                                nvidia,pins = "gen1_i2c_scl_pc4";
+                                nvidia,function = "i2c1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        gen1_i2c_sda_pc5 {
+                                nvidia,pins = "gen1_i2c_sda_pc5";
+                                nvidia,function = "i2c1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Apalis I2C3 (CAM) */
+                        cam_i2c_scl_pbb1 {
+                                nvidia,pins = "cam_i2c_scl_pbb1";
+                                nvidia,function = "i2c3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        cam_i2c_sda_pbb2 {
+                                nvidia,pins = "cam_i2c_sda_pbb2";
+                                nvidia,function = "i2c3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Apalis I2C4 (DDC) */
+                        ddc_scl_pv4 {
+                                nvidia,pins = "ddc_scl_pv4";
+                                nvidia,function = "i2c4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
+                        };
+                        ddc_sda_pv5 {
+                                nvidia,pins = "ddc_sda_pv5";
+                                nvidia,function = "i2c4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Apalis MMC1 */
+                        sdmmc1_cd_n_pv3 { /* CD# GPIO */
+                                nvidia,pins = "sdmmc1_wp_n_pv3";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        clk2_out_pw5 { /* D5 GPIO */
+                                nvidia,pins = "clk2_out_pw5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_dat3_py4 {
+                                nvidia,pins = "sdmmc1_dat3_py4";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_dat2_py5 {
+                                nvidia,pins = "sdmmc1_dat2_py5";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_dat1_py6 {
+                                nvidia,pins = "sdmmc1_dat1_py6";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_dat0_py7 {
+                                nvidia,pins = "sdmmc1_dat0_py7";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_clk_pz0 {
+                                nvidia,pins = "sdmmc1_clk_pz0";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_cmd_pz1 {
+                                nvidia,pins = "sdmmc1_cmd_pz1";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        clk2_req_pcc5 { /* D4 GPIO */
+                                nvidia,pins = "clk2_req_pcc5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_clk_lb_in_pee5 { /* D6 GPIO */
+                                nvidia,pins = "sdmmc3_clk_lb_in_pee5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        usb_vbus_en2_pff1 { /* D7 GPIO */
+                                nvidia,pins = "usb_vbus_en2_pff1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Apalis PWM */
+                        ph0 {
+                                nvidia,pins = "ph0";
+                                nvidia,function = "pwm0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ph1 {
+                                nvidia,pins = "ph1";
+                                nvidia,function = "pwm1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ph2 {
+                                nvidia,pins = "ph2";
+                                nvidia,function = "pwm2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        /* PWM3 active on pu6 being Apalis BKL1_PWM as well */
+                        ph3 {
+                                nvidia,pins = "ph3";
+                                nvidia,function = "pwm3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis SATA1_ACT# */
+                        dap1_dout_pn2 {
+                                nvidia,pins = "dap1_dout_pn2";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis SD1 */
+                        sdmmc3_clk_pa6 {
+                                nvidia,pins = "sdmmc3_clk_pa6";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_cmd_pa7 {
+                                nvidia,pins = "sdmmc3_cmd_pa7";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_dat3_pb4 {
+                                nvidia,pins = "sdmmc3_dat3_pb4";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_dat2_pb5 {
+                                nvidia,pins = "sdmmc3_dat2_pb5";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_dat1_pb6 {
+                                nvidia,pins = "sdmmc3_dat1_pb6";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_dat0_pb7 {
+                                nvidia,pins = "sdmmc3_dat0_pb7";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_cd_n_pv2 { /* CD# GPIO */
+                                nvidia,pins = "sdmmc3_cd_n_pv2";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Apalis SPDIF */
+                        spdif_out_pk5 {
+                                nvidia,pins = "spdif_out_pk5";
+                                nvidia,function = "spdif";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        spdif_in_pk6 {
+                                nvidia,pins = "spdif_in_pk6";
+                                nvidia,function = "spdif";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Apalis SPI1 */
+                        ulpi_clk_py0 {
+                                nvidia,pins = "ulpi_clk_py0";
+                                nvidia,function = "spi1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_dir_py1 {
+                                nvidia,pins = "ulpi_dir_py1";
+                                nvidia,function = "spi1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ulpi_nxt_py2 {
+                                nvidia,pins = "ulpi_nxt_py2";
+                                nvidia,function = "spi1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_stp_py3 {
+                                nvidia,pins = "ulpi_stp_py3";
+                                nvidia,function = "spi1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis SPI2 */
+                        pg5 {
+                                nvidia,pins = "pg5";
+                                nvidia,function = "spi4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pg6 {
+                                nvidia,pins = "pg6";
+                                nvidia,function = "spi4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pg7 {
+                                nvidia,pins = "pg7";
+                                nvidia,function = "spi4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pi3 {
+                                nvidia,pins = "pi3";
+                                nvidia,function = "spi4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis UART1 */
+                        pb1 { /* DCD GPIO */
+                                nvidia,pins = "pb1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pk7 { /* RI GPIO */
+                                nvidia,pins = "pk7";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart1_txd_pu0 {
+                                nvidia,pins = "pu0";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart1_rxd_pu1 {
+                                nvidia,pins = "pu1";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart1_cts_n_pu2 {
+                                nvidia,pins = "pu2";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart1_rts_n_pu3 {
+                                nvidia,pins = "pu3";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart3_cts_n_pa1 { /* DSR GPIO */
+                                nvidia,pins = "uart3_cts_n_pa1";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart3_rts_n_pc0 { /* DTR GPIO */
+                                nvidia,pins = "uart3_rts_n_pc0";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis UART2 */
+                        uart2_txd_pc2 {
+                                nvidia,pins = "uart2_txd_pc2";
+                                nvidia,function = "irda";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart2_rxd_pc3 {
+                                nvidia,pins = "uart2_rxd_pc3";
+                                nvidia,function = "irda";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart2_cts_n_pj5 {
+                                nvidia,pins = "uart2_cts_n_pj5";
+                                nvidia,function = "uartb";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart2_rts_n_pj6 {
+                                nvidia,pins = "uart2_rts_n_pj6";
+                                nvidia,function = "uartb";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis UART3 */
+                        uart3_txd_pw6 {
+                                nvidia,pins = "uart3_txd_pw6";
+                                nvidia,function = "uartc";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart3_rxd_pw7 {
+                                nvidia,pins = "uart3_rxd_pw7";
+                                nvidia,function = "uartc";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Apalis UART4 */
+                        uart4_rxd_pb0 {
+                                nvidia,pins = "pb0";
+                                nvidia,function = "uartd";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart4_txd_pj7 {
+                                nvidia,pins = "pj7";
+                                nvidia,function = "uartd";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis USBH_EN */
+                        gen2_i2c_sda_pt6 {
+                                nvidia,pins = "gen2_i2c_sda_pt6";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis USBH_OC# */
+                        pbb0 {
+                                nvidia,pins = "pbb0";
+                                nvidia,function = "vgp6";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Apalis USBO1_EN */
+                        gen2_i2c_scl_pt5 {
+                                nvidia,pins = "gen2_i2c_scl_pt5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis USBO1_OC# */
+                        pbb4 {
+                                nvidia,pins = "pbb4";
+                                nvidia,function = "vgp4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Apalis WAKE1_MICO */
+                        pex_wake_n_pdd3 {
+                                nvidia,pins = "pex_wake_n_pdd3";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* CORE_PWR_REQ */
+                        core_pwr_req {
+                                nvidia,pins = "core_pwr_req";
+                                nvidia,function = "pwron";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* CPU_PWR_REQ */
+                        cpu_pwr_req {
+                                nvidia,pins = "cpu_pwr_req";
+                                nvidia,function = "cpu";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* DVFS */
+                        dvfs_pwm_px0 {
+                                nvidia,pins = "dvfs_pwm_px0";
+                                nvidia,function = "cldvfs";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dvfs_clk_px2 {
+                                nvidia,pins = "dvfs_clk_px2";
+                                nvidia,function = "cldvfs";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* eMMC */
+                        sdmmc4_dat0_paa0 {
+                                nvidia,pins = "sdmmc4_dat0_paa0";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat1_paa1 {
+                                nvidia,pins = "sdmmc4_dat1_paa1";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat2_paa2 {
+                                nvidia,pins = "sdmmc4_dat2_paa2";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat3_paa3 {
+                                nvidia,pins = "sdmmc4_dat3_paa3";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat4_paa4 {
+                                nvidia,pins = "sdmmc4_dat4_paa4";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat5_paa5 {
+                                nvidia,pins = "sdmmc4_dat5_paa5";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat6_paa6 {
+                                nvidia,pins = "sdmmc4_dat6_paa6";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat7_paa7 {
+                                nvidia,pins = "sdmmc4_dat7_paa7";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_clk_pcc4 {
+                                nvidia,pins = "sdmmc4_clk_pcc4";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_cmd_pt7 {
+                                nvidia,pins = "sdmmc4_cmd_pt7";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* JTAG_RTCK */
+                        jtag_rtck {
+                                nvidia,pins = "jtag_rtck";
+                                nvidia,function = "rtck";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* LAN_DEV_OFF# */
+                        ulpi_data5_po6 {
+                                nvidia,pins = "ulpi_data5_po6";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* LAN_RESET# */
+                        kb_row10_ps2 {
+                                nvidia,pins = "kb_row10_ps2";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* LAN_WAKE# */
+                        ulpi_data4_po5 {
+                                nvidia,pins = "ulpi_data4_po5";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* MCU_INT1# */
+                        pk2 {
+                                nvidia,pins = "pk2";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* MCU_INT2# */
+                        pj2 {
+                                nvidia,pins = "pj2";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* MCU_INT3# */
+                        pi5 {
+                                nvidia,pins = "pi5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* MCU_INT4# */
+                        pj0 {
+                                nvidia,pins = "pj0";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* MCU_RESET */
+                        pbb6 {
+                                nvidia,pins = "pbb6";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* MCU SPI */
+                        gpio_x4_aud_px4 {
+                                nvidia,pins = "gpio_x4_aud_px4";
+                                nvidia,function = "spi2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gpio_x5_aud_px5 {
+                                nvidia,pins = "gpio_x5_aud_px5";
+                                nvidia,function = "spi2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gpio_x6_aud_px6 { /* MCU_CS */
+                                nvidia,pins = "gpio_x6_aud_px6";
+                                nvidia,function = "spi2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gpio_x7_aud_px7 {
+                                nvidia,pins = "gpio_x7_aud_px7";
+                                nvidia,function = "spi2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gpio_w2_aud_pw2 { /* MCU_CSEZP */
+                                nvidia,pins = "gpio_w2_aud_pw2";
+                                nvidia,function = "spi2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* PMIC_CLK_32K */
+                        clk_32k_in {
+                                nvidia,pins = "clk_32k_in";
+                                nvidia,function = "clk";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* PMIC_CPU_OC_INT */
+                        clk_32k_out_pa0 {
+                                nvidia,pins = "clk_32k_out_pa0";
+                                nvidia,function = "soc";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* PWR_I2C */
+                        pwr_i2c_scl_pz6 {
+                                nvidia,pins = "pwr_i2c_scl_pz6";
+                                nvidia,function = "i2cpwr";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        pwr_i2c_sda_pz7 {
+                                nvidia,pins = "pwr_i2c_sda_pz7";
+                                nvidia,function = "i2cpwr";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* PWR_INT_N */
+                        pwr_int_n {
+                                nvidia,pins = "pwr_int_n";
+                                nvidia,function = "pmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* RESET_MOCI_CTRL */
+                        pu4 {
+                                nvidia,pins = "pu4";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* RESET_OUT_N */
+                        reset_out_n {
+                                nvidia,pins = "reset_out_n";
+                                nvidia,function = "reset_out_n";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* SHIFT_CTRL_DIR_IN */
+                        kb_row0_pr0 {
+                                nvidia,pins = "kb_row0_pr0";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row1_pr1 {
+                                nvidia,pins = "kb_row1_pr1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Configure level-shifter as output for HDA */
+                        kb_row11_ps3 {
+                                nvidia,pins = "kb_row11_ps3";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* SHIFT_CTRL_DIR_OUT */
+                        kb_col5_pq5 {
+                                nvidia,pins = "kb_col5_pq5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_col6_pq6 {
+                                nvidia,pins = "kb_col6_pq6";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_col7_pq7 {
+                                nvidia,pins = "kb_col7_pq7";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* SHIFT_CTRL_OE */
+                        kb_col0_pq0 {
+                                nvidia,pins = "kb_col0_pq0";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_col1_pq1 {
+                                nvidia,pins = "kb_col1_pq1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_col2_pq2 {
+                                nvidia,pins = "kb_col2_pq2";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_col4_pq4 {
+                                nvidia,pins = "kb_col4_pq4";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row2_pr2 {
+                                nvidia,pins = "kb_row2_pr2";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* GPIO_PI6 aka TMP451 ALERT#/THERM2# */
+                        pi6 {
+                                nvidia,pins = "pi6";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* TOUCH_INT */
+                        gpio_w3_aud_pw3 {
+                                nvidia,pins = "gpio_w3_aud_pw3";
+                                nvidia,function = "spi6";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        pc7 { /* NC */
+                                nvidia,pins = "pc7";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pg0 { /* NC */
+                                nvidia,pins = "pg0";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pg1 { /* NC */
+                                nvidia,pins = "pg1";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pg2 { /* NC */
+                                nvidia,pins = "pg2";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pg3 { /* NC */
+                                nvidia,pins = "pg3";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pg4 { /* NC */
+                                nvidia,pins = "pg4";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ph4 { /* NC */
+                                nvidia,pins = "ph4";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ph5 { /* NC */
+                                nvidia,pins = "ph5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ph6 { /* NC */
+                                nvidia,pins = "ph6";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ph7 { /* NC */
+                                nvidia,pins = "ph7";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pi0 { /* NC */
+                                nvidia,pins = "pi0";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pi1 { /* NC */
+                                nvidia,pins = "pi1";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pi2 { /* NC */
+                                nvidia,pins = "pi2";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pi4 { /* NC */
+                                nvidia,pins = "pi4";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pi7 { /* NC */
+                                nvidia,pins = "pi7";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pk0 { /* NC */
+                                nvidia,pins = "pk0";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pk1 { /* NC */
+                                nvidia,pins = "pk1";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pk3 { /* NC */
+                                nvidia,pins = "pk3";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pk4 { /* NC */
+                                nvidia,pins = "pk4";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap1_fs_pn0 { /* NC */
+                                nvidia,pins = "dap1_fs_pn0";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap1_din_pn1 { /* NC */
+                                nvidia,pins = "dap1_din_pn1";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap1_sclk_pn3 { /* NC */
+                                nvidia,pins = "dap1_sclk_pn3";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data7_po0 { /* NC */
+                                nvidia,pins = "ulpi_data7_po0";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data0_po1 { /* NC */
+                                nvidia,pins = "ulpi_data0_po1";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data1_po2 { /* NC */
+                                nvidia,pins = "ulpi_data1_po2";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data2_po3 { /* NC */
+                                nvidia,pins = "ulpi_data2_po3";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data3_po4 { /* NC */
+                                nvidia,pins = "ulpi_data3_po4";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data6_po7 { /* NC */
+                                nvidia,pins = "ulpi_data6_po7";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap4_fs_pp4 { /* NC */
+                                nvidia,pins = "dap4_fs_pp4";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap4_din_pp5 { /* NC */
+                                nvidia,pins = "dap4_din_pp5";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap4_dout_pp6 { /* NC */
+                                nvidia,pins = "dap4_dout_pp6";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap4_sclk_pp7 { /* NC */
+                                nvidia,pins = "dap4_sclk_pp7";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_col3_pq3 { /* NC */
+                                nvidia,pins = "kb_col3_pq3";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row3_pr3 { /* NC */
+                                nvidia,pins = "kb_row3_pr3";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row4_pr4 { /* NC */
+                                nvidia,pins = "kb_row4_pr4";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row5_pr5 { /* NC */
+                                nvidia,pins = "kb_row5_pr5";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row6_pr6 { /* NC */
+                                nvidia,pins = "kb_row6_pr6";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row7_pr7 { /* NC */
+                                nvidia,pins = "kb_row7_pr7";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row8_ps0 { /* NC */
+                                nvidia,pins = "kb_row8_ps0";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row9_ps1 { /* NC */
+                                nvidia,pins = "kb_row9_ps1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row12_ps4 { /* NC */
+                                nvidia,pins = "kb_row12_ps4";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row13_ps5 { /* NC */
+                                nvidia,pins = "kb_row13_ps5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row14_ps6 { /* NC */
+                                nvidia,pins = "kb_row14_ps6";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row15_ps7 { /* NC */
+                                nvidia,pins = "kb_row15_ps7";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row16_pt0 { /* NC */
+                                nvidia,pins = "kb_row16_pt0";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row17_pt1 { /* NC */
+                                nvidia,pins = "kb_row17_pt1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pu5 { /* NC */
+                                nvidia,pins = "pu5";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        /*
+                         * PCB Version Indication: V1.2 and later have GPIO_PV0
+                         * wired to GND, was NC before
+                         */
+                        pv0 {
+                                nvidia,pins = "pv0";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pv1 { /* NC */
+                                nvidia,pins = "pv1";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gpio_x1_aud_px1 { /* NC */
+                                nvidia,pins = "gpio_x1_aud_px1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gpio_x3_aud_px3 { /* NC */
+                                nvidia,pins = "gpio_x3_aud_px3";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pbb7 { /* NC */
+                                nvidia,pins = "pbb7";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pcc1 { /* NC */
+                                nvidia,pins = "pcc1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pcc2 { /* NC */
+                                nvidia,pins = "pcc2";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        clk3_req_pee1 { /* NC */
+                                nvidia,pins = "clk3_req_pee1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap_mclk1_req_pee2 { /* NC */
+                                nvidia,pins = "dap_mclk1_req_pee2";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        /*
+                         * Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output
+                         * driver enabled aka not tristated and input driver
+                         * enabled as well as it features some magic properties
+                         * even though the external loopback is disabled and the
+                         * internal loopback used as per
+                         * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
+                         * bits being set to 0xfffd according to the TRM!
+                         */
+                        sdmmc3_clk_lb_out_pee4 { /* NC */
+                                nvidia,pins = "sdmmc3_clk_lb_out_pee4";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                };
+        };
+
+        serial@70006040 {
+                compatible = "nvidia,tegra124-hsuart";
+        };
+
+        serial@70006200 {
+                compatible = "nvidia,tegra124-hsuart";
+        };
+
+        serial@70006300 {
+                compatible = "nvidia,tegra124-hsuart";
+        };
+
+        hdmi_ddc: i2c@7000c700 {
+                clock-frequency = <10000>;
+        };
+
+        /* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */
+        i2c@7000d000 {
+                status = "okay";
+                clock-frequency = <400000>;
+
+                /* SGTL5000 audio codec */
+                sgtl5000: codec@a {
+                        compatible = "fsl,sgtl5000";
+                        reg = <0x0a>;
+                        VDDA-supply = <&reg_3v3>;
+                        VDDIO-supply = <&vddio_1v8>;
+                        clocks = <&tegra_car TEGRA124_CLK_EXTERN1>;
+                };
+
+                pmic: pmic@40 {
+                        compatible = "ams,as3722";
+                        reg = <0x40>;
+                        interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
+                        ams,system-power-controller;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&as3722_default>;
+
+                        as3722_default: pinmux {
+                                gpio2_7 {
+                                        pins = "gpio2", /* PWR_EN_+V3.3 */
+                                               "gpio7"; /* +V1.6_LPO */
+                                        function = "gpio";
+                                        bias-pull-up;
+                                };
+
+                                gpio0_1_3_4_5_6 {
+                                        pins = "gpio0", "gpio1", "gpio3",
+                                               "gpio4", "gpio5", "gpio6";
+                                        bias-high-impedance;
+                                };
+                        };
+
+                        regulators {
+                                vsup-sd2-supply = <&reg_3v3>;
+                                vsup-sd3-supply = <&reg_3v3>;
+                                vsup-sd4-supply = <&reg_3v3>;
+                                vsup-sd5-supply = <&reg_3v3>;
+                                vin-ldo0-supply = <&vddio_ddr_1v35>;
+                                vin-ldo1-6-supply = <&reg_3v3>;
+                                vin-ldo2-5-7-supply = <&vddio_1v8>;
+                                vin-ldo3-4-supply = <&reg_3v3>;
+                                vin-ldo9-10-supply = <&reg_3v3>;
+                                vin-ldo11-supply = <&reg_3v3>;
+
+                                vdd_cpu: sd0 {
+                                        regulator-name = "+VDD_CPU_AP";
+                                        regulator-min-microvolt = <700000>;
+                                        regulator-max-microvolt = <1400000>;
+                                        regulator-min-microamp = <3500000>;
+                                        regulator-max-microamp = <3500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        ams,ext-control = <2>;
+                                };
+
+                                sd1 {
+                                        regulator-name = "+VDD_CORE";
+                                        regulator-min-microvolt = <700000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-min-microamp = <2500000>;
+                                        regulator-max-microamp = <4000000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        ams,ext-control = <1>;
+                                };
+
+                                vddio_ddr_1v35: sd2 {
+                                        regulator-name =
+                                                "+V1.35_VDDIO_DDR(sd2)";
+                                        regulator-min-microvolt = <1350000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                sd3 {
+                                        regulator-name =
+                                                "+V1.35_VDDIO_DDR(sd3)";
+                                        regulator-min-microvolt = <1350000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                vdd_1v05: sd4 {
+                                        regulator-name = "+V1.05";
+                                        regulator-min-microvolt = <1050000>;
+                                        regulator-max-microvolt = <1050000>;
+                                };
+
+                                vddio_1v8: sd5 {
+                                        regulator-name = "+V1.8";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                };
+
+                                vdd_gpu: sd6 {
+                                        regulator-name = "+VDD_GPU_AP";
+                                        regulator-min-microvolt = <650000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-min-microamp = <3500000>;
+                                        regulator-max-microamp = <3500000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                };
+
+                                avdd_1v05: ldo0 {
+                                        regulator-name = "+V1.05_AVDD";
+                                        regulator-min-microvolt = <1050000>;
+                                        regulator-max-microvolt = <1050000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                        ams,ext-control = <1>;
+                                };
+
+                                vddio_sdmmc1: ldo1 {
+                                        regulator-name = "VDDIO_SDMMC1";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+
+                                ldo2 {
+                                        regulator-name = "+V1.2";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                };
+
+                                ldo3 {
+                                        regulator-name = "+V1.05_RTC";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                        ams,enable-tracking;
+                                };
+
+                                /* 1.8V for LVDS, 3.3V for eDP */
+                                ldo4 {
+                                        regulator-name = "AVDD_LVDS0_PLL";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+
+                                /* LDO5 not used */
+
+                                vddio_sdmmc3: ldo6 {
+                                        regulator-name = "VDDIO_SDMMC3";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+
+                                /* LDO7 not used */
+
+                                ldo9 {
+                                        regulator-name = "+V3.3_ETH(ldo9)";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo10 {
+                                        regulator-name = "+V3.3_ETH(ldo10)";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo11 {
+                                        regulator-name = "+V1.8_VPP_FUSE";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                        };
+                };
+
+                /*
+                 * TMP451 temperature sensor
+                 * Note: THERM_N directly connected to AS3722 PMIC THERM
+                 */
+                temperature-sensor@4c {
+                        compatible = "ti,tmp451";
+                        reg = <0x4c>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
+                        #thermal-sensor-cells = <1>;
+                };
+        };
+
+        /* SPI2: MCU SPI */
+        spi@7000d600 {
+                status = "okay";
+                spi-max-frequency = <25000000>;
+        };
+
+        pmc@7000e400 {
+                nvidia,invert-interrupt;
+                nvidia,suspend-mode = <1>;
+                nvidia,cpu-pwr-good-time = <500>;
+                nvidia,cpu-pwr-off-time = <300>;
+                nvidia,core-pwr-good-time = <641 3845>;
+                nvidia,core-pwr-off-time = <61036>;
+                nvidia,core-power-req-active-high;
+                nvidia,sys-clock-req-active-high;
+
+                /* Set power_off bit in ResetControl register of AS3722 PMIC */
+                i2c-thermtrip {
+                        nvidia,i2c-controller-id = <4>;
+                        nvidia,bus-addr = <0x40>;
+                        nvidia,reg-addr = <0x36>;
+                        nvidia,reg-data = <0x2>;
+                };
+        };
+
+        sata@70020000 {
+                phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
+                phy-names = "sata-0";
+                avdd-supply = <&vdd_1v05>;
+                hvdd-supply = <&reg_3v3>;
+                vddio-supply = <&vdd_1v05>;
+        };
+
+        usb@70090000 {
+                /* USBO1, USBO1 (SS), USBH2, USBH4 and USBH4 (SS) */
+                phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
+                       <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
+                       <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>,
+                       <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
+                       <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
+                phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0";
+                avddio-pex-supply = <&vdd_1v05>;
+                avdd-pll-erefe-supply = <&avdd_1v05>;
+                avdd-pll-utmip-supply = <&vddio_1v8>;
+                avdd-usb-ss-pll-supply = <&vdd_1v05>;
+                avdd-usb-supply = <&reg_3v3>;
+                dvddio-pex-supply = <&vdd_1v05>;
+                hvdd-usb-ss-pll-e-supply = <&reg_3v3>;
+                hvdd-usb-ss-supply = <&reg_3v3>;
+        };
+
+        padctl@7009f000 {
+                pads {
+                        usb2 {
+                                status = "okay";
+
+                                lanes {
+                                        usb2-0 {
+                                                nvidia,function = "xusb";
+                                                status = "okay";
+                                        };
+
+                                        usb2-1 {
+                                                nvidia,function = "xusb";
+                                                status = "okay";
+                                        };
+
+                                        usb2-2 {
+                                                nvidia,function = "xusb";
+                                                status = "okay";
+                                        };
+                                };
+                        };
+
+                        pcie {
+                                status = "okay";
+
+                                lanes {
+                                        pcie-0 {
+                                                nvidia,function = "usb3-ss";
+                                                status = "okay";
+                                        };
+
+                                        pcie-1 {
+                                                nvidia,function = "usb3-ss";
+                                                status = "okay";
+                                        };
+
+                                        pcie-2 {
+                                                nvidia,function = "pcie";
+                                                status = "okay";
+                                        };
+
+                                        pcie-3 {
+                                                nvidia,function = "pcie";
+                                                status = "okay";
+                                        };
+
+                                        pcie-4 {
+                                                nvidia,function = "pcie";
+                                                status = "okay";
+                                        };
+                                };
+                        };
+
+                        sata {
+                                status = "okay";
+
+                                lanes {
+                                        sata-0 {
+                                                nvidia,function = "sata";
+                                                status = "okay";
+                                        };
+                                };
+                        };
+                };
+
+                ports {
+                        /* USBO1 */
+                        usb2-0 {
+                                status = "okay";
+                                mode = "otg";
+
+                                vbus-supply = <&reg_usbo1_vbus>;
+                        };
+
+                        /* USBH2 */
+                        usb2-1 {
+                                status = "okay";
+                                mode = "host";
+
+                                vbus-supply = <&reg_usbh_vbus>;
+                        };
+
+                        /* USBH4 */
+                        usb2-2 {
+                                status = "okay";
+                                mode = "host";
+
+                                vbus-supply = <&reg_usbh_vbus>;
+                        };
+
+                        usb3-0 {
+                                nvidia,usb2-companion = <2>;
+                                status = "okay";
+                        };
+
+                        usb3-1 {
+                                nvidia,usb2-companion = <0>;
+                                status = "okay";
+                        };
+                };
+        };
+
+        /* eMMC */
+        sdhci@700b0600 {
+                status = "okay";
+                bus-width = <8>;
+                non-removable;
+        };
+
+        /* CPU DFLL clock */
+        clock@70110000 {
+                status = "okay";
+                vdd-cpu-supply = <&vdd_cpu>;
+                nvidia,i2c-fs-rate = <400000>;
+        };
+
+        ahub@70300000 {
+                i2s@70301200 {
+                        status = "okay";
+                };
+        };
+
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock@0 {
+                        compatible = "fixed-clock";
+                        reg = <0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
+        cpus {
+                cpu@0 {
+                        vdd-cpu-supply = <&vdd_cpu>;
+                };
+        };
+
+        reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll {
+                compatible = "regulator-fixed";
+                regulator-name = "+V1.05_AVDD_HDMI_PLL";
+                regulator-min-microvolt = <1050000>;
+                regulator-max-microvolt = <1050000>;
+                gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
+                vin-supply = <&vdd_1v05>;
+        };
+
+        reg_3v3_mxm: regulator-3v3-mxm {
+                compatible = "regulator-fixed";
+                regulator-name = "+V3.3_MXM";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+                regulator-boot-on;
+        };
+
+        reg_3v3: regulator-3v3 {
+                compatible = "regulator-fixed";
+                regulator-name = "+V3.3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+                regulator-boot-on;
+                /* PWR_EN_+V3.3 */
+                gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+                vin-supply = <&reg_3v3_mxm>;
+        };
+
+        reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
+                compatible = "regulator-fixed";
+                regulator-name = "+V3.3_AVDD_HDMI";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                vin-supply = <&vdd_1v05>;
+        };
+
+        sound {
+                compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1",
+                             "nvidia,tegra-audio-sgtl5000";
+                nvidia,model = "Toradex Apalis TK1";
+                nvidia,audio-routing =
+                        "Headphone Jack", "HP_OUT",
+                        "LINE_IN", "Line In Jack",
+                        "MIC_IN", "Mic Jack";
+                nvidia,i2s-controller = <&tegra_i2s2>;
+                nvidia,audio-codec = <&sgtl5000>;
+                clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
+                         <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA124_CLK_EXTERN1>;
+                clock-names = "pll_a", "pll_a_out0", "mclk";
+        };
+
+        thermal-zones {
+                cpu {
+                        trips {
+                                cpu-shutdown-trip {
+                                        temperature = <101000>;
+                                        hysteresis = <0>;
+                                        type = "critical";
+                                };
+                        };
+                };
+
+                mem {
+                        trips {
+                                mem-shutdown-trip {
+                                        temperature = <101000>;
+                                        hysteresis = <0>;
+                                        type = "critical";
+                                };
+                        };
+                };
+
+                gpu {
+                        trips {
+                                gpu-shutdown-trip {
+                                        temperature = <101000>;
+                                        hysteresis = <0>;
+                                        type = "critical";
+                                };
+                        };
+                };
+        };
+};
+
+&gpio {
+        /* I210 Gigabit Ethernet Controller Reset */
+        lan_reset_n {
+                gpio-hog;
+                gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
+                output-high;
+                line-name = "LAN_RESET_N";
+        };
+
+        /* Control MXM3 pin 26 Reset Module Output Carrier Input */
+        reset_moci_ctrl {
+                gpio-hog;
+                gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
+                output-high;
+                line-name = "RESET_MOCI_CTRL";
+        };
+};
diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi
index 5d9b18ef5af6..65a2161b9b8e 100644
--- a/arch/arm/boot/dts/tegra124-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra124-apalis.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright 2016 Toradex AG
+ * Copyright 2016-2018 Toradex AG
  *
  * This file is dual-licensed: you can use it either under the terms
  * of the GPL or the X11 license, at your option. Note that this dual
@@ -56,7 +56,6 @@
 
         pcie@1003000 {
                 status = "okay";
-
                 avddio-pex-supply = <&vdd_1v05>;
                 avdd-pex-pll-supply = <&vdd_1v05>;
                 avdd-pll-erefe-supply = <&avdd_1v05>;
@@ -85,7 +84,6 @@
                 hdmi@54280000 {
                         pll-supply = <&reg_1v05_avdd_hdmi_pll>;
                         vdd-supply = <&reg_3v3_avdd_hdmi>;
-
                         nvidia,ddc-i2c-bus = <&hdmi_ddc>;
                         nvidia,hpd-gpio =
                                 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
@@ -453,12 +451,12 @@
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
-                        /* PWM3 active on pu6 being Apalis BKL1_PWM */
+                        /* PWM3 active on pu6 being Apalis BKL1_PWM as well */
                         ph3 {
                                 nvidia,pins = "ph3";
-                                nvidia,function = "gmi";
-                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,function = "pwm3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
 
@@ -1579,7 +1577,7 @@
         };
 
         hdmi_ddc: i2c@7000c400 {
-                clock-frequency = <100000>;
+                clock-frequency = <10000>;
         };
 
         /* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */
@@ -1600,15 +1598,11 @@
                         compatible = "ams,as3722";
                         reg = <0x40>;
                         interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
-
                         ams,system-power-controller;
-
                         #interrupt-cells = <2>;
                         interrupt-controller;
-
                         gpio-controller;
                         #gpio-cells = <2>;
-
                         pinctrl-names = "default";
                         pinctrl-0 = <&as3722_default>;
 
@@ -1620,9 +1614,9 @@
                                         bias-pull-up;
                                 };
 
-                                gpio1_3_4_5_6 {
-                                        pins = "gpio1", "gpio3", "gpio4",
-                                               "gpio5", "gpio6";
+                                gpio0_1_3_4_5_6 {
+                                        pins = "gpio0", "gpio1", "gpio3",
+                                               "gpio4", "gpio5", "gpio6";
                                         bias-high-impedance;
                                 };
                         };
@@ -1783,7 +1777,6 @@
                         reg = <0x4c>;
                         interrupt-parent = <&gpio>;
                         interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
-
                         #thermal-sensor-cells = <1>;
                 };
         };
@@ -1816,7 +1809,6 @@
         sata@70020000 {
                 phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
                 phy-names = "sata-0";
-
                 avdd-supply = <&vdd_1v05>;
                 hvdd-supply = <&reg_3v3>;
                 vddio-supply = <&vdd_1v05>;
@@ -1830,7 +1822,6 @@
                        <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
                        <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
                 phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0";
-
                 avddio-pex-supply = <&vdd_1v05>;
                 avdd-pll-erefe-supply = <&avdd_1v05>;
                 avdd-pll-utmip-supply = <&vddio_1v8>;
@@ -2041,53 +2032,50 @@
         thermal-zones {
                 cpu {
                         trips {
-                                trip@0 {
+                                cpu-shutdown-trip {
                                         temperature = <101000>;
                                         hysteresis = <0>;
                                         type = "critical";
                                 };
                         };
-
-                        cooling-maps {
-                                /*
-                                 * There are currently no cooling maps because
-                                 * there are no cooling devices
-                                 */
-                        };
                 };
 
                 mem {
                         trips {
-                                trip@0 {
+                                mem-shutdown-trip {
                                         temperature = <101000>;
                                         hysteresis = <0>;
                                         type = "critical";
                                 };
                         };
-
-                        cooling-maps {
-                                /*
-                                 * There are currently no cooling maps because
-                                 * there are no cooling devices
-                                 */
-                        };
                 };
 
                 gpu {
                         trips {
-                                trip@0 {
+                                gpu-shutdown-trip {
                                         temperature = <101000>;
                                         hysteresis = <0>;
                                         type = "critical";
                                 };
                         };
-
-                        cooling-maps {
-                                /*
-                                 * There are currently no cooling maps because
-                                 * there are no cooling devices
-                                 */
-                        };
                 };
         };
 };
+
+&gpio {
+        /* I210 Gigabit Ethernet Controller Reset */
+        lan_reset_n {
+                gpio-hog;
+                gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
+                output-high;
+                line-name = "LAN_RESET_N";
+        };
+
+        /* Control MXM3 pin 26 Reset Module Output Carrier Input */
+        reset_moci_ctrl {
+                gpio-hog;
+                gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
+                output-high;
+                line-name = "RESET_MOCI_CTRL";
+        };
+};
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
index d112f85e66ed..6dbcf84dafbc 100644
--- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
+++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
@@ -1418,7 +1418,7 @@
                         compatible = "realtek,rt5639";
                         reg = <0x1c>;
                         interrupt-parent = <&gpio>;
-                        interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
+                        interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_EDGE_FALLING>;
                         realtek,ldo1-en-gpios =
                                 <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
                 };
diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts
index 32d9079f025b..89bcc178994d 100644
--- a/arch/arm/boot/dts/tegra124-venice2.dts
+++ b/arch/arm/boot/dts/tegra124-venice2.dts
@@ -613,7 +613,7 @@
                         compatible = "maxim,max98090";
                         reg = <0x10>;
                         interrupt-parent = <&gpio>;
-                        interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
+                        interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_EDGE_FALLING>;
                 };
         };
 
@@ -859,7 +859,7 @@
                                         reg = <0x9>;
                                         interrupt-parent = <&gpio>;
                                         interrupts = <TEGRA_GPIO(J, 0)
-                                                        GPIO_ACTIVE_HIGH>;
+                                                        IRQ_TYPE_EDGE_BOTH>;
                                         ti,ac-detect-gpios = <&gpio
                                                         TEGRA_GPIO(J, 0)
                                                         GPIO_ACTIVE_HIGH>;
@@ -956,11 +956,6 @@
                                                 nvidia,function = "usb3-ss";
                                                 status = "okay";
                                         };
-
-                                        pcie-1 {
-                                                nvidia,function = "usb3-ss";
-                                                status = "okay";
-                                        };
                                 };
                         };
                 };
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index 813ae34edd6a..5c202b3e3bb1 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -213,21 +213,27 @@
                         GPIO_ACTIVE_HIGH>;
         };
 
+        /*
+         * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
+         * board)
+         */
         i2c@7000c000 {
                 clock-frequency = <400000>;
         };
 
+        /* DDC_SCL/SDA on X3 pin 15/16 (e.g. display EDID) */
         i2c_ddc: i2c@7000c400 {
-                clock-frequency = <100000>;
+                clock-frequency = <10000>;
         };
 
-        i2c@7000c500 {
-                clock-frequency = <400000>;
-        };
+        /* GEN2_I2C: unused */
 
+        /* CAM/GEN3_I2C: used as EXT_IO1/2 GPIOs on SODIMM pin 133/127 */
+
+        /* PWR_I2C: power I2C to PMIC and temperature sensor (On-module) */
         i2c@7000d000 {
                 status = "okay";
-                clock-frequency = <400000>;
+                clock-frequency = <100000>;
 
                 pmic: tps6586x@34 {
                         compatible = "ti,tps6586x";
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 864a95872b8d..0a7136462a1a 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -17,7 +17,7 @@
                 #size-cells = <1>;
                 ranges = <0 0x40000000 0x40000>;
 
-                vde_pool: vde {
+                vde_pool: vde@400 {
                         reg = <0x400 0x3fc00>;
                         pool;
                 };
@@ -741,7 +741,7 @@
                 phy_type = "ulpi";
                 clocks = <&tegra_car TEGRA20_CLK_USB2>,
                          <&tegra_car TEGRA20_CLK_PLL_U>,
-                         <&tegra_car TEGRA20_CLK_CDEV2>;
+                         <&tegra_car TEGRA20_CLK_PLL_P_OUT4>;
                 clock-names = "reg", "pll_u", "ulpi-link";
                 resets = <&tegra_car 58>, <&tegra_car 22>;
                 reset-names = "usb", "utmi-pads";
diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts
index 07b945b0391a..0dc85a20bd45 100644
--- a/arch/arm/boot/dts/tegra30-apalis-eval.dts
+++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts
@@ -79,7 +79,7 @@
          */
         i2c@7000c000 {
                 status = "okay";
-                clock-frequency = <100000>;
+                clock-frequency = <400000>;
 
                 pcie-switch@58 {
                         compatible = "plx,pex8605";
@@ -88,7 +88,7 @@
 
                 /* M41T0M6 real time clock on carrier board */
                 rtc@68 {
-                        compatible = "st,m41t00";
+                        compatible = "st,m41t0";
                         reg = <0x68>;
                 };
         };
diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi
index faa8cd2914e8..d1d21ec2a844 100644
--- a/arch/arm/boot/dts/tegra30-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra30-apalis.dtsi
@@ -437,7 +437,7 @@
         };
 
         hdmiddc: i2c@7000c700 {
-                clock-frequency = <100000>;
+                clock-frequency = <10000>;
         };
 
         /*
@@ -597,7 +597,6 @@
 
                         stmpe_touchscreen@0 {
                                 compatible = "st,stmpe-ts";
-                                reg = <0>;
                                 /* 3.25 MHz ADC clock speed */
                                 st,adc-freq = <1>;
                                 /* 8 sample average control */
@@ -657,7 +656,7 @@
                         reg = <1>;
                         clocks = <&clk16m>;
                         interrupt-parent = <&gpio>;
-                        interrupts = <TEGRA_GPIO(W, 3) GPIO_ACTIVE_LOW>;
+                        interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_RISING>;
                         spi-max-frequency = <10000000>;
                 };
         };
@@ -672,7 +671,7 @@
                         reg = <0>;
                         clocks = <&clk16m>;
                         interrupt-parent = <&gpio>;
-                        interrupts = <TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
+                        interrupts = <TEGRA_GPIO(W, 2) IRQ_TYPE_EDGE_RISING>;
                         spi-max-frequency = <10000000>;
                 };
         };
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index 5331a8f7dcf8..ae52a5039506 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -260,14 +260,14 @@
                         };
                         sdmmc3_dat6_pd3 {
                                 nvidia,pins = "sdmmc3_dat6_pd3";
-                                nvidia,function = "rsvd1";
+                                nvidia,function = "spdif";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         sdmmc3_dat7_pd4 {
                                 nvidia,pins = "sdmmc3_dat7_pd4";
-                                nvidia,function = "rsvd1";
+                                nvidia,function = "spdif";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
@@ -281,14 +281,14 @@
                         };
                         vi_vsync_pd6 {
                                 nvidia,pins = "vi_vsync_pd6";
-                                nvidia,function = "rsvd1";
+                                nvidia,function = "ddr";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         vi_hsync_pd7 {
                                 nvidia,pins = "vi_hsync_pd7";
-                                nvidia,function = "rsvd1";
+                                nvidia,function = "ddr";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
@@ -806,7 +806,7 @@
                         };
                         hdmi_int_pn7 {
                                 nvidia,pins = "hdmi_int_pn7";
-                                nvidia,function = "rsvd1";
+                                nvidia,function = "hdmi";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
@@ -841,7 +841,7 @@
                         };
                         ulpi_data3_po4 {
                                 nvidia,pins = "ulpi_data3_po4";
-                                nvidia,function = "rsvd1";
+                                nvidia,function = "uarta";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
@@ -1107,21 +1107,21 @@
                         };
                         vi_d10_pt2 {
                                 nvidia,pins = "vi_d10_pt2";
-                                nvidia,function = "rsvd1";
+                                nvidia,function = "ddr";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         vi_d11_pt3 {
                                 nvidia,pins = "vi_d11_pt3";
-                                nvidia,function = "rsvd1";
+                                nvidia,function = "ddr";
                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
                         vi_d0_pt4 {
                                 nvidia,pins = "vi_d0_pt4";
-                                nvidia,function = "rsvd1";
+                                nvidia,function = "ddr";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
@@ -1151,7 +1151,7 @@
                         };
                         pu0 {
                                 nvidia,pins = "pu0";
-                                nvidia,function = "rsvd1";
+                                nvidia,function = "owr";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
@@ -1172,7 +1172,7 @@
                         };
                         pu3 {
                                 nvidia,pins = "pu3";
-                                nvidia,function = "rsvd1";
+                                nvidia,function = "pwm0";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
@@ -1193,7 +1193,7 @@
                         };
                         pu6 {
                                 nvidia,pins = "pu6";
-                                nvidia,function = "rsvd1";
+                                nvidia,function = "pwm3";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
@@ -1221,7 +1221,7 @@
                         };
                         pv3 {
                                 nvidia,pins = "pv3";
-                                nvidia,function = "rsvd1";
+                                nvidia,function = "clk_12m_out";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
@@ -1510,7 +1510,7 @@
                         };
                         pbb0 {
                                 nvidia,pins = "pbb0";
-                                nvidia,function = "rsvd1";
+                                nvidia,function = "i2s4";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
@@ -1575,7 +1575,7 @@
                         };
                         pcc1 {
                                 nvidia,pins = "pcc1";
-                                nvidia,function = "rsvd1";
+                                nvidia,function = "i2s4";
                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
@@ -1762,7 +1762,7 @@
                         compatible = "realtek,rt5640";
                         reg = <0x1c>;
                         interrupt-parent = <&gpio>;
-                        interrupts = <TEGRA_GPIO(X, 3) GPIO_ACTIVE_HIGH>;
+                        interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_EDGE_FALLING>;
                         realtek,ldo1-en-gpios =
                                 <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>;
                 };
diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
index 3c5fb2430212..16e1f387aa6d 100644
--- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
@@ -56,11 +56,11 @@
          */
         i2c@7000c000 {
                 status = "okay";
-                clock-frequency = <100000>;
+                clock-frequency = <400000>;
 
                 /* M41T0M6 real time clock on carrier board */
                 rtc@68 {
-                        compatible = "st,m41t00";
+                        compatible = "st,m41t0";
                         reg = <0x68>;
                 };
         };
@@ -79,7 +79,7 @@
                         reg = <0>;
                         clocks = <&clk16m>;
                         interrupt-parent = <&gpio>;
-                        interrupts = <TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
+                        interrupts = <TEGRA_GPIO(S, 0) IRQ_TYPE_EDGE_RISING>;
                         spi-max-frequency = <10000000>;
                 };
                 spidev0: spi@1 {
diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi
index 139bfa028b04..c44d8c40c410 100644
--- a/arch/arm/boot/dts/tegra30-colibri.dtsi
+++ b/arch/arm/boot/dts/tegra30-colibri.dtsi
@@ -215,7 +215,7 @@
         };
 
         hdmiddc: i2c@7000c700 {
-                clock-frequency = <100000>;
+                clock-frequency = <10000>;
         };
 
         /*
@@ -363,7 +363,6 @@
 
                         stmpe_touchscreen {
                                 compatible = "st,stmpe-ts";
-                                reg = <0>;
                                 /* 3.25 MHz ADC clock speed */
                                 st,adc-freq = <1>;
                                 /* 8 sample average control */
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index c3e9f1e847db..a110cf84d85f 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -91,6 +91,19 @@
                 };
         };
 
+        iram@40000000 {
+                compatible = "mmio-sram";
+                reg = <0x40000000 0x40000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0 0x40000000 0x40000>;
+
+                vde_pool: vde@400 {
+                        reg = <0x400 0x3fc00>;
+                        pool;
+                };
+        };
+
         host1x@50000000 {
                 compatible = "nvidia,tegra30-host1x", "simple-bus";
                 reg = <0x50000000 0x00024000>;
@@ -358,6 +371,28 @@
                 */
         };
 
+        vde@6001a000 {
+                compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde";
+                reg = <0x6001a000 0x1000   /* Syntax Engine */
+                       0x6001b000 0x1000   /* Video Bitstream Engine */
+                       0x6001c000  0x100   /* Macroblock Engine */
+                       0x6001c200  0x100   /* Post-processing Engine */
+                       0x6001c400  0x100   /* Motion Compensation Engine */
+                       0x6001c600  0x100   /* Transform Engine */
+                       0x6001c800  0x100   /* Pixel prediction block */
+                       0x6001ca00  0x100   /* Video DMA */
+                       0x6001d800  0x400>; /* Video frame controls */
+                reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
+                            "tfe", "ppb", "vdma", "frameid";
+                iram = <&vde_pool>; /* IRAM region */
+                interrupts = <GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
+                             <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
+                             <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
+                interrupt-names = "sync-token", "bsev", "sxe";
+                clocks = <&tegra_car TEGRA30_CLK_VDE>;
+                resets = <&tegra_car 61>;
+        };
+
         apbmisc@70000800 {
                 compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
                 reg = <0x70000800 0x64   /* Chip revision */
diff --git a/arch/arm/boot/dts/uniphier-ld4-ref.dts b/arch/arm/boot/dts/uniphier-ld4-ref.dts
index a3afd0cda42f..21407e159bf7 100644
--- a/arch/arm/boot/dts/uniphier-ld4-ref.dts
+++ b/arch/arm/boot/dts/uniphier-ld4-ref.dts
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier LD4 Reference Board
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier LD4 Reference Board
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 
 /dts-v1/;
 #include "uniphier-ld4.dtsi"
diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi
index 0459e84d4d8e..37950ad2de7c 100644
--- a/arch/arm/boot/dts/uniphier-ld4.dtsi
+++ b/arch/arm/boot/dts/uniphier-ld4.dtsi
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier LD4 SoC
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier LD4 SoC
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 
 #include <dt-bindings/gpio/uniphier-gpio.h>
 
diff --git a/arch/arm/boot/dts/uniphier-ld6b-ref.dts b/arch/arm/boot/dts/uniphier-ld6b-ref.dts
index 811b999800ed..a0a44a422e12 100644
--- a/arch/arm/boot/dts/uniphier-ld6b-ref.dts
+++ b/arch/arm/boot/dts/uniphier-ld6b-ref.dts
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier LD6b Reference Board
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier LD6b Reference Board
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 
 /dts-v1/;
 #include "uniphier-ld6b.dtsi"
@@ -67,6 +65,17 @@
         status = "okay";
 };
 
+&eth {
+        status = "okay";
+        phy-handle = <&ethphy>;
+};
+
+&mdio {
+        ethphy: ethphy@0 {
+                reg = <0>;
+        };
+};
+
 &nand {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/uniphier-ld6b.dtsi b/arch/arm/boot/dts/uniphier-ld6b.dtsi
index 9a7b25cc8233..4d07a94c6b34 100644
--- a/arch/arm/boot/dts/uniphier-ld6b.dtsi
+++ b/arch/arm/boot/dts/uniphier-ld6b.dtsi
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier LD6b SoC
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier LD6b SoC
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 
 /*
  * LD6b consists of two silicon dies: D-chip and A-chip.
diff --git a/arch/arm/boot/dts/uniphier-pinctrl.dtsi b/arch/arm/boot/dts/uniphier-pinctrl.dtsi
index de481c372467..9847af85b542 100644
--- a/arch/arm/boot/dts/uniphier-pinctrl.dtsi
+++ b/arch/arm/boot/dts/uniphier-pinctrl.dtsi
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier SoCs default pinctrl settings
- *
- * Copyright (C) 2015-2017 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier SoCs default pinctrl settings
+//
+// Copyright (C) 2015-2017 Socionext Inc.
+//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 
 &pinctrl {
         pinctrl_aout: aout {
@@ -13,6 +11,46 @@
                 function = "aout";
         };
 
+        pinctrl_ain1: ain1 {
+                groups = "ain1";
+                function = "ain1";
+        };
+
+        pinctrl_ain2: ain2 {
+                groups = "ain2";
+                function = "ain2";
+        };
+
+        pinctrl_ainiec1: ainiec1 {
+                groups = "ainiec1";
+                function = "ainiec1";
+        };
+
+        pinctrl_aout1: aout1 {
+                groups = "aout1";
+                function = "aout1";
+        };
+
+        pinctrl_aout2: aout2 {
+                groups = "aout2";
+                function = "aout2";
+        };
+
+        pinctrl_aout3: aout3 {
+                groups = "aout3";
+                function = "aout3";
+        };
+
+        pinctrl_aoutiec1: aoutiec1 {
+                groups = "aoutiec1";
+                function = "aoutiec1";
+        };
+
+        pinctrl_aoutiec2: aoutiec2 {
+                groups = "aoutiec2";
+                function = "aoutiec2";
+        };
+
         pinctrl_emmc: emmc {
                 groups = "emmc", "emmc_dat8";
                 function = "emmc";
diff --git a/arch/arm/boot/dts/uniphier-pro4-ace.dts b/arch/arm/boot/dts/uniphier-pro4-ace.dts
index 089419cee273..db1b08935ae5 100644
--- a/arch/arm/boot/dts/uniphier-pro4-ace.dts
+++ b/arch/arm/boot/dts/uniphier-pro4-ace.dts
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier Pro4 Ace Board
- *
- * Copyright (C) 2016 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier Pro4 Ace Board
+//
+// Copyright (C) 2016 Socionext Inc.
+//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 
 /dts-v1/;
 #include "uniphier-pro4.dtsi"
@@ -77,3 +75,14 @@
 &usb3 {
         status = "okay";
 };
+
+&eth {
+        status = "okay";
+        phy-handle = <&ethphy>;
+};
+
+&mdio {
+        ethphy: ethphy@1 {
+                reg = <1>;
+        };
+};
diff --git a/arch/arm/boot/dts/uniphier-pro4-ref.dts b/arch/arm/boot/dts/uniphier-pro4-ref.dts
index 6a004e5cf786..efb084983b82 100644
--- a/arch/arm/boot/dts/uniphier-pro4-ref.dts
+++ b/arch/arm/boot/dts/uniphier-pro4-ref.dts
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier Pro4 Reference Board
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier Pro4 Reference Board
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 
 /dts-v1/;
 #include "uniphier-pro4.dtsi"
@@ -75,6 +73,17 @@
         status = "okay";
 };
 
+&eth {
+        status = "okay";
+        phy-handle = <&ethphy>;
+};
+
+&mdio {
+        ethphy: ethphy@0 {
+                reg = <0>;
+        };
+};
+
 &nand {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/uniphier-pro4-sanji.dts b/arch/arm/boot/dts/uniphier-pro4-sanji.dts
index adef212b45b2..dac4d6679a32 100644
--- a/arch/arm/boot/dts/uniphier-pro4-sanji.dts
+++ b/arch/arm/boot/dts/uniphier-pro4-sanji.dts
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier Pro4 Sanji Board
- *
- * Copyright (C) 2016 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier Pro4 Sanji Board
+//
+// Copyright (C) 2016 Socionext Inc.
+//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 
 /dts-v1/;
 #include "uniphier-pro4.dtsi"
@@ -72,3 +70,14 @@
 &usb3 {
         status = "okay";
 };
+
+&eth {
+        status = "okay";
+        phy-handle = <&ethphy>;
+};
+
+&mdio {
+        ethphy: ethphy@1 {
+                reg = <1>;
+        };
+};
diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi
index 1a29a8619856..844124bc9c9c 100644
--- a/arch/arm/boot/dts/uniphier-pro4.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro4.dtsi
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier Pro4 SoC
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier Pro4 SoC
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 
 #include <dt-bindings/gpio/uniphier-gpio.h>
 
@@ -366,6 +364,24 @@
                         };
                 };
 
+                eth: ethernet@65000000 {
+                        compatible = "socionext,uniphier-pro4-ave4";
+                        status = "disabled";
+                        reg = <0x65000000 0x8500>;
+                        interrupts = <0 66 4>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_ether_rgmii>;
+                        clocks = <&sys_clk 6>;
+                        resets = <&sys_rst 6>;
+                        phy-mode = "rgmii";
+                        local-mac-address = [00 00 00 00 00 00];
+
+                        mdio: mdio {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+                };
+
                 nand: nand@68000000 {
                         compatible = "socionext,uniphier-denali-nand-v5a";
                         status = "disabled";
diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi
index f291dd63de9c..06c2cef91ec7 100644
--- a/arch/arm/boot/dts/uniphier-pro5.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro5.dtsi
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier Pro5 SoC
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier Pro5 SoC
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 
 / {
         compatible = "socionext,uniphier-pro5";
diff --git a/arch/arm/boot/dts/uniphier-pxs2-gentil.dts b/arch/arm/boot/dts/uniphier-pxs2-gentil.dts
index 7dfae2667f50..bed26b8ed9a3 100644
--- a/arch/arm/boot/dts/uniphier-pxs2-gentil.dts
+++ b/arch/arm/boot/dts/uniphier-pxs2-gentil.dts
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier PXs2 Gentil Board
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier PXs2 Gentil Board
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 
 /dts-v1/;
 #include "uniphier-pxs2.dtsi"
@@ -34,6 +32,12 @@
                 device_type = "memory";
                 reg = <0x80000000 0x80000000>;
         };
+
+        sound {
+                compatible = "audio-graph-card";
+                label = "UniPhier PXs2";
+                dais = <&i2s_port2>;
+        };
 };
 
 &serial2 {
@@ -50,6 +54,35 @@
         };
 };
 
+&i2s_aux {
+        dai-format = "i2s";
+        remote-endpoint = <&wm_speaker>;
+};
+
 &i2c2 {
         status = "okay";
+
+        wm8960@1a {
+                compatible = "wlf,wm8960";
+                reg = <0x1a>;
+                #sound-dai-cells = <0>;
+
+                port@0 {
+                        wm_speaker: endpoint {
+                                dai-format = "i2s";
+                                remote-endpoint = <&i2s_aux>;
+                        };
+                };
+        };
+};
+
+&eth {
+        status = "okay";
+        phy-handle = <&ethphy>;
+};
+
+&mdio {
+        ethphy: ethphy@1 {
+                reg = <1>;
+        };
 };
diff --git a/arch/arm/boot/dts/uniphier-pxs2-vodka.dts b/arch/arm/boot/dts/uniphier-pxs2-vodka.dts
index 0cf615463a82..b13d2d16ddad 100644
--- a/arch/arm/boot/dts/uniphier-pxs2-vodka.dts
+++ b/arch/arm/boot/dts/uniphier-pxs2-vodka.dts
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier PXs2 Vodka Board
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier PXs2 Vodka Board
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 
 /dts-v1/;
 #include "uniphier-pxs2.dtsi"
@@ -32,12 +30,60 @@
                 device_type = "memory";
                 reg = <0x80000000 0x80000000>;
         };
+
+        sound {
+                compatible = "audio-graph-card";
+                label = "UniPhier PXs2";
+                dais = <&spdif_port0
+                        &comp_spdif_port0>;
+        };
+
+        spdif-out {
+                compatible = "linux,spdif-dit";
+                #sound-dai-cells = <0>;
+
+                port@0 {
+                        spdif_tx: endpoint {
+                                remote-endpoint = <&spdif_hiecout1>;
+                        };
+                };
+        };
+
+        comp-spdif-out {
+                compatible = "linux,spdif-dit";
+                #sound-dai-cells = <0>;
+
+                port@0 {
+                        comp_spdif_tx: endpoint {
+                                remote-endpoint = <&comp_spdif_hiecout1>;
+                        };
+                };
+        };
 };
 
 &serial2 {
         status = "okay";
 };
 
+&spdif_hiecout1 {
+        remote-endpoint = <&spdif_tx>;
+};
+
+&comp_spdif_hiecout1 {
+        remote-endpoint = <&comp_spdif_tx>;
+};
+
 &i2c0 {
         status = "okay";
 };
+
+&eth {
+        status = "okay";
+        phy-handle = <&ethphy>;
+};
+
+&mdio {
+        ethphy: ethphy@1 {
+                reg = <1>;
+        };
+};
diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi
index c083468c17db..595045441c9c 100644
--- a/arch/arm/boot/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier PXs2 SoC
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier PXs2 SoC
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 
 #include <dt-bindings/gpio/uniphier-gpio.h>
 #include <dt-bindings/thermal/thermal.h>
@@ -227,6 +225,60 @@
                                                      <21 217 3>;
                 };
 
+                audio@56000000 {
+                        compatible = "socionext,uniphier-pxs2-aio";
+                        reg = <0x56000000 0x80000>;
+                        interrupts = <0 144 4>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_ain1>,
+                                    <&pinctrl_ain2>,
+                                    <&pinctrl_ainiec1>,
+                                    <&pinctrl_aout2>,
+                                    <&pinctrl_aout3>,
+                                    <&pinctrl_aoutiec1>,
+                                    <&pinctrl_aoutiec2>;
+                        clock-names = "aio";
+                        clocks = <&sys_clk 40>;
+                        reset-names = "aio";
+                        resets = <&sys_rst 40>;
+                        #sound-dai-cells = <1>;
+
+                        i2s_port0: port@0 {
+                                i2s_hdmi: endpoint {
+                                };
+                        };
+
+                        i2s_port1: port@1 {
+                                i2s_line: endpoint {
+                                };
+                        };
+
+                        i2s_port2: port@2 {
+                                i2s_aux: endpoint {
+                                };
+                        };
+
+                        spdif_port0: port@3 {
+                                spdif_hiecout1: endpoint {
+                                };
+                        };
+
+                        spdif_port1: port@4 {
+                                spdif_iecout1: endpoint {
+                                };
+                        };
+
+                        comp_spdif_port0: port@5 {
+                                comp_spdif_hiecout1: endpoint {
+                                };
+                        };
+
+                        comp_spdif_port1: port@6 {
+                                comp_spdif_iecout1: endpoint {
+                                };
+                        };
+                };
+
                 i2c0: i2c@58780000 {
                         compatible = "socionext,uniphier-fi2c";
                         status = "disabled";
@@ -446,6 +498,24 @@
                         };
                 };
 
+                eth: ethernet@65000000 {
+                        compatible = "socionext,uniphier-pxs2-ave4";
+                        status = "disabled";
+                        reg = <0x65000000 0x8500>;
+                        interrupts = <0 66 4>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_ether_rgmii>;
+                        clocks = <&sys_clk 6>;
+                        resets = <&sys_rst 6>;
+                        phy-mode = "rgmii";
+                        local-mac-address = [00 00 00 00 00 00];
+
+                        mdio: mdio {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+                };
+
                 nand: nand@68000000 {
                         compatible = "socionext,uniphier-denali-nand-v5b";
                         status = "disabled";
diff --git a/arch/arm/boot/dts/uniphier-ref-daughter.dtsi b/arch/arm/boot/dts/uniphier-ref-daughter.dtsi
index 7a1c29b558d5..04e60c295319 100644
--- a/arch/arm/boot/dts/uniphier-ref-daughter.dtsi
+++ b/arch/arm/boot/dts/uniphier-ref-daughter.dtsi
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier Reference Daughter Board
- *
- * Copyright (C) 2015-2017 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier Reference Daughter Board
+//
+// Copyright (C) 2015-2017 Socionext Inc.
+//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 
 &i2c0 {
         eeprom@50 {
diff --git a/arch/arm/boot/dts/uniphier-sld8-ref.dts b/arch/arm/boot/dts/uniphier-sld8-ref.dts
index e052ea3b4020..fe386fa2ea4b 100644
--- a/arch/arm/boot/dts/uniphier-sld8-ref.dts
+++ b/arch/arm/boot/dts/uniphier-sld8-ref.dts
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier sLD8 Reference Board
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier sLD8 Reference Board
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 
 /dts-v1/;
 #include "uniphier-sld8.dtsi"
diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi
index bc8c24078faa..e9b9b4f3c558 100644
--- a/arch/arm/boot/dts/uniphier-sld8.dtsi
+++ b/arch/arm/boot/dts/uniphier-sld8.dtsi
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier sLD8 SoC
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier sLD8 SoC
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 
 #include <dt-bindings/gpio/uniphier-gpio.h>
 
diff --git a/arch/arm/boot/dts/uniphier-support-card.dtsi b/arch/arm/boot/dts/uniphier-support-card.dtsi
index e4e7e1bb9172..bf441c2eff79 100644
--- a/arch/arm/boot/dts/uniphier-support-card.dtsi
+++ b/arch/arm/boot/dts/uniphier-support-card.dtsi
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier Support Card (Expansion Board)
- *
- * Copyright (C) 2015-2017 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier Support Card (Expansion Board)
+//
+// Copyright (C) 2015-2017 Socionext Inc.
+//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 
 &system_bus {
         status = "okay";
diff --git a/arch/arm/boot/dts/versatile-ab-ib2.dts b/arch/arm/boot/dts/versatile-ab-ib2.dts
new file mode 100644
index 000000000000..5890cb974f78
--- /dev/null
+++ b/arch/arm/boot/dts/versatile-ab-ib2.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * The Versatile AB with the IB2 expansion board mounted.
+ * This works as a superset of the Versatile AB.
+ */
+
+#include "versatile-ab.dts"
+
+/ {
+        model = "ARM Versatile AB + IB2 board";
+
+        /* Special IB2 control register */
+        ib2_syscon@27000000 {
+                compatible = "arm,versatile-ib2-syscon", "syscon", "simple-mfd";
+                reg = <0x27000000 0x4>;
+
+                led@00.4 {
+                        compatible = "register-bit-led";
+                        offset = <0x00>;
+                        mask = <0x10>;
+                        label = "versatile-ib2:0";
+                        linux,default-trigger = "heartbeat";
+                        default-state = "on";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/versatile-ab.dts b/arch/arm/boot/dts/versatile-ab.dts
index 4a51612996bc..5f61d3609027 100644
--- a/arch/arm/boot/dts/versatile-ab.dts
+++ b/arch/arm/boot/dts/versatile-ab.dts
@@ -30,6 +30,43 @@
                 clock-frequency = <24000000>;
         };
 
+        bridge {
+                compatible = "ti,ths8134b", "ti,ths8134";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@0 {
+                                reg = <0>;
+
+                                vga_bridge_in: endpoint {
+                                        remote-endpoint = <&clcd_pads_vga_dac>;
+                                };
+                        };
+
+                        port@1 {
+                                reg = <1>;
+
+                                vga_bridge_out: endpoint {
+                                        remote-endpoint = <&vga_con_in>;
+                                };
+                        };
+                };
+        };
+
+        vga {
+                compatible = "vga-connector";
+
+                port {
+                        vga_con_in: endpoint {
+                                remote-endpoint = <&vga_bridge_out>;
+                        };
+                };
+        };
+
         core-module@10000000 {
                 compatible = "arm,core-module-versatile", "syscon", "simple-mfd";
                 reg = <0x10000000 0x200>;
@@ -230,7 +267,39 @@
                         reg = <0x10120000 0x1000>;
                         interrupts = <16>;
                         clocks = <&osc1>, <&pclk>;
-                        clock-names = "clcd", "apb_pclk";
+                        clock-names = "clcdclk", "apb_pclk";
+                        /* 800x600 16bpp @ 36MHz works fine */
+                        max-memory-bandwidth = <54000000>;
+
+                        /*
+                         * This port is routed through a PLD (Programmable
+                         * Logic Device) that routes the output from the CLCD
+                         * (after transformations) to the VGA DAC and also an
+                         * external panel connector. The PLD is essential for
+                         * supporting RGB565/BGR565.
+                         *
+                         * The signals from the port thus reaches two endpoints.
+                         * The PLD is managed through a few special bits in the
+                         * FPGA "sysreg".
+                         *
+                         * This arrangement can be clearly seen in
+                         * ARM DUI 0225D, page 3-41, figure 3-19.
+                         */
+                        port@0 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                clcd_pads_panel: endpoint@0 {
+                                        reg = <0>;
+                                        remote-endpoint = <&panel_in>;
+                                        arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
+                                };
+                                clcd_pads_vga_dac: endpoint@1 {
+                                        reg = <1>;
+                                        remote-endpoint = <&vga_bridge_in>;
+                                        arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
+                                };
+                        };
                 };
 
                 sctl@101e0000 {
@@ -319,8 +388,18 @@
                         ranges = <0 0x10000000 0x10000>;
 
                         sysreg@0 {
-                                compatible = "arm,versatile-sysreg", "syscon";
+                                compatible = "arm,versatile-sysreg", "syscon", "simple-mfd";
                                 reg = <0x00000 0x1000>;
+
+                                panel: display@0 {
+                                        compatible = "arm,versatile-tft-panel";
+
+                                        port {
+                                                panel_in: endpoint {
+                                                        remote-endpoint = <&clcd_pads_panel>;
+                                                };
+                                        };
+                                };
                         };
 
                         aaci@4000 {
diff --git a/arch/arm/boot/dts/vf500-colibri.dtsi b/arch/arm/boot/dts/vf500-colibri.dtsi
index 515c4d2f28b0..2e7e3cebba1c 100644
--- a/arch/arm/boot/dts/vf500-colibri.dtsi
+++ b/arch/arm/boot/dts/vf500-colibri.dtsi
@@ -46,7 +46,7 @@
         model = "Toradex Colibri VF50 COM";
         compatible = "toradex,vf610-colibri_vf50", "fsl,vf500";
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x8000000>;
         };
 
diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi
index 348bcd30c0f7..bbff0115e2fb 100644
--- a/arch/arm/boot/dts/vf500.dtsi
+++ b/arch/arm/boot/dts/vf500.dtsi
@@ -39,11 +39,16 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-#include "skeleton.dtsi"
 #include "vfxxx.dtsi"
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
 / {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        chosen { };
+        aliases { };
+        memory { device_type = "memory"; };
+
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/vf610-colibri.dtsi b/arch/arm/boot/dts/vf610-colibri.dtsi
index 395812c52933..aeaf99f1f0fc 100644
--- a/arch/arm/boot/dts/vf610-colibri.dtsi
+++ b/arch/arm/boot/dts/vf610-colibri.dtsi
@@ -46,7 +46,7 @@
         model = "Toradex Colibri VF61 COM";
         compatible = "toradex,vf610-colibri_vf61", "fsl,vf610";
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x10000000>;
         };
 };
diff --git a/arch/arm/boot/dts/vf610-cosmic.dts b/arch/arm/boot/dts/vf610-cosmic.dts
index 5447f2594659..a3014e8d97a9 100644
--- a/arch/arm/boot/dts/vf610-cosmic.dts
+++ b/arch/arm/boot/dts/vf610-cosmic.dts
@@ -19,7 +19,7 @@
                 bootargs = "console=ttyLP1,115200";
         };
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x10000000>;
         };
 
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts
index 6f787e67bd2e..6be7a828ae64 100644
--- a/arch/arm/boot/dts/vf610-twr.dts
+++ b/arch/arm/boot/dts/vf610-twr.dts
@@ -50,7 +50,7 @@
                 bootargs = "console=ttyLP1,115200";
         };
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x8000000>;
         };
 
diff --git a/arch/arm/boot/dts/vf610-zii-dev.dtsi b/arch/arm/boot/dts/vf610-zii-dev.dtsi
index aadd36db0092..4890b8a5aa44 100644
--- a/arch/arm/boot/dts/vf610-zii-dev.dtsi
+++ b/arch/arm/boot/dts/vf610-zii-dev.dtsi
@@ -49,7 +49,7 @@
                 stdout-path = "serial0:115200n8";
         };
 
-        memory {
+        memory@80000000 {
                 reg = <0x80000000 0x20000000>;
         };
 
diff --git a/arch/arm/boot/dts/vf610m4-colibri.dts b/arch/arm/boot/dts/vf610m4-colibri.dts
index 7198e8cceb0d..41ec66a96990 100644
--- a/arch/arm/boot/dts/vf610m4-colibri.dts
+++ b/arch/arm/boot/dts/vf610m4-colibri.dts
@@ -51,10 +51,10 @@
 
         chosen {
                 bootargs = "console=ttyLP2,115200 clk_ignore_unused init=/linuxrc rw";
-                linux,stdout-path = "&uart2";
+                stdout-path = "&uart2";
         };
 
-        memory {
+        memory@8c000000 {
                 reg = <0x8c000000 0x3000000>;
         };
 };
diff --git a/arch/arm/boot/dts/vf610m4.dtsi b/arch/arm/boot/dts/vf610m4.dtsi
index 1474bd34d0f1..8293276b55a6 100644
--- a/arch/arm/boot/dts/vf610m4.dtsi
+++ b/arch/arm/boot/dts/vf610m4.dtsi
@@ -42,10 +42,17 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-#include "skeleton.dtsi"
 #include "armv7-m.dtsi"
 #include "vfxxx.dtsi"
 
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        chosen { };
+        aliases { };
+        memory { device_type = "memory"; };
+};
+
 &mscm_ir {
         interrupt-parent = <&nvic>;
 };
diff --git a/arch/arm/boot/dts/zx296702.dtsi b/arch/arm/boot/dts/zx296702.dtsi
index 8a74efdb6360..240e7a23d81f 100644
--- a/arch/arm/boot/dts/zx296702.dtsi
+++ b/arch/arm/boot/dts/zx296702.dtsi
@@ -56,7 +56,7 @@
                         clocks = <&topclk ZX296702_A9_PERIPHCLK>;
                 };
 
-                l2cc: l2-cache-controller@0x00c00000 {
+                l2cc: l2-cache-controller@c00000 {
                         compatible = "arm,pl310-cache";
                         reg = <0x00c00000 0x1000>;
                         cache-unified;
@@ -67,30 +67,30 @@
                         arm,double-linefill-incr = <0>;
                 };
 
-                pcu: pcu@0xa0008000 {
+                pcu: pcu@a0008000 {
                         compatible = "zte,zx296702-pcu";
                         reg = <0xa0008000 0x1000>;
                 };
 
-                topclk: topclk@0x09800000 {
+                topclk: topclk@9800000 {
                         compatible = "zte,zx296702-topcrm-clk";
                         reg = <0x09800000 0x1000>;
                         #clock-cells = <1>;
                 };
 
-                lsp1clk: lsp1clk@0x09400000 {
+                lsp1clk: lsp1clk@9400000 {
                         compatible = "zte,zx296702-lsp1crpm-clk";
                         reg = <0x09400000 0x1000>;
                         #clock-cells = <1>;
                 };
 
-                lsp0clk: lsp0clk@0x0b000000 {
+                lsp0clk: lsp0clk@b000000 {
                         compatible = "zte,zx296702-lsp0crpm-clk";
                         reg = <0x0b000000 0x1000>;
                         #clock-cells = <1>;
                 };
 
-                uart0: serial@0x09405000 {
+                uart0: serial@9405000 {
                         compatible = "zte,zx296702-uart";
                         reg = <0x09405000 0x1000>;
                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
@@ -98,7 +98,7 @@
                         status = "disabled";
                 };
 
-                uart1: serial@0x09406000 {
+                uart1: serial@9406000 {
                         compatible = "zte,zx296702-uart";
                         reg = <0x09406000 0x1000>;
                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
@@ -106,7 +106,7 @@
                         status = "disabled";
                 };
 
-                mmc0: mmc@0x09408000 {
+                mmc0: mmc@9408000 {
                         compatible = "snps,dw-mshc";
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -119,7 +119,7 @@
                         status = "disabled";
                 };
 
-                mmc1: mmc@0x0b003000 {
+                mmc1: mmc@b003000 {
                         compatible = "snps,dw-mshc";
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -132,7 +132,7 @@
                         status = "disabled";
                 };
 
-                sysctrl: sysctrl@0xa0007000 {
+                sysctrl: sysctrl@a0007000 {
                         compatible = "zte,sysctrl", "syscon";
                         reg = <0xa0007000 0x1000>;
                 };
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 0f79fe1ccd9d..e22507e23303 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -1,14 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
- *  Copyright (C) 2011 - 2014 Xilinx
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
+ * Copyright (C) 2011 - 2014 Xilinx
  */
 
 / {
diff --git a/arch/arm/boot/dts/zynq-cc108.dts b/arch/arm/boot/dts/zynq-cc108.dts
new file mode 100644
index 000000000000..1a0f631c1d8d
--- /dev/null
+++ b/arch/arm/boot/dts/zynq-cc108.dts
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx CC108 board DTS
+ *
+ * (C) Copyright 2007-2018 Xilinx, Inc.
+ * (C) Copyright 2007-2013 Michal Simek
+ * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd
+ *
+ * Michal SIMEK <monstr@monstr.eu>
+ */
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+
+/ {
+        compatible = "xlnx,zynq-cc108", "xlnx,zynq-7000";
+        model = "Xilinx Zynq";
+
+        aliases {
+                ethernet0 = &gem0;
+                serial0 = &uart0;
+        };
+
+        chosen {
+                bootargs = "";
+                stdout-path = "serial0:115200n8";
+        };
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x20000000>;
+        };
+
+        usb_phy0: phy0 {
+                compatible = "usb-nop-xceiv";
+                #phy-cells = <0>;
+        };
+
+        usb_phy1: phy1 {
+                compatible = "usb-nop-xceiv";
+                #phy-cells = <0>;
+        };
+};
+
+&gem0 {
+        status = "okay";
+        phy-mode = "rgmii-id";
+        phy-handle = <&ethernet_phy>;
+
+        ethernet_phy: ethernet-phy@1 {
+                reg = <1>;
+                device_type = "ethernet-phy";
+        };
+};
+
+&sdhci1 {
+        status = "okay";
+        broken-cd ;
+        wp-inverted ;
+};
+
+&uart0 {
+        status = "okay";
+};
+
+&usb0 {
+        status = "okay";
+        dr_mode = "host";
+        usb-phy = <&usb_phy0>;
+};
+
+&usb1 {
+        status = "okay";
+        dr_mode = "host";
+        usb-phy = <&usb_phy1>;
+};
diff --git a/arch/arm/boot/dts/zynq-microzed.dts b/arch/arm/boot/dts/zynq-microzed.dts
index b9376a4904b4..aa4a0b6defb8 100644
--- a/arch/arm/boot/dts/zynq-microzed.dts
+++ b/arch/arm/boot/dts/zynq-microzed.dts
@@ -1,15 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (C) 2011 - 2014 Xilinx
  * Copyright (C) 2016 Jagan Teki <jteki@openedev.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 /dts-v1/;
 /include/ "zynq-7000.dtsi"
@@ -23,7 +15,7 @@
                 serial0 = &uart1;
         };
 
-        memory {
+        memory@0 {
                 device_type = "memory";
                 reg = <0x0 0x40000000>;
         };
diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts
index 0144acfa9793..c05f4b67d4c1 100644
--- a/arch/arm/boot/dts/zynq-parallella.dts
+++ b/arch/arm/boot/dts/zynq-parallella.dts
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (c) 2014 SUSE LINUX Products GmbH
  *
@@ -6,15 +7,6 @@
  *  Copyright (C) 2011 Xilinx
  *  Copyright (C) 2012 National Instruments Corp.
  *  Copyright (C) 2013 Xilinx
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 /dts-v1/;
 /include/ "zynq-7000.dtsi"
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
index 70a5de76b7db..f2330b0cb63d 100644
--- a/arch/arm/boot/dts/zynq-zc702.dts
+++ b/arch/arm/boot/dts/zynq-zc702.dts
@@ -1,15 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  *  Copyright (C) 2011 - 2014 Xilinx
  *  Copyright (C) 2012 National Instruments Corp.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 /dts-v1/;
 #include "zynq-7000.dtsi"
@@ -112,7 +104,7 @@
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_i2c0_default>;
 
-        i2cswitch@74 {
+        i2c-mux@74 {
                 compatible = "nxp,pca9548";
                 #address-cells = <1>;
                 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/zynq-zc706.dts
index cdc326ec3335..3ad1260ff2a1 100644
--- a/arch/arm/boot/dts/zynq-zc706.dts
+++ b/arch/arm/boot/dts/zynq-zc706.dts
@@ -1,15 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  *  Copyright (C) 2011 - 2014 Xilinx
  *  Copyright (C) 2012 National Instruments Corp.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 /dts-v1/;
 #include "zynq-7000.dtsi"
@@ -68,7 +60,7 @@
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_i2c0_default>;
 
-        i2cswitch@74 {
+        i2c-mux@74 {
                 compatible = "nxp,pca9548";
                 #address-cells = <1>;
                 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/zynq-zc770-xm010.dts b/arch/arm/boot/dts/zynq-zc770-xm010.dts
new file mode 100644
index 000000000000..6884f1ad66b7
--- /dev/null
+++ b/arch/arm/boot/dts/zynq-zc770-xm010.dts
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx ZC770 XM010 board DTS
+ *
+ * Copyright (C) 2013-2018 Xilinx, Inc.
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+        compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000";
+        model = "Xilinx Zynq";
+
+        aliases {
+                ethernet0 = &gem0;
+                i2c0 = &i2c0;
+                serial0 = &uart1;
+                spi1 = &spi1;
+        };
+
+        chosen {
+                bootargs = "";
+                stdout-path = "serial0:115200n8";
+        };
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x40000000>;
+        };
+
+        usb_phy0: phy0 {
+                compatible = "usb-nop-xceiv";
+                #phy-cells = <0>;
+        };
+};
+
+&can0 {
+        status = "okay";
+};
+
+&gem0 {
+        status = "okay";
+        phy-mode = "rgmii-id";
+        phy-handle = <&ethernet_phy>;
+
+        ethernet_phy: ethernet-phy@7 {
+                reg = <7>;
+                device_type = "ethernet-phy";
+        };
+};
+
+&i2c0 {
+        status = "okay";
+        clock-frequency = <400000>;
+
+        eeprom: eeprom@52 {
+                compatible = "atmel,24c02";
+                reg = <0x52>;
+        };
+
+};
+
+&sdhci0 {
+        status = "okay";
+};
+
+&spi1 {
+        status = "okay";
+        num-cs = <4>;
+        is-decoded-cs = <0>;
+        flash@0 {
+                compatible = "sst25wf080", "jedec,spi-nor";
+                reg = <1>;
+                spi-max-frequency = <1000000>;
+                partitions {
+                        compatible = "fixed-partitions";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        partition@0 {
+                                label = "data";
+                                reg = <0x0 0x100000>;
+                        };
+                };
+        };
+};
+
+&uart1 {
+        status = "okay";
+};
+
+&usb0 {
+        status = "okay";
+        dr_mode = "host";
+        usb-phy = <&usb_phy0>;
+};
diff --git a/arch/arm/boot/dts/zynq-zc770-xm011.dts b/arch/arm/boot/dts/zynq-zc770-xm011.dts
new file mode 100644
index 000000000000..b78883cee96a
--- /dev/null
+++ b/arch/arm/boot/dts/zynq-zc770-xm011.dts
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx ZC770 XM013 board DTS
+ *
+ * Copyright (C) 2013-2018 Xilinx, Inc.
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+        compatible = "xlnx,zynq-zc770-xm011", "xlnx,zynq-7000";
+        model = "Xilinx Zynq";
+
+        aliases {
+                i2c0 = &i2c1;
+                serial0 = &uart1;
+                spi0 = &spi0;
+        };
+
+        chosen {
+                bootargs = "";
+                stdout-path = "serial0:115200n8";
+        };
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x40000000>;
+        };
+
+        usb_phy1: phy1 {
+                compatible = "usb-nop-xceiv";
+                #phy-cells = <0>;
+        };
+};
+
+&can0 {
+        status = "okay";
+};
+
+&i2c1 {
+        status = "okay";
+        clock-frequency = <400000>;
+
+        eeprom: eeprom@52 {
+                compatible = "atmel,24c02";
+                reg = <0x52>;
+        };
+};
+
+&spi0 {
+        status = "okay";
+        num-cs = <4>;
+        is-decoded-cs = <0>;
+};
+
+&uart1 {
+        status = "okay";
+};
+
+&usb1 {
+        status = "okay";
+        dr_mode = "host";
+        usb-phy = <&usb_phy1>;
+};
diff --git a/arch/arm/boot/dts/zynq-zc770-xm012.dts b/arch/arm/boot/dts/zynq-zc770-xm012.dts
new file mode 100644
index 000000000000..c3169d63600d
--- /dev/null
+++ b/arch/arm/boot/dts/zynq-zc770-xm012.dts
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx ZC770 XM012 board DTS
+ *
+ * Copyright (C) 2013-2018 Xilinx, Inc.
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+        compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000";
+        model = "Xilinx Zynq";
+
+        aliases {
+                i2c0 = &i2c0;
+                i2c1 = &i2c1;
+                serial0 = &uart1;
+                spi0 = &spi1;
+        };
+
+        chosen {
+                bootargs = "";
+                stdout-path = "serial0:115200n8";
+        };
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x40000000>;
+        };
+};
+
+&can1 {
+        status = "okay";
+};
+
+&i2c0 {
+        status = "okay";
+        clock-frequency = <400000>;
+
+        eeprom0: eeprom@52 {
+                compatible = "atmel,24c02";
+                reg = <0x52>;
+        };
+};
+
+&i2c1 {
+        status = "okay";
+        clock-frequency = <400000>;
+
+        eeprom1: eeprom@52 {
+                compatible = "atmel,24c02";
+                reg = <0x52>;
+        };
+};
+
+&spi1 {
+        status = "okay";
+        num-cs = <4>;
+        is-decoded-cs = <0>;
+};
+
+&uart1 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/zynq-zc770-xm013.dts b/arch/arm/boot/dts/zynq-zc770-xm013.dts
new file mode 100644
index 000000000000..8bb66859d774
--- /dev/null
+++ b/arch/arm/boot/dts/zynq-zc770-xm013.dts
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx ZC770 XM013 board DTS
+ *
+ * Copyright (C) 2013 Xilinx, Inc.
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+        compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000";
+        model = "Xilinx Zynq";
+
+        aliases {
+                ethernet0 = &gem1;
+                i2c0 = &i2c1;
+                serial0 = &uart0;
+                spi1 = &spi0;
+        };
+
+        chosen {
+                bootargs = "";
+                stdout-path = "serial0:115200n8";
+        };
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x40000000>;
+        };
+};
+
+&can1 {
+        status = "okay";
+};
+
+&gem1 {
+        status = "okay";
+        phy-mode = "rgmii-id";
+        phy-handle = <&ethernet_phy>;
+
+        ethernet_phy: ethernet-phy@7 {
+                reg = <7>;
+                device_type = "ethernet-phy";
+        };
+};
+
+&i2c1 {
+        status = "okay";
+        clock-frequency = <400000>;
+
+        si570: clock-generator@55 {
+                #clock-cells = <0>;
+                compatible = "silabs,si570";
+                temperature-stability = <50>;
+                reg = <0x55>;
+                factory-fout = <156250000>;
+                clock-frequency = <148500000>;
+        };
+};
+
+&spi0 {
+        status = "okay";
+        num-cs = <4>;
+        is-decoded-cs = <0>;
+        eeprom: eeprom@0 {
+                at25,byte-len = <8192>;
+                at25,addr-mode = <2>;
+                at25,page-size = <32>;
+
+                compatible = "atmel,at25";
+                reg = <2>;
+                spi-max-frequency = <1000000>;
+        };
+};
+
+&uart0 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/zynq-zed.dts b/arch/arm/boot/dts/zynq-zed.dts
index 5e44dc12fd60..53c6883ce1f6 100644
--- a/arch/arm/boot/dts/zynq-zed.dts
+++ b/arch/arm/boot/dts/zynq-zed.dts
@@ -1,15 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  *  Copyright (C) 2011 - 2014 Xilinx
  *  Copyright (C) 2012 National Instruments Corp.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 /dts-v1/;
 #include "zynq-7000.dtsi"
diff --git a/arch/arm/boot/dts/zynq-zybo-z7.dts b/arch/arm/boot/dts/zynq-zybo-z7.dts
new file mode 100644
index 000000000000..1e713dc98920
--- /dev/null
+++ b/arch/arm/boot/dts/zynq-zybo-z7.dts
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+        model = "Zynq ZYBO Z7 Development Board";
+        compatible = "digilent,zynq-zybo-z7", "xlnx,zynq-7000";
+
+        aliases {
+                ethernet0 = &gem0;
+                serial0 = &uart1;
+        };
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x20000000>;
+        };
+
+        chosen {
+                bootargs = "";
+                stdout-path = "serial0:115200n8";
+        };
+
+        usb_phy0: phy0 {
+                #phy-cells = <0>;
+                compatible = "usb-nop-xceiv";
+                reset-gpios = <&gpio0 46 1>;
+        };
+};
+
+&clkc {
+        ps-clk-frequency = <33333333>;
+};
+
+&gem0 {
+        status = "okay";
+        phy-mode = "rgmii-id";
+        phy-handle = <&ethernet_phy>;
+
+        ethernet_phy: ethernet-phy@0 {
+                reg = <0>;
+                device_type = "ethernet-phy";
+        };
+};
+
+&sdhci0 {
+        status = "okay";
+};
+
+&uart1 {
+        status = "okay";
+};
+
+&usb0 {
+        status = "okay";
+        dr_mode = "host";
+        usb-phy = <&usb_phy0>;
+};
diff --git a/arch/arm/boot/dts/zynq-zybo.dts b/arch/arm/boot/dts/zynq-zybo.dts
index e40cafc5ee5b..a6c00e7fa767 100644
--- a/arch/arm/boot/dts/zynq-zybo.dts
+++ b/arch/arm/boot/dts/zynq-zybo.dts
@@ -1,15 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  *  Copyright (C) 2011 - 2014 Xilinx
  *  Copyright (C) 2012 National Instruments Corp.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 /dts-v1/;
 #include "zynq-7000.dtsi"
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index da7387689b88..28f1d714e5b9 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -751,6 +751,7 @@ CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MMC_SH_MMCIF=y
 CONFIG_MMC_SUNXI=y
 CONFIG_MMC_BCM2835=y
+CONFIG_MMC_SDHCI_OMAP=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_CLASS_FLASH=m
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index 2f145c4af93a..bce7e5abcc05 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -319,7 +319,7 @@ CONFIG_MEDIA_CAMERA_SUPPORT=y
 CONFIG_RC_CORE=m
 CONFIG_MEDIA_CONTROLLER=y
 CONFIG_VIDEO_V4L2_SUBDEV_API=y
-CONFIG_LIRC=m
+CONFIG_LIRC=y
 CONFIG_RC_DEVICES=y
 CONFIG_IR_RX51=m
 CONFIG_V4L_PLATFORM_DRIVERS=y
@@ -431,8 +431,11 @@ CONFIG_USB_ZERO=m
 CONFIG_USB_G_NOKIA=m
 CONFIG_MMC=y
 CONFIG_SDIO_UART=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_OMAP=y
 CONFIG_MMC_OMAP_HS=y
+CONFIG_MMC_SDHCI_OMAP=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=m
 CONFIG_LEDS_CPCAP=m
diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c
index 629f8e9981f1..cf2701cb0de8 100644
--- a/arch/arm/kernel/time.c
+++ b/arch/arm/kernel/time.c
@@ -83,7 +83,7 @@ static void dummy_clock_access(struct timespec64 *ts)
 }
 
 static clock_access_fn __read_persistent_clock = dummy_clock_access;
-static clock_access_fn __read_boot_clock = dummy_clock_access;;
+static clock_access_fn __read_boot_clock = dummy_clock_access;
 
 void read_persistent_clock64(struct timespec64 *ts)
 {
diff --git a/arch/arm/kvm/hyp/Makefile b/arch/arm/kvm/hyp/Makefile
index 5638ce0c9524..63d6b404d88e 100644
--- a/arch/arm/kvm/hyp/Makefile
+++ b/arch/arm/kvm/hyp/Makefile
@@ -7,6 +7,8 @@ ccflags-y += -fno-stack-protector -DDISABLE_BRANCH_PROFILING
 
 KVM=../../../../virt/kvm
 
+CFLAGS_ARMV7VE             :=$(call cc-option, -march=armv7ve)
+
 obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/vgic-v2-sr.o
 obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/vgic-v3-sr.o
 obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/timer-sr.o
@@ -15,7 +17,10 @@ obj-$(CONFIG_KVM_ARM_HOST) += tlb.o
 obj-$(CONFIG_KVM_ARM_HOST) += cp15-sr.o
 obj-$(CONFIG_KVM_ARM_HOST) += vfp.o
 obj-$(CONFIG_KVM_ARM_HOST) += banked-sr.o
+CFLAGS_banked-sr.o         += $(CFLAGS_ARMV7VE)
+
 obj-$(CONFIG_KVM_ARM_HOST) += entry.o
 obj-$(CONFIG_KVM_ARM_HOST) += hyp-entry.o
 obj-$(CONFIG_KVM_ARM_HOST) += switch.o
+CFLAGS_switch.o            += $(CFLAGS_ARMV7VE)
 obj-$(CONFIG_KVM_ARM_HOST) += s2-setup.o
diff --git a/arch/arm/kvm/hyp/banked-sr.c b/arch/arm/kvm/hyp/banked-sr.c
index 111bda8cdebd..be4b8b0a40ad 100644
--- a/arch/arm/kvm/hyp/banked-sr.c
+++ b/arch/arm/kvm/hyp/banked-sr.c
@@ -20,6 +20,10 @@
 
 #include <asm/kvm_hyp.h>
 
+/*
+ * gcc before 4.9 doesn't understand -march=armv7ve, so we have to
+ * trick the assembler.
+ */
 __asm__(".arch_extension     virt");
 
 void __hyp_text __banked_save_state(struct kvm_cpu_context *ctxt)
diff --git a/arch/arm/mach-clps711x/board-dt.c b/arch/arm/mach-clps711x/board-dt.c
index ee1f83b1a332..4c89a8e9a2e3 100644
--- a/arch/arm/mach-clps711x/board-dt.c
+++ b/arch/arm/mach-clps711x/board-dt.c
@@ -69,7 +69,7 @@ static void clps711x_restart(enum reboot_mode mode, const char *cmd)
         soft_restart(0);
 }
 
-static const char *clps711x_compat[] __initconst = {
+static const char *const clps711x_compat[] __initconst = {
         "cirrus,ep7209",
         NULL
 };
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index e457f299cd44..d6b11907380c 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -368,7 +368,7 @@ static struct spi_eeprom at25640a = {
         .flags          = EE_ADDR2,
 };
 
-static struct spi_board_info dm355_evm_spi_info[] __initconst = {
+static const struct spi_board_info dm355_evm_spi_info[] __initconst = {
         {
                 .modalias       = "at25",
                 .platform_data  = &at25640a,
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
index be997243447b..fad9a5611a5d 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -217,7 +217,7 @@ static struct spi_eeprom at25640a = {
         .flags          = EE_ADDR2,
 };
 
-static struct spi_board_info dm355_leopard_spi_info[] __initconst = {
+static const struct spi_board_info dm355_leopard_spi_info[] __initconst = {
         {
                 .modalias       = "at25",
                 .platform_data  = &at25640a,
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index e75741fb2c1d..e3780986d2a3 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -726,7 +726,7 @@ static struct spi_eeprom at25640 = {
         .flags          = EE_ADDR2,
 };
 
-static struct spi_board_info dm365_evm_spi_info[] __initconst = {
+static const struct spi_board_info dm365_evm_spi_info[] __initconst = {
         {
                 .modalias       = "at25",
                 .platform_data  = &at25640,
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 6b32dc527edc..2c20599cc350 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -41,7 +41,7 @@ config MACH_ARMADA_375
         depends on ARCH_MULTI_V7
         select ARMADA_370_XP_IRQ
         select ARM_ERRATA_720789
-        select ARM_ERRATA_753970
+        select PL310_ERRATA_753970
         select ARM_GIC
         select ARMADA_375_CLK
         select HAVE_ARM_SCU
@@ -57,7 +57,7 @@ config MACH_ARMADA_38X
         bool "Marvell Armada 380/385 boards"
         depends on ARCH_MULTI_V7
         select ARM_ERRATA_720789
-        select ARM_ERRATA_753970
+        select PL310_ERRATA_753970
         select ARM_GIC
         select ARM_GLOBAL_TIMER
         select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index 43e3e188f521..fa512413a471 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -1011,17 +1011,17 @@ static int clk_debugfs_register_one(struct clk *c)
                 return -ENOMEM;
         c->dent = d;
 
-        d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usecount);
+        d = debugfs_create_u8("usecount", S_IRUGO, c->dent, &c->usecount);
         if (!d) {
                 err = -ENOMEM;
                 goto err_out;
         }
-        d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
+        d = debugfs_create_ulong("rate", S_IRUGO, c->dent, &c->rate);
         if (!d) {
                 err = -ENOMEM;
                 goto err_out;
         }
-        d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
+        d = debugfs_create_x8("flags", S_IRUGO, c->dent, &c->flags);
         if (!d) {
                 err = -ENOMEM;
                 goto err_out;
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index 4bb6751864a5..fc5fb776a710 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -299,8 +299,6 @@ static void irq_save_context(void)
         if (soc_is_dra7xx())
                 return;
 
-        if (!sar_base)
-                sar_base = omap4_get_sar_ram_base();
         if (wakeupgen_ops && wakeupgen_ops->save_context)
                 wakeupgen_ops->save_context();
 }
@@ -598,6 +596,8 @@ static int __init wakeupgen_init(struct device_node *node,
         irq_hotplug_init();
         irq_pm_init();
 
+        sar_base = omap4_get_sar_ram_base();
+
         return 0;
 }
 IRQCHIP_DECLARE(ti_wakeupgen, "ti,omap4-wugen-mpu", wakeupgen_init);
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 124f9af34a15..34156eca8e23 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -977,6 +977,9 @@ static int _enable_clocks(struct omap_hwmod *oh)
 
         pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name);
 
+        if (oh->flags & HWMOD_OPT_CLKS_NEEDED)
+                _enable_optional_clocks(oh);
+
         if (oh->_clk)
                 clk_enable(oh->_clk);
 
@@ -985,9 +988,6 @@ static int _enable_clocks(struct omap_hwmod *oh)
                         clk_enable(os->_clk);
         }
 
-        if (oh->flags & HWMOD_OPT_CLKS_NEEDED)
-                _enable_optional_clocks(oh);
-
         /* The opt clocks are controlled by the device driver. */
 
         return 0;
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 366158a54fcd..6f68576e5695 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -186,7 +186,7 @@ static void omap_pm_end(void)
         cpu_idle_poll_ctrl(false);
 }
 
-static void omap_pm_finish(void)
+static void omap_pm_wake(void)
 {
         if (soc_is_omap34xx())
                 omap_prcm_irq_complete();
@@ -196,7 +196,7 @@ static const struct platform_suspend_ops omap_pm_ops = {
         .begin          = omap_pm_begin,
         .end            = omap_pm_end,
         .enter          = omap_pm_enter,
-        .finish         = omap_pm_finish,
+        .wake           = omap_pm_wake,
         .valid          = suspend_valid_only_mem,
 };
 
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index ece09c9461f7..d61fbd7a2840 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -156,12 +156,6 @@ static struct clock_event_device clockevent_gpt = {
         .tick_resume            = omap2_gp_timer_shutdown,
 };
 
-static struct property device_disabled = {
-        .name = "status",
-        .length = sizeof("disabled"),
-        .value = "disabled",
-};
-
 static const struct of_device_id omap_timer_match[] __initconst = {
         { .compatible = "ti,omap2420-timer", },
         { .compatible = "ti,omap3430-timer", },
@@ -203,8 +197,17 @@ static struct device_node * __init omap_get_timer_dt(const struct of_device_id *
                                   of_get_property(np, "ti,timer-secure", NULL)))
                         continue;
 
-                if (!of_device_is_compatible(np, "ti,omap-counter32k"))
-                        of_add_property(np, &device_disabled);
+                if (!of_device_is_compatible(np, "ti,omap-counter32k")) {
+                        struct property *prop;
+
+                        prop = kzalloc(sizeof(*prop), GFP_KERNEL);
+                        if (!prop)
+                                return NULL;
+                        prop->name = "status";
+                        prop->value = "disabled";
+                        prop->length = strlen(prop->value);
+                        of_add_property(np, prop);
+                }
                 return np;
         }
 
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 57058ac46f49..7e5d7a083707 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -23,7 +23,6 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_platform.h>
-#include <linux/perf/arm_pmu.h>
 #include <linux/regulator/machine.h>
 
 #include <asm/outercache.h>
@@ -112,37 +111,6 @@ static void ux500_restart(enum reboot_mode mode, const char *cmd)
         prcmu_system_reset(0);
 }
 
-/*
- * The PMU IRQ lines of two cores are wired together into a single interrupt.
- * Bounce the interrupt to the other core if it's not ours.
- */
-static irqreturn_t db8500_pmu_handler(int irq, void *dev, irq_handler_t handler)
-{
-        irqreturn_t ret = handler(irq, dev);
-        int other = !smp_processor_id();
-
-        if (ret == IRQ_NONE && cpu_online(other))
-                irq_set_affinity(irq, cpumask_of(other));
-
-        /*
-         * We should be able to get away with the amount of IRQ_NONEs we give,
-         * while still having the spurious IRQ detection code kick in if the
-         * interrupt really starts hitting spuriously.
-         */
-        return ret;
-}
-
-static struct arm_pmu_platdata db8500_pmu_platdata = {
-        .handle_irq             = db8500_pmu_handler,
-        .irq_flags              = IRQF_NOBALANCING | IRQF_NO_THREAD,
-};
-
-static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
-        /* Requires call-back bindings. */
-        OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
-        {},
-};
-
 static struct of_dev_auxdata u8540_auxdata_lookup[] __initdata = {
         OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu", NULL),
         {},
@@ -165,9 +133,6 @@ static void __init u8500_init_machine(void)
         if (of_machine_is_compatible("st-ericsson,u8540"))
                 of_platform_populate(NULL, u8500_local_bus_nodes,
                                      u8540_auxdata_lookup, NULL);
-        else
-                of_platform_populate(NULL, u8500_local_bus_nodes,
-                                     u8500_auxdata_lookup, NULL);
 }
 
 static const char * stericsson_dt_platform_compat[] = {
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
index aff6994950ba..a2399fd66e97 100644
--- a/arch/arm/plat-orion/common.c
+++ b/arch/arm/plat-orion/common.c
@@ -472,28 +472,27 @@ void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data,
 /*****************************************************************************
  * Ethernet switch
  ****************************************************************************/
-static __initconst const char *orion_ge00_mvmdio_bus_name = "orion-mii";
-static __initdata struct mdio_board_info
-                  orion_ge00_switch_board_info;
+static __initdata struct mdio_board_info orion_ge00_switch_board_info = {
+        .bus_id   = "orion-mii",
+        .modalias = "mv88e6085",
+};
 
 void __init orion_ge00_switch_init(struct dsa_chip_data *d)
 {
-        struct mdio_board_info *bd;
         unsigned int i;
 
         if (!IS_BUILTIN(CONFIG_PHYLIB))
                 return;
 
-        for (i = 0; i < ARRAY_SIZE(d->port_names); i++)
-                if (!strcmp(d->port_names[i], "cpu"))
+        for (i = 0; i < ARRAY_SIZE(d->port_names); i++) {
+                if (!strcmp(d->port_names[i], "cpu")) {
+                        d->netdev[i] = &orion_ge00.dev;
                         break;
+                }
+        }
 
-        bd = &orion_ge00_switch_board_info;
-        bd->bus_id = orion_ge00_mvmdio_bus_name;
-        bd->mdio_addr = d->sw_addr;
-        d->netdev[i] = &orion_ge00.dev;
-        strcpy(bd->modalias, "mv88e6085");
-        bd->platform_data = d;
+        orion_ge00_switch_board_info.mdio_addr = d->sw_addr;
+        orion_ge00_switch_board_info.platform_data = d;
 
         mdiobus_register_board_info(&orion_ge00_switch_board_info, 1);
 }
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index fbedbd8f619a..2b1535cdeb7c 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -190,12 +190,24 @@ config ARCH_R8A7796
         help
           This enables support for the Renesas R-Car M3-W SoC.
 
+config ARCH_R8A77965
+        bool "Renesas R-Car M3-N SoC Platform"
+        depends on ARCH_RENESAS
+        help
+          This enables support for the Renesas R-Car M3-N SoC.
+
 config ARCH_R8A77970
         bool "Renesas R-Car V3M SoC Platform"
         depends on ARCH_RENESAS
         help
           This enables support for the Renesas R-Car V3M SoC.
 
+config ARCH_R8A77980
+        bool "Renesas R-Car V3H SoC Platform"
+        depends on ARCH_RENESAS
+        help
+          This enables support for the Renesas R-Car V3H SoC.
+
 config ARCH_R8A77995
         bool "Renesas R-Car D3 SoC Platform"
         depends on ARCH_RENESAS
diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
index f505227b0250..8bebe7da5ed9 100644
--- a/arch/arm64/boot/dts/allwinner/Makefile
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -5,8 +5,11 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-orangepi-win.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-teres-i.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-plus2.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
index a6975670cd1c..2250dec9974c 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
@@ -120,8 +120,7 @@
         pinctrl-names = "default";
         pinctrl-0 = <&mmc0_pins>;
         vmmc-supply = <&reg_dcdc1>;
-        cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
-        cd-inverted;
+        cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
         disable-wp;
         bus-width = <4>;
         status = "okay";
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
index 2beef9e6cb88..e2dce48fa29a 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
@@ -82,8 +82,7 @@
         pinctrl-names = "default";
         pinctrl-0 = <&mmc0_pins>;
         vmmc-supply = <&reg_dcdc1>;
-        cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
-        cd-inverted;
+        cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
         disable-wp;
         bus-width = <4>;
         status = "okay";
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
index 8807664f363a..3b3081b10ecb 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
@@ -68,8 +68,7 @@
         pinctrl-names = "default";
         pinctrl-0 = <&mmc0_pins>;
         vmmc-supply = <&reg_dcdc1>;
-        cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
-        cd-inverted;
+        cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
         disable-wp;
         bus-width = <4>;
         status = "okay";
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
index 240d35731d10..bf42690a3361 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
@@ -67,8 +67,7 @@
         pinctrl-names = "default";
         pinctrl-0 = <&mmc0_pins>;
         vmmc-supply = <&reg_dcdc1>;
-        cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
-        cd-inverted;
+        cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
         status = "okay";
 };
 
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
index 604cdaedac38..a75825798a71 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
@@ -103,8 +103,7 @@
         pinctrl-names = "default";
         pinctrl-0 = <&mmc0_pins>;
         vmmc-supply = <&reg_dcdc1>;
-        cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
-        cd-inverted;
+        cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
         disable-wp;
         bus-width = <4>;
         status = "okay";
@@ -230,6 +229,11 @@
         regulator-name = "vcc-rtc";
 };
 
+/* On Euler connector */
+&spdif {
+        status = "disabled";
+};
+
 /* On Exp and Euler connectors */
 &uart0 {
         pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts
new file mode 100644
index 000000000000..d9baab3dc96b
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts
@@ -0,0 +1,265 @@
+/*
+ * Copyright (C) Harald Geyer <harald@ccbib.org>
+ * based on sun50i-a64-olinuxino.dts by Jagan Teki <jteki@openedev.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+/dts-v1/;
+
+#include "sun50i-a64.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+        model = "Olimex A64 Teres-I";
+        compatible = "olimex,a64-teres-i", "allwinner,sun50i-a64";
+
+        aliases {
+                serial0 = &uart0;
+        };
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+
+                framebuffer-lcd {
+                        eDP25-supply = <&reg_dldo2>;
+                        eDP12-supply = <&reg_dldo3>;
+                };
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+
+                lid-switch {
+                        label = "Lid Switch";
+                        gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 */
+                        linux,input-type = <EV_SW>;
+                        linux,code = <SW_LID>;
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                capslock {
+                        label = "teres-i:green:capslock";
+                        gpios = <&pio 2 7 GPIO_ACTIVE_HIGH>; /* PC7 */
+                };
+
+                numlock {
+                        label = "teres-i:green:numlock";
+                        gpios = <&pio 2 4 GPIO_ACTIVE_HIGH>; /* PC4 */
+                };
+        };
+
+        reg_usb1_vbus: usb1-vbus {
+                compatible = "regulator-fixed";
+                regulator-name = "usb1-vbus";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                enable-active-high;
+                gpio = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
+                status = "okay";
+        };
+
+        wifi_pwrseq: wifi_pwrseq {
+                compatible = "mmc-pwrseq-simple";
+                reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
+        };
+};
+
+&ehci1 {
+        status = "okay";
+};
+
+
+/* The ANX6345 eDP-bridge is on i2c0. There is no linux (mainline)
+ * driver for this chip at the moment, the bootloader initializes it.
+ * However it can be accessed with the i2c-dev driver from user space.
+ */
+&i2c0 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c0_pins>;
+        status = "okay";
+};
+
+&mmc0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc0_pins>;
+        vmmc-supply = <&reg_dcdc1>;
+        cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
+        disable-wp;
+        bus-width = <4>;
+        status = "okay";
+};
+
+&mmc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc1_pins>;
+        vmmc-supply = <&reg_aldo2>;
+        vqmmc-supply = <&reg_dldo4>;
+        mmc-pwrseq = <&wifi_pwrseq>;
+        bus-width = <4>;
+        non-removable;
+        status = "okay";
+
+        rtl8723bs: wifi@1 {
+                reg = <1>;
+                interrupt-parent = <&r_pio>;
+                interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */
+                interrupt-names = "host-wake";
+        };
+};
+
+&mmc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc2_pins>;
+        vmmc-supply = <&reg_dcdc1>;
+        vqmmc-supply = <&reg_dcdc1>;
+        bus-width = <8>;
+        non-removable;
+        cap-mmc-hw-reset;
+        status = "okay";
+};
+
+&ohci1 {
+        status = "okay";
+};
+
+&r_rsb {
+        status = "okay";
+
+        axp803: pmic@3a3 {
+                compatible = "x-powers,axp803";
+                reg = <0x3a3>;
+                interrupt-parent = <&r_intc>;
+                interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+                wakeup-source;
+        };
+};
+
+#include "axp803.dtsi"
+
+&reg_aldo1 {
+        regulator-always-on;
+        regulator-min-microvolt = <2800000>;
+        regulator-max-microvolt = <2800000>;
+        regulator-name = "vcc-pe";
+};
+
+&reg_aldo2 {
+        regulator-always-on;
+        regulator-min-microvolt = <3300000>;
+        regulator-max-microvolt = <3300000>;
+        regulator-name = "vcc-pl";
+};
+
+&reg_aldo3 {
+        regulator-always-on;
+        regulator-min-microvolt = <3000000>;
+        regulator-max-microvolt = <3000000>;
+        regulator-name = "vcc-pll-avcc";
+};
+
+&reg_dcdc1 {
+        regulator-always-on;
+        regulator-min-microvolt = <3300000>;
+        regulator-max-microvolt = <3300000>;
+        regulator-name = "vcc-3v3";
+};
+
+&reg_dcdc2 {
+        regulator-always-on;
+        regulator-min-microvolt = <1040000>;
+        regulator-max-microvolt = <1300000>;
+        regulator-name = "vdd-cpux";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+&reg_dcdc5 {
+        regulator-always-on;
+        regulator-min-microvolt = <1500000>;
+        regulator-max-microvolt = <1500000>;
+        regulator-name = "vcc-ddr3";
+};
+
+&reg_dcdc6 {
+        regulator-always-on;
+        regulator-min-microvolt = <1100000>;
+        regulator-max-microvolt = <1100000>;
+        regulator-name = "vdd-sys";
+};
+
+&reg_dldo1 {
+        regulator-min-microvolt = <3300000>;
+        regulator-max-microvolt = <3300000>;
+        regulator-name = "vcc-hdmi";
+};
+
+&reg_dldo2 {
+        regulator-min-microvolt = <2500000>;
+        regulator-max-microvolt = <2500000>;
+        regulator-name = "vcc-pd";
+};
+
+&reg_dldo3 {
+        regulator-min-microvolt = <1200000>;
+        regulator-max-microvolt = <1200000>;
+        regulator-name = "eDP12";
+};
+
+&reg_dldo4 {
+        regulator-min-microvolt = <3300000>;
+        regulator-max-microvolt = <3300000>;
+        regulator-name = "vcc-wifi-io";
+};
+
+&reg_eldo1 {
+        regulator-min-microvolt = <1800000>;
+        regulator-max-microvolt = <1800000>;
+        regulator-name = "cpvdd";
+};
+
+&reg_eldo2 {
+        regulator-min-microvolt = <1800000>;
+        regulator-max-microvolt = <1800000>;
+        regulator-name = "vcc-dvdd-csi";
+};
+
+&reg_fldo1 {
+        regulator-min-microvolt = <1200000>;
+        regulator-max-microvolt = <1200000>;
+        regulator-name = "vcc-1v2-hsic";
+};
+
+/*
+ * The A64 chip cannot work without this regulator off, although
+ * it seems to be only driving the AR100 core.
+ * Maybe we don't still know well about CPUs domain.
+ */
+&reg_fldo2 {
+        regulator-always-on;
+        regulator-min-microvolt = <1100000>;
+        regulator-max-microvolt = <1100000>;
+        regulator-name = "vdd-cpus";
+};
+
+&reg_rtc_ldo {
+        regulator-name = "vcc-rtc";
+};
+
+&uart0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart0_pins_a>;
+        status = "okay";
+};
+
+&usbphy {
+        usb1_vbus-supply = <&reg_usb1_vbus>;
+        status = "okay";
+};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index d783d164b9c3..1b2ef28c42bd 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -52,6 +52,26 @@
         #address-cells = <1>;
         #size-cells = <1>;
 
+        chosen {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+/*
+ * The pipeline mixer0-lcd0 depends on clock CLK_MIXER0 from DE2 CCU.
+ * However there is no support for this clock on A64 yet, so we depend
+ * on the upstream clocks here to keep them (and thus CLK_MIXER0) up.
+ */
+                simplefb_lcd: framebuffer-lcd {
+                        compatible = "allwinner,simple-framebuffer",
+                                     "simple-framebuffer";
+                        allwinner,pipeline = "mixer0-lcd0";
+                        clocks = <&ccu CLK_TCON0>,
+                                 <&ccu CLK_DE>, <&ccu CLK_BUS_DE>;
+                        status = "disabled";
+                };
+        };
+
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -112,6 +132,24 @@
                 method = "smc";
         };
 
+        sound_spdif {
+                compatible = "simple-audio-card";
+                simple-audio-card,name = "On-board SPDIF";
+
+                simple-audio-card,cpu {
+                        sound-dai = <&spdif>;
+                };
+
+                simple-audio-card,codec {
+                        sound-dai = <&spdif_out>;
+                };
+        };
+
+        spdif_out: spdif-out {
+                #sound-dai-cells = <0>;
+                compatible = "linux,spdif-dit";
+        };
+
         timer {
                 compatible = "arm,armv8-timer";
                 interrupts = <GIC_PPI 13
@@ -291,6 +329,11 @@
                         interrupt-controller;
                         #interrupt-cells = <3>;
 
+                        i2c0_pins: i2c0_pins {
+                                pins = "PH0", "PH1";
+                                function = "i2c0";
+                        };
+
                         i2c1_pins: i2c1_pins {
                                 pins = "PH2", "PH3";
                                 function = "i2c1";
@@ -336,6 +379,11 @@
                                 drive-strength = <40>;
                         };
 
+                        spdif_tx_pin: spdif {
+                                pins = "PH8";
+                                function = "spdif";
+                        };
+
                         spi0_pins: spi0 {
                                 pins = "PC0", "PC1", "PC2", "PC3";
                                 function = "spi0";
@@ -382,6 +430,50 @@
                         };
                 };
 
+                spdif: spdif@1c21000 {
+                        #sound-dai-cells = <0>;
+                        compatible = "allwinner,sun50i-a64-spdif",
+                                     "allwinner,sun8i-h3-spdif";
+                        reg = <0x01c21000 0x400>;
+                        interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
+                        resets = <&ccu RST_BUS_SPDIF>;
+                        clock-names = "apb", "spdif";
+                        dmas = <&dma 2>;
+                        dma-names = "tx";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&spdif_tx_pin>;
+                        status = "disabled";
+                };
+
+                i2s0: i2s@1c22000 {
+                        #sound-dai-cells = <0>;
+                        compatible = "allwinner,sun50i-a64-i2s",
+                                     "allwinner,sun8i-h3-i2s";
+                        reg = <0x01c22000 0x400>;
+                        interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
+                        clock-names = "apb", "mod";
+                        resets = <&ccu RST_BUS_I2S0>;
+                        dma-names = "rx", "tx";
+                        dmas = <&dma 3>, <&dma 3>;
+                        status = "disabled";
+                };
+
+                i2s1: i2s@1c22400 {
+                        #sound-dai-cells = <0>;
+                        compatible = "allwinner,sun50i-a64-i2s",
+                                     "allwinner,sun8i-h3-i2s";
+                        reg = <0x01c22400 0x400>;
+                        interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
+                        clock-names = "apb", "mod";
+                        resets = <&ccu RST_BUS_I2S1>;
+                        dma-names = "rx", "tx";
+                        dmas = <&dma 4>, <&dma 4>;
+                        status = "disabled";
+                };
+
                 uart0: serial@1c28000 {
                         compatible = "snps,dw-apb-uart";
                         reg = <0x01c28000 0x400>;
@@ -593,5 +685,12 @@
                         #address-cells = <1>;
                         #size-cells = <0>;
                 };
+
+                wdt0: watchdog@1c20ca0 {
+                        compatible = "allwinner,sun50i-a64-wdt",
+                                     "allwinner,sun6i-a31-wdt";
+                        reg = <0x01c20ca0 0x20>;
+                        interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+                };
         };
 };
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts
index 1ed9f219deaf..506e25ba028a 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts
@@ -151,8 +151,6 @@
 };
 
 &mmc0 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mmc0_pins_a>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
         cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
@@ -160,8 +158,6 @@
 };
 
 &mmc1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mmc1_pins_a>;
         vmmc-supply = <&reg_vcc3v3>;
         vqmmc-supply = <&reg_vcc3v3>;
         mmc-pwrseq = <&wifi_pwrseq>;
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
index f1447003ea3c..cc268a69786c 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
@@ -126,8 +126,6 @@
 };
 
 &mmc0 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mmc0_pins_a>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
         cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
index 9e51d3a5f4e6..98862c7c7258 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
@@ -67,6 +67,17 @@
                 stdout-path = "serial0:115200n8";
         };
 
+        connector {
+                compatible = "hdmi-connector";
+                type = "a";
+
+                port {
+                        hdmi_con_in: endpoint {
+                                remote-endpoint = <&hdmi_out_con>;
+                        };
+                };
+        };
+
         leds {
                 compatible = "gpio-leds";
 
@@ -121,6 +132,10 @@
         status = "okay";
 };
 
+&de {
+        status = "okay";
+};
+
 &ehci0 {
         status = "okay";
 };
@@ -153,6 +168,16 @@
         };
 };
 
+&hdmi {
+        status = "okay";
+};
+
+&hdmi_out {
+        hdmi_out_con: endpoint {
+                remote-endpoint = <&hdmi_con_in>;
+        };
+};
+
 &ir {
         pinctrl-names = "default";
         pinctrl-0 = <&ir_pins_a>;
@@ -160,8 +185,6 @@
 };
 
 &mmc0 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mmc0_pins_a>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
         cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
index 0f25c4a6f15d..b75ca4d7d001 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
@@ -62,6 +62,17 @@
                 stdout-path = "serial0:115200n8";
         };
 
+        connector {
+                compatible = "hdmi-connector";
+                type = "a";
+
+                port {
+                        hdmi_con_in: endpoint {
+                                remote-endpoint = <&hdmi_out_con>;
+                        };
+                };
+        };
+
         leds {
                 compatible = "gpio-leds";
 
@@ -128,6 +139,10 @@
         status = "okay";
 };
 
+&de {
+        status = "okay";
+};
+
 &ehci0 {
         status = "okay";
 };
@@ -160,6 +175,16 @@
         };
 };
 
+&hdmi {
+        status = "okay";
+};
+
+&hdmi_out {
+        hdmi_out_con: endpoint {
+                remote-endpoint = <&hdmi_con_in>;
+        };
+};
+
 &ir {
         pinctrl-names = "default";
         pinctrl-0 = <&ir_pins_a>;
@@ -167,8 +192,6 @@
 };
 
 &mmc0 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mmc0_pins_a>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
         cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
@@ -176,8 +199,6 @@
 };
 
 &mmc1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mmc1_pins_a>;
         vmmc-supply = <&reg_vcc3v3>;
         mmc-pwrseq = <&wifi_pwrseq>;
         bus-width = <4>;
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts
new file mode 100644
index 000000000000..1238de25a969
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts
@@ -0,0 +1,143 @@
+/*
+ * Copyright (C) 2016 ARM Ltd.
+ * Copyright (C) 2018 Hauke Mehrtens <hauke@hauke-m.de>
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR X11)
+ */
+
+/dts-v1/;
+#include "sun50i-h5.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+        model = "Xunlong Orange Pi Zero Plus";
+        compatible = "xunlong,orangepi-zero-plus", "allwinner,sun50i-h5";
+
+        reg_vcc3v3: vcc3v3 {
+                compatible = "regulator-fixed";
+                regulator-name = "vcc3v3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
+
+        aliases {
+                ethernet0 = &emac;
+                ethernet1 = &rtl8189ftv;
+                serial0 = &uart0;
+        };
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                pwr {
+                        label = "orangepi:green:pwr";
+                        gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */
+                        default-state = "on";
+                };
+
+                status {
+                        label = "orangepi:red:status";
+                        gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>; /* PA17 */
+                };
+        };
+
+        reg_gmac_3v3: gmac-3v3 {
+                compatible = "regulator-fixed";
+                regulator-name = "gmac-3v3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                startup-delay-us = <100000>;
+                enable-active-high;
+                gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
+        };
+};
+
+&ehci0 {
+        status = "okay";
+};
+
+&ehci1 {
+        status = "okay";
+};
+
+&emac {
+        pinctrl-names = "default";
+        pinctrl-0 = <&emac_rgmii_pins>;
+        phy-supply = <&reg_gmac_3v3>;
+        phy-handle = <&ext_rgmii_phy>;
+        phy-mode = "rgmii";
+        status = "okay";
+};
+
+&external_mdio {
+        ext_rgmii_phy: ethernet-phy@1 {
+                compatible = "ethernet-phy-ieee802.3-c22";
+                reg = <1>;
+        };
+};
+
+&mmc0 {
+        vmmc-supply = <&reg_vcc3v3>;
+        bus-width = <4>;
+        cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+        status = "okay";
+};
+
+&mmc1 {
+        vmmc-supply = <&reg_vcc3v3>;
+        bus-width = <4>;
+        non-removable;
+        status = "okay";
+
+        /*
+         * Explicitly define the sdio device, so that we can add an ethernet
+         * alias for it (which e.g. makes u-boot set a mac-address).
+         */
+        rtl8189ftv: sdio_wifi@1 {
+                reg = <1>;
+        };
+};
+
+&spi0  {
+        status = "okay";
+
+        flash@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "mxicy,mx25l1606e", "winbond,w25q128";
+                reg = <0>;
+                spi-max-frequency = <40000000>;
+        };
+};
+
+&ohci0 {
+        status = "okay";
+};
+
+&ohci1 {
+        status = "okay";
+};
+
+&uart0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart0_pins_a>;
+        status = "okay";
+};
+
+&usb_otg {
+        dr_mode = "peripheral";
+        status = "okay";
+};
+
+&usbphy {
+        /* USB Type-A ports' VBUS is always on */
+        usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
+        status = "okay";
+};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts
index af43533c7134..53c8c11620e0 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts
@@ -58,6 +58,17 @@
                 stdout-path = "serial0:115200n8";
         };
 
+        connector {
+                compatible = "hdmi-connector";
+                type = "a";
+
+                port {
+                        hdmi_con_in: endpoint {
+                                remote-endpoint = <&hdmi_out_con>;
+                        };
+                };
+        };
+
         reg_vcc3v3: vcc3v3 {
                 compatible = "regulator-fixed";
                 regulator-name = "vcc3v3";
@@ -73,9 +84,21 @@
         };
 };
 
+&de {
+        status = "okay";
+};
+
+&hdmi {
+        status = "okay";
+};
+
+&hdmi_out {
+        hdmi_out_con: endpoint {
+                remote-endpoint = <&hdmi_con_in>;
+        };
+};
+
 &mmc0 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mmc0_pins_a>;
         vmmc-supply = <&reg_vcc3v3>;
         bus-width = <4>;
         cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
@@ -83,8 +106,6 @@
 };
 
 &mmc1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mmc1_pins_a>;
         vmmc-supply = <&reg_vcc3v3>;
         vqmmc-supply = <&reg_vcc3v3>;
         mmc-pwrseq = <&wifi_pwrseq>;
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
new file mode 100644
index 000000000000..d36de5eb81f3
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.io>
+ */
+
+/dts-v1/;
+
+#include "sun50i-h6.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+        model = "Pine H64";
+        compatible = "pine64,pine-h64", "allwinner,sun50i-h6";
+
+        aliases {
+                serial0 = &uart0;
+        };
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+};
+
+&uart0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart0_ph_pins>;
+        status = "okay";
+};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
new file mode 100644
index 000000000000..56563150d61a
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -0,0 +1,175 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+        interrupt-parent = <&gic>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu0: cpu@0 {
+                        compatible = "arm,cortex-a53", "arm,armv8";
+                        device_type = "cpu";
+                        reg = <0>;
+                        enable-method = "psci";
+                };
+
+                cpu1: cpu@1 {
+                        compatible = "arm,cortex-a53", "arm,armv8";
+                        device_type = "cpu";
+                        reg = <1>;
+                        enable-method = "psci";
+                };
+
+                cpu2: cpu@2 {
+                        compatible = "arm,cortex-a53", "arm,armv8";
+                        device_type = "cpu";
+                        reg = <2>;
+                        enable-method = "psci";
+                };
+
+                cpu3: cpu@3 {
+                        compatible = "arm,cortex-a53", "arm,armv8";
+                        device_type = "cpu";
+                        reg = <3>;
+                        enable-method = "psci";
+                };
+        };
+
+        iosc: internal-osc-clk {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <16000000>;
+                clock-accuracy = <300000000>;
+                clock-output-names = "iosc";
+        };
+
+        osc24M: osc24M_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <24000000>;
+                clock-output-names = "osc24M";
+        };
+
+        osc32k: osc32k_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+                clock-output-names = "osc32k";
+        };
+
+        psci {
+                compatible = "arm,psci-0.2";
+                method = "smc";
+        };
+
+        timer {
+                compatible = "arm,armv8-timer";
+                interrupts = <GIC_PPI 13
+                        (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+                             <GIC_PPI 14
+                        (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+                             <GIC_PPI 11
+                        (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+                             <GIC_PPI 10
+                        (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+        };
+
+        soc {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                ccu: clock@3001000 {
+                        compatible = "allwinner,sun50i-h6-ccu";
+                        reg = <0x03001000 0x1000>;
+                        clocks = <&osc24M>, <&osc32k>, <&iosc>;
+                        clock-names = "hosc", "losc", "iosc";
+                        #clock-cells = <1>;
+                        #reset-cells = <1>;
+                };
+
+                gic: interrupt-controller@3021000 {
+                        compatible = "arm,gic-400";
+                        reg = <0x03021000 0x1000>,
+                              <0x03022000 0x2000>,
+                              <0x03024000 0x2000>,
+                              <0x03026000 0x2000>;
+                        interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+                        interrupt-controller;
+                        #interrupt-cells = <3>;
+                };
+
+                pio: pinctrl@300b000 {
+                        compatible = "allwinner,sun50i-h6-pinctrl";
+                        reg = <0x0300b000 0x400>;
+                        interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&ccu 26>, <&osc24M>, <&osc32k>;
+                        clock-names = "apb", "hosc", "losc";
+                        gpio-controller;
+                        #gpio-cells = <3>;
+                        interrupt-controller;
+                        #interrupt-cells = <3>;
+
+                        uart0_ph_pins: uart0-ph {
+                                pins = "PH0", "PH1";
+                                function = "uart0";
+                        };
+                };
+
+                uart0: serial@5000000 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x05000000 0x400>;
+                        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&ccu 70>;
+                        resets = <&ccu 21>;
+                        status = "disabled";
+                };
+
+                uart1: serial@5000400 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x05000400 0x400>;
+                        interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&ccu 71>;
+                        resets = <&ccu 22>;
+                        status = "disabled";
+                };
+
+                uart2: serial@5000800 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x05000800 0x400>;
+                        interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&ccu 72>;
+                        resets = <&ccu 23>;
+                        status = "disabled";
+                };
+
+                uart3: serial@5000c00 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x05000c00 0x400>;
+                        interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&ccu 73>;
+                        resets = <&ccu 24>;
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
index 000756429b77..54bf6a6c6f7b 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
@@ -100,4 +100,9 @@
 
 &usb0 {
         status = "okay";
+        disable-over-current;
+};
+
+&watchdog0 {
+        status = "okay";
 };
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 447b98d30921..57eedced5a51 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
 /dts-v1/;
@@ -14,6 +13,7 @@
 
         aliases {
                 serial0 = &uart_AO;
+                serial1 = &uart_A;
         };
 };
 
@@ -24,8 +24,16 @@
         pinctrl-names = "default";
 };
 
+&uart_A {
+        status = "okay";
+        pinctrl-0 = <&uart_a_pins>;
+        pinctrl-names = "default";
+};
+
 &uart_AO {
         status = "okay";
+        pinctrl-0 = <&uart_ao_a_pins>;
+        pinctrl-names = "default";
 };
 
 &ir {
@@ -33,3 +41,9 @@
         pinctrl-0 = <&remote_input_ao_pins>;
         pinctrl-names = "default";
 };
+
+&i2c1 {
+        status = "okay";
+        pinctrl-0 = <&i2c1_z_pins>;
+        pinctrl-names = "default";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index a80632641b39..b58808eb3cc8 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
 #include <dt-bindings/gpio/gpio.h>
@@ -163,18 +162,70 @@
                                 status = "disabled";
                         };
 
+                        i2c0: i2c@1f000 {
+                                compatible = "amlogic,meson-axg-i2c";
+                                status = "disabled";
+                                reg = <0x0 0x1f000 0x0 0x20>;
+                                interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                clocks = <&clkc CLKID_I2C>;
+                                clock-names = "clk_i2c";
+                        };
+
+                        i2c1: i2c@1e000 {
+                                compatible = "amlogic,meson-axg-i2c";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                reg = <0x0 0x1e000 0x0 0x20>;
+                                status = "disabled";
+                                interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
+                                clocks = <&clkc CLKID_I2C>;
+                                clock-names = "clk_i2c";
+                        };
+
+                        i2c2: i2c@1d000 {
+                                compatible = "amlogic,meson-axg-i2c";
+                                status = "disabled";
+                                reg = <0x0 0x1d000 0x0 0x20>;
+                                interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                clocks = <&clkc CLKID_I2C>;
+                                clock-names = "clk_i2c";
+                        };
+
+                        i2c3: i2c@1c000 {
+                                compatible = "amlogic,meson-axg-i2c";
+                                status = "disabled";
+                                reg = <0x0 0x1c000 0x0 0x20>;
+                                interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                clocks = <&clkc CLKID_I2C>;
+                                clock-names = "clk_i2c";
+                        };
+
                         uart_A: serial@24000 {
-                                compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
-                                reg = <0x0 0x24000 0x0 0x14>;
+                                compatible = "amlogic,meson-gx-uart";
+                                reg = <0x0 0x24000 0x0 0x18>;
                                 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
                                 status = "disabled";
+                                clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
+                                clock-names = "xtal", "pclk", "baud";
                         };
 
                         uart_B: serial@23000 {
-                                compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
-                                reg = <0x0 0x23000 0x0 0x14>;
+                                compatible = "amlogic,meson-gx-uart";
+                                reg = <0x0 0x23000 0x0 0x18>;
                                 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
                                 status = "disabled";
+                                clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
+                                clock-names = "xtal", "pclk", "baud";
                         };
                 };
 
@@ -234,6 +285,13 @@
                         #size-cells = <2>;
                         ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
 
+                        hwrng: rng {
+                                compatible = "amlogic,meson-rng";
+                                reg = <0x0 0x18 0x0 0x4>;
+                                clocks = <&clkc CLKID_RNG0>;
+                                clock-names = "core";
+                        };
+
                         pinctrl_periphs: pinctrl@480 {
                                 compatible = "amlogic,meson-axg-periphs-pinctrl";
                                 #address-cells = <2>;
@@ -251,6 +309,36 @@
                                         gpio-ranges = <&pinctrl_periphs 0 0 86>;
                                 };
 
+                                eth_rmii_x_pins: eth-x-rmii {
+                                        mux {
+                                                groups = "eth_mdio_x",
+                                                       "eth_mdc_x",
+                                                       "eth_rgmii_rx_clk_x",
+                                                       "eth_rx_dv_x",
+                                                       "eth_rxd0_x",
+                                                       "eth_rxd1_x",
+                                                       "eth_txen_x",
+                                                       "eth_txd0_x",
+                                                       "eth_txd1_x";
+                                                function = "eth";
+                                        };
+                                };
+
+                                eth_rmii_y_pins: eth-y-rmii {
+                                        mux {
+                                                groups = "eth_mdio_y",
+                                                       "eth_mdc_y",
+                                                       "eth_rgmii_rx_clk_y",
+                                                       "eth_rx_dv_y",
+                                                       "eth_rxd0_y",
+                                                       "eth_rxd1_y",
+                                                       "eth_txen_y",
+                                                       "eth_txd0_y",
+                                                       "eth_txd1_y";
+                                                function = "eth";
+                                        };
+                                };
+
                                 eth_rgmii_x_pins: eth-x-rgmii {
                                         mux {
                                                 groups = "eth_mdio_x",
@@ -444,6 +532,134 @@
                                                 function = "spi1";
                                         };
                                 };
+
+                                i2c0_pins: i2c0 {
+                                        mux {
+                                                groups = "i2c0_sck",
+                                                        "i2c0_sda";
+                                                function = "i2c0";
+                                        };
+                                };
+
+                                i2c1_z_pins: i2c1_z {
+                                        mux {
+                                                groups = "i2c1_sck_z",
+                                                        "i2c1_sda_z";
+                                                function = "i2c1";
+                                        };
+                                };
+
+                                i2c1_x_pins: i2c1_x {
+                                        mux {
+                                                groups = "i2c1_sck_x",
+                                                        "i2c1_sda_x";
+                                                function = "i2c1";
+                                        };
+                                };
+
+                                i2c2_x_pins: i2c2_x {
+                                        mux {
+                                                groups = "i2c2_sck_x",
+                                                        "i2c2_sda_x";
+                                                function = "i2c2";
+                                        };
+                                };
+
+                                i2c2_a_pins: i2c2_a {
+                                        mux {
+                                                groups = "i2c2_sck_a",
+                                                        "i2c2_sda_a";
+                                                function = "i2c2";
+                                        };
+                                };
+
+                                i2c3_a6_pins: i2c3_a6 {
+                                        mux {
+                                                groups = "i2c3_sda_a6",
+                                                        "i2c3_sck_a7";
+                                                function = "i2c3";
+                                        };
+                                };
+
+                                i2c3_a12_pins: i2c3_a12 {
+                                        mux {
+                                                groups = "i2c3_sda_a12",
+                                                        "i2c3_sck_a13";
+                                                function = "i2c3";
+                                        };
+                                };
+
+                                i2c3_a19_pins: i2c3_a19 {
+                                        mux {
+                                                groups = "i2c3_sda_a19",
+                                                        "i2c3_sck_a20";
+                                                function = "i2c3";
+                                        };
+                                };
+
+                                uart_a_pins: uart_a {
+                                        mux {
+                                                groups = "uart_tx_a",
+                                                        "uart_rx_a";
+                                                function = "uart_a";
+                                        };
+                                };
+
+                                uart_a_cts_rts_pins: uart_a_cts_rts {
+                                        mux {
+                                                groups = "uart_cts_a",
+                                                        "uart_rts_a";
+                                                function = "uart_a";
+                                        };
+                                };
+
+                                uart_b_x_pins: uart_b_x {
+                                        mux {
+                                                groups = "uart_tx_b_x",
+                                                        "uart_rx_b_x";
+                                                function = "uart_b";
+                                        };
+                                };
+
+                                uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
+                                        mux {
+                                                groups = "uart_cts_b_x",
+                                                        "uart_rts_b_x";
+                                                function = "uart_b";
+                                        };
+                                };
+
+                                uart_b_z_pins: uart_b_z {
+                                        mux {
+                                                groups = "uart_tx_b_z",
+                                                        "uart_rx_b_z";
+                                                function = "uart_b";
+                                        };
+                                };
+
+                                uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
+                                        mux {
+                                                groups = "uart_cts_b_z",
+                                                        "uart_rts_b_z";
+                                                function = "uart_b";
+                                        };
+                                };
+
+                                uart_ao_b_z_pins: uart_ao_b_z {
+                                        mux {
+                                                groups = "uart_ao_tx_b_z",
+                                                        "uart_ao_rx_b_z";
+                                                function = "uart_ao_b_z";
+                                        };
+                                };
+
+                                uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
+                                        mux {
+                                                groups = "uart_ao_cts_b_z",
+                                                        "uart_ao_rts_b_z";
+                                                function = "uart_ao_b_z";
+                                        };
+                                };
                         };
                 };
 
@@ -494,6 +710,44 @@
                                                 function = "remote_input_ao";
                                         };
                                 };
+
+                                uart_ao_a_pins: uart_ao_a {
+                                        mux {
+                                                groups = "uart_ao_tx_a",
+                                                        "uart_ao_rx_a";
+                                                function = "uart_ao_a";
+                                        };
+                                };
+
+                                uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
+                                        mux {
+                                                groups = "uart_ao_cts_a",
+                                                        "uart_ao_rts_a";
+                                                function = "uart_ao_a";
+                                        };
+                                };
+
+                                uart_ao_b_pins: uart_ao_b {
+                                        mux {
+                                                groups = "uart_ao_tx_b",
+                                                        "uart_ao_rx_b";
+                                                function = "uart_ao_b";
+                                        };
+                                };
+
+                                uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
+                                        mux {
+                                                groups = "uart_ao_cts_b",
+                                                        "uart_ao_rts_b";
+                                                function = "uart_ao_b";
+                                        };
+                                };
+                        };
+
+                        sec_AO: ao-secure@140 {
+                                compatible = "amlogic,meson-gx-ao-secure", "syscon";
+                                reg = <0x0 0x140 0x0 0x140>;
+                                amlogic,has-chip-id;
                         };
 
                         pwm_AO_ab: pwm@7000 {
@@ -504,12 +758,23 @@
                         };
 
                         pwm_AO_cd: pwm@2000 {
-                                compatible = "amlogic,axg-ao-pwm";
+                                compatible = "amlogic,meson-axg-ao-pwm";
                                 reg = <0x0 0x02000  0x0 0x20>;
                                 #pwm-cells = <3>;
                                 status = "disabled";
                         };
 
+                        i2c_AO: i2c@5000 {
+                                compatible = "amlogic,meson-axg-i2c";
+                                status = "disabled";
+                                reg = <0x0 0x05000 0x0 0x20>;
+                                interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                clocks = <&clkc CLKID_I2C>;
+                                clock-names = "clk_i2c";
+                        };
+
                         uart_AO: serial@3000 {
                                 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
                                 reg = <0x0 0x3000 0x0 0x18>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
index aeb6d21a3bec..4eef36b22538 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
@@ -1,44 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2016 Endless Computers, Inc.
  * Author: Carlo Caione <carlo@endlessm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /* Common DTSI for same Amlogic Q200/Q201 and P230/P231 boards using either
@@ -48,6 +11,7 @@
 / {
         aliases {
                 serial0 = &uart_AO;
+                ethernet0 = &ethmac;
         };
 
         chosen {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index 6cb3c2a52baf..3c31e21cbed7 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2016 Andreas Färber
  *
@@ -6,44 +7,6 @@
  *
  * Copyright (c) 2016 Endless Computers, Inc.
  * Author: Carlo Caione <carlo@endlessm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 #include <dt-bindings/gpio/gpio.h>
@@ -169,6 +132,7 @@
                 compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse";
                 #address-cells = <1>;
                 #size-cells = <1>;
+                read-only;
 
                 sn: sn@14 {
                         reg = <0x14 0x10>;
@@ -235,14 +199,14 @@
 
                         uart_A: serial@84c0 {
                                 compatible = "amlogic,meson-gx-uart";
-                                reg = <0x0 0x84c0 0x0 0x14>;
+                                reg = <0x0 0x84c0 0x0 0x18>;
                                 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
                                 status = "disabled";
                         };
 
                         uart_B: serial@84dc {
                                 compatible = "amlogic,meson-gx-uart";
-                                reg = <0x0 0x84dc 0x0 0x14>;
+                                reg = <0x0 0x84dc 0x0 0x18>;
                                 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
                                 status = "disabled";
                         };
@@ -287,7 +251,7 @@
 
                         uart_C: serial@8700 {
                                 compatible = "amlogic,meson-gx-uart";
-                                reg = <0x0 0x8700 0x0 0x14>;
+                                reg = <0x0 0x8700 0x0 0x18>;
                                 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
                                 status = "disabled";
                         };
@@ -404,14 +368,14 @@
 
                         uart_AO: serial@4c0 {
                                 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
-                                reg = <0x0 0x004c0 0x0 0x14>;
+                                reg = <0x0 0x004c0 0x0 0x18>;
                                 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
                                 status = "disabled";
                         };
 
                         uart_AO_B: serial@4e0 {
                                 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
-                                reg = <0x0 0x004e0 0x0 0x14>;
+                                reg = <0x0 0x004e0 0x0 0x18>;
                                 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
                                 status = "disabled";
                         };
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
index 011e8e08e429..7d5709c37e95 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
@@ -1,45 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2017 Andreas Färber
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
 /dts-v1/;
@@ -52,6 +13,7 @@
 
         aliases {
                 serial0 = &uart_AO;
+                ethernet0 = &ethmac;
         };
 
         chosen {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts
index 818954b1d57f..4cf7f6e80c6a 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts
@@ -1,45 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2016 Andreas Färber
  * Copyright (c) 2016 BayLibre, Inc.
  * Author: Neil Armstrong <narmstrong@kernel.org>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
@@ -54,6 +17,7 @@
 
         aliases {
                 serial0 = &uart_AO;
+                ethernet0 = &ethmac;
         };
 
         chosen {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
index ee4ada61c59c..54954b314a45 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
@@ -1,45 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2016 Andreas Färber
  * Copyright (c) 2016 BayLibre, Inc.
  * Author: Kevin Hilman <khilman@kernel.org>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
@@ -53,6 +16,7 @@
 
         aliases {
                 serial0 = &uart_AO;
+                ethernet0 = &ethmac;
         };
 
         chosen {
@@ -310,7 +274,7 @@
         pinctrl-names = "default", "clk-gate";
 
         bus-width = <8>;
-        max-frequency = <200000000>;
+        max-frequency = <100000000>;
         non-removable;
         disable-wp;
         cap-mmc-highspeed;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts
index 09f34f7ef084..9d2406a7c4fa 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts
@@ -1,45 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2016 Andreas Färber
  * Copyright (c) 2016 BayLibre, Inc.
  * Author: Kevin Hilman <khilman@kernel.org>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts
index ae3194663d64..56e0dd1ff55c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts
@@ -1,45 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2016 Andreas Färber
  * Copyright (c) 2016 BayLibre, Inc.
  * Author: Kevin Hilman <khilman@kernel.org>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
index 932158a778ef..ce862266b9aa 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
@@ -1,45 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2016 Andreas Färber
  * Copyright (c) 2016 BayLibre, Inc.
  * Author: Kevin Hilman <khilman@kernel.org>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 #include "meson-gxbb.dtsi"
@@ -47,6 +10,7 @@
 / {
         aliases {
                 serial0 = &uart_AO;
+                ethernet0 = &ethmac;
         };
 
         chosen {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-meta.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-meta.dts
index 62fb4968d680..c928adf85388 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-meta.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-meta.dts
@@ -1,43 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2016 Andreas Färber
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-pro.dts
index 9a9663abdf5c..e81e1d68b5fa 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-pro.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-pro.dts
@@ -1,43 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2016 Andreas Färber
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-telos.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-telos.dts
index 2fe167b2609d..a8fca0c6903f 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-telos.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-telos.dts
@@ -1,43 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2016 Andreas Färber
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
index 1fe8e24cf675..93a4acf2c46c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
@@ -1,43 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2016 Andreas Färber
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 #include "meson-gxbb.dtsi"
@@ -47,6 +10,7 @@
 
         aliases {
                 serial0 = &uart_AO;
+                ethernet0 = &ethmac;
         };
 
         chosen {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts
index 1878ac2b2b83..2bfe69902552 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts
@@ -1,92 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2016 BayLibre, Inc.
  * Author: Neil Armstrong <narmstrong@baylibre.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
 
-#include "meson-gxbb-p20x.dtsi"
+#include "meson-gxbb-wetek.dtsi"
 
 / {
         compatible = "wetek,hub", "amlogic,meson-gxbb";
         model = "WeTek Hub";
-
-        leds {
-                compatible = "gpio-leds";
-
-                system {
-                        label = "wetek-play:system-status";
-                        gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>;
-                        default-state = "on";
-                        panic-indicator;
-                };
-        };
-};
-
-&cvbs_connector {
-        status = "disabled";
-};
-
-&ethmac {
-        status = "okay";
-        pinctrl-0 = <&eth_rgmii_pins>;
-        pinctrl-names = "default";
-
-        phy-handle = <&eth_phy0>;
-        phy-mode = "rgmii";
-
-        amlogic,tx-delay-ns = <2>;
-
-        snps,reset-gpio = <&gpio GPIOZ_14 0>;
-        snps,reset-delays-us = <0 10000 1000000>;
-        snps,reset-active-low;
-
-        mdio {
-                compatible = "snps,dwmac-mdio";
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                eth_phy0: ethernet-phy@0 {
-                        /* Realtek RTL8211F (0x001cc916) */
-                        reg = <0>;
-                };
-        };
 };
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts
index f7144fd5e03f..0038522315de 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts
@@ -1,49 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2016 BayLibre, Inc.
  * Author: Neil Armstrong <narmstrong@baylibre.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
 
-#include "meson-gxbb-p20x.dtsi"
+#include "meson-gxbb-wetek.dtsi"
 #include <dt-bindings/input/input.h>
 
 / {
@@ -51,15 +14,6 @@
         model = "WeTek Play 2";
 
         leds {
-                compatible = "gpio-leds";
-
-                system {
-                        label = "wetek-play:system-status";
-                        gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>;
-                        default-state = "on";
-                        panic-indicator;
-                };
-
                 wifi {
                         label = "wetek-play:wifi-status";
                         gpios = <&gpio GPIODV_26 GPIO_ACTIVE_HIGH>;
@@ -85,82 +39,18 @@
                         gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>;
                 };
         };
-
-        cvbs-connector {
-                compatible = "composite-video-connector";
-
-                port {
-                        cvbs_connector_in: endpoint {
-                                remote-endpoint = <&cvbs_vdac_out>;
-                        };
-                };
-        };
-
-        hdmi-connector {
-                compatible = "hdmi-connector";
-                type = "a";
-
-                port {
-                        hdmi_connector_in: endpoint {
-                                remote-endpoint = <&hdmi_tx_tmds_out>;
-                        };
-                };
-        };
-};
-
-&cec_AO {
-        status = "okay";
-        pinctrl-0 = <&ao_cec_pins>;
-        pinctrl-names = "default";
-        hdmi-phandle = <&hdmi_tx>;
-};
-
-&cvbs_vdac_port {
-        cvbs_vdac_out: endpoint {
-                remote-endpoint = <&cvbs_connector_in>;
-        };
 };
 
-&ethmac {
+&i2c_A {
         status = "okay";
-        pinctrl-0 = <&eth_rgmii_pins>;
+        pinctrl-0 = <&i2c_a_pins>;
         pinctrl-names = "default";
-
-        phy-handle = <&eth_phy0>;
-        phy-mode = "rgmii";
-
-        amlogic,tx-delay-ns = <2>;
-
-        snps,reset-gpio = <&gpio GPIOZ_14 0>;
-        snps,reset-delays-us = <0 10000 1000000>;
-        snps,reset-active-low;
-
-        mdio {
-                compatible = "snps,dwmac-mdio";
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                eth_phy0: ethernet-phy@0 {
-                        /* Realtek RTL8211F (0x001cc916) */
-                        reg = <0>;
-                };
-        };
 };
 
-&hdmi_tx {
+&usb1_phy {
         status = "okay";
-        pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
-        pinctrl-names = "default";
 };
 
-&hdmi_tx_tmds_port {
-        hdmi_tx_tmds_out: endpoint {
-                remote-endpoint = <&hdmi_connector_in>;
-        };
-};
-
-&i2c_A {
+&usb1 {
         status = "okay";
-        pinctrl-0 = <&i2c_a_pins>;
-        pinctrl-names = "default";
 };
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi
new file mode 100644
index 000000000000..70325b273bd2
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi
@@ -0,0 +1,256 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2016 Andreas Färber
+ * Copyright (c) 2016 BayLibre, Inc.
+ * Author: Kevin Hilman <khilman@kernel.org>
+ */
+
+#include "meson-gxbb.dtsi"
+
+/ {
+        aliases {
+                serial0 = &uart_AO;
+                ethernet0 = &ethmac;
+        };
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x0 0x0 0x40000000>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                system {
+                        label = "wetek-play:system-status";
+                        gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>;
+                        default-state = "on";
+                        panic-indicator;
+                };
+        };
+
+        usb_pwr: regulator-usb-pwrs {
+                compatible = "regulator-fixed";
+
+                regulator-name = "USB_PWR";
+
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+
+                gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+        };
+
+        vddio_boot: regulator-vddio_boot {
+                compatible = "regulator-fixed";
+                regulator-name = "VDDIO_BOOT";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+        };
+
+        vddao_3v3: regulator-vddao_3v3 {
+                compatible = "regulator-fixed";
+                regulator-name = "VDDAO_3V3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
+
+        vcc_3v3: regulator-vcc_3v3 {
+                compatible = "regulator-fixed";
+                regulator-name = "VCC_3V3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
+
+        emmc_pwrseq: emmc-pwrseq {
+                compatible = "mmc-pwrseq-emmc";
+                reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+        };
+
+        wifi32k: wifi32k {
+                compatible = "pwm-clock";
+                #clock-cells = <0>;
+                clock-frequency = <32768>;
+                pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+        };
+
+        sdio_pwrseq: sdio-pwrseq {
+                compatible = "mmc-pwrseq-simple";
+                reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+                clocks = <&wifi32k>;
+                clock-names = "ext_clock";
+        };
+
+        cvbs-connector {
+                compatible = "composite-video-connector";
+
+                port {
+                        cvbs_connector_in: endpoint {
+                                remote-endpoint = <&cvbs_vdac_out>;
+                        };
+                };
+        };
+
+        hdmi-connector {
+                compatible = "hdmi-connector";
+                type = "a";
+
+                port {
+                        hdmi_connector_in: endpoint {
+                                remote-endpoint = <&hdmi_tx_tmds_out>;
+                        };
+                };
+        };
+};
+
+&cec_AO {
+        status = "okay";
+        pinctrl-0 = <&ao_cec_pins>;
+        pinctrl-names = "default";
+        hdmi-phandle = <&hdmi_tx>;
+};
+
+&cvbs_vdac_port {
+        cvbs_vdac_out: endpoint {
+                remote-endpoint = <&cvbs_connector_in>;
+        };
+};
+
+&ethmac {
+        status = "okay";
+        pinctrl-0 = <&eth_rgmii_pins>;
+        pinctrl-names = "default";
+
+        phy-handle = <&eth_phy0>;
+        phy-mode = "rgmii";
+
+        amlogic,tx-delay-ns = <2>;
+
+        snps,reset-gpio = <&gpio GPIOZ_14 0>;
+        snps,reset-delays-us = <0 10000 1000000>;
+        snps,reset-active-low;
+
+        mdio {
+                compatible = "snps,dwmac-mdio";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                eth_phy0: ethernet-phy@0 {
+                        /* Realtek RTL8211F (0x001cc916) */
+                        reg = <0>;
+                        eee-broken-1000t;
+                };
+        };
+};
+
+&hdmi_tx {
+        status = "okay";
+        pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
+        pinctrl-names = "default";
+};
+
+&hdmi_tx_tmds_port {
+        hdmi_tx_tmds_out: endpoint {
+                remote-endpoint = <&hdmi_connector_in>;
+        };
+};
+
+&ir {
+        status = "okay";
+        pinctrl-0 = <&remote_input_ao_pins>;
+        pinctrl-names = "default";
+};
+
+&pwm_ef {
+        status = "okay";
+        pinctrl-0 = <&pwm_e_pins>;
+        pinctrl-names = "default";
+        clocks = <&clkc CLKID_FCLK_DIV4>;
+        clock-names = "clkin0";
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+        status = "okay";
+        pinctrl-0 = <&sdio_pins>;
+        pinctrl-1 = <&sdio_clk_gate_pins>;
+        pinctrl-names = "default", "clk-gate";
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        bus-width = <4>;
+        cap-sd-highspeed;
+        max-frequency = <100000000>;
+
+        non-removable;
+        disable-wp;
+
+        mmc-pwrseq = <&sdio_pwrseq>;
+
+        vmmc-supply = <&vddao_3v3>;
+        vqmmc-supply = <&vddio_boot>;
+
+        brcmf: wifi@1 {
+                reg = <1>;
+                compatible = "brcm,bcm4329-fmac";
+        };
+};
+
+/* SD card */
+&sd_emmc_b {
+        status = "okay";
+        pinctrl-0 = <&sdcard_pins>;
+        pinctrl-1 = <&sdcard_clk_gate_pins>;
+        pinctrl-names = "default", "clk-gate";
+
+        bus-width = <4>;
+        cap-sd-highspeed;
+        max-frequency = <100000000>;
+        disable-wp;
+
+        cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
+        cd-inverted;
+
+        vmmc-supply = <&vddao_3v3>;
+        vqmmc-supply = <&vcc_3v3>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+        status = "okay";
+        pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
+        pinctrl-1 = <&emmc_clk_gate_pins>;
+        pinctrl-names = "default", "clk-gate";
+
+        bus-width = <8>;
+        cap-mmc-highspeed;
+        max-frequency = <200000000>;
+        non-removable;
+        disable-wp;
+        mmc-ddr-1_8v;
+        mmc-hs200-1_8v;
+
+        mmc-pwrseq = <&emmc_pwrseq>;
+        vmmc-supply = <&vcc_3v3>;
+        vqmmc-supply = <&vddio_boot>;
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_AO {
+        status = "okay";
+        pinctrl-0 = <&uart_ao_a_pins>;
+        pinctrl-names = "default";
+};
+
+&usb0_phy {
+        status = "okay";
+        phy-supply = <&usb_pwr>;
+};
+
+&usb0 {
+        status = "okay";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 3290a4dc3522..562c26a0ba33 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -1,43 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2016 Andreas Färber
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 #include "meson-gx.dtsi"
@@ -284,14 +247,17 @@
                  * MALI_0 and MALI_1 muxed to a single clock by a glitch
                  * free mux to safely change frequency while running.
                  */
-                assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
+                assigned-clocks = <&clkc CLKID_GP0_PLL>,
+                                  <&clkc CLKID_MALI_0_SEL>,
                                   <&clkc CLKID_MALI_0>,
                                   <&clkc CLKID_MALI>; /* Glitch free mux */
-                assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
+                assigned-clock-parents = <0>, /* Do Nothing */
+                                         <&clkc CLKID_GP0_PLL>,
                                          <0>, /* Do Nothing */
                                          <&clkc CLKID_MALI_0>;
-                assigned-clock-rates = <0>, /* Do Nothing */
-                                       <666666666>,
+                assigned-clock-rates = <744000000>,
+                                       <0>, /* Do Nothing */
+                                       <744000000>,
                                        <0>; /* Do Nothing */
         };
 };
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi
index f06cc234693b..eb327664a4d8 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi
@@ -1,8 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2017 BayLibre SAS
  * Author: Neil Armstrong <narmstrong@baylibre.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
 &apb {
@@ -30,14 +29,17 @@
                  * MALI_0 and MALI_1 muxed to a single clock by a glitch
                  * free mux to safely change frequency while running.
                  */
-                assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
+                assigned-clocks = <&clkc CLKID_GP0_PLL>,
+                                  <&clkc CLKID_MALI_0_SEL>,
                                   <&clkc CLKID_MALI_0>,
                                   <&clkc CLKID_MALI>; /* Glitch free mux */
-                assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
+                assigned-clock-parents = <0>, /* Do Nothing */
+                                         <&clkc CLKID_GP0_PLL>,
                                          <0>, /* Do Nothing */
                                          <&clkc CLKID_MALI_0>;
-                assigned-clock-rates = <0>, /* Do Nothing */
-                                       <666666666>,
+                assigned-clock-rates = <744000000>,
+                                       <0>, /* Do Nothing */
+                                       <744000000>,
                                        <0>; /* Do Nothing */
         };
 };
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
index 4f3f03fc31b0..a9f9bb90a877 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
@@ -1,44 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2016 Endless Computers, Inc.
  * Author: Carlo Caione <carlo@endlessm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts
index 95992cf1fe61..80a231476b80 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts
@@ -1,44 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2016 Endless Computers, Inc.
  * Author: Carlo Caione <carlo@endlessm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi
index 5a90e30c1006..43321919547a 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d.dtsi
@@ -1,44 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2016 Endless Computers, Inc.
  * Author: Carlo Caione <carlo@endlessm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 #include "meson-gxl.dtsi"
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts
index e82582574160..f1c410e2da2b 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2017 Carlo Caione
  * Copyright (c) 2016 BayLibre, Inc.
  * Author: Neil Armstrong <narmstrong@kernel.org>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
 /dts-v1/;
@@ -16,6 +15,7 @@
 
         aliases {
                 serial0 = &uart_AO;
+                ethernet0 = &ethmac;
         };
 
         chosen {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
index 71a6e1ce7ad5..d32cf3846370 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
 /dts-v1/;
@@ -29,6 +28,7 @@
 
         aliases {
                 serial2 = &uart_AO_B;
+                ethernet0 = &ethmac;
         };
 
         gpio-keys-polled {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
index 9671f1e3c74a..22bf37404ff1 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2017 BayLibre, SAS.
  * Author: Neil Armstrong <narmstrong@baylibre.com>
  * Author: Jerome Brunet <jbrunet@baylibre.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
 /dts-v1/;
@@ -18,6 +17,7 @@
 
         aliases {
                 serial0 = &uart_AO;
+                ethernet0 = &ethmac;
         };
 
         chosen {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
index 271f14279180..69c721a70e44 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
@@ -1,45 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2016 Andreas Färber
  * Copyright (c) 2016 BayLibre, Inc.
  * Author: Neil Armstrong <narmstrong@kernel.org>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
@@ -52,6 +15,7 @@
 
         aliases {
                 serial0 = &uart_AO;
+                ethernet0 = &ethmac;
         };
 
         chosen {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts
index 6e2bf858291c..5896e8a5d86b 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts
@@ -1,44 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2016 Endless Computers, Inc.
  * Author: Carlo Caione <carlo@endlessm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
index 7005068346a0..0a0953fbc7d4 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
  * Based on meson-gx-p23x-q20x.dtsi:
@@ -5,8 +6,6 @@
  *   Author: Carlo Caione <carlo@endlessm.com>
  * - Copyright (c) 2016 BayLibre, SAS.
  *   Author: Neil Armstrong <narmstrong@baylibre.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
 /* Common DTSI for devices which are based on the P212 reference board. */
@@ -17,6 +16,7 @@
         aliases {
                 serial0 = &uart_AO;
                 serial1 = &uart_A;
+                ethernet0 = &ethmac;
         };
 
         chosen {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi
index 3314a0b3dad9..40c19f69e9dc 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x.dtsi
@@ -1,44 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2016 Endless Computers, Inc.
  * Author: Carlo Caione <carlo@endlessm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 #include "meson-gxl.dtsi"
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
index 4f355f17eed6..e1a39cbed8c9 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
@@ -1,44 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2016 Endless Computers, Inc.
  * Author: Carlo Caione <carlo@endlessm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 #include "meson-gx.dtsi"
@@ -631,6 +594,7 @@
 
                         internal_phy: ethernet-phy@8 {
                                 compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
+                                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
                                 reg = <8>;
                                 max-speed = <100>;
                         };
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
index 1448c3dba08e..4fd46c1546a7 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
  * Copyright (c) 2017 BayLibre, SAS
  * Author: Neil Armstrong <narmstrong@baylibre.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
 /dts-v1/;
@@ -59,8 +58,6 @@
                                       1 1
                                       2 2
                                       3 3>;
-                cooling-min-level = <0>;
-                cooling-max-level = <3>;
                 #cooling-cells = <2>;
         };
 
@@ -209,14 +206,10 @@
 };
 
 &cpu0 {
-        cooling-min-level = <0>;
-        cooling-max-level = <6>;
         #cooling-cells = <2>;
 };
 
 &cpu4 {
-        cooling-min-level = <0>;
-        cooling-max-level = <4>;
         #cooling-cells = <2>;
 };
 
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
index e7a228f6cc7e..f7a1cffab4a8 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
@@ -1,47 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2016 BayLibre, SAS.
  * Author: Neil Armstrong <narmstrong@baylibre.com>
  *
  * Copyright (c) 2016 Endless Computers, Inc.
  * Author: Carlo Caione <carlo@endlessm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
@@ -54,6 +17,7 @@
 
         aliases {
                 serial0 = &uart_AO;
+                ethernet0 = &ethmac;
         };
 
         chosen {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts
index 388fac4f2d97..101417298a1d 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts
@@ -1,44 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2016 Endless Computers, Inc.
  * Author: Carlo Caione <carlo@endlessm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-q201.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-q201.dts
index 95e11d7faab8..8d132b17514a 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-q201.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-q201.dts
@@ -1,44 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2016 Endless Computers, Inc.
  * Author: Carlo Caione <carlo@endlessm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts
index a5e9b955d5ed..7212dc4531e4 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2016-2017 Andreas Färber
  *
@@ -8,44 +9,6 @@
  *
  * Copyright (c) 2016 Endless Computers, Inc.
  * Author: Carlo Caione <carlo@endlessm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
@@ -58,6 +21,7 @@
 
         aliases {
                 serial0 = &uart_AO;
+                ethernet0 = &ethmac;
         };
 
         chosen {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-vega-s96.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-vega-s96.dts
index dc37eecb9514..e2ea6753263b 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-vega-s96.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-vega-s96.dts
@@ -1,9 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2017 BayLibre, SAS.
  * Author: Neil Armstrong <narmstrong@baylibre.com>
  * Copyright (c) 2017 Oleg <balbes-150@yandex.ru>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
 /dts-v1/;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
index 19a798d2ae2f..d076a7c425dd 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
@@ -1,44 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (c) 2016 Endless Computers, Inc.
  * Author: Carlo Caione <carlo@endlessm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 #include "meson-gxl.dtsi"
diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
index f165f04db0c9..eb749c50a736 100644
--- a/arch/arm64/boot/dts/arm/juno-base.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
@@ -68,10 +68,29 @@
                 interrupt-controller;
                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
                 ranges = <0 0 0 0x2c1c0000 0 0x40000>;
+
                 v2m_0: v2m@0 {
                         compatible = "arm,gic-v2m-frame";
                         msi-controller;
-                        reg = <0 0 0 0x1000>;
+                        reg = <0 0 0 0x10000>;
+                };
+
+                v2m@10000 {
+                        compatible = "arm,gic-v2m-frame";
+                        msi-controller;
+                        reg = <0 0x10000 0 0x10000>;
+                };
+
+                v2m@20000 {
+                        compatible = "arm,gic-v2m-frame";
+                        msi-controller;
+                        reg = <0 0x20000 0 0x10000>;
+                };
+
+                v2m@30000 {
+                        compatible = "arm,gic-v2m-frame";
+                        msi-controller;
+                        reg = <0 0x30000 0 0x10000>;
                 };
         };
 
diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi
index 4220fbdcb24a..ff5c4c47b22b 100644
--- a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi
+++ b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi
@@ -98,7 +98,7 @@
                 clock-output-names = "clk125mhz";
         };
 
-        pci {
+        pcie@30000000 {
                 compatible = "pci-host-ecam-generic";
                 device_type = "pci";
                 #interrupt-cells = <1>;
@@ -118,6 +118,7 @@
                 ranges =
                   <0x02000000    0 0x40000000    0 0x40000000    0 0x20000000
                    0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>;
+                bus-range = <0 0xff>;
                 interrupt-map-mask = <0 0 0 7>;
                 interrupt-map =
                       /* addr  pin  ic   icaddr  icintr */
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
index a77462da4a36..a1e3194b7483 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
@@ -14,6 +14,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/sound/samsung-i2s.h>
 
 / {
         aliases {
@@ -112,8 +113,8 @@
 
         sound {
                 compatible = "samsung,tm2-audio";
-                audio-codec = <&wm5110>;
-                i2s-controller = <&i2s0>;
+                audio-codec = <&wm5110>, <&hdmi>;
+                i2s-controller = <&i2s0 0>, <&i2s1 0>;
                 audio-amplifier = <&max98504>;
                 mic-bias-gpios = <&gpr3 2 GPIO_ACTIVE_HIGH>;
                 model = "wm5110";
@@ -217,8 +218,40 @@
 };
 
 &cmu_aud {
-        assigned-clocks = <&cmu_aud CLK_MOUT_AUD_PLL_USER>;
-        assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>;
+        assigned-clocks = <&cmu_aud CLK_MOUT_AUD_PLL_USER>,
+                <&cmu_aud CLK_MOUT_SCLK_AUD_I2S>,
+                <&cmu_aud CLK_MOUT_SCLK_AUD_PCM>,
+                <&cmu_top CLK_MOUT_AUD_PLL>,
+                <&cmu_top CLK_MOUT_AUD_PLL_USER_T>,
+                <&cmu_top CLK_MOUT_SCLK_AUDIO0>,
+                <&cmu_top CLK_MOUT_SCLK_AUDIO1>,
+                <&cmu_top CLK_MOUT_SCLK_SPDIF>,
+
+                <&cmu_aud CLK_DIV_AUD_CA5>,
+                <&cmu_aud CLK_DIV_ACLK_AUD>,
+                <&cmu_aud CLK_DIV_PCLK_DBG_AUD>,
+                <&cmu_aud CLK_DIV_SCLK_AUD_I2S>,
+                <&cmu_aud CLK_DIV_SCLK_AUD_PCM>,
+                <&cmu_aud CLK_DIV_SCLK_AUD_SLIMBUS>,
+                <&cmu_aud CLK_DIV_SCLK_AUD_UART>,
+                <&cmu_top CLK_DIV_SCLK_AUDIO0>,
+                <&cmu_top CLK_DIV_SCLK_AUDIO1>,
+                <&cmu_top CLK_DIV_SCLK_PCM1>,
+                <&cmu_top CLK_DIV_SCLK_I2S1>;
+
+        assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>,
+                <&cmu_aud CLK_MOUT_AUD_PLL_USER>,
+                <&cmu_aud CLK_MOUT_AUD_PLL_USER>,
+                <&cmu_top CLK_FOUT_AUD_PLL>,
+                <&cmu_top CLK_MOUT_AUD_PLL>,
+                <&cmu_top CLK_MOUT_AUD_PLL_USER_T>,
+                <&cmu_top CLK_MOUT_AUD_PLL_USER_T>,
+                <&cmu_top CLK_SCLK_AUDIO0>;
+
+        assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>,
+                <196608001>, <65536001>, <32768001>, <49152001>,
+                <2048001>, <24576001>, <196608001>,
+                <24576001>, <98304001>, <2048001>, <49152001>;
 };
 
 &cmu_fsys {
@@ -267,6 +300,11 @@
                                  <&cmu_top CLK_MOUT_BUS_PLL_USER>;
 };
 
+&cmu_top {
+        assigned-clocks = <&cmu_top CLK_FOUT_AUD_PLL>;
+        assigned-clock-rates = <196608001>;
+};
+
 &cpu0 {
         cpu-supply = <&buck3_reg>;
 };
@@ -779,9 +817,22 @@
                 clocks = <&pmu_system_controller 0>;
                 clock-names = "xtal";
 
-                port {
-                        mhl_to_hdmi: endpoint {
-                                remote-endpoint = <&hdmi_to_mhl>;
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@0 {
+                                reg = <0>;
+                                mhl_to_hdmi: endpoint {
+                                        remote-endpoint = <&hdmi_to_mhl>;
+                                };
+                        };
+
+                        port@1 {
+                                reg = <1>;
+                                mhl_to_musb_con: endpoint {
+                                        remote-endpoint = <&musb_con_to_mhl>;
+                                };
                         };
                 };
         };
@@ -798,6 +849,25 @@
 
                 muic: max77843-muic {
                         compatible = "maxim,max77843-muic";
+
+                        musb_con: musb_connector {
+                                compatible = "samsung,usb-connector-11pin",
+                                             "usb-b-connector";
+                                label = "micro-USB";
+                                type = "micro";
+
+                                ports {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+
+                                        port@3 {
+                                                reg = <3>;
+                                                musb_con_to_mhl: endpoint {
+                                                        remote-endpoint = <&mhl_to_musb_con>;
+                                                };
+                                        };
+                                };
+                        };
                 };
 
                 regulators {
@@ -838,6 +908,12 @@
         status = "okay";
 };
 
+&i2s1 {
+        assigned-clocks = <&i2s1 CLK_I2S_RCLK_SRC>;
+        assigned-clock-parents = <&cmu_peric CLK_SCLK_I2S1>;
+        status = "okay";
+};
+
 &mshc_0 {
         status = "okay";
         mmc-hs200-1_8v;
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 62f276970174..c0231d077fa6 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -969,6 +969,7 @@
                         ddc = <&hsi2c_11>;
                         samsung,syscon-phandle = <&pmu_system_controller>;
                         samsung,sysreg-phandle = <&syscon_disp>;
+                        #sound-dai-cells = <0>;
                         status = "disabled";
                 };
 
@@ -1311,6 +1312,25 @@
                         status = "disabled";
                 };
 
+                i2s1: i2s@14d60000 {
+                        compatible = "samsung,exynos7-i2s";
+                        reg = <0x14d60000 0x100>;
+                        dmas = <&pdma0 31 &pdma0 30>;
+                        dma-names = "tx", "rx";
+                        interrupts = <GIC_SPI 435 IRQ_TYPE_NONE>;
+                        clocks = <&cmu_peric CLK_PCLK_I2S1>,
+                                 <&cmu_peric CLK_PCLK_I2S1>,
+                                 <&cmu_peric CLK_SCLK_I2S1>;
+                        clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
+                        #clock-cells = <1>;
+                        samsung,supports-6ch;
+                        samsung,supports-rstclr;
+                        samsung,supports-tdm;
+                        samsung,supports-low-rfs;
+                        #sound-dai-cells = <1>;
+                        status = "disabled";
+                };
+
                 pwm: pwm@14dd0000 {
                         compatible = "samsung,exynos4210-pwm";
                         reg = <0x14dd0000 0x100>;
@@ -1639,7 +1659,7 @@
                                 power-domains = <&pd_aud>;
                         };
 
-                        i2s0: i2s0@11440000 {
+                        i2s0: i2s@11440000 {
                                 compatible = "samsung,exynos7-i2s";
                                 reg = <0x11440000 0x100>;
                                 dmas = <&adma 0 &adma 2>;
@@ -1651,9 +1671,11 @@
                                         <&cmu_aud CLK_SCLK_AUD_I2S>,
                                         <&cmu_aud CLK_SCLK_I2S_BCLK>;
                                 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
+                                #clock-cells = <1>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&i2s0_bus>;
                                 power-domains = <&pd_aud>;
+                                #sound-dai-cells = <1>;
                                 status = "disabled";
                         };
 
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
index 22723527e626..00dd89b92b42 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -23,7 +23,7 @@
         };
 
         chosen {
-                linux,stdout-path = &serial_2;
+                stdout-path = &serial_2;
         };
 
         memory@40000000 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
index 82b272fb41b9..bb788eddf9f4 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -70,6 +70,24 @@
                         reg = <0x0>;
                         clocks = <&clockgen 1 0>;
                         #cooling-cells = <2>;
+                        cpu-idle-states = <&CPU_PH20>;
+                };
+        };
+
+        idle-states {
+                /*
+                 * PSCI node is not added default, U-boot will add missing
+                 * parts if it determines to use PSCI.
+                 */
+                entry-method = "arm,psci";
+
+                CPU_PH20: cpu-ph20 {
+                        compatible = "arm,idle-state";
+                        idle-state-name = "PH20";
+                        arm,psci-suspend-param = <0x0>;
+                        entry-latency-us = <1000>;
+                        exit-latency-us = <1000>;
+                        min-residency-us = <3000>;
                 };
         };
 
@@ -118,6 +136,37 @@
                 mask = <0x02>;
         };
 
+        thermal-zones {
+                cpu_thermal: cpu-thermal {
+                        polling-delay-passive = <1000>;
+                        polling-delay = <5000>;
+                        thermal-sensors = <&tmu 0>;
+
+                        trips {
+                                cpu_alert: cpu-alert {
+                                        temperature = <85000>;
+                                        hysteresis = <2000>;
+                                        type = "passive";
+                                };
+
+                                cpu_crit: cpu-crit {
+                                        temperature = <95000>;
+                                        hysteresis = <2000>;
+                                        type = "critical";
+                                };
+                        };
+
+                        cooling-maps {
+                                map0 {
+                                        trip = <&cpu_alert>;
+                                        cooling-device =
+                                                <&cpu0 THERMAL_NO_LIMIT
+                                                THERMAL_NO_LIMIT>;
+                                };
+                        };
+                };
+        };
+
         soc {
                 compatible = "simple-bus";
                 #address-cells = <2>;
@@ -304,37 +353,6 @@
                         #thermal-sensor-cells = <1>;
                 };
 
-                thermal-zones {
-                        cpu_thermal: cpu-thermal {
-                                polling-delay-passive = <1000>;
-                                polling-delay = <5000>;
-                                thermal-sensors = <&tmu 0>;
-
-                                trips {
-                                        cpu_alert: cpu-alert {
-                                                temperature = <85000>;
-                                                hysteresis = <2000>;
-                                                type = "passive";
-                                        };
-
-                                        cpu_crit: cpu-crit {
-                                                temperature = <95000>;
-                                                hysteresis = <2000>;
-                                                type = "critical";
-                                        };
-                                };
-
-                                cooling-maps {
-                                        map0 {
-                                                trip = <&cpu_alert>;
-                                                cooling-device =
-                                                        <&cpu0 THERMAL_NO_LIMIT
-                                                        THERMAL_NO_LIMIT>;
-                                        };
-                                };
-                        };
-                };
-
                 i2c0: i2c@2180000 {
                         compatible = "fsl,vf610-i2c";
                         #address-cells = <1>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 380e7c713395..1109f22bda5e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -81,6 +81,7 @@
                         clocks = <&clockgen 1 0>;
                         next-level-cache = <&l2>;
                         #cooling-cells = <2>;
+                        cpu-idle-states = <&CPU_PH20>;
                 };
 
                 cpu1: cpu@1 {
@@ -89,6 +90,7 @@
                         reg = <0x1>;
                         clocks = <&clockgen 1 0>;
                         next-level-cache = <&l2>;
+                        cpu-idle-states = <&CPU_PH20>;
                 };
 
                 cpu2: cpu@2 {
@@ -97,6 +99,7 @@
                         reg = <0x2>;
                         clocks = <&clockgen 1 0>;
                         next-level-cache = <&l2>;
+                        cpu-idle-states = <&CPU_PH20>;
                 };
 
                 cpu3: cpu@3 {
@@ -105,6 +108,7 @@
                         reg = <0x3>;
                         clocks = <&clockgen 1 0>;
                         next-level-cache = <&l2>;
+                        cpu-idle-states = <&CPU_PH20>;
                 };
 
                 l2: l2-cache {
@@ -112,6 +116,23 @@
                 };
         };
 
+        idle-states {
+                /*
+                 * PSCI node is not added default, U-boot will add missing
+                 * parts if it determines to use PSCI.
+                 */
+                entry-method = "arm,psci";
+
+                CPU_PH20: cpu-ph20 {
+                        compatible = "arm,idle-state";
+                        idle-state-name = "PH20";
+                        arm,psci-suspend-param = <0x0>;
+                        entry-latency-us = <1000>;
+                        exit-latency-us = <1000>;
+                        min-residency-us = <3000>;
+                };
+        };
+
         memory@80000000 {
                 device_type = "memory";
                 reg = <0x0 0x80000000 0 0x80000000>;
@@ -159,6 +180,37 @@
                 mask = <0x02>;
         };
 
+        thermal-zones {
+                cpu_thermal: cpu-thermal {
+                        polling-delay-passive = <1000>;
+                        polling-delay = <5000>;
+
+                        thermal-sensors = <&tmu 3>;
+
+                        trips {
+                                cpu_alert: cpu-alert {
+                                        temperature = <85000>;
+                                        hysteresis = <2000>;
+                                        type = "passive";
+                                };
+                                cpu_crit: cpu-crit {
+                                        temperature = <95000>;
+                                        hysteresis = <2000>;
+                                        type = "critical";
+                                };
+                        };
+
+                        cooling-maps {
+                                map0 {
+                                        trip = <&cpu_alert>;
+                                        cooling-device =
+                                                <&cpu0 THERMAL_NO_LIMIT
+                                                THERMAL_NO_LIMIT>;
+                                };
+                        };
+                };
+        };
+
         timer {
                 compatible = "arm,armv8-timer";
                 interrupts = <1 13 0xf08>, /* Physical Secure PPI */
@@ -342,37 +394,6 @@
                         #thermal-sensor-cells = <1>;
                 };
 
-                thermal-zones {
-                        cpu_thermal: cpu-thermal {
-                                polling-delay-passive = <1000>;
-                                polling-delay = <5000>;
-
-                                thermal-sensors = <&tmu 3>;
-
-                                trips {
-                                        cpu_alert: cpu-alert {
-                                                temperature = <85000>;
-                                                hysteresis = <2000>;
-                                                type = "passive";
-                                        };
-                                        cpu_crit: cpu-crit {
-                                                temperature = <95000>;
-                                                hysteresis = <2000>;
-                                                type = "critical";
-                                        };
-                                };
-
-                                cooling-maps {
-                                        map0 {
-                                                trip = <&cpu_alert>;
-                                                cooling-device =
-                                                        <&cpu0 THERMAL_NO_LIMIT
-                                                        THERMAL_NO_LIMIT>;
-                                        };
-                                };
-                        };
-                };
-
                 qman: qman@1880000 {
                         compatible = "fsl,qman";
                         reg = <0x0 0x1880000 0x0 0x10000>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 06b5e12d04d8..136ebfa9b333 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -122,7 +122,7 @@
                 CPU_PH20: cpu-ph20 {
                         compatible = "arm,idle-state";
                         idle-state-name = "PH20";
-                        arm,psci-suspend-param = <0x00010000>;
+                        arm,psci-suspend-param = <0x0>;
                         entry-latency-us = <1000>;
                         exit-latency-us = <1000>;
                         min-residency-us = <3000>;
@@ -131,6 +131,8 @@
 
         memory@80000000 {
                 device_type = "memory";
+                /* Real size will be filled by bootloader */
+                reg = <0x0 0x80000000 0x0 0x0>;
         };
 
         sysclk: sysclk {
@@ -147,6 +149,37 @@
                 mask = <0x02>;
         };
 
+        thermal-zones {
+                cpu_thermal: cpu-thermal {
+                        polling-delay-passive = <1000>;
+                        polling-delay = <5000>;
+                        thermal-sensors = <&tmu 3>;
+
+                        trips {
+                                cpu_alert: cpu-alert {
+                                        temperature = <85000>;
+                                        hysteresis = <2000>;
+                                        type = "passive";
+                                };
+
+                                cpu_crit: cpu-crit {
+                                        temperature = <95000>;
+                                        hysteresis = <2000>;
+                                        type = "critical";
+                                };
+                        };
+
+                        cooling-maps {
+                                map0 {
+                                        trip = <&cpu_alert>;
+                                        cooling-device =
+                                                <&cpu0 THERMAL_NO_LIMIT
+                                                THERMAL_NO_LIMIT>;
+                                };
+                        };
+                };
+        };
+
         timer {
                 compatible = "arm,armv8-timer";
                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) |
@@ -362,37 +395,6 @@
                         #thermal-sensor-cells = <1>;
                 };
 
-                thermal-zones {
-                        cpu_thermal: cpu-thermal {
-                                polling-delay-passive = <1000>;
-                                polling-delay = <5000>;
-                                thermal-sensors = <&tmu 3>;
-
-                                trips {
-                                        cpu_alert: cpu-alert {
-                                                temperature = <85000>;
-                                                hysteresis = <2000>;
-                                                type = "passive";
-                                        };
-
-                                        cpu_crit: cpu-crit {
-                                                temperature = <95000>;
-                                                hysteresis = <2000>;
-                                                type = "critical";
-                                        };
-                                };
-
-                                cooling-maps {
-                                        map0 {
-                                                trip = <&cpu_alert>;
-                                                cooling-device =
-                                                        <&cpu0 THERMAL_NO_LIMIT
-                                                        THERMAL_NO_LIMIT>;
-                                        };
-                                };
-                        };
-                };
-
                 dspi: dspi@2100000 {
                         compatible = "fsl,ls1021a-v1.0-dspi";
                         #address-cells = <1>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index 4fc150cd4ca5..1c6556bcfddf 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -130,7 +130,7 @@
                 CPU_PH20: cpu-ph20 {
                         compatible = "arm,idle-state";
                         idle-state-name = "PH20";
-                        arm,psci-suspend-param = <0x00010000>;
+                        arm,psci-suspend-param = <0x0>;
                         entry-latency-us = <1000>;
                         exit-latency-us = <1000>;
                         min-residency-us = <3000>;
@@ -158,6 +158,44 @@
                 };
         };
 
+        thermal-zones {
+                cpu_thermal: cpu-thermal {
+                        polling-delay-passive = <1000>;
+                        polling-delay = <5000>;
+                        thermal-sensors = <&tmu 0>;
+
+                        trips {
+                                cpu_alert: cpu-alert {
+                                        temperature = <85000>;
+                                        hysteresis = <2000>;
+                                        type = "passive";
+                                };
+
+                                cpu_crit: cpu-crit {
+                                        temperature = <95000>;
+                                        hysteresis = <2000>;
+                                        type = "critical";
+                                };
+                        };
+
+                        cooling-maps {
+                                map0 {
+                                        trip = <&cpu_alert>;
+                                        cooling-device =
+                                                <&cpu0 THERMAL_NO_LIMIT
+                                                THERMAL_NO_LIMIT>;
+                                };
+
+                                map1 {
+                                        trip = <&cpu_alert>;
+                                        cooling-device =
+                                                <&cpu4 THERMAL_NO_LIMIT
+                                                THERMAL_NO_LIMIT>;
+                                };
+                        };
+                };
+        };
+
         timer {
                 compatible = "arm,armv8-timer";
                 interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
@@ -315,44 +353,6 @@
                         #thermal-sensor-cells = <1>;
                 };
 
-                thermal-zones {
-                        cpu_thermal: cpu-thermal {
-                                polling-delay-passive = <1000>;
-                                polling-delay = <5000>;
-                                thermal-sensors = <&tmu 0>;
-
-                                trips {
-                                        cpu_alert: cpu-alert {
-                                                temperature = <85000>;
-                                                hysteresis = <2000>;
-                                                type = "passive";
-                                        };
-
-                                        cpu_crit: cpu-crit {
-                                                temperature = <95000>;
-                                                hysteresis = <2000>;
-                                                type = "critical";
-                                        };
-                                };
-
-                                cooling-maps {
-                                        map0 {
-                                                trip = <&cpu_alert>;
-                                                cooling-device =
-                                                        <&cpu0 THERMAL_NO_LIMIT
-                                                        THERMAL_NO_LIMIT>;
-                                        };
-
-                                        map1 {
-                                                trip = <&cpu_alert>;
-                                                cooling-device =
-                                                        <&cpu4 THERMAL_NO_LIMIT
-                                                        THERMAL_NO_LIMIT>;
-                                        };
-                                };
-                        };
-                };
-
                 duart0: serial@21c0500 {
                         compatible = "fsl,ns16550", "ns16550a";
                         reg = <0x0 0x21c0500 0x0 0x100>;
@@ -612,6 +612,62 @@
                                         <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
                                         <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
                 };
+
+                cluster1_core0_watchdog: wdt@c000000 {
+                        compatible = "arm,sp805-wdt", "arm,primecell";
+                        reg = <0x0 0xc000000 0x0 0x1000>;
+                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+                        clock-names = "apb_pclk", "wdog_clk";
+                };
+
+                cluster1_core1_watchdog: wdt@c010000 {
+                        compatible = "arm,sp805-wdt", "arm,primecell";
+                        reg = <0x0 0xc010000 0x0 0x1000>;
+                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+                        clock-names = "apb_pclk", "wdog_clk";
+                };
+
+                cluster1_core2_watchdog: wdt@c020000 {
+                        compatible = "arm,sp805-wdt", "arm,primecell";
+                        reg = <0x0 0xc020000 0x0 0x1000>;
+                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+                        clock-names = "apb_pclk", "wdog_clk";
+                };
+
+                cluster1_core3_watchdog: wdt@c030000 {
+                        compatible = "arm,sp805-wdt", "arm,primecell";
+                        reg = <0x0 0xc030000 0x0 0x1000>;
+                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+                        clock-names = "apb_pclk", "wdog_clk";
+                };
+
+                cluster2_core0_watchdog: wdt@c100000 {
+                        compatible = "arm,sp805-wdt", "arm,primecell";
+                        reg = <0x0 0xc100000 0x0 0x1000>;
+                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+                        clock-names = "apb_pclk", "wdog_clk";
+                };
+
+                cluster2_core1_watchdog: wdt@c110000 {
+                        compatible = "arm,sp805-wdt", "arm,primecell";
+                        reg = <0x0 0xc110000 0x0 0x1000>;
+                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+                        clock-names = "apb_pclk", "wdog_clk";
+                };
+
+                cluster2_core2_watchdog: wdt@c120000 {
+                        compatible = "arm,sp805-wdt", "arm,primecell";
+                        reg = <0x0 0xc120000 0x0 0x1000>;
+                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+                        clock-names = "apb_pclk", "wdog_clk";
+                };
+
+                cluster2_core3_watchdog: wdt@c130000 {
+                        compatible = "arm,sp805-wdt", "arm,primecell";
+                        reg = <0x0 0xc130000 0x0 0x1000>;
+                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+                        clock-names = "apb_pclk", "wdog_clk";
+                };
         };
 
         firmware {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
index aeaef01d375f..0884e1a77901 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
@@ -143,7 +143,7 @@
         CPU_PW20: cpu-pw20 {
                 compatible = "arm,idle-state";
                 idle-state-name = "PW20";
-                arm,psci-suspend-param = <0x00010000>;
+                arm,psci-suspend-param = <0x0>;
                 entry-latency-us = <2000>;
                 exit-latency-us = <2000>;
                 min-residency-us = <6000>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
index b2374469a830..1de618801c73 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
@@ -140,21 +140,21 @@
 
 &dspi {
         status = "okay";
-        dflash0: n25q128a {
+        dflash0: n25q128a@0 {
                 #address-cells = <1>;
                 #size-cells = <1>;
                 compatible = "st,m25p80";
                 spi-max-frequency = <3000000>;
                 reg = <0>;
         };
-        dflash1: sst25wf040b {
+        dflash1: sst25wf040b@1 {
                 #address-cells = <1>;
                 #size-cells = <1>;
                 compatible = "st,m25p80";
                 spi-max-frequency = <3000000>;
                 reg = <1>;
         };
-        dflash2: en25s64 {
+        dflash2: en25s64@2 {
                 #address-cells = <1>;
                 #size-cells = <1>;
                 compatible = "st,m25p80";
@@ -177,7 +177,7 @@
                 #size-cells = <1>;
                 compatible = "st,m25p80";
                 spi-max-frequency = <20000000>;
-                reg = <0>;
+                reg = <2>;
         };
 };
 
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index f3a40af33af8..137ef4dfc3e9 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -111,6 +111,55 @@
                 mask = <0x2>;
         };
 
+        thermal-zones {
+                cpu_thermal: cpu-thermal {
+                        polling-delay-passive = <1000>;
+                        polling-delay = <5000>;
+
+                        thermal-sensors = <&tmu 4>;
+
+                        trips {
+                                cpu_alert: cpu-alert {
+                                        temperature = <75000>;
+                                        hysteresis = <2000>;
+                                        type = "passive";
+                                };
+                                cpu_crit: cpu-crit {
+                                        temperature = <85000>;
+                                        hysteresis = <2000>;
+                                        type = "critical";
+                                };
+                        };
+
+                        cooling-maps {
+                                map0 {
+                                        trip = <&cpu_alert>;
+                                        cooling-device =
+                                                <&cpu0 THERMAL_NO_LIMIT
+                                                THERMAL_NO_LIMIT>;
+                                };
+                                map1 {
+                                        trip = <&cpu_alert>;
+                                        cooling-device =
+                                                <&cpu2 THERMAL_NO_LIMIT
+                                                THERMAL_NO_LIMIT>;
+                                };
+                                map2 {
+                                        trip = <&cpu_alert>;
+                                        cooling-device =
+                                                <&cpu4 THERMAL_NO_LIMIT
+                                                THERMAL_NO_LIMIT>;
+                                };
+                                map3 {
+                                        trip = <&cpu_alert>;
+                                        cooling-device =
+                                                <&cpu6 THERMAL_NO_LIMIT
+                                                THERMAL_NO_LIMIT>;
+                                };
+                        };
+                };
+        };
+
         timer {
                 compatible = "arm,armv8-timer";
                 interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
@@ -194,55 +243,6 @@
                         #thermal-sensor-cells = <1>;
                 };
 
-                thermal-zones {
-                        cpu_thermal: cpu-thermal {
-                                polling-delay-passive = <1000>;
-                                polling-delay = <5000>;
-
-                                thermal-sensors = <&tmu 4>;
-
-                                trips {
-                                        cpu_alert: cpu-alert {
-                                                temperature = <75000>;
-                                                hysteresis = <2000>;
-                                                type = "passive";
-                                        };
-                                        cpu_crit: cpu-crit {
-                                                temperature = <85000>;
-                                                hysteresis = <2000>;
-                                                type = "critical";
-                                        };
-                                };
-
-                                cooling-maps {
-                                        map0 {
-                                                trip = <&cpu_alert>;
-                                                cooling-device =
-                                                        <&cpu0 THERMAL_NO_LIMIT
-                                                        THERMAL_NO_LIMIT>;
-                                        };
-                                        map1 {
-                                                trip = <&cpu_alert>;
-                                                cooling-device =
-                                                        <&cpu2 THERMAL_NO_LIMIT
-                                                        THERMAL_NO_LIMIT>;
-                                        };
-                                        map2 {
-                                                trip = <&cpu_alert>;
-                                                cooling-device =
-                                                        <&cpu4 THERMAL_NO_LIMIT
-                                                        THERMAL_NO_LIMIT>;
-                                        };
-                                        map3 {
-                                                trip = <&cpu_alert>;
-                                                cooling-device =
-                                                        <&cpu6 THERMAL_NO_LIMIT
-                                                        THERMAL_NO_LIMIT>;
-                                        };
-                                };
-                        };
-                };
-
                 serial0: serial@21c0500 {
                         compatible = "fsl,ns16550", "ns16550a";
                         reg = <0x0 0x21c0500 0x0 0x100>;
diff --git a/arch/arm64/boot/dts/freescale/qoriq-bman-portals.dtsi b/arch/arm64/boot/dts/freescale/qoriq-bman-portals.dtsi
index c3c2be4f5072..ae15307f6e8b 100644
--- a/arch/arm64/boot/dts/freescale/qoriq-bman-portals.dtsi
+++ b/arch/arm64/boot/dts/freescale/qoriq-bman-portals.dtsi
@@ -68,4 +68,10 @@
                 reg = <0x80000 0x4000>, <0x4080000 0x4000>;
                 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
         };
+
+        bman-portal@90000 {
+                compatible = "fsl,bman-portal";
+                reg = <0x90000 0x4000>, <0x4090000 0x4000>;
+                interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+        };
 };
diff --git a/arch/arm64/boot/dts/freescale/qoriq-qman-portals.dtsi b/arch/arm64/boot/dts/freescale/qoriq-qman-portals.dtsi
index 2a9aa060efda..6a93a4a9be0e 100644
--- a/arch/arm64/boot/dts/freescale/qoriq-qman-portals.dtsi
+++ b/arch/arm64/boot/dts/freescale/qoriq-qman-portals.dtsi
@@ -77,4 +77,11 @@
                 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
                 cell-index = <8>;
         };
+
+        qportal9: qman-portal@90000 {
+                compatible = "fsl,qman-portal";
+                reg = <0x90000 0x4000>, <0x4090000 0x4000>;
+                interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+                cell-index = <9>;
+        };
 };
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index 63d4f9dca77f..4ce4c282e19e 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -100,11 +100,7 @@
                         reg = <0x0 0x100>;
                         enable-method = "psci";
                         next-level-cache = <&A73_L2>;
-                        cpu-idle-states = <
-                                        &CPU_NAP
-                                        &CPU_SLEEP
-                                        &CLUSTER_SLEEP_1
-                        >;
+                        cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>;
                         capacity-dmips-mhz = <1024>;
                 };
 
@@ -114,11 +110,7 @@
                         reg = <0x0 0x101>;
                         enable-method = "psci";
                         next-level-cache = <&A73_L2>;
-                        cpu-idle-states = <
-                                        &CPU_NAP
-                                        &CPU_SLEEP
-                                        &CLUSTER_SLEEP_1
-                        >;
+                        cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>;
                         capacity-dmips-mhz = <1024>;
                 };
 
@@ -128,11 +120,7 @@
                         reg = <0x0 0x102>;
                         enable-method = "psci";
                         next-level-cache = <&A73_L2>;
-                        cpu-idle-states = <
-                                        &CPU_NAP
-                                        &CPU_SLEEP
-                                        &CLUSTER_SLEEP_1
-                        >;
+                        cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>;
                         capacity-dmips-mhz = <1024>;
                 };
 
@@ -142,25 +130,13 @@
                         reg = <0x0 0x103>;
                         enable-method = "psci";
                         next-level-cache = <&A73_L2>;
-                        cpu-idle-states = <
-                                        &CPU_NAP
-                                        &CPU_SLEEP
-                                        &CLUSTER_SLEEP_1
-                        >;
+                        cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>;
                         capacity-dmips-mhz = <1024>;
                 };
 
                 idle-states {
                         entry-method = "psci";
 
-                        CPU_NAP: cpu-nap {
-                                compatible = "arm,idle-state";
-                                arm,psci-suspend-param = <0x0000001>;
-                                entry-latency-us = <7>;
-                                exit-latency-us = <2>;
-                                min-residency-us = <15>;
-                        };
-
                         CPU_SLEEP: cpu-sleep {
                                 compatible = "arm,idle-state";
                                 local-timer-stop;
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
index e94fa1a53192..724a0d3b7683 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
@@ -51,7 +51,7 @@
                 #size-cells = <2>;
                 ranges;
 
-                ramoops@0x21f00000 {
+                ramoops@21f00000 {
                         compatible = "ramoops";
                         reg = <0x0 0x21f00000 0x0 0x00100000>;
                         record-size     = <0x00020000>;
@@ -299,7 +299,9 @@
                 /* GPIO blocks 16 thru 19 do not appear to be routed to pins */
 
                 dwmmc_0: dwmmc0@f723d000 {
+                        max-frequency = <150000000>;
                         cap-mmc-highspeed;
+                        mmc-hs200-1_8v;
                         non-removable;
                         bus-width = <0x8>;
                         vmmc-supply = <&ldo19>;
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 6a180d1926e8..586b281cd531 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -88,8 +88,6 @@
                         next-level-cache = <&CLUSTER0_L2>;
                         clocks = <&stub_clock 0>;
                         operating-points-v2 = <&cpu_opp_table>;
-                        cooling-min-level = <4>;
-                        cooling-max-level = <0>;
                         #cooling-cells = <2>; /* min followed by max */
                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
                         dynamic-power-coefficient = <311>;
@@ -817,6 +815,14 @@
                         pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>;
                 };
 
+                watchdog0: watchdog@f8005000 {
+                        compatible = "arm,sp805-wdt", "arm,primecell";
+                        reg = <0x0 0xf8005000 0x0 0x1000>;
+                        interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&ao_ctrl HI6220_WDT0_PCLK>;
+                        clock-names = "apb_pclk";
+                };
+
                 tsensor: tsensor@0,f7030700 {
                         compatible = "hisilicon,tsensor";
                         reg = <0x0 0xf7030700 0x0 0x1000>;
diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
index a049b64f2101..35202ebe62a7 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
@@ -291,6 +291,13 @@
                         #interrupt-cells = <2>;
                         num-pins = <128>;
                 };
+
+                mbigen_pcie0: intc_pcie0 {
+                        msi-parent = <&its_dsa 0x40085>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        num-pins = <10>;
+                };
         };
 
         mbigen_dsa@c0080000 {
@@ -312,6 +319,31 @@
                 };
         };
 
+        /**
+         *  HiSilicon erratum 161010801: This describes the limitation
+         *  of HiSilicon platforms hip06/hip07 to support the SMMUv3
+         *  mappings for PCIe MSI transactions.
+         *  PCIe controller on these platforms has to differentiate the
+         *  MSI payload against other DMA payload and has to modify the
+         *  MSI payload. This makes it difficult for these platforms to
+         *  have a SMMU translation for MSI. In order to workaround this,
+         *  ARM SMMUv3 driver requires a quirk to treat the MSI regions
+         *  separately. Such a quirk is currently missing for DT based
+         *  systems. Hence please make sure that the smmu pcie node on
+         *  hip06 is disabled as this will break the PCIe functionality
+         *  when iommu-map entry is used along with the PCIe node.
+         *  Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html
+         */
+        smmu0: smmu_pcie {
+                compatible = "arm,smmu-v3";
+                reg = <0x0 0xa0040000 0x0 0x20000>;
+                #iommu-cells = <1>;
+                dma-coherent;
+                smmu-cb-memtype = <0x0 0x1>;
+                hisilicon,broken-prefetch-cmd;
+                status = "disabled";
+        };
+
         soc {
                 compatible = "simple-bus";
                 #address-cells = <2>;
@@ -676,6 +708,30 @@
                                      <637 1>,<638 1>,<639 1>;
                         status = "disabled";
                 };
+
+                pcie0: pcie@a0090000 {
+                        compatible = "hisilicon,hip06-pcie-ecam";
+                        reg = <0 0xb0000000 0 0x2000000>,
+                              <0 0xa0090000 0 0x10000>;
+                        bus-range = <0  31>;
+                        msi-map = <0x0000 &its_dsa 0x0000 0x2000>;
+                        msi-map-mask = <0xffff>;
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        device_type = "pci";
+                        dma-coherent;
+                        ranges = <0x02000000 0 0xb2000000 0x0 0xb2000000 0
+                                 0x5ff0000 0x01000000 0 0 0 0xb7ff0000
+                                 0 0x10000>;
+                        #interrupt-cells = <1>;
+                        interrupt-map-mask = <0xf800 0 0 7>;
+                        interrupt-map = <0x0 0 0 1 &mbigen_pcie0 650 4
+                                        0x0 0 0 2 &mbigen_pcie0 650 4
+                                        0x0 0 0 3 &mbigen_pcie0 650 4
+                                        0x0 0 0 4 &mbigen_pcie0 650 4>;
+                        status = "disabled";
+                };
+
         };
 
 };
diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
index 2c01a21c3665..0600a6a84ab7 100644
--- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
@@ -1083,6 +1083,31 @@
                 };
         };
 
+        /**
+         *  HiSilicon erratum 161010801: This describes the limitation
+         *  of HiSilicon platforms hip06/hip07 to support the SMMUv3
+         *  mappings for PCIe MSI transactions.
+         *  PCIe controller on these platforms has to differentiate the
+         *  MSI payload against other DMA payload and has to modify the
+         *  MSI payload. This makes it difficult for these platforms to
+         *  have a SMMU translation for MSI. In order to workaround this,
+         *  ARM SMMUv3 driver requires a quirk to treat the MSI regions
+         *  separately. Such a quirk is currently missing for DT based
+         *  systems. Hence please make sure that the smmu pcie node on
+         *  hip07 is disabled as this will break the PCIe functionality
+         *  when iommu-map entry is used along with the PCIe node.
+         *  Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html
+         */
+        smmu0: smmu_pcie {
+                compatible = "arm,smmu-v3";
+                reg = <0x0 0xa0040000 0x0 0x20000>;
+                #iommu-cells = <1>;
+                dma-coherent;
+                smmu-cb-memtype = <0x0 0x1>;
+                hisilicon,broken-prefetch-cmd;
+                status = "disabled";
+        };
+
         soc {
                 compatible = "simple-bus";
                 #address-cells = <2>;
@@ -1127,6 +1152,12 @@
                         reg = <0x0 0xc0000000 0x0 0x10000>;
                 };
 
+                dsa_cpld: dsa_cpld@78000010 {
+                        compatible = "syscon";
+                        reg = <0x0 0x78000010 0x0 0x100>;
+                        reg-io-width = <2>;
+                };
+
                 pcie_subctl: pcie_subctl@a0000000 {
                         compatible = "hisilicon,pcie-sas-subctrl", "syscon";
                         reg = <0x0 0xa0000000 0x0 0x10000>;
@@ -1258,6 +1289,7 @@
                         port@0 {
                                 reg = <0>;
                                 serdes-syscon = <&serdes_ctrl>;
+                                cpld-syscon = <&dsa_cpld 0x0>;
                                 port-rst-offset = <0>;
                                 port-mode-offset = <0>;
                                 mc-mac-mask = [ff f0 00 00 00 00];
@@ -1267,6 +1299,7 @@
                         port@1 {
                                 reg = <1>;
                                 serdes-syscon= <&serdes_ctrl>;
+                                cpld-syscon = <&dsa_cpld 0x4>;
                                 port-rst-offset = <1>;
                                 port-mode-offset = <1>;
                                 mc-mac-mask = [ff f0 00 00 00 00];
diff --git a/arch/arm64/boot/dts/marvell/armada-371x.dtsi b/arch/arm64/boot/dts/marvell/armada-371x.dtsi
index 11226f7b9ed9..dc1182ec9fa1 100644
--- a/arch/arm64/boot/dts/marvell/armada-371x.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-371x.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Device Tree Include file for Marvell Armada 371x family of SoCs
  * (also named 88F3710)
@@ -6,43 +7,6 @@
  *
  * Gregory CLEMENT <gregory.clement@free-electrons.com>
  *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 #include "armada-37xx.dtsi"
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
index 0f3468e777f7..f2cc00594d64 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Device Tree file for Marvell Armada 3720 development board
  * (DB-88F3720-DDR3)
@@ -5,44 +6,6 @@
  *
  * Gregory CLEMENT <gregory.clement@free-electrons.com>
  *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- *
  * This file is compatible with the version 1.4 and the version 2.0 of
  * the board, however the CON numbers are different between the 2
  * version
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
index bdfb5553ddb5..ef7fd2ca2515 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
@@ -1,46 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Device Tree file for Globalscale Marvell ESPRESSOBin Board
  * Copyright (C) 2016 Marvell
  *
  * Romain Perier <romain.perier@free-electrons.com>
  *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Schematic available at http://espressobin.net/wp-content/uploads/2017/08/ESPRESSObin_V5_Schematics.pdf
  */
 
 /dts-v1/;
diff --git a/arch/arm64/boot/dts/marvell/armada-372x.dtsi b/arch/arm64/boot/dts/marvell/armada-372x.dtsi
index 2554e0baea6b..97558a64e276 100644
--- a/arch/arm64/boot/dts/marvell/armada-372x.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-372x.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Device Tree Include file for Marvell Armada 372x family of SoCs
  * (also named 88F3720)
@@ -6,43 +7,6 @@
  *
  * Gregory CLEMENT <gregory.clement@free-electrons.com>
  *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 #include "armada-37xx.dtsi"
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index 375026867342..97207a61bc79 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Device Tree Include file for Marvell Armada 37xx family of SoCs.
  *
@@ -5,43 +6,6 @@
  *
  * Gregory CLEMENT <gregory.clement@free-electrons.com>
  *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/arch/arm64/boot/dts/marvell/armada-7020.dtsi b/arch/arm64/boot/dts/marvell/armada-7020.dtsi
index 4ab012991d9d..4e46326dd123 100644
--- a/arch/arm64/boot/dts/marvell/armada-7020.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-7020.dtsi
@@ -1,46 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (C) 2016 Marvell Technology Group Ltd.
  *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
  * Device Tree file for the Armada 7020 SoC, made of an AP806 Dual and
  * one CP110.
  */
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
index 3ae05eee2c9a..d6bec058a30a 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
@@ -1,46 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (C) 2016 Marvell Technology Group Ltd.
  *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
  * Device Tree file for Marvell Armada 7040 Development board platform
  */
 
@@ -162,36 +123,48 @@
         };
 };
 
-&cp0_nand {
+&cp0_nand_controller {
         /*
          * SPI on CPM and NAND have common pins on this board. We can
-         * use only one at a time. To enable the NAND (whihch will
+         * use only one at a time. To enable the NAND (which will
          * disable the SPI), the "status = "okay";" line have to be
          * added here.
          */
-        num-cs = <1>;
         pinctrl-0 = <&nand_pins>, <&nand_rb>;
         pinctrl-names = "default";
-        nand-ecc-strength = <4>;
-        nand-ecc-step-size = <512>;
-        marvell,nand-enable-arbiter;
-        nand-on-flash-bbt;
-
-        partition@0 {
-                label = "U-Boot";
-                reg = <0 0x200000>;
-        };
-        partition@200000 {
-                label = "Linux";
-                reg = <0x200000 0xe00000>;
-        };
-        partition@1000000 {
-                label = "Filesystem";
-                reg = <0x1000000 0x3f000000>;
+
+        nand@0 {
+                reg = <0>;
+                label = "pxa3xx_nand-0";
+                nand-rb = <0>;
+                nand-on-flash-bbt;
+                nand-ecc-strength = <4>;
+                nand-ecc-step-size = <512>;
+
+                partitions {
+                        compatible = "fixed-partitions";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        partition@0 {
+                                label = "U-Boot";
+                                reg = <0 0x200000>;
+                        };
+
+                        partition@200000 {
+                                label = "Linux";
+                                reg = <0x200000 0xe00000>;
+                        };
+
+                        partition@1000000 {
+                                label = "Filesystem";
+                                reg = <0x1000000 0x3f000000>;
+                        };
+
+                };
         };
 };
 
-
 &cp0_spi1 {
         status = "okay";
 
diff --git a/arch/arm64/boot/dts/marvell/armada-7040.dtsi b/arch/arm64/boot/dts/marvell/armada-7040.dtsi
index cbe460b8fc00..47247215770d 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-7040.dtsi
@@ -1,46 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (C) 2016 Marvell Technology Group Ltd.
  *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
  * Device Tree file for the Armada 7040 SoC, made of an AP806 Quad and
  * one CP110.
  */
diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
index f63b4fbd642b..e5c6d7c25819 100644
--- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
@@ -1,46 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (C) 2017 Marvell Technology Group Ltd.
  *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
  * Device Tree file for the Armada 70x0 SoC
  */
 
diff --git a/arch/arm64/boot/dts/marvell/armada-8020.dtsi b/arch/arm64/boot/dts/marvell/armada-8020.dtsi
index 3318d6b0214b..ba1307c0fadb 100644
--- a/arch/arm64/boot/dts/marvell/armada-8020.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8020.dtsi
@@ -1,46 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (C) 2016 Marvell Technology Group Ltd.
  *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
  * Device Tree file for the Armada 8020 SoC, made of an AP806 Dual and
  * two CP110.
  */
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
index dba55baff20f..5689fb23bbab 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
@@ -1,46 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (C) 2016 Marvell Technology Group Ltd.
  *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
  * Device Tree file for Marvell Armada 8040 Development board platform
  */
 
@@ -279,27 +240,35 @@
  * Proper NAND usage will require DPR-76 to be in position 1-2, which disables
  * MDIO signal of CP1.
  */
-&cp1_nand {
-        num-cs = <1>;
+&cp1_nand_controller {
         pinctrl-0 = <&nand_pins>, <&nand_rb>;
         pinctrl-names = "default";
-        nand-ecc-strength = <4>;
-        nand-ecc-step-size = <512>;
-        marvell,nand-enable-arbiter;
-        marvell,system-controller = <&cp1_syscon0>;
-        nand-on-flash-bbt;
-
-        partition@0 {
-                label = "U-Boot";
-                reg = <0 0x200000>;
-        };
-        partition@200000 {
-                label = "Linux";
-                reg = <0x200000 0xe00000>;
-        };
-        partition@1000000 {
-                label = "Filesystem";
-                reg = <0x1000000 0x3f000000>;
+
+        nand@0 {
+                reg = <0>;
+                nand-rb = <0>;
+                nand-on-flash-bbt;
+                nand-ecc-strength = <4>;
+                nand-ecc-step-size = <512>;
+
+                partitions {
+                        compatible = "fixed-partitions";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        partition@0 {
+                                label = "U-Boot";
+                                reg = <0 0x200000>;
+                        };
+                        partition@200000 {
+                                label = "Linux";
+                                reg = <0x200000 0xe00000>;
+                        };
+                        partition@1000000 {
+                                label = "Filesystem";
+                                reg = <0x1000000 0x3f000000>;
+                        };
+                };
         };
 };
 
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
index 626e9d0462c3..81de03ef860d 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
@@ -1,46 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (C) 2016 Marvell Technology Group Ltd.
  *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
  * Device Tree file for MACCHIATOBin Armada 8040 community board platform
  */
 
@@ -49,7 +10,7 @@
 #include <dt-bindings/gpio/gpio.h>
 
 / {
-        model = "Marvell 8040 MACHIATOBin";
+        model = "Marvell 8040 MACCHIATOBin";
         compatible = "marvell,armada8040-mcbin", "marvell,armada8040",
                         "marvell,armada-ap806-quad", "marvell,armada-ap806";
 
@@ -163,6 +124,13 @@
         };
 };
 
+/* J25 UART header */
+&cp0_uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&cp0_uart1_pins>;
+        status = "okay";
+};
+
 &cp0_mdio {
         pinctrl-names = "default";
         pinctrl-0 = <&cp0_ge_mdio_pins>;
@@ -195,6 +163,10 @@
                 marvell,pins = "mpp37", "mpp38";
                 marvell,function = "i2c0";
         };
+        cp0_uart1_pins: uart1-pins {
+                marvell,pins = "mpp40", "mpp41";
+                marvell,function = "uart1";
+        };
         cp0_xhci_vbus_pins: xhci0-vbus-pins {
                 marvell,pins = "mpp47";
                 marvell,function = "gpio";
@@ -290,6 +262,17 @@
                 marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16";
                 marvell,function = "spi1";
         };
+        cp1_uart0_pins: uart0-pins {
+                marvell,pins = "mpp6", "mpp7";
+                marvell,function = "uart0";
+        };
+};
+
+/* J27 UART header */
+&cp1_uart0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&cp1_uart0_pins>;
+        status = "okay";
 };
 
 &cp1_sata0 {
diff --git a/arch/arm64/boot/dts/marvell/armada-8040.dtsi b/arch/arm64/boot/dts/marvell/armada-8040.dtsi
index 83d2b40e5981..7699b19224c2 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8040.dtsi
@@ -1,46 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (C) 2016 Marvell Technology Group Ltd.
  *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
  * Device Tree file for the Armada 8040 SoC, made of an AP806 Quad and
  * two CP110.
  */
diff --git a/arch/arm64/boot/dts/marvell/armada-8080-db.dts b/arch/arm64/boot/dts/marvell/armada-8080-db.dts
index 85b58a19a9fb..4ba158f415ce 100644
--- a/arch/arm64/boot/dts/marvell/armada-8080-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8080-db.dts
@@ -1,46 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (C) 2017 Marvell Technology Group Ltd.
  *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
  * Device Tree file for Marvell Armada-8080 Development board platform
  */
 
diff --git a/arch/arm64/boot/dts/marvell/armada-8080.dtsi b/arch/arm64/boot/dts/marvell/armada-8080.dtsi
index d5535b716735..299e814d1ded 100644
--- a/arch/arm64/boot/dts/marvell/armada-8080.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8080.dtsi
@@ -1,46 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (C) 2017 Marvell Technology Group Ltd.
  *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
  * Device Tree file for Marvell Armada-8080 SoC, made of an AP810 OCTA.
  */
 
diff --git a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
index e9c84a1d3c4d..8129b40f12a4 100644
--- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
@@ -1,46 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (C) 2017 Marvell Technology Group Ltd.
  *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
  * Device Tree file for the Armada 80x0 SoC family
  */
 
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
index b98ea137371d..64b5e61a698e 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
@@ -1,46 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (C) 2016 Marvell Technology Group Ltd.
  *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
  * Device Tree file for Marvell Armada AP806.
  */
 
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
index 116164ff260f..746e792767f5 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
@@ -1,46 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (C) 2016 Marvell Technology Group Ltd.
  *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
  * Device Tree file for Marvell Armada AP806.
  */
 
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index f9b66b81f9fc..176e38d54872 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -1,46 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (C) 2016 Marvell Technology Group Ltd.
  *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
  * Device Tree file for Marvell Armada AP806.
  */
 
diff --git a/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi b/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi
index 7f0661e12f5e..7d00ae78fc79 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi
@@ -1,46 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (C) 2017 Marvell Technology Group Ltd.
  *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
  * Device Tree file for Marvell Armada AP810 OCTA cores.
  */
 
diff --git a/arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi b/arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi
index 7e6f039f0f80..8107d120a8a7 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi
@@ -1,46 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (C) 2017 Marvell Technology Group Ltd.
  *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
  * Device Tree file for Marvell Armada AP810.
  */
 
diff --git a/arch/arm64/boot/dts/marvell/armada-common.dtsi b/arch/arm64/boot/dts/marvell/armada-common.dtsi
index c6dd1d81c68d..d5e8aedec188 100644
--- a/arch/arm64/boot/dts/marvell/armada-common.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-common.dtsi
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR X11)
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (C) 2016 Marvell Technology Group Ltd.
  */
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
index a8af4136dbe7..48cad7919efa 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
@@ -1,9 +1,7 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR X11)
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright (C) 2016 Marvell Technology Group Ltd.
- */
-
-/*
+ *
  * Device Tree file for Marvell Armada CP110.
  */
 
@@ -213,7 +211,9 @@
                         reg = <0x500000 0x4000>;
                         dma-coherent;
                         interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&CP110_LABEL(clk) 1 22>;
+                        clock-names = "core", "reg";
+                        clocks = <&CP110_LABEL(clk) 1 22>,
+                                 <&CP110_LABEL(clk) 1 16>;
                         status = "disabled";
                 };
 
@@ -223,7 +223,9 @@
                         reg = <0x510000 0x4000>;
                         dma-coherent;
                         interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&CP110_LABEL(clk) 1 23>;
+                        clock-names = "core", "reg";
+                        clocks = <&CP110_LABEL(clk) 1 23>,
+                                 <&CP110_LABEL(clk) 1 16>;
                         status = "disabled";
                 };
 
@@ -232,7 +234,8 @@
                         "generic-ahci";
                         reg = <0x540000 0x30000>;
                         interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&CP110_LABEL(clk) 1 15>;
+                        clocks = <&CP110_LABEL(clk) 1 15>,
+                                 <&CP110_LABEL(clk) 1 16>;
                         status = "disabled";
                 };
 
@@ -241,7 +244,9 @@
                         reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
                         dma-coherent;
                         msi-parent = <&gic_v2m0>;
-                        clocks = <&CP110_LABEL(clk) 1 8>;
+                        clock-names = "core", "reg";
+                        clocks = <&CP110_LABEL(clk) 1 8>,
+                                 <&CP110_LABEL(clk) 1 14>;
                 };
 
                 CP110_LABEL(xor1): xor@6c0000 {
@@ -249,7 +254,9 @@
                         reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
                         dma-coherent;
                         msi-parent = <&gic_v2m0>;
-                        clocks = <&CP110_LABEL(clk) 1 7>;
+                        clock-names = "core", "reg";
+                        clocks = <&CP110_LABEL(clk) 1 7>,
+                                 <&CP110_LABEL(clk) 1 14>;
                 };
 
                 CP110_LABEL(spi0): spi@700600 {
@@ -257,7 +264,9 @@
                         reg = <0x700600 0x50>;
                         #address-cells = <0x1>;
                         #size-cells = <0x0>;
-                        clocks = <&CP110_LABEL(clk) 1 21>;
+                        clock-names = "core", "axi";
+                        clocks = <&CP110_LABEL(clk) 1 21>,
+                                 <&CP110_LABEL(clk) 1 17>;
                         status = "disabled";
                 };
 
@@ -266,7 +275,9 @@
                         reg = <0x700680 0x50>;
                         #address-cells = <1>;
                         #size-cells = <0>;
-                        clocks = <&CP110_LABEL(clk) 1 21>;
+                        clock-names = "core", "axi";
+                        clocks = <&CP110_LABEL(clk) 1 21>,
+                                 <&CP110_LABEL(clk) 1 17>;
                         status = "disabled";
                 };
 
@@ -276,7 +287,9 @@
                         #address-cells = <1>;
                         #size-cells = <0>;
                         interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&CP110_LABEL(clk) 1 21>;
+                        clock-names = "core", "reg";
+                        clocks = <&CP110_LABEL(clk) 1 21>,
+                                 <&CP110_LABEL(clk) 1 17>;
                         status = "disabled";
                 };
 
@@ -286,23 +299,75 @@
                         #address-cells = <1>;
                         #size-cells = <0>;
                         interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&CP110_LABEL(clk) 1 21>;
+                        clock-names = "core", "reg";
+                        clocks = <&CP110_LABEL(clk) 1 21>,
+                                 <&CP110_LABEL(clk) 1 17>;
+                        status = "disabled";
+                };
+
+                CP110_LABEL(uart0): serial@702000 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x702000 0x100>;
+                        reg-shift = <2>;
+                        interrupts = <ICU_GRP_NSR 122 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-io-width = <1>;
+                        clock-names = "baudclk", "apb_pclk";
+                        clocks = <&CP110_LABEL(clk) 1 21>,
+                                 <&CP110_LABEL(clk) 1 17>;
+                        status = "disabled";
+                };
+
+                CP110_LABEL(uart1): serial@702100 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x702100 0x100>;
+                        reg-shift = <2>;
+                        interrupts = <ICU_GRP_NSR 123 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-io-width = <1>;
+                        clock-names = "baudclk", "apb_pclk";
+                        clocks = <&CP110_LABEL(clk) 1 21>,
+                                 <&CP110_LABEL(clk) 1 17>;
+                        status = "disabled";
+                };
+
+                CP110_LABEL(uart2): serial@702200 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x702200 0x100>;
+                        reg-shift = <2>;
+                        interrupts = <ICU_GRP_NSR 124 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-io-width = <1>;
+                        clock-names = "baudclk", "apb_pclk";
+                        clocks = <&CP110_LABEL(clk) 1 21>,
+                                 <&CP110_LABEL(clk) 1 17>;
                         status = "disabled";
                 };
 
-                CP110_LABEL(nand): nand@720000 {
+                CP110_LABEL(uart3): serial@702300 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x702300 0x100>;
+                        reg-shift = <2>;
+                        interrupts = <ICU_GRP_NSR 125 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-io-width = <1>;
+                        clock-names = "baudclk", "apb_pclk";
+                        clocks = <&CP110_LABEL(clk) 1 21>,
+                                 <&CP110_LABEL(clk) 1 17>;
+                        status = "disabled";
+                };
+
+                CP110_LABEL(nand_controller): nand@720000 {
                         /*
                         * Due to the limitation of the pins available
                         * this controller is only usable on the CPM
                         * for A7K and on the CPS for A8K.
                         */
-                        compatible = "marvell,armada-8k-nand",
-                        "marvell,armada370-nand";
+                        compatible = "marvell,armada-8k-nand-controller",
+                                "marvell,armada370-nand-controller";
                         reg = <0x720000 0x54>;
                         #address-cells = <1>;
-                        #size-cells = <1>;
+                        #size-cells = <0>;
                         interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&CP110_LABEL(clk) 1 2>;
+                        clock-names = "core", "reg";
+                        clocks = <&CP110_LABEL(clk) 1 2>,
+                                 <&CP110_LABEL(clk) 1 17>;
                         marvell,system-controller = <&CP110_LABEL(syscon0)>;
                         status = "disabled";
                 };
@@ -312,7 +377,9 @@
                         "inside-secure,safexcel-eip76";
                         reg = <0x760000 0x7d>;
                         interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&CP110_LABEL(clk) 1 25>;
+                        clock-names = "core", "reg";
+                        clocks = <&CP110_LABEL(clk) 1 25>,
+                                 <&CP110_LABEL(clk) 1 17>;
                         status = "okay";
                 };
 
@@ -337,7 +404,9 @@
                                 <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-names = "mem", "ring0", "ring1",
                                 "ring2", "ring3", "eip";
-                        clocks = <&CP110_LABEL(clk) 1 26>;
+                        clock-names = "core", "reg";
+                        clocks = <&CP110_LABEL(clk) 1 26>,
+                                 <&CP110_LABEL(clk) 1 17>;
                         dma-coherent;
                 };
         };
@@ -364,7 +433,8 @@
                 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
                 interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
                 num-lanes = <1>;
-                clocks = <&CP110_LABEL(clk) 1 13>;
+                clock-names = "core", "reg";
+                clocks = <&CP110_LABEL(clk) 1 13>, <&CP110_LABEL(clk) 1 14>;
                 status = "disabled";
         };
 
@@ -391,7 +461,8 @@
                 interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
 
                 num-lanes = <1>;
-                clocks = <&CP110_LABEL(clk) 1 11>;
+                clock-names = "core", "reg";
+                clocks = <&CP110_LABEL(clk) 1 11>, <&CP110_LABEL(clk) 1 14>;
                 status = "disabled";
         };
 
@@ -418,7 +489,8 @@
                 interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
 
                 num-lanes = <1>;
-                clocks = <&CP110_LABEL(clk) 1 12>;
+                clock-names = "core", "reg";
+                clocks = <&CP110_LABEL(clk) 1 12>, <&CP110_LABEL(clk) 1 14>;
                 status = "disabled";
         };
 };
diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
index 10f9c76cd105..4ce9d6ca0bf7 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
@@ -41,6 +41,10 @@
 
 };
 
+&auxadc {
+        status = "okay";
+};
+
 &cpu0 {
         proc-supply = <&cpus_fixed_vproc0>;
 };
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index fdf66f4fe7c3..9d88f41aefa0 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -289,6 +289,15 @@
                          (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>;
         };
 
+        auxadc: adc@11001000 {
+                compatible = "mediatek,mt2712-auxadc";
+                reg = <0 0x11001000 0 0x1000>;
+                clocks = <&pericfg CLK_PERI_AUXADC>;
+                clock-names = "main";
+                #io-channel-cells = <1>;
+                status = "disabled";
+        };
+
         uart0: serial@11002000 {
                 compatible = "mediatek,mt2712-uart",
                              "mediatek,mt6577-uart";
diff --git a/arch/arm64/boot/dts/mediatek/mt6380.dtsi b/arch/arm64/boot/dts/mediatek/mt6380.dtsi
new file mode 100644
index 000000000000..53b335d2de5f
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6380.dtsi
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for MediaTek MT6380 regulator
+ *
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Chenglin Xu <chenglin.xu@mediatek.com>
+ *         Sean Wang <sean.wang@mediatek.com>
+ */
+
+&pwrap {
+        regulators {
+                compatible = "mediatek,mt6380-regulator";
+
+                mt6380_vcpu_reg: buck-vcore1 {
+                        regulator-name = "vcore1";
+                        regulator-min-microvolt = < 600000>;
+                        regulator-max-microvolt = <1393750>;
+                        regulator-ramp-delay = <6250>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                };
+
+                mt6380_vcore_reg: buck-vcore {
+                        regulator-name = "vcore";
+                        regulator-min-microvolt = <600000>;
+                        regulator-max-microvolt = <1393750>;
+                        regulator-ramp-delay = <6250>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                };
+
+                mt6380_vrf_reg: buck-vrf {
+                        regulator-name = "vrf";
+                        regulator-min-microvolt = <1200000>;
+                        regulator-max-microvolt = <1575000>;
+                        regulator-ramp-delay = <0>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                };
+
+                mt6380_vm_reg: ldo-vm {
+                        regulator-name = "vm";
+                        regulator-min-microvolt = <1050000>;
+                        regulator-max-microvolt = <1400000>;
+                        regulator-ramp-delay = <0>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                };
+
+                mt6380_va_reg: ldo-va {
+                        regulator-name = "va";
+                        regulator-min-microvolt = <2200000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-ramp-delay = <0>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                };
+
+                mt6380_vphy_reg: ldo-vphy {
+                        regulator-name = "vphy";
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                        regulator-ramp-delay = <0>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                };
+
+                mt6380_vddr_reg: ldo-vddr {
+                        regulator-name = "vddr";
+                        regulator-min-microvolt = <1240000>;
+                        regulator-max-microvolt = <1840000>;
+                        regulator-ramp-delay = <0>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                };
+
+                mt6380_vt_reg: ldo-vt {
+                        regulator-name = "vt";
+                        regulator-min-microvolt = <2200000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-ramp-delay = <0>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                };
+        };
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
index c08309df2cc7..45d8655ee423 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
@@ -7,7 +7,11 @@
  */
 
 /dts-v1/;
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
 #include "mt7622.dtsi"
+#include "mt6380.dtsi"
 
 / {
         model = "MediaTek MT7622 RFB1 board";
@@ -17,11 +21,476 @@
                 bootargs = "console=ttyS0,115200n1";
         };
 
+        cpus {
+                cpu@0 {
+                        proc-supply = <&mt6380_vcpu_reg>;
+                        sram-supply = <&mt6380_vm_reg>;
+                };
+
+                cpu@1 {
+                        proc-supply = <&mt6380_vcpu_reg>;
+                        sram-supply = <&mt6380_vm_reg>;
+                };
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys-polled";
+                poll-interval = <100>;
+
+                factory {
+                        label = "factory";
+                        linux,code = <BTN_0>;
+                        gpios = <&pio 0 0>;
+                };
+
+                wps {
+                        label = "wps";
+                        linux,code = <KEY_WPS_BUTTON>;
+                        gpios = <&pio 102 0>;
+                };
+        };
+
         memory {
                 reg = <0 0x40000000 0 0x3F000000>;
         };
+
+        reg_1p8v: regulator-1p8v {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-1.8V";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                regulator-always-on;
+        };
+
+        reg_3p3v: regulator-3p3v {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-3.3V";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-boot-on;
+                regulator-always-on;
+        };
+
+        reg_5v: regulator-5v {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-5V";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-boot-on;
+                regulator-always-on;
+        };
+};
+
+&pcie {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pcie0_pins>;
+        status = "okay";
+
+        pcie@0,0 {
+                status = "okay";
+        };
+};
+
+&pio {
+        /* eMMC is shared pin with parallel NAND */
+        emmc_pins_default: emmc-pins-default {
+                mux {
+                        function = "emmc", "emmc_rst";
+                        groups = "emmc";
+                };
+
+                /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
+                 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
+                 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
+                 */
+                conf-cmd-dat {
+                        pins = "NDL0", "NDL1", "NDL2",
+                               "NDL3", "NDL4", "NDL5",
+                               "NDL6", "NDL7", "NRB";
+                        input-enable;
+                        bias-pull-up;
+                };
+
+                conf-clk {
+                        pins = "NCLE";
+                        bias-pull-down;
+                };
+        };
+
+        emmc_pins_uhs: emmc-pins-uhs {
+                mux {
+                        function = "emmc";
+                        groups = "emmc";
+                };
+
+                conf-cmd-dat {
+                        pins = "NDL0", "NDL1", "NDL2",
+                               "NDL3", "NDL4", "NDL5",
+                               "NDL6", "NDL7", "NRB";
+                        input-enable;
+                        drive-strength = <4>;
+                        bias-pull-up;
+                };
+
+                conf-clk {
+                        pins = "NCLE";
+                        drive-strength = <4>;
+                        bias-pull-down;
+                };
+        };
+
+        eth_pins: eth-pins {
+                mux {
+                        function = "eth";
+                        groups = "mdc_mdio", "rgmii_via_gmac2";
+                };
+        };
+
+        i2c1_pins: i2c1-pins {
+                mux {
+                        function = "i2c";
+                        groups =  "i2c1_0";
+                };
+        };
+
+        i2c2_pins: i2c2-pins {
+                mux {
+                        function = "i2c";
+                        groups =  "i2c2_0";
+                };
+        };
+
+        i2s1_pins: i2s1-pins {
+                mux {
+                        function = "i2s";
+                        groups =  "i2s_out_bclk_ws_mclk",
+                                  "i2s1_in_data",
+                                  "i2s1_out_data";
+                };
+        };
+
+        irrx_pins: irrx-pins {
+                mux {
+                        function = "ir";
+                        groups =  "ir_1_rx";
+                };
+        };
+
+        irtx_pins: irtx-pins {
+                mux {
+                        function = "ir";
+                        groups =  "ir_1_tx";
+                };
+        };
+
+        /* Parallel nand is shared pin with eMMC */
+        parallel_nand_pins: parallel-nand-pins {
+                mux {
+                        function = "flash";
+                        groups = "par_nand";
+                };
+        };
+
+        pcie0_pins: pcie0-pins {
+                mux {
+                        function = "pcie";
+                        groups = "pcie0_pad_perst",
+                                 "pcie0_1_waken",
+                                 "pcie0_1_clkreq";
+                };
+        };
+
+        pcie1_pins: pcie1-pins {
+                mux {
+                        function = "pcie";
+                        groups = "pcie1_pad_perst",
+                                 "pcie1_0_waken",
+                                 "pcie1_0_clkreq";
+                };
+        };
+
+        pmic_bus_pins: pmic-bus-pins {
+                mux {
+                        function = "pmic";
+                        groups = "pmic_bus";
+                };
+        };
+
+        pwm7_pins: pwm1-2-pins {
+                mux {
+                        function = "pwm";
+                        groups = "pwm_ch7_2";
+                };
+        };
+
+        wled_pins: wled-pins {
+                mux {
+                        function = "led";
+                        groups = "wled";
+                };
+        };
+
+        sd0_pins_default: sd0-pins-default {
+                mux {
+                        function = "sd";
+                        groups = "sd_0";
+                };
+
+                /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
+                 *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
+                 *  DAT2, DAT3, CMD, CLK for SD respectively.
+                 */
+                conf-cmd-data {
+                        pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
+                               "I2S2_IN","I2S4_OUT";
+                        input-enable;
+                        drive-strength = <8>;
+                        bias-pull-up;
+                };
+                conf-clk {
+                        pins = "I2S3_OUT";
+                        drive-strength = <12>;
+                        bias-pull-down;
+                };
+                conf-cd {
+                        pins = "TXD3";
+                        bias-pull-up;
+                };
+        };
+
+        sd0_pins_uhs: sd0-pins-uhs {
+                mux {
+                        function = "sd";
+                        groups = "sd_0";
+                };
+
+                conf-cmd-data {
+                        pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
+                               "I2S2_IN","I2S4_OUT";
+                        input-enable;
+                        bias-pull-up;
+                };
+
+                conf-clk {
+                        pins = "I2S3_OUT";
+                        bias-pull-down;
+                };
+        };
+
+        /* Serial NAND is shared pin with SPI-NOR */
+        serial_nand_pins: serial-nand-pins {
+                mux {
+                        function = "flash";
+                        groups = "snfi";
+                };
+        };
+
+        spic0_pins: spic0-pins {
+                mux {
+                        function = "spi";
+                        groups = "spic0_0";
+                };
+        };
+
+        spic1_pins: spic1-pins {
+                mux {
+                        function = "spi";
+                        groups = "spic1_0";
+                };
+        };
+
+        /* SPI-NOR is shared pin with serial NAND */
+        spi_nor_pins: spi-nor-pins {
+                mux {
+                        function = "flash";
+                        groups = "spi_nor";
+                };
+        };
+
+        /* serial NAND is shared pin with SPI-NOR */
+        serial_nand_pins: serial-nand-pins {
+                mux {
+                        function = "flash";
+                        groups = "snfi";
+                };
+        };
+
+        uart0_pins: uart0-pins {
+                mux {
+                        function = "uart";
+                        groups = "uart0_0_tx_rx" ;
+                };
+        };
+
+        uart2_pins: uart2-pins {
+                mux {
+                        function = "uart";
+                        groups = "uart2_1_tx_rx" ;
+                };
+        };
+
+        watchdog_pins: watchdog-pins {
+                mux {
+                        function = "watchdog";
+                        groups = "watchdog";
+                };
+        };
+};
+
+&bch {
+        status = "disabled";
+};
+
+&btif {
+        status = "okay";
+};
+
+&cir {
+        pinctrl-names = "default";
+        pinctrl-0 = <&irrx_pins>;
+        status = "okay";
+};
+
+&eth {
+        pinctrl-names = "default";
+        pinctrl-0 = <&eth_pins>;
+        status = "okay";
+
+        gmac1: mac@1 {
+                compatible = "mediatek,eth-mac";
+                reg = <1>;
+                phy-handle = <&phy5>;
+        };
+
+        mdio-bus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                phy5: ethernet-phy@5 {
+                        reg = <5>;
+                        phy-mode = "sgmii";
+                };
+        };
+};
+
+&i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c1_pins>;
+        status = "okay";
+};
+
+&i2c2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c2_pins>;
+        status = "okay";
+};
+
+&mmc0 {
+        pinctrl-names = "default", "state_uhs";
+        pinctrl-0 = <&emmc_pins_default>;
+        pinctrl-1 = <&emmc_pins_uhs>;
+        status = "okay";
+        bus-width = <8>;
+        max-frequency = <50000000>;
+        cap-mmc-highspeed;
+        mmc-hs200-1_8v;
+        vmmc-supply = <&reg_3p3v>;
+        vqmmc-supply = <&reg_1p8v>;
+        assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
+        assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
+        non-removable;
+};
+
+&mmc1 {
+        pinctrl-names = "default", "state_uhs";
+        pinctrl-0 = <&sd0_pins_default>;
+        pinctrl-1 = <&sd0_pins_uhs>;
+        status = "okay";
+        bus-width = <4>;
+        max-frequency = <50000000>;
+        cap-sd-highspeed;
+        r_smpl = <1>;
+        cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
+        vmmc-supply = <&reg_3p3v>;
+        vqmmc-supply = <&reg_3p3v>;
+        assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
+        assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
+};
+
+&nandc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&parallel_nand_pins>;
+        status = "disabled";
+};
+
+&nor_flash {
+        pinctrl-names = "default";
+        pinctrl-0 = <&spi_nor_pins>;
+        status = "disabled";
+
+        flash@0 {
+                compatible = "jedec,spi-nor";
+                reg = <0>;
+        };
+};
+
+&pwm {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pwm7_pins>;
+        status = "okay";
+};
+
+&pwrap {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pmic_bus_pins>;
+
+        status = "okay";
+};
+
+&sata {
+        status = "okay";
+};
+
+&sata_phy {
+        status = "okay";
+};
+
+&spi0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&spic0_pins>;
+        status = "okay";
+};
+
+&spi1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&spic1_pins>;
+        status = "okay";
+};
+
+&ssusb {
+        vusb33-supply = <&reg_3p3v>;
+        vbus-supply = <&reg_5v>;
+        status = "okay";
+};
+
+&u3phy {
+        status = "okay";
 };
 
 &uart0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart0_pins>;
+        status = "okay";
+};
+
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart2_pins>;
+        status = "okay";
+};
+
+&watchdog {
+        pinctrl-names = "default";
+        pinctrl-0 = <&watchdog_pins>;
         status = "okay";
 };
diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
index b111fec2ed9d..e9d5130df8d1 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -8,6 +8,11 @@
 
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/mt7622-clk.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/power/mt7622-power.h>
+#include <dt-bindings/reset/mt7622-reset.h>
+#include <dt-bindings/thermal/thermal.h>
 
 / {
         compatible = "mediatek,mt7622";
@@ -15,6 +20,50 @@
         #address-cells = <2>;
         #size-cells = <2>;
 
+        cpu_opp_table: opp-table {
+                compatible = "operating-points-v2";
+                opp-shared;
+                opp-300000000 {
+                        opp-hz = /bits/ 64 <30000000>;
+                        opp-microvolt = <950000>;
+                };
+
+                opp-437500000 {
+                        opp-hz = /bits/ 64 <437500000>;
+                        opp-microvolt = <1000000>;
+                };
+
+                opp-600000000 {
+                        opp-hz = /bits/ 64 <600000000>;
+                        opp-microvolt = <1050000>;
+                };
+
+                opp-812500000 {
+                        opp-hz = /bits/ 64 <812500000>;
+                        opp-microvolt = <1100000>;
+                };
+
+                opp-1025000000 {
+                        opp-hz = /bits/ 64 <1025000000>;
+                        opp-microvolt = <1150000>;
+                };
+
+                opp-1137500000 {
+                        opp-hz = /bits/ 64 <1137500000>;
+                        opp-microvolt = <1200000>;
+                };
+
+                opp-1262500000 {
+                        opp-hz = /bits/ 64 <1262500000>;
+                        opp-microvolt = <1250000>;
+                };
+
+                opp-1350000000 {
+                        opp-hz = /bits/ 64 <1350000000>;
+                        opp-microvolt = <1310000>;
+                };
+        };
+
         cpus {
                 #address-cells = <2>;
                 #size-cells = <0>;
@@ -23,6 +72,11 @@
                         device_type = "cpu";
                         compatible = "arm,cortex-a53", "arm,armv8";
                         reg = <0x0 0x0>;
+                        clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
+                                 <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
+                        clock-names = "cpu", "intermediate";
+                        operating-points-v2 = <&cpu_opp_table>;
+                        #cooling-cells = <2>;
                         enable-method = "psci";
                         clock-frequency = <1300000000>;
                 };
@@ -31,21 +85,26 @@
                         device_type = "cpu";
                         compatible = "arm,cortex-a53", "arm,armv8";
                         reg = <0x0 0x1>;
+                        clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
+                                 <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
+                        clock-names = "cpu", "intermediate";
+                        operating-points-v2 = <&cpu_opp_table>;
                         enable-method = "psci";
                         clock-frequency = <1300000000>;
                 };
         };
 
-        uart_clk: dummy25m {
+        pwrap_clk: dummy40m {
                 compatible = "fixed-clock";
+                clock-frequency = <40000000>;
                 #clock-cells = <0>;
-                clock-frequency = <25000000>;
         };
 
-        bus_clk: dummy280m {
+        clk25m: oscillator {
                 compatible = "fixed-clock";
                 #clock-cells = <0>;
-                clock-frequency = <280000000>;
+                clock-frequency = <25000000>;
+                clock-output-names = "clkxtal";
         };
 
         psci {
@@ -65,6 +124,58 @@
                 };
         };
 
+        thermal-zones {
+                cpu_thermal: cpu-thermal {
+                        polling-delay-passive = <1000>;
+                        polling-delay = <1000>;
+
+                        thermal-sensors = <&thermal 0>;
+
+                        trips {
+                                cpu_passive: cpu-passive {
+                                        temperature = <47000>;
+                                        hysteresis = <2000>;
+                                        type = "passive";
+                                };
+
+                                cpu_active: cpu-active {
+                                        temperature = <67000>;
+                                        hysteresis = <2000>;
+                                        type = "active";
+                                };
+
+                                cpu_hot: cpu-hot {
+                                        temperature = <87000>;
+                                        hysteresis = <2000>;
+                                        type = "hot";
+                                };
+
+                                cpu-crit {
+                                        temperature = <107000>;
+                                        hysteresis = <2000>;
+                                        type = "critical";
+                                };
+                        };
+
+                        cooling-maps {
+                                map0 {
+                                        trip = <&cpu_passive>;
+                                        cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                                };
+
+                                map1 {
+                                        trip = <&cpu_active>;
+                                        cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                                };
+
+                                map2 {
+                                        trip = <&cpu_hot>;
+                                        cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                                };
+                        };
+                };
+        };
+
         timer {
                 compatible = "arm,armv8-timer";
                 interrupt-parent = <&gic>;
@@ -78,6 +189,58 @@
                               IRQ_TYPE_LEVEL_HIGH)>;
         };
 
+        infracfg: infracfg@10000000 {
+                compatible = "mediatek,mt7622-infracfg",
+                             "syscon";
+                reg = <0 0x10000000 0 0x1000>;
+                #clock-cells = <1>;
+                #reset-cells = <1>;
+        };
+
+        pwrap: pwrap@10001000 {
+                compatible = "mediatek,mt7622-pwrap";
+                reg = <0 0x10001000 0 0x250>;
+                reg-names = "pwrap";
+                clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>;
+                clock-names = "spi", "wrap";
+                resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>;
+                reset-names = "pwrap";
+                interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+        };
+
+        pericfg: pericfg@10002000 {
+                compatible = "mediatek,mt7622-pericfg",
+                             "syscon";
+                reg = <0 0x10002000 0 0x1000>;
+                #clock-cells = <1>;
+                #reset-cells = <1>;
+        };
+
+        scpsys: scpsys@10006000 {
+                compatible = "mediatek,mt7622-scpsys",
+                             "syscon";
+                #power-domain-cells = <1>;
+                reg = <0 0x10006000 0 0x1000>;
+                interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
+                             <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
+                             <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
+                             <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
+                infracfg = <&infracfg>;
+                clocks = <&topckgen CLK_TOP_HIF_SEL>;
+                clock-names = "hif_sel";
+        };
+
+        cir: cir@10009000 {
+                compatible = "mediatek,mt7622-cir";
+                reg = <0 0x10009000 0 0x1000>;
+                interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>;
+                clocks = <&infracfg CLK_INFRA_IRRX_PD>,
+                         <&topckgen CLK_TOP_AXI_SEL>;
+                clock-names = "clk", "bus";
+                status = "disabled";
+        };
+
         sysirq: interrupt-controller@10200620 {
                 compatible = "mediatek,mt7622-sysirq",
                              "mediatek,mt6577-sysirq";
@@ -87,6 +250,62 @@
                 reg = <0 0x10200620 0 0x20>;
         };
 
+        efuse: efuse@10206000 {
+                compatible = "mediatek,mt7622-efuse",
+                             "mediatek,efuse";
+                reg = <0 0x10206000 0 0x1000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                thermal_calibration: calib@198 {
+                        reg = <0x198 0xc>;
+                };
+        };
+
+        apmixedsys: apmixedsys@10209000 {
+                compatible = "mediatek,mt7622-apmixedsys",
+                             "syscon";
+                reg = <0 0x10209000 0 0x1000>;
+                #clock-cells = <1>;
+        };
+
+        topckgen: topckgen@10210000 {
+                compatible = "mediatek,mt7622-topckgen",
+                             "syscon";
+                reg = <0 0x10210000 0 0x1000>;
+                #clock-cells = <1>;
+        };
+
+        rng: rng@1020f000 {
+                compatible = "mediatek,mt7622-rng",
+                             "mediatek,mt7623-rng";
+                reg = <0 0x1020f000 0 0x1000>;
+                clocks = <&infracfg CLK_INFRA_TRNG>;
+                clock-names = "rng";
+        };
+
+        pio: pinctrl@10211000 {
+                compatible = "mediatek,mt7622-pinctrl";
+                reg = <0 0x10211000 0 0x1000>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        watchdog: watchdog@10212000 {
+                compatible = "mediatek,mt7622-wdt",
+                             "mediatek,mt6589-wdt";
+                reg = <0 0x10212000 0 0x800>;
+        };
+
+        rtc: rtc@10212800 {
+                compatible = "mediatek,mt7622-rtc",
+                             "mediatek,soc-rtc";
+                reg = <0 0x10212800 0 0x200>;
+                interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
+                clocks = <&topckgen CLK_TOP_RTC>;
+                clock-names = "rtc";
+        };
+
         gic: interrupt-controller@10300000 {
                 compatible = "arm,gic-400";
                 interrupt-controller;
@@ -98,13 +317,459 @@
                       <0 0x10360000 0 0x2000>;
         };
 
+        auxadc: adc@11001000 {
+                compatible = "mediatek,mt7622-auxadc";
+                reg = <0 0x11001000 0 0x1000>;
+                clocks = <&pericfg CLK_PERI_AUXADC_PD>;
+                clock-names = "main";
+                #io-channel-cells = <1>;
+        };
+
         uart0: serial@11002000 {
                 compatible = "mediatek,mt7622-uart",
                              "mediatek,mt6577-uart";
                 reg = <0 0x11002000 0 0x400>;
                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
-                clocks = <&uart_clk>, <&bus_clk>;
+                clocks = <&topckgen CLK_TOP_UART_SEL>,
+                         <&pericfg CLK_PERI_UART1_PD>;
+                clock-names = "baud", "bus";
+                status = "disabled";
+        };
+
+        uart1: serial@11003000 {
+                compatible = "mediatek,mt7622-uart",
+                             "mediatek,mt6577-uart";
+                reg = <0 0x11003000 0 0x400>;
+                interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
+                clocks = <&topckgen CLK_TOP_UART_SEL>,
+                         <&pericfg CLK_PERI_UART1_PD>;
+                clock-names = "baud", "bus";
+                status = "disabled";
+        };
+
+        uart2: serial@11004000 {
+                compatible = "mediatek,mt7622-uart",
+                             "mediatek,mt6577-uart";
+                reg = <0 0x11004000 0 0x400>;
+                interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
+                clocks = <&topckgen CLK_TOP_UART_SEL>,
+                         <&pericfg CLK_PERI_UART2_PD>;
+                clock-names = "baud", "bus";
+                status = "disabled";
+        };
+
+        uart3: serial@11005000 {
+                compatible = "mediatek,mt7622-uart",
+                             "mediatek,mt6577-uart";
+                reg = <0 0x11005000 0 0x400>;
+                interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
+                clocks = <&topckgen CLK_TOP_UART_SEL>,
+                         <&pericfg CLK_PERI_UART3_PD>;
+                clock-names = "baud", "bus";
+                status = "disabled";
+        };
+
+        pwm: pwm@11006000 {
+                compatible = "mediatek,mt7622-pwm";
+                reg = <0 0x11006000 0 0x1000>;
+                interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
+                clocks = <&topckgen CLK_TOP_PWM_SEL>,
+                         <&pericfg CLK_PERI_PWM_PD>,
+                         <&pericfg CLK_PERI_PWM1_PD>,
+                         <&pericfg CLK_PERI_PWM2_PD>,
+                         <&pericfg CLK_PERI_PWM3_PD>,
+                         <&pericfg CLK_PERI_PWM4_PD>,
+                         <&pericfg CLK_PERI_PWM5_PD>,
+                         <&pericfg CLK_PERI_PWM6_PD>;
+                clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
+                              "pwm5", "pwm6";
+                status = "disabled";
+        };
+
+        i2c0: i2c@11007000 {
+                compatible = "mediatek,mt7622-i2c";
+                reg = <0 0x11007000 0 0x90>,
+                      <0 0x11000100 0 0x80>;
+                interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
+                clock-div = <16>;
+                clocks = <&pericfg CLK_PERI_I2C0_PD>,
+                         <&pericfg CLK_PERI_AP_DMA_PD>;
+                clock-names = "main", "dma";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+
+        i2c1: i2c@11008000 {
+                compatible = "mediatek,mt7622-i2c";
+                reg = <0 0x11008000 0 0x90>,
+                      <0 0x11000180 0 0x80>;
+                interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
+                clock-div = <16>;
+                clocks = <&pericfg CLK_PERI_I2C1_PD>,
+                         <&pericfg CLK_PERI_AP_DMA_PD>;
+                clock-names = "main", "dma";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+
+        i2c2: i2c@11009000 {
+                compatible = "mediatek,mt7622-i2c";
+                reg = <0 0x11009000 0 0x90>,
+                      <0 0x11000200 0 0x80>;
+                interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
+                clock-div = <16>;
+                clocks = <&pericfg CLK_PERI_I2C2_PD>,
+                         <&pericfg CLK_PERI_AP_DMA_PD>;
+                clock-names = "main", "dma";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+
+        spi0: spi@1100a000 {
+                compatible = "mediatek,mt7622-spi";
+                reg = <0 0x1100a000 0 0x100>;
+                interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
+                clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
+                         <&topckgen CLK_TOP_SPI0_SEL>,
+                         <&pericfg CLK_PERI_SPI0_PD>;
+                clock-names = "parent-clk", "sel-clk", "spi-clk";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+
+        thermal: thermal@1100b000 {
+                #thermal-sensor-cells = <1>;
+                compatible = "mediatek,mt7622-thermal";
+                reg = <0 0x1100b000 0 0x1000>;
+                interrupts = <0 78 IRQ_TYPE_LEVEL_LOW>;
+                clocks = <&pericfg CLK_PERI_THERM_PD>,
+                         <&pericfg CLK_PERI_AUXADC_PD>;
+                clock-names = "therm", "auxadc";
+                resets = <&pericfg MT7622_PERI_THERM_SW_RST>;
+                reset-names = "therm";
+                mediatek,auxadc = <&auxadc>;
+                mediatek,apmixedsys = <&apmixedsys>;
+                nvmem-cells = <&thermal_calibration>;
+                nvmem-cell-names = "calibration-data";
+        };
+
+        btif: serial@1100c000 {
+                compatible = "mediatek,mt7622-btif",
+                             "mediatek,mtk-btif";
+                reg = <0 0x1100c000 0 0x1000>;
+                interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
+                clocks = <&pericfg CLK_PERI_BTIF_PD>;
+                clock-names = "main";
+                reg-shift = <2>;
+                reg-io-width = <4>;
+                status = "disabled";
+        };
+
+        nandc: nfi@1100d000 {
+                compatible = "mediatek,mt7622-nfc";
+                reg = <0 0x1100D000 0 0x1000>;
+                interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
+                clocks = <&pericfg CLK_PERI_NFI_PD>,
+                         <&pericfg CLK_PERI_SNFI_PD>;
+                clock-names = "nfi_clk", "pad_clk";
+                ecc-engine = <&bch>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+
+        bch: ecc@1100e000 {
+                compatible = "mediatek,mt7622-ecc";
+                reg = <0 0x1100e000 0 0x1000>;
+                interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
+                clocks = <&pericfg CLK_PERI_NFIECC_PD>;
+                clock-names = "nfiecc_clk";
+                status = "disabled";
+        };
+
+        nor_flash: spi@11014000 {
+                compatible = "mediatek,mt7622-nor",
+                             "mediatek,mt8173-nor";
+                reg = <0 0x11014000 0 0xe0>;
+                clocks = <&pericfg CLK_PERI_FLASH_PD>,
+                         <&topckgen CLK_TOP_FLASH_SEL>;
+                clock-names = "spi", "sf";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+
+        spi1: spi@11016000 {
+                compatible = "mediatek,mt7622-spi";
+                reg = <0 0x11016000 0 0x100>;
+                interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>;
+                clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
+                         <&topckgen CLK_TOP_SPI1_SEL>,
+                         <&pericfg CLK_PERI_SPI1_PD>;
+                clock-names = "parent-clk", "sel-clk", "spi-clk";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+
+        uart4: serial@11019000 {
+                compatible = "mediatek,mt7622-uart",
+                             "mediatek,mt6577-uart";
+                reg = <0 0x11019000 0 0x400>;
+                interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
+                clocks = <&topckgen CLK_TOP_UART_SEL>,
+                         <&pericfg CLK_PERI_UART4_PD>;
                 clock-names = "baud", "bus";
                 status = "disabled";
         };
+
+        mmc0: mmc@11230000 {
+                compatible = "mediatek,mt7622-mmc";
+                reg = <0 0x11230000 0 0x1000>;
+                interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
+                clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
+                         <&topckgen CLK_TOP_MSDC50_0_SEL>;
+                clock-names = "source", "hclk";
+                status = "disabled";
+        };
+
+        mmc1: mmc@11240000 {
+                compatible = "mediatek,mt7622-mmc";
+                reg = <0 0x11240000 0 0x1000>;
+                interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
+                clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
+                         <&topckgen CLK_TOP_AXI_SEL>;
+                clock-names = "source", "hclk";
+                status = "disabled";
+        };
+
+        ssusbsys: ssusbsys@1a000000 {
+                compatible = "mediatek,mt7622-ssusbsys",
+                             "syscon";
+                reg = <0 0x1a000000 0 0x1000>;
+                #clock-cells = <1>;
+                #reset-cells = <1>;
+        };
+
+        ssusb: usb@1a0c0000 {
+                compatible = "mediatek,mt7622-xhci",
+                             "mediatek,mtk-xhci";
+                reg = <0 0x1a0c0000 0 0x01000>,
+                      <0 0x1a0c4700 0 0x0100>;
+                reg-names = "mac", "ippc";
+                interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
+                power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
+                clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
+                         <&ssusbsys CLK_SSUSB_REF_EN>,
+                         <&ssusbsys CLK_SSUSB_MCU_EN>,
+                         <&ssusbsys CLK_SSUSB_DMA_EN>;
+                clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
+                phys = <&u2port0 PHY_TYPE_USB2>,
+                       <&u3port0 PHY_TYPE_USB3>,
+                       <&u2port1 PHY_TYPE_USB2>;
+
+                status = "disabled";
+        };
+
+        u3phy: usb-phy@1a0c4000 {
+                compatible = "mediatek,mt7622-u3phy",
+                             "mediatek,generic-tphy-v1";
+                reg = <0 0x1a0c4000 0 0x700>;
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
+                status = "disabled";
+
+                u2port0: usb-phy@1a0c4800 {
+                        reg = <0 0x1a0c4800 0 0x0100>;
+                        #phy-cells = <1>;
+                        clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
+                        clock-names = "ref";
+                };
+
+                u3port0: usb-phy@1a0c4900 {
+                        reg = <0 0x1a0c4900 0 0x0700>;
+                        #phy-cells = <1>;
+                        clocks = <&clk25m>;
+                        clock-names = "ref";
+                };
+
+                u2port1: usb-phy@1a0c5000 {
+                        reg = <0 0x1a0c5000 0 0x0100>;
+                        #phy-cells = <1>;
+                        clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
+                        clock-names = "ref";
+                };
+        };
+
+        pciesys: pciesys@1a100800 {
+                compatible = "mediatek,mt7622-pciesys",
+                             "syscon";
+                reg = <0 0x1a100800 0 0x1000>;
+                #clock-cells = <1>;
+                #reset-cells = <1>;
+        };
+
+        pcie: pcie@1a140000 {
+                compatible = "mediatek,mt7622-pcie";
+                device_type = "pci";
+                reg = <0 0x1a140000 0 0x1000>,
+                      <0 0x1a143000 0 0x1000>,
+                      <0 0x1a145000 0 0x1000>;
+                reg-names = "subsys", "port0", "port1";
+                #address-cells = <3>;
+                #size-cells = <2>;
+                interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
+                             <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
+                clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
+                         <&pciesys CLK_PCIE_P1_MAC_EN>,
+                         <&pciesys CLK_PCIE_P0_AHB_EN>,
+                         <&pciesys CLK_PCIE_P0_AHB_EN>,
+                         <&pciesys CLK_PCIE_P0_AUX_EN>,
+                         <&pciesys CLK_PCIE_P1_AUX_EN>,
+                         <&pciesys CLK_PCIE_P0_AXI_EN>,
+                         <&pciesys CLK_PCIE_P1_AXI_EN>,
+                         <&pciesys CLK_PCIE_P0_OBFF_EN>,
+                         <&pciesys CLK_PCIE_P1_OBFF_EN>,
+                         <&pciesys CLK_PCIE_P0_PIPE_EN>,
+                         <&pciesys CLK_PCIE_P1_PIPE_EN>;
+                clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
+                              "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
+                              "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
+                power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
+                bus-range = <0x00 0xff>;
+                ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
+                status = "disabled";
+
+                pcie0: pcie@0,0 {
+                        reg = <0x0000 0 0 0 0>;
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        #interrupt-cells = <1>;
+                        ranges;
+                        status = "disabled";
+
+                        num-lanes = <1>;
+                        interrupt-map-mask = <0 0 0 7>;
+                        interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+                                        <0 0 0 2 &pcie_intc0 1>,
+                                        <0 0 0 3 &pcie_intc0 2>,
+                                        <0 0 0 4 &pcie_intc0 3>;
+                        pcie_intc0: interrupt-controller {
+                                interrupt-controller;
+                                #address-cells = <0>;
+                                #interrupt-cells = <1>;
+                        };
+                };
+
+                pcie1: pcie@1,0 {
+                        reg = <0x0800 0 0 0 0>;
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        #interrupt-cells = <1>;
+                        ranges;
+                        status = "disabled";
+
+                        num-lanes = <1>;
+                        interrupt-map-mask = <0 0 0 7>;
+                        interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+                                        <0 0 0 2 &pcie_intc1 1>,
+                                        <0 0 0 3 &pcie_intc1 2>,
+                                        <0 0 0 4 &pcie_intc1 3>;
+                        pcie_intc1: interrupt-controller {
+                                interrupt-controller;
+                                #address-cells = <0>;
+                                #interrupt-cells = <1>;
+                        };
+                };
+        };
+
+        sata: sata@1a200000 {
+                compatible = "mediatek,mt7622-ahci",
+                             "mediatek,mtk-ahci";
+                reg = <0 0x1a200000 0 0x1100>;
+                interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "hostc";
+                clocks = <&pciesys CLK_SATA_AHB_EN>,
+                         <&pciesys CLK_SATA_AXI_EN>,
+                         <&pciesys CLK_SATA_ASIC_EN>,
+                         <&pciesys CLK_SATA_RBC_EN>,
+                         <&pciesys CLK_SATA_PM_EN>;
+                clock-names = "ahb", "axi", "asic", "rbc", "pm";
+                phys = <&sata_port PHY_TYPE_SATA>;
+                phy-names = "sata-phy";
+                ports-implemented = <0x1>;
+                power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
+                resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
+                         <&pciesys MT7622_SATA_PHY_SW_RST>,
+                         <&pciesys MT7622_SATA_PHY_REG_RST>;
+                reset-names = "axi", "sw", "reg";
+                mediatek,phy-mode = <&pciesys>;
+                status = "disabled";
+        };
+
+        sata_phy: sata-phy@1a243000 {
+                compatible = "mediatek,generic-tphy-v1";
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
+                status = "disabled";
+
+                sata_port: sata-phy@1a243000 {
+                        reg = <0 0x1a243000 0 0x0100>;
+                        clocks = <&topckgen CLK_TOP_ETH_500M>;
+                        clock-names = "ref";
+                        #phy-cells = <1>;
+                };
+        };
+
+        ethsys: syscon@1b000000 {
+                compatible = "mediatek,mt7622-ethsys",
+                             "syscon";
+                reg = <0 0x1b000000 0 0x1000>;
+                #clock-cells = <1>;
+                #reset-cells = <1>;
+        };
+
+        eth: ethernet@1b100000 {
+                compatible = "mediatek,mt7622-eth",
+                             "mediatek,mt2701-eth",
+                             "syscon";
+                reg = <0 0x1b100000 0 0x20000>;
+                interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
+                             <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
+                             <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
+                clocks = <&topckgen CLK_TOP_ETH_SEL>,
+                         <&ethsys CLK_ETH_ESW_EN>,
+                         <&ethsys CLK_ETH_GP0_EN>,
+                         <&ethsys CLK_ETH_GP1_EN>,
+                         <&ethsys CLK_ETH_GP2_EN>,
+                         <&sgmiisys CLK_SGMII_TX250M_EN>,
+                         <&sgmiisys CLK_SGMII_RX250M_EN>,
+                         <&sgmiisys CLK_SGMII_CDR_REF>,
+                         <&sgmiisys CLK_SGMII_CDR_FB>,
+                         <&topckgen CLK_TOP_SGMIIPLL>,
+                         <&apmixedsys CLK_APMIXED_ETH2PLL>;
+                clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
+                              "sgmii_tx250m", "sgmii_rx250m",
+                              "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
+                              "eth2pll";
+                power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
+                mediatek,ethsys = <&ethsys>;
+                mediatek,sgmiisys = <&sgmiisys>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+
+        sgmiisys: sgmiisys@1b128000 {
+                compatible = "mediatek,mt7622-sgmiisys",
+                             "syscon";
+                reg = <0 0x1b128000 0 0x1000>;
+                #clock-cells = <1>;
+        };
 };
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 9fbe4705ee88..94597e33c806 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -341,7 +341,7 @@
                         reg = <0 0x10005000 0 0x1000>;
                 };
 
-                pio: pinctrl@0x10005000 {
+                pio: pinctrl@10005000 {
                         compatible = "mediatek,mt8173-pinctrl";
                         reg = <0 0x1000b000 0 0x1000>;
                         mediatek,pctl-regmap = <&syscfg_pctl_a>;
diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile
index 676aa2f238d1..7c13d7df484e 100644
--- a/arch/arm64/boot/dts/nvidia/Makefile
+++ b/arch/arm64/boot/dts/nvidia/Makefile
@@ -5,3 +5,4 @@ dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-2180.dtb
 dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2571.dtb
 dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-smaug.dtb
 dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p2771-0000.dtb
+dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p2972-0000.dtb
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
new file mode 100644
index 000000000000..ecb034177fc2
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
@@ -0,0 +1,248 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "tegra194.dtsi"
+
+#include <dt-bindings/mfd/max77620.h>
+
+/ {
+        model = "NVIDIA Tegra194 P2888 Processor Module";
+        compatible = "nvidia,p2888", "nvidia,tegra194";
+
+        aliases {
+                sdhci0 = "/cbb/sdhci@3460000";
+                sdhci1 = "/cbb/sdhci@3400000";
+                serial0 = &uartb;
+                i2c0 = "/bpmp/i2c";
+                i2c1 = "/cbb/i2c@3160000";
+                i2c2 = "/cbb/i2c@c240000";
+                i2c3 = "/cbb/i2c@3180000";
+                i2c4 = "/cbb/i2c@3190000";
+                i2c5 = "/cbb/i2c@31c0000";
+                i2c6 = "/cbb/i2c@c250000";
+                i2c7 = "/cbb/i2c@31e0000";
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8";
+                stdout-path = "serial0:115200n8";
+        };
+
+        cbb {
+                serial@3110000 {
+                        status = "okay";
+                };
+
+                /* SDMMC1 (SD/MMC) */
+                sdhci@3400000 {
+/*
+                        cd-gpios = <&gpio TEGRA194_MAIN_GPIO(A, 0) GPIO_ACTIVE_LOW>;
+*/
+                };
+
+                /* SDMMC4 (eMMC) */
+                sdhci@3460000 {
+                        status = "okay";
+                        bus-width = <8>;
+                        non-removable;
+
+                        vqmmc-supply = <&vdd_1v8ls>;
+                        vmmc-supply = <&vdd_emmc_3v3>;
+                };
+
+                pmc@c360000 {
+                        nvidia,invert-interrupt;
+                };
+        };
+
+        bpmp {
+                i2c {
+                        status = "okay";
+
+                        pmic: pmic@3c {
+                                compatible = "maxim,max20024";
+                                reg = <0x3c>;
+
+                                interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
+                                #interrupt-cells = <2>;
+                                interrupt-controller;
+
+                                #gpio-cells = <2>;
+                                gpio-controller;
+
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&max20024_default>;
+
+                                max20024_default: pinmux {
+                                        gpio0 {
+                                                pins = "gpio0";
+                                                function = "gpio";
+                                        };
+
+                                        gpio1 {
+                                                pins = "gpio1";
+                                                function = "fps-out";
+                                                maxim,active-fps-source = <MAX77620_FPS_SRC_DEF>;
+                                        };
+
+                                        gpio2 {
+                                                pins = "gpio2";
+                                                function = "fps-out";
+                                                maxim,active-fps-source = <MAX77620_FPS_SRC_DEF>;
+                                        };
+
+                                        gpio3 {
+                                                pins = "gpio3";
+                                                function = "fps-out";
+                                                maxim,active-fps-source = <MAX77620_FPS_SRC_DEF>;
+                                        };
+
+                                        gpio4 {
+                                                pins = "gpio4";
+                                                function = "32k-out1";
+                                                drive-push-pull = <1>;
+                                        };
+
+                                        gpio6 {
+                                                pins = "gpio6";
+                                                function = "gpio";
+                                                drive-push-pull = <1>;
+                                        };
+
+                                        gpio7 {
+                                                pins = "gpio7";
+                                                function = "gpio";
+                                                drive-push-pull = <0>;
+                                        };
+                                };
+
+                                fps {
+                                        fps0 {
+                                                maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
+                                                maxim,shutdown-fps-time-period-us = <640>;
+                                        };
+
+                                        fps1 {
+                                                maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
+                                                maxim,shutdown-fps-time-period-us = <640>;
+                                                maxim,device-state-on-disabled-event = <MAX77620_FPS_INACTIVE_STATE_SLEEP>;
+                                        };
+
+                                        fps2 {
+                                                maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
+                                                maxim,shutdown-fps-time-period-us = <640>;
+                                        };
+                                };
+
+                                regulators {
+                                        in-sd0-supply = <&vdd_5v0_sys>;
+                                        in-sd1-supply = <&vdd_5v0_sys>;
+                                        in-sd2-supply = <&vdd_5v0_sys>;
+                                        in-sd3-supply = <&vdd_5v0_sys>;
+                                        in-sd4-supply = <&vdd_5v0_sys>;
+
+                                        in-ldo0-1-supply = <&vdd_5v0_sys>;
+                                        in-ldo2-supply = <&vdd_5v0_sys>;
+                                        in-ldo3-5-supply = <&vdd_5v0_sys>;
+                                        in-ldo4-6-supply = <&vdd_5v0_sys>;
+                                        in-ldo7-8-supply = <&vdd_1v8ls>;
+
+                                        sd0 {
+                                                regulator-name = "VDD_1V0";
+                                                regulator-min-microvolt = <1000000>;
+                                                regulator-max-microvolt = <1000000>;
+                                                regulator-always-on;
+                                                regulator-boot-on;
+                                        };
+
+                                        sd1 {
+                                                regulator-name = "VDD_1V8HS";
+                                                regulator-min-microvolt = <1800000>;
+                                                regulator-max-microvolt = <1800000>;
+                                                regulator-always-on;
+                                                regulator-boot-on;
+                                        };
+
+                                        vdd_1v8ls: sd2 {
+                                                regulator-name = "VDD_1V8LS";
+                                                regulator-min-microvolt = <1800000>;
+                                                regulator-max-microvolt = <1800000>;
+                                                regulator-always-on;
+                                                regulator-boot-on;
+                                        };
+
+                                        sd3 {
+                                                regulator-name = "VDD_1V8AO";
+                                                regulator-min-microvolt = <1800000>;
+                                                regulator-max-microvolt = <1800000>;
+                                                regulator-always-on;
+                                                regulator-boot-on;
+                                        };
+
+                                        sd4 {
+                                                regulator-name = "VDD_DDR_1V1";
+                                                regulator-min-microvolt = <1100000>;
+                                                regulator-max-microvolt = <1100000>;
+                                                regulator-always-on;
+                                                regulator-boot-on;
+                                        };
+
+                                        ldo0 {
+                                                regulator-name = "VDD_RTC";
+                                                regulator-min-microvolt = <800000>;
+                                                regulator-max-microvolt = <800000>;
+                                                regulator-always-on;
+                                                regulator-boot-on;
+                                        };
+
+                                        ldo2 {
+                                                regulator-name = "VDD_AO_3V3";
+                                                regulator-min-microvolt = <3300000>;
+                                                regulator-max-microvolt = <3300000>;
+                                                regulator-always-on;
+                                                regulator-boot-on;
+                                        };
+
+                                        vdd_emmc_3v3: ldo3 {
+                                                regulator-name = "VDD_EMMC_3V3";
+                                                regulator-min-microvolt = <3300000>;
+                                                regulator-max-microvolt = <3300000>;
+                                        };
+
+                                        ldo5 {
+                                                regulator-name = "VDD_USB_3V3";
+                                                regulator-min-microvolt = <3300000>;
+                                                regulator-max-microvolt = <3300000>;
+                                        };
+
+                                        ldo6 {
+                                                regulator-name = "VDD_SDIO_3V3";
+                                                regulator-min-microvolt = <3300000>;
+                                                regulator-max-microvolt = <3300000>;
+                                        };
+
+                                        ldo7 {
+                                                regulator-name = "VDD_CSI_1V2";
+                                                regulator-min-microvolt = <1200000>;
+                                                regulator-max-microvolt = <1200000>;
+                                        };
+                                };
+                        };
+                };
+        };
+
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                vdd_5v0_sys: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+
+                        regulator-name = "VIN_SYS_5V0";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                };
+        };
+};
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
new file mode 100644
index 000000000000..9ff3c18280c4
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "tegra194-p2888.dtsi"
+
+/ {
+        model = "NVIDIA Tegra194 P2972-0000 Development Board";
+        compatible = "nvidia,p2972-0000", "nvidia,tegra194";
+
+        cbb {
+                /* SDMMC1 (SD/MMC) */
+                sdhci@3400000 {
+                        status = "okay";
+                };
+        };
+};
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
new file mode 100644
index 000000000000..6322ef265c2f
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -0,0 +1,344 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/clock/tegra194-clock.h>
+#include <dt-bindings/gpio/tegra194-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mailbox/tegra186-hsp.h>
+#include <dt-bindings/reset/tegra194-reset.h>
+
+/ {
+        compatible = "nvidia,tegra194";
+        interrupt-parent = <&gic>;
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        /* control backbone */
+        cbb {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0x0 0x0 0x0 0x40000000>;
+
+                uarta: serial@3100000 {
+                        compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
+                        reg = <0x03100000 0x40>;
+                        reg-shift = <2>;
+                        interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&bpmp TEGRA194_CLK_UARTA>;
+                        clock-names = "serial";
+                        resets = <&bpmp TEGRA194_RESET_UARTA>;
+                        reset-names = "serial";
+                        status = "disabled";
+                };
+
+                uartb: serial@3110000 {
+                        compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
+                        reg = <0x03110000 0x40>;
+                        reg-shift = <2>;
+                        interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&bpmp TEGRA194_CLK_UARTB>;
+                        clock-names = "serial";
+                        resets = <&bpmp TEGRA194_RESET_UARTB>;
+                        reset-names = "serial";
+                        status = "disabled";
+                };
+
+                uartd: serial@3130000 {
+                        compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
+                        reg = <0x03130000 0x40>;
+                        reg-shift = <2>;
+                        interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&bpmp TEGRA194_CLK_UARTD>;
+                        clock-names = "serial";
+                        resets = <&bpmp TEGRA194_RESET_UARTD>;
+                        reset-names = "serial";
+                        status = "disabled";
+                };
+
+                uarte: serial@3140000 {
+                        compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
+                        reg = <0x03140000 0x40>;
+                        reg-shift = <2>;
+                        interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&bpmp TEGRA194_CLK_UARTE>;
+                        clock-names = "serial";
+                        resets = <&bpmp TEGRA194_RESET_UARTE>;
+                        reset-names = "serial";
+                        status = "disabled";
+                };
+
+                uartf: serial@3150000 {
+                        compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
+                        reg = <0x03150000 0x40>;
+                        reg-shift = <2>;
+                        interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&bpmp TEGRA194_CLK_UARTF>;
+                        clock-names = "serial";
+                        resets = <&bpmp TEGRA194_RESET_UARTF>;
+                        reset-names = "serial";
+                        status = "disabled";
+                };
+
+                gen1_i2c: i2c@3160000 {
+                        compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
+                        reg = <0x03160000 0x10000>;
+                        interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&bpmp TEGRA194_CLK_I2C1>;
+                        clock-names = "div-clk";
+                        resets = <&bpmp TEGRA194_RESET_I2C1>;
+                        reset-names = "i2c";
+                        status = "disabled";
+                };
+
+                uarth: serial@3170000 {
+                        compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
+                        reg = <0x03170000 0x40>;
+                        reg-shift = <2>;
+                        interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&bpmp TEGRA194_CLK_UARTH>;
+                        clock-names = "serial";
+                        resets = <&bpmp TEGRA194_RESET_UARTH>;
+                        reset-names = "serial";
+                        status = "disabled";
+                };
+
+                cam_i2c: i2c@3180000 {
+                        compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
+                        reg = <0x03180000 0x10000>;
+                        interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&bpmp TEGRA194_CLK_I2C3>;
+                        clock-names = "div-clk";
+                        resets = <&bpmp TEGRA194_RESET_I2C3>;
+                        reset-names = "i2c";
+                        status = "disabled";
+                };
+
+                /* shares pads with dpaux1 */
+                dp_aux_ch1_i2c: i2c@3190000 {
+                        compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
+                        reg = <0x03190000 0x10000>;
+                        interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&bpmp TEGRA194_CLK_I2C4>;
+                        clock-names = "div-clk";
+                        resets = <&bpmp TEGRA194_RESET_I2C4>;
+                        reset-names = "i2c";
+                        status = "disabled";
+                };
+
+                /* shares pads with dpaux0 */
+                dp_aux_ch0_i2c: i2c@31b0000 {
+                        compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
+                        reg = <0x031b0000 0x10000>;
+                        interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&bpmp TEGRA194_CLK_I2C6>;
+                        clock-names = "div-clk";
+                        resets = <&bpmp TEGRA194_RESET_I2C6>;
+                        reset-names = "i2c";
+                        status = "disabled";
+                };
+
+                gen7_i2c: i2c@31c0000 {
+                        compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
+                        reg = <0x031c0000 0x10000>;
+                        interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&bpmp TEGRA194_CLK_I2C7>;
+                        clock-names = "div-clk";
+                        resets = <&bpmp TEGRA194_RESET_I2C7>;
+                        reset-names = "i2c";
+                        status = "disabled";
+                };
+
+                gen9_i2c: i2c@31e0000 {
+                        compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
+                        reg = <0x031e0000 0x10000>;
+                        interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&bpmp TEGRA194_CLK_I2C9>;
+                        clock-names = "div-clk";
+                        resets = <&bpmp TEGRA194_RESET_I2C9>;
+                        reset-names = "i2c";
+                        status = "disabled";
+                };
+
+                sdmmc1: sdhci@3400000 {
+                        compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
+                        reg = <0x03400000 0x10000>;
+                        interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&bpmp TEGRA194_CLK_SDMMC1>;
+                        clock-names = "sdhci";
+                        resets = <&bpmp TEGRA194_RESET_SDMMC1>;
+                        reset-names = "sdhci";
+                        status = "disabled";
+                };
+
+                sdmmc3: sdhci@3440000 {
+                        compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
+                        reg = <0x03440000 0x10000>;
+                        interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&bpmp TEGRA194_CLK_SDMMC3>;
+                        clock-names = "sdhci";
+                        resets = <&bpmp TEGRA194_RESET_SDMMC3>;
+                        reset-names = "sdhci";
+                        status = "disabled";
+                };
+
+                sdmmc4: sdhci@3460000 {
+                        compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
+                        reg = <0x03460000 0x10000>;
+                        interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&bpmp TEGRA194_CLK_SDMMC4>;
+                        clock-names = "sdhci";
+                        resets = <&bpmp TEGRA194_RESET_SDMMC4>;
+                        reset-names = "sdhci";
+                        status = "disabled";
+                };
+
+                gic: interrupt-controller@3881000 {
+                        compatible = "arm,gic-400";
+                        #interrupt-cells = <3>;
+                        interrupt-controller;
+                        reg = <0x03881000 0x1000>,
+                              <0x03882000 0x2000>,
+                              <0x03884000 0x2000>,
+                              <0x03886000 0x2000>;
+                        interrupts = <GIC_PPI 9
+                                (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+                        interrupt-parent = <&gic>;
+                };
+
+                hsp_top0: hsp@3c00000 {
+                        compatible = "nvidia,tegra186-hsp";
+                        reg = <0x03c00000 0xa0000>;
+                        interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "doorbell";
+                        #mbox-cells = <2>;
+                };
+
+                gen2_i2c: i2c@c240000 {
+                        compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
+                        reg = <0x0c240000 0x10000>;
+                        interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&bpmp TEGRA194_CLK_I2C2>;
+                        clock-names = "div-clk";
+                        resets = <&bpmp TEGRA194_RESET_I2C2>;
+                        reset-names = "i2c";
+                        status = "disabled";
+                };
+
+                gen8_i2c: i2c@c250000 {
+                        compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
+                        reg = <0x0c250000 0x10000>;
+                        interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&bpmp TEGRA194_CLK_I2C8>;
+                        clock-names = "div-clk";
+                        resets = <&bpmp TEGRA194_RESET_I2C8>;
+                        reset-names = "i2c";
+                        status = "disabled";
+                };
+
+                uartc: serial@c280000 {
+                        compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
+                        reg = <0x0c280000 0x40>;
+                        reg-shift = <2>;
+                        interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&bpmp TEGRA194_CLK_UARTC>;
+                        clock-names = "serial";
+                        resets = <&bpmp TEGRA194_RESET_UARTC>;
+                        reset-names = "serial";
+                        status = "disabled";
+                };
+
+                uartg: serial@c290000 {
+                        compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
+                        reg = <0x0c290000 0x40>;
+                        reg-shift = <2>;
+                        interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&bpmp TEGRA194_CLK_UARTG>;
+                        clock-names = "serial";
+                        resets = <&bpmp TEGRA194_RESET_UARTG>;
+                        reset-names = "serial";
+                        status = "disabled";
+                };
+
+                pmc@c360000 {
+                        compatible = "nvidia,tegra194-pmc";
+                        reg = <0x0c360000 0x10000>,
+                              <0x0c370000 0x10000>,
+                              <0x0c380000 0x10000>,
+                              <0x0c390000 0x10000>,
+                              <0x0c3a0000 0x10000>;
+                        reg-names = "pmc", "wake", "aotag", "scratch", "misc";
+                };
+        };
+
+        sysram@40000000 {
+                compatible = "nvidia,tegra194-sysram", "mmio-sram";
+                reg = <0x0 0x40000000 0x0 0x50000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0x0 0x0 0x40000000 0x50000>;
+
+                cpu_bpmp_tx: shmem@4e000 {
+                        compatible = "nvidia,tegra194-bpmp-shmem";
+                        reg = <0x4e000 0x1000>;
+                        label = "cpu-bpmp-tx";
+                        pool;
+                };
+
+                cpu_bpmp_rx: shmem@4f000 {
+                        compatible = "nvidia,tegra194-bpmp-shmem";
+                        reg = <0x4f000 0x1000>;
+                        label = "cpu-bpmp-rx";
+                        pool;
+                };
+        };
+
+        bpmp: bpmp {
+                compatible = "nvidia,tegra186-bpmp";
+                mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
+                                    TEGRA_HSP_DB_MASTER_BPMP>;
+                shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
+                #clock-cells = <1>;
+                #reset-cells = <1>;
+                #power-domain-cells = <1>;
+
+                bpmp_i2c: i2c {
+                        compatible = "nvidia,tegra186-bpmp-i2c";
+                        nvidia,bpmp-bus-id = <5>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+
+                bpmp_thermal: thermal {
+                        compatible = "nvidia,tegra186-bpmp-thermal";
+                        #thermal-sensor-cells = <1>;
+                };
+        };
+
+        timer {
+                compatible = "arm,armv8-timer";
+                interrupts = <GIC_PPI 13
+                                (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 14
+                                (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 11
+                                (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 10
+                                (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+                interrupt-parent = <&gic>;
+        };
+};
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
index d67ef4319f3b..9d5a0e6b2ca4 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
@@ -1325,6 +1325,11 @@
                 status = "okay";
         };
 
+        sata@70020000 {
+                status = "okay";
+                phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
+        };
+
         padctl@7009f000 {
                 status = "okay";
 
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 9c2402108772..3be920efee82 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -798,6 +798,22 @@
                 #iommu-cells = <1>;
         };
 
+        sata@70020000 {
+                compatible = "nvidia,tegra210-ahci";
+                reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
+                      <0x0 0x70020000 0x0 0x7000>, /* SATA */
+                      <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */
+                interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA210_CLK_SATA>,
+                         <&tegra_car TEGRA210_CLK_SATA_OOB>;
+                clock-names = "sata", "sata-oob";
+                resets = <&tegra_car 124>,
+                         <&tegra_car 123>,
+                         <&tegra_car 129>;
+                reset-names = "sata", "sata-oob", "sata-cold";
+                status = "disabled";
+        };
+
         hda@70030000 {
                 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda";
                 reg = <0x0 0x70030000 0x0 0x10000>;
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
index 492a011f14f6..1c8f1b86472d 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
@@ -140,16 +140,16 @@
                 };
 
                 agnoc@0 {
-                        qcom,pcie@00600000 {
+                        qcom,pcie@600000 {
                                 perst-gpio = <&msmgpio 35 GPIO_ACTIVE_LOW>;
                         };
 
-                        qcom,pcie@00608000 {
+                        qcom,pcie@608000 {
                                 status = "okay";
                                 perst-gpio = <&msmgpio 130 GPIO_ACTIVE_LOW>;
                         };
 
-                        qcom,pcie@00610000 {
+                        qcom,pcie@610000 {
                                 status = "okay";
                                 perst-gpio = <&msmgpio 114 GPIO_ACTIVE_LOW>;
                         };
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index e51b04900726..66b318e1de80 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -15,6 +15,7 @@
 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
 #include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/thermal/thermal.h>
 
 / {
         model = "Qualcomm Technologies, Inc. MSM8916";
@@ -113,6 +114,9 @@
                         next-level-cache = <&L2_0>;
                         enable-method = "psci";
                         cpu-idle-states = <&CPU_SPC>;
+                        clocks = <&apcs 0>;
+                        operating-points-v2 = <&cpu_opp_table>;
+                        #cooling-cells = <2>;
                 };
 
                 CPU1: cpu@1 {
@@ -122,6 +126,9 @@
                         next-level-cache = <&L2_0>;
                         enable-method = "psci";
                         cpu-idle-states = <&CPU_SPC>;
+                        clocks = <&apcs 0>;
+                        operating-points-v2 = <&cpu_opp_table>;
+                        #cooling-cells = <2>;
                 };
 
                 CPU2: cpu@2 {
@@ -131,6 +138,9 @@
                         next-level-cache = <&L2_0>;
                         enable-method = "psci";
                         cpu-idle-states = <&CPU_SPC>;
+                        clocks = <&apcs 0>;
+                        operating-points-v2 = <&cpu_opp_table>;
+                        #cooling-cells = <2>;
                 };
 
                 CPU3: cpu@3 {
@@ -140,6 +150,9 @@
                         next-level-cache = <&L2_0>;
                         enable-method = "psci";
                         cpu-idle-states = <&CPU_SPC>;
+                        clocks = <&apcs 0>;
+                        operating-points-v2 = <&cpu_opp_table>;
+                        #cooling-cells = <2>;
                 };
 
                 L2_0: l2-cache {
@@ -188,6 +201,13 @@
                                         type = "critical";
                                 };
                         };
+
+                        cooling-maps {
+                                map0 {
+                                        trip = <&cpu_alert0>;
+                                        cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                                };
+                        };
                 };
 
                 cpu-thermal1 {
@@ -208,10 +228,35 @@
                                         type = "critical";
                                 };
                         };
+
+                        cooling-maps {
+                                map0 {
+                                        trip = <&cpu_alert1>;
+                                        cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                                };
+                        };
                 };
 
         };
 
+        cpu_opp_table: cpu_opp_table {
+                compatible = "operating-points-v2";
+                opp-shared;
+
+                opp-200000000 {
+                        opp-hz = /bits/ 64 <200000000>;
+                };
+                opp-400000000 {
+                        opp-hz = /bits/ 64 <400000000>;
+                };
+                opp-800000000 {
+                        opp-hz = /bits/ 64 <800000000>;
+                };
+                opp-998400000 {
+                        opp-hz = /bits/ 64 <998400000>;
+                };
+        };
+
         gpu_opp_table: opp_table {
                 compatible = "operating-points-v2";
 
@@ -326,9 +371,18 @@
                         status = "disabled";
                 };
 
-                apcs: syscon@b011000 {
-                        compatible = "syscon";
-                        reg = <0x0b011000 0x1000>;
+                a53pll: clock@b016000 {
+                        compatible = "qcom,msm8916-a53pll";
+                        reg = <0xb016000 0x40>;
+                        #clock-cells = <0>;
+                };
+
+                apcs: mailbox@b011000 {
+                        compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
+                        reg = <0xb011000 0x1000>;
+                        #mbox-cells = <1>;
+                        clocks = <&a53pll>;
+                        #clock-cells = <0>;
                 };
 
                 blsp1_uart2: serial@78b0000 {
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 4b2afcc4fdf4..410ae787ebb4 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -75,6 +75,17 @@
                         reg = <0x0 0x86200000 0x0 0x2600000>;
                         no-map;
                 };
+
+                rmtfs@86700000 {
+                        compatible = "qcom,rmtfs-mem";
+
+                        size = <0x0 0x200000>;
+                        alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
+                        no-map;
+
+                        qcom,client-id = <1>;
+                        qcom,vmid = <15>;
+                };
         };
 
         cpus {
@@ -232,10 +243,10 @@
 
         timer {
                 compatible = "arm,armv8-timer";
-                interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-                             <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-                             <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-                             <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+                interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+                             <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+                             <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+                             <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
         };
 
         clocks {
@@ -497,8 +508,8 @@
                 blsp2_spi5: spi@75ba000{
                         compatible = "qcom,spi-qup-v2.2.1";
                         reg = <0x075ba000 0x600>;
-                        interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>,
+                        interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
                                  <&gcc GCC_BLSP2_AHB_CLK>;
                         clock-names = "core", "iface";
                         pinctrl-names = "default", "sleep";
@@ -840,7 +851,7 @@
                         #size-cells = <1>;
                         ranges;
 
-                        pcie0: qcom,pcie@00600000 {
+                        pcie0: qcom,pcie@600000 {
                                 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
                                 status = "disabled";
                                 power-domains = <&gcc PCIE0_GDSC>;
@@ -893,7 +904,7 @@
 
                         };
 
-                        pcie1: qcom,pcie@00608000 {
+                        pcie1: qcom,pcie@608000 {
                                 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
                                 power-domains = <&gcc PCIE1_GDSC>;
                                 bus-range = <0x00 0xff>;
@@ -946,7 +957,7 @@
                                                 "bus_slave";
                         };
 
-                        pcie2: qcom,pcie@00610000 {
+                        pcie2: qcom,pcie@610000 {
                                 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
                                 power-domains = <&gcc PCIE2_GDSC>;
                                 bus-range = <0x00 0xff>;
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 2186d0193b73..5ede06000ea4 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -7,5 +7,7 @@ dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-h3ulcb-kf.dtb
 dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb
 dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb
 dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb
+dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb r8a77965-salvator-xs.dtb
 dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb
+dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb
 dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
index 26769a11a190..f9acd125d687 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
@@ -23,6 +23,7 @@
 
         /delete-node/ mmu@febe0000;
         /delete-node/ mmu@fe980000;
+        /delete-node/ mmu@fd950000;
         /delete-node/ mmu@fd960000;
         /delete-node/ mmu@fd970000;
 
@@ -80,7 +81,7 @@
 
         vspd3: vsp@fea38000 {
                 compatible = "renesas,vsp2";
-                reg = <0 0xfea38000 0 0x4000>;
+                reg = <0 0xfea38000 0 0x8000>;
                 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&cpg CPG_MOD 620>;
                 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index d12df6f2ff09..1d5e3ac0231c 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -41,6 +41,9 @@
                         power-domains = <&sysc R8A7795_PD_CA57_CPU0>;
                         next-level-cache = <&L2_CA57>;
                         enable-method = "psci";
+                        clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
+                        operating-points-v2 = <&cluster0_opp>;
+                        #cooling-cells = <2>;
                 };
 
                 a57_1: cpu@1 {
@@ -50,6 +53,9 @@
                         power-domains = <&sysc R8A7795_PD_CA57_CPU1>;
                         next-level-cache = <&L2_CA57>;
                         enable-method = "psci";
+                        clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
+                        operating-points-v2 = <&cluster0_opp>;
+                        #cooling-cells = <2>;
                 };
 
                 a57_2: cpu@2 {
@@ -59,6 +65,9 @@
                         power-domains = <&sysc R8A7795_PD_CA57_CPU2>;
                         next-level-cache = <&L2_CA57>;
                         enable-method = "psci";
+                        clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
+                        operating-points-v2 = <&cluster0_opp>;
+                        #cooling-cells = <2>;
                 };
 
                 a57_3: cpu@3 {
@@ -68,6 +77,9 @@
                         power-domains = <&sysc R8A7795_PD_CA57_CPU3>;
                         next-level-cache = <&L2_CA57>;
                         enable-method = "psci";
+                        clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
+                        operating-points-v2 = <&cluster0_opp>;
+                        #cooling-cells = <2>;
                 };
 
                 a53_0: cpu@100 {
@@ -77,6 +89,8 @@
                         power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
                         next-level-cache = <&L2_CA53>;
                         enable-method = "psci";
+                        clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
+                        operating-points-v2 = <&cluster1_opp>;
                 };
 
                 a53_1: cpu@101 {
@@ -86,6 +100,8 @@
                         power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
                         next-level-cache = <&L2_CA53>;
                         enable-method = "psci";
+                        clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
+                        operating-points-v2 = <&cluster1_opp>;
                 };
 
                 a53_2: cpu@102 {
@@ -95,6 +111,8 @@
                         power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
                         next-level-cache = <&L2_CA53>;
                         enable-method = "psci";
+                        clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
+                        operating-points-v2 = <&cluster1_opp>;
                 };
 
                 a53_3: cpu@103 {
@@ -104,6 +122,8 @@
                         power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
                         next-level-cache = <&L2_CA53>;
                         enable-method = "psci";
+                        clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
+                        operating-points-v2 = <&cluster1_opp>;
                 };
 
                 L2_CA57: cache-controller-0 {
@@ -165,11 +185,59 @@
                 clock-frequency = <0>;
         };
 
-        /* External SCIF clock - to be overridden by boards that provide it */
-        scif_clk: scif {
-                compatible = "fixed-clock";
-                #clock-cells = <0>;
-                clock-frequency = <0>;
+        cluster0_opp: opp_table0 {
+                compatible = "operating-points-v2";
+                opp-shared;
+
+                opp-500000000 {
+                        opp-hz = /bits/ 64 <500000000>;
+                        opp-microvolt = <830000>;
+                        clock-latency-ns = <300000>;
+                };
+                opp-1000000000 {
+                        opp-hz = /bits/ 64 <1000000000>;
+                        opp-microvolt = <830000>;
+                        clock-latency-ns = <300000>;
+                };
+                opp-1500000000 {
+                        opp-hz = /bits/ 64 <1500000000>;
+                        opp-microvolt = <830000>;
+                        clock-latency-ns = <300000>;
+                        opp-suspend;
+                };
+                opp-1600000000 {
+                        opp-hz = /bits/ 64 <1600000000>;
+                        opp-microvolt = <900000>;
+                        clock-latency-ns = <300000>;
+                        turbo-mode;
+                };
+                opp-1700000000 {
+                        opp-hz = /bits/ 64 <1700000000>;
+                        opp-microvolt = <960000>;
+                        clock-latency-ns = <300000>;
+                        turbo-mode;
+                };
+        };
+
+        cluster1_opp: opp_table1 {
+                compatible = "operating-points-v2";
+                opp-shared;
+
+                opp-800000000 {
+                        opp-hz = /bits/ 64 <800000000>;
+                        opp-microvolt = <820000>;
+                        clock-latency-ns = <300000>;
+                };
+                opp-1000000000 {
+                        opp-hz = /bits/ 64 <1000000000>;
+                        opp-microvolt = <820000>;
+                        clock-latency-ns = <300000>;
+                };
+                opp-1200000000 {
+                        opp-hz = /bits/ 64 <1200000000>;
+                        opp-microvolt = <820000>;
+                        clock-latency-ns = <300000>;
+                };
         };
 
         /* External PCIe clock - can be overridden by the board */
@@ -208,6 +276,13 @@
                 method = "smc";
         };
 
+        /* External SCIF clock - to be overridden by boards that provide it */
+        scif_clk: scif {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+
         soc: soc {
                 compatible = "simple-bus";
                 interrupt-parent = <&gic>;
@@ -470,6 +545,15 @@
                         status = "disabled";
                 };
 
+                ipmmu_pv1: mmu@fd950000 {
+                        compatible = "renesas,ipmmu-r8a7795";
+                        reg = <0 0xfd950000 0 0x1000>;
+                        renesas,ipmmu-main = <&ipmmu_mm 7>;
+                        power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+                        #iommu-cells = <1>;
+                        status = "disabled";
+                };
+
                 ipmmu_pv2: mmu@fd960000 {
                         compatible = "renesas,ipmmu-r8a7795";
                         reg = <0 0xfd960000 0 0x1000>;
@@ -798,7 +882,7 @@
                         clocks = <&cpg CPG_MOD 812>;
                         power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
                         resets = <&cpg 812>;
-                        phy-mode = "rgmii-txid";
+                        phy-mode = "rgmii";
                         iommus = <&ipmmu_ds0 16>;
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -992,8 +1076,9 @@
                                  <&cpg CPG_CORE R8A7795_CLK_S3D1>,
                                  <&scif_clk>;
                         clock-names = "fck", "brg_int", "scif_clk";
-                        dmas = <&dmac1 0x31>, <&dmac1 0x30>;
-                        dma-names = "tx", "rx";
+                        dmas = <&dmac1 0x31>, <&dmac1 0x30>,
+                               <&dmac2 0x31>, <&dmac2 0x30>;
+                        dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
                         resets = <&cpg 520>;
                         status = "disabled";
@@ -1009,8 +1094,9 @@
                                  <&cpg CPG_CORE R8A7795_CLK_S3D1>,
                                  <&scif_clk>;
                         clock-names = "fck", "brg_int", "scif_clk";
-                        dmas = <&dmac1 0x33>, <&dmac1 0x32>;
-                        dma-names = "tx", "rx";
+                        dmas = <&dmac1 0x33>, <&dmac1 0x32>,
+                               <&dmac2 0x33>, <&dmac2 0x32>;
+                        dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
                         resets = <&cpg 519>;
                         status = "disabled";
@@ -1026,8 +1112,9 @@
                                  <&cpg CPG_CORE R8A7795_CLK_S3D1>,
                                  <&scif_clk>;
                         clock-names = "fck", "brg_int", "scif_clk";
-                        dmas = <&dmac1 0x35>, <&dmac1 0x34>;
-                        dma-names = "tx", "rx";
+                        dmas = <&dmac1 0x35>, <&dmac1 0x34>,
+                               <&dmac2 0x35>, <&dmac2 0x34>;
+                        dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
                         resets = <&cpg 518>;
                         status = "disabled";
@@ -1138,8 +1225,9 @@
                                  <&cpg CPG_CORE R8A7795_CLK_S3D1>,
                                  <&scif_clk>;
                         clock-names = "fck", "brg_int", "scif_clk";
-                        dmas = <&dmac1 0x51>, <&dmac1 0x50>;
-                        dma-names = "tx", "rx";
+                        dmas = <&dmac1 0x51>, <&dmac1 0x50>,
+                               <&dmac2 0x51>, <&dmac2 0x50>;
+                        dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
                         resets = <&cpg 207>;
                         status = "disabled";
@@ -1154,8 +1242,9 @@
                                  <&cpg CPG_CORE R8A7795_CLK_S3D1>,
                                  <&scif_clk>;
                         clock-names = "fck", "brg_int", "scif_clk";
-                        dmas = <&dmac1 0x53>, <&dmac1 0x52>;
-                        dma-names = "tx", "rx";
+                        dmas = <&dmac1 0x53>, <&dmac1 0x52>,
+                               <&dmac2 0x53>, <&dmac2 0x52>;
+                        dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
                         resets = <&cpg 206>;
                         status = "disabled";
@@ -1170,8 +1259,9 @@
                                  <&cpg CPG_CORE R8A7795_CLK_S3D1>,
                                  <&scif_clk>;
                         clock-names = "fck", "brg_int", "scif_clk";
-                        dmas = <&dmac1 0x13>, <&dmac1 0x12>;
-                        dma-names = "tx", "rx";
+                        dmas = <&dmac1 0x13>, <&dmac1 0x12>,
+                               <&dmac2 0x13>, <&dmac2 0x12>;
+                        dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
                         resets = <&cpg 310>;
                         status = "disabled";
@@ -1218,8 +1308,9 @@
                                  <&cpg CPG_CORE R8A7795_CLK_S3D1>,
                                  <&scif_clk>;
                         clock-names = "fck", "brg_int", "scif_clk";
-                        dmas = <&dmac1 0x5b>, <&dmac1 0x5a>;
-                        dma-names = "tx", "rx";
+                        dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
+                               <&dmac2 0x5b>, <&dmac2 0x5a>;
+                        dma-names = "tx", "rx", "tx", "rx";
                         power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
                         resets = <&cpg 202>;
                         status = "disabled";
@@ -1251,8 +1342,9 @@
                         clocks = <&cpg CPG_MOD 931>;
                         power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
                         resets = <&cpg 931>;
-                        dmas = <&dmac1 0x91>, <&dmac1 0x90>;
-                        dma-names = "tx", "rx";
+                        dmas = <&dmac1 0x91>, <&dmac1 0x90>,
+                               <&dmac2 0x91>, <&dmac2 0x90>;
+                        dma-names = "tx", "rx", "tx", "rx";
                         i2c-scl-internal-delay-ns = <110>;
                         status = "disabled";
                 };
@@ -1267,8 +1359,9 @@
                         clocks = <&cpg CPG_MOD 930>;
                         power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
                         resets = <&cpg 930>;
-                        dmas = <&dmac1 0x93>, <&dmac1 0x92>;
-                        dma-names = "tx", "rx";
+                        dmas = <&dmac1 0x93>, <&dmac1 0x92>,
+                               <&dmac2 0x93>, <&dmac2 0x92>;
+                        dma-names = "tx", "rx", "tx", "rx";
                         i2c-scl-internal-delay-ns = <6>;
                         status = "disabled";
                 };
@@ -1283,8 +1376,9 @@
                         clocks = <&cpg CPG_MOD 929>;
                         power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
                         resets = <&cpg 929>;
-                        dmas = <&dmac1 0x95>, <&dmac1 0x94>;
-                        dma-names = "tx", "rx";
+                        dmas = <&dmac1 0x95>, <&dmac1 0x94>,
+                               <&dmac2 0x95>, <&dmac2 0x94>;
+                        dma-names = "tx", "rx", "tx", "rx";
                         i2c-scl-internal-delay-ns = <6>;
                         status = "disabled";
                 };
@@ -2143,7 +2237,7 @@
 
                 vspd0: vsp@fea20000 {
                         compatible = "renesas,vsp2";
-                        reg = <0 0xfea20000 0 0x4000>;
+                        reg = <0 0xfea20000 0 0x8000>;
                         interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&cpg CPG_MOD 623>;
                         power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -2163,7 +2257,7 @@
 
                 vspd1: vsp@fea28000 {
                         compatible = "renesas,vsp2";
-                        reg = <0 0xfea28000 0 0x4000>;
+                        reg = <0 0xfea28000 0 0x8000>;
                         interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&cpg CPG_MOD 622>;
                         power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -2183,7 +2277,7 @@
 
                 vspd2: vsp@fea30000 {
                         compatible = "renesas,vsp2";
-                        reg = <0 0xfea30000 0 0x4000>;
+                        reg = <0 0xfea30000 0 0x8000>;
                         interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&cpg CPG_MOD 621>;
                         power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -2320,9 +2414,9 @@
 
                 tsc: thermal@e6198000 {
                         compatible = "renesas,r8a7795-thermal";
-                        reg = <0 0xe6198000 0 0x68>,
-                              <0 0xe61a0000 0 0x5c>,
-                              <0 0xe61a8000 0 0x5c>;
+                        reg = <0 0xe6198000 0 0x100>,
+                              <0 0xe61a0000 0 0x100>,
+                              <0 0xe61a8000 0 0x100>;
                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
                                      <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
                                      <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
@@ -2357,12 +2451,24 @@
                         thermal-sensors = <&tsc 0>;
 
                         trips {
+                                sensor1_passive: sensor1-passive {
+                                        temperature = <95000>;
+                                        hysteresis = <2000>;
+                                        type = "passive";
+                                };
                                 sensor1_crit: sensor1-crit {
                                         temperature = <120000>;
                                         hysteresis = <2000>;
                                         type = "critical";
                                 };
                         };
+
+                        cooling-maps {
+                                map0 {
+                                        trip = <&sensor1_passive>;
+                                        cooling-device = <&a57_0 4 4>;
+                                };
+                        };
                 };
 
                 sensor_thermal2: sensor-thermal2 {
@@ -2371,12 +2477,24 @@
                         thermal-sensors = <&tsc 1>;
 
                         trips {
+                                sensor2_passive: sensor2-passive {
+                                        temperature = <95000>;
+                                        hysteresis = <2000>;
+                                        type = "passive";
+                                };
                                 sensor2_crit: sensor2-crit {
                                         temperature = <120000>;
                                         hysteresis = <2000>;
                                         type = "critical";
                                 };
                         };
+
+                        cooling-maps {
+                                map0 {
+                                        trip = <&sensor2_passive>;
+                                        cooling-device = <&a57_0 4 4>;
+                                };
+                        };
                 };
 
                 sensor_thermal3: sensor-thermal3 {
@@ -2385,12 +2503,24 @@
                         thermal-sensors = <&tsc 2>;
 
                         trips {
+                                sensor3_passive: sensor3-passive {
+                                        temperature = <95000>;
+                                        hysteresis = <2000>;
+                                        type = "passive";
+                                };
                                 sensor3_crit: sensor3-crit {
                                         temperature = <120000>;
                                         hysteresis = <2000>;
                                         type = "critical";
                                 };
                         };
+
+                        cooling-maps {
+                                map0 {
+                                        trip = <&sensor3_passive>;
+                                        cooling-device = <&a57_0 4 4>;
+                                };
+                        };
                 };
         };
 
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index c5192d513d7d..556eb8e45499 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -71,6 +71,9 @@
                         power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
                         next-level-cache = <&L2_CA57>;
                         enable-method = "psci";
+                        clocks =<&cpg CPG_CORE R8A7796_CLK_Z>;
+                        operating-points-v2 = <&cluster0_opp>;
+                        #cooling-cells = <2>;
                 };
 
                 a57_1: cpu@1 {
@@ -80,6 +83,9 @@
                         power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
                         next-level-cache = <&L2_CA57>;
                         enable-method = "psci";
+                        clocks =<&cpg CPG_CORE R8A7796_CLK_Z>;
+                        operating-points-v2 = <&cluster0_opp>;
+                        #cooling-cells = <2>;
                 };
 
                 a53_0: cpu@100 {
@@ -89,6 +95,8 @@
                         power-domains = <&sysc R8A7796_PD_CA53_CPU0>;
                         next-level-cache = <&L2_CA53>;
                         enable-method = "psci";
+                        clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
+                        operating-points-v2 = <&cluster1_opp>;
                 };
 
                 a53_1: cpu@101 {
@@ -98,6 +106,8 @@
                         power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
                         next-level-cache = <&L2_CA53>;
                         enable-method = "psci";
+                        clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
+                        operating-points-v2 = <&cluster1_opp>;
                 };
 
                 a53_2: cpu@102 {
@@ -107,6 +117,8 @@
                         power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
                         next-level-cache = <&L2_CA53>;
                         enable-method = "psci";
+                        clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
+                        operating-points-v2 = <&cluster1_opp>;
                 };
 
                 a53_3: cpu@103 {
@@ -116,6 +128,8 @@
                         power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
                         next-level-cache = <&L2_CA53>;
                         enable-method = "psci";
+                        clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
+                        operating-points-v2 = <&cluster1_opp>;
                 };
 
                 L2_CA57: cache-controller-0 {
@@ -147,6 +161,72 @@
                 clock-frequency = <0>;
         };
 
+        cluster0_opp: opp_table0 {
+                compatible = "operating-points-v2";
+                opp-shared;
+
+                opp-500000000 {
+                        opp-hz = /bits/ 64 <500000000>;
+                        opp-microvolt = <820000>;
+                        clock-latency-ns = <300000>;
+                };
+                opp-1000000000 {
+                        opp-hz = /bits/ 64 <1000000000>;
+                        opp-microvolt = <820000>;
+                        clock-latency-ns = <300000>;
+                };
+                opp-1500000000 {
+                        opp-hz = /bits/ 64 <1500000000>;
+                        opp-microvolt = <820000>;
+                        clock-latency-ns = <300000>;
+                };
+                opp-1600000000 {
+                        opp-hz = /bits/ 64 <1600000000>;
+                        opp-microvolt = <900000>;
+                        clock-latency-ns = <300000>;
+                        turbo-mode;
+                };
+                opp-1700000000 {
+                        opp-hz = /bits/ 64 <1700000000>;
+                        opp-microvolt = <900000>;
+                        clock-latency-ns = <300000>;
+                        turbo-mode;
+                };
+                opp-1800000000 {
+                        opp-hz = /bits/ 64 <1800000000>;
+                        opp-microvolt = <960000>;
+                        clock-latency-ns = <300000>;
+                        turbo-mode;
+                };
+        };
+
+        cluster1_opp: opp_table1 {
+                compatible = "operating-points-v2";
+                opp-shared;
+
+                opp-800000000 {
+                        opp-hz = /bits/ 64 <800000000>;
+                        opp-microvolt = <820000>;
+                        clock-latency-ns = <300000>;
+                };
+                opp-1000000000 {
+                        opp-hz = /bits/ 64 <1000000000>;
+                        opp-microvolt = <820000>;
+                        clock-latency-ns = <300000>;
+                };
+                opp-1200000000 {
+                        opp-hz = /bits/ 64 <1200000000>;
+                        opp-microvolt = <820000>;
+                        clock-latency-ns = <300000>;
+                };
+                opp-1300000000 {
+                        opp-hz = /bits/ 64 <1300000000>;
+                        opp-microvolt = <820000>;
+                        clock-latency-ns = <300000>;
+                        turbo-mode;
+                };
+        };
+
         /* External PCIe clock - can be overridden by the board */
         pcie_bus_clk: pcie_bus {
                 compatible = "fixed-clock";
@@ -894,7 +974,7 @@
                         clocks = <&cpg CPG_MOD 812>;
                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
                         resets = <&cpg 812>;
-                        phy-mode = "rgmii-txid";
+                        phy-mode = "rgmii";
                         iommus = <&ipmmu_ds0 16>;
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -1561,9 +1641,9 @@
 
                 tsc: thermal@e6198000 {
                         compatible = "renesas,r8a7796-thermal";
-                        reg = <0 0xe6198000 0 0x68>,
-                              <0 0xe61a0000 0 0x5c>,
-                              <0 0xe61a8000 0 0x5c>;
+                        reg = <0 0xe6198000 0 0x100>,
+                              <0 0xe61a0000 0 0x100>,
+                              <0 0xe61a8000 0 0x100>;
                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
                                      <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
                                      <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
@@ -1839,7 +1919,7 @@
 
                 vspd0: vsp@fea20000 {
                         compatible = "renesas,vsp2";
-                        reg = <0 0xfea20000 0 0x4000>;
+                        reg = <0 0xfea20000 0 0x8000>;
                         interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&cpg CPG_MOD 623>;
                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@@ -1859,7 +1939,7 @@
 
                 vspd1: vsp@fea28000 {
                         compatible = "renesas,vsp2";
-                        reg = <0 0xfea28000 0 0x4000>;
+                        reg = <0 0xfea28000 0 0x8000>;
                         interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&cpg CPG_MOD 622>;
                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@@ -1879,7 +1959,7 @@
 
                 vspd2: vsp@fea30000 {
                         compatible = "renesas,vsp2";
-                        reg = <0 0xfea30000 0 0x4000>;
+                        reg = <0 0xfea30000 0 0x8000>;
                         interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
                         clocks = <&cpg CPG_MOD 621>;
                         power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@@ -1998,12 +2078,24 @@
                         thermal-sensors = <&tsc 0>;
 
                         trips {
+                                sensor1_passive: sensor1-passive {
+                                        temperature = <95000>;
+                                        hysteresis = <2000>;
+                                        type = "passive";
+                                };
                                 sensor1_crit: sensor1-crit {
                                         temperature = <120000>;
                                         hysteresis = <2000>;
                                         type = "critical";
                                 };
                         };
+
+                        cooling-maps {
+                                map0 {
+                                        trip = <&sensor1_passive>;
+                                        cooling-device = <&a57_0 5 5>;
+                                };
+                        };
                 };
 
                 sensor_thermal2: sensor-thermal2 {
@@ -2012,12 +2104,24 @@
                         thermal-sensors = <&tsc 1>;
 
                         trips {
+                                sensor2_passive: sensor2-passive {
+                                        temperature = <95000>;
+                                        hysteresis = <2000>;
+                                        type = "passive";
+                                };
                                 sensor2_crit: sensor2-crit {
                                         temperature = <120000>;
                                         hysteresis = <2000>;
                                         type = "critical";
                                 };
                         };
+
+                        cooling-maps {
+                                map0 {
+                                        trip = <&sensor2_passive>;
+                                        cooling-device = <&a57_0 5 5>;
+                                };
+                        };
                 };
 
                 sensor_thermal3: sensor-thermal3 {
@@ -2026,12 +2130,24 @@
                         thermal-sensors = <&tsc 2>;
 
                         trips {
+                                sensor3_passive: sensor3-passive {
+                                        temperature = <95000>;
+                                        hysteresis = <2000>;
+                                        type = "passive";
+                                };
                                 sensor3_crit: sensor3-crit {
                                         temperature = <120000>;
                                         hysteresis = <2000>;
                                         type = "critical";
                                 };
                         };
+
+                        cooling-maps {
+                                map0 {
+                                        trip = <&sensor3_passive>;
+                                        cooling-device = <&a57_0 5 5>;
+                                };
+                        };
                 };
         };
 
diff --git a/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts
new file mode 100644
index 000000000000..75d890d91df9
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the Salvator-X board with R-Car M3-N
+ *
+ * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
+ */
+
+/dts-v1/;
+#include "r8a77965.dtsi"
+#include "salvator-x.dtsi"
+
+/ {
+        model = "Renesas Salvator-X board based on r8a77965";
+        compatible = "renesas,salvator-x", "renesas,r8a77965";
+
+        memory@48000000 {
+                device_type = "memory";
+                /* first 128MB is reserved for secure area. */
+                reg = <0x0 0x48000000 0x0 0x78000000>;
+        };
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
new file mode 100644
index 000000000000..a83a00deed9e
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the Salvator-X 2nd version board with R-Car M3-N
+ *
+ * Copyright (C) 2017 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a77965.dtsi"
+#include "salvator-xs.dtsi"
+
+/ {
+        model = "Renesas Salvator-X 2nd version board based on r8a77965";
+        compatible = "renesas,salvator-xs", "renesas,r8a77965";
+
+        memory@48000000 {
+                device_type = "memory";
+                /* first 128MB is reserved for secure area. */
+                reg = <0x0 0x48000000 0x0 0x78000000>;
+        };
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
new file mode 100644
index 000000000000..f0871fcdd984
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -0,0 +1,878 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the r8a77965 SoC
+ *
+ * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
+ *
+ * Based on r8a7796.dtsi
+ * Copyright (C) 2016 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#define CPG_AUDIO_CLK_I         10
+
+/ {
+        compatible = "renesas,r8a77965";
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        aliases {
+                i2c7 = &i2c_dvfs;
+        };
+
+        psci {
+                compatible = "arm,psci-1.0", "arm,psci-0.2";
+                method = "smc";
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                a57_0: cpu@0 {
+                        compatible = "arm,cortex-a57", "arm,armv8";
+                        reg = <0x0>;
+                        device_type = "cpu";
+                        power-domains = <&sysc 0>;
+                        next-level-cache = <&L2_CA57>;
+                        enable-method = "psci";
+                };
+
+                a57_1: cpu@1 {
+                        compatible = "arm,cortex-a57","arm,armv8";
+                        reg = <0x1>;
+                        device_type = "cpu";
+                        power-domains = <&sysc 1>;
+                        next-level-cache = <&L2_CA57>;
+                        enable-method = "psci";
+                };
+
+                L2_CA57: cache-controller-0 {
+                        compatible = "cache";
+                        power-domains = <&sysc 12>;
+                        cache-unified;
+                        cache-level = <2>;
+                };
+        };
+
+        extal_clk: extal {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                /* This value must be overridden by the board */
+                clock-frequency = <0>;
+        };
+
+        extalr_clk: extalr {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                /* This value must be overridden by the board */
+                clock-frequency = <0>;
+        };
+
+        /*
+         * The external audio clocks are configured as 0 Hz fixed frequency
+         * clocks by default.
+         * Boards that provide audio clocks should override them.
+         */
+        audio_clk_a: audio_clk_a {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+
+        audio_clk_b: audio_clk_b {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+
+        audio_clk_c: audio_clk_c {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+
+        /* External CAN clock - to be overridden by boards that provide it */
+        can_clk: can {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+
+        /* External SCIF clock - to be overridden by boards that provide it */
+        scif_clk: scif {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+
+        /* External PCIe clock - can be overridden by the board */
+        pcie_bus_clk: pcie_bus {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+
+        /* External USB clocks - can be overridden by the board */
+        usb3s0_clk: usb3s0 {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+
+        usb_extal_clk: usb_extal {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+
+        timer {
+                compatible = "arm,armv8-timer";
+                interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                                      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                                      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+                                      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+        };
+
+        pmu_a57 {
+                compatible = "arm,cortex-a57-pmu";
+                interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+                                      <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-affinity = <&a57_0>,
+                                     <&a57_1>;
+        };
+
+        soc {
+                compatible = "simple-bus";
+                interrupt-parent = <&gic>;
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
+
+                gic: interrupt-controller@f1010000 {
+                        compatible = "arm,gic-400";
+                        #interrupt-cells = <3>;
+                        #address-cells = <0>;
+                        interrupt-controller;
+                        reg = <0x0 0xf1010000 0 0x1000>,
+                              <0x0 0xf1020000 0 0x20000>,
+                              <0x0 0xf1040000 0 0x20000>,
+                              <0x0 0xf1060000 0 0x20000>;
+                        interrupts = <GIC_PPI 9
+                                        (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+                        clocks = <&cpg CPG_MOD 408>;
+                        clock-names = "clk";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 408>;
+                };
+
+                pfc: pin-controller@e6060000 {
+                        compatible = "renesas,pfc-r8a77965";
+                        reg = <0 0xe6060000 0 0x50c>;
+                };
+
+                cpg: clock-controller@e6150000 {
+                        compatible = "renesas,r8a77965-cpg-mssr";
+                        reg = <0 0xe6150000 0 0x1000>;
+                        clocks = <&extal_clk>, <&extalr_clk>;
+                        clock-names = "extal", "extalr";
+                        #clock-cells = <2>;
+                        #power-domain-cells = <0>;
+                        #reset-cells = <1>;
+                };
+
+                rst: reset-controller@e6160000 {
+                        compatible = "renesas,r8a77965-rst";
+                        reg = <0 0xe6160000 0 0x0200>;
+                };
+
+                prr: chipid@fff00044 {
+                        compatible = "renesas,prr";
+                        reg = <0 0xfff00044 0 4>;
+                };
+
+                sysc: system-controller@e6180000 {
+                        compatible = "renesas,r8a77965-sysc";
+                        reg = <0 0xe6180000 0 0x0400>;
+                        #power-domain-cells = <1>;
+                };
+
+                gpio0: gpio@e6050000 {
+                        compatible = "renesas,gpio-r8a77965",
+                                     "renesas,rcar-gen3-gpio";
+                        reg = <0 0xe6050000 0 0x50>;
+                        interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 0 16>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 912>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 912>;
+                };
+
+                gpio1: gpio@e6051000 {
+                        compatible = "renesas,gpio-r8a77965",
+                                     "renesas,rcar-gen3-gpio";
+                        reg = <0 0xe6051000 0 0x50>;
+                        interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 32 29>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 911>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 911>;
+                };
+
+                gpio2: gpio@e6052000 {
+                        compatible = "renesas,gpio-r8a77965",
+                                     "renesas,rcar-gen3-gpio";
+                        reg = <0 0xe6052000 0 0x50>;
+                        interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 64 15>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 910>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 910>;
+                };
+
+                gpio3: gpio@e6053000 {
+                        compatible = "renesas,gpio-r8a77965",
+                                     "renesas,rcar-gen3-gpio";
+                        reg = <0 0xe6053000 0 0x50>;
+                        interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 96 16>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 909>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 909>;
+                };
+
+                gpio4: gpio@e6054000 {
+                        compatible = "renesas,gpio-r8a77965",
+                                     "renesas,rcar-gen3-gpio";
+                        reg = <0 0xe6054000 0 0x50>;
+                        interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 128 18>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 908>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 908>;
+                };
+
+                gpio5: gpio@e6055000 {
+                        compatible = "renesas,gpio-r8a77965",
+                                     "renesas,rcar-gen3-gpio";
+                        reg = <0 0xe6055000 0 0x50>;
+                        interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 160 26>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 907>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 907>;
+                };
+
+                gpio6: gpio@e6055400 {
+                        compatible = "renesas,gpio-r8a77965",
+                                     "renesas,rcar-gen3-gpio";
+                        reg = <0 0xe6055400 0 0x50>;
+                        interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 192 32>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 906>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 906>;
+                };
+
+                gpio7: gpio@e6055800 {
+                        compatible = "renesas,gpio-r8a77965",
+                                     "renesas,rcar-gen3-gpio";
+                        reg = <0 0xe6055800 0 0x50>;
+                        interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 224 4>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 905>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 905>;
+                };
+
+                intc_ex: interrupt-controller@e61c0000 {
+                        compatible = "renesas,intc-ex-r8a77965", "renesas,irqc";
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        reg = <0 0xe61c0000 0 0x200>;
+                        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 407>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 407>;
+                };
+
+                dmac0: dma-controller@e6700000 {
+                        compatible = "renesas,dmac-r8a77965",
+                                     "renesas,rcar-dmac";
+                        reg = <0 0xe6700000 0 0x10000>;
+                        interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "error",
+                                        "ch0", "ch1", "ch2", "ch3",
+                                        "ch4", "ch5", "ch6", "ch7",
+                                        "ch8", "ch9", "ch10", "ch11",
+                                        "ch12", "ch13", "ch14", "ch15";
+                        clocks = <&cpg CPG_MOD 219>;
+                        clock-names = "fck";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 219>;
+                        #dma-cells = <1>;
+                        dma-channels = <16>;
+                };
+
+                dmac1: dma-controller@e7300000 {
+                        compatible = "renesas,dmac-r8a77965",
+                                     "renesas,rcar-dmac";
+                        reg = <0 0xe7300000 0 0x10000>;
+                        interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "error",
+                                        "ch0", "ch1", "ch2", "ch3",
+                                        "ch4", "ch5", "ch6", "ch7",
+                                        "ch8", "ch9", "ch10", "ch11",
+                                        "ch12", "ch13", "ch14", "ch15";
+                        clocks = <&cpg CPG_MOD 218>;
+                        clock-names = "fck";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 218>;
+                        #dma-cells = <1>;
+                        dma-channels = <16>;
+                };
+
+                dmac2: dma-controller@e7310000 {
+                        compatible = "renesas,dmac-r8a77965",
+                                     "renesas,rcar-dmac";
+                        reg = <0 0xe7310000 0 0x10000>;
+                        interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "error",
+                                        "ch0", "ch1", "ch2", "ch3",
+                                        "ch4", "ch5", "ch6", "ch7",
+                                        "ch8", "ch9", "ch10", "ch11",
+                                        "ch12", "ch13", "ch14", "ch15";
+                        clocks = <&cpg CPG_MOD 217>;
+                        clock-names = "fck";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 217>;
+                        #dma-cells = <1>;
+                        dma-channels = <16>;
+                };
+
+                scif0: serial@e6e60000 {
+                        compatible = "renesas,scif-r8a77965",
+                                     "renesas,rcar-gen3-scif", "renesas,scif";
+                        reg = <0 0xe6e60000 0 64>;
+                        interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 207>,
+                                 <&cpg CPG_CORE 20>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac1 0x51>, <&dmac1 0x50>,
+                               <&dmac2 0x51>, <&dmac2 0x50>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 207>;
+                        status = "disabled";
+                };
+
+                scif1: serial@e6e68000 {
+                        compatible = "renesas,scif-r8a77965",
+                                     "renesas,rcar-gen3-scif", "renesas,scif";
+                        reg = <0 0xe6e68000 0 64>;
+                        interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 206>,
+                                 <&cpg CPG_CORE 20>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac1 0x53>, <&dmac1 0x52>,
+                               <&dmac2 0x53>, <&dmac2 0x52>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 206>;
+                        status = "disabled";
+                };
+
+                scif2: serial@e6e88000 {
+                        compatible = "renesas,scif-r8a77965",
+                                     "renesas,rcar-gen3-scif", "renesas,scif";
+                        reg = <0 0xe6e88000 0 64>;
+                        interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 310>,
+                                 <&cpg CPG_CORE 20>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 310>;
+                        status = "disabled";
+                };
+
+                scif3: serial@e6c50000 {
+                        compatible = "renesas,scif-r8a77965",
+                                     "renesas,rcar-gen3-scif", "renesas,scif";
+                        reg = <0 0xe6c50000 0 64>;
+                        interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 204>,
+                                 <&cpg CPG_CORE 20>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0x57>, <&dmac0 0x56>;
+                        dma-names = "tx", "rx";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 204>;
+                        status = "disabled";
+                };
+
+                scif4: serial@e6c40000 {
+                        compatible = "renesas,scif-r8a77965",
+                                     "renesas,rcar-gen3-scif", "renesas,scif";
+                        reg = <0 0xe6c40000 0 64>;
+                        interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 203>,
+                                 <&cpg CPG_CORE 20>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0x59>, <&dmac0 0x58>;
+                        dma-names = "tx", "rx";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 203>;
+                        status = "disabled";
+                };
+
+                scif5: serial@e6f30000 {
+                        compatible = "renesas,scif-r8a77965",
+                                     "renesas,rcar-gen3-scif", "renesas,scif";
+                        reg = <0 0xe6f30000 0 64>;
+                        interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 202>,
+                                 <&cpg CPG_CORE 20>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
+                               <&dmac2 0x5b>, <&dmac2 0x5a>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 202>;
+                        status = "disabled";
+                };
+
+                avb: ethernet@e6800000 {
+                        compatible = "renesas,etheravb-r8a77965",
+                                     "renesas,etheravb-rcar-gen3";
+                        reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
+                        interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "ch0", "ch1", "ch2", "ch3",
+                                          "ch4", "ch5", "ch6", "ch7",
+                                          "ch8", "ch9", "ch10", "ch11",
+                                          "ch12", "ch13", "ch14", "ch15",
+                                          "ch16", "ch17", "ch18", "ch19",
+                                          "ch20", "ch21", "ch22", "ch23",
+                                          "ch24";
+                        clocks = <&cpg CPG_MOD 812>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 812>;
+                        phy-mode = "rgmii";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                csi20: csi2@fea80000 {
+                        reg = <0 0xfea80000 0 0x10000>;
+                        /* placeholder */
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+                };
+
+                csi40: csi2@feaa0000 {
+                        reg = <0 0xfeaa0000 0 0x10000>;
+                        /* placeholder */
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+                };
+
+                vin0: video@e6ef0000 {
+                        reg = <0 0xe6ef0000 0 0x1000>;
+                        /* placeholder */
+                };
+
+                vin1: video@e6ef1000 {
+                        reg = <0 0xe6ef1000 0 0x1000>;
+                        /* placeholder */
+                };
+
+                vin2: video@e6ef2000 {
+                        reg = <0 0xe6ef2000 0 0x1000>;
+                        /* placeholder */
+                };
+
+                vin3: video@e6ef3000 {
+                        reg = <0 0xe6ef3000 0 0x1000>;
+                        /* placeholder */
+                };
+
+                vin4: video@e6ef4000 {
+                        reg = <0 0xe6ef4000 0 0x1000>;
+                        /* placeholder */
+                };
+
+                vin5: video@e6ef5000 {
+                        reg = <0 0xe6ef5000 0 0x1000>;
+                        /* placeholder */
+                };
+
+                vin6: video@e6ef6000 {
+                        reg = <0 0xe6ef6000 0 0x1000>;
+                        /* placeholder */
+                };
+
+                vin7: video@e6ef7000 {
+                        reg = <0 0xe6ef7000 0 0x1000>;
+                        /* placeholder */
+                };
+
+                ohci0: usb@ee080000 {
+                        reg = <0 0xee080000 0 0x100>;
+                        /* placeholder */
+                };
+
+                ehci0: usb@ee080100 {
+                        reg = <0 0xee080100 0 0x100>;
+                        /* placeholder */
+                };
+
+                usb2_phy0: usb-phy@ee080200 {
+                        reg = <0 0xee080200 0 0x700>;
+                        /* placeholder */
+                };
+
+                usb2_phy1: usb-phy@ee0a0200 {
+                        reg = <0 0xee0a0200 0 0x700>;
+                        /* placeholder */
+                };
+
+                ohci1: usb@ee0a0000 {
+                        reg = <0 0xee0a0000 0 0x100>;
+                        /* placeholder */
+                };
+
+                ehci1: usb@ee0a0100 {
+                        reg = <0 0xee0a0100 0 0x100>;
+                        /* placeholder */
+                };
+
+                i2c0: i2c@e6500000 {
+                        reg = <0 0xe6500000 0 0x40>;
+                        /* placeholder */
+                };
+
+                i2c1: i2c@e6508000 {
+                        reg = <0 0xe6508000 0 0x40>;
+                        /* placeholder */
+                };
+
+                i2c2: i2c@e6510000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        reg = <0 0xe6510000 0 0x40>;
+                        /* placeholder */
+                };
+
+                i2c3: i2c@e66d0000 {
+                        reg = <0 0xe66d0000 0 0x40>;
+                        /* placeholder */
+                };
+
+                i2c4: i2c@e66d8000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        reg = <0 0xe66d8000 0 0x40>;
+                        /* placeholder */
+                };
+
+                i2c5: i2c@e66e0000 {
+                        reg = <0 0xe66e0000 0 0x40>;
+                        /* placeholder */
+                };
+
+                i2c6: i2c@e66e8000 {
+                        reg = <0 0xe66e8000 0 0x40>;
+                        /* placeholder */
+                };
+
+                i2c_dvfs: i2c@e60b0000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,iic-r8a77965",
+                                     "renesas,rcar-gen3-iic",
+                                     "renesas,rmobile-iic";
+                        reg = <0 0xe60b0000 0 0x425>;
+                        interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 926>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 926>;
+                        dmas = <&dmac0 0x11>, <&dmac0 0x10>;
+                        dma-names = "tx", "rx";
+                        status = "disabled";
+                };
+
+                pwm0: pwm@e6e30000 {
+                        reg = <0 0xe6e30000 0 8>;
+                        /* placeholder */
+                };
+
+                pwm1: pwm@e6e31000 {
+                        reg = <0 0xe6e31000 0 8>;
+                        #pwm-cells = <2>;
+                        /* placeholder */
+                };
+
+                pwm2: pwm@e6e32000 {
+                        reg = <0 0xe6e32000 0 8>;
+                        /* placeholder */
+                };
+
+                pwm3: pwm@e6e33000 {
+                        reg = <0 0xe6e33000 0 8>;
+                        /* placeholder */
+                };
+
+                pwm4: pwm@e6e34000 {
+                        reg = <0 0xe6e34000 0 8>;
+                        /* placeholder */
+                };
+
+                pwm5: pwm@e6e35000 {
+                        reg = <0 0xe6e35000 0 8>;
+                        /* placeholder */
+                };
+
+                pwm6: pwm@e6e36000 {
+                        reg = <0 0xe6e36000 0 8>;
+                        /* placeholder */
+                };
+
+                du: display@feb00000 {
+                        reg = <0 0xfeb00000 0 0x80000>,
+                              <0 0xfeb90000 0 0x14>;
+                        /* placeholder */
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@0 {
+                                        reg = <0>;
+                                        du_out_rgb: endpoint {
+                                        };
+                                };
+                                port@1 {
+                                        reg = <1>;
+                                        du_out_hdmi0: endpoint {
+                                        };
+                                };
+                                port@2 {
+                                        reg = <2>;
+                                        du_out_lvds0: endpoint {
+                                        };
+                                };
+                        };
+                };
+
+                hsusb: usb@e6590000 {
+                        reg = <0 0xe6590000 0 0x100>;
+                        /* placeholder */
+                };
+
+                pciec0: pcie@fe000000 {
+                        reg = <0 0xfe000000 0 0x80000>;
+                        /* placeholder */
+                };
+
+                pciec1: pcie@ee800000 {
+                        reg = <0 0xee800000 0 0x80000>;
+                        /* placeholder */
+                };
+
+                rcar_sound: sound@ec500000 {
+                        reg =   <0 0xec500000 0 0x1000>, /* SCU */
+                                <0 0xec5a0000 0 0x100>,  /* ADG */
+                                <0 0xec540000 0 0x1000>, /* SSIU */
+                                <0 0xec541000 0 0x280>,  /* SSI */
+                                <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
+                        /* placeholder */
+
+                        rcar_sound,dvc {
+                                dvc0: dvc-0 {
+                                };
+                                dvc1: dvc-1 {
+                                };
+                        };
+
+                        rcar_sound,src {
+                                src0: src-0 {
+                                };
+                                src1: src-1 {
+                                };
+                        };
+
+                        rcar_sound,ssi {
+                                ssi0: ssi-0 {
+                                };
+                                ssi1: ssi-1 {
+                                };
+                        };
+                };
+
+                sdhi0: sd@ee100000 {
+                        reg = <0 0xee100000 0 0x2000>;
+                        /* placeholder */
+                };
+
+                sdhi1: sd@ee120000 {
+                        reg = <0 0xee120000 0 0x2000>;
+                        /* placeholder */
+                };
+
+                sdhi2: sd@ee140000 {
+                        reg = <0 0xee140000 0 0x2000>;
+                        /* placeholder */
+                };
+
+                sdhi3: sd@ee160000 {
+                        reg = <0 0xee160000 0 0x2000>;
+                        /* placeholder */
+                };
+
+                usb3_phy0: usb-phy@e65ee000 {
+                        reg = <0 0xe65ee000 0 0x90>;
+                        #phy-cells = <0>;
+                        /* placeholder */
+                };
+
+                usb3_peri0: usb@ee020000 {
+                        reg = <0 0xee020000 0 0x400>;
+                        /* placeholder */
+                };
+
+                xhci0: usb@ee000000 {
+                        reg = <0 0xee000000 0 0xc00>;
+                        /* placeholder */
+                };
+
+                wdt0: watchdog@e6020000 {
+                        reg = <0 0xe6020000 0 0x0c>;
+                        /* placeholder */
+                };
+        };
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
index 8fe5c193e049..3c5f598c9766 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
@@ -36,11 +36,14 @@
 &avb {
         renesas,no-ether-link;
         phy-handle = <&phy0>;
+        phy-mode = "rgmii-id";
         status = "okay";
 
         phy0: ethernet-phy@0 {
                 rxc-skew-ps = <1500>;
                 reg = <0>;
+                interrupt-parent = <&gpio1>;
+                interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
         };
 };
 
@@ -52,11 +55,41 @@
         clock-frequency = <32768>;
 };
 
+&i2c0 {
+        pinctrl-0 = <&i2c0_pins>;
+        pinctrl-names = "default";
+
+        status = "okay";
+        clock-frequency = <400000>;
+
+        io_expander: gpio@20 {
+                compatible = "onnn,pca9654";
+                reg = <0x20>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+};
+
+&pfc {
+        i2c0_pins: i2c0 {
+                groups = "i2c0";
+                function = "i2c0";
+        };
+
+        scif0_pins: scif0 {
+                groups = "scif0_data";
+                function = "scif0";
+        };
+};
+
 &rwdt {
         timeout-sec = <60>;
         status = "okay";
 };
 
 &scif0 {
+        pinctrl-0 = <&scif0_pins>;
+        pinctrl-names = "default";
+
         status = "okay";
 };
diff --git a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
index 8624ca87d6b2..a8ceeac77992 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
@@ -34,6 +34,7 @@
 &avb {
         renesas,no-ether-link;
         phy-handle = <&phy0>;
+        phy-mode = "rgmii-id";
         status = "okay";
 
         phy0: ethernet-phy@0 {
@@ -50,6 +51,16 @@
         clock-frequency = <32768>;
 };
 
+&pfc {
+        scif0_pins: scif0 {
+                groups = "scif0_data";
+                function = "scif0";
+        };
+};
+
 &scif0 {
+        pinctrl-0 = <&scif0_pins>;
+        pinctrl-names = "default";
+
         status = "okay";
 };
diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
index c35a117fc447..c6db8ea43906 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -19,9 +19,12 @@
         #address-cells = <2>;
         #size-cells = <2>;
 
-        psci {
-                compatible = "arm,psci-1.0", "arm,psci-0.2";
-                method = "smc";
+        aliases {
+                i2c0 = &i2c0;
+                i2c1 = &i2c1;
+                i2c2 = &i2c2;
+                i2c3 = &i2c3;
+                i2c4 = &i2c4;
         };
 
         cpus {
@@ -60,6 +63,11 @@
                 clock-frequency = <0>;
         };
 
+        psci {
+                compatible = "arm,psci-1.0", "arm,psci-0.2";
+                method = "smc";
+        };
+
         /* External SCIF clock - to be overridden by boards that provide it */
         scif_clk: scif {
                 compatible = "fixed-clock";
@@ -92,18 +100,6 @@
                         resets = <&cpg 408>;
                 };
 
-                timer {
-                        compatible = "arm,armv8-timer";
-                        interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
-                                                  IRQ_TYPE_LEVEL_LOW)>,
-                                     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
-                                                  IRQ_TYPE_LEVEL_LOW)>,
-                                     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
-                                                  IRQ_TYPE_LEVEL_LOW)>,
-                                     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
-                                                  IRQ_TYPE_LEVEL_LOW)>;
-                };
-
                 rwdt: watchdog@e6020000 {
                         compatible = "renesas,r8a77970-wdt",
                                      "renesas,rcar-gen3-wdt";
@@ -178,6 +174,101 @@
                         #iommu-cells = <1>;
                 };
 
+                pfc: pin-controller@e6060000 {
+                        compatible = "renesas,pfc-r8a77970";
+                        reg = <0 0xe6060000 0 0x504>;
+                };
+
+                gpio0: gpio@e6050000 {
+                        compatible = "renesas,gpio-r8a77970",
+                                     "renesas,rcar-gen3-gpio";
+                        reg = <0 0xe6050000 0 0x50>;
+                        interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 0 22>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 912>;
+                        power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+                        resets = <&cpg 912>;
+                };
+
+                gpio1: gpio@e6051000 {
+                        compatible = "renesas,gpio-r8a77970",
+                                     "renesas,rcar-gen3-gpio";
+                        reg = <0 0xe6051000 0 0x50>;
+                        interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 32 28>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 911>;
+                        power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+                        resets = <&cpg 911>;
+                };
+
+                gpio2: gpio@e6052000 {
+                        compatible = "renesas,gpio-r8a77970",
+                                     "renesas,rcar-gen3-gpio";
+                        reg = <0 0xe6052000 0 0x50>;
+                        interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 64 17>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 910>;
+                        power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+                        resets = <&cpg 910>;
+                };
+
+                gpio3: gpio@e6053000 {
+                        compatible = "renesas,gpio-r8a77970",
+                                     "renesas,rcar-gen3-gpio";
+                        reg = <0 0xe6053000 0 0x50>;
+                        interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 96 17>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 909>;
+                        power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+                        resets = <&cpg 909>;
+                };
+
+                gpio4: gpio@e6054000 {
+                        compatible = "renesas,gpio-r8a77970",
+                                     "renesas,rcar-gen3-gpio";
+                        reg = <0 0xe6054000 0 0x50>;
+                        interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 128 6>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 908>;
+                        power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+                        resets = <&cpg 908>;
+                };
+
+                gpio5: gpio@e6055000 {
+                        compatible = "renesas,gpio-r8a77970",
+                                     "renesas,rcar-gen3-gpio";
+                        reg = <0 0xe6055000 0 0x50>;
+                        interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pfc 0 160 15>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        clocks = <&cpg CPG_MOD 907>;
+                        power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+                        resets = <&cpg 907>;
+                };
+
                 intc_ex: interrupt-controller@e61c0000 {
                         compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
                         #interrupt-cells = <2>;
@@ -255,6 +346,91 @@
                                <&ipmmu_ds1 22>, <&ipmmu_ds1 23>;
                 };
 
+                i2c0: i2c@e6500000 {
+                        compatible = "renesas,i2c-r8a77970",
+                                     "renesas,rcar-gen3-i2c";
+                        reg = <0 0xe6500000 0 0x40>;
+                        interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 931>;
+                        power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+                        resets = <&cpg 931>;
+                        dmas = <&dmac1 0x91>, <&dmac1 0x90>,
+                               <&dmac2 0x91>, <&dmac2 0x90>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        i2c-scl-internal-delay-ns = <6>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                i2c1: i2c@e6508000 {
+                        compatible = "renesas,i2c-r8a77970",
+                                     "renesas,rcar-gen3-i2c";
+                        reg = <0 0xe6508000 0 0x40>;
+                        interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 930>;
+                        power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+                        resets = <&cpg 930>;
+                        dmas = <&dmac1 0x93>, <&dmac1 0x92>,
+                               <&dmac2 0x93>, <&dmac2 0x92>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        i2c-scl-internal-delay-ns = <6>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                i2c2: i2c@e6510000 {
+                        compatible = "renesas,i2c-r8a77970",
+                                     "renesas,rcar-gen3-i2c";
+                        reg = <0 0xe6510000 0 0x40>;
+                        interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 929>;
+                        power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+                        resets = <&cpg 929>;
+                        dmas = <&dmac1 0x95>, <&dmac1 0x94>,
+                               <&dmac2 0x95>, <&dmac2 0x94>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        i2c-scl-internal-delay-ns = <6>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                i2c3: i2c@e66d0000 {
+                        compatible = "renesas,i2c-r8a77970",
+                                     "renesas,rcar-gen3-i2c";
+                        reg = <0 0xe66d0000 0 0x40>;
+                        interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 928>;
+                        power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+                        resets = <&cpg 928>;
+                        dmas = <&dmac1 0x97>, <&dmac1 0x96>,
+                               <&dmac2 0x97>, <&dmac2 0x96>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        i2c-scl-internal-delay-ns = <6>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                i2c4: i2c@e66d8000 {
+                        compatible = "renesas,i2c-r8a77970",
+                                     "renesas,rcar-gen3-i2c";
+                        reg = <0 0xe66d8000 0 0x40>;
+                        interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 927>;
+                        power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+                        resets = <&cpg 927>;
+                        dmas = <&dmac1 0x99>, <&dmac1 0x98>,
+                               <&dmac2 0x99>, <&dmac2 0x98>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        i2c-scl-internal-delay-ns = <6>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
                 hscif0: serial@e6540000 {
                         compatible = "renesas,hscif-r8a77970",
                                      "renesas,rcar-gen3-hscif",
@@ -400,7 +576,7 @@
                 avb: ethernet@e6800000 {
                         compatible = "renesas,etheravb-r8a77970",
                                      "renesas,etheravb-rcar-gen3";
-                        reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
+                        reg = <0 0xe6800000 0 0x800>;
                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
                                      <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
@@ -436,10 +612,18 @@
                         clocks = <&cpg CPG_MOD 812>;
                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
                         resets = <&cpg 812>;
-                        phy-mode = "rgmii-id";
+                        phy-mode = "rgmii";
                         iommus = <&ipmmu_rt 3>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                 };
         };
+
+        timer {
+                compatible = "arm,armv8-timer";
+                interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+                                      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+                                      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+                                      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+        };
 };
diff --git a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
new file mode 100644
index 000000000000..06cf6845765a
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the Condor board
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
+ */
+
+/dts-v1/;
+#include "r8a77980.dtsi"
+
+/ {
+        model = "Renesas Condor board based on r8a77980";
+        compatible = "renesas,condor", "renesas,r8a77980";
+
+        aliases {
+                serial0 = &scif0;
+                ethernet0 = &avb;
+        };
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+
+        memory@48000000 {
+                device_type = "memory";
+                /* first 128MB is reserved for secure area. */
+                reg = <0 0x48000000 0 0x78000000>;
+        };
+};
+
+&avb {
+        phy-mode = "rgmii-id";
+        phy-handle = <&phy0>;
+        renesas,no-ether-link;
+        status = "okay";
+
+        phy0: ethernet-phy@0 {
+                rxc-skew-ps = <1500>;
+                reg = <0>;
+        };
+};
+
+&extal_clk {
+        clock-frequency = <16666666>;
+};
+
+&extalr_clk {
+        clock-frequency = <32768>;
+};
+
+&scif0 {
+        status = "okay";
+};
+
+&scif_clk {
+        clock-frequency = <14745600>;
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
new file mode 100644
index 000000000000..03845fd74996
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -0,0 +1,385 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the r8a77980 SoC
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/ {
+        compatible = "renesas,r8a77980";
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                a53_0: cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a53", "arm,armv8";
+                        reg = <0>;
+                        clocks = <&cpg CPG_CORE 0>;
+                        power-domains = <&sysc 5>;
+                        next-level-cache = <&L2_CA53>;
+                        enable-method = "psci";
+                };
+
+                L2_CA53: cache-controller {
+                        compatible = "cache";
+                        power-domains = <&sysc 21>;
+                        cache-unified;
+                        cache-level = <2>;
+                };
+        };
+
+        extal_clk: extal {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                /* This value must be overridden by the board */
+                clock-frequency = <0>;
+        };
+
+        extalr_clk: extalr {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                /* This value must be overridden by the board */
+                clock-frequency = <0>;
+        };
+
+        psci {
+                compatible = "arm,psci-1.0", "arm,psci-0.2";
+                method = "smc";
+        };
+
+        /* External SCIF clock - to be overridden by boards that provide it */
+        scif_clk: scif {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+
+        soc {
+                compatible = "simple-bus";
+                interrupt-parent = <&gic>;
+
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
+
+                cpg: clock-controller@e6150000 {
+                        compatible = "renesas,r8a77980-cpg-mssr";
+                        reg = <0 0xe6150000 0 0x1000>;
+                        clocks = <&extal_clk>, <&extalr_clk>;
+                        clock-names = "extal", "extalr";
+                        #clock-cells = <2>;
+                        #power-domain-cells = <0>;
+                        #reset-cells = <1>;
+                };
+
+                rst: reset-controller@e6160000 {
+                        compatible = "renesas,r8a77980-rst";
+                        reg = <0 0xe6160000 0 0x200>;
+                };
+
+                sysc: system-controller@e6180000 {
+                        compatible = "renesas,r8a77980-sysc";
+                        reg = <0 0xe6180000 0 0x440>;
+                        #power-domain-cells = <1>;
+                };
+
+                hscif0: serial@e6540000 {
+                        compatible = "renesas,hscif-r8a77980",
+                                     "renesas,rcar-gen3-hscif",
+                                     "renesas,hscif";
+                        reg = <0 0xe6540000 0 0x60>;
+                        interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 520>,
+                                 <&cpg CPG_CORE 19>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac1 0x31>, <&dmac1 0x30>,
+                               <&dmac2 0x31>, <&dmac2 0x30>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 520>;
+                        status = "disabled";
+                };
+
+                hscif1: serial@e6550000 {
+                        compatible = "renesas,hscif-r8a77980",
+                                     "renesas,rcar-gen3-hscif",
+                                     "renesas,hscif";
+                        reg = <0 0xe6550000 0 0x60>;
+                        interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 519>,
+                                 <&cpg CPG_CORE 19>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac1 0x33>, <&dmac1 0x32>,
+                               <&dmac2 0x33>, <&dmac2 0x32>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 519>;
+                        status = "disabled";
+                };
+
+                hscif2: serial@e6560000 {
+                        compatible = "renesas,hscif-r8a77980",
+                                     "renesas,rcar-gen3-hscif",
+                                     "renesas,hscif";
+                        reg = <0 0xe6560000 0 0x60>;
+                        interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 518>,
+                                 <&cpg CPG_CORE 19>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac1 0x35>, <&dmac1 0x34>,
+                               <&dmac2 0x35>, <&dmac2 0x34>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 518>;
+                        status = "disabled";
+                };
+
+                hscif3: serial@e66a0000 {
+                        compatible = "renesas,hscif-r8a77980",
+                                     "renesas,rcar-gen3-hscif",
+                                     "renesas,hscif";
+                        reg = <0 0xe66a0000 0 0x60>;
+                        interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 517>,
+                                 <&cpg CPG_CORE 19>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac1 0x37>, <&dmac1 0x36>,
+                               <&dmac2 0x37>, <&dmac2 0x36>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 517>;
+                        status = "disabled";
+                };
+
+                avb: ethernet@e6800000 {
+                        compatible = "renesas,etheravb-r8a77980",
+                                     "renesas,etheravb-rcar-gen3";
+                        reg = <0 0xe6800000 0 0x800>;
+                        interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "ch0", "ch1", "ch2", "ch3",
+                                          "ch4", "ch5", "ch6", "ch7",
+                                          "ch8", "ch9", "ch10", "ch11",
+                                          "ch12", "ch13", "ch14", "ch15",
+                                          "ch16", "ch17", "ch18", "ch19",
+                                          "ch20", "ch21", "ch22", "ch23",
+                                          "ch24";
+                        clocks = <&cpg CPG_MOD 812>;
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 812>;
+                        phy-mode = "rgmii";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+
+                scif0: serial@e6e60000 {
+                        compatible = "renesas,scif-r8a77980",
+                                     "renesas,rcar-gen3-scif",
+                                     "renesas,scif";
+                        reg = <0 0xe6e60000 0 0x40>;
+                        interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 207>,
+                                 <&cpg CPG_CORE 19>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac1 0x51>, <&dmac1 0x50>,
+                               <&dmac2 0x51>, <&dmac2 0x50>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 207>;
+                        status = "disabled";
+                };
+
+                scif1: serial@e6e68000 {
+                        compatible = "renesas,scif-r8a77980",
+                                     "renesas,rcar-gen3-scif",
+                                     "renesas,scif";
+                        reg = <0 0xe6e68000 0 0x40>;
+                        interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 206>,
+                                 <&cpg CPG_CORE 19>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac1 0x53>, <&dmac1 0x52>,
+                               <&dmac2 0x53>, <&dmac2 0x52>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 206>;
+                        status = "disabled";
+                };
+
+                scif3: serial@e6c50000 {
+                        compatible = "renesas,scif-r8a77980",
+                                     "renesas,rcar-gen3-scif",
+                                     "renesas,scif";
+                        reg = <0 0xe6c50000 0 0x40>;
+                        interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 204>,
+                                 <&cpg CPG_CORE 19>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac1 0x57>, <&dmac1 0x56>,
+                               <&dmac2 0x57>, <&dmac2 0x56>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 204>;
+                        status = "disabled";
+                };
+
+                scif4: serial@e6c40000 {
+                        compatible = "renesas,scif-r8a77980",
+                                     "renesas,rcar-gen3-scif",
+                                     "renesas,scif";
+                        reg = <0 0xe6c40000 0 0x40>;
+                        interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 203>,
+                                 <&cpg CPG_CORE 19>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac1 0x59>, <&dmac1 0x58>,
+                               <&dmac2 0x59>, <&dmac2 0x58>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 203>;
+                        status = "disabled";
+                };
+
+                dmac1: dma-controller@e7300000 {
+                        compatible = "renesas,dmac-r8a77980",
+                                     "renesas,rcar-dmac";
+                        reg = <0 0xe7300000 0 0x10000>;
+                        interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "error",
+                                          "ch0", "ch1", "ch2", "ch3",
+                                          "ch4", "ch5", "ch6", "ch7",
+                                          "ch8", "ch9", "ch10", "ch11",
+                                          "ch12", "ch13", "ch14", "ch15";
+                        clocks = <&cpg CPG_MOD 218>;
+                        clock-names = "fck";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 218>;
+                        #dma-cells = <1>;
+                        dma-channels = <16>;
+                };
+
+                dmac2: dma-controller@e7310000 {
+                        compatible = "renesas,dmac-r8a77980",
+                                     "renesas,rcar-dmac";
+                        reg = <0 0xe7310000 0 0x10000>;
+                        interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "error",
+                                          "ch0", "ch1", "ch2", "ch3",
+                                          "ch4", "ch5", "ch6", "ch7",
+                                          "ch8", "ch9", "ch10", "ch11",
+                                          "ch12", "ch13", "ch14", "ch15";
+                        clocks = <&cpg CPG_MOD 217>;
+                        clock-names = "fck";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 217>;
+                        #dma-cells = <1>;
+                        dma-channels = <16>;
+                };
+
+                gic: interrupt-controller@f1010000 {
+                        compatible = "arm,gic-400";
+                        #interrupt-cells = <3>;
+                        #address-cells = <0>;
+                        interrupt-controller;
+                        reg = <0x0 0xf1010000 0 0x1000>,
+                              <0x0 0xf1020000 0 0x20000>,
+                              <0x0 0xf1040000 0 0x20000>,
+                              <0x0 0xf1060000 0 0x20000>;
+                        interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
+                                      IRQ_TYPE_LEVEL_HIGH)>;
+                        clocks = <&cpg CPG_MOD 408>;
+                        clock-names = "clk";
+                        power-domains = <&sysc 32>;
+                        resets = <&cpg 408>;
+                };
+
+                prr: chipid@fff00044 {
+                        compatible = "renesas,prr";
+                        reg = <0 0xfff00044 0 4>;
+                };
+        };
+
+        timer {
+                compatible = "arm,armv8-timer";
+                interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
+                                       IRQ_TYPE_LEVEL_LOW)>,
+                                      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
+                                       IRQ_TYPE_LEVEL_LOW)>,
+                                      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
+                                       IRQ_TYPE_LEVEL_LOW)>,
+                                      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
+                                       IRQ_TYPE_LEVEL_LOW)>;
+        };
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
index 09de73b11db8..d03f19414028 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
@@ -27,11 +27,61 @@
                 stdout-path = "serial0:115200n8";
         };
 
+        vga {
+                compatible = "vga-connector";
+
+                port {
+                        vga_in: endpoint {
+                                remote-endpoint = <&adv7123_out>;
+                        };
+                };
+        };
+
+        vga-encoder {
+                compatible = "adi,adv7123";
+
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@0 {
+                                reg = <0>;
+                                adv7123_in: endpoint {
+                                        remote-endpoint = <&du_out_rgb>;
+                                };
+                        };
+                        port@1 {
+                                reg = <1>;
+                                adv7123_out: endpoint {
+                                        remote-endpoint = <&vga_in>;
+                                };
+                        };
+                };
+        };
+
         memory@48000000 {
                 device_type = "memory";
                 /* first 128MB is reserved for secure area. */
                 reg = <0x0 0x48000000 0x0 0x18000000>;
         };
+
+        reg_1p8v: regulator0 {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-1.8V";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                regulator-boot-on;
+                regulator-always-on;
+        };
+
+        reg_3p3v: regulator1 {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-3.3V";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-boot-on;
+                regulator-always-on;
+        };
 };
 
 &extal_clk {
@@ -46,6 +96,21 @@
                 };
         };
 
+        du_pins: du {
+                groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
+                function = "du";
+        };
+
+        i2c0_pins: i2c0 {
+                groups = "i2c0";
+                function = "i2c0";
+        };
+
+        i2c1_pins: i2c1 {
+                groups = "i2c1";
+                function = "i2c1";
+        };
+
         pwm0_pins: pwm0 {
                 groups = "pwm0_c";
                 function = "pwm0";
@@ -61,12 +126,56 @@
                 function = "scif2";
         };
 
+        sdhi2_pins: sd2 {
+                groups = "mmc_data8", "mmc_ctrl";
+                function = "mmc";
+                power-source = <1800>;
+        };
+
+        sdhi2_pins_uhs: sd2_uhs {
+                groups = "mmc_data8", "mmc_ctrl";
+                function = "mmc";
+                power-source = <1800>;
+        };
+
         usb0_pins: usb0 {
                 groups = "usb0";
                 function = "usb0";
         };
 };
 
+&i2c0 {
+        pinctrl-0 = <&i2c0_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+
+        eeprom@50 {
+                compatible = "rohm,br24t01", "atmel,24c01";
+                reg = <0x50>;
+                pagesize = <8>;
+        };
+};
+
+&i2c1 {
+        pinctrl-0 = <&i2c1_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+};
+
+&du {
+        pinctrl-0 = <&du_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+
+        ports {
+                port@0 {
+                        endpoint {
+                                remote-endpoint = <&adv7123_in>;
+                        };
+                };
+        };
+};
+
 &ehci0 {
         status = "okay";
 };
@@ -80,6 +189,7 @@
         pinctrl-names = "default";
         renesas,no-ether-link;
         phy-handle = <&phy0>;
+        phy-mode = "rgmii-txid";
         status = "okay";
 
         phy0: ethernet-phy@0 {
@@ -97,6 +207,20 @@
         status = "okay";
 };
 
+&sdhi2 {
+        /* used for on-board eMMC */
+        pinctrl-0 = <&sdhi2_pins>;
+        pinctrl-1 = <&sdhi2_pins_uhs>;
+        pinctrl-names = "default", "state_uhs";
+
+        vmmc-supply = <&reg_3p3v>;
+        vqmmc-supply = <&reg_1p8v>;
+        bus-width = <8>;
+        mmc-hs200-1_8v;
+        non-removable;
+        status = "okay";
+};
+
 &usb2_phy0 {
         pinctrl-0 = <&usb0_pins>;
         pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index cff42cd1a6c8..82aed7ee984c 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -58,6 +58,11 @@
                 clock-frequency = <0>;
         };
 
+        pmu_a53 {
+                compatible = "arm,cortex-a53-pmu";
+                interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+        };
+
         scif_clk: scif {
                 compatible = "fixed-clock";
                 #clock-cells = <0>;
@@ -88,18 +93,6 @@
                         resets = <&cpg 408>;
                 };
 
-                timer {
-                        compatible = "arm,armv8-timer";
-                        interrupts = <GIC_PPI 13
-                                        (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
-                                     <GIC_PPI 14
-                                        (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
-                                     <GIC_PPI 11
-                                        (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
-                                     <GIC_PPI 10
-                                        (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
-                };
-
                 rwdt: watchdog@e6020000 {
                         compatible = "renesas,r8a77995-wdt",
                                      "renesas,rcar-gen3-wdt";
@@ -110,11 +103,6 @@
                         status = "disabled";
                 };
 
-                pmu_a53 {
-                        compatible = "arm,cortex-a53-pmu";
-                        interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
-                };
-
                 ipmmu_vi0: mmu@febd0000 {
                         compatible = "renesas,ipmmu-r8a77995";
                         reg = <0 0xfebd0000 0 0x1000>;
@@ -488,7 +476,7 @@
                 avb: ethernet@e6800000 {
                         compatible = "renesas,etheravb-r8a77995",
                                      "renesas,etheravb-rcar-gen3";
-                        reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
+                        reg = <0 0xe6800000 0 0x800>;
                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
                                      <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
@@ -524,7 +512,7 @@
                         clocks = <&cpg CPG_MOD 812>;
                         power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
                         resets = <&cpg 812>;
-                        phy-mode = "rgmii-txid";
+                        phy-mode = "rgmii";
                         iommus = <&ipmmu_ds0 16>;
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -548,6 +536,73 @@
                         status = "disabled";
                 };
 
+                i2c0: i2c@e6500000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a77995",
+                                     "renesas,rcar-gen3-i2c";
+                        reg = <0 0xe6500000 0 0x40>;
+                        interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 931>;
+                        power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+                        resets = <&cpg 931>;
+                        dmas = <&dmac1 0x91>, <&dmac1 0x90>,
+                               <&dmac2 0x91>, <&dmac2 0x90>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        i2c-scl-internal-delay-ns = <6>;
+                        status = "disabled";
+                };
+
+                i2c1: i2c@e6508000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a77995",
+                                     "renesas,rcar-gen3-i2c";
+                        reg = <0 0xe6508000 0 0x40>;
+                        interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 930>;
+                        power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+                        resets = <&cpg 930>;
+                        dmas = <&dmac1 0x93>, <&dmac1 0x92>,
+                               <&dmac2 0x93>, <&dmac2 0x92>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        i2c-scl-internal-delay-ns = <6>;
+                        status = "disabled";
+                };
+
+                i2c2: i2c@e6510000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a77995",
+                                     "renesas,rcar-gen3-i2c";
+                        reg = <0 0xe6510000 0 0x40>;
+                        interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 929>;
+                        power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+                        resets = <&cpg 929>;
+                        dmas = <&dmac1 0x95>, <&dmac1 0x94>,
+                               <&dmac2 0x95>, <&dmac2 0x94>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        i2c-scl-internal-delay-ns = <6>;
+                        status = "disabled";
+                };
+
+                i2c3: i2c@e66d0000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "renesas,i2c-r8a77995",
+                                     "renesas,rcar-gen3-i2c";
+                        reg = <0 0xe66d0000 0 0x40>;
+                        interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 928>;
+                        power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+                        resets = <&cpg 928>;
+                        dmas = <&dmac0 0x97>, <&dmac0 0x96>;
+                        dma-names = "tx", "rx";
+                        i2c-scl-internal-delay-ns = <6>;
+                        status = "disabled";
+                };
+
                 pwm0: pwm@e6e30000 {
                         compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
                         reg = <0 0xe6e30000 0 0x8>;
@@ -636,5 +691,105 @@
                         #phy-cells = <0>;
                         status = "disabled";
                 };
+
+                vspbs: vsp@fe960000 {
+                        compatible = "renesas,vsp2";
+                        reg = <0 0xfe960000 0 0x8000>;
+                        interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 627>;
+                        power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+                        resets = <&cpg 627>;
+                        renesas,fcp = <&fcpvb0>;
+                };
+
+                fcpvb0: fcp@fe96f000 {
+                        compatible = "renesas,fcpv";
+                        reg = <0 0xfe96f000 0 0x200>;
+                        clocks = <&cpg CPG_MOD 607>;
+                        power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+                        resets = <&cpg 607>;
+                        iommus = <&ipmmu_vp0 5>;
+                };
+
+                vspd0: vsp@fea20000 {
+                        compatible = "renesas,vsp2";
+                        reg = <0 0xfea20000 0 0x8000>;
+                        interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 623>;
+                        power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+                        resets = <&cpg 623>;
+                        renesas,fcp = <&fcpvd0>;
+                };
+
+                fcpvd0: fcp@fea27000 {
+                        compatible = "renesas,fcpv";
+                        reg = <0 0xfea27000 0 0x200>;
+                        clocks = <&cpg CPG_MOD 603>;
+                        power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+                        resets = <&cpg 603>;
+                        iommus = <&ipmmu_vi0 8>;
+                };
+
+                vspd1: vsp@fea28000 {
+                        compatible = "renesas,vsp2";
+                        reg = <0 0xfea28000 0 0x8000>;
+                        interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 622>;
+                        power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+                        resets = <&cpg 622>;
+                        renesas,fcp = <&fcpvd1>;
+                };
+
+                fcpvd1: fcp@fea2f000 {
+                        compatible = "renesas,fcpv";
+                        reg = <0 0xfea2f000 0 0x200>;
+                        clocks = <&cpg CPG_MOD 602>;
+                        power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+                        resets = <&cpg 602>;
+                        iommus = <&ipmmu_vi0 9>;
+                };
+
+                du: display@feb00000 {
+                        compatible = "renesas,du-r8a77995";
+                        reg = <0 0xfeb00000 0 0x80000>;
+                        interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&cpg CPG_MOD 724>,
+                                 <&cpg CPG_MOD 723>;
+                        clock-names = "du.0", "du.1";
+                        vsps = <&vspd0 0 &vspd1 0>;
+                        status = "disabled";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port@0 {
+                                        reg = <0>;
+                                        du_out_rgb: endpoint {
+                                        };
+                                };
+
+                                port@1 {
+                                        reg = <1>;
+                                        du_out_lvds0: endpoint {
+                                        };
+                                };
+
+                                port@2 {
+                                        reg = <2>;
+                                        du_out_lvds1: endpoint {
+                                        };
+                                };
+                        };
+                };
+        };
+
+        timer {
+                compatible = "arm,armv8-timer";
+                interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+                                      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+                                      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+                                      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
         };
 };
diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
index c3fafb6025b3..2a7f36abd2dd 100644
--- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
@@ -256,6 +256,7 @@
         pinctrl-0 = <&avb_pins>;
         pinctrl-names = "default";
         phy-handle = <&phy0>;
+        phy-mode = "rgmii-txid";
         status = "okay";
 
         phy0: ethernet-phy@0 {
@@ -338,6 +339,13 @@
 &i2c4 {
         status = "okay";
 
+        pca9654: gpio@20 {
+                compatible = "onnn,pca9654";
+                reg = <0x20>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
         csa_vdd: adc@7c {
                 compatible = "maxim,max9611";
                 reg = <0x7c>;
diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi
index 3e7a6b94e9f8..6f814845f8b6 100644
--- a/arch/arm64/boot/dts/renesas/ulcb.dtsi
+++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi
@@ -146,6 +146,7 @@
         pinctrl-0 = <&avb_pins>;
         pinctrl-names = "default";
         phy-handle = <&phy0>;
+        phy-mode = "rgmii-txid";
         status = "okay";
 
         phy0: ethernet-phy@0 {
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
index 3890468678ce..28257724a56e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
@@ -132,17 +132,16 @@
         assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
         assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
         clock_in_out = "input";
-        /* shows instability at 1GBit right now */
-        max-speed = <100>;
         phy-supply = <&vcc_io>;
         phy-mode = "rgmii";
         pinctrl-names = "default";
         pinctrl-0 = <&rgmiim1_pins>;
+        snps,force_thresh_dma_mode;
         snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
         snps,reset-active-low;
         snps,reset-delays-us = <0 10000 50000>;
-        tx_delay = <0x26>;
-        rx_delay = <0x11>;
+        tx_delay = <0x24>;
+        rx_delay = <0x18>;
         status = "okay";
 };
 
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index a037ee56fead..cae341554486 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -730,7 +730,7 @@
                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
-                clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+                clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
                 fifo-depth = <0x100>;
                 status = "disabled";
         };
@@ -741,7 +741,7 @@
                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
-                clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+                clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
                 fifo-depth = <0x100>;
                 status = "disabled";
         };
@@ -752,7 +752,7 @@
                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
-                clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+                clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
                 fifo-depth = <0x100>;
                 status = "disabled";
         };
diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index aa4d07046a7b..03458ac44201 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -257,7 +257,7 @@
                 max-frequency = <150000000>;
                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
-                clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+                clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
                 fifo-depth = <0x100>;
                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
                 resets = <&cru SRST_SDIO0>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
index 0f873c897d0d..ce592a4c0c4c 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
@@ -457,7 +457,7 @@
         assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
         assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
         assigned-clock-rates = <100000000>;
-        ep-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>;
+        ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;
         num-lanes = <4>;
         pinctrl-names = "default";
         pinctrl-0 = <&pcie_clkreqn_cpm>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 7aa2144e0d47..2605118d4b4c 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1739,8 +1739,8 @@
                 compatible = "rockchip,rk3399-edp";
                 reg = <0x0 0xff970000 0x0 0x8000>;
                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
-                clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
-                clock-names = "dp", "pclk";
+                clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
+                clock-names = "dp", "pclk", "grf";
                 pinctrl-names = "default";
                 pinctrl-0 = <&edp_hpd>;
                 power-domains = <&power RK3399_PD_EDP>;
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts b/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts
index 2452b2243f42..9b4dc41703e3 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts
@@ -1,14 +1,13 @@
-/*
- * Device Tree Source for UniPhier LD11 Global Board
- *
- * Copyright (C) 2016-2017 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *           Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier LD11 Global Board
+//
+// Copyright (C) 2016-2017 Socionext Inc.
+//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+//           Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
 
 /dts-v1/;
+#include <dt-bindings/gpio/uniphier-gpio.h>
 #include "uniphier-ld11.dtsi"
 
 / {
@@ -37,6 +36,53 @@
                 device_type = "memory";
                 reg = <0 0x80000000 0 0x40000000>;
         };
+
+        dvdd_reg: reg-fixed {
+                compatible = "regulator-fixed";
+                regulator-name = "DVDD";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
+
+        amp_vcc_reg: reg-fixed {
+                compatible = "regulator-fixed";
+                regulator-name = "AMP_VCC";
+                regulator-min-microvolt = <24000000>;
+                regulator-max-microvolt = <24000000>;
+        };
+
+        sound {
+                compatible = "audio-graph-card";
+                label = "UniPhier LD11";
+                widgets = "Headphone", "Headphone Jack";
+                dais = <&i2s_port2
+                        &i2s_port3
+                        &i2s_port4
+                        &spdif_port0
+                        &comp_spdif_port0>;
+        };
+
+        spdif-out {
+                compatible = "linux,spdif-dit";
+                #sound-dai-cells = <0>;
+
+                port@0 {
+                        spdif_tx: endpoint {
+                                remote-endpoint = <&spdif_hiecout1>;
+                        };
+                };
+        };
+
+        comp-spdif-out {
+                compatible = "linux,spdif-dit";
+                #sound-dai-cells = <0>;
+
+                port@0 {
+                        comp_spdif_tx: endpoint {
+                                remote-endpoint = <&comp_spdif_hiecout1>;
+                        };
+                };
+        };
 };
 
 &serial0 {
@@ -47,9 +93,43 @@
         status = "okay";
 };
 
+&i2s_hpcmout1 {
+        dai-format = "i2s";
+        remote-endpoint = <&tas_speaker>;
+};
+
+&spdif_hiecout1 {
+        remote-endpoint = <&spdif_tx>;
+};
+
+&comp_spdif_hiecout1 {
+        remote-endpoint = <&comp_spdif_tx>;
+};
+
 &i2c0 {
         status = "okay";
 
+        tas5707a@1d {
+                compatible = "ti,tas5711";
+                reg = <0x1d>;
+                reset-gpios = <&gpio UNIPHIER_GPIO_PORT(23, 4) GPIO_ACTIVE_LOW>;
+                pdn-gpios = <&gpio UNIPHIER_GPIO_PORT(23, 5) GPIO_ACTIVE_LOW>;
+                #sound-dai-cells = <0>;
+                AVDD-supply = <&dvdd_reg>;
+                DVDD-supply = <&dvdd_reg>;
+                PVDD_A-supply = <&amp_vcc_reg>;
+                PVDD_B-supply = <&amp_vcc_reg>;
+                PVDD_C-supply = <&amp_vcc_reg>;
+                PVDD_D-supply = <&amp_vcc_reg>;
+
+                port@0 {
+                        tas_speaker: endpoint {
+                                dai-format = "i2s";
+                                remote-endpoint = <&i2s_hpcmout1>;
+                        };
+                };
+        };
+
         eeprom@50 {
                 compatible = "st,24c64", "atmel,24c64";
                 reg = <0x50>;
@@ -69,6 +149,17 @@
         status = "okay";
 };
 
+&eth {
+        status = "okay";
+        phy-handle = <&ethphy>;
+};
+
+&mdio {
+        ethphy: ethphy@1 {
+                reg = <1>;
+        };
+};
+
 &nand {
         status = "okay";
 };
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts
index 54c53170699a..b8f627348448 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier LD11 Reference Board
- *
- * Copyright (C) 2016 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier LD11 Reference Board
+//
+// Copyright (C) 2016 Socionext Inc.
+//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 
 /dts-v1/;
 #include "uniphier-ld11.dtsi"
@@ -70,3 +68,14 @@
 &usb2 {
         status = "okay";
 };
+
+&eth {
+        status = "okay";
+        phy-handle = <&ethphy>;
+};
+
+&mdio {
+        ethphy: ethphy@1 {
+                reg = <1>;
+        };
+};
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
index cd7c2d0a1f64..efa95573b2aa 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier LD11 SoC
- *
- * Copyright (C) 2016 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier LD11 SoC
+//
+// Copyright (C) 2016 Socionext Inc.
+//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/gpio/uniphier-gpio.h>
@@ -187,6 +185,91 @@
                                                      <21 217 3>;
                 };
 
+                audio@56000000 {
+                        compatible = "socionext,uniphier-ld11-aio";
+                        reg = <0x56000000 0x80000>;
+                        interrupts = <0 144 4>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_aout1>,
+                                    <&pinctrl_aoutiec1>;
+                        clock-names = "aio";
+                        clocks = <&sys_clk 40>;
+                        reset-names = "aio";
+                        resets = <&sys_rst 40>;
+                        #sound-dai-cells = <1>;
+
+                        i2s_port0: port@0 {
+                                i2s_hdmi: endpoint {
+                                };
+                        };
+
+                        i2s_port1: port@1 {
+                                i2s_pcmin2: endpoint {
+                                };
+                        };
+
+                        i2s_port2: port@2 {
+                                i2s_line: endpoint {
+                                        dai-format = "i2s";
+                                        remote-endpoint = <&evea_line>;
+                                };
+                        };
+
+                        i2s_port3: port@3 {
+                                i2s_hpcmout1: endpoint {
+                                };
+                        };
+
+                        i2s_port4: port@4 {
+                                i2s_hp: endpoint {
+                                        dai-format = "i2s";
+                                        remote-endpoint = <&evea_hp>;
+                                };
+                        };
+
+                        spdif_port0: port@5 {
+                                spdif_hiecout1: endpoint {
+                                };
+                        };
+
+                        src_port0: port@6 {
+                                i2s_epcmout2: endpoint {
+                                };
+                        };
+
+                        src_port1: port@7 {
+                                i2s_epcmout3: endpoint {
+                                };
+                        };
+
+                        comp_spdif_port0: port@8 {
+                                comp_spdif_hiecout1: endpoint {
+                                };
+                        };
+                };
+
+                codec@57900000 {
+                        compatible = "socionext,uniphier-evea";
+                        reg = <0x57900000 0x1000>;
+                        clock-names = "evea", "exiv";
+                        clocks = <&sys_clk 41>, <&sys_clk 42>;
+                        reset-names = "evea", "exiv", "adamv";
+                        resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
+                        #sound-dai-cells = <1>;
+
+                        port@0 {
+                                evea_line: endpoint {
+                                        remote-endpoint = <&i2s_line>;
+                                };
+                        };
+
+                        port@1 {
+                                evea_hp: endpoint {
+                                        remote-endpoint = <&i2s_hp>;
+                                };
+                        };
+                };
+
                 adamv@57920000 {
                         compatible = "socionext,uniphier-ld11-adamv",
                                      "simple-mfd", "syscon";
@@ -460,6 +543,22 @@
                         };
                 };
 
+                eth: ethernet@65000000 {
+                        compatible = "socionext,uniphier-ld11-ave4";
+                        status = "disabled";
+                        reg = <0x65000000 0x8500>;
+                        interrupts = <0 66 4>;
+                        clocks = <&sys_clk 6>;
+                        resets = <&sys_rst 6>;
+                        phy-mode = "rmii";
+                        local-mac-address = [00 00 00 00 00 00];
+
+                        mdio: mdio {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+                };
+
                 nand: nand@68000000 {
                         compatible = "socionext,uniphier-denali-nand-v5b";
                         status = "disabled";
@@ -475,3 +574,12 @@
 };
 
 #include "uniphier-pinctrl.dtsi"
+
+&pinctrl_aoutiec1 {
+        drive-strength = <4>;   /* default: 4mA */
+
+        ao1arc {
+                pins = "AO1ARC";
+                drive-strength = <8>;   /* 8mA */
+        };
+};
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts b/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts
index fc2bc9d75d35..fe6608ea3277 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts
@@ -1,14 +1,13 @@
-/*
- * Device Tree Source for UniPhier LD20 Global Board
- *
- * Copyright (C) 2015-2017 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *           Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier LD20 Global Board
+//
+// Copyright (C) 2015-2017 Socionext Inc.
+//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+//           Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
 
 /dts-v1/;
+#include <dt-bindings/gpio/uniphier-gpio.h>
 #include "uniphier-ld20.dtsi"
 
 / {
@@ -37,6 +36,53 @@
                 device_type = "memory";
                 reg = <0 0x80000000 0 0xc0000000>;
         };
+
+        dvdd_reg: reg-fixed {
+                compatible = "regulator-fixed";
+                regulator-name = "DVDD";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
+
+        amp_vcc_reg: reg-fixed {
+                compatible = "regulator-fixed";
+                regulator-name = "AMP_VCC";
+                regulator-min-microvolt = <12000000>;
+                regulator-max-microvolt = <12000000>;
+        };
+
+        sound {
+                compatible = "audio-graph-card";
+                label = "UniPhier LD20";
+                widgets = "Headphone", "Headphone Jack";
+                dais = <&i2s_port2
+                        &i2s_port3
+                        &i2s_port4
+                        &spdif_port0
+                        &comp_spdif_port0>;
+        };
+
+        spdif-out {
+                compatible = "linux,spdif-dit";
+                #sound-dai-cells = <0>;
+
+                port@0 {
+                        spdif_tx: endpoint {
+                                remote-endpoint = <&spdif_hiecout1>;
+                        };
+                };
+        };
+
+        comp-spdif-out {
+                compatible = "linux,spdif-dit";
+                #sound-dai-cells = <0>;
+
+                port@0 {
+                        comp_spdif_tx: endpoint {
+                                remote-endpoint = <&comp_spdif_hiecout1>;
+                        };
+                };
+        };
 };
 
 &serial0 {
@@ -47,8 +93,55 @@
         status = "okay";
 };
 
+&i2s_hpcmout1 {
+        dai-format = "i2s";
+        remote-endpoint = <&tas_speaker>;
+};
+
+&spdif_hiecout1 {
+        remote-endpoint = <&spdif_tx>;
+};
+
+&comp_spdif_hiecout1 {
+        remote-endpoint = <&comp_spdif_tx>;
+};
+
 &i2c0 {
         status = "okay";
+
+        tas5707@1b {
+                compatible = "ti,tas5711";
+                reg = <0x1b>;
+                reset-gpios = <&gpio UNIPHIER_GPIO_PORT(0, 0) GPIO_ACTIVE_LOW>;
+                pdn-gpios = <&gpio UNIPHIER_GPIO_PORT(0, 1) GPIO_ACTIVE_LOW>;
+                #sound-dai-cells = <0>;
+                AVDD-supply = <&dvdd_reg>;
+                DVDD-supply = <&dvdd_reg>;
+                PVDD_A-supply = <&amp_vcc_reg>;
+                PVDD_B-supply = <&amp_vcc_reg>;
+                PVDD_C-supply = <&amp_vcc_reg>;
+                PVDD_D-supply = <&amp_vcc_reg>;
+
+                port@0 {
+                        tas_speaker: endpoint {
+                                dai-format = "i2s";
+                                remote-endpoint = <&i2s_hpcmout1>;
+                        };
+                };
+        };
+};
+
+&eth {
+        status = "okay";
+        phy-mode = "rmii";
+        pinctrl-0 = <&pinctrl_ether_rmii>;
+        phy-handle = <&ethphy>;
+};
+
+&mdio {
+        ethphy: ethphy@1 {
+                reg = <1>;
+        };
 };
 
 &nand {
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts
index 693371033c90..2c1a92fafbfb 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier LD20 Reference Board
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier LD20 Reference Board
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 
 /dts-v1/;
 #include "uniphier-ld20.dtsi"
@@ -58,3 +56,14 @@
 &i2c0 {
         status = "okay";
 };
+
+&eth {
+        status = "okay";
+        phy-handle = <&ethphy>;
+};
+
+&mdio {
+        ethphy: ethphy@0 {
+                reg = <0>;
+        };
+};
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
index 8a3276ba2da1..19c935688a77 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier LD20 SoC
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier LD20 SoC
+//
+// Copyright (C) 2015-2016 Socionext Inc.
+//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/gpio/uniphier-gpio.h>
@@ -287,6 +285,91 @@
                                                      <21 217 3>;
                 };
 
+                audio@56000000 {
+                        compatible = "socionext,uniphier-ld20-aio";
+                        reg = <0x56000000 0x80000>;
+                        interrupts = <0 144 4>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_aout1>,
+                                    <&pinctrl_aoutiec1>;
+                        clock-names = "aio";
+                        clocks = <&sys_clk 40>;
+                        reset-names = "aio";
+                        resets = <&sys_rst 40>;
+                        #sound-dai-cells = <1>;
+
+                        i2s_port0: port@0 {
+                                i2s_hdmi: endpoint {
+                                };
+                        };
+
+                        i2s_port1: port@1 {
+                                i2s_pcmin2: endpoint {
+                                };
+                        };
+
+                        i2s_port2: port@2 {
+                                i2s_line: endpoint {
+                                        dai-format = "i2s";
+                                        remote-endpoint = <&evea_line>;
+                                };
+                        };
+
+                        i2s_port3: port@3 {
+                                i2s_hpcmout1: endpoint {
+                                };
+                        };
+
+                        i2s_port4: port@4 {
+                                i2s_hp: endpoint {
+                                        dai-format = "i2s";
+                                        remote-endpoint = <&evea_hp>;
+                                };
+                        };
+
+                        spdif_port0: port@5 {
+                                spdif_hiecout1: endpoint {
+                                };
+                        };
+
+                        src_port0: port@6 {
+                                i2s_epcmout2: endpoint {
+                                };
+                        };
+
+                        src_port1: port@7 {
+                                i2s_epcmout3: endpoint {
+                                };
+                        };
+
+                        comp_spdif_port0: port@8 {
+                                comp_spdif_hiecout1: endpoint {
+                                };
+                        };
+                };
+
+                codec@57900000 {
+                        compatible = "socionext,uniphier-evea";
+                        reg = <0x57900000 0x1000>;
+                        clock-names = "evea", "exiv";
+                        clocks = <&sys_clk 41>, <&sys_clk 42>;
+                        reset-names = "evea", "exiv", "adamv";
+                        resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
+                        #sound-dai-cells = <1>;
+
+                        port@0 {
+                                evea_line: endpoint {
+                                        remote-endpoint = <&i2s_line>;
+                                };
+                        };
+
+                        port@1 {
+                                evea_hp: endpoint {
+                                        remote-endpoint = <&i2s_hp>;
+                                };
+                        };
+                };
+
                 adamv@57920000 {
                         compatible = "socionext,uniphier-ld20-adamv",
                                      "simple-mfd", "syscon";
@@ -513,6 +596,24 @@
                         };
                 };
 
+                eth: ethernet@65000000 {
+                        compatible = "socionext,uniphier-ld20-ave4";
+                        status = "disabled";
+                        reg = <0x65000000 0x8500>;
+                        interrupts = <0 66 4>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_ether_rgmii>;
+                        clocks = <&sys_clk 6>;
+                        resets = <&sys_rst 6>;
+                        phy-mode = "rgmii";
+                        local-mac-address = [00 00 00 00 00 00];
+
+                        mdio: mdio {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+                };
+
                 nand: nand@68000000 {
                         compatible = "socionext,uniphier-denali-nand-v5b";
                         status = "disabled";
@@ -528,3 +629,21 @@
 };
 
 #include "uniphier-pinctrl.dtsi"
+
+&pinctrl_aout1 {
+        drive-strength = <4>;   /* default: 3.5mA */
+
+        ao1dacck {
+                pins = "AO1DACCK";
+                drive-strength = <5>;   /* 5mA */
+        };
+};
+
+&pinctrl_aoutiec1 {
+        drive-strength = <4>;   /* default: 3.5mA */
+
+        ao1arc {
+                pins = "AO1ARC";
+                drive-strength = <11>;  /* 11mA */
+        };
+};
diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts
index 3c7108729827..e62d068776d5 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts
+++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier PXs3 Reference Board
- *
- * Copyright (C) 2017 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier PXs3 Reference Board
+//
+// Copyright (C) 2017 Socionext Inc.
+//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 
 /dts-v1/;
 #include "uniphier-pxs3.dtsi"
diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
index 234fc58cc599..b537a3c0071f 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
@@ -1,11 +1,9 @@
-/*
- * Device Tree Source for UniPhier PXs3 SoC
- *
- * Copyright (C) 2017 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Device Tree Source for UniPhier PXs3 SoC
+//
+// Copyright (C) 2017 Socionext Inc.
+//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/gpio/uniphier-gpio.h>
diff --git a/arch/arm64/boot/dts/sprd/sc2731.dtsi b/arch/arm64/boot/dts/sprd/sc2731.dtsi
new file mode 100644
index 000000000000..4331006185bf
--- /dev/null
+++ b/arch/arm64/boot/dts/sprd/sc2731.dtsi
@@ -0,0 +1,169 @@
+/*
+ * Spreadtrum SC2731 PMIC dts file
+ *
+ * Copyright (C) 2018, Spreadtrum Communications Inc.
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+&adi_bus {
+        sc2731_pmic: pmic@0 {
+                compatible = "sprd,sc2731";
+                reg = <0>;
+                spi-max-frequency = <26000000>;
+                interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                rtc@280 {
+                        compatible = "sprd,sc27xx-rtc", "sprd,sc2731-rtc";
+                        reg = <0x280>;
+                        interrupt-parent = <&sc2731_pmic>;
+                        interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
+                };
+
+                regulators {
+                        compatible = "sprd,sc27xx-regulator";
+
+                        vddarm0: BUCK_CPU0 {
+                                regulator-name = "vddarm0";
+                                regulator-min-microvolt = <400000>;
+                                regulator-max-microvolt = <1996875>;
+                                regulator-ramp-delay = <25000>;
+                                regulator-always-on;
+                        };
+
+                        vddarm1: BUCK_CPU1 {
+                                regulator-name = "vddarm1";
+                                regulator-min-microvolt = <400000>;
+                                regulator-max-microvolt = <1996875>;
+                                regulator-ramp-delay = <25000>;
+                                regulator-always-on;
+                        };
+
+                        dcdcrf: BUCK_RF {
+                                regulator-name = "dcdcrf";
+                                regulator-min-microvolt = <600000>;
+                                regulator-max-microvolt = <2196875>;
+                                regulator-ramp-delay = <25000>;
+                                regulator-enable-ramp-delay = <100>;
+                                regulator-always-on;
+                        };
+
+                        vddcama0: LDO_CAMA0 {
+                                regulator-name = "vddcama0";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <3750000>;
+                                regulator-enable-ramp-delay = <100>;
+                        };
+
+                        vddcama1: LDO_CAMA1 {
+                                regulator-name = "vddcama1";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <3750000>;
+                                regulator-enable-ramp-delay = <100>;
+                                regulator-ramp-delay = <25000>;
+                        };
+
+                        vddcammot: LDO_CAMMOT {
+                                regulator-name = "vddcammot";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <3750000>;
+                                regulator-enable-ramp-delay = <100>;
+                                regulator-ramp-delay = <25000>;
+                        };
+
+                        vddvldo: LDO_VLDO {
+                                regulator-name = "vddvldo";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <3750000>;
+                                regulator-enable-ramp-delay = <100>;
+                                regulator-ramp-delay = <25000>;
+                        };
+
+                        vddemmccore: LDO_EMMCCORE {
+                                regulator-name = "vddemmccore";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <3750000>;
+                                regulator-enable-ramp-delay = <100>;
+                                regulator-ramp-delay = <25000>;
+                                regulator-boot-on;
+                        };
+
+                        vddsdcore: LDO_SDCORE {
+                                regulator-name = "vddsdcore";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <3750000>;
+                                regulator-enable-ramp-delay = <100>;
+                                regulator-ramp-delay = <25000>;
+                        };
+
+                        vddsdio: LDO_SDIO {
+                                regulator-name = "vddsdio";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <3750000>;
+                                regulator-enable-ramp-delay = <100>;
+                                regulator-ramp-delay = <25000>;
+                        };
+
+                        vddwifipa: LDO_WIFIPA {
+                                regulator-name = "vddwifipa";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <3750000>;
+                                regulator-enable-ramp-delay = <100>;
+                                regulator-ramp-delay = <25000>;
+                        };
+
+                        vddusb33: LDO_USB33 {
+                                regulator-name = "vddusb33";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <3750000>;
+                                regulator-enable-ramp-delay = <100>;
+                                regulator-ramp-delay = <25000>;
+                        };
+
+                        vddcamd0: LDO_CAMD0 {
+                                regulator-name = "vddcamd0";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1793750>;
+                                regulator-enable-ramp-delay = <100>;
+                                regulator-ramp-delay = <25000>;
+                        };
+
+                        vddcamd1: LDO_CAMD1 {
+                                regulator-name = "vddcamd1";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1793750>;
+                                regulator-enable-ramp-delay = <100>;
+                                regulator-ramp-delay = <25000>;
+                        };
+
+                        vddcon: LDO_CON {
+                                regulator-name = "vddcon";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1793750>;
+                                regulator-enable-ramp-delay = <100>;
+                                regulator-ramp-delay = <25000>;
+                        };
+
+                        vddcamio: LDO_CAMIO {
+                                regulator-name = "vddcamio";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1793750>;
+                                regulator-enable-ramp-delay = <100>;
+                                regulator-ramp-delay = <25000>;
+                        };
+
+                        vddsram: LDO_SRAM {
+                                regulator-name = "vddsram";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1793750>;
+                                regulator-enable-ramp-delay = <100>;
+                                regulator-ramp-delay = <25000>;
+                                regulator-always-on;
+                        };
+                };
+        };
+};
diff --git a/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts b/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts
index ae0b28ce6319..985ebb5d157e 100644
--- a/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts
+++ b/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts
@@ -9,6 +9,7 @@
 /dts-v1/;
 
 #include "sc9860.dtsi"
+#include "sc2731.dtsi"
 
 / {
         model = "Spreadtrum SP9860G 3GFHD Board";
@@ -20,6 +21,7 @@
                 serial1 = &uart1; /* UART console */
                 serial2 = &uart2; /* Reserved */
                 serial3 = &uart3; /* for GPS */
+                spi0 = &adi_bus;
         };
 
         memory{
diff --git a/arch/arm64/boot/dts/sprd/whale2.dtsi b/arch/arm64/boot/dts/sprd/whale2.dtsi
index 328009c4638c..66a881e6da92 100644
--- a/arch/arm64/boot/dts/sprd/whale2.dtsi
+++ b/arch/arm64/boot/dts/sprd/whale2.dtsi
@@ -6,6 +6,8 @@
  * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
+#include <dt-bindings/clock/sprd,sc9860-clk.h>
+
 / {
         interrupt-parent = <&gic>;
         #address-cells = <2>;
@@ -104,6 +106,85 @@
                                 status = "disabled";
                         };
                 };
+
+                ap-ahb {
+                        compatible = "simple-bus";
+                        #address-cells = <2>;
+                        #size-cells = <2>;
+                        ranges;
+
+                        ap_dma: dma-controller@20100000 {
+                                compatible = "sprd,sc9860-dma";
+                                reg = <0 0x20100000 0 0x4000>;
+                                interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+                                #dma-cells = <1>;
+                                #dma-channels = <32>;
+                                clock-names = "enable";
+                                clocks = <&apahb_gate CLK_DMA_EB>;
+                        };
+                };
+
+                aon {
+                        compatible = "simple-bus";
+                        #address-cells = <2>;
+                        #size-cells = <2>;
+                        ranges;
+
+                        adi_bus: spi@40030000 {
+                                compatible = "sprd,sc9860-adi";
+                                reg = <0 0x40030000 0 0x10000>;
+                                hwlocks = <&hwlock 0>;
+                                hwlock-names = "adi";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        timer@40050000 {
+                                compatible = "sprd,sc9860-timer";
+                                reg = <0 0x40050000 0 0x20>;
+                                interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&ext_32k>;
+                        };
+
+                        hwlock: hwspinlock@40500000 {
+                                compatible = "sprd,hwspinlock-r3p0";
+                                reg = <0 0x40500000 0 0x1000>;
+                                #hwlock-cells = <1>;
+                                clock-names = "enable";
+                                clocks = <&aon_gate CLK_SPLK_EB>;
+                        };
+
+                        pin_controller: pinctrl@402a0000 {
+                                compatible = "sprd,sc9860-pinctrl";
+                                reg = <0 0x402a0000 0 0x10000>;
+                        };
+
+                        watchdog@40310000 {
+                                compatible = "sprd,sp9860-wdt";
+                                reg = <0 0x40310000 0 0x1000>;
+                                interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+                                timeout-sec = <12>;
+                                clock-names = "enable";
+                                clocks = <&aon_gate CLK_APCPU_WDG_EB>;
+                        };
+                };
+
+                agcp {
+                        compatible = "simple-bus";
+                        #address-cells = <2>;
+                        #size-cells = <2>;
+                        ranges;
+
+                        agcp_dma: dma-controller@41580000 {
+                                compatible = "sprd,sc9860-dma";
+                                reg = <0 0x41580000 0 0x4000>;
+                                #dma-cells = <1>;
+                                #dma-channels = <32>;
+                                clock-names = "enable", "ashb_eb";
+                                clocks = <&agcp_gate CLK_AGCP_DMAAP_EB>,
+                                       <&agcp_gate CLK_AGCP_AP_ASHB_EB>;
+                        };
+                };
         };
 
         ext_32k: ext_32k {
diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
index a2d67084a514..c2a0c00272e2 100644
--- a/arch/arm64/boot/dts/xilinx/Makefile
+++ b/arch/arm64/boot/dts/xilinx/Makefile
@@ -1 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0
 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1232-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1254-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1275-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm015-dc1.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm016-dc2.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm017-dc3.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm018-dc4.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm019-dc5.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu106-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu111-revA.dtb
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
new file mode 100644
index 000000000000..9c09baca7dd7
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
@@ -0,0 +1,213 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Clock specification for Xilinx ZynqMP
+ *
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/ {
+        clk100: clk100 {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <100000000>;
+        };
+
+        clk125: clk125 {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <125000000>;
+        };
+
+        clk200: clk200 {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <200000000>;
+        };
+
+        clk250: clk250 {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <250000000>;
+        };
+
+        clk300: clk300 {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <300000000>;
+        };
+
+        clk600: clk600 {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <600000000>;
+        };
+
+        dp_aclk: clock0 {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <100000000>;
+                clock-accuracy = <100>;
+        };
+
+        dp_aud_clk: clock1 {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <24576000>;
+                clock-accuracy = <100>;
+        };
+
+        dpdma_clk: dpdma_clk {
+                compatible = "fixed-clock";
+                #clock-cells = <0x0>;
+                clock-frequency = <533000000>;
+        };
+
+        drm_clock: drm_clock {
+                compatible = "fixed-clock";
+                #clock-cells = <0x0>;
+                clock-frequency = <262750000>;
+                clock-accuracy = <0x64>;
+        };
+};
+
+&can0 {
+        clocks = <&clk100 &clk100>;
+};
+
+&can1 {
+        clocks = <&clk100 &clk100>;
+};
+
+&fpd_dma_chan1 {
+        clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan2 {
+        clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan3 {
+        clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan4 {
+        clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan5 {
+        clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan6 {
+        clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan7 {
+        clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan8 {
+        clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan1 {
+        clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan2 {
+        clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan3 {
+        clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan4 {
+        clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan5 {
+        clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan6 {
+        clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan7 {
+        clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan8 {
+        clocks = <&clk600>, <&clk100>;
+};
+
+&gem0 {
+        clocks = <&clk125>, <&clk125>, <&clk125>;
+};
+
+&gem1 {
+        clocks = <&clk125>, <&clk125>, <&clk125>;
+};
+
+&gem2 {
+        clocks = <&clk125>, <&clk125>, <&clk125>;
+};
+
+&gem3 {
+        clocks = <&clk125>, <&clk125>, <&clk125>;
+};
+
+&gpio {
+        clocks = <&clk100>;
+};
+
+&i2c0 {
+        clocks = <&clk100>;
+};
+
+&i2c1 {
+        clocks = <&clk100>;
+};
+
+&sata {
+        clocks = <&clk250>;
+};
+
+&sdhci0 {
+        clocks = <&clk200 &clk200>;
+};
+
+&sdhci1 {
+        clocks = <&clk200 &clk200>;
+};
+
+&spi0 {
+        clocks = <&clk200 &clk200>;
+};
+
+&spi1 {
+        clocks = <&clk200 &clk200>;
+};
+
+&uart0 {
+        clocks = <&clk100 &clk100>;
+};
+
+&uart1 {
+        clocks = <&clk100 &clk100>;
+};
+
+&usb0 {
+        clocks = <&clk250>, <&clk250>;
+};
+
+&usb1 {
+        clocks = <&clk250>, <&clk250>;
+};
+
+&watchdog0 {
+        clocks = <&clk250>;
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108-clk.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-ep108-clk.dtsi
index b87b8316f4ac..9f5eedbc2139 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-ep108-clk.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-ep108-clk.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * clock specification for Xilinx ZynqMP ep108 development board
  *
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
index bf552674a834..4b0684911626 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * dts file for Xilinx ZynqMP ep108 development board
  *
@@ -47,7 +48,7 @@
         status = "okay";
         phy-handle = <&phy0>;
         phy-mode = "rgmii-id";
-        phy0: phy@0{
+        phy0: phy@0 {
                 reg = <0>;
                 max-speed = <100>;
         };
@@ -78,10 +79,20 @@
 &sata {
         status = "okay";
         ceva,broken-gen2;
+        /* SATA Phy OOB timing settings */
+        ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
+        ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
+        ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
+        ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>;
+        ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
+        ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
+        ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
+        ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>;
 };
 
 &sdhci0 {
         status = "okay";
+        bus-width = <8>;
 };
 
 &sdhci1 {
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
new file mode 100644
index 000000000000..0f7b4cf6078e
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZC1232
+ *
+ * (C) Copyright 2017 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+
+/ {
+        model = "ZynqMP ZC1232 RevA";
+        compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp";
+
+        aliases {
+                serial0 = &uart0;
+                serial1 = &dcc;
+        };
+
+        chosen {
+                bootargs = "earlycon";
+                stdout-path = "serial0:115200n8";
+        };
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x0 0x0 0x80000000>;
+        };
+};
+
+&dcc {
+        status = "okay";
+};
+
+&sata {
+        status = "okay";
+        /* SATA OOB timing settings */
+        ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+        ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+        ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+        ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+        ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+        ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+        ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+        ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+&uart0 {
+        status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
new file mode 100644
index 000000000000..9092828f92ec
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZC1254
+ *
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+
+/ {
+        model = "ZynqMP ZC1254 RevA";
+        compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp";
+
+        aliases {
+                serial0 = &uart0;
+                serial1 = &dcc;
+        };
+
+        chosen {
+                bootargs = "earlycon";
+                stdout-path = "serial0:115200n8";
+        };
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x0 0x0 0x80000000>;
+        };
+};
+
+&dcc {
+        status = "okay";
+};
+
+&uart0 {
+        status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
new file mode 100644
index 000000000000..4f404c580eec
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZC1275
+ *
+ * (C) Copyright 2017 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+
+/ {
+        model = "ZynqMP ZC1275 RevA";
+        compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp";
+
+        aliases {
+                serial0 = &uart0;
+                serial1 = &dcc;
+        };
+
+        chosen {
+                bootargs = "earlycon";
+                stdout-path = "serial0:115200n8";
+        };
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x0 0x0 0x80000000>;
+        };
+};
+
+&dcc {
+        status = "okay";
+};
+
+&uart0 {
+        status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
new file mode 100644
index 000000000000..9a3e39d1294f
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP zc1751-xm015-dc1
+ *
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+        model = "ZynqMP zc1751-xm015-dc1 RevA";
+        compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+        aliases {
+                ethernet0 = &gem3;
+                i2c0 = &i2c1;
+                mmc0 = &sdhci0;
+                mmc1 = &sdhci1;
+                rtc0 = &rtc;
+                serial0 = &uart0;
+        };
+
+        chosen {
+                bootargs = "earlycon";
+                stdout-path = "serial0:115200n8";
+        };
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+        };
+};
+
+&fpd_dma_chan1 {
+        status = "okay";
+};
+
+&fpd_dma_chan2 {
+        status = "okay";
+};
+
+&fpd_dma_chan3 {
+        status = "okay";
+};
+
+&fpd_dma_chan4 {
+        status = "okay";
+};
+
+&fpd_dma_chan5 {
+        status = "okay";
+};
+
+&fpd_dma_chan6 {
+        status = "okay";
+};
+
+&fpd_dma_chan7 {
+        status = "okay";
+};
+
+&fpd_dma_chan8 {
+        status = "okay";
+};
+
+&gem3 {
+        status = "okay";
+        phy-handle = <&phy0>;
+        phy-mode = "rgmii-id";
+        phy0: phy@0 {
+                reg = <0>;
+        };
+};
+
+&gpio {
+        status = "okay";
+};
+
+
+&i2c1 {
+        status = "okay";
+        clock-frequency = <400000>;
+
+        eeprom: eeprom@55 {
+                compatible = "atmel,24c64"; /* 24AA64 */
+                reg = <0x55>;
+        };
+};
+
+&rtc {
+        status = "okay";
+};
+
+&sata {
+        status = "okay";
+        /* SATA phy OOB timing settings */
+        ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
+        ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
+        ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+        ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+        ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
+        ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
+        ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+        ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+/* eMMC */
+&sdhci0 {
+        status = "okay";
+        bus-width = <8>;
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+        status = "okay";
+};
+
+&uart0 {
+        status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+        status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
new file mode 100644
index 000000000000..11cc67184fa9
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
@@ -0,0 +1,168 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP zc1751-xm016-dc2
+ *
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+        model = "ZynqMP zc1751-xm016-dc2 RevA";
+        compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+        aliases {
+                can0 = &can0;
+                can1 = &can1;
+                ethernet0 = &gem2;
+                i2c0 = &i2c0;
+                rtc0 = &rtc;
+                serial0 = &uart0;
+                serial1 = &uart1;
+                spi0 = &spi0;
+                spi1 = &spi1;
+        };
+
+        chosen {
+                bootargs = "earlycon";
+                stdout-path = "serial0:115200n8";
+        };
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+        };
+};
+
+&can0 {
+        status = "okay";
+};
+
+&can1 {
+        status = "okay";
+};
+
+&fpd_dma_chan1 {
+        status = "okay";
+};
+
+&fpd_dma_chan2 {
+        status = "okay";
+};
+
+&fpd_dma_chan3 {
+        status = "okay";
+};
+
+&fpd_dma_chan4 {
+        status = "okay";
+};
+
+&fpd_dma_chan5 {
+        status = "okay";
+};
+
+&fpd_dma_chan6 {
+        status = "okay";
+};
+
+&fpd_dma_chan7 {
+        status = "okay";
+};
+
+&fpd_dma_chan8 {
+        status = "okay";
+};
+
+&gem2 {
+        status = "okay";
+        phy-handle = <&phy0>;
+        phy-mode = "rgmii-id";
+        phy0: phy@5 {
+                reg = <5>;
+                ti,rx-internal-delay = <0x8>;
+                ti,tx-internal-delay = <0xa>;
+                ti,fifo-depth = <0x1>;
+        };
+};
+
+&gpio {
+        status = "okay";
+};
+
+&i2c0 {
+        status = "okay";
+        clock-frequency = <400000>;
+
+        tca6416_u26: gpio@20 {
+                compatible = "ti,tca6416";
+                reg = <0x20>;
+                gpio-controller;
+                #gpio-cells = <2>;
+                /* IRQ not connected */
+        };
+
+        rtc@68 {
+                compatible = "dallas,ds1339";
+                reg = <0x68>;
+        };
+};
+
+&rtc {
+        status = "okay";
+};
+
+&spi0 {
+        status = "okay";
+        num-cs = <1>;
+
+        spi0_flash0: flash0@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "sst,sst25wf080", "jedec,spi-nor";
+                spi-max-frequency = <50000000>;
+                reg = <0>;
+
+                partition@0 {
+                        label = "data";
+                        reg = <0x0 0x100000>;
+                };
+        };
+};
+
+&spi1 {
+        status = "okay";
+        num-cs = <1>;
+
+        spi1_flash0: flash0@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash";
+                spi-max-frequency = <20000000>;
+                reg = <0>;
+
+                partition@0 {
+                        label = "data";
+                        reg = <0x0 0x84000>;
+                };
+        };
+};
+
+/* ULPI SMSC USB3320 */
+&usb1 {
+        status = "okay";
+};
+
+&uart0 {
+        status = "okay";
+};
+
+&uart1 {
+        status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
new file mode 100644
index 000000000000..7a49deeae647
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP zc1751-xm017-dc3
+ *
+ * (C) Copyright 2016 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+
+/ {
+        model = "ZynqMP zc1751-xm017-dc3 RevA";
+        compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+        aliases {
+                ethernet0 = &gem0;
+                i2c0 = &i2c0;
+                i2c1 = &i2c1;
+                mmc0 = &sdhci1;
+                rtc0 = &rtc;
+                serial0 = &uart0;
+                serial1 = &uart1;
+        };
+
+        chosen {
+                bootargs = "earlycon";
+                stdout-path = "serial0:115200n8";
+        };
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+        };
+};
+
+&fpd_dma_chan1 {
+        status = "okay";
+};
+
+&fpd_dma_chan2 {
+        status = "okay";
+};
+
+&fpd_dma_chan3 {
+        status = "okay";
+};
+
+&fpd_dma_chan4 {
+        status = "okay";
+};
+
+&fpd_dma_chan5 {
+        status = "okay";
+};
+
+&fpd_dma_chan6 {
+        status = "okay";
+};
+
+&fpd_dma_chan7 {
+        status = "okay";
+};
+
+&fpd_dma_chan8 {
+        status = "okay";
+};
+
+&gem0 {
+        status = "okay";
+        phy-handle = <&phy0>;
+        phy-mode = "rgmii-id";
+        phy0: phy@0 { /* VSC8211 */
+                reg = <0>;
+        };
+};
+
+&gpio {
+        status = "okay";
+};
+
+/* just eeprom here */
+&i2c0 {
+        status = "okay";
+        clock-frequency = <400000>;
+
+        tca6416_u26: gpio@20 {
+                compatible = "ti,tca6416";
+                reg = <0x20>;
+                gpio-controller;
+                #gpio-cells = <2>;
+                /* IRQ not connected */
+        };
+
+        rtc@68 {
+                compatible = "dallas,ds1339";
+                reg = <0x68>;
+        };
+};
+
+/* eeprom24c02 and SE98A temp chip pca9306 */
+&i2c1 {
+        status = "okay";
+        clock-frequency = <400000>;
+};
+
+&rtc {
+        status = "okay";
+};
+
+&sata {
+        status = "okay";
+        /* SATA phy OOB timing settings */
+        ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
+        ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
+        ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+        ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+        ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
+        ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
+        ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+        ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+&sdhci1 { /* emmc with some settings */
+        status = "okay";
+};
+
+/* main */
+&uart0 {
+        status = "okay";
+};
+
+/* DB9 */
+&uart1 {
+        status = "okay";
+};
+
+&usb0 {
+        status = "okay";
+        dr_mode = "host";
+};
+
+/* ULPI SMSC USB3320 */
+&usb1 {
+        status = "okay";
+        dr_mode = "host";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
new file mode 100644
index 000000000000..54c7b4f1d1e4
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
@@ -0,0 +1,178 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP zc1751-xm018-dc4
+ *
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+
+/ {
+        model = "ZynqMP zc1751-xm018-dc4";
+        compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+        aliases {
+                ethernet0 = &gem0;
+                ethernet1 = &gem1;
+                ethernet2 = &gem2;
+                ethernet3 = &gem3;
+                i2c0 = &i2c0;
+                i2c1 = &i2c1;
+                rtc0 = &rtc;
+                serial0 = &uart0;
+                serial1 = &uart1;
+        };
+
+        chosen {
+                bootargs = "earlycon";
+                stdout-path = "serial0:115200n8";
+        };
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+        };
+};
+
+&can0 {
+        status = "okay";
+};
+
+&can1 {
+        status = "okay";
+};
+
+&fpd_dma_chan1 {
+        status = "okay";
+};
+
+&fpd_dma_chan2 {
+        status = "okay";
+};
+
+&fpd_dma_chan3 {
+        status = "okay";
+};
+
+&fpd_dma_chan4 {
+        status = "okay";
+};
+
+&fpd_dma_chan5 {
+        status = "okay";
+};
+
+&fpd_dma_chan6 {
+        status = "okay";
+};
+
+&fpd_dma_chan7 {
+        status = "okay";
+};
+
+&fpd_dma_chan8 {
+        status = "okay";
+};
+
+&lpd_dma_chan1 {
+        status = "okay";
+};
+
+&lpd_dma_chan2 {
+        status = "okay";
+};
+
+&lpd_dma_chan3 {
+        status = "okay";
+};
+
+&lpd_dma_chan4 {
+        status = "okay";
+};
+
+&lpd_dma_chan5 {
+        status = "okay";
+};
+
+&lpd_dma_chan6 {
+        status = "okay";
+};
+
+&lpd_dma_chan7 {
+        status = "okay";
+};
+
+&lpd_dma_chan8 {
+        status = "okay";
+};
+
+&gem0 {
+        status = "okay";
+        phy-mode = "rgmii-id";
+        phy-handle = <&ethernet_phy0>;
+        ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */
+                reg = <0>;
+        };
+        ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */
+                reg = <7>;
+        };
+        ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */
+                reg = <3>;
+        };
+        ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */
+                reg = <8>;
+        };
+};
+
+&gem1 {
+        status = "okay";
+        phy-mode = "rgmii-id";
+        phy-handle = <&ethernet_phy7>;
+};
+
+&gem2 {
+        status = "okay";
+        phy-mode = "rgmii-id";
+        phy-handle = <&ethernet_phy3>;
+};
+
+&gem3 {
+        status = "okay";
+        phy-mode = "rgmii-id";
+        phy-handle = <&ethernet_phy8>;
+};
+
+&gpio {
+        status = "okay";
+};
+
+&i2c0 {
+        clock-frequency = <400000>;
+        status = "okay";
+};
+
+&i2c1 {
+        clock-frequency = <400000>;
+        status = "okay";
+};
+
+&rtc {
+        status = "okay";
+};
+
+&uart0 {
+        status = "okay";
+};
+
+&uart1 {
+        status = "okay";
+};
+
+&watchdog0 {
+        status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
new file mode 100644
index 000000000000..b8b5ff13818d
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP zc1751-xm019-dc5
+ *
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ *
+ * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+        model = "ZynqMP zc1751-xm019-dc5 RevA";
+        compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+        aliases {
+                ethernet0 = &gem1;
+                i2c0 = &i2c0;
+                i2c1 = &i2c1;
+                mmc0 = &sdhci0;
+                serial0 = &uart0;
+                serial1 = &uart1;
+        };
+
+        chosen {
+                bootargs = "earlycon";
+                stdout-path = "serial0:115200n8";
+        };
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+        };
+};
+
+&fpd_dma_chan1 {
+        status = "okay";
+};
+
+&fpd_dma_chan2 {
+        status = "okay";
+};
+
+&fpd_dma_chan3 {
+        status = "okay";
+};
+
+&fpd_dma_chan4 {
+        status = "okay";
+};
+
+&fpd_dma_chan5 {
+        status = "okay";
+};
+
+&fpd_dma_chan6 {
+        status = "okay";
+};
+
+&fpd_dma_chan7 {
+        status = "okay";
+};
+
+&fpd_dma_chan8 {
+        status = "okay";
+};
+
+&gem1 {
+        status = "okay";
+        phy-handle = <&phy0>;
+        phy-mode = "rgmii-id";
+        phy0: phy@0 {
+                reg = <0>;
+        };
+};
+
+&gpio {
+        status = "okay";
+};
+
+&i2c0 {
+        status = "okay";
+};
+
+&i2c1 {
+        status = "okay";
+};
+
+&sdhci0 {
+        status = "okay";
+        no-1-8-v;
+};
+
+&ttc0 {
+        status = "okay";
+};
+
+&ttc1 {
+        status = "okay";
+};
+
+&ttc2 {
+        status = "okay";
+};
+
+&ttc3 {
+        status = "okay";
+};
+
+&uart0 {
+        status = "okay";
+};
+
+&uart1 {
+        status = "okay";
+};
+
+&watchdog0 {
+        status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
new file mode 100644
index 000000000000..3e862a9faf26
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
@@ -0,0 +1,289 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU100 revC
+ *
+ * (C) Copyright 2016 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ * Nathalie Chan King Choy
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+        model = "ZynqMP ZCU100 RevC";
+        compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp";
+
+        aliases {
+                i2c0 = &i2c1;
+                rtc0 = &rtc;
+                serial0 = &uart1;
+                serial1 = &uart0;
+                serial2 = &dcc;
+                spi0 = &spi0;
+                spi1 = &spi1;
+                mmc0 = &sdhci0;
+                mmc1 = &sdhci1;
+        };
+
+        chosen {
+                bootargs = "earlycon";
+                stdout-path = "serial0:115200n8";
+        };
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x0 0x0 0x80000000>;
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                autorepeat;
+                sw4 {
+                        label = "sw4";
+                        gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_POWER>;
+                        gpio-key,wakeup;
+                        autorepeat;
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                ds2 {
+                        label = "ds2";
+                        gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "heartbeat";
+                };
+
+                ds3 {
+                        label = "ds3";
+                        gpios = <&gpio 19 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "phy0tx"; /* WLAN tx */
+                        default-state = "off";
+                };
+
+                ds4 {
+                        label = "ds4";
+                        gpios = <&gpio 18 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "phy0rx"; /* WLAN rx */
+                        default-state = "off";
+                };
+
+                ds5 {
+                        label = "ds5";
+                        gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "bluetooth-power";
+                };
+
+                vbus_det { /* U5 USB5744 VBUS detection via MIO25 */
+                        label = "vbus_det";
+                        gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
+                        default-state = "on";
+                };
+
+                bt_power {
+                        label = "bt_power";
+                        gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
+                        default-state = "on";
+                };
+        };
+
+        wmmcsdio_fixed: fixedregulator-mmcsdio {
+                compatible = "regulator-fixed";
+                regulator-name = "wmmcsdio_fixed";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+                regulator-boot-on;
+        };
+
+        sdio_pwrseq: sdio_pwrseq {
+                compatible = "mmc-pwrseq-simple";
+                reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */
+        };
+};
+
+&dcc {
+        status = "okay";
+};
+
+&gpio {
+        status = "okay";
+        gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL",
+                          "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS",
+                          "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1",
+                          "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1",
+                          "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT",
+                          "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE",
+                          "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL",
+                          "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C",
+                          "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E",
+                          "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3",
+                          "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2",
+                          "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3",
+                          "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK",
+                          "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1",
+                          "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6",
+                          "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */
+                          "", "",
+                          "", "", "", "", "", "", "", "", "", "",
+                          "", "", "", "", "", "", "", "", "", "",
+                          "", "", "", "", "", "", "", "", "", "",
+                          "", "", "", "", "", "", "", "", "", "",
+                          "", "", "", "", "", "", "", "", "", "",
+                          "", "", "", "", "", "", "", "", "", "",
+                          "", "", "", "", "", "", "", "", "", "",
+                          "", "", "", "", "", "", "", "", "", "",
+                          "", "", "", "", "", "", "", "", "", "",
+                          "", "", "", "";
+};
+
+&i2c1 {
+        status = "okay";
+        clock-frequency = <100000>;
+        i2c-mux@75 { /* u11 */
+                compatible = "nxp,pca9548";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <0x75>;
+                i2csw_0: i2c@0 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0>;
+                        label = "LS-I2C0";
+                };
+                i2csw_1: i2c@1 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <1>;
+                        label = "LS-I2C1";
+                };
+                i2csw_2: i2c@2 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <2>;
+                        label = "HS-I2C2";
+                };
+                i2csw_3: i2c@3 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <3>;
+                        label = "HS-I2C3";
+                };
+                i2csw_4: i2c@4 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x4>;
+
+                        pmic: pmic@5e { /* Custom TI PMIC u33 */
+                                compatible = "ti,tps65086";
+                                reg = <0x5e>;
+                                interrupt-parent = <&gpio>;
+                                interrupts = <77 GPIO_ACTIVE_LOW>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                        };
+                };
+                i2csw_5: i2c@5 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <5>;
+                        /* PS_PMBUS */
+                        ina226@40 { /* u35 */
+                                compatible = "ti,ina226";
+                                reg = <0x40>;
+                                shunt-resistor = <10000>;
+                                /* MIO31 is alert which should be routed to PMUFW */
+                        };
+                };
+                i2csw_6: i2c@6 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <6>;
+                        /*
+                         * Not Connected
+                         */
+                };
+                i2csw_7: i2c@7 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <7>;
+                        /*
+                         * usb5744 (DNP) - U5
+                         * 100kHz - this is default freq for us
+                         */
+                };
+        };
+};
+
+&rtc {
+        status = "okay";
+};
+
+/* SD0 only supports 3.3V, no level shifter */
+&sdhci0 {
+        status = "okay";
+        no-1-8-v;
+        broken-cd; /* CD has to be enabled by default */
+        disable-wp;
+};
+
+&sdhci1 {
+        status = "okay";
+        bus-width = <0x4>;
+        non-removable;
+        disable-wp;
+        cap-power-off-card;
+        mmc-pwrseq = <&sdio_pwrseq>;
+        vqmmc-supply = <&wmmcsdio_fixed>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        wlcore: wifi@2 {
+                compatible = "ti,wl1831";
+                reg = <2>;
+                interrupt-parent = <&gpio>;
+                interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */
+        };
+};
+
+&spi0 { /* Low Speed connector */
+        status = "okay";
+        label = "LS-SPI0";
+};
+
+&spi1 { /* High Speed connector */
+        status = "okay";
+        label = "HS-SPI1";
+};
+
+&uart0 {
+        status = "okay";
+};
+
+&uart1 {
+        status = "okay";
+
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+        status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb1 {
+        status = "okay";
+};
+
+&watchdog0 {
+        status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
new file mode 100644
index 000000000000..6647e97edba3
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU102 Rev1.0
+ *
+ * (C) Copyright 2016 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+#include "zynqmp-zcu102-revB.dts"
+
+/ {
+        model = "ZynqMP ZCU102 Rev1.0";
+        compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
+};
+
+&eeprom {
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        board_sn: board-sn@0 {
+                reg = <0x0 0x14>;
+        };
+
+        eth_mac: eth-mac@20 {
+                reg = <0x20 0x6>;
+        };
+
+        board_name: board-name@d0 {
+                reg = <0xd0 0x6>;
+        };
+
+        board_revision: board-revision@e0 {
+                reg = <0xe0 0x3>;
+        };
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
new file mode 100644
index 000000000000..5b4ffe646a9b
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
@@ -0,0 +1,548 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU102 RevA
+ *
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+        model = "ZynqMP ZCU102 RevA";
+        compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
+
+        aliases {
+                ethernet0 = &gem3;
+                i2c0 = &i2c0;
+                i2c1 = &i2c1;
+                mmc0 = &sdhci1;
+                rtc0 = &rtc;
+                serial0 = &uart0;
+                serial1 = &uart1;
+                serial2 = &dcc;
+        };
+
+        chosen {
+                bootargs = "earlycon";
+                stdout-path = "serial0:115200n8";
+        };
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                autorepeat;
+                sw19 {
+                        label = "sw19";
+                        gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
+                        linux,code = <KEY_DOWN>;
+                        gpio-key,wakeup;
+                        autorepeat;
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                heartbeat_led {
+                        label = "heartbeat";
+                        gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+};
+
+&can1 {
+        status = "okay";
+};
+
+&dcc {
+        status = "okay";
+};
+
+&fpd_dma_chan1 {
+        status = "okay";
+};
+
+&fpd_dma_chan2 {
+        status = "okay";
+};
+
+&fpd_dma_chan3 {
+        status = "okay";
+};
+
+&fpd_dma_chan4 {
+        status = "okay";
+};
+
+&fpd_dma_chan5 {
+        status = "okay";
+};
+
+&fpd_dma_chan6 {
+        status = "okay";
+};
+
+&fpd_dma_chan7 {
+        status = "okay";
+};
+
+&fpd_dma_chan8 {
+        status = "okay";
+};
+
+&gem3 {
+        status = "okay";
+        phy-handle = <&phy0>;
+        phy-mode = "rgmii-id";
+        phy0: phy@21 {
+                reg = <21>;
+                ti,rx-internal-delay = <0x8>;
+                ti,tx-internal-delay = <0xa>;
+                ti,fifo-depth = <0x1>;
+        };
+};
+
+&gpio {
+        status = "okay";
+};
+
+&i2c0 {
+        status = "okay";
+        clock-frequency = <400000>;
+
+        tca6416_u97: gpio@20 {
+                compatible = "ti,tca6416";
+                reg = <0x20>;
+                gpio-controller;
+                #gpio-cells = <2>;
+                /*
+                 * IRQ not connected
+                 * Lines:
+                 * 0 - PS_GTR_LAN_SEL0
+                 * 1 - PS_GTR_LAN_SEL1
+                 * 2 - PS_GTR_LAN_SEL2
+                 * 3 - PS_GTR_LAN_SEL3
+                 * 4 - PCI_CLK_DIR_SEL
+                 * 5 - IIC_MUX_RESET_B
+                 * 6 - GEM3_EXP_RESET_B
+                 * 7, 10 - 17 - not connected
+                 */
+
+                gtr_sel0 {
+                        gpio-hog;
+                        gpios = <0 0>;
+                        output-low; /* PCIE = 0, DP = 1 */
+                        line-name = "sel0";
+                };
+                gtr_sel1 {
+                        gpio-hog;
+                        gpios = <1 0>;
+                        output-high; /* PCIE = 0, DP = 1 */
+                        line-name = "sel1";
+                };
+                gtr_sel2 {
+                        gpio-hog;
+                        gpios = <2 0>;
+                        output-high; /* PCIE = 0, USB0 = 1 */
+                        line-name = "sel2";
+                };
+                gtr_sel3 {
+                        gpio-hog;
+                        gpios = <3 0>;
+                        output-high; /* PCIE = 0, SATA = 1 */
+                        line-name = "sel3";
+                };
+        };
+
+        tca6416_u61: gpio@21 {
+                compatible = "ti,tca6416";
+                reg = <0x21>;
+                gpio-controller;
+                #gpio-cells = <2>;
+                /*
+                 * IRQ not connected
+                 * Lines:
+                 * 0 - VCCPSPLL_EN
+                 * 1 - MGTRAVCC_EN
+                 * 2 - MGTRAVTT_EN
+                 * 3 - VCCPSDDRPLL_EN
+                 * 4 - MIO26_PMU_INPUT_LS
+                 * 5 - PL_PMBUS_ALERT
+                 * 6 - PS_PMBUS_ALERT
+                 * 7 - MAXIM_PMBUS_ALERT
+                 * 10 - PL_DDR4_VTERM_EN
+                 * 11 - PL_DDR4_VPP_2V5_EN
+                 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
+                 * 13 - PS_DIMM_SUSPEND_EN
+                 * 14 - PS_DDR4_VTERM_EN
+                 * 15 - PS_DDR4_VPP_2V5_EN
+                 * 16 - 17 - not connected
+                 */
+        };
+
+        i2c-mux@75 { /* u60 */
+                compatible = "nxp,pca9544";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <0x75>;
+                i2c@0 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0>;
+                        /* PS_PMBUS */
+                        ina226@40 { /* u76 */
+                                compatible = "ti,ina226";
+                                reg = <0x40>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@41 { /* u77 */
+                                compatible = "ti,ina226";
+                                reg = <0x41>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@42 { /* u78 */
+                                compatible = "ti,ina226";
+                                reg = <0x42>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@43 { /* u87 */
+                                compatible = "ti,ina226";
+                                reg = <0x43>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@44 { /* u85 */
+                                compatible = "ti,ina226";
+                                reg = <0x44>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@45 { /* u86 */
+                                compatible = "ti,ina226";
+                                reg = <0x45>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@46 { /* u93 */
+                                compatible = "ti,ina226";
+                                reg = <0x46>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@47 { /* u88 */
+                                compatible = "ti,ina226";
+                                reg = <0x47>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@4a { /* u15 */
+                                compatible = "ti,ina226";
+                                reg = <0x4a>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@4b { /* u92 */
+                                compatible = "ti,ina226";
+                                reg = <0x4b>;
+                                shunt-resistor = <5000>;
+                        };
+                };
+                i2c@1 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <1>;
+                        /* PL_PMBUS */
+                        ina226@40 { /* u79 */
+                                compatible = "ti,ina226";
+                                reg = <0x40>;
+                                shunt-resistor = <2000>;
+                        };
+                        ina226@41 { /* u81 */
+                                compatible = "ti,ina226";
+                                reg = <0x41>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@42 { /* u80 */
+                                compatible = "ti,ina226";
+                                reg = <0x42>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@43 { /* u84 */
+                                compatible = "ti,ina226";
+                                reg = <0x43>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@44 { /* u16 */
+                                compatible = "ti,ina226";
+                                reg = <0x44>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@45 { /* u65 */
+                                compatible = "ti,ina226";
+                                reg = <0x45>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@46 { /* u74 */
+                                compatible = "ti,ina226";
+                                reg = <0x46>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@47 { /* u75 */
+                                compatible = "ti,ina226";
+                                reg = <0x47>;
+                                shunt-resistor = <5000>;
+                        };
+                };
+                i2c@2 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <2>;
+                        /* MAXIM_PMBUS - 00 */
+                        max15301@a { /* u46 */
+                                compatible = "maxim,max15301";
+                                reg = <0xa>;
+                        };
+                        max15303@b { /* u4 */
+                                compatible = "maxim,max15303";
+                                reg = <0xb>;
+                        };
+                        max15303@10 { /* u13 */
+                                compatible = "maxim,max15303";
+                                reg = <0x10>;
+                        };
+                        max15301@13 { /* u47 */
+                                compatible = "maxim,max15301";
+                                reg = <0x13>;
+                        };
+                        max15303@14 { /* u7 */
+                                compatible = "maxim,max15303";
+                                reg = <0x14>;
+                        };
+                        max15303@15 { /* u6 */
+                                compatible = "maxim,max15303";
+                                reg = <0x15>;
+                        };
+                        max15303@16 { /* u10 */
+                                compatible = "maxim,max15303";
+                                reg = <0x16>;
+                        };
+                        max15303@17 { /* u9 */
+                                compatible = "maxim,max15303";
+                                reg = <0x17>;
+                        };
+                        max15301@18 { /* u63 */
+                                compatible = "maxim,max15301";
+                                reg = <0x18>;
+                        };
+                        max15303@1a { /* u49 */
+                                compatible = "maxim,max15303";
+                                reg = <0x1a>;
+                        };
+                        max15303@1d { /* u18 */
+                                compatible = "maxim,max15303";
+                                reg = <0x1d>;
+                        };
+                        max15303@20 { /* u8 */
+                                compatible = "maxim,max15303";
+                                status = "disabled"; /* unreachable */
+                                reg = <0x20>;
+                        };
+
+                        max20751@72 { /* u95 */
+                                compatible = "maxim,max20751";
+                                reg = <0x72>;
+                        };
+                        max20751@73 { /* u96 */
+                                compatible = "maxim,max20751";
+                                reg = <0x73>;
+                        };
+                };
+                /* Bus 3 is not connected */
+        };
+};
+
+&i2c1 {
+        status = "okay";
+        clock-frequency = <400000>;
+
+        /* PL i2c via PCA9306 - u45 */
+        i2c-mux@74 { /* u34 */
+                compatible = "nxp,pca9548";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <0x74>;
+                i2c@0 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0>;
+                        /*
+                         * IIC_EEPROM 1kB memory which uses 256B blocks
+                         * where every block has different address.
+                         *    0 - 256B address 0x54
+                         * 256B - 512B address 0x55
+                         * 512B - 768B address 0x56
+                         * 768B - 1024B address 0x57
+                         */
+                        eeprom: eeprom@54 { /* u23 */
+                                compatible = "atmel,24c08";
+                                reg = <0x54>;
+                        };
+                };
+                i2c@1 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <1>;
+                        si5341: clock-generator@36 { /* SI5341 - u69 */
+                                reg = <0x36>;
+                        };
+
+                };
+                i2c@2 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <2>;
+                        si570_1: clock-generator@5d { /* USER SI570 - u42 */
+                                #clock-cells = <0>;
+                                compatible = "silabs,si570";
+                                reg = <0x5d>;
+                                temperature-stability = <50>;
+                                factory-fout = <300000000>;
+                                clock-frequency = <300000000>;
+                        };
+                };
+                i2c@3 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <3>;
+                        si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
+                                #clock-cells = <0>;
+                                compatible = "silabs,si570";
+                                reg = <0x5d>;
+                                temperature-stability = <50>; /* copy from zc702 */
+                                factory-fout = <156250000>;
+                                clock-frequency = <148500000>;
+                        };
+                };
+                i2c@4 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <4>;
+                        si5328: clock-generator@69 {/* SI5328 - u20 */
+                                reg = <0x69>;
+                                /*
+                                 * Chip has interrupt present connected to PL
+                                 * interrupt-parent = <&>;
+                                 * interrupts = <>;
+                                 */
+                        };
+                };
+                /* 5 - 7 unconnected */
+        };
+
+        i2c-mux@75 {
+                compatible = "nxp,pca9548"; /* u135 */
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <0x75>;
+
+                i2c@0 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0>;
+                        /* HPC0_IIC */
+                };
+                i2c@1 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <1>;
+                        /* HPC1_IIC */
+                };
+                i2c@2 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <2>;
+                        /* SYSMON */
+                };
+                i2c@3 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <3>;
+                        /* DDR4 SODIMM */
+                };
+                i2c@4 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <4>;
+                        /* SEP 3 */
+                };
+                i2c@5 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <5>;
+                        /* SEP 2 */
+                };
+                i2c@6 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <6>;
+                        /* SEP 1 */
+                };
+                i2c@7 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <7>;
+                        /* SEP 0 */
+                };
+        };
+};
+
+&pcie {
+        status = "okay";
+};
+
+&rtc {
+        status = "okay";
+};
+
+&sata {
+        status = "okay";
+        /* SATA OOB timing settings */
+        ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+        ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+        ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+        ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+        ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+        ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+        ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+        ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+        status = "okay";
+        no-1-8-v;
+};
+
+&uart0 {
+        status = "okay";
+};
+
+&uart1 {
+        status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+        status = "okay";
+};
+
+&watchdog0 {
+        status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
new file mode 100644
index 000000000000..af4d86882a5c
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU102 RevB
+ *
+ * (C) Copyright 2016 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+#include "zynqmp-zcu102-revA.dts"
+
+/ {
+        model = "ZynqMP ZCU102 RevB";
+        compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
+};
+
+&gem3 {
+        phy-handle = <&phyc>;
+        phyc: phy@c {
+                reg = <0xc>;
+                ti,rx-internal-delay = <0x8>;
+                ti,tx-internal-delay = <0xa>;
+                ti,fifo-depth = <0x1>;
+        };
+        /* Cleanup from RevA */
+        /delete-node/ phy@21;
+};
+
+/* Fix collision with u61 */
+&i2c0 {
+        i2c-mux@75 {
+                i2c@2 {
+                        max15303@1b { /* u8 */
+                                compatible = "maxim,max15303";
+                                reg = <0x1b>;
+                        };
+                        /delete-node/ max15303@20;
+                };
+        };
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
new file mode 100644
index 000000000000..d4ad19a38c93
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
@@ -0,0 +1,195 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU104
+ *
+ * (C) Copyright 2017 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+        model = "ZynqMP ZCU104 RevA";
+        compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
+
+        aliases {
+                ethernet0 = &gem3;
+                i2c0 = &i2c1;
+                mmc0 = &sdhci1;
+                rtc0 = &rtc;
+                serial0 = &uart0;
+                serial1 = &uart1;
+                serial2 = &dcc;
+        };
+
+        chosen {
+                bootargs = "earlycon";
+                stdout-path = "serial0:115200n8";
+        };
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x0 0x0 0x80000000>;
+        };
+};
+
+&can1 {
+        status = "okay";
+};
+
+&dcc {
+        status = "okay";
+};
+
+&gem3 {
+        status = "okay";
+        phy-handle = <&phy0>;
+        phy-mode = "rgmii-id";
+        phy0: phy@c {
+                reg = <0xc>;
+                ti,rx-internal-delay = <0x8>;
+                ti,tx-internal-delay = <0xa>;
+                ti,fifo-depth = <0x1>;
+        };
+};
+
+&gpio {
+        status = "okay";
+};
+
+&i2c1 {
+        status = "okay";
+        clock-frequency = <400000>;
+
+        /* Another connection to this bus via PL i2c via PCA9306 - u45 */
+        i2c-mux@74 { /* u34 */
+                compatible = "nxp,pca9548";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <0x74>;
+                i2c@0 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0>;
+                        /*
+                         * IIC_EEPROM 1kB memory which uses 256B blocks
+                         * where every block has different address.
+                         *    0 - 256B address 0x54
+                         * 256B - 512B address 0x55
+                         * 512B - 768B address 0x56
+                         * 768B - 1024B address 0x57
+                         */
+                        eeprom@54 { /* u23 */
+                                compatible = "atmel,24c08";
+                                reg = <0x54>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                        };
+                };
+
+                i2c@1 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <1>;
+                        clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */
+                                reg = <0x6c>;
+                        };
+                };
+
+                i2c@2 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <2>;
+                        irps5401_43: irps54012@43 { /* IRPS5401 - u175 */
+                                reg = <0x43>;
+                        };
+                        irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */
+                                reg = <0x4d>;
+                        };
+                };
+
+                i2c@4 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <4>;
+                        tca6416_u97: gpio@21 {
+                                compatible = "ti,tca6416";
+                                reg = <0x21>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                /*
+                                 * IRQ not connected
+                                 * Lines:
+                                 * 0 - IRPS5401_ALERT_B
+                                 * 1 - HDMI_8T49N241_INT_ALM
+                                 * 2 - MAX6643_OT_B
+                                 * 3 - MAX6643_FANFAIL_B
+                                 * 5 - IIC_MUX_RESET_B
+                                 * 6 - GEM3_EXP_RESET_B
+                                 * 7 - FMC_LPC_PRSNT_M2C_B
+                                 * 4, 10 - 17 - not connected
+                                 */
+                        };
+                };
+
+                i2c@5 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <5>;
+                };
+
+                i2c@7 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <7>;
+                };
+
+                /* 3, 6 not connected */
+        };
+};
+
+&rtc {
+        status = "okay";
+};
+
+&sata {
+        status = "okay";
+        /* SATA OOB timing settings */
+        ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+        ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+        ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+        ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+        ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+        ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+        ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+        ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+        status = "okay";
+        no-1-8-v;
+        disable-wp;
+};
+
+&uart0 {
+        status = "okay";
+};
+
+&uart1 {
+        status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+        status = "okay";
+};
+
+&watchdog0 {
+        status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
new file mode 100644
index 000000000000..668f7f26716a
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
@@ -0,0 +1,522 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU106
+ *
+ * (C) Copyright 2016, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+        model = "ZynqMP ZCU106 RevA";
+        compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp";
+
+        aliases {
+                ethernet0 = &gem3;
+                i2c0 = &i2c0;
+                i2c1 = &i2c1;
+                mmc0 = &sdhci1;
+                rtc0 = &rtc;
+                serial0 = &uart0;
+                serial1 = &uart1;
+                serial2 = &dcc;
+        };
+
+        chosen {
+                bootargs = "earlycon";
+                stdout-path = "serial0:115200n8";
+        };
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                autorepeat;
+                sw19 {
+                        label = "sw19";
+                        gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
+                        linux,code = <KEY_DOWN>;
+                        gpio-key,wakeup;
+                        autorepeat;
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                heartbeat_led {
+                        label = "heartbeat";
+                        gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+};
+
+&can1 {
+        status = "okay";
+};
+
+&dcc {
+        status = "okay";
+};
+
+/* fpd_dma clk 667MHz, lpd_dma 500MHz */
+&fpd_dma_chan1 {
+        status = "okay";
+};
+
+&fpd_dma_chan2 {
+        status = "okay";
+};
+
+&fpd_dma_chan3 {
+        status = "okay";
+};
+
+&fpd_dma_chan4 {
+        status = "okay";
+};
+
+&fpd_dma_chan5 {
+        status = "okay";
+};
+
+&fpd_dma_chan6 {
+        status = "okay";
+};
+
+&fpd_dma_chan7 {
+        status = "okay";
+};
+
+&fpd_dma_chan8 {
+        status = "okay";
+};
+
+&gem3 {
+        status = "okay";
+        phy-handle = <&phy0>;
+        phy-mode = "rgmii-id";
+        phy0: phy@c {
+                reg = <0xc>;
+                ti,rx-internal-delay = <0x8>;
+                ti,tx-internal-delay = <0xa>;
+                ti,fifo-depth = <0x1>;
+        };
+};
+
+&gpio {
+        status = "okay";
+};
+
+&i2c0 {
+        status = "okay";
+        clock-frequency = <400000>;
+
+        tca6416_u97: gpio@20 {
+                compatible = "ti,tca6416";
+                reg = <0x20>;
+                gpio-controller; /* interrupt not connected */
+                #gpio-cells = <2>;
+                /*
+                 * IRQ not connected
+                 * Lines:
+                 * 0 - SFP_SI5328_INT_ALM
+                 * 1 - HDMI_SI5328_INT_ALM
+                 * 5 - IIC_MUX_RESET_B
+                 * 6 - GEM3_EXP_RESET_B
+                 * 10 - FMC_HPC0_PRSNT_M2C_B
+                 * 11 - FMC_HPC1_PRSNT_M2C_B
+                 * 2-4, 7, 12-17 - not connected
+                 */
+        };
+
+        tca6416_u61: gpio@21 {
+                compatible = "ti,tca6416";
+                reg = <0x21>;
+                gpio-controller;
+                #gpio-cells = <2>;
+                /*
+                 * IRQ not connected
+                 * Lines:
+                 * 0 - VCCPSPLL_EN
+                 * 1 - MGTRAVCC_EN
+                 * 2 - MGTRAVTT_EN
+                 * 3 - VCCPSDDRPLL_EN
+                 * 4 - MIO26_PMU_INPUT_LS
+                 * 5 - PL_PMBUS_ALERT
+                 * 6 - PS_PMBUS_ALERT
+                 * 7 - MAXIM_PMBUS_ALERT
+                 * 10 - PL_DDR4_VTERM_EN
+                 * 11 - PL_DDR4_VPP_2V5_EN
+                 * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
+                 * 13 - PS_DIMM_SUSPEND_EN
+                 * 14 - PS_DDR4_VTERM_EN
+                 * 15 - PS_DDR4_VPP_2V5_EN
+                 * 16 - 17 - not connected
+                 */
+        };
+
+        i2c-mux@75 { /* u60 */
+                compatible = "nxp,pca9544";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <0x75>;
+                i2c@0 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0>;
+                        /* PS_PMBUS */
+                        ina226@40 { /* u76 */
+                                compatible = "ti,ina226";
+                                reg = <0x40>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@41 { /* u77 */
+                                compatible = "ti,ina226";
+                                reg = <0x41>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@42 { /* u78 */
+                                compatible = "ti,ina226";
+                                reg = <0x42>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@43 { /* u87 */
+                                compatible = "ti,ina226";
+                                reg = <0x43>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@44 { /* u85 */
+                                compatible = "ti,ina226";
+                                reg = <0x44>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@45 { /* u86 */
+                                compatible = "ti,ina226";
+                                reg = <0x45>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@46 { /* u93 */
+                                compatible = "ti,ina226";
+                                reg = <0x46>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@47 { /* u88 */
+                                compatible = "ti,ina226";
+                                reg = <0x47>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@4a { /* u15 */
+                                compatible = "ti,ina226";
+                                reg = <0x4a>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@4b { /* u92 */
+                                compatible = "ti,ina226";
+                                reg = <0x4b>;
+                                shunt-resistor = <5000>;
+                        };
+                };
+                i2c@1 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <1>;
+                        /* PL_PMBUS */
+                        ina226@40 { /* u79 */
+                                compatible = "ti,ina226";
+                                reg = <0x40>;
+                                shunt-resistor = <2000>;
+                        };
+                        ina226@41 { /* u81 */
+                                compatible = "ti,ina226";
+                                reg = <0x41>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@42 { /* u80 */
+                                compatible = "ti,ina226";
+                                reg = <0x42>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@43 { /* u84 */
+                                compatible = "ti,ina226";
+                                reg = <0x43>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@44 { /* u16 */
+                                compatible = "ti,ina226";
+                                reg = <0x44>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@45 { /* u65 */
+                                compatible = "ti,ina226";
+                                reg = <0x45>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@46 { /* u74 */
+                                compatible = "ti,ina226";
+                                reg = <0x46>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@47 { /* u75 */
+                                compatible = "ti,ina226";
+                                reg = <0x47>;
+                                shunt-resistor = <5000>;
+                        };
+                };
+                i2c@2 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <2>;
+                        /* MAXIM_PMBUS - 00 */
+                        max15301@a { /* u46 */
+                                compatible = "maxim,max15301";
+                                reg = <0xa>;
+                        };
+                        max15303@b { /* u4 */
+                                compatible = "maxim,max15303";
+                                reg = <0xb>;
+                        };
+                        max15303@10 { /* u13 */
+                                compatible = "maxim,max15303";
+                                reg = <0x10>;
+                        };
+                        max15301@13 { /* u47 */
+                                compatible = "maxim,max15301";
+                                reg = <0x13>;
+                        };
+                        max15303@14 { /* u7 */
+                                compatible = "maxim,max15303";
+                                reg = <0x14>;
+                        };
+                        max15303@15 { /* u6 */
+                                compatible = "maxim,max15303";
+                                reg = <0x15>;
+                        };
+                        max15303@16 { /* u10 */
+                                compatible = "maxim,max15303";
+                                reg = <0x16>;
+                        };
+                        max15303@17 { /* u9 */
+                                compatible = "maxim,max15303";
+                                reg = <0x17>;
+                        };
+                        max15301@18 { /* u63 */
+                                compatible = "maxim,max15301";
+                                reg = <0x18>;
+                        };
+                        max15303@1a { /* u49 */
+                                compatible = "maxim,max15303";
+                                reg = <0x1a>;
+                        };
+                        max15303@1b { /* u8 */
+                                compatible = "maxim,max15303";
+                                reg = <0x1b>;
+                        };
+                        max15303@1d { /* u18 */
+                                compatible = "maxim,max15303";
+                                reg = <0x1d>;
+                        };
+
+                        max20751@72 { /* u95 */
+                                compatible = "maxim,max20751";
+                                reg = <0x72>;
+                        };
+                        max20751@73 { /* u96 */
+                                compatible = "maxim,max20751";
+                                reg = <0x73>;
+                        };
+                };
+                /* Bus 3 is not connected */
+        };
+};
+
+&i2c1 {
+        status = "okay";
+        clock-frequency = <400000>;
+
+        /* PL i2c via PCA9306 - u45 */
+        i2c-mux@74 { /* u34 */
+                compatible = "nxp,pca9548";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <0x74>;
+                i2c@0 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0>;
+                        /*
+                         * IIC_EEPROM 1kB memory which uses 256B blocks
+                         * where every block has different address.
+                         *    0 - 256B address 0x54
+                         * 256B - 512B address 0x55
+                         * 512B - 768B address 0x56
+                         * 768B - 1024B address 0x57
+                         */
+                        eeprom: eeprom@54 { /* u23 */
+                                compatible = "atmel,24c08";
+                                reg = <0x54>;
+                        };
+                };
+                i2c@1 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <1>;
+                        si5341: clock-generator@36 { /* SI5341 - u69 */
+                                reg = <0x36>;
+                        };
+
+                };
+                i2c@2 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <2>;
+                        si570_1: clock-generator@5d { /* USER SI570 - u42 */
+                                #clock-cells = <0>;
+                                compatible = "silabs,si570";
+                                reg = <0x5d>;
+                                temperature-stability = <50>;
+                                factory-fout = <300000000>;
+                                clock-frequency = <300000000>;
+                        };
+                };
+                i2c@3 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <3>;
+                        si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
+                                #clock-cells = <0>;
+                                compatible = "silabs,si570";
+                                reg = <0x5d>;
+                                temperature-stability = <50>; /* copy from zc702 */
+                                factory-fout = <156250000>;
+                                clock-frequency = <148500000>;
+                        };
+                };
+                i2c@4 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <4>;
+                        si5328: clock-generator@69 {/* SI5328 - u20 */
+                                reg = <0x69>;
+                        };
+                };
+                i2c@5 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <5>; /* FAN controller */
+                        temp@4c {/* lm96163 - u128 */
+                                compatible = "national,lm96163";
+                                reg = <0x4c>;
+                        };
+                };
+                /* 6 - 7 unconnected */
+        };
+
+        i2c-mux@75 {
+                compatible = "nxp,pca9548"; /* u135 */
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <0x75>;
+
+                i2c@0 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0>;
+                        /* HPC0_IIC */
+                };
+                i2c@1 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <1>;
+                        /* HPC1_IIC */
+                };
+                i2c@2 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <2>;
+                        /* SYSMON */
+                };
+                i2c@3 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <3>;
+                        /* DDR4 SODIMM */
+                };
+                i2c@4 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <4>;
+                        /* SEP 3 */
+                };
+                i2c@5 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <5>;
+                        /* SEP 2 */
+                };
+                i2c@6 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <6>;
+                        /* SEP 1 */
+                };
+                i2c@7 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <7>;
+                        /* SEP 0 */
+                };
+        };
+};
+
+&rtc {
+        status = "okay";
+};
+
+&sata {
+        status = "okay";
+        /* SATA OOB timing settings */
+        ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+        ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+        ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+        ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+        ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+        ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+        ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+        ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+        status = "okay";
+        no-1-8-v;
+};
+
+&uart0 {
+        status = "okay";
+};
+
+&uart1 {
+        status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+        status = "okay";
+};
+
+&watchdog0 {
+        status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
new file mode 100644
index 000000000000..9a9dd6a0142b
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
@@ -0,0 +1,444 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU111
+ *
+ * (C) Copyright 2017 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+        model = "ZynqMP ZCU111 RevA";
+        compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
+
+        aliases {
+                ethernet0 = &gem3;
+                i2c0 = &i2c0;
+                i2c1 = &i2c1;
+                mmc0 = &sdhci1;
+                rtc0 = &rtc;
+                serial0 = &uart0;
+                serial1 = &dcc;
+        };
+
+        chosen {
+                bootargs = "earlycon";
+                stdout-path = "serial0:115200n8";
+        };
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+                /* Another 4GB connected to PL */
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                autorepeat;
+                sw19 {
+                        label = "sw19";
+                        gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
+                        linux,code = <KEY_DOWN>;
+                        gpio-key,wakeup;
+                        autorepeat;
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                heartbeat_led {
+                        label = "heartbeat";
+                        gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+};
+
+&dcc {
+        status = "okay";
+};
+
+&fpd_dma_chan1 {
+        status = "okay";
+};
+
+&fpd_dma_chan2 {
+        status = "okay";
+};
+
+&fpd_dma_chan3 {
+        status = "okay";
+};
+
+&fpd_dma_chan4 {
+        status = "okay";
+};
+
+&fpd_dma_chan5 {
+        status = "okay";
+};
+
+&fpd_dma_chan6 {
+        status = "okay";
+};
+
+&fpd_dma_chan7 {
+        status = "okay";
+};
+
+&fpd_dma_chan8 {
+        status = "okay";
+};
+
+&gem3 {
+        status = "okay";
+        phy-handle = <&phy0>;
+        phy-mode = "rgmii-id";
+        phy0: phy@c {
+                reg = <0xc>;
+                ti,rx-internal-delay = <0x8>;
+                ti,tx-internal-delay = <0xa>;
+                ti,fifo-depth = <0x1>;
+        };
+};
+
+&gpio {
+        status = "okay";
+};
+
+&i2c0 {
+        status = "okay";
+        clock-frequency = <400000>;
+
+        tca6416_u22: gpio@20 {
+                compatible = "ti,tca6416";
+                reg = <0x20>;
+                gpio-controller; /* interrupt not connected */
+                #gpio-cells = <2>;
+                /*
+                 * IRQ not connected
+                 * Lines:
+                 * 0 - MAX6643_OT_B
+                 * 1 - MAX6643_FANFAIL_B
+                 * 2 - MIO26_PMU_INPUT_LS
+                 * 4 - SFP_SI5382_INT_ALM
+                 * 5 - IIC_MUX_RESET_B
+                 * 6 - GEM3_EXP_RESET_B
+                 * 10 - FMCP_HSPC_PRSNT_M2C_B
+                 * 11 - CLK_SPI_MUX_SEL0
+                 * 12 - CLK_SPI_MUX_SEL1
+                 * 16 - IRPS5401_ALERT_B
+                 * 17 - INA226_PMBUS_ALERT
+                 * 3, 7, 13-15 - not connected
+                 */
+        };
+
+        i2c-mux@75 { /* u23 */
+                compatible = "nxp,pca9544";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <0x75>;
+                i2c@0 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0>;
+                        /* PS_PMBUS */
+                        /* PMBUS_ALERT done via pca9544 */
+                        ina226@40 { /* u67 */
+                                compatible = "ti,ina226";
+                                reg = <0x40>;
+                                shunt-resistor = <2000>;
+                        };
+                        ina226@41 { /* u59 */
+                                compatible = "ti,ina226";
+                                reg = <0x41>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@42 { /* u61 */
+                                compatible = "ti,ina226";
+                                reg = <0x42>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@43 { /* u60 */
+                                compatible = "ti,ina226";
+                                reg = <0x43>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@45 { /* u64 */
+                                compatible = "ti,ina226";
+                                reg = <0x45>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@46 { /* u69 */
+                                compatible = "ti,ina226";
+                                reg = <0x46>;
+                                shunt-resistor = <2000>;
+                        };
+                        ina226@47 { /* u66 */
+                                compatible = "ti,ina226";
+                                reg = <0x47>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@48 { /* u65 */
+                                compatible = "ti,ina226";
+                                reg = <0x48>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@49 { /* u63 */
+                                compatible = "ti,ina226";
+                                reg = <0x49>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@4a { /* u3 */
+                                compatible = "ti,ina226";
+                                reg = <0x4a>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@4b { /* u71 */
+                                compatible = "ti,ina226";
+                                reg = <0x4b>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@4c { /* u77 */
+                                compatible = "ti,ina226";
+                                reg = <0x4c>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@4d { /* u73 */
+                                compatible = "ti,ina226";
+                                reg = <0x4d>;
+                                shunt-resistor = <5000>;
+                        };
+                        ina226@4e { /* u79 */
+                                compatible = "ti,ina226";
+                                reg = <0x4e>;
+                                shunt-resistor = <5000>;
+                        };
+                };
+                i2c@1 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <1>;
+                        /* NC */
+                };
+                i2c@2 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <2>;
+                        irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */
+                                reg = <0x43>;
+                        };
+                        irps5401_44: irps54012@44 { /* IRPS5401 - u55 */
+                                reg = <0x44>;
+                        };
+                        irps5401_45: irps54012@45 { /* IRPS5401 - u57 */
+                                reg = <0x45>;
+                        };
+                        /* u68 IR38064 +0 */
+                        /* u70 IR38060 +1 */
+                        /* u74 IR38060 +2 */
+                        /* u75 IR38060 +6 */
+                        /* J19 header too */
+
+                };
+                i2c@3 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <3>;
+                        /* SYSMON */
+                };
+        };
+};
+
+&i2c1 {
+        status = "okay";
+        clock-frequency = <400000>;
+
+        i2c-mux@74 { /* u26 */
+                compatible = "nxp,pca9548";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <0x74>;
+                i2c@0 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0>;
+                        /*
+                         * IIC_EEPROM 1kB memory which uses 256B blocks
+                         * where every block has different address.
+                         *    0 - 256B address 0x54
+                         * 256B - 512B address 0x55
+                         * 512B - 768B address 0x56
+                         * 768B - 1024B address 0x57
+                         */
+                        eeprom: eeprom@54 { /* u88 */
+                                compatible = "atmel,24c08";
+                                reg = <0x54>;
+                        };
+                };
+                i2c@1 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <1>;
+                        si5341: clock-generator@36 { /* SI5341 - u46 */
+                                reg = <0x36>;
+                        };
+
+                };
+                i2c@2 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <2>;
+                        si570_1: clock-generator@5d { /* USER SI570 - u47 */
+                                #clock-cells = <0>;
+                                compatible = "silabs,si570";
+                                reg = <0x5d>;
+                                temperature-stability = <50>;
+                                factory-fout = <300000000>;
+                                clock-frequency = <300000000>;
+                        };
+                };
+                i2c@3 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <3>;
+                        si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */
+                                #clock-cells = <0>;
+                                compatible = "silabs,si570";
+                                reg = <0x5d>;
+                                temperature-stability = <50>;
+                                factory-fout = <156250000>;
+                                clock-frequency = <148500000>;
+                        };
+                };
+                i2c@4 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <4>;
+                        si5328: clock-generator@69 { /* SI5328 - u48 */
+                                reg = <0x69>;
+                        };
+                };
+                i2c@5 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <5>;
+                                sc18is603@2f { /* sc18is602 - u93 */
+                                        compatible = "nxp,sc18is603";
+                                        reg = <0x2f>;
+                                        /* 4 gpios for CS not handled by driver */
+                                        /*
+                                         * USB2ANY cable or
+                                         * LMK04208 - u90 or
+                                         * LMX2594 - u102 or
+                                         * LMX2594 - u103 or
+                                         * LMX2594 - u104
+                                         */
+                                };
+                };
+                i2c@6 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <6>;
+                        /* FMC connector */
+                };
+                /* 7 NC */
+        };
+
+        i2c-mux@75 {
+                compatible = "nxp,pca9548"; /* u27 */
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <0x75>;
+
+                i2c@0 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0>;
+                        /* FMCP_HSPC_IIC */
+                };
+                i2c@1 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <1>;
+                        /* NC */
+                };
+                i2c@2 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <2>;
+                        /* SYSMON */
+                };
+                i2c@3 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <3>;
+                        /* DDR4 SODIMM */
+                };
+                i2c@4 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <4>;
+                        /* SFP3 */
+                };
+                i2c@5 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <5>;
+                        /* SFP2 */
+                };
+                i2c@6 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <6>;
+                        /* SFP1 */
+                };
+                i2c@7 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <7>;
+                        /* SFP0 */
+                };
+        };
+};
+
+&rtc {
+        status = "okay";
+};
+
+&sata {
+        status = "okay";
+        /* SATA OOB timing settings */
+        ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+        ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+        ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+        ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+        ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+        ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+        ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+        ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+        status = "okay";
+        no-1-8-v;
+};
+
+&uart0 {
+        status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+        status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 7665fbddff28..a091e6f03014 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * dts file for Xilinx ZynqMP
  *
@@ -355,7 +356,7 @@
                 };
 
                 gem0: ethernet@ff0b0000 {
-                        compatible = "cdns,gem";
+                        compatible = "cdns,zynqmp-gem", "cdns,gem";
                         status = "disabled";
                         interrupt-parent = <&gic>;
                         interrupts = <0 57 4>, <0 57 4>;
@@ -366,7 +367,7 @@
                 };
 
                 gem1: ethernet@ff0c0000 {
-                        compatible = "cdns,gem";
+                        compatible = "cdns,zynqmp-gem", "cdns,gem";
                         status = "disabled";
                         interrupt-parent = <&gic>;
                         interrupts = <0 59 4>, <0 59 4>;
@@ -377,7 +378,7 @@
                 };
 
                 gem2: ethernet@ff0d0000 {
-                        compatible = "cdns,gem";
+                        compatible = "cdns,zynqmp-gem", "cdns,gem";
                         status = "disabled";
                         interrupt-parent = <&gic>;
                         interrupts = <0 61 4>, <0 61 4>;
@@ -388,7 +389,7 @@
                 };
 
                 gem3: ethernet@ff0e0000 {
-                        compatible = "cdns,gem";
+                        compatible = "cdns,zynqmp-gem", "cdns,gem";
                         status = "disabled";
                         interrupt-parent = <&gic>;
                         interrupts = <0 63 4>, <0 63 4>;
@@ -439,10 +440,10 @@
                         device_type = "pci";
                         interrupt-parent = <&gic>;
                         interrupts = <0 118 4>,
-                                    <0 117 4>,
-                                    <0 116 4>,
-                                    <0 115 4>,  /* MSI_1 [63...32] */
-                                    <0 114 4>;  /* MSI_0 [31...0] */
+                                     <0 117 4>,
+                                     <0 116 4>,
+                                     <0 115 4>, /* MSI_1 [63...32] */
+                                     <0 114 4>; /* MSI_0 [31...0] */
                         interrupt-names = "misc", "dummy", "intx",
                                           "msi1", "msi0";
                         msi-parent = <&pcie>;
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index be7bd19c87ec..350c76a1d15b 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -20,7 +20,7 @@
 
 #define MPIDR_UP_BITMASK        (0x1 << 30)
 #define MPIDR_MT_BITMASK        (0x1 << 24)
-#define MPIDR_HWID_BITMASK      0xff00ffffff
+#define MPIDR_HWID_BITMASK      UL(0xff00ffffff)
 
 #define MPIDR_LEVEL_BITS_SHIFT  3
 #define MPIDR_LEVEL_BITS        (1 << MPIDR_LEVEL_BITS_SHIFT)
diff --git a/arch/arm64/include/asm/hugetlb.h b/arch/arm64/include/asm/hugetlb.h
index 1dca41bea16a..e73f68569624 100644
--- a/arch/arm64/include/asm/hugetlb.h
+++ b/arch/arm64/include/asm/hugetlb.h
@@ -22,7 +22,7 @@
 
 static inline pte_t huge_ptep_get(pte_t *ptep)
 {
-        return *ptep;
+        return READ_ONCE(*ptep);
 }
 
 
diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h
index 9679067a1574..7faed6e48b46 100644
--- a/arch/arm64/include/asm/kvm_mmu.h
+++ b/arch/arm64/include/asm/kvm_mmu.h
@@ -185,42 +185,42 @@ static inline pmd_t kvm_s2pmd_mkexec(pmd_t pmd)
         return pmd;
 }
 
-static inline void kvm_set_s2pte_readonly(pte_t *pte)
+static inline void kvm_set_s2pte_readonly(pte_t *ptep)
 {
         pteval_t old_pteval, pteval;
 
-        pteval = READ_ONCE(pte_val(*pte));
+        pteval = READ_ONCE(pte_val(*ptep));
         do {
                 old_pteval = pteval;
                 pteval &= ~PTE_S2_RDWR;
                 pteval |= PTE_S2_RDONLY;
-                pteval = cmpxchg_relaxed(&pte_val(*pte), old_pteval, pteval);
+                pteval = cmpxchg_relaxed(&pte_val(*ptep), old_pteval, pteval);
         } while (pteval != old_pteval);
 }
 
-static inline bool kvm_s2pte_readonly(pte_t *pte)
+static inline bool kvm_s2pte_readonly(pte_t *ptep)
 {
-        return (pte_val(*pte) & PTE_S2_RDWR) == PTE_S2_RDONLY;
+        return (READ_ONCE(pte_val(*ptep)) & PTE_S2_RDWR) == PTE_S2_RDONLY;
 }
 
-static inline bool kvm_s2pte_exec(pte_t *pte)
+static inline bool kvm_s2pte_exec(pte_t *ptep)
 {
-        return !(pte_val(*pte) & PTE_S2_XN);
+        return !(READ_ONCE(pte_val(*ptep)) & PTE_S2_XN);
 }
 
-static inline void kvm_set_s2pmd_readonly(pmd_t *pmd)
+static inline void kvm_set_s2pmd_readonly(pmd_t *pmdp)
 {
-        kvm_set_s2pte_readonly((pte_t *)pmd);
+        kvm_set_s2pte_readonly((pte_t *)pmdp);
 }
 
-static inline bool kvm_s2pmd_readonly(pmd_t *pmd)
+static inline bool kvm_s2pmd_readonly(pmd_t *pmdp)
 {
-        return kvm_s2pte_readonly((pte_t *)pmd);
+        return kvm_s2pte_readonly((pte_t *)pmdp);
 }
 
-static inline bool kvm_s2pmd_exec(pmd_t *pmd)
+static inline bool kvm_s2pmd_exec(pmd_t *pmdp)
 {
-        return !(pmd_val(*pmd) & PMD_S2_XN);
+        return !(READ_ONCE(pmd_val(*pmdp)) & PMD_S2_XN);
 }
 
 static inline bool kvm_page_empty(void *ptr)
diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h
index 8d3331985d2e..39ec0b8a689e 100644
--- a/arch/arm64/include/asm/mmu_context.h
+++ b/arch/arm64/include/asm/mmu_context.h
@@ -141,13 +141,13 @@ static inline void cpu_install_idmap(void)
  * Atomically replaces the active TTBR1_EL1 PGD with a new VA-compatible PGD,
  * avoiding the possibility of conflicting TLB entries being allocated.
  */
-static inline void cpu_replace_ttbr1(pgd_t *pgd)
+static inline void cpu_replace_ttbr1(pgd_t *pgdp)
 {
         typedef void (ttbr_replace_func)(phys_addr_t);
         extern ttbr_replace_func idmap_cpu_replace_ttbr1;
         ttbr_replace_func *replace_phys;
 
-        phys_addr_t pgd_phys = virt_to_phys(pgd);
+        phys_addr_t pgd_phys = virt_to_phys(pgdp);
 
         replace_phys = (void *)__pa_symbol(idmap_cpu_replace_ttbr1);
 
diff --git a/arch/arm64/include/asm/pgalloc.h b/arch/arm64/include/asm/pgalloc.h
index e9d9f1b006ef..2e05bcd944c8 100644
--- a/arch/arm64/include/asm/pgalloc.h
+++ b/arch/arm64/include/asm/pgalloc.h
@@ -36,23 +36,23 @@ static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
         return (pmd_t *)__get_free_page(PGALLOC_GFP);
 }
 
-static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd)
+static inline void pmd_free(struct mm_struct *mm, pmd_t *pmdp)
 {
-        BUG_ON((unsigned long)pmd & (PAGE_SIZE-1));
-        free_page((unsigned long)pmd);
+        BUG_ON((unsigned long)pmdp & (PAGE_SIZE-1));
+        free_page((unsigned long)pmdp);
 }
 
-static inline void __pud_populate(pud_t *pud, phys_addr_t pmd, pudval_t prot)
+static inline void __pud_populate(pud_t *pudp, phys_addr_t pmdp, pudval_t prot)
 {
-        set_pud(pud, __pud(__phys_to_pud_val(pmd) | prot));
+        set_pud(pudp, __pud(__phys_to_pud_val(pmdp) | prot));
 }
 
-static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
+static inline void pud_populate(struct mm_struct *mm, pud_t *pudp, pmd_t *pmdp)
 {
-        __pud_populate(pud, __pa(pmd), PMD_TYPE_TABLE);
+        __pud_populate(pudp, __pa(pmdp), PMD_TYPE_TABLE);
 }
 #else
-static inline void __pud_populate(pud_t *pud, phys_addr_t pmd, pudval_t prot)
+static inline void __pud_populate(pud_t *pudp, phys_addr_t pmdp, pudval_t prot)
 {
         BUILD_BUG();
 }
@@ -65,30 +65,30 @@ static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long addr)
         return (pud_t *)__get_free_page(PGALLOC_GFP);
 }
 
-static inline void pud_free(struct mm_struct *mm, pud_t *pud)
+static inline void pud_free(struct mm_struct *mm, pud_t *pudp)
 {
-        BUG_ON((unsigned long)pud & (PAGE_SIZE-1));
-        free_page((unsigned long)pud);
+        BUG_ON((unsigned long)pudp & (PAGE_SIZE-1));
+        free_page((unsigned long)pudp);
 }
 
-static inline void __pgd_populate(pgd_t *pgdp, phys_addr_t pud, pgdval_t prot)
+static inline void __pgd_populate(pgd_t *pgdp, phys_addr_t pudp, pgdval_t prot)
 {
-        set_pgd(pgdp, __pgd(__phys_to_pgd_val(pud) | prot));
+        set_pgd(pgdp, __pgd(__phys_to_pgd_val(pudp) | prot));
 }
 
-static inline void pgd_populate(struct mm_struct *mm, pgd_t *pgd, pud_t *pud)
+static inline void pgd_populate(struct mm_struct *mm, pgd_t *pgdp, pud_t *pudp)
 {
-        __pgd_populate(pgd, __pa(pud), PUD_TYPE_TABLE);
+        __pgd_populate(pgdp, __pa(pudp), PUD_TYPE_TABLE);
 }
 #else
-static inline void __pgd_populate(pgd_t *pgdp, phys_addr_t pud, pgdval_t prot)
+static inline void __pgd_populate(pgd_t *pgdp, phys_addr_t pudp, pgdval_t prot)
 {
         BUILD_BUG();
 }
 #endif  /* CONFIG_PGTABLE_LEVELS > 3 */
 
 extern pgd_t *pgd_alloc(struct mm_struct *mm);
-extern void pgd_free(struct mm_struct *mm, pgd_t *pgd);
+extern void pgd_free(struct mm_struct *mm, pgd_t *pgdp);
 
 static inline pte_t *
 pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr)
@@ -114,10 +114,10 @@ pte_alloc_one(struct mm_struct *mm, unsigned long addr)
 /*
  * Free a PTE table.
  */
-static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
+static inline void pte_free_kernel(struct mm_struct *mm, pte_t *ptep)
 {
-        if (pte)
-                free_page((unsigned long)pte);
+        if (ptep)
+                free_page((unsigned long)ptep);
 }
 
 static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
@@ -126,10 +126,10 @@ static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
         __free_page(pte);
 }
 
-static inline void __pmd_populate(pmd_t *pmdp, phys_addr_t pte,
+static inline void __pmd_populate(pmd_t *pmdp, phys_addr_t ptep,
                                   pmdval_t prot)
 {
-        set_pmd(pmdp, __pmd(__phys_to_pmd_val(pte) | prot));
+        set_pmd(pmdp, __pmd(__phys_to_pmd_val(ptep) | prot));
 }
 
 /*
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index 094374c82db0..7e2c27e63cd8 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -218,7 +218,7 @@ static inline pmd_t pmd_mkcont(pmd_t pmd)
 
 static inline void set_pte(pte_t *ptep, pte_t pte)
 {
-        *ptep = pte;
+        WRITE_ONCE(*ptep, pte);
 
         /*
          * Only if the new pte is valid and kernel, otherwise TLB maintenance
@@ -250,6 +250,8 @@ extern void __sync_icache_dcache(pte_t pteval, unsigned long addr);
 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
                               pte_t *ptep, pte_t pte)
 {
+        pte_t old_pte;
+
         if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte))
                 __sync_icache_dcache(pte, addr);
 
@@ -258,14 +260,15 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
          * hardware updates of the pte (ptep_set_access_flags safely changes
          * valid ptes without going through an invalid entry).
          */
-        if (IS_ENABLED(CONFIG_DEBUG_VM) && pte_valid(*ptep) && pte_valid(pte) &&
+        old_pte = READ_ONCE(*ptep);
+        if (IS_ENABLED(CONFIG_DEBUG_VM) && pte_valid(old_pte) && pte_valid(pte) &&
            (mm == current->active_mm || atomic_read(&mm->mm_users) > 1)) {
                 VM_WARN_ONCE(!pte_young(pte),
                              "%s: racy access flag clearing: 0x%016llx -> 0x%016llx",
-                             __func__, pte_val(*ptep), pte_val(pte));
-                VM_WARN_ONCE(pte_write(*ptep) && !pte_dirty(pte),
+                             __func__, pte_val(old_pte), pte_val(pte));
+                VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte),
                              "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx",
-                             __func__, pte_val(*ptep), pte_val(pte));
+                             __func__, pte_val(old_pte), pte_val(pte));
         }
 
         set_pte(ptep, pte);
@@ -431,7 +434,7 @@ extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
 
 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
 {
-        *pmdp = pmd;
+        WRITE_ONCE(*pmdp, pmd);
         dsb(ishst);
         isb();
 }
@@ -482,7 +485,7 @@ static inline phys_addr_t pmd_page_paddr(pmd_t pmd)
 
 static inline void set_pud(pud_t *pudp, pud_t pud)
 {
-        *pudp = pud;
+        WRITE_ONCE(*pudp, pud);
         dsb(ishst);
         isb();
 }
@@ -500,7 +503,7 @@ static inline phys_addr_t pud_page_paddr(pud_t pud)
 /* Find an entry in the second-level page table. */
 #define pmd_index(addr)         (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
 
-#define pmd_offset_phys(dir, addr)      (pud_page_paddr(*(dir)) + pmd_index(addr) * sizeof(pmd_t))
+#define pmd_offset_phys(dir, addr)      (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t))
 #define pmd_offset(dir, addr)           ((pmd_t *)__va(pmd_offset_phys((dir), (addr))))
 
 #define pmd_set_fixmap(addr)            ((pmd_t *)set_fixmap_offset(FIX_PMD, addr))
@@ -535,7 +538,7 @@ static inline phys_addr_t pud_page_paddr(pud_t pud)
 
 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd)
 {
-        *pgdp = pgd;
+        WRITE_ONCE(*pgdp, pgd);
         dsb(ishst);
 }
 
@@ -552,7 +555,7 @@ static inline phys_addr_t pgd_page_paddr(pgd_t pgd)
 /* Find an entry in the frst-level page table. */
 #define pud_index(addr)         (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1))
 
-#define pud_offset_phys(dir, addr)      (pgd_page_paddr(*(dir)) + pud_index(addr) * sizeof(pud_t))
+#define pud_offset_phys(dir, addr)      (pgd_page_paddr(READ_ONCE(*(dir))) + pud_index(addr) * sizeof(pud_t))
 #define pud_offset(dir, addr)           ((pud_t *)__va(pud_offset_phys((dir), (addr))))
 
 #define pud_set_fixmap(addr)            ((pud_t *)set_fixmap_offset(FIX_PUD, addr))
diff --git a/arch/arm64/include/asm/stacktrace.h b/arch/arm64/include/asm/stacktrace.h
index 472ef944e932..902f9edacbea 100644
--- a/arch/arm64/include/asm/stacktrace.h
+++ b/arch/arm64/include/asm/stacktrace.h
@@ -28,7 +28,7 @@ struct stackframe {
         unsigned long fp;
         unsigned long pc;
 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
-        unsigned int graph;
+        int graph;
 #endif
 };
 
diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h
index 543e11f0f657..e66b0fca99c2 100644
--- a/arch/arm64/include/asm/uaccess.h
+++ b/arch/arm64/include/asm/uaccess.h
@@ -72,15 +72,15 @@ static inline void set_fs(mm_segment_t fs)
  * This is equivalent to the following test:
  * (u65)addr + (u65)size <= (u65)current->addr_limit + 1
  */
-static inline unsigned long __range_ok(unsigned long addr, unsigned long size)
+static inline unsigned long __range_ok(const void __user *addr, unsigned long size)
 {
-        unsigned long limit = current_thread_info()->addr_limit;
+        unsigned long ret, limit = current_thread_info()->addr_limit;
 
         __chk_user_ptr(addr);
         asm volatile(
         // A + B <= C + 1 for all A,B,C, in four easy steps:
         // 1: X = A + B; X' = X % 2^64
-        "       adds    %0, %0, %2\n"
+        "       adds    %0, %3, %2\n"
         // 2: Set C = 0 if X > 2^64, to guarantee X' > C in step 4
         "       csel    %1, xzr, %1, hi\n"
         // 3: Set X' = ~0 if X >= 2^64. For X == 2^64, this decrements X'
@@ -92,9 +92,9 @@ static inline unsigned long __range_ok(unsigned long addr, unsigned long size)
         //    testing X' - C == 0, subject to the previous adjustments.
         "       sbcs    xzr, %0, %1\n"
         "       cset    %0, ls\n"
-        : "+r" (addr), "+r" (limit) : "Ir" (size) : "cc");
+        : "=&r" (ret), "+r" (limit) : "Ir" (size), "0" (addr) : "cc");
 
-        return addr;
+        return ret;
 }
 
 /*
@@ -104,7 +104,7 @@ static inline unsigned long __range_ok(unsigned long addr, unsigned long size)
  */
 #define untagged_addr(addr)             sign_extend64(addr, 55)
 
-#define access_ok(type, addr, size)     __range_ok((unsigned long)(addr), size)
+#define access_ok(type, addr, size)     __range_ok(addr, size)
 #define user_addr_max                   get_fs
 
 #define _ASM_EXTABLE(from, to)                                          \
diff --git a/arch/arm64/kernel/armv8_deprecated.c b/arch/arm64/kernel/armv8_deprecated.c
index c33b5e4010ab..68450e954d47 100644
--- a/arch/arm64/kernel/armv8_deprecated.c
+++ b/arch/arm64/kernel/armv8_deprecated.c
@@ -370,6 +370,7 @@ static unsigned int __kprobes aarch32_check_condition(u32 opcode, u32 psr)
 static int swp_handler(struct pt_regs *regs, u32 instr)
 {
         u32 destreg, data, type, address = 0;
+        const void __user *user_ptr;
         int rn, rt2, res = 0;
 
         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
@@ -401,7 +402,8 @@ static int swp_handler(struct pt_regs *regs, u32 instr)
                 aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET), data);
 
         /* Check access in reasonable access range for both SWP and SWPB */
-        if (!access_ok(VERIFY_WRITE, (address & ~3), 4)) {
+        user_ptr = (const void __user *)(unsigned long)(address & ~3);
+        if (!access_ok(VERIFY_WRITE, user_ptr, 4)) {
                 pr_debug("SWP{B} emulation: access to 0x%08x not allowed!\n",
                         address);
                 goto fault;
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 07823595b7f0..52f15cd896e1 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -408,6 +408,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
         },
         {
                 .capability = ARM64_HARDEN_BRANCH_PREDICTOR,
+                MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
+                .enable = qcom_enable_link_stack_sanitization,
+        },
+        {
+                .capability = ARM64_HARDEN_BP_POST_GUEST_EXIT,
+                MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
+        },
+        {
+                .capability = ARM64_HARDEN_BRANCH_PREDICTOR,
                 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
                 .enable = enable_smccc_arch_workaround_1,
         },
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 29b1f873e337..2985a067fc13 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -199,9 +199,11 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
 };
 
 static const struct arm64_ftr_bits ftr_ctr[] = {
-        ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1),   /* RAO */
+        ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1),           /* RES1 */
+        ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 29, 1, 1),      /* DIC */
+        ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 28, 1, 1),      /* IDC */
         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0),     /* CWG */
-        ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),      /* ERG */
+        ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, 20, 4, 0),     /* ERG */
         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1),      /* DminLine */
         /*
          * Linux can handle differing I-cache policies. Userspace JITs will
diff --git a/arch/arm64/kernel/efi.c b/arch/arm64/kernel/efi.c
index f85ac58d08a3..a8bf1c892b90 100644
--- a/arch/arm64/kernel/efi.c
+++ b/arch/arm64/kernel/efi.c
@@ -90,7 +90,7 @@ static int __init set_permissions(pte_t *ptep, pgtable_t token,
                                   unsigned long addr, void *data)
 {
         efi_memory_desc_t *md = data;
-        pte_t pte = *ptep;
+        pte_t pte = READ_ONCE(*ptep);
 
         if (md->attribute & EFI_MEMORY_RO)
                 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY));
diff --git a/arch/arm64/kernel/hibernate.c b/arch/arm64/kernel/hibernate.c
index f20cf7e99249..1ec5f28c39fc 100644
--- a/arch/arm64/kernel/hibernate.c
+++ b/arch/arm64/kernel/hibernate.c
@@ -202,10 +202,10 @@ static int create_safe_exec_page(void *src_start, size_t length,
                                  gfp_t mask)
 {
         int rc = 0;
-        pgd_t *pgd;
-        pud_t *pud;
-        pmd_t *pmd;
-        pte_t *pte;
+        pgd_t *pgdp;
+        pud_t *pudp;
+        pmd_t *pmdp;
+        pte_t *ptep;
         unsigned long dst = (unsigned long)allocator(mask);
 
         if (!dst) {
@@ -216,38 +216,38 @@ static int create_safe_exec_page(void *src_start, size_t length,
         memcpy((void *)dst, src_start, length);
         flush_icache_range(dst, dst + length);
 
-        pgd = pgd_offset_raw(allocator(mask), dst_addr);
-        if (pgd_none(*pgd)) {
-                pud = allocator(mask);
-                if (!pud) {
+        pgdp = pgd_offset_raw(allocator(mask), dst_addr);
+        if (pgd_none(READ_ONCE(*pgdp))) {
+                pudp = allocator(mask);
+                if (!pudp) {
                         rc = -ENOMEM;
                         goto out;
                 }
-                pgd_populate(&init_mm, pgd, pud);
+                pgd_populate(&init_mm, pgdp, pudp);
         }
 
-        pud = pud_offset(pgd, dst_addr);
-        if (pud_none(*pud)) {
-                pmd = allocator(mask);
-                if (!pmd) {
+        pudp = pud_offset(pgdp, dst_addr);
+        if (pud_none(READ_ONCE(*pudp))) {
+                pmdp = allocator(mask);
+                if (!pmdp) {
                         rc = -ENOMEM;
                         goto out;
                 }
-                pud_populate(&init_mm, pud, pmd);
+                pud_populate(&init_mm, pudp, pmdp);
         }
 
-        pmd = pmd_offset(pud, dst_addr);
-        if (pmd_none(*pmd)) {
-                pte = allocator(mask);
-                if (!pte) {
+        pmdp = pmd_offset(pudp, dst_addr);
+        if (pmd_none(READ_ONCE(*pmdp))) {
+                ptep = allocator(mask);
+                if (!ptep) {
                         rc = -ENOMEM;
                         goto out;
                 }
-                pmd_populate_kernel(&init_mm, pmd, pte);
+                pmd_populate_kernel(&init_mm, pmdp, ptep);
         }
 
-        pte = pte_offset_kernel(pmd, dst_addr);
-        set_pte(pte, pfn_pte(virt_to_pfn(dst), PAGE_KERNEL_EXEC));
+        ptep = pte_offset_kernel(pmdp, dst_addr);
+        set_pte(ptep, pfn_pte(virt_to_pfn(dst), PAGE_KERNEL_EXEC));
 
         /*
          * Load our new page tables. A strict BBM approach requires that we
@@ -263,7 +263,7 @@ static int create_safe_exec_page(void *src_start, size_t length,
          */
         cpu_set_reserved_ttbr0();
         local_flush_tlb_all();
-        write_sysreg(phys_to_ttbr(virt_to_phys(pgd)), ttbr0_el1);
+        write_sysreg(phys_to_ttbr(virt_to_phys(pgdp)), ttbr0_el1);
         isb();
 
         *phys_dst_addr = virt_to_phys((void *)dst);
@@ -320,9 +320,9 @@ int swsusp_arch_suspend(void)
         return ret;
 }
 
-static void _copy_pte(pte_t *dst_pte, pte_t *src_pte, unsigned long addr)
+static void _copy_pte(pte_t *dst_ptep, pte_t *src_ptep, unsigned long addr)
 {
-        pte_t pte = *src_pte;
+        pte_t pte = READ_ONCE(*src_ptep);
 
         if (pte_valid(pte)) {
                 /*
@@ -330,7 +330,7 @@ static void _copy_pte(pte_t *dst_pte, pte_t *src_pte, unsigned long addr)
                  * read only (code, rodata). Clear the RDONLY bit from
                  * the temporary mappings we use during restore.
                  */
-                set_pte(dst_pte, pte_mkwrite(pte));
+                set_pte(dst_ptep, pte_mkwrite(pte));
         } else if (debug_pagealloc_enabled() && !pte_none(pte)) {
                 /*
                  * debug_pagealloc will removed the PTE_VALID bit if
@@ -343,112 +343,116 @@ static void _copy_pte(pte_t *dst_pte, pte_t *src_pte, unsigned long addr)
                  */
                 BUG_ON(!pfn_valid(pte_pfn(pte)));
 
-                set_pte(dst_pte, pte_mkpresent(pte_mkwrite(pte)));
+                set_pte(dst_ptep, pte_mkpresent(pte_mkwrite(pte)));
         }
 }
 
-static int copy_pte(pmd_t *dst_pmd, pmd_t *src_pmd, unsigned long start,
+static int copy_pte(pmd_t *dst_pmdp, pmd_t *src_pmdp, unsigned long start,
                     unsigned long end)
 {
-        pte_t *src_pte;
-        pte_t *dst_pte;
+        pte_t *src_ptep;
+        pte_t *dst_ptep;
         unsigned long addr = start;
 
-        dst_pte = (pte_t *)get_safe_page(GFP_ATOMIC);
-        if (!dst_pte)
+        dst_ptep = (pte_t *)get_safe_page(GFP_ATOMIC);
+        if (!dst_ptep)
                 return -ENOMEM;
-        pmd_populate_kernel(&init_mm, dst_pmd, dst_pte);
-        dst_pte = pte_offset_kernel(dst_pmd, start);
+        pmd_populate_kernel(&init_mm, dst_pmdp, dst_ptep);
+        dst_ptep = pte_offset_kernel(dst_pmdp, start);
 
-        src_pte = pte_offset_kernel(src_pmd, start);
+        src_ptep = pte_offset_kernel(src_pmdp, start);
         do {
-                _copy_pte(dst_pte, src_pte, addr);
-        } while (dst_pte++, src_pte++, addr += PAGE_SIZE, addr != end);
+                _copy_pte(dst_ptep, src_ptep, addr);
+        } while (dst_ptep++, src_ptep++, addr += PAGE_SIZE, addr != end);
 
         return 0;
 }
 
-static int copy_pmd(pud_t *dst_pud, pud_t *src_pud, unsigned long start,
+static int copy_pmd(pud_t *dst_pudp, pud_t *src_pudp, unsigned long start,
                     unsigned long end)
 {
-        pmd_t *src_pmd;
-        pmd_t *dst_pmd;
+        pmd_t *src_pmdp;
+        pmd_t *dst_pmdp;
         unsigned long next;
         unsigned long addr = start;
 
-        if (pud_none(*dst_pud)) {
-                dst_pmd = (pmd_t *)get_safe_page(GFP_ATOMIC);
-                if (!dst_pmd)
+        if (pud_none(READ_ONCE(*dst_pudp))) {
+                dst_pmdp = (pmd_t *)get_safe_page(GFP_ATOMIC);
+                if (!dst_pmdp)
                         return -ENOMEM;
-                pud_populate(&init_mm, dst_pud, dst_pmd);
+                pud_populate(&init_mm, dst_pudp, dst_pmdp);
         }
-        dst_pmd = pmd_offset(dst_pud, start);
+        dst_pmdp = pmd_offset(dst_pudp, start);
 
-        src_pmd = pmd_offset(src_pud, start);
+        src_pmdp = pmd_offset(src_pudp, start);
         do {
+                pmd_t pmd = READ_ONCE(*src_pmdp);
+
                 next = pmd_addr_end(addr, end);
-                if (pmd_none(*src_pmd))
+                if (pmd_none(pmd))
                         continue;
-                if (pmd_table(*src_pmd)) {
-                        if (copy_pte(dst_pmd, src_pmd, addr, next))
+                if (pmd_table(pmd)) {
+                        if (copy_pte(dst_pmdp, src_pmdp, addr, next))
                                 return -ENOMEM;
                 } else {
-                        set_pmd(dst_pmd,
-                                __pmd(pmd_val(*src_pmd) & ~PMD_SECT_RDONLY));
+                        set_pmd(dst_pmdp,
+                                __pmd(pmd_val(pmd) & ~PMD_SECT_RDONLY));
                 }
-        } while (dst_pmd++, src_pmd++, addr = next, addr != end);
+        } while (dst_pmdp++, src_pmdp++, addr = next, addr != end);
 
         return 0;
 }
 
-static int copy_pud(pgd_t *dst_pgd, pgd_t *src_pgd, unsigned long start,
+static int copy_pud(pgd_t *dst_pgdp, pgd_t *src_pgdp, unsigned long start,
                     unsigned long end)
 {
-        pud_t *dst_pud;
-        pud_t *src_pud;
+        pud_t *dst_pudp;
+        pud_t *src_pudp;
         unsigned long next;
         unsigned long addr = start;
 
-        if (pgd_none(*dst_pgd)) {
-                dst_pud = (pud_t *)get_safe_page(GFP_ATOMIC);
-                if (!dst_pud)
+        if (pgd_none(READ_ONCE(*dst_pgdp))) {
+                dst_pudp = (pud_t *)get_safe_page(GFP_ATOMIC);
+                if (!dst_pudp)
                         return -ENOMEM;
-                pgd_populate(&init_mm, dst_pgd, dst_pud);
+                pgd_populate(&init_mm, dst_pgdp, dst_pudp);
         }
-        dst_pud = pud_offset(dst_pgd, start);
+        dst_pudp = pud_offset(dst_pgdp, start);
 
-        src_pud = pud_offset(src_pgd, start);
+        src_pudp = pud_offset(src_pgdp, start);
         do {
+                pud_t pud = READ_ONCE(*src_pudp);
+
                 next = pud_addr_end(addr, end);
-                if (pud_none(*src_pud))
+                if (pud_none(pud))
                         continue;
-                if (pud_table(*(src_pud))) {
-                        if (copy_pmd(dst_pud, src_pud, addr, next))
+                if (pud_table(pud)) {
+                        if (copy_pmd(dst_pudp, src_pudp, addr, next))
                                 return -ENOMEM;
                 } else {
-                        set_pud(dst_pud,
-                                __pud(pud_val(*src_pud) & ~PMD_SECT_RDONLY));
+                        set_pud(dst_pudp,
+                                __pud(pud_val(pud) & ~PMD_SECT_RDONLY));
                 }
-        } while (dst_pud++, src_pud++, addr = next, addr != end);
+        } while (dst_pudp++, src_pudp++, addr = next, addr != end);
 
         return 0;
 }
 
-static int copy_page_tables(pgd_t *dst_pgd, unsigned long start,
+static int copy_page_tables(pgd_t *dst_pgdp, unsigned long start,
                             unsigned long end)
 {
         unsigned long next;
         unsigned long addr = start;
-        pgd_t *src_pgd = pgd_offset_k(start);
+        pgd_t *src_pgdp = pgd_offset_k(start);
 
-        dst_pgd = pgd_offset_raw(dst_pgd, start);
+        dst_pgdp = pgd_offset_raw(dst_pgdp, start);
         do {
                 next = pgd_addr_end(addr, end);
-                if (pgd_none(*src_pgd))
+                if (pgd_none(READ_ONCE(*src_pgdp)))
                         continue;
-                if (copy_pud(dst_pgd, src_pgd, addr, next))
+                if (copy_pud(dst_pgdp, src_pgdp, addr, next))
                         return -ENOMEM;
-        } while (dst_pgd++, src_pgd++, addr = next, addr != end);
+        } while (dst_pgdp++, src_pgdp++, addr = next, addr != end);
 
         return 0;
 }
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 75b220ba73a3..85a251b6dfa8 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -908,9 +908,9 @@ static void __armv8pmu_probe_pmu(void *info)
         int pmuver;
 
         dfr0 = read_sysreg(id_aa64dfr0_el1);
-        pmuver = cpuid_feature_extract_signed_field(dfr0,
+        pmuver = cpuid_feature_extract_unsigned_field(dfr0,
                         ID_AA64DFR0_PMUVER_SHIFT);
-        if (pmuver < 1)
+        if (pmuver == 0xf || pmuver == 0)
                 return;
 
         probe->present = true;
diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
index ad8aeb098b31..c0da6efe5465 100644
--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64/kernel/process.c
@@ -220,8 +220,15 @@ void __show_regs(struct pt_regs *regs)
 
         show_regs_print_info(KERN_DEFAULT);
         print_pstate(regs);
-        printk("pc : %pS\n", (void *)regs->pc);
-        printk("lr : %pS\n", (void *)lr);
+
+        if (!user_mode(regs)) {
+                printk("pc : %pS\n", (void *)regs->pc);
+                printk("lr : %pS\n", (void *)lr);
+        } else {
+                printk("pc : %016llx\n", regs->pc);
+                printk("lr : %016llx\n", lr);
+        }
+
         printk("sp : %016llx\n", sp);
 
         i = top_reg;
diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c
index 6618036ae6d4..9ae31f7e2243 100644
--- a/arch/arm64/kernel/ptrace.c
+++ b/arch/arm64/kernel/ptrace.c
@@ -1419,7 +1419,7 @@ static int compat_ptrace_hbp_get(unsigned int note_type,
         u64 addr = 0;
         u32 ctrl = 0;
 
-        int err, idx = compat_ptrace_hbp_num_to_idx(num);;
+        int err, idx = compat_ptrace_hbp_num_to_idx(num);
 
         if (num & 1) {
                 err = ptrace_hbp_get_addr(note_type, tsk, idx, &addr);
diff --git a/arch/arm64/kernel/stacktrace.c b/arch/arm64/kernel/stacktrace.c
index 76809ccd309c..d5718a060672 100644
--- a/arch/arm64/kernel/stacktrace.c
+++ b/arch/arm64/kernel/stacktrace.c
@@ -59,6 +59,11 @@ int notrace unwind_frame(struct task_struct *tsk, struct stackframe *frame)
 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
         if (tsk->ret_stack &&
                         (frame->pc == (unsigned long)return_to_handler)) {
+                if (WARN_ON_ONCE(frame->graph == -1))
+                        return -EINVAL;
+                if (frame->graph < -1)
+                        frame->graph += FTRACE_NOTRACE_DEPTH;
+
                 /*
                  * This is a case where function graph tracer has
                  * modified a return address (LR) in a stack frame
diff --git a/arch/arm64/kernel/sys_compat.c b/arch/arm64/kernel/sys_compat.c
index 8b8bbd3eaa52..a382b2a1b84e 100644
--- a/arch/arm64/kernel/sys_compat.c
+++ b/arch/arm64/kernel/sys_compat.c
@@ -57,7 +57,7 @@ do_compat_cache_op(unsigned long start, unsigned long end, int flags)
         if (end < start || flags)
                 return -EINVAL;
 
-        if (!access_ok(VERIFY_READ, start, end - start))
+        if (!access_ok(VERIFY_READ, (const void __user *)start, end - start))
                 return -EFAULT;
 
         return __do_compat_cache_op(start, end);
diff --git a/arch/arm64/kernel/time.c b/arch/arm64/kernel/time.c
index a4391280fba9..f258636273c9 100644
--- a/arch/arm64/kernel/time.c
+++ b/arch/arm64/kernel/time.c
@@ -52,7 +52,7 @@ unsigned long profile_pc(struct pt_regs *regs)
         frame.fp = regs->regs[29];
         frame.pc = regs->pc;
 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
-        frame.graph = -1; /* no task info */
+        frame.graph = current->curr_ret_stack;
 #endif
         do {
                 int ret = unwind_frame(NULL, &frame);
diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c
index bbb0fde2780e..eb2d15147e8d 100644
--- a/arch/arm64/kernel/traps.c
+++ b/arch/arm64/kernel/traps.c
@@ -57,7 +57,7 @@ static const char *handler[]= {
         "Error"
 };
 
-int show_unhandled_signals = 1;
+int show_unhandled_signals = 0;
 
 static void dump_backtrace_entry(unsigned long where)
 {
@@ -526,14 +526,6 @@ asmlinkage long do_ni_syscall(struct pt_regs *regs)
         }
 #endif
 
-        if (show_unhandled_signals_ratelimited()) {
-                pr_info("%s[%d]: syscall %d\n", current->comm,
-                        task_pid_nr(current), regs->syscallno);
-                dump_instr("", regs);
-                if (user_mode(regs))
-                        __show_regs(regs);
-        }
-
         return sys_ni_syscall();
 }
 
diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c
index 116252a8d3a5..870f4b1587f9 100644
--- a/arch/arm64/kvm/hyp/switch.c
+++ b/arch/arm64/kvm/hyp/switch.c
@@ -407,8 +407,10 @@ again:
                 u32 midr = read_cpuid_id();
 
                 /* Apply BTAC predictors mitigation to all Falkor chips */
-                if ((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR_V1)
+                if (((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR) ||
+                    ((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR_V1)) {
                         __qcom_hyp_sanitize_btac_predictors();
+                }
         }
 
         fp_enabled = __fpsimd_enabled();
diff --git a/arch/arm64/mm/dump.c b/arch/arm64/mm/dump.c
index 7b60d62ac593..65dfc8571bf8 100644
--- a/arch/arm64/mm/dump.c
+++ b/arch/arm64/mm/dump.c
@@ -286,48 +286,52 @@ static void note_page(struct pg_state *st, unsigned long addr, unsigned level,
 
 }
 
-static void walk_pte(struct pg_state *st, pmd_t *pmd, unsigned long start)
+static void walk_pte(struct pg_state *st, pmd_t *pmdp, unsigned long start)
 {
-        pte_t *pte = pte_offset_kernel(pmd, 0UL);
+        pte_t *ptep = pte_offset_kernel(pmdp, 0UL);
         unsigned long addr;
         unsigned i;
 
-        for (i = 0; i < PTRS_PER_PTE; i++, pte++) {
+        for (i = 0; i < PTRS_PER_PTE; i++, ptep++) {
                 addr = start + i * PAGE_SIZE;
-                note_page(st, addr, 4, pte_val(*pte));
+                note_page(st, addr, 4, READ_ONCE(pte_val(*ptep)));
         }
 }
 
-static void walk_pmd(struct pg_state *st, pud_t *pud, unsigned long start)
+static void walk_pmd(struct pg_state *st, pud_t *pudp, unsigned long start)
 {
-        pmd_t *pmd = pmd_offset(pud, 0UL);
+        pmd_t *pmdp = pmd_offset(pudp, 0UL);
         unsigned long addr;
         unsigned i;
 
-        for (i = 0; i < PTRS_PER_PMD; i++, pmd++) {
+        for (i = 0; i < PTRS_PER_PMD; i++, pmdp++) {
+                pmd_t pmd = READ_ONCE(*pmdp);
+
                 addr = start + i * PMD_SIZE;
-                if (pmd_none(*pmd) || pmd_sect(*pmd)) {
-                        note_page(st, addr, 3, pmd_val(*pmd));
+                if (pmd_none(pmd) || pmd_sect(pmd)) {
+                        note_page(st, addr, 3, pmd_val(pmd));
                 } else {
-                        BUG_ON(pmd_bad(*pmd));
-                        walk_pte(st, pmd, addr);
+                        BUG_ON(pmd_bad(pmd));
+                        walk_pte(st, pmdp, addr);
                 }
         }
 }
 
-static void walk_pud(struct pg_state *st, pgd_t *pgd, unsigned long start)
+static void walk_pud(struct pg_state *st, pgd_t *pgdp, unsigned long start)
 {
-        pud_t *pud = pud_offset(pgd, 0UL);
+        pud_t *pudp = pud_offset(pgdp, 0UL);
         unsigned long addr;
         unsigned i;
 
-        for (i = 0; i < PTRS_PER_PUD; i++, pud++) {
+        for (i = 0; i < PTRS_PER_PUD; i++, pudp++) {
+                pud_t pud = READ_ONCE(*pudp);
+
                 addr = start + i * PUD_SIZE;
-                if (pud_none(*pud) || pud_sect(*pud)) {
-                        note_page(st, addr, 2, pud_val(*pud));
+                if (pud_none(pud) || pud_sect(pud)) {
+                        note_page(st, addr, 2, pud_val(pud));
                 } else {
-                        BUG_ON(pud_bad(*pud));
-                        walk_pmd(st, pud, addr);
+                        BUG_ON(pud_bad(pud));
+                        walk_pmd(st, pudp, addr);
                 }
         }
 }
@@ -335,17 +339,19 @@ static void walk_pud(struct pg_state *st, pgd_t *pgd, unsigned long start)
 static void walk_pgd(struct pg_state *st, struct mm_struct *mm,
                      unsigned long start)
 {
-        pgd_t *pgd = pgd_offset(mm, 0UL);
+        pgd_t *pgdp = pgd_offset(mm, 0UL);
         unsigned i;
         unsigned long addr;
 
-        for (i = 0; i < PTRS_PER_PGD; i++, pgd++) {
+        for (i = 0; i < PTRS_PER_PGD; i++, pgdp++) {
+                pgd_t pgd = READ_ONCE(*pgdp);
+
                 addr = start + i * PGDIR_SIZE;
-                if (pgd_none(*pgd)) {
-                        note_page(st, addr, 1, pgd_val(*pgd));
+                if (pgd_none(pgd)) {
+                        note_page(st, addr, 1, pgd_val(pgd));
                 } else {
-                        BUG_ON(pgd_bad(*pgd));
-                        walk_pud(st, pgd, addr);
+                        BUG_ON(pgd_bad(pgd));
+                        walk_pud(st, pgdp, addr);
                 }
         }
 }
diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c
index f76bb2c3c943..bff11553eb05 100644
--- a/arch/arm64/mm/fault.c
+++ b/arch/arm64/mm/fault.c
@@ -130,7 +130,8 @@ static void mem_abort_decode(unsigned int esr)
 void show_pte(unsigned long addr)
 {
         struct mm_struct *mm;
-        pgd_t *pgd;
+        pgd_t *pgdp;
+        pgd_t pgd;
 
         if (addr < TASK_SIZE) {
                 /* TTBR0 */
@@ -149,33 +150,37 @@ void show_pte(unsigned long addr)
                 return;
         }
 
-        pr_alert("%s pgtable: %luk pages, %u-bit VAs, pgd = %p\n",
+        pr_alert("%s pgtable: %luk pages, %u-bit VAs, pgdp = %p\n",
                  mm == &init_mm ? "swapper" : "user", PAGE_SIZE / SZ_1K,
                  VA_BITS, mm->pgd);
-        pgd = pgd_offset(mm, addr);
-        pr_alert("[%016lx] *pgd=%016llx", addr, pgd_val(*pgd));
+        pgdp = pgd_offset(mm, addr);
+        pgd = READ_ONCE(*pgdp);
+        pr_alert("[%016lx] pgd=%016llx", addr, pgd_val(pgd));
 
         do {
-                pud_t *pud;
-                pmd_t *pmd;
-                pte_t *pte;
+                pud_t *pudp, pud;
+                pmd_t *pmdp, pmd;
+                pte_t *ptep, pte;
 
-                if (pgd_none(*pgd) || pgd_bad(*pgd))
+                if (pgd_none(pgd) || pgd_bad(pgd))
                         break;
 
-                pud = pud_offset(pgd, addr);
-                pr_cont(", *pud=%016llx", pud_val(*pud));
-                if (pud_none(*pud) || pud_bad(*pud))
+                pudp = pud_offset(pgdp, addr);
+                pud = READ_ONCE(*pudp);
+                pr_cont(", pud=%016llx", pud_val(pud));
+                if (pud_none(pud) || pud_bad(pud))
                         break;
 
-                pmd = pmd_offset(pud, addr);
-                pr_cont(", *pmd=%016llx", pmd_val(*pmd));
-                if (pmd_none(*pmd) || pmd_bad(*pmd))
+                pmdp = pmd_offset(pudp, addr);
+                pmd = READ_ONCE(*pmdp);
+                pr_cont(", pmd=%016llx", pmd_val(pmd));
+                if (pmd_none(pmd) || pmd_bad(pmd))
                         break;
 
-                pte = pte_offset_map(pmd, addr);
-                pr_cont(", *pte=%016llx", pte_val(*pte));
-                pte_unmap(pte);
+                ptep = pte_offset_map(pmdp, addr);
+                pte = READ_ONCE(*ptep);
+                pr_cont(", pte=%016llx", pte_val(pte));
+                pte_unmap(ptep);
         } while(0);
 
         pr_cont("\n");
@@ -196,8 +201,9 @@ int ptep_set_access_flags(struct vm_area_struct *vma,
                           pte_t entry, int dirty)
 {
         pteval_t old_pteval, pteval;
+        pte_t pte = READ_ONCE(*ptep);
 
-        if (pte_same(*ptep, entry))
+        if (pte_same(pte, entry))
                 return 0;
 
         /* only preserve the access flags and write permission */
@@ -210,7 +216,7 @@ int ptep_set_access_flags(struct vm_area_struct *vma,
          * (calculated as: a & b == ~(~a | ~b)).
          */
         pte_val(entry) ^= PTE_RDONLY;
-        pteval = READ_ONCE(pte_val(*ptep));
+        pteval = pte_val(pte);
         do {
                 old_pteval = pteval;
                 pteval ^= PTE_RDONLY;
diff --git a/arch/arm64/mm/hugetlbpage.c b/arch/arm64/mm/hugetlbpage.c
index 6cb0fa92a651..ecc6818191df 100644
--- a/arch/arm64/mm/hugetlbpage.c
+++ b/arch/arm64/mm/hugetlbpage.c
@@ -54,14 +54,14 @@ static inline pgprot_t pte_pgprot(pte_t pte)
 static int find_num_contig(struct mm_struct *mm, unsigned long addr,
                            pte_t *ptep, size_t *pgsize)
 {
-        pgd_t *pgd = pgd_offset(mm, addr);
-        pud_t *pud;
-        pmd_t *pmd;
+        pgd_t *pgdp = pgd_offset(mm, addr);
+        pud_t *pudp;
+        pmd_t *pmdp;
 
         *pgsize = PAGE_SIZE;
-        pud = pud_offset(pgd, addr);
-        pmd = pmd_offset(pud, addr);
-        if ((pte_t *)pmd == ptep) {
+        pudp = pud_offset(pgdp, addr);
+        pmdp = pmd_offset(pudp, addr);
+        if ((pte_t *)pmdp == ptep) {
                 *pgsize = PMD_SIZE;
                 return CONT_PMDS;
         }
@@ -181,11 +181,8 @@ void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
 
         clear_flush(mm, addr, ptep, pgsize, ncontig);
 
-        for (i = 0; i < ncontig; i++, ptep++, addr += pgsize, pfn += dpfn) {
-                pr_debug("%s: set pte %p to 0x%llx\n", __func__, ptep,
-                         pte_val(pfn_pte(pfn, hugeprot)));
+        for (i = 0; i < ncontig; i++, ptep++, addr += pgsize, pfn += dpfn)
                 set_pte_at(mm, addr, ptep, pfn_pte(pfn, hugeprot));
-        }
 }
 
 void set_huge_swap_pte_at(struct mm_struct *mm, unsigned long addr,
@@ -203,20 +200,20 @@ void set_huge_swap_pte_at(struct mm_struct *mm, unsigned long addr,
 pte_t *huge_pte_alloc(struct mm_struct *mm,
                       unsigned long addr, unsigned long sz)
 {
-        pgd_t *pgd;
-        pud_t *pud;
-        pte_t *pte = NULL;
-
-        pr_debug("%s: addr:0x%lx sz:0x%lx\n", __func__, addr, sz);
-        pgd = pgd_offset(mm, addr);
-        pud = pud_alloc(mm, pgd, addr);
-        if (!pud)
+        pgd_t *pgdp;
+        pud_t *pudp;
+        pmd_t *pmdp;
+        pte_t *ptep = NULL;
+
+        pgdp = pgd_offset(mm, addr);
+        pudp = pud_alloc(mm, pgdp, addr);
+        if (!pudp)
                 return NULL;
 
         if (sz == PUD_SIZE) {
-                pte = (pte_t *)pud;
+                ptep = (pte_t *)pudp;
         } else if (sz == (PAGE_SIZE * CONT_PTES)) {
-                pmd_t *pmd = pmd_alloc(mm, pud, addr);
+                pmdp = pmd_alloc(mm, pudp, addr);
 
                 WARN_ON(addr & (sz - 1));
                 /*
@@ -226,60 +223,55 @@ pte_t *huge_pte_alloc(struct mm_struct *mm,
                  * will be no pte_unmap() to correspond with this
                  * pte_alloc_map().
                  */
-                pte = pte_alloc_map(mm, pmd, addr);
+                ptep = pte_alloc_map(mm, pmdp, addr);
         } else if (sz == PMD_SIZE) {
                 if (IS_ENABLED(CONFIG_ARCH_WANT_HUGE_PMD_SHARE) &&
-                    pud_none(*pud))
-                        pte = huge_pmd_share(mm, addr, pud);
+                    pud_none(READ_ONCE(*pudp)))
+                        ptep = huge_pmd_share(mm, addr, pudp);
                 else
-                        pte = (pte_t *)pmd_alloc(mm, pud, addr);
+                        ptep = (pte_t *)pmd_alloc(mm, pudp, addr);
         } else if (sz == (PMD_SIZE * CONT_PMDS)) {
-                pmd_t *pmd;
-
-                pmd = pmd_alloc(mm, pud, addr);
+                pmdp = pmd_alloc(mm, pudp, addr);
                 WARN_ON(addr & (sz - 1));
-                return (pte_t *)pmd;
+                return (pte_t *)pmdp;
         }
 
-        pr_debug("%s: addr:0x%lx sz:0x%lx ret pte=%p/0x%llx\n", __func__, addr,
-               sz, pte, pte_val(*pte));
-        return pte;
+        return ptep;
 }
 
 pte_t *huge_pte_offset(struct mm_struct *mm,
                        unsigned long addr, unsigned long sz)
 {
-        pgd_t *pgd;
-        pud_t *pud;
-        pmd_t *pmd;
+        pgd_t *pgdp;
+        pud_t *pudp, pud;
+        pmd_t *pmdp, pmd;
 
-        pgd = pgd_offset(mm, addr);
-        pr_debug("%s: addr:0x%lx pgd:%p\n", __func__, addr, pgd);
-        if (!pgd_present(*pgd))
+        pgdp = pgd_offset(mm, addr);
+        if (!pgd_present(READ_ONCE(*pgdp)))
                 return NULL;
 
-        pud = pud_offset(pgd, addr);
-        if (sz != PUD_SIZE && pud_none(*pud))
+        pudp = pud_offset(pgdp, addr);
+        pud = READ_ONCE(*pudp);
+        if (sz != PUD_SIZE && pud_none(pud))
                 return NULL;
         /* hugepage or swap? */
-        if (pud_huge(*pud) || !pud_present(*pud))
-                return (pte_t *)pud;
+        if (pud_huge(pud) || !pud_present(pud))
+                return (pte_t *)pudp;
         /* table; check the next level */
 
         if (sz == CONT_PMD_SIZE)
                 addr &= CONT_PMD_MASK;
 
-        pmd = pmd_offset(pud, addr);
+        pmdp = pmd_offset(pudp, addr);
+        pmd = READ_ONCE(*pmdp);
         if (!(sz == PMD_SIZE || sz == CONT_PMD_SIZE) &&
-            pmd_none(*pmd))
+            pmd_none(pmd))
                 return NULL;
-        if (pmd_huge(*pmd) || !pmd_present(*pmd))
-                return (pte_t *)pmd;
+        if (pmd_huge(pmd) || !pmd_present(pmd))
+                return (pte_t *)pmdp;
 
-        if (sz == CONT_PTE_SIZE) {
-                pte_t *pte = pte_offset_kernel(pmd, (addr & CONT_PTE_MASK));
-                return pte;
-        }
+        if (sz == CONT_PTE_SIZE)
+                return pte_offset_kernel(pmdp, (addr & CONT_PTE_MASK));
 
         return NULL;
 }
@@ -367,7 +359,7 @@ void huge_ptep_set_wrprotect(struct mm_struct *mm,
         size_t pgsize;
         pte_t pte;
 
-        if (!pte_cont(*ptep)) {
+        if (!pte_cont(READ_ONCE(*ptep))) {
                 ptep_set_wrprotect(mm, addr, ptep);
                 return;
         }
@@ -391,7 +383,7 @@ void huge_ptep_clear_flush(struct vm_area_struct *vma,
         size_t pgsize;
         int ncontig;
 
-        if (!pte_cont(*ptep)) {
+        if (!pte_cont(READ_ONCE(*ptep))) {
                 ptep_clear_flush(vma, addr, ptep);
                 return;
         }
diff --git a/arch/arm64/mm/kasan_init.c b/arch/arm64/mm/kasan_init.c
index 6e02e6fb4c7b..dabfc1ecda3d 100644
--- a/arch/arm64/mm/kasan_init.c
+++ b/arch/arm64/mm/kasan_init.c
@@ -44,92 +44,92 @@ static phys_addr_t __init kasan_alloc_zeroed_page(int node)
         return __pa(p);
 }
 
-static pte_t *__init kasan_pte_offset(pmd_t *pmd, unsigned long addr, int node,
+static pte_t *__init kasan_pte_offset(pmd_t *pmdp, unsigned long addr, int node,
                                       bool early)
 {
-        if (pmd_none(*pmd)) {
+        if (pmd_none(READ_ONCE(*pmdp))) {
                 phys_addr_t pte_phys = early ? __pa_symbol(kasan_zero_pte)
                                              : kasan_alloc_zeroed_page(node);
-                __pmd_populate(pmd, pte_phys, PMD_TYPE_TABLE);
+                __pmd_populate(pmdp, pte_phys, PMD_TYPE_TABLE);
         }
 
-        return early ? pte_offset_kimg(pmd, addr)
-                     : pte_offset_kernel(pmd, addr);
+        return early ? pte_offset_kimg(pmdp, addr)
+                     : pte_offset_kernel(pmdp, addr);
 }
 
-static pmd_t *__init kasan_pmd_offset(pud_t *pud, unsigned long addr, int node,
+static pmd_t *__init kasan_pmd_offset(pud_t *pudp, unsigned long addr, int node,
                                       bool early)
 {
-        if (pud_none(*pud)) {
+        if (pud_none(READ_ONCE(*pudp))) {
                 phys_addr_t pmd_phys = early ? __pa_symbol(kasan_zero_pmd)
                                              : kasan_alloc_zeroed_page(node);
-                __pud_populate(pud, pmd_phys, PMD_TYPE_TABLE);
+                __pud_populate(pudp, pmd_phys, PMD_TYPE_TABLE);
         }
 
-        return early ? pmd_offset_kimg(pud, addr) : pmd_offset(pud, addr);
+        return early ? pmd_offset_kimg(pudp, addr) : pmd_offset(pudp, addr);
 }
 
-static pud_t *__init kasan_pud_offset(pgd_t *pgd, unsigned long addr, int node,
+static pud_t *__init kasan_pud_offset(pgd_t *pgdp, unsigned long addr, int node,
                                       bool early)
 {
-        if (pgd_none(*pgd)) {
+        if (pgd_none(READ_ONCE(*pgdp))) {
                 phys_addr_t pud_phys = early ? __pa_symbol(kasan_zero_pud)
                                              : kasan_alloc_zeroed_page(node);
-                __pgd_populate(pgd, pud_phys, PMD_TYPE_TABLE);
+                __pgd_populate(pgdp, pud_phys, PMD_TYPE_TABLE);
         }
 
-        return early ? pud_offset_kimg(pgd, addr) : pud_offset(pgd, addr);
+        return early ? pud_offset_kimg(pgdp, addr) : pud_offset(pgdp, addr);
 }
 
-static void __init kasan_pte_populate(pmd_t *pmd, unsigned long addr,
+static void __init kasan_pte_populate(pmd_t *pmdp, unsigned long addr,
                                       unsigned long end, int node, bool early)
 {
         unsigned long next;
-        pte_t *pte = kasan_pte_offset(pmd, addr, node, early);
+        pte_t *ptep = kasan_pte_offset(pmdp, addr, node, early);
 
         do {
                 phys_addr_t page_phys = early ? __pa_symbol(kasan_zero_page)
                                               : kasan_alloc_zeroed_page(node);
                 next = addr + PAGE_SIZE;
-                set_pte(pte, pfn_pte(__phys_to_pfn(page_phys), PAGE_KERNEL));
-        } while (pte++, addr = next, addr != end && pte_none(*pte));
+                set_pte(ptep, pfn_pte(__phys_to_pfn(page_phys), PAGE_KERNEL));
+        } while (ptep++, addr = next, addr != end && pte_none(READ_ONCE(*ptep)));
 }
 
-static void __init kasan_pmd_populate(pud_t *pud, unsigned long addr,
+static void __init kasan_pmd_populate(pud_t *pudp, unsigned long addr,
                                       unsigned long end, int node, bool early)
 {
         unsigned long next;
-        pmd_t *pmd = kasan_pmd_offset(pud, addr, node, early);
+        pmd_t *pmdp = kasan_pmd_offset(pudp, addr, node, early);
 
         do {
                 next = pmd_addr_end(addr, end);
-                kasan_pte_populate(pmd, addr, next, node, early);
-        } while (pmd++, addr = next, addr != end && pmd_none(*pmd));
+                kasan_pte_populate(pmdp, addr, next, node, early);
+        } while (pmdp++, addr = next, addr != end && pmd_none(READ_ONCE(*pmdp)));
 }
 
-static void __init kasan_pud_populate(pgd_t *pgd, unsigned long addr,
+static void __init kasan_pud_populate(pgd_t *pgdp, unsigned long addr,
                                       unsigned long end, int node, bool early)
 {
         unsigned long next;
-        pud_t *pud = kasan_pud_offset(pgd, addr, node, early);
+        pud_t *pudp = kasan_pud_offset(pgdp, addr, node, early);
 
         do {
                 next = pud_addr_end(addr, end);
-                kasan_pmd_populate(pud, addr, next, node, early);
-        } while (pud++, addr = next, addr != end && pud_none(*pud));
+                kasan_pmd_populate(pudp, addr, next, node, early);
+        } while (pudp++, addr = next, addr != end && pud_none(READ_ONCE(*pudp)));
 }
 
 static void __init kasan_pgd_populate(unsigned long addr, unsigned long end,
                                       int node, bool early)
 {
         unsigned long next;
-        pgd_t *pgd;
+        pgd_t *pgdp;
 
-        pgd = pgd_offset_k(addr);
+        pgdp = pgd_offset_k(addr);
         do {
                 next = pgd_addr_end(addr, end);
-                kasan_pud_populate(pgd, addr, next, node, early);
-        } while (pgd++, addr = next, addr != end);
+                kasan_pud_populate(pgdp, addr, next, node, early);
+        } while (pgdp++, addr = next, addr != end);
 }
 
 /* The early shadow maps everything to a single page of zeroes */
@@ -155,14 +155,14 @@ static void __init kasan_map_populate(unsigned long start, unsigned long end,
  */
 void __init kasan_copy_shadow(pgd_t *pgdir)
 {
-        pgd_t *pgd, *pgd_new, *pgd_end;
+        pgd_t *pgdp, *pgdp_new, *pgdp_end;
 
-        pgd = pgd_offset_k(KASAN_SHADOW_START);
-        pgd_end = pgd_offset_k(KASAN_SHADOW_END);
-        pgd_new = pgd_offset_raw(pgdir, KASAN_SHADOW_START);
+        pgdp = pgd_offset_k(KASAN_SHADOW_START);
+        pgdp_end = pgd_offset_k(KASAN_SHADOW_END);
+        pgdp_new = pgd_offset_raw(pgdir, KASAN_SHADOW_START);
         do {
-                set_pgd(pgd_new, *pgd);
-        } while (pgd++, pgd_new++, pgd != pgd_end);
+                set_pgd(pgdp_new, READ_ONCE(*pgdp));
+        } while (pgdp++, pgdp_new++, pgdp != pgdp_end);
 }
 
 static void __init clear_pgds(unsigned long start,
diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
index 4694cda823c9..84a019f55022 100644
--- a/arch/arm64/mm/mmu.c
+++ b/arch/arm64/mm/mmu.c
@@ -125,45 +125,48 @@ static bool pgattr_change_is_safe(u64 old, u64 new)
         return ((old ^ new) & ~mask) == 0;
 }
 
-static void init_pte(pmd_t *pmd, unsigned long addr, unsigned long end,
+static void init_pte(pmd_t *pmdp, unsigned long addr, unsigned long end,
                      phys_addr_t phys, pgprot_t prot)
 {
-        pte_t *pte;
+        pte_t *ptep;
 
-        pte = pte_set_fixmap_offset(pmd, addr);
+        ptep = pte_set_fixmap_offset(pmdp, addr);
         do {
-                pte_t old_pte = *pte;
+                pte_t old_pte = READ_ONCE(*ptep);
 
-                set_pte(pte, pfn_pte(__phys_to_pfn(phys), prot));
+                set_pte(ptep, pfn_pte(__phys_to_pfn(phys), prot));
 
                 /*
                  * After the PTE entry has been populated once, we
                  * only allow updates to the permission attributes.
                  */
-                BUG_ON(!pgattr_change_is_safe(pte_val(old_pte), pte_val(*pte)));
+                BUG_ON(!pgattr_change_is_safe(pte_val(old_pte),
+                                              READ_ONCE(pte_val(*ptep))));
 
                 phys += PAGE_SIZE;
-        } while (pte++, addr += PAGE_SIZE, addr != end);
+        } while (ptep++, addr += PAGE_SIZE, addr != end);
 
         pte_clear_fixmap();
 }
 
-static void alloc_init_cont_pte(pmd_t *pmd, unsigned long addr,
+static void alloc_init_cont_pte(pmd_t *pmdp, unsigned long addr,
                                 unsigned long end, phys_addr_t phys,
                                 pgprot_t prot,
                                 phys_addr_t (*pgtable_alloc)(void),
                                 int flags)
 {
         unsigned long next;
+        pmd_t pmd = READ_ONCE(*pmdp);
 
-        BUG_ON(pmd_sect(*pmd));
-        if (pmd_none(*pmd)) {
+        BUG_ON(pmd_sect(pmd));
+        if (pmd_none(pmd)) {
                 phys_addr_t pte_phys;
                 BUG_ON(!pgtable_alloc);
                 pte_phys = pgtable_alloc();
-                __pmd_populate(pmd, pte_phys, PMD_TYPE_TABLE);
+                __pmd_populate(pmdp, pte_phys, PMD_TYPE_TABLE);
+                pmd = READ_ONCE(*pmdp);
         }
-        BUG_ON(pmd_bad(*pmd));
+        BUG_ON(pmd_bad(pmd));
 
         do {
                 pgprot_t __prot = prot;
@@ -175,67 +178,69 @@ static void alloc_init_cont_pte(pmd_t *pmd, unsigned long addr,
                     (flags & NO_CONT_MAPPINGS) == 0)
                         __prot = __pgprot(pgprot_val(prot) | PTE_CONT);
 
-                init_pte(pmd, addr, next, phys, __prot);
+                init_pte(pmdp, addr, next, phys, __prot);
 
                 phys += next - addr;
         } while (addr = next, addr != end);
 }
 
-static void init_pmd(pud_t *pud, unsigned long addr, unsigned long end,
+static void init_pmd(pud_t *pudp, unsigned long addr, unsigned long end,
                      phys_addr_t phys, pgprot_t prot,
                      phys_addr_t (*pgtable_alloc)(void), int flags)
 {
         unsigned long next;
-        pmd_t *pmd;
+        pmd_t *pmdp;
 
-        pmd = pmd_set_fixmap_offset(pud, addr);
+        pmdp = pmd_set_fixmap_offset(pudp, addr);
         do {
-                pmd_t old_pmd = *pmd;
+                pmd_t old_pmd = READ_ONCE(*pmdp);
 
                 next = pmd_addr_end(addr, end);
 
                 /* try section mapping first */
                 if (((addr | next | phys) & ~SECTION_MASK) == 0 &&
                     (flags & NO_BLOCK_MAPPINGS) == 0) {
-                        pmd_set_huge(pmd, phys, prot);
+                        pmd_set_huge(pmdp, phys, prot);
 
                         /*
                          * After the PMD entry has been populated once, we
                          * only allow updates to the permission attributes.
                          */
                         BUG_ON(!pgattr_change_is_safe(pmd_val(old_pmd),
-                                                      pmd_val(*pmd)));
+                                                      READ_ONCE(pmd_val(*pmdp))));
                 } else {
-                        alloc_init_cont_pte(pmd, addr, next, phys, prot,
+                        alloc_init_cont_pte(pmdp, addr, next, phys, prot,
                                             pgtable_alloc, flags);
 
                         BUG_ON(pmd_val(old_pmd) != 0 &&
-                               pmd_val(old_pmd) != pmd_val(*pmd));
+                               pmd_val(old_pmd) != READ_ONCE(pmd_val(*pmdp)));
                 }
                 phys += next - addr;
-        } while (pmd++, addr = next, addr != end);
+        } while (pmdp++, addr = next, addr != end);
 
         pmd_clear_fixmap();
 }
 
-static void alloc_init_cont_pmd(pud_t *pud, unsigned long addr,
+static void alloc_init_cont_pmd(pud_t *pudp, unsigned long addr,
                                 unsigned long end, phys_addr_t phys,
                                 pgprot_t prot,
                                 phys_addr_t (*pgtable_alloc)(void), int flags)
 {
         unsigned long next;
+        pud_t pud = READ_ONCE(*pudp);
 
         /*
          * Check for initial section mappings in the pgd/pud.
          */
-        BUG_ON(pud_sect(*pud));
-        if (pud_none(*pud)) {
+        BUG_ON(pud_sect(pud));
+        if (pud_none(pud)) {
                 phys_addr_t pmd_phys;
                 BUG_ON(!pgtable_alloc);
                 pmd_phys = pgtable_alloc();
-                __pud_populate(pud, pmd_phys, PUD_TYPE_TABLE);
+                __pud_populate(pudp, pmd_phys, PUD_TYPE_TABLE);
+                pud = READ_ONCE(*pudp);
         }
-        BUG_ON(pud_bad(*pud));
+        BUG_ON(pud_bad(pud));
 
         do {
                 pgprot_t __prot = prot;
@@ -247,7 +252,7 @@ static void alloc_init_cont_pmd(pud_t *pud, unsigned long addr,
                     (flags & NO_CONT_MAPPINGS) == 0)
                         __prot = __pgprot(pgprot_val(prot) | PTE_CONT);
 
-                init_pmd(pud, addr, next, phys, __prot, pgtable_alloc, flags);
+                init_pmd(pudp, addr, next, phys, __prot, pgtable_alloc, flags);
 
                 phys += next - addr;
         } while (addr = next, addr != end);
@@ -265,25 +270,27 @@ static inline bool use_1G_block(unsigned long addr, unsigned long next,
         return true;
 }
 
-static void alloc_init_pud(pgd_t *pgd, unsigned long addr, unsigned long end,
-                                  phys_addr_t phys, pgprot_t prot,
-                                  phys_addr_t (*pgtable_alloc)(void),
-                                  int flags)
+static void alloc_init_pud(pgd_t *pgdp, unsigned long addr, unsigned long end,
+                           phys_addr_t phys, pgprot_t prot,
+                           phys_addr_t (*pgtable_alloc)(void),
+                           int flags)
 {
-        pud_t *pud;
         unsigned long next;
+        pud_t *pudp;
+        pgd_t pgd = READ_ONCE(*pgdp);
 
-        if (pgd_none(*pgd)) {
+        if (pgd_none(pgd)) {
                 phys_addr_t pud_phys;
                 BUG_ON(!pgtable_alloc);
                 pud_phys = pgtable_alloc();
-                __pgd_populate(pgd, pud_phys, PUD_TYPE_TABLE);
+                __pgd_populate(pgdp, pud_phys, PUD_TYPE_TABLE);
+                pgd = READ_ONCE(*pgdp);
         }
-        BUG_ON(pgd_bad(*pgd));
+        BUG_ON(pgd_bad(pgd));
 
-        pud = pud_set_fixmap_offset(pgd, addr);
+        pudp = pud_set_fixmap_offset(pgdp, addr);
         do {
-                pud_t old_pud = *pud;
+                pud_t old_pud = READ_ONCE(*pudp);
 
                 next = pud_addr_end(addr, end);
 
@@ -292,23 +299,23 @@ static void alloc_init_pud(pgd_t *pgd, unsigned long addr, unsigned long end,
                  */
                 if (use_1G_block(addr, next, phys) &&
                     (flags & NO_BLOCK_MAPPINGS) == 0) {
-                        pud_set_huge(pud, phys, prot);
+                        pud_set_huge(pudp, phys, prot);
 
                         /*
                          * After the PUD entry has been populated once, we
                          * only allow updates to the permission attributes.
                          */
                         BUG_ON(!pgattr_change_is_safe(pud_val(old_pud),
-                                                      pud_val(*pud)));
+                                                      READ_ONCE(pud_val(*pudp))));
                 } else {
-                        alloc_init_cont_pmd(pud, addr, next, phys, prot,
+                        alloc_init_cont_pmd(pudp, addr, next, phys, prot,
                                             pgtable_alloc, flags);
 
                         BUG_ON(pud_val(old_pud) != 0 &&
-                               pud_val(old_pud) != pud_val(*pud));
+                               pud_val(old_pud) != READ_ONCE(pud_val(*pudp)));
                 }
                 phys += next - addr;
-        } while (pud++, addr = next, addr != end);
+        } while (pudp++, addr = next, addr != end);
 
         pud_clear_fixmap();
 }
@@ -320,7 +327,7 @@ static void __create_pgd_mapping(pgd_t *pgdir, phys_addr_t phys,
                                  int flags)
 {
         unsigned long addr, length, end, next;
-        pgd_t *pgd = pgd_offset_raw(pgdir, virt);
+        pgd_t *pgdp = pgd_offset_raw(pgdir, virt);
 
         /*
          * If the virtual and physical address don't have the same offset
@@ -336,10 +343,10 @@ static void __create_pgd_mapping(pgd_t *pgdir, phys_addr_t phys,
         end = addr + length;
         do {
                 next = pgd_addr_end(addr, end);
-                alloc_init_pud(pgd, addr, next, phys, prot, pgtable_alloc,
+                alloc_init_pud(pgdp, addr, next, phys, prot, pgtable_alloc,
                                flags);
                 phys += next - addr;
-        } while (pgd++, addr = next, addr != end);
+        } while (pgdp++, addr = next, addr != end);
 }
 
 static phys_addr_t pgd_pgtable_alloc(void)
@@ -401,10 +408,10 @@ static void update_mapping_prot(phys_addr_t phys, unsigned long virt,
         flush_tlb_kernel_range(virt, virt + size);
 }
 
-static void __init __map_memblock(pgd_t *pgd, phys_addr_t start,
+static void __init __map_memblock(pgd_t *pgdp, phys_addr_t start,
                                   phys_addr_t end, pgprot_t prot, int flags)
 {
-        __create_pgd_mapping(pgd, start, __phys_to_virt(start), end - start,
+        __create_pgd_mapping(pgdp, start, __phys_to_virt(start), end - start,
                              prot, early_pgtable_alloc, flags);
 }
 
@@ -418,7 +425,7 @@ void __init mark_linear_text_alias_ro(void)
                             PAGE_KERNEL_RO);
 }
 
-static void __init map_mem(pgd_t *pgd)
+static void __init map_mem(pgd_t *pgdp)
 {
         phys_addr_t kernel_start = __pa_symbol(_text);
         phys_addr_t kernel_end = __pa_symbol(__init_begin);
@@ -451,7 +458,7 @@ static void __init map_mem(pgd_t *pgd)
                 if (memblock_is_nomap(reg))
                         continue;
 
-                __map_memblock(pgd, start, end, PAGE_KERNEL, flags);
+                __map_memblock(pgdp, start, end, PAGE_KERNEL, flags);
         }
 
         /*
@@ -464,7 +471,7 @@ static void __init map_mem(pgd_t *pgd)
          * Note that contiguous mappings cannot be remapped in this way,
          * so we should avoid them here.
          */
-        __map_memblock(pgd, kernel_start, kernel_end,
+        __map_memblock(pgdp, kernel_start, kernel_end,
                        PAGE_KERNEL, NO_CONT_MAPPINGS);
         memblock_clear_nomap(kernel_start, kernel_end - kernel_start);
 
@@ -475,7 +482,7 @@ static void __init map_mem(pgd_t *pgd)
          * through /sys/kernel/kexec_crash_size interface.
          */
         if (crashk_res.end) {
-                __map_memblock(pgd, crashk_res.start, crashk_res.end + 1,
+                __map_memblock(pgdp, crashk_res.start, crashk_res.end + 1,
                                PAGE_KERNEL,
                                NO_BLOCK_MAPPINGS | NO_CONT_MAPPINGS);
                 memblock_clear_nomap(crashk_res.start,
@@ -499,7 +506,7 @@ void mark_rodata_ro(void)
         debug_checkwx();
 }
 
-static void __init map_kernel_segment(pgd_t *pgd, void *va_start, void *va_end,
+static void __init map_kernel_segment(pgd_t *pgdp, void *va_start, void *va_end,
                                       pgprot_t prot, struct vm_struct *vma,
                                       int flags, unsigned long vm_flags)
 {
@@ -509,7 +516,7 @@ static void __init map_kernel_segment(pgd_t *pgd, void *va_start, void *va_end,
         BUG_ON(!PAGE_ALIGNED(pa_start));
         BUG_ON(!PAGE_ALIGNED(size));
 
-        __create_pgd_mapping(pgd, pa_start, (unsigned long)va_start, size, prot,
+        __create_pgd_mapping(pgdp, pa_start, (unsigned long)va_start, size, prot,
                              early_pgtable_alloc, flags);
 
         if (!(vm_flags & VM_NO_GUARD))
@@ -562,7 +569,7 @@ core_initcall(map_entry_trampoline);
 /*
  * Create fine-grained mappings for the kernel.
  */
-static void __init map_kernel(pgd_t *pgd)
+static void __init map_kernel(pgd_t *pgdp)
 {
         static struct vm_struct vmlinux_text, vmlinux_rodata, vmlinux_inittext,
                                 vmlinux_initdata, vmlinux_data;
@@ -578,24 +585,24 @@ static void __init map_kernel(pgd_t *pgd)
          * Only rodata will be remapped with different permissions later on,
          * all other segments are allowed to use contiguous mappings.
          */
-        map_kernel_segment(pgd, _text, _etext, text_prot, &vmlinux_text, 0,
+        map_kernel_segment(pgdp, _text, _etext, text_prot, &vmlinux_text, 0,
                            VM_NO_GUARD);
-        map_kernel_segment(pgd, __start_rodata, __inittext_begin, PAGE_KERNEL,
+        map_kernel_segment(pgdp, __start_rodata, __inittext_begin, PAGE_KERNEL,
                            &vmlinux_rodata, NO_CONT_MAPPINGS, VM_NO_GUARD);
-        map_kernel_segment(pgd, __inittext_begin, __inittext_end, text_prot,
+        map_kernel_segment(pgdp, __inittext_begin, __inittext_end, text_prot,
                            &vmlinux_inittext, 0, VM_NO_GUARD);
-        map_kernel_segment(pgd, __initdata_begin, __initdata_end, PAGE_KERNEL,
+        map_kernel_segment(pgdp, __initdata_begin, __initdata_end, PAGE_KERNEL,
                            &vmlinux_initdata, 0, VM_NO_GUARD);
-        map_kernel_segment(pgd, _data, _end, PAGE_KERNEL, &vmlinux_data, 0, 0);
+        map_kernel_segment(pgdp, _data, _end, PAGE_KERNEL, &vmlinux_data, 0, 0);
 
-        if (!pgd_val(*pgd_offset_raw(pgd, FIXADDR_START))) {
+        if (!READ_ONCE(pgd_val(*pgd_offset_raw(pgdp, FIXADDR_START)))) {
                 /*
                  * The fixmap falls in a separate pgd to the kernel, and doesn't
                  * live in the carveout for the swapper_pg_dir. We can simply
                  * re-use the existing dir for the fixmap.
                  */
-                set_pgd(pgd_offset_raw(pgd, FIXADDR_START),
-                        *pgd_offset_k(FIXADDR_START));
+                set_pgd(pgd_offset_raw(pgdp, FIXADDR_START),
+                        READ_ONCE(*pgd_offset_k(FIXADDR_START)));
         } else if (CONFIG_PGTABLE_LEVELS > 3) {
                 /*
                  * The fixmap shares its top level pgd entry with the kernel
@@ -604,14 +611,15 @@ static void __init map_kernel(pgd_t *pgd)
                  * entry instead.
                  */
                 BUG_ON(!IS_ENABLED(CONFIG_ARM64_16K_PAGES));
-                pud_populate(&init_mm, pud_set_fixmap_offset(pgd, FIXADDR_START),
+                pud_populate(&init_mm,
+                             pud_set_fixmap_offset(pgdp, FIXADDR_START),
                              lm_alias(bm_pmd));
                 pud_clear_fixmap();
         } else {
                 BUG();
         }
 
-        kasan_copy_shadow(pgd);
+        kasan_copy_shadow(pgdp);
 }
 
 /*
@@ -621,10 +629,10 @@ static void __init map_kernel(pgd_t *pgd)
 void __init paging_init(void)
 {
         phys_addr_t pgd_phys = early_pgtable_alloc();
-        pgd_t *pgd = pgd_set_fixmap(pgd_phys);
+        pgd_t *pgdp = pgd_set_fixmap(pgd_phys);
 
-        map_kernel(pgd);
-        map_mem(pgd);
+        map_kernel(pgdp);
+        map_mem(pgdp);
 
         /*
          * We want to reuse the original swapper_pg_dir so we don't have to
@@ -635,7 +643,7 @@ void __init paging_init(void)
          * To do this we need to go via a temporary pgd.
          */
         cpu_replace_ttbr1(__va(pgd_phys));
-        memcpy(swapper_pg_dir, pgd, PGD_SIZE);
+        memcpy(swapper_pg_dir, pgdp, PGD_SIZE);
         cpu_replace_ttbr1(lm_alias(swapper_pg_dir));
 
         pgd_clear_fixmap();
@@ -655,37 +663,40 @@ void __init paging_init(void)
  */
 int kern_addr_valid(unsigned long addr)
 {
-        pgd_t *pgd;
-        pud_t *pud;
-        pmd_t *pmd;
-        pte_t *pte;
+        pgd_t *pgdp;
+        pud_t *pudp, pud;
+        pmd_t *pmdp, pmd;
+        pte_t *ptep, pte;
 
         if ((((long)addr) >> VA_BITS) != -1UL)
                 return 0;
 
-        pgd = pgd_offset_k(addr);
-        if (pgd_none(*pgd))
+        pgdp = pgd_offset_k(addr);
+        if (pgd_none(READ_ONCE(*pgdp)))
                 return 0;
 
-        pud = pud_offset(pgd, addr);
-        if (pud_none(*pud))
+        pudp = pud_offset(pgdp, addr);
+        pud = READ_ONCE(*pudp);
+        if (pud_none(pud))
                 return 0;
 
-        if (pud_sect(*pud))
-                return pfn_valid(pud_pfn(*pud));
+        if (pud_sect(pud))
+                return pfn_valid(pud_pfn(pud));
 
-        pmd = pmd_offset(pud, addr);
-        if (pmd_none(*pmd))
+        pmdp = pmd_offset(pudp, addr);
+        pmd = READ_ONCE(*pmdp);
+        if (pmd_none(pmd))
                 return 0;
 
-        if (pmd_sect(*pmd))
-                return pfn_valid(pmd_pfn(*pmd));
+        if (pmd_sect(pmd))
+                return pfn_valid(pmd_pfn(pmd));
 
-        pte = pte_offset_kernel(pmd, addr);
-        if (pte_none(*pte))
+        ptep = pte_offset_kernel(pmdp, addr);
+        pte = READ_ONCE(*ptep);
+        if (pte_none(pte))
                 return 0;
 
-        return pfn_valid(pte_pfn(*pte));
+        return pfn_valid(pte_pfn(pte));
 }
 #ifdef CONFIG_SPARSEMEM_VMEMMAP
 #if !ARM64_SWAPPER_USES_SECTION_MAPS
@@ -700,32 +711,32 @@ int __meminit vmemmap_populate(unsigned long start, unsigned long end, int node,
 {
         unsigned long addr = start;
         unsigned long next;
-        pgd_t *pgd;
-        pud_t *pud;
-        pmd_t *pmd;
+        pgd_t *pgdp;
+        pud_t *pudp;
+        pmd_t *pmdp;
 
         do {
                 next = pmd_addr_end(addr, end);
 
-                pgd = vmemmap_pgd_populate(addr, node);
-                if (!pgd)
+                pgdp = vmemmap_pgd_populate(addr, node);
+                if (!pgdp)
                         return -ENOMEM;
 
-                pud = vmemmap_pud_populate(pgd, addr, node);
-                if (!pud)
+                pudp = vmemmap_pud_populate(pgdp, addr, node);
+                if (!pudp)
                         return -ENOMEM;
 
-                pmd = pmd_offset(pud, addr);
-                if (pmd_none(*pmd)) {
+                pmdp = pmd_offset(pudp, addr);
+                if (pmd_none(READ_ONCE(*pmdp))) {
                         void *p = NULL;
 
                         p = vmemmap_alloc_block_buf(PMD_SIZE, node);
                         if (!p)
                                 return -ENOMEM;
 
-                        pmd_set_huge(pmd, __pa(p), __pgprot(PROT_SECT_NORMAL));
+                        pmd_set_huge(pmdp, __pa(p), __pgprot(PROT_SECT_NORMAL));
                 } else
-                        vmemmap_verify((pte_t *)pmd, node, addr, next);
+                        vmemmap_verify((pte_t *)pmdp, node, addr, next);
         } while (addr = next, addr != end);
 
         return 0;
@@ -739,20 +750,22 @@ void vmemmap_free(unsigned long start, unsigned long end,
 
 static inline pud_t * fixmap_pud(unsigned long addr)
 {
-        pgd_t *pgd = pgd_offset_k(addr);
+        pgd_t *pgdp = pgd_offset_k(addr);
+        pgd_t pgd = READ_ONCE(*pgdp);
 
-        BUG_ON(pgd_none(*pgd) || pgd_bad(*pgd));
+        BUG_ON(pgd_none(pgd) || pgd_bad(pgd));
 
-        return pud_offset_kimg(pgd, addr);
+        return pud_offset_kimg(pgdp, addr);
 }
 
 static inline pmd_t * fixmap_pmd(unsigned long addr)
 {
-        pud_t *pud = fixmap_pud(addr);
+        pud_t *pudp = fixmap_pud(addr);
+        pud_t pud = READ_ONCE(*pudp);
 
-        BUG_ON(pud_none(*pud) || pud_bad(*pud));
+        BUG_ON(pud_none(pud) || pud_bad(pud));
 
-        return pmd_offset_kimg(pud, addr);
+        return pmd_offset_kimg(pudp, addr);
 }
 
 static inline pte_t * fixmap_pte(unsigned long addr)
@@ -768,30 +781,31 @@ static inline pte_t * fixmap_pte(unsigned long addr)
  */
 void __init early_fixmap_init(void)
 {
-        pgd_t *pgd;
-        pud_t *pud;
-        pmd_t *pmd;
+        pgd_t *pgdp, pgd;
+        pud_t *pudp;
+        pmd_t *pmdp;
         unsigned long addr = FIXADDR_START;
 
-        pgd = pgd_offset_k(addr);
+        pgdp = pgd_offset_k(addr);
+        pgd = READ_ONCE(*pgdp);
         if (CONFIG_PGTABLE_LEVELS > 3 &&
-            !(pgd_none(*pgd) || pgd_page_paddr(*pgd) == __pa_symbol(bm_pud))) {
+            !(pgd_none(pgd) || pgd_page_paddr(pgd) == __pa_symbol(bm_pud))) {
                 /*
                  * We only end up here if the kernel mapping and the fixmap
                  * share the top level pgd entry, which should only happen on
                  * 16k/4 levels configurations.
                  */
                 BUG_ON(!IS_ENABLED(CONFIG_ARM64_16K_PAGES));
-                pud = pud_offset_kimg(pgd, addr);
+                pudp = pud_offset_kimg(pgdp, addr);
         } else {
-                if (pgd_none(*pgd))
-                        __pgd_populate(pgd, __pa_symbol(bm_pud), PUD_TYPE_TABLE);
-                pud = fixmap_pud(addr);
+                if (pgd_none(pgd))
+                        __pgd_populate(pgdp, __pa_symbol(bm_pud), PUD_TYPE_TABLE);
+                pudp = fixmap_pud(addr);
         }
-        if (pud_none(*pud))
-                __pud_populate(pud, __pa_symbol(bm_pmd), PMD_TYPE_TABLE);
-        pmd = fixmap_pmd(addr);
-        __pmd_populate(pmd, __pa_symbol(bm_pte), PMD_TYPE_TABLE);
+        if (pud_none(READ_ONCE(*pudp)))
+                __pud_populate(pudp, __pa_symbol(bm_pmd), PMD_TYPE_TABLE);
+        pmdp = fixmap_pmd(addr);
+        __pmd_populate(pmdp, __pa_symbol(bm_pte), PMD_TYPE_TABLE);
 
         /*
          * The boot-ioremap range spans multiple pmds, for which
@@ -800,11 +814,11 @@ void __init early_fixmap_init(void)
         BUILD_BUG_ON((__fix_to_virt(FIX_BTMAP_BEGIN) >> PMD_SHIFT)
                      != (__fix_to_virt(FIX_BTMAP_END) >> PMD_SHIFT));
 
-        if ((pmd != fixmap_pmd(fix_to_virt(FIX_BTMAP_BEGIN)))
-             || pmd != fixmap_pmd(fix_to_virt(FIX_BTMAP_END))) {
+        if ((pmdp != fixmap_pmd(fix_to_virt(FIX_BTMAP_BEGIN)))
+             || pmdp != fixmap_pmd(fix_to_virt(FIX_BTMAP_END))) {
                 WARN_ON(1);
-                pr_warn("pmd %p != %p, %p\n",
-                        pmd, fixmap_pmd(fix_to_virt(FIX_BTMAP_BEGIN)),
+                pr_warn("pmdp %p != %p, %p\n",
+                        pmdp, fixmap_pmd(fix_to_virt(FIX_BTMAP_BEGIN)),
                         fixmap_pmd(fix_to_virt(FIX_BTMAP_END)));
                 pr_warn("fix_to_virt(FIX_BTMAP_BEGIN): %08lx\n",
                         fix_to_virt(FIX_BTMAP_BEGIN));
@@ -824,16 +838,16 @@ void __set_fixmap(enum fixed_addresses idx,
                                phys_addr_t phys, pgprot_t flags)
 {
         unsigned long addr = __fix_to_virt(idx);
-        pte_t *pte;
+        pte_t *ptep;
 
         BUG_ON(idx <= FIX_HOLE || idx >= __end_of_fixed_addresses);
 
-        pte = fixmap_pte(addr);
+        ptep = fixmap_pte(addr);
 
         if (pgprot_val(flags)) {
-                set_pte(pte, pfn_pte(phys >> PAGE_SHIFT, flags));
+                set_pte(ptep, pfn_pte(phys >> PAGE_SHIFT, flags));
         } else {
-                pte_clear(&init_mm, addr, pte);
+                pte_clear(&init_mm, addr, ptep);
                 flush_tlb_kernel_range(addr, addr+PAGE_SIZE);
         }
 }
@@ -915,36 +929,46 @@ int __init arch_ioremap_pmd_supported(void)
         return 1;
 }
 
-int pud_set_huge(pud_t *pud, phys_addr_t phys, pgprot_t prot)
+int pud_set_huge(pud_t *pudp, phys_addr_t phys, pgprot_t prot)
 {
         pgprot_t sect_prot = __pgprot(PUD_TYPE_SECT |
                                         pgprot_val(mk_sect_prot(prot)));
+
+        /* ioremap_page_range doesn't honour BBM */
+        if (pud_present(READ_ONCE(*pudp)))
+                return 0;
+
         BUG_ON(phys & ~PUD_MASK);
-        set_pud(pud, pfn_pud(__phys_to_pfn(phys), sect_prot));
+        set_pud(pudp, pfn_pud(__phys_to_pfn(phys), sect_prot));
         return 1;
 }
 
-int pmd_set_huge(pmd_t *pmd, phys_addr_t phys, pgprot_t prot)
+int pmd_set_huge(pmd_t *pmdp, phys_addr_t phys, pgprot_t prot)
 {
         pgprot_t sect_prot = __pgprot(PMD_TYPE_SECT |
                                         pgprot_val(mk_sect_prot(prot)));
+
+        /* ioremap_page_range doesn't honour BBM */
+        if (pmd_present(READ_ONCE(*pmdp)))
+                return 0;
+
         BUG_ON(phys & ~PMD_MASK);
-        set_pmd(pmd, pfn_pmd(__phys_to_pfn(phys), sect_prot));
+        set_pmd(pmdp, pfn_pmd(__phys_to_pfn(phys), sect_prot));
         return 1;
 }
 
-int pud_clear_huge(pud_t *pud)
+int pud_clear_huge(pud_t *pudp)
 {
-        if (!pud_sect(*pud))
+        if (!pud_sect(READ_ONCE(*pudp)))
                 return 0;
-        pud_clear(pud);
+        pud_clear(pudp);
         return 1;
 }
 
-int pmd_clear_huge(pmd_t *pmd)
+int pmd_clear_huge(pmd_t *pmdp)
 {
-        if (!pmd_sect(*pmd))
+        if (!pmd_sect(READ_ONCE(*pmdp)))
                 return 0;
-        pmd_clear(pmd);
+        pmd_clear(pmdp);
         return 1;
 }
diff --git a/arch/arm64/mm/pageattr.c b/arch/arm64/mm/pageattr.c
index a682a0a2a0fa..a56359373d8b 100644
--- a/arch/arm64/mm/pageattr.c
+++ b/arch/arm64/mm/pageattr.c
@@ -29,7 +29,7 @@ static int change_page_range(pte_t *ptep, pgtable_t token, unsigned long addr,
                         void *data)
 {
         struct page_change_data *cdata = data;
-        pte_t pte = *ptep;
+        pte_t pte = READ_ONCE(*ptep);
 
         pte = clear_pte_bit(pte, cdata->clear_mask);
         pte = set_pte_bit(pte, cdata->set_mask);
@@ -156,30 +156,32 @@ void __kernel_map_pages(struct page *page, int numpages, int enable)
  */
 bool kernel_page_present(struct page *page)
 {
-        pgd_t *pgd;
-        pud_t *pud;
-        pmd_t *pmd;
-        pte_t *pte;
+        pgd_t *pgdp;
+        pud_t *pudp, pud;
+        pmd_t *pmdp, pmd;
+        pte_t *ptep;
         unsigned long addr = (unsigned long)page_address(page);
 
-        pgd = pgd_offset_k(addr);
-        if (pgd_none(*pgd))
+        pgdp = pgd_offset_k(addr);
+        if (pgd_none(READ_ONCE(*pgdp)))
                 return false;
 
-        pud = pud_offset(pgd, addr);
-        if (pud_none(*pud))
+        pudp = pud_offset(pgdp, addr);
+        pud = READ_ONCE(*pudp);
+        if (pud_none(pud))
                 return false;
-        if (pud_sect(*pud))
+        if (pud_sect(pud))
                 return true;
 
-        pmd = pmd_offset(pud, addr);
-        if (pmd_none(*pmd))
+        pmdp = pmd_offset(pudp, addr);
+        pmd = READ_ONCE(*pmdp);
+        if (pmd_none(pmd))
                 return false;
-        if (pmd_sect(*pmd))
+        if (pmd_sect(pmd))
                 return true;
 
-        pte = pte_offset_kernel(pmd, addr);
-        return pte_valid(*pte);
+        ptep = pte_offset_kernel(pmdp, addr);
+        return pte_valid(READ_ONCE(*ptep));
 }
 #endif /* CONFIG_HIBERNATION */
 #endif /* CONFIG_DEBUG_PAGEALLOC */
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index 71baed7e592a..c0af47617299 100644
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -205,7 +205,8 @@ ENDPROC(idmap_cpu_replace_ttbr1)
         dc      cvac, cur_\()\type\()p          // Ensure any existing dirty
         dmb     sy                              // lines are written back before
         ldr     \type, [cur_\()\type\()p]       // loading the entry
-        tbz     \type, #0, next_\()\type        // Skip invalid entries
+        tbz     \type, #0, skip_\()\type        // Skip invalid and
+        tbnz    \type, #11, skip_\()\type       // non-global entries
         .endm
 
         .macro __idmap_kpti_put_pgtable_ent_ng, type
@@ -265,8 +266,9 @@ ENTRY(idmap_kpti_install_ng_mappings)
         add     end_pgdp, cur_pgdp, #(PTRS_PER_PGD * 8)
 do_pgd: __idmap_kpti_get_pgtable_ent    pgd
         tbnz    pgd, #1, walk_puds
-        __idmap_kpti_put_pgtable_ent_ng pgd
 next_pgd:
+        __idmap_kpti_put_pgtable_ent_ng pgd
+skip_pgd:
         add     cur_pgdp, cur_pgdp, #8
         cmp     cur_pgdp, end_pgdp
         b.ne    do_pgd
@@ -294,8 +296,9 @@ walk_puds:
         add     end_pudp, cur_pudp, #(PTRS_PER_PUD * 8)
 do_pud: __idmap_kpti_get_pgtable_ent    pud
         tbnz    pud, #1, walk_pmds
-        __idmap_kpti_put_pgtable_ent_ng pud
 next_pud:
+        __idmap_kpti_put_pgtable_ent_ng pud
+skip_pud:
         add     cur_pudp, cur_pudp, 8
         cmp     cur_pudp, end_pudp
         b.ne    do_pud
@@ -314,8 +317,9 @@ walk_pmds:
         add     end_pmdp, cur_pmdp, #(PTRS_PER_PMD * 8)
 do_pmd: __idmap_kpti_get_pgtable_ent    pmd
         tbnz    pmd, #1, walk_ptes
-        __idmap_kpti_put_pgtable_ent_ng pmd
 next_pmd:
+        __idmap_kpti_put_pgtable_ent_ng pmd
+skip_pmd:
         add     cur_pmdp, cur_pmdp, #8
         cmp     cur_pmdp, end_pmdp
         b.ne    do_pmd
@@ -333,7 +337,7 @@ walk_ptes:
         add     end_ptep, cur_ptep, #(PTRS_PER_PTE * 8)
 do_pte: __idmap_kpti_get_pgtable_ent    pte
         __idmap_kpti_put_pgtable_ent_ng pte
-next_pte:
+skip_pte:
         add     cur_ptep, cur_ptep, #8
         cmp     cur_ptep, end_ptep
         b.ne    do_pte
diff --git a/arch/arm64/net/bpf_jit_comp.c b/arch/arm64/net/bpf_jit_comp.c
index 1d4f1da7c58f..a93350451e8e 100644
--- a/arch/arm64/net/bpf_jit_comp.c
+++ b/arch/arm64/net/bpf_jit_comp.c
@@ -250,8 +250,9 @@ static int emit_bpf_tail_call(struct jit_ctx *ctx)
         off = offsetof(struct bpf_array, map.max_entries);
         emit_a64_mov_i64(tmp, off, ctx);
         emit(A64_LDR32(tmp, r2, tmp), ctx);
+        emit(A64_MOV(0, r3, r3), ctx);
         emit(A64_CMP(0, r3, tmp), ctx);
-        emit(A64_B_(A64_COND_GE, jmp_offset), ctx);
+        emit(A64_B_(A64_COND_CS, jmp_offset), ctx);
 
         /* if (tail_call_cnt > MAX_TAIL_CALL_CNT)
          *     goto out;
@@ -259,7 +260,7 @@ static int emit_bpf_tail_call(struct jit_ctx *ctx)
          */
         emit_a64_mov_i64(tmp, MAX_TAIL_CALL_CNT, ctx);
         emit(A64_CMP(1, tcc, tmp), ctx);
-        emit(A64_B_(A64_COND_GT, jmp_offset), ctx);
+        emit(A64_B_(A64_COND_HI, jmp_offset), ctx);
         emit(A64_ADD_I(1, tcc, tcc, 1), ctx);
 
         /* prog = array->ptrs[index];
diff --git a/arch/cris/include/arch-v10/arch/bug.h b/arch/cris/include/arch-v10/arch/bug.h
index 905afeacfedf..06da9d49152a 100644
--- a/arch/cris/include/arch-v10/arch/bug.h
+++ b/arch/cris/include/arch-v10/arch/bug.h
@@ -44,18 +44,25 @@ struct bug_frame {
  * not be used like this with newer versions of gcc.
  */
 #define BUG()                                                           \
+do {                                                                    \
         __asm__ __volatile__ ("clear.d [" __stringify(BUG_MAGIC) "]\n\t"\
                               "movu.w " __stringify(__LINE__) ",$r0\n\t"\
                               "jump 0f\n\t"                             \
                               ".section .rodata\n"                      \
                               "0:\t.string \"" __FILE__ "\"\n\t"        \
-                              ".previous")
+                              ".previous");                             \
+        unreachable();                                                  \
+} while (0)
 #endif
 
 #else
 
 /* This just causes an oops. */
-#define BUG() (*(int *)0 = 0)
+#define BUG()                                                           \
+do {                                                                    \
+        barrier_before_unreachable();                                   \
+        __builtin_trap();                                               \
+} while (0)
 
 #endif
 
diff --git a/arch/ia64/include/asm/bug.h b/arch/ia64/include/asm/bug.h
index bd3eeb8d1cfa..66b37a532765 100644
--- a/arch/ia64/include/asm/bug.h
+++ b/arch/ia64/include/asm/bug.h
@@ -4,7 +4,11 @@
 
 #ifdef CONFIG_BUG
 #define ia64_abort()    __builtin_trap()
-#define BUG() do { printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); ia64_abort(); } while (0)
+#define BUG() do {                                              \
+        printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__);   \
+        barrier_before_unreachable();                           \
+        ia64_abort();                                           \
+} while (0)
 
 /* should this BUG be made generic? */
 #define HAVE_ARCH_BUG
diff --git a/arch/ia64/kernel/Makefile b/arch/ia64/kernel/Makefile
index 0b4c65a1af25..498f3da3f225 100644
--- a/arch/ia64/kernel/Makefile
+++ b/arch/ia64/kernel/Makefile
@@ -41,7 +41,6 @@ ifneq ($(CONFIG_IA64_ESI),)
 obj-y                           += esi_stub.o   # must be in kernel proper
 endif
 obj-$(CONFIG_INTEL_IOMMU)       += pci-dma.o
-obj-$(CONFIG_SWIOTLB)           += pci-swiotlb.o
 
 obj-$(CONFIG_BINFMT_ELF)        += elfcore.o
 
diff --git a/arch/m68k/include/asm/bug.h b/arch/m68k/include/asm/bug.h
index b7e2bf1ba4a6..275dca1435bf 100644
--- a/arch/m68k/include/asm/bug.h
+++ b/arch/m68k/include/asm/bug.h
@@ -8,16 +8,19 @@
 #ifndef CONFIG_SUN3
 #define BUG() do { \
         pr_crit("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \
+        barrier_before_unreachable(); \
         __builtin_trap(); \
 } while (0)
 #else
 #define BUG() do { \
         pr_crit("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \
+        barrier_before_unreachable(); \
         panic("BUG!"); \
 } while (0)
 #endif
 #else
 #define BUG() do { \
+        barrier_before_unreachable(); \
         __builtin_trap(); \
 } while (0)
 #endif
diff --git a/arch/mips/boot/Makefile b/arch/mips/boot/Makefile
index 1bd5c4f00d19..c22da16d67b8 100644
--- a/arch/mips/boot/Makefile
+++ b/arch/mips/boot/Makefile
@@ -126,6 +126,7 @@ $(obj)/vmlinux.its.S: $(addprefix $(srctree)/arch/mips/$(PLATFORM)/,$(ITS_INPUTS
 
 quiet_cmd_cpp_its_S = ITS     $@
       cmd_cpp_its_S = $(CPP) $(cpp_flags) -P -C -o $@ $< \
+                        -D__ASSEMBLY__ \
                         -DKERNEL_NAME="\"Linux $(KERNELRELEASE)\"" \
                         -DVMLINUX_BINARY="\"$(3)\"" \
                         -DVMLINUX_COMPRESSION="\"$(2)\"" \
diff --git a/arch/mips/include/asm/compat.h b/arch/mips/include/asm/compat.h
index 946681db8dc3..9a0fa66b81ac 100644
--- a/arch/mips/include/asm/compat.h
+++ b/arch/mips/include/asm/compat.h
@@ -86,7 +86,6 @@ struct compat_flock {
         compat_off_t    l_len;
         s32             l_sysid;
         compat_pid_t    l_pid;
-        short           __unused;
         s32             pad[4];
 };
 
diff --git a/arch/mips/kernel/mips-cpc.c b/arch/mips/kernel/mips-cpc.c
index 19c88d770054..fcf9af492d60 100644
--- a/arch/mips/kernel/mips-cpc.c
+++ b/arch/mips/kernel/mips-cpc.c
@@ -10,6 +10,8 @@
 
 #include <linux/errno.h>
 #include <linux/percpu.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 #include <linux/spinlock.h>
 
 #include <asm/mips-cps.h>
@@ -22,6 +24,17 @@ static DEFINE_PER_CPU_ALIGNED(unsigned long, cpc_core_lock_flags);
 
 phys_addr_t __weak mips_cpc_default_phys_base(void)
 {
+        struct device_node *cpc_node;
+        struct resource res;
+        int err;
+
+        cpc_node = of_find_compatible_node(of_root, NULL, "mti,mips-cpc");
+        if (cpc_node) {
+                err = of_address_to_resource(cpc_node, 0, &res);
+                if (!err)
+                        return res.start;
+        }
+
         return 0;
 }
 
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 85bc601e9a0d..5f8b0a9e30b3 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -375,6 +375,7 @@ static void __init bootmem_init(void)
         unsigned long reserved_end;
         unsigned long mapstart = ~0UL;
         unsigned long bootmap_size;
+        phys_addr_t ramstart = (phys_addr_t)ULLONG_MAX;
         bool bootmap_valid = false;
         int i;
 
@@ -395,7 +396,8 @@ static void __init bootmem_init(void)
         max_low_pfn = 0;
 
         /*
-         * Find the highest page frame number we have available.
+         * Find the highest page frame number we have available
+         * and the lowest used RAM address
          */
         for (i = 0; i < boot_mem_map.nr_map; i++) {
                 unsigned long start, end;
@@ -407,6 +409,8 @@ static void __init bootmem_init(void)
                 end = PFN_DOWN(boot_mem_map.map[i].addr
                                 + boot_mem_map.map[i].size);
 
+                ramstart = min(ramstart, boot_mem_map.map[i].addr);
+
 #ifndef CONFIG_HIGHMEM
                 /*
                  * Skip highmem here so we get an accurate max_low_pfn if low
@@ -436,6 +440,13 @@ static void __init bootmem_init(void)
                 mapstart = max(reserved_end, start);
         }
 
+        /*
+         * Reserve any memory between the start of RAM and PHYS_OFFSET
+         */
+        if (ramstart > PHYS_OFFSET)
+                add_memory_region(PHYS_OFFSET, ramstart - PHYS_OFFSET,
+                                  BOOT_MEM_RESERVED);
+
         if (min_low_pfn >= max_low_pfn)
                 panic("Incorrect memory mapping !!!");
         if (min_low_pfn > ARCH_PFN_OFFSET) {
@@ -664,9 +675,6 @@ static int __init early_parse_mem(char *p)
 
         add_memory_region(start, size, BOOT_MEM_RAM);
 
-        if (start && start > PHYS_OFFSET)
-                add_memory_region(PHYS_OFFSET, start - PHYS_OFFSET,
-                                BOOT_MEM_RESERVED);
         return 0;
 }
 early_param("mem", early_parse_mem);
diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c
index 87dcac2447c8..9d41732a9146 100644
--- a/arch/mips/kernel/smp-bmips.c
+++ b/arch/mips/kernel/smp-bmips.c
@@ -572,7 +572,7 @@ asmlinkage void __weak plat_wired_tlb_setup(void)
          */
 }
 
-void __init bmips_cpu_setup(void)
+void bmips_cpu_setup(void)
 {
         void __iomem __maybe_unused *cbr = BMIPS_GET_CBR();
         u32 __maybe_unused cfg;
diff --git a/arch/parisc/include/asm/cacheflush.h b/arch/parisc/include/asm/cacheflush.h
index 3742508cc534..bd5ce31936f5 100644
--- a/arch/parisc/include/asm/cacheflush.h
+++ b/arch/parisc/include/asm/cacheflush.h
@@ -26,6 +26,7 @@ void flush_user_icache_range_asm(unsigned long, unsigned long);
 void flush_kernel_icache_range_asm(unsigned long, unsigned long);
 void flush_user_dcache_range_asm(unsigned long, unsigned long);
 void flush_kernel_dcache_range_asm(unsigned long, unsigned long);
+void purge_kernel_dcache_range_asm(unsigned long, unsigned long);
 void flush_kernel_dcache_page_asm(void *);
 void flush_kernel_icache_page(void *);
 
diff --git a/arch/parisc/include/asm/processor.h b/arch/parisc/include/asm/processor.h
index 0e6ab6e4a4e9..2dbe5580a1a4 100644
--- a/arch/parisc/include/asm/processor.h
+++ b/arch/parisc/include/asm/processor.h
@@ -316,6 +316,8 @@ extern int _parisc_requires_coherency;
 #define parisc_requires_coherency()     (0)
 #endif
 
+extern int running_on_qemu;
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* __ASM_PARISC_PROCESSOR_H */
diff --git a/arch/parisc/kernel/cache.c b/arch/parisc/kernel/cache.c
index 19c0c141bc3f..79089778725b 100644
--- a/arch/parisc/kernel/cache.c
+++ b/arch/parisc/kernel/cache.c
@@ -465,10 +465,10 @@ EXPORT_SYMBOL(copy_user_page);
 int __flush_tlb_range(unsigned long sid, unsigned long start,
                       unsigned long end)
 {
-        unsigned long flags, size;
+        unsigned long flags;
 
-        size = (end - start);
-        if (size >= parisc_tlb_flush_threshold) {
+        if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
+            end - start >= parisc_tlb_flush_threshold) {
                 flush_tlb_all();
                 return 1;
         }
@@ -539,13 +539,11 @@ void flush_cache_mm(struct mm_struct *mm)
         struct vm_area_struct *vma;
         pgd_t *pgd;
 
-        /* Flush the TLB to avoid speculation if coherency is required. */
-        if (parisc_requires_coherency())
-                flush_tlb_all();
-
         /* Flushing the whole cache on each cpu takes forever on
            rp3440, etc.  So, avoid it if the mm isn't too big.  */
-        if (mm_total_size(mm) >= parisc_cache_flush_threshold) {
+        if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
+            mm_total_size(mm) >= parisc_cache_flush_threshold) {
+                flush_tlb_all();
                 flush_cache_all();
                 return;
         }
@@ -553,9 +551,9 @@ void flush_cache_mm(struct mm_struct *mm)
         if (mm->context == mfsp(3)) {
                 for (vma = mm->mmap; vma; vma = vma->vm_next) {
                         flush_user_dcache_range_asm(vma->vm_start, vma->vm_end);
-                        if ((vma->vm_flags & VM_EXEC) == 0)
-                                continue;
-                        flush_user_icache_range_asm(vma->vm_start, vma->vm_end);
+                        if (vma->vm_flags & VM_EXEC)
+                                flush_user_icache_range_asm(vma->vm_start, vma->vm_end);
+                        flush_tlb_range(vma, vma->vm_start, vma->vm_end);
                 }
                 return;
         }
@@ -581,14 +579,9 @@ void flush_cache_mm(struct mm_struct *mm)
 void flush_cache_range(struct vm_area_struct *vma,
                 unsigned long start, unsigned long end)
 {
-        BUG_ON(!vma->vm_mm->context);
-
-        /* Flush the TLB to avoid speculation if coherency is required. */
-        if (parisc_requires_coherency())
+        if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
+            end - start >= parisc_cache_flush_threshold) {
                 flush_tlb_range(vma, start, end);
-
-        if ((end - start) >= parisc_cache_flush_threshold
-            || vma->vm_mm->context != mfsp(3)) {
                 flush_cache_all();
                 return;
         }
@@ -596,6 +589,7 @@ void flush_cache_range(struct vm_area_struct *vma,
         flush_user_dcache_range_asm(start, end);
         if (vma->vm_flags & VM_EXEC)
                 flush_user_icache_range_asm(start, end);
+        flush_tlb_range(vma, start, end);
 }
 
 void
@@ -604,8 +598,7 @@ flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long
         BUG_ON(!vma->vm_mm->context);
 
         if (pfn_valid(pfn)) {
-                if (parisc_requires_coherency())
-                        flush_tlb_page(vma, vmaddr);
+                flush_tlb_page(vma, vmaddr);
                 __flush_cache_page(vma, vmaddr, PFN_PHYS(pfn));
         }
 }
@@ -613,21 +606,33 @@ flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long
 void flush_kernel_vmap_range(void *vaddr, int size)
 {
         unsigned long start = (unsigned long)vaddr;
+        unsigned long end = start + size;
 
-        if ((unsigned long)size > parisc_cache_flush_threshold)
+        if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
+            (unsigned long)size >= parisc_cache_flush_threshold) {
+                flush_tlb_kernel_range(start, end);
                 flush_data_cache();
-        else
-                flush_kernel_dcache_range_asm(start, start + size);
+                return;
+        }
+
+        flush_kernel_dcache_range_asm(start, end);
+        flush_tlb_kernel_range(start, end);
 }
 EXPORT_SYMBOL(flush_kernel_vmap_range);
 
 void invalidate_kernel_vmap_range(void *vaddr, int size)
 {
         unsigned long start = (unsigned long)vaddr;
+        unsigned long end = start + size;
 
-        if ((unsigned long)size > parisc_cache_flush_threshold)
+        if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&
+            (unsigned long)size >= parisc_cache_flush_threshold) {
+                flush_tlb_kernel_range(start, end);
                 flush_data_cache();
-        else
-                flush_kernel_dcache_range_asm(start, start + size);
+                return;
+        }
+
+        purge_kernel_dcache_range_asm(start, end);
+        flush_tlb_kernel_range(start, end);
 }
 EXPORT_SYMBOL(invalidate_kernel_vmap_range);
diff --git a/arch/parisc/kernel/head.S b/arch/parisc/kernel/head.S
index bbbe360b458f..fbb4e43fda05 100644
--- a/arch/parisc/kernel/head.S
+++ b/arch/parisc/kernel/head.S
@@ -138,6 +138,16 @@ $pgt_fill_loop:
         std             %dp,0x18(%r10)
 #endif
 
+#ifdef CONFIG_64BIT
+        /* Get PDCE_PROC for monarch CPU. */
+#define MEM_PDC_LO 0x388
+#define MEM_PDC_HI 0x35C
+        ldw             MEM_PDC_LO(%r0),%r3
+        ldw             MEM_PDC_HI(%r0),%r10
+        depd            %r10, 31, 32, %r3        /* move to upper word */
+#endif
+
+
 #ifdef CONFIG_SMP
         /* Set the smp rendezvous address into page zero.
         ** It would be safer to do this in init_smp_config() but
@@ -196,12 +206,6 @@ common_stext:
         ** Someday, palo might not do this for the Monarch either.
         */
 2:
-#define MEM_PDC_LO 0x388
-#define MEM_PDC_HI 0x35C
-        ldw             MEM_PDC_LO(%r0),%r3
-        ldw             MEM_PDC_HI(%r0),%r6
-        depd            %r6, 31, 32, %r3        /* move to upper word */
-
         mfctl           %cr30,%r6               /* PCX-W2 firmware bug */
 
         ldo             PDC_PSW(%r0),%arg0              /* 21 */
@@ -268,6 +272,8 @@ $install_iva:
 aligned_rfi:
         pcxt_ssm_bug
 
+        copy            %r3, %arg0      /* PDCE_PROC for smp_callin() */
+
         rsm             PSW_SM_QUIET,%r0        /* off troublesome PSW bits */
         /* Don't need NOPs, have 8 compliant insn before rfi */
 
diff --git a/arch/parisc/kernel/pacache.S b/arch/parisc/kernel/pacache.S
index 2d40c4ff3f69..67b0f7532e83 100644
--- a/arch/parisc/kernel/pacache.S
+++ b/arch/parisc/kernel/pacache.S
@@ -1110,6 +1110,28 @@ ENTRY_CFI(flush_kernel_dcache_range_asm)
         .procend
 ENDPROC_CFI(flush_kernel_dcache_range_asm)
 
+ENTRY_CFI(purge_kernel_dcache_range_asm)
+        .proc
+        .callinfo NO_CALLS
+        .entry
+
+        ldil            L%dcache_stride, %r1
+        ldw             R%dcache_stride(%r1), %r23
+        ldo             -1(%r23), %r21
+        ANDCM           %r26, %r21, %r26
+
+1:      cmpb,COND(<<),n %r26, %r25,1b
+        pdc,m           %r23(%r26)
+
+        sync
+        syncdma
+        bv              %r0(%r2)
+        nop
+        .exit
+
+        .procend
+ENDPROC_CFI(purge_kernel_dcache_range_asm)
+
 ENTRY_CFI(flush_user_icache_range_asm)
         .proc
         .callinfo NO_CALLS
diff --git a/arch/parisc/kernel/smp.c b/arch/parisc/kernel/smp.c
index 30c28ab14540..4065b5e48c9d 100644
--- a/arch/parisc/kernel/smp.c
+++ b/arch/parisc/kernel/smp.c
@@ -292,10 +292,15 @@ smp_cpu_init(int cpunum)
  * Slaves start using C here. Indirectly called from smp_slave_stext.
  * Do what start_kernel() and main() do for boot strap processor (aka monarch)
  */
-void __init smp_callin(void)
+void __init smp_callin(unsigned long pdce_proc)
 {
         int slave_id = cpu_now_booting;
 
+#ifdef CONFIG_64BIT
+        WARN_ON(((unsigned long)(PAGE0->mem_pdc_hi) << 32
+                        | PAGE0->mem_pdc) != pdce_proc);
+#endif
+
         smp_cpu_init(slave_id);
         preempt_disable();
 
diff --git a/arch/parisc/kernel/time.c b/arch/parisc/kernel/time.c
index 4b8fd6dc22da..f7e684560186 100644
--- a/arch/parisc/kernel/time.c
+++ b/arch/parisc/kernel/time.c
@@ -76,10 +76,10 @@ irqreturn_t __irq_entry timer_interrupt(int irq, void *dev_id)
         next_tick = cpuinfo->it_value;
 
         /* Calculate how many ticks have elapsed. */
+        now = mfctl(16);
         do {
                 ++ticks_elapsed;
                 next_tick += cpt;
-                now = mfctl(16);
         } while (next_tick - now > cpt);
 
         /* Store (in CR16 cycles) up to when we are accounting right now. */
@@ -103,16 +103,17 @@ irqreturn_t __irq_entry timer_interrupt(int irq, void *dev_id)
          * if one or the other wrapped. If "now" is "bigger" we'll end up
          * with a very large unsigned number.
          */
-        while (next_tick - mfctl(16) > cpt)
+        now = mfctl(16);
+        while (next_tick - now > cpt)
                 next_tick += cpt;
 
         /* Program the IT when to deliver the next interrupt.
          * Only bottom 32-bits of next_tick are writable in CR16!
          * Timer interrupt will be delivered at least a few hundred cycles
-         * after the IT fires, so if we are too close (<= 500 cycles) to the
+         * after the IT fires, so if we are too close (<= 8000 cycles) to the
          * next cycle, simply skip it.
          */
-        if (next_tick - mfctl(16) <= 500)
+        if (next_tick - now <= 8000)
                 next_tick += cpt;
         mtctl(next_tick, 16);
 
@@ -248,7 +249,7 @@ static int __init init_cr16_clocksource(void)
          * different sockets, so mark them unstable and lower rating on
          * multi-socket SMP systems.
          */
-        if (num_online_cpus() > 1) {
+        if (num_online_cpus() > 1 && !running_on_qemu) {
                 int cpu;
                 unsigned long cpu0_loc;
                 cpu0_loc = per_cpu(cpu_data, 0).cpu_loc;
diff --git a/arch/parisc/mm/init.c b/arch/parisc/mm/init.c
index 48f41399fc0b..cab32ee824d2 100644
--- a/arch/parisc/mm/init.c
+++ b/arch/parisc/mm/init.c
@@ -629,7 +629,12 @@ void __init mem_init(void)
 #endif
 
         mem_init_print_info(NULL);
-#ifdef CONFIG_DEBUG_KERNEL /* double-sanity-check paranoia */
+
+#if 0
+        /*
+         * Do not expose the virtual kernel memory layout to userspace.
+         * But keep code for debugging purposes.
+         */
         printk("virtual kernel memory layout:\n"
                "    vmalloc : 0x%px - 0x%px   (%4ld MB)\n"
                "    memory  : 0x%px - 0x%px   (%4ld MB)\n"
diff --git a/arch/powerpc/include/asm/book3s/32/pgtable.h b/arch/powerpc/include/asm/book3s/32/pgtable.h
index 30a155c0a6b0..c615abdce119 100644
--- a/arch/powerpc/include/asm/book3s/32/pgtable.h
+++ b/arch/powerpc/include/asm/book3s/32/pgtable.h
@@ -16,6 +16,7 @@
 #define PGD_INDEX_SIZE  (32 - PGDIR_SHIFT)
 
 #define PMD_CACHE_INDEX PMD_INDEX_SIZE
+#define PUD_CACHE_INDEX PUD_INDEX_SIZE
 
 #ifndef __ASSEMBLY__
 #define PTE_TABLE_SIZE  (sizeof(pte_t) << PTE_INDEX_SIZE)
diff --git a/arch/powerpc/include/asm/book3s/64/hash-4k.h b/arch/powerpc/include/asm/book3s/64/hash-4k.h
index 949d691094a4..67c5475311ee 100644
--- a/arch/powerpc/include/asm/book3s/64/hash-4k.h
+++ b/arch/powerpc/include/asm/book3s/64/hash-4k.h
@@ -63,7 +63,8 @@ static inline int hash__hugepd_ok(hugepd_t hpd)
  * keeping the prototype consistent across the two formats.
  */
 static inline unsigned long pte_set_hidx(pte_t *ptep, real_pte_t rpte,
-                        unsigned int subpg_index, unsigned long hidx)
+                                         unsigned int subpg_index, unsigned long hidx,
+                                         int offset)
 {
         return (hidx << H_PAGE_F_GIX_SHIFT) &
                 (H_PAGE_F_SECOND | H_PAGE_F_GIX);
diff --git a/arch/powerpc/include/asm/book3s/64/hash-64k.h b/arch/powerpc/include/asm/book3s/64/hash-64k.h
index 338b7da468ce..3bcf269f8f55 100644
--- a/arch/powerpc/include/asm/book3s/64/hash-64k.h
+++ b/arch/powerpc/include/asm/book3s/64/hash-64k.h
@@ -45,7 +45,7 @@
  * generic accessors and iterators here
  */
 #define __real_pte __real_pte
-static inline real_pte_t __real_pte(pte_t pte, pte_t *ptep)
+static inline real_pte_t __real_pte(pte_t pte, pte_t *ptep, int offset)
 {
         real_pte_t rpte;
         unsigned long *hidxp;
@@ -59,7 +59,7 @@ static inline real_pte_t __real_pte(pte_t pte, pte_t *ptep)
          */
         smp_rmb();
 
-        hidxp = (unsigned long *)(ptep + PTRS_PER_PTE);
+        hidxp = (unsigned long *)(ptep + offset);
         rpte.hidx = *hidxp;
         return rpte;
 }
@@ -86,9 +86,10 @@ static inline unsigned long __rpte_to_hidx(real_pte_t rpte, unsigned long index)
  * expected to modify the PTE bits accordingly and commit the PTE to memory.
  */
 static inline unsigned long pte_set_hidx(pte_t *ptep, real_pte_t rpte,
-                unsigned int subpg_index, unsigned long hidx)
+                                         unsigned int subpg_index,
+                                         unsigned long hidx, int offset)
 {
-        unsigned long *hidxp = (unsigned long *)(ptep + PTRS_PER_PTE);
+        unsigned long *hidxp = (unsigned long *)(ptep + offset);
 
         rpte.hidx &= ~HIDX_BITS(0xfUL, subpg_index);
         *hidxp = rpte.hidx  | HIDX_BITS(HIDX_SHIFT_BY_ONE(hidx), subpg_index);
@@ -140,13 +141,18 @@ static inline int hash__remap_4k_pfn(struct vm_area_struct *vma, unsigned long a
 }
 
 #define H_PTE_TABLE_SIZE        PTE_FRAG_SIZE
-#ifdef CONFIG_TRANSPARENT_HUGEPAGE
+#if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined (CONFIG_HUGETLB_PAGE)
 #define H_PMD_TABLE_SIZE        ((sizeof(pmd_t) << PMD_INDEX_SIZE) + \
                                  (sizeof(unsigned long) << PMD_INDEX_SIZE))
 #else
 #define H_PMD_TABLE_SIZE        (sizeof(pmd_t) << PMD_INDEX_SIZE)
 #endif
+#ifdef CONFIG_HUGETLB_PAGE
+#define H_PUD_TABLE_SIZE        ((sizeof(pud_t) << PUD_INDEX_SIZE) +    \
+                                 (sizeof(unsigned long) << PUD_INDEX_SIZE))
+#else
 #define H_PUD_TABLE_SIZE        (sizeof(pud_t) << PUD_INDEX_SIZE)
+#endif
 #define H_PGD_TABLE_SIZE        (sizeof(pgd_t) << PGD_INDEX_SIZE)
 
 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
diff --git a/arch/powerpc/include/asm/book3s/64/hash.h b/arch/powerpc/include/asm/book3s/64/hash.h
index 0920eff731b3..935adcd92a81 100644
--- a/arch/powerpc/include/asm/book3s/64/hash.h
+++ b/arch/powerpc/include/asm/book3s/64/hash.h
@@ -23,7 +23,8 @@
                                  H_PUD_INDEX_SIZE + H_PGD_INDEX_SIZE + PAGE_SHIFT)
 #define H_PGTABLE_RANGE         (ASM_CONST(1) << H_PGTABLE_EADDR_SIZE)
 
-#if defined(CONFIG_TRANSPARENT_HUGEPAGE) &&  defined(CONFIG_PPC_64K_PAGES)
+#if (defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE)) && \
+        defined(CONFIG_PPC_64K_PAGES)
 /*
  * only with hash 64k we need to use the second half of pmd page table
  * to store pointer to deposited pgtable_t
@@ -33,6 +34,16 @@
 #define H_PMD_CACHE_INDEX       H_PMD_INDEX_SIZE
 #endif
 /*
+ * We store the slot details in the second half of page table.
+ * Increase the pud level table so that hugetlb ptes can be stored
+ * at pud level.
+ */
+#if defined(CONFIG_HUGETLB_PAGE) &&  defined(CONFIG_PPC_64K_PAGES)
+#define H_PUD_CACHE_INDEX       (H_PUD_INDEX_SIZE + 1)
+#else
+#define H_PUD_CACHE_INDEX       (H_PUD_INDEX_SIZE)
+#endif
+/*
  * Define the address range of the kernel non-linear virtual area
  */
 #define H_KERN_VIRT_START ASM_CONST(0xD000000000000000)
diff --git a/arch/powerpc/include/asm/book3s/64/pgalloc.h b/arch/powerpc/include/asm/book3s/64/pgalloc.h
index 1fcfa425cefa..4746bc68d446 100644
--- a/arch/powerpc/include/asm/book3s/64/pgalloc.h
+++ b/arch/powerpc/include/asm/book3s/64/pgalloc.h
@@ -73,10 +73,16 @@ static inline void radix__pgd_free(struct mm_struct *mm, pgd_t *pgd)
 
 static inline pgd_t *pgd_alloc(struct mm_struct *mm)
 {
+        pgd_t *pgd;
+
         if (radix_enabled())
                 return radix__pgd_alloc(mm);
-        return kmem_cache_alloc(PGT_CACHE(PGD_INDEX_SIZE),
-                pgtable_gfp_flags(mm, GFP_KERNEL));
+
+        pgd = kmem_cache_alloc(PGT_CACHE(PGD_INDEX_SIZE),
+                               pgtable_gfp_flags(mm, GFP_KERNEL));
+        memset(pgd, 0, PGD_TABLE_SIZE);
+
+        return pgd;
 }
 
 static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
@@ -93,13 +99,13 @@ static inline void pgd_populate(struct mm_struct *mm, pgd_t *pgd, pud_t *pud)
 
 static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long addr)
 {
-        return kmem_cache_alloc(PGT_CACHE(PUD_INDEX_SIZE),
+        return kmem_cache_alloc(PGT_CACHE(PUD_CACHE_INDEX),
                 pgtable_gfp_flags(mm, GFP_KERNEL));
 }
 
 static inline void pud_free(struct mm_struct *mm, pud_t *pud)
 {
-        kmem_cache_free(PGT_CACHE(PUD_INDEX_SIZE), pud);
+        kmem_cache_free(PGT_CACHE(PUD_CACHE_INDEX), pud);
 }
 
 static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
@@ -115,7 +121,7 @@ static inline void __pud_free_tlb(struct mmu_gather *tlb, pud_t *pud,
          * ahead and flush the page walk cache
          */
         flush_tlb_pgtable(tlb, address);
-        pgtable_free_tlb(tlb, pud, PUD_INDEX_SIZE);
+        pgtable_free_tlb(tlb, pud, PUD_CACHE_INDEX);
 }
 
 static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
diff --git a/arch/powerpc/include/asm/book3s/64/pgtable.h b/arch/powerpc/include/asm/book3s/64/pgtable.h
index 51017726d495..a6b9f1d74600 100644
--- a/arch/powerpc/include/asm/book3s/64/pgtable.h
+++ b/arch/powerpc/include/asm/book3s/64/pgtable.h
@@ -232,11 +232,13 @@ extern unsigned long __pmd_index_size;
 extern unsigned long __pud_index_size;
 extern unsigned long __pgd_index_size;
 extern unsigned long __pmd_cache_index;
+extern unsigned long __pud_cache_index;
 #define PTE_INDEX_SIZE  __pte_index_size
 #define PMD_INDEX_SIZE  __pmd_index_size
 #define PUD_INDEX_SIZE  __pud_index_size
 #define PGD_INDEX_SIZE  __pgd_index_size
 #define PMD_CACHE_INDEX __pmd_cache_index
+#define PUD_CACHE_INDEX __pud_cache_index
 /*
  * Because of use of pte fragments and THP, size of page table
  * are not always derived out of index size above.
@@ -348,7 +350,7 @@ extern unsigned long pci_io_base;
  */
 #ifndef __real_pte
 
-#define __real_pte(e,p)         ((real_pte_t){(e)})
+#define __real_pte(e, p, o)             ((real_pte_t){(e)})
 #define __rpte_to_pte(r)        ((r).pte)
 #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT)
 
diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h
index 176dfb73d42c..471b2274fbeb 100644
--- a/arch/powerpc/include/asm/exception-64s.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -645,7 +645,7 @@ END_FTR_SECTION_NESTED(ftr,ftr,943)
                                           EXC_HV, SOFTEN_TEST_HV, bitmask)
 
 #define MASKABLE_RELON_EXCEPTION_HV_OOL(vec, label, bitmask)            \
-        MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_NOTEST_HV, vec, bitmask);\
+        MASKABLE_EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_HV, vec, bitmask);\
         EXCEPTION_RELON_PROLOG_PSERIES_1(label, EXC_HV)
 
 /*
diff --git a/arch/powerpc/include/asm/firmware.h b/arch/powerpc/include/asm/firmware.h
index 511acfd7ab0d..535add3f7791 100644
--- a/arch/powerpc/include/asm/firmware.h
+++ b/arch/powerpc/include/asm/firmware.h
@@ -52,7 +52,7 @@
 #define FW_FEATURE_TYPE1_AFFINITY ASM_CONST(0x0000000100000000)
 #define FW_FEATURE_PRRN         ASM_CONST(0x0000000200000000)
 #define FW_FEATURE_DRMEM_V2     ASM_CONST(0x0000000400000000)
-#define FW_FEATURE_DRC_INFO     ASM_CONST(0x0000000400000000)
+#define FW_FEATURE_DRC_INFO     ASM_CONST(0x0000000800000000)
 
 #ifndef __ASSEMBLY__
 
diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h
index 88e5e8f17e98..855e17d158b1 100644
--- a/arch/powerpc/include/asm/hw_irq.h
+++ b/arch/powerpc/include/asm/hw_irq.h
@@ -30,6 +30,16 @@
 #define PACA_IRQ_PMI            0x40
 
 /*
+ * Some soft-masked interrupts must be hard masked until they are replayed
+ * (e.g., because the soft-masked handler does not clear the exception).
+ */
+#ifdef CONFIG_PPC_BOOK3S
+#define PACA_IRQ_MUST_HARD_MASK (PACA_IRQ_EE|PACA_IRQ_PMI)
+#else
+#define PACA_IRQ_MUST_HARD_MASK (PACA_IRQ_EE)
+#endif
+
+/*
  * flags for paca->irq_soft_mask
  */
 #define IRQS_ENABLED            0
@@ -244,7 +254,7 @@ static inline bool lazy_irq_pending(void)
 static inline void may_hard_irq_enable(void)
 {
         get_paca()->irq_happened &= ~PACA_IRQ_HARD_DIS;
-        if (!(get_paca()->irq_happened & PACA_IRQ_EE))
+        if (!(get_paca()->irq_happened & PACA_IRQ_MUST_HARD_MASK))
                 __hard_irq_enable();
 }
 
diff --git a/arch/powerpc/include/asm/kexec.h b/arch/powerpc/include/asm/kexec.h
index 9dcbfa6bbb91..d8b1e8e7e035 100644
--- a/arch/powerpc/include/asm/kexec.h
+++ b/arch/powerpc/include/asm/kexec.h
@@ -140,6 +140,12 @@ static inline bool kdump_in_progress(void)
         return false;
 }
 
+static inline void crash_ipi_callback(struct pt_regs *regs) { }
+
+static inline void crash_send_ipi(void (*crash_ipi_callback)(struct pt_regs *))
+{
+}
+
 #endif /* CONFIG_KEXEC_CORE */
 #endif /* ! __ASSEMBLY__ */
 #endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/nohash/32/pgtable.h b/arch/powerpc/include/asm/nohash/32/pgtable.h
index 504a3c36ce5c..03bbd1149530 100644
--- a/arch/powerpc/include/asm/nohash/32/pgtable.h
+++ b/arch/powerpc/include/asm/nohash/32/pgtable.h
@@ -24,6 +24,7 @@ extern int icache_44x_need_flush;
 #define PGD_INDEX_SIZE  (32 - PGDIR_SHIFT)
 
 #define PMD_CACHE_INDEX PMD_INDEX_SIZE
+#define PUD_CACHE_INDEX PUD_INDEX_SIZE
 
 #ifndef __ASSEMBLY__
 #define PTE_TABLE_SIZE  (sizeof(pte_t) << PTE_INDEX_SIZE)
diff --git a/arch/powerpc/include/asm/nohash/64/pgtable.h b/arch/powerpc/include/asm/nohash/64/pgtable.h
index abddf5830ad5..5c5f75d005ad 100644
--- a/arch/powerpc/include/asm/nohash/64/pgtable.h
+++ b/arch/powerpc/include/asm/nohash/64/pgtable.h
@@ -27,6 +27,7 @@
 #else
 #define PMD_CACHE_INDEX PMD_INDEX_SIZE
 #endif
+#define PUD_CACHE_INDEX PUD_INDEX_SIZE
 
 /*
  * Define the address range of the kernel non-linear virtual area
diff --git a/arch/powerpc/include/asm/topology.h b/arch/powerpc/include/asm/topology.h
index 88187c285c70..9f421641a35c 100644
--- a/arch/powerpc/include/asm/topology.h
+++ b/arch/powerpc/include/asm/topology.h
@@ -44,6 +44,11 @@ extern int sysfs_add_device_to_node(struct device *dev, int nid);
 extern void sysfs_remove_device_from_node(struct device *dev, int nid);
 extern int numa_update_cpu_topology(bool cpus_locked);
 
+static inline void update_numa_cpu_lookup_table(unsigned int cpu, int node)
+{
+        numa_cpu_lookup_table[cpu] = node;
+}
+
 static inline int early_cpu_to_node(int cpu)
 {
         int nid;
@@ -76,12 +81,16 @@ static inline int numa_update_cpu_topology(bool cpus_locked)
 {
         return 0;
 }
+
+static inline void update_numa_cpu_lookup_table(unsigned int cpu, int node) {}
+
 #endif /* CONFIG_NUMA */
 
 #if defined(CONFIG_NUMA) && defined(CONFIG_PPC_SPLPAR)
 extern int start_topology_update(void);
 extern int stop_topology_update(void);
 extern int prrn_is_enabled(void);
+extern int find_and_online_cpu_nid(int cpu);
 #else
 static inline int start_topology_update(void)
 {
@@ -95,6 +104,10 @@ static inline int prrn_is_enabled(void)
 {
         return 0;
 }
+static inline int find_and_online_cpu_nid(int cpu)
+{
+        return 0;
+}
 #endif /* CONFIG_NUMA && CONFIG_PPC_SPLPAR */
 
 #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_NEED_MULTIPLE_NODES)
diff --git a/arch/powerpc/kernel/eeh_driver.c b/arch/powerpc/kernel/eeh_driver.c
index beea2182d754..0c0b66fc5bfb 100644
--- a/arch/powerpc/kernel/eeh_driver.c
+++ b/arch/powerpc/kernel/eeh_driver.c
@@ -384,7 +384,8 @@ static void *eeh_report_resume(void *data, void *userdata)
         eeh_pcid_put(dev);
         pci_uevent_ers(dev, PCI_ERS_RESULT_RECOVERED);
 #ifdef CONFIG_PCI_IOV
-        eeh_ops->notify_resume(eeh_dev_to_pdn(edev));
+        if (eeh_ops->notify_resume && eeh_dev_to_pdn(edev))
+                eeh_ops->notify_resume(eeh_dev_to_pdn(edev));
 #endif
         return NULL;
 }
diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S
index ee832d344a5a..9b6e653e501a 100644
--- a/arch/powerpc/kernel/exceptions-64e.S
+++ b/arch/powerpc/kernel/exceptions-64e.S
@@ -943,6 +943,8 @@ kernel_dbg_exc:
 /*
  * An interrupt came in while soft-disabled; We mark paca->irq_happened
  * accordingly and if the interrupt is level sensitive, we hard disable
+ * hard disable (full_mask) corresponds to PACA_IRQ_MUST_HARD_MASK, so
+ * keep these in synch.
  */
 
 .macro masked_interrupt_book3e paca_irq full_mask
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 243d072a225a..3ac87e53b3da 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -1426,7 +1426,7 @@ EXC_COMMON_BEGIN(soft_nmi_common)
  *   triggered and won't automatically refire.
  * - If it was a HMI we return immediately since we handled it in realmode
  *   and it won't refire.
- * - else we hard disable and return.
+ * - Else it is one of PACA_IRQ_MUST_HARD_MASK, so hard disable and return.
  * This is called with r10 containing the value to OR to the paca field.
  */
 #define MASKED_INTERRUPT(_H)                            \
@@ -1441,8 +1441,8 @@ masked_##_H##interrupt:					\
         ori     r10,r10,0xffff;                         \
         mtspr   SPRN_DEC,r10;                           \
         b       MASKED_DEC_HANDLER_LABEL;               \
-1:      andi.   r10,r10,(PACA_IRQ_DBELL|PACA_IRQ_HMI);  \
-        bne     2f;                                     \
+1:      andi.   r10,r10,PACA_IRQ_MUST_HARD_MASK;        \
+        beq     2f;                                     \
         mfspr   r10,SPRN_##_H##SRR1;                    \
         xori    r10,r10,MSR_EE; /* clear MSR_EE */      \
         mtspr   SPRN_##_H##SRR1,r10;                    \
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index adf044daafd7..d22c41c26bb3 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -874,7 +874,7 @@ struct ibm_arch_vec __cacheline_aligned ibm_architecture_vec = {
                 .mmu = 0,
                 .hash_ext = 0,
                 .radix_ext = 0,
-                .byte22 = OV5_FEAT(OV5_DRC_INFO),
+                .byte22 = 0,
         },
 
         /* option vector 6: IBM PAPR hints */
diff --git a/arch/powerpc/kernel/sysfs.c b/arch/powerpc/kernel/sysfs.c
index 5a8bfee6e187..04d0bbd7a1dd 100644
--- a/arch/powerpc/kernel/sysfs.c
+++ b/arch/powerpc/kernel/sysfs.c
@@ -788,7 +788,8 @@ static int register_cpu_online(unsigned int cpu)
         if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
                 device_create_file(s, &dev_attr_pir);
 
-        if (cpu_has_feature(CPU_FTR_ARCH_206))
+        if (cpu_has_feature(CPU_FTR_ARCH_206) &&
+                !firmware_has_feature(FW_FEATURE_LPAR))
                 device_create_file(s, &dev_attr_tscr);
 #endif /* CONFIG_PPC64 */
 
@@ -873,7 +874,8 @@ static int unregister_cpu_online(unsigned int cpu)
         if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
                 device_remove_file(s, &dev_attr_pir);
 
-        if (cpu_has_feature(CPU_FTR_ARCH_206))
+        if (cpu_has_feature(CPU_FTR_ARCH_206) &&
+                !firmware_has_feature(FW_FEATURE_LPAR))
                 device_remove_file(s, &dev_attr_tscr);
 #endif /* CONFIG_PPC64 */
 
diff --git a/arch/powerpc/kvm/book3s_xive.c b/arch/powerpc/kvm/book3s_xive.c
index f0f5cd4d2fe7..f9818d7d3381 100644
--- a/arch/powerpc/kvm/book3s_xive.c
+++ b/arch/powerpc/kvm/book3s_xive.c
@@ -188,7 +188,7 @@ static int xive_provision_queue(struct kvm_vcpu *vcpu, u8 prio)
         if (!qpage) {
                 pr_err("Failed to allocate queue %d for VCPU %d\n",
                        prio, xc->server_num);
-                return -ENOMEM;;
+                return -ENOMEM;
         }
         memset(qpage, 0, 1 << xive->q_order);
 
diff --git a/arch/powerpc/mm/drmem.c b/arch/powerpc/mm/drmem.c
index 1604110c4238..3f1803672c9b 100644
--- a/arch/powerpc/mm/drmem.c
+++ b/arch/powerpc/mm/drmem.c
@@ -98,7 +98,7 @@ static void init_drconf_v2_cell(struct of_drconf_cell_v2 *dr_cell,
         dr_cell->base_addr = cpu_to_be64(lmb->base_addr);
         dr_cell->drc_index = cpu_to_be32(lmb->drc_index);
         dr_cell->aa_index = cpu_to_be32(lmb->aa_index);
-        dr_cell->flags = cpu_to_be32(lmb->flags);
+        dr_cell->flags = cpu_to_be32(drmem_lmb_flags(lmb));
 }
 
 static int drmem_update_dt_v2(struct device_node *memory,
@@ -121,7 +121,7 @@ static int drmem_update_dt_v2(struct device_node *memory,
                 }
 
                 if (prev_lmb->aa_index != lmb->aa_index ||
-                    prev_lmb->flags != lmb->flags)
+                    drmem_lmb_flags(prev_lmb) != drmem_lmb_flags(lmb))
                         lmb_sets++;
 
                 prev_lmb = lmb;
@@ -150,7 +150,7 @@ static int drmem_update_dt_v2(struct device_node *memory,
                 }
 
                 if (prev_lmb->aa_index != lmb->aa_index ||
-                    prev_lmb->flags != lmb->flags) {
+                    drmem_lmb_flags(prev_lmb) != drmem_lmb_flags(lmb)) {
                         /* end of one set, start of another */
                         dr_cell->seq_lmbs = cpu_to_be32(seq_lmbs);
                         dr_cell++;
@@ -216,6 +216,8 @@ static void __init __walk_drmem_v1_lmbs(const __be32 *prop, const __be32 *usm,
         u32 i, n_lmbs;
 
         n_lmbs = of_read_number(prop++, 1);
+        if (n_lmbs == 0)
+                return;
 
         for (i = 0; i < n_lmbs; i++) {
                 read_drconf_v1_cell(&lmb, &prop);
@@ -245,6 +247,8 @@ static void __init __walk_drmem_v2_lmbs(const __be32 *prop, const __be32 *usm,
         u32 i, j, lmb_sets;
 
         lmb_sets = of_read_number(prop++, 1);
+        if (lmb_sets == 0)
+                return;
 
         for (i = 0; i < lmb_sets; i++) {
                 read_drconf_v2_cell(&dr_cell, &prop);
@@ -354,6 +358,8 @@ static void __init init_drmem_v1_lmbs(const __be32 *prop)
         struct drmem_lmb *lmb;
 
         drmem_info->n_lmbs = of_read_number(prop++, 1);
+        if (drmem_info->n_lmbs == 0)
+                return;
 
         drmem_info->lmbs = kcalloc(drmem_info->n_lmbs, sizeof(*lmb),
                                    GFP_KERNEL);
@@ -373,6 +379,8 @@ static void __init init_drmem_v2_lmbs(const __be32 *prop)
         int lmb_index;
 
         lmb_sets = of_read_number(prop++, 1);
+        if (lmb_sets == 0)
+                return;
 
         /* first pass, calculate the number of LMBs */
         p = prop;
diff --git a/arch/powerpc/mm/hash64_4k.c b/arch/powerpc/mm/hash64_4k.c
index 5a69b51d08a3..d573d7d07f25 100644
--- a/arch/powerpc/mm/hash64_4k.c
+++ b/arch/powerpc/mm/hash64_4k.c
@@ -55,7 +55,7 @@ int __hash_page_4K(unsigned long ea, unsigned long access, unsigned long vsid,
          * need to add in 0x1 if it's a read-only user page
          */
         rflags = htab_convert_pte_flags(new_pte);
-        rpte = __real_pte(__pte(old_pte), ptep);
+        rpte = __real_pte(__pte(old_pte), ptep, PTRS_PER_PTE);
 
         if (cpu_has_feature(CPU_FTR_NOEXECUTE) &&
             !cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
@@ -117,7 +117,7 @@ repeat:
                         return -1;
                 }
                 new_pte = (new_pte & ~_PAGE_HPTEFLAGS) | H_PAGE_HASHPTE;
-                new_pte |= pte_set_hidx(ptep, rpte, 0, slot);
+                new_pte |= pte_set_hidx(ptep, rpte, 0, slot, PTRS_PER_PTE);
         }
         *ptep = __pte(new_pte & ~H_PAGE_BUSY);
         return 0;
diff --git a/arch/powerpc/mm/hash64_64k.c b/arch/powerpc/mm/hash64_64k.c
index 2253bbc6a599..e601d95c3b20 100644
--- a/arch/powerpc/mm/hash64_64k.c
+++ b/arch/powerpc/mm/hash64_64k.c
@@ -86,7 +86,7 @@ int __hash_page_4K(unsigned long ea, unsigned long access, unsigned long vsid,
 
         subpg_index = (ea & (PAGE_SIZE - 1)) >> shift;
         vpn  = hpt_vpn(ea, vsid, ssize);
-        rpte = __real_pte(__pte(old_pte), ptep);
+        rpte = __real_pte(__pte(old_pte), ptep, PTRS_PER_PTE);
         /*
          *None of the sub 4k page is hashed
          */
@@ -214,7 +214,7 @@ repeat:
                 return -1;
         }
 
-        new_pte |= pte_set_hidx(ptep, rpte, subpg_index, slot);
+        new_pte |= pte_set_hidx(ptep, rpte, subpg_index, slot, PTRS_PER_PTE);
         new_pte |= H_PAGE_HASHPTE;
 
         *ptep = __pte(new_pte & ~H_PAGE_BUSY);
@@ -262,7 +262,7 @@ int __hash_page_64K(unsigned long ea, unsigned long access,
         } while (!pte_xchg(ptep, __pte(old_pte), __pte(new_pte)));
 
         rflags = htab_convert_pte_flags(new_pte);
-        rpte = __real_pte(__pte(old_pte), ptep);
+        rpte = __real_pte(__pte(old_pte), ptep, PTRS_PER_PTE);
 
         if (cpu_has_feature(CPU_FTR_NOEXECUTE) &&
             !cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
@@ -327,7 +327,7 @@ repeat:
                 }
 
                 new_pte = (new_pte & ~_PAGE_HPTEFLAGS) | H_PAGE_HASHPTE;
-                new_pte |= pte_set_hidx(ptep, rpte, 0, slot);
+                new_pte |= pte_set_hidx(ptep, rpte, 0, slot, PTRS_PER_PTE);
         }
         *ptep = __pte(new_pte & ~H_PAGE_BUSY);
         return 0;
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index 7d07c7e17db6..cf290d415dcd 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -1008,6 +1008,7 @@ void __init hash__early_init_mmu(void)
         __pmd_index_size = H_PMD_INDEX_SIZE;
         __pud_index_size = H_PUD_INDEX_SIZE;
         __pgd_index_size = H_PGD_INDEX_SIZE;
+        __pud_cache_index = H_PUD_CACHE_INDEX;
         __pmd_cache_index = H_PMD_CACHE_INDEX;
         __pte_table_size = H_PTE_TABLE_SIZE;
         __pmd_table_size = H_PMD_TABLE_SIZE;
diff --git a/arch/powerpc/mm/hugetlbpage-hash64.c b/arch/powerpc/mm/hugetlbpage-hash64.c
index 12511f5a015f..b320f5097a06 100644
--- a/arch/powerpc/mm/hugetlbpage-hash64.c
+++ b/arch/powerpc/mm/hugetlbpage-hash64.c
@@ -27,7 +27,7 @@ int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
         unsigned long vpn;
         unsigned long old_pte, new_pte;
         unsigned long rflags, pa, sz;
-        long slot;
+        long slot, offset;
 
         BUG_ON(shift != mmu_psize_defs[mmu_psize].shift);
 
@@ -63,7 +63,11 @@ int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
         } while(!pte_xchg(ptep, __pte(old_pte), __pte(new_pte)));
 
         rflags = htab_convert_pte_flags(new_pte);
-        rpte = __real_pte(__pte(old_pte), ptep);
+        if (unlikely(mmu_psize == MMU_PAGE_16G))
+                offset = PTRS_PER_PUD;
+        else
+                offset = PTRS_PER_PMD;
+        rpte = __real_pte(__pte(old_pte), ptep, offset);
 
         sz = ((1UL) << shift);
         if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
@@ -104,7 +108,7 @@ int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
                         return -1;
                 }
 
-                new_pte |= pte_set_hidx(ptep, rpte, 0, slot);
+                new_pte |= pte_set_hidx(ptep, rpte, 0, slot, offset);
         }
 
         /*
diff --git a/arch/powerpc/mm/init-common.c b/arch/powerpc/mm/init-common.c
index eb8c6c8c4851..2b656e67f2ea 100644
--- a/arch/powerpc/mm/init-common.c
+++ b/arch/powerpc/mm/init-common.c
@@ -100,6 +100,6 @@ void pgtable_cache_init(void)
          * same size as either the pgd or pmd index except with THP enabled
          * on book3s 64
          */
-        if (PUD_INDEX_SIZE && !PGT_CACHE(PUD_INDEX_SIZE))
-                pgtable_cache_add(PUD_INDEX_SIZE, pud_ctor);
+        if (PUD_CACHE_INDEX && !PGT_CACHE(PUD_CACHE_INDEX))
+                pgtable_cache_add(PUD_CACHE_INDEX, pud_ctor);
 }
diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c
index 314d19ab9385..edd8d0bc9364 100644
--- a/arch/powerpc/mm/numa.c
+++ b/arch/powerpc/mm/numa.c
@@ -143,11 +143,6 @@ static void reset_numa_cpu_lookup_table(void)
                 numa_cpu_lookup_table[cpu] = -1;
 }
 
-static void update_numa_cpu_lookup_table(unsigned int cpu, int node)
-{
-        numa_cpu_lookup_table[cpu] = node;
-}
-
 static void map_cpu_to_node(int cpu, int node)
 {
         update_numa_cpu_lookup_table(cpu, node);
diff --git a/arch/powerpc/mm/pgtable-radix.c b/arch/powerpc/mm/pgtable-radix.c
index 573a9a2ee455..2e10a964e290 100644
--- a/arch/powerpc/mm/pgtable-radix.c
+++ b/arch/powerpc/mm/pgtable-radix.c
@@ -17,9 +17,11 @@
 #include <linux/of_fdt.h>
 #include <linux/mm.h>
 #include <linux/string_helpers.h>
+#include <linux/stop_machine.h>
 
 #include <asm/pgtable.h>
 #include <asm/pgalloc.h>
+#include <asm/mmu_context.h>
 #include <asm/dma.h>
 #include <asm/machdep.h>
 #include <asm/mmu.h>
@@ -333,6 +335,22 @@ static void __init radix_init_pgtable(void)
                      "r" (TLBIEL_INVAL_SET_LPID), "r" (0));
         asm volatile("eieio; tlbsync; ptesync" : : : "memory");
         trace_tlbie(0, 0, TLBIEL_INVAL_SET_LPID, 0, 2, 1, 1);
+
+        /*
+         * The init_mm context is given the first available (non-zero) PID,
+         * which is the "guard PID" and contains no page table. PIDR should
+         * never be set to zero because that duplicates the kernel address
+         * space at the 0x0... offset (quadrant 0)!
+         *
+         * An arbitrary PID that may later be allocated by the PID allocator
+         * for userspace processes must not be used either, because that
+         * would cause stale user mappings for that PID on CPUs outside of
+         * the TLB invalidation scheme (because it won't be in mm_cpumask).
+         *
+         * So permanently carve out one PID for the purpose of a guard PID.
+         */
+        init_mm.context.id = mmu_base_pid;
+        mmu_base_pid++;
 }
 
 static void __init radix_init_partition_table(void)
@@ -535,6 +553,7 @@ void __init radix__early_init_mmu(void)
         __pmd_index_size = RADIX_PMD_INDEX_SIZE;
         __pud_index_size = RADIX_PUD_INDEX_SIZE;
         __pgd_index_size = RADIX_PGD_INDEX_SIZE;
+        __pud_cache_index = RADIX_PUD_INDEX_SIZE;
         __pmd_cache_index = RADIX_PMD_INDEX_SIZE;
         __pte_table_size = RADIX_PTE_TABLE_SIZE;
         __pmd_table_size = RADIX_PMD_TABLE_SIZE;
@@ -579,7 +598,8 @@ void __init radix__early_init_mmu(void)
 
         radix_init_iamr();
         radix_init_pgtable();
-
+        /* Switch to the guard PID before turning on MMU */
+        radix__switch_mmu_context(NULL, &init_mm);
         if (cpu_has_feature(CPU_FTR_HVMODE))
                 tlbiel_all();
 }
@@ -604,6 +624,7 @@ void radix__early_init_mmu_secondary(void)
         }
         radix_init_iamr();
 
+        radix__switch_mmu_context(NULL, &init_mm);
         if (cpu_has_feature(CPU_FTR_HVMODE))
                 tlbiel_all();
 }
@@ -666,6 +687,30 @@ static void free_pmd_table(pmd_t *pmd_start, pud_t *pud)
         pud_clear(pud);
 }
 
+struct change_mapping_params {
+        pte_t *pte;
+        unsigned long start;
+        unsigned long end;
+        unsigned long aligned_start;
+        unsigned long aligned_end;
+};
+
+static int stop_machine_change_mapping(void *data)
+{
+        struct change_mapping_params *params =
+                        (struct change_mapping_params *)data;
+
+        if (!data)
+                return -1;
+
+        spin_unlock(&init_mm.page_table_lock);
+        pte_clear(&init_mm, params->aligned_start, params->pte);
+        create_physical_mapping(params->aligned_start, params->start);
+        create_physical_mapping(params->end, params->aligned_end);
+        spin_lock(&init_mm.page_table_lock);
+        return 0;
+}
+
 static void remove_pte_table(pte_t *pte_start, unsigned long addr,
                              unsigned long end)
 {
@@ -694,6 +739,52 @@ static void remove_pte_table(pte_t *pte_start, unsigned long addr,
         }
 }
 
+/*
+ * clear the pte and potentially split the mapping helper
+ */
+static void split_kernel_mapping(unsigned long addr, unsigned long end,
+                                unsigned long size, pte_t *pte)
+{
+        unsigned long mask = ~(size - 1);
+        unsigned long aligned_start = addr & mask;
+        unsigned long aligned_end = addr + size;
+        struct change_mapping_params params;
+        bool split_region = false;
+
+        if ((end - addr) < size) {
+                /*
+                 * We're going to clear the PTE, but not flushed
+                 * the mapping, time to remap and flush. The
+                 * effects if visible outside the processor or
+                 * if we are running in code close to the
+                 * mapping we cleared, we are in trouble.
+                 */
+                if (overlaps_kernel_text(aligned_start, addr) ||
+                        overlaps_kernel_text(end, aligned_end)) {
+                        /*
+                         * Hack, just return, don't pte_clear
+                         */
+                        WARN_ONCE(1, "Linear mapping %lx->%lx overlaps kernel "
+                                  "text, not splitting\n", addr, end);
+                        return;
+                }
+                split_region = true;
+        }
+
+        if (split_region) {
+                params.pte = pte;
+                params.start = addr;
+                params.end = end;
+                params.aligned_start = addr & ~(size - 1);
+                params.aligned_end = min_t(unsigned long, aligned_end,
+                                (unsigned long)__va(memblock_end_of_DRAM()));
+                stop_machine(stop_machine_change_mapping, &params, NULL);
+                return;
+        }
+
+        pte_clear(&init_mm, addr, pte);
+}
+
 static void remove_pmd_table(pmd_t *pmd_start, unsigned long addr,
                              unsigned long end)
 {
@@ -709,13 +800,7 @@ static void remove_pmd_table(pmd_t *pmd_start, unsigned long addr,
                         continue;
 
                 if (pmd_huge(*pmd)) {
-                        if (!IS_ALIGNED(addr, PMD_SIZE) ||
-                            !IS_ALIGNED(next, PMD_SIZE)) {
-                                WARN_ONCE(1, "%s: unaligned range\n", __func__);
-                                continue;
-                        }
-
-                        pte_clear(&init_mm, addr, (pte_t *)pmd);
+                        split_kernel_mapping(addr, end, PMD_SIZE, (pte_t *)pmd);
                         continue;
                 }
 
@@ -740,13 +825,7 @@ static void remove_pud_table(pud_t *pud_start, unsigned long addr,
                         continue;
 
                 if (pud_huge(*pud)) {
-                        if (!IS_ALIGNED(addr, PUD_SIZE) ||
-                            !IS_ALIGNED(next, PUD_SIZE)) {
-                                WARN_ONCE(1, "%s: unaligned range\n", __func__);
-                                continue;
-                        }
-
-                        pte_clear(&init_mm, addr, (pte_t *)pud);
+                        split_kernel_mapping(addr, end, PUD_SIZE, (pte_t *)pud);
                         continue;
                 }
 
@@ -772,13 +851,7 @@ static void remove_pagetable(unsigned long start, unsigned long end)
                         continue;
 
                 if (pgd_huge(*pgd)) {
-                        if (!IS_ALIGNED(addr, PGDIR_SIZE) ||
-                            !IS_ALIGNED(next, PGDIR_SIZE)) {
-                                WARN_ONCE(1, "%s: unaligned range\n", __func__);
-                                continue;
-                        }
-
-                        pte_clear(&init_mm, addr, (pte_t *)pgd);
+                        split_kernel_mapping(addr, end, PGDIR_SIZE, (pte_t *)pgd);
                         continue;
                 }
 
diff --git a/arch/powerpc/mm/pgtable_64.c b/arch/powerpc/mm/pgtable_64.c
index c9a623c2d8a2..28c980eb4422 100644
--- a/arch/powerpc/mm/pgtable_64.c
+++ b/arch/powerpc/mm/pgtable_64.c
@@ -82,6 +82,8 @@ unsigned long __pgd_index_size;
 EXPORT_SYMBOL(__pgd_index_size);
 unsigned long __pmd_cache_index;
 EXPORT_SYMBOL(__pmd_cache_index);
+unsigned long __pud_cache_index;
+EXPORT_SYMBOL(__pud_cache_index);
 unsigned long __pte_table_size;
 EXPORT_SYMBOL(__pte_table_size);
 unsigned long __pmd_table_size;
@@ -471,6 +473,8 @@ void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0,
         if (old & PATB_HR) {
                 asm volatile(PPC_TLBIE_5(%0,%1,2,0,1) : :
                              "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
+                asm volatile(PPC_TLBIE_5(%0,%1,2,1,1) : :
+                             "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
                 trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 1);
         } else {
                 asm volatile(PPC_TLBIE_5(%0,%1,2,0,0) : :
diff --git a/arch/powerpc/mm/tlb_hash64.c b/arch/powerpc/mm/tlb_hash64.c
index 881ebd53ffc2..9b23f12e863c 100644
--- a/arch/powerpc/mm/tlb_hash64.c
+++ b/arch/powerpc/mm/tlb_hash64.c
@@ -51,7 +51,7 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
         unsigned int psize;
         int ssize;
         real_pte_t rpte;
-        int i;
+        int i, offset;
 
         i = batch->index;
 
@@ -67,6 +67,10 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
                 psize = get_slice_psize(mm, addr);
                 /* Mask the address for the correct page size */
                 addr &= ~((1UL << mmu_psize_defs[psize].shift) - 1);
+                if (unlikely(psize == MMU_PAGE_16G))
+                        offset = PTRS_PER_PUD;
+                else
+                        offset = PTRS_PER_PMD;
 #else
                 BUG();
                 psize = pte_pagesize_index(mm, addr, pte); /* shutup gcc */
@@ -78,6 +82,7 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
                  * support 64k pages, this might be different from the
                  * hardware page size encoded in the slice table. */
                 addr &= PAGE_MASK;
+                offset = PTRS_PER_PTE;
         }
 
 
@@ -91,7 +96,7 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
         }
         WARN_ON(vsid == 0);
         vpn = hpt_vpn(addr, vsid, ssize);
-        rpte = __real_pte(__pte(pte), ptep);
+        rpte = __real_pte(__pte(pte), ptep, offset);
 
         /*
          * Check if we have an active batch on this CPU. If not, just
diff --git a/arch/powerpc/net/bpf_jit_comp.c b/arch/powerpc/net/bpf_jit_comp.c
index 872d1f6dd11e..a9636d8cba15 100644
--- a/arch/powerpc/net/bpf_jit_comp.c
+++ b/arch/powerpc/net/bpf_jit_comp.c
@@ -327,6 +327,9 @@ static int bpf_jit_build_body(struct bpf_prog *fp, u32 *image,
                         BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, len) != 4);
                         PPC_LWZ_OFFS(r_A, r_skb, offsetof(struct sk_buff, len));
                         break;
+                case BPF_LDX | BPF_W | BPF_ABS: /* A = *((u32 *)(seccomp_data + K)); */
+                        PPC_LWZ_OFFS(r_A, r_skb, K);
+                        break;
                 case BPF_LDX | BPF_W | BPF_LEN: /* X = skb->len; */
                         PPC_LWZ_OFFS(r_X, r_skb, offsetof(struct sk_buff, len));
                         break;
diff --git a/arch/powerpc/platforms/powernv/opal-imc.c b/arch/powerpc/platforms/powernv/opal-imc.c
index dd4c9b8b8a81..f6f55ab4980e 100644
--- a/arch/powerpc/platforms/powernv/opal-imc.c
+++ b/arch/powerpc/platforms/powernv/opal-imc.c
@@ -199,9 +199,11 @@ static void disable_nest_pmu_counters(void)
         const struct cpumask *l_cpumask;
 
         get_online_cpus();
-        for_each_online_node(nid) {
+        for_each_node_with_cpus(nid) {
                 l_cpumask = cpumask_of_node(nid);
-                cpu = cpumask_first(l_cpumask);
+                cpu = cpumask_first_and(l_cpumask, cpu_online_mask);
+                if (cpu >= nr_cpu_ids)
+                        continue;
                 opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST,
                                        get_hard_smp_processor_id(cpu));
         }
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
index 496e47696ed0..a6c92c78c9b2 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -1854,7 +1854,7 @@ static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
         s64 rc;
 
         if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
-                return -ENODEV;;
+                return -ENODEV;
 
         pe = &phb->ioda.pe_array[pdn->pe_number];
         if (pe->tce_bypass_enabled) {
diff --git a/arch/powerpc/platforms/powernv/setup.c b/arch/powerpc/platforms/powernv/setup.c
index 4fb21e17504a..092715b9674b 100644
--- a/arch/powerpc/platforms/powernv/setup.c
+++ b/arch/powerpc/platforms/powernv/setup.c
@@ -80,6 +80,10 @@ static void pnv_setup_rfi_flush(void)
                 if (np && of_property_read_bool(np, "disabled"))
                         enable--;
 
+                np = of_get_child_by_name(fw_features, "speculation-policy-favor-security");
+                if (np && of_property_read_bool(np, "disabled"))
+                        enable = 0;
+
                 of_node_put(np);
                 of_node_put(fw_features);
         }
diff --git a/arch/powerpc/platforms/powernv/vas-window.c b/arch/powerpc/platforms/powernv/vas-window.c
index 2b3eb01ab110..b7c53a51c31b 100644
--- a/arch/powerpc/platforms/powernv/vas-window.c
+++ b/arch/powerpc/platforms/powernv/vas-window.c
@@ -1063,16 +1063,16 @@ struct vas_window *vas_tx_win_open(int vasid, enum vas_cop_type cop,
                         rc = PTR_ERR(txwin->paste_kaddr);
                         goto free_window;
                 }
+        } else {
+                /*
+                 * A user mapping must ensure that context switch issues
+                 * CP_ABORT for this thread.
+                 */
+                rc = set_thread_uses_vas();
+                if (rc)
+                        goto free_window;
         }
 
-        /*
-         * Now that we have a send window, ensure context switch issues
-         * CP_ABORT for this thread.
-         */
-        rc = -EINVAL;
-        if (set_thread_uses_vas() < 0)
-                goto free_window;
-
         set_vinst_win(vinst, txwin);
 
         return txwin;
diff --git a/arch/powerpc/platforms/pseries/hotplug-cpu.c b/arch/powerpc/platforms/pseries/hotplug-cpu.c
index dceb51454d8d..652d3e96b812 100644
--- a/arch/powerpc/platforms/pseries/hotplug-cpu.c
+++ b/arch/powerpc/platforms/pseries/hotplug-cpu.c
@@ -36,6 +36,7 @@
 #include <asm/xics.h>
 #include <asm/xive.h>
 #include <asm/plpar_wrappers.h>
+#include <asm/topology.h>
 
 #include "pseries.h"
 #include "offline_states.h"
@@ -331,6 +332,7 @@ static void pseries_remove_processor(struct device_node *np)
                         BUG_ON(cpu_online(cpu));
                         set_cpu_present(cpu, false);
                         set_hard_smp_processor_id(cpu, -1);
+                        update_numa_cpu_lookup_table(cpu, -1);
                         break;
                 }
                 if (cpu >= nr_cpu_ids)
@@ -340,8 +342,6 @@ static void pseries_remove_processor(struct device_node *np)
         cpu_maps_update_done();
 }
 
-extern int find_and_online_cpu_nid(int cpu);
-
 static int dlpar_online_cpu(struct device_node *dn)
 {
         int rc = 0;
diff --git a/arch/powerpc/platforms/pseries/ras.c b/arch/powerpc/platforms/pseries/ras.c
index 81d8614e7379..5e1ef9150182 100644
--- a/arch/powerpc/platforms/pseries/ras.c
+++ b/arch/powerpc/platforms/pseries/ras.c
@@ -49,6 +49,28 @@ static irqreturn_t ras_error_interrupt(int irq, void *dev_id);
 
 
 /*
+ * Enable the hotplug interrupt late because processing them may touch other
+ * devices or systems (e.g. hugepages) that have not been initialized at the
+ * subsys stage.
+ */
+int __init init_ras_hotplug_IRQ(void)
+{
+        struct device_node *np;
+
+        /* Hotplug Events */
+        np = of_find_node_by_path("/event-sources/hot-plug-events");
+        if (np != NULL) {
+                if (dlpar_workqueue_init() == 0)
+                        request_event_sources_irqs(np, ras_hotplug_interrupt,
+                                                   "RAS_HOTPLUG");
+                of_node_put(np);
+        }
+
+        return 0;
+}
+machine_late_initcall(pseries, init_ras_hotplug_IRQ);
+
+/*
  * Initialize handlers for the set of interrupts caused by hardware errors
  * and power system events.
  */
@@ -66,15 +88,6 @@ static int __init init_ras_IRQ(void)
                 of_node_put(np);
         }
 
-        /* Hotplug Events */
-        np = of_find_node_by_path("/event-sources/hot-plug-events");
-        if (np != NULL) {
-                if (dlpar_workqueue_init() == 0)
-                        request_event_sources_irqs(np, ras_hotplug_interrupt,
-                                           "RAS_HOTPLUG");
-                of_node_put(np);
-        }
-
         /* EPOW Events */
         np = of_find_node_by_path("/event-sources/epow-events");
         if (np != NULL) {
diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c
index 372d7ada1a0c..1a527625acf7 100644
--- a/arch/powerpc/platforms/pseries/setup.c
+++ b/arch/powerpc/platforms/pseries/setup.c
@@ -482,7 +482,8 @@ static void pseries_setup_rfi_flush(void)
                 if (types == L1D_FLUSH_NONE)
                         types = L1D_FLUSH_FALLBACK;
 
-                if (!(result.behaviour & H_CPU_BEHAV_L1D_FLUSH_PR))
+                if ((!(result.behaviour & H_CPU_BEHAV_L1D_FLUSH_PR)) ||
+                    (!(result.behaviour & H_CPU_BEHAV_FAVOUR_SECURITY)))
                         enable = false;
         } else {
                 /* Default to fallback if case hcall is not available */
diff --git a/arch/powerpc/sysdev/xive/spapr.c b/arch/powerpc/sysdev/xive/spapr.c
index d9c4c9366049..091f1d0d0af1 100644
--- a/arch/powerpc/sysdev/xive/spapr.c
+++ b/arch/powerpc/sysdev/xive/spapr.c
@@ -356,7 +356,8 @@ static int xive_spapr_configure_queue(u32 target, struct xive_q *q, u8 prio,
 
         rc = plpar_int_get_queue_info(0, target, prio, &esn_page, &esn_size);
         if (rc) {
-                pr_err("Error %lld getting queue info prio %d\n", rc, prio);
+                pr_err("Error %lld getting queue info CPU %d prio %d\n", rc,
+                       target, prio);
                 rc = -EIO;
                 goto fail;
         }
@@ -370,7 +371,8 @@ static int xive_spapr_configure_queue(u32 target, struct xive_q *q, u8 prio,
         /* Configure and enable the queue in HW */
         rc = plpar_int_set_queue_config(flags, target, prio, qpage_phys, order);
         if (rc) {
-                pr_err("Error %lld setting queue for prio %d\n", rc, prio);
+                pr_err("Error %lld setting queue for CPU %d prio %d\n", rc,
+                       target, prio);
                 rc = -EIO;
         } else {
                 q->qpage = qpage;
@@ -389,8 +391,8 @@ static int xive_spapr_setup_queue(unsigned int cpu, struct xive_cpu *xc,
         if (IS_ERR(qpage))
                 return PTR_ERR(qpage);
 
-        return xive_spapr_configure_queue(cpu, q, prio, qpage,
-                                          xive_queue_shift);
+        return xive_spapr_configure_queue(get_hard_smp_processor_id(cpu),
+                                          q, prio, qpage, xive_queue_shift);
 }
 
 static void xive_spapr_cleanup_queue(unsigned int cpu, struct xive_cpu *xc,
@@ -399,10 +401,12 @@ static void xive_spapr_cleanup_queue(unsigned int cpu, struct xive_cpu *xc,
         struct xive_q *q = &xc->queue[prio];
         unsigned int alloc_order;
         long rc;
+        int hw_cpu = get_hard_smp_processor_id(cpu);
 
-        rc = plpar_int_set_queue_config(0, cpu, prio, 0, 0);
+        rc = plpar_int_set_queue_config(0, hw_cpu, prio, 0, 0);
         if (rc)
-                pr_err("Error %ld setting queue for prio %d\n", rc, prio);
+                pr_err("Error %ld setting queue for CPU %d prio %d\n", rc,
+                       hw_cpu, prio);
 
         alloc_order = xive_alloc_order(xive_queue_shift);
         free_pages((unsigned long)q->qpage, alloc_order);
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index b6722c246d9c..04807c7f64cc 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -8,7 +8,6 @@ config RISCV
         select OF
         select OF_EARLY_FLATTREE
         select OF_IRQ
-        select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
         select ARCH_WANT_FRAME_POINTERS
         select CLONE_BACKWARDS
         select COMMON_CLK
@@ -20,7 +19,6 @@ config RISCV
         select GENERIC_STRNLEN_USER
         select GENERIC_SMP_IDLE_THREAD
         select GENERIC_ATOMIC64 if !64BIT || !RISCV_ISA_A
-        select ARCH_WANT_OPTIONAL_GPIOLIB
         select HAVE_MEMBLOCK
         select HAVE_MEMBLOCK_NODE_MAP
         select HAVE_DMA_API_DEBUG
@@ -34,7 +32,6 @@ config RISCV
         select HAVE_ARCH_TRACEHOOK
         select MODULES_USE_ELF_RELA if MODULES
         select THREAD_INFO_IN_TASK
-        select RISCV_IRQ_INTC
         select RISCV_TIMER
 
 config MMU
diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h
index c0319cbf1eec..5510366d169a 100644
--- a/arch/riscv/include/asm/barrier.h
+++ b/arch/riscv/include/asm/barrier.h
@@ -34,9 +34,9 @@
 #define wmb()           RISCV_FENCE(ow,ow)
 
 /* These barriers do not need to enforce ordering on devices, just memory. */
-#define smp_mb()        RISCV_FENCE(rw,rw)
-#define smp_rmb()       RISCV_FENCE(r,r)
-#define smp_wmb()       RISCV_FENCE(w,w)
+#define __smp_mb()      RISCV_FENCE(rw,rw)
+#define __smp_rmb()     RISCV_FENCE(r,r)
+#define __smp_wmb()     RISCV_FENCE(w,w)
 
 /*
  * This is a very specific barrier: it's currently only used in two places in
diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index 87fc045be51f..56fa592cfa34 100644
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@ -172,6 +172,9 @@ ENTRY(handle_exception)
         move a1, sp /* pt_regs */
         tail do_IRQ
 1:
+        /* Exceptions run with interrupts enabled */
+        csrs sstatus, SR_SIE
+
         /* Handle syscalls */
         li t0, EXC_SYSCALL
         beq s4, t0, handle_syscall
@@ -198,8 +201,6 @@ handle_syscall:
          */
         addi s2, s2, 0x4
         REG_S s2, PT_SEPC(sp)
-        /* System calls run with interrupts enabled */
-        csrs sstatus, SR_SIE
         /* Trace syscalls, but only if requested by the user. */
         REG_L t0, TASK_TI_FLAGS(tp)
         andi t0, t0, _TIF_SYSCALL_TRACE
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 226eeb190f90..6e07ed37bbff 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -64,7 +64,7 @@ ENTRY(_start)
         /* Start the kernel */
         mv a0, s0
         mv a1, s1
-        call sbi_save
+        call parse_dtb
         tail start_kernel
 
 relocate:
diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
index 09f7064e898c..c11f40c1b2a8 100644
--- a/arch/riscv/kernel/setup.c
+++ b/arch/riscv/kernel/setup.c
@@ -144,7 +144,7 @@ asmlinkage void __init setup_vm(void)
 #endif
 }
 
-void __init sbi_save(unsigned int hartid, void *dtb)
+void __init parse_dtb(unsigned int hartid, void *dtb)
 {
         early_init_dt_scan(__va(dtb));
 }
diff --git a/arch/s390/kvm/intercept.c b/arch/s390/kvm/intercept.c
index 9c7d70715862..07c6e81163bf 100644
--- a/arch/s390/kvm/intercept.c
+++ b/arch/s390/kvm/intercept.c
@@ -22,22 +22,6 @@
 #include "trace.h"
 #include "trace-s390.h"
 
-
-static const intercept_handler_t instruction_handlers[256] = {
-        [0x01] = kvm_s390_handle_01,
-        [0x82] = kvm_s390_handle_lpsw,
-        [0x83] = kvm_s390_handle_diag,
-        [0xaa] = kvm_s390_handle_aa,
-        [0xae] = kvm_s390_handle_sigp,
-        [0xb2] = kvm_s390_handle_b2,
-        [0xb6] = kvm_s390_handle_stctl,
-        [0xb7] = kvm_s390_handle_lctl,
-        [0xb9] = kvm_s390_handle_b9,
-        [0xe3] = kvm_s390_handle_e3,
-        [0xe5] = kvm_s390_handle_e5,
-        [0xeb] = kvm_s390_handle_eb,
-};
-
 u8 kvm_s390_get_ilen(struct kvm_vcpu *vcpu)
 {
         struct kvm_s390_sie_block *sie_block = vcpu->arch.sie_block;
@@ -129,16 +113,39 @@ static int handle_validity(struct kvm_vcpu *vcpu)
 
 static int handle_instruction(struct kvm_vcpu *vcpu)
 {
-        intercept_handler_t handler;
-
         vcpu->stat.exit_instruction++;
         trace_kvm_s390_intercept_instruction(vcpu,
                                              vcpu->arch.sie_block->ipa,
                                              vcpu->arch.sie_block->ipb);
-        handler = instruction_handlers[vcpu->arch.sie_block->ipa >> 8];
-        if (handler)
-                return handler(vcpu);
-        return -EOPNOTSUPP;
+
+        switch (vcpu->arch.sie_block->ipa >> 8) {
+        case 0x01:
+                return kvm_s390_handle_01(vcpu);
+        case 0x82:
+                return kvm_s390_handle_lpsw(vcpu);
+        case 0x83:
+                return kvm_s390_handle_diag(vcpu);
+        case 0xaa:
+                return kvm_s390_handle_aa(vcpu);
+        case 0xae:
+                return kvm_s390_handle_sigp(vcpu);
+        case 0xb2:
+                return kvm_s390_handle_b2(vcpu);
+        case 0xb6:
+                return kvm_s390_handle_stctl(vcpu);
+        case 0xb7:
+                return kvm_s390_handle_lctl(vcpu);
+        case 0xb9:
+                return kvm_s390_handle_b9(vcpu);
+        case 0xe3:
+                return kvm_s390_handle_e3(vcpu);
+        case 0xe5:
+                return kvm_s390_handle_e5(vcpu);
+        case 0xeb:
+                return kvm_s390_handle_eb(vcpu);
+        default:
+                return -EOPNOTSUPP;
+        }
 }
 
 static int inject_prog_on_prog_intercept(struct kvm_vcpu *vcpu)
diff --git a/arch/s390/kvm/interrupt.c b/arch/s390/kvm/interrupt.c
index aabf46f5f883..b04616b57a94 100644
--- a/arch/s390/kvm/interrupt.c
+++ b/arch/s390/kvm/interrupt.c
@@ -169,8 +169,15 @@ static int ckc_interrupts_enabled(struct kvm_vcpu *vcpu)
 
 static int ckc_irq_pending(struct kvm_vcpu *vcpu)
 {
-        if (vcpu->arch.sie_block->ckc >= kvm_s390_get_tod_clock_fast(vcpu->kvm))
+        const u64 now = kvm_s390_get_tod_clock_fast(vcpu->kvm);
+        const u64 ckc = vcpu->arch.sie_block->ckc;
+
+        if (vcpu->arch.sie_block->gcr[0] & 0x0020000000000000ul) {
+                if ((s64)ckc >= (s64)now)
+                        return 0;
+        } else if (ckc >= now) {
                 return 0;
+        }
         return ckc_interrupts_enabled(vcpu);
 }
 
@@ -187,12 +194,6 @@ static int cpu_timer_irq_pending(struct kvm_vcpu *vcpu)
         return kvm_s390_get_cpu_timer(vcpu) >> 63;
 }
 
-static inline int is_ioirq(unsigned long irq_type)
-{
-        return ((irq_type >= IRQ_PEND_IO_ISC_7) &&
-                (irq_type <= IRQ_PEND_IO_ISC_0));
-}
-
 static uint64_t isc_to_isc_bits(int isc)
 {
         return (0x80 >> isc) << 24;
@@ -236,10 +237,15 @@ static inline int kvm_s390_gisa_tac_ipm_gisc(struct kvm_s390_gisa *gisa, u32 gis
         return test_and_clear_bit_inv(IPM_BIT_OFFSET + gisc, (unsigned long *) gisa);
 }
 
-static inline unsigned long pending_irqs(struct kvm_vcpu *vcpu)
+static inline unsigned long pending_irqs_no_gisa(struct kvm_vcpu *vcpu)
 {
         return vcpu->kvm->arch.float_int.pending_irqs |
-                vcpu->arch.local_int.pending_irqs |
+                vcpu->arch.local_int.pending_irqs;
+}
+
+static inline unsigned long pending_irqs(struct kvm_vcpu *vcpu)
+{
+        return pending_irqs_no_gisa(vcpu) |
                 kvm_s390_gisa_get_ipm(vcpu->kvm->arch.gisa) << IRQ_PEND_IO_ISC_7;
 }
 
@@ -337,7 +343,7 @@ static void __reset_intercept_indicators(struct kvm_vcpu *vcpu)
 
 static void set_intercept_indicators_io(struct kvm_vcpu *vcpu)
 {
-        if (!(pending_irqs(vcpu) & IRQ_PEND_IO_MASK))
+        if (!(pending_irqs_no_gisa(vcpu) & IRQ_PEND_IO_MASK))
                 return;
         else if (psw_ioint_disabled(vcpu))
                 kvm_s390_set_cpuflags(vcpu, CPUSTAT_IO_INT);
@@ -1011,24 +1017,6 @@ out:
         return rc;
 }
 
-typedef int (*deliver_irq_t)(struct kvm_vcpu *vcpu);
-
-static const deliver_irq_t deliver_irq_funcs[] = {
-        [IRQ_PEND_MCHK_EX]        = __deliver_machine_check,
-        [IRQ_PEND_MCHK_REP]       = __deliver_machine_check,
-        [IRQ_PEND_PROG]           = __deliver_prog,
-        [IRQ_PEND_EXT_EMERGENCY]  = __deliver_emergency_signal,
-        [IRQ_PEND_EXT_EXTERNAL]   = __deliver_external_call,
-        [IRQ_PEND_EXT_CLOCK_COMP] = __deliver_ckc,
-        [IRQ_PEND_EXT_CPU_TIMER]  = __deliver_cpu_timer,
-        [IRQ_PEND_RESTART]        = __deliver_restart,
-        [IRQ_PEND_SET_PREFIX]     = __deliver_set_prefix,
-        [IRQ_PEND_PFAULT_INIT]    = __deliver_pfault_init,
-        [IRQ_PEND_EXT_SERVICE]    = __deliver_service,
-        [IRQ_PEND_PFAULT_DONE]    = __deliver_pfault_done,
-        [IRQ_PEND_VIRTIO]         = __deliver_virtio,
-};
-
 /* Check whether an external call is pending (deliverable or not) */
 int kvm_s390_ext_call_pending(struct kvm_vcpu *vcpu)
 {
@@ -1066,13 +1054,19 @@ int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
 
 static u64 __calculate_sltime(struct kvm_vcpu *vcpu)
 {
-        u64 now, cputm, sltime = 0;
+        const u64 now = kvm_s390_get_tod_clock_fast(vcpu->kvm);
+        const u64 ckc = vcpu->arch.sie_block->ckc;
+        u64 cputm, sltime = 0;
 
         if (ckc_interrupts_enabled(vcpu)) {
-                now = kvm_s390_get_tod_clock_fast(vcpu->kvm);
-                sltime = tod_to_ns(vcpu->arch.sie_block->ckc - now);
-                /* already expired or overflow? */
-                if (!sltime || vcpu->arch.sie_block->ckc <= now)
+                if (vcpu->arch.sie_block->gcr[0] & 0x0020000000000000ul) {
+                        if ((s64)now < (s64)ckc)
+                                sltime = tod_to_ns((s64)ckc - (s64)now);
+                } else if (now < ckc) {
+                        sltime = tod_to_ns(ckc - now);
+                }
+                /* already expired */
+                if (!sltime)
                         return 0;
                 if (cpu_timer_interrupts_enabled(vcpu)) {
                         cputm = kvm_s390_get_cpu_timer(vcpu);
@@ -1192,7 +1186,6 @@ void kvm_s390_clear_local_irqs(struct kvm_vcpu *vcpu)
 int __must_check kvm_s390_deliver_pending_interrupts(struct kvm_vcpu *vcpu)
 {
         struct kvm_s390_local_interrupt *li = &vcpu->arch.local_int;
-        deliver_irq_t func;
         int rc = 0;
         unsigned long irq_type;
         unsigned long irqs;
@@ -1212,16 +1205,57 @@ int __must_check kvm_s390_deliver_pending_interrupts(struct kvm_vcpu *vcpu)
         while ((irqs = deliverable_irqs(vcpu)) && !rc) {
                 /* bits are in the reverse order of interrupt priority */
                 irq_type = find_last_bit(&irqs, IRQ_PEND_COUNT);
-                if (is_ioirq(irq_type)) {
+                switch (irq_type) {
+                case IRQ_PEND_IO_ISC_0:
+                case IRQ_PEND_IO_ISC_1:
+                case IRQ_PEND_IO_ISC_2:
+                case IRQ_PEND_IO_ISC_3:
+                case IRQ_PEND_IO_ISC_4:
+                case IRQ_PEND_IO_ISC_5:
+                case IRQ_PEND_IO_ISC_6:
+                case IRQ_PEND_IO_ISC_7:
                         rc = __deliver_io(vcpu, irq_type);
-                } else {
-                        func = deliver_irq_funcs[irq_type];
-                        if (!func) {
-                                WARN_ON_ONCE(func == NULL);
-                                clear_bit(irq_type, &li->pending_irqs);
-                                continue;
-                        }
-                        rc = func(vcpu);
+                        break;
+                case IRQ_PEND_MCHK_EX:
+                case IRQ_PEND_MCHK_REP:
+                        rc = __deliver_machine_check(vcpu);
+                        break;
+                case IRQ_PEND_PROG:
+                        rc = __deliver_prog(vcpu);
+                        break;
+                case IRQ_PEND_EXT_EMERGENCY:
+                        rc = __deliver_emergency_signal(vcpu);
+                        break;
+                case IRQ_PEND_EXT_EXTERNAL:
+                        rc = __deliver_external_call(vcpu);
+                        break;
+                case IRQ_PEND_EXT_CLOCK_COMP:
+                        rc = __deliver_ckc(vcpu);
+                        break;
+                case IRQ_PEND_EXT_CPU_TIMER:
+                        rc = __deliver_cpu_timer(vcpu);
+                        break;
+                case IRQ_PEND_RESTART:
+                        rc = __deliver_restart(vcpu);
+                        break;
+                case IRQ_PEND_SET_PREFIX:
+                        rc = __deliver_set_prefix(vcpu);
+                        break;
+                case IRQ_PEND_PFAULT_INIT:
+                        rc = __deliver_pfault_init(vcpu);
+                        break;
+                case IRQ_PEND_EXT_SERVICE:
+                        rc = __deliver_service(vcpu);
+                        break;
+                case IRQ_PEND_PFAULT_DONE:
+                        rc = __deliver_pfault_done(vcpu);
+                        break;
+                case IRQ_PEND_VIRTIO:
+                        rc = __deliver_virtio(vcpu);
+                        break;
+                default:
+                        WARN_ONCE(1, "Unknown pending irq type %ld", irq_type);
+                        clear_bit(irq_type, &li->pending_irqs);
                 }
         }
 
@@ -1701,7 +1735,8 @@ static void __floating_irq_kick(struct kvm *kvm, u64 type)
                 kvm_s390_set_cpuflags(dst_vcpu, CPUSTAT_STOP_INT);
                 break;
         case KVM_S390_INT_IO_MIN...KVM_S390_INT_IO_MAX:
-                kvm_s390_set_cpuflags(dst_vcpu, CPUSTAT_IO_INT);
+                if (!(type & KVM_S390_INT_IO_AI_MASK && kvm->arch.gisa))
+                        kvm_s390_set_cpuflags(dst_vcpu, CPUSTAT_IO_INT);
                 break;
         default:
                 kvm_s390_set_cpuflags(dst_vcpu, CPUSTAT_EXT_INT);
diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c
index ba4c7092335a..77d7818130db 100644
--- a/arch/s390/kvm/kvm-s390.c
+++ b/arch/s390/kvm/kvm-s390.c
@@ -179,6 +179,28 @@ int kvm_arch_hardware_enable(void)
 static void kvm_gmap_notifier(struct gmap *gmap, unsigned long start,
                               unsigned long end);
 
+static void kvm_clock_sync_scb(struct kvm_s390_sie_block *scb, u64 delta)
+{
+        u8 delta_idx = 0;
+
+        /*
+         * The TOD jumps by delta, we have to compensate this by adding
+         * -delta to the epoch.
+         */
+        delta = -delta;
+
+        /* sign-extension - we're adding to signed values below */
+        if ((s64)delta < 0)
+                delta_idx = -1;
+
+        scb->epoch += delta;
+        if (scb->ecd & ECD_MEF) {
+                scb->epdx += delta_idx;
+                if (scb->epoch < delta)
+                        scb->epdx += 1;
+        }
+}
+
 /*
  * This callback is executed during stop_machine(). All CPUs are therefore
  * temporarily stopped. In order not to change guest behavior, we have to
@@ -194,13 +216,17 @@ static int kvm_clock_sync(struct notifier_block *notifier, unsigned long val,
         unsigned long long *delta = v;
 
         list_for_each_entry(kvm, &vm_list, vm_list) {
-                kvm->arch.epoch -= *delta;
                 kvm_for_each_vcpu(i, vcpu, kvm) {
-                        vcpu->arch.sie_block->epoch -= *delta;
+                        kvm_clock_sync_scb(vcpu->arch.sie_block, *delta);
+                        if (i == 0) {
+                                kvm->arch.epoch = vcpu->arch.sie_block->epoch;
+                                kvm->arch.epdx = vcpu->arch.sie_block->epdx;
+                        }
                         if (vcpu->arch.cputm_enabled)
                                 vcpu->arch.cputm_start += *delta;
                         if (vcpu->arch.vsie_block)
-                                vcpu->arch.vsie_block->epoch -= *delta;
+                                kvm_clock_sync_scb(vcpu->arch.vsie_block,
+                                                   *delta);
                 }
         }
         return NOTIFY_OK;
@@ -902,12 +928,9 @@ static int kvm_s390_set_tod_ext(struct kvm *kvm, struct kvm_device_attr *attr)
         if (copy_from_user(&gtod, (void __user *)attr->addr, sizeof(gtod)))
                 return -EFAULT;
 
-        if (test_kvm_facility(kvm, 139))
-                kvm_s390_set_tod_clock_ext(kvm, &gtod);
-        else if (gtod.epoch_idx == 0)
-                kvm_s390_set_tod_clock(kvm, gtod.tod);
-        else
+        if (!test_kvm_facility(kvm, 139) && gtod.epoch_idx)
                 return -EINVAL;
+        kvm_s390_set_tod_clock(kvm, &gtod);
 
         VM_EVENT(kvm, 3, "SET: TOD extension: 0x%x, TOD base: 0x%llx",
                 gtod.epoch_idx, gtod.tod);
@@ -932,13 +955,14 @@ static int kvm_s390_set_tod_high(struct kvm *kvm, struct kvm_device_attr *attr)
 
 static int kvm_s390_set_tod_low(struct kvm *kvm, struct kvm_device_attr *attr)
 {
-        u64 gtod;
+        struct kvm_s390_vm_tod_clock gtod = { 0 };
 
-        if (copy_from_user(&gtod, (void __user *)attr->addr, sizeof(gtod)))
+        if (copy_from_user(&gtod.tod, (void __user *)attr->addr,
+                           sizeof(gtod.tod)))
                 return -EFAULT;
 
-        kvm_s390_set_tod_clock(kvm, gtod);
-        VM_EVENT(kvm, 3, "SET: TOD base: 0x%llx", gtod);
+        kvm_s390_set_tod_clock(kvm, &gtod);
+        VM_EVENT(kvm, 3, "SET: TOD base: 0x%llx", gtod.tod);
         return 0;
 }
 
@@ -2389,6 +2413,7 @@ void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
         mutex_lock(&vcpu->kvm->lock);
         preempt_disable();
         vcpu->arch.sie_block->epoch = vcpu->kvm->arch.epoch;
+        vcpu->arch.sie_block->epdx = vcpu->kvm->arch.epdx;
         preempt_enable();
         mutex_unlock(&vcpu->kvm->lock);
         if (!kvm_is_ucontrol(vcpu->kvm)) {
@@ -3021,8 +3046,8 @@ retry:
         return 0;
 }
 
-void kvm_s390_set_tod_clock_ext(struct kvm *kvm,
-                                 const struct kvm_s390_vm_tod_clock *gtod)
+void kvm_s390_set_tod_clock(struct kvm *kvm,
+                            const struct kvm_s390_vm_tod_clock *gtod)
 {
         struct kvm_vcpu *vcpu;
         struct kvm_s390_tod_clock_ext htod;
@@ -3034,10 +3059,12 @@ void kvm_s390_set_tod_clock_ext(struct kvm *kvm,
         get_tod_clock_ext((char *)&htod);
 
         kvm->arch.epoch = gtod->tod - htod.tod;
-        kvm->arch.epdx = gtod->epoch_idx - htod.epoch_idx;
-
-        if (kvm->arch.epoch > gtod->tod)
-                kvm->arch.epdx -= 1;
+        kvm->arch.epdx = 0;
+        if (test_kvm_facility(kvm, 139)) {
+                kvm->arch.epdx = gtod->epoch_idx - htod.epoch_idx;
+                if (kvm->arch.epoch > gtod->tod)
+                        kvm->arch.epdx -= 1;
+        }
 
         kvm_s390_vcpu_block_all(kvm);
         kvm_for_each_vcpu(i, vcpu, kvm) {
@@ -3050,22 +3077,6 @@ void kvm_s390_set_tod_clock_ext(struct kvm *kvm,
         mutex_unlock(&kvm->lock);
 }
 
-void kvm_s390_set_tod_clock(struct kvm *kvm, u64 tod)
-{
-        struct kvm_vcpu *vcpu;
-        int i;
-
-        mutex_lock(&kvm->lock);
-        preempt_disable();
-        kvm->arch.epoch = tod - get_tod_clock();
-        kvm_s390_vcpu_block_all(kvm);
-        kvm_for_each_vcpu(i, vcpu, kvm)
-                vcpu->arch.sie_block->epoch = kvm->arch.epoch;
-        kvm_s390_vcpu_unblock_all(kvm);
-        preempt_enable();
-        mutex_unlock(&kvm->lock);
-}
-
 /**
  * kvm_arch_fault_in_page - fault-in guest page if necessary
  * @vcpu: The corresponding virtual cpu
diff --git a/arch/s390/kvm/kvm-s390.h b/arch/s390/kvm/kvm-s390.h
index bd31b37b0e6f..f55ac0ef99ea 100644
--- a/arch/s390/kvm/kvm-s390.h
+++ b/arch/s390/kvm/kvm-s390.h
@@ -19,8 +19,6 @@
 #include <asm/processor.h>
 #include <asm/sclp.h>
 
-typedef int (*intercept_handler_t)(struct kvm_vcpu *vcpu);
-
 /* Transactional Memory Execution related macros */
 #define IS_TE_ENABLED(vcpu)     ((vcpu->arch.sie_block->ecb & ECB_TE))
 #define TDB_FORMAT1             1
@@ -283,9 +281,8 @@ int kvm_s390_handle_sigp(struct kvm_vcpu *vcpu);
 int kvm_s390_handle_sigp_pei(struct kvm_vcpu *vcpu);
 
 /* implemented in kvm-s390.c */
-void kvm_s390_set_tod_clock_ext(struct kvm *kvm,
-                                 const struct kvm_s390_vm_tod_clock *gtod);
-void kvm_s390_set_tod_clock(struct kvm *kvm, u64 tod);
+void kvm_s390_set_tod_clock(struct kvm *kvm,
+                            const struct kvm_s390_vm_tod_clock *gtod);
 long kvm_arch_fault_in_page(struct kvm_vcpu *vcpu, gpa_t gpa, int writable);
 int kvm_s390_store_status_unloaded(struct kvm_vcpu *vcpu, unsigned long addr);
 int kvm_s390_vcpu_store_status(struct kvm_vcpu *vcpu, unsigned long addr);
diff --git a/arch/s390/kvm/priv.c b/arch/s390/kvm/priv.c
index c4c4e157c036..f0b4185158af 100644
--- a/arch/s390/kvm/priv.c
+++ b/arch/s390/kvm/priv.c
@@ -85,9 +85,10 @@ int kvm_s390_handle_e3(struct kvm_vcpu *vcpu)
 /* Handle SCK (SET CLOCK) interception */
 static int handle_set_clock(struct kvm_vcpu *vcpu)
 {
+        struct kvm_s390_vm_tod_clock gtod = { 0 };
         int rc;
         u8 ar;
-        u64 op2, val;
+        u64 op2;
 
         vcpu->stat.instruction_sck++;
 
@@ -97,12 +98,12 @@ static int handle_set_clock(struct kvm_vcpu *vcpu)
         op2 = kvm_s390_get_base_disp_s(vcpu, &ar);
         if (op2 & 7)    /* Operand must be on a doubleword boundary */
                 return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
-        rc = read_guest(vcpu, op2, ar, &val, sizeof(val));
+        rc = read_guest(vcpu, op2, ar, &gtod.tod, sizeof(gtod.tod));
         if (rc)
                 return kvm_s390_inject_prog_cond(vcpu, rc);
 
-        VCPU_EVENT(vcpu, 3, "SCK: setting guest TOD to 0x%llx", val);
-        kvm_s390_set_tod_clock(vcpu->kvm, val);
+        VCPU_EVENT(vcpu, 3, "SCK: setting guest TOD to 0x%llx", gtod.tod);
+        kvm_s390_set_tod_clock(vcpu->kvm, &gtod);
 
         kvm_s390_set_psw_cc(vcpu, 0);
         return 0;
@@ -795,55 +796,60 @@ out:
         return rc;
 }
 
-static const intercept_handler_t b2_handlers[256] = {
-        [0x02] = handle_stidp,
-        [0x04] = handle_set_clock,
-        [0x10] = handle_set_prefix,
-        [0x11] = handle_store_prefix,
-        [0x12] = handle_store_cpu_address,
-        [0x14] = kvm_s390_handle_vsie,
-        [0x21] = handle_ipte_interlock,
-        [0x29] = handle_iske,
-        [0x2a] = handle_rrbe,
-        [0x2b] = handle_sske,
-        [0x2c] = handle_test_block,
-        [0x30] = handle_io_inst,
-        [0x31] = handle_io_inst,
-        [0x32] = handle_io_inst,
-        [0x33] = handle_io_inst,
-        [0x34] = handle_io_inst,
-        [0x35] = handle_io_inst,
-        [0x36] = handle_io_inst,
-        [0x37] = handle_io_inst,
-        [0x38] = handle_io_inst,
-        [0x39] = handle_io_inst,
-        [0x3a] = handle_io_inst,
-        [0x3b] = handle_io_inst,
-        [0x3c] = handle_io_inst,
-        [0x50] = handle_ipte_interlock,
-        [0x56] = handle_sthyi,
-        [0x5f] = handle_io_inst,
-        [0x74] = handle_io_inst,
-        [0x76] = handle_io_inst,
-        [0x7d] = handle_stsi,
-        [0xb1] = handle_stfl,
-        [0xb2] = handle_lpswe,
-};
-
 int kvm_s390_handle_b2(struct kvm_vcpu *vcpu)
 {
-        intercept_handler_t handler;
-
-        /*
-         * A lot of B2 instructions are priviledged. Here we check for
-         * the privileged ones, that we can handle in the kernel.
-         * Anything else goes to userspace.
-         */
-        handler = b2_handlers[vcpu->arch.sie_block->ipa & 0x00ff];
-        if (handler)
-                return handler(vcpu);
-
-        return -EOPNOTSUPP;
+        switch (vcpu->arch.sie_block->ipa & 0x00ff) {
+        case 0x02:
+                return handle_stidp(vcpu);
+        case 0x04:
+                return handle_set_clock(vcpu);
+        case 0x10:
+                return handle_set_prefix(vcpu);
+        case 0x11:
+                return handle_store_prefix(vcpu);
+        case 0x12:
+                return handle_store_cpu_address(vcpu);
+        case 0x14:
+                return kvm_s390_handle_vsie(vcpu);
+        case 0x21:
+        case 0x50:
+                return handle_ipte_interlock(vcpu);
+        case 0x29:
+                return handle_iske(vcpu);
+        case 0x2a:
+                return handle_rrbe(vcpu);
+        case 0x2b:
+                return handle_sske(vcpu);
+        case 0x2c:
+                return handle_test_block(vcpu);
+        case 0x30:
+        case 0x31:
+        case 0x32:
+        case 0x33:
+        case 0x34:
+        case 0x35:
+        case 0x36:
+        case 0x37:
+        case 0x38:
+        case 0x39:
+        case 0x3a:
+        case 0x3b:
+        case 0x3c:
+        case 0x5f:
+        case 0x74:
+        case 0x76:
+                return handle_io_inst(vcpu);
+        case 0x56:
+                return handle_sthyi(vcpu);
+        case 0x7d:
+                return handle_stsi(vcpu);
+        case 0xb1:
+                return handle_stfl(vcpu);
+        case 0xb2:
+                return handle_lpswe(vcpu);
+        default:
+                return -EOPNOTSUPP;
+        }
 }
 
 static int handle_epsw(struct kvm_vcpu *vcpu)
@@ -1105,25 +1111,22 @@ static int handle_essa(struct kvm_vcpu *vcpu)
         return 0;
 }
 
-static const intercept_handler_t b9_handlers[256] = {
-        [0x8a] = handle_ipte_interlock,
-        [0x8d] = handle_epsw,
-        [0x8e] = handle_ipte_interlock,
-        [0x8f] = handle_ipte_interlock,
-        [0xab] = handle_essa,
-        [0xaf] = handle_pfmf,
-};
-
 int kvm_s390_handle_b9(struct kvm_vcpu *vcpu)
 {
-        intercept_handler_t handler;
-
-        /* This is handled just as for the B2 instructions. */
-        handler = b9_handlers[vcpu->arch.sie_block->ipa & 0x00ff];
-        if (handler)
-                return handler(vcpu);
-
-        return -EOPNOTSUPP;
+        switch (vcpu->arch.sie_block->ipa & 0x00ff) {
+        case 0x8a:
+        case 0x8e:
+        case 0x8f:
+                return handle_ipte_interlock(vcpu);
+        case 0x8d:
+                return handle_epsw(vcpu);
+        case 0xab:
+                return handle_essa(vcpu);
+        case 0xaf:
+                return handle_pfmf(vcpu);
+        default:
+                return -EOPNOTSUPP;
+        }
 }
 
 int kvm_s390_handle_lctl(struct kvm_vcpu *vcpu)
@@ -1271,22 +1274,20 @@ static int handle_stctg(struct kvm_vcpu *vcpu)
         return rc ? kvm_s390_inject_prog_cond(vcpu, rc) : 0;
 }
 
-static const intercept_handler_t eb_handlers[256] = {
-        [0x2f] = handle_lctlg,
-        [0x25] = handle_stctg,
-        [0x60] = handle_ri,
-        [0x61] = handle_ri,
-        [0x62] = handle_ri,
-};
-
 int kvm_s390_handle_eb(struct kvm_vcpu *vcpu)
 {
-        intercept_handler_t handler;
-
-        handler = eb_handlers[vcpu->arch.sie_block->ipb & 0xff];
-        if (handler)
-                return handler(vcpu);
-        return -EOPNOTSUPP;
+        switch (vcpu->arch.sie_block->ipb & 0x000000ff) {
+        case 0x25:
+                return handle_stctg(vcpu);
+        case 0x2f:
+                return handle_lctlg(vcpu);
+        case 0x60:
+        case 0x61:
+        case 0x62:
+                return handle_ri(vcpu);
+        default:
+                return -EOPNOTSUPP;
+        }
 }
 
 static int handle_tprot(struct kvm_vcpu *vcpu)
@@ -1346,10 +1347,12 @@ out_unlock:
 
 int kvm_s390_handle_e5(struct kvm_vcpu *vcpu)
 {
-        /* For e5xx... instructions we only handle TPROT */
-        if ((vcpu->arch.sie_block->ipa & 0x00ff) == 0x01)
+        switch (vcpu->arch.sie_block->ipa & 0x00ff) {
+        case 0x01:
                 return handle_tprot(vcpu);
-        return -EOPNOTSUPP;
+        default:
+                return -EOPNOTSUPP;
+        }
 }
 
 static int handle_sckpf(struct kvm_vcpu *vcpu)
@@ -1380,17 +1383,14 @@ static int handle_ptff(struct kvm_vcpu *vcpu)
         return 0;
 }
 
-static const intercept_handler_t x01_handlers[256] = {
-        [0x04] = handle_ptff,
-        [0x07] = handle_sckpf,
-};
-
 int kvm_s390_handle_01(struct kvm_vcpu *vcpu)
 {
-        intercept_handler_t handler;
-
-        handler = x01_handlers[vcpu->arch.sie_block->ipa & 0x00ff];
-        if (handler)
-                return handler(vcpu);
-        return -EOPNOTSUPP;
+        switch (vcpu->arch.sie_block->ipa & 0x00ff) {
+        case 0x04:
+                return handle_ptff(vcpu);
+        case 0x07:
+                return handle_sckpf(vcpu);
+        default:
+                return -EOPNOTSUPP;
+        }
 }
diff --git a/arch/s390/kvm/vsie.c b/arch/s390/kvm/vsie.c
index ec772700ff96..8961e3970901 100644
--- a/arch/s390/kvm/vsie.c
+++ b/arch/s390/kvm/vsie.c
@@ -821,6 +821,7 @@ static int do_vsie_run(struct kvm_vcpu *vcpu, struct vsie_page *vsie_page)
 {
         struct kvm_s390_sie_block *scb_s = &vsie_page->scb_s;
         struct kvm_s390_sie_block *scb_o = vsie_page->scb_o;
+        int guest_bp_isolation;
         int rc;
 
         handle_last_fault(vcpu, vsie_page);
@@ -831,6 +832,20 @@ static int do_vsie_run(struct kvm_vcpu *vcpu, struct vsie_page *vsie_page)
                 s390_handle_mcck();
 
         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
+
+        /* save current guest state of bp isolation override */
+        guest_bp_isolation = test_thread_flag(TIF_ISOLATE_BP_GUEST);
+
+        /*
+         * The guest is running with BPBC, so we have to force it on for our
+         * nested guest. This is done by enabling BPBC globally, so the BPBC
+         * control in the SCB (which the nested guest can modify) is simply
+         * ignored.
+         */
+        if (test_kvm_facility(vcpu->kvm, 82) &&
+            vcpu->arch.sie_block->fpf & FPF_BPBC)
+                set_thread_flag(TIF_ISOLATE_BP_GUEST);
+
         local_irq_disable();
         guest_enter_irqoff();
         local_irq_enable();
@@ -840,6 +855,11 @@ static int do_vsie_run(struct kvm_vcpu *vcpu, struct vsie_page *vsie_page)
         local_irq_disable();
         guest_exit_irqoff();
         local_irq_enable();
+
+        /* restore guest state for bp isolation override */
+        if (!guest_bp_isolation)
+                clear_thread_flag(TIF_ISOLATE_BP_GUEST);
+
         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
 
         if (rc == -EINTR) {
diff --git a/arch/sh/boot/dts/Makefile b/arch/sh/boot/dts/Makefile
index 715def00a436..01d0f7fb14cc 100644
--- a/arch/sh/boot/dts/Makefile
+++ b/arch/sh/boot/dts/Makefile
@@ -1 +1,3 @@
-obj-$(CONFIG_USE_BUILTIN_DTB) += $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_SOURCE)).dtb.o
+ifneq ($(CONFIG_BUILTIN_DTB_SOURCE),"")
+obj-y += $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_SOURCE)).dtb.o
+endif
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index 6bf594ace663..8767e45f1b2b 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -430,6 +430,8 @@ config SPARC_LEON
         depends on SPARC32
         select USB_EHCI_BIG_ENDIAN_MMIO
         select USB_EHCI_BIG_ENDIAN_DESC
+        select USB_UHCI_BIG_ENDIAN_MMIO
+        select USB_UHCI_BIG_ENDIAN_DESC
         ---help---
           If you say Y here if you are running on a SPARC-LEON processor.
           The LEON processor is a synthesizable VHDL model of the
diff --git a/arch/sparc/include/asm/bug.h b/arch/sparc/include/asm/bug.h
index 6f17528356b2..ea53e418f6c0 100644
--- a/arch/sparc/include/asm/bug.h
+++ b/arch/sparc/include/asm/bug.h
@@ -9,10 +9,14 @@
 void do_BUG(const char *file, int line);
 #define BUG() do {                                      \
         do_BUG(__FILE__, __LINE__);                     \
+        barrier_before_unreachable();                   \
         __builtin_trap();                               \
 } while (0)
 #else
-#define BUG()           __builtin_trap()
+#define BUG() do {                                      \
+        barrier_before_unreachable();                   \
+        __builtin_trap();                               \
+} while (0)
 #endif
 
 #define HAVE_ARCH_BUG
diff --git a/arch/x86/.gitignore b/arch/x86/.gitignore
index aff152c87cf4..5a82bac5e0bc 100644
--- a/arch/x86/.gitignore
+++ b/arch/x86/.gitignore
@@ -1,6 +1,7 @@
 boot/compressed/vmlinux
 tools/test_get_len
 tools/insn_sanity
+tools/insn_decoder_test
 purgatory/kexec-purgatory.c
 purgatory/purgatory.ro
 
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 63bf349b2b24..eb7f43f23521 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -423,12 +423,6 @@ config X86_MPPARSE
           For old smp systems that do not have proper acpi support. Newer systems
           (esp with 64bit cpus) with acpi support, MADT and DSDT will override it
 
-config X86_BIGSMP
-        bool "Support for big SMP systems with more than 8 CPUs"
-        depends on X86_32 && SMP
-        ---help---
-          This option is needed for the systems that have more than 8 CPUs
-
 config GOLDFISH
        def_bool y
        depends on X86_GOLDFISH
@@ -436,6 +430,7 @@ config GOLDFISH
 config RETPOLINE
         bool "Avoid speculative indirect branches in kernel"
         default y
+        select STACK_VALIDATION if HAVE_STACK_VALIDATION
         help
           Compile kernel with the retpoline compiler options to guard against
           kernel-to-user data leaks by avoiding speculative indirect
@@ -460,6 +455,12 @@ config INTEL_RDT
           Say N if unsure.
 
 if X86_32
+config X86_BIGSMP
+        bool "Support for big SMP systems with more than 8 CPUs"
+        depends on SMP
+        ---help---
+          This option is needed for the systems that have more than 8 CPUs
+
 config X86_EXTENDED_PLATFORM
         bool "Support for extended (non-PC) x86 platforms"
         default y
@@ -949,25 +950,66 @@ config MAXSMP
           Enable maximum number of CPUS and NUMA Nodes for this architecture.
           If unsure, say N.
 
+#
+# The maximum number of CPUs supported:
+#
+# The main config value is NR_CPUS, which defaults to NR_CPUS_DEFAULT,
+# and which can be configured interactively in the
+# [NR_CPUS_RANGE_BEGIN ... NR_CPUS_RANGE_END] range.
+#
+# The ranges are different on 32-bit and 64-bit kernels, depending on
+# hardware capabilities and scalability features of the kernel.
+#
+# ( If MAXSMP is enabled we just use the highest possible value and disable
+#   interactive configuration. )
+#
+
+config NR_CPUS_RANGE_BEGIN
+        int
+        default NR_CPUS_RANGE_END if MAXSMP
+        default    1 if !SMP
+        default    2
+
+config NR_CPUS_RANGE_END
+        int
+        depends on X86_32
+        default   64 if  SMP &&  X86_BIGSMP
+        default    8 if  SMP && !X86_BIGSMP
+        default    1 if !SMP
+
+config NR_CPUS_RANGE_END
+        int
+        depends on X86_64
+        default 8192 if  SMP && ( MAXSMP ||  CPUMASK_OFFSTACK)
+        default  512 if  SMP && (!MAXSMP && !CPUMASK_OFFSTACK)
+        default    1 if !SMP
+
+config NR_CPUS_DEFAULT
+        int
+        depends on X86_32
+        default   32 if  X86_BIGSMP
+        default    8 if  SMP
+        default    1 if !SMP
+
+config NR_CPUS_DEFAULT
+        int
+        depends on X86_64
+        default 8192 if  MAXSMP
+        default   64 if  SMP
+        default    1 if !SMP
+
 config NR_CPUS
         int "Maximum number of CPUs" if SMP && !MAXSMP
-        range 2 8 if SMP && X86_32 && !X86_BIGSMP
-        range 2 64 if SMP && X86_32 && X86_BIGSMP
-        range 2 512 if SMP && !MAXSMP && !CPUMASK_OFFSTACK && X86_64
-        range 2 8192 if SMP && !MAXSMP && CPUMASK_OFFSTACK && X86_64
-        default "1" if !SMP
-        default "8192" if MAXSMP
-        default "32" if SMP && X86_BIGSMP
-        default "8" if SMP && X86_32
-        default "64" if SMP
+        range NR_CPUS_RANGE_BEGIN NR_CPUS_RANGE_END
+        default NR_CPUS_DEFAULT
         ---help---
           This allows you to specify the maximum number of CPUs which this
           kernel will support.  If CPUMASK_OFFSTACK is enabled, the maximum
           supported value is 8192, otherwise the maximum value is 512.  The
           minimum value which makes sense is 2.
 
-          This is purely to save memory - each supported CPU adds
-          approximately eight kilobytes to the kernel image.
+          This is purely to save memory: each supported CPU adds about 8KB
+          to the kernel image.
 
 config SCHED_SMT
         bool "SMT (Hyperthreading) scheduler support"
@@ -1363,7 +1405,7 @@ config HIGHMEM4G
 
 config HIGHMEM64G
         bool "64GB"
-        depends on !M486
+        depends on !M486 && !M586 && !M586TSC && !M586MMX && !MGEODE_LX && !MGEODEGX1 && !MCYRIXIII && !MELAN && !MWINCHIPC6 && !WINCHIP3D && !MK6
         select X86_PAE
         ---help---
           Select this if you have a 32-bit processor and more than 4
diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
index 65a9a4716e34..8b8d2297d486 100644
--- a/arch/x86/Kconfig.cpu
+++ b/arch/x86/Kconfig.cpu
@@ -374,7 +374,7 @@ config X86_TSC
 
 config X86_CMPXCHG64
         def_bool y
-        depends on X86_PAE || X86_64 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MATOM
+        depends on X86_PAE || X86_64 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586TSC || M586MMX || MATOM || MGEODE_LX || MGEODEGX1 || MK6 || MK7 || MK8
 
 # this should be set for all -march=.. options where the compiler
 # generates cmov.
@@ -385,7 +385,7 @@ config X86_CMOV
 config X86_MINIMUM_CPU_FAMILY
         int
         default "64" if X86_64
-        default "6" if X86_32 && X86_P6_NOP
+        default "6" if X86_32 && (MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MEFFICEON || MATOM || MCRUSOE || MCORE2 || MK7 || MK8)
         default "5" if X86_32 && X86_CMPXCHG64
         default "4"
 
diff --git a/arch/x86/Makefile b/arch/x86/Makefile
index fad55160dcb9..498c1b812300 100644
--- a/arch/x86/Makefile
+++ b/arch/x86/Makefile
@@ -232,10 +232,9 @@ KBUILD_CFLAGS += -fno-asynchronous-unwind-tables
 
 # Avoid indirect branches in kernel to deal with Spectre
 ifdef CONFIG_RETPOLINE
-    RETPOLINE_CFLAGS += $(call cc-option,-mindirect-branch=thunk-extern -mindirect-branch-register)
-    ifneq ($(RETPOLINE_CFLAGS),)
-        KBUILD_CFLAGS += $(RETPOLINE_CFLAGS) -DRETPOLINE
-    endif
+ifneq ($(RETPOLINE_CFLAGS),)
+  KBUILD_CFLAGS += $(RETPOLINE_CFLAGS) -DRETPOLINE
+endif
 endif
 
 archscripts: scripts_basic
diff --git a/arch/x86/boot/compressed/eboot.c b/arch/x86/boot/compressed/eboot.c
index 353e20c3f114..886a9115af62 100644
--- a/arch/x86/boot/compressed/eboot.c
+++ b/arch/x86/boot/compressed/eboot.c
@@ -439,7 +439,7 @@ setup_uga32(void **uga_handle, unsigned long size, u32 *width, u32 *height)
         struct efi_uga_draw_protocol *uga = NULL, *first_uga;
         efi_guid_t uga_proto = EFI_UGA_PROTOCOL_GUID;
         unsigned long nr_ugas;
-        u32 *handles = (u32 *)uga_handle;;
+        u32 *handles = (u32 *)uga_handle;
         efi_status_t status = EFI_INVALID_PARAMETER;
         int i;
 
@@ -484,7 +484,7 @@ setup_uga64(void **uga_handle, unsigned long size, u32 *width, u32 *height)
         struct efi_uga_draw_protocol *uga = NULL, *first_uga;
         efi_guid_t uga_proto = EFI_UGA_PROTOCOL_GUID;
         unsigned long nr_ugas;
-        u64 *handles = (u64 *)uga_handle;;
+        u64 *handles = (u64 *)uga_handle;
         efi_status_t status = EFI_INVALID_PARAMETER;
         int i;
 
diff --git a/arch/x86/crypto/sha512-mb/sha512_mb_mgr_init_avx2.c b/arch/x86/crypto/sha512-mb/sha512_mb_mgr_init_avx2.c
index 36870b26067a..d08805032f01 100644
--- a/arch/x86/crypto/sha512-mb/sha512_mb_mgr_init_avx2.c
+++ b/arch/x86/crypto/sha512-mb/sha512_mb_mgr_init_avx2.c
@@ -57,10 +57,12 @@ void sha512_mb_mgr_init_avx2(struct sha512_mb_mgr *state)
 {
         unsigned int j;
 
-        state->lens[0] = 0;
-        state->lens[1] = 1;
-        state->lens[2] = 2;
-        state->lens[3] = 3;
+        /* initially all lanes are unused */
+        state->lens[0] = 0xFFFFFFFF00000000;
+        state->lens[1] = 0xFFFFFFFF00000001;
+        state->lens[2] = 0xFFFFFFFF00000002;
+        state->lens[3] = 0xFFFFFFFF00000003;
+
         state->unused_lanes = 0xFF03020100;
         for (j = 0; j < 4; j++)
                 state->ldata[j].job_in_lane = NULL;
diff --git a/arch/x86/entry/calling.h b/arch/x86/entry/calling.h
index 3f48f695d5e6..be63330c5511 100644
--- a/arch/x86/entry/calling.h
+++ b/arch/x86/entry/calling.h
@@ -97,80 +97,78 @@ For 32-bit we have the following conventions - kernel is built with
 
 #define SIZEOF_PTREGS   21*8
 
-        .macro ALLOC_PT_GPREGS_ON_STACK
-        addq    $-(15*8), %rsp
-        .endm
-
-        .macro SAVE_C_REGS_HELPER offset=0 rax=1 rcx=1 r8910=1 r11=1
-        .if \r11
-        movq %r11, 6*8+\offset(%rsp)
-        .endif
-        .if \r8910
-        movq %r10, 7*8+\offset(%rsp)
-        movq %r9,  8*8+\offset(%rsp)
-        movq %r8,  9*8+\offset(%rsp)
-        .endif
-        .if \rax
-        movq %rax, 10*8+\offset(%rsp)
+.macro PUSH_AND_CLEAR_REGS rdx=%rdx rax=%rax save_ret=0
+        /*
+         * Push registers and sanitize registers of values that a
+         * speculation attack might otherwise want to exploit. The
+         * lower registers are likely clobbered well before they
+         * could be put to use in a speculative execution gadget.
+         * Interleave XOR with PUSH for better uop scheduling:
+         */
+        .if \save_ret
+        pushq   %rsi            /* pt_regs->si */
+        movq    8(%rsp), %rsi   /* temporarily store the return address in %rsi */
+        movq    %rdi, 8(%rsp)   /* pt_regs->di (overwriting original return address) */
+        .else
+        pushq   %rdi            /* pt_regs->di */
+        pushq   %rsi            /* pt_regs->si */
         .endif
-        .if \rcx
-        movq %rcx, 11*8+\offset(%rsp)
+        pushq   \rdx            /* pt_regs->dx */
+        pushq   %rcx            /* pt_regs->cx */
+        pushq   \rax            /* pt_regs->ax */
+        pushq   %r8             /* pt_regs->r8 */
+        xorl    %r8d, %r8d      /* nospec   r8 */
+        pushq   %r9             /* pt_regs->r9 */
+        xorl    %r9d, %r9d      /* nospec   r9 */
+        pushq   %r10            /* pt_regs->r10 */
+        xorl    %r10d, %r10d    /* nospec   r10 */
+        pushq   %r11            /* pt_regs->r11 */
+        xorl    %r11d, %r11d    /* nospec   r11*/
+        pushq   %rbx            /* pt_regs->rbx */
+        xorl    %ebx, %ebx      /* nospec   rbx*/
+        pushq   %rbp            /* pt_regs->rbp */
+        xorl    %ebp, %ebp      /* nospec   rbp*/
+        pushq   %r12            /* pt_regs->r12 */
+        xorl    %r12d, %r12d    /* nospec   r12*/
+        pushq   %r13            /* pt_regs->r13 */
+        xorl    %r13d, %r13d    /* nospec   r13*/
+        pushq   %r14            /* pt_regs->r14 */
+        xorl    %r14d, %r14d    /* nospec   r14*/
+        pushq   %r15            /* pt_regs->r15 */
+        xorl    %r15d, %r15d    /* nospec   r15*/
+        UNWIND_HINT_REGS
+        .if \save_ret
+        pushq   %rsi            /* return address on top of stack */
         .endif
-        movq %rdx, 12*8+\offset(%rsp)
-        movq %rsi, 13*8+\offset(%rsp)
-        movq %rdi, 14*8+\offset(%rsp)
-        UNWIND_HINT_REGS offset=\offset extra=0
-        .endm
-        .macro SAVE_C_REGS offset=0
-        SAVE_C_REGS_HELPER \offset, 1, 1, 1, 1
-        .endm
-        .macro SAVE_C_REGS_EXCEPT_RAX_RCX offset=0
-        SAVE_C_REGS_HELPER \offset, 0, 0, 1, 1
-        .endm
-        .macro SAVE_C_REGS_EXCEPT_R891011
-        SAVE_C_REGS_HELPER 0, 1, 1, 0, 0
-        .endm
-        .macro SAVE_C_REGS_EXCEPT_RCX_R891011
-        SAVE_C_REGS_HELPER 0, 1, 0, 0, 0
-        .endm
-        .macro SAVE_C_REGS_EXCEPT_RAX_RCX_R11
-        SAVE_C_REGS_HELPER 0, 0, 0, 1, 0
-        .endm
-
-        .macro SAVE_EXTRA_REGS offset=0
-        movq %r15, 0*8+\offset(%rsp)
-        movq %r14, 1*8+\offset(%rsp)
-        movq %r13, 2*8+\offset(%rsp)
-        movq %r12, 3*8+\offset(%rsp)
-        movq %rbp, 4*8+\offset(%rsp)
-        movq %rbx, 5*8+\offset(%rsp)
-        UNWIND_HINT_REGS offset=\offset
-        .endm
-
-        .macro POP_EXTRA_REGS
+.endm
+
+.macro POP_REGS pop_rdi=1 skip_r11rcx=0
         popq %r15
         popq %r14
         popq %r13
         popq %r12
         popq %rbp
         popq %rbx
-        .endm
-
-        .macro POP_C_REGS
+        .if \skip_r11rcx
+        popq %rsi
+        .else
         popq %r11
+        .endif
         popq %r10
         popq %r9
         popq %r8
         popq %rax
+        .if \skip_r11rcx
+        popq %rsi
+        .else
         popq %rcx
+        .endif
         popq %rdx
         popq %rsi
+        .if \pop_rdi
         popq %rdi
-        .endm
-
-        .macro icebp
-        .byte 0xf1
-        .endm
+        .endif
+.endm
 
 /*
  * This is a sneaky trick to help the unwinder find pt_regs on the stack.  The
@@ -178,17 +176,12 @@ For 32-bit we have the following conventions - kernel is built with
  * is just setting the LSB, which makes it an invalid stack address and is also
  * a signal to the unwinder that it's a pt_regs pointer in disguise.
  *
- * NOTE: This macro must be used *after* SAVE_EXTRA_REGS because it corrupts
+ * NOTE: This macro must be used *after* PUSH_AND_CLEAR_REGS because it corrupts
  * the original rbp.
  */
 .macro ENCODE_FRAME_POINTER ptregs_offset=0
 #ifdef CONFIG_FRAME_POINTER
-        .if \ptregs_offset
-                leaq \ptregs_offset(%rsp), %rbp
-        .else
-                mov %rsp, %rbp
-        .endif
-        orq     $0x1, %rbp
+        leaq 1+\ptregs_offset(%rsp), %rbp
 #endif
 .endm
 
diff --git a/arch/x86/entry/entry_32.S b/arch/x86/entry/entry_32.S
index 16c2c022540d..6ad064c8cf35 100644
--- a/arch/x86/entry/entry_32.S
+++ b/arch/x86/entry/entry_32.S
@@ -252,8 +252,7 @@ ENTRY(__switch_to_asm)
          * exist, overwrite the RSB with entries which capture
          * speculative execution to prevent attack.
          */
-        /* Clobbers %ebx */
-        FILL_RETURN_BUFFER RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW
+        FILL_RETURN_BUFFER %ebx, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW
 #endif
 
         /* restore callee-saved registers */
diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S
index 30c8c5344c4a..805f52703ee3 100644
--- a/arch/x86/entry/entry_64.S
+++ b/arch/x86/entry/entry_64.S
@@ -55,7 +55,7 @@ END(native_usergs_sysret64)
 
 .macro TRACE_IRQS_FLAGS flags:req
 #ifdef CONFIG_TRACE_IRQFLAGS
-        bt      $9, \flags              /* interrupts off? */
+        btl     $9, \flags              /* interrupts off? */
         jnc     1f
         TRACE_IRQS_ON
 1:
@@ -213,7 +213,7 @@ ENTRY(entry_SYSCALL_64)
 
         swapgs
         /*
-         * This path is not taken when PAGE_TABLE_ISOLATION is disabled so it
+         * This path is only taken when PAGE_TABLE_ISOLATION is disabled so it
          * is not required to switch CR3.
          */
         movq    %rsp, PER_CPU_VAR(rsp_scratch)
@@ -227,22 +227,8 @@ ENTRY(entry_SYSCALL_64)
         pushq   %rcx                            /* pt_regs->ip */
 GLOBAL(entry_SYSCALL_64_after_hwframe)
         pushq   %rax                            /* pt_regs->orig_ax */
-        pushq   %rdi                            /* pt_regs->di */
-        pushq   %rsi                            /* pt_regs->si */
-        pushq   %rdx                            /* pt_regs->dx */
-        pushq   %rcx                            /* pt_regs->cx */
-        pushq   $-ENOSYS                        /* pt_regs->ax */
-        pushq   %r8                             /* pt_regs->r8 */
-        pushq   %r9                             /* pt_regs->r9 */
-        pushq   %r10                            /* pt_regs->r10 */
-        pushq   %r11                            /* pt_regs->r11 */
-        pushq   %rbx                            /* pt_regs->rbx */
-        pushq   %rbp                            /* pt_regs->rbp */
-        pushq   %r12                            /* pt_regs->r12 */
-        pushq   %r13                            /* pt_regs->r13 */
-        pushq   %r14                            /* pt_regs->r14 */
-        pushq   %r15                            /* pt_regs->r15 */
-        UNWIND_HINT_REGS
+
+        PUSH_AND_CLEAR_REGS rax=$-ENOSYS
 
         TRACE_IRQS_OFF
 
@@ -321,15 +307,7 @@ GLOBAL(entry_SYSCALL_64_after_hwframe)
 syscall_return_via_sysret:
         /* rcx and r11 are already restored (see code above) */
         UNWIND_HINT_EMPTY
-        POP_EXTRA_REGS
-        popq    %rsi    /* skip r11 */
-        popq    %r10
-        popq    %r9
-        popq    %r8
-        popq    %rax
-        popq    %rsi    /* skip rcx */
-        popq    %rdx
-        popq    %rsi
+        POP_REGS pop_rdi=0 skip_r11rcx=1
 
         /*
          * Now all regs are restored except RSP and RDI.
@@ -386,8 +364,7 @@ ENTRY(__switch_to_asm)
          * exist, overwrite the RSB with entries which capture
          * speculative execution to prevent attack.
          */
-        /* Clobbers %rbx */
-        FILL_RETURN_BUFFER RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW
+        FILL_RETURN_BUFFER %r12, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW
 #endif
 
         /* restore callee-saved registers */
@@ -471,9 +448,19 @@ END(irq_entries_start)
  *
  * The invariant is that, if irq_count != -1, then the IRQ stack is in use.
  */
-.macro ENTER_IRQ_STACK regs=1 old_rsp
+.macro ENTER_IRQ_STACK regs=1 old_rsp save_ret=0
         DEBUG_ENTRY_ASSERT_IRQS_OFF
+
+        .if \save_ret
+        /*
+         * If save_ret is set, the original stack contains one additional
+         * entry -- the return address. Therefore, move the address one
+         * entry below %rsp to \old_rsp.
+         */
+        leaq    8(%rsp), \old_rsp
+        .else
         movq    %rsp, \old_rsp
+        .endif
 
         .if \regs
         UNWIND_HINT_REGS base=\old_rsp
@@ -519,6 +506,15 @@ END(irq_entries_start)
         .if \regs
         UNWIND_HINT_REGS indirect=1
         .endif
+
+        .if \save_ret
+        /*
+         * Push the return address to the stack. This return address can
+         * be found at the "real" original RSP, which was offset by 8 at
+         * the beginning of this macro.
+         */
+        pushq   -8(\old_rsp)
+        .endif
 .endm
 
 /*
@@ -542,29 +538,65 @@ END(irq_entries_start)
 .endm
 
 /*
- * Interrupt entry/exit.
- *
- * Interrupt entry points save only callee clobbered registers in fast path.
+ * Interrupt entry helper function.
  *
- * Entry runs with interrupts off.
+ * Entry runs with interrupts off. Stack layout at entry:
+ * +----------------------------------------------------+
+ * | regs->ss                                           |
+ * | regs->rsp                                          |
+ * | regs->eflags                                       |
+ * | regs->cs                                           |
+ * | regs->ip                                           |
+ * +----------------------------------------------------+
+ * | regs->orig_ax = ~(interrupt number)                |
+ * +----------------------------------------------------+
+ * | return address                                     |
+ * +----------------------------------------------------+
  */
-
-/* 0(%rsp): ~(interrupt number) */
-        .macro interrupt func
+ENTRY(interrupt_entry)
+        UNWIND_HINT_FUNC
+        ASM_CLAC
         cld
 
-        testb   $3, CS-ORIG_RAX(%rsp)
+        testb   $3, CS-ORIG_RAX+8(%rsp)
         jz      1f
         SWAPGS
-        call    switch_to_thread_stack
+
+        /*
+         * Switch to the thread stack. The IRET frame and orig_ax are
+         * on the stack, as well as the return address. RDI..R12 are
+         * not (yet) on the stack and space has not (yet) been
+         * allocated for them.
+         */
+        pushq   %rdi
+
+        /* Need to switch before accessing the thread stack. */
+        SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi
+        movq    %rsp, %rdi
+        movq    PER_CPU_VAR(cpu_current_top_of_stack), %rsp
+
+         /*
+          * We have RDI, return address, and orig_ax on the stack on
+          * top of the IRET frame. That means offset=24
+          */
+        UNWIND_HINT_IRET_REGS base=%rdi offset=24
+
+        pushq   7*8(%rdi)               /* regs->ss */
+        pushq   6*8(%rdi)               /* regs->rsp */
+        pushq   5*8(%rdi)               /* regs->eflags */
+        pushq   4*8(%rdi)               /* regs->cs */
+        pushq   3*8(%rdi)               /* regs->ip */
+        pushq   2*8(%rdi)               /* regs->orig_ax */
+        pushq   8(%rdi)                 /* return address */
+        UNWIND_HINT_FUNC
+
+        movq    (%rdi), %rdi
 1:
 
-        ALLOC_PT_GPREGS_ON_STACK
-        SAVE_C_REGS
-        SAVE_EXTRA_REGS
-        ENCODE_FRAME_POINTER
+        PUSH_AND_CLEAR_REGS save_ret=1
+        ENCODE_FRAME_POINTER 8
 
-        testb   $3, CS(%rsp)
+        testb   $3, CS+8(%rsp)
         jz      1f
 
         /*
@@ -572,7 +604,7 @@ END(irq_entries_start)
          *
          * We need to tell lockdep that IRQs are off.  We can't do this until
          * we fix gsbase, and we should do it before enter_from_user_mode
-         * (which can take locks).  Since TRACE_IRQS_OFF idempotent,
+         * (which can take locks).  Since TRACE_IRQS_OFF is idempotent,
          * the simplest way to handle it is to just call it twice if
          * we enter from user mode.  There's no reason to optimize this since
          * TRACE_IRQS_OFF is a no-op if lockdep is off.
@@ -582,12 +614,15 @@ END(irq_entries_start)
         CALL_enter_from_user_mode
 
 1:
-        ENTER_IRQ_STACK old_rsp=%rdi
+        ENTER_IRQ_STACK old_rsp=%rdi save_ret=1
         /* We entered an interrupt context - irqs are off: */
         TRACE_IRQS_OFF
 
-        call    \func   /* rdi points to pt_regs */
-        .endm
+        ret
+END(interrupt_entry)
+
+
+/* Interrupt entry/exit. */
 
         /*
          * The interrupt stubs push (~vector+0x80) onto the stack and
@@ -595,9 +630,10 @@ END(irq_entries_start)
          */
         .p2align CONFIG_X86_L1_CACHE_SHIFT
 common_interrupt:
-        ASM_CLAC
         addq    $-0x80, (%rsp)                  /* Adjust vector to [-256, -1] range */
-        interrupt do_IRQ
+        call    interrupt_entry
+        UNWIND_HINT_REGS indirect=1
+        call    do_IRQ  /* rdi points to pt_regs */
         /* 0(%rsp): old RSP */
 ret_from_intr:
         DISABLE_INTERRUPTS(CLBR_ANY)
@@ -622,15 +658,7 @@ GLOBAL(swapgs_restore_regs_and_return_to_usermode)
         ud2
 1:
 #endif
-        POP_EXTRA_REGS
-        popq    %r11
-        popq    %r10
-        popq    %r9
-        popq    %r8
-        popq    %rax
-        popq    %rcx
-        popq    %rdx
-        popq    %rsi
+        POP_REGS pop_rdi=0
 
         /*
          * The stack is now user RDI, orig_ax, RIP, CS, EFLAGS, RSP, SS.
@@ -688,8 +716,7 @@ GLOBAL(restore_regs_and_return_to_kernel)
         ud2
 1:
 #endif
-        POP_EXTRA_REGS
-        POP_C_REGS
+        POP_REGS
         addq    $8, %rsp        /* skip regs->orig_ax */
         /*
          * ARCH_HAS_MEMBARRIER_SYNC_CORE rely on IRET core serialization
@@ -799,10 +826,11 @@ END(common_interrupt)
 .macro apicinterrupt3 num sym do_sym
 ENTRY(\sym)
         UNWIND_HINT_IRET_REGS
-        ASM_CLAC
         pushq   $~(\num)
 .Lcommon_\sym:
-        interrupt \do_sym
+        call    interrupt_entry
+        UNWIND_HINT_REGS indirect=1
+        call    \do_sym /* rdi points to pt_regs */
         jmp     ret_from_intr
 END(\sym)
 .endm
@@ -865,34 +893,6 @@ apicinterrupt IRQ_WORK_VECTOR			irq_work_interrupt		smp_irq_work_interrupt
  */
 #define CPU_TSS_IST(x) PER_CPU_VAR(cpu_tss_rw) + (TSS_ist + ((x) - 1) * 8)
 
-/*
- * Switch to the thread stack.  This is called with the IRET frame and
- * orig_ax on the stack.  (That is, RDI..R12 are not on the stack and
- * space has not been allocated for them.)
- */
-ENTRY(switch_to_thread_stack)
-        UNWIND_HINT_FUNC
-
-        pushq   %rdi
-        /* Need to switch before accessing the thread stack. */
-        SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi
-        movq    %rsp, %rdi
-        movq    PER_CPU_VAR(cpu_current_top_of_stack), %rsp
-        UNWIND_HINT sp_offset=16 sp_reg=ORC_REG_DI
-
-        pushq   7*8(%rdi)               /* regs->ss */
-        pushq   6*8(%rdi)               /* regs->rsp */
-        pushq   5*8(%rdi)               /* regs->eflags */
-        pushq   4*8(%rdi)               /* regs->cs */
-        pushq   3*8(%rdi)               /* regs->ip */
-        pushq   2*8(%rdi)               /* regs->orig_ax */
-        pushq   8(%rdi)                 /* return address */
-        UNWIND_HINT_FUNC
-
-        movq    (%rdi), %rdi
-        ret
-END(switch_to_thread_stack)
-
 .macro idtentry sym do_sym has_error_code:req paranoid=0 shift_ist=-1
 ENTRY(\sym)
         UNWIND_HINT_IRET_REGS offset=\has_error_code*8
@@ -908,10 +908,8 @@ ENTRY(\sym)
         pushq   $-1                             /* ORIG_RAX: no syscall to restart */
         .endif
 
-        ALLOC_PT_GPREGS_ON_STACK
-
         .if \paranoid < 2
-        testb   $3, CS(%rsp)                    /* If coming from userspace, switch stacks */
+        testb   $3, CS-ORIG_RAX(%rsp)           /* If coming from userspace, switch stacks */
         jnz     .Lfrom_usermode_switch_stack_\@
         .endif
 
@@ -1121,9 +1119,7 @@ ENTRY(xen_failsafe_callback)
         addq    $0x30, %rsp
         UNWIND_HINT_IRET_REGS
         pushq   $-1 /* orig_ax = -1 => not a system call */
-        ALLOC_PT_GPREGS_ON_STACK
-        SAVE_C_REGS
-        SAVE_EXTRA_REGS
+        PUSH_AND_CLEAR_REGS
         ENCODE_FRAME_POINTER
         jmp     error_exit
 END(xen_failsafe_callback)
@@ -1170,8 +1166,7 @@ idtentry machine_check		do_mce			has_error_code=0	paranoid=1
 ENTRY(paranoid_entry)
         UNWIND_HINT_FUNC
         cld
-        SAVE_C_REGS 8
-        SAVE_EXTRA_REGS 8
+        PUSH_AND_CLEAR_REGS save_ret=1
         ENCODE_FRAME_POINTER 8
         movl    $1, %ebx
         movl    $MSR_GS_BASE, %ecx
@@ -1211,21 +1206,20 @@ ENTRY(paranoid_exit)
         jmp     .Lparanoid_exit_restore
 .Lparanoid_exit_no_swapgs:
         TRACE_IRQS_IRETQ_DEBUG
+        RESTORE_CR3     scratch_reg=%rbx save_reg=%r14
 .Lparanoid_exit_restore:
         jmp restore_regs_and_return_to_kernel
 END(paranoid_exit)
 
 /*
- * Save all registers in pt_regs, and switch gs if needed.
+ * Save all registers in pt_regs, and switch GS if needed.
  * Return: EBX=0: came from user mode; EBX=1: otherwise
  */
 ENTRY(error_entry)
         UNWIND_HINT_FUNC
         cld
-        SAVE_C_REGS 8
-        SAVE_EXTRA_REGS 8
+        PUSH_AND_CLEAR_REGS save_ret=1
         ENCODE_FRAME_POINTER 8
-        xorl    %ebx, %ebx
         testb   $3, CS+8(%rsp)
         jz      .Lerror_kernelspace
 
@@ -1406,22 +1400,7 @@ ENTRY(nmi)
         pushq   1*8(%rdx)       /* pt_regs->rip */
         UNWIND_HINT_IRET_REGS
         pushq   $-1             /* pt_regs->orig_ax */
-        pushq   %rdi            /* pt_regs->di */
-        pushq   %rsi            /* pt_regs->si */
-        pushq   (%rdx)          /* pt_regs->dx */
-        pushq   %rcx            /* pt_regs->cx */
-        pushq   %rax            /* pt_regs->ax */
-        pushq   %r8             /* pt_regs->r8 */
-        pushq   %r9             /* pt_regs->r9 */
-        pushq   %r10            /* pt_regs->r10 */
-        pushq   %r11            /* pt_regs->r11 */
-        pushq   %rbx            /* pt_regs->rbx */
-        pushq   %rbp            /* pt_regs->rbp */
-        pushq   %r12            /* pt_regs->r12 */
-        pushq   %r13            /* pt_regs->r13 */
-        pushq   %r14            /* pt_regs->r14 */
-        pushq   %r15            /* pt_regs->r15 */
-        UNWIND_HINT_REGS
+        PUSH_AND_CLEAR_REGS rdx=(%rdx)
         ENCODE_FRAME_POINTER
 
         /*
@@ -1631,7 +1610,6 @@ end_repeat_nmi:
          * frame to point back to repeat_nmi.
          */
         pushq   $-1                             /* ORIG_RAX: no syscall to restart */
-        ALLOC_PT_GPREGS_ON_STACK
 
         /*
          * Use paranoid_entry to handle SWAPGS, but no need to use paranoid_exit
@@ -1655,8 +1633,7 @@ end_repeat_nmi:
 nmi_swapgs:
         SWAPGS_UNSAFE_STACK
 nmi_restore:
-        POP_EXTRA_REGS
-        POP_C_REGS
+        POP_REGS
 
         /*
          * Skip orig_ax and the "outermost" frame to point RSP at the "iret"
diff --git a/arch/x86/entry/entry_64_compat.S b/arch/x86/entry/entry_64_compat.S
index 98d5358e4041..e811dd9c5e99 100644
--- a/arch/x86/entry/entry_64_compat.S
+++ b/arch/x86/entry/entry_64_compat.S
@@ -85,15 +85,25 @@ ENTRY(entry_SYSENTER_compat)
         pushq   %rcx                    /* pt_regs->cx */
         pushq   $-ENOSYS                /* pt_regs->ax */
         pushq   $0                      /* pt_regs->r8  = 0 */
+        xorl    %r8d, %r8d              /* nospec   r8 */
         pushq   $0                      /* pt_regs->r9  = 0 */
+        xorl    %r9d, %r9d              /* nospec   r9 */
         pushq   $0                      /* pt_regs->r10 = 0 */
+        xorl    %r10d, %r10d            /* nospec   r10 */
         pushq   $0                      /* pt_regs->r11 = 0 */
+        xorl    %r11d, %r11d            /* nospec   r11 */
         pushq   %rbx                    /* pt_regs->rbx */
+        xorl    %ebx, %ebx              /* nospec   rbx */
         pushq   %rbp                    /* pt_regs->rbp (will be overwritten) */
+        xorl    %ebp, %ebp              /* nospec   rbp */
         pushq   $0                      /* pt_regs->r12 = 0 */
+        xorl    %r12d, %r12d            /* nospec   r12 */
         pushq   $0                      /* pt_regs->r13 = 0 */
+        xorl    %r13d, %r13d            /* nospec   r13 */
         pushq   $0                      /* pt_regs->r14 = 0 */
+        xorl    %r14d, %r14d            /* nospec   r14 */
         pushq   $0                      /* pt_regs->r15 = 0 */
+        xorl    %r15d, %r15d            /* nospec   r15 */
         cld
 
         /*
@@ -214,15 +224,25 @@ GLOBAL(entry_SYSCALL_compat_after_hwframe)
         pushq   %rbp                    /* pt_regs->cx (stashed in bp) */
         pushq   $-ENOSYS                /* pt_regs->ax */
         pushq   $0                      /* pt_regs->r8  = 0 */
+        xorl    %r8d, %r8d              /* nospec   r8 */
         pushq   $0                      /* pt_regs->r9  = 0 */
+        xorl    %r9d, %r9d              /* nospec   r9 */
         pushq   $0                      /* pt_regs->r10 = 0 */
+        xorl    %r10d, %r10d            /* nospec   r10 */
         pushq   $0                      /* pt_regs->r11 = 0 */
+        xorl    %r11d, %r11d            /* nospec   r11 */
         pushq   %rbx                    /* pt_regs->rbx */
+        xorl    %ebx, %ebx              /* nospec   rbx */
         pushq   %rbp                    /* pt_regs->rbp (will be overwritten) */
+        xorl    %ebp, %ebp              /* nospec   rbp */
         pushq   $0                      /* pt_regs->r12 = 0 */
+        xorl    %r12d, %r12d            /* nospec   r12 */
         pushq   $0                      /* pt_regs->r13 = 0 */
+        xorl    %r13d, %r13d            /* nospec   r13 */
         pushq   $0                      /* pt_regs->r14 = 0 */
+        xorl    %r14d, %r14d            /* nospec   r14 */
         pushq   $0                      /* pt_regs->r15 = 0 */
+        xorl    %r15d, %r15d            /* nospec   r15 */
 
         /*
          * User mode is traced as though IRQs are on, and SYSENTER
@@ -278,9 +298,9 @@ sysret32_from_system_call:
          */
         SWITCH_TO_USER_CR3_NOSTACK scratch_reg=%r8 scratch_reg2=%r9
 
-        xorq    %r8, %r8
-        xorq    %r9, %r9
-        xorq    %r10, %r10
+        xorl    %r8d, %r8d
+        xorl    %r9d, %r9d
+        xorl    %r10d, %r10d
         swapgs
         sysretl
 END(entry_SYSCALL_compat)
@@ -327,10 +347,23 @@ ENTRY(entry_INT80_compat)
          */
         movl    %eax, %eax
 
+        /* switch to thread stack expects orig_ax and rdi to be pushed */
         pushq   %rax                    /* pt_regs->orig_ax */
+        pushq   %rdi                    /* pt_regs->di */
+
+        /* Need to switch before accessing the thread stack. */
+        SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi
+        movq    %rsp, %rdi
+        movq    PER_CPU_VAR(cpu_current_top_of_stack), %rsp
+
+        pushq   6*8(%rdi)               /* regs->ss */
+        pushq   5*8(%rdi)               /* regs->rsp */
+        pushq   4*8(%rdi)               /* regs->eflags */
+        pushq   3*8(%rdi)               /* regs->cs */
+        pushq   2*8(%rdi)               /* regs->ip */
+        pushq   1*8(%rdi)               /* regs->orig_ax */
 
-        /* switch to thread stack expects orig_ax to be pushed */
-        call    switch_to_thread_stack
+        movq    (%rdi), %rdi            /* restore %rdi */
 
         pushq   %rdi                    /* pt_regs->di */
         pushq   %rsi                    /* pt_regs->si */
@@ -338,15 +371,25 @@ ENTRY(entry_INT80_compat)
         pushq   %rcx                    /* pt_regs->cx */
         pushq   $-ENOSYS                /* pt_regs->ax */
         pushq   $0                      /* pt_regs->r8  = 0 */
+        xorl    %r8d, %r8d              /* nospec   r8 */
         pushq   $0                      /* pt_regs->r9  = 0 */
+        xorl    %r9d, %r9d              /* nospec   r9 */
         pushq   $0                      /* pt_regs->r10 = 0 */
+        xorl    %r10d, %r10d            /* nospec   r10 */
         pushq   $0                      /* pt_regs->r11 = 0 */
+        xorl    %r11d, %r11d            /* nospec   r11 */
         pushq   %rbx                    /* pt_regs->rbx */
+        xorl    %ebx, %ebx              /* nospec   rbx */
         pushq   %rbp                    /* pt_regs->rbp */
+        xorl    %ebp, %ebp              /* nospec   rbp */
         pushq   %r12                    /* pt_regs->r12 */
+        xorl    %r12d, %r12d            /* nospec   r12 */
         pushq   %r13                    /* pt_regs->r13 */
+        xorl    %r13d, %r13d            /* nospec   r13 */
         pushq   %r14                    /* pt_regs->r14 */
+        xorl    %r14d, %r14d            /* nospec   r14 */
         pushq   %r15                    /* pt_regs->r15 */
+        xorl    %r15d, %r15d            /* nospec   r15 */
         cld
 
         /*
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 731153a4681e..56457cb73448 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3559,7 +3559,7 @@ static int intel_snb_pebs_broken(int cpu)
                 break;
 
         case INTEL_FAM6_SANDYBRIDGE_X:
-                switch (cpu_data(cpu).x86_mask) {
+                switch (cpu_data(cpu).x86_stepping) {
                 case 6: rev = 0x618; break;
                 case 7: rev = 0x70c; break;
                 }
diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
index ae64d0b69729..cf372b90557e 100644
--- a/arch/x86/events/intel/lbr.c
+++ b/arch/x86/events/intel/lbr.c
@@ -1186,7 +1186,7 @@ void __init intel_pmu_lbr_init_atom(void)
          * on PMU interrupt
          */
         if (boot_cpu_data.x86_model == 28
-            && boot_cpu_data.x86_mask < 10) {
+            && boot_cpu_data.x86_stepping < 10) {
                 pr_cont("LBR disabled due to erratum");
                 return;
         }
diff --git a/arch/x86/events/intel/p6.c b/arch/x86/events/intel/p6.c
index a5604c352930..408879b0c0d4 100644
--- a/arch/x86/events/intel/p6.c
+++ b/arch/x86/events/intel/p6.c
@@ -234,7 +234,7 @@ static __initconst const struct x86_pmu p6_pmu = {
 
 static __init void p6_pmu_rdpmc_quirk(void)
 {
-        if (boot_cpu_data.x86_mask < 9) {
+        if (boot_cpu_data.x86_stepping < 9) {
                 /*
                  * PPro erratum 26; fixed in stepping 9 and above.
                  */
diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h
index 44f5d79d5105..11881726ed37 100644
--- a/arch/x86/include/asm/acpi.h
+++ b/arch/x86/include/asm/acpi.h
@@ -94,7 +94,7 @@ static inline unsigned int acpi_processor_cstate_check(unsigned int max_cstate)
         if (boot_cpu_data.x86 == 0x0F &&
             boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
             boot_cpu_data.x86_model <= 0x05 &&
-            boot_cpu_data.x86_mask < 0x0A)
+            boot_cpu_data.x86_stepping < 0x0A)
                 return 1;
         else if (boot_cpu_has(X86_BUG_AMD_APIC_C1E))
                 return 1;
diff --git a/arch/x86/include/asm/apm.h b/arch/x86/include/asm/apm.h
index 4d4015ddcf26..c356098b6fb9 100644
--- a/arch/x86/include/asm/apm.h
+++ b/arch/x86/include/asm/apm.h
@@ -7,6 +7,8 @@
 #ifndef _ASM_X86_MACH_DEFAULT_APM_H
 #define _ASM_X86_MACH_DEFAULT_APM_H
 
+#include <asm/nospec-branch.h>
+
 #ifdef APM_ZERO_SEGS
 #       define APM_DO_ZERO_SEGS \
                 "pushl %%ds\n\t" \
@@ -32,6 +34,7 @@ static inline void apm_bios_call_asm(u32 func, u32 ebx_in, u32 ecx_in,
          * N.B. We do NOT need a cld after the BIOS call
          * because we always save and restore the flags.
          */
+        firmware_restrict_branch_speculation_start();
         __asm__ __volatile__(APM_DO_ZERO_SEGS
                 "pushl %%edi\n\t"
                 "pushl %%ebp\n\t"
@@ -44,6 +47,7 @@ static inline void apm_bios_call_asm(u32 func, u32 ebx_in, u32 ecx_in,
                   "=S" (*esi)
                 : "a" (func), "b" (ebx_in), "c" (ecx_in)
                 : "memory", "cc");
+        firmware_restrict_branch_speculation_end();
 }
 
 static inline bool apm_bios_call_simple_asm(u32 func, u32 ebx_in,
@@ -56,6 +60,7 @@ static inline bool apm_bios_call_simple_asm(u32 func, u32 ebx_in,
          * N.B. We do NOT need a cld after the BIOS call
          * because we always save and restore the flags.
          */
+        firmware_restrict_branch_speculation_start();
         __asm__ __volatile__(APM_DO_ZERO_SEGS
                 "pushl %%edi\n\t"
                 "pushl %%ebp\n\t"
@@ -68,6 +73,7 @@ static inline bool apm_bios_call_simple_asm(u32 func, u32 ebx_in,
                   "=S" (si)
                 : "a" (func), "b" (ebx_in), "c" (ecx_in)
                 : "memory", "cc");
+        firmware_restrict_branch_speculation_end();
         return error;
 }
 
diff --git a/arch/x86/include/asm/asm-prototypes.h b/arch/x86/include/asm/asm-prototypes.h
index 4d111616524b..1908214b9125 100644
--- a/arch/x86/include/asm/asm-prototypes.h
+++ b/arch/x86/include/asm/asm-prototypes.h
@@ -38,7 +38,4 @@ INDIRECT_THUNK(dx)
 INDIRECT_THUNK(si)
 INDIRECT_THUNK(di)
 INDIRECT_THUNK(bp)
-asmlinkage void __fill_rsb(void);
-asmlinkage void __clear_rsb(void);
-
 #endif /* CONFIG_RETPOLINE */
diff --git a/arch/x86/include/asm/barrier.h b/arch/x86/include/asm/barrier.h
index 30d406146016..e1259f043ae9 100644
--- a/arch/x86/include/asm/barrier.h
+++ b/arch/x86/include/asm/barrier.h
@@ -40,7 +40,7 @@ static inline unsigned long array_index_mask_nospec(unsigned long index,
 
         asm ("cmp %1,%2; sbb %0,%0;"
                         :"=r" (mask)
-                        :"r"(size),"r" (index)
+                        :"g"(size),"r" (index)
                         :"cc");
         return mask;
 }
diff --git a/arch/x86/include/asm/bitops.h b/arch/x86/include/asm/bitops.h
index 3fa039855b8f..9f645ba57dbb 100644
--- a/arch/x86/include/asm/bitops.h
+++ b/arch/x86/include/asm/bitops.h
@@ -78,7 +78,7 @@ set_bit(long nr, volatile unsigned long *addr)
                         : "iq" ((u8)CONST_MASK(nr))
                         : "memory");
         } else {
-                asm volatile(LOCK_PREFIX "bts %1,%0"
+                asm volatile(LOCK_PREFIX __ASM_SIZE(bts) " %1,%0"
                         : BITOP_ADDR(addr) : "Ir" (nr) : "memory");
         }
 }
@@ -94,7 +94,7 @@ set_bit(long nr, volatile unsigned long *addr)
  */
 static __always_inline void __set_bit(long nr, volatile unsigned long *addr)
 {
-        asm volatile("bts %1,%0" : ADDR : "Ir" (nr) : "memory");
+        asm volatile(__ASM_SIZE(bts) " %1,%0" : ADDR : "Ir" (nr) : "memory");
 }
 
 /**
@@ -115,7 +115,7 @@ clear_bit(long nr, volatile unsigned long *addr)
                         : CONST_MASK_ADDR(nr, addr)
                         : "iq" ((u8)~CONST_MASK(nr)));
         } else {
-                asm volatile(LOCK_PREFIX "btr %1,%0"
+                asm volatile(LOCK_PREFIX __ASM_SIZE(btr) " %1,%0"
                         : BITOP_ADDR(addr)
                         : "Ir" (nr));
         }
@@ -137,7 +137,7 @@ static __always_inline void clear_bit_unlock(long nr, volatile unsigned long *ad
 
 static __always_inline void __clear_bit(long nr, volatile unsigned long *addr)
 {
-        asm volatile("btr %1,%0" : ADDR : "Ir" (nr));
+        asm volatile(__ASM_SIZE(btr) " %1,%0" : ADDR : "Ir" (nr));
 }
 
 static __always_inline bool clear_bit_unlock_is_negative_byte(long nr, volatile unsigned long *addr)
@@ -182,7 +182,7 @@ static __always_inline void __clear_bit_unlock(long nr, volatile unsigned long *
  */
 static __always_inline void __change_bit(long nr, volatile unsigned long *addr)
 {
-        asm volatile("btc %1,%0" : ADDR : "Ir" (nr));
+        asm volatile(__ASM_SIZE(btc) " %1,%0" : ADDR : "Ir" (nr));
 }
 
 /**
@@ -201,7 +201,7 @@ static __always_inline void change_bit(long nr, volatile unsigned long *addr)
                         : CONST_MASK_ADDR(nr, addr)
                         : "iq" ((u8)CONST_MASK(nr)));
         } else {
-                asm volatile(LOCK_PREFIX "btc %1,%0"
+                asm volatile(LOCK_PREFIX __ASM_SIZE(btc) " %1,%0"
                         : BITOP_ADDR(addr)
                         : "Ir" (nr));
         }
@@ -217,7 +217,8 @@ static __always_inline void change_bit(long nr, volatile unsigned long *addr)
  */
 static __always_inline bool test_and_set_bit(long nr, volatile unsigned long *addr)
 {
-        GEN_BINARY_RMWcc(LOCK_PREFIX "bts", *addr, "Ir", nr, "%0", c);
+        GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(bts),
+                         *addr, "Ir", nr, "%0", c);
 }
 
 /**
@@ -246,7 +247,7 @@ static __always_inline bool __test_and_set_bit(long nr, volatile unsigned long *
 {
         bool oldbit;
 
-        asm("bts %2,%1"
+        asm(__ASM_SIZE(bts) " %2,%1"
             CC_SET(c)
             : CC_OUT(c) (oldbit), ADDR
             : "Ir" (nr));
@@ -263,7 +264,8 @@ static __always_inline bool __test_and_set_bit(long nr, volatile unsigned long *
  */
 static __always_inline bool test_and_clear_bit(long nr, volatile unsigned long *addr)
 {
-        GEN_BINARY_RMWcc(LOCK_PREFIX "btr", *addr, "Ir", nr, "%0", c);
+        GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(btr),
+                         *addr, "Ir", nr, "%0", c);
 }
 
 /**
@@ -286,7 +288,7 @@ static __always_inline bool __test_and_clear_bit(long nr, volatile unsigned long
 {
         bool oldbit;
 
-        asm volatile("btr %2,%1"
+        asm volatile(__ASM_SIZE(btr) " %2,%1"
                      CC_SET(c)
                      : CC_OUT(c) (oldbit), ADDR
                      : "Ir" (nr));
@@ -298,7 +300,7 @@ static __always_inline bool __test_and_change_bit(long nr, volatile unsigned lon
 {
         bool oldbit;
 
-        asm volatile("btc %2,%1"
+        asm volatile(__ASM_SIZE(btc) " %2,%1"
                      CC_SET(c)
                      : CC_OUT(c) (oldbit), ADDR
                      : "Ir" (nr) : "memory");
@@ -316,7 +318,8 @@ static __always_inline bool __test_and_change_bit(long nr, volatile unsigned lon
  */
 static __always_inline bool test_and_change_bit(long nr, volatile unsigned long *addr)
 {
-        GEN_BINARY_RMWcc(LOCK_PREFIX "btc", *addr, "Ir", nr, "%0", c);
+        GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(btc),
+                         *addr, "Ir", nr, "%0", c);
 }
 
 static __always_inline bool constant_test_bit(long nr, const volatile unsigned long *addr)
@@ -329,7 +332,7 @@ static __always_inline bool variable_test_bit(long nr, volatile const unsigned l
 {
         bool oldbit;
 
-        asm volatile("bt %2,%1"
+        asm volatile(__ASM_SIZE(bt) " %2,%1"
                      CC_SET(c)
                      : CC_OUT(c) (oldbit)
                      : "m" (*(unsigned long *)addr), "Ir" (nr));
diff --git a/arch/x86/include/asm/bug.h b/arch/x86/include/asm/bug.h
index 34d99af43994..6804d6642767 100644
--- a/arch/x86/include/asm/bug.h
+++ b/arch/x86/include/asm/bug.h
@@ -5,23 +5,20 @@
 #include <linux/stringify.h>
 
 /*
- * Since some emulators terminate on UD2, we cannot use it for WARN.
- * Since various instruction decoders disagree on the length of UD1,
- * we cannot use it either. So use UD0 for WARN.
+ * Despite that some emulators terminate on UD2, we use it for WARN().
  *
- * (binutils knows about "ud1" but {en,de}codes it as 2 bytes, whereas
- *  our kernel decoder thinks it takes a ModRM byte, which seems consistent
- *  with various things like the Intel SDM instruction encoding rules)
+ * Since various instruction decoders/specs disagree on the encoding of
+ * UD0/UD1.
  */
 
-#define ASM_UD0         ".byte 0x0f, 0xff"
+#define ASM_UD0         ".byte 0x0f, 0xff" /* + ModRM (for Intel) */
 #define ASM_UD1         ".byte 0x0f, 0xb9" /* + ModRM */
 #define ASM_UD2         ".byte 0x0f, 0x0b"
 
 #define INSN_UD0        0xff0f
 #define INSN_UD2        0x0b0f
 
-#define LEN_UD0         2
+#define LEN_UD2         2
 
 #ifdef CONFIG_GENERIC_BUG
 
@@ -77,7 +74,11 @@ do {								\
         unreachable();                                          \
 } while (0)
 
-#define __WARN_FLAGS(flags)     _BUG_FLAGS(ASM_UD0, BUGFLAG_WARNING|(flags))
+#define __WARN_FLAGS(flags)                                     \
+do {                                                            \
+        _BUG_FLAGS(ASM_UD2, BUGFLAG_WARNING|(flags));           \
+        annotate_reachable();                                   \
+} while (0)
 
 #include <asm-generic/bug.h>
 
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 70eddb3922ff..736771c9822e 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -148,45 +148,46 @@ extern void clear_cpu_cap(struct cpuinfo_x86 *c, unsigned int bit);
  */
 static __always_inline __pure bool _static_cpu_has(u16 bit)
 {
-                asm_volatile_goto("1: jmp 6f\n"
-                         "2:\n"
-                         ".skip -(((5f-4f) - (2b-1b)) > 0) * "
-                                 "((5f-4f) - (2b-1b)),0x90\n"
-                         "3:\n"
-                         ".section .altinstructions,\"a\"\n"
-                         " .long 1b - .\n"              /* src offset */
-                         " .long 4f - .\n"              /* repl offset */
-                         " .word %P1\n"                 /* always replace */
-                         " .byte 3b - 1b\n"             /* src len */
-                         " .byte 5f - 4f\n"             /* repl len */
-                         " .byte 3b - 2b\n"             /* pad len */
-                         ".previous\n"
-                         ".section .altinstr_replacement,\"ax\"\n"
-                         "4: jmp %l[t_no]\n"
-                         "5:\n"
-                         ".previous\n"
-                         ".section .altinstructions,\"a\"\n"
-                         " .long 1b - .\n"              /* src offset */
-                         " .long 0\n"                   /* no replacement */
-                         " .word %P0\n"                 /* feature bit */
-                         " .byte 3b - 1b\n"             /* src len */
-                         " .byte 0\n"                   /* repl len */
-                         " .byte 0\n"                   /* pad len */
-                         ".previous\n"
-                         ".section .altinstr_aux,\"ax\"\n"
-                         "6:\n"
-                         " testb %[bitnum],%[cap_byte]\n"
-                         " jnz %l[t_yes]\n"
-                         " jmp %l[t_no]\n"
-                         ".previous\n"
-                         : : "i" (bit), "i" (X86_FEATURE_ALWAYS),
-                             [bitnum] "i" (1 << (bit & 7)),
-                             [cap_byte] "m" (((const char *)boot_cpu_data.x86_capability)[bit >> 3])
-                         : : t_yes, t_no);
-        t_yes:
-                return true;
-        t_no:
-                return false;
+        asm_volatile_goto("1: jmp 6f\n"
+                 "2:\n"
+                 ".skip -(((5f-4f) - (2b-1b)) > 0) * "
+                         "((5f-4f) - (2b-1b)),0x90\n"
+                 "3:\n"
+                 ".section .altinstructions,\"a\"\n"
+                 " .long 1b - .\n"              /* src offset */
+                 " .long 4f - .\n"              /* repl offset */
+                 " .word %P[always]\n"          /* always replace */
+                 " .byte 3b - 1b\n"             /* src len */
+                 " .byte 5f - 4f\n"             /* repl len */
+                 " .byte 3b - 2b\n"             /* pad len */
+                 ".previous\n"
+                 ".section .altinstr_replacement,\"ax\"\n"
+                 "4: jmp %l[t_no]\n"
+                 "5:\n"
+                 ".previous\n"
+                 ".section .altinstructions,\"a\"\n"
+                 " .long 1b - .\n"              /* src offset */
+                 " .long 0\n"                   /* no replacement */
+                 " .word %P[feature]\n"         /* feature bit */
+                 " .byte 3b - 1b\n"             /* src len */
+                 " .byte 0\n"                   /* repl len */
+                 " .byte 0\n"                   /* pad len */
+                 ".previous\n"
+                 ".section .altinstr_aux,\"ax\"\n"
+                 "6:\n"
+                 " testb %[bitnum],%[cap_byte]\n"
+                 " jnz %l[t_yes]\n"
+                 " jmp %l[t_no]\n"
+                 ".previous\n"
+                 : : [feature]  "i" (bit),
+                     [always]   "i" (X86_FEATURE_ALWAYS),
+                     [bitnum]   "i" (1 << (bit & 7)),
+                     [cap_byte] "m" (((const char *)boot_cpu_data.x86_capability)[bit >> 3])
+                 : : t_yes, t_no);
+t_yes:
+        return true;
+t_no:
+        return false;
 }
 
 #define static_cpu_has(bit)                                     \
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 0dfe4d3f74e2..f41079da38c5 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -213,6 +213,7 @@
 #define X86_FEATURE_SEV                 ( 7*32+20) /* AMD Secure Encrypted Virtualization */
 
 #define X86_FEATURE_USE_IBPB            ( 7*32+21) /* "" Indirect Branch Prediction Barrier enabled */
+#define X86_FEATURE_USE_IBRS_FW         ( 7*32+22) /* "" Use IBRS during runtime firmware calls */
 
 /* Virtualization flags: Linux defined, word 8 */
 #define X86_FEATURE_TPR_SHADOW          ( 8*32+ 0) /* Intel TPR Shadow */
diff --git a/arch/x86/include/asm/efi.h b/arch/x86/include/asm/efi.h
index 85f6ccb80b91..a399c1ebf6f0 100644
--- a/arch/x86/include/asm/efi.h
+++ b/arch/x86/include/asm/efi.h
@@ -6,6 +6,7 @@
 #include <asm/pgtable.h>
 #include <asm/processor-flags.h>
 #include <asm/tlb.h>
+#include <asm/nospec-branch.h>
 
 /*
  * We map the EFI regions needed for runtime services non-contiguously,
@@ -36,8 +37,18 @@
 
 extern asmlinkage unsigned long efi_call_phys(void *, ...);
 
-#define arch_efi_call_virt_setup()      kernel_fpu_begin()
-#define arch_efi_call_virt_teardown()   kernel_fpu_end()
+#define arch_efi_call_virt_setup()                                      \
+({                                                                      \
+        kernel_fpu_begin();                                             \
+        firmware_restrict_branch_speculation_start();                   \
+})
+
+#define arch_efi_call_virt_teardown()                                   \
+({                                                                      \
+        firmware_restrict_branch_speculation_end();                     \
+        kernel_fpu_end();                                               \
+})
+
 
 /*
  * Wrap all the virtual calls in a way that forces the parameters on the stack.
@@ -73,6 +84,7 @@ struct efi_scratch {
         efi_sync_low_kernel_mappings();                                 \
         preempt_disable();                                              \
         __kernel_fpu_begin();                                           \
+        firmware_restrict_branch_speculation_start();                   \
                                                                         \
         if (efi_scratch.use_pgd) {                                      \
                 efi_scratch.prev_cr3 = __read_cr3();                    \
@@ -91,6 +103,7 @@ struct efi_scratch {
                 __flush_tlb_all();                                      \
         }                                                               \
                                                                         \
+        firmware_restrict_branch_speculation_end();                     \
         __kernel_fpu_end();                                             \
         preempt_enable();                                               \
 })
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index dd6f57a54a26..b605a5b6a30c 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -507,6 +507,7 @@ struct kvm_vcpu_arch {
         u64 smi_count;
         bool tpr_access_reporting;
         u64 ia32_xss;
+        u64 microcode_version;
 
         /*
          * Paging state of the vcpu
@@ -1095,6 +1096,8 @@ struct kvm_x86_ops {
         int (*mem_enc_op)(struct kvm *kvm, void __user *argp);
         int (*mem_enc_reg_region)(struct kvm *kvm, struct kvm_enc_region *argp);
         int (*mem_enc_unreg_region)(struct kvm *kvm, struct kvm_enc_region *argp);
+
+        int (*get_msr_feature)(struct kvm_msr_entry *entry);
 };
 
 struct kvm_arch_async_pf {
@@ -1464,7 +1467,4 @@ static inline int kvm_cpu_get_apicid(int mps_cpu)
 #define put_smstate(type, buf, offset, val)                      \
         *(type *)((buf) + (offset) - 0x7e00) = val
 
-void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
-                unsigned long start, unsigned long end);
-
 #endif /* _ASM_X86_KVM_HOST_H */
diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h
index 55520cec8b27..7fb1047d61c7 100644
--- a/arch/x86/include/asm/microcode.h
+++ b/arch/x86/include/asm/microcode.h
@@ -37,7 +37,12 @@ struct cpu_signature {
 
 struct device;
 
-enum ucode_state { UCODE_ERROR, UCODE_OK, UCODE_NFOUND };
+enum ucode_state {
+        UCODE_OK        = 0,
+        UCODE_UPDATED,
+        UCODE_NFOUND,
+        UCODE_ERROR,
+};
 
 struct microcode_ops {
         enum ucode_state (*request_microcode_user) (int cpu,
@@ -54,7 +59,7 @@ struct microcode_ops {
          * are being called.
          * See also the "Synchronization" section in microcode_core.c.
          */
-        int (*apply_microcode) (int cpu);
+        enum ucode_state (*apply_microcode) (int cpu);
         int (*collect_cpu_info) (int cpu, struct cpu_signature *csig);
 };
 
diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_context.h
index c931b88982a0..1de72ce514cd 100644
--- a/arch/x86/include/asm/mmu_context.h
+++ b/arch/x86/include/asm/mmu_context.h
@@ -74,6 +74,7 @@ static inline void *ldt_slot_va(int slot)
         return (void *)(LDT_BASE_ADDR + LDT_SLOT_STRIDE * slot);
 #else
         BUG();
+        return (void *)fix_to_virt(FIX_HOLE);
 #endif
 }
 
diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/nospec-branch.h
index 4d57894635f2..d0dabeae0505 100644
--- a/arch/x86/include/asm/nospec-branch.h
+++ b/arch/x86/include/asm/nospec-branch.h
@@ -6,6 +6,51 @@
 #include <asm/alternative.h>
 #include <asm/alternative-asm.h>
 #include <asm/cpufeatures.h>
+#include <asm/msr-index.h>
+
+/*
+ * Fill the CPU return stack buffer.
+ *
+ * Each entry in the RSB, if used for a speculative 'ret', contains an
+ * infinite 'pause; lfence; jmp' loop to capture speculative execution.
+ *
+ * This is required in various cases for retpoline and IBRS-based
+ * mitigations for the Spectre variant 2 vulnerability. Sometimes to
+ * eliminate potentially bogus entries from the RSB, and sometimes
+ * purely to ensure that it doesn't get empty, which on some CPUs would
+ * allow predictions from other (unwanted!) sources to be used.
+ *
+ * We define a CPP macro such that it can be used from both .S files and
+ * inline assembly. It's possible to do a .macro and then include that
+ * from C via asm(".include <asm/nospec-branch.h>") but let's not go there.
+ */
+
+#define RSB_CLEAR_LOOPS         32      /* To forcibly overwrite all entries */
+#define RSB_FILL_LOOPS          16      /* To avoid underflow */
+
+/*
+ * Google experimented with loop-unrolling and this turned out to be
+ * the optimal version — two calls, each with their own speculation
+ * trap should their return address end up getting used, in a loop.
+ */
+#define __FILL_RETURN_BUFFER(reg, nr, sp)       \
+        mov     $(nr/2), reg;                   \
+771:                                            \
+        call    772f;                           \
+773:    /* speculation trap */                  \
+        pause;                                  \
+        lfence;                                 \
+        jmp     773b;                           \
+772:                                            \
+        call    774f;                           \
+775:    /* speculation trap */                  \
+        pause;                                  \
+        lfence;                                 \
+        jmp     775b;                           \
+774:                                            \
+        dec     reg;                            \
+        jnz     771b;                           \
+        add     $(BITS_PER_LONG/8) * nr, sp;
 
 #ifdef __ASSEMBLY__
 
@@ -23,6 +68,18 @@
 .endm
 
 /*
+ * This should be used immediately before an indirect jump/call. It tells
+ * objtool the subsequent indirect jump/call is vouched safe for retpoline
+ * builds.
+ */
+.macro ANNOTATE_RETPOLINE_SAFE
+        .Lannotate_\@:
+        .pushsection .discard.retpoline_safe
+        _ASM_PTR .Lannotate_\@
+        .popsection
+.endm
+
+/*
  * These are the bare retpoline primitives for indirect jmp and call.
  * Do not use these directly; they only exist to make the ALTERNATIVE
  * invocation below less ugly.
@@ -58,9 +115,9 @@
 .macro JMP_NOSPEC reg:req
 #ifdef CONFIG_RETPOLINE
         ANNOTATE_NOSPEC_ALTERNATIVE
-        ALTERNATIVE_2 __stringify(jmp *\reg),                           \
+        ALTERNATIVE_2 __stringify(ANNOTATE_RETPOLINE_SAFE; jmp *\reg),  \
                 __stringify(RETPOLINE_JMP \reg), X86_FEATURE_RETPOLINE, \
-                __stringify(lfence; jmp *\reg), X86_FEATURE_RETPOLINE_AMD
+                __stringify(lfence; ANNOTATE_RETPOLINE_SAFE; jmp *\reg), X86_FEATURE_RETPOLINE_AMD
 #else
         jmp     *\reg
 #endif
@@ -69,18 +126,25 @@
 .macro CALL_NOSPEC reg:req
 #ifdef CONFIG_RETPOLINE
         ANNOTATE_NOSPEC_ALTERNATIVE
-        ALTERNATIVE_2 __stringify(call *\reg),                          \
+        ALTERNATIVE_2 __stringify(ANNOTATE_RETPOLINE_SAFE; call *\reg), \
                 __stringify(RETPOLINE_CALL \reg), X86_FEATURE_RETPOLINE,\
-                __stringify(lfence; call *\reg), X86_FEATURE_RETPOLINE_AMD
+                __stringify(lfence; ANNOTATE_RETPOLINE_SAFE; call *\reg), X86_FEATURE_RETPOLINE_AMD
 #else
         call    *\reg
 #endif
 .endm
 
-/* This clobbers the BX register */
-.macro FILL_RETURN_BUFFER nr:req ftr:req
+ /*
+  * A simpler FILL_RETURN_BUFFER macro. Don't make people use the CPP
+  * monstrosity above, manually.
+  */
+.macro FILL_RETURN_BUFFER reg:req nr:req ftr:req
 #ifdef CONFIG_RETPOLINE
-        ALTERNATIVE "", "call __clear_rsb", \ftr
+        ANNOTATE_NOSPEC_ALTERNATIVE
+        ALTERNATIVE "jmp .Lskip_rsb_\@",                                \
+                __stringify(__FILL_RETURN_BUFFER(\reg,\nr,%_ASM_SP))    \
+                \ftr
+.Lskip_rsb_\@:
 #endif
 .endm
 
@@ -92,6 +156,12 @@
         ".long 999b - .\n\t"                                    \
         ".popsection\n\t"
 
+#define ANNOTATE_RETPOLINE_SAFE                                 \
+        "999:\n\t"                                              \
+        ".pushsection .discard.retpoline_safe\n\t"              \
+        _ASM_PTR " 999b\n\t"                                    \
+        ".popsection\n\t"
+
 #if defined(CONFIG_X86_64) && defined(RETPOLINE)
 
 /*
@@ -101,6 +171,7 @@
 # define CALL_NOSPEC                                            \
         ANNOTATE_NOSPEC_ALTERNATIVE                             \
         ALTERNATIVE(                                            \
+        ANNOTATE_RETPOLINE_SAFE                                 \
         "call *%[thunk_target]\n",                              \
         "call __x86_indirect_thunk_%V[thunk_target]\n",         \
         X86_FEATURE_RETPOLINE)
@@ -155,20 +226,90 @@ extern char __indirect_thunk_end[];
 static inline void vmexit_fill_RSB(void)
 {
 #ifdef CONFIG_RETPOLINE
-        alternative_input("",
-                          "call __fill_rsb",
-                          X86_FEATURE_RETPOLINE,
-                          ASM_NO_INPUT_CLOBBER(_ASM_BX, "memory"));
+        unsigned long loops;
+
+        asm volatile (ANNOTATE_NOSPEC_ALTERNATIVE
+                      ALTERNATIVE("jmp 910f",
+                                  __stringify(__FILL_RETURN_BUFFER(%0, RSB_CLEAR_LOOPS, %1)),
+                                  X86_FEATURE_RETPOLINE)
+                      "910:"
+                      : "=r" (loops), ASM_CALL_CONSTRAINT
+                      : : "memory" );
 #endif
 }
 
+#define alternative_msr_write(_msr, _val, _feature)             \
+        asm volatile(ALTERNATIVE("",                            \
+                                 "movl %[msr], %%ecx\n\t"       \
+                                 "movl %[val], %%eax\n\t"       \
+                                 "movl $0, %%edx\n\t"           \
+                                 "wrmsr",                       \
+                                 _feature)                      \
+                     : : [msr] "i" (_msr), [val] "i" (_val)     \
+                     : "eax", "ecx", "edx", "memory")
+
 static inline void indirect_branch_prediction_barrier(void)
 {
-        alternative_input("",
-                          "call __ibp_barrier",
-                          X86_FEATURE_USE_IBPB,
-                          ASM_NO_INPUT_CLOBBER("eax", "ecx", "edx", "memory"));
+        alternative_msr_write(MSR_IA32_PRED_CMD, PRED_CMD_IBPB,
+                              X86_FEATURE_USE_IBPB);
 }
 
+/*
+ * With retpoline, we must use IBRS to restrict branch prediction
+ * before calling into firmware.
+ *
+ * (Implemented as CPP macros due to header hell.)
+ */
+#define firmware_restrict_branch_speculation_start()                    \
+do {                                                                    \
+        preempt_disable();                                              \
+        alternative_msr_write(MSR_IA32_SPEC_CTRL, SPEC_CTRL_IBRS,       \
+                              X86_FEATURE_USE_IBRS_FW);                 \
+} while (0)
+
+#define firmware_restrict_branch_speculation_end()                      \
+do {                                                                    \
+        alternative_msr_write(MSR_IA32_SPEC_CTRL, 0,                    \
+                              X86_FEATURE_USE_IBRS_FW);                 \
+        preempt_enable();                                               \
+} while (0)
+
 #endif /* __ASSEMBLY__ */
+
+/*
+ * Below is used in the eBPF JIT compiler and emits the byte sequence
+ * for the following assembly:
+ *
+ * With retpolines configured:
+ *
+ *    callq do_rop
+ *  spec_trap:
+ *    pause
+ *    lfence
+ *    jmp spec_trap
+ *  do_rop:
+ *    mov %rax,(%rsp)
+ *    retq
+ *
+ * Without retpolines configured:
+ *
+ *    jmp *%rax
+ */
+#ifdef CONFIG_RETPOLINE
+# define RETPOLINE_RAX_BPF_JIT_SIZE     17
+# define RETPOLINE_RAX_BPF_JIT()                                \
+        EMIT1_off32(0xE8, 7);    /* callq do_rop */             \
+        /* spec_trap: */                                        \
+        EMIT2(0xF3, 0x90);       /* pause */                    \
+        EMIT3(0x0F, 0xAE, 0xE8); /* lfence */                   \
+        EMIT2(0xEB, 0xF9);       /* jmp spec_trap */            \
+        /* do_rop: */                                           \
+        EMIT4(0x48, 0x89, 0x04, 0x24); /* mov %rax,(%rsp) */    \
+        EMIT1(0xC3);             /* retq */
+#else
+# define RETPOLINE_RAX_BPF_JIT_SIZE     2
+# define RETPOLINE_RAX_BPF_JIT()                                \
+        EMIT2(0xFF, 0xE0);       /* jmp *%rax */
+#endif
+
 #endif /* _ASM_X86_NOSPEC_BRANCH_H_ */
diff --git a/arch/x86/include/asm/page_64.h b/arch/x86/include/asm/page_64.h
index 4baa6bceb232..d652a3808065 100644
--- a/arch/x86/include/asm/page_64.h
+++ b/arch/x86/include/asm/page_64.h
@@ -52,10 +52,6 @@ static inline void clear_page(void *page)
 
 void copy_page(void *to, void *from);
 
-#ifdef CONFIG_X86_MCE
-#define arch_unmap_kpfn arch_unmap_kpfn
-#endif
-
 #endif  /* !__ASSEMBLY__ */
 
 #ifdef CONFIG_X86_VSYSCALL_EMULATION
diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h
index 892df375b615..c83a2f418cea 100644
--- a/arch/x86/include/asm/paravirt.h
+++ b/arch/x86/include/asm/paravirt.h
@@ -7,6 +7,7 @@
 #ifdef CONFIG_PARAVIRT
 #include <asm/pgtable_types.h>
 #include <asm/asm.h>
+#include <asm/nospec-branch.h>
 
 #include <asm/paravirt_types.h>
 
@@ -297,9 +298,9 @@ static inline void __flush_tlb_global(void)
 {
         PVOP_VCALL0(pv_mmu_ops.flush_tlb_kernel);
 }
-static inline void __flush_tlb_single(unsigned long addr)
+static inline void __flush_tlb_one_user(unsigned long addr)
 {
-        PVOP_VCALL1(pv_mmu_ops.flush_tlb_single, addr);
+        PVOP_VCALL1(pv_mmu_ops.flush_tlb_one_user, addr);
 }
 
 static inline void flush_tlb_others(const struct cpumask *cpumask,
@@ -879,23 +880,27 @@ extern void default_banner(void);
 
 #define INTERRUPT_RETURN                                                \
         PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_iret), CLBR_NONE,       \
-                  jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_iret))
+                  ANNOTATE_RETPOLINE_SAFE;                                      \
+                  jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_iret);)
 
 #define DISABLE_INTERRUPTS(clobbers)                                    \
         PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_disable), clobbers, \
                   PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE);            \
+                  ANNOTATE_RETPOLINE_SAFE;                                      \
                   call PARA_INDIRECT(pv_irq_ops+PV_IRQ_irq_disable);    \
                   PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);)
 
 #define ENABLE_INTERRUPTS(clobbers)                                     \
         PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_enable), clobbers,  \
                   PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE);            \
+                  ANNOTATE_RETPOLINE_SAFE;                                      \
                   call PARA_INDIRECT(pv_irq_ops+PV_IRQ_irq_enable);     \
                   PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);)
 
 #ifdef CONFIG_X86_32
 #define GET_CR0_INTO_EAX                                \
         push %ecx; push %edx;                           \
+        ANNOTATE_RETPOLINE_SAFE;                                \
         call PARA_INDIRECT(pv_cpu_ops+PV_CPU_read_cr0); \
         pop %edx; pop %ecx
 #else   /* !CONFIG_X86_32 */
@@ -917,21 +922,25 @@ extern void default_banner(void);
  */
 #define SWAPGS                                                          \
         PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_swapgs), CLBR_NONE,     \
-                  call PARA_INDIRECT(pv_cpu_ops+PV_CPU_swapgs)          \
+                  ANNOTATE_RETPOLINE_SAFE;                                      \
+                  call PARA_INDIRECT(pv_cpu_ops+PV_CPU_swapgs);         \
                  )
 
 #define GET_CR2_INTO_RAX                                \
-        call PARA_INDIRECT(pv_mmu_ops+PV_MMU_read_cr2)
+        ANNOTATE_RETPOLINE_SAFE;                                \
+        call PARA_INDIRECT(pv_mmu_ops+PV_MMU_read_cr2);
 
 #define USERGS_SYSRET64                                                 \
         PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_usergs_sysret64),       \
                   CLBR_NONE,                                            \
-                  jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_usergs_sysret64))
+                  ANNOTATE_RETPOLINE_SAFE;                                      \
+                  jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_usergs_sysret64);)
 
 #ifdef CONFIG_DEBUG_ENTRY
 #define SAVE_FLAGS(clobbers)                                        \
         PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_save_fl), clobbers, \
                   PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE);        \
+                  ANNOTATE_RETPOLINE_SAFE;                                  \
                   call PARA_INDIRECT(pv_irq_ops+PV_IRQ_save_fl);    \
                   PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);)
 #endif
diff --git a/arch/x86/include/asm/paravirt_types.h b/arch/x86/include/asm/paravirt_types.h
index 6ec54d01972d..180bc0bff0fb 100644
--- a/arch/x86/include/asm/paravirt_types.h
+++ b/arch/x86/include/asm/paravirt_types.h
@@ -43,6 +43,7 @@
 #include <asm/desc_defs.h>
 #include <asm/kmap_types.h>
 #include <asm/pgtable_types.h>
+#include <asm/nospec-branch.h>
 
 struct page;
 struct thread_struct;
@@ -217,7 +218,7 @@ struct pv_mmu_ops {
         /* TLB operations */
         void (*flush_tlb_user)(void);
         void (*flush_tlb_kernel)(void);
-        void (*flush_tlb_single)(unsigned long addr);
+        void (*flush_tlb_one_user)(unsigned long addr);
         void (*flush_tlb_others)(const struct cpumask *cpus,
                                  const struct flush_tlb_info *info);
 
@@ -392,7 +393,9 @@ int paravirt_disable_iospace(void);
  * offset into the paravirt_patch_template structure, and can therefore be
  * freely converted back into a structure offset.
  */
-#define PARAVIRT_CALL   "call *%c[paravirt_opptr];"
+#define PARAVIRT_CALL                                   \
+        ANNOTATE_RETPOLINE_SAFE                         \
+        "call *%c[paravirt_opptr];"
 
 /*
  * These macros are intended to wrap calls through one of the paravirt
diff --git a/arch/x86/include/asm/percpu.h b/arch/x86/include/asm/percpu.h
index ba3c523aaf16..a06b07399d17 100644
--- a/arch/x86/include/asm/percpu.h
+++ b/arch/x86/include/asm/percpu.h
@@ -526,7 +526,7 @@ static inline bool x86_this_cpu_variable_test_bit(int nr,
 {
         bool oldbit;
 
-        asm volatile("bt "__percpu_arg(2)",%1"
+        asm volatile("btl "__percpu_arg(2)",%1"
                         CC_SET(c)
                         : CC_OUT(c) (oldbit)
                         : "m" (*(unsigned long __percpu *)addr), "Ir" (nr));
diff --git a/arch/x86/include/asm/pgtable.h b/arch/x86/include/asm/pgtable.h
index 63c2552b6b65..b444d83cfc95 100644
--- a/arch/x86/include/asm/pgtable.h
+++ b/arch/x86/include/asm/pgtable.h
@@ -350,14 +350,14 @@ static inline pmd_t pmd_set_flags(pmd_t pmd, pmdval_t set)
 {
         pmdval_t v = native_pmd_val(pmd);
 
-        return __pmd(v | set);
+        return native_make_pmd(v | set);
 }
 
 static inline pmd_t pmd_clear_flags(pmd_t pmd, pmdval_t clear)
 {
         pmdval_t v = native_pmd_val(pmd);
 
-        return __pmd(v & ~clear);
+        return native_make_pmd(v & ~clear);
 }
 
 static inline pmd_t pmd_mkold(pmd_t pmd)
@@ -409,14 +409,14 @@ static inline pud_t pud_set_flags(pud_t pud, pudval_t set)
 {
         pudval_t v = native_pud_val(pud);
 
-        return __pud(v | set);
+        return native_make_pud(v | set);
 }
 
 static inline pud_t pud_clear_flags(pud_t pud, pudval_t clear)
 {
         pudval_t v = native_pud_val(pud);
 
-        return __pud(v & ~clear);
+        return native_make_pud(v & ~clear);
 }
 
 static inline pud_t pud_mkold(pud_t pud)
diff --git a/arch/x86/include/asm/pgtable_32.h b/arch/x86/include/asm/pgtable_32.h
index e67c0620aec2..b3ec519e3982 100644
--- a/arch/x86/include/asm/pgtable_32.h
+++ b/arch/x86/include/asm/pgtable_32.h
@@ -32,6 +32,7 @@ extern pmd_t initial_pg_pmd[];
 static inline void pgtable_cache_init(void) { }
 static inline void check_pgt_cache(void) { }
 void paging_init(void);
+void sync_initial_page_table(void);
 
 /*
  * Define this if things work differently on an i386 and an i486:
@@ -61,7 +62,7 @@ void paging_init(void);
 #define kpte_clear_flush(ptep, vaddr)           \
 do {                                            \
         pte_clear(&init_mm, (vaddr), (ptep));   \
-        __flush_tlb_one((vaddr));               \
+        __flush_tlb_one_kernel((vaddr));                \
 } while (0)
 
 #endif /* !__ASSEMBLY__ */
diff --git a/arch/x86/include/asm/pgtable_64.h b/arch/x86/include/asm/pgtable_64.h
index 81462e9a34f6..1149d2112b2e 100644
--- a/arch/x86/include/asm/pgtable_64.h
+++ b/arch/x86/include/asm/pgtable_64.h
@@ -28,6 +28,7 @@ extern pgd_t init_top_pgt[];
 #define swapper_pg_dir init_top_pgt
 
 extern void paging_init(void);
+static inline void sync_initial_page_table(void) { }
 
 #define pte_ERROR(e)                                    \
         pr_err("%s:%d: bad pte %p(%016lx)\n",           \
diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgtable_types.h
index 3696398a9475..246f15b4e64c 100644
--- a/arch/x86/include/asm/pgtable_types.h
+++ b/arch/x86/include/asm/pgtable_types.h
@@ -323,6 +323,11 @@ static inline pudval_t native_pud_val(pud_t pud)
 #else
 #include <asm-generic/pgtable-nopud.h>
 
+static inline pud_t native_make_pud(pudval_t val)
+{
+        return (pud_t) { .p4d.pgd = native_make_pgd(val) };
+}
+
 static inline pudval_t native_pud_val(pud_t pud)
 {
         return native_pgd_val(pud.p4d.pgd);
@@ -344,6 +349,11 @@ static inline pmdval_t native_pmd_val(pmd_t pmd)
 #else
 #include <asm-generic/pgtable-nopmd.h>
 
+static inline pmd_t native_make_pmd(pmdval_t val)
+{
+        return (pmd_t) { .pud.p4d.pgd = native_make_pgd(val) };
+}
+
 static inline pmdval_t native_pmd_val(pmd_t pmd)
 {
         return native_pgd_val(pmd.pud.p4d.pgd);
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 793bae7e7ce3..b0ccd4847a58 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -91,7 +91,7 @@ struct cpuinfo_x86 {
         __u8                    x86;            /* CPU family */
         __u8                    x86_vendor;     /* CPU vendor */
         __u8                    x86_model;
-        __u8                    x86_mask;
+        __u8                    x86_stepping;
 #ifdef CONFIG_X86_64
         /* Number of 4K pages in DTLB/ITLB combined(in pages): */
         int                     x86_tlbsize;
@@ -109,7 +109,7 @@ struct cpuinfo_x86 {
         char                    x86_vendor_id[16];
         char                    x86_model_id[64];
         /* in KB - valid for CPUS which support this call: */
-        int                     x86_cache_size;
+        unsigned int            x86_cache_size;
         int                     x86_cache_alignment;    /* In bytes */
         /* Cache QoS architectural values: */
         int                     x86_cache_max_rmid;     /* max index */
@@ -977,7 +977,5 @@ bool xen_set_default_idle(void);
 
 void stop_this_cpu(void *dummy);
 void df_debug(struct pt_regs *regs, long error_code);
-
-void __ibp_barrier(void);
-
+void microcode_check(void);
 #endif /* _ASM_X86_PROCESSOR_H */
diff --git a/arch/x86/include/asm/refcount.h b/arch/x86/include/asm/refcount.h
index 4e44250e7d0d..4cf11d88d3b3 100644
--- a/arch/x86/include/asm/refcount.h
+++ b/arch/x86/include/asm/refcount.h
@@ -17,7 +17,7 @@
 #define _REFCOUNT_EXCEPTION                             \
         ".pushsection .text..refcount\n"                \
         "111:\tlea %[counter], %%" _ASM_CX "\n"         \
-        "112:\t" ASM_UD0 "\n"                           \
+        "112:\t" ASM_UD2 "\n"                           \
         ASM_UNREACHABLE                                 \
         ".popsection\n"                                 \
         "113:\n"                                        \
@@ -67,13 +67,13 @@ static __always_inline __must_check
 bool refcount_sub_and_test(unsigned int i, refcount_t *r)
 {
         GEN_BINARY_SUFFIXED_RMWcc(LOCK_PREFIX "subl", REFCOUNT_CHECK_LT_ZERO,
-                                  r->refs.counter, "er", i, "%0", e);
+                                  r->refs.counter, "er", i, "%0", e, "cx");
 }
 
 static __always_inline __must_check bool refcount_dec_and_test(refcount_t *r)
 {
         GEN_UNARY_SUFFIXED_RMWcc(LOCK_PREFIX "decl", REFCOUNT_CHECK_LT_ZERO,
-                                 r->refs.counter, "%0", e);
+                                 r->refs.counter, "%0", e, "cx");
 }
 
 static __always_inline __must_check
diff --git a/arch/x86/include/asm/rmwcc.h b/arch/x86/include/asm/rmwcc.h
index f91c365e57c3..4914a3e7c803 100644
--- a/arch/x86/include/asm/rmwcc.h
+++ b/arch/x86/include/asm/rmwcc.h
@@ -2,8 +2,7 @@
 #ifndef _ASM_X86_RMWcc
 #define _ASM_X86_RMWcc
 
-#define __CLOBBERS_MEM          "memory"
-#define __CLOBBERS_MEM_CC_CX    "memory", "cc", "cx"
+#define __CLOBBERS_MEM(clb...)  "memory", ## clb
 
 #if !defined(__GCC_ASM_FLAG_OUTPUTS__) && defined(CC_HAVE_ASM_GOTO)
 
@@ -40,18 +39,19 @@ do {									\
 #endif /* defined(__GCC_ASM_FLAG_OUTPUTS__) || !defined(CC_HAVE_ASM_GOTO) */
 
 #define GEN_UNARY_RMWcc(op, var, arg0, cc)                              \
-        __GEN_RMWcc(op " " arg0, var, cc, __CLOBBERS_MEM)
+        __GEN_RMWcc(op " " arg0, var, cc, __CLOBBERS_MEM())
 
-#define GEN_UNARY_SUFFIXED_RMWcc(op, suffix, var, arg0, cc)             \
+#define GEN_UNARY_SUFFIXED_RMWcc(op, suffix, var, arg0, cc, clobbers...)\
         __GEN_RMWcc(op " " arg0 "\n\t" suffix, var, cc,                 \
-                    __CLOBBERS_MEM_CC_CX)
+                    __CLOBBERS_MEM(clobbers))
 
 #define GEN_BINARY_RMWcc(op, var, vcon, val, arg0, cc)                  \
         __GEN_RMWcc(op __BINARY_RMWcc_ARG arg0, var, cc,                \
-                    __CLOBBERS_MEM, vcon (val))
+                    __CLOBBERS_MEM(), vcon (val))
 
-#define GEN_BINARY_SUFFIXED_RMWcc(op, suffix, var, vcon, val, arg0, cc) \
+#define GEN_BINARY_SUFFIXED_RMWcc(op, suffix, var, vcon, val, arg0, cc, \
+                                  clobbers...)                          \
         __GEN_RMWcc(op __BINARY_RMWcc_ARG arg0 "\n\t" suffix, var, cc,  \
-                    __CLOBBERS_MEM_CC_CX, vcon (val))
+                    __CLOBBERS_MEM(clobbers), vcon (val))
 
 #endif /* _ASM_X86_RMWcc */
diff --git a/arch/x86/include/asm/smp.h b/arch/x86/include/asm/smp.h
index 461f53d27708..a4189762b266 100644
--- a/arch/x86/include/asm/smp.h
+++ b/arch/x86/include/asm/smp.h
@@ -129,6 +129,7 @@ static inline void arch_send_call_function_ipi_mask(const struct cpumask *mask)
 void cpu_disable_common(void);
 void native_smp_prepare_boot_cpu(void);
 void native_smp_prepare_cpus(unsigned int max_cpus);
+void calculate_max_logical_packages(void);
 void native_smp_cpus_done(unsigned int max_cpus);
 void common_cpu_up(unsigned int cpunum, struct task_struct *tidle);
 int native_cpu_up(unsigned int cpunum, struct task_struct *tidle);
diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h
index 2b8f18ca5874..84137c22fdfa 100644
--- a/arch/x86/include/asm/tlbflush.h
+++ b/arch/x86/include/asm/tlbflush.h
@@ -140,7 +140,7 @@ static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid)
 #else
 #define __flush_tlb() __native_flush_tlb()
 #define __flush_tlb_global() __native_flush_tlb_global()
-#define __flush_tlb_single(addr) __native_flush_tlb_single(addr)
+#define __flush_tlb_one_user(addr) __native_flush_tlb_one_user(addr)
 #endif
 
 static inline bool tlb_defer_switch_to_init_mm(void)
@@ -400,7 +400,7 @@ static inline void __native_flush_tlb_global(void)
 /*
  * flush one page in the user mapping
  */
-static inline void __native_flush_tlb_single(unsigned long addr)
+static inline void __native_flush_tlb_one_user(unsigned long addr)
 {
         u32 loaded_mm_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid);
 
@@ -437,18 +437,31 @@ static inline void __flush_tlb_all(void)
 /*
  * flush one page in the kernel mapping
  */
-static inline void __flush_tlb_one(unsigned long addr)
+static inline void __flush_tlb_one_kernel(unsigned long addr)
 {
         count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE);
-        __flush_tlb_single(addr);
+
+        /*
+         * If PTI is off, then __flush_tlb_one_user() is just INVLPG or its
+         * paravirt equivalent.  Even with PCID, this is sufficient: we only
+         * use PCID if we also use global PTEs for the kernel mapping, and
+         * INVLPG flushes global translations across all address spaces.
+         *
+         * If PTI is on, then the kernel is mapped with non-global PTEs, and
+         * __flush_tlb_one_user() will flush the given address for the current
+         * kernel address space and for its usermode counterpart, but it does
+         * not flush it for other address spaces.
+         */
+        __flush_tlb_one_user(addr);
 
         if (!static_cpu_has(X86_FEATURE_PTI))
                 return;
 
         /*
-         * __flush_tlb_single() will have cleared the TLB entry for this ASID,
-         * but since kernel space is replicated across all, we must also
-         * invalidate all others.
+         * See above.  We need to propagate the flush to all other address
+         * spaces.  In principle, we only need to propagate it to kernelmode
+         * address spaces, but the extra bookkeeping we would need is not
+         * worth it.
          */
         invalidate_other_asid();
 }
diff --git a/arch/x86/include/uapi/asm/hyperv.h b/arch/x86/include/uapi/asm/hyperv.h
index 197c2e6c7376..099414345865 100644
--- a/arch/x86/include/uapi/asm/hyperv.h
+++ b/arch/x86/include/uapi/asm/hyperv.h
@@ -241,24 +241,24 @@
 #define HV_X64_MSR_REENLIGHTENMENT_CONTROL      0x40000106
 
 struct hv_reenlightenment_control {
-        u64 vector:8;
-        u64 reserved1:8;
-        u64 enabled:1;
-        u64 reserved2:15;
-        u64 target_vp:32;
+        __u64 vector:8;
+        __u64 reserved1:8;
+        __u64 enabled:1;
+        __u64 reserved2:15;
+        __u64 target_vp:32;
 };
 
 #define HV_X64_MSR_TSC_EMULATION_CONTROL        0x40000107
 #define HV_X64_MSR_TSC_EMULATION_STATUS         0x40000108
 
 struct hv_tsc_emulation_control {
-        u64 enabled:1;
-        u64 reserved:63;
+        __u64 enabled:1;
+        __u64 reserved:63;
 };
 
 struct hv_tsc_emulation_status {
-        u64 inprogress:1;
-        u64 reserved:63;
+        __u64 inprogress:1;
+        __u64 reserved:63;
 };
 
 #define HV_X64_MSR_HYPERCALL_ENABLE             0x00000001
diff --git a/arch/x86/include/uapi/asm/kvm_para.h b/arch/x86/include/uapi/asm/kvm_para.h
index 7a2ade4aa235..6cfa9c8cb7d6 100644
--- a/arch/x86/include/uapi/asm/kvm_para.h
+++ b/arch/x86/include/uapi/asm/kvm_para.h
@@ -26,6 +26,7 @@
 #define KVM_FEATURE_PV_EOI              6
 #define KVM_FEATURE_PV_UNHALT           7
 #define KVM_FEATURE_PV_TLB_FLUSH        9
+#define KVM_FEATURE_ASYNC_PF_VMEXIT     10
 
 /* The last 8 bits are used to indicate how to interpret the flags field
  * in pvclock structure. If no bits are set, all flags are ignored.
diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index 6db28f17ff28..c88e0b127810 100644
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/amd_nb.c
@@ -235,7 +235,7 @@ int amd_cache_northbridges(void)
         if (boot_cpu_data.x86 == 0x10 &&
             boot_cpu_data.x86_model >= 0x8 &&
             (boot_cpu_data.x86_model > 0x9 ||
-             boot_cpu_data.x86_mask >= 0x1))
+             boot_cpu_data.x86_stepping >= 0x1))
                 amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
 
         if (boot_cpu_data.x86 == 0x15)
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 25ddf02598d2..b203af0855b5 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -546,7 +546,7 @@ static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
 
 static u32 hsx_deadline_rev(void)
 {
-        switch (boot_cpu_data.x86_mask) {
+        switch (boot_cpu_data.x86_stepping) {
         case 0x02: return 0x3a; /* EP */
         case 0x04: return 0x0f; /* EX */
         }
@@ -556,7 +556,7 @@ static u32 hsx_deadline_rev(void)
 
 static u32 bdx_deadline_rev(void)
 {
-        switch (boot_cpu_data.x86_mask) {
+        switch (boot_cpu_data.x86_stepping) {
         case 0x02: return 0x00000011;
         case 0x03: return 0x0700000e;
         case 0x04: return 0x0f00000c;
@@ -568,7 +568,7 @@ static u32 bdx_deadline_rev(void)
 
 static u32 skx_deadline_rev(void)
 {
-        switch (boot_cpu_data.x86_mask) {
+        switch (boot_cpu_data.x86_stepping) {
         case 0x03: return 0x01000136;
         case 0x04: return 0x02000014;
         }
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index 8ad2e410974f..7c5538769f7e 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -1603,7 +1603,7 @@ static void __init delay_with_tsc(void)
         do {
                 rep_nop();
                 now = rdtsc();
-        } while ((now - start) < 40000000000UL / HZ &&
+        } while ((now - start) < 40000000000ULL / HZ &&
                 time_before_eq(jiffies, end));
 }
 
diff --git a/arch/x86/kernel/apic/vector.c b/arch/x86/kernel/apic/vector.c
index 3cc471beb50b..bb6f7a2148d7 100644
--- a/arch/x86/kernel/apic/vector.c
+++ b/arch/x86/kernel/apic/vector.c
@@ -134,21 +134,40 @@ static void apic_update_vector(struct irq_data *irqd, unsigned int newvec,
 {
         struct apic_chip_data *apicd = apic_chip_data(irqd);
         struct irq_desc *desc = irq_data_to_desc(irqd);
+        bool managed = irqd_affinity_is_managed(irqd);
 
         lockdep_assert_held(&vector_lock);
 
         trace_vector_update(irqd->irq, newvec, newcpu, apicd->vector,
                             apicd->cpu);
 
-        /* Setup the vector move, if required  */
-        if (apicd->vector && cpu_online(apicd->cpu)) {
+        /*
+         * If there is no vector associated or if the associated vector is
+         * the shutdown vector, which is associated to make PCI/MSI
+         * shutdown mode work, then there is nothing to release. Clear out
+         * prev_vector for this and the offlined target case.
+         */
+        apicd->prev_vector = 0;
+        if (!apicd->vector || apicd->vector == MANAGED_IRQ_SHUTDOWN_VECTOR)
+                goto setnew;
+        /*
+         * If the target CPU of the previous vector is online, then mark
+         * the vector as move in progress and store it for cleanup when the
+         * first interrupt on the new vector arrives. If the target CPU is
+         * offline then the regular release mechanism via the cleanup
+         * vector is not possible and the vector can be immediately freed
+         * in the underlying matrix allocator.
+         */
+        if (cpu_online(apicd->cpu)) {
                 apicd->move_in_progress = true;
                 apicd->prev_vector = apicd->vector;
                 apicd->prev_cpu = apicd->cpu;
         } else {
-                apicd->prev_vector = 0;
+                irq_matrix_free(vector_matrix, apicd->cpu, apicd->vector,
+                                managed);
         }
 
+setnew:
         apicd->vector = newvec;
         apicd->cpu = newcpu;
         BUG_ON(!IS_ERR_OR_NULL(per_cpu(vector_irq, newcpu)[newvec]));
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index 46b675aaf20b..f11910b44638 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -1176,16 +1176,25 @@ static void __init decode_gam_rng_tbl(unsigned long ptr)
 
         uv_gre_table = gre;
         for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
+                unsigned long size = ((unsigned long)(gre->limit - lgre)
+                                        << UV_GAM_RANGE_SHFT);
+                int order = 0;
+                char suffix[] = " KMGTPE";
+
+                while (size > 9999 && order < sizeof(suffix)) {
+                        size /= 1024;
+                        order++;
+                }
+
                 if (!index) {
                         pr_info("UV: GAM Range Table...\n");
                         pr_info("UV:  # %20s %14s %5s %4s %5s %3s %2s\n", "Range", "", "Size", "Type", "NASID", "SID", "PN");
                 }
-                pr_info("UV: %2d: 0x%014lx-0x%014lx %5luG %3d   %04x  %02x %02x\n",
+                pr_info("UV: %2d: 0x%014lx-0x%014lx %5lu%c %3d   %04x  %02x %02x\n",
                         index++,
                         (unsigned long)lgre << UV_GAM_RANGE_SHFT,
                         (unsigned long)gre->limit << UV_GAM_RANGE_SHFT,
-                        ((unsigned long)(gre->limit - lgre)) >>
-                                (30 - UV_GAM_RANGE_SHFT), /* 64M -> 1G */
+                        size, suffix[order],
                         gre->type, gre->nasid, gre->sockid, gre->pnode);
 
                 lgre = gre->limit;
diff --git a/arch/x86/kernel/asm-offsets_32.c b/arch/x86/kernel/asm-offsets_32.c
index fa1261eefa16..f91ba53e06c8 100644
--- a/arch/x86/kernel/asm-offsets_32.c
+++ b/arch/x86/kernel/asm-offsets_32.c
@@ -18,7 +18,7 @@ void foo(void)
         OFFSET(CPUINFO_x86, cpuinfo_x86, x86);
         OFFSET(CPUINFO_x86_vendor, cpuinfo_x86, x86_vendor);
         OFFSET(CPUINFO_x86_model, cpuinfo_x86, x86_model);
-        OFFSET(CPUINFO_x86_mask, cpuinfo_x86, x86_mask);
+        OFFSET(CPUINFO_x86_stepping, cpuinfo_x86, x86_stepping);
         OFFSET(CPUINFO_cpuid_level, cpuinfo_x86, cpuid_level);
         OFFSET(CPUINFO_x86_capability, cpuinfo_x86, x86_capability);
         OFFSET(CPUINFO_x86_vendor_id, cpuinfo_x86, x86_vendor_id);
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 5bddbdcbc4a3..f0e6456ca7d3 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -119,7 +119,7 @@ static void init_amd_k6(struct cpuinfo_x86 *c)
                 return;
         }
 
-        if (c->x86_model == 6 && c->x86_mask == 1) {
+        if (c->x86_model == 6 && c->x86_stepping == 1) {
                 const int K6_BUG_LOOP = 1000000;
                 int n;
                 void (*f_vide)(void);
@@ -149,7 +149,7 @@ static void init_amd_k6(struct cpuinfo_x86 *c)
 
         /* K6 with old style WHCR */
         if (c->x86_model < 8 ||
-           (c->x86_model == 8 && c->x86_mask < 8)) {
+           (c->x86_model == 8 && c->x86_stepping < 8)) {
                 /* We can only write allocate on the low 508Mb */
                 if (mbytes > 508)
                         mbytes = 508;
@@ -168,7 +168,7 @@ static void init_amd_k6(struct cpuinfo_x86 *c)
                 return;
         }
 
-        if ((c->x86_model == 8 && c->x86_mask > 7) ||
+        if ((c->x86_model == 8 && c->x86_stepping > 7) ||
              c->x86_model == 9 || c->x86_model == 13) {
                 /* The more serious chips .. */
 
@@ -221,7 +221,7 @@ static void init_amd_k7(struct cpuinfo_x86 *c)
          * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
          * As per AMD technical note 27212 0.2
          */
-        if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
+        if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) {
                 rdmsr(MSR_K7_CLK_CTL, l, h);
                 if ((l & 0xfff00000) != 0x20000000) {
                         pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
@@ -241,12 +241,12 @@ static void init_amd_k7(struct cpuinfo_x86 *c)
          * but they are not certified as MP capable.
          */
         /* Athlon 660/661 is valid. */
-        if ((c->x86_model == 6) && ((c->x86_mask == 0) ||
-            (c->x86_mask == 1)))
+        if ((c->x86_model == 6) && ((c->x86_stepping == 0) ||
+            (c->x86_stepping == 1)))
                 return;
 
         /* Duron 670 is valid */
-        if ((c->x86_model == 7) && (c->x86_mask == 0))
+        if ((c->x86_model == 7) && (c->x86_stepping == 0))
                 return;
 
         /*
@@ -256,8 +256,8 @@ static void init_amd_k7(struct cpuinfo_x86 *c)
          * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
          * more.
          */
-        if (((c->x86_model == 6) && (c->x86_mask >= 2)) ||
-            ((c->x86_model == 7) && (c->x86_mask >= 1)) ||
+        if (((c->x86_model == 6) && (c->x86_stepping >= 2)) ||
+            ((c->x86_model == 7) && (c->x86_stepping >= 1)) ||
              (c->x86_model > 7))
                 if (cpu_has(c, X86_FEATURE_MP))
                         return;
@@ -628,7 +628,7 @@ static void early_init_amd(struct cpuinfo_x86 *c)
         /*  Set MTRR capability flag if appropriate */
         if (c->x86 == 5)
                 if (c->x86_model == 13 || c->x86_model == 9 ||
-                    (c->x86_model == 8 && c->x86_mask >= 8))
+                    (c->x86_model == 8 && c->x86_stepping >= 8))
                         set_cpu_cap(c, X86_FEATURE_K6_MTRR);
 #endif
 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
@@ -795,7 +795,7 @@ static void init_amd_zn(struct cpuinfo_x86 *c)
          * Fix erratum 1076: CPB feature bit not being set in CPUID. It affects
          * all up to and including B1.
          */
-        if (c->x86_model <= 1 && c->x86_mask <= 1)
+        if (c->x86_model <= 1 && c->x86_stepping <= 1)
                 set_cpu_cap(c, X86_FEATURE_CPB);
 }
 
@@ -906,11 +906,11 @@ static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
         /* AMD errata T13 (order #21922) */
         if ((c->x86 == 6)) {
                 /* Duron Rev A0 */
-                if (c->x86_model == 3 && c->x86_mask == 0)
+                if (c->x86_model == 3 && c->x86_stepping == 0)
                         size = 64;
                 /* Tbird rev A1/A2 */
                 if (c->x86_model == 4 &&
-                        (c->x86_mask == 0 || c->x86_mask == 1))
+                        (c->x86_stepping == 0 || c->x86_stepping == 1))
                         size = 256;
         }
         return size;
@@ -1047,7 +1047,7 @@ static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
         }
 
         /* OSVW unavailable or ID unknown, match family-model-stepping range */
-        ms = (cpu->x86_model << 4) | cpu->x86_mask;
+        ms = (cpu->x86_model << 4) | cpu->x86_stepping;
         while ((range = *erratum++))
                 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
                     (ms >= AMD_MODEL_RANGE_START(range)) &&
diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index 71949bf2de5a..bfca937bdcc3 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -162,8 +162,7 @@ static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
         if (cmdline_find_option_bool(boot_command_line, "nospectre_v2"))
                 return SPECTRE_V2_CMD_NONE;
         else {
-                ret = cmdline_find_option(boot_command_line, "spectre_v2", arg,
-                                          sizeof(arg));
+                ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg));
                 if (ret < 0)
                         return SPECTRE_V2_CMD_AUTO;
 
@@ -175,8 +174,7 @@ static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
                 }
 
                 if (i >= ARRAY_SIZE(mitigation_options)) {
-                        pr_err("unknown option (%s). Switching to AUTO select\n",
-                               mitigation_options[i].option);
+                        pr_err("unknown option (%s). Switching to AUTO select\n", arg);
                         return SPECTRE_V2_CMD_AUTO;
                 }
         }
@@ -185,8 +183,7 @@ static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
              cmd == SPECTRE_V2_CMD_RETPOLINE_AMD ||
              cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) &&
             !IS_ENABLED(CONFIG_RETPOLINE)) {
-                pr_err("%s selected but not compiled in. Switching to AUTO select\n",
-                       mitigation_options[i].option);
+                pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option);
                 return SPECTRE_V2_CMD_AUTO;
         }
 
@@ -256,14 +253,14 @@ static void __init spectre_v2_select_mitigation(void)
                         goto retpoline_auto;
                 break;
         }
-        pr_err("kernel not compiled with retpoline; no mitigation available!");
+        pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!");
         return;
 
 retpoline_auto:
         if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
         retpoline_amd:
                 if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
-                        pr_err("LFENCE not serializing. Switching to generic retpoline\n");
+                        pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");
                         goto retpoline_generic;
                 }
                 mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD :
@@ -281,7 +278,7 @@ retpoline_auto:
         pr_info("%s\n", spectre_v2_strings[mode]);
 
         /*
-         * If neither SMEP or KPTI are available, there is a risk of
+         * If neither SMEP nor PTI are available, there is a risk of
          * hitting userspace addresses in the RSB after a context switch
          * from a shallow call stack to a deeper one. To prevent this fill
          * the entire RSB, even when using IBRS.
@@ -295,21 +292,29 @@ retpoline_auto:
         if ((!boot_cpu_has(X86_FEATURE_PTI) &&
              !boot_cpu_has(X86_FEATURE_SMEP)) || is_skylake_era()) {
                 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
-                pr_info("Filling RSB on context switch\n");
+                pr_info("Spectre v2 mitigation: Filling RSB on context switch\n");
         }
 
         /* Initialize Indirect Branch Prediction Barrier if supported */
         if (boot_cpu_has(X86_FEATURE_IBPB)) {
                 setup_force_cpu_cap(X86_FEATURE_USE_IBPB);
-                pr_info("Enabling Indirect Branch Prediction Barrier\n");
+                pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n");
+        }
+
+        /*
+         * Retpoline means the kernel is safe because it has no indirect
+         * branches. But firmware isn't, so use IBRS to protect that.
+         */
+        if (boot_cpu_has(X86_FEATURE_IBRS)) {
+                setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW);
+                pr_info("Enabling Restricted Speculation for firmware calls\n");
         }
 }
 
 #undef pr_fmt
 
 #ifdef CONFIG_SYSFS
-ssize_t cpu_show_meltdown(struct device *dev,
-                          struct device_attribute *attr, char *buf)
+ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
 {
         if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
                 return sprintf(buf, "Not affected\n");
@@ -318,28 +323,21 @@ ssize_t cpu_show_meltdown(struct device *dev,
         return sprintf(buf, "Vulnerable\n");
 }
 
-ssize_t cpu_show_spectre_v1(struct device *dev,
-                            struct device_attribute *attr, char *buf)
+ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
 {
         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V1))
                 return sprintf(buf, "Not affected\n");
         return sprintf(buf, "Mitigation: __user pointer sanitization\n");
 }
 
-ssize_t cpu_show_spectre_v2(struct device *dev,
-                            struct device_attribute *attr, char *buf)
+ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
 {
         if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
                 return sprintf(buf, "Not affected\n");
 
-        return sprintf(buf, "%s%s%s\n", spectre_v2_strings[spectre_v2_enabled],
+        return sprintf(buf, "%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled],
                        boot_cpu_has(X86_FEATURE_USE_IBPB) ? ", IBPB" : "",
+                       boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "",
                        spectre_v2_module_string());
 }
 #endif
-
-void __ibp_barrier(void)
-{
-        __wrmsr(MSR_IA32_PRED_CMD, PRED_CMD_IBPB, 0);
-}
-EXPORT_SYMBOL_GPL(__ibp_barrier);
diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index c578cd29c2d2..e5ec0f11c0de 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -140,7 +140,7 @@ static void init_centaur(struct cpuinfo_x86 *c)
                         clear_cpu_cap(c, X86_FEATURE_TSC);
                         break;
                 case 8:
-                        switch (c->x86_mask) {
+                        switch (c->x86_stepping) {
                         default:
                         name = "2";
                                 break;
@@ -215,7 +215,7 @@ centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size)
          *  - Note, it seems this may only be in engineering samples.
          */
         if ((c->x86 == 6) && (c->x86_model == 9) &&
-                                (c->x86_mask == 1) && (size == 65))
+                                (c->x86_stepping == 1) && (size == 65))
                 size -= 1;
         return size;
 }
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index d63f4b5706e4..348cf4821240 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -731,7 +731,7 @@ void cpu_detect(struct cpuinfo_x86 *c)
                 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
                 c->x86          = x86_family(tfms);
                 c->x86_model    = x86_model(tfms);
-                c->x86_mask     = x86_stepping(tfms);
+                c->x86_stepping = x86_stepping(tfms);
 
                 if (cap0 & (1<<19)) {
                         c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
@@ -1184,9 +1184,9 @@ static void identify_cpu(struct cpuinfo_x86 *c)
         int i;
 
         c->loops_per_jiffy = loops_per_jiffy;
-        c->x86_cache_size = -1;
+        c->x86_cache_size = 0;
         c->x86_vendor = X86_VENDOR_UNKNOWN;
-        c->x86_model = c->x86_mask = 0; /* So far unknown... */
+        c->x86_model = c->x86_stepping = 0;     /* So far unknown... */
         c->x86_vendor_id[0] = '\0'; /* Unset */
         c->x86_model_id[0] = '\0';  /* Unset */
         c->x86_max_cores = 1;
@@ -1378,8 +1378,8 @@ void print_cpu_info(struct cpuinfo_x86 *c)
 
         pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
 
-        if (c->x86_mask || c->cpuid_level >= 0)
-                pr_cont(", stepping: 0x%x)\n", c->x86_mask);
+        if (c->x86_stepping || c->cpuid_level >= 0)
+                pr_cont(", stepping: 0x%x)\n", c->x86_stepping);
         else
                 pr_cont(")\n");
 }
@@ -1749,3 +1749,33 @@ static int __init init_cpu_syscore(void)
         return 0;
 }
 core_initcall(init_cpu_syscore);
+
+/*
+ * The microcode loader calls this upon late microcode load to recheck features,
+ * only when microcode has been updated. Caller holds microcode_mutex and CPU
+ * hotplug lock.
+ */
+void microcode_check(void)
+{
+        struct cpuinfo_x86 info;
+
+        perf_check_microcode();
+
+        /* Reload CPUID max function as it might've changed. */
+        info.cpuid_level = cpuid_eax(0);
+
+        /*
+         * Copy all capability leafs to pick up the synthetic ones so that
+         * memcmp() below doesn't fail on that. The ones coming from CPUID will
+         * get overwritten in get_cpu_cap().
+         */
+        memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability));
+
+        get_cpu_cap(&info);
+
+        if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)))
+                return;
+
+        pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n");
+        pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n");
+}
diff --git a/arch/x86/kernel/cpu/cyrix.c b/arch/x86/kernel/cpu/cyrix.c
index 6b4bb335641f..8949b7ae6d92 100644
--- a/arch/x86/kernel/cpu/cyrix.c
+++ b/arch/x86/kernel/cpu/cyrix.c
@@ -215,7 +215,7 @@ static void init_cyrix(struct cpuinfo_x86 *c)
 
         /* common case step number/rev -- exceptions handled below */
         c->x86_model = (dir1 >> 4) + 1;
-        c->x86_mask = dir1 & 0xf;
+        c->x86_stepping = dir1 & 0xf;
 
         /* Now cook; the original recipe is by Channing Corn, from Cyrix.
          * We do the same thing for each generation: we work out
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 319bf989fad1..d19e903214b4 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -116,14 +116,13 @@ struct sku_microcode {
         u32 microcode;
 };
 static const struct sku_microcode spectre_bad_microcodes[] = {
-        { INTEL_FAM6_KABYLAKE_DESKTOP,  0x0B,   0x84 },
-        { INTEL_FAM6_KABYLAKE_DESKTOP,  0x0A,   0x84 },
-        { INTEL_FAM6_KABYLAKE_DESKTOP,  0x09,   0x84 },
-        { INTEL_FAM6_KABYLAKE_MOBILE,   0x0A,   0x84 },
-        { INTEL_FAM6_KABYLAKE_MOBILE,   0x09,   0x84 },
+        { INTEL_FAM6_KABYLAKE_DESKTOP,  0x0B,   0x80 },
+        { INTEL_FAM6_KABYLAKE_DESKTOP,  0x0A,   0x80 },
+        { INTEL_FAM6_KABYLAKE_DESKTOP,  0x09,   0x80 },
+        { INTEL_FAM6_KABYLAKE_MOBILE,   0x0A,   0x80 },
+        { INTEL_FAM6_KABYLAKE_MOBILE,   0x09,   0x80 },
         { INTEL_FAM6_SKYLAKE_X,         0x03,   0x0100013e },
         { INTEL_FAM6_SKYLAKE_X,         0x04,   0x0200003c },
-        { INTEL_FAM6_SKYLAKE_MOBILE,    0x03,   0xc2 },
         { INTEL_FAM6_SKYLAKE_DESKTOP,   0x03,   0xc2 },
         { INTEL_FAM6_BROADWELL_CORE,    0x04,   0x28 },
         { INTEL_FAM6_BROADWELL_GT3E,    0x01,   0x1b },
@@ -136,8 +135,6 @@ static const struct sku_microcode spectre_bad_microcodes[] = {
         { INTEL_FAM6_HASWELL_X,         0x02,   0x3b },
         { INTEL_FAM6_HASWELL_X,         0x04,   0x10 },
         { INTEL_FAM6_IVYBRIDGE_X,       0x04,   0x42a },
-        /* Updated in the 20180108 release; blacklist until we know otherwise */
-        { INTEL_FAM6_ATOM_GEMINI_LAKE,  0x01,   0x22 },
         /* Observed in the wild */
         { INTEL_FAM6_SANDYBRIDGE_X,     0x06,   0x61b },
         { INTEL_FAM6_SANDYBRIDGE_X,     0x07,   0x712 },
@@ -149,7 +146,7 @@ static bool bad_spectre_microcode(struct cpuinfo_x86 *c)
 
         for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) {
                 if (c->x86_model == spectre_bad_microcodes[i].model &&
-                    c->x86_mask == spectre_bad_microcodes[i].stepping)
+                    c->x86_stepping == spectre_bad_microcodes[i].stepping)
                         return (c->microcode <= spectre_bad_microcodes[i].microcode);
         }
         return false;
@@ -196,7 +193,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)
          * need the microcode to have already been loaded... so if it is
          * not, recommend a BIOS update and disable large pages.
          */
-        if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 &&
+        if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_stepping <= 2 &&
             c->microcode < 0x20e) {
                 pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n");
                 clear_cpu_cap(c, X86_FEATURE_PSE);
@@ -212,7 +209,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)
 
         /* CPUID workaround for 0F33/0F34 CPU */
         if (c->x86 == 0xF && c->x86_model == 0x3
-            && (c->x86_mask == 0x3 || c->x86_mask == 0x4))
+            && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4))
                 c->x86_phys_bits = 36;
 
         /*
@@ -310,7 +307,7 @@ int ppro_with_ram_bug(void)
         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
             boot_cpu_data.x86 == 6 &&
             boot_cpu_data.x86_model == 1 &&
-            boot_cpu_data.x86_mask < 8) {
+            boot_cpu_data.x86_stepping < 8) {
                 pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n");
                 return 1;
         }
@@ -327,7 +324,7 @@ static void intel_smp_check(struct cpuinfo_x86 *c)
          * Mask B, Pentium, but not Pentium MMX
          */
         if (c->x86 == 5 &&
-            c->x86_mask >= 1 && c->x86_mask <= 4 &&
+            c->x86_stepping >= 1 && c->x86_stepping <= 4 &&
             c->x86_model <= 3) {
                 /*
                  * Remember we have B step Pentia with bugs
@@ -370,7 +367,7 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
          * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
          * model 3 mask 3
          */
-        if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
+        if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633)
                 clear_cpu_cap(c, X86_FEATURE_SEP);
 
         /*
@@ -388,7 +385,7 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
          * P4 Xeon erratum 037 workaround.
          * Hardware prefetcher may cause stale data to be loaded into the cache.
          */
-        if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
+        if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) {
                 if (msr_set_bit(MSR_IA32_MISC_ENABLE,
                                 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) {
                         pr_info("CPU: C0 stepping P4 Xeon detected.\n");
@@ -403,7 +400,7 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
          * Specification Update").
          */
         if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
-            (c->x86_mask < 0x6 || c->x86_mask == 0xb))
+            (c->x86_stepping < 0x6 || c->x86_stepping == 0xb))
                 set_cpu_bug(c, X86_BUG_11AP);
 
 
@@ -650,7 +647,7 @@ static void init_intel(struct cpuinfo_x86 *c)
                 case 6:
                         if (l2 == 128)
                                 p = "Celeron (Mendocino)";
-                        else if (c->x86_mask == 0 || c->x86_mask == 5)
+                        else if (c->x86_stepping == 0 || c->x86_stepping == 5)
                                 p = "Celeron-A";
                         break;
 
diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c
index 410629f10ad3..589b948e6e01 100644
--- a/arch/x86/kernel/cpu/intel_rdt.c
+++ b/arch/x86/kernel/cpu/intel_rdt.c
@@ -819,7 +819,7 @@ static __init void rdt_quirks(void)
                         cache_alloc_hsw_probe();
                 break;
         case INTEL_FAM6_SKYLAKE_X:
-                if (boot_cpu_data.x86_mask <= 4)
+                if (boot_cpu_data.x86_stepping <= 4)
                         set_rdt_options("!cmt,!mbmtotal,!mbmlocal,!l3cat");
         }
 }
diff --git a/arch/x86/kernel/cpu/intel_rdt_rdtgroup.c b/arch/x86/kernel/cpu/intel_rdt_rdtgroup.c
index bdab7d2f51af..fca759d272a1 100644
--- a/arch/x86/kernel/cpu/intel_rdt_rdtgroup.c
+++ b/arch/x86/kernel/cpu/intel_rdt_rdtgroup.c
@@ -1804,6 +1804,7 @@ static int rdtgroup_mkdir_ctrl_mon(struct kernfs_node *parent_kn,
                 goto out_common_fail;
         }
         closid = ret;
+        ret = 0;
 
         rdtgrp->closid = closid;
         list_add(&rdtgrp->rdtgroup_list, &rdt_all_groups);
diff --git a/arch/x86/kernel/cpu/mcheck/mce-internal.h b/arch/x86/kernel/cpu/mcheck/mce-internal.h
index aa0d5df9dc60..e956eb267061 100644
--- a/arch/x86/kernel/cpu/mcheck/mce-internal.h
+++ b/arch/x86/kernel/cpu/mcheck/mce-internal.h
@@ -115,4 +115,19 @@ static inline void mce_unregister_injector_chain(struct notifier_block *nb)	{ }
 
 extern struct mca_config mca_cfg;
 
+#ifndef CONFIG_X86_64
+/*
+ * On 32-bit systems it would be difficult to safely unmap a poison page
+ * from the kernel 1:1 map because there are no non-canonical addresses that
+ * we can use to refer to the address without risking a speculative access.
+ * However, this isn't much of an issue because:
+ * 1) Few unmappable pages are in the 1:1 map. Most are in HIGHMEM which
+ *    are only mapped into the kernel as needed
+ * 2) Few people would run a 32-bit kernel on a machine that supports
+ *    recoverable errors because they have too much memory to boot 32-bit.
+ */
+static inline void mce_unmap_kpfn(unsigned long pfn) {}
+#define mce_unmap_kpfn mce_unmap_kpfn
+#endif
+
 #endif /* __X86_MCE_INTERNAL_H__ */
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 3a8e88a611eb..8ff94d1e2dce 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -105,6 +105,10 @@ static struct irq_work mce_irq_work;
 
 static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs);
 
+#ifndef mce_unmap_kpfn
+static void mce_unmap_kpfn(unsigned long pfn);
+#endif
+
 /*
  * CPU/chipset specific EDAC code can register a notifier call here to print
  * MCE errors in a human-readable form.
@@ -234,7 +238,7 @@ static void __print_mce(struct mce *m)
                         m->cs, m->ip);
 
                 if (m->cs == __KERNEL_CS)
-                        pr_cont("{%pS}", (void *)m->ip);
+                        pr_cont("{%pS}", (void *)(unsigned long)m->ip);
                 pr_cont("\n");
         }
 
@@ -590,7 +594,8 @@ static int srao_decode_notifier(struct notifier_block *nb, unsigned long val,
 
         if (mce_usable_address(mce) && (mce->severity == MCE_AO_SEVERITY)) {
                 pfn = mce->addr >> PAGE_SHIFT;
-                memory_failure(pfn, 0);
+                if (!memory_failure(pfn, 0))
+                        mce_unmap_kpfn(pfn);
         }
 
         return NOTIFY_OK;
@@ -1057,12 +1062,13 @@ static int do_memory_failure(struct mce *m)
         ret = memory_failure(m->addr >> PAGE_SHIFT, flags);
         if (ret)
                 pr_err("Memory error not recovered");
+        else
+                mce_unmap_kpfn(m->addr >> PAGE_SHIFT);
         return ret;
 }
 
-#if defined(arch_unmap_kpfn) && defined(CONFIG_MEMORY_FAILURE)
-
-void arch_unmap_kpfn(unsigned long pfn)
+#ifndef mce_unmap_kpfn
+static void mce_unmap_kpfn(unsigned long pfn)
 {
         unsigned long decoy_addr;
 
@@ -1073,7 +1079,7 @@ void arch_unmap_kpfn(unsigned long pfn)
          * We would like to just call:
          *      set_memory_np((unsigned long)pfn_to_kaddr(pfn), 1);
          * but doing that would radically increase the odds of a
-         * speculative access to the posion page because we'd have
+         * speculative access to the poison page because we'd have
          * the virtual address of the kernel 1:1 mapping sitting
          * around in registers.
          * Instead we get tricky.  We create a non-canonical address
@@ -1098,7 +1104,6 @@ void arch_unmap_kpfn(unsigned long pfn)
 
         if (set_memory_np(decoy_addr, 1))
                 pr_warn("Could not invalidate pfn=0x%lx from 1:1 map\n", pfn);
-
 }
 #endif
 
diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/microcode/amd.c
index 330b8462d426..a998e1a7d46f 100644
--- a/arch/x86/kernel/cpu/microcode/amd.c
+++ b/arch/x86/kernel/cpu/microcode/amd.c
@@ -498,7 +498,7 @@ static unsigned int verify_patch_size(u8 family, u32 patch_size,
         return patch_size;
 }
 
-static int apply_microcode_amd(int cpu)
+static enum ucode_state apply_microcode_amd(int cpu)
 {
         struct cpuinfo_x86 *c = &cpu_data(cpu);
         struct microcode_amd *mc_amd;
@@ -512,7 +512,7 @@ static int apply_microcode_amd(int cpu)
 
         p = find_patch(cpu);
         if (!p)
-                return 0;
+                return UCODE_NFOUND;
 
         mc_amd  = p->data;
         uci->mc = p->data;
@@ -523,13 +523,13 @@ static int apply_microcode_amd(int cpu)
         if (rev >= mc_amd->hdr.patch_id) {
                 c->microcode = rev;
                 uci->cpu_sig.rev = rev;
-                return 0;
+                return UCODE_OK;
         }
 
         if (__apply_microcode_amd(mc_amd)) {
                 pr_err("CPU%d: update failed for patch_level=0x%08x\n",
                         cpu, mc_amd->hdr.patch_id);
-                return -1;
+                return UCODE_ERROR;
         }
         pr_info("CPU%d: new patch_level=0x%08x\n", cpu,
                 mc_amd->hdr.patch_id);
@@ -537,7 +537,7 @@ static int apply_microcode_amd(int cpu)
         uci->cpu_sig.rev = mc_amd->hdr.patch_id;
         c->microcode = mc_amd->hdr.patch_id;
 
-        return 0;
+        return UCODE_UPDATED;
 }
 
 static int install_equiv_cpu_table(const u8 *buf)
diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c
index 319dd65f98a2..aa1b9a422f2b 100644
--- a/arch/x86/kernel/cpu/microcode/core.c
+++ b/arch/x86/kernel/cpu/microcode/core.c
@@ -374,7 +374,7 @@ static int collect_cpu_info(int cpu)
 }
 
 struct apply_microcode_ctx {
-        int err;
+        enum ucode_state err;
 };
 
 static void apply_microcode_local(void *arg)
@@ -489,31 +489,30 @@ static void __exit microcode_dev_exit(void)
 /* fake device for request_firmware */
 static struct platform_device   *microcode_pdev;
 
-static int reload_for_cpu(int cpu)
+static enum ucode_state reload_for_cpu(int cpu)
 {
         struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
         enum ucode_state ustate;
-        int err = 0;
 
         if (!uci->valid)
-                return err;
+                return UCODE_OK;
 
         ustate = microcode_ops->request_microcode_fw(cpu, &microcode_pdev->dev, true);
-        if (ustate == UCODE_OK)
-                apply_microcode_on_target(cpu);
-        else
-                if (ustate == UCODE_ERROR)
-                        err = -EINVAL;
-        return err;
+        if (ustate != UCODE_OK)
+                return ustate;
+
+        return apply_microcode_on_target(cpu);
 }
 
 static ssize_t reload_store(struct device *dev,
                             struct device_attribute *attr,
                             const char *buf, size_t size)
 {
+        enum ucode_state tmp_ret = UCODE_OK;
+        bool do_callback = false;
         unsigned long val;
+        ssize_t ret = 0;
         int cpu;
-        ssize_t ret = 0, tmp_ret;
 
         ret = kstrtoul(buf, 0, &val);
         if (ret)
@@ -526,15 +525,21 @@ static ssize_t reload_store(struct device *dev,
         mutex_lock(&microcode_mutex);
         for_each_online_cpu(cpu) {
                 tmp_ret = reload_for_cpu(cpu);
-                if (tmp_ret != 0)
+                if (tmp_ret > UCODE_NFOUND) {
                         pr_warn("Error reloading microcode on CPU %d\n", cpu);
 
-                /* save retval of the first encountered reload error */
-                if (!ret)
-                        ret = tmp_ret;
+                        /* set retval for the first encountered reload error */
+                        if (!ret)
+                                ret = -EINVAL;
+                }
+
+                if (tmp_ret == UCODE_UPDATED)
+                        do_callback = true;
         }
-        if (!ret)
-                perf_check_microcode();
+
+        if (!ret && do_callback)
+                microcode_check();
+
         mutex_unlock(&microcode_mutex);
         put_online_cpus();
 
diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c
index f7c55b0e753a..923054a6b760 100644
--- a/arch/x86/kernel/cpu/microcode/intel.c
+++ b/arch/x86/kernel/cpu/microcode/intel.c
@@ -772,7 +772,7 @@ static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
         return 0;
 }
 
-static int apply_microcode_intel(int cpu)
+static enum ucode_state apply_microcode_intel(int cpu)
 {
         struct microcode_intel *mc;
         struct ucode_cpu_info *uci;
@@ -782,7 +782,7 @@ static int apply_microcode_intel(int cpu)
 
         /* We should bind the task to the CPU */
         if (WARN_ON(raw_smp_processor_id() != cpu))
-                return -1;
+                return UCODE_ERROR;
 
         uci = ucode_cpu_info + cpu;
         mc = uci->mc;
@@ -790,7 +790,7 @@ static int apply_microcode_intel(int cpu)
                 /* Look for a newer patch in our cache: */
                 mc = find_patch(uci);
                 if (!mc)
-                        return 0;
+                        return UCODE_NFOUND;
         }
 
         /* write microcode via MSR 0x79 */
@@ -801,7 +801,7 @@ static int apply_microcode_intel(int cpu)
         if (rev != mc->hdr.rev) {
                 pr_err("CPU%d update to revision 0x%x failed\n",
                        cpu, mc->hdr.rev);
-                return -1;
+                return UCODE_ERROR;
         }
 
         if (rev != prev_rev) {
@@ -818,7 +818,7 @@ static int apply_microcode_intel(int cpu)
         uci->cpu_sig.rev = rev;
         c->microcode = rev;
 
-        return 0;
+        return UCODE_UPDATED;
 }
 
 static enum ucode_state generic_load_microcode(int cpu, void *data, size_t size,
@@ -921,7 +921,7 @@ static bool is_blacklisted(unsigned int cpu)
          */
         if (c->x86 == 6 &&
             c->x86_model == INTEL_FAM6_BROADWELL_X &&
-            c->x86_mask == 0x01 &&
+            c->x86_stepping == 0x01 &&
             llc_size_per_core > 2621440 &&
             c->microcode < 0x0b000021) {
                 pr_err_once("Erratum BDF90: late loading with revision < 0x0b000021 (0x%x) disabled.\n", c->microcode);
@@ -944,7 +944,7 @@ static enum ucode_state request_microcode_fw(int cpu, struct device *device,
                 return UCODE_NFOUND;
 
         sprintf(name, "intel-ucode/%02x-%02x-%02x",
-                c->x86, c->x86_model, c->x86_mask);
+                c->x86, c->x86_model, c->x86_stepping);
 
         if (request_firmware_direct(&firmware, name, device)) {
                 pr_debug("data file %s load failed\n", name);
@@ -982,7 +982,7 @@ static struct microcode_ops microcode_intel_ops = {
 
 static int __init calc_llc_size_per_core(struct cpuinfo_x86 *c)
 {
-        u64 llc_size = c->x86_cache_size * 1024;
+        u64 llc_size = c->x86_cache_size * 1024ULL;
 
         do_div(llc_size, c->x86_max_cores);
 
diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c
index fdc55215d44d..e12ee86906c6 100644
--- a/arch/x86/kernel/cpu/mtrr/generic.c
+++ b/arch/x86/kernel/cpu/mtrr/generic.c
@@ -859,7 +859,7 @@ int generic_validate_add_page(unsigned long base, unsigned long size,
          */
         if (is_cpu(INTEL) && boot_cpu_data.x86 == 6 &&
             boot_cpu_data.x86_model == 1 &&
-            boot_cpu_data.x86_mask <= 7) {
+            boot_cpu_data.x86_stepping <= 7) {
                 if (base & ((1 << (22 - PAGE_SHIFT)) - 1)) {
                         pr_warn("mtrr: base(0x%lx000) is not 4 MiB aligned\n", base);
                         return -EINVAL;
diff --git a/arch/x86/kernel/cpu/mtrr/main.c b/arch/x86/kernel/cpu/mtrr/main.c
index 40d5a8a75212..7468de429087 100644
--- a/arch/x86/kernel/cpu/mtrr/main.c
+++ b/arch/x86/kernel/cpu/mtrr/main.c
@@ -711,8 +711,8 @@ void __init mtrr_bp_init(void)
                         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
                             boot_cpu_data.x86 == 0xF &&
                             boot_cpu_data.x86_model == 0x3 &&
-                            (boot_cpu_data.x86_mask == 0x3 ||
-                             boot_cpu_data.x86_mask == 0x4))
+                            (boot_cpu_data.x86_stepping == 0x3 ||
+                             boot_cpu_data.x86_stepping == 0x4))
                                 phys_addr = 36;
 
                         size_or_mask = SIZE_OR_MASK_BITS(phys_addr);
diff --git a/arch/x86/kernel/cpu/proc.c b/arch/x86/kernel/cpu/proc.c
index e7ecedafa1c8..2c8522a39ed5 100644
--- a/arch/x86/kernel/cpu/proc.c
+++ b/arch/x86/kernel/cpu/proc.c
@@ -72,8 +72,8 @@ static int show_cpuinfo(struct seq_file *m, void *v)
                    c->x86_model,
                    c->x86_model_id[0] ? c->x86_model_id : "unknown");
 
-        if (c->x86_mask || c->cpuid_level >= 0)
-                seq_printf(m, "stepping\t: %d\n", c->x86_mask);
+        if (c->x86_stepping || c->cpuid_level >= 0)
+                seq_printf(m, "stepping\t: %d\n", c->x86_stepping);
         else
                 seq_puts(m, "stepping\t: unknown\n");
         if (c->microcode)
@@ -91,8 +91,8 @@ static int show_cpuinfo(struct seq_file *m, void *v)
         }
 
         /* Cache size */
-        if (c->x86_cache_size >= 0)
-                seq_printf(m, "cache size\t: %d KB\n", c->x86_cache_size);
+        if (c->x86_cache_size)
+                seq_printf(m, "cache size\t: %u KB\n", c->x86_cache_size);
 
         show_cpuinfo_core(m, c, cpu);
         show_cpuinfo_misc(m, c);
diff --git a/arch/x86/kernel/head_32.S b/arch/x86/kernel/head_32.S
index c29020907886..b59e4fb40fd9 100644
--- a/arch/x86/kernel/head_32.S
+++ b/arch/x86/kernel/head_32.S
@@ -37,7 +37,7 @@
 #define X86             new_cpu_data+CPUINFO_x86
 #define X86_VENDOR      new_cpu_data+CPUINFO_x86_vendor
 #define X86_MODEL       new_cpu_data+CPUINFO_x86_model
-#define X86_MASK        new_cpu_data+CPUINFO_x86_mask
+#define X86_STEPPING    new_cpu_data+CPUINFO_x86_stepping
 #define X86_HARD_MATH   new_cpu_data+CPUINFO_hard_math
 #define X86_CPUID       new_cpu_data+CPUINFO_cpuid_level
 #define X86_CAPABILITY  new_cpu_data+CPUINFO_x86_capability
@@ -332,7 +332,7 @@ ENTRY(startup_32_smp)
         shrb $4,%al
         movb %al,X86_MODEL
         andb $0x0f,%cl          # mask mask revision
-        movb %cl,X86_MASK
+        movb %cl,X86_STEPPING
         movl %edx,X86_CAPABILITY
 
 .Lis486:
diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S
index 04a625f0fcda..0f545b3cf926 100644
--- a/arch/x86/kernel/head_64.S
+++ b/arch/x86/kernel/head_64.S
@@ -23,6 +23,7 @@
 #include <asm/nops.h>
 #include "../entry/calling.h"
 #include <asm/export.h>
+#include <asm/nospec-branch.h>
 
 #ifdef CONFIG_PARAVIRT
 #include <asm/asm-offsets.h>
@@ -134,6 +135,7 @@ ENTRY(secondary_startup_64)
 
         /* Ensure I am executing from virtual addresses */
         movq    $1f, %rax
+        ANNOTATE_RETPOLINE_SAFE
         jmp     *%rax
 1:
         UNWIND_HINT_EMPTY
diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c
index 4e37d1a851a6..bc1a27280c4b 100644
--- a/arch/x86/kernel/kvm.c
+++ b/arch/x86/kernel/kvm.c
@@ -49,7 +49,7 @@
 
 static int kvmapf = 1;
 
-static int parse_no_kvmapf(char *arg)
+static int __init parse_no_kvmapf(char *arg)
 {
         kvmapf = 0;
         return 0;
@@ -58,7 +58,7 @@ static int parse_no_kvmapf(char *arg)
 early_param("no-kvmapf", parse_no_kvmapf);
 
 static int steal_acc = 1;
-static int parse_no_stealacc(char *arg)
+static int __init parse_no_stealacc(char *arg)
 {
         steal_acc = 0;
         return 0;
@@ -67,7 +67,7 @@ static int parse_no_stealacc(char *arg)
 early_param("no-steal-acc", parse_no_stealacc);
 
 static int kvmclock_vsyscall = 1;
-static int parse_no_kvmclock_vsyscall(char *arg)
+static int __init parse_no_kvmclock_vsyscall(char *arg)
 {
         kvmclock_vsyscall = 0;
         return 0;
@@ -341,10 +341,10 @@ static void kvm_guest_cpu_init(void)
 #endif
                 pa |= KVM_ASYNC_PF_ENABLED;
 
-                /* Async page fault support for L1 hypervisor is optional */
-                if (wrmsr_safe(MSR_KVM_ASYNC_PF_EN,
-                        (pa | KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT) & 0xffffffff, pa >> 32) < 0)
-                        wrmsrl(MSR_KVM_ASYNC_PF_EN, pa);
+                if (kvm_para_has_feature(KVM_FEATURE_ASYNC_PF_VMEXIT))
+                        pa |= KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
+
+                wrmsrl(MSR_KVM_ASYNC_PF_EN, pa);
                 __this_cpu_write(apf_reason.enabled, 1);
                 printk(KERN_INFO"KVM setup async PF for cpu %d\n",
                        smp_processor_id());
@@ -545,7 +545,8 @@ static void __init kvm_guest_init(void)
                 pv_time_ops.steal_clock = kvm_steal_clock;
         }
 
-        if (kvm_para_has_feature(KVM_FEATURE_PV_TLB_FLUSH))
+        if (kvm_para_has_feature(KVM_FEATURE_PV_TLB_FLUSH) &&
+            !kvm_para_has_feature(KVM_FEATURE_STEAL_TIME))
                 pv_mmu_ops.flush_tlb_others = kvm_flush_tlb_others;
 
         if (kvm_para_has_feature(KVM_FEATURE_PV_EOI))
@@ -633,7 +634,8 @@ static __init int kvm_setup_pv_tlb_flush(void)
 {
         int cpu;
 
-        if (kvm_para_has_feature(KVM_FEATURE_PV_TLB_FLUSH)) {
+        if (kvm_para_has_feature(KVM_FEATURE_PV_TLB_FLUSH) &&
+            !kvm_para_has_feature(KVM_FEATURE_STEAL_TIME)) {
                 for_each_possible_cpu(cpu) {
                         zalloc_cpumask_var_node(per_cpu_ptr(&__pv_tlb_mask, cpu),
                                 GFP_KERNEL, cpu_to_node(cpu));
diff --git a/arch/x86/kernel/machine_kexec_64.c b/arch/x86/kernel/machine_kexec_64.c
index 1f790cf9d38f..3b7427aa7d85 100644
--- a/arch/x86/kernel/machine_kexec_64.c
+++ b/arch/x86/kernel/machine_kexec_64.c
@@ -542,6 +542,7 @@ int arch_kexec_apply_relocations_add(const Elf64_Ehdr *ehdr,
                                 goto overflow;
                         break;
                 case R_X86_64_PC32:
+                case R_X86_64_PLT32:
                         value -= (u64)address;
                         *(u32 *)location = value;
                         break;
diff --git a/arch/x86/kernel/module.c b/arch/x86/kernel/module.c
index da0c160e5589..f58336af095c 100644
--- a/arch/x86/kernel/module.c
+++ b/arch/x86/kernel/module.c
@@ -191,6 +191,7 @@ int apply_relocate_add(Elf64_Shdr *sechdrs,
                                 goto overflow;
                         break;
                 case R_X86_64_PC32:
+                case R_X86_64_PLT32:
                         if (*(u32 *)loc != 0)
                                 goto invalid_relocation;
                         val -= (u64)loc;
diff --git a/arch/x86/kernel/mpparse.c b/arch/x86/kernel/mpparse.c
index 27d0a1712663..f1c5eb99d445 100644
--- a/arch/x86/kernel/mpparse.c
+++ b/arch/x86/kernel/mpparse.c
@@ -410,7 +410,7 @@ static inline void __init construct_default_ISA_mptable(int mpc_default_type)
         processor.apicver = mpc_default_type > 4 ? 0x10 : 0x01;
         processor.cpuflag = CPU_ENABLED;
         processor.cpufeature = (boot_cpu_data.x86 << 8) |
-            (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
+            (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_stepping;
         processor.featureflag = boot_cpu_data.x86_capability[CPUID_1_EDX];
         processor.reserved[0] = 0;
         processor.reserved[1] = 0;
diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c
index 041096bdef86..99dc79e76bdc 100644
--- a/arch/x86/kernel/paravirt.c
+++ b/arch/x86/kernel/paravirt.c
@@ -200,9 +200,9 @@ static void native_flush_tlb_global(void)
         __native_flush_tlb_global();
 }
 
-static void native_flush_tlb_single(unsigned long addr)
+static void native_flush_tlb_one_user(unsigned long addr)
 {
-        __native_flush_tlb_single(addr);
+        __native_flush_tlb_one_user(addr);
 }
 
 struct static_key paravirt_steal_enabled;
@@ -401,7 +401,7 @@ struct pv_mmu_ops pv_mmu_ops __ro_after_init = {
 
         .flush_tlb_user = native_flush_tlb,
         .flush_tlb_kernel = native_flush_tlb_global,
-        .flush_tlb_single = native_flush_tlb_single,
+        .flush_tlb_one_user = native_flush_tlb_one_user,
         .flush_tlb_others = native_flush_tlb_others,
 
         .pgd_alloc = __paravirt_pgd_alloc,
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
index 1ae67e982af7..4c616be28506 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -1204,20 +1204,13 @@ void __init setup_arch(char **cmdline_p)
 
         kasan_init();
 
-#ifdef CONFIG_X86_32
-        /* sync back kernel address range */
-        clone_pgd_range(initial_page_table + KERNEL_PGD_BOUNDARY,
-                        swapper_pg_dir     + KERNEL_PGD_BOUNDARY,
-                        KERNEL_PGD_PTRS);
-
         /*
-         * sync back low identity map too.  It is used for example
-         * in the 32-bit EFI stub.
+         * Sync back kernel address range.
+         *
+         * FIXME: Can the later sync in setup_cpu_entry_areas() replace
+         * this call?
          */
-        clone_pgd_range(initial_page_table,
-                        swapper_pg_dir     + KERNEL_PGD_BOUNDARY,
-                        min(KERNEL_PGD_PTRS, KERNEL_PGD_BOUNDARY));
-#endif
+        sync_initial_page_table();
 
         tboot_probe();
 
diff --git a/arch/x86/kernel/setup_percpu.c b/arch/x86/kernel/setup_percpu.c
index 497aa766fab3..ea554f812ee1 100644
--- a/arch/x86/kernel/setup_percpu.c
+++ b/arch/x86/kernel/setup_percpu.c
@@ -287,24 +287,15 @@ void __init setup_per_cpu_areas(void)
         /* Setup cpu initialized, callin, callout masks */
         setup_cpu_local_masks();
 
-#ifdef CONFIG_X86_32
         /*
          * Sync back kernel address range again.  We already did this in
          * setup_arch(), but percpu data also needs to be available in
          * the smpboot asm.  We can't reliably pick up percpu mappings
          * using vmalloc_fault(), because exception dispatch needs
          * percpu data.
+         *
+         * FIXME: Can the later sync in setup_cpu_entry_areas() replace
+         * this call?
          */
-        clone_pgd_range(initial_page_table + KERNEL_PGD_BOUNDARY,
-                        swapper_pg_dir     + KERNEL_PGD_BOUNDARY,
-                        KERNEL_PGD_PTRS);
-
-        /*
-         * sync back low identity map too.  It is used for example
-         * in the 32-bit EFI stub.
-         */
-        clone_pgd_range(initial_page_table,
-                        swapper_pg_dir     + KERNEL_PGD_BOUNDARY,
-                        min(KERNEL_PGD_PTRS, KERNEL_PGD_BOUNDARY));
-#endif
+        sync_initial_page_table();
 }
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index 6f27facbaa9b..ff99e2b6fc54 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -1281,11 +1281,10 @@ void __init native_smp_prepare_boot_cpu(void)
         cpu_set_state_online(me);
 }
 
-void __init native_smp_cpus_done(unsigned int max_cpus)
+void __init calculate_max_logical_packages(void)
 {
         int ncpus;
 
-        pr_debug("Boot done\n");
         /*
          * Today neither Intel nor AMD support heterogenous systems so
          * extrapolate the boot cpu's data to all packages.
@@ -1293,6 +1292,13 @@ void __init native_smp_cpus_done(unsigned int max_cpus)
         ncpus = cpu_data(0).booted_cores * topology_max_smt_threads();
         __max_logical_packages = DIV_ROUND_UP(nr_cpu_ids, ncpus);
         pr_info("Max logical packages: %u\n", __max_logical_packages);
+}
+
+void __init native_smp_cpus_done(unsigned int max_cpus)
+{
+        pr_debug("Boot done\n");
+
+        calculate_max_logical_packages();
 
         if (x86_has_numa_in_package)
                 set_sched_topology(x86_numa_in_package_topology);
@@ -1430,8 +1436,8 @@ static void remove_siblinginfo(int cpu)
         cpumask_clear(cpu_llc_shared_mask(cpu));
         cpumask_clear(topology_sibling_cpumask(cpu));
         cpumask_clear(topology_core_cpumask(cpu));
-        c->phys_proc_id = 0;
         c->cpu_core_id = 0;
+        c->booted_cores = 0;
         cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
         recompute_smt_state();
 }
diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c
index 446c9ef8cfc3..3d9b2308e7fa 100644
--- a/arch/x86/kernel/traps.c
+++ b/arch/x86/kernel/traps.c
@@ -181,7 +181,7 @@ int fixup_bug(struct pt_regs *regs, int trapnr)
                 break;
 
         case BUG_TRAP_TYPE_WARN:
-                regs->ip += LEN_UD0;
+                regs->ip += LEN_UD2;
                 return 1;
         }
 
diff --git a/arch/x86/kernel/unwind_orc.c b/arch/x86/kernel/unwind_orc.c
index 1f9188f5357c..feb28fee6cea 100644
--- a/arch/x86/kernel/unwind_orc.c
+++ b/arch/x86/kernel/unwind_orc.c
@@ -5,7 +5,6 @@
 #include <asm/unwind.h>
 #include <asm/orc_types.h>
 #include <asm/orc_lookup.h>
-#include <asm/sections.h>
 
 #define orc_warn(fmt, ...) \
         printk_deferred_once(KERN_WARNING pr_fmt("WARNING: " fmt), ##__VA_ARGS__)
@@ -148,7 +147,7 @@ static struct orc_entry *orc_find(unsigned long ip)
         }
 
         /* vmlinux .init slow lookup: */
-        if (ip >= (unsigned long)_sinittext && ip < (unsigned long)_einittext)
+        if (init_kernel_text(ip))
                 return __orc_find(__start_orc_unwind_ip, __start_orc_unwind,
                                   __stop_orc_unwind_ip - __start_orc_unwind_ip, ip);
 
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index a0c5a69bc7c4..b671fc2d0422 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -607,7 +607,8 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
                              (1 << KVM_FEATURE_PV_EOI) |
                              (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT) |
                              (1 << KVM_FEATURE_PV_UNHALT) |
-                             (1 << KVM_FEATURE_PV_TLB_FLUSH);
+                             (1 << KVM_FEATURE_PV_TLB_FLUSH) |
+                             (1 << KVM_FEATURE_ASYNC_PF_VMEXIT);
 
                 if (sched_info_on())
                         entry->eax |= (1 << KVM_FEATURE_STEAL_TIME);
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 924ac8ce9d50..391dda8d43b7 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -2002,14 +2002,13 @@ void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
 
 void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
 {
-        struct kvm_lapic *apic;
+        struct kvm_lapic *apic = vcpu->arch.apic;
         int i;
 
-        apic_debug("%s\n", __func__);
+        if (!apic)
+                return;
 
-        ASSERT(vcpu);
-        apic = vcpu->arch.apic;
-        ASSERT(apic != NULL);
+        apic_debug("%s\n", __func__);
 
         /* Stop the timer in case it's a reset to an active apic */
         hrtimer_cancel(&apic->lapic_timer.timer);
@@ -2165,7 +2164,6 @@ int kvm_create_lapic(struct kvm_vcpu *vcpu)
          */
         vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
         static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
-        kvm_lapic_reset(vcpu, false);
         kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
 
         return 0;
@@ -2569,7 +2567,6 @@ void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
 
         pe = xchg(&apic->pending_events, 0);
         if (test_bit(KVM_APIC_INIT, &pe)) {
-                kvm_lapic_reset(vcpu, true);
                 kvm_vcpu_reset(vcpu, true);
                 if (kvm_vcpu_is_bsp(apic->vcpu))
                         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
index 8eca1d04aeb8..f551962ac294 100644
--- a/arch/x86/kvm/mmu.c
+++ b/arch/x86/kvm/mmu.c
@@ -3029,7 +3029,7 @@ static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn)
                 return RET_PF_RETRY;
         }
 
-        return -EFAULT;
+        return RET_PF_EMULATE;
 }
 
 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
@@ -5080,7 +5080,7 @@ void kvm_mmu_uninit_vm(struct kvm *kvm)
 typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head);
 
 /* The caller should hold mmu-lock before calling this function. */
-static bool
+static __always_inline bool
 slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot,
                         slot_level_handler fn, int start_level, int end_level,
                         gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb)
@@ -5110,7 +5110,7 @@ slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot,
         return flush;
 }
 
-static bool
+static __always_inline bool
 slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
                   slot_level_handler fn, int start_level, int end_level,
                   bool lock_flush_tlb)
@@ -5121,7 +5121,7 @@ slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
                         lock_flush_tlb);
 }
 
-static bool
+static __always_inline bool
 slot_handle_all_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
                       slot_level_handler fn, bool lock_flush_tlb)
 {
@@ -5129,7 +5129,7 @@ slot_handle_all_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
                                  PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
 }
 
-static bool
+static __always_inline bool
 slot_handle_large_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
                         slot_level_handler fn, bool lock_flush_tlb)
 {
@@ -5137,7 +5137,7 @@ slot_handle_large_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
                                  PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
 }
 
-static bool
+static __always_inline bool
 slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot,
                  slot_level_handler fn, bool lock_flush_tlb)
 {
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index b3e488a74828..be9c839e2c89 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -49,6 +49,7 @@
 #include <asm/debugreg.h>
 #include <asm/kvm_para.h>
 #include <asm/irq_remapping.h>
+#include <asm/microcode.h>
 #include <asm/nospec-branch.h>
 
 #include <asm/virtext.h>
@@ -178,6 +179,8 @@ struct vcpu_svm {
         uint64_t sysenter_eip;
         uint64_t tsc_aux;
 
+        u64 msr_decfg;
+
         u64 next_rip;
 
         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
@@ -300,6 +303,8 @@ module_param(vgif, int, 0444);
 static int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
 module_param(sev, int, 0444);
 
+static u8 rsm_ins_bytes[] = "\x0f\xaa";
+
 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
 static void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa);
 static void svm_complete_interrupts(struct vcpu_svm *svm);
@@ -1383,6 +1388,7 @@ static void init_vmcb(struct vcpu_svm *svm)
         set_intercept(svm, INTERCEPT_SKINIT);
         set_intercept(svm, INTERCEPT_WBINVD);
         set_intercept(svm, INTERCEPT_XSETBV);
+        set_intercept(svm, INTERCEPT_RSM);
 
         if (!kvm_mwait_in_guest()) {
                 set_intercept(svm, INTERCEPT_MONITOR);
@@ -1902,6 +1908,7 @@ static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
         u32 dummy;
         u32 eax = 1;
 
+        vcpu->arch.microcode_version = 0x01000065;
         svm->spec_ctrl = 0;
 
         if (!init_event) {
@@ -3699,6 +3706,12 @@ static int emulate_on_interception(struct vcpu_svm *svm)
         return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
 }
 
+static int rsm_interception(struct vcpu_svm *svm)
+{
+        return x86_emulate_instruction(&svm->vcpu, 0, 0,
+                                       rsm_ins_bytes, 2) == EMULATE_DONE;
+}
+
 static int rdpmc_interception(struct vcpu_svm *svm)
 {
         int err;
@@ -3860,6 +3873,22 @@ static int cr8_write_interception(struct vcpu_svm *svm)
         return 0;
 }
 
+static int svm_get_msr_feature(struct kvm_msr_entry *msr)
+{
+        msr->data = 0;
+
+        switch (msr->index) {
+        case MSR_F10H_DECFG:
+                if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
+                        msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
+                break;
+        default:
+                return 1;
+        }
+
+        return 0;
+}
+
 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 {
         struct vcpu_svm *svm = to_svm(vcpu);
@@ -3935,9 +3964,6 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 
                 msr_info->data = svm->spec_ctrl;
                 break;
-        case MSR_IA32_UCODE_REV:
-                msr_info->data = 0x01000065;
-                break;
         case MSR_F15H_IC_CFG: {
 
                 int family, model;
@@ -3955,6 +3981,9 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
                         msr_info->data = 0x1E;
                 }
                 break;
+        case MSR_F10H_DECFG:
+                msr_info->data = svm->msr_decfg;
+                break;
         default:
                 return kvm_get_msr_common(vcpu, msr_info);
         }
@@ -4133,6 +4162,24 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
         case MSR_VM_IGNNE:
                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
                 break;
+        case MSR_F10H_DECFG: {
+                struct kvm_msr_entry msr_entry;
+
+                msr_entry.index = msr->index;
+                if (svm_get_msr_feature(&msr_entry))
+                        return 1;
+
+                /* Check the supported bits */
+                if (data & ~msr_entry.data)
+                        return 1;
+
+                /* Don't allow the guest to change a bit, #GP */
+                if (!msr->host_initiated && (data ^ msr_entry.data))
+                        return 1;
+
+                svm->msr_decfg = data;
+                break;
+        }
         case MSR_IA32_APICBASE:
                 if (kvm_vcpu_apicv_active(vcpu))
                         avic_update_vapic_bar(to_svm(vcpu), data);
@@ -4541,7 +4588,7 @@ static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
         [SVM_EXIT_MWAIT]                        = mwait_interception,
         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
         [SVM_EXIT_NPF]                          = npf_interception,
-        [SVM_EXIT_RSM]                          = emulate_on_interception,
+        [SVM_EXIT_RSM]                          = rsm_interception,
         [SVM_EXIT_AVIC_INCOMPLETE_IPI]          = avic_incomplete_ipi_interception,
         [SVM_EXIT_AVIC_UNACCELERATED_ACCESS]    = avic_unaccelerated_access_interception,
 };
@@ -5355,7 +5402,7 @@ static void svm_vcpu_run(struct kvm_vcpu *vcpu)
          * being speculatively taken.
          */
         if (svm->spec_ctrl)
-                wrmsrl(MSR_IA32_SPEC_CTRL, svm->spec_ctrl);
+                native_wrmsrl(MSR_IA32_SPEC_CTRL, svm->spec_ctrl);
 
         asm volatile (
                 "push %%" _ASM_BP "; \n\t"
@@ -5464,11 +5511,11 @@ static void svm_vcpu_run(struct kvm_vcpu *vcpu)
          * If the L02 MSR bitmap does not intercept the MSR, then we need to
          * save it.
          */
-        if (!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL))
-                rdmsrl(MSR_IA32_SPEC_CTRL, svm->spec_ctrl);
+        if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
+                svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
 
         if (svm->spec_ctrl)
-                wrmsrl(MSR_IA32_SPEC_CTRL, 0);
+                native_wrmsrl(MSR_IA32_SPEC_CTRL, 0);
 
         /* Eliminate branch target predictions from guest mode */
         vmexit_fill_RSB();
@@ -6236,16 +6283,18 @@ e_free:
 
 static int sev_launch_measure(struct kvm *kvm, struct kvm_sev_cmd *argp)
 {
+        void __user *measure = (void __user *)(uintptr_t)argp->data;
         struct kvm_sev_info *sev = &kvm->arch.sev_info;
         struct sev_data_launch_measure *data;
         struct kvm_sev_launch_measure params;
+        void __user *p = NULL;
         void *blob = NULL;
         int ret;
 
         if (!sev_guest(kvm))
                 return -ENOTTY;
 
-        if (copy_from_user(&params, (void __user *)(uintptr_t)argp->data, sizeof(params)))
+        if (copy_from_user(&params, measure, sizeof(params)))
                 return -EFAULT;
 
         data = kzalloc(sizeof(*data), GFP_KERNEL);
@@ -6256,17 +6305,13 @@ static int sev_launch_measure(struct kvm *kvm, struct kvm_sev_cmd *argp)
         if (!params.len)
                 goto cmd;
 
-        if (params.uaddr) {
+        p = (void __user *)(uintptr_t)params.uaddr;
+        if (p) {
                 if (params.len > SEV_FW_BLOB_MAX_SIZE) {
                         ret = -EINVAL;
                         goto e_free;
                 }
 
-                if (!access_ok(VERIFY_WRITE, params.uaddr, params.len)) {
-                        ret = -EFAULT;
-                        goto e_free;
-                }
-
                 ret = -ENOMEM;
                 blob = kmalloc(params.len, GFP_KERNEL);
                 if (!blob)
@@ -6290,13 +6335,13 @@ cmd:
                 goto e_free_blob;
 
         if (blob) {
-                if (copy_to_user((void __user *)(uintptr_t)params.uaddr, blob, params.len))
+                if (copy_to_user(p, blob, params.len))
                         ret = -EFAULT;
         }
 
 done:
         params.len = data->len;
-        if (copy_to_user((void __user *)(uintptr_t)argp->data, &params, sizeof(params)))
+        if (copy_to_user(measure, &params, sizeof(params)))
                 ret = -EFAULT;
 e_free_blob:
         kfree(blob);
@@ -6597,7 +6642,7 @@ static int sev_launch_secret(struct kvm *kvm, struct kvm_sev_cmd *argp)
         struct page **pages;
         void *blob, *hdr;
         unsigned long n;
-        int ret;
+        int ret, offset;
 
         if (!sev_guest(kvm))
                 return -ENOTTY;
@@ -6623,6 +6668,10 @@ static int sev_launch_secret(struct kvm *kvm, struct kvm_sev_cmd *argp)
         if (!data)
                 goto e_unpin_memory;
 
+        offset = params.guest_uaddr & (PAGE_SIZE - 1);
+        data->guest_address = __sme_page_pa(pages[0]) + offset;
+        data->guest_len = params.guest_len;
+
         blob = psp_copy_user_blob(params.trans_uaddr, params.trans_len);
         if (IS_ERR(blob)) {
                 ret = PTR_ERR(blob);
@@ -6637,8 +6686,8 @@ static int sev_launch_secret(struct kvm *kvm, struct kvm_sev_cmd *argp)
                 ret = PTR_ERR(hdr);
                 goto e_free_blob;
         }
-        data->trans_address = __psp_pa(blob);
-        data->trans_len = params.trans_len;
+        data->hdr_address = __psp_pa(hdr);
+        data->hdr_len = params.hdr_len;
 
         data->handle = sev->handle;
         ret = sev_issue_cmd(kvm, SEV_CMD_LAUNCH_UPDATE_SECRET, data, &argp->error);
@@ -6821,6 +6870,7 @@ static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
         .vcpu_unblocking = svm_vcpu_unblocking,
 
         .update_bp_intercept = update_bp_intercept,
+        .get_msr_feature = svm_get_msr_feature,
         .get_msr = svm_get_msr,
         .set_msr = svm_set_msr,
         .get_segment_base = svm_get_segment_base,
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index f427723dc7db..051dab74e4e9 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -51,6 +51,7 @@
 #include <asm/apic.h>
 #include <asm/irq_remapping.h>
 #include <asm/mmu_context.h>
+#include <asm/microcode.h>
 #include <asm/nospec-branch.h>
 
 #include "trace.h"
@@ -3226,6 +3227,11 @@ static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
         return !(val & ~valid_bits);
 }
 
+static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
+{
+        return 1;
+}
+
 /*
  * Reads an msr value (of 'msr_index') into 'pdata'.
  * Returns 0 on success, non-0 otherwise.
@@ -4485,7 +4491,8 @@ static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
                               SECONDARY_EXEC_DESC);
                 hw_cr4 &= ~X86_CR4_UMIP;
-        } else
+        } else if (!is_guest_mode(vcpu) ||
+                   !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC))
                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
                                 SECONDARY_EXEC_DESC);
 
@@ -5765,6 +5772,7 @@ static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
         vmx->rmode.vm86_active = 0;
         vmx->spec_ctrl = 0;
 
+        vcpu->arch.microcode_version = 0x100000000ULL;
         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
         kvm_set_cr8(vcpu, 0);
 
@@ -9452,7 +9460,7 @@ static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
          * being speculatively taken.
          */
         if (vmx->spec_ctrl)
-                wrmsrl(MSR_IA32_SPEC_CTRL, vmx->spec_ctrl);
+                native_wrmsrl(MSR_IA32_SPEC_CTRL, vmx->spec_ctrl);
 
         vmx->__launched = vmx->loaded_vmcs->launched;
         asm(
@@ -9587,11 +9595,11 @@ static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
          * If the L02 MSR bitmap does not intercept the MSR, then we need to
          * save it.
          */
-        if (!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL))
-                rdmsrl(MSR_IA32_SPEC_CTRL, vmx->spec_ctrl);
+        if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
+                vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
 
         if (vmx->spec_ctrl)
-                wrmsrl(MSR_IA32_SPEC_CTRL, 0);
+                native_wrmsrl(MSR_IA32_SPEC_CTRL, 0);
 
         /* Eliminate branch target predictions from guest mode */
         vmexit_fill_RSB();
@@ -10136,7 +10144,10 @@ static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
                         (unsigned long)(vmcs12->posted_intr_desc_addr &
                         (PAGE_SIZE - 1)));
         }
-        if (!nested_vmx_prepare_msr_bitmap(vcpu, vmcs12))
+        if (nested_vmx_prepare_msr_bitmap(vcpu, vmcs12))
+                vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
+                              CPU_BASED_USE_MSR_BITMAPS);
+        else
                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
                                 CPU_BASED_USE_MSR_BITMAPS);
 }
@@ -10224,8 +10235,8 @@ static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
          *    updated to reflect this when L1 (or its L2s) actually write to
          *    the MSR.
          */
-        bool pred_cmd = msr_write_intercepted_l01(vcpu, MSR_IA32_PRED_CMD);
-        bool spec_ctrl = msr_write_intercepted_l01(vcpu, MSR_IA32_SPEC_CTRL);
+        bool pred_cmd = !msr_write_intercepted_l01(vcpu, MSR_IA32_PRED_CMD);
+        bool spec_ctrl = !msr_write_intercepted_l01(vcpu, MSR_IA32_SPEC_CTRL);
 
         /* Nothing to do if the MSR bitmap is not in use.  */
         if (!cpu_has_vmx_msr_bitmap() ||
@@ -11196,7 +11207,12 @@ static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
         if (ret)
                 return ret;
 
-        if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
+        /*
+         * If we're entering a halted L2 vcpu and the L2 vcpu won't be woken
+         * by event injection, halt vcpu.
+         */
+        if ((vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT) &&
+            !(vmcs12->vm_entry_intr_info_field & INTR_INFO_VALID_MASK))
                 return kvm_vcpu_halt(vcpu);
 
         vmx->nested.nested_run_pending = 1;
@@ -12287,6 +12303,7 @@ static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
         .vcpu_put = vmx_vcpu_put,
 
         .update_bp_intercept = update_exception_bitmap,
+        .get_msr_feature = vmx_get_msr_feature,
         .get_msr = vmx_get_msr,
         .set_msr = vmx_set_msr,
         .get_segment_base = vmx_get_segment_base,
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index c8a0b545ac20..18b5ca7a3197 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -1049,6 +1049,45 @@ static u32 emulated_msrs[] = {
 
 static unsigned num_emulated_msrs;
 
+/*
+ * List of msr numbers which are used to expose MSR-based features that
+ * can be used by a hypervisor to validate requested CPU features.
+ */
+static u32 msr_based_features[] = {
+        MSR_F10H_DECFG,
+        MSR_IA32_UCODE_REV,
+};
+
+static unsigned int num_msr_based_features;
+
+static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
+{
+        switch (msr->index) {
+        case MSR_IA32_UCODE_REV:
+                rdmsrl(msr->index, msr->data);
+                break;
+        default:
+                if (kvm_x86_ops->get_msr_feature(msr))
+                        return 1;
+        }
+        return 0;
+}
+
+static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
+{
+        struct kvm_msr_entry msr;
+        int r;
+
+        msr.index = index;
+        r = kvm_get_msr_feature(&msr);
+        if (r)
+                return r;
+
+        *data = msr.data;
+
+        return 0;
+}
+
 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
 {
         if (efer & efer_reserved_bits)
@@ -2222,7 +2261,6 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 
         switch (msr) {
         case MSR_AMD64_NB_CFG:
-        case MSR_IA32_UCODE_REV:
         case MSR_IA32_UCODE_WRITE:
         case MSR_VM_HSAVE_PA:
         case MSR_AMD64_PATCH_LOADER:
@@ -2230,6 +2268,10 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
         case MSR_AMD64_DC_CFG:
                 break;
 
+        case MSR_IA32_UCODE_REV:
+                if (msr_info->host_initiated)
+                        vcpu->arch.microcode_version = data;
+                break;
         case MSR_EFER:
                 return set_efer(vcpu, data);
         case MSR_K7_HWCR:
@@ -2525,7 +2567,7 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
                 msr_info->data = 0;
                 break;
         case MSR_IA32_UCODE_REV:
-                msr_info->data = 0x100000000ULL;
+                msr_info->data = vcpu->arch.microcode_version;
                 break;
         case MSR_MTRRcap:
         case 0x200 ... 0x2ff:
@@ -2680,13 +2722,11 @@ static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
                     int (*do_msr)(struct kvm_vcpu *vcpu,
                                   unsigned index, u64 *data))
 {
-        int i, idx;
+        int i;
 
-        idx = srcu_read_lock(&vcpu->kvm->srcu);
         for (i = 0; i < msrs->nmsrs; ++i)
                 if (do_msr(vcpu, entries[i].index, &entries[i].data))
                         break;
-        srcu_read_unlock(&vcpu->kvm->srcu, idx);
 
         return i;
 }
@@ -2785,6 +2825,7 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
         case KVM_CAP_SET_BOOT_CPU_ID:
         case KVM_CAP_SPLIT_IRQCHIP:
         case KVM_CAP_IMMEDIATE_EXIT:
+        case KVM_CAP_GET_MSR_FEATURES:
                 r = 1;
                 break;
         case KVM_CAP_ADJUST_CLOCK:
@@ -2899,6 +2940,31 @@ long kvm_arch_dev_ioctl(struct file *filp,
                         goto out;
                 r = 0;
                 break;
+        case KVM_GET_MSR_FEATURE_INDEX_LIST: {
+                struct kvm_msr_list __user *user_msr_list = argp;
+                struct kvm_msr_list msr_list;
+                unsigned int n;
+
+                r = -EFAULT;
+                if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
+                        goto out;
+                n = msr_list.nmsrs;
+                msr_list.nmsrs = num_msr_based_features;
+                if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
+                        goto out;
+                r = -E2BIG;
+                if (n < msr_list.nmsrs)
+                        goto out;
+                r = -EFAULT;
+                if (copy_to_user(user_msr_list->indices, &msr_based_features,
+                                 num_msr_based_features * sizeof(u32)))
+                        goto out;
+                r = 0;
+                break;
+        }
+        case KVM_GET_MSRS:
+                r = msr_io(NULL, argp, do_get_msr_feature, 1);
+                break;
         }
         default:
                 r = -EINVAL;
@@ -3636,12 +3702,18 @@ long kvm_arch_vcpu_ioctl(struct file *filp,
                 r = 0;
                 break;
         }
-        case KVM_GET_MSRS:
+        case KVM_GET_MSRS: {
+                int idx = srcu_read_lock(&vcpu->kvm->srcu);
                 r = msr_io(vcpu, argp, do_get_msr, 1);
+                srcu_read_unlock(&vcpu->kvm->srcu, idx);
                 break;
-        case KVM_SET_MSRS:
+        }
+        case KVM_SET_MSRS: {
+                int idx = srcu_read_lock(&vcpu->kvm->srcu);
                 r = msr_io(vcpu, argp, do_set_msr, 0);
+                srcu_read_unlock(&vcpu->kvm->srcu, idx);
                 break;
+        }
         case KVM_TPR_ACCESS_REPORTING: {
                 struct kvm_tpr_access_ctl tac;
 
@@ -4464,6 +4536,19 @@ static void kvm_init_msr_list(void)
                 j++;
         }
         num_emulated_msrs = j;
+
+        for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
+                struct kvm_msr_entry msr;
+
+                msr.index = msr_based_features[i];
+                if (kvm_get_msr_feature(&msr))
+                        continue;
+
+                if (j < i)
+                        msr_based_features[j] = msr_based_features[i];
+                j++;
+        }
+        num_msr_based_features = j;
 }
 
 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
@@ -8017,6 +8102,8 @@ void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
 
 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
 {
+        kvm_lapic_reset(vcpu, init_event);
+
         vcpu->arch.hflags = 0;
 
         vcpu->arch.smi_pending = 0;
@@ -8460,10 +8547,8 @@ int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
                         return r;
         }
 
-        if (!size) {
-                r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
-                WARN_ON(r < 0);
-        }
+        if (!size)
+                vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
 
         return 0;
 }
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index 91e9700cc6dc..25a972c61b0a 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -28,7 +28,6 @@ lib-$(CONFIG_INSTRUCTION_DECODER) += insn.o inat.o insn-eval.o
 lib-$(CONFIG_RANDOMIZE_BASE) += kaslr.o
 lib-$(CONFIG_FUNCTION_ERROR_INJECTION)  += error-inject.o
 lib-$(CONFIG_RETPOLINE) += retpoline.o
-OBJECT_FILES_NON_STANDARD_retpoline.o :=y
 
 obj-y += msr.o msr-reg.o msr-reg-export.o hweight.o
 
diff --git a/arch/x86/lib/cpu.c b/arch/x86/lib/cpu.c
index d6f848d1211d..2dd1fe13a37b 100644
--- a/arch/x86/lib/cpu.c
+++ b/arch/x86/lib/cpu.c
@@ -18,7 +18,7 @@ unsigned int x86_model(unsigned int sig)
 {
         unsigned int fam, model;
 
-         fam = x86_family(sig);
+        fam = x86_family(sig);
 
         model = (sig >> 4) & 0xf;
 
diff --git a/arch/x86/lib/error-inject.c b/arch/x86/lib/error-inject.c
index 7b881d03d0dd..3cdf06128d13 100644
--- a/arch/x86/lib/error-inject.c
+++ b/arch/x86/lib/error-inject.c
@@ -7,6 +7,7 @@ asmlinkage void just_return_func(void);
 
 asm(
         ".type just_return_func, @function\n"
+        ".globl just_return_func\n"
         "just_return_func:\n"
         "       ret\n"
         ".size just_return_func, .-just_return_func\n"
diff --git a/arch/x86/lib/retpoline.S b/arch/x86/lib/retpoline.S
index 480edc3a5e03..c909961e678a 100644
--- a/arch/x86/lib/retpoline.S
+++ b/arch/x86/lib/retpoline.S
@@ -7,7 +7,6 @@
 #include <asm/alternative-asm.h>
 #include <asm/export.h>
 #include <asm/nospec-branch.h>
-#include <asm/bitsperlong.h>
 
 .macro THUNK reg
         .section .text.__x86.indirect_thunk
@@ -47,58 +46,3 @@ GENERATE_THUNK(r13)
 GENERATE_THUNK(r14)
 GENERATE_THUNK(r15)
 #endif
-
-/*
- * Fill the CPU return stack buffer.
- *
- * Each entry in the RSB, if used for a speculative 'ret', contains an
- * infinite 'pause; lfence; jmp' loop to capture speculative execution.
- *
- * This is required in various cases for retpoline and IBRS-based
- * mitigations for the Spectre variant 2 vulnerability. Sometimes to
- * eliminate potentially bogus entries from the RSB, and sometimes
- * purely to ensure that it doesn't get empty, which on some CPUs would
- * allow predictions from other (unwanted!) sources to be used.
- *
- * Google experimented with loop-unrolling and this turned out to be
- * the optimal version - two calls, each with their own speculation
- * trap should their return address end up getting used, in a loop.
- */
-.macro STUFF_RSB nr:req sp:req
-        mov     $(\nr / 2), %_ASM_BX
-        .align 16
-771:
-        call    772f
-773:                                            /* speculation trap */
-        pause
-        lfence
-        jmp     773b
-        .align 16
-772:
-        call    774f
-775:                                            /* speculation trap */
-        pause
-        lfence
-        jmp     775b
-        .align 16
-774:
-        dec     %_ASM_BX
-        jnz     771b
-        add     $((BITS_PER_LONG/8) * \nr), \sp
-.endm
-
-#define RSB_FILL_LOOPS          16      /* To avoid underflow */
-
-ENTRY(__fill_rsb)
-        STUFF_RSB RSB_FILL_LOOPS, %_ASM_SP
-        ret
-END(__fill_rsb)
-EXPORT_SYMBOL_GPL(__fill_rsb)
-
-#define RSB_CLEAR_LOOPS         32      /* To forcibly overwrite all entries */
-
-ENTRY(__clear_rsb)
-        STUFF_RSB RSB_CLEAR_LOOPS, %_ASM_SP
-        ret
-END(__clear_rsb)
-EXPORT_SYMBOL_GPL(__clear_rsb)
diff --git a/arch/x86/mm/cpu_entry_area.c b/arch/x86/mm/cpu_entry_area.c
index b9283cc27622..476d810639a8 100644
--- a/arch/x86/mm/cpu_entry_area.c
+++ b/arch/x86/mm/cpu_entry_area.c
@@ -163,4 +163,10 @@ void __init setup_cpu_entry_areas(void)
 
         for_each_possible_cpu(cpu)
                 setup_cpu_entry_area(cpu);
+
+        /*
+         * This is the last essential update to swapper_pgdir which needs
+         * to be synchronized to initial_page_table on 32bit.
+         */
+        sync_initial_page_table();
 }
diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c
index 800de815519c..c88573d90f3e 100644
--- a/arch/x86/mm/fault.c
+++ b/arch/x86/mm/fault.c
@@ -1248,10 +1248,6 @@ __do_page_fault(struct pt_regs *regs, unsigned long error_code,
         tsk = current;
         mm = tsk->mm;
 
-        /*
-         * Detect and handle instructions that would cause a page fault for
-         * both a tracked kernel page and a userspace page.
-         */
         prefetchw(&mm->mmap_sem);
 
         if (unlikely(kmmio_fault(regs, address)))
diff --git a/arch/x86/mm/init_32.c b/arch/x86/mm/init_32.c
index 79cb066f40c0..396e1f0151ac 100644
--- a/arch/x86/mm/init_32.c
+++ b/arch/x86/mm/init_32.c
@@ -453,6 +453,21 @@ static inline void permanent_kmaps_init(pgd_t *pgd_base)
 }
 #endif /* CONFIG_HIGHMEM */
 
+void __init sync_initial_page_table(void)
+{
+        clone_pgd_range(initial_page_table + KERNEL_PGD_BOUNDARY,
+                        swapper_pg_dir     + KERNEL_PGD_BOUNDARY,
+                        KERNEL_PGD_PTRS);
+
+        /*
+         * sync back low identity map too.  It is used for example
+         * in the 32-bit EFI stub.
+         */
+        clone_pgd_range(initial_page_table,
+                        swapper_pg_dir     + KERNEL_PGD_BOUNDARY,
+                        min(KERNEL_PGD_PTRS, KERNEL_PGD_BOUNDARY));
+}
+
 void __init native_pagetable_init(void)
 {
         unsigned long pfn, va;
diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c
index 1ab42c852069..8b72923f1d35 100644
--- a/arch/x86/mm/init_64.c
+++ b/arch/x86/mm/init_64.c
@@ -256,7 +256,7 @@ static void __set_pte_vaddr(pud_t *pud, unsigned long vaddr, pte_t new_pte)
          * It's enough to flush this one mapping.
          * (PGE mappings get flushed as well)
          */
-        __flush_tlb_one(vaddr);
+        __flush_tlb_one_kernel(vaddr);
 }
 
 void set_pte_vaddr_p4d(p4d_t *p4d_page, unsigned long vaddr, pte_t new_pte)
@@ -1193,8 +1193,8 @@ void __init mem_init(void)
         register_page_bootmem_info();
 
         /* Register memory areas for /proc/kcore */
-        kclist_add(&kcore_vsyscall, (void *)VSYSCALL_ADDR,
-                         PAGE_SIZE, KCORE_OTHER);
+        if (get_gate_vma(&init_mm))
+                kclist_add(&kcore_vsyscall, (void *)VSYSCALL_ADDR, PAGE_SIZE, KCORE_USER);
 
         mem_init_print_info(NULL);
 }
diff --git a/arch/x86/mm/ioremap.c b/arch/x86/mm/ioremap.c
index c45b6ec5357b..e2db83bebc3b 100644
--- a/arch/x86/mm/ioremap.c
+++ b/arch/x86/mm/ioremap.c
@@ -820,5 +820,5 @@ void __init __early_set_fixmap(enum fixed_addresses idx,
                 set_pte(pte, pfn_pte(phys >> PAGE_SHIFT, flags));
         else
                 pte_clear(&init_mm, addr, pte);
-        __flush_tlb_one(addr);
+        __flush_tlb_one_kernel(addr);
 }
diff --git a/arch/x86/mm/kmmio.c b/arch/x86/mm/kmmio.c
index 58477ec3d66d..7c8686709636 100644
--- a/arch/x86/mm/kmmio.c
+++ b/arch/x86/mm/kmmio.c
@@ -168,7 +168,7 @@ static int clear_page_presence(struct kmmio_fault_page *f, bool clear)
                 return -1;
         }
 
-        __flush_tlb_one(f->addr);
+        __flush_tlb_one_kernel(f->addr);
         return 0;
 }
 
diff --git a/arch/x86/mm/mem_encrypt_boot.S b/arch/x86/mm/mem_encrypt_boot.S
index 01f682cf77a8..40a6085063d6 100644
--- a/arch/x86/mm/mem_encrypt_boot.S
+++ b/arch/x86/mm/mem_encrypt_boot.S
@@ -15,6 +15,7 @@
 #include <asm/page.h>
 #include <asm/processor-flags.h>
 #include <asm/msr-index.h>
+#include <asm/nospec-branch.h>
 
         .text
         .code64
@@ -59,6 +60,7 @@ ENTRY(sme_encrypt_execute)
         movq    %rax, %r8               /* Workarea encryption routine */
         addq    $PAGE_SIZE, %r8         /* Workarea intermediate copy buffer */
 
+        ANNOTATE_RETPOLINE_SAFE
         call    *%rax                   /* Call the encryption routine */
 
         pop     %r12
diff --git a/arch/x86/mm/pgtable_32.c b/arch/x86/mm/pgtable_32.c
index c3c5274410a9..9bb7f0ab9fe6 100644
--- a/arch/x86/mm/pgtable_32.c
+++ b/arch/x86/mm/pgtable_32.c
@@ -63,7 +63,7 @@ void set_pte_vaddr(unsigned long vaddr, pte_t pteval)
          * It's enough to flush this one mapping.
          * (PGE mappings get flushed as well)
          */
-        __flush_tlb_one(vaddr);
+        __flush_tlb_one_kernel(vaddr);
 }
 
 unsigned long __FIXADDR_TOP = 0xfffff000;
diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c
index 8dcc0607f805..7f1a51399674 100644
--- a/arch/x86/mm/tlb.c
+++ b/arch/x86/mm/tlb.c
@@ -498,7 +498,7 @@ static void flush_tlb_func_common(const struct flush_tlb_info *f,
          *    flush that changes context.tlb_gen from 2 to 3.  If they get
          *    processed on this CPU in reverse order, we'll see
          *     local_tlb_gen == 1, mm_tlb_gen == 3, and end != TLB_FLUSH_ALL.
-         *    If we were to use __flush_tlb_single() and set local_tlb_gen to
+         *    If we were to use __flush_tlb_one_user() and set local_tlb_gen to
          *    3, we'd be break the invariant: we'd update local_tlb_gen above
          *    1 without the full flush that's needed for tlb_gen 2.
          *
@@ -519,7 +519,7 @@ static void flush_tlb_func_common(const struct flush_tlb_info *f,
 
                 addr = f->start;
                 while (addr < f->end) {
-                        __flush_tlb_single(addr);
+                        __flush_tlb_one_user(addr);
                         addr += PAGE_SIZE;
                 }
                 if (local)
@@ -666,7 +666,7 @@ static void do_kernel_range_flush(void *info)
 
         /* flush range by one by one 'invlpg' */
         for (addr = f->start; addr < f->end; addr += PAGE_SIZE)
-                __flush_tlb_one(addr);
+                __flush_tlb_one_kernel(addr);
 }
 
 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
diff --git a/arch/x86/net/bpf_jit_comp.c b/arch/x86/net/bpf_jit_comp.c
index 4923d92f918d..45e4eb5bcbb2 100644
--- a/arch/x86/net/bpf_jit_comp.c
+++ b/arch/x86/net/bpf_jit_comp.c
@@ -13,6 +13,7 @@
 #include <linux/if_vlan.h>
 #include <asm/cacheflush.h>
 #include <asm/set_memory.h>
+#include <asm/nospec-branch.h>
 #include <linux/bpf.h>
 
 /*
@@ -290,7 +291,7 @@ static void emit_bpf_tail_call(u8 **pprog)
         EMIT2(0x89, 0xD2);                        /* mov edx, edx */
         EMIT3(0x39, 0x56,                         /* cmp dword ptr [rsi + 16], edx */
               offsetof(struct bpf_array, map.max_entries));
-#define OFFSET1 43 /* number of bytes to jump */
+#define OFFSET1 (41 + RETPOLINE_RAX_BPF_JIT_SIZE) /* number of bytes to jump */
         EMIT2(X86_JBE, OFFSET1);                  /* jbe out */
         label1 = cnt;
 
@@ -299,7 +300,7 @@ static void emit_bpf_tail_call(u8 **pprog)
          */
         EMIT2_off32(0x8B, 0x85, 36);              /* mov eax, dword ptr [rbp + 36] */
         EMIT3(0x83, 0xF8, MAX_TAIL_CALL_CNT);     /* cmp eax, MAX_TAIL_CALL_CNT */
-#define OFFSET2 32
+#define OFFSET2 (30 + RETPOLINE_RAX_BPF_JIT_SIZE)
         EMIT2(X86_JA, OFFSET2);                   /* ja out */
         label2 = cnt;
         EMIT3(0x83, 0xC0, 0x01);                  /* add eax, 1 */
@@ -313,7 +314,7 @@ static void emit_bpf_tail_call(u8 **pprog)
          *   goto out;
          */
         EMIT3(0x48, 0x85, 0xC0);                  /* test rax,rax */
-#define OFFSET3 10
+#define OFFSET3 (8 + RETPOLINE_RAX_BPF_JIT_SIZE)
         EMIT2(X86_JE, OFFSET3);                   /* je out */
         label3 = cnt;
 
@@ -326,7 +327,7 @@ static void emit_bpf_tail_call(u8 **pprog)
          * rdi == ctx (1st arg)
          * rax == prog->bpf_func + prologue_size
          */
-        EMIT2(0xFF, 0xE0);                        /* jmp rax */
+        RETPOLINE_RAX_BPF_JIT();
 
         /* out: */
         BUILD_BUG_ON(cnt - label1 != OFFSET1);
diff --git a/arch/x86/oprofile/nmi_int.c b/arch/x86/oprofile/nmi_int.c
index 174c59774cc9..a7a7677265b6 100644
--- a/arch/x86/oprofile/nmi_int.c
+++ b/arch/x86/oprofile/nmi_int.c
@@ -460,7 +460,7 @@ static int nmi_setup(void)
                 goto fail;
 
         for_each_possible_cpu(cpu) {
-                if (!cpu)
+                if (!IS_ENABLED(CONFIG_SMP) || !cpu)
                         continue;
 
                 memcpy(per_cpu(cpu_msrs, cpu).counters,
diff --git a/arch/x86/platform/intel-mid/intel-mid.c b/arch/x86/platform/intel-mid/intel-mid.c
index 2c67bae6bb53..fb1df9488e98 100644
--- a/arch/x86/platform/intel-mid/intel-mid.c
+++ b/arch/x86/platform/intel-mid/intel-mid.c
@@ -79,7 +79,7 @@ static void intel_mid_power_off(void)
 
 static void intel_mid_reboot(void)
 {
-        intel_scu_ipc_simple_command(IPCMSG_COLD_BOOT, 0);
+        intel_scu_ipc_simple_command(IPCMSG_COLD_RESET, 0);
 }
 
 static unsigned long __init intel_mid_calibrate_tsc(void)
diff --git a/arch/x86/platform/uv/tlb_uv.c b/arch/x86/platform/uv/tlb_uv.c
index c2e9285d1bf1..db77e087adaf 100644
--- a/arch/x86/platform/uv/tlb_uv.c
+++ b/arch/x86/platform/uv/tlb_uv.c
@@ -299,7 +299,7 @@ static void bau_process_message(struct msg_desc *mdp, struct bau_control *bcp,
                 local_flush_tlb();
                 stat->d_alltlb++;
         } else {
-                __flush_tlb_single(msg->address);
+                __flush_tlb_one_user(msg->address);
                 stat->d_onetlb++;
         }
         stat->d_requestee++;
diff --git a/arch/x86/realmode/rm/trampoline_64.S b/arch/x86/realmode/rm/trampoline_64.S
index de53bd15df5a..24bb7598774e 100644
--- a/arch/x86/realmode/rm/trampoline_64.S
+++ b/arch/x86/realmode/rm/trampoline_64.S
@@ -102,7 +102,7 @@ ENTRY(startup_32)
          * don't we'll eventually crash trying to execute encrypted
          * instructions.
          */
-        bt      $TH_FLAGS_SME_ACTIVE_BIT, pa_tr_flags
+        btl     $TH_FLAGS_SME_ACTIVE_BIT, pa_tr_flags
         jnc     .Ldone
         movl    $MSR_K8_SYSCFG, %ecx
         rdmsr
diff --git a/arch/x86/tools/relocs.c b/arch/x86/tools/relocs.c
index 5d73c443e778..220e97841e49 100644
--- a/arch/x86/tools/relocs.c
+++ b/arch/x86/tools/relocs.c
@@ -770,9 +770,12 @@ static int do_reloc64(struct section *sec, Elf_Rel *rel, ElfW(Sym) *sym,
                 break;
 
         case R_X86_64_PC32:
+        case R_X86_64_PLT32:
                 /*
                  * PC relative relocations don't need to be adjusted unless
                  * referencing a percpu symbol.
+                 *
+                 * NB: R_X86_64_PLT32 can be treated as R_X86_64_PC32.
                  */
                 if (is_percpu_sym(sym, symname))
                         add_reloc(&relocs32neg, offset);
diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c
index c047f42552e1..3c2c2530737e 100644
--- a/arch/x86/xen/enlighten_pv.c
+++ b/arch/x86/xen/enlighten_pv.c
@@ -1376,8 +1376,6 @@ asmlinkage __visible void __init xen_start_kernel(void)
 
         if (!xen_initial_domain()) {
                 add_preferred_console("xenboot", 0, NULL);
-                add_preferred_console("tty", 0, NULL);
-                add_preferred_console("hvc", 0, NULL);
                 if (pci_xen)
                         x86_init.pci.arch_init = pci_xen_init;
         } else {
@@ -1410,6 +1408,10 @@ asmlinkage __visible void __init xen_start_kernel(void)
 
                 xen_boot_params_init_edd();
         }
+
+        add_preferred_console("tty", 0, NULL);
+        add_preferred_console("hvc", 0, NULL);
+
 #ifdef CONFIG_PCI
         /* PCI BIOS service won't work from a PV guest. */
         pci_probe &= ~PCI_PROBE_BIOS;
diff --git a/arch/x86/xen/mmu_pv.c b/arch/x86/xen/mmu_pv.c
index d85076223a69..aae88fec9941 100644
--- a/arch/x86/xen/mmu_pv.c
+++ b/arch/x86/xen/mmu_pv.c
@@ -1300,12 +1300,12 @@ static void xen_flush_tlb(void)
         preempt_enable();
 }
 
-static void xen_flush_tlb_single(unsigned long addr)
+static void xen_flush_tlb_one_user(unsigned long addr)
 {
         struct mmuext_op *op;
         struct multicall_space mcs;
 
-        trace_xen_mmu_flush_tlb_single(addr);
+        trace_xen_mmu_flush_tlb_one_user(addr);
 
         preempt_disable();
 
@@ -2370,7 +2370,7 @@ static const struct pv_mmu_ops xen_mmu_ops __initconst = {
 
         .flush_tlb_user = xen_flush_tlb,
         .flush_tlb_kernel = xen_flush_tlb,
-        .flush_tlb_single = xen_flush_tlb_single,
+        .flush_tlb_one_user = xen_flush_tlb_one_user,
         .flush_tlb_others = xen_flush_tlb_others,
 
         .pgd_alloc = xen_pgd_alloc,
diff --git a/arch/x86/xen/smp.c b/arch/x86/xen/smp.c
index 77c959cf81e7..7a43b2ae19f1 100644
--- a/arch/x86/xen/smp.c
+++ b/arch/x86/xen/smp.c
@@ -122,6 +122,8 @@ void __init xen_smp_cpus_done(unsigned int max_cpus)
 
         if (xen_hvm_domain())
                 native_smp_cpus_done(max_cpus);
+        else
+                calculate_max_logical_packages();
 
         if (xen_have_vcpu_info_placement)
                 return;
diff --git a/arch/x86/xen/suspend.c b/arch/x86/xen/suspend.c
index d9f96cc5d743..1d83152c761b 100644
--- a/arch/x86/xen/suspend.c
+++ b/arch/x86/xen/suspend.c
@@ -1,12 +1,15 @@
 // SPDX-License-Identifier: GPL-2.0
 #include <linux/types.h>
 #include <linux/tick.h>
+#include <linux/percpu-defs.h>
 
 #include <xen/xen.h>
 #include <xen/interface/xen.h>
 #include <xen/grant_table.h>
 #include <xen/events.h>
 
+#include <asm/cpufeatures.h>
+#include <asm/msr-index.h>
 #include <asm/xen/hypercall.h>
 #include <asm/xen/page.h>
 #include <asm/fixmap.h>
@@ -15,6 +18,8 @@
 #include "mmu.h"
 #include "pmu.h"
 
+static DEFINE_PER_CPU(u64, spec_ctrl);
+
 void xen_arch_pre_suspend(void)
 {
         xen_save_time_memory_area();
@@ -35,6 +40,9 @@ void xen_arch_post_suspend(int cancelled)
 
 static void xen_vcpu_notify_restore(void *data)
 {
+        if (xen_pv_domain() && boot_cpu_has(X86_FEATURE_SPEC_CTRL))
+                wrmsrl(MSR_IA32_SPEC_CTRL, this_cpu_read(spec_ctrl));
+
         /* Boot processor notified via generic timekeeping_resume() */
         if (smp_processor_id() == 0)
                 return;
@@ -44,7 +52,15 @@ static void xen_vcpu_notify_restore(void *data)
 
 static void xen_vcpu_notify_suspend(void *data)
 {
+        u64 tmp;
+
         tick_suspend_local();
+
+        if (xen_pv_domain() && boot_cpu_has(X86_FEATURE_SPEC_CTRL)) {
+                rdmsrl(MSR_IA32_SPEC_CTRL, tmp);
+                this_cpu_write(spec_ctrl, tmp);
+                wrmsrl(MSR_IA32_SPEC_CTRL, 0);
+        }
 }
 
 void xen_arch_resume(void)
diff --git a/arch/xtensa/kernel/pci-dma.c b/arch/xtensa/kernel/pci-dma.c
index 623720a11143..732631ce250f 100644
--- a/arch/xtensa/kernel/pci-dma.c
+++ b/arch/xtensa/kernel/pci-dma.c
@@ -16,6 +16,7 @@
  */
 
 #include <linux/dma-contiguous.h>
+#include <linux/dma-direct.h>
 #include <linux/gfp.h>
 #include <linux/highmem.h>
 #include <linux/mm.h>
@@ -123,7 +124,7 @@ static void *xtensa_dma_alloc(struct device *dev, size_t size,
                               unsigned long attrs)
 {
         unsigned long ret;
-        unsigned long uncached = 0;
+        unsigned long uncached;
         unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
         struct page *page = NULL;
 
@@ -144,15 +145,27 @@ static void *xtensa_dma_alloc(struct device *dev, size_t size,
         if (!page)
                 return NULL;
 
-        ret = (unsigned long)page_address(page);
+        *handle = phys_to_dma(dev, page_to_phys(page));
 
-        /* We currently don't support coherent memory outside KSEG */
+#ifdef CONFIG_MMU
+        if (PageHighMem(page)) {
+                void *p;
 
+                p = dma_common_contiguous_remap(page, size, VM_MAP,
+                                                pgprot_noncached(PAGE_KERNEL),
+                                                __builtin_return_address(0));
+                if (!p) {
+                        if (!dma_release_from_contiguous(dev, page, count))
+                                __free_pages(page, get_order(size));
+                }
+                return p;
+        }
+#endif
+        ret = (unsigned long)page_address(page);
         BUG_ON(ret < XCHAL_KSEG_CACHED_VADDR ||
                ret > XCHAL_KSEG_CACHED_VADDR + XCHAL_KSEG_SIZE - 1);
 
         uncached = ret + XCHAL_KSEG_BYPASS_VADDR - XCHAL_KSEG_CACHED_VADDR;
-        *handle = virt_to_bus((void *)ret);
         __invalidate_dcache_range(ret, size);
 
         return (void *)uncached;
@@ -161,13 +174,20 @@ static void *xtensa_dma_alloc(struct device *dev, size_t size,
 static void xtensa_dma_free(struct device *dev, size_t size, void *vaddr,
                             dma_addr_t dma_handle, unsigned long attrs)
 {
-        unsigned long addr = (unsigned long)vaddr +
-                XCHAL_KSEG_CACHED_VADDR - XCHAL_KSEG_BYPASS_VADDR;
-        struct page *page = virt_to_page(addr);
         unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
-
-        BUG_ON(addr < XCHAL_KSEG_CACHED_VADDR ||
-               addr > XCHAL_KSEG_CACHED_VADDR + XCHAL_KSEG_SIZE - 1);
+        unsigned long addr = (unsigned long)vaddr;
+        struct page *page;
+
+        if (addr >= XCHAL_KSEG_BYPASS_VADDR &&
+            addr - XCHAL_KSEG_BYPASS_VADDR < XCHAL_KSEG_SIZE) {
+                addr += XCHAL_KSEG_CACHED_VADDR - XCHAL_KSEG_BYPASS_VADDR;
+                page = virt_to_page(addr);
+        } else {
+#ifdef CONFIG_MMU
+                dma_common_free_remap(vaddr, size, VM_MAP);
+#endif
+                page = pfn_to_page(PHYS_PFN(dma_to_phys(dev, dma_handle)));
+        }
 
         if (!dma_release_from_contiguous(dev, page, count))
                 __free_pages(page, get_order(size));
diff --git a/arch/xtensa/mm/init.c b/arch/xtensa/mm/init.c
index d776ec0d7b22..34aead7dcb48 100644
--- a/arch/xtensa/mm/init.c
+++ b/arch/xtensa/mm/init.c
@@ -79,19 +79,75 @@ void __init zones_init(void)
         free_area_init_node(0, zones_size, ARCH_PFN_OFFSET, NULL);
 }
 
+#ifdef CONFIG_HIGHMEM
+static void __init free_area_high(unsigned long pfn, unsigned long end)
+{
+        for (; pfn < end; pfn++)
+                free_highmem_page(pfn_to_page(pfn));
+}
+
+static void __init free_highpages(void)
+{
+        unsigned long max_low = max_low_pfn;
+        struct memblock_region *mem, *res;
+
+        reset_all_zones_managed_pages();
+        /* set highmem page free */
+        for_each_memblock(memory, mem) {
+                unsigned long start = memblock_region_memory_base_pfn(mem);
+                unsigned long end = memblock_region_memory_end_pfn(mem);
+
+                /* Ignore complete lowmem entries */
+                if (end <= max_low)
+                        continue;
+
+                if (memblock_is_nomap(mem))
+                        continue;
+
+                /* Truncate partial highmem entries */
+                if (start < max_low)
+                        start = max_low;
+
+                /* Find and exclude any reserved regions */
+                for_each_memblock(reserved, res) {
+                        unsigned long res_start, res_end;
+
+                        res_start = memblock_region_reserved_base_pfn(res);
+                        res_end = memblock_region_reserved_end_pfn(res);
+
+                        if (res_end < start)
+                                continue;
+                        if (res_start < start)
+                                res_start = start;
+                        if (res_start > end)
+                                res_start = end;
+                        if (res_end > end)
+                                res_end = end;
+                        if (res_start != start)
+                                free_area_high(start, res_start);
+                        start = res_end;
+                        if (start == end)
+                                break;
+                }
+
+                /* And now free anything which remains */
+                if (start < end)
+                        free_area_high(start, end);
+        }
+}
+#else
+static void __init free_highpages(void)
+{
+}
+#endif
+
 /*
  * Initialize memory pages.
  */
 
 void __init mem_init(void)
 {
-#ifdef CONFIG_HIGHMEM
-        unsigned long tmp;
-
-        reset_all_zones_managed_pages();
-        for (tmp = max_low_pfn; tmp < max_pfn; tmp++)
-                free_highmem_page(pfn_to_page(tmp));
-#endif
+        free_highpages();
 
         max_mapnr = max_pfn - ARCH_PFN_OFFSET;
         high_memory = (void *)__va(max_low_pfn << PAGE_SHIFT);
diff --git a/block/blk-cgroup.c b/block/blk-cgroup.c
index 4117524ca45b..c2033a232a44 100644
--- a/block/blk-cgroup.c
+++ b/block/blk-cgroup.c
@@ -812,7 +812,6 @@ int blkg_conf_prep(struct blkcg *blkcg, const struct blkcg_policy *pol,
         struct gendisk *disk;
         struct request_queue *q;
         struct blkcg_gq *blkg;
-        struct module *owner;
         unsigned int major, minor;
         int key_len, part, ret;
         char *body;
@@ -904,9 +903,7 @@ fail_unlock:
         spin_unlock_irq(q->queue_lock);
         rcu_read_unlock();
 fail:
-        owner = disk->fops->owner;
-        put_disk(disk);
-        module_put(owner);
+        put_disk_and_module(disk);
         /*
          * If queue was bypassing, we should retry.  Do so after a
          * short msleep().  It isn't strictly necessary but queue
@@ -931,13 +928,9 @@ EXPORT_SYMBOL_GPL(blkg_conf_prep);
 void blkg_conf_finish(struct blkg_conf_ctx *ctx)
         __releases(ctx->disk->queue->queue_lock) __releases(rcu)
 {
-        struct module *owner;
-
         spin_unlock_irq(ctx->disk->queue->queue_lock);
         rcu_read_unlock();
-        owner = ctx->disk->fops->owner;
-        put_disk(ctx->disk);
-        module_put(owner);
+        put_disk_and_module(ctx->disk);
 }
 EXPORT_SYMBOL_GPL(blkg_conf_finish);
 
diff --git a/block/blk-core.c b/block/blk-core.c
index 2d1a7bbe0634..6d82c4f7fadd 100644
--- a/block/blk-core.c
+++ b/block/blk-core.c
@@ -2434,7 +2434,7 @@ blk_qc_t submit_bio(struct bio *bio)
                 unsigned int count;
 
                 if (unlikely(bio_op(bio) == REQ_OP_WRITE_SAME))
-                        count = queue_logical_block_size(bio->bi_disk->queue);
+                        count = queue_logical_block_size(bio->bi_disk->queue) >> 9;
                 else
                         count = bio_sectors(bio);
 
diff --git a/block/blk-mq.c b/block/blk-mq.c
index df93102e2149..16e83e6df404 100644
--- a/block/blk-mq.c
+++ b/block/blk-mq.c
@@ -712,7 +712,6 @@ static void __blk_mq_requeue_request(struct request *rq)
 
         trace_block_rq_requeue(q, rq);
         wbt_requeue(q->rq_wb, &rq->issue_stat);
-        blk_mq_sched_requeue_request(rq);
 
         if (blk_mq_rq_state(rq) != MQ_RQ_IDLE) {
                 blk_mq_rq_update_state(rq, MQ_RQ_IDLE);
@@ -725,6 +724,9 @@ void blk_mq_requeue_request(struct request *rq, bool kick_requeue_list)
 {
         __blk_mq_requeue_request(rq);
 
+        /* this request will be re-inserted to io scheduler queue */
+        blk_mq_sched_requeue_request(rq);
+
         BUG_ON(blk_queued_rq(rq));
         blk_mq_add_to_requeue_list(rq, true, kick_requeue_list);
 }
@@ -3164,6 +3166,7 @@ static bool __blk_mq_poll(struct blk_mq_hw_ctx *hctx, struct request *rq)
                 cpu_relax();
         }
 
+        __set_current_state(TASK_RUNNING);
         return false;
 }
 
diff --git a/block/genhd.c b/block/genhd.c
index 88a53c188cb7..9656f9e9f99e 100644
--- a/block/genhd.c
+++ b/block/genhd.c
@@ -547,7 +547,7 @@ static int exact_lock(dev_t devt, void *data)
 {
         struct gendisk *p = data;
 
-        if (!get_disk(p))
+        if (!get_disk_and_module(p))
                 return -1;
         return 0;
 }
@@ -717,6 +717,11 @@ void del_gendisk(struct gendisk *disk)
         blk_integrity_del(disk);
         disk_del_events(disk);
 
+        /*
+         * Block lookups of the disk until all bdevs are unhashed and the
+         * disk is marked as dead (GENHD_FL_UP cleared).
+         */
+        down_write(&disk->lookup_sem);
         /* invalidate stuff */
         disk_part_iter_init(&piter, disk,
                              DISK_PITER_INCL_EMPTY | DISK_PITER_REVERSE);
@@ -731,6 +736,7 @@ void del_gendisk(struct gendisk *disk)
         bdev_unhash_inode(disk_devt(disk));
         set_capacity(disk, 0);
         disk->flags &= ~GENHD_FL_UP;
+        up_write(&disk->lookup_sem);
 
         if (!(disk->flags & GENHD_FL_HIDDEN))
                 sysfs_remove_link(&disk_to_dev(disk)->kobj, "bdi");
@@ -809,16 +815,28 @@ struct gendisk *get_gendisk(dev_t devt, int *partno)
 
                 spin_lock_bh(&ext_devt_lock);
                 part = idr_find(&ext_devt_idr, blk_mangle_minor(MINOR(devt)));
-                if (part && get_disk(part_to_disk(part))) {
+                if (part && get_disk_and_module(part_to_disk(part))) {
                         *partno = part->partno;
                         disk = part_to_disk(part);
                 }
                 spin_unlock_bh(&ext_devt_lock);
         }
 
-        if (disk && unlikely(disk->flags & GENHD_FL_HIDDEN)) {
-                put_disk(disk);
+        if (!disk)
+                return NULL;
+
+        /*
+         * Synchronize with del_gendisk() to not return disk that is being
+         * destroyed.
+         */
+        down_read(&disk->lookup_sem);
+        if (unlikely((disk->flags & GENHD_FL_HIDDEN) ||
+                     !(disk->flags & GENHD_FL_UP))) {
+                up_read(&disk->lookup_sem);
+                put_disk_and_module(disk);
                 disk = NULL;
+        } else {
+                up_read(&disk->lookup_sem);
         }
         return disk;
 }
@@ -1418,6 +1436,7 @@ struct gendisk *__alloc_disk_node(int minors, int node_id)
                         kfree(disk);
                         return NULL;
                 }
+                init_rwsem(&disk->lookup_sem);
                 disk->node_id = node_id;
                 if (disk_expand_part_tbl(disk, 0)) {
                         free_part_stats(&disk->part0);
@@ -1453,7 +1472,7 @@ struct gendisk *__alloc_disk_node(int minors, int node_id)
 }
 EXPORT_SYMBOL(__alloc_disk_node);
 
-struct kobject *get_disk(struct gendisk *disk)
+struct kobject *get_disk_and_module(struct gendisk *disk)
 {
         struct module *owner;
         struct kobject *kobj;
@@ -1471,17 +1490,30 @@ struct kobject *get_disk(struct gendisk *disk)
         return kobj;
 
 }
-
-EXPORT_SYMBOL(get_disk);
+EXPORT_SYMBOL(get_disk_and_module);
 
 void put_disk(struct gendisk *disk)
 {
         if (disk)
                 kobject_put(&disk_to_dev(disk)->kobj);
 }
-
 EXPORT_SYMBOL(put_disk);
 
+/*
+ * This is a counterpart of get_disk_and_module() and thus also of
+ * get_gendisk().
+ */
+void put_disk_and_module(struct gendisk *disk)
+{
+        if (disk) {
+                struct module *owner = disk->fops->owner;
+
+                put_disk(disk);
+                module_put(owner);
+        }
+}
+EXPORT_SYMBOL(put_disk_and_module);
+
 static void set_disk_ro_uevent(struct gendisk *gd, int ro)
 {
         char event[] = "DISK_RO=1";
diff --git a/block/ioctl.c b/block/ioctl.c
index 1668506d8ed8..3884d810efd2 100644
--- a/block/ioctl.c
+++ b/block/ioctl.c
@@ -225,7 +225,7 @@ static int blk_ioctl_discard(struct block_device *bdev, fmode_t mode,
 
         if (start + len > i_size_read(bdev->bd_inode))
                 return -EINVAL;
-        truncate_inode_pages_range(mapping, start, start + len);
+        truncate_inode_pages_range(mapping, start, start + len - 1);
         return blkdev_issue_discard(bdev, start >> 9, len >> 9,
                                     GFP_KERNEL, flags);
 }
diff --git a/block/kyber-iosched.c b/block/kyber-iosched.c
index f95c60774ce8..0d6d25e32e1f 100644
--- a/block/kyber-iosched.c
+++ b/block/kyber-iosched.c
@@ -833,6 +833,7 @@ static struct elevator_type kyber_sched = {
                 .limit_depth = kyber_limit_depth,
                 .prepare_request = kyber_prepare_request,
                 .finish_request = kyber_finish_request,
+                .requeue_request = kyber_finish_request,
                 .completed_request = kyber_completed_request,
                 .dispatch_request = kyber_dispatch_request,
                 .has_work = kyber_has_work,
diff --git a/block/mq-deadline.c b/block/mq-deadline.c
index c56f211c8440..8ec0ba9f5386 100644
--- a/block/mq-deadline.c
+++ b/block/mq-deadline.c
@@ -536,12 +536,21 @@ static void dd_insert_requests(struct blk_mq_hw_ctx *hctx,
 }
 
 /*
+ * Nothing to do here. This is defined only to ensure that .finish_request
+ * method is called upon request completion.
+ */
+static void dd_prepare_request(struct request *rq, struct bio *bio)
+{
+}
+
+/*
  * For zoned block devices, write unlock the target zone of
  * completed write requests. Do this while holding the zone lock
  * spinlock so that the zone is never unlocked while deadline_fifo_request()
- * while deadline_next_request() are executing.
+ * or deadline_next_request() are executing. This function is called for
+ * all requests, whether or not these requests complete successfully.
  */
-static void dd_completed_request(struct request *rq)
+static void dd_finish_request(struct request *rq)
 {
         struct request_queue *q = rq->q;
 
@@ -756,7 +765,8 @@ static struct elevator_type mq_deadline = {
         .ops.mq = {
                 .insert_requests        = dd_insert_requests,
                 .dispatch_request       = dd_dispatch_request,
-                .completed_request      = dd_completed_request,
+                .prepare_request        = dd_prepare_request,
+                .finish_request         = dd_finish_request,
                 .next_request           = elv_rb_latter_request,
                 .former_request         = elv_rb_former_request,
                 .bio_merge              = dd_bio_merge,
diff --git a/block/partition-generic.c b/block/partition-generic.c
index 91622db9aedf..08dabcd8b6ae 100644
--- a/block/partition-generic.c
+++ b/block/partition-generic.c
@@ -51,6 +51,12 @@ const char *bdevname(struct block_device *bdev, char *buf)
 
 EXPORT_SYMBOL(bdevname);
 
+const char *bio_devname(struct bio *bio, char *buf)
+{
+        return disk_name(bio->bi_disk, bio->bi_partno, buf);
+}
+EXPORT_SYMBOL(bio_devname);
+
 /*
  * There's very little reason to use this, you should really
  * have a struct block_device just about everywhere and use
diff --git a/block/sed-opal.c b/block/sed-opal.c
index 9ed51d0c6b1d..e4929eec547f 100644
--- a/block/sed-opal.c
+++ b/block/sed-opal.c
@@ -490,7 +490,7 @@ static int opal_discovery0_end(struct opal_dev *dev)
 
         if (!found_com_id) {
                 pr_debug("Could not find OPAL comid for device. Returning early\n");
-                return -EOPNOTSUPP;;
+                return -EOPNOTSUPP;
         }
 
         dev->comid = comid;
diff --git a/certs/blacklist_nohashes.c b/certs/blacklist_nohashes.c
index 73fd99098ad7..753b703ef0ef 100644
--- a/certs/blacklist_nohashes.c
+++ b/certs/blacklist_nohashes.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 #include "blacklist.h"
 
-const char __initdata *const blacklist_hashes[] = {
+const char __initconst *const blacklist_hashes[] = {
         NULL
 };
diff --git a/crypto/asymmetric_keys/pkcs7_trust.c b/crypto/asymmetric_keys/pkcs7_trust.c
index 1f4e25f10049..598906b1e28d 100644
--- a/crypto/asymmetric_keys/pkcs7_trust.c
+++ b/crypto/asymmetric_keys/pkcs7_trust.c
@@ -106,6 +106,7 @@ static int pkcs7_validate_trust_one(struct pkcs7_message *pkcs7,
                 pr_devel("sinfo %u: Direct signer is key %x\n",
                          sinfo->index, key_serial(key));
                 x509 = NULL;
+                sig = sinfo->sig;
                 goto matched;
         }
         if (PTR_ERR(key) != -ENOKEY)
diff --git a/crypto/asymmetric_keys/pkcs7_verify.c b/crypto/asymmetric_keys/pkcs7_verify.c
index 39e6de0c2761..97c77f66b20d 100644
--- a/crypto/asymmetric_keys/pkcs7_verify.c
+++ b/crypto/asymmetric_keys/pkcs7_verify.c
@@ -270,7 +270,7 @@ static int pkcs7_verify_sig_chain(struct pkcs7_message *pkcs7,
                                 sinfo->index);
                         return 0;
                 }
-                ret = public_key_verify_signature(p->pub, p->sig);
+                ret = public_key_verify_signature(p->pub, x509->sig);
                 if (ret < 0)
                         return ret;
                 x509->signer = p;
@@ -366,8 +366,7 @@ static int pkcs7_verify_one(struct pkcs7_message *pkcs7,
  *
  *  (*) -EBADMSG if some part of the message was invalid, or:
  *
- *  (*) 0 if no signature chains were found to be blacklisted or to contain
- *      unsupported crypto, or:
+ *  (*) 0 if a signature chain passed verification, or:
  *
  *  (*) -EKEYREJECTED if a blacklisted key was encountered, or:
  *
@@ -423,8 +422,11 @@ int pkcs7_verify(struct pkcs7_message *pkcs7,
 
         for (sinfo = pkcs7->signed_infos; sinfo; sinfo = sinfo->next) {
                 ret = pkcs7_verify_one(pkcs7, sinfo);
-                if (sinfo->blacklisted && actual_ret == -ENOPKG)
-                        actual_ret = -EKEYREJECTED;
+                if (sinfo->blacklisted) {
+                        if (actual_ret == -ENOPKG)
+                                actual_ret = -EKEYREJECTED;
+                        continue;
+                }
                 if (ret < 0) {
                         if (ret == -ENOPKG) {
                                 sinfo->unsupported_crypto = true;
diff --git a/crypto/asymmetric_keys/public_key.c b/crypto/asymmetric_keys/public_key.c
index de996586762a..e929fe1e4106 100644
--- a/crypto/asymmetric_keys/public_key.c
+++ b/crypto/asymmetric_keys/public_key.c
@@ -79,9 +79,11 @@ int public_key_verify_signature(const struct public_key *pkey,
 
         BUG_ON(!pkey);
         BUG_ON(!sig);
-        BUG_ON(!sig->digest);
         BUG_ON(!sig->s);
 
+        if (!sig->digest)
+                return -ENOPKG;
+
         alg_name = sig->pkey_algo;
         if (strcmp(sig->pkey_algo, "rsa") == 0) {
                 /* The data wangled by the RSA algorithm is typically padded
diff --git a/crypto/asymmetric_keys/restrict.c b/crypto/asymmetric_keys/restrict.c
index 86fb68508952..7c93c7728454 100644
--- a/crypto/asymmetric_keys/restrict.c
+++ b/crypto/asymmetric_keys/restrict.c
@@ -67,8 +67,9 @@ __setup("ca_keys=", ca_keys_setup);
  *
  * Returns 0 if the new certificate was accepted, -ENOKEY if we couldn't find a
  * matching parent certificate in the trusted list, -EKEYREJECTED if the
- * signature check fails or the key is blacklisted and some other error if
- * there is a matching certificate but the signature check cannot be performed.
+ * signature check fails or the key is blacklisted, -ENOPKG if the signature
+ * uses unsupported crypto, or some other error if there is a matching
+ * certificate but the signature check cannot be performed.
  */
 int restrict_link_by_signature(struct key *dest_keyring,
                                const struct key_type *type,
@@ -88,6 +89,8 @@ int restrict_link_by_signature(struct key *dest_keyring,
                 return -EOPNOTSUPP;
 
         sig = payload->data[asym_auth];
+        if (!sig)
+                return -ENOPKG;
         if (!sig->auth_ids[0] && !sig->auth_ids[1])
                 return -ENOKEY;
 
@@ -139,6 +142,8 @@ static int key_or_keyring_common(struct key *dest_keyring,
                 return -EOPNOTSUPP;
 
         sig = payload->data[asym_auth];
+        if (!sig)
+                return -ENOPKG;
         if (!sig->auth_ids[0] && !sig->auth_ids[1])
                 return -ENOKEY;
 
@@ -222,9 +227,9 @@ static int key_or_keyring_common(struct key *dest_keyring,
  *
  * Returns 0 if the new certificate was accepted, -ENOKEY if we
  * couldn't find a matching parent certificate in the trusted list,
- * -EKEYREJECTED if the signature check fails, and some other error if
- * there is a matching certificate but the signature check cannot be
- * performed.
+ * -EKEYREJECTED if the signature check fails, -ENOPKG if the signature uses
+ * unsupported crypto, or some other error if there is a matching certificate
+ * but the signature check cannot be performed.
  */
 int restrict_link_by_key_or_keyring(struct key *dest_keyring,
                                     const struct key_type *type,
@@ -249,9 +254,9 @@ int restrict_link_by_key_or_keyring(struct key *dest_keyring,
  *
  * Returns 0 if the new certificate was accepted, -ENOKEY if we
  * couldn't find a matching parent certificate in the trusted list,
- * -EKEYREJECTED if the signature check fails, and some other error if
- * there is a matching certificate but the signature check cannot be
- * performed.
+ * -EKEYREJECTED if the signature check fails, -ENOPKG if the signature uses
+ * unsupported crypto, or some other error if there is a matching certificate
+ * but the signature check cannot be performed.
  */
 int restrict_link_by_key_or_keyring_chain(struct key *dest_keyring,
                                           const struct key_type *type,
diff --git a/crypto/sha3_generic.c b/crypto/sha3_generic.c
index a965b9d80559..ded148783303 100644
--- a/crypto/sha3_generic.c
+++ b/crypto/sha3_generic.c
@@ -20,6 +20,20 @@
 #include <crypto/sha3.h>
 #include <asm/unaligned.h>
 
+/*
+ * On some 32-bit architectures (mn10300 and h8300), GCC ends up using
+ * over 1 KB of stack if we inline the round calculation into the loop
+ * in keccakf(). On the other hand, on 64-bit architectures with plenty
+ * of [64-bit wide] general purpose registers, not inlining it severely
+ * hurts performance. So let's use 64-bitness as a heuristic to decide
+ * whether to inline or not.
+ */
+#ifdef CONFIG_64BIT
+#define SHA3_INLINE     inline
+#else
+#define SHA3_INLINE     noinline
+#endif
+
 #define KECCAK_ROUNDS 24
 
 static const u64 keccakf_rndc[24] = {
@@ -35,111 +49,115 @@ static const u64 keccakf_rndc[24] = {
 
 /* update the state with given number of rounds */
 
-static void __attribute__((__optimize__("O3"))) keccakf(u64 st[25])
+static SHA3_INLINE void keccakf_round(u64 st[25])
 {
         u64 t[5], tt, bc[5];
-        int round;
 
-        for (round = 0; round < KECCAK_ROUNDS; round++) {
+        /* Theta */
+        bc[0] = st[0] ^ st[5] ^ st[10] ^ st[15] ^ st[20];
+        bc[1] = st[1] ^ st[6] ^ st[11] ^ st[16] ^ st[21];
+        bc[2] = st[2] ^ st[7] ^ st[12] ^ st[17] ^ st[22];
+        bc[3] = st[3] ^ st[8] ^ st[13] ^ st[18] ^ st[23];
+        bc[4] = st[4] ^ st[9] ^ st[14] ^ st[19] ^ st[24];
+
+        t[0] = bc[4] ^ rol64(bc[1], 1);
+        t[1] = bc[0] ^ rol64(bc[2], 1);
+        t[2] = bc[1] ^ rol64(bc[3], 1);
+        t[3] = bc[2] ^ rol64(bc[4], 1);
+        t[4] = bc[3] ^ rol64(bc[0], 1);
+
+        st[0] ^= t[0];
+
+        /* Rho Pi */
+        tt = st[1];
+        st[ 1] = rol64(st[ 6] ^ t[1], 44);
+        st[ 6] = rol64(st[ 9] ^ t[4], 20);
+        st[ 9] = rol64(st[22] ^ t[2], 61);
+        st[22] = rol64(st[14] ^ t[4], 39);
+        st[14] = rol64(st[20] ^ t[0], 18);
+        st[20] = rol64(st[ 2] ^ t[2], 62);
+        st[ 2] = rol64(st[12] ^ t[2], 43);
+        st[12] = rol64(st[13] ^ t[3], 25);
+        st[13] = rol64(st[19] ^ t[4],  8);
+        st[19] = rol64(st[23] ^ t[3], 56);
+        st[23] = rol64(st[15] ^ t[0], 41);
+        st[15] = rol64(st[ 4] ^ t[4], 27);
+        st[ 4] = rol64(st[24] ^ t[4], 14);
+        st[24] = rol64(st[21] ^ t[1],  2);
+        st[21] = rol64(st[ 8] ^ t[3], 55);
+        st[ 8] = rol64(st[16] ^ t[1], 45);
+        st[16] = rol64(st[ 5] ^ t[0], 36);
+        st[ 5] = rol64(st[ 3] ^ t[3], 28);
+        st[ 3] = rol64(st[18] ^ t[3], 21);
+        st[18] = rol64(st[17] ^ t[2], 15);
+        st[17] = rol64(st[11] ^ t[1], 10);
+        st[11] = rol64(st[ 7] ^ t[2],  6);
+        st[ 7] = rol64(st[10] ^ t[0],  3);
+        st[10] = rol64(    tt ^ t[1],  1);
+
+        /* Chi */
+        bc[ 0] = ~st[ 1] & st[ 2];
+        bc[ 1] = ~st[ 2] & st[ 3];
+        bc[ 2] = ~st[ 3] & st[ 4];
+        bc[ 3] = ~st[ 4] & st[ 0];
+        bc[ 4] = ~st[ 0] & st[ 1];
+        st[ 0] ^= bc[ 0];
+        st[ 1] ^= bc[ 1];
+        st[ 2] ^= bc[ 2];
+        st[ 3] ^= bc[ 3];
+        st[ 4] ^= bc[ 4];
+
+        bc[ 0] = ~st[ 6] & st[ 7];
+        bc[ 1] = ~st[ 7] & st[ 8];
+        bc[ 2] = ~st[ 8] & st[ 9];
+        bc[ 3] = ~st[ 9] & st[ 5];
+        bc[ 4] = ~st[ 5] & st[ 6];
+        st[ 5] ^= bc[ 0];
+        st[ 6] ^= bc[ 1];
+        st[ 7] ^= bc[ 2];
+        st[ 8] ^= bc[ 3];
+        st[ 9] ^= bc[ 4];
+
+        bc[ 0] = ~st[11] & st[12];
+        bc[ 1] = ~st[12] & st[13];
+        bc[ 2] = ~st[13] & st[14];
+        bc[ 3] = ~st[14] & st[10];
+        bc[ 4] = ~st[10] & st[11];
+        st[10] ^= bc[ 0];
+        st[11] ^= bc[ 1];
+        st[12] ^= bc[ 2];
+        st[13] ^= bc[ 3];
+        st[14] ^= bc[ 4];
+
+        bc[ 0] = ~st[16] & st[17];
+        bc[ 1] = ~st[17] & st[18];
+        bc[ 2] = ~st[18] & st[19];
+        bc[ 3] = ~st[19] & st[15];
+        bc[ 4] = ~st[15] & st[16];
+        st[15] ^= bc[ 0];
+        st[16] ^= bc[ 1];
+        st[17] ^= bc[ 2];
+        st[18] ^= bc[ 3];
+        st[19] ^= bc[ 4];
+
+        bc[ 0] = ~st[21] & st[22];
+        bc[ 1] = ~st[22] & st[23];
+        bc[ 2] = ~st[23] & st[24];
+        bc[ 3] = ~st[24] & st[20];
+        bc[ 4] = ~st[20] & st[21];
+        st[20] ^= bc[ 0];
+        st[21] ^= bc[ 1];
+        st[22] ^= bc[ 2];
+        st[23] ^= bc[ 3];
+        st[24] ^= bc[ 4];
+}
 
-                /* Theta */
-                bc[0] = st[0] ^ st[5] ^ st[10] ^ st[15] ^ st[20];
-                bc[1] = st[1] ^ st[6] ^ st[11] ^ st[16] ^ st[21];
-                bc[2] = st[2] ^ st[7] ^ st[12] ^ st[17] ^ st[22];
-                bc[3] = st[3] ^ st[8] ^ st[13] ^ st[18] ^ st[23];
-                bc[4] = st[4] ^ st[9] ^ st[14] ^ st[19] ^ st[24];
-
-                t[0] = bc[4] ^ rol64(bc[1], 1);
-                t[1] = bc[0] ^ rol64(bc[2], 1);
-                t[2] = bc[1] ^ rol64(bc[3], 1);
-                t[3] = bc[2] ^ rol64(bc[4], 1);
-                t[4] = bc[3] ^ rol64(bc[0], 1);
-
-                st[0] ^= t[0];
-
-                /* Rho Pi */
-                tt = st[1];
-                st[ 1] = rol64(st[ 6] ^ t[1], 44);
-                st[ 6] = rol64(st[ 9] ^ t[4], 20);
-                st[ 9] = rol64(st[22] ^ t[2], 61);
-                st[22] = rol64(st[14] ^ t[4], 39);
-                st[14] = rol64(st[20] ^ t[0], 18);
-                st[20] = rol64(st[ 2] ^ t[2], 62);
-                st[ 2] = rol64(st[12] ^ t[2], 43);
-                st[12] = rol64(st[13] ^ t[3], 25);
-                st[13] = rol64(st[19] ^ t[4],  8);
-                st[19] = rol64(st[23] ^ t[3], 56);
-                st[23] = rol64(st[15] ^ t[0], 41);
-                st[15] = rol64(st[ 4] ^ t[4], 27);
-                st[ 4] = rol64(st[24] ^ t[4], 14);
-                st[24] = rol64(st[21] ^ t[1],  2);
-                st[21] = rol64(st[ 8] ^ t[3], 55);
-                st[ 8] = rol64(st[16] ^ t[1], 45);
-                st[16] = rol64(st[ 5] ^ t[0], 36);
-                st[ 5] = rol64(st[ 3] ^ t[3], 28);
-                st[ 3] = rol64(st[18] ^ t[3], 21);
-                st[18] = rol64(st[17] ^ t[2], 15);
-                st[17] = rol64(st[11] ^ t[1], 10);
-                st[11] = rol64(st[ 7] ^ t[2],  6);
-                st[ 7] = rol64(st[10] ^ t[0],  3);
-                st[10] = rol64(    tt ^ t[1],  1);
-
-                /* Chi */
-                bc[ 0] = ~st[ 1] & st[ 2];
-                bc[ 1] = ~st[ 2] & st[ 3];
-                bc[ 2] = ~st[ 3] & st[ 4];
-                bc[ 3] = ~st[ 4] & st[ 0];
-                bc[ 4] = ~st[ 0] & st[ 1];
-                st[ 0] ^= bc[ 0];
-                st[ 1] ^= bc[ 1];
-                st[ 2] ^= bc[ 2];
-                st[ 3] ^= bc[ 3];
-                st[ 4] ^= bc[ 4];
-
-                bc[ 0] = ~st[ 6] & st[ 7];
-                bc[ 1] = ~st[ 7] & st[ 8];
-                bc[ 2] = ~st[ 8] & st[ 9];
-                bc[ 3] = ~st[ 9] & st[ 5];
-                bc[ 4] = ~st[ 5] & st[ 6];
-                st[ 5] ^= bc[ 0];
-                st[ 6] ^= bc[ 1];
-                st[ 7] ^= bc[ 2];
-                st[ 8] ^= bc[ 3];
-                st[ 9] ^= bc[ 4];
-
-                bc[ 0] = ~st[11] & st[12];
-                bc[ 1] = ~st[12] & st[13];
-                bc[ 2] = ~st[13] & st[14];
-                bc[ 3] = ~st[14] & st[10];
-                bc[ 4] = ~st[10] & st[11];
-                st[10] ^= bc[ 0];
-                st[11] ^= bc[ 1];
-                st[12] ^= bc[ 2];
-                st[13] ^= bc[ 3];
-                st[14] ^= bc[ 4];
-
-                bc[ 0] = ~st[16] & st[17];
-                bc[ 1] = ~st[17] & st[18];
-                bc[ 2] = ~st[18] & st[19];
-                bc[ 3] = ~st[19] & st[15];
-                bc[ 4] = ~st[15] & st[16];
-                st[15] ^= bc[ 0];
-                st[16] ^= bc[ 1];
-                st[17] ^= bc[ 2];
-                st[18] ^= bc[ 3];
-                st[19] ^= bc[ 4];
-
-                bc[ 0] = ~st[21] & st[22];
-                bc[ 1] = ~st[22] & st[23];
-                bc[ 2] = ~st[23] & st[24];
-                bc[ 3] = ~st[24] & st[20];
-                bc[ 4] = ~st[20] & st[21];
-                st[20] ^= bc[ 0];
-                st[21] ^= bc[ 1];
-                st[22] ^= bc[ 2];
-                st[23] ^= bc[ 3];
-                st[24] ^= bc[ 4];
+static void __optimize("O3") keccakf(u64 st[25])
+{
+        int round;
 
+        for (round = 0; round < KECCAK_ROUNDS; round++) {
+                keccakf_round(st);
                 /* Iota */
                 st[0] ^= keccakf_rndc[round];
         }
diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c
index 676c9788e1c8..0dad0bd9327b 100644
--- a/drivers/acpi/bus.c
+++ b/drivers/acpi/bus.c
@@ -660,13 +660,15 @@ struct acpi_device *acpi_companion_match(const struct device *dev)
  * acpi_of_match_device - Match device object using the "compatible" property.
  * @adev: ACPI device object to match.
  * @of_match_table: List of device IDs to match against.
+ * @of_id: OF ID if matched
  *
  * If @dev has an ACPI companion which has ACPI_DT_NAMESPACE_HID in its list of
  * identifiers and a _DSD object with the "compatible" property, use that
  * property to match against the given list of identifiers.
  */
 static bool acpi_of_match_device(struct acpi_device *adev,
-                                 const struct of_device_id *of_match_table)
+                                 const struct of_device_id *of_match_table,
+                                 const struct of_device_id **of_id)
 {
         const union acpi_object *of_compatible, *obj;
         int i, nval;
@@ -690,8 +692,11 @@ static bool acpi_of_match_device(struct acpi_device *adev,
                 const struct of_device_id *id;
 
                 for (id = of_match_table; id->compatible[0]; id++)
-                        if (!strcasecmp(obj->string.pointer, id->compatible))
+                        if (!strcasecmp(obj->string.pointer, id->compatible)) {
+                                if (of_id)
+                                        *of_id = id;
                                 return true;
+                        }
         }
 
         return false;
@@ -762,10 +767,11 @@ static bool __acpi_match_device_cls(const struct acpi_device_id *id,
         return true;
 }
 
-static const struct acpi_device_id *__acpi_match_device(
-        struct acpi_device *device,
-        const struct acpi_device_id *ids,
-        const struct of_device_id *of_ids)
+static bool __acpi_match_device(struct acpi_device *device,
+                                const struct acpi_device_id *acpi_ids,
+                                const struct of_device_id *of_ids,
+                                const struct acpi_device_id **acpi_id,
+                                const struct of_device_id **of_id)
 {
         const struct acpi_device_id *id;
         struct acpi_hardware_id *hwid;
@@ -775,30 +781,32 @@ static const struct acpi_device_id *__acpi_match_device(
          * driver for it.
          */
         if (!device || !device->status.present)
-                return NULL;
+                return false;
 
         list_for_each_entry(hwid, &device->pnp.ids, list) {
                 /* First, check the ACPI/PNP IDs provided by the caller. */
-                for (id = ids; id->id[0] || id->cls; id++) {
-                        if (id->id[0] && !strcmp((char *) id->id, hwid->id))
-                                return id;
-                        else if (id->cls && __acpi_match_device_cls(id, hwid))
-                                return id;
+                if (acpi_ids) {
+                        for (id = acpi_ids; id->id[0] || id->cls; id++) {
+                                if (id->id[0] && !strcmp((char *)id->id, hwid->id))
+                                        goto out_acpi_match;
+                                if (id->cls && __acpi_match_device_cls(id, hwid))
+                                        goto out_acpi_match;
+                        }
                 }
 
                 /*
                  * Next, check ACPI_DT_NAMESPACE_HID and try to match the
                  * "compatible" property if found.
-                 *
-                 * The id returned by the below is not valid, but the only
-                 * caller passing non-NULL of_ids here is only interested in
-                 * whether or not the return value is NULL.
                  */
-                if (!strcmp(ACPI_DT_NAMESPACE_HID, hwid->id)
-                    && acpi_of_match_device(device, of_ids))
-                        return id;
+                if (!strcmp(ACPI_DT_NAMESPACE_HID, hwid->id))
+                        return acpi_of_match_device(device, of_ids, of_id);
         }
-        return NULL;
+        return false;
+
+out_acpi_match:
+        if (acpi_id)
+                *acpi_id = id;
+        return true;
 }
 
 /**
@@ -815,32 +823,29 @@ static const struct acpi_device_id *__acpi_match_device(
 const struct acpi_device_id *acpi_match_device(const struct acpi_device_id *ids,
                                                const struct device *dev)
 {
-        return __acpi_match_device(acpi_companion_match(dev), ids, NULL);
+        const struct acpi_device_id *id = NULL;
+
+        __acpi_match_device(acpi_companion_match(dev), ids, NULL, &id, NULL);
+        return id;
 }
 EXPORT_SYMBOL_GPL(acpi_match_device);
 
-void *acpi_get_match_data(const struct device *dev)
+const void *acpi_device_get_match_data(const struct device *dev)
 {
         const struct acpi_device_id *match;
 
-        if (!dev->driver)
-                return NULL;
-
-        if (!dev->driver->acpi_match_table)
-                return NULL;
-
         match = acpi_match_device(dev->driver->acpi_match_table, dev);
         if (!match)
                 return NULL;
 
-        return (void *)match->driver_data;
+        return (const void *)match->driver_data;
 }
-EXPORT_SYMBOL_GPL(acpi_get_match_data);
+EXPORT_SYMBOL_GPL(acpi_device_get_match_data);
 
 int acpi_match_device_ids(struct acpi_device *device,
                           const struct acpi_device_id *ids)
 {
-        return __acpi_match_device(device, ids, NULL) ? 0 : -ENOENT;
+        return __acpi_match_device(device, ids, NULL, NULL, NULL) ? 0 : -ENOENT;
 }
 EXPORT_SYMBOL(acpi_match_device_ids);
 
@@ -849,10 +854,12 @@ bool acpi_driver_match_device(struct device *dev,
 {
         if (!drv->acpi_match_table)
                 return acpi_of_match_device(ACPI_COMPANION(dev),
-                                            drv->of_match_table);
+                                            drv->of_match_table,
+                                            NULL);
 
-        return !!__acpi_match_device(acpi_companion_match(dev),
-                                     drv->acpi_match_table, drv->of_match_table);
+        return __acpi_match_device(acpi_companion_match(dev),
+                                   drv->acpi_match_table, drv->of_match_table,
+                                   NULL, NULL);
 }
 EXPORT_SYMBOL_GPL(acpi_driver_match_device);
 
diff --git a/drivers/acpi/ec.c b/drivers/acpi/ec.c
index d9f38c645e4a..30a572956557 100644
--- a/drivers/acpi/ec.c
+++ b/drivers/acpi/ec.c
@@ -1927,6 +1927,9 @@ static int acpi_ec_suspend_noirq(struct device *dev)
             ec->reference_count >= 1)
                 acpi_set_gpe(NULL, ec->gpe, ACPI_GPE_DISABLE);
 
+        if (acpi_sleep_no_ec_events())
+                acpi_ec_enter_noirq(ec);
+
         return 0;
 }
 
@@ -1934,6 +1937,9 @@ static int acpi_ec_resume_noirq(struct device *dev)
 {
         struct acpi_ec *ec = acpi_driver_data(to_acpi_device(dev));
 
+        if (acpi_sleep_no_ec_events())
+                acpi_ec_leave_noirq(ec);
+
         if (ec_no_wakeup && test_bit(EC_FLAGS_STARTED, &ec->flags) &&
             ec->reference_count >= 1)
                 acpi_set_gpe(NULL, ec->gpe, ACPI_GPE_ENABLE);
diff --git a/drivers/acpi/property.c b/drivers/acpi/property.c
index 466d1503aba0..5815356ea6ad 100644
--- a/drivers/acpi/property.c
+++ b/drivers/acpi/property.c
@@ -1271,11 +1271,11 @@ static int acpi_fwnode_graph_parse_endpoint(const struct fwnode_handle *fwnode,
         return 0;
 }
 
-static void *
+static const void *
 acpi_fwnode_device_get_match_data(const struct fwnode_handle *fwnode,
                                   const struct device *dev)
 {
-        return acpi_get_match_data(dev);
+        return acpi_device_get_match_data(dev);
 }
 
 #define DECLARE_ACPI_FWNODE_OPS(ops) \
diff --git a/drivers/acpi/spcr.c b/drivers/acpi/spcr.c
index 89e97d21a89c..9d52743080a4 100644
--- a/drivers/acpi/spcr.c
+++ b/drivers/acpi/spcr.c
@@ -115,6 +115,7 @@ int __init acpi_parse_spcr(bool enable_earlycon, bool enable_console)
                         table->serial_port.access_width))) {
                 default:
                         pr_err("Unexpected SPCR Access Width.  Defaulting to byte size\n");
+                        /* fall through */
                 case 8:
                         iotype = "mmio";
                         break;
diff --git a/drivers/android/binder.c b/drivers/android/binder.c
index 15e3d3c2260d..764b63a5aade 100644
--- a/drivers/android/binder.c
+++ b/drivers/android/binder.c
@@ -1991,8 +1991,14 @@ static void binder_send_failed_reply(struct binder_transaction *t,
                                         &target_thread->reply_error.work);
                                 wake_up_interruptible(&target_thread->wait);
                         } else {
-                                WARN(1, "Unexpected reply error: %u\n",
-                                                target_thread->reply_error.cmd);
+                                /*
+                                 * Cannot get here for normal operation, but
+                                 * we can if multiple synchronous transactions
+                                 * are sent without blocking for responses.
+                                 * Just ignore the 2nd error in this case.
+                                 */
+                                pr_warn("Unexpected reply error: %u\n",
+                                        target_thread->reply_error.cmd);
                         }
                         binder_inner_proc_unlock(target_thread->proc);
                         binder_thread_dec_tmpref(target_thread);
@@ -2193,7 +2199,7 @@ static void binder_transaction_buffer_release(struct binder_proc *proc,
         int debug_id = buffer->debug_id;
 
         binder_debug(BINDER_DEBUG_TRANSACTION,
-                     "%d buffer release %d, size %zd-%zd, failed at %p\n",
+                     "%d buffer release %d, size %zd-%zd, failed at %pK\n",
                      proc->pid, buffer->debug_id,
                      buffer->data_size, buffer->offsets_size, failed_at);
 
@@ -3705,7 +3711,7 @@ static int binder_thread_write(struct binder_proc *proc,
                                 }
                         }
                         binder_debug(BINDER_DEBUG_DEAD_BINDER,
-                                     "%d:%d BC_DEAD_BINDER_DONE %016llx found %p\n",
+                                     "%d:%d BC_DEAD_BINDER_DONE %016llx found %pK\n",
                                      proc->pid, thread->pid, (u64)cookie,
                                      death);
                         if (death == NULL) {
@@ -4376,6 +4382,15 @@ static int binder_thread_release(struct binder_proc *proc,
 
         binder_inner_proc_unlock(thread->proc);
 
+        /*
+         * This is needed to avoid races between wake_up_poll() above and
+         * and ep_remove_waitqueue() called for other reasons (eg the epoll file
+         * descriptor being closed); ep_remove_waitqueue() holds an RCU read
+         * lock, so we can be sure it's done after calling synchronize_rcu().
+         */
+        if (thread->looper & BINDER_LOOPER_STATE_POLL)
+                synchronize_rcu();
+
         if (send_reply)
                 binder_send_failed_reply(send_reply, BR_DEAD_REPLY);
         binder_release_work(proc, &thread->todo);
@@ -4391,6 +4406,8 @@ static __poll_t binder_poll(struct file *filp,
         bool wait_for_proc_work;
 
         thread = binder_get_thread(proc);
+        if (!thread)
+                return POLLERR;
 
         binder_inner_proc_lock(thread->proc);
         thread->looper |= BINDER_LOOPER_STATE_POLL;
@@ -5034,7 +5051,7 @@ static void print_binder_transaction_ilocked(struct seq_file *m,
         spin_lock(&t->lock);
         to_proc = t->to_proc;
         seq_printf(m,
-                   "%s %d: %p from %d:%d to %d:%d code %x flags %x pri %ld r%d",
+                   "%s %d: %pK from %d:%d to %d:%d code %x flags %x pri %ld r%d",
                    prefix, t->debug_id, t,
                    t->from ? t->from->proc->pid : 0,
                    t->from ? t->from->pid : 0,
@@ -5058,7 +5075,7 @@ static void print_binder_transaction_ilocked(struct seq_file *m,
         }
         if (buffer->target_node)
                 seq_printf(m, " node %d", buffer->target_node->debug_id);
-        seq_printf(m, " size %zd:%zd data %p\n",
+        seq_printf(m, " size %zd:%zd data %pK\n",
                    buffer->data_size, buffer->offsets_size,
                    buffer->data);
 }
diff --git a/drivers/base/core.c b/drivers/base/core.c
index b2261f92f2f1..5847364f25d9 100644
--- a/drivers/base/core.c
+++ b/drivers/base/core.c
@@ -310,6 +310,9 @@ static void __device_link_del(struct device_link *link)
         dev_info(link->consumer, "Dropping the link to %s\n",
                  dev_name(link->supplier));
 
+        if (link->flags & DL_FLAG_PM_RUNTIME)
+                pm_runtime_drop_link(link->consumer);
+
         list_del(&link->s_node);
         list_del(&link->c_node);
         device_link_free(link);
diff --git a/drivers/base/power/wakeirq.c b/drivers/base/power/wakeirq.c
index a8ac86e4d79e..6637fc319269 100644
--- a/drivers/base/power/wakeirq.c
+++ b/drivers/base/power/wakeirq.c
@@ -321,7 +321,8 @@ void dev_pm_arm_wake_irq(struct wake_irq *wirq)
                 return;
 
         if (device_may_wakeup(wirq->dev)) {
-                if (wirq->status & WAKE_IRQ_DEDICATED_ALLOCATED)
+                if (wirq->status & WAKE_IRQ_DEDICATED_ALLOCATED &&
+                    !pm_runtime_status_suspended(wirq->dev))
                         enable_irq(wirq->irq);
 
                 enable_irq_wake(wirq->irq);
@@ -343,7 +344,8 @@ void dev_pm_disarm_wake_irq(struct wake_irq *wirq)
         if (device_may_wakeup(wirq->dev)) {
                 disable_irq_wake(wirq->irq);
 
-                if (wirq->status & WAKE_IRQ_DEDICATED_ALLOCATED)
+                if (wirq->status & WAKE_IRQ_DEDICATED_ALLOCATED &&
+                    !pm_runtime_status_suspended(wirq->dev))
                         disable_irq_nosync(wirq->irq);
         }
 }
diff --git a/drivers/base/property.c b/drivers/base/property.c
index 302236281d83..8f205f6461ed 100644
--- a/drivers/base/property.c
+++ b/drivers/base/property.c
@@ -1410,9 +1410,8 @@ int fwnode_graph_parse_endpoint(const struct fwnode_handle *fwnode,
 }
 EXPORT_SYMBOL(fwnode_graph_parse_endpoint);
 
-void *device_get_match_data(struct device *dev)
+const void *device_get_match_data(struct device *dev)
 {
-        return fwnode_call_ptr_op(dev_fwnode(dev), device_get_match_data,
-                                  dev);
+        return fwnode_call_ptr_op(dev_fwnode(dev), device_get_match_data, dev);
 }
 EXPORT_SYMBOL_GPL(device_get_match_data);
diff --git a/drivers/block/amiflop.c b/drivers/block/amiflop.c
index e5aa62fcf5a8..3aaf6af3ec23 100644
--- a/drivers/block/amiflop.c
+++ b/drivers/block/amiflop.c
@@ -1758,7 +1758,7 @@ static struct kobject *floppy_find(dev_t dev, int *part, void *data)
         if (unit[drive].type->code == FD_NODRIVE)
                 return NULL;
         *part = 0;
-        return get_disk(unit[drive].gendisk);
+        return get_disk_and_module(unit[drive].gendisk);
 }
 
 static int __init amiga_floppy_probe(struct platform_device *pdev)
diff --git a/drivers/block/ataflop.c b/drivers/block/ataflop.c
index 8bc3b9fd8dd2..dfb2c2622e5a 100644
--- a/drivers/block/ataflop.c
+++ b/drivers/block/ataflop.c
@@ -1917,7 +1917,7 @@ static struct kobject *floppy_find(dev_t dev, int *part, void *data)
         if (drive >= FD_MAX_UNITS || type > NUM_DISK_MINORS)
                 return NULL;
         *part = 0;
-        return get_disk(unit[drive].disk);
+        return get_disk_and_module(unit[drive].disk);
 }
 
 static int __init atari_floppy_init (void)
diff --git a/drivers/block/brd.c b/drivers/block/brd.c
index 8028a3a7e7fd..deea78e485da 100644
--- a/drivers/block/brd.c
+++ b/drivers/block/brd.c
@@ -456,7 +456,7 @@ static struct kobject *brd_probe(dev_t dev, int *part, void *data)
 
         mutex_lock(&brd_devices_mutex);
         brd = brd_init_one(MINOR(dev) / max_part, &new);
-        kobj = brd ? get_disk(brd->brd_disk) : NULL;
+        kobj = brd ? get_disk_and_module(brd->brd_disk) : NULL;
         mutex_unlock(&brd_devices_mutex);
 
         if (new)
diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c
index eae484acfbbc..8ec7235fc93b 100644
--- a/drivers/block/floppy.c
+++ b/drivers/block/floppy.c
@@ -4505,7 +4505,7 @@ static struct kobject *floppy_find(dev_t dev, int *part, void *data)
         if (((*part >> 2) & 0x1f) >= ARRAY_SIZE(floppy_type))
                 return NULL;
         *part = 0;
-        return get_disk(disks[drive]);
+        return get_disk_and_module(disks[drive]);
 }
 
 static int __init do_floppy_init(void)
diff --git a/drivers/block/loop.c b/drivers/block/loop.c
index d5fe720cf149..87855b5123a6 100644
--- a/drivers/block/loop.c
+++ b/drivers/block/loop.c
@@ -1922,7 +1922,7 @@ static struct kobject *loop_probe(dev_t dev, int *part, void *data)
         if (err < 0)
                 kobj = NULL;
         else
-                kobj = get_disk(lo->lo_disk);
+                kobj = get_disk_and_module(lo->lo_disk);
         mutex_unlock(&loop_index_mutex);
 
         *part = 0;
diff --git a/drivers/block/nbd.c b/drivers/block/nbd.c
index 5f2a4240a204..86258b00a1d4 100644
--- a/drivers/block/nbd.c
+++ b/drivers/block/nbd.c
@@ -1591,7 +1591,7 @@ again:
                         if (new_index < 0) {
                                 mutex_unlock(&nbd_index_mutex);
                                 printk(KERN_ERR "nbd: failed to add new device\n");
-                                return ret;
+                                return new_index;
                         }
                         nbd = idr_find(&nbd_index_idr, new_index);
                 }
diff --git a/drivers/block/pktcdvd.c b/drivers/block/pktcdvd.c
index 531a0915066b..c61d20c9f3f8 100644
--- a/drivers/block/pktcdvd.c
+++ b/drivers/block/pktcdvd.c
@@ -1122,7 +1122,7 @@ static int pkt_start_recovery(struct packet_data *pkt)
         pkt->sector = new_sector;
 
         bio_reset(pkt->bio);
-        bio_set_set(pkt->bio, pd->bdev);
+        bio_set_dev(pkt->bio, pd->bdev);
         bio_set_op_attrs(pkt->bio, REQ_OP_WRITE, 0);
         pkt->bio->bi_iter.bi_sector = new_sector;
         pkt->bio->bi_iter.bi_size = pkt->frames * CD_FRAMESIZE;
diff --git a/drivers/block/swim.c b/drivers/block/swim.c
index 84434d3ea19b..64e066eba72e 100644
--- a/drivers/block/swim.c
+++ b/drivers/block/swim.c
@@ -799,7 +799,7 @@ static struct kobject *floppy_find(dev_t dev, int *part, void *data)
                 return NULL;
 
         *part = 0;
-        return get_disk(swd->unit[drive].disk);
+        return get_disk_and_module(swd->unit[drive].disk);
 }
 
 static int swim_add_floppy(struct swim_priv *swd, enum drive_location location)
diff --git a/drivers/block/z2ram.c b/drivers/block/z2ram.c
index 41c95c9b2ab4..8f9130ab5887 100644
--- a/drivers/block/z2ram.c
+++ b/drivers/block/z2ram.c
@@ -332,7 +332,7 @@ static const struct block_device_operations z2_fops =
 static struct kobject *z2_find(dev_t dev, int *part, void *data)
 {
         *part = 0;
-        return get_disk(z2ram_gendisk);
+        return get_disk_and_module(z2ram_gendisk);
 }
 
 static struct request_queue *z2_queue;
diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c
index 4d46003c46cf..cdaeeea7999c 100644
--- a/drivers/bus/ti-sysc.c
+++ b/drivers/bus/ti-sysc.c
@@ -630,7 +630,7 @@ static int sysc_init_dts_quirks(struct sysc *ddata)
         for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) {
                 prop = of_get_property(np, sysc_dts_quirks[i].name, &len);
                 if (!prop)
-                        break;
+                        continue;
 
                 ddata->cfg.quirks |= sysc_dts_quirks[i].mask;
         }
diff --git a/drivers/char/hw_random/via-rng.c b/drivers/char/hw_random/via-rng.c
index d1f5bb534e0e..6e9df558325b 100644
--- a/drivers/char/hw_random/via-rng.c
+++ b/drivers/char/hw_random/via-rng.c
@@ -162,7 +162,7 @@ static int via_rng_init(struct hwrng *rng)
         /* Enable secondary noise source on CPUs where it is present. */
 
         /* Nehemiah stepping 8 and higher */
-        if ((c->x86_model == 9) && (c->x86_mask > 7))
+        if ((c->x86_model == 9) && (c->x86_stepping > 7))
                 lo |= VIA_NOISESRC2;
 
         /* Esther */
diff --git a/drivers/char/tpm/st33zp24/st33zp24.c b/drivers/char/tpm/st33zp24/st33zp24.c
index 4d1dc8b46877..f95b9c75175b 100644
--- a/drivers/char/tpm/st33zp24/st33zp24.c
+++ b/drivers/char/tpm/st33zp24/st33zp24.c
@@ -457,7 +457,7 @@ static int st33zp24_recv(struct tpm_chip *chip, unsigned char *buf,
                             size_t count)
 {
         int size = 0;
-        int expected;
+        u32 expected;
 
         if (!chip)
                 return -EBUSY;
@@ -474,7 +474,7 @@ static int st33zp24_recv(struct tpm_chip *chip, unsigned char *buf,
         }
 
         expected = be32_to_cpu(*(__be32 *)(buf + 2));
-        if (expected > count) {
+        if (expected > count || expected < TPM_HEADER_SIZE) {
                 size = -EIO;
                 goto out;
         }
diff --git a/drivers/char/tpm/tpm-interface.c b/drivers/char/tpm/tpm-interface.c
index 76df4fbcf089..9e80a953d693 100644
--- a/drivers/char/tpm/tpm-interface.c
+++ b/drivers/char/tpm/tpm-interface.c
@@ -1190,6 +1190,10 @@ int tpm_get_random(struct tpm_chip *chip, u8 *out, size_t max)
                         break;
 
                 recd = be32_to_cpu(tpm_cmd.params.getrandom_out.rng_data_len);
+                if (recd > num_bytes) {
+                        total = -EFAULT;
+                        break;
+                }
 
                 rlength = be32_to_cpu(tpm_cmd.header.out.length);
                 if (rlength < offsetof(struct tpm_getrandom_out, rng_data) +
diff --git a/drivers/char/tpm/tpm2-cmd.c b/drivers/char/tpm/tpm2-cmd.c
index c17e75348a99..a700f8f9ead7 100644
--- a/drivers/char/tpm/tpm2-cmd.c
+++ b/drivers/char/tpm/tpm2-cmd.c
@@ -683,6 +683,10 @@ static int tpm2_unseal_cmd(struct tpm_chip *chip,
         if (!rc) {
                 data_len = be16_to_cpup(
                         (__be16 *) &buf.data[TPM_HEADER_SIZE + 4]);
+                if (data_len < MIN_KEY_SIZE ||  data_len > MAX_KEY_SIZE + 1) {
+                        rc = -EFAULT;
+                        goto out;
+                }
 
                 rlength = be32_to_cpu(((struct tpm2_cmd *)&buf)
                                         ->header.out.length);
diff --git a/drivers/char/tpm/tpm_i2c_infineon.c b/drivers/char/tpm/tpm_i2c_infineon.c
index c1dd39eaaeeb..6116cd05e228 100644
--- a/drivers/char/tpm/tpm_i2c_infineon.c
+++ b/drivers/char/tpm/tpm_i2c_infineon.c
@@ -473,7 +473,8 @@ static int recv_data(struct tpm_chip *chip, u8 *buf, size_t count)
 static int tpm_tis_i2c_recv(struct tpm_chip *chip, u8 *buf, size_t count)
 {
         int size = 0;
-        int expected, status;
+        int status;
+        u32 expected;
 
         if (count < TPM_HEADER_SIZE) {
                 size = -EIO;
@@ -488,7 +489,7 @@ static int tpm_tis_i2c_recv(struct tpm_chip *chip, u8 *buf, size_t count)
         }
 
         expected = be32_to_cpu(*(__be32 *)(buf + 2));
-        if ((size_t) expected > count) {
+        if (((size_t) expected > count) || (expected < TPM_HEADER_SIZE)) {
                 size = -EIO;
                 goto out;
         }
diff --git a/drivers/char/tpm/tpm_i2c_nuvoton.c b/drivers/char/tpm/tpm_i2c_nuvoton.c
index c6428771841f..caa86b19c76d 100644
--- a/drivers/char/tpm/tpm_i2c_nuvoton.c
+++ b/drivers/char/tpm/tpm_i2c_nuvoton.c
@@ -281,7 +281,11 @@ static int i2c_nuvoton_recv(struct tpm_chip *chip, u8 *buf, size_t count)
         struct device *dev = chip->dev.parent;
         struct i2c_client *client = to_i2c_client(dev);
         s32 rc;
-        int expected, status, burst_count, retries, size = 0;
+        int status;
+        int burst_count;
+        int retries;
+        int size = 0;
+        u32 expected;
 
         if (count < TPM_HEADER_SIZE) {
                 i2c_nuvoton_ready(chip);    /* return to idle */
@@ -323,7 +327,7 @@ static int i2c_nuvoton_recv(struct tpm_chip *chip, u8 *buf, size_t count)
                  * to machine native
                  */
                 expected = be32_to_cpu(*(__be32 *) (buf + 2));
-                if (expected > count) {
+                if (expected > count || expected < size) {
                         dev_err(dev, "%s() expected > count\n", __func__);
                         size = -EIO;
                         continue;
diff --git a/drivers/char/tpm/tpm_tis_core.c b/drivers/char/tpm/tpm_tis_core.c
index 183a5f54d875..da074e3db19b 100644
--- a/drivers/char/tpm/tpm_tis_core.c
+++ b/drivers/char/tpm/tpm_tis_core.c
@@ -270,7 +270,8 @@ static int tpm_tis_recv(struct tpm_chip *chip, u8 *buf, size_t count)
 {
         struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
         int size = 0;
-        int expected, status;
+        int status;
+        u32 expected;
 
         if (count < TPM_HEADER_SIZE) {
                 size = -EIO;
@@ -285,7 +286,7 @@ static int tpm_tis_recv(struct tpm_chip *chip, u8 *buf, size_t count)
         }
 
         expected = be32_to_cpu(*(__be32 *) (buf + 2));
-        if (expected > count) {
+        if (expected > count || expected < TPM_HEADER_SIZE) {
                 size = -EIO;
                 goto out;
         }
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index 80dc211eb74b..617beb234259 100644
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -795,6 +795,8 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
         clks[IMX7D_DRAM_PHYM_ALT_ROOT_CLK] = imx_clk_gate4("dram_phym_alt_root_clk", "dram_phym_alt_post_div", base + 0x4130, 0);
         clks[IMX7D_DRAM_ALT_ROOT_CLK] = imx_clk_gate4("dram_alt_root_clk", "dram_alt_post_div", base + 0x4130, 0);
         clks[IMX7D_OCOTP_CLK] = imx_clk_gate4("ocotp_clk", "ipg_root_clk", base + 0x4230, 0);
+        clks[IMX7D_SNVS_CLK] = imx_clk_gate4("snvs_clk", "ipg_root_clk", base + 0x4250, 0);
+        clks[IMX7D_CAAM_CLK] = imx_clk_gate4("caam_clk", "ipg_root_clk", base + 0x4240, 0);
         clks[IMX7D_USB_HSIC_ROOT_CLK] = imx_clk_gate4("usb_hsic_root_clk", "usb_hsic_post_div", base + 0x4420, 0);
         clks[IMX7D_SDMA_CORE_CLK] = imx_clk_gate4("sdma_root_clk", "ahb_root_clk", base + 0x4480, 0);
         clks[IMX7D_PCIE_CTRL_ROOT_CLK] = imx_clk_gate4("pcie_ctrl_root_clk", "pcie_ctrl_post_div", base + 0x4600, 0);
@@ -857,6 +859,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
         clks[IMX7D_WDOG2_ROOT_CLK] = imx_clk_gate4("wdog2_root_clk", "wdog_post_div", base + 0x49d0, 0);
         clks[IMX7D_WDOG3_ROOT_CLK] = imx_clk_gate4("wdog3_root_clk", "wdog_post_div", base + 0x49e0, 0);
         clks[IMX7D_WDOG4_ROOT_CLK] = imx_clk_gate4("wdog4_root_clk", "wdog_post_div", base + 0x49f0, 0);
+        clks[IMX7D_KPP_ROOT_CLK] = imx_clk_gate4("kpp_root_clk", "ipg_root_clk", base + 0x4aa0, 0);
         clks[IMX7D_CSI_MCLK_ROOT_CLK] = imx_clk_gate4("csi_mclk_root_clk", "csi_mclk_post_div", base + 0x4490, 0);
         clks[IMX7D_AUDIO_MCLK_ROOT_CLK] = imx_clk_gate4("audio_mclk_root_clk", "audio_mclk_post_div", base + 0x4790, 0);
         clks[IMX7D_WRCLK_ROOT_CLK] = imx_clk_gate4("wrclk_root_clk", "wrclk_post_div", base + 0x47a0, 0);
diff --git a/drivers/clocksource/arc_timer.c b/drivers/clocksource/arc_timer.c
index 4927355f9cbe..471b428d8034 100644
--- a/drivers/clocksource/arc_timer.c
+++ b/drivers/clocksource/arc_timer.c
@@ -251,9 +251,14 @@ static irqreturn_t timer_irq_handler(int irq, void *dev_id)
         int irq_reenable = clockevent_state_periodic(evt);
 
         /*
-         * Any write to CTRL reg ACks the interrupt, we rewrite the
-         * Count when [N]ot [H]alted bit.
-         * And re-arm it if perioid by [I]nterrupt [E]nable bit
+         * 1. ACK the interrupt
+         *    - For ARC700, any write to CTRL reg ACKs it, so just rewrite
+         *      Count when [N]ot [H]alted bit.
+         *    - For HS3x, it is a bit subtle. On taken count-down interrupt,
+         *      IP bit [3] is set, which needs to be cleared for ACK'ing.
+         *      The write below can only update the other two bits, hence
+         *      explicitly clears IP bit
+         * 2. Re-arm interrupt if periodic by writing to IE bit [0]
          */
         write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH);
 
diff --git a/drivers/clocksource/fsl_ftm_timer.c b/drivers/clocksource/fsl_ftm_timer.c
index 3ee7e6fea621..846d18daf893 100644
--- a/drivers/clocksource/fsl_ftm_timer.c
+++ b/drivers/clocksource/fsl_ftm_timer.c
@@ -281,7 +281,7 @@ static int __init __ftm_clk_init(struct device_node *np, char *cnt_name,
 
 static unsigned long __init ftm_clk_init(struct device_node *np)
 {
-        unsigned long freq;
+        long freq;
 
         freq = __ftm_clk_init(np, "ftm-evt-counter-en", "ftm-evt");
         if (freq <= 0)
diff --git a/drivers/clocksource/mips-gic-timer.c b/drivers/clocksource/mips-gic-timer.c
index a04808a21d4e..986b6796b631 100644
--- a/drivers/clocksource/mips-gic-timer.c
+++ b/drivers/clocksource/mips-gic-timer.c
@@ -166,7 +166,7 @@ static int __init __gic_clocksource_init(void)
 
         /* Set clocksource mask. */
         count_width = read_gic_config() & GIC_CONFIG_COUNTBITS;
-        count_width >>= __fls(GIC_CONFIG_COUNTBITS);
+        count_width >>= __ffs(GIC_CONFIG_COUNTBITS);
         count_width *= 4;
         count_width += 32;
         gic_clocksource.mask = CLOCKSOURCE_MASK(count_width);
@@ -205,12 +205,12 @@ static int __init gic_clocksource_of_init(struct device_node *node)
         } else if (of_property_read_u32(node, "clock-frequency",
                                         &gic_frequency)) {
                 pr_err("GIC frequency not specified.\n");
-                return -EINVAL;;
+                return -EINVAL;
         }
         gic_timer_irq = irq_of_parse_and_map(node, 0);
         if (!gic_timer_irq) {
                 pr_err("GIC timer IRQ not specified.\n");
-                return -EINVAL;;
+                return -EINVAL;
         }
 
         ret = __gic_clocksource_init();
diff --git a/drivers/clocksource/timer-sun5i.c b/drivers/clocksource/timer-sun5i.c
index 2a3fe83ec337..3b56ea3f52af 100644
--- a/drivers/clocksource/timer-sun5i.c
+++ b/drivers/clocksource/timer-sun5i.c
@@ -334,7 +334,7 @@ static int __init sun5i_timer_init(struct device_node *node)
         timer_base = of_io_request_and_map(node, 0, of_node_full_name(node));
         if (IS_ERR(timer_base)) {
                 pr_err("Can't map registers\n");
-                return PTR_ERR(timer_base);;
+                return PTR_ERR(timer_base);
         }
 
         irq = irq_of_parse_and_map(node, 0);
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 3a88e33b0cfe..fb586e09682d 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -44,10 +44,10 @@ config ARM_DT_BL_CPUFREQ
 
 config ARM_SCPI_CPUFREQ
         tristate "SCPI based CPUfreq driver"
-        depends on ARM_BIG_LITTLE_CPUFREQ && ARM_SCPI_PROTOCOL && COMMON_CLK_SCPI
+        depends on ARM_SCPI_PROTOCOL && COMMON_CLK_SCPI
         help
-          This adds the CPUfreq driver support for ARM big.LITTLE platforms
-          using SCPI protocol for CPU power management.
+          This adds the CPUfreq driver support for ARM platforms using SCPI
+          protocol for CPU power management.
 
           This driver uses SCPI Message Protocol driver to interact with the
           firmware providing the CPU DVFS functionality.
diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c
index 3a2ca0f79daf..d0c34df0529c 100644
--- a/drivers/cpufreq/acpi-cpufreq.c
+++ b/drivers/cpufreq/acpi-cpufreq.c
@@ -629,7 +629,7 @@ static int acpi_cpufreq_blacklist(struct cpuinfo_x86 *c)
         if (c->x86_vendor == X86_VENDOR_INTEL) {
                 if ((c->x86 == 15) &&
                     (c->x86_model == 6) &&
-                    (c->x86_mask == 8)) {
+                    (c->x86_stepping == 8)) {
                         pr_info("Intel(R) Xeon(R) 7100 Errata AL30, processors may lock up on frequency changes: disabling acpi-cpufreq\n");
                         return -ENODEV;
                     }
diff --git a/drivers/cpufreq/longhaul.c b/drivers/cpufreq/longhaul.c
index 942632a27b50..f730b6528c18 100644
--- a/drivers/cpufreq/longhaul.c
+++ b/drivers/cpufreq/longhaul.c
@@ -775,7 +775,7 @@ static int longhaul_cpu_init(struct cpufreq_policy *policy)
                 break;
 
         case 7:
-                switch (c->x86_mask) {
+                switch (c->x86_stepping) {
                 case 0:
                         longhaul_version = TYPE_LONGHAUL_V1;
                         cpu_model = CPU_SAMUEL2;
@@ -787,7 +787,7 @@ static int longhaul_cpu_init(struct cpufreq_policy *policy)
                         break;
                 case 1 ... 15:
                         longhaul_version = TYPE_LONGHAUL_V2;
-                        if (c->x86_mask < 8) {
+                        if (c->x86_stepping < 8) {
                                 cpu_model = CPU_SAMUEL2;
                                 cpuname = "C3 'Samuel 2' [C5B]";
                         } else {
@@ -814,7 +814,7 @@ static int longhaul_cpu_init(struct cpufreq_policy *policy)
                 numscales = 32;
                 memcpy(mults, nehemiah_mults, sizeof(nehemiah_mults));
                 memcpy(eblcr, nehemiah_eblcr, sizeof(nehemiah_eblcr));
-                switch (c->x86_mask) {
+                switch (c->x86_stepping) {
                 case 0 ... 1:
                         cpu_model = CPU_NEHEMIAH;
                         cpuname = "C3 'Nehemiah A' [C5XLOE]";
diff --git a/drivers/cpufreq/p4-clockmod.c b/drivers/cpufreq/p4-clockmod.c
index fd77812313f3..a25741b1281b 100644
--- a/drivers/cpufreq/p4-clockmod.c
+++ b/drivers/cpufreq/p4-clockmod.c
@@ -168,7 +168,7 @@ static int cpufreq_p4_cpu_init(struct cpufreq_policy *policy)
 #endif
 
         /* Errata workaround */
-        cpuid = (c->x86 << 8) | (c->x86_model << 4) | c->x86_mask;
+        cpuid = (c->x86 << 8) | (c->x86_model << 4) | c->x86_stepping;
         switch (cpuid) {
         case 0x0f07:
         case 0x0f0a:
diff --git a/drivers/cpufreq/powernow-k7.c b/drivers/cpufreq/powernow-k7.c
index 80ac313e6c59..302e9ce793a0 100644
--- a/drivers/cpufreq/powernow-k7.c
+++ b/drivers/cpufreq/powernow-k7.c
@@ -131,7 +131,7 @@ static int check_powernow(void)
                 return 0;
         }
 
-        if ((c->x86_model == 6) && (c->x86_mask == 0)) {
+        if ((c->x86_model == 6) && (c->x86_stepping == 0)) {
                 pr_info("K7 660[A0] core detected, enabling errata workarounds\n");
                 have_a0 = 1;
         }
diff --git a/drivers/cpufreq/s3c24xx-cpufreq.c b/drivers/cpufreq/s3c24xx-cpufreq.c
index 7b596fa38ad2..6bebc1f9f55a 100644
--- a/drivers/cpufreq/s3c24xx-cpufreq.c
+++ b/drivers/cpufreq/s3c24xx-cpufreq.c
@@ -351,7 +351,13 @@ struct clk *s3c_cpufreq_clk_get(struct device *dev, const char *name)
 static int s3c_cpufreq_init(struct cpufreq_policy *policy)
 {
         policy->clk = clk_arm;
-        return cpufreq_generic_init(policy, ftab, cpu_cur.info->latency);
+
+        policy->cpuinfo.transition_latency = cpu_cur.info->latency;
+
+        if (ftab)
+                return cpufreq_table_validate_and_show(policy, ftab);
+
+        return 0;
 }
 
 static int __init s3c_cpufreq_initclks(void)
diff --git a/drivers/cpufreq/scpi-cpufreq.c b/drivers/cpufreq/scpi-cpufreq.c
index c32a833e1b00..d300a163945f 100644
--- a/drivers/cpufreq/scpi-cpufreq.c
+++ b/drivers/cpufreq/scpi-cpufreq.c
@@ -51,15 +51,23 @@ static unsigned int scpi_cpufreq_get_rate(unsigned int cpu)
 static int
 scpi_cpufreq_set_target(struct cpufreq_policy *policy, unsigned int index)
 {
+        unsigned long freq = policy->freq_table[index].frequency;
         struct scpi_data *priv = policy->driver_data;
-        u64 rate = policy->freq_table[index].frequency * 1000;
+        u64 rate = freq * 1000;
         int ret;
 
         ret = clk_set_rate(priv->clk, rate);
-        if (!ret && (clk_get_rate(priv->clk) != rate))
-                ret = -EIO;
 
-        return ret;
+        if (ret)
+                return ret;
+
+        if (clk_get_rate(priv->clk) != rate)
+                return -EIO;
+
+        arch_set_freq_scale(policy->related_cpus, freq,
+                            policy->cpuinfo.max_freq);
+
+        return 0;
 }
 
 static int
diff --git a/drivers/cpufreq/speedstep-centrino.c b/drivers/cpufreq/speedstep-centrino.c
index 41bc5397f4bb..4fa5adf16c70 100644
--- a/drivers/cpufreq/speedstep-centrino.c
+++ b/drivers/cpufreq/speedstep-centrino.c
@@ -37,7 +37,7 @@ struct cpu_id
 {
         __u8    x86;            /* CPU family */
         __u8    x86_model;      /* model */
-        __u8    x86_mask;       /* stepping */
+        __u8    x86_stepping;   /* stepping */
 };
 
 enum {
@@ -277,7 +277,7 @@ static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c,
 {
         if ((c->x86 == x->x86) &&
             (c->x86_model == x->x86_model) &&
-            (c->x86_mask == x->x86_mask))
+            (c->x86_stepping == x->x86_stepping))
                 return 1;
         return 0;
 }
diff --git a/drivers/cpufreq/speedstep-lib.c b/drivers/cpufreq/speedstep-lib.c
index 8085ec9000d1..e3a9962ee410 100644
--- a/drivers/cpufreq/speedstep-lib.c
+++ b/drivers/cpufreq/speedstep-lib.c
@@ -272,9 +272,9 @@ unsigned int speedstep_detect_processor(void)
                 ebx = cpuid_ebx(0x00000001);
                 ebx &= 0x000000FF;
 
-                pr_debug("ebx value is %x, x86_mask is %x\n", ebx, c->x86_mask);
+                pr_debug("ebx value is %x, x86_stepping is %x\n", ebx, c->x86_stepping);
 
-                switch (c->x86_mask) {
+                switch (c->x86_stepping) {
                 case 4:
                         /*
                          * B-stepping [M-P4-M]
@@ -361,7 +361,7 @@ unsigned int speedstep_detect_processor(void)
                                 msr_lo, msr_hi);
                 if ((msr_hi & (1<<18)) &&
                     (relaxed_check ? 1 : (msr_hi & (3<<24)))) {
-                        if (c->x86_mask == 0x01) {
+                        if (c->x86_stepping == 0x01) {
                                 pr_debug("early PIII version\n");
                                 return SPEEDSTEP_CPU_PIII_C_EARLY;
                         } else
diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 75d280cb2dc0..e843cf410373 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -228,12 +228,16 @@ static int instantiate_rng(struct device *ctrldev, int state_handle_mask,
                  * without any error (HW optimizations for later
                  * CAAM eras), then try again.
                  */
+                if (ret)
+                        break;
+
                 rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK;
                 if ((status && status != JRSTA_SSRC_JUMP_HALT_CC) ||
-                    !(rdsta_val & (1 << sh_idx)))
+                    !(rdsta_val & (1 << sh_idx))) {
                         ret = -EAGAIN;
-                if (ret)
                         break;
+                }
+
                 dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx);
                 /* Clear the contents before recreating the descriptor */
                 memset(desc, 0x00, CAAM_CMD_SZ * 7);
diff --git a/drivers/crypto/ccp/psp-dev.c b/drivers/crypto/ccp/psp-dev.c
index fcfa5b1eae61..b3afb6cc9d72 100644
--- a/drivers/crypto/ccp/psp-dev.c
+++ b/drivers/crypto/ccp/psp-dev.c
@@ -211,7 +211,7 @@ static int __sev_platform_shutdown_locked(int *error)
 {
         int ret;
 
-        ret = __sev_do_cmd_locked(SEV_CMD_SHUTDOWN, 0, error);
+        ret = __sev_do_cmd_locked(SEV_CMD_SHUTDOWN, NULL, error);
         if (ret)
                 return ret;
 
@@ -271,7 +271,7 @@ static int sev_ioctl_do_reset(struct sev_issue_cmd *argp)
                         return rc;
         }
 
-        return __sev_do_cmd_locked(SEV_CMD_FACTORY_RESET, 0, &argp->error);
+        return __sev_do_cmd_locked(SEV_CMD_FACTORY_RESET, NULL, &argp->error);
 }
 
 static int sev_ioctl_do_platform_status(struct sev_issue_cmd *argp)
@@ -299,7 +299,7 @@ static int sev_ioctl_do_pek_pdh_gen(int cmd, struct sev_issue_cmd *argp)
                         return rc;
         }
 
-        return __sev_do_cmd_locked(cmd, 0, &argp->error);
+        return __sev_do_cmd_locked(cmd, NULL, &argp->error);
 }
 
 static int sev_ioctl_do_pek_csr(struct sev_issue_cmd *argp)
@@ -624,7 +624,7 @@ EXPORT_SYMBOL_GPL(sev_guest_decommission);
 
 int sev_guest_df_flush(int *error)
 {
-        return sev_do_cmd(SEV_CMD_DF_FLUSH, 0, error);
+        return sev_do_cmd(SEV_CMD_DF_FLUSH, NULL, error);
 }
 EXPORT_SYMBOL_GPL(sev_guest_df_flush);
 
diff --git a/drivers/crypto/padlock-aes.c b/drivers/crypto/padlock-aes.c
index 4b6642a25df5..1c6cbda56afe 100644
--- a/drivers/crypto/padlock-aes.c
+++ b/drivers/crypto/padlock-aes.c
@@ -512,7 +512,7 @@ static int __init padlock_init(void)
 
         printk(KERN_NOTICE PFX "Using VIA PadLock ACE for AES algorithm.\n");
 
-        if (c->x86 == 6 && c->x86_model == 15 && c->x86_mask == 2) {
+        if (c->x86 == 6 && c->x86_model == 15 && c->x86_stepping == 2) {
                 ecb_fetch_blocks = MAX_ECB_FETCH_BLOCKS;
                 cbc_fetch_blocks = MAX_CBC_FETCH_BLOCKS;
                 printk(KERN_NOTICE PFX "VIA Nano stepping 2 detected: enabling workaround.\n");
diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
index 188f44b7eb27..5d64c08b7f47 100644
--- a/drivers/crypto/s5p-sss.c
+++ b/drivers/crypto/s5p-sss.c
@@ -1922,15 +1922,21 @@ static void s5p_aes_crypt_start(struct s5p_aes_dev *dev, unsigned long mode)
         uint32_t aes_control;
         unsigned long flags;
         int err;
+        u8 *iv;
 
         aes_control = SSS_AES_KEY_CHANGE_MODE;
         if (mode & FLAGS_AES_DECRYPT)
                 aes_control |= SSS_AES_MODE_DECRYPT;
 
-        if ((mode & FLAGS_AES_MODE_MASK) == FLAGS_AES_CBC)
+        if ((mode & FLAGS_AES_MODE_MASK) == FLAGS_AES_CBC) {
                 aes_control |= SSS_AES_CHAIN_MODE_CBC;
-        else if ((mode & FLAGS_AES_MODE_MASK) == FLAGS_AES_CTR)
+                iv = req->info;
+        } else if ((mode & FLAGS_AES_MODE_MASK) == FLAGS_AES_CTR) {
                 aes_control |= SSS_AES_CHAIN_MODE_CTR;
+                iv = req->info;
+        } else {
+                iv = NULL; /* AES_ECB */
+        }
 
         if (dev->ctx->keylen == AES_KEYSIZE_192)
                 aes_control |= SSS_AES_KEY_SIZE_192;
@@ -1961,7 +1967,7 @@ static void s5p_aes_crypt_start(struct s5p_aes_dev *dev, unsigned long mode)
                 goto outdata_error;
 
         SSS_AES_WRITE(dev, AES_CONTROL, aes_control);
-        s5p_set_aes(dev, dev->ctx->aes_key, req->info, dev->ctx->keylen);
+        s5p_set_aes(dev, dev->ctx->aes_key, iv, dev->ctx->keylen);
 
         s5p_set_dma_indata(dev,  dev->sg_src);
         s5p_set_dma_outdata(dev, dev->sg_dst);
diff --git a/drivers/crypto/sunxi-ss/sun4i-ss-prng.c b/drivers/crypto/sunxi-ss/sun4i-ss-prng.c
index 0d01d1624252..63d636424161 100644
--- a/drivers/crypto/sunxi-ss/sun4i-ss-prng.c
+++ b/drivers/crypto/sunxi-ss/sun4i-ss-prng.c
@@ -28,7 +28,7 @@ int sun4i_ss_prng_generate(struct crypto_rng *tfm, const u8 *src,
         algt = container_of(alg, struct sun4i_ss_alg_template, alg.rng);
         ss = algt->ss;
 
-        spin_lock(&ss->slock);
+        spin_lock_bh(&ss->slock);
 
         writel(mode, ss->base + SS_CTL);
 
@@ -51,6 +51,6 @@ int sun4i_ss_prng_generate(struct crypto_rng *tfm, const u8 *src,
         }
 
         writel(0, ss->base + SS_CTL);
-        spin_unlock(&ss->slock);
-        return dlen;
+        spin_unlock_bh(&ss->slock);
+        return 0;
 }
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index 9c80e0cb1664..6882fa2f8bad 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -1138,6 +1138,10 @@ static int talitos_sg_map(struct device *dev, struct scatterlist *src,
         struct talitos_private *priv = dev_get_drvdata(dev);
         bool is_sec1 = has_ftr_sec1(priv);
 
+        if (!src) {
+                to_talitos_ptr(ptr, 0, 0, is_sec1);
+                return 1;
+        }
         if (sg_count == 1) {
                 to_talitos_ptr(ptr, sg_dma_address(src) + offset, len, is_sec1);
                 return sg_count;
diff --git a/drivers/dax/super.c b/drivers/dax/super.c
index 473af694ad1c..ecdc292aa4e4 100644
--- a/drivers/dax/super.c
+++ b/drivers/dax/super.c
@@ -246,12 +246,6 @@ long dax_direct_access(struct dax_device *dax_dev, pgoff_t pgoff, long nr_pages,
 {
         long avail;
 
-        /*
-         * The device driver is allowed to sleep, in order to make the
-         * memory directly accessible.
-         */
-        might_sleep();
-
         if (!dax_dev)
                 return -EOPNOTSUPP;
 
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 8b16ec595fa7..329cb96f886f 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -3147,7 +3147,7 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt)
         struct amd64_family_type *fam_type = NULL;
 
         pvt->ext_model  = boot_cpu_data.x86_model >> 4;
-        pvt->stepping   = boot_cpu_data.x86_mask;
+        pvt->stepping   = boot_cpu_data.x86_stepping;
         pvt->model      = boot_cpu_data.x86_model;
         pvt->fam        = boot_cpu_data.x86;
 
diff --git a/drivers/edac/sb_edac.c b/drivers/edac/sb_edac.c
index f34430f99fd8..872100215ca0 100644
--- a/drivers/edac/sb_edac.c
+++ b/drivers/edac/sb_edac.c
@@ -279,7 +279,7 @@ static const u32 correrrthrsld[] = {
  * sbridge structs
  */
 
-#define NUM_CHANNELS            4       /* Max channels per MC */
+#define NUM_CHANNELS            6       /* Max channels per MC */
 #define MAX_DIMMS               3       /* Max DIMMS per channel */
 #define KNL_MAX_CHAS            38      /* KNL max num. of Cache Home Agents */
 #define KNL_MAX_CHANNELS        6       /* KNL max num. of PCI channels */
diff --git a/drivers/extcon/extcon-axp288.c b/drivers/extcon/extcon-axp288.c
index 0a44d43802fe..3ec4c715e240 100644
--- a/drivers/extcon/extcon-axp288.c
+++ b/drivers/extcon/extcon-axp288.c
@@ -1,7 +1,6 @@
 /*
  * extcon-axp288.c - X-Power AXP288 PMIC extcon cable detection driver
  *
- * Copyright (C) 2016-2017 Hans de Goede <hdegoede@redhat.com>
  * Copyright (C) 2015 Intel Corporation
  * Author: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
  *
@@ -98,15 +97,13 @@ struct axp288_extcon_info {
         struct device *dev;
         struct regmap *regmap;
         struct regmap_irq_chip_data *regmap_irqc;
-        struct delayed_work det_work;
         int irq[EXTCON_IRQ_END];
         struct extcon_dev *edev;
         unsigned int previous_cable;
-        bool first_detect_done;
 };
 
 /* Power up/down reason string array */
-static char *axp288_pwr_up_down_info[] = {
+static const char * const axp288_pwr_up_down_info[] = {
         "Last wake caused by user pressing the power button",
         "Last wake caused by a charger insertion",
         "Last wake caused by a battery insertion",
@@ -124,7 +121,7 @@ static char *axp288_pwr_up_down_info[] = {
  */
 static void axp288_extcon_log_rsi(struct axp288_extcon_info *info)
 {
-        char **rsi;
+        const char * const *rsi;
         unsigned int val, i, clear_mask = 0;
         int ret;
 
@@ -140,25 +137,6 @@ static void axp288_extcon_log_rsi(struct axp288_extcon_info *info)
         regmap_write(info->regmap, AXP288_PS_BOOT_REASON_REG, clear_mask);
 }
 
-static void axp288_chrg_detect_complete(struct axp288_extcon_info *info)
-{
-        /*
-         * We depend on other drivers to do things like mux the data lines,
-         * enable/disable vbus based on the id-pin, etc. Sometimes the BIOS has
-         * not set these things up correctly resulting in the initial charger
-         * cable type detection giving a wrong result and we end up not charging
-         * or charging at only 0.5A.
-         *
-         * So we schedule a second cable type detection after 2 seconds to
-         * give the other drivers time to load and do their thing.
-         */
-        if (!info->first_detect_done) {
-                queue_delayed_work(system_wq, &info->det_work,
-                                   msecs_to_jiffies(2000));
-                info->first_detect_done = true;
-        }
-}
-
 static int axp288_handle_chrg_det_event(struct axp288_extcon_info *info)
 {
         int ret, stat, cfg, pwr_stat;
@@ -223,8 +201,6 @@ no_vbus:
                 info->previous_cable = cable;
         }
 
-        axp288_chrg_detect_complete(info);
-
         return 0;
 
 dev_det_ret:
@@ -246,11 +222,8 @@ static irqreturn_t axp288_extcon_isr(int irq, void *data)
         return IRQ_HANDLED;
 }
 
-static void axp288_extcon_det_work(struct work_struct *work)
+static void axp288_extcon_enable(struct axp288_extcon_info *info)
 {
-        struct axp288_extcon_info *info =
-                container_of(work, struct axp288_extcon_info, det_work.work);
-
         regmap_update_bits(info->regmap, AXP288_BC_GLOBAL_REG,
                                                 BC_GLOBAL_RUN, 0);
         /* Enable the charger detection logic */
@@ -272,7 +245,6 @@ static int axp288_extcon_probe(struct platform_device *pdev)
         info->regmap = axp20x->regmap;
         info->regmap_irqc = axp20x->regmap_irqc;
         info->previous_cable = EXTCON_NONE;
-        INIT_DELAYED_WORK(&info->det_work, axp288_extcon_det_work);
 
         platform_set_drvdata(pdev, info);
 
@@ -318,7 +290,7 @@ static int axp288_extcon_probe(struct platform_device *pdev)
         }
 
         /* Start charger cable type detection */
-        queue_delayed_work(system_wq, &info->det_work, 0);
+        axp288_extcon_enable(info);
 
         return 0;
 }
diff --git a/drivers/extcon/extcon-intel-int3496.c b/drivers/extcon/extcon-intel-int3496.c
index c8691b5a9cb0..191e99f06a9a 100644
--- a/drivers/extcon/extcon-intel-int3496.c
+++ b/drivers/extcon/extcon-intel-int3496.c
@@ -153,8 +153,9 @@ static int int3496_probe(struct platform_device *pdev)
                 return ret;
         }
 
-        /* queue initial processing of id-pin */
+        /* process id-pin so that we start with the right status */
         queue_delayed_work(system_wq, &data->work, 0);
+        flush_delayed_work(&data->work);
 
         platform_set_drvdata(pdev, data);
 
diff --git a/drivers/gpio/gpiolib-of.c b/drivers/gpio/gpiolib-of.c
index 564bb7a31da4..84e5a9df2344 100644
--- a/drivers/gpio/gpiolib-of.c
+++ b/drivers/gpio/gpiolib-of.c
@@ -241,6 +241,19 @@ struct gpio_desc *of_find_gpio(struct device *dev, const char *con_id,
 
                 desc = of_get_named_gpiod_flags(dev->of_node, prop_name, idx,
                                                 &of_flags);
+                /*
+                 * -EPROBE_DEFER in our case means that we found a
+                 * valid GPIO property, but no controller has been
+                 * registered so far.
+                 *
+                 * This means we don't need to look any further for
+                 * alternate name conventions, and we should really
+                 * preserve the return code for our user to be able to
+                 * retry probing later.
+                 */
+                if (IS_ERR(desc) && PTR_ERR(desc) == -EPROBE_DEFER)
+                        return desc;
+
                 if (!IS_ERR(desc) || (PTR_ERR(desc) != -ENOENT))
                         break;
         }
@@ -250,7 +263,7 @@ struct gpio_desc *of_find_gpio(struct device *dev, const char *con_id,
                 desc = of_find_spi_gpio(dev, con_id, &of_flags);
 
         /* Special handling for regulator GPIOs if used */
-        if (IS_ERR(desc))
+        if (IS_ERR(desc) && PTR_ERR(desc) != -EPROBE_DEFER)
                 desc = of_find_regulator_gpio(dev, con_id, &of_flags);
 
         if (IS_ERR(desc))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index d5a2eefd6c3e..74edba18b159 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1156,7 +1156,7 @@ static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
 /*
  * Writeback
  */
-#define AMDGPU_MAX_WB 512       /* Reserve at most 512 WB slots for amdgpu-owned rings. */
+#define AMDGPU_MAX_WB 128       /* Reserve at most 128 WB slots for amdgpu-owned rings. */
 
 struct amdgpu_wb {
         struct amdgpu_bo        *wb_obj;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
index e2c3c5ec42d1..c53095b3b0fb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
@@ -568,6 +568,7 @@ static const struct amdgpu_px_quirk amdgpu_px_quirk_list[] = {
         /* HG _PR3 doesn't seem to work on this A+A weston board */
         { 0x1002, 0x6900, 0x1002, 0x0124, AMDGPU_PX_QUIRK_FORCE_ATPX },
         { 0x1002, 0x6900, 0x1028, 0x0812, AMDGPU_PX_QUIRK_FORCE_ATPX },
+        { 0x1002, 0x6900, 0x1028, 0x0813, AMDGPU_PX_QUIRK_FORCE_ATPX },
         { 0, 0, 0, 0, 0 },
 };
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
index 8ca3783f2deb..74d2efaec52f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
@@ -736,9 +736,11 @@ amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force)
         enum drm_connector_status ret = connector_status_disconnected;
         int r;
 
-        r = pm_runtime_get_sync(connector->dev->dev);
-        if (r < 0)
-                return connector_status_disconnected;
+        if (!drm_kms_helper_is_poll_worker()) {
+                r = pm_runtime_get_sync(connector->dev->dev);
+                if (r < 0)
+                        return connector_status_disconnected;
+        }
 
         if (encoder) {
                 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
@@ -757,8 +759,12 @@ amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force)
         /* check acpi lid status ??? */
 
         amdgpu_connector_update_scratch_regs(connector, ret);
-        pm_runtime_mark_last_busy(connector->dev->dev);
-        pm_runtime_put_autosuspend(connector->dev->dev);
+
+        if (!drm_kms_helper_is_poll_worker()) {
+                pm_runtime_mark_last_busy(connector->dev->dev);
+                pm_runtime_put_autosuspend(connector->dev->dev);
+        }
+
         return ret;
 }
 
@@ -868,9 +874,11 @@ amdgpu_connector_vga_detect(struct drm_connector *connector, bool force)
         enum drm_connector_status ret = connector_status_disconnected;
         int r;
 
-        r = pm_runtime_get_sync(connector->dev->dev);
-        if (r < 0)
-                return connector_status_disconnected;
+        if (!drm_kms_helper_is_poll_worker()) {
+                r = pm_runtime_get_sync(connector->dev->dev);
+                if (r < 0)
+                        return connector_status_disconnected;
+        }
 
         encoder = amdgpu_connector_best_single_encoder(connector);
         if (!encoder)
@@ -924,8 +932,10 @@ amdgpu_connector_vga_detect(struct drm_connector *connector, bool force)
         amdgpu_connector_update_scratch_regs(connector, ret);
 
 out:
-        pm_runtime_mark_last_busy(connector->dev->dev);
-        pm_runtime_put_autosuspend(connector->dev->dev);
+        if (!drm_kms_helper_is_poll_worker()) {
+                pm_runtime_mark_last_busy(connector->dev->dev);
+                pm_runtime_put_autosuspend(connector->dev->dev);
+        }
 
         return ret;
 }
@@ -988,9 +998,11 @@ amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force)
         enum drm_connector_status ret = connector_status_disconnected;
         bool dret = false, broken_edid = false;
 
-        r = pm_runtime_get_sync(connector->dev->dev);
-        if (r < 0)
-                return connector_status_disconnected;
+        if (!drm_kms_helper_is_poll_worker()) {
+                r = pm_runtime_get_sync(connector->dev->dev);
+                if (r < 0)
+                        return connector_status_disconnected;
+        }
 
         if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
                 ret = connector->status;
@@ -1115,8 +1127,10 @@ out:
         amdgpu_connector_update_scratch_regs(connector, ret);
 
 exit:
-        pm_runtime_mark_last_busy(connector->dev->dev);
-        pm_runtime_put_autosuspend(connector->dev->dev);
+        if (!drm_kms_helper_is_poll_worker()) {
+                pm_runtime_mark_last_busy(connector->dev->dev);
+                pm_runtime_put_autosuspend(connector->dev->dev);
+        }
 
         return ret;
 }
@@ -1359,9 +1373,11 @@ amdgpu_connector_dp_detect(struct drm_connector *connector, bool force)
         struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
         int r;
 
-        r = pm_runtime_get_sync(connector->dev->dev);
-        if (r < 0)
-                return connector_status_disconnected;
+        if (!drm_kms_helper_is_poll_worker()) {
+                r = pm_runtime_get_sync(connector->dev->dev);
+                if (r < 0)
+                        return connector_status_disconnected;
+        }
 
         if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
                 ret = connector->status;
@@ -1429,8 +1445,10 @@ amdgpu_connector_dp_detect(struct drm_connector *connector, bool force)
 
         amdgpu_connector_update_scratch_regs(connector, ret);
 out:
-        pm_runtime_mark_last_busy(connector->dev->dev);
-        pm_runtime_put_autosuspend(connector->dev->dev);
+        if (!drm_kms_helper_is_poll_worker()) {
+                pm_runtime_mark_last_busy(connector->dev->dev);
+                pm_runtime_put_autosuspend(connector->dev->dev);
+        }
 
         return ret;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 00a50cc5ec9a..af1b879a9ee9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -492,7 +492,7 @@ static int amdgpu_device_wb_init(struct amdgpu_device *adev)
                 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
 
                 /* clear wb memory */
-                memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t));
+                memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t) * 8);
         }
 
         return 0;
@@ -530,8 +530,9 @@ int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb)
  */
 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb)
 {
+        wb >>= 3;
         if (wb < adev->wb.num_wb)
-                __clear_bit(wb >> 3, adev->wb.used);
+                __clear_bit(wb, adev->wb.used);
 }
 
 /**
@@ -1455,11 +1456,6 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
                 if (!adev->ip_blocks[i].status.hw)
                         continue;
-                if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
-                        amdgpu_free_static_csa(adev);
-                        amdgpu_device_wb_fini(adev);
-                        amdgpu_device_vram_scratch_fini(adev);
-                }
 
                 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
                         adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
@@ -1486,6 +1482,13 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
                 if (!adev->ip_blocks[i].status.sw)
                         continue;
+
+                if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
+                        amdgpu_free_static_csa(adev);
+                        amdgpu_device_wb_fini(adev);
+                        amdgpu_device_vram_scratch_fini(adev);
+                }
+
                 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
                 /* XXX handle errors */
                 if (r) {
@@ -2284,14 +2287,6 @@ int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
                                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
                         }
                         drm_modeset_unlock_all(dev);
-                } else {
-                        /*
-                         * There is no equivalent atomic helper to turn on
-                         * display, so we defined our own function for this,
-                         * once suspend resume is supported by the atomic
-                         * framework this will be reworked
-                         */
-                        amdgpu_dm_display_resume(adev);
                 }
         }
 
@@ -2726,7 +2721,6 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
         if (amdgpu_device_has_dc_support(adev)) {
                 if (drm_atomic_helper_resume(adev->ddev, state))
                         dev_info(adev->dev, "drm resume failed:%d\n", r);
-                amdgpu_dm_display_resume(adev);
         } else {
                 drm_helper_resume_force_mode(adev->ddev);
         }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
index e14ab34d8262..7c2be32c5aea 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
@@ -75,7 +75,7 @@ static int amdgpu_gtt_mgr_init(struct ttm_mem_type_manager *man,
 static int amdgpu_gtt_mgr_fini(struct ttm_mem_type_manager *man)
 {
         struct amdgpu_gtt_mgr *mgr = man->priv;
-
+        spin_lock(&mgr->lock);
         drm_mm_takedown(&mgr->mm);
         spin_unlock(&mgr->lock);
         kfree(mgr);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index 56bcd59c3399..36483e0d3c97 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -257,7 +257,8 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
         r = drm_irq_install(adev->ddev, adev->ddev->pdev->irq);
         if (r) {
                 adev->irq.installed = false;
-                flush_work(&adev->hotplug_work);
+                if (!amdgpu_device_has_dc_support(adev))
+                        flush_work(&adev->hotplug_work);
                 cancel_work_sync(&adev->reset_work);
                 return r;
         }
@@ -282,7 +283,8 @@ void amdgpu_irq_fini(struct amdgpu_device *adev)
                 adev->irq.installed = false;
                 if (adev->irq.msi_enabled)
                         pci_disable_msi(adev->pdev);
-                flush_work(&adev->hotplug_work);
+                if (!amdgpu_device_has_dc_support(adev))
+                        flush_work(&adev->hotplug_work);
                 cancel_work_sync(&adev->reset_work);
         }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 2719937e09d6..3b7e7af09ead 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -634,7 +634,7 @@ static int gmc_v9_0_late_init(void *handle)
         for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i)
                 BUG_ON(vm_inv_eng[i] > 16);
 
-        if (adev->asic_type == CHIP_VEGA10) {
+        if (adev->asic_type == CHIP_VEGA10 && !amdgpu_sriov_vf(adev)) {
                 r = gmc_v9_0_ecc_available(adev);
                 if (r == 1) {
                         DRM_INFO("ECC is active.\n");
@@ -682,7 +682,10 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
         adev->mc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
         if (!adev->mc.vram_width) {
                 /* hbm memory channel size */
-                chansize = 128;
+                if (adev->flags & AMD_IS_APU)
+                        chansize = 64;
+                else
+                        chansize = 128;
 
                 tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);
                 tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index e92fb372bc99..91cf95a8c39c 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -238,31 +238,27 @@ static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring)
 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
 {
         struct amdgpu_device *adev = ring->adev;
-        u64 *wptr = NULL;
-        uint64_t local_wptr = 0;
+        u64 wptr;
 
         if (ring->use_doorbell) {
                 /* XXX check if swapping is necessary on BE */
-                wptr = ((u64 *)&adev->wb.wb[ring->wptr_offs]);
-                DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", *wptr);
-                *wptr = (*wptr) >> 2;
-                DRM_DEBUG("wptr/doorbell after shift == 0x%016llx\n", *wptr);
+                wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
+                DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
         } else {
                 u32 lowbit, highbit;
                 int me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
 
-                wptr = &local_wptr;
                 lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR)) >> 2;
                 highbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
 
                 DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n",
                                 me, highbit, lowbit);
-                *wptr = highbit;
-                *wptr = (*wptr) << 32;
-                *wptr |= lowbit;
+                wptr = highbit;
+                wptr = wptr << 32;
+                wptr |= lowbit;
         }
 
-        return *wptr;
+        return wptr >> 2;
 }
 
 /**
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index b2bfedaf57f1..9bab4842cd44 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -1618,7 +1618,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_enc_ring_vm_funcs = {
         .set_wptr = uvd_v6_0_enc_ring_set_wptr,
         .emit_frame_size =
                 4 + /* uvd_v6_0_enc_ring_emit_pipeline_sync */
-                6 + /* uvd_v6_0_enc_ring_emit_vm_flush */
+                5 + /* uvd_v6_0_enc_ring_emit_vm_flush */
                 5 + 5 + /* uvd_v6_0_enc_ring_emit_fence x2 vm fence */
                 1, /* uvd_v6_0_enc_ring_insert_end */
         .emit_ib_size = 5, /* uvd_v6_0_enc_ring_emit_ib */
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 1ce4c98385e3..862835dc054e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -629,11 +629,13 @@ static int dm_resume(void *handle)
 {
         struct amdgpu_device *adev = handle;
         struct amdgpu_display_manager *dm = &adev->dm;
+        int ret = 0;
 
         /* power on hardware */
         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
 
-        return 0;
+        ret = amdgpu_dm_display_resume(adev);
+        return ret;
 }
 
 int amdgpu_dm_display_resume(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 61e8c3e02d16..639421a00ab6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -718,7 +718,7 @@ static enum link_training_result perform_channel_equalization_sequence(
         uint32_t retries_ch_eq;
         enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
         union lane_align_status_updated dpcd_lane_status_updated = {{0}};
-        union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {{{0}}};;
+        union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {{{0}}};
 
         hw_tr_pattern = get_supported_tp(link);
 
@@ -1465,7 +1465,7 @@ void decide_link_settings(struct dc_stream_state *stream,
         /* MST doesn't perform link training for now
          * TODO: add MST specific link training routine
          */
-        if (is_mst_supported(link)) {
+        if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
                 *link_setting = link->verified_link_cap;
                 return;
         }
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 261811e0c094..539c3e0a6292 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -197,7 +197,8 @@ bool dc_stream_set_cursor_attributes(
         for (i = 0; i < MAX_PIPES; i++) {
                 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
 
-                if (pipe_ctx->stream != stream || (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp))
+                if (pipe_ctx->stream != stream || (!pipe_ctx->plane_res.xfm &&
+                    !pipe_ctx->plane_res.dpp) || !pipe_ctx->plane_res.ipp)
                         continue;
                 if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
                         continue;
@@ -273,7 +274,8 @@ bool dc_stream_set_cursor_position(
                 if (pipe_ctx->stream != stream ||
                                 (!pipe_ctx->plane_res.mi  && !pipe_ctx->plane_res.hubp) ||
                                 !pipe_ctx->plane_state ||
-                                (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp))
+                                (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) ||
+                                !pipe_ctx->plane_res.ipp)
                         continue;
 
                 if (pipe_ctx->plane_state->address.type
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 4c3223a4d62b..adb6e7b9280c 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -162,7 +162,7 @@ static int pp_hw_init(void *handle)
                 if(hwmgr->smumgr_funcs->start_smu(pp_handle->hwmgr)) {
                         pr_err("smc start failed\n");
                         hwmgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
-                        return -EINVAL;;
+                        return -EINVAL;
                 }
                 if (ret == PP_DPM_DISABLED)
                         goto exit;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 41e42beff213..08e8a793714f 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -2756,10 +2756,13 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
                                     PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
 
 
-        disable_mclk_switching = ((1 < info.display_count) ||
-                                  disable_mclk_switching_for_frame_lock ||
-                                  smu7_vblank_too_short(hwmgr, mode_info.vblank_time_us) ||
-                                  (mode_info.refresh_rate > 120));
+        if (info.display_count == 0)
+                disable_mclk_switching = false;
+        else
+                disable_mclk_switching = ((1 < info.display_count) ||
+                                          disable_mclk_switching_for_frame_lock ||
+                                          smu7_vblank_too_short(hwmgr, mode_info.vblank_time_us) ||
+                                          (mode_info.refresh_rate > 120));
 
         sclk = smu7_ps->performance_levels[0].engine_clock;
         mclk = smu7_ps->performance_levels[0].memory_clock;
@@ -4534,13 +4537,6 @@ static int smu7_set_power_profile_state(struct pp_hwmgr *hwmgr,
         int tmp_result, result = 0;
         uint32_t sclk_mask = 0, mclk_mask = 0;
 
-        if (hwmgr->chip_id == CHIP_FIJI) {
-                if (request->type == AMD_PP_GFX_PROFILE)
-                        smu7_enable_power_containment(hwmgr);
-                else if (request->type == AMD_PP_COMPUTE_PROFILE)
-                        smu7_disable_power_containment(hwmgr);
-        }
-
         if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_AUTO)
                 return -EINVAL;
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 2d55dabc77d4..5f9c3efb532f 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -3168,10 +3168,13 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
         disable_mclk_switching_for_vr = PP_CAP(PHM_PlatformCaps_DisableMclkSwitchForVR);
         force_mclk_high = PP_CAP(PHM_PlatformCaps_ForceMclkHigh);
 
-        disable_mclk_switching = (info.display_count > 1) ||
-                                    disable_mclk_switching_for_frame_lock ||
-                                    disable_mclk_switching_for_vr ||
-                                    force_mclk_high;
+        if (info.display_count == 0)
+                disable_mclk_switching = false;
+        else
+                disable_mclk_switching = (info.display_count > 1) ||
+                        disable_mclk_switching_for_frame_lock ||
+                        disable_mclk_switching_for_vr ||
+                        force_mclk_high;
 
         sclk = vega10_ps->performance_levels[0].gfx_clock;
         mclk = vega10_ps->performance_levels[0].mem_clock;
diff --git a/drivers/gpu/drm/cirrus/cirrus_mode.c b/drivers/gpu/drm/cirrus/cirrus_mode.c
index cd23b1b28259..c91b9b054e3f 100644
--- a/drivers/gpu/drm/cirrus/cirrus_mode.c
+++ b/drivers/gpu/drm/cirrus/cirrus_mode.c
@@ -294,22 +294,7 @@ static void cirrus_crtc_prepare(struct drm_crtc *crtc)
 {
 }
 
-/*
- * This is called after a mode is programmed. It should reverse anything done
- * by the prepare function
- */
-static void cirrus_crtc_commit(struct drm_crtc *crtc)
-{
-}
-
-/*
- * The core can pass us a set of gamma values to program. We actually only
- * use this for 8-bit mode so can't perform smooth fades on deeper modes,
- * but it's a requirement that we provide the function
- */
-static int cirrus_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
-                                 u16 *blue, uint32_t size,
-                                 struct drm_modeset_acquire_ctx *ctx)
+static void cirrus_crtc_load_lut(struct drm_crtc *crtc)
 {
         struct drm_device *dev = crtc->dev;
         struct cirrus_device *cdev = dev->dev_private;
@@ -317,7 +302,7 @@ static int cirrus_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
         int i;
 
         if (!crtc->enabled)
-                return 0;
+                return;
 
         r = crtc->gamma_store;
         g = r + crtc->gamma_size;
@@ -330,6 +315,27 @@ static int cirrus_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
                 WREG8(PALETTE_DATA, *g++ >> 8);
                 WREG8(PALETTE_DATA, *b++ >> 8);
         }
+}
+
+/*
+ * This is called after a mode is programmed. It should reverse anything done
+ * by the prepare function
+ */
+static void cirrus_crtc_commit(struct drm_crtc *crtc)
+{
+        cirrus_crtc_load_lut(crtc);
+}
+
+/*
+ * The core can pass us a set of gamma values to program. We actually only
+ * use this for 8-bit mode so can't perform smooth fades on deeper modes,
+ * but it's a requirement that we provide the function
+ */
+static int cirrus_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
+                                 u16 *blue, uint32_t size,
+                                 struct drm_modeset_acquire_ctx *ctx)
+{
+        cirrus_crtc_load_lut(crtc);
 
         return 0;
 }
diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c
index ab4032167094..ae3cbfe9e01c 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -1878,6 +1878,8 @@ int drm_atomic_helper_setup_commit(struct drm_atomic_state *state,
                 new_crtc_state->event->base.completion = &commit->flip_done;
                 new_crtc_state->event->base.completion_release = release_crtc_commit;
                 drm_crtc_commit_get(commit);
+
+                commit->abort_completion = true;
         }
 
         for_each_oldnew_connector_in_state(state, conn, old_conn_state, new_conn_state, i) {
@@ -3421,8 +3423,21 @@ EXPORT_SYMBOL(drm_atomic_helper_crtc_duplicate_state);
 void __drm_atomic_helper_crtc_destroy_state(struct drm_crtc_state *state)
 {
         if (state->commit) {
+                /*
+                 * In the event that a non-blocking commit returns
+                 * -ERESTARTSYS before the commit_tail work is queued, we will
+                 * have an extra reference to the commit object. Release it, if
+                 * the event has not been consumed by the worker.
+                 *
+                 * state->event may be freed, so we can't directly look at
+                 * state->event->base.completion.
+                 */
+                if (state->event && state->commit->abort_completion)
+                        drm_crtc_commit_put(state->commit);
+
                 kfree(state->commit->event);
                 state->commit->event = NULL;
+
                 drm_crtc_commit_put(state->commit);
         }
 
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index ddd537914575..4f751a9d71a3 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -113,6 +113,9 @@ static const struct edid_quirk {
         /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
         { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
 
+        /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
+        { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC },
+
         /* Belinea 10 15 55 */
         { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
         { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
@@ -162,6 +165,24 @@ static const struct edid_quirk {
 
         /* HTC Vive VR Headset */
         { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
+
+        /* Oculus Rift DK1, DK2, and CV1 VR Headsets */
+        { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP },
+        { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP },
+        { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP },
+
+        /* Windows Mixed Reality Headsets */
+        { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP },
+        { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP },
+        { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP },
+        { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP },
+        { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP },
+        { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP },
+        { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP },
+        { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP },
+
+        /* Sony PlayStation VR Headset */
+        { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP },
 };
 
 /*
diff --git a/drivers/gpu/drm/drm_framebuffer.c b/drivers/gpu/drm/drm_framebuffer.c
index 5a13ff29f4f0..c0530a1af5e3 100644
--- a/drivers/gpu/drm/drm_framebuffer.c
+++ b/drivers/gpu/drm/drm_framebuffer.c
@@ -121,6 +121,10 @@ int drm_mode_addfb(struct drm_device *dev,
         r.pixel_format = drm_mode_legacy_fb_format(or->bpp, or->depth);
         r.handles[0] = or->handle;
 
+        if (r.pixel_format == DRM_FORMAT_XRGB2101010 &&
+            dev->driver->driver_features & DRIVER_PREFER_XBGR_30BPP)
+                r.pixel_format = DRM_FORMAT_XBGR2101010;
+
         ret = drm_mode_addfb2(dev, &r, file_priv);
         if (ret)
                 return ret;
diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c
index 186c4e90cc1c..89eef1bb4ddc 100644
--- a/drivers/gpu/drm/drm_mm.c
+++ b/drivers/gpu/drm/drm_mm.c
@@ -836,9 +836,24 @@ struct drm_mm_node *drm_mm_scan_color_evict(struct drm_mm_scan *scan)
         if (!mm->color_adjust)
                 return NULL;
 
-        hole = list_first_entry(&mm->hole_stack, typeof(*hole), hole_stack);
-        hole_start = __drm_mm_hole_node_start(hole);
-        hole_end = hole_start + hole->hole_size;
+        /*
+         * The hole found during scanning should ideally be the first element
+         * in the hole_stack list, but due to side-effects in the driver it
+         * may not be.
+         */
+        list_for_each_entry(hole, &mm->hole_stack, hole_stack) {
+                hole_start = __drm_mm_hole_node_start(hole);
+                hole_end = hole_start + hole->hole_size;
+
+                if (hole_start <= scan->hit_start &&
+                    hole_end >= scan->hit_end)
+                        break;
+        }
+
+        /* We should only be called after we found the hole previously */
+        DRM_MM_BUG_ON(&hole->hole_stack == &mm->hole_stack);
+        if (unlikely(&hole->hole_stack == &mm->hole_stack))
+                return NULL;
 
         DRM_MM_BUG_ON(hole_start > scan->hit_start);
         DRM_MM_BUG_ON(hole_end < scan->hit_end);
diff --git a/drivers/gpu/drm/drm_probe_helper.c b/drivers/gpu/drm/drm_probe_helper.c
index 555fbe54d6e2..00b8445ba819 100644
--- a/drivers/gpu/drm/drm_probe_helper.c
+++ b/drivers/gpu/drm/drm_probe_helper.c
@@ -654,6 +654,26 @@ out:
 }
 
 /**
+ * drm_kms_helper_is_poll_worker - is %current task an output poll worker?
+ *
+ * Determine if %current task is an output poll worker.  This can be used
+ * to select distinct code paths for output polling versus other contexts.
+ *
+ * One use case is to avoid a deadlock between the output poll worker and
+ * the autosuspend worker wherein the latter waits for polling to finish
+ * upon calling drm_kms_helper_poll_disable(), while the former waits for
+ * runtime suspend to finish upon calling pm_runtime_get_sync() in a
+ * connector ->detect hook.
+ */
+bool drm_kms_helper_is_poll_worker(void)
+{
+        struct work_struct *work = current_work();
+
+        return work && work->func == output_poll_execute;
+}
+EXPORT_SYMBOL(drm_kms_helper_is_poll_worker);
+
+/**
  * drm_kms_helper_poll_disable - disable output polling
  * @dev: drm_device
  *
diff --git a/drivers/gpu/drm/exynos/exynos_drm_g2d.c b/drivers/gpu/drm/exynos/exynos_drm_g2d.c
index 2b8bf2dd6387..f68ef1b3a28c 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_g2d.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_g2d.c
@@ -286,7 +286,6 @@ static int g2d_init_cmdlist(struct g2d_data *g2d)
 
         node = kcalloc(G2D_CMDLIST_NUM, sizeof(*node), GFP_KERNEL);
         if (!node) {
-                dev_err(dev, "failed to allocate memory\n");
                 ret = -ENOMEM;
                 goto err;
         }
@@ -926,7 +925,7 @@ static void g2d_finish_event(struct g2d_data *g2d, u32 cmdlist_no)
         struct drm_device *drm_dev = g2d->subdrv.drm_dev;
         struct g2d_runqueue_node *runqueue_node = g2d->runqueue_node;
         struct drm_exynos_pending_g2d_event *e;
-        struct timeval now;
+        struct timespec64 now;
 
         if (list_empty(&runqueue_node->event_list))
                 return;
@@ -934,9 +933,9 @@ static void g2d_finish_event(struct g2d_data *g2d, u32 cmdlist_no)
         e = list_first_entry(&runqueue_node->event_list,
                              struct drm_exynos_pending_g2d_event, base.link);
 
-        do_gettimeofday(&now);
+        ktime_get_ts64(&now);
         e->event.tv_sec = now.tv_sec;
-        e->event.tv_usec = now.tv_usec;
+        e->event.tv_usec = now.tv_nsec / NSEC_PER_USEC;
         e->event.cmdlist_no = cmdlist_no;
 
         drm_send_event(drm_dev, &e->base);
@@ -1358,10 +1357,9 @@ int exynos_g2d_exec_ioctl(struct drm_device *drm_dev, void *data,
                 return -EFAULT;
 
         runqueue_node = kmem_cache_alloc(g2d->runqueue_slab, GFP_KERNEL);
-        if (!runqueue_node) {
-                dev_err(dev, "failed to allocate memory\n");
+        if (!runqueue_node)
                 return -ENOMEM;
-        }
+
         run_cmdlist = &runqueue_node->run_cmdlist;
         event_list = &runqueue_node->event_list;
         INIT_LIST_HEAD(run_cmdlist);
diff --git a/drivers/gpu/drm/exynos/exynos_drm_rotator.h b/drivers/gpu/drm/exynos/exynos_drm_rotator.h
deleted file mode 100644
index 71a0b4c0c1e8..000000000000
--- a/drivers/gpu/drm/exynos/exynos_drm_rotator.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * Copyright (c) 2012 Samsung Electronics Co., Ltd.
- *
- * Authors:
- *      YoungJun Cho <yj44.cho@samsung.com>
- *      Eunchul Kim <chulspro.kim@samsung.com>
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#ifndef _EXYNOS_DRM_ROTATOR_H_
-#define _EXYNOS_DRM_ROTATOR_H_
-
-/* TODO */
-
-#endif
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c
index a4b75a46f946..abd84cbcf1c2 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -1068,10 +1068,13 @@ static void hdmi_audio_config(struct hdmi_context *hdata)
         /* Configuration I2S input ports. Configure I2S_PIN_SEL_0~4 */
         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_0, HDMI_I2S_SEL_SCLK(5)
                         | HDMI_I2S_SEL_LRCK(6));
-        hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_1, HDMI_I2S_SEL_SDATA1(1)
-                        | HDMI_I2S_SEL_SDATA2(4));
+
+        hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_1, HDMI_I2S_SEL_SDATA1(3)
+                        | HDMI_I2S_SEL_SDATA0(4));
+
         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_2, HDMI_I2S_SEL_SDATA3(1)
                         | HDMI_I2S_SEL_SDATA2(2));
+
         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_3, HDMI_I2S_SEL_DSD(0));
 
         /* I2S_CON_1 & 2 */
diff --git a/drivers/gpu/drm/exynos/regs-fimc.h b/drivers/gpu/drm/exynos/regs-fimc.h
index 30496134a3d0..d7cbe53c4c01 100644
--- a/drivers/gpu/drm/exynos/regs-fimc.h
+++ b/drivers/gpu/drm/exynos/regs-fimc.h
@@ -569,7 +569,7 @@
 #define EXYNOS_CIIMGEFF_FIN_EMBOSSING           (4 << 26)
 #define EXYNOS_CIIMGEFF_FIN_SILHOUETTE          (5 << 26)
 #define EXYNOS_CIIMGEFF_FIN_MASK                        (7 << 26)
-#define EXYNOS_CIIMGEFF_PAT_CBCR_MASK           ((0xff < 13) | (0xff < 0))
+#define EXYNOS_CIIMGEFF_PAT_CBCR_MASK           ((0xff << 13) | (0xff << 0))
 
 /* Real input DMA size register */
 #define EXYNOS_CIREAL_ISIZE_AUTOLOAD_ENABLE     (1 << 31)
diff --git a/drivers/gpu/drm/exynos/regs-hdmi.h b/drivers/gpu/drm/exynos/regs-hdmi.h
index 04be0f7e8193..4420c203ac85 100644
--- a/drivers/gpu/drm/exynos/regs-hdmi.h
+++ b/drivers/gpu/drm/exynos/regs-hdmi.h
@@ -464,7 +464,7 @@
 
 /* I2S_PIN_SEL_1 */
 #define HDMI_I2S_SEL_SDATA1(x)          (((x) & 0x7) << 4)
-#define HDMI_I2S_SEL_SDATA2(x)          ((x) & 0x7)
+#define HDMI_I2S_SEL_SDATA0(x)          ((x) & 0x7)
 
 /* I2S_PIN_SEL_2 */
 #define HDMI_I2S_SEL_SDATA3(x)          (((x) & 0x7) << 4)
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index 909499b73d03..021f722e2481 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -733,6 +733,25 @@ static ssize_t intel_vgpu_rw(struct mdev_device *mdev, char *buf,
         return ret == 0 ? count : ret;
 }
 
+static bool gtt_entry(struct mdev_device *mdev, loff_t *ppos)
+{
+        struct intel_vgpu *vgpu = mdev_get_drvdata(mdev);
+        unsigned int index = VFIO_PCI_OFFSET_TO_INDEX(*ppos);
+        struct intel_gvt *gvt = vgpu->gvt;
+        int offset;
+
+        /* Only allow MMIO GGTT entry access */
+        if (index != PCI_BASE_ADDRESS_0)
+                return false;
+
+        offset = (u64)(*ppos & VFIO_PCI_OFFSET_MASK) -
+                intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_0);
+
+        return (offset >= gvt->device_info.gtt_start_offset &&
+                offset < gvt->device_info.gtt_start_offset + gvt_ggtt_sz(gvt)) ?
+                        true : false;
+}
+
 static ssize_t intel_vgpu_read(struct mdev_device *mdev, char __user *buf,
                         size_t count, loff_t *ppos)
 {
@@ -742,7 +761,21 @@ static ssize_t intel_vgpu_read(struct mdev_device *mdev, char __user *buf,
         while (count) {
                 size_t filled;
 
-                if (count >= 4 && !(*ppos % 4)) {
+                /* Only support GGTT entry 8 bytes read */
+                if (count >= 8 && !(*ppos % 8) &&
+                        gtt_entry(mdev, ppos)) {
+                        u64 val;
+
+                        ret = intel_vgpu_rw(mdev, (char *)&val, sizeof(val),
+                                        ppos, false);
+                        if (ret <= 0)
+                                goto read_err;
+
+                        if (copy_to_user(buf, &val, sizeof(val)))
+                                goto read_err;
+
+                        filled = 8;
+                } else if (count >= 4 && !(*ppos % 4)) {
                         u32 val;
 
                         ret = intel_vgpu_rw(mdev, (char *)&val, sizeof(val),
@@ -802,7 +835,21 @@ static ssize_t intel_vgpu_write(struct mdev_device *mdev,
         while (count) {
                 size_t filled;
 
-                if (count >= 4 && !(*ppos % 4)) {
+                /* Only support GGTT entry 8 bytes write */
+                if (count >= 8 && !(*ppos % 8) &&
+                        gtt_entry(mdev, ppos)) {
+                        u64 val;
+
+                        if (copy_from_user(&val, buf, sizeof(val)))
+                                goto write_err;
+
+                        ret = intel_vgpu_rw(mdev, (char *)&val, sizeof(val),
+                                        ppos, true);
+                        if (ret <= 0)
+                                goto write_err;
+
+                        filled = 8;
+                } else if (count >= 4 && !(*ppos % 4)) {
                         u32 val;
 
                         if (copy_from_user(&val, buf, sizeof(val)))
diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
index 73ad6e90e49d..256f1bb522b7 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -118,6 +118,7 @@ static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
         {RCS, HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */
         {RCS, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */
         {RCS, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */
+        {RCS, GEN8_ROW_CHICKEN, 0xffff, true}, /* 0xe4f0 */
         {RCS, TRVATTL3PTRDW(0), 0, false}, /* 0x4de0 */
         {RCS, TRVATTL3PTRDW(1), 0, false}, /* 0x4de4 */
         {RCS, TRNULLDETCT, 0, false}, /* 0x4de8 */
diff --git a/drivers/gpu/drm/i915/gvt/trace.h b/drivers/gpu/drm/i915/gvt/trace.h
index 7a2511538f34..736bd2bc5127 100644
--- a/drivers/gpu/drm/i915/gvt/trace.h
+++ b/drivers/gpu/drm/i915/gvt/trace.h
@@ -333,7 +333,7 @@ TRACE_EVENT(render_mmio,
         TP_PROTO(int old_id, int new_id, char *action, unsigned int reg,
                  unsigned int old_val, unsigned int new_val),
 
-        TP_ARGS(old_id, new_id, action, reg, new_val, old_val),
+        TP_ARGS(old_id, new_id, action, reg, old_val, new_val),
 
         TP_STRUCT__entry(
                 __field(int, old_id)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 173d0095e3b2..2f5209de0391 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1433,19 +1433,7 @@ void i915_driver_unload(struct drm_device *dev)
 
         intel_modeset_cleanup(dev);
 
-        /*
-         * free the memory space allocated for the child device
-         * config parsed from VBT
-         */
-        if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
-                kfree(dev_priv->vbt.child_dev);
-                dev_priv->vbt.child_dev = NULL;
-                dev_priv->vbt.child_dev_num = 0;
-        }
-        kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
-        dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
-        kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
-        dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
+        intel_bios_cleanup(dev_priv);
 
         vga_switcheroo_unregister_client(pdev);
         vga_client_register(pdev, NULL, NULL, NULL);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a42deebedb0f..d307429a5ae0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1349,6 +1349,7 @@ struct intel_vbt_data {
                 u32 size;
                 u8 *data;
                 const u8 *sequence[MIPI_SEQ_MAX];
+                u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
         } dsi;
 
         int crt_ddc_pin;
@@ -3657,6 +3658,7 @@ extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
 
 /* intel_bios.c */
 void intel_bios_init(struct drm_i915_private *dev_priv);
+void intel_bios_cleanup(struct drm_i915_private *dev_priv);
 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 648e7536ff51..0c963fcf31ff 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -803,7 +803,7 @@ int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
 
         case I915_CONTEXT_PARAM_PRIORITY:
                 {
-                        int priority = args->value;
+                        s64 priority = args->value;
 
                         if (args->size)
                                 ret = -EINVAL;
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 4401068ff468..3ab1ace2a6bd 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -505,6 +505,8 @@ eb_add_vma(struct i915_execbuffer *eb, unsigned int i, struct i915_vma *vma)
                 list_add_tail(&vma->exec_link, &eb->unbound);
                 if (drm_mm_node_allocated(&vma->node))
                         err = i915_vma_unbind(vma);
+                if (unlikely(err))
+                        vma->exec_flags = NULL;
         }
         return err;
 }
@@ -2410,7 +2412,7 @@ err_request:
         if (out_fence) {
                 if (err == 0) {
                         fd_install(out_fence_fd, out_fence->file);
-                        args->rsvd2 &= GENMASK_ULL(0, 31); /* keep in-fence */
+                        args->rsvd2 &= GENMASK_ULL(31, 0); /* keep in-fence */
                         args->rsvd2 |= (u64)out_fence_fd << 32;
                         out_fence_fd = -1;
                 } else {
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c
index e09d18df8b7f..a3e93d46316a 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -476,8 +476,6 @@ void __i915_gem_request_submit(struct drm_i915_gem_request *request)
         GEM_BUG_ON(!irqs_disabled());
         lockdep_assert_held(&engine->timeline->lock);
 
-        trace_i915_gem_request_execute(request);
-
         /* Transfer from per-context onto the global per-engine timeline */
         timeline = engine->timeline;
         GEM_BUG_ON(timeline == request->timeline);
@@ -501,6 +499,8 @@ void __i915_gem_request_submit(struct drm_i915_gem_request *request)
         list_move_tail(&request->link, &timeline->requests);
         spin_unlock(&request->timeline->lock);
 
+        trace_i915_gem_request_execute(request);
+
         wake_up_all(&request->execute);
 }
 
diff --git a/drivers/gpu/drm/i915/i915_oa_cflgt3.c b/drivers/gpu/drm/i915/i915_oa_cflgt3.c
index 42ff06fe54a3..792facdb6702 100644
--- a/drivers/gpu/drm/i915/i915_oa_cflgt3.c
+++ b/drivers/gpu/drm/i915/i915_oa_cflgt3.c
@@ -84,9 +84,9 @@ show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
 void
 i915_perf_load_test_config_cflgt3(struct drm_i915_private *dev_priv)
 {
-        strncpy(dev_priv->perf.oa.test_config.uuid,
+        strlcpy(dev_priv->perf.oa.test_config.uuid,
                 "577e8e2c-3fa0-4875-8743-3538d585e3b0",
-                UUID_STRING_LEN);
+                sizeof(dev_priv->perf.oa.test_config.uuid));
         dev_priv->perf.oa.test_config.id = 1;
 
         dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa;
diff --git a/drivers/gpu/drm/i915/i915_oa_cnl.c b/drivers/gpu/drm/i915/i915_oa_cnl.c
index ff0ac3627cc4..ba9140c87cc0 100644
--- a/drivers/gpu/drm/i915/i915_oa_cnl.c
+++ b/drivers/gpu/drm/i915/i915_oa_cnl.c
@@ -96,9 +96,9 @@ show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
 void
 i915_perf_load_test_config_cnl(struct drm_i915_private *dev_priv)
 {
-        strncpy(dev_priv->perf.oa.test_config.uuid,
+        strlcpy(dev_priv->perf.oa.test_config.uuid,
                 "db41edd4-d8e7-4730-ad11-b9a2d6833503",
-                UUID_STRING_LEN);
+                sizeof(dev_priv->perf.oa.test_config.uuid));
         dev_priv->perf.oa.test_config.id = 1;
 
         dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa;
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 55a8a1e29424..0e9b98c32b62 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -285,26 +285,41 @@ static u64 count_interrupts(struct drm_i915_private *i915)
         return sum;
 }
 
-static void i915_pmu_event_destroy(struct perf_event *event)
+static void engine_event_destroy(struct perf_event *event)
 {
-        WARN_ON(event->parent);
+        struct drm_i915_private *i915 =
+                container_of(event->pmu, typeof(*i915), pmu.base);
+        struct intel_engine_cs *engine;
+
+        engine = intel_engine_lookup_user(i915,
+                                          engine_event_class(event),
+                                          engine_event_instance(event));
+        if (WARN_ON_ONCE(!engine))
+                return;
+
+        if (engine_event_sample(event) == I915_SAMPLE_BUSY &&
+            intel_engine_supports_stats(engine))
+                intel_disable_engine_stats(engine);
 }
 
-static int engine_event_init(struct perf_event *event)
+static void i915_pmu_event_destroy(struct perf_event *event)
 {
-        struct drm_i915_private *i915 =
-                container_of(event->pmu, typeof(*i915), pmu.base);
+        WARN_ON(event->parent);
 
-        if (!intel_engine_lookup_user(i915, engine_event_class(event),
-                                      engine_event_instance(event)))
-                return -ENODEV;
+        if (is_engine_event(event))
+                engine_event_destroy(event);
+}
 
-        switch (engine_event_sample(event)) {
+static int
+engine_event_status(struct intel_engine_cs *engine,
+                    enum drm_i915_pmu_engine_sample sample)
+{
+        switch (sample) {
         case I915_SAMPLE_BUSY:
         case I915_SAMPLE_WAIT:
                 break;
         case I915_SAMPLE_SEMA:
-                if (INTEL_GEN(i915) < 6)
+                if (INTEL_GEN(engine->i915) < 6)
                         return -ENODEV;
                 break;
         default:
@@ -314,6 +329,30 @@ static int engine_event_init(struct perf_event *event)
         return 0;
 }
 
+static int engine_event_init(struct perf_event *event)
+{
+        struct drm_i915_private *i915 =
+                container_of(event->pmu, typeof(*i915), pmu.base);
+        struct intel_engine_cs *engine;
+        u8 sample;
+        int ret;
+
+        engine = intel_engine_lookup_user(i915, engine_event_class(event),
+                                          engine_event_instance(event));
+        if (!engine)
+                return -ENODEV;
+
+        sample = engine_event_sample(event);
+        ret = engine_event_status(engine, sample);
+        if (ret)
+                return ret;
+
+        if (sample == I915_SAMPLE_BUSY && intel_engine_supports_stats(engine))
+                ret = intel_enable_engine_stats(engine);
+
+        return ret;
+}
+
 static int i915_pmu_event_init(struct perf_event *event)
 {
         struct drm_i915_private *i915 =
@@ -370,7 +409,94 @@ static int i915_pmu_event_init(struct perf_event *event)
         return 0;
 }
 
-static u64 __i915_pmu_event_read(struct perf_event *event)
+static u64 __get_rc6(struct drm_i915_private *i915)
+{
+        u64 val;
+
+        val = intel_rc6_residency_ns(i915,
+                                     IS_VALLEYVIEW(i915) ?
+                                     VLV_GT_RENDER_RC6 :
+                                     GEN6_GT_GFX_RC6);
+
+        if (HAS_RC6p(i915))
+                val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6p);
+
+        if (HAS_RC6pp(i915))
+                val += intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6pp);
+
+        return val;
+}
+
+static u64 get_rc6(struct drm_i915_private *i915, bool locked)
+{
+#if IS_ENABLED(CONFIG_PM)
+        unsigned long flags;
+        u64 val;
+
+        if (intel_runtime_pm_get_if_in_use(i915)) {
+                val = __get_rc6(i915);
+                intel_runtime_pm_put(i915);
+
+                /*
+                 * If we are coming back from being runtime suspended we must
+                 * be careful not to report a larger value than returned
+                 * previously.
+                 */
+
+                if (!locked)
+                        spin_lock_irqsave(&i915->pmu.lock, flags);
+
+                if (val >= i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur) {
+                        i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur = 0;
+                        i915->pmu.sample[__I915_SAMPLE_RC6].cur = val;
+                } else {
+                        val = i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur;
+                }
+
+                if (!locked)
+                        spin_unlock_irqrestore(&i915->pmu.lock, flags);
+        } else {
+                struct pci_dev *pdev = i915->drm.pdev;
+                struct device *kdev = &pdev->dev;
+                unsigned long flags2;
+
+                /*
+                 * We are runtime suspended.
+                 *
+                 * Report the delta from when the device was suspended to now,
+                 * on top of the last known real value, as the approximated RC6
+                 * counter value.
+                 */
+                if (!locked)
+                        spin_lock_irqsave(&i915->pmu.lock, flags);
+
+                spin_lock_irqsave(&kdev->power.lock, flags2);
+
+                if (!i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur)
+                        i915->pmu.suspended_jiffies_last =
+                                                kdev->power.suspended_jiffies;
+
+                val = kdev->power.suspended_jiffies -
+                      i915->pmu.suspended_jiffies_last;
+                val += jiffies - kdev->power.accounting_timestamp;
+
+                spin_unlock_irqrestore(&kdev->power.lock, flags2);
+
+                val = jiffies_to_nsecs(val);
+                val += i915->pmu.sample[__I915_SAMPLE_RC6].cur;
+                i915->pmu.sample[__I915_SAMPLE_RC6_ESTIMATED].cur = val;
+
+                if (!locked)
+                        spin_unlock_irqrestore(&i915->pmu.lock, flags);
+        }
+
+        return val;
+#else
+        return __get_rc6(i915);
+#endif
+}
+
+static u64 __i915_pmu_event_read(struct perf_event *event, bool locked)
 {
         struct drm_i915_private *i915 =
                 container_of(event->pmu, typeof(*i915), pmu.base);
@@ -387,7 +513,7 @@ static u64 __i915_pmu_event_read(struct perf_event *event)
                 if (WARN_ON_ONCE(!engine)) {
                         /* Do nothing */
                 } else if (sample == I915_SAMPLE_BUSY &&
-                           engine->pmu.busy_stats) {
+                           intel_engine_supports_stats(engine)) {
                         val = ktime_to_ns(intel_engine_get_busy_time(engine));
                 } else {
                         val = engine->pmu.sample[sample].cur;
@@ -408,18 +534,7 @@ static u64 __i915_pmu_event_read(struct perf_event *event)
                         val = count_interrupts(i915);
                         break;
                 case I915_PMU_RC6_RESIDENCY:
-                        intel_runtime_pm_get(i915);
-                        val = intel_rc6_residency_ns(i915,
-                                                     IS_VALLEYVIEW(i915) ?
-                                                     VLV_GT_RENDER_RC6 :
-                                                     GEN6_GT_GFX_RC6);
-                        if (HAS_RC6p(i915))
-                                val += intel_rc6_residency_ns(i915,
-                                                              GEN6_GT_GFX_RC6p);
-                        if (HAS_RC6pp(i915))
-                                val += intel_rc6_residency_ns(i915,
-                                                              GEN6_GT_GFX_RC6pp);
-                        intel_runtime_pm_put(i915);
+                        val = get_rc6(i915, locked);
                         break;
                 }
         }
@@ -434,7 +549,7 @@ static void i915_pmu_event_read(struct perf_event *event)
 
 again:
         prev = local64_read(&hwc->prev_count);
-        new = __i915_pmu_event_read(event);
+        new = __i915_pmu_event_read(event, false);
 
         if (local64_cmpxchg(&hwc->prev_count, prev, new) != prev)
                 goto again;
@@ -442,12 +557,6 @@ again:
         local64_add(new - prev, &event->count);
 }
 
-static bool engine_needs_busy_stats(struct intel_engine_cs *engine)
-{
-        return intel_engine_supports_stats(engine) &&
-               (engine->pmu.enable & BIT(I915_SAMPLE_BUSY));
-}
-
 static void i915_pmu_enable(struct perf_event *event)
 {
         struct drm_i915_private *i915 =
@@ -487,21 +596,7 @@ static void i915_pmu_enable(struct perf_event *event)
 
                 GEM_BUG_ON(sample >= I915_PMU_SAMPLE_BITS);
                 GEM_BUG_ON(engine->pmu.enable_count[sample] == ~0);
-                if (engine->pmu.enable_count[sample]++ == 0) {
-                        /*
-                         * Enable engine busy stats tracking if needed or
-                         * alternatively cancel the scheduled disable.
-                         *
-                         * If the delayed disable was pending, cancel it and
-                         * in this case do not enable since it already is.
-                         */
-                        if (engine_needs_busy_stats(engine) &&
-                            !engine->pmu.busy_stats) {
-                                engine->pmu.busy_stats = true;
-                                if (!cancel_delayed_work(&engine->pmu.disable_busy_stats))
-                                        intel_enable_engine_stats(engine);
-                        }
-                }
+                engine->pmu.enable_count[sample]++;
         }
 
         /*
@@ -509,19 +604,11 @@ static void i915_pmu_enable(struct perf_event *event)
          * for all listeners. Even when the event was already enabled and has
          * an existing non-zero value.
          */
-        local64_set(&event->hw.prev_count, __i915_pmu_event_read(event));
+        local64_set(&event->hw.prev_count, __i915_pmu_event_read(event, true));
 
         spin_unlock_irqrestore(&i915->pmu.lock, flags);
 }
 
-static void __disable_busy_stats(struct work_struct *work)
-{
-        struct intel_engine_cs *engine =
-               container_of(work, typeof(*engine), pmu.disable_busy_stats.work);
-
-        intel_disable_engine_stats(engine);
-}
-
 static void i915_pmu_disable(struct perf_event *event)
 {
         struct drm_i915_private *i915 =
@@ -545,26 +632,8 @@ static void i915_pmu_disable(struct perf_event *event)
                  * Decrement the reference count and clear the enabled
                  * bitmask when the last listener on an event goes away.
                  */
-                if (--engine->pmu.enable_count[sample] == 0) {
+                if (--engine->pmu.enable_count[sample] == 0)
                         engine->pmu.enable &= ~BIT(sample);
-                        if (!engine_needs_busy_stats(engine) &&
-                            engine->pmu.busy_stats) {
-                                engine->pmu.busy_stats = false;
-                                /*
-                                 * We request a delayed disable to handle the
-                                 * rapid on/off cycles on events, which can
-                                 * happen when tools like perf stat start, in a
-                                 * nicer way.
-                                 *
-                                 * In addition, this also helps with busy stats
-                                 * accuracy with background CPU offline/online
-                                 * migration events.
-                                 */
-                                queue_delayed_work(system_wq,
-                                                   &engine->pmu.disable_busy_stats,
-                                                   round_jiffies_up_relative(HZ));
-                        }
-                }
         }
 
         GEM_BUG_ON(bit >= I915_PMU_MASK_BITS);
@@ -797,8 +866,6 @@ static void i915_pmu_unregister_cpuhp_state(struct drm_i915_private *i915)
 
 void i915_pmu_register(struct drm_i915_private *i915)
 {
-        struct intel_engine_cs *engine;
-        enum intel_engine_id id;
         int ret;
 
         if (INTEL_GEN(i915) <= 2) {
@@ -820,10 +887,6 @@ void i915_pmu_register(struct drm_i915_private *i915)
         hrtimer_init(&i915->pmu.timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
         i915->pmu.timer.function = i915_sample;
 
-        for_each_engine(engine, i915, id)
-                INIT_DELAYED_WORK(&engine->pmu.disable_busy_stats,
-                                  __disable_busy_stats);
-
         ret = perf_pmu_register(&i915->pmu.base, "i915", -1);
         if (ret)
                 goto err;
@@ -843,9 +906,6 @@ err:
 
 void i915_pmu_unregister(struct drm_i915_private *i915)
 {
-        struct intel_engine_cs *engine;
-        enum intel_engine_id id;
-
         if (!i915->pmu.base.event_init)
                 return;
 
@@ -853,11 +913,6 @@ void i915_pmu_unregister(struct drm_i915_private *i915)
 
         hrtimer_cancel(&i915->pmu.timer);
 
-        for_each_engine(engine, i915, id) {
-                GEM_BUG_ON(engine->pmu.busy_stats);
-                flush_delayed_work(&engine->pmu.disable_busy_stats);
-        }
-
         i915_pmu_unregister_cpuhp_state(i915);
 
         perf_pmu_unregister(&i915->pmu.base);
diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h
index 40c154d13565..bb62df15afa4 100644
--- a/drivers/gpu/drm/i915/i915_pmu.h
+++ b/drivers/gpu/drm/i915/i915_pmu.h
@@ -27,6 +27,8 @@
 enum {
         __I915_SAMPLE_FREQ_ACT = 0,
         __I915_SAMPLE_FREQ_REQ,
+        __I915_SAMPLE_RC6,
+        __I915_SAMPLE_RC6_ESTIMATED,
         __I915_NUM_PMU_SAMPLERS
 };
 
@@ -94,6 +96,10 @@ struct i915_pmu {
          * struct intel_engine_cs.
          */
         struct i915_pmu_sample sample[__I915_NUM_PMU_SAMPLERS];
+        /**
+         * @suspended_jiffies_last: Cached suspend time from PM core.
+         */
+        unsigned long suspended_jiffies_last;
 };
 
 #ifdef CONFIG_PERF_EVENTS
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a2108e35c599..33eb0c5b1d32 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2027,7 +2027,7 @@ enum i915_power_well_id {
 #define _CNL_PORT_TX_DW5_LN0_AE         0x162454
 #define _CNL_PORT_TX_DW5_LN0_B          0x162654
 #define _CNL_PORT_TX_DW5_LN0_C          0x162C54
-#define _CNL_PORT_TX_DW5_LN0_D          0x162ED4
+#define _CNL_PORT_TX_DW5_LN0_D          0x162E54
 #define _CNL_PORT_TX_DW5_LN0_F          0x162854
 #define CNL_PORT_TX_DW5_GRP(port)       _MMIO_PORT6(port, \
                                                     _CNL_PORT_TX_DW5_GRP_AE, \
@@ -2058,7 +2058,7 @@ enum i915_power_well_id {
 #define _CNL_PORT_TX_DW7_LN0_AE         0x16245C
 #define _CNL_PORT_TX_DW7_LN0_B          0x16265C
 #define _CNL_PORT_TX_DW7_LN0_C          0x162C5C
-#define _CNL_PORT_TX_DW7_LN0_D          0x162EDC
+#define _CNL_PORT_TX_DW7_LN0_D          0x162E5C
 #define _CNL_PORT_TX_DW7_LN0_F          0x16285C
 #define CNL_PORT_TX_DW7_GRP(port)       _MMIO_PORT6(port, \
                                                     _CNL_PORT_TX_DW7_GRP_AE, \
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index 522d54fecb53..4a01f62a392d 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -779,11 +779,11 @@ static struct intel_encoder *get_saved_enc(struct drm_i915_private *dev_priv,
 {
         struct intel_encoder *encoder;
 
-        if (WARN_ON(pipe >= ARRAY_SIZE(dev_priv->av_enc_map)))
-                return NULL;
-
         /* MST */
         if (pipe >= 0) {
+                if (WARN_ON(pipe >= ARRAY_SIZE(dev_priv->av_enc_map)))
+                        return NULL;
+
                 encoder = dev_priv->av_enc_map[pipe];
                 /*
                  * when bootup, audio driver may not know it is
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index f7f771749e48..b49a2df44430 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -947,6 +947,86 @@ static int goto_next_sequence_v3(const u8 *data, int index, int total)
         return 0;
 }
 
+/*
+ * Get len of pre-fixed deassert fragment from a v1 init OTP sequence,
+ * skip all delay + gpio operands and stop at the first DSI packet op.
+ */
+static int get_init_otp_deassert_fragment_len(struct drm_i915_private *dev_priv)
+{
+        const u8 *data = dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP];
+        int index, len;
+
+        if (WARN_ON(!data || dev_priv->vbt.dsi.seq_version != 1))
+                return 0;
+
+        /* index = 1 to skip sequence byte */
+        for (index = 1; data[index] != MIPI_SEQ_ELEM_END; index += len) {
+                switch (data[index]) {
+                case MIPI_SEQ_ELEM_SEND_PKT:
+                        return index == 1 ? 0 : index;
+                case MIPI_SEQ_ELEM_DELAY:
+                        len = 5; /* 1 byte for operand + uint32 */
+                        break;
+                case MIPI_SEQ_ELEM_GPIO:
+                        len = 3; /* 1 byte for op, 1 for gpio_nr, 1 for value */
+                        break;
+                default:
+                        return 0;
+                }
+        }
+
+        return 0;
+}
+
+/*
+ * Some v1 VBT MIPI sequences do the deassert in the init OTP sequence.
+ * The deassert must be done before calling intel_dsi_device_ready, so for
+ * these devices we split the init OTP sequence into a deassert sequence and
+ * the actual init OTP part.
+ */
+static void fixup_mipi_sequences(struct drm_i915_private *dev_priv)
+{
+        u8 *init_otp;
+        int len;
+
+        /* Limit this to VLV for now. */
+        if (!IS_VALLEYVIEW(dev_priv))
+                return;
+
+        /* Limit this to v1 vid-mode sequences */
+        if (dev_priv->vbt.dsi.config->is_cmd_mode ||
+            dev_priv->vbt.dsi.seq_version != 1)
+                return;
+
+        /* Only do this if there are otp and assert seqs and no deassert seq */
+        if (!dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] ||
+            !dev_priv->vbt.dsi.sequence[MIPI_SEQ_ASSERT_RESET] ||
+            dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET])
+                return;
+
+        /* The deassert-sequence ends at the first DSI packet */
+        len = get_init_otp_deassert_fragment_len(dev_priv);
+        if (!len)
+                return;
+
+        DRM_DEBUG_KMS("Using init OTP fragment to deassert reset\n");
+
+        /* Copy the fragment, update seq byte and terminate it */
+        init_otp = (u8 *)dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP];
+        dev_priv->vbt.dsi.deassert_seq = kmemdup(init_otp, len + 1, GFP_KERNEL);
+        if (!dev_priv->vbt.dsi.deassert_seq)
+                return;
+        dev_priv->vbt.dsi.deassert_seq[0] = MIPI_SEQ_DEASSERT_RESET;
+        dev_priv->vbt.dsi.deassert_seq[len] = MIPI_SEQ_ELEM_END;
+        /* Use the copy for deassert */
+        dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET] =
+                dev_priv->vbt.dsi.deassert_seq;
+        /* Replace the last byte of the fragment with init OTP seq byte */
+        init_otp[len - 1] = MIPI_SEQ_INIT_OTP;
+        /* And make MIPI_MIPI_SEQ_INIT_OTP point to it */
+        dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] = init_otp + len - 1;
+}
+
 static void
 parse_mipi_sequence(struct drm_i915_private *dev_priv,
                     const struct bdb_header *bdb)
@@ -1016,6 +1096,8 @@ parse_mipi_sequence(struct drm_i915_private *dev_priv,
         dev_priv->vbt.dsi.size = seq_size;
         dev_priv->vbt.dsi.seq_version = sequence->version;
 
+        fixup_mipi_sequences(dev_priv);
+
         DRM_DEBUG_DRIVER("MIPI related VBT parsing complete\n");
         return;
 
@@ -1589,6 +1671,29 @@ out:
 }
 
 /**
+ * intel_bios_cleanup - Free any resources allocated by intel_bios_init()
+ * @dev_priv: i915 device instance
+ */
+void intel_bios_cleanup(struct drm_i915_private *dev_priv)
+{
+        kfree(dev_priv->vbt.child_dev);
+        dev_priv->vbt.child_dev = NULL;
+        dev_priv->vbt.child_dev_num = 0;
+        kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
+        dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
+        kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
+        dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
+        kfree(dev_priv->vbt.dsi.data);
+        dev_priv->vbt.dsi.data = NULL;
+        kfree(dev_priv->vbt.dsi.pps);
+        dev_priv->vbt.dsi.pps = NULL;
+        kfree(dev_priv->vbt.dsi.config);
+        dev_priv->vbt.dsi.config = NULL;
+        kfree(dev_priv->vbt.dsi.deassert_seq);
+        dev_priv->vbt.dsi.deassert_seq = NULL;
+}
+
+/**
  * intel_bios_is_tv_present - is integrated TV present in VBT
  * @dev_priv:   i915 device instance
  *
diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index bd40fea16b4f..f54ddda9fdad 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -594,29 +594,16 @@ void intel_engine_remove_wait(struct intel_engine_cs *engine,
         spin_unlock_irq(&b->rb_lock);
 }
 
-static bool signal_valid(const struct drm_i915_gem_request *request)
-{
-        return intel_wait_check_request(&request->signaling.wait, request);
-}
-
 static bool signal_complete(const struct drm_i915_gem_request *request)
 {
         if (!request)
                 return false;
 
-        /* If another process served as the bottom-half it may have already
-         * signalled that this wait is already completed.
-         */
-        if (intel_wait_complete(&request->signaling.wait))
-                return signal_valid(request);
-
-        /* Carefully check if the request is complete, giving time for the
+        /*
+         * Carefully check if the request is complete, giving time for the
          * seqno to be visible or if the GPU hung.
          */
-        if (__i915_request_irq_complete(request))
-                return true;
-
-        return false;
+        return __i915_request_irq_complete(request);
 }
 
 static struct drm_i915_gem_request *to_signaler(struct rb_node *rb)
@@ -659,9 +646,13 @@ static int intel_breadcrumbs_signaler(void *arg)
                         request = i915_gem_request_get_rcu(request);
                 rcu_read_unlock();
                 if (signal_complete(request)) {
-                        local_bh_disable();
-                        dma_fence_signal(&request->fence);
-                        local_bh_enable(); /* kick start the tasklets */
+                        if (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
+                                      &request->fence.flags)) {
+                                local_bh_disable();
+                                dma_fence_signal(&request->fence);
+                                GEM_BUG_ON(!i915_gem_request_completed(request));
+                                local_bh_enable(); /* kick start the tasklets */
+                        }
 
                         spin_lock_irq(&b->rb_lock);
 
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 5dc118f26b51..1704c8897afd 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1952,6 +1952,14 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
         if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
                 min_cdclk = max(2 * 96000, min_cdclk);
 
+        /*
+         * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
+         * than 320000KHz.
+         */
+        if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
+            IS_VALLEYVIEW(dev_priv))
+                min_cdclk = max(320000, min_cdclk);
+
         if (min_cdclk > dev_priv->max_cdclk_freq) {
                 DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d kHz)\n",
                               min_cdclk, dev_priv->max_cdclk_freq);
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index d790bdc227ff..fa960cfd2764 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1458,7 +1458,9 @@ static bool ring_is_idle(struct intel_engine_cs *engine)
         struct drm_i915_private *dev_priv = engine->i915;
         bool idle = true;
 
-        intel_runtime_pm_get(dev_priv);
+        /* If the whole device is asleep, the engine must be idle */
+        if (!intel_runtime_pm_get_if_in_use(dev_priv))
+                return true;
 
         /* First check that no commands are left in the ring */
         if ((I915_READ_HEAD(engine) & HEAD_ADDR) !=
@@ -1943,16 +1945,22 @@ intel_engine_lookup_user(struct drm_i915_private *i915, u8 class, u8 instance)
  */
 int intel_enable_engine_stats(struct intel_engine_cs *engine)
 {
+        struct intel_engine_execlists *execlists = &engine->execlists;
         unsigned long flags;
+        int err = 0;
 
         if (!intel_engine_supports_stats(engine))
                 return -ENODEV;
 
+        tasklet_disable(&execlists->tasklet);
         spin_lock_irqsave(&engine->stats.lock, flags);
-        if (engine->stats.enabled == ~0)
-                goto busy;
+
+        if (unlikely(engine->stats.enabled == ~0)) {
+                err = -EBUSY;
+                goto unlock;
+        }
+
         if (engine->stats.enabled++ == 0) {
-                struct intel_engine_execlists *execlists = &engine->execlists;
                 const struct execlist_port *port = execlists->port;
                 unsigned int num_ports = execlists_num_ports(execlists);
 
@@ -1967,14 +1975,12 @@ int intel_enable_engine_stats(struct intel_engine_cs *engine)
                 if (engine->stats.active)
                         engine->stats.start = engine->stats.enabled_at;
         }
-        spin_unlock_irqrestore(&engine->stats.lock, flags);
-
-        return 0;
 
-busy:
+unlock:
         spin_unlock_irqrestore(&engine->stats.lock, flags);
+        tasklet_enable(&execlists->tasklet);
 
-        return -EBUSY;
+        return err;
 }
 
 static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index c5ff203e42d6..a0e7a6c2a57c 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -366,20 +366,6 @@ struct intel_engine_cs {
                  */
 #define I915_ENGINE_SAMPLE_MAX (I915_SAMPLE_SEMA + 1)
                 struct i915_pmu_sample sample[I915_ENGINE_SAMPLE_MAX];
-                /**
-                 * @busy_stats: Has enablement of engine stats tracking been
-                 *              requested.
-                 */
-                bool busy_stats;
-                /**
-                 * @disable_busy_stats: Work item for busy stats disabling.
-                 *
-                 * Same as with @enable_busy_stats action, with the difference
-                 * that we delay it in case there are rapid enable-disable
-                 * actions, which can happen during tool startup (like perf
-                 * stat).
-                 */
-                struct delayed_work disable_busy_stats;
         } pmu;
 
         /*
diff --git a/drivers/gpu/drm/meson/meson_crtc.c b/drivers/gpu/drm/meson/meson_crtc.c
index 5155f0179b61..05520202c967 100644
--- a/drivers/gpu/drm/meson/meson_crtc.c
+++ b/drivers/gpu/drm/meson/meson_crtc.c
@@ -36,6 +36,7 @@
 #include "meson_venc.h"
 #include "meson_vpp.h"
 #include "meson_viu.h"
+#include "meson_canvas.h"
 #include "meson_registers.h"
 
 /* CRTC definition */
@@ -192,6 +193,11 @@ void meson_crtc_irq(struct meson_drm *priv)
                 } else
                         meson_vpp_disable_interlace_vscaler_osd1(priv);
 
+                meson_canvas_setup(priv, MESON_CANVAS_ID_OSD1,
+                           priv->viu.osd1_addr, priv->viu.osd1_stride,
+                           priv->viu.osd1_height, MESON_CANVAS_WRAP_NONE,
+                           MESON_CANVAS_BLKMODE_LINEAR);
+
                 /* Enable OSD1 */
                 writel_bits_relaxed(VPP_OSD1_POSTBLEND, VPP_OSD1_POSTBLEND,
                                     priv->io_base + _REG(VPP_MISC));
diff --git a/drivers/gpu/drm/meson/meson_drv.h b/drivers/gpu/drm/meson/meson_drv.h
index 5e8b392b9d1f..8450d6ac8c9b 100644
--- a/drivers/gpu/drm/meson/meson_drv.h
+++ b/drivers/gpu/drm/meson/meson_drv.h
@@ -43,6 +43,9 @@ struct meson_drm {
                 bool osd1_commit;
                 uint32_t osd1_ctrl_stat;
                 uint32_t osd1_blk0_cfg[5];
+                uint32_t osd1_addr;
+                uint32_t osd1_stride;
+                uint32_t osd1_height;
         } viu;
 
         struct {
diff --git a/drivers/gpu/drm/meson/meson_plane.c b/drivers/gpu/drm/meson/meson_plane.c
index d0a6ac8390f3..27bd3503e1e4 100644
--- a/drivers/gpu/drm/meson/meson_plane.c
+++ b/drivers/gpu/drm/meson/meson_plane.c
@@ -164,10 +164,9 @@ static void meson_plane_atomic_update(struct drm_plane *plane,
         /* Update Canvas with buffer address */
         gem = drm_fb_cma_get_gem_obj(fb, 0);
 
-        meson_canvas_setup(priv, MESON_CANVAS_ID_OSD1,
-                           gem->paddr, fb->pitches[0],
-                           fb->height, MESON_CANVAS_WRAP_NONE,
-                           MESON_CANVAS_BLKMODE_LINEAR);
+        priv->viu.osd1_addr = gem->paddr;
+        priv->viu.osd1_stride = fb->pitches[0];
+        priv->viu.osd1_height = fb->height;
 
         spin_unlock_irqrestore(&priv->drm->event_lock, flags);
 }
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
index 3e9bba4d6624..6d8e3a9a6fc0 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
@@ -680,7 +680,7 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev)
         } else {
                 dev_info(&pdev->dev,
                          "no iommu, fallback to phys contig buffers for scanout\n");
-                aspace = NULL;;
+                aspace = NULL;
         }
 
         pm_runtime_put_sync(&pdev->dev);
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c
index 69d6e61a01ec..6ed9cb053dfa 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
@@ -570,9 +570,15 @@ nouveau_connector_detect(struct drm_connector *connector, bool force)
                 nv_connector->edid = NULL;
         }
 
-        ret = pm_runtime_get_sync(connector->dev->dev);
-        if (ret < 0 && ret != -EACCES)
-                return conn_status;
+        /* Outputs are only polled while runtime active, so acquiring a
+         * runtime PM ref here is unnecessary (and would deadlock upon
+         * runtime suspend because it waits for polling to finish).
+         */
+        if (!drm_kms_helper_is_poll_worker()) {
+                ret = pm_runtime_get_sync(connector->dev->dev);
+                if (ret < 0 && ret != -EACCES)
+                        return conn_status;
+        }
 
         nv_encoder = nouveau_connector_ddc_detect(connector);
         if (nv_encoder && (i2c = nv_encoder->i2c) != NULL) {
@@ -647,8 +653,10 @@ detect_analog:
 
  out:
 
-        pm_runtime_mark_last_busy(connector->dev->dev);
-        pm_runtime_put_autosuspend(connector->dev->dev);
+        if (!drm_kms_helper_is_poll_worker()) {
+                pm_runtime_mark_last_busy(connector->dev->dev);
+                pm_runtime_put_autosuspend(connector->dev->dev);
+        }
 
         return conn_status;
 }
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index dd8d4352ed99..caddce88d2d8 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -4477,6 +4477,7 @@ nv50_display_create(struct drm_device *dev)
         nouveau_display(dev)->fini = nv50_display_fini;
         disp->disp = &nouveau_display(dev)->disp;
         dev->mode_config.funcs = &nv50_disp_func;
+        dev->driver->driver_features |= DRIVER_PREFER_XBGR_30BPP;
         if (nouveau_atomic)
                 dev->driver->driver_features |= DRIVER_ATOMIC;
 
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c
index bf62303571b3..3695cde669f8 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c
@@ -301,7 +301,7 @@ nvkm_therm_attr_set(struct nvkm_therm *therm,
 void
 nvkm_therm_clkgate_enable(struct nvkm_therm *therm)
 {
-        if (!therm->func->clkgate_enable || !therm->clkgating_enabled)
+        if (!therm || !therm->func->clkgate_enable || !therm->clkgating_enabled)
                 return;
 
         nvkm_debug(&therm->subdev,
@@ -312,7 +312,7 @@ nvkm_therm_clkgate_enable(struct nvkm_therm *therm)
 void
 nvkm_therm_clkgate_fini(struct nvkm_therm *therm, bool suspend)
 {
-        if (!therm->func->clkgate_fini || !therm->clkgating_enabled)
+        if (!therm || !therm->func->clkgate_fini || !therm->clkgating_enabled)
                 return;
 
         nvkm_debug(&therm->subdev,
@@ -395,7 +395,7 @@ void
 nvkm_therm_clkgate_init(struct nvkm_therm *therm,
                         const struct nvkm_therm_clkgate_pack *p)
 {
-        if (!therm->func->clkgate_init || !therm->clkgating_enabled)
+        if (!therm || !therm->func->clkgate_init || !therm->clkgating_enabled)
                 return;
 
         therm->func->clkgate_init(therm, p);
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index 5012f5e47a1e..2e2ca3c6b47d 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -899,9 +899,11 @@ radeon_lvds_detect(struct drm_connector *connector, bool force)
         enum drm_connector_status ret = connector_status_disconnected;
         int r;
 
-        r = pm_runtime_get_sync(connector->dev->dev);
-        if (r < 0)
-                return connector_status_disconnected;
+        if (!drm_kms_helper_is_poll_worker()) {
+                r = pm_runtime_get_sync(connector->dev->dev);
+                if (r < 0)
+                        return connector_status_disconnected;
+        }
 
         if (encoder) {
                 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
@@ -924,8 +926,12 @@ radeon_lvds_detect(struct drm_connector *connector, bool force)
         /* check acpi lid status ??? */
 
         radeon_connector_update_scratch_regs(connector, ret);
-        pm_runtime_mark_last_busy(connector->dev->dev);
-        pm_runtime_put_autosuspend(connector->dev->dev);
+
+        if (!drm_kms_helper_is_poll_worker()) {
+                pm_runtime_mark_last_busy(connector->dev->dev);
+                pm_runtime_put_autosuspend(connector->dev->dev);
+        }
+
         return ret;
 }
 
@@ -1039,9 +1045,11 @@ radeon_vga_detect(struct drm_connector *connector, bool force)
         enum drm_connector_status ret = connector_status_disconnected;
         int r;
 
-        r = pm_runtime_get_sync(connector->dev->dev);
-        if (r < 0)
-                return connector_status_disconnected;
+        if (!drm_kms_helper_is_poll_worker()) {
+                r = pm_runtime_get_sync(connector->dev->dev);
+                if (r < 0)
+                        return connector_status_disconnected;
+        }
 
         encoder = radeon_best_single_encoder(connector);
         if (!encoder)
@@ -1108,8 +1116,10 @@ radeon_vga_detect(struct drm_connector *connector, bool force)
         radeon_connector_update_scratch_regs(connector, ret);
 
 out:
-        pm_runtime_mark_last_busy(connector->dev->dev);
-        pm_runtime_put_autosuspend(connector->dev->dev);
+        if (!drm_kms_helper_is_poll_worker()) {
+                pm_runtime_mark_last_busy(connector->dev->dev);
+                pm_runtime_put_autosuspend(connector->dev->dev);
+        }
 
         return ret;
 }
@@ -1173,9 +1183,11 @@ radeon_tv_detect(struct drm_connector *connector, bool force)
         if (!radeon_connector->dac_load_detect)
                 return ret;
 
-        r = pm_runtime_get_sync(connector->dev->dev);
-        if (r < 0)
-                return connector_status_disconnected;
+        if (!drm_kms_helper_is_poll_worker()) {
+                r = pm_runtime_get_sync(connector->dev->dev);
+                if (r < 0)
+                        return connector_status_disconnected;
+        }
 
         encoder = radeon_best_single_encoder(connector);
         if (!encoder)
@@ -1187,8 +1199,12 @@ radeon_tv_detect(struct drm_connector *connector, bool force)
         if (ret == connector_status_connected)
                 ret = radeon_connector_analog_encoder_conflict_solve(connector, encoder, ret, false);
         radeon_connector_update_scratch_regs(connector, ret);
-        pm_runtime_mark_last_busy(connector->dev->dev);
-        pm_runtime_put_autosuspend(connector->dev->dev);
+
+        if (!drm_kms_helper_is_poll_worker()) {
+                pm_runtime_mark_last_busy(connector->dev->dev);
+                pm_runtime_put_autosuspend(connector->dev->dev);
+        }
+
         return ret;
 }
 
@@ -1251,9 +1267,11 @@ radeon_dvi_detect(struct drm_connector *connector, bool force)
         enum drm_connector_status ret = connector_status_disconnected;
         bool dret = false, broken_edid = false;
 
-        r = pm_runtime_get_sync(connector->dev->dev);
-        if (r < 0)
-                return connector_status_disconnected;
+        if (!drm_kms_helper_is_poll_worker()) {
+                r = pm_runtime_get_sync(connector->dev->dev);
+                if (r < 0)
+                        return connector_status_disconnected;
+        }
 
         if (radeon_connector->detected_hpd_without_ddc) {
                 force = true;
@@ -1436,8 +1454,10 @@ out:
         }
 
 exit:
-        pm_runtime_mark_last_busy(connector->dev->dev);
-        pm_runtime_put_autosuspend(connector->dev->dev);
+        if (!drm_kms_helper_is_poll_worker()) {
+                pm_runtime_mark_last_busy(connector->dev->dev);
+                pm_runtime_put_autosuspend(connector->dev->dev);
+        }
 
         return ret;
 }
@@ -1688,9 +1708,11 @@ radeon_dp_detect(struct drm_connector *connector, bool force)
         if (radeon_dig_connector->is_mst)
                 return connector_status_disconnected;
 
-        r = pm_runtime_get_sync(connector->dev->dev);
-        if (r < 0)
-                return connector_status_disconnected;
+        if (!drm_kms_helper_is_poll_worker()) {
+                r = pm_runtime_get_sync(connector->dev->dev);
+                if (r < 0)
+                        return connector_status_disconnected;
+        }
 
         if (!force && radeon_check_hpd_status_unchanged(connector)) {
                 ret = connector->status;
@@ -1777,8 +1799,10 @@ radeon_dp_detect(struct drm_connector *connector, bool force)
         }
 
 out:
-        pm_runtime_mark_last_busy(connector->dev->dev);
-        pm_runtime_put_autosuspend(connector->dev->dev);
+        if (!drm_kms_helper_is_poll_worker()) {
+                pm_runtime_mark_last_busy(connector->dev->dev);
+                pm_runtime_put_autosuspend(connector->dev->dev);
+        }
 
         return ret;
 }
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 8d3e3d2e0090..7828a5e10629 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -1365,6 +1365,10 @@ int radeon_device_init(struct radeon_device *rdev,
         if ((rdev->flags & RADEON_IS_PCI) &&
             (rdev->family <= CHIP_RS740))
                 rdev->need_dma32 = true;
+#ifdef CONFIG_PPC64
+        if (rdev->family == CHIP_CEDAR)
+                rdev->need_dma32 = true;
+#endif
 
         dma_bits = rdev->need_dma32 ? 32 : 40;
         r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index 326ad068c15a..4b6542538ff9 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -47,7 +47,6 @@ static bool radeon_pm_in_vbl(struct radeon_device *rdev);
 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
 static void radeon_pm_update_profile(struct radeon_device *rdev);
 static void radeon_pm_set_clocks(struct radeon_device *rdev);
-static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev);
 
 int radeon_pm_get_type_index(struct radeon_device *rdev,
                              enum radeon_pm_state_type ps_type,
@@ -80,8 +79,6 @@ void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
                                 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power);
                 }
                 mutex_unlock(&rdev->pm.mutex);
-                /* allow new DPM state to be picked */
-                radeon_pm_compute_clocks_dpm(rdev);
         } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
                 if (rdev->pm.profile == PM_PROFILE_AUTO) {
                         mutex_lock(&rdev->pm.mutex);
@@ -885,8 +882,7 @@ static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
         /* balanced states don't exist at the moment */
         if (dpm_state == POWER_STATE_TYPE_BALANCED)
-                dpm_state = rdev->pm.dpm.ac_power ?
-                        POWER_STATE_TYPE_PERFORMANCE : POWER_STATE_TYPE_BATTERY;
+                dpm_state = POWER_STATE_TYPE_PERFORMANCE;
 
 restart_search:
         /* Pick the best power state based on current conditions */
diff --git a/drivers/gpu/drm/scheduler/gpu_scheduler.c b/drivers/gpu/drm/scheduler/gpu_scheduler.c
index 2c18996d59c5..0d95888ccc3e 100644
--- a/drivers/gpu/drm/scheduler/gpu_scheduler.c
+++ b/drivers/gpu/drm/scheduler/gpu_scheduler.c
@@ -461,7 +461,7 @@ void drm_sched_hw_job_reset(struct drm_gpu_scheduler *sched, struct drm_sched_jo
 {
         struct drm_sched_job *s_job;
         struct drm_sched_entity *entity, *tmp;
-        int i;;
+        int i;
 
         spin_lock(&sched->job_list_lock);
         list_for_each_entry_reverse(s_job, &sched->ring_mirror_list, node) {
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index 3c15cf24b503..b3960118deb9 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -260,7 +260,7 @@ static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon,
                                         const struct drm_display_mode *mode)
 {
         /* Configure the dot clock */
-        clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
+        clk_set_rate_exclusive(tcon->dclk, mode->crtc_clock * 1000);
 
         /* Set the resolution */
         regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
@@ -335,6 +335,9 @@ static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon,
         regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
                            SUN4I_TCON_GCTL_IOMAP_MASK,
                            SUN4I_TCON_GCTL_IOMAP_TCON0);
+
+        /* Enable the output on the pins */
+        regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0xe0000000);
 }
 
 static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
@@ -418,7 +421,7 @@ static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
         WARN_ON(!tcon->quirks->has_channel_1);
 
         /* Configure the dot clock */
-        clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000);
+        clk_set_rate_exclusive(tcon->sclk1, mode->crtc_clock * 1000);
 
         /* Adjust clock delay */
         clk_delay = sun4i_tcon_get_clk_delay(mode, 1);
diff --git a/drivers/gpu/drm/virtio/virtgpu_ioctl.c b/drivers/gpu/drm/virtio/virtgpu_ioctl.c
index 5720a0d4ac0a..677ac16c8a6d 100644
--- a/drivers/gpu/drm/virtio/virtgpu_ioctl.c
+++ b/drivers/gpu/drm/virtio/virtgpu_ioctl.c
@@ -197,6 +197,9 @@ static int virtio_gpu_getparam_ioctl(struct drm_device *dev, void *data,
         case VIRTGPU_PARAM_3D_FEATURES:
                 value = vgdev->has_virgl_3d == true ? 1 : 0;
                 break;
+        case VIRTGPU_PARAM_CAPSET_QUERY_FIX:
+                value = 1;
+                break;
         default:
                 return -EINVAL;
         }
@@ -472,7 +475,7 @@ static int virtio_gpu_get_caps_ioctl(struct drm_device *dev,
 {
         struct virtio_gpu_device *vgdev = dev->dev_private;
         struct drm_virtgpu_get_caps *args = data;
-        int size;
+        unsigned size, host_caps_size;
         int i;
         int found_valid = -1;
         int ret;
@@ -481,6 +484,10 @@ static int virtio_gpu_get_caps_ioctl(struct drm_device *dev,
         if (vgdev->num_capsets == 0)
                 return -ENOSYS;
 
+        /* don't allow userspace to pass 0 */
+        if (args->size == 0)
+                return -EINVAL;
+
         spin_lock(&vgdev->display_info_lock);
         for (i = 0; i < vgdev->num_capsets; i++) {
                 if (vgdev->capsets[i].id == args->cap_set_id) {
@@ -496,11 +503,9 @@ static int virtio_gpu_get_caps_ioctl(struct drm_device *dev,
                 return -EINVAL;
         }
 
-        size = vgdev->capsets[found_valid].max_size;
-        if (args->size > size) {
-                spin_unlock(&vgdev->display_info_lock);
-                return -EINVAL;
-        }
+        host_caps_size = vgdev->capsets[found_valid].max_size;
+        /* only copy to user the minimum of the host caps size or the guest caps size */
+        size = min(args->size, host_caps_size);
 
         list_for_each_entry(cache_ent, &vgdev->cap_cache, head) {
                 if (cache_ent->id == args->cap_set_id &&
diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c
index 658fa2d3e40c..48685cddbad1 100644
--- a/drivers/gpu/ipu-v3/ipu-common.c
+++ b/drivers/gpu/ipu-v3/ipu-common.c
@@ -1089,7 +1089,7 @@ static void ipu_irq_handler(struct irq_desc *desc)
 {
         struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
         struct irq_chip *chip = irq_desc_get_chip(desc);
-        const int int_reg[] = { 0, 1, 2, 3, 10, 11, 12, 13, 14};
+        static const int int_reg[] = { 0, 1, 2, 3, 10, 11, 12, 13, 14};
 
         chained_irq_enter(chip, desc);
 
@@ -1102,7 +1102,7 @@ static void ipu_err_irq_handler(struct irq_desc *desc)
 {
         struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
         struct irq_chip *chip = irq_desc_get_chip(desc);
-        const int int_reg[] = { 4, 5, 8, 9};
+        static const int int_reg[] = { 4, 5, 8, 9};
 
         chained_irq_enter(chip, desc);
 
diff --git a/drivers/gpu/ipu-v3/ipu-cpmem.c b/drivers/gpu/ipu-v3/ipu-cpmem.c
index bb9c087e6c0d..9f2d9ec42add 100644
--- a/drivers/gpu/ipu-v3/ipu-cpmem.c
+++ b/drivers/gpu/ipu-v3/ipu-cpmem.c
@@ -788,12 +788,14 @@ int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image)
         case V4L2_PIX_FMT_SGBRG8:
         case V4L2_PIX_FMT_SGRBG8:
         case V4L2_PIX_FMT_SRGGB8:
+        case V4L2_PIX_FMT_GREY:
                 offset = image->rect.left + image->rect.top * pix->bytesperline;
                 break;
         case V4L2_PIX_FMT_SBGGR16:
         case V4L2_PIX_FMT_SGBRG16:
         case V4L2_PIX_FMT_SGRBG16:
         case V4L2_PIX_FMT_SRGGB16:
+        case V4L2_PIX_FMT_Y16:
                 offset = image->rect.left * 2 +
                          image->rect.top * pix->bytesperline;
                 break;
diff --git a/drivers/gpu/ipu-v3/ipu-csi.c b/drivers/gpu/ipu-v3/ipu-csi.c
index 24e12b87a0cb..caa05b0702e1 100644
--- a/drivers/gpu/ipu-v3/ipu-csi.c
+++ b/drivers/gpu/ipu-v3/ipu-csi.c
@@ -288,6 +288,7 @@ static int mbus_code_to_bus_cfg(struct ipu_csi_bus_config *cfg, u32 mbus_code)
         case MEDIA_BUS_FMT_SGBRG10_1X10:
         case MEDIA_BUS_FMT_SGRBG10_1X10:
         case MEDIA_BUS_FMT_SRGGB10_1X10:
+        case MEDIA_BUS_FMT_Y10_1X10:
                 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
                 cfg->mipi_dt = MIPI_DT_RAW10;
                 cfg->data_width = IPU_CSI_DATA_WIDTH_10;
@@ -296,6 +297,7 @@ static int mbus_code_to_bus_cfg(struct ipu_csi_bus_config *cfg, u32 mbus_code)
         case MEDIA_BUS_FMT_SGBRG12_1X12:
         case MEDIA_BUS_FMT_SGRBG12_1X12:
         case MEDIA_BUS_FMT_SRGGB12_1X12:
+        case MEDIA_BUS_FMT_Y12_1X12:
                 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
                 cfg->mipi_dt = MIPI_DT_RAW12;
                 cfg->data_width = IPU_CSI_DATA_WIDTH_12;
diff --git a/drivers/gpu/ipu-v3/ipu-pre.c b/drivers/gpu/ipu-v3/ipu-pre.c
index f1cec3d70498..0f70e8847540 100644
--- a/drivers/gpu/ipu-v3/ipu-pre.c
+++ b/drivers/gpu/ipu-v3/ipu-pre.c
@@ -129,11 +129,14 @@ ipu_pre_lookup_by_phandle(struct device *dev, const char *name, int index)
                 if (pre_node == pre->dev->of_node) {
                         mutex_unlock(&ipu_pre_list_mutex);
                         device_link_add(dev, pre->dev, DL_FLAG_AUTOREMOVE);
+                        of_node_put(pre_node);
                         return pre;
                 }
         }
         mutex_unlock(&ipu_pre_list_mutex);
 
+        of_node_put(pre_node);
+
         return NULL;
 }
 
diff --git a/drivers/gpu/ipu-v3/ipu-prg.c b/drivers/gpu/ipu-v3/ipu-prg.c
index 067365c733c6..97b99500153d 100644
--- a/drivers/gpu/ipu-v3/ipu-prg.c
+++ b/drivers/gpu/ipu-v3/ipu-prg.c
@@ -102,11 +102,14 @@ ipu_prg_lookup_by_phandle(struct device *dev, const char *name, int ipu_id)
                         mutex_unlock(&ipu_prg_list_mutex);
                         device_link_add(dev, prg->dev, DL_FLAG_AUTOREMOVE);
                         prg->id = ipu_id;
+                        of_node_put(prg_node);
                         return prg;
                 }
         }
         mutex_unlock(&ipu_prg_list_mutex);
 
+        of_node_put(prg_node);
+
         return NULL;
 }
 
diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h
index 43ddcdfbd0da..9454ac134ce2 100644
--- a/drivers/hid/hid-ids.h
+++ b/drivers/hid/hid-ids.h
@@ -645,6 +645,9 @@
 #define USB_DEVICE_ID_LD_MICROCASSYTIME         0x1033
 #define USB_DEVICE_ID_LD_MICROCASSYTEMPERATURE  0x1035
 #define USB_DEVICE_ID_LD_MICROCASSYPH           0x1038
+#define USB_DEVICE_ID_LD_POWERANALYSERCASSY     0x1040
+#define USB_DEVICE_ID_LD_CONVERTERCONTROLLERCASSY       0x1042
+#define USB_DEVICE_ID_LD_MACHINETESTCASSY       0x1043
 #define USB_DEVICE_ID_LD_JWM            0x1080
 #define USB_DEVICE_ID_LD_DMMP           0x1081
 #define USB_DEVICE_ID_LD_UMIP           0x1090
diff --git a/drivers/hid/hid-quirks.c b/drivers/hid/hid-quirks.c
index 5f6035a5ce36..e92b77fa574a 100644
--- a/drivers/hid/hid-quirks.c
+++ b/drivers/hid/hid-quirks.c
@@ -809,6 +809,9 @@ static const struct hid_device_id hid_ignore_list[] = {
         { HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_MICROCASSYTIME) },
         { HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_MICROCASSYTEMPERATURE) },
         { HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_MICROCASSYPH) },
+        { HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_POWERANALYSERCASSY) },
+        { HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_CONVERTERCONTROLLERCASSY) },
+        { HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_MACHINETESTCASSY) },
         { HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_JWM) },
         { HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_DMMP) },
         { HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_UMIP) },
diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c
index 4bdbf77f7197..72c338eb5fae 100644
--- a/drivers/hwmon/coretemp.c
+++ b/drivers/hwmon/coretemp.c
@@ -269,13 +269,13 @@ static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
         for (i = 0; i < ARRAY_SIZE(tjmax_model_table); i++) {
                 const struct tjmax_model *tm = &tjmax_model_table[i];
                 if (c->x86_model == tm->model &&
-                    (tm->mask == ANY || c->x86_mask == tm->mask))
+                    (tm->mask == ANY || c->x86_stepping == tm->mask))
                         return tm->tjmax;
         }
 
         /* Early chips have no MSR for TjMax */
 
-        if (c->x86_model == 0xf && c->x86_mask < 4)
+        if (c->x86_model == 0xf && c->x86_stepping < 4)
                 usemsr_ee = 0;
 
         if (c->x86_model > 0xe && usemsr_ee) {
@@ -426,7 +426,7 @@ static int chk_ucode_version(unsigned int cpu)
          * Readings might stop update when processor visited too deep sleep,
          * fixed for stepping D0 (6EC).
          */
-        if (c->x86_model == 0xe && c->x86_mask < 0xc && c->microcode < 0x39) {
+        if (c->x86_model == 0xe && c->x86_stepping < 0xc && c->microcode < 0x39) {
                 pr_err("Errata AE18 not fixed, update BIOS or microcode of the CPU!\n");
                 return -ENODEV;
         }
diff --git a/drivers/hwmon/hwmon-vid.c b/drivers/hwmon/hwmon-vid.c
index ef91b8a67549..84e91286fc4f 100644
--- a/drivers/hwmon/hwmon-vid.c
+++ b/drivers/hwmon/hwmon-vid.c
@@ -293,7 +293,7 @@ u8 vid_which_vrm(void)
         if (c->x86 < 6)         /* Any CPU with family lower than 6 */
                 return 0;       /* doesn't have VID */
 
-        vrm_ret = find_vrm(c->x86, c->x86_model, c->x86_mask, c->x86_vendor);
+        vrm_ret = find_vrm(c->x86, c->x86_model, c->x86_stepping, c->x86_vendor);
         if (vrm_ret == 134)
                 vrm_ret = get_via_model_d_vrm();
         if (vrm_ret == 0)
diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c
index 06b4e1c78bd8..051a72eecb24 100644
--- a/drivers/hwmon/k10temp.c
+++ b/drivers/hwmon/k10temp.c
@@ -129,7 +129,10 @@ static ssize_t temp1_input_show(struct device *dev,
 
         data->read_tempreg(data->pdev, &regval);
         temp = (regval >> 21) * 125;
-        temp -= data->temp_offset;
+        if (temp > data->temp_offset)
+                temp -= data->temp_offset;
+        else
+                temp = 0;
 
         return sprintf(buf, "%u\n", temp);
 }
@@ -227,7 +230,7 @@ static bool has_erratum_319(struct pci_dev *pdev)
          * and AM3 formats, but that's the best we can do.
          */
         return boot_cpu_data.x86_model < 4 ||
-               (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_mask <= 2);
+               (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2);
 }
 
 static int k10temp_probe(struct pci_dev *pdev,
diff --git a/drivers/hwmon/k8temp.c b/drivers/hwmon/k8temp.c
index 5a632bcf869b..e59f9113fb93 100644
--- a/drivers/hwmon/k8temp.c
+++ b/drivers/hwmon/k8temp.c
@@ -187,7 +187,7 @@ static int k8temp_probe(struct pci_dev *pdev,
                 return -ENOMEM;
 
         model = boot_cpu_data.x86_model;
-        stepping = boot_cpu_data.x86_mask;
+        stepping = boot_cpu_data.x86_stepping;
 
         /* feature available since SH-C0, exclude older revisions */
         if ((model == 4 && stepping == 0) ||
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index a9805c7cb305..e2954fb86d65 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -123,8 +123,10 @@ config I2C_I801
             Wildcat Point (PCH)
             Wildcat Point-LP (PCH)
             BayTrail (SOC)
+            Braswell (SOC)
             Sunrise Point-H (PCH)
             Sunrise Point-LP (PCH)
+            Kaby Lake-H (PCH)
             DNV (SOC)
             Broxton (SOC)
             Lewisburg (PCH)
diff --git a/drivers/i2c/busses/i2c-bcm2835.c b/drivers/i2c/busses/i2c-bcm2835.c
index cd07a69e2e93..44deae78913e 100644
--- a/drivers/i2c/busses/i2c-bcm2835.c
+++ b/drivers/i2c/busses/i2c-bcm2835.c
@@ -50,6 +50,9 @@
 #define BCM2835_I2C_S_CLKT      BIT(9)
 #define BCM2835_I2C_S_LEN       BIT(10) /* Fake bit for SW error reporting */
 
+#define BCM2835_I2C_FEDL_SHIFT  16
+#define BCM2835_I2C_REDL_SHIFT  0
+
 #define BCM2835_I2C_CDIV_MIN    0x0002
 #define BCM2835_I2C_CDIV_MAX    0xFFFE
 
@@ -81,7 +84,7 @@ static inline u32 bcm2835_i2c_readl(struct bcm2835_i2c_dev *i2c_dev, u32 reg)
 
 static int bcm2835_i2c_set_divider(struct bcm2835_i2c_dev *i2c_dev)
 {
-        u32 divider;
+        u32 divider, redl, fedl;
 
         divider = DIV_ROUND_UP(clk_get_rate(i2c_dev->clk),
                                i2c_dev->bus_clk_rate);
@@ -100,6 +103,22 @@ static int bcm2835_i2c_set_divider(struct bcm2835_i2c_dev *i2c_dev)
 
         bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DIV, divider);
 
+        /*
+         * Number of core clocks to wait after falling edge before
+         * outputting the next data bit.  Note that both FEDL and REDL
+         * can't be greater than CDIV/2.
+         */
+        fedl = max(divider / 16, 1u);
+
+        /*
+         * Number of core clocks to wait after rising edge before
+         * sampling the next incoming data bit.
+         */
+        redl = max(divider / 4, 1u);
+
+        bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DEL,
+                           (fedl << BCM2835_I2C_FEDL_SHIFT) |
+                           (redl << BCM2835_I2C_REDL_SHIFT));
         return 0;
 }
 
diff --git a/drivers/i2c/busses/i2c-designware-master.c b/drivers/i2c/busses/i2c-designware-master.c
index ae691884d071..05732531829f 100644
--- a/drivers/i2c/busses/i2c-designware-master.c
+++ b/drivers/i2c/busses/i2c-designware-master.c
@@ -209,7 +209,7 @@ static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
         i2c_dw_disable_int(dev);
 
         /* Enable the adapter */
-        __i2c_dw_enable(dev, true);
+        __i2c_dw_enable_and_wait(dev, true);
 
         /* Clear and enable interrupts */
         dw_readl(dev, DW_IC_CLR_INTR);
@@ -644,7 +644,7 @@ static int i2c_dw_init_recovery_info(struct dw_i2c_dev *dev)
         gpio = devm_gpiod_get(dev->dev, "scl", GPIOD_OUT_HIGH);
         if (IS_ERR(gpio)) {
                 r = PTR_ERR(gpio);
-                if (r == -ENOENT)
+                if (r == -ENOENT || r == -ENOSYS)
                         return 0;
                 return r;
         }
diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c
index 8eac00efadc1..692b34125866 100644
--- a/drivers/i2c/busses/i2c-i801.c
+++ b/drivers/i2c/busses/i2c-i801.c
@@ -58,6 +58,7 @@
  * Wildcat Point (PCH)          0x8ca2  32      hard    yes     yes     yes
  * Wildcat Point-LP (PCH)       0x9ca2  32      hard    yes     yes     yes
  * BayTrail (SOC)               0x0f12  32      hard    yes     yes     yes
+ * Braswell (SOC)               0x2292  32      hard    yes     yes     yes
  * Sunrise Point-H (PCH)        0xa123  32      hard    yes     yes     yes
  * Sunrise Point-LP (PCH)       0x9d23  32      hard    yes     yes     yes
  * DNV (SOC)                    0x19df  32      hard    yes     yes     yes
diff --git a/drivers/i2c/busses/i2c-octeon-core.c b/drivers/i2c/busses/i2c-octeon-core.c
index 1d8775799056..d9607905dc2f 100644
--- a/drivers/i2c/busses/i2c-octeon-core.c
+++ b/drivers/i2c/busses/i2c-octeon-core.c
@@ -233,6 +233,7 @@ static int octeon_i2c_check_status(struct octeon_i2c *i2c, int final_read)
                 return -EOPNOTSUPP;
 
         case STAT_TXDATA_NAK:
+        case STAT_BUS_ERROR:
                 return -EIO;
         case STAT_TXADDR_NAK:
         case STAT_RXADDR_NAK:
diff --git a/drivers/i2c/busses/i2c-octeon-core.h b/drivers/i2c/busses/i2c-octeon-core.h
index a7ef19855bb8..9bb9f64fdda0 100644
--- a/drivers/i2c/busses/i2c-octeon-core.h
+++ b/drivers/i2c/busses/i2c-octeon-core.h
@@ -43,7 +43,7 @@
 #define TWSI_CTL_AAK            0x04    /* Assert ACK */
 
 /* Status values */
-#define STAT_ERROR              0x00
+#define STAT_BUS_ERROR          0x00
 #define STAT_START              0x08
 #define STAT_REP_START          0x10
 #define STAT_TXADDR_ACK         0x18
diff --git a/drivers/i2c/busses/i2c-sirf.c b/drivers/i2c/busses/i2c-sirf.c
index 2fd8b6d00391..87197ece0f90 100644
--- a/drivers/i2c/busses/i2c-sirf.c
+++ b/drivers/i2c/busses/i2c-sirf.c
@@ -341,7 +341,7 @@ static int i2c_sirfsoc_probe(struct platform_device *pdev)
         platform_set_drvdata(pdev, adap);
         init_completion(&siic->done);
 
-        /* Controller Initalisation */
+        /* Controller initialisation */
 
         writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL);
         while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
@@ -369,7 +369,7 @@ static int i2c_sirfsoc_probe(struct platform_device *pdev)
          * but they start to affect the speed when clock is set to faster
          * frequencies.
          * Through the actual tests, use the different user_div value(which
-         * in the divider formular 'Fio / (Fi2c * user_div)') to adapt
+         * in the divider formula 'Fio / (Fi2c * user_div)') to adapt
          * the different ranges of i2c bus clock frequency, to make the SCL
          * more accurate.
          */
diff --git a/drivers/ide/ide-probe.c b/drivers/ide/ide-probe.c
index 17fd55af4d92..caa20eb5f26b 100644
--- a/drivers/ide/ide-probe.c
+++ b/drivers/ide/ide-probe.c
@@ -928,7 +928,7 @@ static int exact_lock(dev_t dev, void *data)
 {
         struct gendisk *p = data;
 
-        if (!get_disk(p))
+        if (!get_disk_and_module(p))
                 return -1;
         return 0;
 }
diff --git a/drivers/iio/adc/aspeed_adc.c b/drivers/iio/adc/aspeed_adc.c
index 327a49ba1991..9515ca165dfd 100644
--- a/drivers/iio/adc/aspeed_adc.c
+++ b/drivers/iio/adc/aspeed_adc.c
@@ -243,7 +243,7 @@ static int aspeed_adc_probe(struct platform_device *pdev)
                                          ASPEED_ADC_INIT_POLLING_TIME,
                                          ASPEED_ADC_INIT_TIMEOUT);
                 if (ret)
-                        goto scaler_error;
+                        goto poll_timeout_error;
         }
 
         /* Start all channels in normal mode. */
@@ -274,9 +274,10 @@ iio_register_error:
         writel(ASPEED_OPERATION_MODE_POWER_DOWN,
                 data->base + ASPEED_REG_ENGINE_CONTROL);
         clk_disable_unprepare(data->clk_scaler->clk);
-reset_error:
-        reset_control_assert(data->rst);
 clk_enable_error:
+poll_timeout_error:
+        reset_control_assert(data->rst);
+reset_error:
         clk_hw_unregister_divider(data->clk_scaler);
 scaler_error:
         clk_hw_unregister_divider(data->clk_prescaler);
diff --git a/drivers/iio/adc/stm32-adc.c b/drivers/iio/adc/stm32-adc.c
index 7f5def465340..9a2583caedaa 100644
--- a/drivers/iio/adc/stm32-adc.c
+++ b/drivers/iio/adc/stm32-adc.c
@@ -722,8 +722,6 @@ static int stm32h7_adc_enable(struct stm32_adc *adc)
         int ret;
         u32 val;
 
-        /* Clear ADRDY by writing one, then enable ADC */
-        stm32_adc_set_bits(adc, STM32H7_ADC_ISR, STM32H7_ADRDY);
         stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADEN);
 
         /* Poll for ADRDY to be set (after adc startup time) */
@@ -731,8 +729,11 @@ static int stm32h7_adc_enable(struct stm32_adc *adc)
                                            val & STM32H7_ADRDY,
                                            100, STM32_ADC_TIMEOUT_US);
         if (ret) {
-                stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADEN);
+                stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS);
                 dev_err(&indio_dev->dev, "Failed to enable ADC\n");
+        } else {
+                /* Clear ADRDY by writing one */
+                stm32_adc_set_bits(adc, STM32H7_ADC_ISR, STM32H7_ADRDY);
         }
 
         return ret;
diff --git a/drivers/iio/imu/adis_trigger.c b/drivers/iio/imu/adis_trigger.c
index 0dd5a381be64..457372f36791 100644
--- a/drivers/iio/imu/adis_trigger.c
+++ b/drivers/iio/imu/adis_trigger.c
@@ -46,6 +46,10 @@ int adis_probe_trigger(struct adis *adis, struct iio_dev *indio_dev)
         if (adis->trig == NULL)
                 return -ENOMEM;
 
+        adis->trig->dev.parent = &adis->spi->dev;
+        adis->trig->ops = &adis_trigger_ops;
+        iio_trigger_set_drvdata(adis->trig, adis);
+
         ret = request_irq(adis->spi->irq,
                           &iio_trigger_generic_data_rdy_poll,
                           IRQF_TRIGGER_RISING,
@@ -54,9 +58,6 @@ int adis_probe_trigger(struct adis *adis, struct iio_dev *indio_dev)
         if (ret)
                 goto error_free_trig;
 
-        adis->trig->dev.parent = &adis->spi->dev;
-        adis->trig->ops = &adis_trigger_ops;
-        iio_trigger_set_drvdata(adis->trig, adis);
         ret = iio_trigger_register(adis->trig);
 
         indio_dev->trig = iio_trigger_get(adis->trig);
diff --git a/drivers/iio/industrialio-buffer.c b/drivers/iio/industrialio-buffer.c
index 79abf70a126d..cd5bfe39591b 100644
--- a/drivers/iio/industrialio-buffer.c
+++ b/drivers/iio/industrialio-buffer.c
@@ -175,7 +175,7 @@ __poll_t iio_buffer_poll(struct file *filp,
         struct iio_dev *indio_dev = filp->private_data;
         struct iio_buffer *rb = indio_dev->buffer;
 
-        if (!indio_dev->info)
+        if (!indio_dev->info || rb == NULL)
                 return 0;
 
         poll_wait(filp, &rb->pollq, wait);
diff --git a/drivers/iio/proximity/Kconfig b/drivers/iio/proximity/Kconfig
index fcb1c4ba5e41..f726f9427602 100644
--- a/drivers/iio/proximity/Kconfig
+++ b/drivers/iio/proximity/Kconfig
@@ -68,6 +68,8 @@ config SX9500
 
 config SRF08
         tristate "Devantech SRF02/SRF08/SRF10 ultrasonic ranger sensor"
+        select IIO_BUFFER
+        select IIO_TRIGGERED_BUFFER
         depends on I2C
         help
           Say Y here to build a driver for Devantech SRF02/SRF08/SRF10
diff --git a/drivers/infiniband/core/core_priv.h b/drivers/infiniband/core/core_priv.h
index c4560d84dfae..25bb178f6074 100644
--- a/drivers/infiniband/core/core_priv.h
+++ b/drivers/infiniband/core/core_priv.h
@@ -305,16 +305,21 @@ void nldev_exit(void);
 static inline struct ib_qp *_ib_create_qp(struct ib_device *dev,
                                           struct ib_pd *pd,
                                           struct ib_qp_init_attr *attr,
-                                          struct ib_udata *udata)
+                                          struct ib_udata *udata,
+                                          struct ib_uobject *uobj)
 {
         struct ib_qp *qp;
 
+        if (!dev->create_qp)
+                return ERR_PTR(-EOPNOTSUPP);
+
         qp = dev->create_qp(pd, attr, udata);
         if (IS_ERR(qp))
                 return qp;
 
         qp->device = dev;
         qp->pd = pd;
+        qp->uobject = uobj;
         /*
          * We don't track XRC QPs for now, because they don't have PD
          * and more importantly they are created internaly by driver,
diff --git a/drivers/infiniband/core/rdma_core.c b/drivers/infiniband/core/rdma_core.c
index 85b5ee4defa4..d8eead5d106d 100644
--- a/drivers/infiniband/core/rdma_core.c
+++ b/drivers/infiniband/core/rdma_core.c
@@ -141,7 +141,12 @@ static struct ib_uobject *alloc_uobj(struct ib_ucontext *context,
          */
         uobj->context = context;
         uobj->type = type;
-        atomic_set(&uobj->usecnt, 0);
+        /*
+         * Allocated objects start out as write locked to deny any other
+         * syscalls from accessing them until they are committed. See
+         * rdma_alloc_commit_uobject
+         */
+        atomic_set(&uobj->usecnt, -1);
         kref_init(&uobj->ref);
 
         return uobj;
@@ -196,7 +201,15 @@ static struct ib_uobject *lookup_get_idr_uobject(const struct uverbs_obj_type *t
                 goto free;
         }
 
-        uverbs_uobject_get(uobj);
+        /*
+         * The idr_find is guaranteed to return a pointer to something that
+         * isn't freed yet, or NULL, as the free after idr_remove goes through
+         * kfree_rcu(). However the object may still have been released and
+         * kfree() could be called at any time.
+         */
+        if (!kref_get_unless_zero(&uobj->ref))
+                uobj = ERR_PTR(-ENOENT);
+
 free:
         rcu_read_unlock();
         return uobj;
@@ -399,13 +412,13 @@ static int __must_check remove_commit_fd_uobject(struct ib_uobject *uobj,
         return ret;
 }
 
-static void lockdep_check(struct ib_uobject *uobj, bool exclusive)
+static void assert_uverbs_usecnt(struct ib_uobject *uobj, bool exclusive)
 {
 #ifdef CONFIG_LOCKDEP
         if (exclusive)
-                WARN_ON(atomic_read(&uobj->usecnt) > 0);
+                WARN_ON(atomic_read(&uobj->usecnt) != -1);
         else
-                WARN_ON(atomic_read(&uobj->usecnt) == -1);
+                WARN_ON(atomic_read(&uobj->usecnt) <= 0);
 #endif
 }
 
@@ -444,7 +457,7 @@ int __must_check rdma_remove_commit_uobject(struct ib_uobject *uobj)
                 WARN(true, "ib_uverbs: Cleanup is running while removing an uobject\n");
                 return 0;
         }
-        lockdep_check(uobj, true);
+        assert_uverbs_usecnt(uobj, true);
         ret = _rdma_remove_commit_uobject(uobj, RDMA_REMOVE_DESTROY);
 
         up_read(&ucontext->cleanup_rwsem);
@@ -474,16 +487,17 @@ int rdma_explicit_destroy(struct ib_uobject *uobject)
                 WARN(true, "ib_uverbs: Cleanup is running while removing an uobject\n");
                 return 0;
         }
-        lockdep_check(uobject, true);
+        assert_uverbs_usecnt(uobject, true);
         ret = uobject->type->type_class->remove_commit(uobject,
                                                        RDMA_REMOVE_DESTROY);
         if (ret)
-                return ret;
+                goto out;
 
         uobject->type = &null_obj_type;
 
+out:
         up_read(&ucontext->cleanup_rwsem);
-        return 0;
+        return ret;
 }
 
 static void alloc_commit_idr_uobject(struct ib_uobject *uobj)
@@ -527,6 +541,10 @@ int rdma_alloc_commit_uobject(struct ib_uobject *uobj)
                 return ret;
         }
 
+        /* matches atomic_set(-1) in alloc_uobj */
+        assert_uverbs_usecnt(uobj, true);
+        atomic_set(&uobj->usecnt, 0);
+
         uobj->type->type_class->alloc_commit(uobj);
         up_read(&uobj->context->cleanup_rwsem);
 
@@ -561,7 +579,7 @@ static void lookup_put_fd_uobject(struct ib_uobject *uobj, bool exclusive)
 
 void rdma_lookup_put_uobject(struct ib_uobject *uobj, bool exclusive)
 {
-        lockdep_check(uobj, exclusive);
+        assert_uverbs_usecnt(uobj, exclusive);
         uobj->type->type_class->lookup_put(uobj, exclusive);
         /*
          * In order to unlock an object, either decrease its usecnt for
diff --git a/drivers/infiniband/core/restrack.c b/drivers/infiniband/core/restrack.c
index 857637bf46da..3dbc4e4cca41 100644
--- a/drivers/infiniband/core/restrack.c
+++ b/drivers/infiniband/core/restrack.c
@@ -7,7 +7,6 @@
 #include <rdma/restrack.h>
 #include <linux/mutex.h>
 #include <linux/sched/task.h>
-#include <linux/uaccess.h>
 #include <linux/pid_namespace.h>
 
 void rdma_restrack_init(struct rdma_restrack_root *res)
@@ -63,7 +62,6 @@ static struct ib_device *res_to_dev(struct rdma_restrack_entry *res)
 {
         enum rdma_restrack_type type = res->type;
         struct ib_device *dev;
-        struct ib_xrcd *xrcd;
         struct ib_pd *pd;
         struct ib_cq *cq;
         struct ib_qp *qp;
@@ -81,10 +79,6 @@ static struct ib_device *res_to_dev(struct rdma_restrack_entry *res)
                 qp = container_of(res, struct ib_qp, res);
                 dev = qp->device;
                 break;
-        case RDMA_RESTRACK_XRCD:
-                xrcd = container_of(res, struct ib_xrcd, res);
-                dev = xrcd->device;
-                break;
         default:
                 WARN_ONCE(true, "Wrong resource tracking type %u\n", type);
                 return NULL;
@@ -93,6 +87,21 @@ static struct ib_device *res_to_dev(struct rdma_restrack_entry *res)
         return dev;
 }
 
+static bool res_is_user(struct rdma_restrack_entry *res)
+{
+        switch (res->type) {
+        case RDMA_RESTRACK_PD:
+                return container_of(res, struct ib_pd, res)->uobject;
+        case RDMA_RESTRACK_CQ:
+                return container_of(res, struct ib_cq, res)->uobject;
+        case RDMA_RESTRACK_QP:
+                return container_of(res, struct ib_qp, res)->uobject;
+        default:
+                WARN_ONCE(true, "Wrong resource tracking type %u\n", res->type);
+                return false;
+        }
+}
+
 void rdma_restrack_add(struct rdma_restrack_entry *res)
 {
         struct ib_device *dev = res_to_dev(res);
@@ -100,7 +109,7 @@ void rdma_restrack_add(struct rdma_restrack_entry *res)
         if (!dev)
                 return;
 
-        if (!uaccess_kernel()) {
+        if (res_is_user(res)) {
                 get_task_struct(current);
                 res->task = current;
                 res->kern_name = NULL;
diff --git a/drivers/infiniband/core/uverbs_cmd.c b/drivers/infiniband/core/uverbs_cmd.c
index 256934d1f64f..a148de35df8d 100644
--- a/drivers/infiniband/core/uverbs_cmd.c
+++ b/drivers/infiniband/core/uverbs_cmd.c
@@ -562,9 +562,10 @@ ssize_t ib_uverbs_open_xrcd(struct ib_uverbs_file *file,
         if (f.file)
                 fdput(f);
 
+        mutex_unlock(&file->device->xrcd_tree_mutex);
+
         uobj_alloc_commit(&obj->uobject);
 
-        mutex_unlock(&file->device->xrcd_tree_mutex);
         return in_len;
 
 err_copy:
@@ -603,10 +604,8 @@ ssize_t ib_uverbs_close_xrcd(struct ib_uverbs_file *file,
 
         uobj  = uobj_get_write(uobj_get_type(xrcd), cmd.xrcd_handle,
                                file->ucontext);
-        if (IS_ERR(uobj)) {
-                mutex_unlock(&file->device->xrcd_tree_mutex);
+        if (IS_ERR(uobj))
                 return PTR_ERR(uobj);
-        }
 
         ret = uobj_remove_commit(uobj);
         return ret ?: in_len;
@@ -979,6 +978,9 @@ static struct ib_ucq_object *create_cq(struct ib_uverbs_file *file,
         struct ib_uverbs_ex_create_cq_resp resp;
         struct ib_cq_init_attr attr = {};
 
+        if (!ib_dev->create_cq)
+                return ERR_PTR(-EOPNOTSUPP);
+
         if (cmd->comp_vector >= file->device->num_comp_vectors)
                 return ERR_PTR(-EINVAL);
 
@@ -1030,14 +1032,14 @@ static struct ib_ucq_object *create_cq(struct ib_uverbs_file *file,
         resp.response_length = offsetof(typeof(resp), response_length) +
                 sizeof(resp.response_length);
 
+        cq->res.type = RDMA_RESTRACK_CQ;
+        rdma_restrack_add(&cq->res);
+
         ret = cb(file, obj, &resp, ucore, context);
         if (ret)
                 goto err_cb;
 
         uobj_alloc_commit(&obj->uobject);
-        cq->res.type = RDMA_RESTRACK_CQ;
-        rdma_restrack_add(&cq->res);
-
         return obj;
 
 err_cb:
@@ -1518,7 +1520,8 @@ static int create_qp(struct ib_uverbs_file *file,
         if (cmd->qp_type == IB_QPT_XRC_TGT)
                 qp = ib_create_qp(pd, &attr);
         else
-                qp = _ib_create_qp(device, pd, &attr, uhw);
+                qp = _ib_create_qp(device, pd, &attr, uhw,
+                                   &obj->uevent.uobject);
 
         if (IS_ERR(qp)) {
                 ret = PTR_ERR(qp);
@@ -1550,8 +1553,10 @@ static int create_qp(struct ib_uverbs_file *file,
                         atomic_inc(&attr.srq->usecnt);
                 if (ind_tbl)
                         atomic_inc(&ind_tbl->usecnt);
+        } else {
+                /* It is done in _ib_create_qp for other QP types */
+                qp->uobject = &obj->uevent.uobject;
         }
-        qp->uobject = &obj->uevent.uobject;
 
         obj->uevent.uobject.object = qp;
 
@@ -1971,8 +1976,15 @@ static int modify_qp(struct ib_uverbs_file *file,
                 goto release_qp;
         }
 
+        if ((cmd->base.attr_mask & IB_QP_AV) &&
+            !rdma_is_port_valid(qp->device, cmd->base.dest.port_num)) {
+                ret = -EINVAL;
+                goto release_qp;
+        }
+
         if ((cmd->base.attr_mask & IB_QP_ALT_PATH) &&
-            !rdma_is_port_valid(qp->device, cmd->base.alt_port_num)) {
+            (!rdma_is_port_valid(qp->device, cmd->base.alt_port_num) ||
+            !rdma_is_port_valid(qp->device, cmd->base.alt_dest.port_num))) {
                 ret = -EINVAL;
                 goto release_qp;
         }
@@ -2941,6 +2953,11 @@ int ib_uverbs_ex_create_wq(struct ib_uverbs_file *file,
                 wq_init_attr.create_flags = cmd.create_flags;
         obj->uevent.events_reported = 0;
         INIT_LIST_HEAD(&obj->uevent.event_list);
+
+        if (!pd->device->create_wq) {
+                err = -EOPNOTSUPP;
+                goto err_put_cq;
+        }
         wq = pd->device->create_wq(pd, &wq_init_attr, uhw);
         if (IS_ERR(wq)) {
                 err = PTR_ERR(wq);
@@ -3084,7 +3101,12 @@ int ib_uverbs_ex_modify_wq(struct ib_uverbs_file *file,
                 wq_attr.flags = cmd.flags;
                 wq_attr.flags_mask = cmd.flags_mask;
         }
+        if (!wq->device->modify_wq) {
+                ret = -EOPNOTSUPP;
+                goto out;
+        }
         ret = wq->device->modify_wq(wq, &wq_attr, cmd.attr_mask, uhw);
+out:
         uobj_put_obj_read(wq);
         return ret;
 }
@@ -3181,6 +3203,11 @@ int ib_uverbs_ex_create_rwq_ind_table(struct ib_uverbs_file *file,
 
         init_attr.log_ind_tbl_size = cmd.log_ind_tbl_size;
         init_attr.ind_tbl = wqs;
+
+        if (!ib_dev->create_rwq_ind_table) {
+                err = -EOPNOTSUPP;
+                goto err_uobj;
+        }
         rwq_ind_tbl = ib_dev->create_rwq_ind_table(ib_dev, &init_attr, uhw);
 
         if (IS_ERR(rwq_ind_tbl)) {
@@ -3770,6 +3797,9 @@ int ib_uverbs_ex_query_device(struct ib_uverbs_file *file,
         struct ib_device_attr attr = {0};
         int err;
 
+        if (!ib_dev->query_device)
+                return -EOPNOTSUPP;
+
         if (ucore->inlen < sizeof(cmd))
                 return -EINVAL;
 
diff --git a/drivers/infiniband/core/uverbs_ioctl.c b/drivers/infiniband/core/uverbs_ioctl.c
index d96dc1d17be1..339b85145044 100644
--- a/drivers/infiniband/core/uverbs_ioctl.c
+++ b/drivers/infiniband/core/uverbs_ioctl.c
@@ -59,6 +59,9 @@ static int uverbs_process_attr(struct ib_device *ibdev,
                         return 0;
         }
 
+        if (test_bit(attr_id, attr_bundle_h->valid_bitmap))
+                return -EINVAL;
+
         spec = &attr_spec_bucket->attrs[attr_id];
         e = &elements[attr_id];
         e->uattr = uattr_ptr;
diff --git a/drivers/infiniband/core/uverbs_ioctl_merge.c b/drivers/infiniband/core/uverbs_ioctl_merge.c
index 062485f9300d..62e1eb1d2a28 100644
--- a/drivers/infiniband/core/uverbs_ioctl_merge.c
+++ b/drivers/infiniband/core/uverbs_ioctl_merge.c
@@ -114,6 +114,7 @@ static size_t get_elements_above_id(const void **iters,
         short min = SHRT_MAX;
         const void *elem;
         int i, j, last_stored = -1;
+        unsigned int equal_min = 0;
 
         for_each_element(elem, i, j, elements, num_elements, num_offset,
                          data_offset) {
@@ -136,6 +137,10 @@ static size_t get_elements_above_id(const void **iters,
                  */
                 iters[last_stored == i ? num_iters - 1 : num_iters++] = elem;
                 last_stored = i;
+                if (min == GET_ID(id))
+                        equal_min++;
+                else
+                        equal_min = 1;
                 min = GET_ID(id);
         }
 
@@ -146,15 +151,10 @@ static size_t get_elements_above_id(const void **iters,
          * Therefore, we need to clean the beginning of the array to make sure
          * all ids of final elements are equal to min.
          */
-        for (i = num_iters - 1; i >= 0 &&
-             GET_ID(*(u16 *)(iters[i] + id_offset)) == min; i--)
-                ;
-
-        num_iters -= i + 1;
-        memmove(iters, iters + i + 1, sizeof(*iters) * num_iters);
+        memmove(iters, iters + num_iters - equal_min, sizeof(*iters) * equal_min);
 
         *min_id = min;
-        return num_iters;
+        return equal_min;
 }
 
 #define find_max_element_entry_id(num_elements, elements, num_objects_fld, \
@@ -322,7 +322,7 @@ static struct uverbs_method_spec *build_method_with_attrs(const struct uverbs_me
                 hash = kzalloc(sizeof(*hash) +
                                ALIGN(sizeof(*hash->attrs) * (attr_max_bucket + 1),
                                      sizeof(long)) +
-                               BITS_TO_LONGS(attr_max_bucket) * sizeof(long),
+                               BITS_TO_LONGS(attr_max_bucket + 1) * sizeof(long),
                                GFP_KERNEL);
                 if (!hash) {
                         res = -ENOMEM;
@@ -509,7 +509,7 @@ static struct uverbs_object_spec *build_object_with_methods(const struct uverbs_
                          * first handler which != NULL. This also defines the
                          * set of flags used for this handler.
                          */
-                        for (i = num_object_defs - 1;
+                        for (i = num_method_defs - 1;
                              i >= 0 && !method_defs[i]->handler; i--)
                                 ;
                         hash->methods[min_id++] = method;
diff --git a/drivers/infiniband/core/uverbs_main.c b/drivers/infiniband/core/uverbs_main.c
index 395a3b091229..b1ca223aa380 100644
--- a/drivers/infiniband/core/uverbs_main.c
+++ b/drivers/infiniband/core/uverbs_main.c
@@ -650,12 +650,21 @@ static int verify_command_mask(struct ib_device *ib_dev, __u32 command)
         return -1;
 }
 
+static bool verify_command_idx(u32 command, bool extended)
+{
+        if (extended)
+                return command < ARRAY_SIZE(uverbs_ex_cmd_table);
+
+        return command < ARRAY_SIZE(uverbs_cmd_table);
+}
+
 static ssize_t ib_uverbs_write(struct file *filp, const char __user *buf,
                              size_t count, loff_t *pos)
 {
         struct ib_uverbs_file *file = filp->private_data;
         struct ib_device *ib_dev;
         struct ib_uverbs_cmd_hdr hdr;
+        bool extended_command;
         __u32 command;
         __u32 flags;
         int srcu_key;
@@ -688,6 +697,15 @@ static ssize_t ib_uverbs_write(struct file *filp, const char __user *buf,
         }
 
         command = hdr.command & IB_USER_VERBS_CMD_COMMAND_MASK;
+        flags = (hdr.command &
+                 IB_USER_VERBS_CMD_FLAGS_MASK) >> IB_USER_VERBS_CMD_FLAGS_SHIFT;
+
+        extended_command = flags & IB_USER_VERBS_CMD_FLAG_EXTENDED;
+        if (!verify_command_idx(command, extended_command)) {
+                ret = -EINVAL;
+                goto out;
+        }
+
         if (verify_command_mask(ib_dev, command)) {
                 ret = -EOPNOTSUPP;
                 goto out;
@@ -699,12 +717,8 @@ static ssize_t ib_uverbs_write(struct file *filp, const char __user *buf,
                 goto out;
         }
 
-        flags = (hdr.command &
-                 IB_USER_VERBS_CMD_FLAGS_MASK) >> IB_USER_VERBS_CMD_FLAGS_SHIFT;
-
         if (!flags) {
-                if (command >= ARRAY_SIZE(uverbs_cmd_table) ||
-                    !uverbs_cmd_table[command]) {
+                if (!uverbs_cmd_table[command]) {
                         ret = -EINVAL;
                         goto out;
                 }
@@ -725,8 +739,7 @@ static ssize_t ib_uverbs_write(struct file *filp, const char __user *buf,
                 struct ib_udata uhw;
                 size_t written_count = count;
 
-                if (command >= ARRAY_SIZE(uverbs_ex_cmd_table) ||
-                    !uverbs_ex_cmd_table[command]) {
+                if (!uverbs_ex_cmd_table[command]) {
                         ret = -ENOSYS;
                         goto out;
                 }
@@ -942,6 +955,7 @@ static const struct file_operations uverbs_fops = {
         .llseek  = no_llseek,
 #if IS_ENABLED(CONFIG_INFINIBAND_EXP_USER_ACCESS)
         .unlocked_ioctl = ib_uverbs_ioctl,
+        .compat_ioctl = ib_uverbs_ioctl,
 #endif
 };
 
@@ -954,6 +968,7 @@ static const struct file_operations uverbs_mmap_fops = {
         .llseek  = no_llseek,
 #if IS_ENABLED(CONFIG_INFINIBAND_EXP_USER_ACCESS)
         .unlocked_ioctl = ib_uverbs_ioctl,
+        .compat_ioctl = ib_uverbs_ioctl,
 #endif
 };
 
diff --git a/drivers/infiniband/core/uverbs_std_types.c b/drivers/infiniband/core/uverbs_std_types.c
index cab0ac3556eb..df1360e6774f 100644
--- a/drivers/infiniband/core/uverbs_std_types.c
+++ b/drivers/infiniband/core/uverbs_std_types.c
@@ -234,15 +234,18 @@ static void create_udata(struct uverbs_attr_bundle *ctx,
                 uverbs_attr_get(ctx, UVERBS_UHW_OUT);
 
         if (!IS_ERR(uhw_in)) {
-                udata->inbuf = uhw_in->ptr_attr.ptr;
                 udata->inlen = uhw_in->ptr_attr.len;
+                if (uverbs_attr_ptr_is_inline(uhw_in))
+                        udata->inbuf = &uhw_in->uattr->data;
+                else
+                        udata->inbuf = u64_to_user_ptr(uhw_in->ptr_attr.data);
         } else {
                 udata->inbuf = NULL;
                 udata->inlen = 0;
         }
 
         if (!IS_ERR(uhw_out)) {
-                udata->outbuf = uhw_out->ptr_attr.ptr;
+                udata->outbuf = u64_to_user_ptr(uhw_out->ptr_attr.data);
                 udata->outlen = uhw_out->ptr_attr.len;
         } else {
                 udata->outbuf = NULL;
@@ -323,7 +326,8 @@ static int uverbs_create_cq_handler(struct ib_device *ib_dev,
         cq->res.type = RDMA_RESTRACK_CQ;
         rdma_restrack_add(&cq->res);
 
-        ret = uverbs_copy_to(attrs, CREATE_CQ_RESP_CQE, &cq->cqe);
+        ret = uverbs_copy_to(attrs, CREATE_CQ_RESP_CQE, &cq->cqe,
+                             sizeof(cq->cqe));
         if (ret)
                 goto err_cq;
 
@@ -375,7 +379,7 @@ static int uverbs_destroy_cq_handler(struct ib_device *ib_dev,
         resp.comp_events_reported  = obj->comp_events_reported;
         resp.async_events_reported = obj->async_events_reported;
 
-        return uverbs_copy_to(attrs, DESTROY_CQ_RESP, &resp);
+        return uverbs_copy_to(attrs, DESTROY_CQ_RESP, &resp, sizeof(resp));
 }
 
 static DECLARE_UVERBS_METHOD(
diff --git a/drivers/infiniband/core/verbs.c b/drivers/infiniband/core/verbs.c
index 16ebc6372c31..93025d2009b8 100644
--- a/drivers/infiniband/core/verbs.c
+++ b/drivers/infiniband/core/verbs.c
@@ -887,7 +887,7 @@ struct ib_qp *ib_create_qp(struct ib_pd *pd,
         if (qp_init_attr->cap.max_rdma_ctxs)
                 rdma_rw_init_qp(device, qp_init_attr);
 
-        qp = _ib_create_qp(device, pd, qp_init_attr, NULL);
+        qp = _ib_create_qp(device, pd, qp_init_attr, NULL, NULL);
         if (IS_ERR(qp))
                 return qp;
 
@@ -898,7 +898,6 @@ struct ib_qp *ib_create_qp(struct ib_pd *pd,
         }
 
         qp->real_qp    = qp;
-        qp->uobject    = NULL;
         qp->qp_type    = qp_init_attr->qp_type;
         qp->rwq_ind_tbl = qp_init_attr->rwq_ind_tbl;
 
diff --git a/drivers/infiniband/hw/bnxt_re/bnxt_re.h b/drivers/infiniband/hw/bnxt_re/bnxt_re.h
index ca32057e886f..3eb7a8387116 100644
--- a/drivers/infiniband/hw/bnxt_re/bnxt_re.h
+++ b/drivers/infiniband/hw/bnxt_re/bnxt_re.h
@@ -120,7 +120,6 @@ struct bnxt_re_dev {
 #define BNXT_RE_FLAG_HAVE_L2_REF                3
 #define BNXT_RE_FLAG_RCFW_CHANNEL_EN            4
 #define BNXT_RE_FLAG_QOS_WORK_REG               5
-#define BNXT_RE_FLAG_TASK_IN_PROG               6
 #define BNXT_RE_FLAG_ISSUE_ROCE_STATS          29
         struct net_device               *netdev;
         unsigned int                    version, major, minor;
@@ -158,6 +157,7 @@ struct bnxt_re_dev {
         atomic_t                        srq_count;
         atomic_t                        mr_count;
         atomic_t                        mw_count;
+        atomic_t                        sched_count;
         /* Max of 2 lossless traffic class supported per port */
         u16                             cosq[2];
 
diff --git a/drivers/infiniband/hw/bnxt_re/ib_verbs.c b/drivers/infiniband/hw/bnxt_re/ib_verbs.c
index ae9e9ff54826..643174d949a8 100644
--- a/drivers/infiniband/hw/bnxt_re/ib_verbs.c
+++ b/drivers/infiniband/hw/bnxt_re/ib_verbs.c
@@ -174,10 +174,8 @@ int bnxt_re_query_device(struct ib_device *ibdev,
         ib_attr->max_pd = dev_attr->max_pd;
         ib_attr->max_qp_rd_atom = dev_attr->max_qp_rd_atom;
         ib_attr->max_qp_init_rd_atom = dev_attr->max_qp_init_rd_atom;
-        if (dev_attr->is_atomic) {
-                ib_attr->atomic_cap = IB_ATOMIC_HCA;
-                ib_attr->masked_atomic_cap = IB_ATOMIC_HCA;
-        }
+        ib_attr->atomic_cap = IB_ATOMIC_NONE;
+        ib_attr->masked_atomic_cap = IB_ATOMIC_NONE;
 
         ib_attr->max_ee_rd_atom = 0;
         ib_attr->max_res_rd_atom = 0;
@@ -787,20 +785,51 @@ int bnxt_re_query_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr)
         return 0;
 }
 
+static unsigned long bnxt_re_lock_cqs(struct bnxt_re_qp *qp)
+        __acquires(&qp->scq->cq_lock) __acquires(&qp->rcq->cq_lock)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&qp->scq->cq_lock, flags);
+        if (qp->rcq != qp->scq)
+                spin_lock(&qp->rcq->cq_lock);
+        else
+                __acquire(&qp->rcq->cq_lock);
+
+        return flags;
+}
+
+static void bnxt_re_unlock_cqs(struct bnxt_re_qp *qp,
+                               unsigned long flags)
+        __releases(&qp->scq->cq_lock) __releases(&qp->rcq->cq_lock)
+{
+        if (qp->rcq != qp->scq)
+                spin_unlock(&qp->rcq->cq_lock);
+        else
+                __release(&qp->rcq->cq_lock);
+        spin_unlock_irqrestore(&qp->scq->cq_lock, flags);
+}
+
 /* Queue Pairs */
 int bnxt_re_destroy_qp(struct ib_qp *ib_qp)
 {
         struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
         struct bnxt_re_dev *rdev = qp->rdev;
         int rc;
+        unsigned int flags;
 
         bnxt_qplib_flush_cqn_wq(&qp->qplib_qp);
-        bnxt_qplib_del_flush_qp(&qp->qplib_qp);
         rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp);
         if (rc) {
                 dev_err(rdev_to_dev(rdev), "Failed to destroy HW QP");
                 return rc;
         }
+
+        flags = bnxt_re_lock_cqs(qp);
+        bnxt_qplib_clean_qp(&qp->qplib_qp);
+        bnxt_re_unlock_cqs(qp, flags);
+        bnxt_qplib_free_qp_res(&rdev->qplib_res, &qp->qplib_qp);
+
         if (ib_qp->qp_type == IB_QPT_GSI && rdev->qp1_sqp) {
                 rc = bnxt_qplib_destroy_ah(&rdev->qplib_res,
                                            &rdev->sqp_ah->qplib_ah);
@@ -810,7 +839,7 @@ int bnxt_re_destroy_qp(struct ib_qp *ib_qp)
                         return rc;
                 }
 
-                bnxt_qplib_del_flush_qp(&qp->qplib_qp);
+                bnxt_qplib_clean_qp(&qp->qplib_qp);
                 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res,
                                            &rdev->qp1_sqp->qplib_qp);
                 if (rc) {
@@ -1069,6 +1098,7 @@ struct ib_qp *bnxt_re_create_qp(struct ib_pd *ib_pd,
                         goto fail;
                 }
                 qp->qplib_qp.scq = &cq->qplib_cq;
+                qp->scq = cq;
         }
 
         if (qp_init_attr->recv_cq) {
@@ -1080,6 +1110,7 @@ struct ib_qp *bnxt_re_create_qp(struct ib_pd *ib_pd,
                         goto fail;
                 }
                 qp->qplib_qp.rcq = &cq->qplib_cq;
+                qp->rcq = cq;
         }
 
         if (qp_init_attr->srq) {
@@ -1185,7 +1216,7 @@ struct ib_qp *bnxt_re_create_qp(struct ib_pd *ib_pd,
                 rc = bnxt_qplib_create_qp(&rdev->qplib_res, &qp->qplib_qp);
                 if (rc) {
                         dev_err(rdev_to_dev(rdev), "Failed to create HW QP");
-                        goto fail;
+                        goto free_umem;
                 }
         }
 
@@ -1213,6 +1244,13 @@ struct ib_qp *bnxt_re_create_qp(struct ib_pd *ib_pd,
         return &qp->ib_qp;
 qp_destroy:
         bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp);
+free_umem:
+        if (udata) {
+                if (qp->rumem)
+                        ib_umem_release(qp->rumem);
+                if (qp->sumem)
+                        ib_umem_release(qp->sumem);
+        }
 fail:
         kfree(qp);
         return ERR_PTR(rc);
@@ -1603,7 +1641,7 @@ int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,
                         dev_dbg(rdev_to_dev(rdev),
                                 "Move QP = %p out of flush list\n",
                                 qp);
-                        bnxt_qplib_del_flush_qp(&qp->qplib_qp);
+                        bnxt_qplib_clean_qp(&qp->qplib_qp);
                 }
         }
         if (qp_attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) {
diff --git a/drivers/infiniband/hw/bnxt_re/ib_verbs.h b/drivers/infiniband/hw/bnxt_re/ib_verbs.h
index 423ebe012f95..b88a48d43a9d 100644
--- a/drivers/infiniband/hw/bnxt_re/ib_verbs.h
+++ b/drivers/infiniband/hw/bnxt_re/ib_verbs.h
@@ -89,6 +89,8 @@ struct bnxt_re_qp {
         /* QP1 */
         u32                     send_psn;
         struct ib_ud_header     qp1_hdr;
+        struct bnxt_re_cq       *scq;
+        struct bnxt_re_cq       *rcq;
 };
 
 struct bnxt_re_cq {
diff --git a/drivers/infiniband/hw/bnxt_re/main.c b/drivers/infiniband/hw/bnxt_re/main.c
index 508d00a5a106..33a448036c2e 100644
--- a/drivers/infiniband/hw/bnxt_re/main.c
+++ b/drivers/infiniband/hw/bnxt_re/main.c
@@ -656,7 +656,6 @@ static void bnxt_re_dev_remove(struct bnxt_re_dev *rdev)
         mutex_unlock(&bnxt_re_dev_lock);
 
         synchronize_rcu();
-        flush_workqueue(bnxt_re_wq);
 
         ib_dealloc_device(&rdev->ibdev);
         /* rdev is gone */
@@ -1441,7 +1440,7 @@ static void bnxt_re_task(struct work_struct *work)
                 break;
         }
         smp_mb__before_atomic();
-        clear_bit(BNXT_RE_FLAG_TASK_IN_PROG, &rdev->flags);
+        atomic_dec(&rdev->sched_count);
         kfree(re_work);
 }
 
@@ -1503,7 +1502,7 @@ static int bnxt_re_netdev_event(struct notifier_block *notifier,
                 /* netdev notifier will call NETDEV_UNREGISTER again later since
                  * we are still holding the reference to the netdev
                  */
-                if (test_bit(BNXT_RE_FLAG_TASK_IN_PROG, &rdev->flags))
+                if (atomic_read(&rdev->sched_count) > 0)
                         goto exit;
                 bnxt_re_ib_unreg(rdev, false);
                 bnxt_re_remove_one(rdev);
@@ -1523,7 +1522,7 @@ static int bnxt_re_netdev_event(struct notifier_block *notifier,
                         re_work->vlan_dev = (real_dev == netdev ?
                                              NULL : netdev);
                         INIT_WORK(&re_work->work, bnxt_re_task);
-                        set_bit(BNXT_RE_FLAG_TASK_IN_PROG, &rdev->flags);
+                        atomic_inc(&rdev->sched_count);
                         queue_work(bnxt_re_wq, &re_work->work);
                 }
         }
@@ -1578,6 +1577,11 @@ static void __exit bnxt_re_mod_exit(void)
         */
         list_for_each_entry_safe_reverse(rdev, next, &to_be_deleted, list) {
                 dev_info(rdev_to_dev(rdev), "Unregistering Device");
+                /*
+                 * Flush out any scheduled tasks before destroying the
+                 * resources
+                 */
+                flush_workqueue(bnxt_re_wq);
                 bnxt_re_dev_stop(rdev);
                 bnxt_re_ib_unreg(rdev, true);
                 bnxt_re_remove_one(rdev);
diff --git a/drivers/infiniband/hw/bnxt_re/qplib_fp.c b/drivers/infiniband/hw/bnxt_re/qplib_fp.c
index 1b0e94697fe3..3ea5b9624f6b 100644
--- a/drivers/infiniband/hw/bnxt_re/qplib_fp.c
+++ b/drivers/infiniband/hw/bnxt_re/qplib_fp.c
@@ -173,7 +173,7 @@ static void __bnxt_qplib_del_flush_qp(struct bnxt_qplib_qp *qp)
         }
 }
 
-void bnxt_qplib_del_flush_qp(struct bnxt_qplib_qp *qp)
+void bnxt_qplib_clean_qp(struct bnxt_qplib_qp *qp)
 {
         unsigned long flags;
 
@@ -1419,7 +1419,6 @@ int bnxt_qplib_destroy_qp(struct bnxt_qplib_res *res,
         struct bnxt_qplib_rcfw *rcfw = res->rcfw;
         struct cmdq_destroy_qp req;
         struct creq_destroy_qp_resp resp;
-        unsigned long flags;
         u16 cmd_flags = 0;
         int rc;
 
@@ -1437,19 +1436,12 @@ int bnxt_qplib_destroy_qp(struct bnxt_qplib_res *res,
                 return rc;
         }
 
-        /* Must walk the associated CQs to nullified the QP ptr */
-        spin_lock_irqsave(&qp->scq->hwq.lock, flags);
-
-        __clean_cq(qp->scq, (u64)(unsigned long)qp);
-
-        if (qp->rcq && qp->rcq != qp->scq) {
-                spin_lock(&qp->rcq->hwq.lock);
-                __clean_cq(qp->rcq, (u64)(unsigned long)qp);
-                spin_unlock(&qp->rcq->hwq.lock);
-        }
-
-        spin_unlock_irqrestore(&qp->scq->hwq.lock, flags);
+        return 0;
+}
 
+void bnxt_qplib_free_qp_res(struct bnxt_qplib_res *res,
+                            struct bnxt_qplib_qp *qp)
+{
         bnxt_qplib_free_qp_hdr_buf(res, qp);
         bnxt_qplib_free_hwq(res->pdev, &qp->sq.hwq);
         kfree(qp->sq.swq);
@@ -1462,7 +1454,6 @@ int bnxt_qplib_destroy_qp(struct bnxt_qplib_res *res,
         if (qp->orrq.max_elements)
                 bnxt_qplib_free_hwq(res->pdev, &qp->orrq);
 
-        return 0;
 }
 
 void *bnxt_qplib_get_qp1_sq_buf(struct bnxt_qplib_qp *qp,
diff --git a/drivers/infiniband/hw/bnxt_re/qplib_fp.h b/drivers/infiniband/hw/bnxt_re/qplib_fp.h
index 211b27a8f9e2..ca0a2ffa3509 100644
--- a/drivers/infiniband/hw/bnxt_re/qplib_fp.h
+++ b/drivers/infiniband/hw/bnxt_re/qplib_fp.h
@@ -478,6 +478,9 @@ int bnxt_qplib_create_qp(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp);
 int bnxt_qplib_modify_qp(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp);
 int bnxt_qplib_query_qp(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp);
 int bnxt_qplib_destroy_qp(struct bnxt_qplib_res *res, struct bnxt_qplib_qp *qp);
+void bnxt_qplib_clean_qp(struct bnxt_qplib_qp *qp);
+void bnxt_qplib_free_qp_res(struct bnxt_qplib_res *res,
+                            struct bnxt_qplib_qp *qp);
 void *bnxt_qplib_get_qp1_sq_buf(struct bnxt_qplib_qp *qp,
                                 struct bnxt_qplib_sge *sge);
 void *bnxt_qplib_get_qp1_rq_buf(struct bnxt_qplib_qp *qp,
@@ -500,7 +503,6 @@ void bnxt_qplib_req_notify_cq(struct bnxt_qplib_cq *cq, u32 arm_type);
 void bnxt_qplib_free_nq(struct bnxt_qplib_nq *nq);
 int bnxt_qplib_alloc_nq(struct pci_dev *pdev, struct bnxt_qplib_nq *nq);
 void bnxt_qplib_add_flush_qp(struct bnxt_qplib_qp *qp);
-void bnxt_qplib_del_flush_qp(struct bnxt_qplib_qp *qp);
 void bnxt_qplib_acquire_cq_locks(struct bnxt_qplib_qp *qp,
                                  unsigned long *flags);
 void bnxt_qplib_release_cq_locks(struct bnxt_qplib_qp *qp,
diff --git a/drivers/infiniband/hw/bnxt_re/qplib_sp.c b/drivers/infiniband/hw/bnxt_re/qplib_sp.c
index c015c1861351..03057983341f 100644
--- a/drivers/infiniband/hw/bnxt_re/qplib_sp.c
+++ b/drivers/infiniband/hw/bnxt_re/qplib_sp.c
@@ -52,18 +52,6 @@ const struct bnxt_qplib_gid bnxt_qplib_gid_zero = {{ 0, 0, 0, 0, 0, 0, 0, 0,
 
 /* Device */
 
-static bool bnxt_qplib_is_atomic_cap(struct bnxt_qplib_rcfw *rcfw)
-{
-        int rc;
-        u16 pcie_ctl2;
-
-        rc = pcie_capability_read_word(rcfw->pdev, PCI_EXP_DEVCTL2,
-                                       &pcie_ctl2);
-        if (rc)
-                return false;
-        return !!(pcie_ctl2 & PCI_EXP_DEVCTL2_ATOMIC_REQ);
-}
-
 static void bnxt_qplib_query_version(struct bnxt_qplib_rcfw *rcfw,
                                      char *fw_ver)
 {
@@ -165,7 +153,7 @@ int bnxt_qplib_get_dev_attr(struct bnxt_qplib_rcfw *rcfw,
                 attr->tqm_alloc_reqs[i * 4 + 3] = *(++tqm_alloc);
         }
 
-        attr->is_atomic = bnxt_qplib_is_atomic_cap(rcfw);
+        attr->is_atomic = 0;
 bail:
         bnxt_qplib_rcfw_free_sbuf(rcfw, sbuf);
         return rc;
diff --git a/drivers/infiniband/hw/vmw_pvrdma/pvrdma_cq.c b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_cq.c
index faa9478c14a6..f95b97646c25 100644
--- a/drivers/infiniband/hw/vmw_pvrdma/pvrdma_cq.c
+++ b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_cq.c
@@ -114,6 +114,7 @@ struct ib_cq *pvrdma_create_cq(struct ib_device *ibdev,
         union pvrdma_cmd_resp rsp;
         struct pvrdma_cmd_create_cq *cmd = &req.create_cq;
         struct pvrdma_cmd_create_cq_resp *resp = &rsp.create_cq_resp;
+        struct pvrdma_create_cq_resp cq_resp = {0};
         struct pvrdma_create_cq ucmd;
 
         BUILD_BUG_ON(sizeof(struct pvrdma_cqe) != 64);
@@ -197,6 +198,7 @@ struct ib_cq *pvrdma_create_cq(struct ib_device *ibdev,
 
         cq->ibcq.cqe = resp->cqe;
         cq->cq_handle = resp->cq_handle;
+        cq_resp.cqn = resp->cq_handle;
         spin_lock_irqsave(&dev->cq_tbl_lock, flags);
         dev->cq_tbl[cq->cq_handle % dev->dsr->caps.max_cq] = cq;
         spin_unlock_irqrestore(&dev->cq_tbl_lock, flags);
@@ -205,7 +207,7 @@ struct ib_cq *pvrdma_create_cq(struct ib_device *ibdev,
                 cq->uar = &(to_vucontext(context)->uar);
 
                 /* Copy udata back. */
-                if (ib_copy_to_udata(udata, &cq->cq_handle, sizeof(__u32))) {
+                if (ib_copy_to_udata(udata, &cq_resp, sizeof(cq_resp))) {
                         dev_warn(&dev->pdev->dev,
                                  "failed to copy back udata\n");
                         pvrdma_destroy_cq(&cq->ibcq);
diff --git a/drivers/infiniband/hw/vmw_pvrdma/pvrdma_srq.c b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_srq.c
index 5acebb1ef631..af235967a9c2 100644
--- a/drivers/infiniband/hw/vmw_pvrdma/pvrdma_srq.c
+++ b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_srq.c
@@ -113,6 +113,7 @@ struct ib_srq *pvrdma_create_srq(struct ib_pd *pd,
         union pvrdma_cmd_resp rsp;
         struct pvrdma_cmd_create_srq *cmd = &req.create_srq;
         struct pvrdma_cmd_create_srq_resp *resp = &rsp.create_srq_resp;
+        struct pvrdma_create_srq_resp srq_resp = {0};
         struct pvrdma_create_srq ucmd;
         unsigned long flags;
         int ret;
@@ -204,12 +205,13 @@ struct ib_srq *pvrdma_create_srq(struct ib_pd *pd,
         }
 
         srq->srq_handle = resp->srqn;
+        srq_resp.srqn = resp->srqn;
         spin_lock_irqsave(&dev->srq_tbl_lock, flags);
         dev->srq_tbl[srq->srq_handle % dev->dsr->caps.max_srq] = srq;
         spin_unlock_irqrestore(&dev->srq_tbl_lock, flags);
 
         /* Copy udata back. */
-        if (ib_copy_to_udata(udata, &srq->srq_handle, sizeof(__u32))) {
+        if (ib_copy_to_udata(udata, &srq_resp, sizeof(srq_resp))) {
                 dev_warn(&dev->pdev->dev, "failed to copy back udata\n");
                 pvrdma_destroy_srq(&srq->ibsrq);
                 return ERR_PTR(-EINVAL);
diff --git a/drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.c b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.c
index 16b96616ef7e..a51463cd2f37 100644
--- a/drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.c
+++ b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.c
@@ -447,6 +447,7 @@ struct ib_pd *pvrdma_alloc_pd(struct ib_device *ibdev,
         union pvrdma_cmd_resp rsp;
         struct pvrdma_cmd_create_pd *cmd = &req.create_pd;
         struct pvrdma_cmd_create_pd_resp *resp = &rsp.create_pd_resp;
+        struct pvrdma_alloc_pd_resp pd_resp = {0};
         int ret;
         void *ptr;
 
@@ -475,9 +476,10 @@ struct ib_pd *pvrdma_alloc_pd(struct ib_device *ibdev,
         pd->privileged = !context;
         pd->pd_handle = resp->pd_handle;
         pd->pdn = resp->pd_handle;
+        pd_resp.pdn = resp->pd_handle;
 
         if (context) {
-                if (ib_copy_to_udata(udata, &pd->pdn, sizeof(__u32))) {
+                if (ib_copy_to_udata(udata, &pd_resp, sizeof(pd_resp))) {
                         dev_warn(&dev->pdev->dev,
                                  "failed to copy back protection domain\n");
                         pvrdma_dealloc_pd(&pd->ibpd);
diff --git a/drivers/infiniband/ulp/ipoib/ipoib_fs.c b/drivers/infiniband/ulp/ipoib/ipoib_fs.c
index 11f74cbe6660..ea302b054601 100644
--- a/drivers/infiniband/ulp/ipoib/ipoib_fs.c
+++ b/drivers/infiniband/ulp/ipoib/ipoib_fs.c
@@ -281,8 +281,6 @@ void ipoib_delete_debug_files(struct net_device *dev)
 {
         struct ipoib_dev_priv *priv = ipoib_priv(dev);
 
-        WARN_ONCE(!priv->mcg_dentry, "null mcg debug file\n");
-        WARN_ONCE(!priv->path_dentry, "null path debug file\n");
         debugfs_remove(priv->mcg_dentry);
         debugfs_remove(priv->path_dentry);
         priv->mcg_dentry = priv->path_dentry = NULL;
diff --git a/drivers/iommu/intel-svm.c b/drivers/iommu/intel-svm.c
index 35a408d0ae4f..99bc9bd64b9e 100644
--- a/drivers/iommu/intel-svm.c
+++ b/drivers/iommu/intel-svm.c
@@ -205,7 +205,7 @@ static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_d
                          * for example, an "address" value of 0x12345f000 will
                          * flush from 0x123440000 to 0x12347ffff (256KiB). */
                         unsigned long last = address + ((unsigned long)(pages - 1) << VTD_PAGE_SHIFT);
-                        unsigned long mask = __rounddown_pow_of_two(address ^ last);;
+                        unsigned long mask = __rounddown_pow_of_two(address ^ last);
 
                         desc.high = QI_DEV_EIOTLB_ADDR((address & ~mask) | (mask - 1)) | QI_DEV_EIOTLB_SIZE;
                 } else {
diff --git a/drivers/irqchip/irq-bcm7038-l1.c b/drivers/irqchip/irq-bcm7038-l1.c
index 55cfb986225b..faf734ff4cf3 100644
--- a/drivers/irqchip/irq-bcm7038-l1.c
+++ b/drivers/irqchip/irq-bcm7038-l1.c
@@ -339,9 +339,6 @@ int __init bcm7038_l1_of_init(struct device_node *dn,
                 goto out_unmap;
         }
 
-        pr_info("registered BCM7038 L1 intc (mem: 0x%p, IRQs: %d)\n",
-                intc->cpus[0]->map_base, IRQS_PER_WORD * intc->n_words);
-
         return 0;
 
 out_unmap:
diff --git a/drivers/irqchip/irq-bcm7120-l2.c b/drivers/irqchip/irq-bcm7120-l2.c
index 983640eba418..8968e5e93fcb 100644
--- a/drivers/irqchip/irq-bcm7120-l2.c
+++ b/drivers/irqchip/irq-bcm7120-l2.c
@@ -318,9 +318,6 @@ static int __init bcm7120_l2_intc_probe(struct device_node *dn,
                 }
         }
 
-        pr_info("registered %s intc (mem: 0x%p, parent IRQ(s): %d)\n",
-                        intc_name, data->map_base[0], data->num_parent_irqs);
-
         return 0;
 
 out_free_domain:
diff --git a/drivers/irqchip/irq-brcmstb-l2.c b/drivers/irqchip/irq-brcmstb-l2.c
index 691d20eb0bec..0e65f609352e 100644
--- a/drivers/irqchip/irq-brcmstb-l2.c
+++ b/drivers/irqchip/irq-brcmstb-l2.c
@@ -262,9 +262,6 @@ static int __init brcmstb_l2_intc_of_init(struct device_node *np,
                 ct->chip.irq_set_wake = irq_gc_set_wake;
         }
 
-        pr_info("registered L2 intc (mem: 0x%p, parent irq: %d)\n",
-                        base, parent_irq);
-
         return 0;
 
 out_free_domain:
diff --git a/drivers/irqchip/irq-gic-v2m.c b/drivers/irqchip/irq-gic-v2m.c
index 993a8426a453..1ff38aff9f29 100644
--- a/drivers/irqchip/irq-gic-v2m.c
+++ b/drivers/irqchip/irq-gic-v2m.c
@@ -94,7 +94,7 @@ static struct irq_chip gicv2m_msi_irq_chip = {
 
 static struct msi_domain_info gicv2m_msi_domain_info = {
         .flags  = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
-                   MSI_FLAG_PCI_MSIX),
+                   MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI),
         .chip   = &gicv2m_msi_irq_chip,
 };
 
@@ -155,18 +155,12 @@ static int gicv2m_irq_gic_domain_alloc(struct irq_domain *domain,
         return 0;
 }
 
-static void gicv2m_unalloc_msi(struct v2m_data *v2m, unsigned int hwirq)
+static void gicv2m_unalloc_msi(struct v2m_data *v2m, unsigned int hwirq,
+                               int nr_irqs)
 {
-        int pos;
-
-        pos = hwirq - v2m->spi_start;
-        if (pos < 0 || pos >= v2m->nr_spis) {
-                pr_err("Failed to teardown msi. Invalid hwirq %d\n", hwirq);
-                return;
-        }
-
         spin_lock(&v2m_lock);
-        __clear_bit(pos, v2m->bm);
+        bitmap_release_region(v2m->bm, hwirq - v2m->spi_start,
+                              get_count_order(nr_irqs));
         spin_unlock(&v2m_lock);
 }
 
@@ -174,13 +168,13 @@ static int gicv2m_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
                                    unsigned int nr_irqs, void *args)
 {
         struct v2m_data *v2m = NULL, *tmp;
-        int hwirq, offset, err = 0;
+        int hwirq, offset, i, err = 0;
 
         spin_lock(&v2m_lock);
         list_for_each_entry(tmp, &v2m_nodes, entry) {
-                offset = find_first_zero_bit(tmp->bm, tmp->nr_spis);
-                if (offset < tmp->nr_spis) {
-                        __set_bit(offset, tmp->bm);
+                offset = bitmap_find_free_region(tmp->bm, tmp->nr_spis,
+                                                 get_count_order(nr_irqs));
+                if (offset >= 0) {
                         v2m = tmp;
                         break;
                 }
@@ -192,16 +186,21 @@ static int gicv2m_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
 
         hwirq = v2m->spi_start + offset;
 
-        err = gicv2m_irq_gic_domain_alloc(domain, virq, hwirq);
-        if (err) {
-                gicv2m_unalloc_msi(v2m, hwirq);
-                return err;
-        }
+        for (i = 0; i < nr_irqs; i++) {
+                err = gicv2m_irq_gic_domain_alloc(domain, virq + i, hwirq + i);
+                if (err)
+                        goto fail;
 
-        irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
-                                      &gicv2m_irq_chip, v2m);
+                irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
+                                              &gicv2m_irq_chip, v2m);
+        }
 
         return 0;
+
+fail:
+        irq_domain_free_irqs_parent(domain, virq, nr_irqs);
+        gicv2m_unalloc_msi(v2m, hwirq, get_count_order(nr_irqs));
+        return err;
 }
 
 static void gicv2m_irq_domain_free(struct irq_domain *domain,
@@ -210,8 +209,7 @@ static void gicv2m_irq_domain_free(struct irq_domain *domain,
         struct irq_data *d = irq_domain_get_irq_data(domain, virq);
         struct v2m_data *v2m = irq_data_get_irq_chip_data(d);
 
-        BUG_ON(nr_irqs != 1);
-        gicv2m_unalloc_msi(v2m, d->hwirq);
+        gicv2m_unalloc_msi(v2m, d->hwirq, nr_irqs);
         irq_domain_free_irqs_parent(domain, virq, nr_irqs);
 }
 
diff --git a/drivers/irqchip/irq-gic-v3-its-pci-msi.c b/drivers/irqchip/irq-gic-v3-its-pci-msi.c
index 14a8c0a7e095..25a98de5cfb2 100644
--- a/drivers/irqchip/irq-gic-v3-its-pci-msi.c
+++ b/drivers/irqchip/irq-gic-v3-its-pci-msi.c
@@ -132,6 +132,8 @@ static int __init its_pci_of_msi_init(void)
 
         for (np = of_find_matching_node(NULL, its_device_id); np;
              np = of_find_matching_node(np, its_device_id)) {
+                if (!of_device_is_available(np))
+                        continue;
                 if (!of_property_read_bool(np, "msi-controller"))
                         continue;
 
diff --git a/drivers/irqchip/irq-gic-v3-its-platform-msi.c b/drivers/irqchip/irq-gic-v3-its-platform-msi.c
index 833a90fe33ae..8881a053c173 100644
--- a/drivers/irqchip/irq-gic-v3-its-platform-msi.c
+++ b/drivers/irqchip/irq-gic-v3-its-platform-msi.c
@@ -154,6 +154,8 @@ static void __init its_pmsi_of_init(void)
 
         for (np = of_find_matching_node(NULL, its_device_id); np;
              np = of_find_matching_node(np, its_device_id)) {
+                if (!of_device_is_available(np))
+                        continue;
                 if (!of_property_read_bool(np, "msi-controller"))
                         continue;
 
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 06f025fd5726..1d3056f53747 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -3314,6 +3314,8 @@ static int __init its_of_probe(struct device_node *node)
 
         for (np = of_find_matching_node(node, its_device_id); np;
              np = of_find_matching_node(np, its_device_id)) {
+                if (!of_device_is_available(np))
+                        continue;
                 if (!of_property_read_bool(np, "msi-controller")) {
                         pr_warn("%pOF: no msi-controller property, ITS ignored\n",
                                 np);
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index a57c0fbbd34a..d99cc07903ec 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -673,7 +673,7 @@ static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq)
                MPIDR_TO_SGI_RS(cluster_id)              |
                tlist << ICC_SGI1R_TARGET_LIST_SHIFT);
 
-        pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val);
+        pr_devel("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val);
         gic_write_sgi1r(val);
 }
 
@@ -688,7 +688,7 @@ static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
          * Ensure that stores to Normal memory are visible to the
          * other CPUs before issuing the IPI.
          */
-        smp_wmb();
+        wmb();
 
         for_each_cpu(cpu, mask) {
                 u64 cluster_id = MPIDR_TO_SGI_CLUSTER_ID(cpu_logical_map(cpu));
diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index ef92a4d2038e..d32268cc1174 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -424,8 +424,6 @@ static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq,
         spin_lock_irqsave(&gic_lock, flags);
         write_gic_map_pin(intr, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin);
         write_gic_map_vp(intr, BIT(mips_cm_vp_id(cpu)));
-        gic_clear_pcpu_masks(intr);
-        set_bit(intr, per_cpu_ptr(pcpu_masks, cpu));
         irq_data_update_effective_affinity(data, cpumask_of(cpu));
         spin_unlock_irqrestore(&gic_lock, flags);
 
diff --git a/drivers/macintosh/macio_asic.c b/drivers/macintosh/macio_asic.c
index 62f541f968f6..07074820a167 100644
--- a/drivers/macintosh/macio_asic.c
+++ b/drivers/macintosh/macio_asic.c
@@ -375,6 +375,7 @@ static struct macio_dev * macio_add_one_device(struct macio_chip *chip,
         dev->ofdev.dev.of_node = np;
         dev->ofdev.archdata.dma_mask = 0xffffffffUL;
         dev->ofdev.dev.dma_mask = &dev->ofdev.archdata.dma_mask;
+        dev->ofdev.dev.coherent_dma_mask = dev->ofdev.archdata.dma_mask;
         dev->ofdev.dev.parent = parent;
         dev->ofdev.dev.bus = &macio_bus_type;
         dev->ofdev.dev.release = macio_release_dev;
diff --git a/drivers/md/bcache/request.c b/drivers/md/bcache/request.c
index 1a46b41dac70..6422846b546e 100644
--- a/drivers/md/bcache/request.c
+++ b/drivers/md/bcache/request.c
@@ -659,11 +659,11 @@ static void do_bio_hook(struct search *s, struct bio *orig_bio)
 static void search_free(struct closure *cl)
 {
         struct search *s = container_of(cl, struct search, cl);
-        bio_complete(s);
 
         if (s->iop.bio)
                 bio_put(s->iop.bio);
 
+        bio_complete(s);
         closure_debug_destroy(cl);
         mempool_free(s, s->d->c->search);
 }
diff --git a/drivers/md/bcache/super.c b/drivers/md/bcache/super.c
index 312895788036..4d1d8dfb2d2a 100644
--- a/drivers/md/bcache/super.c
+++ b/drivers/md/bcache/super.c
@@ -1274,7 +1274,7 @@ static int flash_devs_run(struct cache_set *c)
         struct uuid_entry *u;
 
         for (u = c->uuids;
-             u < c->uuids + c->devices_max_used && !ret;
+             u < c->uuids + c->nr_uuids && !ret;
              u++)
                 if (UUID_FLASH_ONLY(u))
                         ret = flash_dev_run(c, u);
diff --git a/drivers/md/dm.c b/drivers/md/dm.c
index d6de00f367ef..68136806d365 100644
--- a/drivers/md/dm.c
+++ b/drivers/md/dm.c
@@ -903,7 +903,8 @@ static void dec_pending(struct dm_io *io, blk_status_t error)
                         queue_io(md, bio);
                 } else {
                         /* done with normal IO or empty flush */
-                        bio->bi_status = io_error;
+                        if (io_error)
+                                bio->bi_status = io_error;
                         bio_endio(bio);
                 }
         }
diff --git a/drivers/md/md-multipath.c b/drivers/md/md-multipath.c
index e40065bdbfc8..0a7e99d62c69 100644
--- a/drivers/md/md-multipath.c
+++ b/drivers/md/md-multipath.c
@@ -157,7 +157,7 @@ static void multipath_status(struct seq_file *seq, struct mddev *mddev)
                 seq_printf (seq, "%s", rdev && test_bit(In_sync, &rdev->flags) ? "U" : "_");
         }
         rcu_read_unlock();
-        seq_printf (seq, "]");
+        seq_putc(seq, ']');
 }
 
 static int multipath_congested(struct mddev *mddev, int bits)
diff --git a/drivers/md/md.c b/drivers/md/md.c
index bc67ab6844f0..254e44e44668 100644
--- a/drivers/md/md.c
+++ b/drivers/md/md.c
@@ -801,6 +801,9 @@ void md_super_write(struct mddev *mddev, struct md_rdev *rdev,
         struct bio *bio;
         int ff = 0;
 
+        if (!page)
+                return;
+
         if (test_bit(Faulty, &rdev->flags))
                 return;
 
@@ -5452,6 +5455,7 @@ int md_run(struct mddev *mddev)
          * the only valid external interface is through the md
          * device.
          */
+        mddev->has_superblocks = false;
         rdev_for_each(rdev, mddev) {
                 if (test_bit(Faulty, &rdev->flags))
                         continue;
@@ -5465,6 +5469,9 @@ int md_run(struct mddev *mddev)
                                 set_disk_ro(mddev->gendisk, 1);
                 }
 
+                if (rdev->sb_page)
+                        mddev->has_superblocks = true;
+
                 /* perform some consistency tests on the device.
                  * We don't want the data to overlap the metadata,
                  * Internal Bitmap issues have been handled elsewhere.
@@ -5497,8 +5504,10 @@ int md_run(struct mddev *mddev)
         }
         if (mddev->sync_set == NULL) {
                 mddev->sync_set = bioset_create(BIO_POOL_SIZE, 0, BIOSET_NEED_BVECS);
-                if (!mddev->sync_set)
-                        return -ENOMEM;
+                if (!mddev->sync_set) {
+                        err = -ENOMEM;
+                        goto abort;
+                }
         }
 
         spin_lock(&pers_lock);
@@ -5511,7 +5520,8 @@ int md_run(struct mddev *mddev)
                 else
                         pr_warn("md: personality for level %s is not loaded!\n",
                                 mddev->clevel);
-                return -EINVAL;
+                err = -EINVAL;
+                goto abort;
         }
         spin_unlock(&pers_lock);
         if (mddev->level != pers->level) {
@@ -5524,7 +5534,8 @@ int md_run(struct mddev *mddev)
             pers->start_reshape == NULL) {
                 /* This personality cannot handle reshaping... */
                 module_put(pers->owner);
-                return -EINVAL;
+                err = -EINVAL;
+                goto abort;
         }
 
         if (pers->sync_request) {
@@ -5593,7 +5604,7 @@ int md_run(struct mddev *mddev)
                 mddev->private = NULL;
                 module_put(pers->owner);
                 bitmap_destroy(mddev);
-                return err;
+                goto abort;
         }
         if (mddev->queue) {
                 bool nonrot = true;
@@ -5655,6 +5666,18 @@ int md_run(struct mddev *mddev)
         sysfs_notify_dirent_safe(mddev->sysfs_action);
         sysfs_notify(&mddev->kobj, NULL, "degraded");
         return 0;
+
+abort:
+        if (mddev->bio_set) {
+                bioset_free(mddev->bio_set);
+                mddev->bio_set = NULL;
+        }
+        if (mddev->sync_set) {
+                bioset_free(mddev->sync_set);
+                mddev->sync_set = NULL;
+        }
+
+        return err;
 }
 EXPORT_SYMBOL_GPL(md_run);
 
@@ -8049,6 +8072,7 @@ EXPORT_SYMBOL(md_done_sync);
 bool md_write_start(struct mddev *mddev, struct bio *bi)
 {
         int did_change = 0;
+
         if (bio_data_dir(bi) != WRITE)
                 return true;
 
@@ -8081,6 +8105,8 @@ bool md_write_start(struct mddev *mddev, struct bio *bi)
         rcu_read_unlock();
         if (did_change)
                 sysfs_notify_dirent_safe(mddev->sysfs_state);
+        if (!mddev->has_superblocks)
+                return true;
         wait_event(mddev->sb_wait,
                    !test_bit(MD_SB_CHANGE_PENDING, &mddev->sb_flags) ||
                    mddev->suspended);
@@ -8543,6 +8569,19 @@ void md_do_sync(struct md_thread *thread)
         set_mask_bits(&mddev->sb_flags, 0,
                       BIT(MD_SB_CHANGE_PENDING) | BIT(MD_SB_CHANGE_DEVS));
 
+        if (test_bit(MD_RECOVERY_RESHAPE, &mddev->recovery) &&
+                        !test_bit(MD_RECOVERY_INTR, &mddev->recovery) &&
+                        mddev->delta_disks > 0 &&
+                        mddev->pers->finish_reshape &&
+                        mddev->pers->size &&
+                        mddev->queue) {
+                mddev_lock_nointr(mddev);
+                md_set_array_sectors(mddev, mddev->pers->size(mddev, 0, 0));
+                mddev_unlock(mddev);
+                set_capacity(mddev->gendisk, mddev->array_sectors);
+                revalidate_disk(mddev->gendisk);
+        }
+
         spin_lock(&mddev->lock);
         if (!test_bit(MD_RECOVERY_INTR, &mddev->recovery)) {
                 /* We completed so min/max setting can be forgotten if used. */
@@ -8569,6 +8608,10 @@ static int remove_and_add_spares(struct mddev *mddev,
         int removed = 0;
         bool remove_some = false;
 
+        if (this && test_bit(MD_RECOVERY_RUNNING, &mddev->recovery))
+                /* Mustn't remove devices when resync thread is running */
+                return 0;
+
         rdev_for_each(rdev, mddev) {
                 if ((this == NULL || rdev == this) &&
                     rdev->raid_disk >= 0 &&
diff --git a/drivers/md/md.h b/drivers/md/md.h
index 58cd20a5e85e..fbc925cce810 100644
--- a/drivers/md/md.h
+++ b/drivers/md/md.h
@@ -468,6 +468,8 @@ struct mddev {
         void (*sync_super)(struct mddev *mddev, struct md_rdev *rdev);
         struct md_cluster_info          *cluster_info;
         unsigned int                    good_device_nr; /* good device num within cluster raid */
+
+        bool    has_superblocks:1;
 };
 
 enum recovery_flags {
diff --git a/drivers/md/raid1.c b/drivers/md/raid1.c
index b2eae332e1a2..fe872dc6712e 100644
--- a/drivers/md/raid1.c
+++ b/drivers/md/raid1.c
@@ -1108,7 +1108,7 @@ static void alloc_behind_master_bio(struct r1bio *r1_bio,
 
         bio_copy_data(behind_bio, bio);
 skip_copy:
-        r1_bio->behind_master_bio = behind_bio;;
+        r1_bio->behind_master_bio = behind_bio;
         set_bit(R1BIO_BehindIO, &r1_bio->state);
 
         return;
@@ -1809,6 +1809,17 @@ static int raid1_remove_disk(struct mddev *mddev, struct md_rdev *rdev)
                         struct md_rdev *repl =
                                 conf->mirrors[conf->raid_disks + number].rdev;
                         freeze_array(conf, 0);
+                        if (atomic_read(&repl->nr_pending)) {
+                                /* It means that some queued IO of retry_list
+                                 * hold repl. Thus, we cannot set replacement
+                                 * as NULL, avoiding rdev NULL pointer
+                                 * dereference in sync_request_write and
+                                 * handle_write_finished.
+                                 */
+                                err = -EBUSY;
+                                unfreeze_array(conf);
+                                goto abort;
+                        }
                         clear_bit(Replacement, &repl->flags);
                         p->rdev = repl;
                         conf->mirrors[conf->raid_disks + number].rdev = NULL;
diff --git a/drivers/md/raid1.h b/drivers/md/raid1.h
index c7294e7557e0..eb84bc68e2fd 100644
--- a/drivers/md/raid1.h
+++ b/drivers/md/raid1.h
@@ -26,6 +26,18 @@
 #define BARRIER_BUCKETS_NR_BITS         (PAGE_SHIFT - ilog2(sizeof(atomic_t)))
 #define BARRIER_BUCKETS_NR              (1<<BARRIER_BUCKETS_NR_BITS)
 
+/* Note: raid1_info.rdev can be set to NULL asynchronously by raid1_remove_disk.
+ * There are three safe ways to access raid1_info.rdev.
+ * 1/ when holding mddev->reconfig_mutex
+ * 2/ when resync/recovery is known to be happening - i.e. in code that is
+ *    called as part of performing resync/recovery.
+ * 3/ while holding rcu_read_lock(), use rcu_dereference to get the pointer
+ *    and if it is non-NULL, increment rdev->nr_pending before dropping the
+ *    RCU lock.
+ * When .rdev is set to NULL, the nr_pending count checked again and if it has
+ * been incremented, the pointer is put back in .rdev.
+ */
+
 struct raid1_info {
         struct md_rdev  *rdev;
         sector_t        head_position;
diff --git a/drivers/md/raid10.c b/drivers/md/raid10.c
index 99c9207899a7..c5e6c60fc0d4 100644
--- a/drivers/md/raid10.c
+++ b/drivers/md/raid10.c
@@ -141,7 +141,7 @@ static void r10bio_pool_free(void *r10_bio, void *data)
 #define RESYNC_WINDOW (1024*1024)
 /* maximum number of concurrent requests, memory permitting */
 #define RESYNC_DEPTH (32*1024*1024/RESYNC_BLOCK_SIZE)
-#define CLUSTER_RESYNC_WINDOW (16 * RESYNC_WINDOW)
+#define CLUSTER_RESYNC_WINDOW (32 * RESYNC_WINDOW)
 #define CLUSTER_RESYNC_WINDOW_SECTORS (CLUSTER_RESYNC_WINDOW >> 9)
 
 /*
@@ -2655,7 +2655,8 @@ static void handle_write_completed(struct r10conf *conf, struct r10bio *r10_bio)
                 for (m = 0; m < conf->copies; m++) {
                         int dev = r10_bio->devs[m].devnum;
                         rdev = conf->mirrors[dev].rdev;
-                        if (r10_bio->devs[m].bio == NULL)
+                        if (r10_bio->devs[m].bio == NULL ||
+                                r10_bio->devs[m].bio->bi_end_io == NULL)
                                 continue;
                         if (!r10_bio->devs[m].bio->bi_status) {
                                 rdev_clear_badblocks(
@@ -2670,7 +2671,8 @@ static void handle_write_completed(struct r10conf *conf, struct r10bio *r10_bio)
                                         md_error(conf->mddev, rdev);
                         }
                         rdev = conf->mirrors[dev].replacement;
-                        if (r10_bio->devs[m].repl_bio == NULL)
+                        if (r10_bio->devs[m].repl_bio == NULL ||
+                                r10_bio->devs[m].repl_bio->bi_end_io == NULL)
                                 continue;
 
                         if (!r10_bio->devs[m].repl_bio->bi_status) {
@@ -3782,7 +3784,7 @@ static int raid10_run(struct mddev *mddev)
                 if (fc > 1 || fo > 0) {
                         pr_err("only near layout is supported by clustered"
                                 " raid10\n");
-                        goto out;
+                        goto out_free_conf;
                 }
         }
 
@@ -4830,17 +4832,11 @@ static void raid10_finish_reshape(struct mddev *mddev)
                 return;
 
         if (mddev->delta_disks > 0) {
-                sector_t size = raid10_size(mddev, 0, 0);
-                md_set_array_sectors(mddev, size);
                 if (mddev->recovery_cp > mddev->resync_max_sectors) {
                         mddev->recovery_cp = mddev->resync_max_sectors;
                         set_bit(MD_RECOVERY_NEEDED, &mddev->recovery);
                 }
-                mddev->resync_max_sectors = size;
-                if (mddev->queue) {
-                        set_capacity(mddev->gendisk, mddev->array_sectors);
-                        revalidate_disk(mddev->gendisk);
-                }
+                mddev->resync_max_sectors = mddev->array_sectors;
         } else {
                 int d;
                 rcu_read_lock();
diff --git a/drivers/md/raid10.h b/drivers/md/raid10.h
index db2ac22ac1b4..e2e8840de9bf 100644
--- a/drivers/md/raid10.h
+++ b/drivers/md/raid10.h
@@ -2,6 +2,19 @@
 #ifndef _RAID10_H
 #define _RAID10_H
 
+/* Note: raid10_info.rdev can be set to NULL asynchronously by
+ * raid10_remove_disk.
+ * There are three safe ways to access raid10_info.rdev.
+ * 1/ when holding mddev->reconfig_mutex
+ * 2/ when resync/recovery/reshape is known to be happening - i.e. in code
+ *    that is called as part of performing resync/recovery/reshape.
+ * 3/ while holding rcu_read_lock(), use rcu_dereference to get the pointer
+ *    and if it is non-NULL, increment rdev->nr_pending before dropping the
+ *    RCU lock.
+ * When .rdev is set to NULL, the nr_pending count checked again and if it has
+ * been incremented, the pointer is put back in .rdev.
+ */
+
 struct raid10_info {
         struct md_rdev  *rdev, *replacement;
         sector_t        head_position;
diff --git a/drivers/md/raid5-log.h b/drivers/md/raid5-log.h
index 0c76bcedfc1c..a001808a2b77 100644
--- a/drivers/md/raid5-log.h
+++ b/drivers/md/raid5-log.h
@@ -44,6 +44,7 @@ extern void ppl_write_stripe_run(struct r5conf *conf);
 extern void ppl_stripe_write_finished(struct stripe_head *sh);
 extern int ppl_modify_log(struct r5conf *conf, struct md_rdev *rdev, bool add);
 extern void ppl_quiesce(struct r5conf *conf, int quiesce);
+extern int ppl_handle_flush_request(struct r5l_log *log, struct bio *bio);
 
 static inline bool raid5_has_ppl(struct r5conf *conf)
 {
@@ -104,7 +105,7 @@ static inline int log_handle_flush_request(struct r5conf *conf, struct bio *bio)
         if (conf->log)
                 ret = r5l_handle_flush_request(conf->log, bio);
         else if (raid5_has_ppl(conf))
-                ret = 0;
+                ret = ppl_handle_flush_request(conf->log, bio);
 
         return ret;
 }
diff --git a/drivers/md/raid5-ppl.c b/drivers/md/raid5-ppl.c
index 2764c2290062..42890a08375b 100644
--- a/drivers/md/raid5-ppl.c
+++ b/drivers/md/raid5-ppl.c
@@ -693,6 +693,16 @@ void ppl_quiesce(struct r5conf *conf, int quiesce)
         }
 }
 
+int ppl_handle_flush_request(struct r5l_log *log, struct bio *bio)
+{
+        if (bio->bi_iter.bi_size == 0) {
+                bio_endio(bio);
+                return 0;
+        }
+        bio->bi_opf &= ~REQ_PREFLUSH;
+        return -EAGAIN;
+}
+
 void ppl_stripe_write_finished(struct stripe_head *sh)
 {
         struct ppl_io_unit *io;
diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c
index 50d01144b805..b5d2601483e3 100644
--- a/drivers/md/raid5.c
+++ b/drivers/md/raid5.c
@@ -2196,15 +2196,16 @@ static int grow_one_stripe(struct r5conf *conf, gfp_t gfp)
 static int grow_stripes(struct r5conf *conf, int num)
 {
         struct kmem_cache *sc;
+        size_t namelen = sizeof(conf->cache_name[0]);
         int devs = max(conf->raid_disks, conf->previous_raid_disks);
 
         if (conf->mddev->gendisk)
-                sprintf(conf->cache_name[0],
+                snprintf(conf->cache_name[0], namelen,
                         "raid%d-%s", conf->level, mdname(conf->mddev));
         else
-                sprintf(conf->cache_name[0],
+                snprintf(conf->cache_name[0], namelen,
                         "raid%d-%p", conf->level, conf->mddev);
-        sprintf(conf->cache_name[1], "%s-alt", conf->cache_name[0]);
+        snprintf(conf->cache_name[1], namelen, "%.27s-alt", conf->cache_name[0]);
 
         conf->active_name = 0;
         sc = kmem_cache_create(conf->cache_name[conf->active_name],
@@ -6764,9 +6765,7 @@ static void free_conf(struct r5conf *conf)
 
         log_exit(conf);
 
-        if (conf->shrinker.nr_deferred)
-                unregister_shrinker(&conf->shrinker);
-
+        unregister_shrinker(&conf->shrinker);
         free_thread_groups(conf);
         shrink_stripes(conf);
         raid5_free_percpu(conf);
@@ -8001,13 +8000,7 @@ static void raid5_finish_reshape(struct mddev *mddev)
 
         if (!test_bit(MD_RECOVERY_INTR, &mddev->recovery)) {
 
-                if (mddev->delta_disks > 0) {
-                        md_set_array_sectors(mddev, raid5_size(mddev, 0, 0));
-                        if (mddev->queue) {
-                                set_capacity(mddev->gendisk, mddev->array_sectors);
-                                revalidate_disk(mddev->gendisk);
-                        }
-                } else {
+                if (mddev->delta_disks <= 0) {
                         int d;
                         spin_lock_irq(&conf->device_lock);
                         mddev->degraded = raid5_calc_degraded(conf);
diff --git a/drivers/md/raid5.h b/drivers/md/raid5.h
index 2e6123825095..3f8da26032ac 100644
--- a/drivers/md/raid5.h
+++ b/drivers/md/raid5.h
@@ -450,6 +450,18 @@ enum {
  * HANDLE gets cleared if stripe_handle leaves nothing locked.
  */
 
+/* Note: disk_info.rdev can be set to NULL asynchronously by raid5_remove_disk.
+ * There are three safe ways to access disk_info.rdev.
+ * 1/ when holding mddev->reconfig_mutex
+ * 2/ when resync/recovery/reshape is known to be happening - i.e. in code that
+ *    is called as part of performing resync/recovery/reshape.
+ * 3/ while holding rcu_read_lock(), use rcu_dereference to get the pointer
+ *    and if it is non-NULL, increment rdev->nr_pending before dropping the RCU
+ *    lock.
+ * When .rdev is set to NULL, the nr_pending count checked again and if
+ * it has been incremented, the pointer is put back in .rdev.
+ */
+
 struct disk_info {
         struct md_rdev  *rdev, *replacement;
         struct page     *extra_page; /* extra page to use in prexor */
diff --git a/drivers/media/Kconfig b/drivers/media/Kconfig
index 145e12bfb819..372c074bb1b9 100644
--- a/drivers/media/Kconfig
+++ b/drivers/media/Kconfig
@@ -147,6 +147,8 @@ config DVB_CORE
 config DVB_MMAP
         bool "Enable DVB memory-mapped API (EXPERIMENTAL)"
         depends on DVB_CORE
+        depends on VIDEO_V4L2=y || VIDEO_V4L2=DVB_CORE
+        select VIDEOBUF2_VMALLOC
         default n
         help
           This option enables DVB experimental memory-mapped API, with
diff --git a/drivers/media/common/videobuf2/Kconfig b/drivers/media/common/videobuf2/Kconfig
index 5df05250de94..17c32ea58395 100644
--- a/drivers/media/common/videobuf2/Kconfig
+++ b/drivers/media/common/videobuf2/Kconfig
@@ -3,6 +3,9 @@ config VIDEOBUF2_CORE
         select DMA_SHARED_BUFFER
         tristate
 
+config VIDEOBUF2_V4L2
+        tristate
+
 config VIDEOBUF2_MEMOPS
         tristate
         select FRAME_VECTOR
diff --git a/drivers/media/common/videobuf2/Makefile b/drivers/media/common/videobuf2/Makefile
index 19de5ccda20b..77bebe8b202f 100644
--- a/drivers/media/common/videobuf2/Makefile
+++ b/drivers/media/common/videobuf2/Makefile
@@ -1,5 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0
+videobuf2-common-objs := videobuf2-core.o
 
-obj-$(CONFIG_VIDEOBUF2_CORE) += videobuf2-core.o videobuf2-v4l2.o
+ifeq ($(CONFIG_TRACEPOINTS),y)
+  videobuf2-common-objs += vb2-trace.o
+endif
+
+obj-$(CONFIG_VIDEOBUF2_CORE) += videobuf2-common.o
+obj-$(CONFIG_VIDEOBUF2_V4L2) += videobuf2-v4l2.o
 obj-$(CONFIG_VIDEOBUF2_MEMOPS) += videobuf2-memops.o
 obj-$(CONFIG_VIDEOBUF2_VMALLOC) += videobuf2-vmalloc.o
 obj-$(CONFIG_VIDEOBUF2_DMA_CONTIG) += videobuf2-dma-contig.o
diff --git a/drivers/media/v4l2-core/vb2-trace.c b/drivers/media/common/videobuf2/vb2-trace.c
index 4c0f39d271f0..4c0f39d271f0 100644
--- a/drivers/media/v4l2-core/vb2-trace.c
+++ b/drivers/media/common/videobuf2/vb2-trace.c
diff --git a/drivers/media/dvb-core/Makefile b/drivers/media/dvb-core/Makefile
index 3a105d82019a..62b028ded9f7 100644
--- a/drivers/media/dvb-core/Makefile
+++ b/drivers/media/dvb-core/Makefile
@@ -4,7 +4,7 @@
 #
 
 dvb-net-$(CONFIG_DVB_NET) := dvb_net.o
-dvb-vb2-$(CONFIG_DVB_MMSP) := dvb_vb2.o
+dvb-vb2-$(CONFIG_DVB_MMAP) := dvb_vb2.o
 
 dvb-core-objs := dvbdev.o dmxdev.o dvb_demux.o                  \
                  dvb_ca_en50221.o dvb_frontend.o                \
diff --git a/drivers/media/dvb-core/dmxdev.c b/drivers/media/dvb-core/dmxdev.c
index 6d53af00190e..61a750fae465 100644
--- a/drivers/media/dvb-core/dmxdev.c
+++ b/drivers/media/dvb-core/dmxdev.c
@@ -128,11 +128,7 @@ static int dvb_dvr_open(struct inode *inode, struct file *file)
         struct dvb_device *dvbdev = file->private_data;
         struct dmxdev *dmxdev = dvbdev->priv;
         struct dmx_frontend *front;
-#ifndef DVB_MMAP
         bool need_ringbuffer = false;
-#else
-        const bool need_ringbuffer = true;
-#endif
 
         dprintk("%s\n", __func__);
 
@@ -144,17 +140,31 @@ static int dvb_dvr_open(struct inode *inode, struct file *file)
                 return -ENODEV;
         }
 
-#ifndef DVB_MMAP
+        dmxdev->may_do_mmap = 0;
+
+        /*
+         * The logic here is a little tricky due to the ifdef.
+         *
+         * The ringbuffer is used for both read and mmap.
+         *
+         * It is not needed, however, on two situations:
+         *      - Write devices (access with O_WRONLY);
+         *      - For duplex device nodes, opened with O_RDWR.
+         */
+
         if ((file->f_flags & O_ACCMODE) == O_RDONLY)
                 need_ringbuffer = true;
-#else
-        if ((file->f_flags & O_ACCMODE) == O_RDWR) {
+        else if ((file->f_flags & O_ACCMODE) == O_RDWR) {
                 if (!(dmxdev->capabilities & DMXDEV_CAP_DUPLEX)) {
+#ifdef CONFIG_DVB_MMAP
+                        dmxdev->may_do_mmap = 1;
+                        need_ringbuffer = true;
+#else
                         mutex_unlock(&dmxdev->mutex);
                         return -EOPNOTSUPP;
+#endif
                 }
         }
-#endif
 
         if (need_ringbuffer) {
                 void *mem;
@@ -169,8 +179,9 @@ static int dvb_dvr_open(struct inode *inode, struct file *file)
                         return -ENOMEM;
                 }
                 dvb_ringbuffer_init(&dmxdev->dvr_buffer, mem, DVR_BUFFER_SIZE);
-                dvb_vb2_init(&dmxdev->dvr_vb2_ctx, "dvr",
-                             file->f_flags & O_NONBLOCK);
+                if (dmxdev->may_do_mmap)
+                        dvb_vb2_init(&dmxdev->dvr_vb2_ctx, "dvr",
+                                     file->f_flags & O_NONBLOCK);
                 dvbdev->readers--;
         }
 
@@ -200,11 +211,6 @@ static int dvb_dvr_release(struct inode *inode, struct file *file)
 {
         struct dvb_device *dvbdev = file->private_data;
         struct dmxdev *dmxdev = dvbdev->priv;
-#ifndef DVB_MMAP
-        bool need_ringbuffer = false;
-#else
-        const bool need_ringbuffer = true;
-#endif
 
         mutex_lock(&dmxdev->mutex);
 
@@ -213,15 +219,14 @@ static int dvb_dvr_release(struct inode *inode, struct file *file)
                 dmxdev->demux->connect_frontend(dmxdev->demux,
                                                 dmxdev->dvr_orig_fe);
         }
-#ifndef DVB_MMAP
-        if ((file->f_flags & O_ACCMODE) == O_RDONLY)
-                need_ringbuffer = true;
-#endif
 
-        if (need_ringbuffer) {
-                if (dvb_vb2_is_streaming(&dmxdev->dvr_vb2_ctx))
-                        dvb_vb2_stream_off(&dmxdev->dvr_vb2_ctx);
-                dvb_vb2_release(&dmxdev->dvr_vb2_ctx);
+        if (((file->f_flags & O_ACCMODE) == O_RDONLY) ||
+            dmxdev->may_do_mmap) {
+                if (dmxdev->may_do_mmap) {
+                        if (dvb_vb2_is_streaming(&dmxdev->dvr_vb2_ctx))
+                                dvb_vb2_stream_off(&dmxdev->dvr_vb2_ctx);
+                        dvb_vb2_release(&dmxdev->dvr_vb2_ctx);
+                }
                 dvbdev->readers++;
                 if (dmxdev->dvr_buffer.data) {
                         void *mem = dmxdev->dvr_buffer.data;
@@ -380,7 +385,8 @@ static void dvb_dmxdev_filter_timer(struct dmxdev_filter *dmxdevfilter)
 
 static int dvb_dmxdev_section_callback(const u8 *buffer1, size_t buffer1_len,
                                        const u8 *buffer2, size_t buffer2_len,
-                                       struct dmx_section_filter *filter)
+                                       struct dmx_section_filter *filter,
+                                       u32 *buffer_flags)
 {
         struct dmxdev_filter *dmxdevfilter = filter->priv;
         int ret;
@@ -399,10 +405,12 @@ static int dvb_dmxdev_section_callback(const u8 *buffer1, size_t buffer1_len,
         dprintk("section callback %*ph\n", 6, buffer1);
         if (dvb_vb2_is_streaming(&dmxdevfilter->vb2_ctx)) {
                 ret = dvb_vb2_fill_buffer(&dmxdevfilter->vb2_ctx,
-                                          buffer1, buffer1_len);
+                                          buffer1, buffer1_len,
+                                          buffer_flags);
                 if (ret == buffer1_len)
                         ret = dvb_vb2_fill_buffer(&dmxdevfilter->vb2_ctx,
-                                                  buffer2, buffer2_len);
+                                                  buffer2, buffer2_len,
+                                                  buffer_flags);
         } else {
                 ret = dvb_dmxdev_buffer_write(&dmxdevfilter->buffer,
                                               buffer1, buffer1_len);
@@ -422,11 +430,12 @@ static int dvb_dmxdev_section_callback(const u8 *buffer1, size_t buffer1_len,
 
 static int dvb_dmxdev_ts_callback(const u8 *buffer1, size_t buffer1_len,
                                   const u8 *buffer2, size_t buffer2_len,
-                                  struct dmx_ts_feed *feed)
+                                  struct dmx_ts_feed *feed,
+                                  u32 *buffer_flags)
 {
         struct dmxdev_filter *dmxdevfilter = feed->priv;
         struct dvb_ringbuffer *buffer;
-#ifdef DVB_MMAP
+#ifdef CONFIG_DVB_MMAP
         struct dvb_vb2_ctx *ctx;
 #endif
         int ret;
@@ -440,20 +449,22 @@ static int dvb_dmxdev_ts_callback(const u8 *buffer1, size_t buffer1_len,
         if (dmxdevfilter->params.pes.output == DMX_OUT_TAP ||
             dmxdevfilter->params.pes.output == DMX_OUT_TSDEMUX_TAP) {
                 buffer = &dmxdevfilter->buffer;
-#ifdef DVB_MMAP
+#ifdef CONFIG_DVB_MMAP
                 ctx = &dmxdevfilter->vb2_ctx;
 #endif
         } else {
                 buffer = &dmxdevfilter->dev->dvr_buffer;
-#ifdef DVB_MMAP
+#ifdef CONFIG_DVB_MMAP
                 ctx = &dmxdevfilter->dev->dvr_vb2_ctx;
 #endif
         }
 
         if (dvb_vb2_is_streaming(ctx)) {
-                ret = dvb_vb2_fill_buffer(ctx, buffer1, buffer1_len);
+                ret = dvb_vb2_fill_buffer(ctx, buffer1, buffer1_len,
+                                          buffer_flags);
                 if (ret == buffer1_len)
-                        ret = dvb_vb2_fill_buffer(ctx, buffer2, buffer2_len);
+                        ret = dvb_vb2_fill_buffer(ctx, buffer2, buffer2_len,
+                                                  buffer_flags);
         } else {
                 if (buffer->error) {
                         spin_unlock(&dmxdevfilter->dev->lock);
@@ -802,6 +813,12 @@ static int dvb_demux_open(struct inode *inode, struct file *file)
         mutex_init(&dmxdevfilter->mutex);
         file->private_data = dmxdevfilter;
 
+#ifdef CONFIG_DVB_MMAP
+        dmxdev->may_do_mmap = 1;
+#else
+        dmxdev->may_do_mmap = 0;
+#endif
+
         dvb_ringbuffer_init(&dmxdevfilter->buffer, NULL, 8192);
         dvb_vb2_init(&dmxdevfilter->vb2_ctx, "demux_filter",
                      file->f_flags & O_NONBLOCK);
@@ -1111,7 +1128,7 @@ static int dvb_demux_do_ioctl(struct file *file,
                 mutex_unlock(&dmxdevfilter->mutex);
                 break;
 
-#ifdef DVB_MMAP
+#ifdef CONFIG_DVB_MMAP
         case DMX_REQBUFS:
                 if (mutex_lock_interruptible(&dmxdevfilter->mutex)) {
                         mutex_unlock(&dmxdev->mutex);
@@ -1160,7 +1177,7 @@ static int dvb_demux_do_ioctl(struct file *file,
                 break;
 #endif
         default:
-                ret = -EINVAL;
+                ret = -ENOTTY;
                 break;
         }
         mutex_unlock(&dmxdev->mutex);
@@ -1199,13 +1216,16 @@ static __poll_t dvb_demux_poll(struct file *file, poll_table *wait)
         return mask;
 }
 
-#ifdef DVB_MMAP
+#ifdef CONFIG_DVB_MMAP
 static int dvb_demux_mmap(struct file *file, struct vm_area_struct *vma)
 {
         struct dmxdev_filter *dmxdevfilter = file->private_data;
         struct dmxdev *dmxdev = dmxdevfilter->dev;
         int ret;
 
+        if (!dmxdev->may_do_mmap)
+                return -ENOTTY;
+
         if (mutex_lock_interruptible(&dmxdev->mutex))
                 return -ERESTARTSYS;
 
@@ -1249,7 +1269,7 @@ static const struct file_operations dvb_demux_fops = {
         .release = dvb_demux_release,
         .poll = dvb_demux_poll,
         .llseek = default_llseek,
-#ifdef DVB_MMAP
+#ifdef CONFIG_DVB_MMAP
         .mmap = dvb_demux_mmap,
 #endif
 };
@@ -1280,7 +1300,7 @@ static int dvb_dvr_do_ioctl(struct file *file,
                 ret = dvb_dvr_set_buffer_size(dmxdev, arg);
                 break;
 
-#ifdef DVB_MMAP
+#ifdef CONFIG_DVB_MMAP
         case DMX_REQBUFS:
                 ret = dvb_vb2_reqbufs(&dmxdev->dvr_vb2_ctx, parg);
                 break;
@@ -1304,7 +1324,7 @@ static int dvb_dvr_do_ioctl(struct file *file,
                 break;
 #endif
         default:
-                ret = -EINVAL;
+                ret = -ENOTTY;
                 break;
         }
         mutex_unlock(&dmxdev->mutex);
@@ -1322,11 +1342,6 @@ static __poll_t dvb_dvr_poll(struct file *file, poll_table *wait)
         struct dvb_device *dvbdev = file->private_data;
         struct dmxdev *dmxdev = dvbdev->priv;
         __poll_t mask = 0;
-#ifndef DVB_MMAP
-        bool need_ringbuffer = false;
-#else
-        const bool need_ringbuffer = true;
-#endif
 
         dprintk("%s\n", __func__);
 
@@ -1337,11 +1352,8 @@ static __poll_t dvb_dvr_poll(struct file *file, poll_table *wait)
 
         poll_wait(file, &dmxdev->dvr_buffer.queue, wait);
 
-#ifndef DVB_MMAP
-        if ((file->f_flags & O_ACCMODE) == O_RDONLY)
-                need_ringbuffer = true;
-#endif
-        if (need_ringbuffer) {
+        if (((file->f_flags & O_ACCMODE) == O_RDONLY) ||
+            dmxdev->may_do_mmap) {
                 if (dmxdev->dvr_buffer.error)
                         mask |= (EPOLLIN | EPOLLRDNORM | EPOLLPRI | EPOLLERR);
 
@@ -1353,13 +1365,16 @@ static __poll_t dvb_dvr_poll(struct file *file, poll_table *wait)
         return mask;
 }
 
-#ifdef DVB_MMAP
+#ifdef CONFIG_DVB_MMAP
 static int dvb_dvr_mmap(struct file *file, struct vm_area_struct *vma)
 {
         struct dvb_device *dvbdev = file->private_data;
         struct dmxdev *dmxdev = dvbdev->priv;
         int ret;
 
+        if (!dmxdev->may_do_mmap)
+                return -ENOTTY;
+
         if (dmxdev->exit)
                 return -ENODEV;
 
@@ -1381,7 +1396,7 @@ static const struct file_operations dvb_dvr_fops = {
         .release = dvb_dvr_release,
         .poll = dvb_dvr_poll,
         .llseek = default_llseek,
-#ifdef DVB_MMAP
+#ifdef CONFIG_DVB_MMAP
         .mmap = dvb_dvr_mmap,
 #endif
 };
diff --git a/drivers/media/dvb-core/dvb_demux.c b/drivers/media/dvb-core/dvb_demux.c
index 210eed0269b0..f45091246bdc 100644
--- a/drivers/media/dvb-core/dvb_demux.c
+++ b/drivers/media/dvb-core/dvb_demux.c
@@ -55,6 +55,17 @@ MODULE_PARM_DESC(dvb_demux_feed_err_pkts,
                 dprintk(x);                             \
 } while (0)
 
+#ifdef CONFIG_DVB_DEMUX_SECTION_LOSS_LOG
+#  define dprintk_sect_loss(x...) dprintk(x)
+#else
+#  define dprintk_sect_loss(x...)
+#endif
+
+#define set_buf_flags(__feed, __flag)                   \
+        do {                                            \
+                (__feed)->buffer_flags |= (__flag);     \
+        } while (0)
+
 /******************************************************************************
  * static inlined helper functions
  ******************************************************************************/
@@ -104,31 +115,30 @@ static inline int dvb_dmx_swfilter_payload(struct dvb_demux_feed *feed,
 {
         int count = payload(buf);
         int p;
-#ifdef CONFIG_DVB_DEMUX_SECTION_LOSS_LOG
         int ccok;
         u8 cc;
-#endif
 
         if (count == 0)
                 return -1;
 
         p = 188 - count;
 
-#ifdef CONFIG_DVB_DEMUX_SECTION_LOSS_LOG
         cc = buf[3] & 0x0f;
         ccok = ((feed->cc + 1) & 0x0f) == cc;
         feed->cc = cc;
-        if (!ccok)
-                dprintk("missed packet: %d instead of %d!\n",
-                        cc, (feed->cc + 1) & 0x0f);
-#endif
+        if (!ccok) {
+                set_buf_flags(feed, DMX_BUFFER_FLAG_DISCONTINUITY_DETECTED);
+                dprintk_sect_loss("missed packet: %d instead of %d!\n",
+                                  cc, (feed->cc + 1) & 0x0f);
+        }
 
         if (buf[1] & 0x40)      // PUSI ?
                 feed->peslen = 0xfffa;
 
         feed->peslen += count;
 
-        return feed->cb.ts(&buf[p], count, NULL, 0, &feed->feed.ts);
+        return feed->cb.ts(&buf[p], count, NULL, 0, &feed->feed.ts,
+                           &feed->buffer_flags);
 }
 
 static int dvb_dmx_swfilter_sectionfilter(struct dvb_demux_feed *feed,
@@ -150,7 +160,7 @@ static int dvb_dmx_swfilter_sectionfilter(struct dvb_demux_feed *feed,
                 return 0;
 
         return feed->cb.sec(feed->feed.sec.secbuf, feed->feed.sec.seclen,
-                            NULL, 0, &f->filter);
+                            NULL, 0, &f->filter, &feed->buffer_flags);
 }
 
 static inline int dvb_dmx_swfilter_section_feed(struct dvb_demux_feed *feed)
@@ -169,8 +179,10 @@ static inline int dvb_dmx_swfilter_section_feed(struct dvb_demux_feed *feed)
         if (sec->check_crc) {
                 section_syntax_indicator = ((sec->secbuf[1] & 0x80) != 0);
                 if (section_syntax_indicator &&
-                    demux->check_crc32(feed, sec->secbuf, sec->seclen))
+                    demux->check_crc32(feed, sec->secbuf, sec->seclen)) {
+                        set_buf_flags(feed, DMX_BUFFER_FLAG_HAD_CRC32_DISCARD);
                         return -1;
+                }
         }
 
         do {
@@ -187,7 +199,6 @@ static void dvb_dmx_swfilter_section_new(struct dvb_demux_feed *feed)
 {
         struct dmx_section_feed *sec = &feed->feed.sec;
 
-#ifdef CONFIG_DVB_DEMUX_SECTION_LOSS_LOG
         if (sec->secbufp < sec->tsfeedp) {
                 int n = sec->tsfeedp - sec->secbufp;
 
@@ -197,12 +208,13 @@ static void dvb_dmx_swfilter_section_new(struct dvb_demux_feed *feed)
                  * but just first and last.
                  */
                 if (sec->secbuf[0] != 0xff || sec->secbuf[n - 1] != 0xff) {
-                        dprintk("section ts padding loss: %d/%d\n",
-                               n, sec->tsfeedp);
-                        dprintk("pad data: %*ph\n", n, sec->secbuf);
+                        set_buf_flags(feed,
+                                      DMX_BUFFER_FLAG_DISCONTINUITY_DETECTED);
+                        dprintk_sect_loss("section ts padding loss: %d/%d\n",
+                                          n, sec->tsfeedp);
+                        dprintk_sect_loss("pad data: %*ph\n", n, sec->secbuf);
                 }
         }
-#endif
 
         sec->tsfeedp = sec->secbufp = sec->seclen = 0;
         sec->secbuf = sec->secbuf_base;
@@ -237,11 +249,10 @@ static int dvb_dmx_swfilter_section_copy_dump(struct dvb_demux_feed *feed,
                 return 0;
 
         if (sec->tsfeedp + len > DMX_MAX_SECFEED_SIZE) {
-#ifdef CONFIG_DVB_DEMUX_SECTION_LOSS_LOG
-                dprintk("section buffer full loss: %d/%d\n",
-                        sec->tsfeedp + len - DMX_MAX_SECFEED_SIZE,
-                        DMX_MAX_SECFEED_SIZE);
-#endif
+                set_buf_flags(feed, DMX_BUFFER_FLAG_DISCONTINUITY_DETECTED);
+                dprintk_sect_loss("section buffer full loss: %d/%d\n",
+                                  sec->tsfeedp + len - DMX_MAX_SECFEED_SIZE,
+                                  DMX_MAX_SECFEED_SIZE);
                 len = DMX_MAX_SECFEED_SIZE - sec->tsfeedp;
         }
 
@@ -269,12 +280,13 @@ static int dvb_dmx_swfilter_section_copy_dump(struct dvb_demux_feed *feed,
                 sec->seclen = seclen;
                 sec->crc_val = ~0;
                 /* dump [secbuf .. secbuf+seclen) */
-                if (feed->pusi_seen)
+                if (feed->pusi_seen) {
                         dvb_dmx_swfilter_section_feed(feed);
-#ifdef CONFIG_DVB_DEMUX_SECTION_LOSS_LOG
-                else
-                        dprintk("pusi not seen, discarding section data\n");
-#endif
+                } else {
+                        set_buf_flags(feed,
+                                      DMX_BUFFER_FLAG_DISCONTINUITY_DETECTED);
+                        dprintk_sect_loss("pusi not seen, discarding section data\n");
+                }
                 sec->secbufp += seclen; /* secbufp and secbuf moving together is */
                 sec->secbuf += seclen;  /* redundant but saves pointer arithmetic */
         }
@@ -307,18 +319,22 @@ static int dvb_dmx_swfilter_section_packet(struct dvb_demux_feed *feed,
         }
 
         if (!ccok || dc_i) {
-#ifdef CONFIG_DVB_DEMUX_SECTION_LOSS_LOG
-                if (dc_i)
-                        dprintk("%d frame with disconnect indicator\n",
+                if (dc_i) {
+                        set_buf_flags(feed,
+                                      DMX_BUFFER_FLAG_DISCONTINUITY_INDICATOR);
+                        dprintk_sect_loss("%d frame with disconnect indicator\n",
                                 cc);
-                else
-                        dprintk("discontinuity: %d instead of %d. %d bytes lost\n",
+                } else {
+                        set_buf_flags(feed,
+                                      DMX_BUFFER_FLAG_DISCONTINUITY_DETECTED);
+                        dprintk_sect_loss("discontinuity: %d instead of %d. %d bytes lost\n",
                                 cc, (feed->cc + 1) & 0x0f, count + 4);
+                }
                 /*
-                 * those bytes under sume circumstances will again be reported
+                 * those bytes under some circumstances will again be reported
                  * in the following dvb_dmx_swfilter_section_new
                  */
-#endif
+
                 /*
                  * Discontinuity detected. Reset pusi_seen to
                  * stop feeding of suspicious data until next PUSI=1 arrives
@@ -326,6 +342,7 @@ static int dvb_dmx_swfilter_section_packet(struct dvb_demux_feed *feed,
                  * FIXME: does it make sense if the MPEG-TS is the one
                  *      reporting discontinuity?
                  */
+
                 feed->pusi_seen = false;
                 dvb_dmx_swfilter_section_new(feed);
         }
@@ -345,11 +362,11 @@ static int dvb_dmx_swfilter_section_packet(struct dvb_demux_feed *feed,
                         dvb_dmx_swfilter_section_new(feed);
                         dvb_dmx_swfilter_section_copy_dump(feed, after,
                                                            after_len);
+                } else if (count > 0) {
+                        set_buf_flags(feed,
+                                      DMX_BUFFER_FLAG_DISCONTINUITY_DETECTED);
+                        dprintk_sect_loss("PUSI=1 but %d bytes lost\n", count);
                 }
-#ifdef CONFIG_DVB_DEMUX_SECTION_LOSS_LOG
-                else if (count > 0)
-                        dprintk("PUSI=1 but %d bytes lost\n", count);
-#endif
         } else {
                 /* PUSI=0 (is not set), no section boundary */
                 dvb_dmx_swfilter_section_copy_dump(feed, &buf[p], count);
@@ -369,7 +386,8 @@ static inline void dvb_dmx_swfilter_packet_type(struct dvb_demux_feed *feed,
                         if (feed->ts_type & TS_PAYLOAD_ONLY)
                                 dvb_dmx_swfilter_payload(feed, buf);
                         else
-                                feed->cb.ts(buf, 188, NULL, 0, &feed->feed.ts);
+                                feed->cb.ts(buf, 188, NULL, 0, &feed->feed.ts,
+                                            &feed->buffer_flags);
                 }
                 /* Used only on full-featured devices */
                 if (feed->ts_type & TS_DECODER)
@@ -430,6 +448,11 @@ static void dvb_dmx_swfilter_packet(struct dvb_demux *demux, const u8 *buf)
         }
 
         if (buf[1] & 0x80) {
+                list_for_each_entry(feed, &demux->feed_list, list_head) {
+                        if ((feed->pid != pid) && (feed->pid != 0x2000))
+                                continue;
+                        set_buf_flags(feed, DMX_BUFFER_FLAG_TEI);
+                }
                 dprintk_tscheck("TEI detected. PID=0x%x data1=0x%x\n",
                                 pid, buf[1]);
                 /* data in this packet can't be trusted - drop it unless
@@ -445,6 +468,13 @@ static void dvb_dmx_swfilter_packet(struct dvb_demux *demux, const u8 *buf)
                                                 (demux->cnt_storage[pid] + 1) & 0xf;
 
                                 if ((buf[3] & 0xf) != demux->cnt_storage[pid]) {
+                                        list_for_each_entry(feed, &demux->feed_list, list_head) {
+                                                if ((feed->pid != pid) && (feed->pid != 0x2000))
+                                                        continue;
+                                                set_buf_flags(feed,
+                                                              DMX_BUFFER_PKT_COUNTER_MISMATCH);
+                                        }
+
                                         dprintk_tscheck("TS packet counter mismatch. PID=0x%x expected 0x%x got 0x%x\n",
                                                         pid, demux->cnt_storage[pid],
                                                         buf[3] & 0xf);
@@ -466,7 +496,8 @@ static void dvb_dmx_swfilter_packet(struct dvb_demux *demux, const u8 *buf)
                 if (feed->pid == pid)
                         dvb_dmx_swfilter_packet_type(feed, buf);
                 else if (feed->pid == 0x2000)
-                        feed->cb.ts(buf, 188, NULL, 0, &feed->feed.ts);
+                        feed->cb.ts(buf, 188, NULL, 0, &feed->feed.ts,
+                                    &feed->buffer_flags);
         }
 }
 
@@ -585,7 +616,8 @@ void dvb_dmx_swfilter_raw(struct dvb_demux *demux, const u8 *buf, size_t count)
 
         spin_lock_irqsave(&demux->lock, flags);
 
-        demux->feed->cb.ts(buf, count, NULL, 0, &demux->feed->feed.ts);
+        demux->feed->cb.ts(buf, count, NULL, 0, &demux->feed->feed.ts,
+                           &demux->feed->buffer_flags);
 
         spin_unlock_irqrestore(&demux->lock, flags);
 }
@@ -785,6 +817,7 @@ static int dvbdmx_allocate_ts_feed(struct dmx_demux *dmx,
         feed->demux = demux;
         feed->pid = 0xffff;
         feed->peslen = 0xfffa;
+        feed->buffer_flags = 0;
 
         (*ts_feed) = &feed->feed.ts;
         (*ts_feed)->parent = dmx;
@@ -1042,6 +1075,7 @@ static int dvbdmx_allocate_section_feed(struct dmx_demux *demux,
         dvbdmxfeed->cb.sec = callback;
         dvbdmxfeed->demux = dvbdmx;
         dvbdmxfeed->pid = 0xffff;
+        dvbdmxfeed->buffer_flags = 0;
         dvbdmxfeed->feed.sec.secbuf = dvbdmxfeed->feed.sec.secbuf_base;
         dvbdmxfeed->feed.sec.secbufp = dvbdmxfeed->feed.sec.seclen = 0;
         dvbdmxfeed->feed.sec.tsfeedp = 0;
diff --git a/drivers/media/dvb-core/dvb_net.c b/drivers/media/dvb-core/dvb_net.c
index b6c7eec863b9..ba39f9942e1d 100644
--- a/drivers/media/dvb-core/dvb_net.c
+++ b/drivers/media/dvb-core/dvb_net.c
@@ -883,7 +883,8 @@ static void dvb_net_ule(struct net_device *dev, const u8 *buf, size_t buf_len)
 
 static int dvb_net_ts_callback(const u8 *buffer1, size_t buffer1_len,
                                const u8 *buffer2, size_t buffer2_len,
-                               struct dmx_ts_feed *feed)
+                               struct dmx_ts_feed *feed,
+                               u32 *buffer_flags)
 {
         struct net_device *dev = feed->priv;
 
@@ -992,7 +993,7 @@ static void dvb_net_sec(struct net_device *dev,
 
 static int dvb_net_sec_callback(const u8 *buffer1, size_t buffer1_len,
                  const u8 *buffer2, size_t buffer2_len,
-                 struct dmx_section_filter *filter)
+                 struct dmx_section_filter *filter, u32 *buffer_flags)
 {
         struct net_device *dev = filter->priv;
 
diff --git a/drivers/media/dvb-core/dvb_vb2.c b/drivers/media/dvb-core/dvb_vb2.c
index 763145d74e83..b811adf88afa 100644
--- a/drivers/media/dvb-core/dvb_vb2.c
+++ b/drivers/media/dvb-core/dvb_vb2.c
@@ -256,7 +256,8 @@ int dvb_vb2_is_streaming(struct dvb_vb2_ctx *ctx)
 }
 
 int dvb_vb2_fill_buffer(struct dvb_vb2_ctx *ctx,
-                        const unsigned char *src, int len)
+                        const unsigned char *src, int len,
+                        enum dmx_buffer_flags *buffer_flags)
 {
         unsigned long flags = 0;
         void *vbuf = NULL;
@@ -264,15 +265,17 @@ int dvb_vb2_fill_buffer(struct dvb_vb2_ctx *ctx,
         unsigned char *psrc = (unsigned char *)src;
         int ll = 0;
 
-        dprintk(3, "[%s] %d bytes are rcvd\n", ctx->name, len);
-        if (!src) {
-                dprintk(3, "[%s]:NULL pointer src\n", ctx->name);
-                /**normal case: This func is called twice from demux driver
-                 * once with valid src pointer, second time with NULL pointer
-                 */
+        /*
+         * normal case: This func is called twice from demux driver
+         * one with valid src pointer, second time with NULL pointer
+         */
+        if (!src || !len)
                 return 0;
-        }
         spin_lock_irqsave(&ctx->slock, flags);
+        if (buffer_flags && *buffer_flags) {
+                ctx->flags |= *buffer_flags;
+                *buffer_flags = 0;
+        }
         while (todo) {
                 if (!ctx->buf) {
                         if (list_empty(&ctx->dvb_q)) {
@@ -395,6 +398,7 @@ int dvb_vb2_qbuf(struct dvb_vb2_ctx *ctx, struct dmx_buffer *b)
 
 int dvb_vb2_dqbuf(struct dvb_vb2_ctx *ctx, struct dmx_buffer *b)
 {
+        unsigned long flags;
         int ret;
 
         ret = vb2_core_dqbuf(&ctx->vb_q, &b->index, b, ctx->nonblocking);
@@ -402,7 +406,16 @@ int dvb_vb2_dqbuf(struct dvb_vb2_ctx *ctx, struct dmx_buffer *b)
                 dprintk(1, "[%s] errno=%d\n", ctx->name, ret);
                 return ret;
         }
-        dprintk(5, "[%s] index=%d\n", ctx->name, b->index);
+
+        spin_lock_irqsave(&ctx->slock, flags);
+        b->count = ctx->count++;
+        b->flags = ctx->flags;
+        ctx->flags = 0;
+        spin_unlock_irqrestore(&ctx->slock, flags);
+
+        dprintk(5, "[%s] index=%d, count=%d, flags=%d\n",
+                ctx->name, b->index, ctx->count, b->flags);
+
 
         return 0;
 }
diff --git a/drivers/media/dvb-frontends/m88ds3103.c b/drivers/media/dvb-frontends/m88ds3103.c
index 50bce68ffd66..65d157fe76d1 100644
--- a/drivers/media/dvb-frontends/m88ds3103.c
+++ b/drivers/media/dvb-frontends/m88ds3103.c
@@ -1262,11 +1262,12 @@ static int m88ds3103_select(struct i2c_mux_core *muxc, u32 chan)
  * New users must use I2C client binding directly!
  */
 struct dvb_frontend *m88ds3103_attach(const struct m88ds3103_config *cfg,
-                struct i2c_adapter *i2c, struct i2c_adapter **tuner_i2c_adapter)
+                                      struct i2c_adapter *i2c,
+                                      struct i2c_adapter **tuner_i2c_adapter)
 {
         struct i2c_client *client;
         struct i2c_board_info board_info;
-        struct m88ds3103_platform_data pdata;
+        struct m88ds3103_platform_data pdata = {};
 
         pdata.clk = cfg->clock;
         pdata.i2c_wr_max = cfg->i2c_wr_max;
@@ -1409,6 +1410,8 @@ static int m88ds3103_probe(struct i2c_client *client,
         case M88DS3103_CHIP_ID:
                 break;
         default:
+                ret = -ENODEV;
+                dev_err(&client->dev, "Unknown device. Chip_id=%02x\n", dev->chip_id);
                 goto err_kfree;
         }
 
diff --git a/drivers/media/i2c/tvp5150.c b/drivers/media/i2c/tvp5150.c
index 3c1851984b90..2476d812f669 100644
--- a/drivers/media/i2c/tvp5150.c
+++ b/drivers/media/i2c/tvp5150.c
@@ -505,80 +505,77 @@ static struct i2c_vbi_ram_value vbi_ram_default[] =
         /* FIXME: Current api doesn't handle all VBI types, those not
            yet supported are placed under #if 0 */
 #if 0
-        {0x010, /* Teletext, SECAM, WST System A */
+        [0] = {0x010, /* Teletext, SECAM, WST System A */
                 {V4L2_SLICED_TELETEXT_SECAM,6,23,1},
                 { 0xaa, 0xaa, 0xff, 0xff, 0xe7, 0x2e, 0x20, 0x26,
                   0xe6, 0xb4, 0x0e, 0x00, 0x00, 0x00, 0x10, 0x00 }
         },
 #endif
-        {0x030, /* Teletext, PAL, WST System B */
+        [1] = {0x030, /* Teletext, PAL, WST System B */
                 {V4L2_SLICED_TELETEXT_B,6,22,1},
                 { 0xaa, 0xaa, 0xff, 0xff, 0x27, 0x2e, 0x20, 0x2b,
                   0xa6, 0x72, 0x10, 0x00, 0x00, 0x00, 0x10, 0x00 }
         },
 #if 0
-        {0x050, /* Teletext, PAL, WST System C */
+        [2] = {0x050, /* Teletext, PAL, WST System C */
                 {V4L2_SLICED_TELETEXT_PAL_C,6,22,1},
                 { 0xaa, 0xaa, 0xff, 0xff, 0xe7, 0x2e, 0x20, 0x22,
                   0xa6, 0x98, 0x0d, 0x00, 0x00, 0x00, 0x10, 0x00 }
         },
-        {0x070, /* Teletext, NTSC, WST System B */
+        [3] = {0x070, /* Teletext, NTSC, WST System B */
                 {V4L2_SLICED_TELETEXT_NTSC_B,10,21,1},
                 { 0xaa, 0xaa, 0xff, 0xff, 0x27, 0x2e, 0x20, 0x23,
                   0x69, 0x93, 0x0d, 0x00, 0x00, 0x00, 0x10, 0x00 }
         },
-        {0x090, /* Tetetext, NTSC NABTS System C */
+        [4] = {0x090, /* Tetetext, NTSC NABTS System C */
                 {V4L2_SLICED_TELETEXT_NTSC_C,10,21,1},
                 { 0xaa, 0xaa, 0xff, 0xff, 0xe7, 0x2e, 0x20, 0x22,
                   0x69, 0x93, 0x0d, 0x00, 0x00, 0x00, 0x15, 0x00 }
         },
-        {0x0b0, /* Teletext, NTSC-J, NABTS System D */
+        [5] = {0x0b0, /* Teletext, NTSC-J, NABTS System D */
                 {V4L2_SLICED_TELETEXT_NTSC_D,10,21,1},
                 { 0xaa, 0xaa, 0xff, 0xff, 0xa7, 0x2e, 0x20, 0x23,
                   0x69, 0x93, 0x0d, 0x00, 0x00, 0x00, 0x10, 0x00 }
         },
-        {0x0d0, /* Closed Caption, PAL/SECAM */
+        [6] = {0x0d0, /* Closed Caption, PAL/SECAM */
                 {V4L2_SLICED_CAPTION_625,22,22,1},
                 { 0xaa, 0x2a, 0xff, 0x3f, 0x04, 0x51, 0x6e, 0x02,
                   0xa6, 0x7b, 0x09, 0x00, 0x00, 0x00, 0x27, 0x00 }
         },
 #endif
-        {0x0f0, /* Closed Caption, NTSC */
+        [7] = {0x0f0, /* Closed Caption, NTSC */
                 {V4L2_SLICED_CAPTION_525,21,21,1},
                 { 0xaa, 0x2a, 0xff, 0x3f, 0x04, 0x51, 0x6e, 0x02,
                   0x69, 0x8c, 0x09, 0x00, 0x00, 0x00, 0x27, 0x00 }
         },
-        {0x110, /* Wide Screen Signal, PAL/SECAM */
+        [8] = {0x110, /* Wide Screen Signal, PAL/SECAM */
                 {V4L2_SLICED_WSS_625,23,23,1},
                 { 0x5b, 0x55, 0xc5, 0xff, 0x00, 0x71, 0x6e, 0x42,
                   0xa6, 0xcd, 0x0f, 0x00, 0x00, 0x00, 0x3a, 0x00 }
         },
 #if 0
-        {0x130, /* Wide Screen Signal, NTSC C */
+        [9] = {0x130, /* Wide Screen Signal, NTSC C */
                 {V4L2_SLICED_WSS_525,20,20,1},
                 { 0x38, 0x00, 0x3f, 0x00, 0x00, 0x71, 0x6e, 0x43,
                   0x69, 0x7c, 0x08, 0x00, 0x00, 0x00, 0x39, 0x00 }
         },
-        {0x150, /* Vertical Interval Timecode (VITC), PAL/SECAM */
+        [10] = {0x150, /* Vertical Interval Timecode (VITC), PAL/SECAM */
                 {V4l2_SLICED_VITC_625,6,22,0},
                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x8f, 0x6d, 0x49,
                   0xa6, 0x85, 0x08, 0x00, 0x00, 0x00, 0x4c, 0x00 }
         },
-        {0x170, /* Vertical Interval Timecode (VITC), NTSC */
+        [11] = {0x170, /* Vertical Interval Timecode (VITC), NTSC */
                 {V4l2_SLICED_VITC_525,10,20,0},
                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x8f, 0x6d, 0x49,
                   0x69, 0x94, 0x08, 0x00, 0x00, 0x00, 0x4c, 0x00 }
         },
 #endif
-        {0x190, /* Video Program System (VPS), PAL */
+        [12] = {0x190, /* Video Program System (VPS), PAL */
                 {V4L2_SLICED_VPS,16,16,0},
                 { 0xaa, 0xaa, 0xff, 0xff, 0xba, 0xce, 0x2b, 0x0d,
                   0xa6, 0xda, 0x0b, 0x00, 0x00, 0x00, 0x60, 0x00 }
         },
         /* 0x1d0 User programmable */
-
-        /* End of struct */
-        { (u16)-1 }
 };
 
 static int tvp5150_write_inittab(struct v4l2_subdev *sd,
@@ -591,10 +588,10 @@ static int tvp5150_write_inittab(struct v4l2_subdev *sd,
         return 0;
 }
 
-static int tvp5150_vdp_init(struct v4l2_subdev *sd,
-                                const struct i2c_vbi_ram_value *regs)
+static int tvp5150_vdp_init(struct v4l2_subdev *sd)
 {
         unsigned int i;
+        int j;
 
         /* Disable Full Field */
         tvp5150_write(sd, TVP5150_FULL_FIELD_ENA, 0);
@@ -604,14 +601,17 @@ static int tvp5150_vdp_init(struct v4l2_subdev *sd,
                 tvp5150_write(sd, i, 0xff);
 
         /* Load Ram Table */
-        while (regs->reg != (u16)-1) {
+        for (j = 0; j < ARRAY_SIZE(vbi_ram_default); j++) {
+                const struct i2c_vbi_ram_value *regs = &vbi_ram_default[j];
+
+                if (!regs->type.vbi_type)
+                        continue;
+
                 tvp5150_write(sd, TVP5150_CONF_RAM_ADDR_HIGH, regs->reg >> 8);
                 tvp5150_write(sd, TVP5150_CONF_RAM_ADDR_LOW, regs->reg);
 
                 for (i = 0; i < 16; i++)
                         tvp5150_write(sd, TVP5150_VDP_CONF_RAM_DATA, regs->values[i]);
-
-                regs++;
         }
         return 0;
 }
@@ -620,19 +620,23 @@ static int tvp5150_vdp_init(struct v4l2_subdev *sd,
 static int tvp5150_g_sliced_vbi_cap(struct v4l2_subdev *sd,
                                 struct v4l2_sliced_vbi_cap *cap)
 {
-        const struct i2c_vbi_ram_value *regs = vbi_ram_default;
-        int line;
+        int line, i;
 
         dev_dbg_lvl(sd->dev, 1, debug, "g_sliced_vbi_cap\n");
         memset(cap, 0, sizeof *cap);
 
-        while (regs->reg != (u16)-1 ) {
-                for (line=regs->type.ini_line;line<=regs->type.end_line;line++) {
+        for (i = 0; i < ARRAY_SIZE(vbi_ram_default); i++) {
+                const struct i2c_vbi_ram_value *regs = &vbi_ram_default[i];
+
+                if (!regs->type.vbi_type)
+                        continue;
+
+                for (line = regs->type.ini_line;
+                     line <= regs->type.end_line;
+                     line++) {
                         cap->service_lines[0][line] |= regs->type.vbi_type;
                 }
                 cap->service_set |= regs->type.vbi_type;
-
-                regs++;
         }
         return 0;
 }
@@ -651,14 +655,13 @@ static int tvp5150_g_sliced_vbi_cap(struct v4l2_subdev *sd,
  *      MSB = field2
  */
 static int tvp5150_set_vbi(struct v4l2_subdev *sd,
-                        const struct i2c_vbi_ram_value *regs,
                         unsigned int type,u8 flags, int line,
                         const int fields)
 {
         struct tvp5150 *decoder = to_tvp5150(sd);
         v4l2_std_id std = decoder->norm;
         u8 reg;
-        int pos = 0;
+        int i, pos = 0;
 
         if (std == V4L2_STD_ALL) {
                 dev_err(sd->dev, "VBI can't be configured without knowing number of lines\n");
@@ -671,19 +674,19 @@ static int tvp5150_set_vbi(struct v4l2_subdev *sd,
         if (line < 6 || line > 27)
                 return 0;
 
-        while (regs->reg != (u16)-1) {
+        for (i = 0; i < ARRAY_SIZE(vbi_ram_default); i++) {
+                const struct i2c_vbi_ram_value *regs =  &vbi_ram_default[i];
+
+                if (!regs->type.vbi_type)
+                        continue;
+
                 if ((type & regs->type.vbi_type) &&
                     (line >= regs->type.ini_line) &&
                     (line <= regs->type.end_line))
                         break;
-
-                regs++;
                 pos++;
         }
 
-        if (regs->reg == (u16)-1)
-                return 0;
-
         type = pos | (flags & 0xf0);
         reg = ((line - 6) << 1) + TVP5150_LINE_MODE_INI;
 
@@ -696,8 +699,7 @@ static int tvp5150_set_vbi(struct v4l2_subdev *sd,
         return type;
 }
 
-static int tvp5150_get_vbi(struct v4l2_subdev *sd,
-                        const struct i2c_vbi_ram_value *regs, int line)
+static int tvp5150_get_vbi(struct v4l2_subdev *sd, int line)
 {
         struct tvp5150 *decoder = to_tvp5150(sd);
         v4l2_std_id std = decoder->norm;
@@ -726,8 +728,8 @@ static int tvp5150_get_vbi(struct v4l2_subdev *sd,
                         return 0;
                 }
                 pos = ret & 0x0f;
-                if (pos < 0x0f)
-                        type |= regs[pos].type.vbi_type;
+                if (pos < ARRAY_SIZE(vbi_ram_default))
+                        type |= vbi_ram_default[pos].type.vbi_type;
         }
 
         return type;
@@ -788,7 +790,7 @@ static int tvp5150_reset(struct v4l2_subdev *sd, u32 val)
         tvp5150_write_inittab(sd, tvp5150_init_default);
 
         /* Initializes VDP registers */
-        tvp5150_vdp_init(sd, vbi_ram_default);
+        tvp5150_vdp_init(sd);
 
         /* Selects decoder input */
         tvp5150_selmux(sd);
@@ -1121,8 +1123,8 @@ static int tvp5150_s_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_f
                 for (i = 0; i <= 23; i++) {
                         svbi->service_lines[1][i] = 0;
                         svbi->service_lines[0][i] =
-                                tvp5150_set_vbi(sd, vbi_ram_default,
-                                       svbi->service_lines[0][i], 0xf0, i, 3);
+                                tvp5150_set_vbi(sd, svbi->service_lines[0][i],
+                                                0xf0, i, 3);
                 }
                 /* Enables FIFO */
                 tvp5150_write(sd, TVP5150_FIFO_OUT_CTRL, 1);
@@ -1148,7 +1150,7 @@ static int tvp5150_g_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_f
 
         for (i = 0; i <= 23; i++) {
                 svbi->service_lines[0][i] =
-                        tvp5150_get_vbi(sd, vbi_ram_default, i);
+                        tvp5150_get_vbi(sd, i);
                 mask |= svbi->service_lines[0][i];
         }
         svbi->service_set = mask;
diff --git a/drivers/media/pci/ttpci/av7110.c b/drivers/media/pci/ttpci/av7110.c
index dc8e577b2f74..d6816effb878 100644
--- a/drivers/media/pci/ttpci/av7110.c
+++ b/drivers/media/pci/ttpci/av7110.c
@@ -324,14 +324,15 @@ static int DvbDmxFilterCallback(u8 *buffer1, size_t buffer1_len,
                 }
                 return dvbdmxfilter->feed->cb.sec(buffer1, buffer1_len,
                                                   buffer2, buffer2_len,
-                                                  &dvbdmxfilter->filter);
+                                                  &dvbdmxfilter->filter, NULL);
         case DMX_TYPE_TS:
                 if (!(dvbdmxfilter->feed->ts_type & TS_PACKET))
                         return 0;
                 if (dvbdmxfilter->feed->ts_type & TS_PAYLOAD_ONLY)
                         return dvbdmxfilter->feed->cb.ts(buffer1, buffer1_len,
                                                          buffer2, buffer2_len,
-                                                         &dvbdmxfilter->feed->feed.ts);
+                                                         &dvbdmxfilter->feed->feed.ts,
+                                                         NULL);
                 else
                         av7110_p2t_write(buffer1, buffer1_len,
                                          dvbdmxfilter->feed->pid,
diff --git a/drivers/media/pci/ttpci/av7110_av.c b/drivers/media/pci/ttpci/av7110_av.c
index 4daba76ec240..ef1bc17cdc4d 100644
--- a/drivers/media/pci/ttpci/av7110_av.c
+++ b/drivers/media/pci/ttpci/av7110_av.c
@@ -99,7 +99,7 @@ int av7110_record_cb(struct dvb_filter_pes2ts *p2t, u8 *buf, size_t len)
                 buf[4] = buf[5] = 0;
         if (dvbdmxfeed->ts_type & TS_PAYLOAD_ONLY)
                 return dvbdmxfeed->cb.ts(buf, len, NULL, 0,
-                                         &dvbdmxfeed->feed.ts);
+                                         &dvbdmxfeed->feed.ts, NULL);
         else
                 return dvb_filter_pes2ts(p2t, buf, len, 1);
 }
@@ -109,7 +109,7 @@ static int dvb_filter_pes2ts_cb(void *priv, unsigned char *data)
         struct dvb_demux_feed *dvbdmxfeed = (struct dvb_demux_feed *) priv;
 
         dvbdmxfeed->cb.ts(data, 188, NULL, 0,
-                          &dvbdmxfeed->feed.ts);
+                          &dvbdmxfeed->feed.ts, NULL);
         return 0;
 }
 
@@ -814,7 +814,7 @@ static void p_to_t(u8 const *buf, long int length, u16 pid, u8 *counter,
                         memcpy(obuf + l, buf + c, TS_SIZE - l);
                         c = length;
                 }
-                feed->cb.ts(obuf, 188, NULL, 0, &feed->feed.ts);
+                feed->cb.ts(obuf, 188, NULL, 0, &feed->feed.ts, NULL);
                 pes_start = 0;
         }
 }
diff --git a/drivers/media/usb/au0828/Kconfig b/drivers/media/usb/au0828/Kconfig
index 70521e0b4c53..bfaa806633df 100644
--- a/drivers/media/usb/au0828/Kconfig
+++ b/drivers/media/usb/au0828/Kconfig
@@ -1,7 +1,7 @@
 
 config VIDEO_AU0828
         tristate "Auvitek AU0828 support"
-        depends on I2C && INPUT && DVB_CORE && USB
+        depends on I2C && INPUT && DVB_CORE && USB && VIDEO_V4L2
         select I2C_ALGOBIT
         select VIDEO_TVEEPROM
         select VIDEOBUF2_VMALLOC
diff --git a/drivers/media/usb/ttusb-dec/ttusb_dec.c b/drivers/media/usb/ttusb-dec/ttusb_dec.c
index a8900f5571f7..44ca66cb9b8f 100644
--- a/drivers/media/usb/ttusb-dec/ttusb_dec.c
+++ b/drivers/media/usb/ttusb-dec/ttusb_dec.c
@@ -428,7 +428,7 @@ static int ttusb_dec_audio_pes2ts_cb(void *priv, unsigned char *data)
         struct ttusb_dec *dec = priv;
 
         dec->audio_filter->feed->cb.ts(data, 188, NULL, 0,
-                                       &dec->audio_filter->feed->feed.ts);
+                                       &dec->audio_filter->feed->feed.ts, NULL);
 
         return 0;
 }
@@ -438,7 +438,7 @@ static int ttusb_dec_video_pes2ts_cb(void *priv, unsigned char *data)
         struct ttusb_dec *dec = priv;
 
         dec->video_filter->feed->cb.ts(data, 188, NULL, 0,
-                                       &dec->video_filter->feed->feed.ts);
+                                       &dec->video_filter->feed->feed.ts, NULL);
 
         return 0;
 }
@@ -490,7 +490,7 @@ static void ttusb_dec_process_pva(struct ttusb_dec *dec, u8 *pva, int length)
 
                 if (output_pva) {
                         dec->video_filter->feed->cb.ts(pva, length, NULL, 0,
-                                &dec->video_filter->feed->feed.ts);
+                                &dec->video_filter->feed->feed.ts, NULL);
                         return;
                 }
 
@@ -551,7 +551,7 @@ static void ttusb_dec_process_pva(struct ttusb_dec *dec, u8 *pva, int length)
         case 0x02:              /* MainAudioStream */
                 if (output_pva) {
                         dec->audio_filter->feed->cb.ts(pva, length, NULL, 0,
-                                &dec->audio_filter->feed->feed.ts);
+                                &dec->audio_filter->feed->feed.ts, NULL);
                         return;
                 }
 
@@ -589,7 +589,7 @@ static void ttusb_dec_process_filter(struct ttusb_dec *dec, u8 *packet,
 
         if (filter)
                 filter->feed->cb.sec(&packet[2], length - 2, NULL, 0,
-                                     &filter->filter);
+                                     &filter->filter, NULL);
 }
 
 static void ttusb_dec_process_packet(struct ttusb_dec *dec)
diff --git a/drivers/media/v4l2-core/Kconfig b/drivers/media/v4l2-core/Kconfig
index bf52fbd07aed..8e37e7c5e0f7 100644
--- a/drivers/media/v4l2-core/Kconfig
+++ b/drivers/media/v4l2-core/Kconfig
@@ -7,6 +7,7 @@ config VIDEO_V4L2
         tristate
         depends on (I2C || I2C=n) && VIDEO_DEV
         select RATIONAL
+        select VIDEOBUF2_V4L2 if VIDEOBUF2_CORE
         default (I2C || I2C=n) && VIDEO_DEV
 
 config VIDEO_ADV_DEBUG
diff --git a/drivers/media/v4l2-core/Makefile b/drivers/media/v4l2-core/Makefile
index 80de2cb9c476..7df54582e956 100644
--- a/drivers/media/v4l2-core/Makefile
+++ b/drivers/media/v4l2-core/Makefile
@@ -13,7 +13,7 @@ ifeq ($(CONFIG_COMPAT),y)
 endif
 obj-$(CONFIG_V4L2_FWNODE) += v4l2-fwnode.o
 ifeq ($(CONFIG_TRACEPOINTS),y)
-  videodev-objs += vb2-trace.o v4l2-trace.o
+  videodev-objs += v4l2-trace.o
 endif
 videodev-$(CONFIG_MEDIA_CONTROLLER) += v4l2-mc.o
 
@@ -35,4 +35,3 @@ obj-$(CONFIG_VIDEOBUF_DVB) += videobuf-dvb.o
 
 ccflags-y += -I$(srctree)/drivers/media/dvb-frontends
 ccflags-y += -I$(srctree)/drivers/media/tuners
-
diff --git a/drivers/memory/brcmstb_dpfe.c b/drivers/memory/brcmstb_dpfe.c
index 0a7bdbed3a6f..e9c1485c32b9 100644
--- a/drivers/memory/brcmstb_dpfe.c
+++ b/drivers/memory/brcmstb_dpfe.c
@@ -45,8 +45,16 @@
 #define REG_TO_DCPU_MBOX        0x10
 #define REG_TO_HOST_MBOX        0x14
 
+/* Macros to process offsets returned by the DCPU */
+#define DRAM_MSG_ADDR_OFFSET    0x0
+#define DRAM_MSG_TYPE_OFFSET    0x1c
+#define DRAM_MSG_ADDR_MASK      ((1UL << DRAM_MSG_TYPE_OFFSET) - 1)
+#define DRAM_MSG_TYPE_MASK      ((1UL << \
+                                 (BITS_PER_LONG - DRAM_MSG_TYPE_OFFSET)) - 1)
+
 /* Message RAM */
-#define DCPU_MSG_RAM(x)         (0x100 + (x) * sizeof(u32))
+#define DCPU_MSG_RAM_START      0x100
+#define DCPU_MSG_RAM(x)         (DCPU_MSG_RAM_START + (x) * sizeof(u32))
 
 /* DRAM Info Offsets & Masks */
 #define DRAM_INFO_INTERVAL      0x0
@@ -255,6 +263,40 @@ static unsigned int get_msg_chksum(const u32 msg[])
         return sum;
 }
 
+static void __iomem *get_msg_ptr(struct private_data *priv, u32 response,
+                                 char *buf, ssize_t *size)
+{
+        unsigned int msg_type;
+        unsigned int offset;
+        void __iomem *ptr = NULL;
+
+        msg_type = (response >> DRAM_MSG_TYPE_OFFSET) & DRAM_MSG_TYPE_MASK;
+        offset = (response >> DRAM_MSG_ADDR_OFFSET) & DRAM_MSG_ADDR_MASK;
+
+        /*
+         * msg_type == 1: the offset is relative to the message RAM
+         * msg_type == 0: the offset is relative to the data RAM (this is the
+         *                previous way of passing data)
+         * msg_type is anything else: there's critical hardware problem
+         */
+        switch (msg_type) {
+        case 1:
+                ptr = priv->regs + DCPU_MSG_RAM_START + offset;
+                break;
+        case 0:
+                ptr = priv->dmem + offset;
+                break;
+        default:
+                dev_emerg(priv->dev, "invalid message reply from DCPU: %#x\n",
+                        response);
+                if (buf && size)
+                        *size = sprintf(buf,
+                                "FATAL: communication error with DCPU\n");
+        }
+
+        return ptr;
+}
+
 static int __send_command(struct private_data *priv, unsigned int cmd,
                           u32 result[])
 {
@@ -507,7 +549,7 @@ static ssize_t show_info(struct device *dev, struct device_attribute *devattr,
 {
         u32 response[MSG_FIELD_MAX];
         unsigned int info;
-        int ret;
+        ssize_t ret;
 
         ret = generic_show(DPFE_CMD_GET_INFO, response, dev, buf);
         if (ret)
@@ -528,18 +570,19 @@ static ssize_t show_refresh(struct device *dev,
         u32 response[MSG_FIELD_MAX];
         void __iomem *info;
         struct private_data *priv;
-        unsigned int offset;
         u8 refresh, sr_abort, ppre, thermal_offs, tuf;
         u32 mr4;
-        int ret;
+        ssize_t ret;
 
         ret = generic_show(DPFE_CMD_GET_REFRESH, response, dev, buf);
         if (ret)
                 return ret;
 
         priv = dev_get_drvdata(dev);
-        offset = response[MSG_ARG0];
-        info = priv->dmem + offset;
+
+        info = get_msg_ptr(priv, response[MSG_ARG0], buf, &ret);
+        if (!info)
+                return ret;
 
         mr4 = readl_relaxed(info + DRAM_INFO_MR4) & DRAM_INFO_MR4_MASK;
 
@@ -561,7 +604,6 @@ static ssize_t store_refresh(struct device *dev, struct device_attribute *attr,
         u32 response[MSG_FIELD_MAX];
         struct private_data *priv;
         void __iomem *info;
-        unsigned int offset;
         unsigned long val;
         int ret;
 
@@ -574,8 +616,10 @@ static ssize_t store_refresh(struct device *dev, struct device_attribute *attr,
         if (ret)
                 return ret;
 
-        offset = response[MSG_ARG0];
-        info = priv->dmem + offset;
+        info = get_msg_ptr(priv, response[MSG_ARG0], NULL, NULL);
+        if (!info)
+                return -EIO;
+
         writel_relaxed(val, info + DRAM_INFO_INTERVAL);
 
         return count;
@@ -587,23 +631,25 @@ static ssize_t show_vendor(struct device *dev, struct device_attribute *devattr,
         u32 response[MSG_FIELD_MAX];
         struct private_data *priv;
         void __iomem *info;
-        unsigned int offset;
-        int ret;
+        ssize_t ret;
 
         ret = generic_show(DPFE_CMD_GET_VENDOR, response, dev, buf);
         if (ret)
                 return ret;
 
-        offset = response[MSG_ARG0];
         priv = dev_get_drvdata(dev);
-        info = priv->dmem + offset;
+
+        info = get_msg_ptr(priv, response[MSG_ARG0], buf, &ret);
+        if (!info)
+                return ret;
 
         return sprintf(buf, "%#x %#x %#x %#x %#x\n",
                        readl_relaxed(info + DRAM_VENDOR_MR5) & DRAM_VENDOR_MASK,
                        readl_relaxed(info + DRAM_VENDOR_MR6) & DRAM_VENDOR_MASK,
                        readl_relaxed(info + DRAM_VENDOR_MR7) & DRAM_VENDOR_MASK,
                        readl_relaxed(info + DRAM_VENDOR_MR8) & DRAM_VENDOR_MASK,
-                       readl_relaxed(info + DRAM_VENDOR_ERROR));
+                       readl_relaxed(info + DRAM_VENDOR_ERROR) &
+                                     DRAM_VENDOR_MASK);
 }
 
 static int brcmstb_dpfe_resume(struct platform_device *pdev)
diff --git a/drivers/message/fusion/mptctl.c b/drivers/message/fusion/mptctl.c
index 8d12017b9893..4470630dd545 100644
--- a/drivers/message/fusion/mptctl.c
+++ b/drivers/message/fusion/mptctl.c
@@ -2687,6 +2687,8 @@ mptctl_hp_targetinfo(unsigned long arg)
                                 __FILE__, __LINE__, iocnum);
                 return -ENODEV;
         }
+        if (karg.hdr.id >= MPT_MAX_FC_DEVICES)
+                return -EINVAL;
         dctlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mptctl_hp_targetinfo called.\n",
             ioc->name));
 
diff --git a/drivers/misc/mei/bus.c b/drivers/misc/mei/bus.c
index 3e5eabdae8d9..772d02922529 100644
--- a/drivers/misc/mei/bus.c
+++ b/drivers/misc/mei/bus.c
@@ -548,12 +548,6 @@ int mei_cldev_disable(struct mei_cl_device *cldev)
                 goto out;
         }
 
-        if (bus->dev_state == MEI_DEV_POWER_DOWN) {
-                dev_dbg(bus->dev, "Device is powering down, don't bother with disconnection\n");
-                err = 0;
-                goto out;
-        }
-
         err = mei_cl_disconnect(cl);
         if (err < 0)
                 dev_err(bus->dev, "Could not disconnect from the ME client\n");
diff --git a/drivers/misc/mei/client.c b/drivers/misc/mei/client.c
index be64969d986a..7e60c1817c31 100644
--- a/drivers/misc/mei/client.c
+++ b/drivers/misc/mei/client.c
@@ -945,6 +945,12 @@ int mei_cl_disconnect(struct mei_cl *cl)
                 return 0;
         }
 
+        if (dev->dev_state == MEI_DEV_POWER_DOWN) {
+                cl_dbg(dev, cl, "Device is powering down, don't bother with disconnection\n");
+                mei_cl_set_disconnected(cl);
+                return 0;
+        }
+
         rets = pm_runtime_get(dev->dev);
         if (rets < 0 && rets != -EINPROGRESS) {
                 pm_runtime_put_noidle(dev->dev);
diff --git a/drivers/misc/mei/hw-me-regs.h b/drivers/misc/mei/hw-me-regs.h
index 0ccccbaf530d..e4b10b2d1a08 100644
--- a/drivers/misc/mei/hw-me-regs.h
+++ b/drivers/misc/mei/hw-me-regs.h
@@ -132,6 +132,11 @@
 #define MEI_DEV_ID_KBP        0xA2BA  /* Kaby Point */
 #define MEI_DEV_ID_KBP_2      0xA2BB  /* Kaby Point 2 */
 
+#define MEI_DEV_ID_CNP_LP     0x9DE0  /* Cannon Point LP */
+#define MEI_DEV_ID_CNP_LP_4   0x9DE4  /* Cannon Point LP 4 (iTouch) */
+#define MEI_DEV_ID_CNP_H      0xA360  /* Cannon Point H */
+#define MEI_DEV_ID_CNP_H_4    0xA364  /* Cannon Point H 4 (iTouch) */
+
 /*
  * MEI HW Section
  */
diff --git a/drivers/misc/mei/pci-me.c b/drivers/misc/mei/pci-me.c
index 4a0ccda4d04b..ea4e152270a3 100644
--- a/drivers/misc/mei/pci-me.c
+++ b/drivers/misc/mei/pci-me.c
@@ -98,6 +98,11 @@ static const struct pci_device_id mei_me_pci_tbl[] = {
         {MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)},
         {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)},
 
+        {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH8_CFG)},
+        {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_4, MEI_ME_PCH8_CFG)},
+        {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH8_CFG)},
+        {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_4, MEI_ME_PCH8_CFG)},
+
         /* required last entry */
         {0, }
 };
diff --git a/drivers/misc/ocxl/file.c b/drivers/misc/ocxl/file.c
index d9aa407db06a..337462e1569f 100644
--- a/drivers/misc/ocxl/file.c
+++ b/drivers/misc/ocxl/file.c
@@ -133,8 +133,10 @@ static long afu_ioctl(struct file *file, unsigned int cmd,
                 if (!rc) {
                         rc = copy_to_user((u64 __user *) args, &irq_offset,
                                         sizeof(irq_offset));
-                        if (rc)
+                        if (rc) {
                                 ocxl_afu_irq_free(ctx, irq_offset);
+                                return -EFAULT;
+                        }
                 }
                 break;
 
@@ -277,7 +279,7 @@ static ssize_t afu_read(struct file *file, char __user *buf, size_t count,
         struct ocxl_context *ctx = file->private_data;
         struct ocxl_kernel_event_header header;
         ssize_t rc;
-        size_t used = 0;
+        ssize_t used = 0;
         DEFINE_WAIT(event_wait);
 
         memset(&header, 0, sizeof(header));
@@ -329,7 +331,7 @@ static ssize_t afu_read(struct file *file, char __user *buf, size_t count,
 
         used += sizeof(header);
 
-        rc = (ssize_t) used;
+        rc = used;
         return rc;
 }
 
diff --git a/drivers/mmc/core/mmc_ops.c b/drivers/mmc/core/mmc_ops.c
index 908e4db03535..42d6aa89a48a 100644
--- a/drivers/mmc/core/mmc_ops.c
+++ b/drivers/mmc/core/mmc_ops.c
@@ -848,7 +848,6 @@ int mmc_interrupt_hpi(struct mmc_card *card)
                 return 1;
         }
 
-        mmc_claim_host(card->host);
         err = mmc_send_status(card, &status);
         if (err) {
                 pr_err("%s: Get card status fail\n", mmc_hostname(card->host));
@@ -890,7 +889,6 @@ int mmc_interrupt_hpi(struct mmc_card *card)
         } while (!err);
 
 out:
-        mmc_release_host(card->host);
         return err;
 }
 
@@ -932,9 +930,7 @@ static int mmc_read_bkops_status(struct mmc_card *card)
         int err;
         u8 *ext_csd;
 
-        mmc_claim_host(card->host);
         err = mmc_get_ext_csd(card, &ext_csd);
-        mmc_release_host(card->host);
         if (err)
                 return err;
 
diff --git a/drivers/mmc/host/bcm2835.c b/drivers/mmc/host/bcm2835.c
index 229dc18f0581..768972af8b85 100644
--- a/drivers/mmc/host/bcm2835.c
+++ b/drivers/mmc/host/bcm2835.c
@@ -1265,7 +1265,8 @@ static int bcm2835_add_host(struct bcm2835_host *host)
         char pio_limit_string[20];
         int ret;
 
-        mmc->f_max = host->max_clk;
+        if (!mmc->f_max || mmc->f_max > host->max_clk)
+                mmc->f_max = host->max_clk;
         mmc->f_min = host->max_clk / SDCDIV_MAX_CDIV;
 
         mmc->max_busy_timeout = ~0 / (mmc->f_max / 1000);
diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index 35026795be28..fa41d9422d57 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -487,6 +487,7 @@ static unsigned long exynos_dwmmc_caps[4] = {
 
 static const struct dw_mci_drv_data exynos_drv_data = {
         .caps                   = exynos_dwmmc_caps,
+        .num_caps               = ARRAY_SIZE(exynos_dwmmc_caps),
         .init                   = dw_mci_exynos_priv_init,
         .set_ios                = dw_mci_exynos_set_ios,
         .parse_dt               = dw_mci_exynos_parse_dt,
diff --git a/drivers/mmc/host/dw_mmc-k3.c b/drivers/mmc/host/dw_mmc-k3.c
index 73fd75c3c824..89cdb3d533bb 100644
--- a/drivers/mmc/host/dw_mmc-k3.c
+++ b/drivers/mmc/host/dw_mmc-k3.c
@@ -135,6 +135,9 @@ static int dw_mci_hi6220_parse_dt(struct dw_mci *host)
         if (priv->ctrl_id < 0)
                 priv->ctrl_id = 0;
 
+        if (priv->ctrl_id >= TIMING_MODE)
+                return -EINVAL;
+
         host->priv = priv;
         return 0;
 }
@@ -207,6 +210,7 @@ static int dw_mci_hi6220_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
 
 static const struct dw_mci_drv_data hi6220_data = {
         .caps                   = dw_mci_hi6220_caps,
+        .num_caps               = ARRAY_SIZE(dw_mci_hi6220_caps),
         .switch_voltage         = dw_mci_hi6220_switch_voltage,
         .set_ios                = dw_mci_hi6220_set_ios,
         .parse_dt               = dw_mci_hi6220_parse_dt,
diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c
index a3f1c2b30145..339295212935 100644
--- a/drivers/mmc/host/dw_mmc-rockchip.c
+++ b/drivers/mmc/host/dw_mmc-rockchip.c
@@ -319,6 +319,7 @@ static const struct dw_mci_drv_data rk2928_drv_data = {
 
 static const struct dw_mci_drv_data rk3288_drv_data = {
         .caps                   = dw_mci_rk3288_dwmmc_caps,
+        .num_caps               = ARRAY_SIZE(dw_mci_rk3288_dwmmc_caps),
         .set_ios                = dw_mci_rk3288_set_ios,
         .execute_tuning         = dw_mci_rk3288_execute_tuning,
         .parse_dt               = dw_mci_rk3288_parse_dt,
diff --git a/drivers/mmc/host/dw_mmc-zx.c b/drivers/mmc/host/dw_mmc-zx.c
index d38e94ae2b85..c06b5393312f 100644
--- a/drivers/mmc/host/dw_mmc-zx.c
+++ b/drivers/mmc/host/dw_mmc-zx.c
@@ -195,6 +195,7 @@ static unsigned long zx_dwmmc_caps[3] = {
 
 static const struct dw_mci_drv_data zx_drv_data = {
         .caps                   = zx_dwmmc_caps,
+        .num_caps               = ARRAY_SIZE(zx_dwmmc_caps),
         .execute_tuning         = dw_mci_zx_execute_tuning,
         .prepare_hs400_tuning   = dw_mci_zx_prepare_hs400_tuning,
         .parse_dt               = dw_mci_zx_parse_dt,
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 0aa39975f33b..d9b4acefed31 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -165,6 +165,8 @@ static int dw_mci_regs_show(struct seq_file *s, void *v)
 {
         struct dw_mci *host = s->private;
 
+        pm_runtime_get_sync(host->dev);
+
         seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS));
         seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS));
         seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD));
@@ -172,6 +174,8 @@ static int dw_mci_regs_show(struct seq_file *s, void *v)
         seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK));
         seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA));
 
+        pm_runtime_put_autosuspend(host->dev);
+
         return 0;
 }
 
@@ -2778,12 +2782,57 @@ static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
         return IRQ_HANDLED;
 }
 
+static int dw_mci_init_slot_caps(struct dw_mci_slot *slot)
+{
+        struct dw_mci *host = slot->host;
+        const struct dw_mci_drv_data *drv_data = host->drv_data;
+        struct mmc_host *mmc = slot->mmc;
+        int ctrl_id;
+
+        if (host->pdata->caps)
+                mmc->caps = host->pdata->caps;
+
+        /*
+         * Support MMC_CAP_ERASE by default.
+         * It needs to use trim/discard/erase commands.
+         */
+        mmc->caps |= MMC_CAP_ERASE;
+
+        if (host->pdata->pm_caps)
+                mmc->pm_caps = host->pdata->pm_caps;
+
+        if (host->dev->of_node) {
+                ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
+                if (ctrl_id < 0)
+                        ctrl_id = 0;
+        } else {
+                ctrl_id = to_platform_device(host->dev)->id;
+        }
+
+        if (drv_data && drv_data->caps) {
+                if (ctrl_id >= drv_data->num_caps) {
+                        dev_err(host->dev, "invalid controller id %d\n",
+                                ctrl_id);
+                        return -EINVAL;
+                }
+                mmc->caps |= drv_data->caps[ctrl_id];
+        }
+
+        if (host->pdata->caps2)
+                mmc->caps2 = host->pdata->caps2;
+
+        /* Process SDIO IRQs through the sdio_irq_work. */
+        if (mmc->caps & MMC_CAP_SDIO_IRQ)
+                mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
+
+        return 0;
+}
+
 static int dw_mci_init_slot(struct dw_mci *host)
 {
         struct mmc_host *mmc;
         struct dw_mci_slot *slot;
-        const struct dw_mci_drv_data *drv_data = host->drv_data;
-        int ctrl_id, ret;
+        int ret;
         u32 freq[2];
 
         mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
@@ -2817,38 +2866,13 @@ static int dw_mci_init_slot(struct dw_mci *host)
         if (!mmc->ocr_avail)
                 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
 
-        if (host->pdata->caps)
-                mmc->caps = host->pdata->caps;
-
-        /*
-         * Support MMC_CAP_ERASE by default.
-         * It needs to use trim/discard/erase commands.
-         */
-        mmc->caps |= MMC_CAP_ERASE;
-
-        if (host->pdata->pm_caps)
-                mmc->pm_caps = host->pdata->pm_caps;
-
-        if (host->dev->of_node) {
-                ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
-                if (ctrl_id < 0)
-                        ctrl_id = 0;
-        } else {
-                ctrl_id = to_platform_device(host->dev)->id;
-        }
-        if (drv_data && drv_data->caps)
-                mmc->caps |= drv_data->caps[ctrl_id];
-
-        if (host->pdata->caps2)
-                mmc->caps2 = host->pdata->caps2;
-
         ret = mmc_of_parse(mmc);
         if (ret)
                 goto err_host_allocated;
 
-        /* Process SDIO IRQs through the sdio_irq_work. */
-        if (mmc->caps & MMC_CAP_SDIO_IRQ)
-                mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
+        ret = dw_mci_init_slot_caps(slot);
+        if (ret)
+                goto err_host_allocated;
 
         /* Useful defaults if platform data is unset. */
         if (host->use_dma == TRANS_MODE_IDMAC) {
diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h
index e3124f06a47e..1424bd490dd1 100644
--- a/drivers/mmc/host/dw_mmc.h
+++ b/drivers/mmc/host/dw_mmc.h
@@ -543,6 +543,7 @@ struct dw_mci_slot {
 /**
  * dw_mci driver data - dw-mshc implementation specific driver data.
  * @caps: mmc subsystem specified capabilities of the controller(s).
+ * @num_caps: number of capabilities specified by @caps.
  * @init: early implementation specific initialization.
  * @set_ios: handle bus specific extensions.
  * @parse_dt: parse implementation specific device tree properties.
@@ -554,6 +555,7 @@ struct dw_mci_slot {
  */
 struct dw_mci_drv_data {
         unsigned long   *caps;
+        u32             num_caps;
         int             (*init)(struct dw_mci *host);
         void            (*set_ios)(struct dw_mci *host, struct mmc_ios *ios);
         int             (*parse_dt)(struct dw_mci *host);
diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
index 22438ebfe4e6..4f972b879fe6 100644
--- a/drivers/mmc/host/meson-gx-mmc.c
+++ b/drivers/mmc/host/meson-gx-mmc.c
@@ -717,22 +717,6 @@ static int meson_mmc_clk_phase_tuning(struct mmc_host *mmc, u32 opcode,
 static int meson_mmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
 {
         struct meson_host *host = mmc_priv(mmc);
-        int ret;
-
-        /*
-         * If this is the initial tuning, try to get a sane Rx starting
-         * phase before doing the actual tuning.
-         */
-        if (!mmc->doing_retune) {
-                ret = meson_mmc_clk_phase_tuning(mmc, opcode, host->rx_clk);
-
-                if (ret)
-                        return ret;
-        }
-
-        ret = meson_mmc_clk_phase_tuning(mmc, opcode, host->tx_clk);
-        if (ret)
-                return ret;
 
         return meson_mmc_clk_phase_tuning(mmc, opcode, host->rx_clk);
 }
@@ -763,9 +747,8 @@ static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
                 if (!IS_ERR(mmc->supply.vmmc))
                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
 
-                /* Reset phases */
+                /* Reset rx phase */
                 clk_set_phase(host->rx_clk, 0);
-                clk_set_phase(host->tx_clk, 270);
 
                 break;
 
diff --git a/drivers/mmc/host/sdhci-pci-core.c b/drivers/mmc/host/sdhci-pci-core.c
index 6d1a983e6227..82c4f05f91d8 100644
--- a/drivers/mmc/host/sdhci-pci-core.c
+++ b/drivers/mmc/host/sdhci-pci-core.c
@@ -654,9 +654,36 @@ static void byt_read_dsm(struct sdhci_pci_slot *slot)
         slot->chip->rpm_retune = intel_host->d3_retune;
 }
 
-static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
+static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode)
+{
+        int err = sdhci_execute_tuning(mmc, opcode);
+        struct sdhci_host *host = mmc_priv(mmc);
+
+        if (err)
+                return err;
+
+        /*
+         * Tuning can leave the IP in an active state (Buffer Read Enable bit
+         * set) which prevents the entry to low power states (i.e. S0i3). Data
+         * reset will clear it.
+         */
+        sdhci_reset(host, SDHCI_RESET_DATA);
+
+        return 0;
+}
+
+static void byt_probe_slot(struct sdhci_pci_slot *slot)
 {
+        struct mmc_host_ops *ops = &slot->host->mmc_host_ops;
+
         byt_read_dsm(slot);
+
+        ops->execute_tuning = intel_execute_tuning;
+}
+
+static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
+{
+        byt_probe_slot(slot);
         slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
                                  MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
                                  MMC_CAP_CMD_DURING_TFR |
@@ -779,7 +806,7 @@ static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
 {
         int err;
 
-        byt_read_dsm(slot);
+        byt_probe_slot(slot);
 
         err = ni_set_max_freq(slot);
         if (err)
@@ -792,7 +819,7 @@ static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
 
 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
 {
-        byt_read_dsm(slot);
+        byt_probe_slot(slot);
         slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
                                  MMC_CAP_WAIT_WHILE_BUSY;
         return 0;
@@ -800,7 +827,7 @@ static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
 
 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
 {
-        byt_read_dsm(slot);
+        byt_probe_slot(slot);
         slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY |
                                  MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE;
         slot->cd_idx = 0;
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index e6b8c59f2c0d..736ac887303c 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -328,7 +328,7 @@ config MTD_NAND_MARVELL
         tristate "NAND controller support on Marvell boards"
         depends on PXA3xx || ARCH_MMP || PLAT_ORION || ARCH_MVEBU || \
                    COMPILE_TEST
-        depends on HAS_IOMEM
+        depends on HAS_IOMEM && HAS_DMA
         help
           This enables the NAND flash controller driver for Marvell boards,
           including:
diff --git a/drivers/mtd/nand/vf610_nfc.c b/drivers/mtd/nand/vf610_nfc.c
index 80d31a58e558..f367144f3c6f 100644
--- a/drivers/mtd/nand/vf610_nfc.c
+++ b/drivers/mtd/nand/vf610_nfc.c
@@ -752,10 +752,8 @@ static int vf610_nfc_probe(struct platform_device *pdev)
                 if (mtd->oobsize > 64)
                         mtd->oobsize = 64;
 
-                /*
-                 * mtd->ecclayout is not specified here because we're using the
-                 * default large page ECC layout defined in NAND core.
-                 */
+                /* Use default large page ECC layout defined in NAND core */
+                mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
                 if (chip->ecc.strength == 32) {
                         nfc->ecc_mode = ECC_60_BYTE;
                         chip->ecc.bytes = 60;
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-pci.c b/drivers/net/ethernet/amd/xgbe/xgbe-pci.c
index 3e5833cf1fab..eb23f9ba1a9a 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-pci.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-pci.c
@@ -426,6 +426,8 @@ static int xgbe_pci_resume(struct pci_dev *pdev)
         struct net_device *netdev = pdata->netdev;
         int ret = 0;
 
+        XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff);
+
         pdata->lpm_ctrl &= ~MDIO_CTRL1_LPOWER;
         XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, pdata->lpm_ctrl);
 
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_pci_func.c b/drivers/net/ethernet/aquantia/atlantic/aq_pci_func.c
index 22889fc158f2..87c4308b52a7 100644
--- a/drivers/net/ethernet/aquantia/atlantic/aq_pci_func.c
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_pci_func.c
@@ -226,6 +226,10 @@ static int aq_pci_probe(struct pci_dev *pdev,
                 goto err_ioremap;
 
         self->aq_hw = kzalloc(sizeof(*self->aq_hw), GFP_KERNEL);
+        if (!self->aq_hw) {
+                err = -ENOMEM;
+                goto err_ioremap;
+        }
         self->aq_hw->aq_nic_cfg = aq_nic_get_cfg(self);
 
         for (bar = 0; bar < 4; ++bar) {
@@ -235,19 +239,19 @@ static int aq_pci_probe(struct pci_dev *pdev,
                         mmio_pa = pci_resource_start(pdev, bar);
                         if (mmio_pa == 0U) {
                                 err = -EIO;
-                                goto err_ioremap;
+                                goto err_free_aq_hw;
                         }
 
                         reg_sz = pci_resource_len(pdev, bar);
                         if ((reg_sz <= 24 /*ATL_REGS_SIZE*/)) {
                                 err = -EIO;
-                                goto err_ioremap;
+                                goto err_free_aq_hw;
                         }
 
                         self->aq_hw->mmio = ioremap_nocache(mmio_pa, reg_sz);
                         if (!self->aq_hw->mmio) {
                                 err = -EIO;
-                                goto err_ioremap;
+                                goto err_free_aq_hw;
                         }
                         break;
                 }
@@ -255,7 +259,7 @@ static int aq_pci_probe(struct pci_dev *pdev,
 
         if (bar == 4) {
                 err = -EIO;
-                goto err_ioremap;
+                goto err_free_aq_hw;
         }
 
         numvecs = min((u8)AQ_CFG_VECS_DEF,
@@ -290,6 +294,8 @@ err_register:
         aq_pci_free_irq_vectors(self);
 err_hwinit:
         iounmap(self->aq_hw->mmio);
+err_free_aq_hw:
+        kfree(self->aq_hw);
 err_ioremap:
         free_netdev(ndev);
 err_pci_func:
diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c
index a77ee2f8fb8d..c1841db1b500 100644
--- a/drivers/net/ethernet/broadcom/tg3.c
+++ b/drivers/net/ethernet/broadcom/tg3.c
@@ -820,7 +820,7 @@ static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
 
                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
 
-                udelay(10);
+                usleep_range(10, 20);
                 timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
         }
 
@@ -922,8 +922,8 @@ static int tg3_ape_send_event(struct tg3 *tp, u32 event)
         if (!(apedata & APE_FW_STATUS_READY))
                 return -EAGAIN;
 
-        /* Wait for up to 1 millisecond for APE to service previous event. */
-        err = tg3_ape_event_lock(tp, 1000);
+        /* Wait for up to 20 millisecond for APE to service previous event. */
+        err = tg3_ape_event_lock(tp, 20000);
         if (err)
                 return err;
 
@@ -946,6 +946,7 @@ static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
 
         switch (kind) {
         case RESET_KIND_INIT:
+                tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++);
                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
                                 APE_HOST_SEG_SIG_MAGIC);
                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
@@ -962,13 +963,6 @@ static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
                 event = APE_EVENT_STATUS_STATE_START;
                 break;
         case RESET_KIND_SHUTDOWN:
-                /* With the interface we are currently using,
-                 * APE does not track driver state.  Wiping
-                 * out the HOST SEGMENT SIGNATURE forces
-                 * the APE to assume OS absent status.
-                 */
-                tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
-
                 if (device_may_wakeup(&tp->pdev->dev) &&
                     tg3_flag(tp, WOL_ENABLE)) {
                         tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
@@ -990,6 +984,18 @@ static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
         tg3_ape_send_event(tp, event);
 }
 
+static void tg3_send_ape_heartbeat(struct tg3 *tp,
+                                   unsigned long interval)
+{
+        /* Check if hb interval has exceeded */
+        if (!tg3_flag(tp, ENABLE_APE) ||
+            time_before(jiffies, tp->ape_hb_jiffies + interval))
+                return;
+
+        tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++);
+        tp->ape_hb_jiffies = jiffies;
+}
+
 static void tg3_disable_ints(struct tg3 *tp)
 {
         int i;
@@ -7262,6 +7268,7 @@ static int tg3_poll_msix(struct napi_struct *napi, int budget)
                 }
         }
 
+        tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL << 1);
         return work_done;
 
 tx_recovery:
@@ -7344,6 +7351,7 @@ static int tg3_poll(struct napi_struct *napi, int budget)
                 }
         }
 
+        tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL << 1);
         return work_done;
 
 tx_recovery:
@@ -10732,7 +10740,7 @@ static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
         if (tg3_flag(tp, ENABLE_APE))
                 /* Write our heartbeat update interval to APE. */
                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
-                                APE_HOST_HEARTBEAT_INT_DISABLE);
+                                APE_HOST_HEARTBEAT_INT_5SEC);
 
         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
 
@@ -11077,6 +11085,9 @@ static void tg3_timer(struct timer_list *t)
                 tp->asf_counter = tp->asf_multiplier;
         }
 
+        /* Update the APE heartbeat every 5 seconds.*/
+        tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL);
+
         spin_unlock(&tp->lock);
 
 restart_timer:
@@ -16653,6 +16664,8 @@ static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent)
                                        pci_state_reg);
 
                 tg3_ape_lock_init(tp);
+                tp->ape_hb_interval =
+                        msecs_to_jiffies(APE_HOST_HEARTBEAT_INT_5SEC);
         }
 
         /* Set up tp->grc_local_ctrl before calling
diff --git a/drivers/net/ethernet/broadcom/tg3.h b/drivers/net/ethernet/broadcom/tg3.h
index 47f51cc0566d..1d61aa3efda1 100644
--- a/drivers/net/ethernet/broadcom/tg3.h
+++ b/drivers/net/ethernet/broadcom/tg3.h
@@ -2508,6 +2508,7 @@
 #define TG3_APE_LOCK_PHY3               5
 #define TG3_APE_LOCK_GPIO               7
 
+#define TG3_APE_HB_INTERVAL             (tp->ape_hb_interval)
 #define TG3_EEPROM_SB_F1R2_MBA_OFF      0x10
 
 
@@ -3423,6 +3424,10 @@ struct tg3 {
         struct device                   *hwmon_dev;
         bool                            link_up;
         bool                            pcierr_recovery;
+
+        u32                             ape_hb;
+        unsigned long                   ape_hb_interval;
+        unsigned long                   ape_hb_jiffies;
 };
 
 /* Accessor macros for chip and asic attributes
diff --git a/drivers/net/ethernet/cavium/common/cavium_ptp.c b/drivers/net/ethernet/cavium/common/cavium_ptp.c
index c87c9c684a33..d59497a7bdce 100644
--- a/drivers/net/ethernet/cavium/common/cavium_ptp.c
+++ b/drivers/net/ethernet/cavium/common/cavium_ptp.c
@@ -75,6 +75,8 @@ EXPORT_SYMBOL(cavium_ptp_get);
 
 void cavium_ptp_put(struct cavium_ptp *ptp)
 {
+        if (!ptp)
+                return;
         pci_dev_put(ptp->pdev);
 }
 EXPORT_SYMBOL(cavium_ptp_put);
diff --git a/drivers/net/ethernet/cavium/thunder/nicvf_main.c b/drivers/net/ethernet/cavium/thunder/nicvf_main.c
index b68cde9f17d2..7d9c5ffbd041 100644
--- a/drivers/net/ethernet/cavium/thunder/nicvf_main.c
+++ b/drivers/net/ethernet/cavium/thunder/nicvf_main.c
@@ -67,11 +67,6 @@ module_param(cpi_alg, int, S_IRUGO);
 MODULE_PARM_DESC(cpi_alg,
                  "PFC algorithm (0=none, 1=VLAN, 2=VLAN16, 3=IP Diffserv)");
 
-struct nicvf_xdp_tx {
-        u64 dma_addr;
-        u8  qidx;
-};
-
 static inline u8 nicvf_netdev_qidx(struct nicvf *nic, u8 qidx)
 {
         if (nic->sqs_mode)
@@ -507,29 +502,14 @@ static int nicvf_init_resources(struct nicvf *nic)
         return 0;
 }
 
-static void nicvf_unmap_page(struct nicvf *nic, struct page *page, u64 dma_addr)
-{
-        /* Check if it's a recycled page, if not unmap the DMA mapping.
-         * Recycled page holds an extra reference.
-         */
-        if (page_ref_count(page) == 1) {
-                dma_addr &= PAGE_MASK;
-                dma_unmap_page_attrs(&nic->pdev->dev, dma_addr,
-                                     RCV_FRAG_LEN + XDP_HEADROOM,
-                                     DMA_FROM_DEVICE,
-                                     DMA_ATTR_SKIP_CPU_SYNC);
-        }
-}
-
 static inline bool nicvf_xdp_rx(struct nicvf *nic, struct bpf_prog *prog,
                                 struct cqe_rx_t *cqe_rx, struct snd_queue *sq,
                                 struct rcv_queue *rq, struct sk_buff **skb)
 {
         struct xdp_buff xdp;
         struct page *page;
-        struct nicvf_xdp_tx *xdp_tx = NULL;
         u32 action;
-        u16 len, err, offset = 0;
+        u16 len, offset = 0;
         u64 dma_addr, cpu_addr;
         void *orig_data;
 
@@ -543,7 +523,7 @@ static inline bool nicvf_xdp_rx(struct nicvf *nic, struct bpf_prog *prog,
         cpu_addr = (u64)phys_to_virt(cpu_addr);
         page = virt_to_page((void *)cpu_addr);
 
-        xdp.data_hard_start = page_address(page) + RCV_BUF_HEADROOM;
+        xdp.data_hard_start = page_address(page);
         xdp.data = (void *)cpu_addr;
         xdp_set_data_meta_invalid(&xdp);
         xdp.data_end = xdp.data + len;
@@ -563,7 +543,18 @@ static inline bool nicvf_xdp_rx(struct nicvf *nic, struct bpf_prog *prog,
 
         switch (action) {
         case XDP_PASS:
-                nicvf_unmap_page(nic, page, dma_addr);
+                /* Check if it's a recycled page, if not
+                 * unmap the DMA mapping.
+                 *
+                 * Recycled page holds an extra reference.
+                 */
+                if (page_ref_count(page) == 1) {
+                        dma_addr &= PAGE_MASK;
+                        dma_unmap_page_attrs(&nic->pdev->dev, dma_addr,
+                                             RCV_FRAG_LEN + XDP_PACKET_HEADROOM,
+                                             DMA_FROM_DEVICE,
+                                             DMA_ATTR_SKIP_CPU_SYNC);
+                }
 
                 /* Build SKB and pass on packet to network stack */
                 *skb = build_skb(xdp.data,
@@ -576,20 +567,6 @@ static inline bool nicvf_xdp_rx(struct nicvf *nic, struct bpf_prog *prog,
         case XDP_TX:
                 nicvf_xdp_sq_append_pkt(nic, sq, (u64)xdp.data, dma_addr, len);
                 return true;
-        case XDP_REDIRECT:
-                /* Save DMA address for use while transmitting */
-                xdp_tx = (struct nicvf_xdp_tx *)page_address(page);
-                xdp_tx->dma_addr = dma_addr;
-                xdp_tx->qidx = nicvf_netdev_qidx(nic, cqe_rx->rq_idx);
-
-                err = xdp_do_redirect(nic->pnicvf->netdev, &xdp, prog);
-                if (!err)
-                        return true;
-
-                /* Free the page on error */
-                nicvf_unmap_page(nic, page, dma_addr);
-                put_page(page);
-                break;
         default:
                 bpf_warn_invalid_xdp_action(action);
                 /* fall through */
@@ -597,7 +574,18 @@ static inline bool nicvf_xdp_rx(struct nicvf *nic, struct bpf_prog *prog,
                 trace_xdp_exception(nic->netdev, prog, action);
                 /* fall through */
         case XDP_DROP:
-                nicvf_unmap_page(nic, page, dma_addr);
+                /* Check if it's a recycled page, if not
+                 * unmap the DMA mapping.
+                 *
+                 * Recycled page holds an extra reference.
+                 */
+                if (page_ref_count(page) == 1) {
+                        dma_addr &= PAGE_MASK;
+                        dma_unmap_page_attrs(&nic->pdev->dev, dma_addr,
+                                             RCV_FRAG_LEN + XDP_PACKET_HEADROOM,
+                                             DMA_FROM_DEVICE,
+                                             DMA_ATTR_SKIP_CPU_SYNC);
+                }
                 put_page(page);
                 return true;
         }
@@ -1864,50 +1852,6 @@ static int nicvf_xdp(struct net_device *netdev, struct netdev_bpf *xdp)
         }
 }
 
-static int nicvf_xdp_xmit(struct net_device *netdev, struct xdp_buff *xdp)
-{
-        struct nicvf *nic = netdev_priv(netdev);
-        struct nicvf *snic = nic;
-        struct nicvf_xdp_tx *xdp_tx;
-        struct snd_queue *sq;
-        struct page *page;
-        int err, qidx;
-
-        if (!netif_running(netdev) || !nic->xdp_prog)
-                return -EINVAL;
-
-        page = virt_to_page(xdp->data);
-        xdp_tx = (struct nicvf_xdp_tx *)page_address(page);
-        qidx = xdp_tx->qidx;
-
-        if (xdp_tx->qidx >= nic->xdp_tx_queues)
-                return -EINVAL;
-
-        /* Get secondary Qset's info */
-        if (xdp_tx->qidx >= MAX_SND_QUEUES_PER_QS) {
-                qidx = xdp_tx->qidx / MAX_SND_QUEUES_PER_QS;
-                snic = (struct nicvf *)nic->snicvf[qidx - 1];
-                if (!snic)
-                        return -EINVAL;
-                qidx = xdp_tx->qidx % MAX_SND_QUEUES_PER_QS;
-        }
-
-        sq = &snic->qs->sq[qidx];
-        err = nicvf_xdp_sq_append_pkt(snic, sq, (u64)xdp->data,
-                                      xdp_tx->dma_addr,
-                                      xdp->data_end - xdp->data);
-        if (err)
-                return -ENOMEM;
-
-        nicvf_xdp_sq_doorbell(snic, sq, qidx);
-        return 0;
-}
-
-static void nicvf_xdp_flush(struct net_device *dev)
-{
-        return;
-}
-
 static int nicvf_config_hwtstamp(struct net_device *netdev, struct ifreq *ifr)
 {
         struct hwtstamp_config config;
@@ -1986,8 +1930,6 @@ static const struct net_device_ops nicvf_netdev_ops = {
         .ndo_fix_features       = nicvf_fix_features,
         .ndo_set_features       = nicvf_set_features,
         .ndo_bpf                = nicvf_xdp,
-        .ndo_xdp_xmit           = nicvf_xdp_xmit,
-        .ndo_xdp_flush          = nicvf_xdp_flush,
         .ndo_do_ioctl           = nicvf_ioctl,
 };
 
diff --git a/drivers/net/ethernet/cavium/thunder/nicvf_queues.c b/drivers/net/ethernet/cavium/thunder/nicvf_queues.c
index 3eae9ff9b53a..d42704d07484 100644
--- a/drivers/net/ethernet/cavium/thunder/nicvf_queues.c
+++ b/drivers/net/ethernet/cavium/thunder/nicvf_queues.c
@@ -204,7 +204,7 @@ static inline int nicvf_alloc_rcv_buffer(struct nicvf *nic, struct rbdr *rbdr,
 
         /* Reserve space for header modifications by BPF program */
         if (rbdr->is_xdp)
-                buf_len += XDP_HEADROOM;
+                buf_len += XDP_PACKET_HEADROOM;
 
         /* Check if it's recycled */
         if (pgcache)
@@ -224,9 +224,8 @@ ret:
                         nic->rb_page = NULL;
                         return -ENOMEM;
                 }
-
                 if (pgcache)
-                        pgcache->dma_addr = *rbuf + XDP_HEADROOM;
+                        pgcache->dma_addr = *rbuf + XDP_PACKET_HEADROOM;
                 nic->rb_page_offset += buf_len;
         }
 
@@ -1244,7 +1243,7 @@ int nicvf_xdp_sq_append_pkt(struct nicvf *nic, struct snd_queue *sq,
         int qentry;
 
         if (subdesc_cnt > sq->xdp_free_cnt)
-                return -1;
+                return 0;
 
         qentry = nicvf_get_sq_desc(sq, subdesc_cnt);
 
@@ -1255,7 +1254,7 @@ int nicvf_xdp_sq_append_pkt(struct nicvf *nic, struct snd_queue *sq,
 
         sq->xdp_desc_cnt += subdesc_cnt;
 
-        return 0;
+        return 1;
 }
 
 /* Calculate no of SQ subdescriptors needed to transmit all
@@ -1656,7 +1655,7 @@ static void nicvf_unmap_rcv_buffer(struct nicvf *nic, u64 dma_addr,
                 if (page_ref_count(page) != 1)
                         return;
 
-                len += XDP_HEADROOM;
+                len += XDP_PACKET_HEADROOM;
                 /* Receive buffers in XDP mode are mapped from page start */
                 dma_addr &= PAGE_MASK;
         }
diff --git a/drivers/net/ethernet/cavium/thunder/nicvf_queues.h b/drivers/net/ethernet/cavium/thunder/nicvf_queues.h
index ce1eed7a6d63..5e9a03cf1b4d 100644
--- a/drivers/net/ethernet/cavium/thunder/nicvf_queues.h
+++ b/drivers/net/ethernet/cavium/thunder/nicvf_queues.h
@@ -11,7 +11,6 @@
 
 #include <linux/netdevice.h>
 #include <linux/iommu.h>
-#include <linux/bpf.h>
 #include <net/xdp.h>
 #include "q_struct.h"
 
@@ -94,9 +93,6 @@
 #define RCV_FRAG_LEN     (SKB_DATA_ALIGN(DMA_BUFFER_LEN + NET_SKB_PAD) + \
                          SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
 
-#define RCV_BUF_HEADROOM        128 /* To store dma address for XDP redirect */
-#define XDP_HEADROOM            (XDP_PACKET_HEADROOM + RCV_BUF_HEADROOM)
-
 #define MAX_CQES_FOR_TX         ((SND_QUEUE_LEN / MIN_SQ_DESC_PER_PKT_XMIT) * \
                                  MAX_CQE_PER_PKT_XMIT)
 
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c b/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c
index 557fd8bfd54e..00a1d2d13169 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c
@@ -472,7 +472,7 @@ int cudbg_collect_cim_la(struct cudbg_init *pdbg_init,
 
         if (is_t6(padap->params.chip)) {
                 size = padap->params.cim_la_size / 10 + 1;
-                size *= 11 * sizeof(u32);
+                size *= 10 * sizeof(u32);
         } else {
                 size = padap->params.cim_la_size / 8;
                 size *= 8 * sizeof(u32);
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_cudbg.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_cudbg.c
index 30485f9a598f..143686c60234 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_cudbg.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_cudbg.c
@@ -102,7 +102,7 @@ static u32 cxgb4_get_entity_length(struct adapter *adap, u32 entity)
         case CUDBG_CIM_LA:
                 if (is_t6(adap->params.chip)) {
                         len = adap->params.cim_la_size / 10 + 1;
-                        len *= 11 * sizeof(u32);
+                        len *= 10 * sizeof(u32);
                 } else {
                         len = adap->params.cim_la_size / 8;
                         len *= 8 * sizeof(u32);
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
index 56bc626ef006..7b452e85de2a 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
@@ -4982,9 +4982,10 @@ static int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs)
 
         pcie_fw = readl(adap->regs + PCIE_FW_A);
         /* Check if cxgb4 is the MASTER and fw is initialized */
-        if (!(pcie_fw & PCIE_FW_INIT_F) ||
+        if (num_vfs &&
+            (!(pcie_fw & PCIE_FW_INIT_F) ||
             !(pcie_fw & PCIE_FW_MASTER_VLD_F) ||
-            PCIE_FW_MASTER_G(pcie_fw) != CXGB4_UNIFIED_PF) {
+            PCIE_FW_MASTER_G(pcie_fw) != CXGB4_UNIFIED_PF)) {
                 dev_warn(&pdev->dev,
                          "cxgb4 driver needs to be MASTER to support SRIOV\n");
                 return -EOPNOTSUPP;
@@ -5599,24 +5600,24 @@ static void remove_one(struct pci_dev *pdev)
 #if IS_ENABLED(CONFIG_IPV6)
                 t4_cleanup_clip_tbl(adapter);
 #endif
-                iounmap(adapter->regs);
                 if (!is_t4(adapter->params.chip))
                         iounmap(adapter->bar2);
-                pci_disable_pcie_error_reporting(pdev);
-                if ((adapter->flags & DEV_ENABLED)) {
-                        pci_disable_device(pdev);
-                        adapter->flags &= ~DEV_ENABLED;
-                }
-                pci_release_regions(pdev);
-                kfree(adapter->mbox_log);
-                synchronize_rcu();
-                kfree(adapter);
         }
 #ifdef CONFIG_PCI_IOV
         else {
                 cxgb4_iov_configure(adapter->pdev, 0);
         }
 #endif
+        iounmap(adapter->regs);
+        pci_disable_pcie_error_reporting(pdev);
+        if ((adapter->flags & DEV_ENABLED)) {
+                pci_disable_device(pdev);
+                adapter->flags &= ~DEV_ENABLED;
+        }
+        pci_release_regions(pdev);
+        kfree(adapter->mbox_log);
+        synchronize_rcu();
+        kfree(adapter);
 }
 
 /* "Shutdown" quiesces the device, stopping Ingress Packet and Interrupt
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
index 047609ef0515..920bccd6bc40 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
@@ -2637,7 +2637,6 @@ void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
 }
 
 #define EEPROM_STAT_ADDR   0x7bfc
-#define VPD_SIZE           0x800
 #define VPD_BASE           0x400
 #define VPD_BASE_OLD       0
 #define VPD_LEN            1024
@@ -2704,15 +2703,6 @@ int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p)
         if (!vpd)
                 return -ENOMEM;
 
-        /* We have two VPD data structures stored in the adapter VPD area.
-         * By default, Linux calculates the size of the VPD area by traversing
-         * the first VPD area at offset 0x0, so we need to tell the OS what
-         * our real VPD size is.
-         */
-        ret = pci_set_vpd_size(adapter->pdev, VPD_SIZE);
-        if (ret < 0)
-                goto out;
-
         /* Card information normally starts at VPD_BASE but early cards had
          * it at 0.
          */
diff --git a/drivers/net/ethernet/freescale/gianfar.c b/drivers/net/ethernet/freescale/gianfar.c
index 3bdeb295514b..f5c87bd35fa1 100644
--- a/drivers/net/ethernet/freescale/gianfar.c
+++ b/drivers/net/ethernet/freescale/gianfar.c
@@ -2934,29 +2934,17 @@ static bool gfar_add_rx_frag(struct gfar_rx_buff *rxb, u32 lstatus,
 {
         int size = lstatus & BD_LENGTH_MASK;
         struct page *page = rxb->page;
-        bool last = !!(lstatus & BD_LFLAG(RXBD_LAST));
-
-        /* Remove the FCS from the packet length */
-        if (last)
-                size -= ETH_FCS_LEN;
 
         if (likely(first)) {
                 skb_put(skb, size);
         } else {
                 /* the last fragments' length contains the full frame length */
-                if (last)
+                if (lstatus & BD_LFLAG(RXBD_LAST))
                         size -= skb->len;
 
-                /* Add the last fragment if it contains something other than
-                 * the FCS, otherwise drop it and trim off any part of the FCS
-                 * that was already received.
-                 */
-                if (size > 0)
-                        skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
-                                        rxb->page_offset + RXBUF_ALIGNMENT,
-                                        size, GFAR_RXB_TRUESIZE);
-                else if (size < 0)
-                        pskb_trim(skb, skb->len + size);
+                skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
+                                rxb->page_offset + RXBUF_ALIGNMENT,
+                                size, GFAR_RXB_TRUESIZE);
         }
 
         /* try reuse page */
@@ -3069,6 +3057,9 @@ static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb)
         if (priv->padding)
                 skb_pull(skb, priv->padding);
 
+        /* Trim off the FCS */
+        pskb_trim(skb, skb->len - ETH_FCS_LEN);
+
         if (ndev->features & NETIF_F_RXCSUM)
                 gfar_rx_checksum(skb, fcb);
 
diff --git a/drivers/net/ethernet/ibm/ibmvnic.c b/drivers/net/ethernet/ibm/ibmvnic.c
index 27447260215d..1b3cc8bb0705 100644
--- a/drivers/net/ethernet/ibm/ibmvnic.c
+++ b/drivers/net/ethernet/ibm/ibmvnic.c
@@ -791,6 +791,18 @@ static int ibmvnic_login(struct net_device *netdev)
         return 0;
 }
 
+static void release_login_buffer(struct ibmvnic_adapter *adapter)
+{
+        kfree(adapter->login_buf);
+        adapter->login_buf = NULL;
+}
+
+static void release_login_rsp_buffer(struct ibmvnic_adapter *adapter)
+{
+        kfree(adapter->login_rsp_buf);
+        adapter->login_rsp_buf = NULL;
+}
+
 static void release_resources(struct ibmvnic_adapter *adapter)
 {
         int i;
@@ -813,6 +825,10 @@ static void release_resources(struct ibmvnic_adapter *adapter)
                         }
                 }
         }
+        kfree(adapter->napi);
+        adapter->napi = NULL;
+
+        release_login_rsp_buffer(adapter);
 }
 
 static int set_link_state(struct ibmvnic_adapter *adapter, u8 link_state)
@@ -1057,6 +1073,35 @@ static int ibmvnic_open(struct net_device *netdev)
         return rc;
 }
 
+static void clean_rx_pools(struct ibmvnic_adapter *adapter)
+{
+        struct ibmvnic_rx_pool *rx_pool;
+        u64 rx_entries;
+        int rx_scrqs;
+        int i, j;
+
+        if (!adapter->rx_pool)
+                return;
+
+        rx_scrqs = be32_to_cpu(adapter->login_rsp_buf->num_rxadd_subcrqs);
+        rx_entries = adapter->req_rx_add_entries_per_subcrq;
+
+        /* Free any remaining skbs in the rx buffer pools */
+        for (i = 0; i < rx_scrqs; i++) {
+                rx_pool = &adapter->rx_pool[i];
+                if (!rx_pool)
+                        continue;
+
+                netdev_dbg(adapter->netdev, "Cleaning rx_pool[%d]\n", i);
+                for (j = 0; j < rx_entries; j++) {
+                        if (rx_pool->rx_buff[j].skb) {
+                                dev_kfree_skb_any(rx_pool->rx_buff[j].skb);
+                                rx_pool->rx_buff[j].skb = NULL;
+                        }
+                }
+        }
+}
+
 static void clean_tx_pools(struct ibmvnic_adapter *adapter)
 {
         struct ibmvnic_tx_pool *tx_pool;
@@ -1134,7 +1179,7 @@ static int __ibmvnic_close(struct net_device *netdev)
                         }
                 }
         }
-
+        clean_rx_pools(adapter);
         clean_tx_pools(adapter);
         adapter->state = VNIC_CLOSED;
         return rc;
@@ -1670,8 +1715,6 @@ static int do_reset(struct ibmvnic_adapter *adapter,
                 return 0;
         }
 
-        netif_carrier_on(netdev);
-
         /* kick napi */
         for (i = 0; i < adapter->req_rx_queues; i++)
                 napi_schedule(&adapter->napi[i]);
@@ -1679,6 +1722,8 @@ static int do_reset(struct ibmvnic_adapter *adapter,
         if (adapter->reset_reason != VNIC_RESET_FAILOVER)
                 netdev_notify_peers(netdev);
 
+        netif_carrier_on(netdev);
+
         return 0;
 }
 
@@ -1853,6 +1898,12 @@ restart_poll:
                                    be16_to_cpu(next->rx_comp.rc));
                         /* free the entry */
                         next->rx_comp.first = 0;
+                        dev_kfree_skb_any(rx_buff->skb);
+                        remove_buff_from_pool(adapter, rx_buff);
+                        continue;
+                } else if (!rx_buff->skb) {
+                        /* free the entry */
+                        next->rx_comp.first = 0;
                         remove_buff_from_pool(adapter, rx_buff);
                         continue;
                 }
@@ -3013,6 +3064,7 @@ static void send_login(struct ibmvnic_adapter *adapter)
         struct vnic_login_client_data *vlcd;
         int i;
 
+        release_login_rsp_buffer(adapter);
         client_data_len = vnic_client_data_len(adapter);
 
         buffer_size =
@@ -3738,6 +3790,7 @@ static int handle_login_rsp(union ibmvnic_crq *login_rsp_crq,
                 ibmvnic_remove(adapter->vdev);
                 return -EIO;
         }
+        release_login_buffer(adapter);
         complete(&adapter->init_done);
 
         return 0;
diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/marvell/mvpp2.c
index a1d7b88cf083..5a1668cdb461 100644
--- a/drivers/net/ethernet/marvell/mvpp2.c
+++ b/drivers/net/ethernet/marvell/mvpp2.c
@@ -7137,6 +7137,7 @@ static void mvpp2_set_rx_mode(struct net_device *dev)
         int id = port->id;
         bool allmulti = dev->flags & IFF_ALLMULTI;
 
+retry:
         mvpp2_prs_mac_promisc_set(priv, id, dev->flags & IFF_PROMISC);
         mvpp2_prs_mac_multi_set(priv, id, MVPP2_PE_MAC_MC_ALL, allmulti);
         mvpp2_prs_mac_multi_set(priv, id, MVPP2_PE_MAC_MC_IP6, allmulti);
@@ -7144,9 +7145,13 @@ static void mvpp2_set_rx_mode(struct net_device *dev)
         /* Remove all port->id's mcast enries */
         mvpp2_prs_mcast_del_all(priv, id);
 
-        if (allmulti && !netdev_mc_empty(dev)) {
-                netdev_for_each_mc_addr(ha, dev)
-                        mvpp2_prs_mac_da_accept(priv, id, ha->addr, true);
+        if (!allmulti) {
+                netdev_for_each_mc_addr(ha, dev) {
+                        if (mvpp2_prs_mac_da_accept(priv, id, ha->addr, true)) {
+                                allmulti = true;
+                                goto retry;
+                        }
+                }
         }
 }
 
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c b/drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c
index 0be4575b58a2..fd509160c8f6 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c
@@ -96,10 +96,10 @@ static void print_lyr_2_4_hdrs(struct trace_seq *p,
                                           "%pI4");
                 } else if (ethertype.v == ETH_P_IPV6) {
                         static const struct in6_addr full_ones = {
-                                .in6_u.u6_addr32 = {htonl(0xffffffff),
-                                                    htonl(0xffffffff),
-                                                    htonl(0xffffffff),
-                                                    htonl(0xffffffff)},
+                                .in6_u.u6_addr32 = {__constant_htonl(0xffffffff),
+                                                    __constant_htonl(0xffffffff),
+                                                    __constant_htonl(0xffffffff),
+                                                    __constant_htonl(0xffffffff)},
                         };
                         DECLARE_MASK_VAL(struct in6_addr, src_ipv6);
                         DECLARE_MASK_VAL(struct in6_addr, dst_ipv6);
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
index 47bab842c5ee..da94c8cba5ee 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
@@ -1768,13 +1768,16 @@ static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
         param->wq.linear = 1;
 }
 
-static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
+static void mlx5e_build_drop_rq_param(struct mlx5_core_dev *mdev,
+                                      struct mlx5e_rq_param *param)
 {
         void *rqc = param->rqc;
         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
 
         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
+
+        param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
 }
 
 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
@@ -2634,6 +2637,9 @@ static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
                                struct mlx5e_cq *cq,
                                struct mlx5e_cq_param *param)
 {
+        param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
+        param->wq.db_numa_node  = dev_to_node(&mdev->pdev->dev);
+
         return mlx5e_alloc_cq_common(mdev, param, cq);
 }
 
@@ -2645,7 +2651,7 @@ static int mlx5e_open_drop_rq(struct mlx5_core_dev *mdev,
         struct mlx5e_cq *cq = &drop_rq->cq;
         int err;
 
-        mlx5e_build_drop_rq_param(&rq_param);
+        mlx5e_build_drop_rq_param(mdev, &rq_param);
 
         err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
         if (err)
@@ -2994,8 +3000,8 @@ static int mlx5e_setup_tc_block(struct net_device *dev,
 }
 #endif
 
-int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
-                   void *type_data)
+static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
+                          void *type_data)
 {
         switch (type) {
 #ifdef CONFIG_MLX5_ESWITCH
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c
index 0d4bb0688faa..e5c3ab46a24a 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c
@@ -36,6 +36,7 @@
 #include <linux/tcp.h>
 #include <linux/bpf_trace.h>
 #include <net/busy_poll.h>
+#include <net/ip6_checksum.h>
 #include "en.h"
 #include "en_tc.h"
 #include "eswitch.h"
@@ -546,20 +547,33 @@ bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq)
         return true;
 }
 
+static void mlx5e_lro_update_tcp_hdr(struct mlx5_cqe64 *cqe, struct tcphdr *tcp)
+{
+        u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
+        u8 tcp_ack     = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) ||
+                         (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA);
+
+        tcp->check                      = 0;
+        tcp->psh                        = get_cqe_lro_tcppsh(cqe);
+
+        if (tcp_ack) {
+                tcp->ack                = 1;
+                tcp->ack_seq            = cqe->lro_ack_seq_num;
+                tcp->window             = cqe->lro_tcp_win;
+        }
+}
+
 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
                                  u32 cqe_bcnt)
 {
         struct ethhdr   *eth = (struct ethhdr *)(skb->data);
         struct tcphdr   *tcp;
         int network_depth = 0;
+        __wsum check;
         __be16 proto;
         u16 tot_len;
         void *ip_p;
 
-        u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
-        u8 tcp_ack = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) ||
-                (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA);
-
         proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
 
         tot_len = cqe_bcnt - network_depth;
@@ -576,23 +590,30 @@ static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
                 ipv4->check             = 0;
                 ipv4->check             = ip_fast_csum((unsigned char *)ipv4,
                                                        ipv4->ihl);
+
+                mlx5e_lro_update_tcp_hdr(cqe, tcp);
+                check = csum_partial(tcp, tcp->doff * 4,
+                                     csum_unfold((__force __sum16)cqe->check_sum));
+                /* Almost done, don't forget the pseudo header */
+                tcp->check = csum_tcpudp_magic(ipv4->saddr, ipv4->daddr,
+                                               tot_len - sizeof(struct iphdr),
+                                               IPPROTO_TCP, check);
         } else {
+                u16 payload_len = tot_len - sizeof(struct ipv6hdr);
                 struct ipv6hdr *ipv6 = ip_p;
 
                 tcp = ip_p + sizeof(struct ipv6hdr);
                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
 
                 ipv6->hop_limit         = cqe->lro_min_ttl;
-                ipv6->payload_len       = cpu_to_be16(tot_len -
-                                                      sizeof(struct ipv6hdr));
-        }
-
-        tcp->psh = get_cqe_lro_tcppsh(cqe);
-
-        if (tcp_ack) {
-                tcp->ack                = 1;
-                tcp->ack_seq            = cqe->lro_ack_seq_num;
-                tcp->window             = cqe->lro_tcp_win;
+                ipv6->payload_len       = cpu_to_be16(payload_len);
+
+                mlx5e_lro_update_tcp_hdr(cqe, tcp);
+                check = csum_partial(tcp, tcp->doff * 4,
+                                     csum_unfold((__force __sum16)cqe->check_sum));
+                /* Almost done, don't forget the pseudo header */
+                tcp->check = csum_ipv6_magic(&ipv6->saddr, &ipv6->daddr, payload_len,
+                                             IPPROTO_TCP, check);
         }
 }
 
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_selftest.c b/drivers/net/ethernet/mellanox/mlx5/core/en_selftest.c
index 5a4608281f38..707976482c09 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_selftest.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_selftest.c
@@ -216,7 +216,8 @@ mlx5e_test_loopback_validate(struct sk_buff *skb,
         if (iph->protocol != IPPROTO_UDP)
                 goto out;
 
-        udph = udp_hdr(skb);
+        /* Don't assume skb_transport_header() was set */
+        udph = (struct udphdr *)((u8 *)iph + 4 * iph->ihl);
         if (udph->dest != htons(9))
                 goto out;
 
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
index fd98b0dc610f..fa86a1466718 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
@@ -2529,7 +2529,8 @@ static int parse_tc_fdb_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
                         if (tcf_vlan_action(a) == TCA_VLAN_ACT_POP) {
                                 attr->action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
                         } else if (tcf_vlan_action(a) == TCA_VLAN_ACT_PUSH) {
-                                if (tcf_vlan_push_proto(a) != htons(ETH_P_8021Q))
+                                if (tcf_vlan_push_proto(a) != htons(ETH_P_8021Q) ||
+                                    tcf_vlan_push_prio(a))
                                         return -EOPNOTSUPP;
 
                                 attr->action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c
index 569b42a01026..11b4f1089d1c 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c
@@ -176,7 +176,7 @@ static inline u16 mlx5e_calc_min_inline(enum mlx5_inline_modes mode,
         default:
                 hlen = mlx5e_skb_l2_header_offset(skb);
         }
-        return min_t(u16, hlen, skb->len);
+        return min_t(u16, hlen, skb_headlen(skb));
 }
 
 static inline void mlx5e_tx_skb_pull_inline(unsigned char **skb_data,
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c
index 5ecf2cddc16d..c2b1d7d351fc 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c
@@ -1529,6 +1529,10 @@ static void esw_enable_vport(struct mlx5_eswitch *esw, int vport_num,
 
         esw_debug(esw->dev, "Enabling VPORT(%d)\n", vport_num);
 
+        /* Create steering drop counters for ingress and egress ACLs */
+        if (vport_num && esw->mode == SRIOV_LEGACY)
+                esw_vport_create_drop_counters(vport);
+
         /* Restore old vport configuration */
         esw_apply_vport_conf(esw, vport);
 
@@ -1545,10 +1549,6 @@ static void esw_enable_vport(struct mlx5_eswitch *esw, int vport_num,
         if (!vport_num)
                 vport->info.trusted = true;
 
-        /* create steering drop counters for ingress and egress ACLs */
-        if (vport_num && esw->mode == SRIOV_LEGACY)
-                esw_vport_create_drop_counters(vport);
-
         esw_vport_change_handle_locked(vport);
 
         esw->enabled_vports++;
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c
index c025c98700e4..31fc2cfac3b3 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c
@@ -1429,7 +1429,8 @@ static bool check_conflicting_actions(u32 action1, u32 action2)
 
         if (xored_actions & (MLX5_FLOW_CONTEXT_ACTION_DROP  |
                              MLX5_FLOW_CONTEXT_ACTION_ENCAP |
-                             MLX5_FLOW_CONTEXT_ACTION_DECAP))
+                             MLX5_FLOW_CONTEXT_ACTION_DECAP |
+                             MLX5_FLOW_CONTEXT_ACTION_MOD_HDR))
                 return true;
 
         return false;
@@ -1758,8 +1759,11 @@ search_again_locked:
 
         /* Collect all fgs which has a matching match_criteria */
         err = build_match_list(&match_head, ft, spec);
-        if (err)
+        if (err) {
+                if (take_write)
+                        up_write_ref_node(&ft->node);
                 return ERR_PTR(err);
+        }
 
         if (!take_write)
                 up_read_ref_node(&ft->node);
@@ -1768,8 +1772,11 @@ search_again_locked:
                                       dest_num, version);
         free_match_list(&match_head);
         if (!IS_ERR(rule) ||
-            (PTR_ERR(rule) != -ENOENT && PTR_ERR(rule) != -EAGAIN))
+            (PTR_ERR(rule) != -ENOENT && PTR_ERR(rule) != -EAGAIN)) {
+                if (take_write)
+                        up_write_ref_node(&ft->node);
                 return rule;
+        }
 
         if (!take_write) {
                 nested_down_write_ref_node(&ft->node, FS_LOCK_GRANDPARENT);
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
index e159243e0fcf..857035583ccd 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
@@ -34,6 +34,7 @@
 #include <linux/highmem.h>
 #include <rdma/mlx5-abi.h>
 #include "en.h"
+#include "clock.h"
 
 enum {
         MLX5_CYCLES_SHIFT       = 23
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/ethernet/mellanox/mlx5/core/main.c
index 2ef641c91c26..ae391e4b7070 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/main.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c
@@ -551,7 +551,7 @@ static int handle_hca_cap(struct mlx5_core_dev *dev)
                 MLX5_SET(cmd_hca_cap,
                          set_hca_cap,
                          cache_line_128byte,
-                         cache_line_size() == 128 ? 1 : 0);
+                         cache_line_size() >= 128 ? 1 : 0);
 
         if (MLX5_CAP_GEN_MAX(dev, dct))
                 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c
index f0b25baba09a..f7948e983637 100644
--- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c
+++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c
@@ -788,6 +788,9 @@ static struct mlxsw_sp_vr *mlxsw_sp_vr_create(struct mlxsw_sp *mlxsw_sp,
                                               u32 tb_id,
                                               struct netlink_ext_ack *extack)
 {
+        struct mlxsw_sp_mr_table *mr4_table;
+        struct mlxsw_sp_fib *fib4;
+        struct mlxsw_sp_fib *fib6;
         struct mlxsw_sp_vr *vr;
         int err;
 
@@ -796,29 +799,30 @@ static struct mlxsw_sp_vr *mlxsw_sp_vr_create(struct mlxsw_sp *mlxsw_sp,
                 NL_SET_ERR_MSG(extack, "spectrum: Exceeded number of supported virtual routers");
                 return ERR_PTR(-EBUSY);
         }
-        vr->fib4 = mlxsw_sp_fib_create(mlxsw_sp, vr, MLXSW_SP_L3_PROTO_IPV4);
-        if (IS_ERR(vr->fib4))
-                return ERR_CAST(vr->fib4);
-        vr->fib6 = mlxsw_sp_fib_create(mlxsw_sp, vr, MLXSW_SP_L3_PROTO_IPV6);
-        if (IS_ERR(vr->fib6)) {
-                err = PTR_ERR(vr->fib6);
+        fib4 = mlxsw_sp_fib_create(mlxsw_sp, vr, MLXSW_SP_L3_PROTO_IPV4);
+        if (IS_ERR(fib4))
+                return ERR_CAST(fib4);
+        fib6 = mlxsw_sp_fib_create(mlxsw_sp, vr, MLXSW_SP_L3_PROTO_IPV6);
+        if (IS_ERR(fib6)) {
+                err = PTR_ERR(fib6);
                 goto err_fib6_create;
         }
-        vr->mr4_table = mlxsw_sp_mr_table_create(mlxsw_sp, vr->id,
-                                                 MLXSW_SP_L3_PROTO_IPV4);
-        if (IS_ERR(vr->mr4_table)) {
-                err = PTR_ERR(vr->mr4_table);
+        mr4_table = mlxsw_sp_mr_table_create(mlxsw_sp, vr->id,
+                                             MLXSW_SP_L3_PROTO_IPV4);
+        if (IS_ERR(mr4_table)) {
+                err = PTR_ERR(mr4_table);
                 goto err_mr_table_create;
         }
+        vr->fib4 = fib4;
+        vr->fib6 = fib6;
+        vr->mr4_table = mr4_table;
         vr->tb_id = tb_id;
         return vr;
 
 err_mr_table_create:
-        mlxsw_sp_fib_destroy(mlxsw_sp, vr->fib6);
-        vr->fib6 = NULL;
+        mlxsw_sp_fib_destroy(mlxsw_sp, fib6);
 err_fib6_create:
-        mlxsw_sp_fib_destroy(mlxsw_sp, vr->fib4);
-        vr->fib4 = NULL;
+        mlxsw_sp_fib_destroy(mlxsw_sp, fib4);
         return ERR_PTR(err);
 }
 
@@ -3790,6 +3794,9 @@ mlxsw_sp_fib4_entry_offload_unset(struct mlxsw_sp_fib_entry *fib_entry)
         struct mlxsw_sp_nexthop_group *nh_grp = fib_entry->nh_group;
         int i;
 
+        if (!list_is_singular(&nh_grp->fib_list))
+                return;
+
         for (i = 0; i < nh_grp->count; i++) {
                 struct mlxsw_sp_nexthop *nh = &nh_grp->nexthops[i];
 
diff --git a/drivers/net/ethernet/qualcomm/rmnet/rmnet_config.c b/drivers/net/ethernet/qualcomm/rmnet/rmnet_config.c
index 7e7704daf5f1..c4949183eef3 100644
--- a/drivers/net/ethernet/qualcomm/rmnet/rmnet_config.c
+++ b/drivers/net/ethernet/qualcomm/rmnet/rmnet_config.c
@@ -43,12 +43,6 @@
 
 /* Local Definitions and Declarations */
 
-struct rmnet_walk_data {
-        struct net_device *real_dev;
-        struct list_head *head;
-        struct rmnet_port *port;
-};
-
 static int rmnet_is_real_dev_registered(const struct net_device *real_dev)
 {
         return rcu_access_pointer(real_dev->rx_handler) == rmnet_rx_handler;
@@ -112,17 +106,14 @@ static int rmnet_register_real_device(struct net_device *real_dev)
 static void rmnet_unregister_bridge(struct net_device *dev,
                                     struct rmnet_port *port)
 {
-        struct net_device *rmnet_dev, *bridge_dev;
         struct rmnet_port *bridge_port;
+        struct net_device *bridge_dev;
 
         if (port->rmnet_mode != RMNET_EPMODE_BRIDGE)
                 return;
 
         /* bridge slave handling */
         if (!port->nr_rmnet_devs) {
-                rmnet_dev = netdev_master_upper_dev_get_rcu(dev);
-                netdev_upper_dev_unlink(dev, rmnet_dev);
-
                 bridge_dev = port->bridge_ep;
 
                 bridge_port = rmnet_get_port_rtnl(bridge_dev);
@@ -132,9 +123,6 @@ static void rmnet_unregister_bridge(struct net_device *dev,
                 bridge_dev = port->bridge_ep;
 
                 bridge_port = rmnet_get_port_rtnl(bridge_dev);
-                rmnet_dev = netdev_master_upper_dev_get_rcu(bridge_dev);
-                netdev_upper_dev_unlink(bridge_dev, rmnet_dev);
-
                 rmnet_unregister_real_device(bridge_dev, bridge_port);
         }
 }
@@ -173,10 +161,6 @@ static int rmnet_newlink(struct net *src_net, struct net_device *dev,
         if (err)
                 goto err1;
 
-        err = netdev_master_upper_dev_link(dev, real_dev, NULL, NULL, extack);
-        if (err)
-                goto err2;
-
         port->rmnet_mode = mode;
 
         hlist_add_head_rcu(&ep->hlnode, &port->muxed_ep[mux_id]);
@@ -193,8 +177,6 @@ static int rmnet_newlink(struct net *src_net, struct net_device *dev,
 
         return 0;
 
-err2:
-        rmnet_vnd_dellink(mux_id, port, ep);
 err1:
         rmnet_unregister_real_device(real_dev, port);
 err0:
@@ -204,14 +186,13 @@ err0:
 
 static void rmnet_dellink(struct net_device *dev, struct list_head *head)
 {
+        struct rmnet_priv *priv = netdev_priv(dev);
         struct net_device *real_dev;
         struct rmnet_endpoint *ep;
         struct rmnet_port *port;
         u8 mux_id;
 
-        rcu_read_lock();
-        real_dev = netdev_master_upper_dev_get_rcu(dev);
-        rcu_read_unlock();
+        real_dev = priv->real_dev;
 
         if (!real_dev || !rmnet_is_real_dev_registered(real_dev))
                 return;
@@ -219,7 +200,6 @@ static void rmnet_dellink(struct net_device *dev, struct list_head *head)
         port = rmnet_get_port_rtnl(real_dev);
 
         mux_id = rmnet_vnd_get_mux(dev);
-        netdev_upper_dev_unlink(dev, real_dev);
 
         ep = rmnet_get_endpoint(port, mux_id);
         if (ep) {
@@ -233,30 +213,13 @@ static void rmnet_dellink(struct net_device *dev, struct list_head *head)
         unregister_netdevice_queue(dev, head);
 }
 
-static int rmnet_dev_walk_unreg(struct net_device *rmnet_dev, void *data)
-{
-        struct rmnet_walk_data *d = data;
-        struct rmnet_endpoint *ep;
-        u8 mux_id;
-
-        mux_id = rmnet_vnd_get_mux(rmnet_dev);
-        ep = rmnet_get_endpoint(d->port, mux_id);
-        if (ep) {
-                hlist_del_init_rcu(&ep->hlnode);
-                rmnet_vnd_dellink(mux_id, d->port, ep);
-                kfree(ep);
-        }
-        netdev_upper_dev_unlink(rmnet_dev, d->real_dev);
-        unregister_netdevice_queue(rmnet_dev, d->head);
-
-        return 0;
-}
-
 static void rmnet_force_unassociate_device(struct net_device *dev)
 {
         struct net_device *real_dev = dev;
-        struct rmnet_walk_data d;
+        struct hlist_node *tmp_ep;
+        struct rmnet_endpoint *ep;
         struct rmnet_port *port;
+        unsigned long bkt_ep;
         LIST_HEAD(list);
 
         if (!rmnet_is_real_dev_registered(real_dev))
@@ -264,16 +227,19 @@ static void rmnet_force_unassociate_device(struct net_device *dev)
 
         ASSERT_RTNL();
 
-        d.real_dev = real_dev;
-        d.head = &list;
-
         port = rmnet_get_port_rtnl(dev);
-        d.port = port;
 
         rcu_read_lock();
         rmnet_unregister_bridge(dev, port);
 
-        netdev_walk_all_lower_dev_rcu(real_dev, rmnet_dev_walk_unreg, &d);
+        hash_for_each_safe(port->muxed_ep, bkt_ep, tmp_ep, ep, hlnode) {
+                unregister_netdevice_queue(ep->egress_dev, &list);
+                rmnet_vnd_dellink(ep->mux_id, port, ep);
+
+                hlist_del_init_rcu(&ep->hlnode);
+                kfree(ep);
+        }
+
         rcu_read_unlock();
         unregister_netdevice_many(&list);
 
@@ -422,11 +388,6 @@ int rmnet_add_bridge(struct net_device *rmnet_dev,
         if (err)
                 return -EBUSY;
 
-        err = netdev_master_upper_dev_link(slave_dev, rmnet_dev, NULL, NULL,
-                                           extack);
-        if (err)
-                return -EINVAL;
-
         slave_port = rmnet_get_port(slave_dev);
         slave_port->rmnet_mode = RMNET_EPMODE_BRIDGE;
         slave_port->bridge_ep = real_dev;
@@ -449,7 +410,6 @@ int rmnet_del_bridge(struct net_device *rmnet_dev,
         port->rmnet_mode = RMNET_EPMODE_VND;
         port->bridge_ep = NULL;
 
-        netdev_upper_dev_unlink(slave_dev, rmnet_dev);
         slave_port = rmnet_get_port(slave_dev);
         rmnet_unregister_real_device(slave_dev, slave_port);
 
diff --git a/drivers/net/ethernet/qualcomm/rmnet/rmnet_map_command.c b/drivers/net/ethernet/qualcomm/rmnet/rmnet_map_command.c
index 6bc328fb88e1..b0dbca070c00 100644
--- a/drivers/net/ethernet/qualcomm/rmnet/rmnet_map_command.c
+++ b/drivers/net/ethernet/qualcomm/rmnet/rmnet_map_command.c
@@ -38,6 +38,11 @@ static u8 rmnet_map_do_flow_control(struct sk_buff *skb,
         }
 
         ep = rmnet_get_endpoint(port, mux_id);
+        if (!ep) {
+                kfree_skb(skb);
+                return RX_HANDLER_CONSUMED;
+        }
+
         vnd = ep->egress_dev;
 
         ip_family = cmd->flow_control.ip_family;
diff --git a/drivers/net/ethernet/qualcomm/rmnet/rmnet_vnd.c b/drivers/net/ethernet/qualcomm/rmnet/rmnet_vnd.c
index 570a227acdd8..346d310914df 100644
--- a/drivers/net/ethernet/qualcomm/rmnet/rmnet_vnd.c
+++ b/drivers/net/ethernet/qualcomm/rmnet/rmnet_vnd.c
@@ -121,7 +121,7 @@ static void rmnet_get_stats64(struct net_device *dev,
         memset(&total_stats, 0, sizeof(struct rmnet_vnd_stats));
 
         for_each_possible_cpu(cpu) {
-                pcpu_ptr = this_cpu_ptr(priv->pcpu_stats);
+                pcpu_ptr = per_cpu_ptr(priv->pcpu_stats, cpu);
 
                 do {
                         start = u64_stats_fetch_begin_irq(&pcpu_ptr->syncp);
diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
index c87f57ca4437..a95fbd5510d9 100644
--- a/drivers/net/ethernet/renesas/ravb_main.c
+++ b/drivers/net/ethernet/renesas/ravb_main.c
@@ -2255,9 +2255,6 @@ static int ravb_wol_setup(struct net_device *ndev)
         /* Enable MagicPacket */
         ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
 
-        /* Increased clock usage so device won't be suspended */
-        clk_enable(priv->clk);
-
         return enable_irq_wake(priv->emac_irq);
 }
 
@@ -2276,9 +2273,6 @@ static int ravb_wol_restore(struct net_device *ndev)
         if (ret < 0)
                 return ret;
 
-        /* Restore clock usage count */
-        clk_disable(priv->clk);
-
         return disable_irq_wake(priv->emac_irq);
 }
 
diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
index a197e11f3a56..92dcf8717fc6 100644
--- a/drivers/net/ethernet/renesas/sh_eth.c
+++ b/drivers/net/ethernet/renesas/sh_eth.c
@@ -40,7 +40,6 @@
 #include <linux/slab.h>
 #include <linux/ethtool.h>
 #include <linux/if_vlan.h>
-#include <linux/clk.h>
 #include <linux/sh_eth.h>
 #include <linux/of_mdio.h>
 
@@ -2304,7 +2303,7 @@ static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
         wol->supported = 0;
         wol->wolopts = 0;
 
-        if (mdp->cd->magic && mdp->clk) {
+        if (mdp->cd->magic) {
                 wol->supported = WAKE_MAGIC;
                 wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0;
         }
@@ -2314,7 +2313,7 @@ static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
 {
         struct sh_eth_private *mdp = netdev_priv(ndev);
 
-        if (!mdp->cd->magic || !mdp->clk || wol->wolopts & ~WAKE_MAGIC)
+        if (!mdp->cd->magic || wol->wolopts & ~WAKE_MAGIC)
                 return -EOPNOTSUPP;
 
         mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
@@ -3153,11 +3152,6 @@ static int sh_eth_drv_probe(struct platform_device *pdev)
                 goto out_release;
         }
 
-        /* Get clock, if not found that's OK but Wake-On-Lan is unavailable */
-        mdp->clk = devm_clk_get(&pdev->dev, NULL);
-        if (IS_ERR(mdp->clk))
-                mdp->clk = NULL;
-
         ndev->base_addr = res->start;
 
         spin_lock_init(&mdp->lock);
@@ -3278,7 +3272,7 @@ static int sh_eth_drv_probe(struct platform_device *pdev)
         if (ret)
                 goto out_napi_del;
 
-        if (mdp->cd->magic && mdp->clk)
+        if (mdp->cd->magic)
                 device_set_wakeup_capable(&pdev->dev, 1);
 
         /* print device information */
@@ -3331,9 +3325,6 @@ static int sh_eth_wol_setup(struct net_device *ndev)
         /* Enable MagicPacket */
         sh_eth_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
 
-        /* Increased clock usage so device won't be suspended */
-        clk_enable(mdp->clk);
-
         return enable_irq_wake(ndev->irq);
 }
 
@@ -3359,9 +3350,6 @@ static int sh_eth_wol_restore(struct net_device *ndev)
         if (ret < 0)
                 return ret;
 
-        /* Restore clock usage count */
-        clk_disable(mdp->clk);
-
         return disable_irq_wake(ndev->irq);
 }
 
diff --git a/drivers/net/ethernet/smsc/Kconfig b/drivers/net/ethernet/smsc/Kconfig
index 63aca9f847e1..4c2f612e4414 100644
--- a/drivers/net/ethernet/smsc/Kconfig
+++ b/drivers/net/ethernet/smsc/Kconfig
@@ -20,7 +20,7 @@ if NET_VENDOR_SMSC
 
 config SMC9194
         tristate "SMC 9194 support"
-        depends on (ISA || MAC && BROKEN)
+        depends on ISA
         select CRC32
         ---help---
           This is support for the SMC9xxx based Ethernet cards. Choose this
diff --git a/drivers/net/macvlan.c b/drivers/net/macvlan.c
index a0f2be81d52e..8fc02d9db3d0 100644
--- a/drivers/net/macvlan.c
+++ b/drivers/net/macvlan.c
@@ -1451,7 +1451,7 @@ destroy_macvlan_port:
         /* the macvlan port may be freed by macvlan_uninit when fail to register.
          * so we destroy the macvlan port only when it's valid.
          */
-        if (create && macvlan_port_get_rtnl(dev))
+        if (create && macvlan_port_get_rtnl(lowerdev))
                 macvlan_port_destroy(port->dev);
         return err;
 }
diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
index b13eed21c87d..d39ae77707ef 100644
--- a/drivers/net/phy/phy_device.c
+++ b/drivers/net/phy/phy_device.c
@@ -1382,7 +1382,7 @@ int genphy_setup_forced(struct phy_device *phydev)
                 ctl |= BMCR_FULLDPLX;
 
         return phy_modify(phydev, MII_BMCR,
-                          BMCR_LOOPBACK | BMCR_ISOLATE | BMCR_PDOWN, ctl);
+                          ~(BMCR_LOOPBACK | BMCR_ISOLATE | BMCR_PDOWN), ctl);
 }
 EXPORT_SYMBOL(genphy_setup_forced);
 
diff --git a/drivers/net/thunderbolt.c b/drivers/net/thunderbolt.c
index ca5e375de27c..e0d6760f3219 100644
--- a/drivers/net/thunderbolt.c
+++ b/drivers/net/thunderbolt.c
@@ -166,6 +166,8 @@ struct tbnet_ring {
  * @connected_work: Worker that finalizes the ThunderboltIP connection
  *                  setup and enables DMA paths for high speed data
  *                  transfers
+ * @disconnect_work: Worker that handles tearing down the ThunderboltIP
+ *                   connection
  * @rx_hdr: Copy of the currently processed Rx frame. Used when a
  *          network packet consists of multiple Thunderbolt frames.
  *          In host byte order.
@@ -190,6 +192,7 @@ struct tbnet {
         int login_retries;
         struct delayed_work login_work;
         struct work_struct connected_work;
+        struct work_struct disconnect_work;
         struct thunderbolt_ip_frame_header rx_hdr;
         struct tbnet_ring rx_ring;
         atomic_t frame_id;
@@ -445,7 +448,7 @@ static int tbnet_handle_packet(const void *buf, size_t size, void *data)
         case TBIP_LOGOUT:
                 ret = tbnet_logout_response(net, route, sequence, command_id);
                 if (!ret)
-                        tbnet_tear_down(net, false);
+                        queue_work(system_long_wq, &net->disconnect_work);
                 break;
 
         default:
@@ -659,6 +662,13 @@ static void tbnet_login_work(struct work_struct *work)
         }
 }
 
+static void tbnet_disconnect_work(struct work_struct *work)
+{
+        struct tbnet *net = container_of(work, typeof(*net), disconnect_work);
+
+        tbnet_tear_down(net, false);
+}
+
 static bool tbnet_check_frame(struct tbnet *net, const struct tbnet_frame *tf,
                               const struct thunderbolt_ip_frame_header *hdr)
 {
@@ -881,6 +891,7 @@ static int tbnet_stop(struct net_device *dev)
 
         napi_disable(&net->napi);
 
+        cancel_work_sync(&net->disconnect_work);
         tbnet_tear_down(net, true);
 
         tb_ring_free(net->rx_ring.ring);
@@ -1195,6 +1206,7 @@ static int tbnet_probe(struct tb_service *svc, const struct tb_service_id *id)
         net = netdev_priv(dev);
         INIT_DELAYED_WORK(&net->login_work, tbnet_login_work);
         INIT_WORK(&net->connected_work, tbnet_connected_work);
+        INIT_WORK(&net->disconnect_work, tbnet_disconnect_work);
         mutex_init(&net->connection_lock);
         atomic_set(&net->command_id, 0);
         atomic_set(&net->frame_id, 0);
@@ -1270,10 +1282,7 @@ static int __maybe_unused tbnet_suspend(struct device *dev)
         stop_login(net);
         if (netif_running(net->dev)) {
                 netif_device_detach(net->dev);
-                tb_ring_stop(net->rx_ring.ring);
-                tb_ring_stop(net->tx_ring.ring);
-                tbnet_free_buffers(&net->rx_ring);
-                tbnet_free_buffers(&net->tx_ring);
+                tbnet_tear_down(net, true);
         }
 
         return 0;
diff --git a/drivers/net/tun.c b/drivers/net/tun.c
index 81e6cc951e7f..b52258c327d2 100644
--- a/drivers/net/tun.c
+++ b/drivers/net/tun.c
@@ -1489,27 +1489,23 @@ static struct sk_buff *tun_napi_alloc_frags(struct tun_file *tfile,
         skb->truesize += skb->data_len;
 
         for (i = 1; i < it->nr_segs; i++) {
+                struct page_frag *pfrag = &current->task_frag;
                 size_t fragsz = it->iov[i].iov_len;
-                unsigned long offset;
-                struct page *page;
-                void *data;
 
                 if (fragsz == 0 || fragsz > PAGE_SIZE) {
                         err = -EINVAL;
                         goto free;
                 }
 
-                local_bh_disable();
-                data = napi_alloc_frag(fragsz);
-                local_bh_enable();
-                if (!data) {
+                if (!skb_page_frag_refill(fragsz, pfrag, GFP_KERNEL)) {
                         err = -ENOMEM;
                         goto free;
                 }
 
-                page = virt_to_head_page(data);
-                offset = data - page_address(page);
-                skb_fill_page_desc(skb, i - 1, page, offset, fragsz);
+                skb_fill_page_desc(skb, i - 1, pfrag->page,
+                                   pfrag->offset, fragsz);
+                page_ref_inc(pfrag->page);
+                pfrag->offset += fragsz;
         }
 
         return skb;
diff --git a/drivers/net/usb/smsc75xx.c b/drivers/net/usb/smsc75xx.c
index d0a113743195..7a6a1fe79309 100644
--- a/drivers/net/usb/smsc75xx.c
+++ b/drivers/net/usb/smsc75xx.c
@@ -954,10 +954,11 @@ static int smsc75xx_set_features(struct net_device *netdev,
         /* it's racing here! */
 
         ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
-        if (ret < 0)
+        if (ret < 0) {
                 netdev_warn(dev->net, "Error writing RFE_CTL\n");
-
-        return ret;
+                return ret;
+        }
+        return 0;
 }
 
 static int smsc75xx_wait_ready(struct usbnet *dev, int in_pm)
diff --git a/drivers/net/virtio_net.c b/drivers/net/virtio_net.c
index 626c27352ae2..9bb9e562b893 100644
--- a/drivers/net/virtio_net.c
+++ b/drivers/net/virtio_net.c
@@ -443,12 +443,8 @@ static bool __virtnet_xdp_xmit(struct virtnet_info *vi,
         sg_init_one(sq->sg, xdp->data, xdp->data_end - xdp->data);
 
         err = virtqueue_add_outbuf(sq->vq, sq->sg, 1, xdp->data, GFP_ATOMIC);
-        if (unlikely(err)) {
-                struct page *page = virt_to_head_page(xdp->data);
-
-                put_page(page);
-                return false;
-        }
+        if (unlikely(err))
+                return false; /* Caller handle free/refcnt */
 
         return true;
 }
@@ -456,8 +452,18 @@ static bool __virtnet_xdp_xmit(struct virtnet_info *vi,
 static int virtnet_xdp_xmit(struct net_device *dev, struct xdp_buff *xdp)
 {
         struct virtnet_info *vi = netdev_priv(dev);
-        bool sent = __virtnet_xdp_xmit(vi, xdp);
+        struct receive_queue *rq = vi->rq;
+        struct bpf_prog *xdp_prog;
+        bool sent;
 
+        /* Only allow ndo_xdp_xmit if XDP is loaded on dev, as this
+         * indicate XDP resources have been successfully allocated.
+         */
+        xdp_prog = rcu_dereference(rq->xdp_prog);
+        if (!xdp_prog)
+                return -ENXIO;
+
+        sent = __virtnet_xdp_xmit(vi, xdp);
         if (!sent)
                 return -ENOSPC;
         return 0;
@@ -546,8 +552,11 @@ static struct sk_buff *receive_small(struct net_device *dev,
         unsigned int buflen = SKB_DATA_ALIGN(GOOD_PACKET_LEN + headroom) +
                               SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
         struct page *page = virt_to_head_page(buf);
-        unsigned int delta = 0, err;
+        unsigned int delta = 0;
         struct page *xdp_page;
+        bool sent;
+        int err;
+
         len -= vi->hdr_len;
 
         rcu_read_lock();
@@ -558,7 +567,7 @@ static struct sk_buff *receive_small(struct net_device *dev,
                 void *orig_data;
                 u32 act;
 
-                if (unlikely(hdr->hdr.gso_type || hdr->hdr.flags))
+                if (unlikely(hdr->hdr.gso_type))
                         goto err_xdp;
 
                 if (unlikely(xdp_headroom < virtnet_get_headroom(vi))) {
@@ -596,16 +605,19 @@ static struct sk_buff *receive_small(struct net_device *dev,
                         delta = orig_data - xdp.data;
                         break;
                 case XDP_TX:
-                        if (unlikely(!__virtnet_xdp_xmit(vi, &xdp)))
+                        sent = __virtnet_xdp_xmit(vi, &xdp);
+                        if (unlikely(!sent)) {
                                 trace_xdp_exception(vi->dev, xdp_prog, act);
-                        else
-                                *xdp_xmit = true;
+                                goto err_xdp;
+                        }
+                        *xdp_xmit = true;
                         rcu_read_unlock();
                         goto xdp_xmit;
                 case XDP_REDIRECT:
                         err = xdp_do_redirect(dev, &xdp, xdp_prog);
-                        if (!err)
-                                *xdp_xmit = true;
+                        if (err)
+                                goto err_xdp;
+                        *xdp_xmit = true;
                         rcu_read_unlock();
                         goto xdp_xmit;
                 default:
@@ -677,7 +689,7 @@ static struct sk_buff *receive_mergeable(struct net_device *dev,
         struct bpf_prog *xdp_prog;
         unsigned int truesize;
         unsigned int headroom = mergeable_ctx_to_headroom(ctx);
-        int err;
+        bool sent;
 
         head_skb = NULL;
 
@@ -746,20 +758,18 @@ static struct sk_buff *receive_mergeable(struct net_device *dev,
                         }
                         break;
                 case XDP_TX:
-                        if (unlikely(!__virtnet_xdp_xmit(vi, &xdp)))
+                        sent = __virtnet_xdp_xmit(vi, &xdp);
+                        if (unlikely(!sent)) {
                                 trace_xdp_exception(vi->dev, xdp_prog, act);
-                        else
-                                *xdp_xmit = true;
+                                if (unlikely(xdp_page != page))
+                                        put_page(xdp_page);
+                                goto err_xdp;
+                        }
+                        *xdp_xmit = true;
                         if (unlikely(xdp_page != page))
                                 goto err_xdp;
                         rcu_read_unlock();
                         goto xdp_xmit;
-                case XDP_REDIRECT:
-                        err = xdp_do_redirect(dev, &xdp, xdp_prog);
-                        if (!err)
-                                *xdp_xmit = true;
-                        rcu_read_unlock();
-                        goto xdp_xmit;
                 default:
                         bpf_warn_invalid_xdp_action(act);
                 case XDP_ABORTED:
diff --git a/drivers/net/wireless/mac80211_hwsim.c b/drivers/net/wireless/mac80211_hwsim.c
index 1cf22e62e3dd..6e0af815f25e 100644
--- a/drivers/net/wireless/mac80211_hwsim.c
+++ b/drivers/net/wireless/mac80211_hwsim.c
@@ -3516,7 +3516,7 @@ static int __init init_mac80211_hwsim(void)
 
         spin_lock_init(&hwsim_radio_lock);
 
-        hwsim_wq = alloc_workqueue("hwsim_wq",WQ_MEM_RECLAIM,0);
+        hwsim_wq = alloc_workqueue("hwsim_wq", 0, 0);
         if (!hwsim_wq)
                 return -ENOMEM;
         rhashtable_init(&hwsim_radios_rht, &hwsim_rht_params);
diff --git a/drivers/net/xen-netfront.c b/drivers/net/xen-netfront.c
index 8328d395e332..3127bc8633ca 100644
--- a/drivers/net/xen-netfront.c
+++ b/drivers/net/xen-netfront.c
@@ -2005,7 +2005,10 @@ static void netback_changed(struct xenbus_device *dev,
         case XenbusStateInitialised:
         case XenbusStateReconfiguring:
         case XenbusStateReconfigured:
+                break;
+
         case XenbusStateUnknown:
+                wake_up_all(&module_unload_q);
                 break;
 
         case XenbusStateInitWait:
@@ -2136,7 +2139,9 @@ static int xennet_remove(struct xenbus_device *dev)
                 xenbus_switch_state(dev, XenbusStateClosing);
                 wait_event(module_unload_q,
                            xenbus_read_driver_state(dev->otherend) ==
-                           XenbusStateClosing);
+                           XenbusStateClosing ||
+                           xenbus_read_driver_state(dev->otherend) ==
+                           XenbusStateUnknown);
 
                 xenbus_switch_state(dev, XenbusStateClosed);
                 wait_event(module_unload_q,
diff --git a/drivers/nvdimm/pmem.c b/drivers/nvdimm/pmem.c
index 10041ac4032c..06f8dcc52ca6 100644
--- a/drivers/nvdimm/pmem.c
+++ b/drivers/nvdimm/pmem.c
@@ -335,8 +335,7 @@ static int pmem_attach_disk(struct device *dev,
                 dev_warn(dev, "unable to guarantee persistence of writes\n");
                 fua = 0;
         }
-        wbc = nvdimm_has_cache(nd_region) &&
-                !test_bit(ND_REGION_PERSIST_CACHE, &nd_region->flags);
+        wbc = nvdimm_has_cache(nd_region);
 
         if (!devm_request_mem_region(dev, res->start, resource_size(res),
                                 dev_name(&ndns->dev))) {
diff --git a/drivers/nvme/host/core.c b/drivers/nvme/host/core.c
index f431c32774f3..817e5e2766da 100644
--- a/drivers/nvme/host/core.c
+++ b/drivers/nvme/host/core.c
@@ -120,8 +120,12 @@ int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl)
         int ret;
 
         ret = nvme_reset_ctrl(ctrl);
-        if (!ret)
+        if (!ret) {
                 flush_work(&ctrl->reset_work);
+                if (ctrl->state != NVME_CTRL_LIVE)
+                        ret = -ENETRESET;
+        }
+
         return ret;
 }
 EXPORT_SYMBOL_GPL(nvme_reset_ctrl_sync);
@@ -265,7 +269,7 @@ bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
         switch (new_state) {
         case NVME_CTRL_ADMIN_ONLY:
                 switch (old_state) {
-                case NVME_CTRL_RECONNECTING:
+                case NVME_CTRL_CONNECTING:
                         changed = true;
                         /* FALLTHRU */
                 default:
@@ -276,7 +280,7 @@ bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
                 switch (old_state) {
                 case NVME_CTRL_NEW:
                 case NVME_CTRL_RESETTING:
-                case NVME_CTRL_RECONNECTING:
+                case NVME_CTRL_CONNECTING:
                         changed = true;
                         /* FALLTHRU */
                 default:
@@ -294,9 +298,9 @@ bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
                         break;
                 }
                 break;
-        case NVME_CTRL_RECONNECTING:
+        case NVME_CTRL_CONNECTING:
                 switch (old_state) {
-                case NVME_CTRL_LIVE:
+                case NVME_CTRL_NEW:
                 case NVME_CTRL_RESETTING:
                         changed = true;
                         /* FALLTHRU */
@@ -309,7 +313,7 @@ bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
                 case NVME_CTRL_LIVE:
                 case NVME_CTRL_ADMIN_ONLY:
                 case NVME_CTRL_RESETTING:
-                case NVME_CTRL_RECONNECTING:
+                case NVME_CTRL_CONNECTING:
                         changed = true;
                         /* FALLTHRU */
                 default:
@@ -518,9 +522,11 @@ static blk_status_t nvme_setup_discard(struct nvme_ns *ns, struct request *req,
                 u64 slba = nvme_block_nr(ns, bio->bi_iter.bi_sector);
                 u32 nlb = bio->bi_iter.bi_size >> ns->lba_shift;
 
-                range[n].cattr = cpu_to_le32(0);
-                range[n].nlb = cpu_to_le32(nlb);
-                range[n].slba = cpu_to_le64(slba);
+                if (n < segments) {
+                        range[n].cattr = cpu_to_le32(0);
+                        range[n].nlb = cpu_to_le32(nlb);
+                        range[n].slba = cpu_to_le64(slba);
+                }
                 n++;
         }
 
@@ -794,13 +800,9 @@ static void nvme_keep_alive_end_io(struct request *rq, blk_status_t status)
 
 static int nvme_keep_alive(struct nvme_ctrl *ctrl)
 {
-        struct nvme_command c;
         struct request *rq;
 
-        memset(&c, 0, sizeof(c));
-        c.common.opcode = nvme_admin_keep_alive;
-
-        rq = nvme_alloc_request(ctrl->admin_q, &c, BLK_MQ_REQ_RESERVED,
+        rq = nvme_alloc_request(ctrl->admin_q, &ctrl->ka_cmd, BLK_MQ_REQ_RESERVED,
                         NVME_QID_ANY);
         if (IS_ERR(rq))
                 return PTR_ERR(rq);
@@ -832,6 +834,8 @@ void nvme_start_keep_alive(struct nvme_ctrl *ctrl)
                 return;
 
         INIT_DELAYED_WORK(&ctrl->ka_work, nvme_keep_alive_work);
+        memset(&ctrl->ka_cmd, 0, sizeof(ctrl->ka_cmd));
+        ctrl->ka_cmd.common.opcode = nvme_admin_keep_alive;
         schedule_delayed_work(&ctrl->ka_work, ctrl->kato * HZ);
 }
 EXPORT_SYMBOL_GPL(nvme_start_keep_alive);
@@ -1117,14 +1121,19 @@ static u32 nvme_passthru_start(struct nvme_ctrl *ctrl, struct nvme_ns *ns,
 
 static void nvme_update_formats(struct nvme_ctrl *ctrl)
 {
-        struct nvme_ns *ns;
+        struct nvme_ns *ns, *next;
+        LIST_HEAD(rm_list);
 
         mutex_lock(&ctrl->namespaces_mutex);
         list_for_each_entry(ns, &ctrl->namespaces, list) {
-                if (ns->disk && nvme_revalidate_disk(ns->disk))
-                        nvme_ns_remove(ns);
+                if (ns->disk && nvme_revalidate_disk(ns->disk)) {
+                        list_move_tail(&ns->list, &rm_list);
+                }
         }
         mutex_unlock(&ctrl->namespaces_mutex);
+
+        list_for_each_entry_safe(ns, next, &rm_list, list)
+                nvme_ns_remove(ns);
 }
 
 static void nvme_passthru_end(struct nvme_ctrl *ctrl, u32 effects)
@@ -2687,7 +2696,7 @@ static ssize_t nvme_sysfs_show_state(struct device *dev,
                 [NVME_CTRL_LIVE]        = "live",
                 [NVME_CTRL_ADMIN_ONLY]  = "only-admin",
                 [NVME_CTRL_RESETTING]   = "resetting",
-                [NVME_CTRL_RECONNECTING]= "reconnecting",
+                [NVME_CTRL_CONNECTING]  = "connecting",
                 [NVME_CTRL_DELETING]    = "deleting",
                 [NVME_CTRL_DEAD]        = "dead",
         };
@@ -2835,7 +2844,7 @@ out:
 }
 
 static int nvme_init_ns_head(struct nvme_ns *ns, unsigned nsid,
-                struct nvme_id_ns *id, bool *new)
+                struct nvme_id_ns *id)
 {
         struct nvme_ctrl *ctrl = ns->ctrl;
         bool is_shared = id->nmic & (1 << 0);
@@ -2851,8 +2860,6 @@ static int nvme_init_ns_head(struct nvme_ns *ns, unsigned nsid,
                         ret = PTR_ERR(head);
                         goto out_unlock;
                 }
-
-                *new = true;
         } else {
                 struct nvme_ns_ids ids;
 
@@ -2864,8 +2871,6 @@ static int nvme_init_ns_head(struct nvme_ns *ns, unsigned nsid,
                         ret = -EINVAL;
                         goto out_unlock;
                 }
-
-                *new = false;
         }
 
         list_add_tail(&ns->siblings, &head->list);
@@ -2936,7 +2941,6 @@ static void nvme_alloc_ns(struct nvme_ctrl *ctrl, unsigned nsid)
         struct nvme_id_ns *id;
         char disk_name[DISK_NAME_LEN];
         int node = dev_to_node(ctrl->dev), flags = GENHD_FL_EXT_DEVT;
-        bool new = true;
 
         ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
         if (!ns)
@@ -2962,7 +2966,7 @@ static void nvme_alloc_ns(struct nvme_ctrl *ctrl, unsigned nsid)
         if (id->ncap == 0)
                 goto out_free_id;
 
-        if (nvme_init_ns_head(ns, nsid, id, &new))
+        if (nvme_init_ns_head(ns, nsid, id))
                 goto out_free_id;
         nvme_setup_streams_ns(ctrl, ns);
         
@@ -3028,8 +3032,7 @@ static void nvme_alloc_ns(struct nvme_ctrl *ctrl, unsigned nsid)
                 pr_warn("%s: failed to register lightnvm sysfs group for identification\n",
                         ns->disk->disk_name);
 
-        if (new)
-                nvme_mpath_add_disk(ns->head);
+        nvme_mpath_add_disk(ns->head);
         nvme_mpath_add_disk_links(ns);
         return;
  out_unlink_ns:
diff --git a/drivers/nvme/host/fabrics.c b/drivers/nvme/host/fabrics.c
index 5dd4ceefed8f..a1c58e35075e 100644
--- a/drivers/nvme/host/fabrics.c
+++ b/drivers/nvme/host/fabrics.c
@@ -493,7 +493,7 @@ EXPORT_SYMBOL_GPL(nvmf_should_reconnect);
  */
 int nvmf_register_transport(struct nvmf_transport_ops *ops)
 {
-        if (!ops->create_ctrl || !ops->module)
+        if (!ops->create_ctrl)
                 return -EINVAL;
 
         down_write(&nvmf_transports_rwsem);
diff --git a/drivers/nvme/host/fabrics.h b/drivers/nvme/host/fabrics.h
index 25b19f722f5b..a3145d90c1d2 100644
--- a/drivers/nvme/host/fabrics.h
+++ b/drivers/nvme/host/fabrics.h
@@ -171,13 +171,14 @@ static inline blk_status_t nvmf_check_init_req(struct nvme_ctrl *ctrl,
             cmd->common.opcode != nvme_fabrics_command ||
             cmd->fabrics.fctype != nvme_fabrics_type_connect) {
                 /*
-                 * Reconnecting state means transport disruption, which can take
-                 * a long time and even might fail permanently, fail fast to
-                 * give upper layers a chance to failover.
+                 * Connecting state means transport disruption or initial
+                 * establishment, which can take a long time and even might
+                 * fail permanently, fail fast to give upper layers a chance
+                 * to failover.
                  * Deleting state means that the ctrl will never accept commands
                  * again, fail it permanently.
                  */
-                if (ctrl->state == NVME_CTRL_RECONNECTING ||
+                if (ctrl->state == NVME_CTRL_CONNECTING ||
                     ctrl->state == NVME_CTRL_DELETING) {
                         nvme_req(rq)->status = NVME_SC_ABORT_REQ;
                         return BLK_STS_IOERR;
diff --git a/drivers/nvme/host/fc.c b/drivers/nvme/host/fc.c
index b856d7c919d2..7f51f8414b97 100644
--- a/drivers/nvme/host/fc.c
+++ b/drivers/nvme/host/fc.c
@@ -55,9 +55,7 @@ struct nvme_fc_queue {
 
 enum nvme_fcop_flags {
         FCOP_FLAGS_TERMIO       = (1 << 0),
-        FCOP_FLAGS_RELEASED     = (1 << 1),
-        FCOP_FLAGS_COMPLETE     = (1 << 2),
-        FCOP_FLAGS_AEN          = (1 << 3),
+        FCOP_FLAGS_AEN          = (1 << 1),
 };
 
 struct nvmefc_ls_req_op {
@@ -532,7 +530,7 @@ nvme_fc_resume_controller(struct nvme_fc_ctrl *ctrl)
 {
         switch (ctrl->ctrl.state) {
         case NVME_CTRL_NEW:
-        case NVME_CTRL_RECONNECTING:
+        case NVME_CTRL_CONNECTING:
                 /*
                  * As all reconnects were suppressed, schedule a
                  * connect.
@@ -777,7 +775,7 @@ nvme_fc_ctrl_connectivity_loss(struct nvme_fc_ctrl *ctrl)
                 }
                 break;
 
-        case NVME_CTRL_RECONNECTING:
+        case NVME_CTRL_CONNECTING:
                 /*
                  * The association has already been terminated and the
                  * controller is attempting reconnects.  No need to do anything
@@ -1470,7 +1468,6 @@ nvme_fc_xmt_disconnect_assoc(struct nvme_fc_ctrl *ctrl)
 
 /* *********************** NVME Ctrl Routines **************************** */
 
-static void __nvme_fc_final_op_cleanup(struct request *rq);
 static void nvme_fc_error_recovery(struct nvme_fc_ctrl *ctrl, char *errmsg);
 
 static int
@@ -1512,13 +1509,19 @@ nvme_fc_exit_request(struct blk_mq_tag_set *set, struct request *rq,
 static int
 __nvme_fc_abort_op(struct nvme_fc_ctrl *ctrl, struct nvme_fc_fcp_op *op)
 {
-        int state;
+        unsigned long flags;
+        int opstate;
+
+        spin_lock_irqsave(&ctrl->lock, flags);
+        opstate = atomic_xchg(&op->state, FCPOP_STATE_ABORTED);
+        if (opstate != FCPOP_STATE_ACTIVE)
+                atomic_set(&op->state, opstate);
+        else if (ctrl->flags & FCCTRL_TERMIO)
+                ctrl->iocnt++;
+        spin_unlock_irqrestore(&ctrl->lock, flags);
 
-        state = atomic_xchg(&op->state, FCPOP_STATE_ABORTED);
-        if (state != FCPOP_STATE_ACTIVE) {
-                atomic_set(&op->state, state);
+        if (opstate != FCPOP_STATE_ACTIVE)
                 return -ECANCELED;
-        }
 
         ctrl->lport->ops->fcp_abort(&ctrl->lport->localport,
                                         &ctrl->rport->remoteport,
@@ -1532,60 +1535,26 @@ static void
 nvme_fc_abort_aen_ops(struct nvme_fc_ctrl *ctrl)
 {
         struct nvme_fc_fcp_op *aen_op = ctrl->aen_ops;
-        unsigned long flags;
-        int i, ret;
-
-        for (i = 0; i < NVME_NR_AEN_COMMANDS; i++, aen_op++) {
-                if (atomic_read(&aen_op->state) != FCPOP_STATE_ACTIVE)
-                        continue;
-
-                spin_lock_irqsave(&ctrl->lock, flags);
-                if (ctrl->flags & FCCTRL_TERMIO) {
-                        ctrl->iocnt++;
-                        aen_op->flags |= FCOP_FLAGS_TERMIO;
-                }
-                spin_unlock_irqrestore(&ctrl->lock, flags);
-
-                ret = __nvme_fc_abort_op(ctrl, aen_op);
-                if (ret) {
-                        /*
-                         * if __nvme_fc_abort_op failed the io wasn't
-                         * active. Thus this call path is running in
-                         * parallel to the io complete. Treat as non-error.
-                         */
+        int i;
 
-                        /* back out the flags/counters */
-                        spin_lock_irqsave(&ctrl->lock, flags);
-                        if (ctrl->flags & FCCTRL_TERMIO)
-                                ctrl->iocnt--;
-                        aen_op->flags &= ~FCOP_FLAGS_TERMIO;
-                        spin_unlock_irqrestore(&ctrl->lock, flags);
-                        return;
-                }
-        }
+        for (i = 0; i < NVME_NR_AEN_COMMANDS; i++, aen_op++)
+                __nvme_fc_abort_op(ctrl, aen_op);
 }
 
-static inline int
+static inline void
 __nvme_fc_fcpop_chk_teardowns(struct nvme_fc_ctrl *ctrl,
-                struct nvme_fc_fcp_op *op)
+                struct nvme_fc_fcp_op *op, int opstate)
 {
         unsigned long flags;
-        bool complete_rq = false;
 
-        spin_lock_irqsave(&ctrl->lock, flags);
-        if (unlikely(op->flags & FCOP_FLAGS_TERMIO)) {
+        if (opstate == FCPOP_STATE_ABORTED) {
+                spin_lock_irqsave(&ctrl->lock, flags);
                 if (ctrl->flags & FCCTRL_TERMIO) {
                         if (!--ctrl->iocnt)
                                 wake_up(&ctrl->ioabort_wait);
                 }
+                spin_unlock_irqrestore(&ctrl->lock, flags);
         }
-        if (op->flags & FCOP_FLAGS_RELEASED)
-                complete_rq = true;
-        else
-                op->flags |= FCOP_FLAGS_COMPLETE;
-        spin_unlock_irqrestore(&ctrl->lock, flags);
-
-        return complete_rq;
 }
 
 static void
@@ -1601,6 +1570,7 @@ nvme_fc_fcpio_done(struct nvmefc_fcp_req *req)
         __le16 status = cpu_to_le16(NVME_SC_SUCCESS << 1);
         union nvme_result result;
         bool terminate_assoc = true;
+        int opstate;
 
         /*
          * WARNING:
@@ -1639,11 +1609,12 @@ nvme_fc_fcpio_done(struct nvmefc_fcp_req *req)
          * association to be terminated.
          */
 
+        opstate = atomic_xchg(&op->state, FCPOP_STATE_COMPLETE);
+
         fc_dma_sync_single_for_cpu(ctrl->lport->dev, op->fcp_req.rspdma,
                                 sizeof(op->rsp_iu), DMA_FROM_DEVICE);
 
-        if (atomic_read(&op->state) == FCPOP_STATE_ABORTED ||
-                        op->flags & FCOP_FLAGS_TERMIO)
+        if (opstate == FCPOP_STATE_ABORTED)
                 status = cpu_to_le16(NVME_SC_ABORT_REQ << 1);
         else if (freq->status)
                 status = cpu_to_le16(NVME_SC_INTERNAL << 1);
@@ -1708,7 +1679,7 @@ nvme_fc_fcpio_done(struct nvmefc_fcp_req *req)
 done:
         if (op->flags & FCOP_FLAGS_AEN) {
                 nvme_complete_async_event(&queue->ctrl->ctrl, status, &result);
-                __nvme_fc_fcpop_chk_teardowns(ctrl, op);
+                __nvme_fc_fcpop_chk_teardowns(ctrl, op, opstate);
                 atomic_set(&op->state, FCPOP_STATE_IDLE);
                 op->flags = FCOP_FLAGS_AEN;     /* clear other flags */
                 nvme_fc_ctrl_put(ctrl);
@@ -1722,13 +1693,11 @@ done:
         if (status &&
             (blk_queue_dying(rq->q) ||
              ctrl->ctrl.state == NVME_CTRL_NEW ||
-             ctrl->ctrl.state == NVME_CTRL_RECONNECTING))
+             ctrl->ctrl.state == NVME_CTRL_CONNECTING))
                 status |= cpu_to_le16(NVME_SC_DNR << 1);
 
-        if (__nvme_fc_fcpop_chk_teardowns(ctrl, op))
-                __nvme_fc_final_op_cleanup(rq);
-        else
-                nvme_end_request(rq, status, result);
+        __nvme_fc_fcpop_chk_teardowns(ctrl, op, opstate);
+        nvme_end_request(rq, status, result);
 
 check_error:
         if (terminate_assoc)
@@ -2415,46 +2384,16 @@ nvme_fc_submit_async_event(struct nvme_ctrl *arg)
 }
 
 static void
-__nvme_fc_final_op_cleanup(struct request *rq)
+nvme_fc_complete_rq(struct request *rq)
 {
         struct nvme_fc_fcp_op *op = blk_mq_rq_to_pdu(rq);
         struct nvme_fc_ctrl *ctrl = op->ctrl;
 
         atomic_set(&op->state, FCPOP_STATE_IDLE);
-        op->flags &= ~(FCOP_FLAGS_TERMIO | FCOP_FLAGS_RELEASED |
-                        FCOP_FLAGS_COMPLETE);
 
         nvme_fc_unmap_data(ctrl, rq, op);
         nvme_complete_rq(rq);
         nvme_fc_ctrl_put(ctrl);
-
-}
-
-static void
-nvme_fc_complete_rq(struct request *rq)
-{
-        struct nvme_fc_fcp_op *op = blk_mq_rq_to_pdu(rq);
-        struct nvme_fc_ctrl *ctrl = op->ctrl;
-        unsigned long flags;
-        bool completed = false;
-
-        /*
-         * the core layer, on controller resets after calling
-         * nvme_shutdown_ctrl(), calls complete_rq without our
-         * calling blk_mq_complete_request(), thus there may still
-         * be live i/o outstanding with the LLDD. Means transport has
-         * to track complete calls vs fcpio_done calls to know what
-         * path to take on completes and dones.
-         */
-        spin_lock_irqsave(&ctrl->lock, flags);
-        if (op->flags & FCOP_FLAGS_COMPLETE)
-                completed = true;
-        else
-                op->flags |= FCOP_FLAGS_RELEASED;
-        spin_unlock_irqrestore(&ctrl->lock, flags);
-
-        if (completed)
-                __nvme_fc_final_op_cleanup(rq);
 }
 
 /*
@@ -2476,35 +2415,11 @@ nvme_fc_terminate_exchange(struct request *req, void *data, bool reserved)
         struct nvme_ctrl *nctrl = data;
         struct nvme_fc_ctrl *ctrl = to_fc_ctrl(nctrl);
         struct nvme_fc_fcp_op *op = blk_mq_rq_to_pdu(req);
-        unsigned long flags;
-        int status;
 
         if (!blk_mq_request_started(req))
                 return;
 
-        spin_lock_irqsave(&ctrl->lock, flags);
-        if (ctrl->flags & FCCTRL_TERMIO) {
-                ctrl->iocnt++;
-                op->flags |= FCOP_FLAGS_TERMIO;
-        }
-        spin_unlock_irqrestore(&ctrl->lock, flags);
-
-        status = __nvme_fc_abort_op(ctrl, op);
-        if (status) {
-                /*
-                 * if __nvme_fc_abort_op failed the io wasn't
-                 * active. Thus this call path is running in
-                 * parallel to the io complete. Treat as non-error.
-                 */
-
-                /* back out the flags/counters */
-                spin_lock_irqsave(&ctrl->lock, flags);
-                if (ctrl->flags & FCCTRL_TERMIO)
-                        ctrl->iocnt--;
-                op->flags &= ~FCOP_FLAGS_TERMIO;
-                spin_unlock_irqrestore(&ctrl->lock, flags);
-                return;
-        }
+        __nvme_fc_abort_op(ctrl, op);
 }
 
 
@@ -2943,7 +2858,7 @@ nvme_fc_reconnect_or_delete(struct nvme_fc_ctrl *ctrl, int status)
         unsigned long recon_delay = ctrl->ctrl.opts->reconnect_delay * HZ;
         bool recon = true;
 
-        if (ctrl->ctrl.state != NVME_CTRL_RECONNECTING)
+        if (ctrl->ctrl.state != NVME_CTRL_CONNECTING)
                 return;
 
         if (portptr->port_state == FC_OBJSTATE_ONLINE)
@@ -2991,10 +2906,10 @@ nvme_fc_reset_ctrl_work(struct work_struct *work)
         /* will block will waiting for io to terminate */
         nvme_fc_delete_association(ctrl);
 
-        if (!nvme_change_ctrl_state(&ctrl->ctrl, NVME_CTRL_RECONNECTING)) {
+        if (!nvme_change_ctrl_state(&ctrl->ctrl, NVME_CTRL_CONNECTING)) {
                 dev_err(ctrl->ctrl.device,
                         "NVME-FC{%d}: error_recovery: Couldn't change state "
-                        "to RECONNECTING\n", ctrl->cnum);
+                        "to CONNECTING\n", ctrl->cnum);
                 return;
         }
 
@@ -3195,7 +3110,7 @@ nvme_fc_init_ctrl(struct device *dev, struct nvmf_ctrl_options *opts,
          * transport errors (frame drop, LS failure) inherently must kill
          * the association. The transport is coded so that any command used
          * to create the association (prior to a LIVE state transition
-         * while NEW or RECONNECTING) will fail if it completes in error or
+         * while NEW or CONNECTING) will fail if it completes in error or
          * times out.
          *
          * As such: as the connect request was mostly likely due to a
diff --git a/drivers/nvme/host/multipath.c b/drivers/nvme/host/multipath.c
index 3b211d9e58b8..b7e5c6db4d92 100644
--- a/drivers/nvme/host/multipath.c
+++ b/drivers/nvme/host/multipath.c
@@ -198,11 +198,16 @@ void nvme_mpath_add_disk(struct nvme_ns_head *head)
 {
         if (!head->disk)
                 return;
-        device_add_disk(&head->subsys->dev, head->disk);
-        if (sysfs_create_group(&disk_to_dev(head->disk)->kobj,
-                        &nvme_ns_id_attr_group))
-                pr_warn("%s: failed to create sysfs group for identification\n",
-                        head->disk->disk_name);
+
+        mutex_lock(&head->subsys->lock);
+        if (!(head->disk->flags & GENHD_FL_UP)) {
+                device_add_disk(&head->subsys->dev, head->disk);
+                if (sysfs_create_group(&disk_to_dev(head->disk)->kobj,
+                                &nvme_ns_id_attr_group))
+                        pr_warn("%s: failed to create sysfs group for identification\n",
+                                head->disk->disk_name);
+        }
+        mutex_unlock(&head->subsys->lock);
 }
 
 void nvme_mpath_add_disk_links(struct nvme_ns *ns)
diff --git a/drivers/nvme/host/nvme.h b/drivers/nvme/host/nvme.h
index 8e4550fa08f8..0521e4707d1c 100644
--- a/drivers/nvme/host/nvme.h
+++ b/drivers/nvme/host/nvme.h
@@ -123,7 +123,7 @@ enum nvme_ctrl_state {
         NVME_CTRL_LIVE,
         NVME_CTRL_ADMIN_ONLY,    /* Only admin queue live */
         NVME_CTRL_RESETTING,
-        NVME_CTRL_RECONNECTING,
+        NVME_CTRL_CONNECTING,
         NVME_CTRL_DELETING,
         NVME_CTRL_DEAD,
 };
@@ -183,6 +183,7 @@ struct nvme_ctrl {
         struct work_struct scan_work;
         struct work_struct async_event_work;
         struct delayed_work ka_work;
+        struct nvme_command ka_cmd;
         struct work_struct fw_act_work;
 
         /* Power saving configuration */
diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
index 6fe7af00a1f4..5933a5c732e8 100644
--- a/drivers/nvme/host/pci.c
+++ b/drivers/nvme/host/pci.c
@@ -1141,7 +1141,7 @@ static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
         /* If there is a reset/reinit ongoing, we shouldn't reset again. */
         switch (dev->ctrl.state) {
         case NVME_CTRL_RESETTING:
-        case NVME_CTRL_RECONNECTING:
+        case NVME_CTRL_CONNECTING:
                 return false;
         default:
                 break;
@@ -1215,13 +1215,17 @@ static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
          * cancellation error. All outstanding requests are completed on
          * shutdown, so we return BLK_EH_HANDLED.
          */
-        if (dev->ctrl.state == NVME_CTRL_RESETTING) {
+        switch (dev->ctrl.state) {
+        case NVME_CTRL_CONNECTING:
+        case NVME_CTRL_RESETTING:
                 dev_warn(dev->ctrl.device,
                          "I/O %d QID %d timeout, disable controller\n",
                          req->tag, nvmeq->qid);
                 nvme_dev_disable(dev, false);
                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
                 return BLK_EH_HANDLED;
+        default:
+                break;
         }
 
         /*
@@ -1364,18 +1368,14 @@ static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
                                 int qid, int depth)
 {
-        if (qid && dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
-                unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
-                                                      dev->ctrl.page_size);
-                nvmeq->sq_dma_addr = dev->cmb_bus_addr + offset;
-                nvmeq->sq_cmds_io = dev->cmb + offset;
-        } else {
-                nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
-                                        &nvmeq->sq_dma_addr, GFP_KERNEL);
-                if (!nvmeq->sq_cmds)
-                        return -ENOMEM;
-        }
+        /* CMB SQEs will be mapped before creation */
+        if (qid && dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS))
+                return 0;
 
+        nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
+                                            &nvmeq->sq_dma_addr, GFP_KERNEL);
+        if (!nvmeq->sq_cmds)
+                return -ENOMEM;
         return 0;
 }
 
@@ -1449,10 +1449,17 @@ static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
         struct nvme_dev *dev = nvmeq->dev;
         int result;
 
+        if (dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
+                unsigned offset = (qid - 1) * roundup(SQ_SIZE(nvmeq->q_depth),
+                                                      dev->ctrl.page_size);
+                nvmeq->sq_dma_addr = dev->cmb_bus_addr + offset;
+                nvmeq->sq_cmds_io = dev->cmb + offset;
+        }
+
         nvmeq->cq_vector = qid - 1;
         result = adapter_alloc_cq(dev, qid, nvmeq);
         if (result < 0)
-                return result;
+                goto release_vector;
 
         result = adapter_alloc_sq(dev, qid, nvmeq);
         if (result < 0)
@@ -1466,9 +1473,12 @@ static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
         return result;
 
  release_sq:
+        dev->online_queues--;
         adapter_delete_sq(dev, qid);
  release_cq:
         adapter_delete_cq(dev, qid);
+ release_vector:
+        nvmeq->cq_vector = -1;
         return result;
 }
 
@@ -2288,12 +2298,12 @@ static void nvme_reset_work(struct work_struct *work)
                 nvme_dev_disable(dev, false);
 
         /*
-         * Introduce RECONNECTING state from nvme-fc/rdma transports to mark the
+         * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
          * initializing procedure here.
          */
-        if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RECONNECTING)) {
+        if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
                 dev_warn(dev->ctrl.device,
-                        "failed to mark controller RECONNECTING\n");
+                        "failed to mark controller CONNECTING\n");
                 goto out;
         }
 
diff --git a/drivers/nvme/host/rdma.c b/drivers/nvme/host/rdma.c
index 2bc059f7d73c..4d84a73ee12d 100644
--- a/drivers/nvme/host/rdma.c
+++ b/drivers/nvme/host/rdma.c
@@ -887,7 +887,7 @@ free_ctrl:
 static void nvme_rdma_reconnect_or_remove(struct nvme_rdma_ctrl *ctrl)
 {
         /* If we are resetting/deleting then do nothing */
-        if (ctrl->ctrl.state != NVME_CTRL_RECONNECTING) {
+        if (ctrl->ctrl.state != NVME_CTRL_CONNECTING) {
                 WARN_ON_ONCE(ctrl->ctrl.state == NVME_CTRL_NEW ||
                         ctrl->ctrl.state == NVME_CTRL_LIVE);
                 return;
@@ -973,7 +973,7 @@ static void nvme_rdma_error_recovery_work(struct work_struct *work)
         blk_mq_unquiesce_queue(ctrl->ctrl.admin_q);
         nvme_start_queues(&ctrl->ctrl);
 
-        if (!nvme_change_ctrl_state(&ctrl->ctrl, NVME_CTRL_RECONNECTING)) {
+        if (!nvme_change_ctrl_state(&ctrl->ctrl, NVME_CTRL_CONNECTING)) {
                 /* state change failure should never happen */
                 WARN_ON_ONCE(1);
                 return;
@@ -1051,7 +1051,7 @@ static void nvme_rdma_unmap_data(struct nvme_rdma_queue *queue,
         struct nvme_rdma_device *dev = queue->device;
         struct ib_device *ibdev = dev->dev;
 
-        if (!blk_rq_bytes(rq))
+        if (!blk_rq_payload_bytes(rq))
                 return;
 
         if (req->mr) {
@@ -1166,7 +1166,7 @@ static int nvme_rdma_map_data(struct nvme_rdma_queue *queue,
 
         c->common.flags |= NVME_CMD_SGL_METABUF;
 
-        if (!blk_rq_bytes(rq))
+        if (!blk_rq_payload_bytes(rq))
                 return nvme_rdma_set_sg_null(c);
 
         req->sg_table.sgl = req->first_sgl;
@@ -1756,7 +1756,7 @@ static void nvme_rdma_reset_ctrl_work(struct work_struct *work)
         nvme_stop_ctrl(&ctrl->ctrl);
         nvme_rdma_shutdown_ctrl(ctrl, false);
 
-        if (!nvme_change_ctrl_state(&ctrl->ctrl, NVME_CTRL_RECONNECTING)) {
+        if (!nvme_change_ctrl_state(&ctrl->ctrl, NVME_CTRL_CONNECTING)) {
                 /* state change failure should never happen */
                 WARN_ON_ONCE(1);
                 return;
@@ -1784,11 +1784,8 @@ static void nvme_rdma_reset_ctrl_work(struct work_struct *work)
         return;
 
 out_fail:
-        dev_warn(ctrl->ctrl.device, "Removing after reset failure\n");
-        nvme_remove_namespaces(&ctrl->ctrl);
-        nvme_rdma_shutdown_ctrl(ctrl, true);
-        nvme_uninit_ctrl(&ctrl->ctrl);
-        nvme_put_ctrl(&ctrl->ctrl);
+        ++ctrl->ctrl.nr_reconnects;
+        nvme_rdma_reconnect_or_remove(ctrl);
 }
 
 static const struct nvme_ctrl_ops nvme_rdma_ctrl_ops = {
@@ -1942,6 +1939,9 @@ static struct nvme_ctrl *nvme_rdma_create_ctrl(struct device *dev,
         if (!ctrl->queues)
                 goto out_uninit_ctrl;
 
+        changed = nvme_change_ctrl_state(&ctrl->ctrl, NVME_CTRL_CONNECTING);
+        WARN_ON_ONCE(!changed);
+
         ret = nvme_rdma_configure_admin_queue(ctrl, true);
         if (ret)
                 goto out_kfree_queues;
diff --git a/drivers/nvme/target/core.c b/drivers/nvme/target/core.c
index 0bd737117a80..a78029e4e5f4 100644
--- a/drivers/nvme/target/core.c
+++ b/drivers/nvme/target/core.c
@@ -520,9 +520,12 @@ bool nvmet_req_init(struct nvmet_req *req, struct nvmet_cq *cq,
                 goto fail;
         }
 
-        /* either variant of SGLs is fine, as we don't support metadata */
-        if (unlikely((flags & NVME_CMD_SGL_ALL) != NVME_CMD_SGL_METABUF &&
-                     (flags & NVME_CMD_SGL_ALL) != NVME_CMD_SGL_METASEG)) {
+        /*
+         * For fabrics, PSDT field shall describe metadata pointer (MPTR) that
+         * contains an address of a single contiguous physical buffer that is
+         * byte aligned.
+         */
+        if (unlikely((flags & NVME_CMD_SGL_ALL) != NVME_CMD_SGL_METABUF)) {
                 status = NVME_SC_INVALID_FIELD | NVME_SC_DNR;
                 goto fail;
         }
diff --git a/drivers/nvme/target/io-cmd.c b/drivers/nvme/target/io-cmd.c
index 0a4372a016f2..28bbdff4a88b 100644
--- a/drivers/nvme/target/io-cmd.c
+++ b/drivers/nvme/target/io-cmd.c
@@ -105,10 +105,13 @@ static void nvmet_execute_flush(struct nvmet_req *req)
 static u16 nvmet_discard_range(struct nvmet_ns *ns,
                 struct nvme_dsm_range *range, struct bio **bio)
 {
-        if (__blkdev_issue_discard(ns->bdev,
+        int ret;
+
+        ret = __blkdev_issue_discard(ns->bdev,
                         le64_to_cpu(range->slba) << (ns->blksize_shift - 9),
                         le32_to_cpu(range->nlb) << (ns->blksize_shift - 9),
-                        GFP_KERNEL, 0, bio))
+                        GFP_KERNEL, 0, bio);
+        if (ret && ret != -EOPNOTSUPP)
                 return NVME_SC_INTERNAL | NVME_SC_DNR;
         return 0;
 }
diff --git a/drivers/nvme/target/loop.c b/drivers/nvme/target/loop.c
index 7991ec3a17db..861d1509b22b 100644
--- a/drivers/nvme/target/loop.c
+++ b/drivers/nvme/target/loop.c
@@ -184,7 +184,7 @@ static blk_status_t nvme_loop_queue_rq(struct blk_mq_hw_ctx *hctx,
                 return BLK_STS_OK;
         }
 
-        if (blk_rq_bytes(req)) {
+        if (blk_rq_payload_bytes(req)) {
                 iod->sg_table.sgl = iod->first_sgl;
                 if (sg_alloc_table_chained(&iod->sg_table,
                                 blk_rq_nr_phys_segments(req),
@@ -193,7 +193,7 @@ static blk_status_t nvme_loop_queue_rq(struct blk_mq_hw_ctx *hctx,
 
                 iod->req.sg = iod->sg_table.sgl;
                 iod->req.sg_cnt = blk_rq_map_sg(req->q, req, iod->sg_table.sgl);
-                iod->req.transfer_len = blk_rq_bytes(req);
+                iod->req.transfer_len = blk_rq_payload_bytes(req);
         }
 
         blk_mq_start_request(req);
diff --git a/drivers/of/property.c b/drivers/of/property.c
index 36ed84e26d9c..f46828e3b082 100644
--- a/drivers/of/property.c
+++ b/drivers/of/property.c
@@ -977,11 +977,11 @@ static int of_fwnode_graph_parse_endpoint(const struct fwnode_handle *fwnode,
         return 0;
 }
 
-static void *
+static const void *
 of_fwnode_device_get_match_data(const struct fwnode_handle *fwnode,
                                 const struct device *dev)
 {
-        return (void *)of_device_get_match_data(dev);
+        return of_device_get_match_data(dev);
 }
 
 const struct fwnode_operations of_fwnode_ops = {
diff --git a/drivers/opp/cpu.c b/drivers/opp/cpu.c
index 2d87bc1adf38..0c0910709435 100644
--- a/drivers/opp/cpu.c
+++ b/drivers/opp/cpu.c
@@ -55,7 +55,7 @@ int dev_pm_opp_init_cpufreq_table(struct device *dev,
         if (max_opps <= 0)
                 return max_opps ? max_opps : -ENODATA;
 
-        freq_table = kcalloc((max_opps + 1), sizeof(*freq_table), GFP_ATOMIC);
+        freq_table = kcalloc((max_opps + 1), sizeof(*freq_table), GFP_KERNEL);
         if (!freq_table)
                 return -ENOMEM;
 
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index fc734014206f..8b14bd326d4a 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -3419,22 +3419,29 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
 
 static void quirk_chelsio_extend_vpd(struct pci_dev *dev)
 {
-        pci_set_vpd_size(dev, 8192);
-}
-
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x20, quirk_chelsio_extend_vpd);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x21, quirk_chelsio_extend_vpd);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x22, quirk_chelsio_extend_vpd);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x23, quirk_chelsio_extend_vpd);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x24, quirk_chelsio_extend_vpd);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x25, quirk_chelsio_extend_vpd);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x26, quirk_chelsio_extend_vpd);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x30, quirk_chelsio_extend_vpd);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x31, quirk_chelsio_extend_vpd);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x32, quirk_chelsio_extend_vpd);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x35, quirk_chelsio_extend_vpd);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x36, quirk_chelsio_extend_vpd);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x37, quirk_chelsio_extend_vpd);
+        int chip = (dev->device & 0xf000) >> 12;
+        int func = (dev->device & 0x0f00) >>  8;
+        int prod = (dev->device & 0x00ff) >>  0;
+
+        /*
+         * If this is a T3-based adapter, there's a 1KB VPD area at offset
+         * 0xc00 which contains the preferred VPD values.  If this is a T4 or
+         * later based adapter, the special VPD is at offset 0x400 for the
+         * Physical Functions (the SR-IOV Virtual Functions have no VPD
+         * Capabilities).  The PCI VPD Access core routines will normally
+         * compute the size of the VPD by parsing the VPD Data Structure at
+         * offset 0x000.  This will result in silent failures when attempting
+         * to accesses these other VPD areas which are beyond those computed
+         * limits.
+         */
+        if (chip == 0x0 && prod >= 0x20)
+                pci_set_vpd_size(dev, 8192);
+        else if (chip >= 0x4 && func < 0x8)
+                pci_set_vpd_size(dev, 2048);
+}
+
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
+                        quirk_chelsio_extend_vpd);
 
 #ifdef CONFIG_ACPI
 /*
diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c
index 369d48d6c6f1..365447240d95 100644
--- a/drivers/pci/setup-res.c
+++ b/drivers/pci/setup-res.c
@@ -401,6 +401,10 @@ void pci_release_resource(struct pci_dev *dev, int resno)
         struct resource *res = dev->resource + resno;
 
         pci_info(dev, "BAR %d: releasing %pR\n", resno, res);
+
+        if (!res->parent)
+                return;
+
         release_resource(res);
         res->end = resource_size(res) - 1;
         res->start = 0;
diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c
index 7bc5eee96b31..0c2ed11c0603 100644
--- a/drivers/perf/arm_pmu.c
+++ b/drivers/perf/arm_pmu.c
@@ -17,7 +17,6 @@
 #include <linux/export.h>
 #include <linux/kernel.h>
 #include <linux/perf/arm_pmu.h>
-#include <linux/platform_device.h>
 #include <linux/slab.h>
 #include <linux/sched/clock.h>
 #include <linux/spinlock.h>
@@ -26,6 +25,9 @@
 
 #include <asm/irq_regs.h>
 
+static DEFINE_PER_CPU(struct arm_pmu *, cpu_armpmu);
+static DEFINE_PER_CPU(int, cpu_irq);
+
 static int
 armpmu_map_cache_event(const unsigned (*cache_map)
                                       [PERF_COUNT_HW_CACHE_MAX]
@@ -320,17 +322,9 @@ validate_group(struct perf_event *event)
         return 0;
 }
 
-static struct arm_pmu_platdata *armpmu_get_platdata(struct arm_pmu *armpmu)
-{
-        struct platform_device *pdev = armpmu->plat_device;
-
-        return pdev ? dev_get_platdata(&pdev->dev) : NULL;
-}
-
 static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
 {
         struct arm_pmu *armpmu;
-        struct arm_pmu_platdata *plat;
         int ret;
         u64 start_clock, finish_clock;
 
@@ -341,14 +335,11 @@ static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
          * dereference.
          */
         armpmu = *(void **)dev;
-
-        plat = armpmu_get_platdata(armpmu);
+        if (WARN_ON_ONCE(!armpmu))
+                return IRQ_NONE;
 
         start_clock = sched_clock();
-        if (plat && plat->handle_irq)
-                ret = plat->handle_irq(irq, armpmu, armpmu->handle_irq);
-        else
-                ret = armpmu->handle_irq(irq, armpmu);
+        ret = armpmu->handle_irq(irq, armpmu);
         finish_clock = sched_clock();
 
         perf_sample_event_took(finish_clock - start_clock);
@@ -531,54 +522,41 @@ int perf_num_counters(void)
 }
 EXPORT_SYMBOL_GPL(perf_num_counters);
 
-void armpmu_free_irq(struct arm_pmu *armpmu, int cpu)
+static int armpmu_count_irq_users(const int irq)
 {
-        struct pmu_hw_events __percpu *hw_events = armpmu->hw_events;
-        int irq = per_cpu(hw_events->irq, cpu);
+        int cpu, count = 0;
 
-        if (!cpumask_test_and_clear_cpu(cpu, &armpmu->active_irqs))
-                return;
-
-        if (irq_is_percpu_devid(irq)) {
-                free_percpu_irq(irq, &hw_events->percpu_pmu);
-                cpumask_clear(&armpmu->active_irqs);
-                return;
+        for_each_possible_cpu(cpu) {
+                if (per_cpu(cpu_irq, cpu) == irq)
+                        count++;
         }
 
-        free_irq(irq, per_cpu_ptr(&hw_events->percpu_pmu, cpu));
+        return count;
 }
 
-void armpmu_free_irqs(struct arm_pmu *armpmu)
+void armpmu_free_irq(int irq, int cpu)
 {
-        int cpu;
+        if (per_cpu(cpu_irq, cpu) == 0)
+                return;
+        if (WARN_ON(irq != per_cpu(cpu_irq, cpu)))
+                return;
+
+        if (!irq_is_percpu_devid(irq))
+                free_irq(irq, per_cpu_ptr(&cpu_armpmu, cpu));
+        else if (armpmu_count_irq_users(irq) == 1)
+                free_percpu_irq(irq, &cpu_armpmu);
 
-        for_each_cpu(cpu, &armpmu->supported_cpus)
-                armpmu_free_irq(armpmu, cpu);
+        per_cpu(cpu_irq, cpu) = 0;
 }
 
-int armpmu_request_irq(struct arm_pmu *armpmu, int cpu)
+int armpmu_request_irq(int irq, int cpu)
 {
         int err = 0;
-        struct pmu_hw_events __percpu *hw_events = armpmu->hw_events;
         const irq_handler_t handler = armpmu_dispatch_irq;
-        int irq = per_cpu(hw_events->irq, cpu);
         if (!irq)
                 return 0;
 
-        if (irq_is_percpu_devid(irq) && cpumask_empty(&armpmu->active_irqs)) {
-                err = request_percpu_irq(irq, handler, "arm-pmu",
-                                         &hw_events->percpu_pmu);
-        } else if (irq_is_percpu_devid(irq)) {
-                int other_cpu = cpumask_first(&armpmu->active_irqs);
-                int other_irq = per_cpu(hw_events->irq, other_cpu);
-
-                if (irq != other_irq) {
-                        pr_warn("mismatched PPIs detected.\n");
-                        err = -EINVAL;
-                        goto err_out;
-                }
-        } else {
-                struct arm_pmu_platdata *platdata = armpmu_get_platdata(armpmu);
+        if (!irq_is_percpu_devid(irq)) {
                 unsigned long irq_flags;
 
                 err = irq_force_affinity(irq, cpumask_of(cpu));
@@ -589,22 +567,22 @@ int armpmu_request_irq(struct arm_pmu *armpmu, int cpu)
                         goto err_out;
                 }
 
-                if (platdata && platdata->irq_flags) {
-                        irq_flags = platdata->irq_flags;
-                } else {
-                        irq_flags = IRQF_PERCPU |
-                                    IRQF_NOBALANCING |
-                                    IRQF_NO_THREAD;
-                }
+                irq_flags = IRQF_PERCPU |
+                            IRQF_NOBALANCING |
+                            IRQF_NO_THREAD;
 
+                irq_set_status_flags(irq, IRQ_NOAUTOEN);
                 err = request_irq(irq, handler, irq_flags, "arm-pmu",
-                                  per_cpu_ptr(&hw_events->percpu_pmu, cpu));
+                                  per_cpu_ptr(&cpu_armpmu, cpu));
+        } else if (armpmu_count_irq_users(irq) == 0) {
+                err = request_percpu_irq(irq, handler, "arm-pmu",
+                                         &cpu_armpmu);
         }
 
         if (err)
                 goto err_out;
 
-        cpumask_set_cpu(cpu, &armpmu->active_irqs);
+        per_cpu(cpu_irq, cpu) = irq;
         return 0;
 
 err_out:
@@ -612,19 +590,6 @@ err_out:
         return err;
 }
 
-int armpmu_request_irqs(struct arm_pmu *armpmu)
-{
-        int cpu, err;
-
-        for_each_cpu(cpu, &armpmu->supported_cpus) {
-                err = armpmu_request_irq(armpmu, cpu);
-                if (err)
-                        break;
-        }
-
-        return err;
-}
-
 static int armpmu_get_cpu_irq(struct arm_pmu *pmu, int cpu)
 {
         struct pmu_hw_events __percpu *hw_events = pmu->hw_events;
@@ -647,12 +612,14 @@ static int arm_perf_starting_cpu(unsigned int cpu, struct hlist_node *node)
         if (pmu->reset)
                 pmu->reset(pmu);
 
+        per_cpu(cpu_armpmu, cpu) = pmu;
+
         irq = armpmu_get_cpu_irq(pmu, cpu);
         if (irq) {
-                if (irq_is_percpu_devid(irq)) {
+                if (irq_is_percpu_devid(irq))
                         enable_percpu_irq(irq, IRQ_TYPE_NONE);
-                        return 0;
-                }
+                else
+                        enable_irq(irq);
         }
 
         return 0;
@@ -667,8 +634,14 @@ static int arm_perf_teardown_cpu(unsigned int cpu, struct hlist_node *node)
                 return 0;
 
         irq = armpmu_get_cpu_irq(pmu, cpu);
-        if (irq && irq_is_percpu_devid(irq))
-                disable_percpu_irq(irq);
+        if (irq) {
+                if (irq_is_percpu_devid(irq))
+                        disable_percpu_irq(irq);
+                else
+                        disable_irq(irq);
+        }
+
+        per_cpu(cpu_armpmu, cpu) = NULL;
 
         return 0;
 }
@@ -800,18 +773,18 @@ static void cpu_pmu_destroy(struct arm_pmu *cpu_pmu)
                                             &cpu_pmu->node);
 }
 
-struct arm_pmu *armpmu_alloc(void)
+static struct arm_pmu *__armpmu_alloc(gfp_t flags)
 {
         struct arm_pmu *pmu;
         int cpu;
 
-        pmu = kzalloc(sizeof(*pmu), GFP_KERNEL);
+        pmu = kzalloc(sizeof(*pmu), flags);
         if (!pmu) {
                 pr_info("failed to allocate PMU device!\n");
                 goto out;
         }
 
-        pmu->hw_events = alloc_percpu(struct pmu_hw_events);
+        pmu->hw_events = alloc_percpu_gfp(struct pmu_hw_events, flags);
         if (!pmu->hw_events) {
                 pr_info("failed to allocate per-cpu PMU data.\n");
                 goto out_free_pmu;
@@ -857,6 +830,17 @@ out:
         return NULL;
 }
 
+struct arm_pmu *armpmu_alloc(void)
+{
+        return __armpmu_alloc(GFP_KERNEL);
+}
+
+struct arm_pmu *armpmu_alloc_atomic(void)
+{
+        return __armpmu_alloc(GFP_ATOMIC);
+}
+
+
 void armpmu_free(struct arm_pmu *pmu)
 {
         free_percpu(pmu->hw_events);
diff --git a/drivers/perf/arm_pmu_acpi.c b/drivers/perf/arm_pmu_acpi.c
index 705f1a390e31..0f197516d708 100644
--- a/drivers/perf/arm_pmu_acpi.c
+++ b/drivers/perf/arm_pmu_acpi.c
@@ -11,6 +11,8 @@
 #include <linux/acpi.h>
 #include <linux/cpumask.h>
 #include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/irqdesc.h>
 #include <linux/percpu.h>
 #include <linux/perf/arm_pmu.h>
 
@@ -87,7 +89,13 @@ static int arm_pmu_acpi_parse_irqs(void)
                         pr_warn("No ACPI PMU IRQ for CPU%d\n", cpu);
                 }
 
+                /*
+                 * Log and request the IRQ so the core arm_pmu code can manage
+                 * it. We'll have to sanity-check IRQs later when we associate
+                 * them with their PMUs.
+                 */
                 per_cpu(pmu_irqs, cpu) = irq;
+                armpmu_request_irq(irq, cpu);
         }
 
         return 0;
@@ -127,7 +135,7 @@ static struct arm_pmu *arm_pmu_acpi_find_alloc_pmu(void)
                 return pmu;
         }
 
-        pmu = armpmu_alloc();
+        pmu = armpmu_alloc_atomic();
         if (!pmu) {
                 pr_warn("Unable to allocate PMU for CPU%d\n",
                         smp_processor_id());
@@ -140,6 +148,35 @@ static struct arm_pmu *arm_pmu_acpi_find_alloc_pmu(void)
 }
 
 /*
+ * Check whether the new IRQ is compatible with those already associated with
+ * the PMU (e.g. we don't have mismatched PPIs).
+ */
+static bool pmu_irq_matches(struct arm_pmu *pmu, int irq)
+{
+        struct pmu_hw_events __percpu *hw_events = pmu->hw_events;
+        int cpu;
+
+        if (!irq)
+                return true;
+
+        for_each_cpu(cpu, &pmu->supported_cpus) {
+                int other_irq = per_cpu(hw_events->irq, cpu);
+                if (!other_irq)
+                        continue;
+
+                if (irq == other_irq)
+                        continue;
+                if (!irq_is_percpu_devid(irq) && !irq_is_percpu_devid(other_irq))
+                        continue;
+
+                pr_warn("mismatched PPIs detected\n");
+                return false;
+        }
+
+        return true;
+}
+
+/*
  * This must run before the common arm_pmu hotplug logic, so that we can
  * associate a CPU and its interrupt before the common code tries to manage the
  * affinity and so on.
@@ -164,19 +201,14 @@ static int arm_pmu_acpi_cpu_starting(unsigned int cpu)
         if (!pmu)
                 return -ENOMEM;
 
-        cpumask_set_cpu(cpu, &pmu->supported_cpus);
-
         per_cpu(probed_pmus, cpu) = pmu;
 
-        /*
-         * Log and request the IRQ so the core arm_pmu code can manage it.  In
-         * some situations (e.g. mismatched PPIs), we may fail to request the
-         * IRQ. However, it may be too late for us to do anything about it.
-         * The common ARM PMU code will log a warning in this case.
-         */
-        hw_events = pmu->hw_events;
-        per_cpu(hw_events->irq, cpu) = irq;
-        armpmu_request_irq(pmu, cpu);
+        if (pmu_irq_matches(pmu, irq)) {
+                hw_events = pmu->hw_events;
+                per_cpu(hw_events->irq, cpu) = irq;
+        }
+
+        cpumask_set_cpu(cpu, &pmu->supported_cpus);
 
         /*
          * Ideally, we'd probe the PMU here when we find the first matching
@@ -247,11 +279,6 @@ static int arm_pmu_acpi_init(void)
         if (acpi_disabled)
                 return 0;
 
-        /*
-         * We can't request IRQs yet, since we don't know the cookie value
-         * until we know which CPUs share the same logical PMU. We'll handle
-         * that in arm_pmu_acpi_cpu_starting().
-         */
         ret = arm_pmu_acpi_parse_irqs();
         if (ret)
                 return ret;
diff --git a/drivers/perf/arm_pmu_platform.c b/drivers/perf/arm_pmu_platform.c
index 46501cc79fd7..7729eda5909d 100644
--- a/drivers/perf/arm_pmu_platform.c
+++ b/drivers/perf/arm_pmu_platform.c
@@ -127,13 +127,6 @@ static int pmu_parse_irqs(struct arm_pmu *pmu)
                         pdev->dev.of_node);
         }
 
-        /*
-         * Some platforms have all PMU IRQs OR'd into a single IRQ, with a
-         * special platdata function that attempts to demux them.
-         */
-        if (dev_get_platdata(&pdev->dev))
-                cpumask_setall(&pmu->supported_cpus);
-
         for (i = 0; i < num_irqs; i++) {
                 int cpu, irq;
 
@@ -164,6 +157,36 @@ static int pmu_parse_irqs(struct arm_pmu *pmu)
         return 0;
 }
 
+static int armpmu_request_irqs(struct arm_pmu *armpmu)
+{
+        struct pmu_hw_events __percpu *hw_events = armpmu->hw_events;
+        int cpu, err;
+
+        for_each_cpu(cpu, &armpmu->supported_cpus) {
+                int irq = per_cpu(hw_events->irq, cpu);
+                if (!irq)
+                        continue;
+
+                err = armpmu_request_irq(irq, cpu);
+                if (err)
+                        break;
+        }
+
+        return err;
+}
+
+static void armpmu_free_irqs(struct arm_pmu *armpmu)
+{
+        int cpu;
+        struct pmu_hw_events __percpu *hw_events = armpmu->hw_events;
+
+        for_each_cpu(cpu, &armpmu->supported_cpus) {
+                int irq = per_cpu(hw_events->irq, cpu);
+
+                armpmu_free_irq(irq, cpu);
+        }
+}
+
 int arm_pmu_device_probe(struct platform_device *pdev,
                          const struct of_device_id *of_table,
                          const struct pmu_probe_info *probe_table)
diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg.c b/drivers/pinctrl/meson/pinctrl-meson-axg.c
index 1fda9d6c7ea3..4b91ff74779b 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-axg.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-axg.c
@@ -716,7 +716,7 @@ static const char * const uart_b_groups[] = {
         "uart_tx_b_x", "uart_rx_b_x", "uart_cts_b_x", "uart_rts_b_x",
 };
 
-static const char * const uart_ao_b_gpioz_groups[] = {
+static const char * const uart_ao_b_z_groups[] = {
         "uart_ao_tx_b_z", "uart_ao_rx_b_z",
         "uart_ao_cts_b_z", "uart_ao_rts_b_z",
 };
@@ -855,7 +855,7 @@ static struct meson_pmx_func meson_axg_periphs_functions[] = {
         FUNCTION(nand),
         FUNCTION(uart_a),
         FUNCTION(uart_b),
-        FUNCTION(uart_ao_b_gpioz),
+        FUNCTION(uart_ao_b_z),
         FUNCTION(i2c0),
         FUNCTION(i2c1),
         FUNCTION(i2c2),
diff --git a/drivers/platform/x86/dell-laptop.c b/drivers/platform/x86/dell-laptop.c
index 2a68f59d2228..c52c6723374b 100644
--- a/drivers/platform/x86/dell-laptop.c
+++ b/drivers/platform/x86/dell-laptop.c
@@ -127,24 +127,6 @@ static const struct dmi_system_id dell_device_table[] __initconst = {
                 },
         },
         {
-                .matches = {
-                        DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
-                        DMI_MATCH(DMI_CHASSIS_TYPE, "30"), /*Tablet*/
-                },
-        },
-        {
-                .matches = {
-                        DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
-                        DMI_MATCH(DMI_CHASSIS_TYPE, "31"), /*Convertible*/
-                },
-        },
-        {
-                .matches = {
-                        DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
-                        DMI_MATCH(DMI_CHASSIS_TYPE, "32"), /*Detachable*/
-                },
-        },
-        {
                 .ident = "Dell Computer Corporation",
                 .matches = {
                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Computer Corporation"),
@@ -1279,7 +1261,7 @@ static int kbd_get_state(struct kbd_state *state)
         struct calling_interface_buffer buffer;
         int ret;
 
-        dell_fill_request(&buffer, 0, 0, 0, 0);
+        dell_fill_request(&buffer, 0x1, 0, 0, 0);
         ret = dell_send_request(&buffer,
                                 CLASS_KBD_BACKLIGHT, SELECT_KBD_BACKLIGHT);
         if (ret)
diff --git a/drivers/platform/x86/ideapad-laptop.c b/drivers/platform/x86/ideapad-laptop.c
index 5b6f18b18801..535199c9e6bc 100644
--- a/drivers/platform/x86/ideapad-laptop.c
+++ b/drivers/platform/x86/ideapad-laptop.c
@@ -113,7 +113,7 @@ MODULE_PARM_DESC(no_bt_rfkill, "No rfkill for bluetooth.");
 /*
  * ACPI Helpers
  */
-#define IDEAPAD_EC_TIMEOUT (100) /* in ms */
+#define IDEAPAD_EC_TIMEOUT (200) /* in ms */
 
 static int read_method_int(acpi_handle handle, const char *method, int *val)
 {
diff --git a/drivers/platform/x86/intel-hid.c b/drivers/platform/x86/intel-hid.c
index d1a01311c1a2..5e3df194723e 100644
--- a/drivers/platform/x86/intel-hid.c
+++ b/drivers/platform/x86/intel-hid.c
@@ -376,6 +376,7 @@ static int intel_hid_remove(struct platform_device *device)
 {
         acpi_handle handle = ACPI_HANDLE(&device->dev);
 
+        device_init_wakeup(&device->dev, false);
         acpi_remove_notify_handler(handle, ACPI_DEVICE_NOTIFY, notify_handler);
         intel_hid_set_enable(&device->dev, false);
         intel_button_array_enable(&device->dev, false);
diff --git a/drivers/platform/x86/intel-vbtn.c b/drivers/platform/x86/intel-vbtn.c
index b703d6f5b099..c13780b8dabb 100644
--- a/drivers/platform/x86/intel-vbtn.c
+++ b/drivers/platform/x86/intel-vbtn.c
@@ -7,6 +7,7 @@
  */
 
 #include <linux/acpi.h>
+#include <linux/dmi.h>
 #include <linux/input.h>
 #include <linux/input/sparse-keymap.h>
 #include <linux/kernel.h>
@@ -97,9 +98,35 @@ out_unknown:
         dev_dbg(&device->dev, "unknown event index 0x%x\n", event);
 }
 
-static int intel_vbtn_probe(struct platform_device *device)
+static void detect_tablet_mode(struct platform_device *device)
 {
+        const char *chassis_type = dmi_get_system_info(DMI_CHASSIS_TYPE);
+        struct intel_vbtn_priv *priv = dev_get_drvdata(&device->dev);
+        acpi_handle handle = ACPI_HANDLE(&device->dev);
         struct acpi_buffer vgbs_output = { ACPI_ALLOCATE_BUFFER, NULL };
+        union acpi_object *obj;
+        acpi_status status;
+        int m;
+
+        if (!(chassis_type && strcmp(chassis_type, "31") == 0))
+                goto out;
+
+        status = acpi_evaluate_object(handle, "VGBS", NULL, &vgbs_output);
+        if (ACPI_FAILURE(status))
+                goto out;
+
+        obj = vgbs_output.pointer;
+        if (!(obj && obj->type == ACPI_TYPE_INTEGER))
+                goto out;
+
+        m = !(obj->integer.value & TABLET_MODE_FLAG);
+        input_report_switch(priv->input_dev, SW_TABLET_MODE, m);
+out:
+        kfree(vgbs_output.pointer);
+}
+
+static int intel_vbtn_probe(struct platform_device *device)
+{
         acpi_handle handle = ACPI_HANDLE(&device->dev);
         struct intel_vbtn_priv *priv;
         acpi_status status;
@@ -122,22 +149,7 @@ static int intel_vbtn_probe(struct platform_device *device)
                 return err;
         }
 
-        /*
-         * VGBS being present and returning something means we have
-         * a tablet mode switch.
-         */
-        status = acpi_evaluate_object(handle, "VGBS", NULL, &vgbs_output);
-        if (ACPI_SUCCESS(status)) {
-                union acpi_object *obj = vgbs_output.pointer;
-
-                if (obj && obj->type == ACPI_TYPE_INTEGER) {
-                        int m = !(obj->integer.value & TABLET_MODE_FLAG);
-
-                        input_report_switch(priv->input_dev, SW_TABLET_MODE, m);
-                }
-        }
-
-        kfree(vgbs_output.pointer);
+        detect_tablet_mode(device);
 
         status = acpi_install_notify_handler(handle,
                                              ACPI_DEVICE_NOTIFY,
@@ -154,6 +166,7 @@ static int intel_vbtn_remove(struct platform_device *device)
 {
         acpi_handle handle = ACPI_HANDLE(&device->dev);
 
+        device_init_wakeup(&device->dev, false);
         acpi_remove_notify_handler(handle, ACPI_DEVICE_NOTIFY, notify_handler);
 
         /*
diff --git a/drivers/platform/x86/wmi.c b/drivers/platform/x86/wmi.c
index daa68acbc900..8796211ef24a 100644
--- a/drivers/platform/x86/wmi.c
+++ b/drivers/platform/x86/wmi.c
@@ -933,7 +933,7 @@ static int wmi_dev_probe(struct device *dev)
                         goto probe_failure;
                 }
 
-                buf = kmalloc(strlen(wdriver->driver.name) + 4, GFP_KERNEL);
+                buf = kmalloc(strlen(wdriver->driver.name) + 5, GFP_KERNEL);
                 if (!buf) {
                         ret = -ENOMEM;
                         goto probe_string_failure;
@@ -945,7 +945,7 @@ static int wmi_dev_probe(struct device *dev)
                 wblock->char_dev.mode = 0444;
                 ret = misc_register(&wblock->char_dev);
                 if (ret) {
-                        dev_warn(dev, "failed to register char dev: %d", ret);
+                        dev_warn(dev, "failed to register char dev: %d\n", ret);
                         ret = -ENOMEM;
                         goto probe_misc_failure;
                 }
@@ -1048,7 +1048,7 @@ static int wmi_create_device(struct device *wmi_bus_dev,
 
         if (result) {
                 dev_warn(wmi_bus_dev,
-                         "%s data block query control method not found",
+                         "%s data block query control method not found\n",
                          method);
                 return result;
         }
@@ -1198,7 +1198,7 @@ static int parse_wdg(struct device *wmi_bus_dev, struct acpi_device *device)
 
                 retval = device_add(&wblock->dev.dev);
                 if (retval) {
-                        dev_err(wmi_bus_dev, "failed to register %pULL\n",
+                        dev_err(wmi_bus_dev, "failed to register %pUL\n",
                                 wblock->gblock.guid);
                         if (debug_event)
                                 wmi_method_enable(wblock, 0);
diff --git a/drivers/s390/virtio/virtio_ccw.c b/drivers/s390/virtio/virtio_ccw.c
index ba2e0856d22c..8f5c1d7f751a 100644
--- a/drivers/s390/virtio/virtio_ccw.c
+++ b/drivers/s390/virtio/virtio_ccw.c
@@ -1297,6 +1297,9 @@ static int virtio_ccw_cio_notify(struct ccw_device *cdev, int event)
                 vcdev->device_lost = true;
                 rc = NOTIFY_DONE;
                 break;
+        case CIO_OPER:
+                rc = NOTIFY_OK;
+                break;
         default:
                 rc = NOTIFY_DONE;
                 break;
@@ -1309,6 +1312,27 @@ static struct ccw_device_id virtio_ids[] = {
         {},
 };
 
+#ifdef CONFIG_PM_SLEEP
+static int virtio_ccw_freeze(struct ccw_device *cdev)
+{
+        struct virtio_ccw_device *vcdev = dev_get_drvdata(&cdev->dev);
+
+        return virtio_device_freeze(&vcdev->vdev);
+}
+
+static int virtio_ccw_restore(struct ccw_device *cdev)
+{
+        struct virtio_ccw_device *vcdev = dev_get_drvdata(&cdev->dev);
+        int ret;
+
+        ret = virtio_ccw_set_transport_rev(vcdev);
+        if (ret)
+                return ret;
+
+        return virtio_device_restore(&vcdev->vdev);
+}
+#endif
+
 static struct ccw_driver virtio_ccw_driver = {
         .driver = {
                 .owner = THIS_MODULE,
@@ -1321,6 +1345,11 @@ static struct ccw_driver virtio_ccw_driver = {
         .set_online = virtio_ccw_online,
         .notify = virtio_ccw_cio_notify,
         .int_class = IRQIO_VIR,
+#ifdef CONFIG_PM_SLEEP
+        .freeze = virtio_ccw_freeze,
+        .thaw = virtio_ccw_restore,
+        .restore = virtio_ccw_restore,
+#endif
 };
 
 static int __init pure_hex(char **cp, unsigned int *val, int min_digit,
diff --git a/drivers/scsi/Makefile b/drivers/scsi/Makefile
index fcfd28d2884c..de1b3fce936d 100644
--- a/drivers/scsi/Makefile
+++ b/drivers/scsi/Makefile
@@ -185,7 +185,6 @@ ncr53c8xx-flags-$(CONFIG_SCSI_ZALON) \
 CFLAGS_ncr53c8xx.o      := $(ncr53c8xx-flags-y) $(ncr53c8xx-flags-m)
 zalon7xx-objs   := zalon.o ncr53c8xx.o
 NCR_Q720_mod-objs       := NCR_Q720.o ncr53c8xx.o
-oktagon_esp_mod-objs    := oktagon_esp.o oktagon_io.o
 
 # Files generated that shall be removed upon make clean
 clean-files :=  53c700_d.h 53c700_u.h
diff --git a/drivers/scsi/aacraid/linit.c b/drivers/scsi/aacraid/linit.c
index b3b931ab77eb..2664ea0df35f 100644
--- a/drivers/scsi/aacraid/linit.c
+++ b/drivers/scsi/aacraid/linit.c
@@ -1693,8 +1693,10 @@ static int aac_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
          *      Map in the registers from the adapter.
          */
         aac->base_size = AAC_MIN_FOOTPRINT_SIZE;
-        if ((*aac_drivers[index].init)(aac))
+        if ((*aac_drivers[index].init)(aac)) {
+                error = -ENODEV;
                 goto out_unmap;
+        }
 
         if (aac->sync_mode) {
                 if (aac_sync_mode)
diff --git a/drivers/scsi/aic7xxx/aiclib.c b/drivers/scsi/aic7xxx/aiclib.c
deleted file mode 100644
index 828ae3d9a510..000000000000
--- a/drivers/scsi/aic7xxx/aiclib.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Implementation of Utility functions for all SCSI device types.
- *
- * Copyright (c) 1997, 1998, 1999 Justin T. Gibbs.
- * Copyright (c) 1997, 1998 Kenneth D. Merry.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions, and the following disclaimer,
- *    without modification, immediately at the beginning of the file.
- * 2. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * $FreeBSD: src/sys/cam/scsi/scsi_all.c,v 1.38 2002/09/23 04:56:35 mjacob Exp $
- * $Id$
- */
-
-#include "aiclib.h"
-
diff --git a/drivers/scsi/bnx2fc/bnx2fc_io.c b/drivers/scsi/bnx2fc/bnx2fc_io.c
index 8e2f767147cb..5a645b8b9af1 100644
--- a/drivers/scsi/bnx2fc/bnx2fc_io.c
+++ b/drivers/scsi/bnx2fc/bnx2fc_io.c
@@ -1889,6 +1889,7 @@ void bnx2fc_process_scsi_cmd_compl(struct bnx2fc_cmd *io_req,
                 /* we will not receive ABTS response for this IO */
                 BNX2FC_IO_DBG(io_req, "Timer context finished processing "
                            "this scsi cmd\n");
+                return;
         }
 
         /* Cancel the timeout_work, as we received IO completion */
diff --git a/drivers/scsi/csiostor/csio_lnode.c b/drivers/scsi/csiostor/csio_lnode.c
index be5ee2d37815..7dbbbb81a1e7 100644
--- a/drivers/scsi/csiostor/csio_lnode.c
+++ b/drivers/scsi/csiostor/csio_lnode.c
@@ -114,7 +114,7 @@ static enum csio_ln_ev fwevt_to_lnevt[] = {
 static struct csio_lnode *
 csio_ln_lookup_by_portid(struct csio_hw *hw, uint8_t portid)
 {
-        struct csio_lnode *ln = hw->rln;
+        struct csio_lnode *ln;
         struct list_head *tmp;
 
         /* Match siblings lnode with portid */
diff --git a/drivers/scsi/device_handler/scsi_dh_alua.c b/drivers/scsi/device_handler/scsi_dh_alua.c
index 022e421c2185..4b44325d1a82 100644
--- a/drivers/scsi/device_handler/scsi_dh_alua.c
+++ b/drivers/scsi/device_handler/scsi_dh_alua.c
@@ -876,6 +876,11 @@ static void alua_rtpg_work(struct work_struct *work)
 
 /**
  * alua_rtpg_queue() - cause RTPG to be submitted asynchronously
+ * @pg: ALUA port group associated with @sdev.
+ * @sdev: SCSI device for which to submit an RTPG.
+ * @qdata: Information about the callback to invoke after the RTPG.
+ * @force: Whether or not to submit an RTPG if a work item that will submit an
+ *         RTPG already has been scheduled.
  *
  * Returns true if and only if alua_rtpg_work() will be called asynchronously.
  * That function is responsible for calling @qdata->fn().
diff --git a/drivers/scsi/ibmvscsi/ibmvfc.h b/drivers/scsi/ibmvscsi/ibmvfc.h
index 9a0696f68f37..b81a53c4a9a8 100644
--- a/drivers/scsi/ibmvscsi/ibmvfc.h
+++ b/drivers/scsi/ibmvscsi/ibmvfc.h
@@ -367,7 +367,7 @@ enum ibmvfc_fcp_rsp_info_codes {
 };
 
 struct ibmvfc_fcp_rsp_info {
-        __be16 reserved;
+        u8 reserved[3];
         u8 rsp_code;
         u8 reserved2[4];
 }__attribute__((packed, aligned (2)));
diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c b/drivers/scsi/mpt3sas/mpt3sas_base.c
index 13d6e4ec3022..59a87ca328d3 100644
--- a/drivers/scsi/mpt3sas/mpt3sas_base.c
+++ b/drivers/scsi/mpt3sas/mpt3sas_base.c
@@ -2410,8 +2410,11 @@ _base_assign_reply_queues(struct MPT3SAS_ADAPTER *ioc)
                                 continue;
                         }
 
-                        for_each_cpu(cpu, mask)
+                        for_each_cpu_and(cpu, mask, cpu_online_mask) {
+                                if (cpu >= ioc->cpu_msix_table_sz)
+                                        break;
                                 ioc->cpu_msix_table[cpu] = reply_q->msix_index;
+                        }
                 }
                 return;
         }
diff --git a/drivers/scsi/qedi/qedi_main.c b/drivers/scsi/qedi/qedi_main.c
index 029e2e69b29f..f57a94b4f0d9 100644
--- a/drivers/scsi/qedi/qedi_main.c
+++ b/drivers/scsi/qedi/qedi_main.c
@@ -1724,7 +1724,6 @@ static ssize_t qedi_show_boot_eth_info(void *data, int type, char *buf)
 {
         struct qedi_ctx *qedi = data;
         struct nvm_iscsi_initiator *initiator;
-        char *str = buf;
         int rc = 1;
         u32 ipv6_en, dhcp_en, ip_len;
         struct nvm_iscsi_block *block;
@@ -1758,32 +1757,32 @@ static ssize_t qedi_show_boot_eth_info(void *data, int type, char *buf)
 
         switch (type) {
         case ISCSI_BOOT_ETH_IP_ADDR:
-                rc = snprintf(str, ip_len, fmt, ip);
+                rc = snprintf(buf, ip_len, fmt, ip);
                 break;
         case ISCSI_BOOT_ETH_SUBNET_MASK:
-                rc = snprintf(str, ip_len, fmt, sub);
+                rc = snprintf(buf, ip_len, fmt, sub);
                 break;
         case ISCSI_BOOT_ETH_GATEWAY:
-                rc = snprintf(str, ip_len, fmt, gw);
+                rc = snprintf(buf, ip_len, fmt, gw);
                 break;
         case ISCSI_BOOT_ETH_FLAGS:
-                rc = snprintf(str, 3, "%hhd\n",
+                rc = snprintf(buf, 3, "%hhd\n",
                               SYSFS_FLAG_FW_SEL_BOOT);
                 break;
         case ISCSI_BOOT_ETH_INDEX:
-                rc = snprintf(str, 3, "0\n");
+                rc = snprintf(buf, 3, "0\n");
                 break;
         case ISCSI_BOOT_ETH_MAC:
-                rc = sysfs_format_mac(str, qedi->mac, ETH_ALEN);
+                rc = sysfs_format_mac(buf, qedi->mac, ETH_ALEN);
                 break;
         case ISCSI_BOOT_ETH_VLAN:
-                rc = snprintf(str, 12, "%d\n",
+                rc = snprintf(buf, 12, "%d\n",
                               GET_FIELD2(initiator->generic_cont0,
                                          NVM_ISCSI_CFG_INITIATOR_VLAN));
                 break;
         case ISCSI_BOOT_ETH_ORIGIN:
                 if (dhcp_en)
-                        rc = snprintf(str, 3, "3\n");
+                        rc = snprintf(buf, 3, "3\n");
                 break;
         default:
                 rc = 0;
@@ -1819,7 +1818,6 @@ static ssize_t qedi_show_boot_ini_info(void *data, int type, char *buf)
 {
         struct qedi_ctx *qedi = data;
         struct nvm_iscsi_initiator *initiator;
-        char *str = buf;
         int rc;
         struct nvm_iscsi_block *block;
 
@@ -1831,8 +1829,8 @@ static ssize_t qedi_show_boot_ini_info(void *data, int type, char *buf)
 
         switch (type) {
         case ISCSI_BOOT_INI_INITIATOR_NAME:
-                rc = snprintf(str, NVM_ISCSI_CFG_ISCSI_NAME_MAX_LEN, "%s\n",
-                              initiator->initiator_name.byte);
+                rc = sprintf(buf, "%.*s\n", NVM_ISCSI_CFG_ISCSI_NAME_MAX_LEN,
+                             initiator->initiator_name.byte);
                 break;
         default:
                 rc = 0;
@@ -1860,7 +1858,6 @@ static ssize_t
 qedi_show_boot_tgt_info(struct qedi_ctx *qedi, int type,
                         char *buf, enum qedi_nvm_tgts idx)
 {
-        char *str = buf;
         int rc = 1;
         u32 ctrl_flags, ipv6_en, chap_en, mchap_en, ip_len;
         struct nvm_iscsi_block *block;
@@ -1899,48 +1896,48 @@ qedi_show_boot_tgt_info(struct qedi_ctx *qedi, int type,
 
         switch (type) {
         case ISCSI_BOOT_TGT_NAME:
-                rc = snprintf(str, NVM_ISCSI_CFG_ISCSI_NAME_MAX_LEN, "%s\n",
-                              block->target[idx].target_name.byte);
+                rc = sprintf(buf, "%.*s\n", NVM_ISCSI_CFG_ISCSI_NAME_MAX_LEN,
+                             block->target[idx].target_name.byte);
                 break;
         case ISCSI_BOOT_TGT_IP_ADDR:
                 if (ipv6_en)
-                        rc = snprintf(str, ip_len, "%pI6\n",
+                        rc = snprintf(buf, ip_len, "%pI6\n",
                                       block->target[idx].ipv6_addr.byte);
                 else
-                        rc = snprintf(str, ip_len, "%pI4\n",
+                        rc = snprintf(buf, ip_len, "%pI4\n",
                                       block->target[idx].ipv4_addr.byte);
                 break;
         case ISCSI_BOOT_TGT_PORT:
-                rc = snprintf(str, 12, "%d\n",
+                rc = snprintf(buf, 12, "%d\n",
                               GET_FIELD2(block->target[idx].generic_cont0,
                                          NVM_ISCSI_CFG_TARGET_TCP_PORT));
                 break;
         case ISCSI_BOOT_TGT_LUN:
-                rc = snprintf(str, 22, "%.*d\n",
+                rc = snprintf(buf, 22, "%.*d\n",
                               block->target[idx].lun.value[1],
                               block->target[idx].lun.value[0]);
                 break;
         case ISCSI_BOOT_TGT_CHAP_NAME:
-                rc = snprintf(str, NVM_ISCSI_CFG_CHAP_NAME_MAX_LEN, "%s\n",
-                              chap_name);
+                rc = sprintf(buf, "%.*s\n", NVM_ISCSI_CFG_CHAP_NAME_MAX_LEN,
+                             chap_name);
                 break;
         case ISCSI_BOOT_TGT_CHAP_SECRET:
-                rc = snprintf(str, NVM_ISCSI_CFG_CHAP_PWD_MAX_LEN, "%s\n",
-                              chap_secret);
+                rc = sprintf(buf, "%.*s\n", NVM_ISCSI_CFG_CHAP_NAME_MAX_LEN,
+                             chap_secret);
                 break;
         case ISCSI_BOOT_TGT_REV_CHAP_NAME:
-                rc = snprintf(str, NVM_ISCSI_CFG_CHAP_NAME_MAX_LEN, "%s\n",
-                              mchap_name);
+                rc = sprintf(buf, "%.*s\n", NVM_ISCSI_CFG_CHAP_NAME_MAX_LEN,
+                             mchap_name);
                 break;
         case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
-                rc = snprintf(str, NVM_ISCSI_CFG_CHAP_PWD_MAX_LEN, "%s\n",
-                              mchap_secret);
+                rc = sprintf(buf, "%.*s\n", NVM_ISCSI_CFG_CHAP_NAME_MAX_LEN,
+                             mchap_secret);
                 break;
         case ISCSI_BOOT_TGT_FLAGS:
-                rc = snprintf(str, 3, "%hhd\n", SYSFS_FLAG_FW_SEL_BOOT);
+                rc = snprintf(buf, 3, "%hhd\n", SYSFS_FLAG_FW_SEL_BOOT);
                 break;
         case ISCSI_BOOT_TGT_NIC_ASSOC:
-                rc = snprintf(str, 3, "0\n");
+                rc = snprintf(buf, 3, "0\n");
                 break;
         default:
                 rc = 0;
diff --git a/drivers/scsi/qla2xxx/qla_init.c b/drivers/scsi/qla2xxx/qla_init.c
index aececf664654..2dea1129d396 100644
--- a/drivers/scsi/qla2xxx/qla_init.c
+++ b/drivers/scsi/qla2xxx/qla_init.c
@@ -59,8 +59,6 @@ qla2x00_sp_timeout(struct timer_list *t)
         req->outstanding_cmds[sp->handle] = NULL;
         iocb = &sp->u.iocb_cmd;
         iocb->timeout(sp);
-        if (sp->type != SRB_ELS_DCMD)
-                sp->free(sp);
         spin_unlock_irqrestore(&vha->hw->hardware_lock, flags);
 }
 
@@ -102,7 +100,6 @@ qla2x00_async_iocb_timeout(void *data)
         srb_t *sp = data;
         fc_port_t *fcport = sp->fcport;
         struct srb_iocb *lio = &sp->u.iocb_cmd;
-        struct event_arg ea;
 
         if (fcport) {
                 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
@@ -117,25 +114,13 @@ qla2x00_async_iocb_timeout(void *data)
 
         switch (sp->type) {
         case SRB_LOGIN_CMD:
-                if (!fcport)
-                        break;
                 /* Retry as needed. */
                 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
                 lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
                         QLA_LOGIO_LOGIN_RETRIED : 0;
-                memset(&ea, 0, sizeof(ea));
-                ea.event = FCME_PLOGI_DONE;
-                ea.fcport = sp->fcport;
-                ea.data[0] = lio->u.logio.data[0];
-                ea.data[1] = lio->u.logio.data[1];
-                ea.sp = sp;
-                qla24xx_handle_plogi_done_event(fcport->vha, &ea);
+                sp->done(sp, QLA_FUNCTION_TIMEOUT);
                 break;
         case SRB_LOGOUT_CMD:
-                if (!fcport)
-                        break;
-                qlt_logo_completion_handler(fcport, QLA_FUNCTION_TIMEOUT);
-                break;
         case SRB_CT_PTHRU_CMD:
         case SRB_MB_IOCB:
         case SRB_NACK_PLOGI:
@@ -235,12 +220,10 @@ static void
 qla2x00_async_logout_sp_done(void *ptr, int res)
 {
         srb_t *sp = ptr;
-        struct srb_iocb *lio = &sp->u.iocb_cmd;
 
         sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
-        if (!test_bit(UNLOADING, &sp->vha->dpc_flags))
-                qla2x00_post_async_logout_done_work(sp->vha, sp->fcport,
-                    lio->u.logio.data);
+        sp->fcport->login_gen++;
+        qlt_logo_completion_handler(sp->fcport, res);
         sp->free(sp);
 }
 
diff --git a/drivers/scsi/qla2xxx/qla_iocb.c b/drivers/scsi/qla2xxx/qla_iocb.c
index 1b62e943ec49..8d00d559bd26 100644
--- a/drivers/scsi/qla2xxx/qla_iocb.c
+++ b/drivers/scsi/qla2xxx/qla_iocb.c
@@ -3275,12 +3275,11 @@ qla24xx_abort_iocb(srb_t *sp, struct abort_entry_24xx *abt_iocb)
         memset(abt_iocb, 0, sizeof(struct abort_entry_24xx));
         abt_iocb->entry_type = ABORT_IOCB_TYPE;
         abt_iocb->entry_count = 1;
-        abt_iocb->handle =
-             cpu_to_le32(MAKE_HANDLE(aio->u.abt.req_que_no,
-                 aio->u.abt.cmd_hndl));
+        abt_iocb->handle = cpu_to_le32(MAKE_HANDLE(req->id, sp->handle));
         abt_iocb->nport_handle = cpu_to_le16(sp->fcport->loop_id);
         abt_iocb->handle_to_abort =
-            cpu_to_le32(MAKE_HANDLE(req->id, aio->u.abt.cmd_hndl));
+            cpu_to_le32(MAKE_HANDLE(aio->u.abt.req_que_no,
+                                    aio->u.abt.cmd_hndl));
         abt_iocb->port_id[0] = sp->fcport->d_id.b.al_pa;
         abt_iocb->port_id[1] = sp->fcport->d_id.b.area;
         abt_iocb->port_id[2] = sp->fcport->d_id.b.domain;
diff --git a/drivers/scsi/qla2xxx/qla_isr.c b/drivers/scsi/qla2xxx/qla_isr.c
index 14109d86c3f6..89f93ebd819d 100644
--- a/drivers/scsi/qla2xxx/qla_isr.c
+++ b/drivers/scsi/qla2xxx/qla_isr.c
@@ -272,7 +272,8 @@ qla2x00_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 
         /* Read all mbox registers? */
-        mboxes = (1 << ha->mbx_count) - 1;
+        WARN_ON_ONCE(ha->mbx_count > 32);
+        mboxes = (1ULL << ha->mbx_count) - 1;
         if (!ha->mcp)
                 ql_dbg(ql_dbg_async, vha, 0x5001, "MBX pointer ERROR.\n");
         else
@@ -2880,7 +2881,8 @@ qla24xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 
         /* Read all mbox registers? */
-        mboxes = (1 << ha->mbx_count) - 1;
+        WARN_ON_ONCE(ha->mbx_count > 32);
+        mboxes = (1ULL << ha->mbx_count) - 1;
         if (!ha->mcp)
                 ql_dbg(ql_dbg_async, vha, 0x504e, "MBX pointer ERROR.\n");
         else
diff --git a/drivers/scsi/qla2xxx/qla_os.c b/drivers/scsi/qla2xxx/qla_os.c
index 12ee6e02d146..afcb5567998a 100644
--- a/drivers/scsi/qla2xxx/qla_os.c
+++ b/drivers/scsi/qla2xxx/qla_os.c
@@ -3625,6 +3625,8 @@ qla2x00_remove_one(struct pci_dev *pdev)
         }
         qla2x00_wait_for_hba_ready(base_vha);
 
+        qla2x00_wait_for_sess_deletion(base_vha);
+
         /*
          * if UNLOAD flag is already set, then continue unload,
          * where it was set first.
diff --git a/drivers/scsi/qla2xxx/qla_target.c b/drivers/scsi/qla2xxx/qla_target.c
index fc89af8fe256..896b2d8bd803 100644
--- a/drivers/scsi/qla2xxx/qla_target.c
+++ b/drivers/scsi/qla2xxx/qla_target.c
@@ -4871,8 +4871,6 @@ static int qlt_24xx_handle_els(struct scsi_qla_host *vha,
                                     sess);
                                 qlt_send_term_imm_notif(vha, iocb, 1);
                                 res = 0;
-                                spin_lock_irqsave(&tgt->ha->tgt.sess_lock,
-                                    flags);
                                 break;
                         }
 
diff --git a/drivers/scsi/qla4xxx/ql4_def.h b/drivers/scsi/qla4xxx/ql4_def.h
index fc233717355f..817f312023a9 100644
--- a/drivers/scsi/qla4xxx/ql4_def.h
+++ b/drivers/scsi/qla4xxx/ql4_def.h
@@ -168,6 +168,8 @@
 #define DEV_DB_NON_PERSISTENT   0
 #define DEV_DB_PERSISTENT       1
 
+#define QL4_ISP_REG_DISCONNECT 0xffffffffU
+
 #define COPY_ISID(dst_isid, src_isid) {                 \
         int i, j;                                       \
         for (i = 0, j = ISID_SIZE - 1; i < ISID_SIZE;)  \
diff --git a/drivers/scsi/qla4xxx/ql4_os.c b/drivers/scsi/qla4xxx/ql4_os.c
index 82e889bbe0ed..fc2c97d9a0d6 100644
--- a/drivers/scsi/qla4xxx/ql4_os.c
+++ b/drivers/scsi/qla4xxx/ql4_os.c
@@ -262,6 +262,24 @@ static struct iscsi_transport qla4xxx_iscsi_transport = {
 
 static struct scsi_transport_template *qla4xxx_scsi_transport;
 
+static int qla4xxx_isp_check_reg(struct scsi_qla_host *ha)
+{
+        u32 reg_val = 0;
+        int rval = QLA_SUCCESS;
+
+        if (is_qla8022(ha))
+                reg_val = readl(&ha->qla4_82xx_reg->host_status);
+        else if (is_qla8032(ha) || is_qla8042(ha))
+                reg_val = qla4_8xxx_rd_direct(ha, QLA8XXX_PEG_ALIVE_COUNTER);
+        else
+                reg_val = readw(&ha->reg->ctrl_status);
+
+        if (reg_val == QL4_ISP_REG_DISCONNECT)
+                rval = QLA_ERROR;
+
+        return rval;
+}
+
 static int qla4xxx_send_ping(struct Scsi_Host *shost, uint32_t iface_num,
                              uint32_t iface_type, uint32_t payload_size,
                              uint32_t pid, struct sockaddr *dst_addr)
@@ -9186,10 +9204,17 @@ static int qla4xxx_eh_abort(struct scsi_cmnd *cmd)
         struct srb *srb = NULL;
         int ret = SUCCESS;
         int wait = 0;
+        int rval;
 
         ql4_printk(KERN_INFO, ha, "scsi%ld:%d:%llu: Abort command issued cmd=%p, cdb=0x%x\n",
                    ha->host_no, id, lun, cmd, cmd->cmnd[0]);
 
+        rval = qla4xxx_isp_check_reg(ha);
+        if (rval != QLA_SUCCESS) {
+                ql4_printk(KERN_INFO, ha, "PCI/Register disconnect, exiting.\n");
+                return FAILED;
+        }
+
         spin_lock_irqsave(&ha->hardware_lock, flags);
         srb = (struct srb *) CMD_SP(cmd);
         if (!srb) {
@@ -9241,6 +9266,7 @@ static int qla4xxx_eh_device_reset(struct scsi_cmnd *cmd)
         struct scsi_qla_host *ha = to_qla_host(cmd->device->host);
         struct ddb_entry *ddb_entry = cmd->device->hostdata;
         int ret = FAILED, stat;
+        int rval;
 
         if (!ddb_entry)
                 return ret;
@@ -9260,6 +9286,12 @@ static int qla4xxx_eh_device_reset(struct scsi_cmnd *cmd)
                       cmd, jiffies, cmd->request->timeout / HZ,
                       ha->dpc_flags, cmd->result, cmd->allowed));
 
+        rval = qla4xxx_isp_check_reg(ha);
+        if (rval != QLA_SUCCESS) {
+                ql4_printk(KERN_INFO, ha, "PCI/Register disconnect, exiting.\n");
+                return FAILED;
+        }
+
         /* FIXME: wait for hba to go online */
         stat = qla4xxx_reset_lun(ha, ddb_entry, cmd->device->lun);
         if (stat != QLA_SUCCESS) {
@@ -9303,6 +9335,7 @@ static int qla4xxx_eh_target_reset(struct scsi_cmnd *cmd)
         struct scsi_qla_host *ha = to_qla_host(cmd->device->host);
         struct ddb_entry *ddb_entry = cmd->device->hostdata;
         int stat, ret;
+        int rval;
 
         if (!ddb_entry)
                 return FAILED;
@@ -9320,6 +9353,12 @@ static int qla4xxx_eh_target_reset(struct scsi_cmnd *cmd)
                       ha->host_no, cmd, jiffies, cmd->request->timeout / HZ,
                       ha->dpc_flags, cmd->result, cmd->allowed));
 
+        rval = qla4xxx_isp_check_reg(ha);
+        if (rval != QLA_SUCCESS) {
+                ql4_printk(KERN_INFO, ha, "PCI/Register disconnect, exiting.\n");
+                return FAILED;
+        }
+
         stat = qla4xxx_reset_target(ha, ddb_entry);
         if (stat != QLA_SUCCESS) {
                 starget_printk(KERN_INFO, scsi_target(cmd->device),
@@ -9374,9 +9413,16 @@ static int qla4xxx_eh_host_reset(struct scsi_cmnd *cmd)
 {
         int return_status = FAILED;
         struct scsi_qla_host *ha;
+        int rval;
 
         ha = to_qla_host(cmd->device->host);
 
+        rval = qla4xxx_isp_check_reg(ha);
+        if (rval != QLA_SUCCESS) {
+                ql4_printk(KERN_INFO, ha, "PCI/Register disconnect, exiting.\n");
+                return FAILED;
+        }
+
         if ((is_qla8032(ha) || is_qla8042(ha)) && ql4xdontresethba)
                 qla4_83xx_set_idc_dontreset(ha);
 
diff --git a/drivers/scsi/storvsc_drv.c b/drivers/scsi/storvsc_drv.c
index 40fc7a590e81..6be5ab32c94f 100644
--- a/drivers/scsi/storvsc_drv.c
+++ b/drivers/scsi/storvsc_drv.c
@@ -1657,7 +1657,7 @@ static struct scsi_host_template scsi_driver = {
         .eh_timed_out =         storvsc_eh_timed_out,
         .slave_alloc =          storvsc_device_alloc,
         .slave_configure =      storvsc_device_configure,
-        .cmd_per_lun =          255,
+        .cmd_per_lun =          2048,
         .this_id =              -1,
         .use_clustering =       ENABLE_CLUSTERING,
         /* Make sure we dont get a sg segment crosses a page boundary */
diff --git a/drivers/scsi/sym53c8xx_2/sym_hipd.c b/drivers/scsi/sym53c8xx_2/sym_hipd.c
index ca360daa6a25..378af306fda1 100644
--- a/drivers/scsi/sym53c8xx_2/sym_hipd.c
+++ b/drivers/scsi/sym53c8xx_2/sym_hipd.c
@@ -536,7 +536,7 @@ sym_getsync(struct sym_hcb *np, u_char dt, u_char sfac, u_char *divp, u_char *fa
          *  Look for the greatest clock divisor that allows an 
          *  input speed faster than the period.
          */
-        while (div-- > 0)
+        while (--div > 0)
                 if (kpc >= (div_10M[div] << 2)) break;
 
         /*
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index a355d989b414..c7da2c185990 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -4352,6 +4352,8 @@ static int ufshcd_slave_alloc(struct scsi_device *sdev)
         /* REPORT SUPPORTED OPERATION CODES is not supported */
         sdev->no_report_opcodes = 1;
 
+        /* WRITE_SAME command is not supported */
+        sdev->no_write_same = 1;
 
         ufshcd_set_queue_depth(sdev);
 
diff --git a/drivers/soc/amlogic/meson-gx-socinfo.c b/drivers/soc/amlogic/meson-gx-socinfo.c
index f2d8c3c53ea4..8bdaa9b43d49 100644
--- a/drivers/soc/amlogic/meson-gx-socinfo.c
+++ b/drivers/soc/amlogic/meson-gx-socinfo.c
@@ -41,6 +41,7 @@ static const struct meson_gx_package_id {
         unsigned int pack_id;
 } soc_packages[] = {
         { "S905", 0x1f, 0 },
+        { "S905H", 0x1f, 0x13 },
         { "S905M", 0x1f, 0x20 },
         { "S905D", 0x21, 0 },
         { "S905X", 0x21, 0x80 },
diff --git a/drivers/soc/imx/gpc.c b/drivers/soc/imx/gpc.c
index 53f7275d6cbd..750f93197411 100644
--- a/drivers/soc/imx/gpc.c
+++ b/drivers/soc/imx/gpc.c
@@ -348,7 +348,7 @@ static int imx_gpc_old_dt_init(struct device *dev, struct regmap *regmap,
                 if (i == 1) {
                         domain->supply = devm_regulator_get(dev, "pu");
                         if (IS_ERR(domain->supply))
-                                return PTR_ERR(domain->supply);;
+                                return PTR_ERR(domain->supply);
 
                         ret = imx_pgc_get_clocks(dev, domain);
                         if (ret)
@@ -470,13 +470,21 @@ static int imx_gpc_probe(struct platform_device *pdev)
 
 static int imx_gpc_remove(struct platform_device *pdev)
 {
+        struct device_node *pgc_node;
         int ret;
 
+        pgc_node = of_get_child_by_name(pdev->dev.of_node, "pgc");
+
+        /* bail out if DT too old and doesn't provide the necessary info */
+        if (!of_property_read_bool(pdev->dev.of_node, "#power-domain-cells") &&
+            !pgc_node)
+                return 0;
+
         /*
          * If the old DT binding is used the toplevel driver needs to
          * de-register the power domains
          */
-        if (!of_get_child_by_name(pdev->dev.of_node, "pgc")) {
+        if (!pgc_node) {
                 of_genpd_del_provider(pdev->dev.of_node);
 
                 ret = pm_genpd_remove(&imx_gpc_domains[GPC_PGC_DOMAIN_PU].base);
diff --git a/drivers/staging/android/ashmem.c b/drivers/staging/android/ashmem.c
index bbdc53b686dd..6dbba5aff191 100644
--- a/drivers/staging/android/ashmem.c
+++ b/drivers/staging/android/ashmem.c
@@ -702,30 +702,32 @@ static int ashmem_pin_unpin(struct ashmem_area *asma, unsigned long cmd,
         size_t pgstart, pgend;
         int ret = -EINVAL;
 
+        mutex_lock(&ashmem_mutex);
+
         if (unlikely(!asma->file))
-                return -EINVAL;
+                goto out_unlock;
 
-        if (unlikely(copy_from_user(&pin, p, sizeof(pin))))
-                return -EFAULT;
+        if (unlikely(copy_from_user(&pin, p, sizeof(pin)))) {
+                ret = -EFAULT;
+                goto out_unlock;
+        }
 
         /* per custom, you can pass zero for len to mean "everything onward" */
         if (!pin.len)
                 pin.len = PAGE_ALIGN(asma->size) - pin.offset;
 
         if (unlikely((pin.offset | pin.len) & ~PAGE_MASK))
-                return -EINVAL;
+                goto out_unlock;
 
         if (unlikely(((__u32)-1) - pin.offset < pin.len))
-                return -EINVAL;
+                goto out_unlock;
 
         if (unlikely(PAGE_ALIGN(asma->size) < pin.offset + pin.len))
-                return -EINVAL;
+                goto out_unlock;
 
         pgstart = pin.offset / PAGE_SIZE;
         pgend = pgstart + (pin.len / PAGE_SIZE) - 1;
 
-        mutex_lock(&ashmem_mutex);
-
         switch (cmd) {
         case ASHMEM_PIN:
                 ret = ashmem_pin(asma, pgstart, pgend);
@@ -738,6 +740,7 @@ static int ashmem_pin_unpin(struct ashmem_area *asma, unsigned long cmd,
                 break;
         }
 
+out_unlock:
         mutex_unlock(&ashmem_mutex);
 
         return ret;
diff --git a/drivers/staging/android/ion/ion_cma_heap.c b/drivers/staging/android/ion/ion_cma_heap.c
index 94e06925c712..49718c96bf9e 100644
--- a/drivers/staging/android/ion/ion_cma_heap.c
+++ b/drivers/staging/android/ion/ion_cma_heap.c
@@ -12,6 +12,7 @@
 #include <linux/err.h>
 #include <linux/cma.h>
 #include <linux/scatterlist.h>
+#include <linux/highmem.h>
 
 #include "ion.h"
 
@@ -42,6 +43,22 @@ static int ion_cma_allocate(struct ion_heap *heap, struct ion_buffer *buffer,
         if (!pages)
                 return -ENOMEM;
 
+        if (PageHighMem(pages)) {
+                unsigned long nr_clear_pages = nr_pages;
+                struct page *page = pages;
+
+                while (nr_clear_pages > 0) {
+                        void *vaddr = kmap_atomic(page);
+
+                        memset(vaddr, 0, PAGE_SIZE);
+                        kunmap_atomic(vaddr);
+                        page++;
+                        nr_clear_pages--;
+                }
+        } else {
+                memset(page_address(pages), 0, size);
+        }
+
         table = kmalloc(sizeof(*table), GFP_KERNEL);
         if (!table)
                 goto err;
diff --git a/drivers/staging/fsl-mc/bus/Kconfig b/drivers/staging/fsl-mc/bus/Kconfig
index 1f9100049176..b35ef7ee6901 100644
--- a/drivers/staging/fsl-mc/bus/Kconfig
+++ b/drivers/staging/fsl-mc/bus/Kconfig
@@ -7,7 +7,7 @@
 
 config FSL_MC_BUS
         bool "QorIQ DPAA2 fsl-mc bus driver"
-        depends on OF && (ARCH_LAYERSCAPE || (COMPILE_TEST && (ARM || ARM64 || X86 || PPC)))
+        depends on OF && (ARCH_LAYERSCAPE || (COMPILE_TEST && (ARM || ARM64 || X86_LOCAL_APIC || PPC)))
         select GENERIC_MSI_IRQ_DOMAIN
         help
           Driver to enable the bus infrastructure for the QorIQ DPAA2
diff --git a/drivers/staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c b/drivers/staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c
index 5064d5ddf581..fc2013aade51 100644
--- a/drivers/staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c
+++ b/drivers/staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c
@@ -73,6 +73,8 @@ static int __init its_fsl_mc_msi_init(void)
 
         for (np = of_find_matching_node(NULL, its_device_id); np;
              np = of_find_matching_node(np, its_device_id)) {
+                if (!of_device_is_available(np))
+                        continue;
                 if (!of_property_read_bool(np, "msi-controller"))
                         continue;
 
diff --git a/drivers/staging/iio/adc/ad7192.c b/drivers/staging/iio/adc/ad7192.c
index f01595593ce2..425e8b82533b 100644
--- a/drivers/staging/iio/adc/ad7192.c
+++ b/drivers/staging/iio/adc/ad7192.c
@@ -141,6 +141,8 @@
 #define AD7192_GPOCON_P1DAT     BIT(1) /* P1 state */
 #define AD7192_GPOCON_P0DAT     BIT(0) /* P0 state */
 
+#define AD7192_EXT_FREQ_MHZ_MIN 2457600
+#define AD7192_EXT_FREQ_MHZ_MAX 5120000
 #define AD7192_INT_FREQ_MHZ     4915200
 
 /* NOTE:
@@ -218,6 +220,12 @@ static int ad7192_calibrate_all(struct ad7192_state *st)
                                 ARRAY_SIZE(ad7192_calib_arr));
 }
 
+static inline bool ad7192_valid_external_frequency(u32 freq)
+{
+        return (freq >= AD7192_EXT_FREQ_MHZ_MIN &&
+                freq <= AD7192_EXT_FREQ_MHZ_MAX);
+}
+
 static int ad7192_setup(struct ad7192_state *st,
                         const struct ad7192_platform_data *pdata)
 {
@@ -243,17 +251,20 @@ static int ad7192_setup(struct ad7192_state *st,
                          id);
 
         switch (pdata->clock_source_sel) {
-        case AD7192_CLK_EXT_MCLK1_2:
-        case AD7192_CLK_EXT_MCLK2:
-                st->mclk = AD7192_INT_FREQ_MHZ;
-                break;
         case AD7192_CLK_INT:
         case AD7192_CLK_INT_CO:
-                if (pdata->ext_clk_hz)
-                        st->mclk = pdata->ext_clk_hz;
-                else
-                        st->mclk = AD7192_INT_FREQ_MHZ;
+                st->mclk = AD7192_INT_FREQ_MHZ;
                 break;
+        case AD7192_CLK_EXT_MCLK1_2:
+        case AD7192_CLK_EXT_MCLK2:
+                if (ad7192_valid_external_frequency(pdata->ext_clk_hz)) {
+                        st->mclk = pdata->ext_clk_hz;
+                        break;
+                }
+                dev_err(&st->sd.spi->dev, "Invalid frequency setting %u\n",
+                        pdata->ext_clk_hz);
+                ret = -EINVAL;
+                goto out;
         default:
                 ret = -EINVAL;
                 goto out;
diff --git a/drivers/staging/iio/impedance-analyzer/ad5933.c b/drivers/staging/iio/impedance-analyzer/ad5933.c
index 2b28fb9c0048..3bcf49466361 100644
--- a/drivers/staging/iio/impedance-analyzer/ad5933.c
+++ b/drivers/staging/iio/impedance-analyzer/ad5933.c
@@ -648,8 +648,6 @@ static int ad5933_register_ring_funcs_and_init(struct iio_dev *indio_dev)
         /* Ring buffer functions - here trigger setup related */
         indio_dev->setup_ops = &ad5933_ring_setup_ops;
 
-        indio_dev->modes |= INDIO_BUFFER_HARDWARE;
-
         return 0;
 }
 
@@ -762,7 +760,7 @@ static int ad5933_probe(struct i2c_client *client,
         indio_dev->dev.parent = &client->dev;
         indio_dev->info = &ad5933_info;
         indio_dev->name = id->name;
-        indio_dev->modes = INDIO_DIRECT_MODE;
+        indio_dev->modes = (INDIO_BUFFER_SOFTWARE | INDIO_DIRECT_MODE);
         indio_dev->channels = ad5933_channels;
         indio_dev->num_channels = ARRAY_SIZE(ad5933_channels);
 
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index f699abab1787..148f3ee70286 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -19,6 +19,12 @@ config USB_EHCI_BIG_ENDIAN_MMIO
 config USB_EHCI_BIG_ENDIAN_DESC
         bool
 
+config USB_UHCI_BIG_ENDIAN_MMIO
+        bool
+
+config USB_UHCI_BIG_ENDIAN_DESC
+        bool
+
 menuconfig USB_SUPPORT
         bool "USB support"
         depends on HAS_IOMEM
diff --git a/drivers/usb/class/cdc-acm.c b/drivers/usb/class/cdc-acm.c
index 06b3b54a0e68..7b366a6c0b49 100644
--- a/drivers/usb/class/cdc-acm.c
+++ b/drivers/usb/class/cdc-acm.c
@@ -174,6 +174,7 @@ static int acm_wb_alloc(struct acm *acm)
                 wb = &acm->wb[wbn];
                 if (!wb->use) {
                         wb->use = 1;
+                        wb->len = 0;
                         return wbn;
                 }
                 wbn = (wbn + 1) % ACM_NW;
@@ -805,16 +806,18 @@ static int acm_tty_write(struct tty_struct *tty,
 static void acm_tty_flush_chars(struct tty_struct *tty)
 {
         struct acm *acm = tty->driver_data;
-        struct acm_wb *cur = acm->putbuffer;
+        struct acm_wb *cur;
         int err;
         unsigned long flags;
 
+        spin_lock_irqsave(&acm->write_lock, flags);
+
+        cur = acm->putbuffer;
         if (!cur) /* nothing to do */
-                return;
+                goto out;
 
         acm->putbuffer = NULL;
         err = usb_autopm_get_interface_async(acm->control);
-        spin_lock_irqsave(&acm->write_lock, flags);
         if (err < 0) {
                 cur->use = 0;
                 acm->putbuffer = cur;
diff --git a/drivers/usb/core/quirks.c b/drivers/usb/core/quirks.c
index 4024926c1d68..f4a548471f0f 100644
--- a/drivers/usb/core/quirks.c
+++ b/drivers/usb/core/quirks.c
@@ -226,6 +226,9 @@ static const struct usb_device_id usb_quirk_list[] = {
         { USB_DEVICE(0x1a0a, 0x0200), .driver_info =
                         USB_QUIRK_LINEAR_UFRAME_INTR_BINTERVAL },
 
+        /* Corsair K70 RGB */
+        { USB_DEVICE(0x1b1c, 0x1b13), .driver_info = USB_QUIRK_DELAY_INIT },
+
         /* Corsair Strafe RGB */
         { USB_DEVICE(0x1b1c, 0x1b20), .driver_info = USB_QUIRK_DELAY_INIT },
 
diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
index e4c3ce0de5de..5bcad1d869b5 100644
--- a/drivers/usb/dwc2/gadget.c
+++ b/drivers/usb/dwc2/gadget.c
@@ -1917,7 +1917,9 @@ static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
                 /* Not specific buffer needed for ep0 ZLP */
                 dma_addr_t dma = hs_ep->desc_list_dma;
 
-                dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep);
+                if (!index)
+                        dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep);
+
                 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0);
         } else {
                 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
@@ -2974,9 +2976,13 @@ static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
         if (ints & DXEPINT_STSPHSERCVD) {
                 dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__);
 
-                /* Move to STATUS IN for DDMA */
-                if (using_desc_dma(hsotg))
-                        dwc2_hsotg_ep0_zlp(hsotg, true);
+                /* Safety check EP0 state when STSPHSERCVD asserted */
+                if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
+                        /* Move to STATUS IN for DDMA */
+                        if (using_desc_dma(hsotg))
+                                dwc2_hsotg_ep0_zlp(hsotg, true);
+                }
+
         }
 
         if (ints & DXEPINT_BACK2BACKSETUP)
@@ -3375,12 +3381,6 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
         dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
                DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0);
 
-        dwc2_hsotg_enqueue_setup(hsotg);
-
-        dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
-                dwc2_readl(hsotg->regs + DIEPCTL0),
-                dwc2_readl(hsotg->regs + DOEPCTL0));
-
         /* clear global NAKs */
         val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
         if (!is_usb_reset)
@@ -3391,6 +3391,12 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
         mdelay(3);
 
         hsotg->lx_state = DWC2_L0;
+
+        dwc2_hsotg_enqueue_setup(hsotg);
+
+        dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
+                dwc2_readl(hsotg->regs + DIEPCTL0),
+                dwc2_readl(hsotg->regs + DOEPCTL0));
 }
 
 static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index ade2ab00d37a..f1d838a4acd6 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -100,6 +100,8 @@ static void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
         reg |= DWC3_GCTL_PRTCAPDIR(mode);
         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
+
+        dwc->current_dr_role = mode;
 }
 
 static void __dwc3_set_mode(struct work_struct *work)
@@ -133,8 +135,6 @@ static void __dwc3_set_mode(struct work_struct *work)
 
         dwc3_set_prtcap(dwc, dwc->desired_dr_role);
 
-        dwc->current_dr_role = dwc->desired_dr_role;
-
         spin_unlock_irqrestore(&dwc->lock, flags);
 
         switch (dwc->desired_dr_role) {
@@ -219,7 +219,7 @@ static int dwc3_core_soft_reset(struct dwc3 *dwc)
          * XHCI driver will reset the host block. If dwc3 was configured for
          * host-only mode, then we can return early.
          */
-        if (dwc->dr_mode == USB_DR_MODE_HOST)
+        if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
                 return 0;
 
         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
@@ -234,6 +234,9 @@ static int dwc3_core_soft_reset(struct dwc3 *dwc)
                 udelay(1);
         } while (--retries);
 
+        phy_exit(dwc->usb3_generic_phy);
+        phy_exit(dwc->usb2_generic_phy);
+
         return -ETIMEDOUT;
 }
 
@@ -483,6 +486,22 @@ static void dwc3_cache_hwparams(struct dwc3 *dwc)
         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 }
 
+static int dwc3_core_ulpi_init(struct dwc3 *dwc)
+{
+        int intf;
+        int ret = 0;
+
+        intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
+
+        if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
+            (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
+             dwc->hsphy_interface &&
+             !strncmp(dwc->hsphy_interface, "ulpi", 4)))
+                ret = dwc3_ulpi_init(dwc);
+
+        return ret;
+}
+
 /**
  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
  * @dwc: Pointer to our controller context structure
@@ -494,7 +513,6 @@ static void dwc3_cache_hwparams(struct dwc3 *dwc)
 static int dwc3_phy_setup(struct dwc3 *dwc)
 {
         u32 reg;
-        int ret;
 
         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 
@@ -565,9 +583,6 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
                 }
                 /* FALLTHROUGH */
         case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
-                ret = dwc3_ulpi_init(dwc);
-                if (ret)
-                        return ret;
                 /* FALLTHROUGH */
         default:
                 break;
@@ -724,6 +739,7 @@ static void dwc3_core_setup_global_control(struct dwc3 *dwc)
 }
 
 static int dwc3_core_get_phy(struct dwc3 *dwc);
+static int dwc3_core_ulpi_init(struct dwc3 *dwc);
 
 /**
  * dwc3_core_init - Low-level initialization of DWC3 Core
@@ -755,17 +771,27 @@ static int dwc3_core_init(struct dwc3 *dwc)
                         dwc->maximum_speed = USB_SPEED_HIGH;
         }
 
-        ret = dwc3_core_get_phy(dwc);
+        ret = dwc3_phy_setup(dwc);
         if (ret)
                 goto err0;
 
-        ret = dwc3_core_soft_reset(dwc);
-        if (ret)
-                goto err0;
+        if (!dwc->ulpi_ready) {
+                ret = dwc3_core_ulpi_init(dwc);
+                if (ret)
+                        goto err0;
+                dwc->ulpi_ready = true;
+        }
 
-        ret = dwc3_phy_setup(dwc);
+        if (!dwc->phys_ready) {
+                ret = dwc3_core_get_phy(dwc);
+                if (ret)
+                        goto err0a;
+                dwc->phys_ready = true;
+        }
+
+        ret = dwc3_core_soft_reset(dwc);
         if (ret)
-                goto err0;
+                goto err0a;
 
         dwc3_core_setup_global_control(dwc);
         dwc3_core_num_eps(dwc);
@@ -838,6 +864,9 @@ err1:
         phy_exit(dwc->usb2_generic_phy);
         phy_exit(dwc->usb3_generic_phy);
 
+err0a:
+        dwc3_ulpi_exit(dwc);
+
 err0:
         return ret;
 }
@@ -916,7 +945,6 @@ static int dwc3_core_init_mode(struct dwc3 *dwc)
 
         switch (dwc->dr_mode) {
         case USB_DR_MODE_PERIPHERAL:
-                dwc->current_dr_role = DWC3_GCTL_PRTCAP_DEVICE;
                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 
                 if (dwc->usb2_phy)
@@ -932,7 +960,6 @@ static int dwc3_core_init_mode(struct dwc3 *dwc)
                 }
                 break;
         case USB_DR_MODE_HOST:
-                dwc->current_dr_role = DWC3_GCTL_PRTCAP_HOST;
                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
 
                 if (dwc->usb2_phy)
@@ -1234,7 +1261,6 @@ err4:
 
 err3:
         dwc3_free_event_buffers(dwc);
-        dwc3_ulpi_exit(dwc);
 
 err2:
         pm_runtime_allow(&pdev->dev);
@@ -1284,7 +1310,7 @@ static int dwc3_remove(struct platform_device *pdev)
 }
 
 #ifdef CONFIG_PM
-static int dwc3_suspend_common(struct dwc3 *dwc)
+static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
 {
         unsigned long   flags;
 
@@ -1296,6 +1322,10 @@ static int dwc3_suspend_common(struct dwc3 *dwc)
                 dwc3_core_exit(dwc);
                 break;
         case DWC3_GCTL_PRTCAP_HOST:
+                /* do nothing during host runtime_suspend */
+                if (!PMSG_IS_AUTO(msg))
+                        dwc3_core_exit(dwc);
+                break;
         default:
                 /* do nothing */
                 break;
@@ -1304,7 +1334,7 @@ static int dwc3_suspend_common(struct dwc3 *dwc)
         return 0;
 }
 
-static int dwc3_resume_common(struct dwc3 *dwc)
+static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
 {
         unsigned long   flags;
         int             ret;
@@ -1320,6 +1350,13 @@ static int dwc3_resume_common(struct dwc3 *dwc)
                 spin_unlock_irqrestore(&dwc->lock, flags);
                 break;
         case DWC3_GCTL_PRTCAP_HOST:
+                /* nothing to do on host runtime_resume */
+                if (!PMSG_IS_AUTO(msg)) {
+                        ret = dwc3_core_init(dwc);
+                        if (ret)
+                                return ret;
+                }
+                break;
         default:
                 /* do nothing */
                 break;
@@ -1331,12 +1368,11 @@ static int dwc3_resume_common(struct dwc3 *dwc)
 static int dwc3_runtime_checks(struct dwc3 *dwc)
 {
         switch (dwc->current_dr_role) {
-        case USB_DR_MODE_PERIPHERAL:
-        case USB_DR_MODE_OTG:
+        case DWC3_GCTL_PRTCAP_DEVICE:
                 if (dwc->connected)
                         return -EBUSY;
                 break;
-        case USB_DR_MODE_HOST:
+        case DWC3_GCTL_PRTCAP_HOST:
         default:
                 /* do nothing */
                 break;
@@ -1353,7 +1389,7 @@ static int dwc3_runtime_suspend(struct device *dev)
         if (dwc3_runtime_checks(dwc))
                 return -EBUSY;
 
-        ret = dwc3_suspend_common(dwc);
+        ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
         if (ret)
                 return ret;
 
@@ -1369,7 +1405,7 @@ static int dwc3_runtime_resume(struct device *dev)
 
         device_init_wakeup(dev, false);
 
-        ret = dwc3_resume_common(dwc);
+        ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
         if (ret)
                 return ret;
 
@@ -1416,7 +1452,7 @@ static int dwc3_suspend(struct device *dev)
         struct dwc3     *dwc = dev_get_drvdata(dev);
         int             ret;
 
-        ret = dwc3_suspend_common(dwc);
+        ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
         if (ret)
                 return ret;
 
@@ -1432,7 +1468,7 @@ static int dwc3_resume(struct device *dev)
 
         pinctrl_pm_select_default_state(dev);
 
-        ret = dwc3_resume_common(dwc);
+        ret = dwc3_resume_common(dwc, PMSG_RESUME);
         if (ret)
                 return ret;
 
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 03c7aaaac926..860d2bc184d1 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -158,13 +158,15 @@
 #define DWC3_GDBGFIFOSPACE_TYPE(n)      (((n) << 5) & 0x1e0)
 #define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff)
 
-#define DWC3_TXFIFOQ            1
-#define DWC3_RXFIFOQ            3
-#define DWC3_TXREQQ             5
-#define DWC3_RXREQQ             7
-#define DWC3_RXINFOQ            9
-#define DWC3_DESCFETCHQ         13
-#define DWC3_EVENTQ             15
+#define DWC3_TXFIFOQ            0
+#define DWC3_RXFIFOQ            1
+#define DWC3_TXREQQ             2
+#define DWC3_RXREQQ             3
+#define DWC3_RXINFOQ            4
+#define DWC3_PSTATQ             5
+#define DWC3_DESCFETCHQ         6
+#define DWC3_EVENTQ             7
+#define DWC3_AUXEVENTQ          8
 
 /* Global RX Threshold Configuration Register */
 #define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19)
@@ -795,7 +797,9 @@ struct dwc3_scratchpad_array {
  * @usb3_phy: pointer to USB3 PHY
  * @usb2_generic_phy: pointer to USB2 PHY
  * @usb3_generic_phy: pointer to USB3 PHY
+ * @phys_ready: flag to indicate that PHYs are ready
  * @ulpi: pointer to ulpi interface
+ * @ulpi_ready: flag to indicate that ULPI is initialized
  * @u2sel: parameter from Set SEL request.
  * @u2pel: parameter from Set SEL request.
  * @u1sel: parameter from Set SEL request.
@@ -893,7 +897,10 @@ struct dwc3 {
         struct phy              *usb2_generic_phy;
         struct phy              *usb3_generic_phy;
 
+        bool                    phys_ready;
+
         struct ulpi             *ulpi;
+        bool                    ulpi_ready;
 
         void __iomem            *regs;
         size_t                  regs_size;
diff --git a/drivers/usb/dwc3/dwc3-of-simple.c b/drivers/usb/dwc3/dwc3-of-simple.c
index 7ae0eefc7cc7..e54c3622eb28 100644
--- a/drivers/usb/dwc3/dwc3-of-simple.c
+++ b/drivers/usb/dwc3/dwc3-of-simple.c
@@ -143,6 +143,7 @@ static int dwc3_of_simple_remove(struct platform_device *pdev)
                 clk_disable_unprepare(simple->clks[i]);
                 clk_put(simple->clks[i]);
         }
+        simple->num_clocks = 0;
 
         reset_control_assert(simple->resets);
         reset_control_put(simple->resets);
diff --git a/drivers/usb/dwc3/dwc3-omap.c b/drivers/usb/dwc3/dwc3-omap.c
index a4719e853b85..ed8b86517675 100644
--- a/drivers/usb/dwc3/dwc3-omap.c
+++ b/drivers/usb/dwc3/dwc3-omap.c
@@ -582,9 +582,25 @@ static int dwc3_omap_resume(struct device *dev)
         return 0;
 }
 
+static void dwc3_omap_complete(struct device *dev)
+{
+        struct dwc3_omap        *omap = dev_get_drvdata(dev);
+
+        if (extcon_get_state(omap->edev, EXTCON_USB))
+                dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
+        else
+                dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF);
+
+        if (extcon_get_state(omap->edev, EXTCON_USB_HOST))
+                dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
+        else
+                dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT);
+}
+
 static const struct dev_pm_ops dwc3_omap_dev_pm_ops = {
 
         SET_SYSTEM_SLEEP_PM_OPS(dwc3_omap_suspend, dwc3_omap_resume)
+        .complete = dwc3_omap_complete,
 };
 
 #define DEV_PM_OPS      (&dwc3_omap_dev_pm_ops)
diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
index 9c2e4a17918e..18be31d5743a 100644
--- a/drivers/usb/dwc3/ep0.c
+++ b/drivers/usb/dwc3/ep0.c
@@ -854,7 +854,12 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc,
                 trb++;
                 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
                 trace_dwc3_complete_trb(ep0, trb);
-                ep0->trb_enqueue = 0;
+
+                if (r->direction)
+                        dwc->eps[1]->trb_enqueue = 0;
+                else
+                        dwc->eps[0]->trb_enqueue = 0;
+
                 dwc->ep0_bounced = false;
         }
 
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index 616ef49ccb49..2bda4eb1e9ac 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -2745,6 +2745,8 @@ static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
                 break;
         }
 
+        dwc->eps[1]->endpoint.maxpacket = dwc->gadget.ep0->maxpacket;
+
         /* Enable USB2 LPM Capability */
 
         if ((dwc->revision > DWC3_REVISION_194A) &&
diff --git a/drivers/usb/gadget/function/f_fs.c b/drivers/usb/gadget/function/f_fs.c
index 8f2cf3baa19c..c2592d883f67 100644
--- a/drivers/usb/gadget/function/f_fs.c
+++ b/drivers/usb/gadget/function/f_fs.c
@@ -1855,44 +1855,20 @@ static int ffs_func_eps_enable(struct ffs_function *func)
 
         spin_lock_irqsave(&func->ffs->eps_lock, flags);
         while(count--) {
-                struct usb_endpoint_descriptor *ds;
-                struct usb_ss_ep_comp_descriptor *comp_desc = NULL;
-                int needs_comp_desc = false;
-                int desc_idx;
-
-                if (ffs->gadget->speed == USB_SPEED_SUPER) {
-                        desc_idx = 2;
-                        needs_comp_desc = true;
-                } else if (ffs->gadget->speed == USB_SPEED_HIGH)
-                        desc_idx = 1;
-                else
-                        desc_idx = 0;
-
-                /* fall-back to lower speed if desc missing for current speed */
-                do {
-                        ds = ep->descs[desc_idx];
-                } while (!ds && --desc_idx >= 0);
-
-                if (!ds) {
-                        ret = -EINVAL;
-                        break;
-                }
-
                 ep->ep->driver_data = ep;
-                ep->ep->desc = ds;
 
-                if (needs_comp_desc) {
-                        comp_desc = (struct usb_ss_ep_comp_descriptor *)(ds +
-                                        USB_DT_ENDPOINT_SIZE);
-                        ep->ep->maxburst = comp_desc->bMaxBurst + 1;
-                        ep->ep->comp_desc = comp_desc;
+                ret = config_ep_by_speed(func->gadget, &func->function, ep->ep);
+                if (ret) {
+                        pr_err("%s: config_ep_by_speed(%s) returned %d\n",
+                                        __func__, ep->ep->name, ret);
+                        break;
                 }
 
                 ret = usb_ep_enable(ep->ep);
                 if (likely(!ret)) {
                         epfile->ep = ep;
-                        epfile->in = usb_endpoint_dir_in(ds);
-                        epfile->isoc = usb_endpoint_xfer_isoc(ds);
+                        epfile->in = usb_endpoint_dir_in(ep->ep->desc);
+                        epfile->isoc = usb_endpoint_xfer_isoc(ep->ep->desc);
                 } else {
                         break;
                 }
@@ -2979,10 +2955,8 @@ static int _ffs_func_bind(struct usb_configuration *c,
         struct ffs_data *ffs = func->ffs;
 
         const int full = !!func->ffs->fs_descs_count;
-        const int high = gadget_is_dualspeed(func->gadget) &&
-                func->ffs->hs_descs_count;
-        const int super = gadget_is_superspeed(func->gadget) &&
-                func->ffs->ss_descs_count;
+        const int high = !!func->ffs->hs_descs_count;
+        const int super = !!func->ffs->ss_descs_count;
 
         int fs_len, hs_len, ss_len, ret, i;
         struct ffs_ep *eps_ptr;
diff --git a/drivers/usb/gadget/function/f_uac2.c b/drivers/usb/gadget/function/f_uac2.c
index 11fe788b4308..d2dc1f00180b 100644
--- a/drivers/usb/gadget/function/f_uac2.c
+++ b/drivers/usb/gadget/function/f_uac2.c
@@ -524,6 +524,8 @@ afunc_bind(struct usb_configuration *cfg, struct usb_function *fn)
                 dev_err(dev, "%s:%d Error!\n", __func__, __LINE__);
                 return ret;
         }
+        iad_desc.bFirstInterface = ret;
+
         std_ac_if_desc.bInterfaceNumber = ret;
         uac2->ac_intf = ret;
         uac2->ac_alt = 0;
diff --git a/drivers/usb/gadget/udc/Kconfig b/drivers/usb/gadget/udc/Kconfig
index 1e9567091d86..0875d38476ee 100644
--- a/drivers/usb/gadget/udc/Kconfig
+++ b/drivers/usb/gadget/udc/Kconfig
@@ -274,7 +274,6 @@ config USB_SNP_UDC_PLAT
         tristate "Synopsys USB 2.0 Device controller"
         depends on USB_GADGET && OF && HAS_DMA
         depends on EXTCON || EXTCON=n
-        select USB_GADGET_DUALSPEED
         select USB_SNP_CORE
         default ARCH_BCM_IPROC
         help
diff --git a/drivers/usb/gadget/udc/bdc/bdc_pci.c b/drivers/usb/gadget/udc/bdc/bdc_pci.c
index 1e940f054cb8..6dbc489513cd 100644
--- a/drivers/usb/gadget/udc/bdc/bdc_pci.c
+++ b/drivers/usb/gadget/udc/bdc/bdc_pci.c
@@ -77,6 +77,7 @@ static int bdc_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)
         if (ret) {
                 dev_err(&pci->dev,
                         "couldn't add resources to bdc device\n");
+                platform_device_put(bdc);
                 return ret;
         }
 
diff --git a/drivers/usb/gadget/udc/core.c b/drivers/usb/gadget/udc/core.c
index 859d5b11ba4c..1f8b19d9cf97 100644
--- a/drivers/usb/gadget/udc/core.c
+++ b/drivers/usb/gadget/udc/core.c
@@ -180,8 +180,8 @@ EXPORT_SYMBOL_GPL(usb_ep_alloc_request);
 void usb_ep_free_request(struct usb_ep *ep,
                                        struct usb_request *req)
 {
-        ep->ops->free_request(ep, req);
         trace_usb_ep_free_request(ep, req, 0);
+        ep->ops->free_request(ep, req);
 }
 EXPORT_SYMBOL_GPL(usb_ep_free_request);
 
diff --git a/drivers/usb/gadget/udc/fsl_udc_core.c b/drivers/usb/gadget/udc/fsl_udc_core.c
index e5b4ee96c4bf..56b517a38865 100644
--- a/drivers/usb/gadget/udc/fsl_udc_core.c
+++ b/drivers/usb/gadget/udc/fsl_udc_core.c
@@ -1305,7 +1305,7 @@ static void udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe)
 {
         struct fsl_ep *ep = get_ep_by_pipe(udc, pipe);
 
-        if (ep->name)
+        if (ep->ep.name)
                 nuke(ep, -ESHUTDOWN);
 }
 
@@ -1693,7 +1693,7 @@ static void dtd_complete_irq(struct fsl_udc *udc)
                 curr_ep = get_ep_by_pipe(udc, i);
 
                 /* If the ep is configured */
-                if (curr_ep->name == NULL) {
+                if (!curr_ep->ep.name) {
                         WARNING("Invalid EP?");
                         continue;
                 }
diff --git a/drivers/usb/gadget/udc/renesas_usb3.c b/drivers/usb/gadget/udc/renesas_usb3.c
index 6e87af248367..409cde4e6a51 100644
--- a/drivers/usb/gadget/udc/renesas_usb3.c
+++ b/drivers/usb/gadget/udc/renesas_usb3.c
@@ -2410,7 +2410,7 @@ static int renesas_usb3_remove(struct platform_device *pdev)
         __renesas_usb3_ep_free_request(usb3->ep0_req);
         if (usb3->phy)
                 phy_put(usb3->phy);
-        pm_runtime_disable(usb3_to_dev(usb3));
+        pm_runtime_disable(&pdev->dev);
 
         return 0;
 }
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 6150bed7cfa8..4fcfb3084b36 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -633,14 +633,6 @@ config USB_UHCI_ASPEED
        bool
        default y if ARCH_ASPEED
 
-config USB_UHCI_BIG_ENDIAN_MMIO
-        bool
-        default y if SPARC_LEON
-
-config USB_UHCI_BIG_ENDIAN_DESC
-        bool
-        default y if SPARC_LEON
-
 config USB_FHCI_HCD
         tristate "Freescale QE USB Host Controller support"
         depends on OF_GPIO && QE_GPIO && QUICC_ENGINE
diff --git a/drivers/usb/host/ehci-hub.c b/drivers/usb/host/ehci-hub.c
index facafdf8fb95..d7641cbdee43 100644
--- a/drivers/usb/host/ehci-hub.c
+++ b/drivers/usb/host/ehci-hub.c
@@ -774,12 +774,12 @@ static struct urb *request_single_step_set_feature_urb(
         atomic_inc(&urb->use_count);
         atomic_inc(&urb->dev->urbnum);
         urb->setup_dma = dma_map_single(
-                        hcd->self.controller,
+                        hcd->self.sysdev,
                         urb->setup_packet,
                         sizeof(struct usb_ctrlrequest),
                         DMA_TO_DEVICE);
         urb->transfer_dma = dma_map_single(
-                        hcd->self.controller,
+                        hcd->self.sysdev,
                         urb->transfer_buffer,
                         urb->transfer_buffer_length,
                         DMA_FROM_DEVICE);
diff --git a/drivers/usb/host/ehci-q.c b/drivers/usb/host/ehci-q.c
index 88158324dcae..327630405695 100644
--- a/drivers/usb/host/ehci-q.c
+++ b/drivers/usb/host/ehci-q.c
@@ -1188,10 +1188,10 @@ static int submit_single_step_set_feature(
          * 15 secs after the setup
          */
         if (is_setup) {
-                /* SETUP pid */
+                /* SETUP pid, and interrupt after SETUP completion */
                 qtd_fill(ehci, qtd, urb->setup_dma,
                                 sizeof(struct usb_ctrlrequest),
-                                token | (2 /* "setup" */ << 8), 8);
+                                QTD_IOC | token | (2 /* "setup" */ << 8), 8);
 
                 submit_async(ehci, urb, &qtd_list, GFP_ATOMIC);
                 return 0; /*Return now; we shall come back after 15 seconds*/
@@ -1228,12 +1228,8 @@ static int submit_single_step_set_feature(
         qtd_prev->hw_next = QTD_NEXT(ehci, qtd->qtd_dma);
         list_add_tail(&qtd->qtd_list, head);
 
-        /* dont fill any data in such packets */
-        qtd_fill(ehci, qtd, 0, 0, token, 0);
-
-        /* by default, enable interrupt on urb completion */
-        if (likely(!(urb->transfer_flags & URB_NO_INTERRUPT)))
-                qtd->hw_token |= cpu_to_hc32(ehci, QTD_IOC);
+        /* Interrupt after STATUS completion */
+        qtd_fill(ehci, qtd, 0, 0, token | QTD_IOC, 0);
 
         submit_async(ehci, urb, &qtd_list, GFP_KERNEL);
 
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index ee9676349333..84f88fa411cd 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -74,6 +74,7 @@ static const char	hcd_name [] = "ohci_hcd";
 
 #define STATECHANGE_DELAY       msecs_to_jiffies(300)
 #define IO_WATCHDOG_DELAY       msecs_to_jiffies(275)
+#define IO_WATCHDOG_OFF         0xffffff00
 
 #include "ohci.h"
 #include "pci-quirks.h"
@@ -231,7 +232,7 @@ static int ohci_urb_enqueue (
                 }
 
                 /* Start up the I/O watchdog timer, if it's not running */
-                if (!timer_pending(&ohci->io_watchdog) &&
+                if (ohci->prev_frame_no == IO_WATCHDOG_OFF &&
                                 list_empty(&ohci->eds_in_use) &&
                                 !(ohci->flags & OHCI_QUIRK_QEMU)) {
                         ohci->prev_frame_no = ohci_frame_no(ohci);
@@ -501,6 +502,7 @@ static int ohci_init (struct ohci_hcd *ohci)
                 return 0;
 
         timer_setup(&ohci->io_watchdog, io_watchdog_func, 0);
+        ohci->prev_frame_no = IO_WATCHDOG_OFF;
 
         ohci->hcca = dma_alloc_coherent (hcd->self.controller,
                         sizeof(*ohci->hcca), &ohci->hcca_dma, GFP_KERNEL);
@@ -730,7 +732,7 @@ static void io_watchdog_func(struct timer_list *t)
         u32             head;
         struct ed       *ed;
         struct td       *td, *td_start, *td_next;
-        unsigned        frame_no;
+        unsigned        frame_no, prev_frame_no = IO_WATCHDOG_OFF;
         unsigned long   flags;
 
         spin_lock_irqsave(&ohci->lock, flags);
@@ -835,7 +837,7 @@ static void io_watchdog_func(struct timer_list *t)
                         }
                 }
                 if (!list_empty(&ohci->eds_in_use)) {
-                        ohci->prev_frame_no = frame_no;
+                        prev_frame_no = frame_no;
                         ohci->prev_wdh_cnt = ohci->wdh_cnt;
                         ohci->prev_donehead = ohci_readl(ohci,
                                         &ohci->regs->donehead);
@@ -845,6 +847,7 @@ static void io_watchdog_func(struct timer_list *t)
         }
 
  done:
+        ohci->prev_frame_no = prev_frame_no;
         spin_unlock_irqrestore(&ohci->lock, flags);
 }
 
@@ -973,6 +976,7 @@ static void ohci_stop (struct usb_hcd *hcd)
         if (quirk_nec(ohci))
                 flush_work(&ohci->nec_work);
         del_timer_sync(&ohci->io_watchdog);
+        ohci->prev_frame_no = IO_WATCHDOG_OFF;
 
         ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
         ohci_usb_reset(ohci);
diff --git a/drivers/usb/host/ohci-hub.c b/drivers/usb/host/ohci-hub.c
index fb7aaa3b9d06..634f3c7bf774 100644
--- a/drivers/usb/host/ohci-hub.c
+++ b/drivers/usb/host/ohci-hub.c
@@ -311,8 +311,10 @@ static int ohci_bus_suspend (struct usb_hcd *hcd)
                 rc = ohci_rh_suspend (ohci, 0);
         spin_unlock_irq (&ohci->lock);
 
-        if (rc == 0)
+        if (rc == 0) {
                 del_timer_sync(&ohci->io_watchdog);
+                ohci->prev_frame_no = IO_WATCHDOG_OFF;
+        }
         return rc;
 }
 
diff --git a/drivers/usb/host/ohci-q.c b/drivers/usb/host/ohci-q.c
index b2ec8c399363..4ccb85a67bb3 100644
--- a/drivers/usb/host/ohci-q.c
+++ b/drivers/usb/host/ohci-q.c
@@ -1019,6 +1019,8 @@ skip_ed:
                  * have modified this list.  normally it's just prepending
                  * entries (which we'd ignore), but paranoia won't hurt.
                  */
+                *last = ed->ed_next;
+                ed->ed_next = NULL;
                 modified = 0;
 
                 /* unlink urbs as requested, but rescan the list after
@@ -1077,21 +1079,22 @@ rescan_this:
                         goto rescan_this;
 
                 /*
-                 * If no TDs are queued, take ED off the ed_rm_list.
+                 * If no TDs are queued, ED is now idle.
                  * Otherwise, if the HC is running, reschedule.
-                 * If not, leave it on the list for further dequeues.
+                 * If the HC isn't running, add ED back to the
+                 * start of the list for later processing.
                  */
                 if (list_empty(&ed->td_list)) {
-                        *last = ed->ed_next;
-                        ed->ed_next = NULL;
                         ed->state = ED_IDLE;
                         list_del(&ed->in_use_list);
                 } else if (ohci->rh_state == OHCI_RH_RUNNING) {
-                        *last = ed->ed_next;
-                        ed->ed_next = NULL;
                         ed_schedule(ohci, ed);
                 } else {
-                        last = &ed->ed_next;
+                        ed->ed_next = ohci->ed_rm_list;
+                        ohci->ed_rm_list = ed;
+                        /* Don't loop on the same ED */
+                        if (last == &ohci->ed_rm_list)
+                                last = &ed->ed_next;
                 }
 
                 if (modified)
diff --git a/drivers/usb/host/pci-quirks.c b/drivers/usb/host/pci-quirks.c
index 161536717025..67ad4bb6919a 100644
--- a/drivers/usb/host/pci-quirks.c
+++ b/drivers/usb/host/pci-quirks.c
@@ -66,6 +66,23 @@
 #define AX_INDXC                0x30
 #define AX_DATAC                0x34
 
+#define PT_ADDR_INDX            0xE8
+#define PT_READ_INDX            0xE4
+#define PT_SIG_1_ADDR           0xA520
+#define PT_SIG_2_ADDR           0xA521
+#define PT_SIG_3_ADDR           0xA522
+#define PT_SIG_4_ADDR           0xA523
+#define PT_SIG_1_DATA           0x78
+#define PT_SIG_2_DATA           0x56
+#define PT_SIG_3_DATA           0x34
+#define PT_SIG_4_DATA           0x12
+#define PT4_P1_REG              0xB521
+#define PT4_P2_REG              0xB522
+#define PT2_P1_REG              0xD520
+#define PT2_P2_REG              0xD521
+#define PT1_P1_REG              0xD522
+#define PT1_P2_REG              0xD523
+
 #define NB_PCIE_INDX_ADDR       0xe0
 #define NB_PCIE_INDX_DATA       0xe4
 #define PCIE_P_CNTL             0x10040
@@ -513,6 +530,98 @@ void usb_amd_dev_put(void)
 EXPORT_SYMBOL_GPL(usb_amd_dev_put);
 
 /*
+ * Check if port is disabled in BIOS on AMD Promontory host.
+ * BIOS Disabled ports may wake on connect/disconnect and need
+ * driver workaround to keep them disabled.
+ * Returns true if port is marked disabled.
+ */
+bool usb_amd_pt_check_port(struct device *device, int port)
+{
+        unsigned char value, port_shift;
+        struct pci_dev *pdev;
+        u16 reg;
+
+        pdev = to_pci_dev(device);
+        pci_write_config_word(pdev, PT_ADDR_INDX, PT_SIG_1_ADDR);
+
+        pci_read_config_byte(pdev, PT_READ_INDX, &value);
+        if (value != PT_SIG_1_DATA)
+                return false;
+
+        pci_write_config_word(pdev, PT_ADDR_INDX, PT_SIG_2_ADDR);
+
+        pci_read_config_byte(pdev, PT_READ_INDX, &value);
+        if (value != PT_SIG_2_DATA)
+                return false;
+
+        pci_write_config_word(pdev, PT_ADDR_INDX, PT_SIG_3_ADDR);
+
+        pci_read_config_byte(pdev, PT_READ_INDX, &value);
+        if (value != PT_SIG_3_DATA)
+                return false;
+
+        pci_write_config_word(pdev, PT_ADDR_INDX, PT_SIG_4_ADDR);
+
+        pci_read_config_byte(pdev, PT_READ_INDX, &value);
+        if (value != PT_SIG_4_DATA)
+                return false;
+
+        /* Check disabled port setting, if bit is set port is enabled */
+        switch (pdev->device) {
+        case 0x43b9:
+        case 0x43ba:
+        /*
+         * device is AMD_PROMONTORYA_4(0x43b9) or PROMONTORYA_3(0x43ba)
+         * PT4_P1_REG bits[7..1] represents USB2.0 ports 6 to 0
+         * PT4_P2_REG bits[6..0] represents ports 13 to 7
+         */
+                if (port > 6) {
+                        reg = PT4_P2_REG;
+                        port_shift = port - 7;
+                } else {
+                        reg = PT4_P1_REG;
+                        port_shift = port + 1;
+                }
+                break;
+        case 0x43bb:
+        /*
+         * device is AMD_PROMONTORYA_2(0x43bb)
+         * PT2_P1_REG bits[7..5] represents USB2.0 ports 2 to 0
+         * PT2_P2_REG bits[5..0] represents ports 9 to 3
+         */
+                if (port > 2) {
+                        reg = PT2_P2_REG;
+                        port_shift = port - 3;
+                } else {
+                        reg = PT2_P1_REG;
+                        port_shift = port + 5;
+                }
+                break;
+        case 0x43bc:
+        /*
+         * device is AMD_PROMONTORYA_1(0x43bc)
+         * PT1_P1_REG[7..4] represents USB2.0 ports 3 to 0
+         * PT1_P2_REG[5..0] represents ports 9 to 4
+         */
+                if (port > 3) {
+                        reg = PT1_P2_REG;
+                        port_shift = port - 4;
+                } else {
+                        reg = PT1_P1_REG;
+                        port_shift = port + 4;
+                }
+                break;
+        default:
+                return false;
+        }
+        pci_write_config_word(pdev, PT_ADDR_INDX, reg);
+        pci_read_config_byte(pdev, PT_READ_INDX, &value);
+
+        return !(value & BIT(port_shift));
+}
+EXPORT_SYMBOL_GPL(usb_amd_pt_check_port);
+
+/*
  * Make sure the controller is completely inactive, unable to
  * generate interrupts or do DMA.
  */
diff --git a/drivers/usb/host/pci-quirks.h b/drivers/usb/host/pci-quirks.h
index b68dcb5dd0fd..4ca0d9b7e463 100644
--- a/drivers/usb/host/pci-quirks.h
+++ b/drivers/usb/host/pci-quirks.h
@@ -17,6 +17,7 @@ void usb_enable_intel_xhci_ports(struct pci_dev *xhci_pdev);
 void usb_disable_xhci_ports(struct pci_dev *xhci_pdev);
 void sb800_prefetch(struct device *dev, int on);
 bool usb_xhci_needs_pci_reset(struct pci_dev *pdev);
+bool usb_amd_pt_check_port(struct device *device, int port);
 #else
 struct pci_dev;
 static inline void usb_amd_quirk_pll_disable(void) {}
@@ -25,6 +26,10 @@ static inline void usb_asmedia_modifyflowcontrol(struct pci_dev *pdev) {}
 static inline void usb_amd_dev_put(void) {}
 static inline void usb_disable_xhci_ports(struct pci_dev *xhci_pdev) {}
 static inline void sb800_prefetch(struct device *dev, int on) {}
+static inline bool usb_amd_pt_check_port(struct device *device, int port)
+{
+        return false;
+}
 #endif  /* CONFIG_USB_PCI */
 
 #endif  /*  __LINUX_USB_PCI_QUIRKS_H  */
diff --git a/drivers/usb/host/xhci-debugfs.c b/drivers/usb/host/xhci-debugfs.c
index e26e685d8a57..5851052d4668 100644
--- a/drivers/usb/host/xhci-debugfs.c
+++ b/drivers/usb/host/xhci-debugfs.c
@@ -211,7 +211,7 @@ static void xhci_ring_dump_segment(struct seq_file *s,
 static int xhci_ring_trb_show(struct seq_file *s, void *unused)
 {
         int                     i;
-        struct xhci_ring        *ring = s->private;
+        struct xhci_ring        *ring = *(struct xhci_ring **)s->private;
         struct xhci_segment     *seg = ring->first_seg;
 
         for (i = 0; i < ring->num_segs; i++) {
@@ -387,7 +387,7 @@ void xhci_debugfs_create_endpoint(struct xhci_hcd *xhci,
 
         snprintf(epriv->name, sizeof(epriv->name), "ep%02d", ep_index);
         epriv->root = xhci_debugfs_create_ring_dir(xhci,
-                                                   &dev->eps[ep_index].new_ring,
+                                                   &dev->eps[ep_index].ring,
                                                    epriv->name,
                                                    spriv->root);
         spriv->eps[ep_index] = epriv;
diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c
index 46d5e08f05f1..72ebbc908e19 100644
--- a/drivers/usb/host/xhci-hub.c
+++ b/drivers/usb/host/xhci-hub.c
@@ -1224,17 +1224,17 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
                                 temp = readl(port_array[wIndex]);
                                 break;
                         }
-
-                        /* Software should not attempt to set
-                         * port link state above '3' (U3) and the port
-                         * must be enabled.
-                         */
-                        if ((temp & PORT_PE) == 0 ||
-                                (link_state > USB_SS_PORT_LS_U3)) {
-                                xhci_warn(xhci, "Cannot set link state.\n");
+                        /* Port must be enabled */
+                        if (!(temp & PORT_PE)) {
+                                retval = -ENODEV;
+                                break;
+                        }
+                        /* Can't set port link state above '3' (U3) */
+                        if (link_state > USB_SS_PORT_LS_U3) {
+                                xhci_warn(xhci, "Cannot set port %d link state %d\n",
+                                         wIndex, link_state);
                                 goto error;
                         }
-
                         if (link_state == USB_SS_PORT_LS_U3) {
                                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
                                                 wIndex + 1);
@@ -1522,6 +1522,13 @@ int xhci_bus_suspend(struct usb_hcd *hcd)
                                 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
                                 t2 &= ~PORT_WKDISC_E;
                         }
+
+                        if ((xhci->quirks & XHCI_U2_DISABLE_WAKE) &&
+                            (hcd->speed < HCD_USB3)) {
+                                if (usb_amd_pt_check_port(hcd->self.controller,
+                                                          port_index))
+                                        t2 &= ~PORT_WAKE_BITS;
+                        }
                 } else
                         t2 &= ~PORT_WAKE_BITS;
 
diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
index 6c79037876db..5262fa571a5d 100644
--- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c
@@ -42,6 +42,10 @@
 #define PCI_DEVICE_ID_INTEL_APL_XHCI                    0x5aa8
 #define PCI_DEVICE_ID_INTEL_DNV_XHCI                    0x19d0
 
+#define PCI_DEVICE_ID_AMD_PROMONTORYA_4                 0x43b9
+#define PCI_DEVICE_ID_AMD_PROMONTORYA_3                 0x43ba
+#define PCI_DEVICE_ID_AMD_PROMONTORYA_2                 0x43bb
+#define PCI_DEVICE_ID_AMD_PROMONTORYA_1                 0x43bc
 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI                0x1142
 
 static const char hcd_name[] = "xhci_hcd";
@@ -125,6 +129,13 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
         if (pdev->vendor == PCI_VENDOR_ID_AMD)
                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 
+        if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
+                ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
+                (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
+                (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
+                (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
+                xhci->quirks |= XHCI_U2_DISABLE_WAKE;
+
         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
                 xhci->quirks |= XHCI_LPM_SUPPORT;
                 xhci->quirks |= XHCI_INTEL_HOST;
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index 1eeb3396300f..25d4b748a56f 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -646,8 +646,6 @@ static void xhci_stop(struct usb_hcd *hcd)
                 return;
         }
 
-        xhci_debugfs_exit(xhci);
-
         xhci_dbc_exit(xhci);
 
         spin_lock_irq(&xhci->lock);
@@ -680,6 +678,7 @@ static void xhci_stop(struct usb_hcd *hcd)
 
         xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
         xhci_mem_cleanup(xhci);
+        xhci_debugfs_exit(xhci);
         xhci_dbg_trace(xhci, trace_xhci_dbg_init,
                         "xhci_stop completed - status = %x",
                         readl(&xhci->op_regs->status));
@@ -1014,6 +1013,7 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
 
                 xhci_dbg(xhci, "cleaning up memory\n");
                 xhci_mem_cleanup(xhci);
+                xhci_debugfs_exit(xhci);
                 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
                             readl(&xhci->op_regs->status));
 
@@ -3544,12 +3544,10 @@ static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
                 virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING;
                 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
         }
-
+        xhci_debugfs_remove_slot(xhci, udev->slot_id);
         ret = xhci_disable_slot(xhci, udev->slot_id);
-        if (ret) {
-                xhci_debugfs_remove_slot(xhci, udev->slot_id);
+        if (ret)
                 xhci_free_virt_device(xhci, udev->slot_id);
-        }
 }
 
 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id)
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index 96099a245c69..e4d7d3d06a75 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -1822,7 +1822,7 @@ struct xhci_hcd {
 /* For controller with a broken Port Disable implementation */
 #define XHCI_BROKEN_PORT_PED    (1 << 25)
 #define XHCI_LIMIT_ENDPOINT_INTERVAL_7  (1 << 26)
-/* Reserved. It was XHCI_U2_DISABLE_WAKE */
+#define XHCI_U2_DISABLE_WAKE    (1 << 27)
 #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL (1 << 28)
 #define XHCI_HW_LPM_DISABLE     (1 << 29)
 
diff --git a/drivers/usb/misc/ldusb.c b/drivers/usb/misc/ldusb.c
index 63b9e85dc0e9..236a60f53099 100644
--- a/drivers/usb/misc/ldusb.c
+++ b/drivers/usb/misc/ldusb.c
@@ -42,6 +42,9 @@
 #define USB_DEVICE_ID_LD_MICROCASSYTIME         0x1033  /* USB Product ID of Micro-CASSY Time (reserved) */
 #define USB_DEVICE_ID_LD_MICROCASSYTEMPERATURE  0x1035  /* USB Product ID of Micro-CASSY Temperature */
 #define USB_DEVICE_ID_LD_MICROCASSYPH           0x1038  /* USB Product ID of Micro-CASSY pH */
+#define USB_DEVICE_ID_LD_POWERANALYSERCASSY     0x1040  /* USB Product ID of Power Analyser CASSY */
+#define USB_DEVICE_ID_LD_CONVERTERCONTROLLERCASSY       0x1042  /* USB Product ID of Converter Controller CASSY */
+#define USB_DEVICE_ID_LD_MACHINETESTCASSY       0x1043  /* USB Product ID of Machine Test CASSY */
 #define USB_DEVICE_ID_LD_JWM            0x1080  /* USB Product ID of Joule and Wattmeter */
 #define USB_DEVICE_ID_LD_DMMP           0x1081  /* USB Product ID of Digital Multimeter P (reserved) */
 #define USB_DEVICE_ID_LD_UMIP           0x1090  /* USB Product ID of UMI P */
@@ -84,6 +87,9 @@ static const struct usb_device_id ld_usb_table[] = {
         { USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_MICROCASSYTIME) },
         { USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_MICROCASSYTEMPERATURE) },
         { USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_MICROCASSYPH) },
+        { USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_POWERANALYSERCASSY) },
+        { USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_CONVERTERCONTROLLERCASSY) },
+        { USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_MACHINETESTCASSY) },
         { USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_JWM) },
         { USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_DMMP) },
         { USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_UMIP) },
diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
index 968bf1e8b0fe..eef4ad578b31 100644
--- a/drivers/usb/musb/musb_core.c
+++ b/drivers/usb/musb/musb_core.c
@@ -2708,7 +2708,8 @@ static int musb_resume(struct device *dev)
         if ((devctl & mask) != (musb->context.devctl & mask))
                 musb->port1_status = 0;
 
-        musb_start(musb);
+        musb_enable_interrupts(musb);
+        musb_platform_enable(musb);
 
         spin_lock_irqsave(&musb->lock, flags);
         error = musb_run_resume_work(musb);
diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
index 394b4ac86161..45ed32c2cba9 100644
--- a/drivers/usb/musb/musb_host.c
+++ b/drivers/usb/musb/musb_host.c
@@ -391,13 +391,7 @@ static void musb_advance_schedule(struct musb *musb, struct urb *urb,
                 }
         }
 
-        /*
-         * The pipe must be broken if current urb->status is set, so don't
-         * start next urb.
-         * TODO: to minimize the risk of regression, only check urb->status
-         * for RX, until we have a test case to understand the behavior of TX.
-         */
-        if ((!status || !is_in) && qh && qh->is_ready) {
+        if (qh != NULL && qh->is_ready) {
                 musb_dbg(musb, "... next ep%d %cX urb %p",
                     hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh));
                 musb_start_urb(musb, is_in, qh);
diff --git a/drivers/usb/phy/phy-mxs-usb.c b/drivers/usb/phy/phy-mxs-usb.c
index da031c45395a..fbec863350f6 100644
--- a/drivers/usb/phy/phy-mxs-usb.c
+++ b/drivers/usb/phy/phy-mxs-usb.c
@@ -602,6 +602,9 @@ static enum usb_charger_type mxs_phy_charger_detect(struct usb_phy *phy)
         void __iomem *base = phy->io_priv;
         enum usb_charger_type chgr_type = UNKNOWN_TYPE;
 
+        if (!regmap)
+                return UNKNOWN_TYPE;
+
         if (mxs_charger_data_contact_detect(mxs_phy))
                 return chgr_type;
 
diff --git a/drivers/usb/renesas_usbhs/fifo.c b/drivers/usb/renesas_usbhs/fifo.c
index 5925d111bd47..39fa2fc1b8b7 100644
--- a/drivers/usb/renesas_usbhs/fifo.c
+++ b/drivers/usb/renesas_usbhs/fifo.c
@@ -982,6 +982,10 @@ static int usbhsf_dma_prepare_pop_with_usb_dmac(struct usbhs_pkt *pkt,
         if ((uintptr_t)pkt->buf & (USBHS_USB_DMAC_XFER_SIZE - 1))
                 goto usbhsf_pio_prepare_pop;
 
+        /* return at this time if the pipe is running */
+        if (usbhs_pipe_is_running(pipe))
+                return 0;
+
         usbhs_pipe_config_change_bfre(pipe, 1);
 
         ret = usbhsf_fifo_select(pipe, fifo, 0);
@@ -1172,6 +1176,7 @@ static int usbhsf_dma_pop_done_with_usb_dmac(struct usbhs_pkt *pkt,
         usbhsf_fifo_clear(pipe, fifo);
         pkt->actual = usbhs_dma_calc_received_size(pkt, chan, rcv_len);
 
+        usbhs_pipe_running(pipe, 0);
         usbhsf_dma_stop(pipe, fifo);
         usbhsf_dma_unmap(pkt);
         usbhsf_fifo_unselect(pipe, pipe->fifo);
diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c
index 5db8ed517e0e..2d8d9150da0c 100644
--- a/drivers/usb/serial/option.c
+++ b/drivers/usb/serial/option.c
@@ -241,6 +241,7 @@ static void option_instat_callback(struct urb *urb);
 #define QUECTEL_PRODUCT_EC21                    0x0121
 #define QUECTEL_PRODUCT_EC25                    0x0125
 #define QUECTEL_PRODUCT_BG96                    0x0296
+#define QUECTEL_PRODUCT_EP06                    0x0306
 
 #define CMOTECH_VENDOR_ID                       0x16d8
 #define CMOTECH_PRODUCT_6001                    0x6001
@@ -689,6 +690,10 @@ static const struct option_blacklist_info yuga_clm920_nc5_blacklist = {
         .reserved = BIT(1) | BIT(4),
 };
 
+static const struct option_blacklist_info quectel_ep06_blacklist = {
+        .reserved = BIT(4) | BIT(5),
+};
+
 static const struct usb_device_id option_ids[] = {
         { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_COLT) },
         { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_RICOLA) },
@@ -1203,6 +1208,8 @@ static const struct usb_device_id option_ids[] = {
           .driver_info = (kernel_ulong_t)&net_intf4_blacklist },
         { USB_DEVICE(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_BG96),
           .driver_info = (kernel_ulong_t)&net_intf4_blacklist },
+        { USB_DEVICE(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EP06),
+          .driver_info = (kernel_ulong_t)&quectel_ep06_blacklist },
         { USB_DEVICE(CMOTECH_VENDOR_ID, CMOTECH_PRODUCT_6001) },
         { USB_DEVICE(CMOTECH_VENDOR_ID, CMOTECH_PRODUCT_CMU_300) },
         { USB_DEVICE(CMOTECH_VENDOR_ID, CMOTECH_PRODUCT_6003),
diff --git a/drivers/usb/usbip/stub_dev.c b/drivers/usb/usbip/stub_dev.c
index 49e552472c3f..dd8ef36ab10e 100644
--- a/drivers/usb/usbip/stub_dev.c
+++ b/drivers/usb/usbip/stub_dev.c
@@ -73,6 +73,7 @@ static ssize_t usbip_sockfd_store(struct device *dev, struct device_attribute *a
                         goto err;
 
                 sdev->ud.tcp_socket = socket;
+                sdev->ud.sockfd = sockfd;
 
                 spin_unlock_irq(&sdev->ud.lock);
 
@@ -172,6 +173,7 @@ static void stub_shutdown_connection(struct usbip_device *ud)
         if (ud->tcp_socket) {
                 sockfd_put(ud->tcp_socket);
                 ud->tcp_socket = NULL;
+                ud->sockfd = -1;
         }
 
         /* 3. free used data */
@@ -266,6 +268,7 @@ static struct stub_device *stub_device_alloc(struct usb_device *udev)
         sdev->ud.status         = SDEV_ST_AVAILABLE;
         spin_lock_init(&sdev->ud.lock);
         sdev->ud.tcp_socket     = NULL;
+        sdev->ud.sockfd         = -1;
 
         INIT_LIST_HEAD(&sdev->priv_init);
         INIT_LIST_HEAD(&sdev->priv_tx);
diff --git a/drivers/usb/usbip/vhci_hcd.c b/drivers/usb/usbip/vhci_hcd.c
index c3e1008aa491..20e3d4609583 100644
--- a/drivers/usb/usbip/vhci_hcd.c
+++ b/drivers/usb/usbip/vhci_hcd.c
@@ -984,6 +984,7 @@ static void vhci_shutdown_connection(struct usbip_device *ud)
         if (vdev->ud.tcp_socket) {
                 sockfd_put(vdev->ud.tcp_socket);
                 vdev->ud.tcp_socket = NULL;
+                vdev->ud.sockfd = -1;
         }
         pr_info("release socket\n");
 
@@ -1030,6 +1031,7 @@ static void vhci_device_reset(struct usbip_device *ud)
         if (ud->tcp_socket) {
                 sockfd_put(ud->tcp_socket);
                 ud->tcp_socket = NULL;
+                ud->sockfd = -1;
         }
         ud->status = VDEV_ST_NULL;
 
diff --git a/drivers/vfio/vfio_iommu_type1.c b/drivers/vfio/vfio_iommu_type1.c
index e30e29ae4819..45657e2b1ff7 100644
--- a/drivers/vfio/vfio_iommu_type1.c
+++ b/drivers/vfio/vfio_iommu_type1.c
@@ -338,11 +338,12 @@ static int vaddr_get_pfn(struct mm_struct *mm, unsigned long vaddr,
 {
         struct page *page[1];
         struct vm_area_struct *vma;
+        struct vm_area_struct *vmas[1];
         int ret;
 
         if (mm == current->mm) {
-                ret = get_user_pages_fast(vaddr, 1, !!(prot & IOMMU_WRITE),
-                                          page);
+                ret = get_user_pages_longterm(vaddr, 1, !!(prot & IOMMU_WRITE),
+                                              page, vmas);
         } else {
                 unsigned int flags = 0;
 
@@ -351,7 +352,18 @@ static int vaddr_get_pfn(struct mm_struct *mm, unsigned long vaddr,
 
                 down_read(&mm->mmap_sem);
                 ret = get_user_pages_remote(NULL, mm, vaddr, 1, flags, page,
-                                            NULL, NULL);
+                                            vmas, NULL);
+                /*
+                 * The lifetime of a vaddr_get_pfn() page pin is
+                 * userspace-controlled. In the fs-dax case this could
+                 * lead to indefinite stalls in filesystem operations.
+                 * Disallow attempts to pin fs-dax pages via this
+                 * interface.
+                 */
+                if (ret > 0 && vma_is_fsdax(vmas[0])) {
+                        ret = -EOPNOTSUPP;
+                        put_page(page[0]);
+                }
                 up_read(&mm->mmap_sem);
         }
 
diff --git a/drivers/video/fbdev/geode/video_gx.c b/drivers/video/fbdev/geode/video_gx.c
index 6082f653c68a..67773e8bbb95 100644
--- a/drivers/video/fbdev/geode/video_gx.c
+++ b/drivers/video/fbdev/geode/video_gx.c
@@ -127,7 +127,7 @@ void gx_set_dclk_frequency(struct fb_info *info)
         int timeout = 1000;
 
         /* Rev. 1 Geode GXs use a 14 MHz reference clock instead of 48 MHz. */
-        if (cpu_data(0).x86_mask == 1) {
+        if (cpu_data(0).x86_stepping == 1) {
                 pll_table = gx_pll_table_14MHz;
                 pll_table_len = ARRAY_SIZE(gx_pll_table_14MHz);
         } else {
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index aff773bcebdb..37460cd6cabb 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -226,6 +226,7 @@ config ZIIRAVE_WATCHDOG
 config RAVE_SP_WATCHDOG
         tristate "RAVE SP Watchdog timer"
         depends on RAVE_SP_CORE
+        depends on NVMEM || !NVMEM
         select WATCHDOG_CORE
         help
           Support for the watchdog on RAVE SP device.
@@ -903,6 +904,7 @@ config F71808E_WDT
 config SP5100_TCO
         tristate "AMD/ATI SP5100 TCO Timer/Watchdog"
         depends on X86 && PCI
+        select WATCHDOG_CORE
         ---help---
           Hardware watchdog driver for the AMD/ATI SP5100 chipset. The TCO
           (Total Cost of Ownership) timer is a watchdog timer that will reboot
@@ -1008,6 +1010,7 @@ config WAFER_WDT
 config I6300ESB_WDT
         tristate "Intel 6300ESB Timer/Watchdog"
         depends on PCI
+        select WATCHDOG_CORE
         ---help---
           Hardware driver for the watchdog timer built into the Intel
           6300ESB controller hub.
@@ -1837,6 +1840,7 @@ config WATCHDOG_SUN4V
 config XEN_WDT
         tristate "Xen Watchdog support"
         depends on XEN
+        select WATCHDOG_CORE
         help
           Say Y here to support the hypervisor watchdog capability provided
           by Xen 4.0 and newer.  The watchdog timeout period is normally one
diff --git a/drivers/xen/events/events_base.c b/drivers/xen/events/events_base.c
index 1ab4bd11f5f3..762378f1811c 100644
--- a/drivers/xen/events/events_base.c
+++ b/drivers/xen/events/events_base.c
@@ -755,8 +755,8 @@ out:
         mutex_unlock(&irq_mapping_update_lock);
         return irq;
 error_irq:
-        for (; i >= 0; i--)
-                __unbind_from_irq(irq + i);
+        while (nvec--)
+                __unbind_from_irq(irq + nvec);
         mutex_unlock(&irq_mapping_update_lock);
         return ret;
 }
diff --git a/drivers/xen/pvcalls-back.c b/drivers/xen/pvcalls-back.c
index 156e5aea36db..b1092fbefa63 100644
--- a/drivers/xen/pvcalls-back.c
+++ b/drivers/xen/pvcalls-back.c
@@ -416,7 +416,7 @@ static int pvcalls_back_connect(struct xenbus_device *dev,
                                         sock);
         if (!map) {
                 ret = -EFAULT;
-                sock_release(map->sock);
+                sock_release(sock);
         }
 
 out:
diff --git a/drivers/xen/pvcalls-front.c b/drivers/xen/pvcalls-front.c
index 753d9cb437d0..2f11ca72a281 100644
--- a/drivers/xen/pvcalls-front.c
+++ b/drivers/xen/pvcalls-front.c
@@ -60,6 +60,7 @@ struct sock_mapping {
         bool active_socket;
         struct list_head list;
         struct socket *sock;
+        atomic_t refcount;
         union {
                 struct {
                         int irq;
@@ -72,20 +73,25 @@ struct sock_mapping {
                         wait_queue_head_t inflight_conn_req;
                 } active;
                 struct {
-                /* Socket status */
+                /*
+                 * Socket status, needs to be 64-bit aligned due to the
+                 * test_and_* functions which have this requirement on arm64.
+                 */
 #define PVCALLS_STATUS_UNINITALIZED  0
 #define PVCALLS_STATUS_BIND          1
 #define PVCALLS_STATUS_LISTEN        2
-                        uint8_t status;
+                        uint8_t status __attribute__((aligned(8)));
                 /*
                  * Internal state-machine flags.
                  * Only one accept operation can be inflight for a socket.
                  * Only one poll operation can be inflight for a given socket.
+                 * flags needs to be 64-bit aligned due to the test_and_*
+                 * functions which have this requirement on arm64.
                  */
 #define PVCALLS_FLAG_ACCEPT_INFLIGHT 0
 #define PVCALLS_FLAG_POLL_INFLIGHT   1
 #define PVCALLS_FLAG_POLL_RET        2
-                        uint8_t flags;
+                        uint8_t flags __attribute__((aligned(8)));
                         uint32_t inflight_req_id;
                         struct sock_mapping *accept_map;
                         wait_queue_head_t inflight_accept_req;
@@ -93,6 +99,32 @@ struct sock_mapping {
         };
 };
 
+static inline struct sock_mapping *pvcalls_enter_sock(struct socket *sock)
+{
+        struct sock_mapping *map;
+
+        if (!pvcalls_front_dev ||
+                dev_get_drvdata(&pvcalls_front_dev->dev) == NULL)
+                return ERR_PTR(-ENOTCONN);
+
+        map = (struct sock_mapping *)sock->sk->sk_send_head;
+        if (map == NULL)
+                return ERR_PTR(-ENOTSOCK);
+
+        pvcalls_enter();
+        atomic_inc(&map->refcount);
+        return map;
+}
+
+static inline void pvcalls_exit_sock(struct socket *sock)
+{
+        struct sock_mapping *map;
+
+        map = (struct sock_mapping *)sock->sk->sk_send_head;
+        atomic_dec(&map->refcount);
+        pvcalls_exit();
+}
+
 static inline int get_request(struct pvcalls_bedata *bedata, int *req_id)
 {
         *req_id = bedata->ring.req_prod_pvt & (RING_SIZE(&bedata->ring) - 1);
@@ -369,31 +401,23 @@ int pvcalls_front_connect(struct socket *sock, struct sockaddr *addr,
         if (addr->sa_family != AF_INET || sock->type != SOCK_STREAM)
                 return -EOPNOTSUPP;
 
-        pvcalls_enter();
-        if (!pvcalls_front_dev) {
-                pvcalls_exit();
-                return -ENOTCONN;
-        }
+        map = pvcalls_enter_sock(sock);
+        if (IS_ERR(map))
+                return PTR_ERR(map);
 
         bedata = dev_get_drvdata(&pvcalls_front_dev->dev);
 
-        map = (struct sock_mapping *)sock->sk->sk_send_head;
-        if (!map) {
-                pvcalls_exit();
-                return -ENOTSOCK;
-        }
-
         spin_lock(&bedata->socket_lock);
         ret = get_request(bedata, &req_id);
         if (ret < 0) {
                 spin_unlock(&bedata->socket_lock);
-                pvcalls_exit();
+                pvcalls_exit_sock(sock);
                 return ret;
         }
         ret = create_active(map, &evtchn);
         if (ret < 0) {
                 spin_unlock(&bedata->socket_lock);
-                pvcalls_exit();
+                pvcalls_exit_sock(sock);
                 return ret;
         }
 
@@ -423,7 +447,7 @@ int pvcalls_front_connect(struct socket *sock, struct sockaddr *addr,
         smp_rmb();
         ret = bedata->rsp[req_id].ret;
         bedata->rsp[req_id].req_id = PVCALLS_INVALID_ID;
-        pvcalls_exit();
+        pvcalls_exit_sock(sock);
         return ret;
 }
 
@@ -488,23 +512,15 @@ int pvcalls_front_sendmsg(struct socket *sock, struct msghdr *msg,
         if (flags & (MSG_CONFIRM|MSG_DONTROUTE|MSG_EOR|MSG_OOB))
                 return -EOPNOTSUPP;
 
-        pvcalls_enter();
-        if (!pvcalls_front_dev) {
-                pvcalls_exit();
-                return -ENOTCONN;
-        }
+        map = pvcalls_enter_sock(sock);
+        if (IS_ERR(map))
+                return PTR_ERR(map);
         bedata = dev_get_drvdata(&pvcalls_front_dev->dev);
 
-        map = (struct sock_mapping *) sock->sk->sk_send_head;
-        if (!map) {
-                pvcalls_exit();
-                return -ENOTSOCK;
-        }
-
         mutex_lock(&map->active.out_mutex);
         if ((flags & MSG_DONTWAIT) && !pvcalls_front_write_todo(map)) {
                 mutex_unlock(&map->active.out_mutex);
-                pvcalls_exit();
+                pvcalls_exit_sock(sock);
                 return -EAGAIN;
         }
         if (len > INT_MAX)
@@ -526,7 +542,7 @@ again:
                 tot_sent = sent;
 
         mutex_unlock(&map->active.out_mutex);
-        pvcalls_exit();
+        pvcalls_exit_sock(sock);
         return tot_sent;
 }
 
@@ -591,19 +607,11 @@ int pvcalls_front_recvmsg(struct socket *sock, struct msghdr *msg, size_t len,
         if (flags & (MSG_CMSG_CLOEXEC|MSG_ERRQUEUE|MSG_OOB|MSG_TRUNC))
                 return -EOPNOTSUPP;
 
-        pvcalls_enter();
-        if (!pvcalls_front_dev) {
-                pvcalls_exit();
-                return -ENOTCONN;
-        }
+        map = pvcalls_enter_sock(sock);
+        if (IS_ERR(map))
+                return PTR_ERR(map);
         bedata = dev_get_drvdata(&pvcalls_front_dev->dev);
 
-        map = (struct sock_mapping *) sock->sk->sk_send_head;
-        if (!map) {
-                pvcalls_exit();
-                return -ENOTSOCK;
-        }
-
         mutex_lock(&map->active.in_mutex);
         if (len > XEN_FLEX_RING_SIZE(PVCALLS_RING_ORDER))
                 len = XEN_FLEX_RING_SIZE(PVCALLS_RING_ORDER);
@@ -623,7 +631,7 @@ int pvcalls_front_recvmsg(struct socket *sock, struct msghdr *msg, size_t len,
                 ret = 0;
 
         mutex_unlock(&map->active.in_mutex);
-        pvcalls_exit();
+        pvcalls_exit_sock(sock);
         return ret;
 }
 
@@ -637,24 +645,16 @@ int pvcalls_front_bind(struct socket *sock, struct sockaddr *addr, int addr_len)
         if (addr->sa_family != AF_INET || sock->type != SOCK_STREAM)
                 return -EOPNOTSUPP;
 
-        pvcalls_enter();
-        if (!pvcalls_front_dev) {
-                pvcalls_exit();
-                return -ENOTCONN;
-        }
+        map = pvcalls_enter_sock(sock);
+        if (IS_ERR(map))
+                return PTR_ERR(map);
         bedata = dev_get_drvdata(&pvcalls_front_dev->dev);
 
-        map = (struct sock_mapping *) sock->sk->sk_send_head;
-        if (map == NULL) {
-                pvcalls_exit();
-                return -ENOTSOCK;
-        }
-
         spin_lock(&bedata->socket_lock);
         ret = get_request(bedata, &req_id);
         if (ret < 0) {
                 spin_unlock(&bedata->socket_lock);
-                pvcalls_exit();
+                pvcalls_exit_sock(sock);
                 return ret;
         }
         req = RING_GET_REQUEST(&bedata->ring, req_id);
@@ -684,7 +684,7 @@ int pvcalls_front_bind(struct socket *sock, struct sockaddr *addr, int addr_len)
         bedata->rsp[req_id].req_id = PVCALLS_INVALID_ID;
 
         map->passive.status = PVCALLS_STATUS_BIND;
-        pvcalls_exit();
+        pvcalls_exit_sock(sock);
         return 0;
 }
 
@@ -695,21 +695,13 @@ int pvcalls_front_listen(struct socket *sock, int backlog)
         struct xen_pvcalls_request *req;
         int notify, req_id, ret;
 
-        pvcalls_enter();
-        if (!pvcalls_front_dev) {
-                pvcalls_exit();
-                return -ENOTCONN;
-        }
+        map = pvcalls_enter_sock(sock);
+        if (IS_ERR(map))
+                return PTR_ERR(map);
         bedata = dev_get_drvdata(&pvcalls_front_dev->dev);
 
-        map = (struct sock_mapping *) sock->sk->sk_send_head;
-        if (!map) {
-                pvcalls_exit();
-                return -ENOTSOCK;
-        }
-
         if (map->passive.status != PVCALLS_STATUS_BIND) {
-                pvcalls_exit();
+                pvcalls_exit_sock(sock);
                 return -EOPNOTSUPP;
         }
 
@@ -717,7 +709,7 @@ int pvcalls_front_listen(struct socket *sock, int backlog)
         ret = get_request(bedata, &req_id);
         if (ret < 0) {
                 spin_unlock(&bedata->socket_lock);
-                pvcalls_exit();
+                pvcalls_exit_sock(sock);
                 return ret;
         }
         req = RING_GET_REQUEST(&bedata->ring, req_id);
@@ -741,7 +733,7 @@ int pvcalls_front_listen(struct socket *sock, int backlog)
         bedata->rsp[req_id].req_id = PVCALLS_INVALID_ID;
 
         map->passive.status = PVCALLS_STATUS_LISTEN;
-        pvcalls_exit();
+        pvcalls_exit_sock(sock);
         return ret;
 }
 
@@ -753,21 +745,13 @@ int pvcalls_front_accept(struct socket *sock, struct socket *newsock, int flags)
         struct xen_pvcalls_request *req;
         int notify, req_id, ret, evtchn, nonblock;
 
-        pvcalls_enter();
-        if (!pvcalls_front_dev) {
-                pvcalls_exit();
-                return -ENOTCONN;
-        }
+        map = pvcalls_enter_sock(sock);
+        if (IS_ERR(map))
+                return PTR_ERR(map);
         bedata = dev_get_drvdata(&pvcalls_front_dev->dev);
 
-        map = (struct sock_mapping *) sock->sk->sk_send_head;
-        if (!map) {
-                pvcalls_exit();
-                return -ENOTSOCK;
-        }
-
         if (map->passive.status != PVCALLS_STATUS_LISTEN) {
-                pvcalls_exit();
+                pvcalls_exit_sock(sock);
                 return -EINVAL;
         }
 
@@ -785,13 +769,13 @@ int pvcalls_front_accept(struct socket *sock, struct socket *newsock, int flags)
                         goto received;
                 }
                 if (nonblock) {
-                        pvcalls_exit();
+                        pvcalls_exit_sock(sock);
                         return -EAGAIN;
                 }
                 if (wait_event_interruptible(map->passive.inflight_accept_req,
                         !test_and_set_bit(PVCALLS_FLAG_ACCEPT_INFLIGHT,
                                           (void *)&map->passive.flags))) {
-                        pvcalls_exit();
+                        pvcalls_exit_sock(sock);
                         return -EINTR;
                 }
         }
@@ -802,7 +786,7 @@ int pvcalls_front_accept(struct socket *sock, struct socket *newsock, int flags)
                 clear_bit(PVCALLS_FLAG_ACCEPT_INFLIGHT,
                           (void *)&map->passive.flags);
                 spin_unlock(&bedata->socket_lock);
-                pvcalls_exit();
+                pvcalls_exit_sock(sock);
                 return ret;
         }
         map2 = kzalloc(sizeof(*map2), GFP_ATOMIC);
@@ -810,7 +794,7 @@ int pvcalls_front_accept(struct socket *sock, struct socket *newsock, int flags)
                 clear_bit(PVCALLS_FLAG_ACCEPT_INFLIGHT,
                           (void *)&map->passive.flags);
                 spin_unlock(&bedata->socket_lock);
-                pvcalls_exit();
+                pvcalls_exit_sock(sock);
                 return -ENOMEM;
         }
         ret = create_active(map2, &evtchn);
@@ -819,7 +803,7 @@ int pvcalls_front_accept(struct socket *sock, struct socket *newsock, int flags)
                 clear_bit(PVCALLS_FLAG_ACCEPT_INFLIGHT,
                           (void *)&map->passive.flags);
                 spin_unlock(&bedata->socket_lock);
-                pvcalls_exit();
+                pvcalls_exit_sock(sock);
                 return ret;
         }
         list_add_tail(&map2->list, &bedata->socket_mappings);
@@ -841,13 +825,13 @@ int pvcalls_front_accept(struct socket *sock, struct socket *newsock, int flags)
         /* We could check if we have received a response before returning. */
         if (nonblock) {
                 WRITE_ONCE(map->passive.inflight_req_id, req_id);
-                pvcalls_exit();
+                pvcalls_exit_sock(sock);
                 return -EAGAIN;
         }
 
         if (wait_event_interruptible(bedata->inflight_req,
                 READ_ONCE(bedata->rsp[req_id].req_id) == req_id)) {
-                pvcalls_exit();
+                pvcalls_exit_sock(sock);
                 return -EINTR;
         }
         /* read req_id, then the content */
@@ -862,7 +846,7 @@ received:
                 clear_bit(PVCALLS_FLAG_ACCEPT_INFLIGHT,
                           (void *)&map->passive.flags);
                 pvcalls_front_free_map(bedata, map2);
-                pvcalls_exit();
+                pvcalls_exit_sock(sock);
                 return -ENOMEM;
         }
         newsock->sk->sk_send_head = (void *)map2;
@@ -874,7 +858,7 @@ received:
         clear_bit(PVCALLS_FLAG_ACCEPT_INFLIGHT, (void *)&map->passive.flags);
         wake_up(&map->passive.inflight_accept_req);
 
-        pvcalls_exit();
+        pvcalls_exit_sock(sock);
         return ret;
 }
 
@@ -965,23 +949,16 @@ __poll_t pvcalls_front_poll(struct file *file, struct socket *sock,
         struct sock_mapping *map;
         __poll_t ret;
 
-        pvcalls_enter();
-        if (!pvcalls_front_dev) {
-                pvcalls_exit();
+        map = pvcalls_enter_sock(sock);
+        if (IS_ERR(map))
                 return EPOLLNVAL;
-        }
         bedata = dev_get_drvdata(&pvcalls_front_dev->dev);
 
-        map = (struct sock_mapping *) sock->sk->sk_send_head;
-        if (!map) {
-                pvcalls_exit();
-                return EPOLLNVAL;
-        }
         if (map->active_socket)
                 ret = pvcalls_front_poll_active(file, bedata, map, wait);
         else
                 ret = pvcalls_front_poll_passive(file, bedata, map, wait);
-        pvcalls_exit();
+        pvcalls_exit_sock(sock);
         return ret;
 }
 
@@ -995,25 +972,20 @@ int pvcalls_front_release(struct socket *sock)
         if (sock->sk == NULL)
                 return 0;
 
-        pvcalls_enter();
-        if (!pvcalls_front_dev) {
-                pvcalls_exit();
-                return -EIO;
+        map = pvcalls_enter_sock(sock);
+        if (IS_ERR(map)) {
+                if (PTR_ERR(map) == -ENOTCONN)
+                        return -EIO;
+                else
+                        return 0;
         }
-
         bedata = dev_get_drvdata(&pvcalls_front_dev->dev);
 
-        map = (struct sock_mapping *) sock->sk->sk_send_head;
-        if (map == NULL) {
-                pvcalls_exit();
-                return 0;
-        }
-
         spin_lock(&bedata->socket_lock);
         ret = get_request(bedata, &req_id);
         if (ret < 0) {
                 spin_unlock(&bedata->socket_lock);
-                pvcalls_exit();
+                pvcalls_exit_sock(sock);
                 return ret;
         }
         sock->sk->sk_send_head = NULL;
@@ -1043,14 +1015,20 @@ int pvcalls_front_release(struct socket *sock)
                 /*
                  * We need to make sure that sendmsg/recvmsg on this socket have
                  * not started before we've cleared sk_send_head here. The
-                 * easiest (though not optimal) way to guarantee this is to see
-                 * that no pvcall (other than us) is in progress.
+                 * easiest way to guarantee this is to see that no pvcalls
+                 * (other than us) is in progress on this socket.
                  */
-                while (atomic_read(&pvcalls_refcount) > 1)
+                while (atomic_read(&map->refcount) > 1)
                         cpu_relax();
 
                 pvcalls_front_free_map(bedata, map);
         } else {
+                wake_up(&bedata->inflight_req);
+                wake_up(&map->passive.inflight_accept_req);
+
+                while (atomic_read(&map->refcount) > 1)
+                        cpu_relax();
+
                 spin_lock(&bedata->socket_lock);
                 list_del(&map->list);
                 spin_unlock(&bedata->socket_lock);
diff --git a/drivers/xen/tmem.c b/drivers/xen/tmem.c
index bf13d1ec51f3..04e7b3b29bac 100644
--- a/drivers/xen/tmem.c
+++ b/drivers/xen/tmem.c
@@ -284,6 +284,10 @@ static int tmem_frontswap_store(unsigned type, pgoff_t offset,
         int pool = tmem_frontswap_poolid;
         int ret;
 
+        /* THP isn't supported */
+        if (PageTransHuge(page))
+                return -1;
+
         if (pool < 0)
                 return -1;
         if (ind64 != ind)
diff --git a/drivers/xen/xenbus/xenbus.h b/drivers/xen/xenbus/xenbus.h
index 149c5e7efc89..092981171df1 100644
--- a/drivers/xen/xenbus/xenbus.h
+++ b/drivers/xen/xenbus/xenbus.h
@@ -76,6 +76,7 @@ struct xb_req_data {
         struct list_head list;
         wait_queue_head_t wq;
         struct xsd_sockmsg msg;
+        uint32_t caller_req_id;
         enum xsd_sockmsg_type type;
         char *body;
         const struct kvec *vec;
diff --git a/drivers/xen/xenbus/xenbus_comms.c b/drivers/xen/xenbus/xenbus_comms.c
index 5b081a01779d..d239fc3c5e3d 100644
--- a/drivers/xen/xenbus/xenbus_comms.c
+++ b/drivers/xen/xenbus/xenbus_comms.c
@@ -309,6 +309,7 @@ static int process_msg(void)
                         goto out;
 
                 if (req->state == xb_req_state_wait_reply) {
+                        req->msg.req_id = req->caller_req_id;
                         req->msg.type = state.msg.type;
                         req->msg.len = state.msg.len;
                         req->body = state.body;
diff --git a/drivers/xen/xenbus/xenbus_xs.c b/drivers/xen/xenbus/xenbus_xs.c
index 3e59590c7254..3f3b29398ab8 100644
--- a/drivers/xen/xenbus/xenbus_xs.c
+++ b/drivers/xen/xenbus/xenbus_xs.c
@@ -227,6 +227,8 @@ static void xs_send(struct xb_req_data *req, struct xsd_sockmsg *msg)
         req->state = xb_req_state_queued;
         init_waitqueue_head(&req->wq);
 
+        /* Save the caller req_id and restore it later in the reply */
+        req->caller_req_id = req->msg.req_id;
         req->msg.req_id = xs_request_enter(req);
 
         mutex_lock(&xb_write_mutex);
@@ -310,6 +312,7 @@ static void *xs_talkv(struct xenbus_transaction t,
         req->num_vecs = num_vecs;
         req->cb = xs_wake_up;
 
+        msg.req_id = 0;
         msg.tx_id = t.id;
         msg.type = type;
         msg.len = 0;
diff --git a/fs/block_dev.c b/fs/block_dev.c
index 4a181fcb5175..fe09ef9c21f3 100644
--- a/fs/block_dev.c
+++ b/fs/block_dev.c
@@ -1058,6 +1058,27 @@ retry:
         return 0;
 }
 
+static struct gendisk *bdev_get_gendisk(struct block_device *bdev, int *partno)
+{
+        struct gendisk *disk = get_gendisk(bdev->bd_dev, partno);
+
+        if (!disk)
+                return NULL;
+        /*
+         * Now that we hold gendisk reference we make sure bdev we looked up is
+         * not stale. If it is, it means device got removed and created before
+         * we looked up gendisk and we fail open in such case. Associating
+         * unhashed bdev with newly created gendisk could lead to two bdevs
+         * (and thus two independent caches) being associated with one device
+         * which is bad.
+         */
+        if (inode_unhashed(bdev->bd_inode)) {
+                put_disk_and_module(disk);
+                return NULL;
+        }
+        return disk;
+}
+
 /**
  * bd_start_claiming - start claiming a block device
  * @bdev: block device of interest
@@ -1094,7 +1115,7 @@ static struct block_device *bd_start_claiming(struct block_device *bdev,
          * @bdev might not have been initialized properly yet, look up
          * and grab the outer block device the hard way.
          */
-        disk = get_gendisk(bdev->bd_dev, &partno);
+        disk = bdev_get_gendisk(bdev, &partno);
         if (!disk)
                 return ERR_PTR(-ENXIO);
 
@@ -1111,8 +1132,7 @@ static struct block_device *bd_start_claiming(struct block_device *bdev,
         else
                 whole = bdgrab(bdev);
 
-        module_put(disk->fops->owner);
-        put_disk(disk);
+        put_disk_and_module(disk);
         if (!whole)
                 return ERR_PTR(-ENOMEM);
 
@@ -1407,10 +1427,10 @@ static void __blkdev_put(struct block_device *bdev, fmode_t mode, int for_part);
 static int __blkdev_get(struct block_device *bdev, fmode_t mode, int for_part)
 {
         struct gendisk *disk;
-        struct module *owner;
         int ret;
         int partno;
         int perm = 0;
+        bool first_open = false;
 
         if (mode & FMODE_READ)
                 perm |= MAY_READ;
@@ -1430,14 +1450,14 @@ static int __blkdev_get(struct block_device *bdev, fmode_t mode, int for_part)
  restart:
 
         ret = -ENXIO;
-        disk = get_gendisk(bdev->bd_dev, &partno);
+        disk = bdev_get_gendisk(bdev, &partno);
         if (!disk)
                 goto out;
-        owner = disk->fops->owner;
 
         disk_block_events(disk);
         mutex_lock_nested(&bdev->bd_mutex, for_part);
         if (!bdev->bd_openers) {
+                first_open = true;
                 bdev->bd_disk = disk;
                 bdev->bd_queue = disk->queue;
                 bdev->bd_contains = bdev;
@@ -1463,8 +1483,7 @@ static int __blkdev_get(struct block_device *bdev, fmode_t mode, int for_part)
                                         bdev->bd_queue = NULL;
                                         mutex_unlock(&bdev->bd_mutex);
                                         disk_unblock_events(disk);
-                                        put_disk(disk);
-                                        module_put(owner);
+                                        put_disk_and_module(disk);
                                         goto restart;
                                 }
                         }
@@ -1524,15 +1543,15 @@ static int __blkdev_get(struct block_device *bdev, fmode_t mode, int for_part)
                         if (ret)
                                 goto out_unlock_bdev;
                 }
-                /* only one opener holds refs to the module and disk */
-                put_disk(disk);
-                module_put(owner);
         }
         bdev->bd_openers++;
         if (for_part)
                 bdev->bd_part_count++;
         mutex_unlock(&bdev->bd_mutex);
         disk_unblock_events(disk);
+        /* only one opener holds refs to the module and disk */
+        if (!first_open)
+                put_disk_and_module(disk);
         return 0;
 
  out_clear:
@@ -1546,8 +1565,7 @@ static int __blkdev_get(struct block_device *bdev, fmode_t mode, int for_part)
  out_unlock_bdev:
         mutex_unlock(&bdev->bd_mutex);
         disk_unblock_events(disk);
-        put_disk(disk);
-        module_put(owner);
+        put_disk_and_module(disk);
  out:
         bdput(bdev);
 
@@ -1770,8 +1788,6 @@ static void __blkdev_put(struct block_device *bdev, fmode_t mode, int for_part)
                         disk->fops->release(disk, mode);
         }
         if (!bdev->bd_openers) {
-                struct module *owner = disk->fops->owner;
-
                 disk_put_part(bdev->bd_part);
                 bdev->bd_part = NULL;
                 bdev->bd_disk = NULL;
@@ -1779,8 +1795,7 @@ static void __blkdev_put(struct block_device *bdev, fmode_t mode, int for_part)
                         victim = bdev->bd_contains;
                 bdev->bd_contains = NULL;
 
-                put_disk(disk);
-                module_put(owner);
+                put_disk_and_module(disk);
         }
         mutex_unlock(&bdev->bd_mutex);
         bdput(bdev);
diff --git a/fs/btrfs/backref.c b/fs/btrfs/backref.c
index e4054e533f6d..f94b2d8c744a 100644
--- a/fs/btrfs/backref.c
+++ b/fs/btrfs/backref.c
@@ -1264,7 +1264,16 @@ again:
         while (node) {
                 ref = rb_entry(node, struct prelim_ref, rbnode);
                 node = rb_next(&ref->rbnode);
-                WARN_ON(ref->count < 0);
+                /*
+                 * ref->count < 0 can happen here if there are delayed
+                 * refs with a node->action of BTRFS_DROP_DELAYED_REF.
+                 * prelim_ref_insert() relies on this when merging
+                 * identical refs to keep the overall count correct.
+                 * prelim_ref_insert() will merge only those refs
+                 * which compare identically.  Any refs having
+                 * e.g. different offsets would not be merged,
+                 * and would retain their original ref->count < 0.
+                 */
                 if (roots && ref->count && ref->root_id && ref->parent == 0) {
                         if (sc && sc->root_objectid &&
                             ref->root_id != sc->root_objectid) {
diff --git a/fs/btrfs/ctree.h b/fs/btrfs/ctree.h
index 1a462ab85c49..da308774b8a4 100644
--- a/fs/btrfs/ctree.h
+++ b/fs/btrfs/ctree.h
@@ -2974,7 +2974,7 @@ static inline void free_fs_info(struct btrfs_fs_info *fs_info)
         kfree(fs_info->super_copy);
         kfree(fs_info->super_for_commit);
         security_free_mnt_opts(&fs_info->security_opts);
-        kfree(fs_info);
+        kvfree(fs_info);
 }
 
 /* tree mod log functions from ctree.c */
@@ -3095,7 +3095,10 @@ btrfs_lookup_inode_extref(struct btrfs_trans_handle *trans,
                           u64 inode_objectid, u64 ref_objectid, int ins_len,
                           int cow);
 
-int btrfs_find_name_in_ext_backref(struct btrfs_path *path,
+int btrfs_find_name_in_backref(struct extent_buffer *leaf, int slot,
+                               const char *name,
+                               int name_len, struct btrfs_inode_ref **ref_ret);
+int btrfs_find_name_in_ext_backref(struct extent_buffer *leaf, int slot,
                                    u64 ref_objectid, const char *name,
                                    int name_len,
                                    struct btrfs_inode_extref **extref_ret);
diff --git a/fs/btrfs/delayed-ref.c b/fs/btrfs/delayed-ref.c
index a1a40cf382e3..7ab5e0128f0c 100644
--- a/fs/btrfs/delayed-ref.c
+++ b/fs/btrfs/delayed-ref.c
@@ -821,7 +821,8 @@ int btrfs_add_delayed_tree_ref(struct btrfs_fs_info *fs_info,
         spin_unlock(&delayed_refs->lock);
 
         if (qrecord_inserted)
-                return btrfs_qgroup_trace_extent_post(fs_info, record);
+                btrfs_qgroup_trace_extent_post(fs_info, record);
+
         return 0;
 
 free_head_ref:
diff --git a/fs/btrfs/extent-tree.c b/fs/btrfs/extent-tree.c
index 05751a677da4..c1618ab9fecf 100644
--- a/fs/btrfs/extent-tree.c
+++ b/fs/btrfs/extent-tree.c
@@ -2147,6 +2147,10 @@ int btrfs_discard_extent(struct btrfs_fs_info *fs_info, u64 bytenr,
                         u64 bytes;
                         struct request_queue *req_q;
 
+                        if (!stripe->dev->bdev) {
+                                ASSERT(btrfs_test_opt(fs_info, DEGRADED));
+                                continue;
+                        }
                         req_q = bdev_get_queue(stripe->dev->bdev);
                         if (!blk_queue_discard(req_q))
                                 continue;
diff --git a/fs/btrfs/inode-item.c b/fs/btrfs/inode-item.c
index 39c968f80157..65e1a76bf755 100644
--- a/fs/btrfs/inode-item.c
+++ b/fs/btrfs/inode-item.c
@@ -22,10 +22,10 @@
 #include "transaction.h"
 #include "print-tree.h"
 
-static int find_name_in_backref(struct btrfs_path *path, const char *name,
-                         int name_len, struct btrfs_inode_ref **ref_ret)
+int btrfs_find_name_in_backref(struct extent_buffer *leaf, int slot,
+                               const char *name,
+                               int name_len, struct btrfs_inode_ref **ref_ret)
 {
-        struct extent_buffer *leaf;
         struct btrfs_inode_ref *ref;
         unsigned long ptr;
         unsigned long name_ptr;
@@ -33,9 +33,8 @@ static int find_name_in_backref(struct btrfs_path *path, const char *name,
         u32 cur_offset = 0;
         int len;
 
-        leaf = path->nodes[0];
-        item_size = btrfs_item_size_nr(leaf, path->slots[0]);
-        ptr = btrfs_item_ptr_offset(leaf, path->slots[0]);
+        item_size = btrfs_item_size_nr(leaf, slot);
+        ptr = btrfs_item_ptr_offset(leaf, slot);
         while (cur_offset < item_size) {
                 ref = (struct btrfs_inode_ref *)(ptr + cur_offset);
                 len = btrfs_inode_ref_name_len(leaf, ref);
@@ -44,18 +43,19 @@ static int find_name_in_backref(struct btrfs_path *path, const char *name,
                 if (len != name_len)
                         continue;
                 if (memcmp_extent_buffer(leaf, name, name_ptr, name_len) == 0) {
-                        *ref_ret = ref;
+                        if (ref_ret)
+                                *ref_ret = ref;
                         return 1;
                 }
         }
         return 0;
 }
 
-int btrfs_find_name_in_ext_backref(struct btrfs_path *path, u64 ref_objectid,
+int btrfs_find_name_in_ext_backref(struct extent_buffer *leaf, int slot,
+                                   u64 ref_objectid,
                                    const char *name, int name_len,
                                    struct btrfs_inode_extref **extref_ret)
 {
-        struct extent_buffer *leaf;
         struct btrfs_inode_extref *extref;
         unsigned long ptr;
         unsigned long name_ptr;
@@ -63,9 +63,8 @@ int btrfs_find_name_in_ext_backref(struct btrfs_path *path, u64 ref_objectid,
         u32 cur_offset = 0;
         int ref_name_len;
 
-        leaf = path->nodes[0];
-        item_size = btrfs_item_size_nr(leaf, path->slots[0]);
-        ptr = btrfs_item_ptr_offset(leaf, path->slots[0]);
+        item_size = btrfs_item_size_nr(leaf, slot);
+        ptr = btrfs_item_ptr_offset(leaf, slot);
 
         /*
          * Search all extended backrefs in this item. We're only
@@ -113,7 +112,9 @@ btrfs_lookup_inode_extref(struct btrfs_trans_handle *trans,
                 return ERR_PTR(ret);
         if (ret > 0)
                 return NULL;
-        if (!btrfs_find_name_in_ext_backref(path, ref_objectid, name, name_len, &extref))
+        if (!btrfs_find_name_in_ext_backref(path->nodes[0], path->slots[0],
+                                            ref_objectid, name, name_len,
+                                            &extref))
                 return NULL;
         return extref;
 }
@@ -155,7 +156,8 @@ static int btrfs_del_inode_extref(struct btrfs_trans_handle *trans,
          * This should always succeed so error here will make the FS
          * readonly.
          */
-        if (!btrfs_find_name_in_ext_backref(path, ref_objectid,
+        if (!btrfs_find_name_in_ext_backref(path->nodes[0], path->slots[0],
+                                            ref_objectid,
                                             name, name_len, &extref)) {
                 btrfs_handle_fs_error(root->fs_info, -ENOENT, NULL);
                 ret = -EROFS;
@@ -225,7 +227,8 @@ int btrfs_del_inode_ref(struct btrfs_trans_handle *trans,
         } else if (ret < 0) {
                 goto out;
         }
-        if (!find_name_in_backref(path, name, name_len, &ref)) {
+        if (!btrfs_find_name_in_backref(path->nodes[0], path->slots[0],
+                                        name, name_len, &ref)) {
                 ret = -ENOENT;
                 search_ext_refs = 1;
                 goto out;
@@ -293,7 +296,9 @@ static int btrfs_insert_inode_extref(struct btrfs_trans_handle *trans,
         ret = btrfs_insert_empty_item(trans, root, path, &key,
                                       ins_len);
         if (ret == -EEXIST) {
-                if (btrfs_find_name_in_ext_backref(path, ref_objectid,
+                if (btrfs_find_name_in_ext_backref(path->nodes[0],
+                                                   path->slots[0],
+                                                   ref_objectid,
                                                    name, name_len, NULL))
                         goto out;
 
@@ -351,7 +356,8 @@ int btrfs_insert_inode_ref(struct btrfs_trans_handle *trans,
         if (ret == -EEXIST) {
                 u32 old_size;
 
-                if (find_name_in_backref(path, name, name_len, &ref))
+                if (btrfs_find_name_in_backref(path->nodes[0], path->slots[0],
+                                               name, name_len, &ref))
                         goto out;
 
                 old_size = btrfs_item_size_nr(path->nodes[0], path->slots[0]);
@@ -365,7 +371,9 @@ int btrfs_insert_inode_ref(struct btrfs_trans_handle *trans,
                 ret = 0;
         } else if (ret < 0) {
                 if (ret == -EOVERFLOW) {
-                        if (find_name_in_backref(path, name, name_len, &ref))
+                        if (btrfs_find_name_in_backref(path->nodes[0],
+                                                       path->slots[0],
+                                                       name, name_len, &ref))
                                 ret = -EEXIST;
                         else
                                 ret = -EMLINK;
diff --git a/fs/btrfs/inode.c b/fs/btrfs/inode.c
index 53ca025655fc..f53470112670 100644
--- a/fs/btrfs/inode.c
+++ b/fs/btrfs/inode.c
@@ -1335,8 +1335,11 @@ next_slot:
                 leaf = path->nodes[0];
                 if (path->slots[0] >= btrfs_header_nritems(leaf)) {
                         ret = btrfs_next_leaf(root, path);
-                        if (ret < 0)
+                        if (ret < 0) {
+                                if (cow_start != (u64)-1)
+                                        cur_offset = cow_start;
                                 goto error;
+                        }
                         if (ret > 0)
                                 break;
                         leaf = path->nodes[0];
@@ -2040,12 +2043,15 @@ static noinline int add_pending_csums(struct btrfs_trans_handle *trans,
                              struct inode *inode, struct list_head *list)
 {
         struct btrfs_ordered_sum *sum;
+        int ret;
 
         list_for_each_entry(sum, list, list) {
                 trans->adding_csums = true;
-                btrfs_csum_file_blocks(trans,
+                ret = btrfs_csum_file_blocks(trans,
                        BTRFS_I(inode)->root->fs_info->csum_root, sum);
                 trans->adding_csums = false;
+                if (ret)
+                        return ret;
         }
         return 0;
 }
@@ -3059,7 +3065,11 @@ static int btrfs_finish_ordered_io(struct btrfs_ordered_extent *ordered_extent)
                 goto out;
         }
 
-        add_pending_csums(trans, inode, &ordered_extent->list);
+        ret = add_pending_csums(trans, inode, &ordered_extent->list);
+        if (ret) {
+                btrfs_abort_transaction(trans, ret);
+                goto out;
+        }
 
         btrfs_ordered_update_i_size(inode, 0, ordered_extent);
         ret = btrfs_update_inode_fallback(trans, root, inode);
@@ -3385,6 +3395,11 @@ int btrfs_orphan_add(struct btrfs_trans_handle *trans,
                 ret = btrfs_orphan_reserve_metadata(trans, inode);
                 ASSERT(!ret);
                 if (ret) {
+                        /*
+                         * dec doesn't need spin_lock as ->orphan_block_rsv
+                         * would be released only if ->orphan_inodes is
+                         * zero.
+                         */
                         atomic_dec(&root->orphan_inodes);
                         clear_bit(BTRFS_INODE_ORPHAN_META_RESERVED,
                                   &inode->runtime_flags);
@@ -3399,12 +3414,17 @@ int btrfs_orphan_add(struct btrfs_trans_handle *trans,
         if (insert >= 1) {
                 ret = btrfs_insert_orphan_item(trans, root, btrfs_ino(inode));
                 if (ret) {
-                        atomic_dec(&root->orphan_inodes);
                         if (reserve) {
                                 clear_bit(BTRFS_INODE_ORPHAN_META_RESERVED,
                                           &inode->runtime_flags);
                                 btrfs_orphan_release_metadata(inode);
                         }
+                        /*
+                         * btrfs_orphan_commit_root may race with us and set
+                         * ->orphan_block_rsv to zero, in order to avoid that,
+                         * decrease ->orphan_inodes after everything is done.
+                         */
+                        atomic_dec(&root->orphan_inodes);
                         if (ret != -EEXIST) {
                                 clear_bit(BTRFS_INODE_HAS_ORPHAN_ITEM,
                                           &inode->runtime_flags);
@@ -3436,28 +3456,26 @@ static int btrfs_orphan_del(struct btrfs_trans_handle *trans,
 {
         struct btrfs_root *root = inode->root;
         int delete_item = 0;
-        int release_rsv = 0;
         int ret = 0;
 
-        spin_lock(&root->orphan_lock);
         if (test_and_clear_bit(BTRFS_INODE_HAS_ORPHAN_ITEM,
                                &inode->runtime_flags))
                 delete_item = 1;
 
+        if (delete_item && trans)
+                ret = btrfs_del_orphan_item(trans, root, btrfs_ino(inode));
+
         if (test_and_clear_bit(BTRFS_INODE_ORPHAN_META_RESERVED,
                                &inode->runtime_flags))
-                release_rsv = 1;
-        spin_unlock(&root->orphan_lock);
+                btrfs_orphan_release_metadata(inode);
 
-        if (delete_item) {
+        /*
+         * btrfs_orphan_commit_root may race with us and set ->orphan_block_rsv
+         * to zero, in order to avoid that, decrease ->orphan_inodes after
+         * everything is done.
+         */
+        if (delete_item)
                 atomic_dec(&root->orphan_inodes);
-                if (trans)
-                        ret = btrfs_del_orphan_item(trans, root,
-                                                    btrfs_ino(inode));
-        }
-
-        if (release_rsv)
-                btrfs_orphan_release_metadata(inode);
 
         return ret;
 }
@@ -5281,7 +5299,7 @@ void btrfs_evict_inode(struct inode *inode)
         trace_btrfs_inode_evict(inode);
 
         if (!root) {
-                kmem_cache_free(btrfs_inode_cachep, BTRFS_I(inode));
+                clear_inode(inode);
                 return;
         }
 
diff --git a/fs/btrfs/qgroup.c b/fs/btrfs/qgroup.c
index 9e61dd624f7b..aa259d6986e1 100644
--- a/fs/btrfs/qgroup.c
+++ b/fs/btrfs/qgroup.c
@@ -1442,8 +1442,13 @@ int btrfs_qgroup_trace_extent_post(struct btrfs_fs_info *fs_info,
         int ret;
 
         ret = btrfs_find_all_roots(NULL, fs_info, bytenr, 0, &old_root, false);
-        if (ret < 0)
-                return ret;
+        if (ret < 0) {
+                fs_info->qgroup_flags |= BTRFS_QGROUP_STATUS_FLAG_INCONSISTENT;
+                btrfs_warn(fs_info,
+"error accounting new delayed refs extent (err code: %d), quota inconsistent",
+                        ret);
+                return 0;
+        }
 
         /*
          * Here we don't need to get the lock of
diff --git a/fs/btrfs/relocation.c b/fs/btrfs/relocation.c
index f0c3f00e97cb..cd2298d185dd 100644
--- a/fs/btrfs/relocation.c
+++ b/fs/btrfs/relocation.c
@@ -3268,8 +3268,22 @@ static int relocate_file_extent_cluster(struct inode *inode,
                         nr++;
                 }
 
-                btrfs_set_extent_delalloc(inode, page_start, page_end, 0, NULL,
-                                          0);
+                ret = btrfs_set_extent_delalloc(inode, page_start, page_end, 0,
+                                                NULL, 0);
+                if (ret) {
+                        unlock_page(page);
+                        put_page(page);
+                        btrfs_delalloc_release_metadata(BTRFS_I(inode),
+                                                         PAGE_SIZE);
+                        btrfs_delalloc_release_extents(BTRFS_I(inode),
+                                                       PAGE_SIZE);
+
+                        clear_extent_bits(&BTRFS_I(inode)->io_tree,
+                                          page_start, page_end,
+                                          EXTENT_LOCKED | EXTENT_BOUNDARY);
+                        goto out;
+
+                }
                 set_page_dirty(page);
 
                 unlock_extent(&BTRFS_I(inode)->io_tree,
diff --git a/fs/btrfs/send.c b/fs/btrfs/send.c
index f306c608dc28..484e2af793de 100644
--- a/fs/btrfs/send.c
+++ b/fs/btrfs/send.c
@@ -5005,6 +5005,9 @@ static int send_hole(struct send_ctx *sctx, u64 end)
         u64 len;
         int ret = 0;
 
+        if (sctx->flags & BTRFS_SEND_FLAG_NO_FILE_DATA)
+                return send_update_extent(sctx, offset, end - offset);
+
         p = fs_path_alloc();
         if (!p)
                 return -ENOMEM;
diff --git a/fs/btrfs/super.c b/fs/btrfs/super.c
index 6e71a2a78363..4b817947e00f 100644
--- a/fs/btrfs/super.c
+++ b/fs/btrfs/super.c
@@ -1545,7 +1545,7 @@ static struct dentry *btrfs_mount_root(struct file_system_type *fs_type,
          * it for searching for existing supers, so this lets us do that and
          * then open_ctree will properly initialize everything later.
          */
-        fs_info = kzalloc(sizeof(struct btrfs_fs_info), GFP_KERNEL);
+        fs_info = kvzalloc(sizeof(struct btrfs_fs_info), GFP_KERNEL);
         if (!fs_info) {
                 error = -ENOMEM;
                 goto error_sec_opts;
diff --git a/fs/btrfs/sysfs.c b/fs/btrfs/sysfs.c
index a8bafed931f4..d11c70bff5a9 100644
--- a/fs/btrfs/sysfs.c
+++ b/fs/btrfs/sysfs.c
@@ -423,7 +423,7 @@ static ssize_t btrfs_nodesize_show(struct kobject *kobj,
 {
         struct btrfs_fs_info *fs_info = to_fs_info(kobj);
 
-        return snprintf(buf, PAGE_SIZE, "%u\n", fs_info->super_copy->nodesize);
+        return snprintf(buf, PAGE_SIZE, "%u\n", fs_info->nodesize);
 }
 
 BTRFS_ATTR(, nodesize, btrfs_nodesize_show);
@@ -433,8 +433,7 @@ static ssize_t btrfs_sectorsize_show(struct kobject *kobj,
 {
         struct btrfs_fs_info *fs_info = to_fs_info(kobj);
 
-        return snprintf(buf, PAGE_SIZE, "%u\n",
-                        fs_info->super_copy->sectorsize);
+        return snprintf(buf, PAGE_SIZE, "%u\n", fs_info->sectorsize);
 }
 
 BTRFS_ATTR(, sectorsize, btrfs_sectorsize_show);
@@ -444,8 +443,7 @@ static ssize_t btrfs_clone_alignment_show(struct kobject *kobj,
 {
         struct btrfs_fs_info *fs_info = to_fs_info(kobj);
 
-        return snprintf(buf, PAGE_SIZE, "%u\n",
-                        fs_info->super_copy->sectorsize);
+        return snprintf(buf, PAGE_SIZE, "%u\n", fs_info->sectorsize);
 }
 
 BTRFS_ATTR(, clone_alignment, btrfs_clone_alignment_show);
diff --git a/fs/btrfs/transaction.c b/fs/btrfs/transaction.c
index 04f07144b45c..9220f004001c 100644
--- a/fs/btrfs/transaction.c
+++ b/fs/btrfs/transaction.c
@@ -1722,19 +1722,23 @@ static void update_super_roots(struct btrfs_fs_info *fs_info)
 
         super = fs_info->super_copy;
 
+        /* update latest btrfs_super_block::chunk_root refs */
         root_item = &fs_info->chunk_root->root_item;
-        super->chunk_root = root_item->bytenr;
-        super->chunk_root_generation = root_item->generation;
-        super->chunk_root_level = root_item->level;
+        btrfs_set_super_chunk_root(super, root_item->bytenr);
+        btrfs_set_super_chunk_root_generation(super, root_item->generation);
+        btrfs_set_super_chunk_root_level(super, root_item->level);
 
+        /* update latest btrfs_super_block::root refs */
         root_item = &fs_info->tree_root->root_item;
-        super->root = root_item->bytenr;
-        super->generation = root_item->generation;
-        super->root_level = root_item->level;
+        btrfs_set_super_root(super, root_item->bytenr);
+        btrfs_set_super_generation(super, root_item->generation);
+        btrfs_set_super_root_level(super, root_item->level);
+
         if (btrfs_test_opt(fs_info, SPACE_CACHE))
-                super->cache_generation = root_item->generation;
+                btrfs_set_super_cache_generation(super, root_item->generation);
         if (test_bit(BTRFS_FS_UPDATE_UUID_TREE_GEN, &fs_info->flags))
-                super->uuid_tree_generation = root_item->generation;
+                btrfs_set_super_uuid_tree_generation(super,
+                                                     root_item->generation);
 }
 
 int btrfs_transaction_in_commit(struct btrfs_fs_info *info)
diff --git a/fs/btrfs/tree-log.c b/fs/btrfs/tree-log.c
index afadaadab18e..434457794c27 100644
--- a/fs/btrfs/tree-log.c
+++ b/fs/btrfs/tree-log.c
@@ -29,6 +29,7 @@
 #include "hash.h"
 #include "compression.h"
 #include "qgroup.h"
+#include "inode-map.h"
 
 /* magic values for the inode_only field in btrfs_log_inode:
  *
@@ -966,7 +967,9 @@ static noinline int backref_in_log(struct btrfs_root *log,
         ptr = btrfs_item_ptr_offset(path->nodes[0], path->slots[0]);
 
         if (key->type == BTRFS_INODE_EXTREF_KEY) {
-                if (btrfs_find_name_in_ext_backref(path, ref_objectid,
+                if (btrfs_find_name_in_ext_backref(path->nodes[0],
+                                                   path->slots[0],
+                                                   ref_objectid,
                                                    name, namelen, NULL))
                         match = 1;
 
@@ -1190,7 +1193,8 @@ static int extref_get_fields(struct extent_buffer *eb, unsigned long ref_ptr,
         read_extent_buffer(eb, *name, (unsigned long)&extref->name,
                            *namelen);
 
-        *index = btrfs_inode_extref_index(eb, extref);
+        if (index)
+                *index = btrfs_inode_extref_index(eb, extref);
         if (parent_objectid)
                 *parent_objectid = btrfs_inode_extref_parent(eb, extref);
 
@@ -1211,12 +1215,102 @@ static int ref_get_fields(struct extent_buffer *eb, unsigned long ref_ptr,
 
         read_extent_buffer(eb, *name, (unsigned long)(ref + 1), *namelen);
 
-        *index = btrfs_inode_ref_index(eb, ref);
+        if (index)
+                *index = btrfs_inode_ref_index(eb, ref);
 
         return 0;
 }
 
 /*
+ * Take an inode reference item from the log tree and iterate all names from the
+ * inode reference item in the subvolume tree with the same key (if it exists).
+ * For any name that is not in the inode reference item from the log tree, do a
+ * proper unlink of that name (that is, remove its entry from the inode
+ * reference item and both dir index keys).
+ */
+static int unlink_old_inode_refs(struct btrfs_trans_handle *trans,
+                                 struct btrfs_root *root,
+                                 struct btrfs_path *path,
+                                 struct btrfs_inode *inode,
+                                 struct extent_buffer *log_eb,
+                                 int log_slot,
+                                 struct btrfs_key *key)
+{
+        int ret;
+        unsigned long ref_ptr;
+        unsigned long ref_end;
+        struct extent_buffer *eb;
+
+again:
+        btrfs_release_path(path);
+        ret = btrfs_search_slot(NULL, root, key, path, 0, 0);
+        if (ret > 0) {
+                ret = 0;
+                goto out;
+        }
+        if (ret < 0)
+                goto out;
+
+        eb = path->nodes[0];
+        ref_ptr = btrfs_item_ptr_offset(eb, path->slots[0]);
+        ref_end = ref_ptr + btrfs_item_size_nr(eb, path->slots[0]);
+        while (ref_ptr < ref_end) {
+                char *name = NULL;
+                int namelen;
+                u64 parent_id;
+
+                if (key->type == BTRFS_INODE_EXTREF_KEY) {
+                        ret = extref_get_fields(eb, ref_ptr, &namelen, &name,
+                                                NULL, &parent_id);
+                } else {
+                        parent_id = key->offset;
+                        ret = ref_get_fields(eb, ref_ptr, &namelen, &name,
+                                             NULL);
+                }
+                if (ret)
+                        goto out;
+
+                if (key->type == BTRFS_INODE_EXTREF_KEY)
+                        ret = btrfs_find_name_in_ext_backref(log_eb, log_slot,
+                                                             parent_id, name,
+                                                             namelen, NULL);
+                else
+                        ret = btrfs_find_name_in_backref(log_eb, log_slot, name,
+                                                         namelen, NULL);
+
+                if (!ret) {
+                        struct inode *dir;
+
+                        btrfs_release_path(path);
+                        dir = read_one_inode(root, parent_id);
+                        if (!dir) {
+                                ret = -ENOENT;
+                                kfree(name);
+                                goto out;
+                        }
+                        ret = btrfs_unlink_inode(trans, root, BTRFS_I(dir),
+                                                 inode, name, namelen);
+                        kfree(name);
+                        iput(dir);
+                        if (ret)
+                                goto out;
+                        goto again;
+                }
+
+                kfree(name);
+                ref_ptr += namelen;
+                if (key->type == BTRFS_INODE_EXTREF_KEY)
+                        ref_ptr += sizeof(struct btrfs_inode_extref);
+                else
+                        ref_ptr += sizeof(struct btrfs_inode_ref);
+        }
+        ret = 0;
+ out:
+        btrfs_release_path(path);
+        return ret;
+}
+
+/*
  * replay one inode back reference item found in the log tree.
  * eb, slot and key refer to the buffer and key found in the log tree.
  * root is the destination we are replaying into, and path is for temp
@@ -1344,6 +1438,19 @@ static noinline int add_inode_ref(struct btrfs_trans_handle *trans,
                 }
         }
 
+        /*
+         * Before we overwrite the inode reference item in the subvolume tree
+         * with the item from the log tree, we must unlink all names from the
+         * parent directory that are in the subvolume's tree inode reference
+         * item, otherwise we end up with an inconsistent subvolume tree where
+         * dir index entries exist for a name but there is no inode reference
+         * item with the same name.
+         */
+        ret = unlink_old_inode_refs(trans, root, path, BTRFS_I(inode), eb, slot,
+                                    key);
+        if (ret)
+                goto out;
+
         /* finally write the back reference in the inode */
         ret = overwrite_item(trans, root, path, eb, slot, key);
 out:
@@ -2472,6 +2579,9 @@ static noinline int walk_down_log_tree(struct btrfs_trans_handle *trans,
                                         clean_tree_block(fs_info, next);
                                         btrfs_wait_tree_block_writeback(next);
                                         btrfs_tree_unlock(next);
+                                } else {
+                                        if (test_and_clear_bit(EXTENT_BUFFER_DIRTY, &next->bflags))
+                                                clear_extent_buffer_dirty(next);
                                 }
 
                                 WARN_ON(root_owner !=
@@ -2552,6 +2662,9 @@ static noinline int walk_up_log_tree(struct btrfs_trans_handle *trans,
                                         clean_tree_block(fs_info, next);
                                         btrfs_wait_tree_block_writeback(next);
                                         btrfs_tree_unlock(next);
+                                } else {
+                                        if (test_and_clear_bit(EXTENT_BUFFER_DIRTY, &next->bflags))
+                                                clear_extent_buffer_dirty(next);
                                 }
 
                                 WARN_ON(root_owner != BTRFS_TREE_LOG_OBJECTID);
@@ -2630,6 +2743,9 @@ static int walk_log_tree(struct btrfs_trans_handle *trans,
                                 clean_tree_block(fs_info, next);
                                 btrfs_wait_tree_block_writeback(next);
                                 btrfs_tree_unlock(next);
+                        } else {
+                                if (test_and_clear_bit(EXTENT_BUFFER_DIRTY, &next->bflags))
+                                        clear_extent_buffer_dirty(next);
                         }
 
                         WARN_ON(log->root_key.objectid !=
@@ -3018,13 +3134,14 @@ static void free_log_tree(struct btrfs_trans_handle *trans,
 
         while (1) {
                 ret = find_first_extent_bit(&log->dirty_log_pages,
-                                0, &start, &end, EXTENT_DIRTY | EXTENT_NEW,
+                                0, &start, &end,
+                                EXTENT_DIRTY | EXTENT_NEW | EXTENT_NEED_WAIT,
                                 NULL);
                 if (ret)
                         break;
 
                 clear_extent_bits(&log->dirty_log_pages, start, end,
-                                  EXTENT_DIRTY | EXTENT_NEW);
+                                  EXTENT_DIRTY | EXTENT_NEW | EXTENT_NEED_WAIT);
         }
 
         /*
@@ -5677,6 +5794,23 @@ again:
                                                       path);
                 }
 
+                if (!ret && wc.stage == LOG_WALK_REPLAY_ALL) {
+                        struct btrfs_root *root = wc.replay_dest;
+
+                        btrfs_release_path(path);
+
+                        /*
+                         * We have just replayed everything, and the highest
+                         * objectid of fs roots probably has changed in case
+                         * some inode_item's got replayed.
+                         *
+                         * root->objectid_mutex is not acquired as log replay
+                         * could only happen during mount.
+                         */
+                        ret = btrfs_find_highest_objectid(root,
+                                                  &root->highest_objectid);
+                }
+
                 key.offset = found_key.offset - 1;
                 wc.replay_dest->log_root = NULL;
                 free_extent_buffer(log->node);
@@ -5825,7 +5959,7 @@ int btrfs_log_new_name(struct btrfs_trans_handle *trans,
          * this will force the logging code to walk the dentry chain
          * up for the file
          */
-        if (S_ISREG(inode->vfs_inode.i_mode))
+        if (!S_ISDIR(inode->vfs_inode.i_mode))
                 inode->last_unlink_trans = trans->transid;
 
         /*
diff --git a/fs/btrfs/volumes.c b/fs/btrfs/volumes.c
index b5036bd69e6a..b2d05c6b1c56 100644
--- a/fs/btrfs/volumes.c
+++ b/fs/btrfs/volumes.c
@@ -645,6 +645,7 @@ static void btrfs_free_stale_devices(const char *path,
                                 btrfs_sysfs_remove_fsid(fs_devs);
                                 list_del(&fs_devs->list);
                                 free_fs_devices(fs_devs);
+                                break;
                         } else {
                                 fs_devs->num_devices--;
                                 list_del(&dev->dev_list);
@@ -4828,10 +4829,13 @@ static int __btrfs_alloc_chunk(struct btrfs_trans_handle *trans,
         ndevs = min(ndevs, devs_max);
 
         /*
-         * the primary goal is to maximize the number of stripes, so use as many
-         * devices as possible, even if the stripes are not maximum sized.
+         * The primary goal is to maximize the number of stripes, so use as
+         * many devices as possible, even if the stripes are not maximum sized.
+         *
+         * The DUP profile stores more than one stripe per device, the
+         * max_avail is the total size so we have to adjust.
          */
-        stripe_size = devices_info[ndevs-1].max_avail;
+        stripe_size = div_u64(devices_info[ndevs - 1].max_avail, dev_stripes);
         num_stripes = ndevs * dev_stripes;
 
         /*
@@ -4866,8 +4870,6 @@ static int __btrfs_alloc_chunk(struct btrfs_trans_handle *trans,
                         stripe_size = devices_info[ndevs-1].max_avail;
         }
 
-        stripe_size = div_u64(stripe_size, dev_stripes);
-
         /* align to BTRFS_STRIPE_LEN */
         stripe_size = round_down(stripe_size, BTRFS_STRIPE_LEN);
 
diff --git a/fs/ceph/caps.c b/fs/ceph/caps.c
index 6582c4507e6c..0e5bd3e3344e 100644
--- a/fs/ceph/caps.c
+++ b/fs/ceph/caps.c
@@ -3965,6 +3965,32 @@ void ceph_put_fmode(struct ceph_inode_info *ci, int fmode)
 }
 
 /*
+ * For a soon-to-be unlinked file, drop the AUTH_RDCACHE caps. If it
+ * looks like the link count will hit 0, drop any other caps (other
+ * than PIN) we don't specifically want (due to the file still being
+ * open).
+ */
+int ceph_drop_caps_for_unlink(struct inode *inode)
+{
+        struct ceph_inode_info *ci = ceph_inode(inode);
+        int drop = CEPH_CAP_LINK_SHARED | CEPH_CAP_LINK_EXCL;
+
+        spin_lock(&ci->i_ceph_lock);
+        if (inode->i_nlink == 1) {
+                drop |= ~(__ceph_caps_wanted(ci) | CEPH_CAP_PIN);
+
+                ci->i_ceph_flags |= CEPH_I_NODELAY;
+                if (__ceph_caps_dirty(ci)) {
+                        struct ceph_mds_client *mdsc =
+                                ceph_inode_to_client(inode)->mdsc;
+                        __cap_delay_requeue_front(mdsc, ci);
+                }
+        }
+        spin_unlock(&ci->i_ceph_lock);
+        return drop;
+}
+
+/*
  * Helpers for embedding cap and dentry lease releases into mds
  * requests.
  *
diff --git a/fs/ceph/dir.c b/fs/ceph/dir.c
index 0c4346806e17..f1d9c6cc0491 100644
--- a/fs/ceph/dir.c
+++ b/fs/ceph/dir.c
@@ -1003,26 +1003,6 @@ static int ceph_link(struct dentry *old_dentry, struct inode *dir,
 }
 
 /*
- * For a soon-to-be unlinked file, drop the AUTH_RDCACHE caps.  If it
- * looks like the link count will hit 0, drop any other caps (other
- * than PIN) we don't specifically want (due to the file still being
- * open).
- */
-static int drop_caps_for_unlink(struct inode *inode)
-{
-        struct ceph_inode_info *ci = ceph_inode(inode);
-        int drop = CEPH_CAP_LINK_SHARED | CEPH_CAP_LINK_EXCL;
-
-        spin_lock(&ci->i_ceph_lock);
-        if (inode->i_nlink == 1) {
-                drop |= ~(__ceph_caps_wanted(ci) | CEPH_CAP_PIN);
-                ci->i_ceph_flags |= CEPH_I_NODELAY;
-        }
-        spin_unlock(&ci->i_ceph_lock);
-        return drop;
-}
-
-/*
  * rmdir and unlink are differ only by the metadata op code
  */
 static int ceph_unlink(struct inode *dir, struct dentry *dentry)
@@ -1056,7 +1036,7 @@ static int ceph_unlink(struct inode *dir, struct dentry *dentry)
         set_bit(CEPH_MDS_R_PARENT_LOCKED, &req->r_req_flags);
         req->r_dentry_drop = CEPH_CAP_FILE_SHARED;
         req->r_dentry_unless = CEPH_CAP_FILE_EXCL;
-        req->r_inode_drop = drop_caps_for_unlink(inode);
+        req->r_inode_drop = ceph_drop_caps_for_unlink(inode);
         err = ceph_mdsc_do_request(mdsc, dir, req);
         if (!err && !req->r_reply_info.head->is_dentry)
                 d_delete(dentry);
@@ -1104,8 +1084,10 @@ static int ceph_rename(struct inode *old_dir, struct dentry *old_dentry,
         req->r_dentry_unless = CEPH_CAP_FILE_EXCL;
         /* release LINK_RDCACHE on source inode (mds will lock it) */
         req->r_old_inode_drop = CEPH_CAP_LINK_SHARED | CEPH_CAP_LINK_EXCL;
-        if (d_really_is_positive(new_dentry))
-                req->r_inode_drop = drop_caps_for_unlink(d_inode(new_dentry));
+        if (d_really_is_positive(new_dentry)) {
+                req->r_inode_drop =
+                        ceph_drop_caps_for_unlink(d_inode(new_dentry));
+        }
         err = ceph_mdsc_do_request(mdsc, old_dir, req);
         if (!err && !req->r_reply_info.head->is_dentry) {
                 /*
diff --git a/fs/ceph/super.c b/fs/ceph/super.c
index a62d2a9841dc..fb2bc9c15a23 100644
--- a/fs/ceph/super.c
+++ b/fs/ceph/super.c
@@ -225,6 +225,7 @@ static int parse_fsopt_token(char *c, void *private)
                         return -ENOMEM;
                 break;
         case Opt_mds_namespace:
+                kfree(fsopt->mds_namespace);
                 fsopt->mds_namespace = kstrndup(argstr[0].from,
                                                 argstr[0].to-argstr[0].from,
                                                 GFP_KERNEL);
@@ -232,6 +233,7 @@ static int parse_fsopt_token(char *c, void *private)
                         return -ENOMEM;
                 break;
         case Opt_fscache_uniq:
+                kfree(fsopt->fscache_uniq);
                 fsopt->fscache_uniq = kstrndup(argstr[0].from,
                                                argstr[0].to-argstr[0].from,
                                                GFP_KERNEL);
@@ -711,14 +713,17 @@ static int __init init_caches(void)
                 goto bad_dentry;
 
         ceph_file_cachep = KMEM_CACHE(ceph_file_info, SLAB_MEM_SPREAD);
-
         if (!ceph_file_cachep)
                 goto bad_file;
 
-        if ((error = ceph_fscache_register()))
-                goto bad_file;
+        error = ceph_fscache_register();
+        if (error)
+                goto bad_fscache;
 
         return 0;
+
+bad_fscache:
+        kmem_cache_destroy(ceph_file_cachep);
 bad_file:
         kmem_cache_destroy(ceph_dentry_cachep);
 bad_dentry:
@@ -836,7 +841,6 @@ static struct dentry *ceph_real_mount(struct ceph_fs_client *fsc)
         int err;
         unsigned long started = jiffies;  /* note the start time */
         struct dentry *root;
-        int first = 0;   /* first vfsmount for this super_block */
 
         dout("mount start %p\n", fsc);
         mutex_lock(&fsc->client->mount_mutex);
@@ -861,17 +865,17 @@ static struct dentry *ceph_real_mount(struct ceph_fs_client *fsc)
                         path = fsc->mount_options->server_path + 1;
                         dout("mount opening path %s\n", path);
                 }
+
+                err = ceph_fs_debugfs_init(fsc);
+                if (err < 0)
+                        goto out;
+
                 root = open_root_dentry(fsc, path, started);
                 if (IS_ERR(root)) {
                         err = PTR_ERR(root);
                         goto out;
                 }
                 fsc->sb->s_root = dget(root);
-                first = 1;
-
-                err = ceph_fs_debugfs_init(fsc);
-                if (err < 0)
-                        goto fail;
         } else {
                 root = dget(fsc->sb->s_root);
         }
@@ -881,11 +885,6 @@ static struct dentry *ceph_real_mount(struct ceph_fs_client *fsc)
         mutex_unlock(&fsc->client->mount_mutex);
         return root;
 
-fail:
-        if (first) {
-                dput(fsc->sb->s_root);
-                fsc->sb->s_root = NULL;
-        }
 out:
         mutex_unlock(&fsc->client->mount_mutex);
         return ERR_PTR(err);
diff --git a/fs/ceph/super.h b/fs/ceph/super.h
index 21b2e5b004eb..1c2086e0fec2 100644
--- a/fs/ceph/super.h
+++ b/fs/ceph/super.h
@@ -987,7 +987,7 @@ extern void ceph_check_caps(struct ceph_inode_info *ci, int flags,
                             struct ceph_mds_session *session);
 extern void ceph_check_delayed_caps(struct ceph_mds_client *mdsc);
 extern void ceph_flush_dirty_caps(struct ceph_mds_client *mdsc);
-
+extern int  ceph_drop_caps_for_unlink(struct inode *inode);
 extern int ceph_encode_inode_release(void **p, struct inode *inode,
                                      int mds, int drop, int unless, int force);
 extern int ceph_encode_dentry_release(void **p, struct dentry *dn,
diff --git a/fs/direct-io.c b/fs/direct-io.c
index a0ca9e48e993..1357ef563893 100644
--- a/fs/direct-io.c
+++ b/fs/direct-io.c
@@ -1274,8 +1274,7 @@ do_blockdev_direct_IO(struct kiocb *iocb, struct inode *inode,
          */
         if (dio->is_async && iov_iter_rw(iter) == WRITE) {
                 retval = 0;
-                if ((iocb->ki_filp->f_flags & O_DSYNC) ||
-                    IS_SYNC(iocb->ki_filp->f_mapping->host))
+                if (iocb->ki_flags & IOCB_DSYNC)
                         retval = dio_set_defer_completion(dio);
                 else if (!dio->inode->i_sb->s_dio_done_wq) {
                         /*
diff --git a/fs/efivarfs/file.c b/fs/efivarfs/file.c
index 5f22e74bbade..8e568428c88b 100644
--- a/fs/efivarfs/file.c
+++ b/fs/efivarfs/file.c
@@ -8,6 +8,7 @@
  */
 
 #include <linux/efi.h>
+#include <linux/delay.h>
 #include <linux/fs.h>
 #include <linux/slab.h>
 #include <linux/mount.h>
@@ -74,6 +75,11 @@ static ssize_t efivarfs_file_read(struct file *file, char __user *userbuf,
         ssize_t size = 0;
         int err;
 
+        while (!__ratelimit(&file->f_cred->user->ratelimit)) {
+                if (!msleep_interruptible(50))
+                        return -EINTR;
+        }
+
         err = efivar_entry_size(var, &datasize);
 
         /*
diff --git a/fs/gfs2/bmap.c b/fs/gfs2/bmap.c
index 86863792f36a..86d6a4435c87 100644
--- a/fs/gfs2/bmap.c
+++ b/fs/gfs2/bmap.c
@@ -716,7 +716,7 @@ int gfs2_iomap_begin(struct inode *inode, loff_t pos, loff_t length,
         __be64 *ptr;
         sector_t lblock;
         sector_t lend;
-        int ret;
+        int ret = 0;
         int eob;
         unsigned int len;
         struct buffer_head *bh;
@@ -728,12 +728,14 @@ int gfs2_iomap_begin(struct inode *inode, loff_t pos, loff_t length,
                 goto out;
         }
 
-        if ((flags & IOMAP_REPORT) && gfs2_is_stuffed(ip)) {
-                gfs2_stuffed_iomap(inode, iomap);
-                if (pos >= iomap->length)
-                        return -ENOENT;
-                ret = 0;
-                goto out;
+        if (gfs2_is_stuffed(ip)) {
+                if (flags & IOMAP_REPORT) {
+                        gfs2_stuffed_iomap(inode, iomap);
+                        if (pos >= iomap->length)
+                                ret = -ENOENT;
+                        goto out;
+                }
+                BUG_ON(!(flags & IOMAP_WRITE));
         }
 
         lblock = pos >> inode->i_blkbits;
@@ -744,7 +746,7 @@ int gfs2_iomap_begin(struct inode *inode, loff_t pos, loff_t length,
         iomap->type = IOMAP_HOLE;
         iomap->length = (u64)(lend - lblock) << inode->i_blkbits;
         iomap->flags = IOMAP_F_MERGED;
-        bmap_lock(ip, 0);
+        bmap_lock(ip, flags & IOMAP_WRITE);
 
         /*
          * Directory data blocks have a struct gfs2_meta_header header, so the
@@ -787,27 +789,28 @@ int gfs2_iomap_begin(struct inode *inode, loff_t pos, loff_t length,
                 iomap->flags |= IOMAP_F_BOUNDARY;
         iomap->length = (u64)len << inode->i_blkbits;
 
-        ret = 0;
-
 out_release:
         release_metapath(&mp);
-        bmap_unlock(ip, 0);
+        bmap_unlock(ip, flags & IOMAP_WRITE);
 out:
         trace_gfs2_iomap_end(ip, iomap, ret);
         return ret;
 
 do_alloc:
-        if (!(flags & IOMAP_WRITE)) {
-                if (pos >= i_size_read(inode)) {
+        if (flags & IOMAP_WRITE) {
+                ret = gfs2_iomap_alloc(inode, iomap, flags, &mp);
+        } else if (flags & IOMAP_REPORT) {
+                loff_t size = i_size_read(inode);
+                if (pos >= size)
                         ret = -ENOENT;
-                        goto out_release;
-                }
-                ret = 0;
-                iomap->length = hole_size(inode, lblock, &mp);
-                goto out_release;
+                else if (height <= ip->i_height)
+                        iomap->length = hole_size(inode, lblock, &mp);
+                else
+                        iomap->length = size - pos;
+        } else {
+                if (height <= ip->i_height)
+                        iomap->length = hole_size(inode, lblock, &mp);
         }
-
-        ret = gfs2_iomap_alloc(inode, iomap, flags, &mp);
         goto out_release;
 }
 
diff --git a/fs/nfs/callback_proc.c b/fs/nfs/callback_proc.c
index 2435af56b87e..a50d7813e3ea 100644
--- a/fs/nfs/callback_proc.c
+++ b/fs/nfs/callback_proc.c
@@ -572,7 +572,7 @@ out:
 }
 
 static bool
-validate_bitmap_values(unsigned long mask)
+validate_bitmap_values(unsigned int mask)
 {
         return (mask & ~RCA4_TYPE_MASK_ALL) == 0;
 }
@@ -596,17 +596,15 @@ __be32 nfs4_callback_recallany(void *argp, void *resp,
                 goto out;
 
         status = cpu_to_be32(NFS4_OK);
-        if (test_bit(RCA4_TYPE_MASK_RDATA_DLG, (const unsigned long *)
-                     &args->craa_type_mask))
+        if (args->craa_type_mask & BIT(RCA4_TYPE_MASK_RDATA_DLG))
                 flags = FMODE_READ;
-        if (test_bit(RCA4_TYPE_MASK_WDATA_DLG, (const unsigned long *)
-                     &args->craa_type_mask))
+        if (args->craa_type_mask & BIT(RCA4_TYPE_MASK_WDATA_DLG))
                 flags |= FMODE_WRITE;
-        if (test_bit(RCA4_TYPE_MASK_FILE_LAYOUT, (const unsigned long *)
-                     &args->craa_type_mask))
-                pnfs_recall_all_layouts(cps->clp);
         if (flags)
                 nfs_expire_unused_delegation_types(cps->clp, flags);
+
+        if (args->craa_type_mask & BIT(RCA4_TYPE_MASK_FILE_LAYOUT))
+                pnfs_recall_all_layouts(cps->clp);
 out:
         dprintk("%s: exit with status = %d\n", __func__, ntohl(status));
         return status;
diff --git a/fs/nfs/nfs3proc.c b/fs/nfs/nfs3proc.c
index 49f848fd1f04..7327930ad970 100644
--- a/fs/nfs/nfs3proc.c
+++ b/fs/nfs/nfs3proc.c
@@ -873,7 +873,7 @@ static void nfs3_nlm_release_call(void *data)
         }
 }
 
-const struct nlmclnt_operations nlmclnt_fl_close_lock_ops = {
+static const struct nlmclnt_operations nlmclnt_fl_close_lock_ops = {
         .nlmclnt_alloc_call = nfs3_nlm_alloc_call,
         .nlmclnt_unlock_prepare = nfs3_nlm_unlock_prepare,
         .nlmclnt_release_call = nfs3_nlm_release_call,
diff --git a/fs/nfs/nfs4client.c b/fs/nfs/nfs4client.c
index 04612c24d394..979631411a0e 100644
--- a/fs/nfs/nfs4client.c
+++ b/fs/nfs/nfs4client.c
@@ -868,8 +868,10 @@ static int nfs4_set_client(struct nfs_server *server,
         if (IS_ERR(clp))
                 return PTR_ERR(clp);
 
-        if (server->nfs_client == clp)
+        if (server->nfs_client == clp) {
+                nfs_put_client(clp);
                 return -ELOOP;
+        }
 
         /*
          * Query for the lease time on clientid setup or renewal
@@ -1244,11 +1246,11 @@ int nfs4_update_server(struct nfs_server *server, const char *hostname,
                                 clp->cl_proto, clnt->cl_timeout,
                                 clp->cl_minorversion, net);
         clear_bit(NFS_MIG_TSM_POSSIBLE, &server->mig_status);
-        nfs_put_client(clp);
         if (error != 0) {
                 nfs_server_insert_lists(server);
                 return error;
         }
+        nfs_put_client(clp);
 
         if (server->nfs_client->cl_hostname == NULL)
                 server->nfs_client->cl_hostname = kstrdup(hostname, GFP_KERNEL);
diff --git a/fs/proc/kcore.c b/fs/proc/kcore.c
index e8a93bc8285d..d1e82761de81 100644
--- a/fs/proc/kcore.c
+++ b/fs/proc/kcore.c
@@ -510,6 +510,10 @@ read_kcore(struct file *file, char __user *buffer, size_t buflen, loff_t *fpos)
                         /* we have to zero-fill user buffer even if no read */
                         if (copy_to_user(buffer, buf, tsz))
                                 return -EFAULT;
+                } else if (m->type == KCORE_USER) {
+                        /* User page is handled prior to normal kernel page: */
+                        if (copy_to_user(buffer, (char *)start, tsz))
+                                return -EFAULT;
                 } else {
                         if (kern_addr_valid(start)) {
                                 /*
diff --git a/fs/signalfd.c b/fs/signalfd.c
index 9990957264e3..76bf9cc62074 100644
--- a/fs/signalfd.c
+++ b/fs/signalfd.c
@@ -118,13 +118,22 @@ static int signalfd_copyinfo(struct signalfd_siginfo __user *uinfo,
                 err |= __put_user(kinfo->si_trapno, &uinfo->ssi_trapno);
 #endif
 #ifdef BUS_MCEERR_AO
-                /* 
+                /*
+                 * Other callers might not initialize the si_lsb field,
+                 * so check explicitly for the right codes here.
+                 */
+                if (kinfo->si_signo == SIGBUS &&
+                     kinfo->si_code == BUS_MCEERR_AO)
+                        err |= __put_user((short) kinfo->si_addr_lsb,
+                                          &uinfo->ssi_addr_lsb);
+#endif
+#ifdef BUS_MCEERR_AR
+                /*
                  * Other callers might not initialize the si_lsb field,
                  * so check explicitly for the right codes here.
                  */
                 if (kinfo->si_signo == SIGBUS &&
-                    (kinfo->si_code == BUS_MCEERR_AR ||
-                     kinfo->si_code == BUS_MCEERR_AO))
+                    kinfo->si_code == BUS_MCEERR_AR)
                         err |= __put_user((short) kinfo->si_addr_lsb,
                                           &uinfo->ssi_addr_lsb);
 #endif
diff --git a/fs/xfs/scrub/agheader.c b/fs/xfs/scrub/agheader.c
index fd975524f460..05c66e05ae20 100644
--- a/fs/xfs/scrub/agheader.c
+++ b/fs/xfs/scrub/agheader.c
@@ -767,7 +767,7 @@ int
 xfs_scrub_agfl(
         struct xfs_scrub_context        *sc)
 {
-        struct xfs_scrub_agfl_info      sai = { 0 };
+        struct xfs_scrub_agfl_info      sai;
         struct xfs_agf                  *agf;
         xfs_agnumber_t                  agno;
         unsigned int                    agflcount;
@@ -795,6 +795,7 @@ xfs_scrub_agfl(
                 xfs_scrub_block_set_corrupt(sc, sc->sa.agf_bp);
                 goto out;
         }
+        memset(&sai, 0, sizeof(sai));
         sai.sz_entries = agflcount;
         sai.entries = kmem_zalloc(sizeof(xfs_agblock_t) * agflcount, KM_NOFS);
         if (!sai.entries) {
diff --git a/fs/xfs/xfs_refcount_item.c b/fs/xfs/xfs_refcount_item.c
index 3a55d6fc271b..7a39f40645f7 100644
--- a/fs/xfs/xfs_refcount_item.c
+++ b/fs/xfs/xfs_refcount_item.c
@@ -23,6 +23,7 @@
 #include "xfs_log_format.h"
 #include "xfs_trans_resv.h"
 #include "xfs_bit.h"
+#include "xfs_shared.h"
 #include "xfs_mount.h"
 #include "xfs_defer.h"
 #include "xfs_trans.h"
@@ -456,10 +457,12 @@ xfs_cui_recover(
          * transaction.  Normally, any work that needs to be deferred
          * gets attached to the same defer_ops that scheduled the
          * refcount update.  However, we're in log recovery here, so we
-         * we create our own defer_ops and use that to finish up any
-         * work that doesn't fit.
+         * we use the passed in defer_ops and to finish up any work that
+         * doesn't fit.  We need to reserve enough blocks to handle a
+         * full btree split on either end of the refcount range.
          */
-        error = xfs_trans_alloc(mp, &M_RES(mp)->tr_itruncate, 0, 0, 0, &tp);
+        error = xfs_trans_alloc(mp, &M_RES(mp)->tr_itruncate,
+                        mp->m_refc_maxlevels * 2, 0, XFS_TRANS_RESERVE, &tp);
         if (error)
                 return error;
         cudp = xfs_trans_get_cud(tp, cuip);
diff --git a/fs/xfs/xfs_rmap_item.c b/fs/xfs/xfs_rmap_item.c
index f3b139c9aa16..49d3124863a8 100644
--- a/fs/xfs/xfs_rmap_item.c
+++ b/fs/xfs/xfs_rmap_item.c
@@ -23,6 +23,7 @@
 #include "xfs_log_format.h"
 #include "xfs_trans_resv.h"
 #include "xfs_bit.h"
+#include "xfs_shared.h"
 #include "xfs_mount.h"
 #include "xfs_defer.h"
 #include "xfs_trans.h"
@@ -470,7 +471,8 @@ xfs_rui_recover(
                 }
         }
 
-        error = xfs_trans_alloc(mp, &M_RES(mp)->tr_itruncate, 0, 0, 0, &tp);
+        error = xfs_trans_alloc(mp, &M_RES(mp)->tr_itruncate,
+                        mp->m_rmap_maxlevels, 0, XFS_TRANS_RESERVE, &tp);
         if (error)
                 return error;
         rudp = xfs_trans_get_rud(tp, ruip);
diff --git a/fs/xfs/xfs_super.c b/fs/xfs/xfs_super.c
index 7aba628dc527..93588ea3d3d2 100644
--- a/fs/xfs/xfs_super.c
+++ b/fs/xfs/xfs_super.c
@@ -250,6 +250,7 @@ xfs_parseargs(
                                 return -EINVAL;
                         break;
                 case Opt_logdev:
+                        kfree(mp->m_logname);
                         mp->m_logname = match_strdup(args);
                         if (!mp->m_logname)
                                 return -ENOMEM;
@@ -258,6 +259,7 @@ xfs_parseargs(
                         xfs_warn(mp, "%s option not allowed on this system", p);
                         return -EINVAL;
                 case Opt_rtdev:
+                        kfree(mp->m_rtname);
                         mp->m_rtname = match_strdup(args);
                         if (!mp->m_rtname)
                                 return -ENOMEM;
diff --git a/include/asm-generic/bitops/lock.h b/include/asm-generic/bitops/lock.h
index bc397573c43a..67ab280ad134 100644
--- a/include/asm-generic/bitops/lock.h
+++ b/include/asm-generic/bitops/lock.h
@@ -7,7 +7,8 @@
  * @nr: Bit to set
  * @addr: Address to count from
  *
- * This operation is atomic and provides acquire barrier semantics.
+ * This operation is atomic and provides acquire barrier semantics if
+ * the returned value is 0.
  * It can be used to implement bit locks.
  */
 #define test_and_set_bit_lock(nr, addr) test_and_set_bit(nr, addr)
diff --git a/include/asm-generic/bug.h b/include/asm-generic/bug.h
index 963b755d19b0..a7613e1b0c87 100644
--- a/include/asm-generic/bug.h
+++ b/include/asm-generic/bug.h
@@ -52,6 +52,7 @@ struct bug_entry {
 #ifndef HAVE_ARCH_BUG
 #define BUG() do { \
         printk("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __func__); \
+        barrier_before_unreachable(); \
         panic("BUG!"); \
 } while (0)
 #endif
diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h
index 1c27526c499e..cf13842a6dbd 100644
--- a/include/drm/drm_atomic.h
+++ b/include/drm/drm_atomic.h
@@ -134,6 +134,15 @@ struct drm_crtc_commit {
          * &drm_pending_vblank_event pointer to clean up private events.
          */
         struct drm_pending_vblank_event *event;
+
+        /**
+         * @abort_completion:
+         *
+         * A flag that's set after drm_atomic_helper_setup_commit takes a second
+         * reference for the completion of $drm_crtc_state.event. It's used by
+         * the free code to remove the second reference if commit fails.
+         */
+        bool abort_completion;
 };
 
 struct __drm_planes_state {
diff --git a/include/drm/drm_crtc_helper.h b/include/drm/drm_crtc_helper.h
index 76e237bd989b..6914633037a5 100644
--- a/include/drm/drm_crtc_helper.h
+++ b/include/drm/drm_crtc_helper.h
@@ -77,5 +77,6 @@ void drm_kms_helper_hotplug_event(struct drm_device *dev);
 
 void drm_kms_helper_poll_disable(struct drm_device *dev);
 void drm_kms_helper_poll_enable(struct drm_device *dev);
+bool drm_kms_helper_is_poll_worker(void);
 
 #endif
diff --git a/include/drm/drm_drv.h b/include/drm/drm_drv.h
index d32b688eb346..d23dcdd1bd95 100644
--- a/include/drm/drm_drv.h
+++ b/include/drm/drm_drv.h
@@ -56,6 +56,7 @@ struct drm_printer;
 #define DRIVER_ATOMIC                   0x10000
 #define DRIVER_KMS_LEGACY_CONTEXT       0x20000
 #define DRIVER_SYNCOBJ                  0x40000
+#define DRIVER_PREFER_XBGR_30BPP        0x80000
 
 /**
  * struct drm_driver - DRM driver structure
diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h
index e2f99ae72d5c..b2325d3e236a 100644
--- a/include/dt-bindings/clock/imx7d-clock.h
+++ b/include/dt-bindings/clock/imx7d-clock.h
@@ -452,5 +452,8 @@
 #define IMX7D_OCOTP_CLK                 439
 #define IMX7D_NAND_RAWNAND_CLK          440
 #define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 441
-#define IMX7D_CLK_END                   442
+#define IMX7D_SNVS_CLK                  442
+#define IMX7D_CAAM_CLK                  443
+#define IMX7D_KPP_ROOT_CLK              444
+#define IMX7D_CLK_END                   445
 #endif /* __DT_BINDINGS_CLOCK_IMX7D_H */
diff --git a/include/dt-bindings/clock/tegra194-clock.h b/include/dt-bindings/clock/tegra194-clock.h
new file mode 100644
index 000000000000..a2ff66342d69
--- /dev/null
+++ b/include/dt-bindings/clock/tegra194-clock.h
@@ -0,0 +1,321 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */
+
+#ifndef __ABI_MACH_T194_CLOCK_H
+#define __ABI_MACH_T194_CLOCK_H
+
+#define TEGRA194_CLK_ACTMON                     1
+#define TEGRA194_CLK_ADSP                       2
+#define TEGRA194_CLK_ADSPNEON                   3
+#define TEGRA194_CLK_AHUB                       4
+#define TEGRA194_CLK_APB2APE                    5
+#define TEGRA194_CLK_APE                        6
+#define TEGRA194_CLK_AUD_MCLK                   7
+#define TEGRA194_CLK_AXI_CBB                    8
+#define TEGRA194_CLK_CAN1                       9
+#define TEGRA194_CLK_CAN1_HOST                  10
+#define TEGRA194_CLK_CAN2                       11
+#define TEGRA194_CLK_CAN2_HOST                  12
+#define TEGRA194_CLK_CEC                        13
+#define TEGRA194_CLK_CLK_M                      14
+#define TEGRA194_CLK_DMIC1                      15
+#define TEGRA194_CLK_DMIC2                      16
+#define TEGRA194_CLK_DMIC3                      17
+#define TEGRA194_CLK_DMIC4                      18
+#define TEGRA194_CLK_DPAUX                      19
+#define TEGRA194_CLK_DPAUX1                     20
+#define TEGRA194_CLK_ACLK                       21
+#define TEGRA194_CLK_MSS_ENCRYPT                22
+#define TEGRA194_CLK_EQOS_RX_INPUT              23
+#define TEGRA194_CLK_IQC2                       24
+#define TEGRA194_CLK_AON_APB                    25
+#define TEGRA194_CLK_AON_NIC                    26
+#define TEGRA194_CLK_AON_CPU_NIC                27
+#define TEGRA194_CLK_PLLA1                      28
+#define TEGRA194_CLK_DSPK1                      29
+#define TEGRA194_CLK_DSPK2                      30
+#define TEGRA194_CLK_EMC                        31
+#define TEGRA194_CLK_EQOS_AXI                   32
+#define TEGRA194_CLK_EQOS_PTP_REF               33
+#define TEGRA194_CLK_EQOS_RX                    34
+#define TEGRA194_CLK_EQOS_TX                    35
+#define TEGRA194_CLK_EXTPERIPH1                 36
+#define TEGRA194_CLK_EXTPERIPH2                 37
+#define TEGRA194_CLK_EXTPERIPH3                 38
+#define TEGRA194_CLK_EXTPERIPH4                 39
+#define TEGRA194_CLK_FUSE                       40
+#define TEGRA194_CLK_GPCCLK                     41
+#define TEGRA194_CLK_GPU_PWR                    42
+#define TEGRA194_CLK_HDA                        43
+#define TEGRA194_CLK_HDA2CODEC_2X               44
+#define TEGRA194_CLK_HDA2HDMICODEC              45
+#define TEGRA194_CLK_HOST1X                     46
+#define TEGRA194_CLK_HSIC_TRK                   47
+#define TEGRA194_CLK_I2C1                       48
+#define TEGRA194_CLK_I2C2                       49
+#define TEGRA194_CLK_I2C3                       50
+#define TEGRA194_CLK_I2C4                       51
+#define TEGRA194_CLK_I2C6                       52
+#define TEGRA194_CLK_I2C7                       53
+#define TEGRA194_CLK_I2C8                       54
+#define TEGRA194_CLK_I2C9                       55
+#define TEGRA194_CLK_I2S1                       56
+#define TEGRA194_CLK_I2S1_SYNC_INPUT            57
+#define TEGRA194_CLK_I2S2                       58
+#define TEGRA194_CLK_I2S2_SYNC_INPUT            59
+#define TEGRA194_CLK_I2S3                       60
+#define TEGRA194_CLK_I2S3_SYNC_INPUT            61
+#define TEGRA194_CLK_I2S4                       62
+#define TEGRA194_CLK_I2S4_SYNC_INPUT            63
+#define TEGRA194_CLK_I2S5                       64
+#define TEGRA194_CLK_I2S5_SYNC_INPUT            65
+#define TEGRA194_CLK_I2S6                       66
+#define TEGRA194_CLK_I2S6_SYNC_INPUT            67
+#define TEGRA194_CLK_IQC1                       68
+#define TEGRA194_CLK_ISP                        69
+#define TEGRA194_CLK_KFUSE                      70
+#define TEGRA194_CLK_MAUD                       71
+#define TEGRA194_CLK_MIPI_CAL                   72
+#define TEGRA194_CLK_MPHY_CORE_PLL_FIXED        73
+#define TEGRA194_CLK_MPHY_L0_RX_ANA             74
+#define TEGRA194_CLK_MPHY_L0_RX_LS_BIT          75
+#define TEGRA194_CLK_MPHY_L0_RX_SYMB            76
+#define TEGRA194_CLK_MPHY_L0_TX_LS_3XBIT        77
+#define TEGRA194_CLK_MPHY_L0_TX_SYMB            78
+#define TEGRA194_CLK_MPHY_L1_RX_ANA             79
+#define TEGRA194_CLK_MPHY_TX_1MHZ_REF           80
+#define TEGRA194_CLK_NVCSI                      81
+#define TEGRA194_CLK_NVCSILP                    82
+#define TEGRA194_CLK_NVDEC                      83
+#define TEGRA194_CLK_NVDISPLAYHUB               84
+#define TEGRA194_CLK_NVDISPLAY_DISP             85
+#define TEGRA194_CLK_NVDISPLAY_P0               86
+#define TEGRA194_CLK_NVDISPLAY_P1               87
+#define TEGRA194_CLK_NVDISPLAY_P2               88
+#define TEGRA194_CLK_NVENC                      89
+#define TEGRA194_CLK_NVJPG                      90
+#define TEGRA194_CLK_OSC                        91
+#define TEGRA194_CLK_AON_TOUCH                  92
+#define TEGRA194_CLK_PLLA                       93
+#define TEGRA194_CLK_PLLAON                     94
+#define TEGRA194_CLK_PLLD                       95
+#define TEGRA194_CLK_PLLD2                      96
+#define TEGRA194_CLK_PLLD3                      97
+#define TEGRA194_CLK_PLLDP                      98
+#define TEGRA194_CLK_PLLD4                      99
+#define TEGRA194_CLK_PLLE                       100
+#define TEGRA194_CLK_PLLP                       101
+#define TEGRA194_CLK_PLLP_OUT0                  102
+#define TEGRA194_CLK_UTMIPLL                    103
+#define TEGRA194_CLK_PLLA_OUT0                  104
+#define TEGRA194_CLK_PWM1                       105
+#define TEGRA194_CLK_PWM2                       106
+#define TEGRA194_CLK_PWM3                       107
+#define TEGRA194_CLK_PWM4                       108
+#define TEGRA194_CLK_PWM5                       109
+#define TEGRA194_CLK_PWM6                       110
+#define TEGRA194_CLK_PWM7                       111
+#define TEGRA194_CLK_PWM8                       112
+#define TEGRA194_CLK_RCE_CPU_NIC                113
+#define TEGRA194_CLK_RCE_NIC                    114
+#define TEGRA194_CLK_SATA                       115
+#define TEGRA194_CLK_SATA_OOB                   116
+#define TEGRA194_CLK_AON_I2C_SLOW               117
+#define TEGRA194_CLK_SCE_CPU_NIC                118
+#define TEGRA194_CLK_SCE_NIC                    119
+#define TEGRA194_CLK_SDMMC1                     120
+#define TEGRA194_CLK_UPHY_PLL3                  121
+#define TEGRA194_CLK_SDMMC3                     122
+#define TEGRA194_CLK_SDMMC4                     123
+#define TEGRA194_CLK_SE                         124
+#define TEGRA194_CLK_SOR0_OUT                   125
+#define TEGRA194_CLK_SOR0_REF                   126
+#define TEGRA194_CLK_SOR0_PAD_CLKOUT            127
+#define TEGRA194_CLK_SOR1_OUT                   128
+#define TEGRA194_CLK_SOR1_REF                   129
+#define TEGRA194_CLK_SOR1_PAD_CLKOUT            130
+#define TEGRA194_CLK_SOR_SAFE                   131
+#define TEGRA194_CLK_IQC1_IN                    132
+#define TEGRA194_CLK_IQC2_IN                    133
+#define TEGRA194_CLK_DMIC5                      134
+#define TEGRA194_CLK_SPI1                       135
+#define TEGRA194_CLK_SPI2                       136
+#define TEGRA194_CLK_SPI3                       137
+#define TEGRA194_CLK_I2C_SLOW                   138
+#define TEGRA194_CLK_SYNC_DMIC1                 139
+#define TEGRA194_CLK_SYNC_DMIC2                 140
+#define TEGRA194_CLK_SYNC_DMIC3                 141
+#define TEGRA194_CLK_SYNC_DMIC4                 142
+#define TEGRA194_CLK_SYNC_DSPK1                 143
+#define TEGRA194_CLK_SYNC_DSPK2                 144
+#define TEGRA194_CLK_SYNC_I2S1                  145
+#define TEGRA194_CLK_SYNC_I2S2                  146
+#define TEGRA194_CLK_SYNC_I2S3                  147
+#define TEGRA194_CLK_SYNC_I2S4                  148
+#define TEGRA194_CLK_SYNC_I2S5                  149
+#define TEGRA194_CLK_SYNC_I2S6                  150
+#define TEGRA194_CLK_MPHY_FORCE_LS_MODE         151
+#define TEGRA194_CLK_TACH                       152
+#define TEGRA194_CLK_TSEC                       153
+#define TEGRA194_CLK_TSECB                      154
+#define TEGRA194_CLK_UARTA                      155
+#define TEGRA194_CLK_UARTB                      156
+#define TEGRA194_CLK_UARTC                      157
+#define TEGRA194_CLK_UARTD                      158
+#define TEGRA194_CLK_UARTE                      159
+#define TEGRA194_CLK_UARTF                      160
+#define TEGRA194_CLK_UARTG                      161
+#define TEGRA194_CLK_UART_FST_MIPI_CAL          162
+#define TEGRA194_CLK_UFSDEV_REF                 163
+#define TEGRA194_CLK_UFSHC                      164
+#define TEGRA194_CLK_USB2_TRK                   165
+#define TEGRA194_CLK_VI                         166
+#define TEGRA194_CLK_VIC                        167
+#define TEGRA194_CLK_PVA0_AXI                   168
+#define TEGRA194_CLK_PVA0_VPS0                  169
+#define TEGRA194_CLK_PVA0_VPS1                  170
+#define TEGRA194_CLK_PVA1_AXI                   171
+#define TEGRA194_CLK_PVA1_VPS0                  172
+#define TEGRA194_CLK_PVA1_VPS1                  173
+#define TEGRA194_CLK_DLA0_FALCON                174
+#define TEGRA194_CLK_DLA0_CORE                  175
+#define TEGRA194_CLK_DLA1_FALCON                176
+#define TEGRA194_CLK_DLA1_CORE                  177
+#define TEGRA194_CLK_SOR2_OUT                   178
+#define TEGRA194_CLK_SOR2_REF                   179
+#define TEGRA194_CLK_SOR2_PAD_CLKOUT            180
+#define TEGRA194_CLK_SOR3_OUT                   181
+#define TEGRA194_CLK_SOR3_REF                   182
+#define TEGRA194_CLK_SOR3_PAD_CLKOUT            183
+#define TEGRA194_CLK_NVDISPLAY_P3               184
+#define TEGRA194_CLK_DPAUX2                     185
+#define TEGRA194_CLK_DPAUX3                     186
+#define TEGRA194_CLK_NVDEC1                     187
+#define TEGRA194_CLK_NVENC1                     188
+#define TEGRA194_CLK_SE_FREE                    189
+#define TEGRA194_CLK_UARTH                      190
+#define TEGRA194_CLK_FUSE_SERIAL                191
+#define TEGRA194_CLK_QSPI0                      192
+#define TEGRA194_CLK_QSPI1                      193
+#define TEGRA194_CLK_QSPI0_PM                   194
+#define TEGRA194_CLK_QSPI1_PM                   195
+#define TEGRA194_CLK_VI_CONST                   196
+#define TEGRA194_CLK_NAFLL_BPMP                 197
+#define TEGRA194_CLK_NAFLL_SCE                  198
+#define TEGRA194_CLK_NAFLL_NVDEC                199
+#define TEGRA194_CLK_NAFLL_NVJPG                200
+#define TEGRA194_CLK_NAFLL_TSEC                 201
+#define TEGRA194_CLK_NAFLL_TSECB                202
+#define TEGRA194_CLK_NAFLL_VI                   203
+#define TEGRA194_CLK_NAFLL_SE                   204
+#define TEGRA194_CLK_NAFLL_NVENC                205
+#define TEGRA194_CLK_NAFLL_ISP                  206
+#define TEGRA194_CLK_NAFLL_VIC                  207
+#define TEGRA194_CLK_NAFLL_NVDISPLAYHUB         208
+#define TEGRA194_CLK_NAFLL_AXICBB               209
+#define TEGRA194_CLK_NAFLL_DLA                  210
+#define TEGRA194_CLK_NAFLL_PVA_CORE             211
+#define TEGRA194_CLK_NAFLL_PVA_VPS              212
+#define TEGRA194_CLK_NAFLL_CVNAS                213
+#define TEGRA194_CLK_NAFLL_RCE                  214
+#define TEGRA194_CLK_NAFLL_NVENC1               215
+#define TEGRA194_CLK_NAFLL_DLA_FALCON           216
+#define TEGRA194_CLK_NAFLL_NVDEC1               217
+#define TEGRA194_CLK_NAFLL_GPU                  218
+#define TEGRA194_CLK_SDMMC_LEGACY_TM            219
+#define TEGRA194_CLK_PEX0_CORE_0                220
+#define TEGRA194_CLK_PEX0_CORE_1                221
+#define TEGRA194_CLK_PEX0_CORE_2                222
+#define TEGRA194_CLK_PEX0_CORE_3                223
+#define TEGRA194_CLK_PEX0_CORE_4                224
+#define TEGRA194_CLK_PEX1_CORE_5                225
+#define TEGRA194_CLK_PEX_REF1                   226
+#define TEGRA194_CLK_PEX_REF2                   227
+#define TEGRA194_CLK_CSI_A                      229
+#define TEGRA194_CLK_CSI_B                      230
+#define TEGRA194_CLK_CSI_C                      231
+#define TEGRA194_CLK_CSI_D                      232
+#define TEGRA194_CLK_CSI_E                      233
+#define TEGRA194_CLK_CSI_F                      234
+#define TEGRA194_CLK_CSI_G                      235
+#define TEGRA194_CLK_CSI_H                      236
+#define TEGRA194_CLK_PLLC4                      237
+#define TEGRA194_CLK_PLLC4_OUT                  238
+#define TEGRA194_CLK_PLLC4_OUT1                 239
+#define TEGRA194_CLK_PLLC4_OUT2                 240
+#define TEGRA194_CLK_PLLC4_MUXED                241
+#define TEGRA194_CLK_PLLC4_VCO_DIV2             242
+#define TEGRA194_CLK_CSI_A_PAD                  244
+#define TEGRA194_CLK_CSI_B_PAD                  245
+#define TEGRA194_CLK_CSI_C_PAD                  246
+#define TEGRA194_CLK_CSI_D_PAD                  247
+#define TEGRA194_CLK_CSI_E_PAD                  248
+#define TEGRA194_CLK_CSI_F_PAD                  249
+#define TEGRA194_CLK_CSI_G_PAD                  250
+#define TEGRA194_CLK_CSI_H_PAD                  251
+#define TEGRA194_CLK_PEX_SATA_USB_RX_BYP        254
+#define TEGRA194_CLK_PEX_USB_PAD_PLL0_MGMT      255
+#define TEGRA194_CLK_PEX_USB_PAD_PLL1_MGMT      256
+#define TEGRA194_CLK_PEX_USB_PAD_PLL2_MGMT      257
+#define TEGRA194_CLK_PEX_USB_PAD_PLL3_MGMT      258
+#define TEGRA194_CLK_XUSB_CORE_DEV              265
+#define TEGRA194_CLK_XUSB_CORE_MUX              266
+#define TEGRA194_CLK_XUSB_CORE_HOST             267
+#define TEGRA194_CLK_XUSB_CORE_SS               268
+#define TEGRA194_CLK_XUSB_FALCON                269
+#define TEGRA194_CLK_XUSB_FALCON_HOST           270
+#define TEGRA194_CLK_XUSB_FALCON_SS             271
+#define TEGRA194_CLK_XUSB_FS                    272
+#define TEGRA194_CLK_XUSB_FS_HOST               273
+#define TEGRA194_CLK_XUSB_FS_DEV                274
+#define TEGRA194_CLK_XUSB_SS                    275
+#define TEGRA194_CLK_XUSB_SS_DEV                276
+#define TEGRA194_CLK_XUSB_SS_SUPERSPEED         277
+#define TEGRA194_CLK_PLLDISPHUB                 278
+#define TEGRA194_CLK_PLLDISPHUB_DIV             279
+#define TEGRA194_CLK_NAFLL_CLUSTER0             280
+#define TEGRA194_CLK_NAFLL_CLUSTER1             281
+#define TEGRA194_CLK_NAFLL_CLUSTER2             282
+#define TEGRA194_CLK_NAFLL_CLUSTER3             283
+#define TEGRA194_CLK_CAN1_CORE                  284
+#define TEGRA194_CLK_CAN2_CORE                  285
+#define TEGRA194_CLK_PLLA1_OUT1                 286
+#define TEGRA194_CLK_PLLREFE_VCOOUT             288
+#define TEGRA194_CLK_CLK_32K                    289
+#define TEGRA194_CLK_SPDIFIN_SYNC_INPUT         290
+#define TEGRA194_CLK_UTMIPLL_CLKOUT48           291
+#define TEGRA194_CLK_UTMIPLL_CLKOUT480          292
+#define TEGRA194_CLK_CVNAS                      293
+#define TEGRA194_CLK_PLLNVCSI                   294
+#define TEGRA194_CLK_PVA0_CPU_AXI               295
+#define TEGRA194_CLK_PVA1_CPU_AXI               296
+#define TEGRA194_CLK_PVA0_VPS                   297
+#define TEGRA194_CLK_PVA1_VPS                   298
+#define TEGRA194_CLK_DLA0_FALCON_MUX            299
+#define TEGRA194_CLK_DLA1_FALCON_MUX            300
+#define TEGRA194_CLK_DLA0_CORE_MUX              301
+#define TEGRA194_CLK_DLA1_CORE_MUX              302
+#define TEGRA194_CLK_UTMIPLL_HPS                304
+#define TEGRA194_CLK_I2C5                       305
+#define TEGRA194_CLK_I2C10                      306
+#define TEGRA194_CLK_BPMP_CPU_NIC               307
+#define TEGRA194_CLK_BPMP_APB                   308
+#define TEGRA194_CLK_TSC                        309
+#define TEGRA194_CLK_EMCSA                      310
+#define TEGRA194_CLK_EMCSB                      311
+#define TEGRA194_CLK_EMCSC                      312
+#define TEGRA194_CLK_EMCSD                      313
+#define TEGRA194_CLK_PLLC                       314
+#define TEGRA194_CLK_PLLC2                      315
+#define TEGRA194_CLK_PLLC3                      316
+#define TEGRA194_CLK_TSC_REF                    317
+#define TEGRA194_CLK_FUSE_BURN                  318
+#define TEGRA194_CLK_PEX0_CORE_0M               319
+#define TEGRA194_CLK_PEX0_CORE_1M               320
+#define TEGRA194_CLK_PEX0_CORE_2M               321
+#define TEGRA194_CLK_PEX0_CORE_3M               322
+#define TEGRA194_CLK_PEX0_CORE_4M               323
+#define TEGRA194_CLK_PEX1_CORE_5M               324
+#define TEGRA194_CLK_PLLE_HPS                   326
+
+#endif
diff --git a/include/dt-bindings/gpio/tegra194-gpio.h b/include/dt-bindings/gpio/tegra194-gpio.h
new file mode 100644
index 000000000000..ede860225f6b
--- /dev/null
+++ b/include/dt-bindings/gpio/tegra194-gpio.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */
+
+/*
+ * This header provides constants for binding nvidia,tegra194-gpio*.
+ *
+ * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
+ * provide names for this.
+ *
+ * The second cell contains standard flag values specified in gpio.h.
+ */
+
+#ifndef _DT_BINDINGS_GPIO_TEGRA194_GPIO_H
+#define _DT_BINDINGS_GPIO_TEGRA194_GPIO_H
+
+#include <dt-bindings/gpio/gpio.h>
+
+/* GPIOs implemented by main GPIO controller */
+#define TEGRA194_MAIN_GPIO_PORT_A 0
+#define TEGRA194_MAIN_GPIO_PORT_B 1
+#define TEGRA194_MAIN_GPIO_PORT_C 2
+#define TEGRA194_MAIN_GPIO_PORT_D 3
+#define TEGRA194_MAIN_GPIO_PORT_E 4
+#define TEGRA194_MAIN_GPIO_PORT_F 5
+#define TEGRA194_MAIN_GPIO_PORT_G 6
+#define TEGRA194_MAIN_GPIO_PORT_H 7
+#define TEGRA194_MAIN_GPIO_PORT_I 8
+#define TEGRA194_MAIN_GPIO_PORT_J 9
+#define TEGRA194_MAIN_GPIO_PORT_K 10
+#define TEGRA194_MAIN_GPIO_PORT_L 11
+#define TEGRA194_MAIN_GPIO_PORT_M 12
+#define TEGRA194_MAIN_GPIO_PORT_N 13
+#define TEGRA194_MAIN_GPIO_PORT_O 14
+#define TEGRA194_MAIN_GPIO_PORT_P 15
+#define TEGRA194_MAIN_GPIO_PORT_Q 16
+#define TEGRA194_MAIN_GPIO_PORT_R 17
+#define TEGRA194_MAIN_GPIO_PORT_S 18
+#define TEGRA194_MAIN_GPIO_PORT_T 19
+#define TEGRA194_MAIN_GPIO_PORT_U 20
+#define TEGRA194_MAIN_GPIO_PORT_V 21
+#define TEGRA194_MAIN_GPIO_PORT_W 22
+#define TEGRA194_MAIN_GPIO_PORT_X 23
+#define TEGRA194_MAIN_GPIO_PORT_Y 24
+#define TEGRA194_MAIN_GPIO_PORT_Z 25
+#define TEGRA194_MAIN_GPIO_PORT_FF 26
+#define TEGRA194_MAIN_GPIO_PORT_GG 27
+
+#define TEGRA194_MAIN_GPIO(port, offset) \
+        ((TEGRA194_MAIN_GPIO_PORT_##port * 8) + offset)
+
+/* GPIOs implemented by AON GPIO controller */
+#define TEGRA194_AON_GPIO_PORT_AA 0
+#define TEGRA194_AON_GPIO_PORT_BB 1
+#define TEGRA194_AON_GPIO_PORT_CC 2
+#define TEGRA194_AON_GPIO_PORT_DD 3
+#define TEGRA194_AON_GPIO_PORT_EE 4
+
+#define TEGRA194_AON_GPIO(port, offset) \
+        ((TEGRA194_AON_GPIO_PORT_##port * 8) + offset)
+
+#endif
diff --git a/include/dt-bindings/mfd/stm32f7-rcc.h b/include/dt-bindings/mfd/stm32f7-rcc.h
index 8b7b7197ffd7..a90f3613c584 100644
--- a/include/dt-bindings/mfd/stm32f7-rcc.h
+++ b/include/dt-bindings/mfd/stm32f7-rcc.h
@@ -91,6 +91,7 @@
 #define STM32F7_RCC_APB2_TIM8           1
 #define STM32F7_RCC_APB2_USART1         4
 #define STM32F7_RCC_APB2_USART6         5
+#define STM32F7_RCC_APB2_SDMMC2         7
 #define STM32F7_RCC_APB2_ADC1           8
 #define STM32F7_RCC_APB2_ADC2           9
 #define STM32F7_RCC_APB2_ADC3           10
diff --git a/include/dt-bindings/power/tegra194-powergate.h b/include/dt-bindings/power/tegra194-powergate.h
new file mode 100644
index 000000000000..82253742a493
--- /dev/null
+++ b/include/dt-bindings/power/tegra194-powergate.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */
+
+#ifndef __ABI_MACH_T194_POWERGATE_T194_H_
+#define __ABI_MACH_T194_POWERGATE_T194_H_
+
+#define TEGRA194_POWER_DOMAIN_AUD       1
+#define TEGRA194_POWER_DOMAIN_DISP      2
+#define TEGRA194_POWER_DOMAIN_DISPB     3
+#define TEGRA194_POWER_DOMAIN_DISPC     4
+#define TEGRA194_POWER_DOMAIN_ISPA      5
+#define TEGRA194_POWER_DOMAIN_NVDECA    6
+#define TEGRA194_POWER_DOMAIN_NVJPG     7
+#define TEGRA194_POWER_DOMAIN_NVENCA    8
+#define TEGRA194_POWER_DOMAIN_NVENCB    9
+#define TEGRA194_POWER_DOMAIN_NVDECB    10
+#define TEGRA194_POWER_DOMAIN_SAX       11
+#define TEGRA194_POWER_DOMAIN_VE        12
+#define TEGRA194_POWER_DOMAIN_VIC       13
+#define TEGRA194_POWER_DOMAIN_XUSBA     14
+#define TEGRA194_POWER_DOMAIN_XUSBB     15
+#define TEGRA194_POWER_DOMAIN_XUSBC     16
+#define TEGRA194_POWER_DOMAIN_PCIEX8A   17
+#define TEGRA194_POWER_DOMAIN_PCIEX4A   18
+#define TEGRA194_POWER_DOMAIN_PCIEX1A   19
+#define TEGRA194_POWER_DOMAIN_PCIEX8B   21
+#define TEGRA194_POWER_DOMAIN_PVAA      22
+#define TEGRA194_POWER_DOMAIN_PVAB      23
+#define TEGRA194_POWER_DOMAIN_DLAA      24
+#define TEGRA194_POWER_DOMAIN_DLAB      25
+#define TEGRA194_POWER_DOMAIN_CV        26
+#define TEGRA194_POWER_DOMAIN_GPU       27
+#define TEGRA194_POWER_DOMAIN_MAX       27
+
+#endif
diff --git a/include/dt-bindings/reset/tegra194-reset.h b/include/dt-bindings/reset/tegra194-reset.h
new file mode 100644
index 000000000000..473afaa25bfb
--- /dev/null
+++ b/include/dt-bindings/reset/tegra194-reset.h
@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */
+
+#ifndef __ABI_MACH_T194_RESET_H
+#define __ABI_MACH_T194_RESET_H
+
+#define TEGRA194_RESET_ACTMON                   1
+#define TEGRA194_RESET_ADSP_ALL                 2
+#define TEGRA194_RESET_AFI                      3
+#define TEGRA194_RESET_CAN1                     4
+#define TEGRA194_RESET_CAN2                     5
+#define TEGRA194_RESET_DLA0                     6
+#define TEGRA194_RESET_DLA1                     7
+#define TEGRA194_RESET_DPAUX                    8
+#define TEGRA194_RESET_DPAUX1                   9
+#define TEGRA194_RESET_DPAUX2                   10
+#define TEGRA194_RESET_DPAUX3                   11
+#define TEGRA194_RESET_EQOS                     17
+#define TEGRA194_RESET_GPCDMA                   18
+#define TEGRA194_RESET_GPU                      19
+#define TEGRA194_RESET_HDA                      20
+#define TEGRA194_RESET_HDA2CODEC_2X             21
+#define TEGRA194_RESET_HDA2HDMICODEC            22
+#define TEGRA194_RESET_HOST1X                   23
+#define TEGRA194_RESET_I2C1                     24
+#define TEGRA194_RESET_I2C10                    25
+#define TEGRA194_RESET_RSVD_26                  26
+#define TEGRA194_RESET_RSVD_27                  27
+#define TEGRA194_RESET_RSVD_28                  28
+#define TEGRA194_RESET_I2C2                     29
+#define TEGRA194_RESET_I2C3                     30
+#define TEGRA194_RESET_I2C4                     31
+#define TEGRA194_RESET_I2C6                     32
+#define TEGRA194_RESET_I2C7                     33
+#define TEGRA194_RESET_I2C8                     34
+#define TEGRA194_RESET_I2C9                     35
+#define TEGRA194_RESET_ISP                      36
+#define TEGRA194_RESET_MIPI_CAL                 37
+#define TEGRA194_RESET_MPHY_CLK_CTL             38
+#define TEGRA194_RESET_MPHY_L0_RX               39
+#define TEGRA194_RESET_MPHY_L0_TX               40
+#define TEGRA194_RESET_MPHY_L1_RX               41
+#define TEGRA194_RESET_MPHY_L1_TX               42
+#define TEGRA194_RESET_NVCSI                    43
+#define TEGRA194_RESET_NVDEC                    44
+#define TEGRA194_RESET_NVDISPLAY0_HEAD0         45
+#define TEGRA194_RESET_NVDISPLAY0_HEAD1         46
+#define TEGRA194_RESET_NVDISPLAY0_HEAD2         47
+#define TEGRA194_RESET_NVDISPLAY0_HEAD3         48
+#define TEGRA194_RESET_NVDISPLAY0_MISC          49
+#define TEGRA194_RESET_NVDISPLAY0_WGRP0         50
+#define TEGRA194_RESET_NVDISPLAY0_WGRP1         51
+#define TEGRA194_RESET_NVDISPLAY0_WGRP2         52
+#define TEGRA194_RESET_NVDISPLAY0_WGRP3         53
+#define TEGRA194_RESET_NVDISPLAY0_WGRP4         54
+#define TEGRA194_RESET_NVDISPLAY0_WGRP5         55
+#define TEGRA194_RESET_RSVD_56                  56
+#define TEGRA194_RESET_RSVD_57                  57
+#define TEGRA194_RESET_RSVD_58                  58
+#define TEGRA194_RESET_NVENC                    59
+#define TEGRA194_RESET_NVENC1                   60
+#define TEGRA194_RESET_NVJPG                    61
+#define TEGRA194_RESET_PCIE                     62
+#define TEGRA194_RESET_PCIEXCLK                 63
+#define TEGRA194_RESET_RSVD_64                  64
+#define TEGRA194_RESET_RSVD_65                  65
+#define TEGRA194_RESET_PVA0_ALL                 66
+#define TEGRA194_RESET_PVA1_ALL                 67
+#define TEGRA194_RESET_PWM1                     68
+#define TEGRA194_RESET_PWM2                     69
+#define TEGRA194_RESET_PWM3                     70
+#define TEGRA194_RESET_PWM4                     71
+#define TEGRA194_RESET_PWM5                     72
+#define TEGRA194_RESET_PWM6                     73
+#define TEGRA194_RESET_PWM7                     74
+#define TEGRA194_RESET_PWM8                     75
+#define TEGRA194_RESET_QSPI0                    76
+#define TEGRA194_RESET_QSPI1                    77
+#define TEGRA194_RESET_SATA                     78
+#define TEGRA194_RESET_SATACOLD                 79
+#define TEGRA194_RESET_SCE_ALL                  80
+#define TEGRA194_RESET_RCE_ALL                  81
+#define TEGRA194_RESET_SDMMC1                   82
+#define TEGRA194_RESET_RSVD_83                  83
+#define TEGRA194_RESET_SDMMC3                   84
+#define TEGRA194_RESET_SDMMC4                   85
+#define TEGRA194_RESET_SE                       86
+#define TEGRA194_RESET_SOR0                     87
+#define TEGRA194_RESET_SOR1                     88
+#define TEGRA194_RESET_SOR2                     89
+#define TEGRA194_RESET_SOR3                     90
+#define TEGRA194_RESET_SPI1                     91
+#define TEGRA194_RESET_SPI2                     92
+#define TEGRA194_RESET_SPI3                     93
+#define TEGRA194_RESET_SPI4                     94
+#define TEGRA194_RESET_TACH                     95
+#define TEGRA194_RESET_RSVD_96                  96
+#define TEGRA194_RESET_TSCTNVI                  97
+#define TEGRA194_RESET_TSEC                     98
+#define TEGRA194_RESET_TSECB                    99
+#define TEGRA194_RESET_UARTA                    100
+#define TEGRA194_RESET_UARTB                    101
+#define TEGRA194_RESET_UARTC                    102
+#define TEGRA194_RESET_UARTD                    103
+#define TEGRA194_RESET_UARTE                    104
+#define TEGRA194_RESET_UARTF                    105
+#define TEGRA194_RESET_UARTG                    106
+#define TEGRA194_RESET_UARTH                    107
+#define TEGRA194_RESET_UFSHC                    108
+#define TEGRA194_RESET_UFSHC_AXI_M              109
+#define TEGRA194_RESET_UFSHC_LP_SEQ             110
+#define TEGRA194_RESET_RSVD_111                 111
+#define TEGRA194_RESET_VI                       112
+#define TEGRA194_RESET_VIC                      113
+#define TEGRA194_RESET_XUSB_PADCTL              114
+#define TEGRA194_RESET_NVDEC1                   115
+#define TEGRA194_RESET_PEX0_CORE_0              116
+#define TEGRA194_RESET_PEX0_CORE_1              117
+#define TEGRA194_RESET_PEX0_CORE_2              118
+#define TEGRA194_RESET_PEX0_CORE_3              119
+#define TEGRA194_RESET_PEX0_CORE_4              120
+#define TEGRA194_RESET_PEX0_CORE_0_APB          121
+#define TEGRA194_RESET_PEX0_CORE_1_APB          122
+#define TEGRA194_RESET_PEX0_CORE_2_APB          123
+#define TEGRA194_RESET_PEX0_CORE_3_APB          124
+#define TEGRA194_RESET_PEX0_CORE_4_APB          125
+#define TEGRA194_RESET_PEX0_COMMON_APB          126
+#define TEGRA194_RESET_PEX1_CORE_5              129
+#define TEGRA194_RESET_PEX1_CORE_5_APB          130
+#define TEGRA194_RESET_CVNAS                    131
+#define TEGRA194_RESET_CVNAS_FCM                132
+#define TEGRA194_RESET_DMIC5                    144
+#define TEGRA194_RESET_APE                      145
+#define TEGRA194_RESET_PEX_USB_UPHY             146
+#define TEGRA194_RESET_PEX_USB_UPHY_L0          147
+#define TEGRA194_RESET_PEX_USB_UPHY_L1          148
+#define TEGRA194_RESET_PEX_USB_UPHY_L2          149
+#define TEGRA194_RESET_PEX_USB_UPHY_L3          150
+#define TEGRA194_RESET_PEX_USB_UPHY_L4          151
+#define TEGRA194_RESET_PEX_USB_UPHY_L5          152
+#define TEGRA194_RESET_PEX_USB_UPHY_L6          153
+#define TEGRA194_RESET_PEX_USB_UPHY_L7          154
+#define TEGRA194_RESET_PEX_USB_UPHY_L8          155
+#define TEGRA194_RESET_PEX_USB_UPHY_L9          156
+#define TEGRA194_RESET_PEX_USB_UPHY_L10         157
+#define TEGRA194_RESET_PEX_USB_UPHY_L11         158
+#define TEGRA194_RESET_PEX_USB_UPHY_PLL0        159
+#define TEGRA194_RESET_PEX_USB_UPHY_PLL1        160
+#define TEGRA194_RESET_PEX_USB_UPHY_PLL2        161
+#define TEGRA194_RESET_PEX_USB_UPHY_PLL3        162
+
+#endif
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index 64e10746f282..968173ec2726 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -587,7 +587,7 @@ extern int acpi_nvs_for_each_region(int (*func)(__u64, __u64, void *),
 const struct acpi_device_id *acpi_match_device(const struct acpi_device_id *ids,
                                                const struct device *dev);
 
-void *acpi_get_match_data(const struct device *dev);
+const void *acpi_device_get_match_data(const struct device *dev);
 extern bool acpi_driver_match_device(struct device *dev,
                                      const struct device_driver *drv);
 int acpi_device_uevent_modalias(struct device *, struct kobj_uevent_env *);
@@ -766,7 +766,7 @@ static inline const struct acpi_device_id *acpi_match_device(
         return NULL;
 }
 
-static inline void *acpi_get_match_data(const struct device *dev)
+static inline const void *acpi_device_get_match_data(const struct device *dev)
 {
         return NULL;
 }
diff --git a/include/linux/bio.h b/include/linux/bio.h
index d0eb659fa733..ce547a25e8ae 100644
--- a/include/linux/bio.h
+++ b/include/linux/bio.h
@@ -511,6 +511,7 @@ void zero_fill_bio(struct bio *bio);
 extern struct bio_vec *bvec_alloc(gfp_t, int, unsigned long *, mempool_t *);
 extern void bvec_free(mempool_t *, struct bio_vec *, unsigned int);
 extern unsigned int bvec_nr_vecs(unsigned short idx);
+extern const char *bio_devname(struct bio *bio, char *buffer);
 
 #define bio_set_dev(bio, bdev)                  \
 do {                                            \
@@ -529,9 +530,6 @@ do {						\
 #define bio_dev(bio) \
         disk_devt((bio)->bi_disk)
 
-#define bio_devname(bio, buf) \
-        __bdevname(bio_dev(bio), (buf))
-
 #ifdef CONFIG_BLK_CGROUP
 int bio_associate_blkcg(struct bio *bio, struct cgroup_subsys_state *blkcg_css);
 void bio_disassociate_task(struct bio *bio);
diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h
index 4f3df807cf8f..ed63f3b69c12 100644
--- a/include/linux/blkdev.h
+++ b/include/linux/blkdev.h
@@ -49,7 +49,7 @@ struct blk_stat_callback;
 #define BLKDEV_MIN_RQ   4
 #define BLKDEV_MAX_RQ   128     /* Default maximum */
 
-/* Must be consisitent with blk_mq_poll_stats_bkt() */
+/* Must be consistent with blk_mq_poll_stats_bkt() */
 #define BLK_MQ_POLL_STATS_BKTS 16
 
 /*
diff --git a/include/linux/compiler-clang.h b/include/linux/compiler-clang.h
index d02a4df3f473..d3f264a5b04d 100644
--- a/include/linux/compiler-clang.h
+++ b/include/linux/compiler-clang.h
@@ -27,3 +27,8 @@
 #if __has_feature(address_sanitizer)
 #define __SANITIZE_ADDRESS__
 #endif
+
+/* Clang doesn't have a way to turn it off per-function, yet. */
+#ifdef __noretpoline
+#undef __noretpoline
+#endif
diff --git a/include/linux/compiler-gcc.h b/include/linux/compiler-gcc.h
index 631354acfa72..e2c7f4369eff 100644
--- a/include/linux/compiler-gcc.h
+++ b/include/linux/compiler-gcc.h
@@ -93,6 +93,10 @@
 #define __weak          __attribute__((weak))
 #define __alias(symbol) __attribute__((alias(#symbol)))
 
+#ifdef RETPOLINE
+#define __noretpoline __attribute__((indirect_branch("keep")))
+#endif
+
 /*
  * it doesn't make sense on ARM (currently the only user of __naked)
  * to trace naked functions because then mcount is called without
@@ -167,8 +171,6 @@
 
 #if GCC_VERSION >= 40100
 # define __compiletime_object_size(obj) __builtin_object_size(obj, 0)
-
-#define __nostackprotector      __attribute__((__optimize__("no-stack-protector")))
 #endif
 
 #if GCC_VERSION >= 40300
@@ -196,6 +198,11 @@
 #endif /* __CHECKER__ */
 #endif /* GCC_VERSION >= 40300 */
 
+#if GCC_VERSION >= 40400
+#define __optimize(level)       __attribute__((__optimize__(level)))
+#define __nostackprotector      __optimize("no-stack-protector")
+#endif /* GCC_VERSION >= 40400 */
+
 #if GCC_VERSION >= 40500
 
 #ifndef __CHECKER__
@@ -205,6 +212,15 @@
 #endif
 
 /*
+ * calling noreturn functions, __builtin_unreachable() and __builtin_trap()
+ * confuse the stack allocation in gcc, leading to overly large stack
+ * frames, see https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82365
+ *
+ * Adding an empty inline assembly before it works around the problem
+ */
+#define barrier_before_unreachable() asm volatile("")
+
+/*
  * Mark a position in code as unreachable.  This can be used to
  * suppress control flow warnings after asm blocks that transfer
  * control elsewhere.
@@ -214,7 +230,11 @@
  * unreleased.  Really, we need to have autoconf for the kernel.
  */
 #define unreachable() \
-        do { annotate_unreachable(); __builtin_unreachable(); } while (0)
+        do {                                    \
+                annotate_unreachable();         \
+                barrier_before_unreachable();   \
+                __builtin_unreachable();        \
+        } while (0)
 
 /* Mark a function definition as prohibited from being cloned. */
 #define __noclone       __attribute__((__noclone__, __optimize__("no-tracer")))
diff --git a/include/linux/compiler.h b/include/linux/compiler.h
index c2cc57a2f508..ab4711c63601 100644
--- a/include/linux/compiler.h
+++ b/include/linux/compiler.h
@@ -86,6 +86,11 @@ void ftrace_likely_update(struct ftrace_likely_data *f, int val,
 # define barrier_data(ptr) barrier()
 #endif
 
+/* workaround for GCC PR82365 if needed */
+#ifndef barrier_before_unreachable
+# define barrier_before_unreachable() do { } while (0)
+#endif
+
 /* Unreachable code */
 #ifdef CONFIG_STACK_VALIDATION
 /*
@@ -277,6 +282,10 @@ unsigned long read_word_at_a_time(const void *addr)
 
 #endif /* __ASSEMBLY__ */
 
+#ifndef __optimize
+# define __optimize(level)
+#endif
+
 /* Compile time object size, -1 for unknown */
 #ifndef __compiletime_object_size
 # define __compiletime_object_size(obj) -1
diff --git a/include/linux/cpuidle.h b/include/linux/cpuidle.h
index 871f9e21810c..0b3fc229086c 100644
--- a/include/linux/cpuidle.h
+++ b/include/linux/cpuidle.h
@@ -225,7 +225,7 @@ static inline void cpuidle_coupled_parallel_barrier(struct cpuidle_device *dev,
 }
 #endif
 
-#ifdef CONFIG_ARCH_HAS_CPU_RELAX
+#if defined(CONFIG_CPU_IDLE) && defined(CONFIG_ARCH_HAS_CPU_RELAX)
 void cpuidle_poll_state_init(struct cpuidle_driver *drv);
 #else
 static inline void cpuidle_poll_state_init(struct cpuidle_driver *drv) {}
diff --git a/include/linux/cpumask.h b/include/linux/cpumask.h
index d4a2a7dcd72d..bf53d893ad02 100644
--- a/include/linux/cpumask.h
+++ b/include/linux/cpumask.h
@@ -170,6 +170,8 @@ static inline unsigned int cpumask_local_spread(unsigned int i, int node)
         for ((cpu) = 0; (cpu) < 1; (cpu)++, (void)mask)
 #define for_each_cpu_not(cpu, mask)             \
         for ((cpu) = 0; (cpu) < 1; (cpu)++, (void)mask)
+#define for_each_cpu_wrap(cpu, mask, start)     \
+        for ((cpu) = 0; (cpu) < 1; (cpu)++, (void)mask, (void)(start))
 #define for_each_cpu_and(cpu, mask, and)        \
         for ((cpu) = 0; (cpu) < 1; (cpu)++, (void)mask, (void)and)
 #else
diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h
index 34fe8463d10e..eb9eab4ecd6d 100644
--- a/include/linux/dma-mapping.h
+++ b/include/linux/dma-mapping.h
@@ -578,7 +578,7 @@ static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
 
 /*
  * This is a hack for the legacy x86 forbid_dac and iommu_sac_force. Please
- * don't use this is new code.
+ * don't use this in new code.
  */
 #ifndef arch_dma_supported
 #define arch_dma_supported(dev, mask)   (1)
diff --git a/include/linux/fs.h b/include/linux/fs.h
index 2a815560fda0..79c413985305 100644
--- a/include/linux/fs.h
+++ b/include/linux/fs.h
@@ -3198,7 +3198,7 @@ static inline bool vma_is_fsdax(struct vm_area_struct *vma)
         if (!vma_is_dax(vma))
                 return false;
         inode = file_inode(vma->vm_file);
-        if (inode->i_mode == S_IFCHR)
+        if (S_ISCHR(inode->i_mode))
                 return false; /* device-dax */
         return true;
 }
diff --git a/include/linux/fwnode.h b/include/linux/fwnode.h
index 4fa1a489efe4..4fe8f289b3f6 100644
--- a/include/linux/fwnode.h
+++ b/include/linux/fwnode.h
@@ -73,8 +73,8 @@ struct fwnode_operations {
         struct fwnode_handle *(*get)(struct fwnode_handle *fwnode);
         void (*put)(struct fwnode_handle *fwnode);
         bool (*device_is_available)(const struct fwnode_handle *fwnode);
-        void *(*device_get_match_data)(const struct fwnode_handle *fwnode,
-                                       const struct device *dev);
+        const void *(*device_get_match_data)(const struct fwnode_handle *fwnode,
+                                             const struct device *dev);
         bool (*property_present)(const struct fwnode_handle *fwnode,
                                  const char *propname);
         int (*property_read_int_array)(const struct fwnode_handle *fwnode,
diff --git a/include/linux/genhd.h b/include/linux/genhd.h
index 5e3531027b51..c826b0b5232a 100644
--- a/include/linux/genhd.h
+++ b/include/linux/genhd.h
@@ -198,6 +198,7 @@ struct gendisk {
         void *private_data;
 
         int flags;
+        struct rw_semaphore lookup_sem;
         struct kobject *slave_dir;
 
         struct timer_rand_state *random;
@@ -600,8 +601,9 @@ extern void delete_partition(struct gendisk *, int);
 extern void printk_all_partitions(void);
 
 extern struct gendisk *__alloc_disk_node(int minors, int node_id);
-extern struct kobject *get_disk(struct gendisk *disk);
+extern struct kobject *get_disk_and_module(struct gendisk *disk);
 extern void put_disk(struct gendisk *disk);
+extern void put_disk_and_module(struct gendisk *disk);
 extern void blk_register_region(dev_t devt, unsigned long range,
                         struct module *module,
                         struct kobject *(*probe)(dev_t, int *, void *),
diff --git a/include/linux/init.h b/include/linux/init.h
index 506a98151131..bc27cf03c41e 100644
--- a/include/linux/init.h
+++ b/include/linux/init.h
@@ -6,10 +6,10 @@
 #include <linux/types.h>
 
 /* Built-in __init functions needn't be compiled with retpoline */
-#if defined(RETPOLINE) && !defined(MODULE)
-#define __noretpoline __attribute__((indirect_branch("keep")))
+#if defined(__noretpoline) && !defined(MODULE)
+#define __noinitretpoline __noretpoline
 #else
-#define __noretpoline
+#define __noinitretpoline
 #endif
 
 /* These macros are used to mark some functions or 
@@ -47,7 +47,7 @@
 
 /* These are for everybody (although not all archs will actually
    discard it in modules) */
-#define __init          __section(.init.text) __cold  __latent_entropy __noretpoline
+#define __init          __section(.init.text) __cold  __latent_entropy __noinitretpoline
 #define __initdata      __section(.init.data)
 #define __initconst     __section(.init.rodata)
 #define __exitdata      __section(.exit.data)
diff --git a/include/linux/jump_label.h b/include/linux/jump_label.h
index b6a29c126cc4..2168cc6b8b30 100644
--- a/include/linux/jump_label.h
+++ b/include/linux/jump_label.h
@@ -151,6 +151,7 @@ extern struct jump_entry __start___jump_table[];
 extern struct jump_entry __stop___jump_table[];
 
 extern void jump_label_init(void);
+extern void jump_label_invalidate_init(void);
 extern void jump_label_lock(void);
 extern void jump_label_unlock(void);
 extern void arch_jump_label_transform(struct jump_entry *entry,
@@ -198,6 +199,8 @@ static __always_inline void jump_label_init(void)
         static_key_initialized = true;
 }
 
+static inline void jump_label_invalidate_init(void) {}
+
 static __always_inline bool static_key_false(struct static_key *key)
 {
         if (unlikely(static_key_count(key) > 0))
diff --git a/include/linux/kconfig.h b/include/linux/kconfig.h
index fec5076eda91..dcde9471897d 100644
--- a/include/linux/kconfig.h
+++ b/include/linux/kconfig.h
@@ -4,6 +4,12 @@
 
 #include <generated/autoconf.h>
 
+#ifdef CONFIG_CPU_BIG_ENDIAN
+#define __BIG_ENDIAN 4321
+#else
+#define __LITTLE_ENDIAN 1234
+#endif
+
 #define __ARG_PLACEHOLDER_1 0,
 #define __take_second_arg(__ignored, val, ...) val
 
@@ -64,4 +70,7 @@
  */
 #define IS_ENABLED(option) __or(IS_BUILTIN(option), IS_MODULE(option))
 
+/* Make sure we always have all types and struct attributes defined. */
+#include <linux/compiler_types.h>
+
 #endif /* __LINUX_KCONFIG_H */
diff --git a/include/linux/kcore.h b/include/linux/kcore.h
index 7ff25a808fef..80db19d3a505 100644
--- a/include/linux/kcore.h
+++ b/include/linux/kcore.h
@@ -10,6 +10,7 @@ enum kcore_type {
         KCORE_VMALLOC,
         KCORE_RAM,
         KCORE_VMEMMAP,
+        KCORE_USER,
         KCORE_OTHER,
 };
 
diff --git a/include/linux/kernel.h b/include/linux/kernel.h
index ce51455e2adf..3fd291503576 100644
--- a/include/linux/kernel.h
+++ b/include/linux/kernel.h
@@ -472,6 +472,7 @@ extern bool parse_option_str(const char *str, const char *option);
 extern char *next_arg(char *args, char **param, char **val);
 
 extern int core_kernel_text(unsigned long addr);
+extern int init_kernel_text(unsigned long addr);
 extern int core_kernel_data(unsigned long addr);
 extern int __kernel_text_address(unsigned long addr);
 extern int kernel_text_address(unsigned long addr);
diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h
index ac0062b74aed..6930c63126c7 100644
--- a/include/linux/kvm_host.h
+++ b/include/linux/kvm_host.h
@@ -1105,7 +1105,6 @@ static inline void kvm_irq_routing_update(struct kvm *kvm)
 {
 }
 #endif
-void kvm_arch_irq_routing_update(struct kvm *kvm);
 
 static inline int kvm_ioeventfd(struct kvm *kvm, struct kvm_ioeventfd *args)
 {
@@ -1114,6 +1113,8 @@ static inline int kvm_ioeventfd(struct kvm *kvm, struct kvm_ioeventfd *args)
 
 #endif /* CONFIG_HAVE_KVM_EVENTFD */
 
+void kvm_arch_irq_routing_update(struct kvm *kvm);
+
 static inline void kvm_make_request(int req, struct kvm_vcpu *vcpu)
 {
         /*
@@ -1272,4 +1273,7 @@ static inline long kvm_arch_vcpu_async_ioctl(struct file *filp,
 }
 #endif /* CONFIG_HAVE_KVM_VCPU_ASYNC_IOCTL */
 
+void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
+                unsigned long start, unsigned long end);
+
 #endif
diff --git a/include/linux/memcontrol.h b/include/linux/memcontrol.h
index 882046863581..c46016bb25eb 100644
--- a/include/linux/memcontrol.h
+++ b/include/linux/memcontrol.h
@@ -523,9 +523,11 @@ static inline void __mod_memcg_state(struct mem_cgroup *memcg,
 static inline void mod_memcg_state(struct mem_cgroup *memcg,
                                    int idx, int val)
 {
-        preempt_disable();
+        unsigned long flags;
+
+        local_irq_save(flags);
         __mod_memcg_state(memcg, idx, val);
-        preempt_enable();
+        local_irq_restore(flags);
 }
 
 /**
@@ -606,9 +608,11 @@ static inline void __mod_lruvec_state(struct lruvec *lruvec,
 static inline void mod_lruvec_state(struct lruvec *lruvec,
                                     enum node_stat_item idx, int val)
 {
-        preempt_disable();
+        unsigned long flags;
+
+        local_irq_save(flags);
         __mod_lruvec_state(lruvec, idx, val);
-        preempt_enable();
+        local_irq_restore(flags);
 }
 
 static inline void __mod_lruvec_page_state(struct page *page,
@@ -630,9 +634,11 @@ static inline void __mod_lruvec_page_state(struct page *page,
 static inline void mod_lruvec_page_state(struct page *page,
                                          enum node_stat_item idx, int val)
 {
-        preempt_disable();
+        unsigned long flags;
+
+        local_irq_save(flags);
         __mod_lruvec_page_state(page, idx, val);
-        preempt_enable();
+        local_irq_restore(flags);
 }
 
 unsigned long mem_cgroup_soft_limit_reclaim(pg_data_t *pgdat, int order,
@@ -659,9 +665,11 @@ static inline void __count_memcg_events(struct mem_cgroup *memcg,
 static inline void count_memcg_events(struct mem_cgroup *memcg,
                                       int idx, unsigned long count)
 {
-        preempt_disable();
+        unsigned long flags;
+
+        local_irq_save(flags);
         __count_memcg_events(memcg, idx, count);
-        preempt_enable();
+        local_irq_restore(flags);
 }
 
 /* idx can be of type enum memcg_event_item or vm_event_item */
diff --git a/include/linux/mm_inline.h b/include/linux/mm_inline.h
index c30b32e3c862..10191c28fc04 100644
--- a/include/linux/mm_inline.h
+++ b/include/linux/mm_inline.h
@@ -127,10 +127,4 @@ static __always_inline enum lru_list page_lru(struct page *page)
 
 #define lru_to_page(head) (list_entry((head)->prev, struct page, lru))
 
-#ifdef arch_unmap_kpfn
-extern void arch_unmap_kpfn(unsigned long pfn);
-#else
-static __always_inline void arch_unmap_kpfn(unsigned long pfn) { }
-#endif
-
 #endif
diff --git a/include/linux/mutex.h b/include/linux/mutex.h
index f25c13423bd4..cb3bbed4e633 100644
--- a/include/linux/mutex.h
+++ b/include/linux/mutex.h
@@ -66,6 +66,11 @@ struct mutex {
 #endif
 };
 
+/*
+ * Internal helper function; C doesn't allow us to hide it :/
+ *
+ * DO NOT USE (outside of mutex code).
+ */
 static inline struct task_struct *__mutex_owner(struct mutex *lock)
 {
         return (struct task_struct *)(atomic_long_read(&lock->owner) & ~0x07);
diff --git a/include/linux/nospec.h b/include/linux/nospec.h
index b99bced39ac2..e791ebc65c9c 100644
--- a/include/linux/nospec.h
+++ b/include/linux/nospec.h
@@ -5,6 +5,7 @@
 
 #ifndef _LINUX_NOSPEC_H
 #define _LINUX_NOSPEC_H
+#include <asm/barrier.h>
 
 /**
  * array_index_mask_nospec() - generate a ~0 mask when index < size, 0 otherwise
@@ -20,20 +21,6 @@ static inline unsigned long array_index_mask_nospec(unsigned long index,
                                                     unsigned long size)
 {
         /*
-         * Warn developers about inappropriate array_index_nospec() usage.
-         *
-         * Even if the CPU speculates past the WARN_ONCE branch, the
-         * sign bit of @index is taken into account when generating the
-         * mask.
-         *
-         * This warning is compiled out when the compiler can infer that
-         * @index and @size are less than LONG_MAX.
-         */
-        if (WARN_ONCE(index > LONG_MAX || size > LONG_MAX,
-                        "array_index_nospec() limited to range of [0, LONG_MAX]\n"))
-                return 0;
-
-        /*
          * Always calculate and emit the mask even if the compiler
          * thinks the mask is not needed. The compiler does not take
          * into account the value of @index under speculation.
@@ -66,7 +53,6 @@ static inline unsigned long array_index_mask_nospec(unsigned long index,
         BUILD_BUG_ON(sizeof(_i) > sizeof(long));                        \
         BUILD_BUG_ON(sizeof(_s) > sizeof(long));                        \
                                                                         \
-        _i &= _mask;                                                    \
-        _i;                                                             \
+        (typeof(_i)) (_i & _mask);                                      \
 })
 #endif /* _LINUX_NOSPEC_H */
diff --git a/include/linux/perf/arm_pmu.h b/include/linux/perf/arm_pmu.h
index af0f44effd44..40036a57d072 100644
--- a/include/linux/perf/arm_pmu.h
+++ b/include/linux/perf/arm_pmu.h
@@ -14,26 +14,10 @@
 
 #include <linux/interrupt.h>
 #include <linux/perf_event.h>
+#include <linux/platform_device.h>
 #include <linux/sysfs.h>
 #include <asm/cputype.h>
 
-/*
- * struct arm_pmu_platdata - ARM PMU platform data
- *
- * @handle_irq: an optional handler which will be called from the
- *      interrupt and passed the address of the low level handler,
- *      and can be used to implement any platform specific handling
- *      before or after calling it.
- *
- * @irq_flags: if non-zero, these flags will be passed to request_irq
- *             when requesting interrupts for this PMU device.
- */
-struct arm_pmu_platdata {
-        irqreturn_t (*handle_irq)(int irq, void *dev,
-                                  irq_handler_t pmu_handler);
-        unsigned long irq_flags;
-};
-
 #ifdef CONFIG_ARM_PMU
 
 /*
@@ -92,7 +76,6 @@ enum armpmu_attr_groups {
 
 struct arm_pmu {
         struct pmu      pmu;
-        cpumask_t       active_irqs;
         cpumask_t       supported_cpus;
         char            *name;
         irqreturn_t     (*handle_irq)(int irq_num, void *dev);
@@ -174,12 +157,11 @@ static inline int arm_pmu_acpi_probe(armpmu_init_fn init_fn) { return 0; }
 
 /* Internal functions only for core arm_pmu code */
 struct arm_pmu *armpmu_alloc(void);
+struct arm_pmu *armpmu_alloc_atomic(void);
 void armpmu_free(struct arm_pmu *pmu);
 int armpmu_register(struct arm_pmu *pmu);
-int armpmu_request_irqs(struct arm_pmu *armpmu);
-void armpmu_free_irqs(struct arm_pmu *armpmu);
-int armpmu_request_irq(struct arm_pmu *armpmu, int cpu);
-void armpmu_free_irq(struct arm_pmu *armpmu, int cpu);
+int armpmu_request_irq(int irq, int cpu);
+void armpmu_free_irq(int irq, int cpu);
 
 #define ARMV8_PMU_PDEV_NAME "armv8-pmu"
 
diff --git a/include/linux/property.h b/include/linux/property.h
index 769d372c1edf..2eea4b310fc2 100644
--- a/include/linux/property.h
+++ b/include/linux/property.h
@@ -283,7 +283,7 @@ bool device_dma_supported(struct device *dev);
 
 enum dev_dma_attr device_get_dma_attr(struct device *dev);
 
-void *device_get_match_data(struct device *dev);
+const void *device_get_match_data(struct device *dev);
 
 int device_get_phy_mode(struct device *dev);
 
diff --git a/include/linux/ptr_ring.h b/include/linux/ptr_ring.h
index b884b7794187..e6335227b844 100644
--- a/include/linux/ptr_ring.h
+++ b/include/linux/ptr_ring.h
@@ -469,7 +469,7 @@ static inline int ptr_ring_consume_batched_bh(struct ptr_ring *r,
  */
 static inline void **__ptr_ring_init_queue_alloc(unsigned int size, gfp_t gfp)
 {
-        if (size * sizeof(void *) > KMALLOC_MAX_SIZE)
+        if (size > KMALLOC_MAX_SIZE / sizeof(void *))
                 return NULL;
         return kvmalloc_array(size, sizeof(void *), gfp | __GFP_ZERO);
 }
diff --git a/include/linux/sched/mm.h b/include/linux/sched/mm.h
index 1149533aa2fa..9806184bb3d5 100644
--- a/include/linux/sched/mm.h
+++ b/include/linux/sched/mm.h
@@ -36,7 +36,18 @@ static inline void mmgrab(struct mm_struct *mm)
         atomic_inc(&mm->mm_count);
 }
 
-extern void mmdrop(struct mm_struct *mm);
+extern void __mmdrop(struct mm_struct *mm);
+
+static inline void mmdrop(struct mm_struct *mm)
+{
+        /*
+         * The implicit full barrier implied by atomic_dec_and_test() is
+         * required by the membarrier system call before returning to
+         * user-space, after storing to rq->curr.
+         */
+        if (unlikely(atomic_dec_and_test(&mm->mm_count)))
+                __mmdrop(mm);
+}
 
 /**
  * mmget() - Pin the address space associated with a &struct mm_struct.
diff --git a/include/linux/sched/user.h b/include/linux/sched/user.h
index 0dcf4e480ef7..96fe289c4c6e 100644
--- a/include/linux/sched/user.h
+++ b/include/linux/sched/user.h
@@ -4,6 +4,7 @@
 
 #include <linux/uidgid.h>
 #include <linux/atomic.h>
+#include <linux/ratelimit.h>
 
 struct key;
 
@@ -41,6 +42,9 @@ struct user_struct {
     defined(CONFIG_NET)
         atomic_long_t locked_vm;
 #endif
+
+        /* Miscellaneous per-user rate limit */
+        struct ratelimit_state ratelimit;
 };
 
 extern int uids_sysfs_init(void);
diff --git a/include/linux/semaphore.h b/include/linux/semaphore.h
index dc368b8ce215..11c86fbfeb98 100644
--- a/include/linux/semaphore.h
+++ b/include/linux/semaphore.h
@@ -4,7 +4,7 @@
  *
  * Distributed under the terms of the GNU GPL, version 2
  *
- * Please see kernel/semaphore.c for documentation of these functions
+ * Please see kernel/locking/semaphore.c for documentation of these functions
  */
 #ifndef __LINUX_SEMAPHORE_H
 #define __LINUX_SEMAPHORE_H
diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h
index 5ebc0f869720..c1e66bdcf583 100644
--- a/include/linux/skbuff.h
+++ b/include/linux/skbuff.h
@@ -3646,7 +3646,7 @@ static inline bool __skb_checksum_validate_needed(struct sk_buff *skb,
         return true;
 }
 
-/* For small packets <= CHECKSUM_BREAK peform checksum complete directly
+/* For small packets <= CHECKSUM_BREAK perform checksum complete directly
  * in checksum_init.
  */
 #define CHECKSUM_BREAK 76
diff --git a/include/linux/swap.h b/include/linux/swap.h
index 7b6a59f722a3..a1a3f4ed94ce 100644
--- a/include/linux/swap.h
+++ b/include/linux/swap.h
@@ -337,8 +337,6 @@ extern void deactivate_file_page(struct page *page);
 extern void mark_page_lazyfree(struct page *page);
 extern void swap_setup(void);
 
-extern void add_page_to_unevictable_list(struct page *page);
-
 extern void lru_cache_add_active_or_unevictable(struct page *page,
                                                 struct vm_area_struct *vma);
 
diff --git a/include/linux/workqueue.h b/include/linux/workqueue.h
index 4a54ef96aff5..bc0cda180c8b 100644
--- a/include/linux/workqueue.h
+++ b/include/linux/workqueue.h
@@ -465,6 +465,7 @@ extern bool cancel_delayed_work_sync(struct delayed_work *dwork);
 
 extern void workqueue_set_max_active(struct workqueue_struct *wq,
                                      int max_active);
+extern struct work_struct *current_work(void);
 extern bool current_is_workqueue_rescuer(void);
 extern bool workqueue_congested(int cpu, struct workqueue_struct *wq);
 extern unsigned int work_busy(struct work_struct *work);
diff --git a/include/media/demux.h b/include/media/demux.h
index c4df6cee48e6..bf00a5a41a90 100644
--- a/include/media/demux.h
+++ b/include/media/demux.h
@@ -117,7 +117,7 @@ struct dmx_ts_feed {
  *                specified by @filter_value that will be used on the filter
  *                match logic.
  * @filter_mode:  Contains a 16 bytes (128 bits) filter mode.
- * @parent:       Pointer to struct dmx_section_feed.
+ * @parent:       Back-pointer to struct dmx_section_feed.
  * @priv:         Pointer to private data of the API client.
  *
  *
@@ -130,8 +130,9 @@ struct dmx_section_filter {
         u8 filter_value[DMX_MAX_FILTER_SIZE];
         u8 filter_mask[DMX_MAX_FILTER_SIZE];
         u8 filter_mode[DMX_MAX_FILTER_SIZE];
-        struct dmx_section_feed *parent; /* Back-pointer */
-        void *priv; /* Pointer to private data of the API client */
+        struct dmx_section_feed *parent;
+
+        void *priv;
 };
 
 /**
@@ -193,6 +194,10 @@ struct dmx_section_feed {
  * @buffer2:            Pointer to the tail of the filtered TS packets, or NULL.
  * @buffer2_length:     Length of the TS data in buffer2.
  * @source:             Indicates which TS feed is the source of the callback.
+ * @buffer_flags:       Address where buffer flags are stored. Those are
+ *                      used to report discontinuity users via DVB
+ *                      memory mapped API, as defined by
+ *                      &enum dmx_buffer_flags.
  *
  * This function callback prototype, provided by the client of the demux API,
  * is called from the demux code. The function is only called when filtering
@@ -245,7 +250,8 @@ typedef int (*dmx_ts_cb)(const u8 *buffer1,
                          size_t buffer1_length,
                          const u8 *buffer2,
                          size_t buffer2_length,
-                         struct dmx_ts_feed *source);
+                         struct dmx_ts_feed *source,
+                         u32 *buffer_flags);
 
 /**
  * typedef dmx_section_cb - DVB demux TS filter callback function prototype
@@ -261,6 +267,10 @@ typedef int (*dmx_ts_cb)(const u8 *buffer1,
  *                      including headers and CRC.
  * @source:             Indicates which section feed is the source of the
  *                      callback.
+ * @buffer_flags:       Address where buffer flags are stored. Those are
+ *                      used to report discontinuity users via DVB
+ *                      memory mapped API, as defined by
+ *                      &enum dmx_buffer_flags.
  *
  * This function callback prototype, provided by the client of the demux API,
  * is called from the demux code. The function is only called when
@@ -286,7 +296,8 @@ typedef int (*dmx_section_cb)(const u8 *buffer1,
                               size_t buffer1_len,
                               const u8 *buffer2,
                               size_t buffer2_len,
-                              struct dmx_section_filter *source);
+                              struct dmx_section_filter *source,
+                              u32 *buffer_flags);
 
 /*
  * DVB Front-End
diff --git a/include/media/dmxdev.h b/include/media/dmxdev.h
index 2f5cb2c7b6a7..baafa3b8aca4 100644
--- a/include/media/dmxdev.h
+++ b/include/media/dmxdev.h
@@ -163,6 +163,7 @@ struct dmxdev_filter {
  * @demux:              pointer to &struct dmx_demux.
  * @filternum:          number of filters.
  * @capabilities:       demux capabilities as defined by &enum dmx_demux_caps.
+ * @may_do_mmap:        flag used to indicate if the device may do mmap.
  * @exit:               flag to indicate that the demux is being released.
  * @dvr_orig_fe:        pointer to &struct dmx_frontend.
  * @dvr_buffer:         embedded &struct dvb_ringbuffer for DVB output.
@@ -180,6 +181,7 @@ struct dmxdev {
         int filternum;
         int capabilities;
 
+        unsigned int may_do_mmap:1;
         unsigned int exit:1;
 #define DMXDEV_CAP_DUPLEX 1
         struct dmx_frontend *dvr_orig_fe;
diff --git a/include/media/dvb_demux.h b/include/media/dvb_demux.h
index b07092038f4b..3b6aeca7a49e 100644
--- a/include/media/dvb_demux.h
+++ b/include/media/dvb_demux.h
@@ -115,6 +115,8 @@ struct dvb_demux_filter {
  * @pid:        PID to be filtered.
  * @timeout:    feed timeout.
  * @filter:     pointer to &struct dvb_demux_filter.
+ * @buffer_flags: Buffer flags used to report discontinuity users via DVB
+ *                memory mapped API, as defined by &enum dmx_buffer_flags.
  * @ts_type:    type of TS, as defined by &enum ts_filter_type.
  * @pes_type:   type of PES, as defined by &enum dmx_ts_pes.
  * @cc:         MPEG-TS packet continuity counter
@@ -145,6 +147,8 @@ struct dvb_demux_feed {
         ktime_t timeout;
         struct dvb_demux_filter *filter;
 
+        u32 buffer_flags;
+
         enum ts_filter_type ts_type;
         enum dmx_ts_pes pes_type;
 
diff --git a/include/media/dvb_vb2.h b/include/media/dvb_vb2.h
index 01d1202d1a55..8cb88452cd6c 100644
--- a/include/media/dvb_vb2.h
+++ b/include/media/dvb_vb2.h
@@ -85,6 +85,12 @@ struct dvb_buffer {
  * @nonblocking:
  *              If different than zero, device is operating on non-blocking
  *              mode.
+ * @flags:      buffer flags as defined by &enum dmx_buffer_flags.
+ *              Filled only at &DMX_DQBUF. &DMX_QBUF should zero this field.
+ * @count:      monotonic counter for filled buffers. Helps to identify
+ *              data stream loses. Filled only at &DMX_DQBUF. &DMX_QBUF should
+ *              zero this field.
+ *
  * @name:       name of the device type. Currently, it can either be
  *              "dvr" or "demux_filter".
  */
@@ -100,10 +106,14 @@ struct dvb_vb2_ctx {
         int     buf_siz;
         int     buf_cnt;
         int     nonblocking;
+
+        enum dmx_buffer_flags flags;
+        u32     count;
+
         char    name[DVB_VB2_NAME_MAX + 1];
 };
 
-#ifndef DVB_MMAP
+#ifndef CONFIG_DVB_MMAP
 static inline int dvb_vb2_init(struct dvb_vb2_ctx *ctx,
                                const char *name, int non_blocking)
 {
@@ -114,7 +124,7 @@ static inline int dvb_vb2_release(struct dvb_vb2_ctx *ctx)
         return 0;
 };
 #define dvb_vb2_is_streaming(ctx) (0)
-#define dvb_vb2_fill_buffer(ctx, file, wait) (0)
+#define dvb_vb2_fill_buffer(ctx, file, wait, flags) (0)
 
 static inline __poll_t dvb_vb2_poll(struct dvb_vb2_ctx *ctx,
                                     struct file *file,
@@ -153,9 +163,13 @@ int dvb_vb2_is_streaming(struct dvb_vb2_ctx *ctx);
  * @ctx:        control struct for VB2 handler
  * @src:        place where the data is stored
  * @len:        number of bytes to be copied from @src
+ * @buffer_flags:
+ *              pointer to buffer flags as defined by &enum dmx_buffer_flags.
+ *              can be NULL.
  */
 int dvb_vb2_fill_buffer(struct dvb_vb2_ctx *ctx,
-                        const unsigned char *src, int len);
+                        const unsigned char *src, int len,
+                        enum dmx_buffer_flags *buffer_flags);
 
 /**
  * dvb_vb2_poll - Wrapper to vb2_core_streamon() for Digital TV
diff --git a/include/net/mac80211.h b/include/net/mac80211.h
index 906e90223066..c96511fa9198 100644
--- a/include/net/mac80211.h
+++ b/include/net/mac80211.h
@@ -4149,7 +4149,7 @@ void ieee80211_sta_uapsd_trigger(struct ieee80211_sta *sta, u8 tid);
  * The TX headroom reserved by mac80211 for its own tx_status functions.
  * This is enough for the radiotap header.
  */
-#define IEEE80211_TX_STATUS_HEADROOM    14
+#define IEEE80211_TX_STATUS_HEADROOM    ALIGN(14, 4)
 
 /**
  * ieee80211_sta_set_buffered - inform mac80211 about driver-buffered frames
diff --git a/include/net/regulatory.h b/include/net/regulatory.h
index ebc5a2ed8631..f83cacce3308 100644
--- a/include/net/regulatory.h
+++ b/include/net/regulatory.h
@@ -78,7 +78,7 @@ struct regulatory_request {
         int wiphy_idx;
         enum nl80211_reg_initiator initiator;
         enum nl80211_user_reg_hint_type user_reg_hint_type;
-        char alpha2[2];
+        char alpha2[3];
         enum nl80211_dfs_regions dfs_region;
         bool intersect;
         bool processed;
diff --git a/include/net/udplite.h b/include/net/udplite.h
index 81bdbf97319b..9185e45b997f 100644
--- a/include/net/udplite.h
+++ b/include/net/udplite.h
@@ -64,6 +64,7 @@ static inline int udplite_checksum_init(struct sk_buff *skb, struct udphdr *uh)
                 UDP_SKB_CB(skb)->cscov = cscov;
                 if (skb->ip_summed == CHECKSUM_COMPLETE)
                         skb->ip_summed = CHECKSUM_NONE;
+                skb->csum_valid = 0;
         }
 
         return 0;
diff --git a/include/rdma/restrack.h b/include/rdma/restrack.h
index c2d81167c858..2cdf8dcf4bdc 100644
--- a/include/rdma/restrack.h
+++ b/include/rdma/restrack.h
@@ -29,10 +29,6 @@ enum rdma_restrack_type {
          */
         RDMA_RESTRACK_QP,
         /**
-         * @RDMA_RESTRACK_XRCD: XRC domain (XRCD)
-         */
-        RDMA_RESTRACK_XRCD,
-        /**
          * @RDMA_RESTRACK_MAX: Last entry, used for array dclarations
          */
         RDMA_RESTRACK_MAX
diff --git a/include/rdma/uverbs_ioctl.h b/include/rdma/uverbs_ioctl.h
index 6da44079aa58..38287d9d23a1 100644
--- a/include/rdma/uverbs_ioctl.h
+++ b/include/rdma/uverbs_ioctl.h
@@ -276,10 +276,7 @@ struct uverbs_object_tree_def {
  */
 
 struct uverbs_ptr_attr {
-        union {
-                u64             data;
-                void    __user *ptr;
-        };
+        u64             data;
         u16             len;
         /* Combination of bits from enum UVERBS_ATTR_F_XXXX */
         u16             flags;
@@ -351,38 +348,60 @@ static inline const struct uverbs_attr *uverbs_attr_get(const struct uverbs_attr
 }
 
 static inline int uverbs_copy_to(const struct uverbs_attr_bundle *attrs_bundle,
-                                 size_t idx, const void *from)
+                                 size_t idx, const void *from, size_t size)
 {
         const struct uverbs_attr *attr = uverbs_attr_get(attrs_bundle, idx);
         u16 flags;
+        size_t min_size;
 
         if (IS_ERR(attr))
                 return PTR_ERR(attr);
 
+        min_size = min_t(size_t, attr->ptr_attr.len, size);
+        if (copy_to_user(u64_to_user_ptr(attr->ptr_attr.data), from, min_size))
+                return -EFAULT;
+
         flags = attr->ptr_attr.flags | UVERBS_ATTR_F_VALID_OUTPUT;
-        return (!copy_to_user(attr->ptr_attr.ptr, from, attr->ptr_attr.len) &&
-                !put_user(flags, &attr->uattr->flags)) ? 0 : -EFAULT;
+        if (put_user(flags, &attr->uattr->flags))
+                return -EFAULT;
+
+        return 0;
 }
 
-static inline int _uverbs_copy_from(void *to, size_t to_size,
+static inline bool uverbs_attr_ptr_is_inline(const struct uverbs_attr *attr)
+{
+        return attr->ptr_attr.len <= sizeof(attr->ptr_attr.data);
+}
+
+static inline int _uverbs_copy_from(void *to,
                                     const struct uverbs_attr_bundle *attrs_bundle,
-                                    size_t idx)
+                                    size_t idx,
+                                    size_t size)
 {
         const struct uverbs_attr *attr = uverbs_attr_get(attrs_bundle, idx);
 
         if (IS_ERR(attr))
                 return PTR_ERR(attr);
 
-        if (to_size <= sizeof(((struct ib_uverbs_attr *)0)->data))
+        /*
+         * Validation ensures attr->ptr_attr.len >= size. If the caller is
+         * using UVERBS_ATTR_SPEC_F_MIN_SZ then it must call copy_from with
+         * the right size.
+         */
+        if (unlikely(size < attr->ptr_attr.len))
+                return -EINVAL;
+
+        if (uverbs_attr_ptr_is_inline(attr))
                 memcpy(to, &attr->ptr_attr.data, attr->ptr_attr.len);
-        else if (copy_from_user(to, attr->ptr_attr.ptr, attr->ptr_attr.len))
+        else if (copy_from_user(to, u64_to_user_ptr(attr->ptr_attr.data),
+                                attr->ptr_attr.len))
                 return -EFAULT;
 
         return 0;
 }
 
 #define uverbs_copy_from(to, attrs_bundle, idx)                               \
-        _uverbs_copy_from(to, sizeof(*(to)), attrs_bundle, idx)
+        _uverbs_copy_from(to, attrs_bundle, idx, sizeof(*to))
 
 /* =================================================
  *       Definitions -> Specs infrastructure
diff --git a/include/soc/arc/mcip.h b/include/soc/arc/mcip.h
index c2d1b15da136..a91f25151a5b 100644
--- a/include/soc/arc/mcip.h
+++ b/include/soc/arc/mcip.h
@@ -15,6 +15,7 @@
 
 #define ARC_REG_MCIP_BCR        0x0d0
 #define ARC_REG_MCIP_IDU_BCR    0x0D5
+#define ARC_REG_GFRC_BUILD      0x0D6
 #define ARC_REG_MCIP_CMD        0x600
 #define ARC_REG_MCIP_WDATA      0x601
 #define ARC_REG_MCIP_READBACK   0x602
@@ -36,10 +37,14 @@ struct mcip_cmd {
 #define CMD_SEMA_RELEASE                0x12
 
 #define CMD_DEBUG_SET_MASK              0x34
+#define CMD_DEBUG_READ_MASK             0x35
 #define CMD_DEBUG_SET_SELECT            0x36
+#define CMD_DEBUG_READ_SELECT           0x37
 
 #define CMD_GFRC_READ_LO                0x42
 #define CMD_GFRC_READ_HI                0x43
+#define CMD_GFRC_SET_CORE               0x47
+#define CMD_GFRC_READ_CORE              0x48
 
 #define CMD_IDU_ENABLE                  0x71
 #define CMD_IDU_DISABLE                 0x72
diff --git a/include/sound/ac97/regs.h b/include/sound/ac97/regs.h
index 4bb86d379bd5..9a4fa0c3264a 100644
--- a/include/sound/ac97/regs.h
+++ b/include/sound/ac97/regs.h
@@ -31,7 +31,7 @@
 #define AC97_HEADPHONE          0x04    /* Headphone Volume (optional) */
 #define AC97_MASTER_MONO        0x06    /* Master Volume Mono (optional) */
 #define AC97_MASTER_TONE        0x08    /* Master Tone (Bass & Treble) (optional) */
-#define AC97_PC_BEEP            0x0a    /* PC Beep Volume (optinal) */
+#define AC97_PC_BEEP            0x0a    /* PC Beep Volume (optional) */
 #define AC97_PHONE              0x0c    /* Phone Volume (optional) */
 #define AC97_MIC                0x0e    /* MIC Volume */
 #define AC97_LINE               0x10    /* Line In Volume */
diff --git a/include/trace/events/xen.h b/include/trace/events/xen.h
index b8adf05c534e..7dd8f34c37df 100644
--- a/include/trace/events/xen.h
+++ b/include/trace/events/xen.h
@@ -368,7 +368,7 @@ TRACE_EVENT(xen_mmu_flush_tlb,
             TP_printk("%s", "")
         );
 
-TRACE_EVENT(xen_mmu_flush_tlb_single,
+TRACE_EVENT(xen_mmu_flush_tlb_one_user,
             TP_PROTO(unsigned long addr),
             TP_ARGS(addr),
             TP_STRUCT__entry(
diff --git a/include/uapi/drm/virtgpu_drm.h b/include/uapi/drm/virtgpu_drm.h
index 91a31ffed828..9a781f0611df 100644
--- a/include/uapi/drm/virtgpu_drm.h
+++ b/include/uapi/drm/virtgpu_drm.h
@@ -63,6 +63,7 @@ struct drm_virtgpu_execbuffer {
 };
 
 #define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */
+#define VIRTGPU_PARAM_CAPSET_QUERY_FIX 2 /* do we have the capset fix */
 
 struct drm_virtgpu_getparam {
         __u64 param;
diff --git a/include/uapi/linux/blktrace_api.h b/include/uapi/linux/blktrace_api.h
index 20d1490d6377..3c50e07ee833 100644
--- a/include/uapi/linux/blktrace_api.h
+++ b/include/uapi/linux/blktrace_api.h
@@ -131,7 +131,7 @@ enum {
 #define BLKTRACE_BDEV_SIZE      32
 
 /*
- * User setup structure passed with BLKTRACESTART
+ * User setup structure passed with BLKTRACESETUP
  */
 struct blk_user_trace_setup {
         char name[BLKTRACE_BDEV_SIZE];  /* output */
diff --git a/include/uapi/linux/dvb/dmx.h b/include/uapi/linux/dvb/dmx.h
index 5f3c5a918f00..b4112f0b6dd3 100644
--- a/include/uapi/linux/dvb/dmx.h
+++ b/include/uapi/linux/dvb/dmx.h
@@ -212,6 +212,32 @@ struct dmx_stc {
 };
 
 /**
+ * enum dmx_buffer_flags - DMX memory-mapped buffer flags
+ *
+ * @DMX_BUFFER_FLAG_HAD_CRC32_DISCARD:
+ *      Indicates that the Kernel discarded one or more frames due to wrong
+ *      CRC32 checksum.
+ * @DMX_BUFFER_FLAG_TEI:
+ *      Indicates that the Kernel has detected a Transport Error indicator
+ *      (TEI) on a filtered pid.
+ * @DMX_BUFFER_PKT_COUNTER_MISMATCH:
+ *      Indicates that the Kernel has detected a packet counter mismatch
+ *      on a filtered pid.
+ * @DMX_BUFFER_FLAG_DISCONTINUITY_DETECTED:
+ *      Indicates that the Kernel has detected one or more frame discontinuity.
+ * @DMX_BUFFER_FLAG_DISCONTINUITY_INDICATOR:
+ *      Received at least one packet with a frame discontinuity indicator.
+ */
+
+enum dmx_buffer_flags {
+        DMX_BUFFER_FLAG_HAD_CRC32_DISCARD               = 1 << 0,
+        DMX_BUFFER_FLAG_TEI                             = 1 << 1,
+        DMX_BUFFER_PKT_COUNTER_MISMATCH                 = 1 << 2,
+        DMX_BUFFER_FLAG_DISCONTINUITY_DETECTED          = 1 << 3,
+        DMX_BUFFER_FLAG_DISCONTINUITY_INDICATOR         = 1 << 4,
+};
+
+/**
  * struct dmx_buffer - dmx buffer info
  *
  * @index:      id number of the buffer
@@ -220,15 +246,24 @@ struct dmx_stc {
  *              offset from the start of the device memory for this plane,
  *              (or a "cookie" that should be passed to mmap() as offset)
  * @length:     size in bytes of the buffer
+ * @flags:      bit array of buffer flags as defined by &enum dmx_buffer_flags.
+ *              Filled only at &DMX_DQBUF.
+ * @count:      monotonic counter for filled buffers. Helps to identify
+ *              data stream loses. Filled only at &DMX_DQBUF.
  *
  * Contains data exchanged by application and driver using one of the streaming
  * I/O methods.
+ *
+ * Please notice that, for &DMX_QBUF, only @index should be filled.
+ * On &DMX_DQBUF calls, all fields will be filled by the Kernel.
  */
 struct dmx_buffer {
         __u32                   index;
         __u32                   bytesused;
         __u32                   offset;
         __u32                   length;
+        __u32                   flags;
+        __u32                   count;
 };
 
 /**
diff --git a/include/uapi/linux/if_ether.h b/include/uapi/linux/if_ether.h
index f8cb5760ea4f..8bbbcb5cd94b 100644
--- a/include/uapi/linux/if_ether.h
+++ b/include/uapi/linux/if_ether.h
@@ -23,7 +23,6 @@
 #define _UAPI_LINUX_IF_ETHER_H
 
 #include <linux/types.h>
-#include <linux/libc-compat.h>
 
 /*
  *      IEEE 802.3 Ethernet magic constants.  The frame sizes omit the preamble
@@ -151,6 +150,11 @@
  *      This is an Ethernet frame header.
  */
 
+/* allow libcs like musl to deactivate this, glibc does not implement this. */
+#ifndef __UAPI_DEF_ETHHDR
+#define __UAPI_DEF_ETHHDR               1
+#endif
+
 #if __UAPI_DEF_ETHHDR
 struct ethhdr {
         unsigned char   h_dest[ETH_ALEN];       /* destination eth addr */
diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
index 0fb5ef939732..7b26d4b0b052 100644
--- a/include/uapi/linux/kvm.h
+++ b/include/uapi/linux/kvm.h
@@ -761,6 +761,7 @@ struct kvm_ppc_resize_hpt {
 #define KVM_TRACE_PAUSE           __KVM_DEPRECATED_MAIN_0x07
 #define KVM_TRACE_DISABLE         __KVM_DEPRECATED_MAIN_0x08
 #define KVM_GET_EMULATED_CPUID    _IOWR(KVMIO, 0x09, struct kvm_cpuid2)
+#define KVM_GET_MSR_FEATURE_INDEX_LIST    _IOWR(KVMIO, 0x0a, struct kvm_msr_list)
 
 /*
  * Extension capability list.
@@ -934,6 +935,7 @@ struct kvm_ppc_resize_hpt {
 #define KVM_CAP_S390_AIS_MIGRATION 150
 #define KVM_CAP_PPC_GET_CPU_CHAR 151
 #define KVM_CAP_S390_BPB 152
+#define KVM_CAP_GET_MSR_FEATURES 153
 
 #ifdef KVM_CAP_IRQ_ROUTING
 
diff --git a/include/uapi/linux/libc-compat.h b/include/uapi/linux/libc-compat.h
index fc29efaa918c..8254c937c9f4 100644
--- a/include/uapi/linux/libc-compat.h
+++ b/include/uapi/linux/libc-compat.h
@@ -264,10 +264,4 @@
 
 #endif /* __GLIBC__ */
 
-/* Definitions for if_ether.h */
-/* allow libcs like musl to deactivate this, glibc does not implement this. */
-#ifndef __UAPI_DEF_ETHHDR
-#define __UAPI_DEF_ETHHDR               1
-#endif
-
 #endif /* _UAPI_LIBC_COMPAT_H */
diff --git a/include/uapi/linux/psp-sev.h b/include/uapi/linux/psp-sev.h
index 3d77fe91239a..9008f31c7eb6 100644
--- a/include/uapi/linux/psp-sev.h
+++ b/include/uapi/linux/psp-sev.h
@@ -42,7 +42,7 @@ typedef enum {
         SEV_RET_INVALID_PLATFORM_STATE,
         SEV_RET_INVALID_GUEST_STATE,
         SEV_RET_INAVLID_CONFIG,
-        SEV_RET_INVALID_len,
+        SEV_RET_INVALID_LEN,
         SEV_RET_ALREADY_OWNED,
         SEV_RET_INVALID_CERTIFICATE,
         SEV_RET_POLICY_FAILURE,
diff --git a/include/uapi/linux/ptrace.h b/include/uapi/linux/ptrace.h
index e46d82b91166..d5a1b8a492b9 100644
--- a/include/uapi/linux/ptrace.h
+++ b/include/uapi/linux/ptrace.h
@@ -69,8 +69,8 @@ struct ptrace_peeksiginfo_args {
 #define PTRACE_SECCOMP_GET_METADATA     0x420d
 
 struct seccomp_metadata {
-        unsigned long filter_off;       /* Input: which filter */
-        unsigned int flags;             /* Output: filter's flags */
+        __u64 filter_off;       /* Input: which filter */
+        __u64 flags;            /* Output: filter's flags */
 };
 
 /* Read signals from a shared (process wide) queue */
diff --git a/include/uapi/rdma/rdma_user_ioctl.h b/include/uapi/rdma/rdma_user_ioctl.h
index 03557b5f9aa6..46de0885e800 100644
--- a/include/uapi/rdma/rdma_user_ioctl.h
+++ b/include/uapi/rdma/rdma_user_ioctl.h
@@ -65,7 +65,7 @@ struct ib_uverbs_attr {
         __u16 len;              /* only for pointers */
         __u16 flags;            /* combination of UVERBS_ATTR_F_XXXX */
         __u16 reserved;
-        __u64 data;             /* ptr to command, inline data or idr/fd */
+        __aligned_u64 data;     /* ptr to command, inline data or idr/fd */
 };
 
 struct ib_uverbs_ioctl_hdr {
@@ -73,7 +73,7 @@ struct ib_uverbs_ioctl_hdr {
         __u16 object_id;
         __u16 method_id;
         __u16 num_attrs;
-        __u64 reserved;
+        __aligned_u64 reserved;
         struct ib_uverbs_attr  attrs[0];
 };
 
diff --git a/init/main.c b/init/main.c
index a8100b954839..969eaf140ef0 100644
--- a/init/main.c
+++ b/init/main.c
@@ -89,6 +89,7 @@
 #include <linux/io.h>
 #include <linux/cache.h>
 #include <linux/rodata_test.h>
+#include <linux/jump_label.h>
 
 #include <asm/io.h>
 #include <asm/bugs.h>
@@ -1000,6 +1001,7 @@ static int __ref kernel_init(void *unused)
         /* need to finish all async __init code before freeing the memory */
         async_synchronize_full();
         ftrace_free_init_mem();
+        jump_label_invalidate_init();
         free_initmem();
         mark_readonly();
         system_state = SYSTEM_RUNNING;
diff --git a/kernel/bpf/arraymap.c b/kernel/bpf/arraymap.c
index b1f66480135b..14750e7c5ee4 100644
--- a/kernel/bpf/arraymap.c
+++ b/kernel/bpf/arraymap.c
@@ -26,8 +26,10 @@ static void bpf_array_free_percpu(struct bpf_array *array)
 {
         int i;
 
-        for (i = 0; i < array->map.max_entries; i++)
+        for (i = 0; i < array->map.max_entries; i++) {
                 free_percpu(array->pptrs[i]);
+                cond_resched();
+        }
 }
 
 static int bpf_array_alloc_percpu(struct bpf_array *array)
@@ -43,6 +45,7 @@ static int bpf_array_alloc_percpu(struct bpf_array *array)
                         return -ENOMEM;
                 }
                 array->pptrs[i] = ptr;
+                cond_resched();
         }
 
         return 0;
@@ -73,11 +76,11 @@ static int array_map_alloc_check(union bpf_attr *attr)
 static struct bpf_map *array_map_alloc(union bpf_attr *attr)
 {
         bool percpu = attr->map_type == BPF_MAP_TYPE_PERCPU_ARRAY;
-        int numa_node = bpf_map_attr_numa_node(attr);
+        int ret, numa_node = bpf_map_attr_numa_node(attr);
         u32 elem_size, index_mask, max_entries;
         bool unpriv = !capable(CAP_SYS_ADMIN);
+        u64 cost, array_size, mask64;
         struct bpf_array *array;
-        u64 array_size, mask64;
 
         elem_size = round_up(attr->value_size, 8);
 
@@ -109,8 +112,19 @@ static struct bpf_map *array_map_alloc(union bpf_attr *attr)
                 array_size += (u64) max_entries * elem_size;
 
         /* make sure there is no u32 overflow later in round_up() */
-        if (array_size >= U32_MAX - PAGE_SIZE)
+        cost = array_size;
+        if (cost >= U32_MAX - PAGE_SIZE)
                 return ERR_PTR(-ENOMEM);
+        if (percpu) {
+                cost += (u64)attr->max_entries * elem_size * num_possible_cpus();
+                if (cost >= U32_MAX - PAGE_SIZE)
+                        return ERR_PTR(-ENOMEM);
+        }
+        cost = round_up(cost, PAGE_SIZE) >> PAGE_SHIFT;
+
+        ret = bpf_map_precharge_memlock(cost);
+        if (ret < 0)
+                return ERR_PTR(ret);
 
         /* allocate all map elements and zero-initialize them */
         array = bpf_map_area_alloc(array_size, numa_node);
@@ -121,20 +135,13 @@ static struct bpf_map *array_map_alloc(union bpf_attr *attr)
 
         /* copy mandatory map attributes */
         bpf_map_init_from_attr(&array->map, attr);
+        array->map.pages = cost;
         array->elem_size = elem_size;
 
-        if (!percpu)
-                goto out;
-
-        array_size += (u64) attr->max_entries * elem_size * num_possible_cpus();
-
-        if (array_size >= U32_MAX - PAGE_SIZE ||
-            bpf_array_alloc_percpu(array)) {
+        if (percpu && bpf_array_alloc_percpu(array)) {
                 bpf_map_area_free(array);
                 return ERR_PTR(-ENOMEM);
         }
-out:
-        array->map.pages = round_up(array_size, PAGE_SIZE) >> PAGE_SHIFT;
 
         return &array->map;
 }
diff --git a/kernel/bpf/core.c b/kernel/bpf/core.c
index 29ca9208dcfa..d315b393abdd 100644
--- a/kernel/bpf/core.c
+++ b/kernel/bpf/core.c
@@ -1590,7 +1590,7 @@ int bpf_prog_array_copy_to_user(struct bpf_prog_array __rcu *progs,
          * so always copy 'cnt' prog_ids to the user.
          * In a rare race the user will see zero prog_ids
          */
-        ids = kcalloc(cnt, sizeof(u32), GFP_USER);
+        ids = kcalloc(cnt, sizeof(u32), GFP_USER | __GFP_NOWARN);
         if (!ids)
                 return -ENOMEM;
         rcu_read_lock();
diff --git a/kernel/bpf/cpumap.c b/kernel/bpf/cpumap.c
index fbfdada6caee..a4bb0b34375a 100644
--- a/kernel/bpf/cpumap.c
+++ b/kernel/bpf/cpumap.c
@@ -334,7 +334,7 @@ static int cpu_map_kthread_run(void *data)
 static struct bpf_cpu_map_entry *__cpu_map_entry_alloc(u32 qsize, u32 cpu,
                                                        int map_id)
 {
-        gfp_t gfp = GFP_ATOMIC|__GFP_NOWARN;
+        gfp_t gfp = GFP_KERNEL | __GFP_NOWARN;
         struct bpf_cpu_map_entry *rcpu;
         int numa, err;
 
diff --git a/kernel/bpf/lpm_trie.c b/kernel/bpf/lpm_trie.c
index 7b469d10d0e9..b4b5b81e7251 100644
--- a/kernel/bpf/lpm_trie.c
+++ b/kernel/bpf/lpm_trie.c
@@ -555,7 +555,10 @@ static void trie_free(struct bpf_map *map)
         struct lpm_trie_node __rcu **slot;
         struct lpm_trie_node *node;
 
-        raw_spin_lock(&trie->lock);
+        /* Wait for outstanding programs to complete
+         * update/lookup/delete/get_next_key and free the trie.
+         */
+        synchronize_rcu();
 
         /* Always start at the root and walk down to a node that has no
          * children. Then free that node, nullify its reference in the parent
@@ -566,10 +569,9 @@ static void trie_free(struct bpf_map *map)
                 slot = &trie->root;
 
                 for (;;) {
-                        node = rcu_dereference_protected(*slot,
-                                        lockdep_is_held(&trie->lock));
+                        node = rcu_dereference_protected(*slot, 1);
                         if (!node)
-                                goto unlock;
+                                goto out;
 
                         if (rcu_access_pointer(node->child[0])) {
                                 slot = &node->child[0];
@@ -587,8 +589,8 @@ static void trie_free(struct bpf_map *map)
                 }
         }
 
-unlock:
-        raw_spin_unlock(&trie->lock);
+out:
+        kfree(trie);
 }
 
 static int trie_get_next_key(struct bpf_map *map, void *_key, void *_next_key)
diff --git a/kernel/bpf/sockmap.c b/kernel/bpf/sockmap.c
index 48c33417d13c..a927e89dad6e 100644
--- a/kernel/bpf/sockmap.c
+++ b/kernel/bpf/sockmap.c
@@ -521,8 +521,8 @@ static struct smap_psock *smap_init_psock(struct sock *sock,
 static struct bpf_map *sock_map_alloc(union bpf_attr *attr)
 {
         struct bpf_stab *stab;
-        int err = -EINVAL;
         u64 cost;
+        int err;
 
         if (!capable(CAP_NET_ADMIN))
                 return ERR_PTR(-EPERM);
@@ -547,6 +547,7 @@ static struct bpf_map *sock_map_alloc(union bpf_attr *attr)
 
         /* make sure page count doesn't overflow */
         cost = (u64) stab->map.max_entries * sizeof(struct sock *);
+        err = -EINVAL;
         if (cost >= U32_MAX - PAGE_SIZE)
                 goto free_stab;
 
diff --git a/kernel/extable.c b/kernel/extable.c
index a17fdb63dc3e..6a5b61ebc66c 100644
--- a/kernel/extable.c
+++ b/kernel/extable.c
@@ -64,7 +64,7 @@ const struct exception_table_entry *search_exception_tables(unsigned long addr)
         return e;
 }
 
-static inline int init_kernel_text(unsigned long addr)
+int init_kernel_text(unsigned long addr)
 {
         if (addr >= (unsigned long)_sinittext &&
             addr < (unsigned long)_einittext)
diff --git a/kernel/fork.c b/kernel/fork.c
index be8aa5b98666..e5d9d405ae4e 100644
--- a/kernel/fork.c
+++ b/kernel/fork.c
@@ -592,7 +592,7 @@ static void check_mm(struct mm_struct *mm)
  * is dropped: either by a lazy thread or by
  * mmput. Free the page directory and the mm.
  */
-static void __mmdrop(struct mm_struct *mm)
+void __mmdrop(struct mm_struct *mm)
 {
         BUG_ON(mm == &init_mm);
         mm_free_pgd(mm);
@@ -603,18 +603,7 @@ static void __mmdrop(struct mm_struct *mm)
         put_user_ns(mm->user_ns);
         free_mm(mm);
 }
-
-void mmdrop(struct mm_struct *mm)
-{
-        /*
-         * The implicit full barrier implied by atomic_dec_and_test() is
-         * required by the membarrier system call before returning to
-         * user-space, after storing to rq->curr.
-         */
-        if (unlikely(atomic_dec_and_test(&mm->mm_count)))
-                __mmdrop(mm);
-}
-EXPORT_SYMBOL_GPL(mmdrop);
+EXPORT_SYMBOL_GPL(__mmdrop);
 
 static void mmdrop_async_fn(struct work_struct *work)
 {
diff --git a/kernel/irq/irqdomain.c b/kernel/irq/irqdomain.c
index e6a9c36470ee..82b8b18ee1eb 100644
--- a/kernel/irq/irqdomain.c
+++ b/kernel/irq/irqdomain.c
@@ -1726,25 +1726,14 @@ static int irq_domain_debug_show(struct seq_file *m, void *p)
         irq_domain_debug_show_one(m, d, 0);
         return 0;
 }
-
-static int irq_domain_debug_open(struct inode *inode, struct file *file)
-{
-        return single_open(file, irq_domain_debug_show, inode->i_private);
-}
-
-static const struct file_operations dfs_domain_ops = {
-        .open           = irq_domain_debug_open,
-        .read           = seq_read,
-        .llseek         = seq_lseek,
-        .release        = single_release,
-};
+DEFINE_SHOW_ATTRIBUTE(irq_domain_debug);
 
 static void debugfs_add_domain_dir(struct irq_domain *d)
 {
         if (!d->name || !domain_dir || d->debugfs_file)
                 return;
         d->debugfs_file = debugfs_create_file(d->name, 0444, domain_dir, d,
-                                              &dfs_domain_ops);
+                                              &irq_domain_debug_fops);
 }
 
 static void debugfs_remove_domain_dir(struct irq_domain *d)
@@ -1760,7 +1749,8 @@ void __init irq_domain_debugfs_init(struct dentry *root)
         if (!domain_dir)
                 return;
 
-        debugfs_create_file("default", 0444, domain_dir, NULL, &dfs_domain_ops);
+        debugfs_create_file("default", 0444, domain_dir, NULL,
+                            &irq_domain_debug_fops);
         mutex_lock(&irq_domain_mutex);
         list_for_each_entry(d, &irq_domain_list, link)
                 debugfs_add_domain_dir(d);
diff --git a/kernel/irq/matrix.c b/kernel/irq/matrix.c
index 5187dfe809ac..4c5770407031 100644
--- a/kernel/irq/matrix.c
+++ b/kernel/irq/matrix.c
@@ -16,6 +16,7 @@ struct cpumap {
         unsigned int            available;
         unsigned int            allocated;
         unsigned int            managed;
+        bool                    initialized;
         bool                    online;
         unsigned long           alloc_map[IRQ_MATRIX_SIZE];
         unsigned long           managed_map[IRQ_MATRIX_SIZE];
@@ -81,9 +82,11 @@ void irq_matrix_online(struct irq_matrix *m)
 
         BUG_ON(cm->online);
 
-        bitmap_zero(cm->alloc_map, m->matrix_bits);
-        cm->available = m->alloc_size - (cm->managed + m->systembits_inalloc);
-        cm->allocated = 0;
+        if (!cm->initialized) {
+                cm->available = m->alloc_size;
+                cm->available -= cm->managed + m->systembits_inalloc;
+                cm->initialized = true;
+        }
         m->global_available += cm->available;
         cm->online = true;
         m->online_maps++;
@@ -370,14 +373,16 @@ void irq_matrix_free(struct irq_matrix *m, unsigned int cpu,
         if (WARN_ON_ONCE(bit < m->alloc_start || bit >= m->alloc_end))
                 return;
 
-        if (cm->online) {
-                clear_bit(bit, cm->alloc_map);
-                cm->allocated--;
+        clear_bit(bit, cm->alloc_map);
+        cm->allocated--;
+
+        if (cm->online)
                 m->total_allocated--;
-                if (!managed) {
-                        cm->available++;
+
+        if (!managed) {
+                cm->available++;
+                if (cm->online)
                         m->global_available++;
-                }
         }
         trace_irq_matrix_free(bit, cpu, m, cm);
 }
diff --git a/kernel/jump_label.c b/kernel/jump_label.c
index b4517095db6a..52a0a7af8640 100644
--- a/kernel/jump_label.c
+++ b/kernel/jump_label.c
@@ -366,12 +366,15 @@ static void __jump_label_update(struct static_key *key,
 {
         for (; (entry < stop) && (jump_entry_key(entry) == key); entry++) {
                 /*
-                 * entry->code set to 0 invalidates module init text sections
-                 * kernel_text_address() verifies we are not in core kernel
-                 * init code, see jump_label_invalidate_module_init().
+                 * An entry->code of 0 indicates an entry which has been
+                 * disabled because it was in an init text area.
                  */
-                if (entry->code && kernel_text_address(entry->code))
-                        arch_jump_label_transform(entry, jump_label_type(entry));
+                if (entry->code) {
+                        if (kernel_text_address(entry->code))
+                                arch_jump_label_transform(entry, jump_label_type(entry));
+                        else
+                                WARN_ONCE(1, "can't patch jump_label at %pS", (void *)entry->code);
+                }
         }
 }
 
@@ -417,6 +420,19 @@ void __init jump_label_init(void)
         cpus_read_unlock();
 }
 
+/* Disable any jump label entries in __init code */
+void __init jump_label_invalidate_init(void)
+{
+        struct jump_entry *iter_start = __start___jump_table;
+        struct jump_entry *iter_stop = __stop___jump_table;
+        struct jump_entry *iter;
+
+        for (iter = iter_start; iter < iter_stop; iter++) {
+                if (init_kernel_text(iter->code))
+                        iter->code = 0;
+        }
+}
+
 #ifdef CONFIG_MODULES
 
 static enum jump_label_type jump_label_init_type(struct jump_entry *entry)
@@ -633,6 +649,7 @@ static void jump_label_del_module(struct module *mod)
         }
 }
 
+/* Disable any jump label entries in module init code */
 static void jump_label_invalidate_module_init(struct module *mod)
 {
         struct jump_entry *iter_start = mod->jump_entries;
diff --git a/kernel/kprobes.c b/kernel/kprobes.c
index da2ccf142358..102160ff5c66 100644
--- a/kernel/kprobes.c
+++ b/kernel/kprobes.c
@@ -978,67 +978,90 @@ static int prepare_kprobe(struct kprobe *p)
 }
 
 /* Caller must lock kprobe_mutex */
-static void arm_kprobe_ftrace(struct kprobe *p)
+static int arm_kprobe_ftrace(struct kprobe *p)
 {
-        int ret;
+        int ret = 0;
 
         ret = ftrace_set_filter_ip(&kprobe_ftrace_ops,
                                    (unsigned long)p->addr, 0, 0);
-        WARN(ret < 0, "Failed to arm kprobe-ftrace at %p (%d)\n", p->addr, ret);
-        kprobe_ftrace_enabled++;
-        if (kprobe_ftrace_enabled == 1) {
+        if (ret) {
+                pr_debug("Failed to arm kprobe-ftrace at %p (%d)\n", p->addr, ret);
+                return ret;
+        }
+
+        if (kprobe_ftrace_enabled == 0) {
                 ret = register_ftrace_function(&kprobe_ftrace_ops);
-                WARN(ret < 0, "Failed to init kprobe-ftrace (%d)\n", ret);
+                if (ret) {
+                        pr_debug("Failed to init kprobe-ftrace (%d)\n", ret);
+                        goto err_ftrace;
+                }
         }
+
+        kprobe_ftrace_enabled++;
+        return ret;
+
+err_ftrace:
+        /*
+         * Note: Since kprobe_ftrace_ops has IPMODIFY set, and ftrace requires a
+         * non-empty filter_hash for IPMODIFY ops, we're safe from an accidental
+         * empty filter_hash which would undesirably trace all functions.
+         */
+        ftrace_set_filter_ip(&kprobe_ftrace_ops, (unsigned long)p->addr, 1, 0);
+        return ret;
 }
 
 /* Caller must lock kprobe_mutex */
-static void disarm_kprobe_ftrace(struct kprobe *p)
+static int disarm_kprobe_ftrace(struct kprobe *p)
 {
-        int ret;
+        int ret = 0;
 
-        kprobe_ftrace_enabled--;
-        if (kprobe_ftrace_enabled == 0) {
+        if (kprobe_ftrace_enabled == 1) {
                 ret = unregister_ftrace_function(&kprobe_ftrace_ops);
-                WARN(ret < 0, "Failed to init kprobe-ftrace (%d)\n", ret);
+                if (WARN(ret < 0, "Failed to unregister kprobe-ftrace (%d)\n", ret))
+                        return ret;
         }
+
+        kprobe_ftrace_enabled--;
+
         ret = ftrace_set_filter_ip(&kprobe_ftrace_ops,
                            (unsigned long)p->addr, 1, 0);
         WARN(ret < 0, "Failed to disarm kprobe-ftrace at %p (%d)\n", p->addr, ret);
+        return ret;
 }
 #else   /* !CONFIG_KPROBES_ON_FTRACE */
 #define prepare_kprobe(p)       arch_prepare_kprobe(p)
-#define arm_kprobe_ftrace(p)    do {} while (0)
-#define disarm_kprobe_ftrace(p) do {} while (0)
+#define arm_kprobe_ftrace(p)    (-ENODEV)
+#define disarm_kprobe_ftrace(p) (-ENODEV)
 #endif
 
 /* Arm a kprobe with text_mutex */
-static void arm_kprobe(struct kprobe *kp)
+static int arm_kprobe(struct kprobe *kp)
 {
-        if (unlikely(kprobe_ftrace(kp))) {
-                arm_kprobe_ftrace(kp);
-                return;
-        }
+        if (unlikely(kprobe_ftrace(kp)))
+                return arm_kprobe_ftrace(kp);
+
         cpus_read_lock();
         mutex_lock(&text_mutex);
         __arm_kprobe(kp);
         mutex_unlock(&text_mutex);
         cpus_read_unlock();
+
+        return 0;
 }
 
 /* Disarm a kprobe with text_mutex */
-static void disarm_kprobe(struct kprobe *kp, bool reopt)
+static int disarm_kprobe(struct kprobe *kp, bool reopt)
 {
-        if (unlikely(kprobe_ftrace(kp))) {
-                disarm_kprobe_ftrace(kp);
-                return;
-        }
+        if (unlikely(kprobe_ftrace(kp)))
+                return disarm_kprobe_ftrace(kp);
 
         cpus_read_lock();
         mutex_lock(&text_mutex);
         __disarm_kprobe(kp, reopt);
         mutex_unlock(&text_mutex);
         cpus_read_unlock();
+
+        return 0;
 }
 
 /*
@@ -1362,9 +1385,15 @@ out:
 
         if (ret == 0 && kprobe_disabled(ap) && !kprobe_disabled(p)) {
                 ap->flags &= ~KPROBE_FLAG_DISABLED;
-                if (!kprobes_all_disarmed)
+                if (!kprobes_all_disarmed) {
                         /* Arm the breakpoint again. */
-                        arm_kprobe(ap);
+                        ret = arm_kprobe(ap);
+                        if (ret) {
+                                ap->flags |= KPROBE_FLAG_DISABLED;
+                                list_del_rcu(&p->list);
+                                synchronize_sched();
+                        }
+                }
         }
         return ret;
 }
@@ -1573,8 +1602,14 @@ int register_kprobe(struct kprobe *p)
         hlist_add_head_rcu(&p->hlist,
                        &kprobe_table[hash_ptr(p->addr, KPROBE_HASH_BITS)]);
 
-        if (!kprobes_all_disarmed && !kprobe_disabled(p))
-                arm_kprobe(p);
+        if (!kprobes_all_disarmed && !kprobe_disabled(p)) {
+                ret = arm_kprobe(p);
+                if (ret) {
+                        hlist_del_rcu(&p->hlist);
+                        synchronize_sched();
+                        goto out;
+                }
+        }
 
         /* Try to optimize kprobe */
         try_to_optimize_kprobe(p);
@@ -1608,11 +1643,12 @@ static int aggr_kprobe_disabled(struct kprobe *ap)
 static struct kprobe *__disable_kprobe(struct kprobe *p)
 {
         struct kprobe *orig_p;
+        int ret;
 
         /* Get an original kprobe for return */
         orig_p = __get_valid_kprobe(p);
         if (unlikely(orig_p == NULL))
-                return NULL;
+                return ERR_PTR(-EINVAL);
 
         if (!kprobe_disabled(p)) {
                 /* Disable probe if it is a child probe */
@@ -1626,8 +1662,13 @@ static struct kprobe *__disable_kprobe(struct kprobe *p)
                          * should have already been disarmed, so
                          * skip unneed disarming process.
                          */
-                        if (!kprobes_all_disarmed)
-                                disarm_kprobe(orig_p, true);
+                        if (!kprobes_all_disarmed) {
+                                ret = disarm_kprobe(orig_p, true);
+                                if (ret) {
+                                        p->flags &= ~KPROBE_FLAG_DISABLED;
+                                        return ERR_PTR(ret);
+                                }
+                        }
                         orig_p->flags |= KPROBE_FLAG_DISABLED;
                 }
         }
@@ -1644,8 +1685,8 @@ static int __unregister_kprobe_top(struct kprobe *p)
 
         /* Disable kprobe. This will disarm it if needed. */
         ap = __disable_kprobe(p);
-        if (ap == NULL)
-                return -EINVAL;
+        if (IS_ERR(ap))
+                return PTR_ERR(ap);
 
         if (ap == p)
                 /*
@@ -2078,12 +2119,14 @@ static void kill_kprobe(struct kprobe *p)
 int disable_kprobe(struct kprobe *kp)
 {
         int ret = 0;
+        struct kprobe *p;
 
         mutex_lock(&kprobe_mutex);
 
         /* Disable this kprobe */
-        if (__disable_kprobe(kp) == NULL)
-                ret = -EINVAL;
+        p = __disable_kprobe(kp);
+        if (IS_ERR(p))
+                ret = PTR_ERR(p);
 
         mutex_unlock(&kprobe_mutex);
         return ret;
@@ -2116,7 +2159,9 @@ int enable_kprobe(struct kprobe *kp)
 
         if (!kprobes_all_disarmed && kprobe_disabled(p)) {
                 p->flags &= ~KPROBE_FLAG_DISABLED;
-                arm_kprobe(p);
+                ret = arm_kprobe(p);
+                if (ret)
+                        p->flags |= KPROBE_FLAG_DISABLED;
         }
 out:
         mutex_unlock(&kprobe_mutex);
@@ -2407,11 +2452,12 @@ static const struct file_operations debugfs_kprobe_blacklist_ops = {
         .release        = seq_release,
 };
 
-static void arm_all_kprobes(void)
+static int arm_all_kprobes(void)
 {
         struct hlist_head *head;
         struct kprobe *p;
-        unsigned int i;
+        unsigned int i, total = 0, errors = 0;
+        int err, ret = 0;
 
         mutex_lock(&kprobe_mutex);
 
@@ -2428,46 +2474,74 @@ static void arm_all_kprobes(void)
         /* Arming kprobes doesn't optimize kprobe itself */
         for (i = 0; i < KPROBE_TABLE_SIZE; i++) {
                 head = &kprobe_table[i];
-                hlist_for_each_entry_rcu(p, head, hlist)
-                        if (!kprobe_disabled(p))
-                                arm_kprobe(p);
+                /* Arm all kprobes on a best-effort basis */
+                hlist_for_each_entry_rcu(p, head, hlist) {
+                        if (!kprobe_disabled(p)) {
+                                err = arm_kprobe(p);
+                                if (err)  {
+                                        errors++;
+                                        ret = err;
+                                }
+                                total++;
+                        }
+                }
         }
 
-        printk(KERN_INFO "Kprobes globally enabled\n");
+        if (errors)
+                pr_warn("Kprobes globally enabled, but failed to arm %d out of %d probes\n",
+                        errors, total);
+        else
+                pr_info("Kprobes globally enabled\n");
 
 already_enabled:
         mutex_unlock(&kprobe_mutex);
-        return;
+        return ret;
 }
 
-static void disarm_all_kprobes(void)
+static int disarm_all_kprobes(void)
 {
         struct hlist_head *head;
         struct kprobe *p;
-        unsigned int i;
+        unsigned int i, total = 0, errors = 0;
+        int err, ret = 0;
 
         mutex_lock(&kprobe_mutex);
 
         /* If kprobes are already disarmed, just return */
         if (kprobes_all_disarmed) {
                 mutex_unlock(&kprobe_mutex);
-                return;
+                return 0;
         }
 
         kprobes_all_disarmed = true;
-        printk(KERN_INFO "Kprobes globally disabled\n");
 
         for (i = 0; i < KPROBE_TABLE_SIZE; i++) {
                 head = &kprobe_table[i];
+                /* Disarm all kprobes on a best-effort basis */
                 hlist_for_each_entry_rcu(p, head, hlist) {
-                        if (!arch_trampoline_kprobe(p) && !kprobe_disabled(p))
-                                disarm_kprobe(p, false);
+                        if (!arch_trampoline_kprobe(p) && !kprobe_disabled(p)) {
+                                err = disarm_kprobe(p, false);
+                                if (err) {
+                                        errors++;
+                                        ret = err;
+                                }
+                                total++;
+                        }
                 }
         }
+
+        if (errors)
+                pr_warn("Kprobes globally disabled, but failed to disarm %d out of %d probes\n",
+                        errors, total);
+        else
+                pr_info("Kprobes globally disabled\n");
+
         mutex_unlock(&kprobe_mutex);
 
         /* Wait for disarming all kprobes by optimizer */
         wait_for_kprobe_optimizer();
+
+        return ret;
 }
 
 /*
@@ -2494,6 +2568,7 @@ static ssize_t write_enabled_file_bool(struct file *file,
 {
         char buf[32];
         size_t buf_size;
+        int ret = 0;
 
         buf_size = min(count, (sizeof(buf)-1));
         if (copy_from_user(buf, user_buf, buf_size))
@@ -2504,17 +2579,20 @@ static ssize_t write_enabled_file_bool(struct file *file,
         case 'y':
         case 'Y':
         case '1':
-                arm_all_kprobes();
+                ret = arm_all_kprobes();
                 break;
         case 'n':
         case 'N':
         case '0':
-                disarm_all_kprobes();
+                ret = disarm_all_kprobes();
                 break;
         default:
                 return -EINVAL;
         }
 
+        if (ret)
+                return ret;
+
         return count;
 }
 
diff --git a/kernel/locking/qspinlock.c b/kernel/locking/qspinlock.c
index 38ece035039e..d880296245c5 100644
--- a/kernel/locking/qspinlock.c
+++ b/kernel/locking/qspinlock.c
@@ -379,6 +379,14 @@ queue:
         tail = encode_tail(smp_processor_id(), idx);
 
         node += idx;
+
+        /*
+         * Ensure that we increment the head node->count before initialising
+         * the actual node. If the compiler is kind enough to reorder these
+         * stores, then an IRQ could overwrite our assignments.
+         */
+        barrier();
+
         node->locked = 0;
         node->next = NULL;
         pv_init_node(node);
@@ -408,14 +416,15 @@ queue:
          */
         if (old & _Q_TAIL_MASK) {
                 prev = decode_tail(old);
+
                 /*
-                 * The above xchg_tail() is also a load of @lock which
-                 * generates, through decode_tail(), a pointer.  The address
-                 * dependency matches the RELEASE of xchg_tail() such that
-                 * the subsequent access to @prev happens after.
+                 * We must ensure that the stores to @node are observed before
+                 * the write to prev->next. The address dependency from
+                 * xchg_tail is not sufficient to ensure this because the read
+                 * component of xchg_tail is unordered with respect to the
+                 * initialisation of @node.
                  */
-
-                WRITE_ONCE(prev->next, node);
+                smp_store_release(&prev->next, node);
 
                 pv_wait_node(node, prev);
                 arch_mcs_spin_lock_contended(&node->locked);
diff --git a/kernel/memremap.c b/kernel/memremap.c
index 4849be5f9b3c..4dd4274cabe2 100644
--- a/kernel/memremap.c
+++ b/kernel/memremap.c
@@ -275,8 +275,15 @@ static unsigned long pfn_end(struct dev_pagemap *pgmap)
         return (res->start + resource_size(res)) >> PAGE_SHIFT;
 }
 
+static unsigned long pfn_next(unsigned long pfn)
+{
+        if (pfn % 1024 == 0)
+                cond_resched();
+        return pfn + 1;
+}
+
 #define for_each_device_pfn(pfn, map) \
-        for (pfn = pfn_first(map); pfn < pfn_end(map); pfn++)
+        for (pfn = pfn_first(map); pfn < pfn_end(map); pfn = pfn_next(pfn))
 
 static void devm_memremap_pages_release(void *data)
 {
@@ -337,10 +344,10 @@ void *devm_memremap_pages(struct device *dev, struct dev_pagemap *pgmap)
         resource_size_t align_start, align_size, align_end;
         struct vmem_altmap *altmap = pgmap->altmap_valid ?
                         &pgmap->altmap : NULL;
+        struct resource *res = &pgmap->res;
         unsigned long pfn, pgoff, order;
         pgprot_t pgprot = PAGE_KERNEL;
-        int error, nid, is_ram, i = 0;
-        struct resource *res = &pgmap->res;
+        int error, nid, is_ram;
 
         align_start = res->start & ~(SECTION_SIZE - 1);
         align_size = ALIGN(res->start + resource_size(res), SECTION_SIZE)
@@ -409,8 +416,6 @@ void *devm_memremap_pages(struct device *dev, struct dev_pagemap *pgmap)
                 list_del(&page->lru);
                 page->pgmap = pgmap;
                 percpu_ref_get(pgmap->ref);
-                if (!(++i % 1024))
-                        cond_resched();
         }
 
         devm_add_action(dev, devm_memremap_pages_release, pgmap);
diff --git a/kernel/printk/printk.c b/kernel/printk/printk.c
index fc1123583fa6..f274fbef821d 100644
--- a/kernel/printk/printk.c
+++ b/kernel/printk/printk.c
@@ -2397,7 +2397,7 @@ skip:
 
                 if (console_lock_spinning_disable_and_check()) {
                         printk_safe_exit_irqrestore(flags);
-                        return;
+                        goto out;
                 }
 
                 printk_safe_exit_irqrestore(flags);
@@ -2430,6 +2430,7 @@ skip:
         if (retry && console_trylock())
                 goto again;
 
+out:
         if (wake_klogd)
                 wake_up_klogd();
 }
diff --git a/kernel/relay.c b/kernel/relay.c
index c3029402f15c..c955b10c973c 100644
--- a/kernel/relay.c
+++ b/kernel/relay.c
@@ -163,7 +163,7 @@ static struct rchan_buf *relay_create_buf(struct rchan *chan)
 {
         struct rchan_buf *buf;
 
-        if (chan->n_subbufs > UINT_MAX / sizeof(size_t *))
+        if (chan->n_subbufs > KMALLOC_MAX_SIZE / sizeof(size_t *))
                 return NULL;
 
         buf = kzalloc(sizeof(struct rchan_buf), GFP_KERNEL);
diff --git a/kernel/sched/core.c b/kernel/sched/core.c
index bf724c1952ea..e7c535eee0a6 100644
--- a/kernel/sched/core.c
+++ b/kernel/sched/core.c
@@ -2601,19 +2601,31 @@ static inline void finish_task(struct task_struct *prev)
 #endif
 }
 
-static inline void finish_lock_switch(struct rq *rq)
+static inline void
+prepare_lock_switch(struct rq *rq, struct task_struct *next, struct rq_flags *rf)
 {
+        /*
+         * Since the runqueue lock will be released by the next
+         * task (which is an invalid locking op but in the case
+         * of the scheduler it's an obvious special-case), so we
+         * do an early lockdep release here:
+         */
+        rq_unpin_lock(rq, rf);
+        spin_release(&rq->lock.dep_map, 1, _THIS_IP_);
 #ifdef CONFIG_DEBUG_SPINLOCK
         /* this is a valid case when another task releases the spinlock */
-        rq->lock.owner = current;
+        rq->lock.owner = next;
 #endif
+}
+
+static inline void finish_lock_switch(struct rq *rq)
+{
         /*
          * If we are tracking spinlock dependencies then we have to
          * fix up the runqueue lock - which gets 'carried over' from
          * prev into current:
          */
         spin_acquire(&rq->lock.dep_map, 0, 0, _THIS_IP_);
-
         raw_spin_unlock_irq(&rq->lock);
 }
 
@@ -2844,14 +2856,7 @@ context_switch(struct rq *rq, struct task_struct *prev,
 
         rq->clock_update_flags &= ~(RQCF_ACT_SKIP|RQCF_REQ_SKIP);
 
-        /*
-         * Since the runqueue lock will be released by the next
-         * task (which is an invalid locking op but in the case
-         * of the scheduler it's an obvious special-case), so we
-         * do an early lockdep release here:
-         */
-        rq_unpin_lock(rq, rf);
-        spin_release(&rq->lock.dep_map, 1, _THIS_IP_);
+        prepare_lock_switch(rq, next, rf);
 
         /* Here we just switch the register state and the stack. */
         switch_to(prev, next, prev);
diff --git a/kernel/sched/cpufreq_schedutil.c b/kernel/sched/cpufreq_schedutil.c
index dd062a1c8cf0..7936f548e071 100644
--- a/kernel/sched/cpufreq_schedutil.c
+++ b/kernel/sched/cpufreq_schedutil.c
@@ -19,8 +19,6 @@
 
 #include "sched.h"
 
-#define SUGOV_KTHREAD_PRIORITY  50
-
 struct sugov_tunables {
         struct gov_attr_set attr_set;
         unsigned int rate_limit_us;
diff --git a/kernel/sched/deadline.c b/kernel/sched/deadline.c
index 9bb0e0c412ec..9df09782025c 100644
--- a/kernel/sched/deadline.c
+++ b/kernel/sched/deadline.c
@@ -1153,6 +1153,7 @@ static void update_curr_dl(struct rq *rq)
         struct sched_dl_entity *dl_se = &curr->dl;
         u64 delta_exec, scaled_delta_exec;
         int cpu = cpu_of(rq);
+        u64 now;
 
         if (!dl_task(curr) || !on_dl_rq(dl_se))
                 return;
@@ -1165,7 +1166,8 @@ static void update_curr_dl(struct rq *rq)
          * natural solution, but the full ramifications of this
          * approach need further study.
          */
-        delta_exec = rq_clock_task(rq) - curr->se.exec_start;
+        now = rq_clock_task(rq);
+        delta_exec = now - curr->se.exec_start;
         if (unlikely((s64)delta_exec <= 0)) {
                 if (unlikely(dl_se->dl_yielded))
                         goto throttle;
@@ -1178,7 +1180,7 @@ static void update_curr_dl(struct rq *rq)
         curr->se.sum_exec_runtime += delta_exec;
         account_group_exec_runtime(curr, delta_exec);
 
-        curr->se.exec_start = rq_clock_task(rq);
+        curr->se.exec_start = now;
         cgroup_account_cputime(curr, delta_exec);
 
         sched_rt_avg_update(rq, delta_exec);
diff --git a/kernel/sched/rt.c b/kernel/sched/rt.c
index 663b2355a3aa..aad49451584e 100644
--- a/kernel/sched/rt.c
+++ b/kernel/sched/rt.c
@@ -950,12 +950,13 @@ static void update_curr_rt(struct rq *rq)
 {
         struct task_struct *curr = rq->curr;
         struct sched_rt_entity *rt_se = &curr->rt;
-        u64 now = rq_clock_task(rq);
         u64 delta_exec;
+        u64 now;
 
         if (curr->sched_class != &rt_sched_class)
                 return;
 
+        now = rq_clock_task(rq);
         delta_exec = now - curr->se.exec_start;
         if (unlikely((s64)delta_exec <= 0))
                 return;
diff --git a/kernel/seccomp.c b/kernel/seccomp.c
index 940fa408a288..dc77548167ef 100644
--- a/kernel/seccomp.c
+++ b/kernel/seccomp.c
@@ -1076,14 +1076,16 @@ long seccomp_get_metadata(struct task_struct *task,
 
         size = min_t(unsigned long, size, sizeof(kmd));
 
-        if (copy_from_user(&kmd, data, size))
+        if (size < sizeof(kmd.filter_off))
+                return -EINVAL;
+
+        if (copy_from_user(&kmd.filter_off, data, sizeof(kmd.filter_off)))
                 return -EFAULT;
 
         filter = get_nth_filter(task, kmd.filter_off);
         if (IS_ERR(filter))
                 return PTR_ERR(filter);
 
-        memset(&kmd, 0, sizeof(kmd));
         if (filter->log)
                 kmd.flags |= SECCOMP_FILTER_FLAG_LOG;
 
diff --git a/kernel/time/timer.c b/kernel/time/timer.c
index 48150ab42de9..4a4fd567fb26 100644
--- a/kernel/time/timer.c
+++ b/kernel/time/timer.c
@@ -1894,6 +1894,12 @@ int timers_dead_cpu(unsigned int cpu)
                 raw_spin_lock_irq(&new_base->lock);
                 raw_spin_lock_nested(&old_base->lock, SINGLE_DEPTH_NESTING);
 
+                /*
+                 * The current CPUs base clock might be stale. Update it
+                 * before moving the timers over.
+                 */
+                forward_timer_base(new_base);
+
                 BUG_ON(old_base->running_timer);
 
                 for (i = 0; i < WHEEL_SIZE; i++)
diff --git a/kernel/trace/bpf_trace.c b/kernel/trace/bpf_trace.c
index fc2838ac8b78..c0a9e310d715 100644
--- a/kernel/trace/bpf_trace.c
+++ b/kernel/trace/bpf_trace.c
@@ -872,6 +872,8 @@ int perf_event_query_prog_array(struct perf_event *event, void __user *info)
                 return -EINVAL;
         if (copy_from_user(&query, uquery, sizeof(query)))
                 return -EFAULT;
+        if (query.ids_len > BPF_TRACE_MAX_PROGS)
+                return -E2BIG;
 
         mutex_lock(&bpf_event_mutex);
         ret = bpf_prog_array_copy_info(event->tp_event->prog_array,
diff --git a/kernel/user.c b/kernel/user.c
index 9a20acce460d..36288d840675 100644
--- a/kernel/user.c
+++ b/kernel/user.c
@@ -101,6 +101,7 @@ struct user_struct root_user = {
         .sigpending     = ATOMIC_INIT(0),
         .locked_shm     = 0,
         .uid            = GLOBAL_ROOT_UID,
+        .ratelimit      = RATELIMIT_STATE_INIT(root_user.ratelimit, 0, 0),
 };
 
 /*
@@ -191,6 +192,8 @@ struct user_struct *alloc_uid(kuid_t uid)
 
                 new->uid = uid;
                 atomic_set(&new->__count, 1);
+                ratelimit_state_init(&new->ratelimit, HZ, 100);
+                ratelimit_set_flags(&new->ratelimit, RATELIMIT_MSG_ON_RELEASE);
 
                 /*
                  * Before adding this, check whether we raced
diff --git a/kernel/workqueue.c b/kernel/workqueue.c
index 017044c26233..bb9a519cbf50 100644
--- a/kernel/workqueue.c
+++ b/kernel/workqueue.c
@@ -4180,6 +4180,22 @@ void workqueue_set_max_active(struct workqueue_struct *wq, int max_active)
 EXPORT_SYMBOL_GPL(workqueue_set_max_active);
 
 /**
+ * current_work - retrieve %current task's work struct
+ *
+ * Determine if %current task is a workqueue worker and what it's working on.
+ * Useful to find out the context that the %current task is running in.
+ *
+ * Return: work struct if %current task is a workqueue worker, %NULL otherwise.
+ */
+struct work_struct *current_work(void)
+{
+        struct worker *worker = current_wq_worker();
+
+        return worker ? worker->current_work : NULL;
+}
+EXPORT_SYMBOL(current_work);
+
+/**
  * current_is_workqueue_rescuer - is %current workqueue rescuer?
  *
  * Determine whether %current is a workqueue rescuer.  Can be used from
diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug
index 6088408ef26c..64155e310a9f 100644
--- a/lib/Kconfig.debug
+++ b/lib/Kconfig.debug
@@ -1642,6 +1642,7 @@ config DMA_API_DEBUG
 
 menuconfig RUNTIME_TESTING_MENU
         bool "Runtime Testing"
+        def_bool y
 
 if RUNTIME_TESTING_MENU
 
diff --git a/lib/dma-debug.c b/lib/dma-debug.c
index 1b34d210452c..7f5cdc1e6b29 100644
--- a/lib/dma-debug.c
+++ b/lib/dma-debug.c
@@ -1491,12 +1491,12 @@ void debug_dma_alloc_coherent(struct device *dev, size_t size,
         if (unlikely(virt == NULL))
                 return;
 
-        entry = dma_entry_alloc();
-        if (!entry)
+        /* handle vmalloc and linear addresses */
+        if (!is_vmalloc_addr(virt) && !virt_addr_valid(virt))
                 return;
 
-        /* handle vmalloc and linear addresses */
-        if (!is_vmalloc_addr(virt) && !virt_to_page(virt))
+        entry = dma_entry_alloc();
+        if (!entry)
                 return;
 
         entry->type      = dma_debug_coherent;
@@ -1528,7 +1528,7 @@ void debug_dma_free_coherent(struct device *dev, size_t size,
         };
 
         /* handle vmalloc and linear addresses */
-        if (!is_vmalloc_addr(virt) && !virt_to_page(virt))
+        if (!is_vmalloc_addr(virt) && !virt_addr_valid(virt))
                 return;
 
         if (is_vmalloc_addr(virt))
diff --git a/lib/dma-direct.c b/lib/dma-direct.c
index 40b1f92f2214..c9e8e21cb334 100644
--- a/lib/dma-direct.c
+++ b/lib/dma-direct.c
@@ -84,6 +84,10 @@ again:
         return page_address(page);
 }
 
+/*
+ * NOTE: this function must never look at the dma_addr argument, because we want
+ * to be able to use it as a helper for iommu implementations as well.
+ */
 void dma_direct_free(struct device *dev, size_t size, void *cpu_addr,
                 dma_addr_t dma_addr, unsigned long attrs)
 {
@@ -152,5 +156,6 @@ const struct dma_map_ops dma_direct_ops = {
         .map_sg                 = dma_direct_map_sg,
         .dma_supported          = dma_direct_supported,
         .mapping_error          = dma_direct_mapping_error,
+        .is_phys                = 1,
 };
 EXPORT_SYMBOL(dma_direct_ops);
diff --git a/lib/idr.c b/lib/idr.c
index c98d77fcf393..823b813f08f8 100644
--- a/lib/idr.c
+++ b/lib/idr.c
@@ -36,8 +36,8 @@ int idr_alloc_u32(struct idr *idr, void *ptr, u32 *nextid,
 {
         struct radix_tree_iter iter;
         void __rcu **slot;
-        int base = idr->idr_base;
-        int id = *nextid;
+        unsigned int base = idr->idr_base;
+        unsigned int id = *nextid;
 
         if (WARN_ON_ONCE(radix_tree_is_internal_node(ptr)))
                 return -EINVAL;
@@ -204,10 +204,11 @@ int idr_for_each(const struct idr *idr,
 
         radix_tree_for_each_slot(slot, &idr->idr_rt, &iter, 0) {
                 int ret;
+                unsigned long id = iter.index + base;
 
-                if (WARN_ON_ONCE(iter.index > INT_MAX))
+                if (WARN_ON_ONCE(id > INT_MAX))
                         break;
-                ret = fn(iter.index + base, rcu_dereference_raw(*slot), data);
+                ret = fn(id, rcu_dereference_raw(*slot), data);
                 if (ret)
                         return ret;
         }
@@ -230,8 +231,8 @@ void *idr_get_next(struct idr *idr, int *nextid)
 {
         struct radix_tree_iter iter;
         void __rcu **slot;
-        int base = idr->idr_base;
-        int id = *nextid;
+        unsigned long base = idr->idr_base;
+        unsigned long id = *nextid;
 
         id = (id < base) ? 0 : id - base;
         slot = radix_tree_iter_find(&idr->idr_rt, &iter, id);
@@ -431,7 +432,6 @@ int ida_get_new_above(struct ida *ida, int start, int *id)
                         bitmap = this_cpu_xchg(ida_bitmap, NULL);
                         if (!bitmap)
                                 return -EAGAIN;
-                        memset(bitmap, 0, sizeof(*bitmap));
                         bitmap->bitmap[0] = tmp >> RADIX_TREE_EXCEPTIONAL_SHIFT;
                         rcu_assign_pointer(*slot, bitmap);
                 }
@@ -464,7 +464,6 @@ int ida_get_new_above(struct ida *ida, int start, int *id)
                         bitmap = this_cpu_xchg(ida_bitmap, NULL);
                         if (!bitmap)
                                 return -EAGAIN;
-                        memset(bitmap, 0, sizeof(*bitmap));
                         __set_bit(bit, bitmap->bitmap);
                         radix_tree_iter_replace(root, &iter, slot, bitmap);
                 }
diff --git a/lib/radix-tree.c b/lib/radix-tree.c
index 0a7ae3288a24..8e00138d593f 100644
--- a/lib/radix-tree.c
+++ b/lib/radix-tree.c
@@ -2125,7 +2125,7 @@ int ida_pre_get(struct ida *ida, gfp_t gfp)
                 preempt_enable();
 
         if (!this_cpu_read(ida_bitmap)) {
-                struct ida_bitmap *bitmap = kmalloc(sizeof(*bitmap), gfp);
+                struct ida_bitmap *bitmap = kzalloc(sizeof(*bitmap), gfp);
                 if (!bitmap)
                         return 0;
                 if (this_cpu_cmpxchg(ida_bitmap, NULL, bitmap))
diff --git a/lib/vsprintf.c b/lib/vsprintf.c
index 77ee6ced11b1..d7a708f82559 100644
--- a/lib/vsprintf.c
+++ b/lib/vsprintf.c
@@ -1849,7 +1849,7 @@ char *pointer(const char *fmt, char *buf, char *end, void *ptr,
 {
         const int default_width = 2 * sizeof(void *);
 
-        if (!ptr && *fmt != 'K') {
+        if (!ptr && *fmt != 'K' && *fmt != 'x') {
                 /*
                  * Print (null) with the same width as a pointer so it makes
                  * tabular output look nice.
diff --git a/mm/memory-failure.c b/mm/memory-failure.c
index 4b80ccee4535..8291b75f42c8 100644
--- a/mm/memory-failure.c
+++ b/mm/memory-failure.c
@@ -1139,8 +1139,6 @@ int memory_failure(unsigned long pfn, int flags)
                 return 0;
         }
 
-        arch_unmap_kpfn(pfn);
-
         orig_head = hpage = compound_head(p);
         num_poisoned_pages_inc();
 
diff --git a/mm/memory.c b/mm/memory.c
index dd8de96f5547..5fcfc24904d1 100644
--- a/mm/memory.c
+++ b/mm/memory.c
@@ -80,7 +80,7 @@
 
 #include "internal.h"
 
-#ifdef LAST_CPUPID_NOT_IN_PAGE_FLAGS
+#if defined(LAST_CPUPID_NOT_IN_PAGE_FLAGS) && !defined(CONFIG_COMPILE_TEST)
 #warning Unfortunate NUMA and NUMA Balancing config, growing page-frame for last_cpupid.
 #endif
 
diff --git a/mm/mlock.c b/mm/mlock.c
index 79398200e423..74e5a6547c3d 100644
--- a/mm/mlock.c
+++ b/mm/mlock.c
@@ -64,6 +64,12 @@ void clear_page_mlock(struct page *page)
         mod_zone_page_state(page_zone(page), NR_MLOCK,
                             -hpage_nr_pages(page));
         count_vm_event(UNEVICTABLE_PGCLEARED);
+        /*
+         * The previous TestClearPageMlocked() corresponds to the smp_mb()
+         * in __pagevec_lru_add_fn().
+         *
+         * See __pagevec_lru_add_fn for more explanation.
+         */
         if (!isolate_lru_page(page)) {
                 putback_lru_page(page);
         } else {
diff --git a/mm/page_alloc.c b/mm/page_alloc.c
index 81e18ceef579..cb416723538f 100644
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
@@ -46,6 +46,7 @@
 #include <linux/stop_machine.h>
 #include <linux/sort.h>
 #include <linux/pfn.h>
+#include <xen/xen.h>
 #include <linux/backing-dev.h>
 #include <linux/fault-inject.h>
 #include <linux/page-isolation.h>
@@ -347,6 +348,9 @@ static inline bool update_defer_init(pg_data_t *pgdat,
         /* Always populate low zones for address-constrained allocations */
         if (zone_end < pgdat_end_pfn(pgdat))
                 return true;
+        /* Xen PV domains need page structures early */
+        if (xen_pv_domain())
+                return true;
         (*nr_initialised)++;
         if ((*nr_initialised > pgdat->static_init_pgcnt) &&
             (pfn & (PAGES_PER_SECTION - 1)) == 0) {
diff --git a/mm/swap.c b/mm/swap.c
index 567a7b96e41d..0f17330dd0e5 100644
--- a/mm/swap.c
+++ b/mm/swap.c
@@ -446,30 +446,6 @@ void lru_cache_add(struct page *page)
 }
 
 /**
- * add_page_to_unevictable_list - add a page to the unevictable list
- * @page:  the page to be added to the unevictable list
- *
- * Add page directly to its zone's unevictable list.  To avoid races with
- * tasks that might be making the page evictable, through eg. munlock,
- * munmap or exit, while it's not on the lru, we want to add the page
- * while it's locked or otherwise "invisible" to other tasks.  This is
- * difficult to do when using the pagevec cache, so bypass that.
- */
-void add_page_to_unevictable_list(struct page *page)
-{
-        struct pglist_data *pgdat = page_pgdat(page);
-        struct lruvec *lruvec;
-
-        spin_lock_irq(&pgdat->lru_lock);
-        lruvec = mem_cgroup_page_lruvec(page, pgdat);
-        ClearPageActive(page);
-        SetPageUnevictable(page);
-        SetPageLRU(page);
-        add_page_to_lru_list(page, lruvec, LRU_UNEVICTABLE);
-        spin_unlock_irq(&pgdat->lru_lock);
-}
-
-/**
  * lru_cache_add_active_or_unevictable
  * @page:  the page to be added to LRU
  * @vma:   vma in which page is mapped for determining reclaimability
@@ -484,13 +460,9 @@ void lru_cache_add_active_or_unevictable(struct page *page,
 {
         VM_BUG_ON_PAGE(PageLRU(page), page);
 
-        if (likely((vma->vm_flags & (VM_LOCKED | VM_SPECIAL)) != VM_LOCKED)) {
+        if (likely((vma->vm_flags & (VM_LOCKED | VM_SPECIAL)) != VM_LOCKED))
                 SetPageActive(page);
-                lru_cache_add(page);
-                return;
-        }
-
-        if (!TestSetPageMlocked(page)) {
+        else if (!TestSetPageMlocked(page)) {
                 /*
                  * We use the irq-unsafe __mod_zone_page_stat because this
                  * counter is not modified from interrupt context, and the pte
@@ -500,7 +472,7 @@ void lru_cache_add_active_or_unevictable(struct page *page,
                                     hpage_nr_pages(page));
                 count_vm_event(UNEVICTABLE_PGMLOCKED);
         }
-        add_page_to_unevictable_list(page);
+        lru_cache_add(page);
 }
 
 /*
@@ -886,15 +858,55 @@ void lru_add_page_tail(struct page *page, struct page *page_tail,
 static void __pagevec_lru_add_fn(struct page *page, struct lruvec *lruvec,
                                  void *arg)
 {
-        int file = page_is_file_cache(page);
-        int active = PageActive(page);
-        enum lru_list lru = page_lru(page);
+        enum lru_list lru;
+        int was_unevictable = TestClearPageUnevictable(page);
 
         VM_BUG_ON_PAGE(PageLRU(page), page);
 
         SetPageLRU(page);
+        /*
+         * Page becomes evictable in two ways:
+         * 1) Within LRU lock [munlock_vma_pages() and __munlock_pagevec()].
+         * 2) Before acquiring LRU lock to put the page to correct LRU and then
+         *   a) do PageLRU check with lock [check_move_unevictable_pages]
+         *   b) do PageLRU check before lock [clear_page_mlock]
+         *
+         * (1) & (2a) are ok as LRU lock will serialize them. For (2b), we need
+         * following strict ordering:
+         *
+         * #0: __pagevec_lru_add_fn             #1: clear_page_mlock
+         *
+         * SetPageLRU()                         TestClearPageMlocked()
+         * smp_mb() // explicit ordering        // above provides strict
+         *                                      // ordering
+         * PageMlocked()                        PageLRU()
+         *
+         *
+         * if '#1' does not observe setting of PG_lru by '#0' and fails
+         * isolation, the explicit barrier will make sure that page_evictable
+         * check will put the page in correct LRU. Without smp_mb(), SetPageLRU
+         * can be reordered after PageMlocked check and can make '#1' to fail
+         * the isolation of the page whose Mlocked bit is cleared (#0 is also
+         * looking at the same page) and the evictable page will be stranded
+         * in an unevictable LRU.
+         */
+        smp_mb();
+
+        if (page_evictable(page)) {
+                lru = page_lru(page);
+                update_page_reclaim_stat(lruvec, page_is_file_cache(page),
+                                         PageActive(page));
+                if (was_unevictable)
+                        count_vm_event(UNEVICTABLE_PGRESCUED);
+        } else {
+                lru = LRU_UNEVICTABLE;
+                ClearPageActive(page);
+                SetPageUnevictable(page);
+                if (!was_unevictable)
+                        count_vm_event(UNEVICTABLE_PGCULLED);
+        }
+
         add_page_to_lru_list(page, lruvec, lru);
-        update_page_reclaim_stat(lruvec, file, active);
         trace_mm_lru_insertion(page, lru);
 }
 
@@ -913,7 +925,7 @@ EXPORT_SYMBOL(__pagevec_lru_add);
  * @pvec:       Where the resulting entries are placed
  * @mapping:    The address_space to search
  * @start:      The starting entry index
- * @nr_pages:   The maximum number of pages
+ * @nr_entries: The maximum number of pages
  * @indices:    The cache indices corresponding to the entries in @pvec
  *
  * pagevec_lookup_entries() will search for and return a group of up
diff --git a/mm/vmalloc.c b/mm/vmalloc.c
index 673942094328..ebff729cc956 100644
--- a/mm/vmalloc.c
+++ b/mm/vmalloc.c
@@ -1943,11 +1943,15 @@ void *vmalloc_exec(unsigned long size)
 }
 
 #if defined(CONFIG_64BIT) && defined(CONFIG_ZONE_DMA32)
-#define GFP_VMALLOC32 GFP_DMA32 | GFP_KERNEL
+#define GFP_VMALLOC32 (GFP_DMA32 | GFP_KERNEL)
 #elif defined(CONFIG_64BIT) && defined(CONFIG_ZONE_DMA)
-#define GFP_VMALLOC32 GFP_DMA | GFP_KERNEL
+#define GFP_VMALLOC32 (GFP_DMA | GFP_KERNEL)
 #else
-#define GFP_VMALLOC32 GFP_KERNEL
+/*
+ * 64b systems should always have either DMA or DMA32 zones. For others
+ * GFP_DMA32 should do the right thing and use the normal zone.
+ */
+#define GFP_VMALLOC32 GFP_DMA32 | GFP_KERNEL
 #endif
 
 /**
diff --git a/mm/vmscan.c b/mm/vmscan.c
index 444749669187..bee53495a829 100644
--- a/mm/vmscan.c
+++ b/mm/vmscan.c
@@ -769,64 +769,7 @@ int remove_mapping(struct address_space *mapping, struct page *page)
  */
 void putback_lru_page(struct page *page)
 {
-        bool is_unevictable;
-        int was_unevictable = PageUnevictable(page);
-
-        VM_BUG_ON_PAGE(PageLRU(page), page);
-
-redo:
-        ClearPageUnevictable(page);
-
-        if (page_evictable(page)) {
-                /*
-                 * For evictable pages, we can use the cache.
-                 * In event of a race, worst case is we end up with an
-                 * unevictable page on [in]active list.
-                 * We know how to handle that.
-                 */
-                is_unevictable = false;
-                lru_cache_add(page);
-        } else {
-                /*
-                 * Put unevictable pages directly on zone's unevictable
-                 * list.
-                 */
-                is_unevictable = true;
-                add_page_to_unevictable_list(page);
-                /*
-                 * When racing with an mlock or AS_UNEVICTABLE clearing
-                 * (page is unlocked) make sure that if the other thread
-                 * does not observe our setting of PG_lru and fails
-                 * isolation/check_move_unevictable_pages,
-                 * we see PG_mlocked/AS_UNEVICTABLE cleared below and move
-                 * the page back to the evictable list.
-                 *
-                 * The other side is TestClearPageMlocked() or shmem_lock().
-                 */
-                smp_mb();
-        }
-
-        /*
-         * page's status can change while we move it among lru. If an evictable
-         * page is on unevictable list, it never be freed. To avoid that,
-         * check after we added it to the list, again.
-         */
-        if (is_unevictable && page_evictable(page)) {
-                if (!isolate_lru_page(page)) {
-                        put_page(page);
-                        goto redo;
-                }
-                /* This means someone else dropped this page from LRU
-                 * So, it will be freed or putback to LRU again. There is
-                 * nothing to do here.
-                 */
-        }
-
-        if (was_unevictable && !is_unevictable)
-                count_vm_event(UNEVICTABLE_PGRESCUED);
-        else if (!was_unevictable && is_unevictable)
-                count_vm_event(UNEVICTABLE_PGCULLED);
-
+        lru_cache_add(page);
         put_page(page);         /* drop ref from isolate */
 }
 
diff --git a/mm/zpool.c b/mm/zpool.c
index f8cb83e7699b..01a771e304fa 100644
--- a/mm/zpool.c
+++ b/mm/zpool.c
@@ -360,7 +360,7 @@ u64 zpool_get_total_size(struct zpool *zpool)
 
 /**
  * zpool_evictable() - Test if zpool is potentially evictable
- * @pool        The zpool to test
+ * @zpool:      The zpool to test
  *
  * Zpool is only potentially evictable when it's created with struct
  * zpool_ops.evict and its driver implements struct zpool_driver.shrink.
diff --git a/mm/zswap.c b/mm/zswap.c
index c004aa4fd3f4..61a5c41972db 100644
--- a/mm/zswap.c
+++ b/mm/zswap.c
@@ -1007,6 +1007,12 @@ static int zswap_frontswap_store(unsigned type, pgoff_t offset,
         u8 *src, *dst;
         struct zswap_header zhdr = { .swpentry = swp_entry(type, offset) };
 
+        /* THP isn't supported */
+        if (PageTransHuge(page)) {
+                ret = -EINVAL;
+                goto reject;
+        }
+
         if (!zswap_enabled || !tree) {
                 ret = -ENODEV;
                 goto reject;
diff --git a/net/9p/trans_virtio.c b/net/9p/trans_virtio.c
index f3a4efcf1456..3aa5a93ad107 100644
--- a/net/9p/trans_virtio.c
+++ b/net/9p/trans_virtio.c
@@ -160,7 +160,8 @@ static void req_done(struct virtqueue *vq)
                 spin_unlock_irqrestore(&chan->lock, flags);
                 /* Wakeup if anyone waiting for VirtIO ring space. */
                 wake_up(chan->vc_wq);
-                p9_client_cb(chan->client, req, REQ_STATUS_RCVD);
+                if (len)
+                        p9_client_cb(chan->client, req, REQ_STATUS_RCVD);
         }
 }
 
diff --git a/net/bridge/br_sysfs_if.c b/net/bridge/br_sysfs_if.c
index 0254c35b2bf0..126a8ea73c96 100644
--- a/net/bridge/br_sysfs_if.c
+++ b/net/bridge/br_sysfs_if.c
@@ -255,6 +255,9 @@ static ssize_t brport_show(struct kobject *kobj,
         struct brport_attribute *brport_attr = to_brport_attr(attr);
         struct net_bridge_port *p = to_brport(kobj);
 
+        if (!brport_attr->show)
+                return -EINVAL;
+
         return brport_attr->show(p, buf);
 }
 
diff --git a/net/bridge/netfilter/ebt_among.c b/net/bridge/netfilter/ebt_among.c
index 279527f8b1fe..ce7152a12bd8 100644
--- a/net/bridge/netfilter/ebt_among.c
+++ b/net/bridge/netfilter/ebt_among.c
@@ -187,17 +187,17 @@ static int ebt_among_mt_check(const struct xt_mtchk_param *par)
         expected_length += ebt_mac_wormhash_size(wh_src);
 
         if (em->match_size != EBT_ALIGN(expected_length)) {
-                pr_info("wrong size: %d against expected %d, rounded to %zd\n",
-                        em->match_size, expected_length,
-                        EBT_ALIGN(expected_length));
+                pr_err_ratelimited("wrong size: %d against expected %d, rounded to %zd\n",
+                                   em->match_size, expected_length,
+                                   EBT_ALIGN(expected_length));
                 return -EINVAL;
         }
         if (wh_dst && (err = ebt_mac_wormhash_check_integrity(wh_dst))) {
-                pr_info("dst integrity fail: %x\n", -err);
+                pr_err_ratelimited("dst integrity fail: %x\n", -err);
                 return -EINVAL;
         }
         if (wh_src && (err = ebt_mac_wormhash_check_integrity(wh_src))) {
-                pr_info("src integrity fail: %x\n", -err);
+                pr_err_ratelimited("src integrity fail: %x\n", -err);
                 return -EINVAL;
         }
         return 0;
diff --git a/net/bridge/netfilter/ebt_limit.c b/net/bridge/netfilter/ebt_limit.c
index 61a9f1be1263..165b9d678cf1 100644
--- a/net/bridge/netfilter/ebt_limit.c
+++ b/net/bridge/netfilter/ebt_limit.c
@@ -72,8 +72,8 @@ static int ebt_limit_mt_check(const struct xt_mtchk_param *par)
         /* Check for overflow. */
         if (info->burst == 0 ||
             user2credits(info->avg * info->burst) < user2credits(info->avg)) {
-                pr_info("overflow, try lower: %u/%u\n",
-                        info->avg, info->burst);
+                pr_info_ratelimited("overflow, try lower: %u/%u\n",
+                                    info->avg, info->burst);
                 return -EINVAL;
         }
 
diff --git a/net/ceph/ceph_common.c b/net/ceph/ceph_common.c
index 1e492ef2a33d..4d4c82229e9e 100644
--- a/net/ceph/ceph_common.c
+++ b/net/ceph/ceph_common.c
@@ -418,6 +418,7 @@ ceph_parse_options(char *options, const char *dev_name,
                                 opt->flags |= CEPH_OPT_FSID;
                         break;
                 case Opt_name:
+                        kfree(opt->name);
                         opt->name = kstrndup(argstr[0].from,
                                               argstr[0].to-argstr[0].from,
                                               GFP_KERNEL);
@@ -427,6 +428,9 @@ ceph_parse_options(char *options, const char *dev_name,
                         }
                         break;
                 case Opt_secret:
+                        ceph_crypto_key_destroy(opt->key);
+                        kfree(opt->key);
+
                         opt->key = kzalloc(sizeof(*opt->key), GFP_KERNEL);
                         if (!opt->key) {
                                 err = -ENOMEM;
@@ -437,6 +441,9 @@ ceph_parse_options(char *options, const char *dev_name,
                                 goto out;
                         break;
                 case Opt_key:
+                        ceph_crypto_key_destroy(opt->key);
+                        kfree(opt->key);
+
                         opt->key = kzalloc(sizeof(*opt->key), GFP_KERNEL);
                         if (!opt->key) {
                                 err = -ENOMEM;
diff --git a/net/core/dev.c b/net/core/dev.c
index dda9d7b9a840..d4362befe7e2 100644
--- a/net/core/dev.c
+++ b/net/core/dev.c
@@ -2382,8 +2382,11 @@ EXPORT_SYMBOL(netdev_set_num_tc);
  */
 int netif_set_real_num_tx_queues(struct net_device *dev, unsigned int txq)
 {
+        bool disabling;
         int rc;
 
+        disabling = txq < dev->real_num_tx_queues;
+
         if (txq < 1 || txq > dev->num_tx_queues)
                 return -EINVAL;
 
@@ -2399,15 +2402,19 @@ int netif_set_real_num_tx_queues(struct net_device *dev, unsigned int txq)
                 if (dev->num_tc)
                         netif_setup_tc(dev, txq);
 
-                if (txq < dev->real_num_tx_queues) {
+                dev->real_num_tx_queues = txq;
+
+                if (disabling) {
+                        synchronize_net();
                         qdisc_reset_all_tx_gt(dev, txq);
 #ifdef CONFIG_XPS
                         netif_reset_xps_queues_gt(dev, txq);
 #endif
                 }
+        } else {
+                dev->real_num_tx_queues = txq;
         }
 
-        dev->real_num_tx_queues = txq;
         return 0;
 }
 EXPORT_SYMBOL(netif_set_real_num_tx_queues);
diff --git a/net/core/filter.c b/net/core/filter.c
index 08ab4c65a998..0c121adbdbaa 100644
--- a/net/core/filter.c
+++ b/net/core/filter.c
@@ -3381,17 +3381,13 @@ BPF_CALL_2(bpf_sock_ops_cb_flags_set, struct bpf_sock_ops_kern *, bpf_sock,
         struct sock *sk = bpf_sock->sk;
         int val = argval & BPF_SOCK_OPS_ALL_CB_FLAGS;
 
-        if (!sk_fullsock(sk))
+        if (!IS_ENABLED(CONFIG_INET) || !sk_fullsock(sk))
                 return -EINVAL;
 
-#ifdef CONFIG_INET
         if (val)
                 tcp_sk(sk)->bpf_sock_ops_cb_flags = val;
 
         return argval & (~BPF_SOCK_OPS_ALL_CB_FLAGS);
-#else
-        return -EINVAL;
-#endif
 }
 
 static const struct bpf_func_proto bpf_sock_ops_cb_flags_set_proto = {
diff --git a/net/core/gen_estimator.c b/net/core/gen_estimator.c
index 0a3f88f08727..98fd12721221 100644
--- a/net/core/gen_estimator.c
+++ b/net/core/gen_estimator.c
@@ -66,6 +66,7 @@ struct net_rate_estimator {
 static void est_fetch_counters(struct net_rate_estimator *e,
                                struct gnet_stats_basic_packed *b)
 {
+        memset(b, 0, sizeof(*b));
         if (e->stats_lock)
                 spin_lock(e->stats_lock);
 
diff --git a/net/decnet/af_decnet.c b/net/decnet/af_decnet.c
index 91dd09f79808..791aff68af88 100644
--- a/net/decnet/af_decnet.c
+++ b/net/decnet/af_decnet.c
@@ -1338,6 +1338,12 @@ static int dn_setsockopt(struct socket *sock, int level, int optname, char __use
         lock_sock(sk);
         err = __dn_setsockopt(sock, level, optname, optval, optlen, 0);
         release_sock(sk);
+#ifdef CONFIG_NETFILTER
+        /* we need to exclude all possible ENOPROTOOPTs except default case */
+        if (err == -ENOPROTOOPT && optname != DSO_LINKINFO &&
+            optname != DSO_STREAM && optname != DSO_SEQPACKET)
+                err = nf_setsockopt(sk, PF_DECnet, optname, optval, optlen);
+#endif
 
         return err;
 }
@@ -1445,15 +1451,6 @@ static int __dn_setsockopt(struct socket *sock, int level,int optname, char __us
                 dn_nsp_send_disc(sk, 0x38, 0, sk->sk_allocation);
                 break;
 
-        default:
-#ifdef CONFIG_NETFILTER
-                return nf_setsockopt(sk, PF_DECnet, optname, optval, optlen);
-#endif
-        case DSO_LINKINFO:
-        case DSO_STREAM:
-        case DSO_SEQPACKET:
-                return -ENOPROTOOPT;
-
         case DSO_MAXWINDOW:
                 if (optlen != sizeof(unsigned long))
                         return -EINVAL;
@@ -1501,6 +1498,12 @@ static int __dn_setsockopt(struct socket *sock, int level,int optname, char __us
                         return -EINVAL;
                 scp->info_loc = u.info;
                 break;
+
+        case DSO_LINKINFO:
+        case DSO_STREAM:
+        case DSO_SEQPACKET:
+        default:
+                return -ENOPROTOOPT;
         }
 
         return 0;
@@ -1514,6 +1517,20 @@ static int dn_getsockopt(struct socket *sock, int level, int optname, char __use
         lock_sock(sk);
         err = __dn_getsockopt(sock, level, optname, optval, optlen, 0);
         release_sock(sk);
+#ifdef CONFIG_NETFILTER
+        if (err == -ENOPROTOOPT && optname != DSO_STREAM &&
+            optname != DSO_SEQPACKET && optname != DSO_CONACCEPT &&
+            optname != DSO_CONREJECT) {
+                int len;
+
+                if (get_user(len, optlen))
+                        return -EFAULT;
+
+                err = nf_getsockopt(sk, PF_DECnet, optname, optval, &len);
+                if (err >= 0)
+                        err = put_user(len, optlen);
+        }
+#endif
 
         return err;
 }
@@ -1579,26 +1596,6 @@ static int __dn_getsockopt(struct socket *sock, int level,int optname, char __us
                 r_data = &link;
                 break;
 
-        default:
-#ifdef CONFIG_NETFILTER
-        {
-                int ret, len;
-
-                if (get_user(len, optlen))
-                        return -EFAULT;
-
-                ret = nf_getsockopt(sk, PF_DECnet, optname, optval, &len);
-                if (ret >= 0)
-                        ret = put_user(len, optlen);
-                return ret;
-        }
-#endif
-        case DSO_STREAM:
-        case DSO_SEQPACKET:
-        case DSO_CONACCEPT:
-        case DSO_CONREJECT:
-                return -ENOPROTOOPT;
-
         case DSO_MAXWINDOW:
                 if (r_len > sizeof(unsigned long))
                         r_len = sizeof(unsigned long);
@@ -1630,6 +1627,13 @@ static int __dn_getsockopt(struct socket *sock, int level,int optname, char __us
                         r_len = sizeof(unsigned char);
                 r_data = &scp->info_rem;
                 break;
+
+        case DSO_STREAM:
+        case DSO_SEQPACKET:
+        case DSO_CONACCEPT:
+        case DSO_CONREJECT:
+        default:
+                return -ENOPROTOOPT;
         }
 
         if (r_data) {
diff --git a/net/ipv4/fib_semantics.c b/net/ipv4/fib_semantics.c
index c586597da20d..7d36a950d961 100644
--- a/net/ipv4/fib_semantics.c
+++ b/net/ipv4/fib_semantics.c
@@ -646,6 +646,11 @@ int fib_nh_match(struct fib_config *cfg, struct fib_info *fi,
                                             fi->fib_nh, cfg, extack))
                                 return 1;
                 }
+#ifdef CONFIG_IP_ROUTE_CLASSID
+                if (cfg->fc_flow &&
+                    cfg->fc_flow != fi->fib_nh->nh_tclassid)
+                        return 1;
+#endif
                 if ((!cfg->fc_oif || cfg->fc_oif == fi->fib_nh->nh_oif) &&
                     (!cfg->fc_gw  || cfg->fc_gw == fi->fib_nh->nh_gw))
                         return 0;
diff --git a/net/ipv4/ip_sockglue.c b/net/ipv4/ip_sockglue.c
index 008be04ac1cc..9c41a0cef1a5 100644
--- a/net/ipv4/ip_sockglue.c
+++ b/net/ipv4/ip_sockglue.c
@@ -1567,10 +1567,7 @@ int ip_getsockopt(struct sock *sk, int level,
                 if (get_user(len, optlen))
                         return -EFAULT;
 
-                lock_sock(sk);
-                err = nf_getsockopt(sk, PF_INET, optname, optval,
-                                &len);
-                release_sock(sk);
+                err = nf_getsockopt(sk, PF_INET, optname, optval, &len);
                 if (err >= 0)
                         err = put_user(len, optlen);
                 return err;
@@ -1602,9 +1599,7 @@ int compat_ip_getsockopt(struct sock *sk, int level, int optname,
                 if (get_user(len, optlen))
                         return -EFAULT;
 
-                lock_sock(sk);
                 err = compat_nf_getsockopt(sk, PF_INET, optname, optval, &len);
-                release_sock(sk);
                 if (err >= 0)
                         err = put_user(len, optlen);
                 return err;
diff --git a/net/ipv4/netfilter/arp_tables.c b/net/ipv4/netfilter/arp_tables.c
index 4ffe302f9b82..e3e420f3ba7b 100644
--- a/net/ipv4/netfilter/arp_tables.c
+++ b/net/ipv4/netfilter/arp_tables.c
@@ -252,6 +252,10 @@ unsigned int arpt_do_table(struct sk_buff *skb,
                         }
                         if (table_base + v
                             != arpt_next_entry(e)) {
+                                if (unlikely(stackidx >= private->stacksize)) {
+                                        verdict = NF_DROP;
+                                        break;
+                                }
                                 jumpstack[stackidx++] = e;
                         }
 
diff --git a/net/ipv4/netfilter/ip_tables.c b/net/ipv4/netfilter/ip_tables.c
index 9a71f3149507..e38395a8dcf2 100644
--- a/net/ipv4/netfilter/ip_tables.c
+++ b/net/ipv4/netfilter/ip_tables.c
@@ -330,8 +330,13 @@ ipt_do_table(struct sk_buff *skb,
                                 continue;
                         }
                         if (table_base + v != ipt_next_entry(e) &&
-                            !(e->ip.flags & IPT_F_GOTO))
+                            !(e->ip.flags & IPT_F_GOTO)) {
+                                if (unlikely(stackidx >= private->stacksize)) {
+                                        verdict = NF_DROP;
+                                        break;
+                                }
                                 jumpstack[stackidx++] = e;
+                        }
 
                         e = get_entry(table_base, v);
                         continue;
diff --git a/net/ipv4/netfilter/ipt_CLUSTERIP.c b/net/ipv4/netfilter/ipt_CLUSTERIP.c
index 3a84a60f6b39..4b02ab39ebc5 100644
--- a/net/ipv4/netfilter/ipt_CLUSTERIP.c
+++ b/net/ipv4/netfilter/ipt_CLUSTERIP.c
@@ -107,12 +107,6 @@ clusterip_config_entry_put(struct net *net, struct clusterip_config *c)
 
         local_bh_disable();
         if (refcount_dec_and_lock(&c->entries, &cn->lock)) {
-                list_del_rcu(&c->list);
-                spin_unlock(&cn->lock);
-                local_bh_enable();
-
-                unregister_netdevice_notifier(&c->notifier);
-
                 /* In case anyone still accesses the file, the open/close
                  * functions are also incrementing the refcount on their own,
                  * so it's safe to remove the entry even if it's in use. */
@@ -120,6 +114,12 @@ clusterip_config_entry_put(struct net *net, struct clusterip_config *c)
                 if (cn->procdir)
                         proc_remove(c->pde);
 #endif
+                list_del_rcu(&c->list);
+                spin_unlock(&cn->lock);
+                local_bh_enable();
+
+                unregister_netdevice_notifier(&c->notifier);
+
                 return;
         }
         local_bh_enable();
@@ -154,8 +154,12 @@ clusterip_config_find_get(struct net *net, __be32 clusterip, int entry)
 #endif
                 if (unlikely(!refcount_inc_not_zero(&c->refcount)))
                         c = NULL;
-                else if (entry)
-                        refcount_inc(&c->entries);
+                else if (entry) {
+                        if (unlikely(!refcount_inc_not_zero(&c->entries))) {
+                                clusterip_config_put(c);
+                                c = NULL;
+                        }
+                }
         }
         rcu_read_unlock_bh();
 
diff --git a/net/ipv4/netfilter/ipt_ECN.c b/net/ipv4/netfilter/ipt_ECN.c
index 270765236f5e..aaaf9a81fbc9 100644
--- a/net/ipv4/netfilter/ipt_ECN.c
+++ b/net/ipv4/netfilter/ipt_ECN.c
@@ -98,17 +98,15 @@ static int ecn_tg_check(const struct xt_tgchk_param *par)
         const struct ipt_ECN_info *einfo = par->targinfo;
         const struct ipt_entry *e = par->entryinfo;
 
-        if (einfo->operation & IPT_ECN_OP_MASK) {
-                pr_info("unsupported ECN operation %x\n", einfo->operation);
+        if (einfo->operation & IPT_ECN_OP_MASK)
                 return -EINVAL;
-        }
-        if (einfo->ip_ect & ~IPT_ECN_IP_MASK) {
-                pr_info("new ECT codepoint %x out of mask\n", einfo->ip_ect);
+
+        if (einfo->ip_ect & ~IPT_ECN_IP_MASK)
                 return -EINVAL;
-        }
+
         if ((einfo->operation & (IPT_ECN_OP_SET_ECE|IPT_ECN_OP_SET_CWR)) &&
             (e->ip.proto != IPPROTO_TCP || (e->ip.invflags & XT_INV_PROTO))) {
-                pr_info("cannot use TCP operations on a non-tcp rule\n");
+                pr_info_ratelimited("cannot use operation on non-tcp rule\n");
                 return -EINVAL;
         }
         return 0;
diff --git a/net/ipv4/netfilter/ipt_REJECT.c b/net/ipv4/netfilter/ipt_REJECT.c
index 8bd0d7b26632..e8bed3390e58 100644
--- a/net/ipv4/netfilter/ipt_REJECT.c
+++ b/net/ipv4/netfilter/ipt_REJECT.c
@@ -74,13 +74,13 @@ static int reject_tg_check(const struct xt_tgchk_param *par)
         const struct ipt_entry *e = par->entryinfo;
 
         if (rejinfo->with == IPT_ICMP_ECHOREPLY) {
-                pr_info("ECHOREPLY no longer supported.\n");
+                pr_info_ratelimited("ECHOREPLY no longer supported.\n");
                 return -EINVAL;
         } else if (rejinfo->with == IPT_TCP_RESET) {
                 /* Must specify that it's a TCP packet */
                 if (e->ip.proto != IPPROTO_TCP ||
                     (e->ip.invflags & XT_INV_PROTO)) {
-                        pr_info("TCP_RESET invalid for non-tcp\n");
+                        pr_info_ratelimited("TCP_RESET invalid for non-tcp\n");
                         return -EINVAL;
                 }
         }
diff --git a/net/ipv4/netfilter/ipt_rpfilter.c b/net/ipv4/netfilter/ipt_rpfilter.c
index 37fb9552e858..fd01f13c896a 100644
--- a/net/ipv4/netfilter/ipt_rpfilter.c
+++ b/net/ipv4/netfilter/ipt_rpfilter.c
@@ -105,14 +105,14 @@ static int rpfilter_check(const struct xt_mtchk_param *par)
         const struct xt_rpfilter_info *info = par->matchinfo;
         unsigned int options = ~XT_RPFILTER_OPTION_MASK;
         if (info->flags & options) {
-                pr_info("unknown options encountered");
+                pr_info_ratelimited("unknown options\n");
                 return -EINVAL;
         }
 
         if (strcmp(par->table, "mangle") != 0 &&
             strcmp(par->table, "raw") != 0) {
-                pr_info("match only valid in the \'raw\' "
-                        "or \'mangle\' tables, not \'%s\'.\n", par->table);
+                pr_info_ratelimited("only valid in \'raw\' or \'mangle\' table, not \'%s\'\n",
+                                    par->table);
                 return -EINVAL;
         }
 
diff --git a/net/ipv4/route.c b/net/ipv4/route.c
index 49cc1c1df1ba..a4f44d815a61 100644
--- a/net/ipv4/route.c
+++ b/net/ipv4/route.c
@@ -1826,6 +1826,8 @@ int fib_multipath_hash(const struct fib_info *fi, const struct flowi4 *fl4,
                                 return skb_get_hash_raw(skb) >> 1;
                         memset(&hash_keys, 0, sizeof(hash_keys));
                         skb_flow_dissect_flow_keys(skb, &keys, flag);
+
+                        hash_keys.control.addr_type = FLOW_DISSECTOR_KEY_IPV4_ADDRS;
                         hash_keys.addrs.v4addrs.src = keys.addrs.v4addrs.src;
                         hash_keys.addrs.v4addrs.dst = keys.addrs.v4addrs.dst;
                         hash_keys.ports.src = keys.ports.src;
diff --git a/net/ipv4/tcp_output.c b/net/ipv4/tcp_output.c
index e9f985e42405..6818042cd8a9 100644
--- a/net/ipv4/tcp_output.c
+++ b/net/ipv4/tcp_output.c
@@ -1730,7 +1730,7 @@ u32 tcp_tso_autosize(const struct sock *sk, unsigned int mss_now,
          */
         segs = max_t(u32, bytes / mss_now, min_tso_segs);
 
-        return min_t(u32, segs, sk->sk_gso_max_segs);
+        return segs;
 }
 EXPORT_SYMBOL(tcp_tso_autosize);
 
@@ -1742,9 +1742,10 @@ static u32 tcp_tso_segs(struct sock *sk, unsigned int mss_now)
         const struct tcp_congestion_ops *ca_ops = inet_csk(sk)->icsk_ca_ops;
         u32 tso_segs = ca_ops->tso_segs_goal ? ca_ops->tso_segs_goal(sk) : 0;
 
-        return tso_segs ? :
-                tcp_tso_autosize(sk, mss_now,
-                                 sock_net(sk)->ipv4.sysctl_tcp_min_tso_segs);
+        if (!tso_segs)
+                tso_segs = tcp_tso_autosize(sk, mss_now,
+                                sock_net(sk)->ipv4.sysctl_tcp_min_tso_segs);
+        return min_t(u32, tso_segs, sk->sk_gso_max_segs);
 }
 
 /* Returns the portion of skb which can be sent right away */
@@ -2027,6 +2028,24 @@ static inline void tcp_mtu_check_reprobe(struct sock *sk)
         }
 }
 
+static bool tcp_can_coalesce_send_queue_head(struct sock *sk, int len)
+{
+        struct sk_buff *skb, *next;
+
+        skb = tcp_send_head(sk);
+        tcp_for_write_queue_from_safe(skb, next, sk) {
+                if (len <= skb->len)
+                        break;
+
+                if (unlikely(TCP_SKB_CB(skb)->eor))
+                        return false;
+
+                len -= skb->len;
+        }
+
+        return true;
+}
+
 /* Create a new MTU probe if we are ready.
  * MTU probe is regularly attempting to increase the path MTU by
  * deliberately sending larger packets.  This discovers routing
@@ -2099,6 +2118,9 @@ static int tcp_mtu_probe(struct sock *sk)
                         return 0;
         }
 
+        if (!tcp_can_coalesce_send_queue_head(sk, probe_size))
+                return -1;
+
         /* We're allowed to probe.  Build it now. */
         nskb = sk_stream_alloc_skb(sk, probe_size, GFP_ATOMIC, false);
         if (!nskb)
@@ -2134,6 +2156,10 @@ static int tcp_mtu_probe(struct sock *sk)
                         /* We've eaten all the data from this skb.
                          * Throw it away. */
                         TCP_SKB_CB(nskb)->tcp_flags |= TCP_SKB_CB(skb)->tcp_flags;
+                        /* If this is the last SKB we copy and eor is set
+                         * we need to propagate it to the new skb.
+                         */
+                        TCP_SKB_CB(nskb)->eor = TCP_SKB_CB(skb)->eor;
                         tcp_unlink_write_queue(skb, sk);
                         sk_wmem_free_skb(sk, skb);
                 } else {
diff --git a/net/ipv4/udp.c b/net/ipv4/udp.c
index bfaefe560b5c..e5ef7c38c934 100644
--- a/net/ipv4/udp.c
+++ b/net/ipv4/udp.c
@@ -2024,6 +2024,11 @@ static inline int udp4_csum_init(struct sk_buff *skb, struct udphdr *uh,
                 err = udplite_checksum_init(skb, uh);
                 if (err)
                         return err;
+
+                if (UDP_SKB_CB(skb)->partial_cov) {
+                        skb->csum = inet_compute_pseudo(skb, proto);
+                        return 0;
+                }
         }
 
         /* Note, we are only interested in != 0 or == 0, thus the
diff --git a/net/ipv6/ip6_checksum.c b/net/ipv6/ip6_checksum.c
index ec43d18b5ff9..547515e8450a 100644
--- a/net/ipv6/ip6_checksum.c
+++ b/net/ipv6/ip6_checksum.c
@@ -73,6 +73,11 @@ int udp6_csum_init(struct sk_buff *skb, struct udphdr *uh, int proto)
                 err = udplite_checksum_init(skb, uh);
                 if (err)
                         return err;
+
+                if (UDP_SKB_CB(skb)->partial_cov) {
+                        skb->csum = ip6_compute_pseudo(skb, proto);
+                        return 0;
+                }
         }
 
         /* To support RFC 6936 (allow zero checksum in UDP/IPV6 for tunnels)
diff --git a/net/ipv6/ipv6_sockglue.c b/net/ipv6/ipv6_sockglue.c
index d78d41fc4b1a..24535169663d 100644
--- a/net/ipv6/ipv6_sockglue.c
+++ b/net/ipv6/ipv6_sockglue.c
@@ -1367,10 +1367,7 @@ int ipv6_getsockopt(struct sock *sk, int level, int optname,
                 if (get_user(len, optlen))
                         return -EFAULT;
 
-                lock_sock(sk);
-                err = nf_getsockopt(sk, PF_INET6, optname, optval,
-                                &len);
-                release_sock(sk);
+                err = nf_getsockopt(sk, PF_INET6, optname, optval, &len);
                 if (err >= 0)
                         err = put_user(len, optlen);
         }
@@ -1409,10 +1406,7 @@ int compat_ipv6_getsockopt(struct sock *sk, int level, int optname,
                 if (get_user(len, optlen))
                         return -EFAULT;
 
-                lock_sock(sk);
-                err = compat_nf_getsockopt(sk, PF_INET6,
-                                           optname, optval, &len);
-                release_sock(sk);
+                err = compat_nf_getsockopt(sk, PF_INET6, optname, optval, &len);
                 if (err >= 0)
                         err = put_user(len, optlen);
         }
diff --git a/net/ipv6/netfilter/ip6_tables.c b/net/ipv6/netfilter/ip6_tables.c
index af4c917e0836..62358b93bbac 100644
--- a/net/ipv6/netfilter/ip6_tables.c
+++ b/net/ipv6/netfilter/ip6_tables.c
@@ -352,6 +352,10 @@ ip6t_do_table(struct sk_buff *skb,
                         }
                         if (table_base + v != ip6t_next_entry(e) &&
                             !(e->ipv6.flags & IP6T_F_GOTO)) {
+                                if (unlikely(stackidx >= private->stacksize)) {
+                                        verdict = NF_DROP;
+                                        break;
+                                }
                                 jumpstack[stackidx++] = e;
                         }
 
diff --git a/net/ipv6/netfilter/ip6t_REJECT.c b/net/ipv6/netfilter/ip6t_REJECT.c
index fa51a205918d..38dea8ff680f 100644
--- a/net/ipv6/netfilter/ip6t_REJECT.c
+++ b/net/ipv6/netfilter/ip6t_REJECT.c
@@ -85,14 +85,14 @@ static int reject_tg6_check(const struct xt_tgchk_param *par)
         const struct ip6t_entry *e = par->entryinfo;
 
         if (rejinfo->with == IP6T_ICMP6_ECHOREPLY) {
-                pr_info("ECHOREPLY is not supported.\n");
+                pr_info_ratelimited("ECHOREPLY is not supported\n");
                 return -EINVAL;
         } else if (rejinfo->with == IP6T_TCP_RESET) {
                 /* Must specify that it's a TCP packet */
                 if (!(e->ipv6.flags & IP6T_F_PROTO) ||
                     e->ipv6.proto != IPPROTO_TCP ||
                     (e->ipv6.invflags & XT_INV_PROTO)) {
-                        pr_info("TCP_RESET illegal for non-tcp\n");
+                        pr_info_ratelimited("TCP_RESET illegal for non-tcp\n");
                         return -EINVAL;
                 }
         }
diff --git a/net/ipv6/netfilter/ip6t_rpfilter.c b/net/ipv6/netfilter/ip6t_rpfilter.c
index b12e61b7b16c..94deb69bbbda 100644
--- a/net/ipv6/netfilter/ip6t_rpfilter.c
+++ b/net/ipv6/netfilter/ip6t_rpfilter.c
@@ -103,14 +103,14 @@ static int rpfilter_check(const struct xt_mtchk_param *par)
         unsigned int options = ~XT_RPFILTER_OPTION_MASK;
 
         if (info->flags & options) {
-                pr_info("unknown options encountered");
+                pr_info_ratelimited("unknown options\n");
                 return -EINVAL;
         }
 
         if (strcmp(par->table, "mangle") != 0 &&
             strcmp(par->table, "raw") != 0) {
-                pr_info("match only valid in the \'raw\' "
-                        "or \'mangle\' tables, not \'%s\'.\n", par->table);
+                pr_info_ratelimited("only valid in \'raw\' or \'mangle\' table, not \'%s\'\n",
+                                    par->table);
                 return -EINVAL;
         }
 
diff --git a/net/ipv6/netfilter/ip6t_srh.c b/net/ipv6/netfilter/ip6t_srh.c
index 9642164107ce..33719d5560c8 100644
--- a/net/ipv6/netfilter/ip6t_srh.c
+++ b/net/ipv6/netfilter/ip6t_srh.c
@@ -122,12 +122,14 @@ static int srh_mt6_check(const struct xt_mtchk_param *par)
         const struct ip6t_srh *srhinfo = par->matchinfo;
 
         if (srhinfo->mt_flags & ~IP6T_SRH_MASK) {
-                pr_err("unknown srh match flags  %X\n", srhinfo->mt_flags);
+                pr_info_ratelimited("unknown srh match flags  %X\n",
+                                    srhinfo->mt_flags);
                 return -EINVAL;
         }
 
         if (srhinfo->mt_invflags & ~IP6T_SRH_INV_MASK) {
-                pr_err("unknown srh invflags %X\n", srhinfo->mt_invflags);
+                pr_info_ratelimited("unknown srh invflags %X\n",
+                                    srhinfo->mt_invflags);
                 return -EINVAL;
         }
 
diff --git a/net/ipv6/sit.c b/net/ipv6/sit.c
index 3873d3877135..3a1775a62973 100644
--- a/net/ipv6/sit.c
+++ b/net/ipv6/sit.c
@@ -182,7 +182,7 @@ static void ipip6_tunnel_clone_6rd(struct net_device *dev, struct sit_net *sitn)
 #ifdef CONFIG_IPV6_SIT_6RD
         struct ip_tunnel *t = netdev_priv(dev);
 
-        if (t->dev == sitn->fb_tunnel_dev) {
+        if (dev == sitn->fb_tunnel_dev) {
                 ipv6_addr_set(&t->ip6rd.prefix, htonl(0x20020000), 0, 0, 0);
                 t->ip6rd.relay_prefix = 0;
                 t->ip6rd.prefixlen = 16;
diff --git a/net/mac80211/agg-rx.c b/net/mac80211/agg-rx.c
index a8b1616cec41..1f3188d03840 100644
--- a/net/mac80211/agg-rx.c
+++ b/net/mac80211/agg-rx.c
@@ -8,6 +8,7 @@
  * Copyright 2007, Michael Wu <flamingice@sourmilk.net>
  * Copyright 2007-2010, Intel Corporation
  * Copyright(c) 2015-2017 Intel Deutschland GmbH
+ * Copyright (C) 2018        Intel Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -304,9 +305,6 @@ void ___ieee80211_start_rx_ba_session(struct sta_info *sta,
                          * driver so reject the timeout update.
                          */
                         status = WLAN_STATUS_REQUEST_DECLINED;
-                        ieee80211_send_addba_resp(sta->sdata, sta->sta.addr,
-                                                  tid, dialog_token, status,
-                                                  1, buf_size, timeout);
                         goto end;
                 }
 
diff --git a/net/mac80211/cfg.c b/net/mac80211/cfg.c
index 46028e12e216..f4195a0f0279 100644
--- a/net/mac80211/cfg.c
+++ b/net/mac80211/cfg.c
@@ -2892,7 +2892,7 @@ cfg80211_beacon_dup(struct cfg80211_beacon_data *beacon)
         }
         if (beacon->probe_resp_len) {
                 new_beacon->probe_resp_len = beacon->probe_resp_len;
-                beacon->probe_resp = pos;
+                new_beacon->probe_resp = pos;
                 memcpy(pos, beacon->probe_resp, beacon->probe_resp_len);
                 pos += beacon->probe_resp_len;
         }
diff --git a/net/mac80211/ieee80211_i.h b/net/mac80211/ieee80211_i.h
index 26900025de2f..ae9c33cd8ada 100644
--- a/net/mac80211/ieee80211_i.h
+++ b/net/mac80211/ieee80211_i.h
@@ -1467,7 +1467,7 @@ struct ieee802_11_elems {
         const struct ieee80211_timeout_interval_ie *timeout_int;
         const u8 *opmode_notif;
         const struct ieee80211_sec_chan_offs_ie *sec_chan_offs;
-        const struct ieee80211_mesh_chansw_params_ie *mesh_chansw_params_ie;
+        struct ieee80211_mesh_chansw_params_ie *mesh_chansw_params_ie;
         const struct ieee80211_bss_max_idle_period_ie *max_idle_period_ie;
 
         /* length of them, respectively */
diff --git a/net/mac80211/mesh.c b/net/mac80211/mesh.c
index 73ac607beb5d..6a381cbe1e33 100644
--- a/net/mac80211/mesh.c
+++ b/net/mac80211/mesh.c
@@ -1255,13 +1255,12 @@ int ieee80211_mesh_csa_beacon(struct ieee80211_sub_if_data *sdata,
 }
 
 static int mesh_fwd_csa_frame(struct ieee80211_sub_if_data *sdata,
-                               struct ieee80211_mgmt *mgmt, size_t len)
+                               struct ieee80211_mgmt *mgmt, size_t len,
+                               struct ieee802_11_elems *elems)
 {
         struct ieee80211_mgmt *mgmt_fwd;
         struct sk_buff *skb;
         struct ieee80211_local *local = sdata->local;
-        u8 *pos = mgmt->u.action.u.chan_switch.variable;
-        size_t offset_ttl;
 
         skb = dev_alloc_skb(local->tx_headroom + len);
         if (!skb)
@@ -1269,13 +1268,9 @@ static int mesh_fwd_csa_frame(struct ieee80211_sub_if_data *sdata,
         skb_reserve(skb, local->tx_headroom);
         mgmt_fwd = skb_put(skb, len);
 
-        /* offset_ttl is based on whether the secondary channel
-         * offset is available or not. Subtract 1 from the mesh TTL
-         * and disable the initiator flag before forwarding.
-         */
-        offset_ttl = (len < 42) ? 7 : 10;
-        *(pos + offset_ttl) -= 1;
-        *(pos + offset_ttl + 1) &= ~WLAN_EID_CHAN_SWITCH_PARAM_INITIATOR;
+        elems->mesh_chansw_params_ie->mesh_ttl--;
+        elems->mesh_chansw_params_ie->mesh_flags &=
+                ~WLAN_EID_CHAN_SWITCH_PARAM_INITIATOR;
 
         memcpy(mgmt_fwd, mgmt, len);
         eth_broadcast_addr(mgmt_fwd->da);
@@ -1323,7 +1318,7 @@ static void mesh_rx_csa_frame(struct ieee80211_sub_if_data *sdata,
 
         /* forward or re-broadcast the CSA frame */
         if (fwd_csa) {
-                if (mesh_fwd_csa_frame(sdata, mgmt, len) < 0)
+                if (mesh_fwd_csa_frame(sdata, mgmt, len, &elems) < 0)
                         mcsa_dbg(sdata, "Failed to forward the CSA frame");
         }
 }
diff --git a/net/mac80211/spectmgmt.c b/net/mac80211/spectmgmt.c
index ee0181778a42..029334835747 100644
--- a/net/mac80211/spectmgmt.c
+++ b/net/mac80211/spectmgmt.c
@@ -8,6 +8,7 @@
  * Copyright 2007, Michael Wu <flamingice@sourmilk.net>
  * Copyright 2007-2008, Intel Corporation
  * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
+ * Copyright (C) 2018        Intel Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -27,7 +28,7 @@ int ieee80211_parse_ch_switch_ie(struct ieee80211_sub_if_data *sdata,
                                  u32 sta_flags, u8 *bssid,
                                  struct ieee80211_csa_ie *csa_ie)
 {
-        enum nl80211_band new_band;
+        enum nl80211_band new_band = current_band;
         int new_freq;
         u8 new_chan_no;
         struct ieee80211_channel *new_chan;
@@ -55,15 +56,13 @@ int ieee80211_parse_ch_switch_ie(struct ieee80211_sub_if_data *sdata,
                                 elems->ext_chansw_ie->new_operating_class,
                                 &new_band)) {
                         sdata_info(sdata,
-                                   "cannot understand ECSA IE operating class %d, disconnecting\n",
+                                   "cannot understand ECSA IE operating class, %d, ignoring\n",
                                    elems->ext_chansw_ie->new_operating_class);
-                        return -EINVAL;
                 }
                 new_chan_no = elems->ext_chansw_ie->new_ch_num;
                 csa_ie->count = elems->ext_chansw_ie->count;
                 csa_ie->mode = elems->ext_chansw_ie->mode;
         } else if (elems->ch_switch_ie) {
-                new_band = current_band;
                 new_chan_no = elems->ch_switch_ie->new_ch_num;
                 csa_ie->count = elems->ch_switch_ie->count;
                 csa_ie->mode = elems->ch_switch_ie->mode;
diff --git a/net/mac80211/sta_info.c b/net/mac80211/sta_info.c
index 0c5627f8a104..af0b608ee8ed 100644
--- a/net/mac80211/sta_info.c
+++ b/net/mac80211/sta_info.c
@@ -314,7 +314,7 @@ struct sta_info *sta_info_alloc(struct ieee80211_sub_if_data *sdata,
 
         if (ieee80211_hw_check(hw, USES_RSS)) {
                 sta->pcpu_rx_stats =
-                        alloc_percpu(struct ieee80211_sta_rx_stats);
+                        alloc_percpu_gfp(struct ieee80211_sta_rx_stats, gfp);
                 if (!sta->pcpu_rx_stats)
                         goto free;
         }
@@ -433,6 +433,7 @@ free_txq:
         if (sta->sta.txq[0])
                 kfree(to_txq_info(sta->sta.txq[0]));
 free:
+        free_percpu(sta->pcpu_rx_stats);
 #ifdef CONFIG_MAC80211_MESH
         kfree(sta->mesh);
 #endif
diff --git a/net/netfilter/nf_nat_proto_common.c b/net/netfilter/nf_nat_proto_common.c
index fbce552a796e..7d7466dbf663 100644
--- a/net/netfilter/nf_nat_proto_common.c
+++ b/net/netfilter/nf_nat_proto_common.c
@@ -41,7 +41,7 @@ void nf_nat_l4proto_unique_tuple(const struct nf_nat_l3proto *l3proto,
                                  const struct nf_conn *ct,
                                  u16 *rover)
 {
-        unsigned int range_size, min, i;
+        unsigned int range_size, min, max, i;
         __be16 *portptr;
         u_int16_t off;
 
@@ -71,7 +71,10 @@ void nf_nat_l4proto_unique_tuple(const struct nf_nat_l3proto *l3proto,
                 }
         } else {
                 min = ntohs(range->min_proto.all);
-                range_size = ntohs(range->max_proto.all) - min + 1;
+                max = ntohs(range->max_proto.all);
+                if (unlikely(max < min))
+                        swap(max, min);
+                range_size = max - min + 1;
         }
 
         if (range->flags & NF_NAT_RANGE_PROTO_RANDOM) {
diff --git a/net/netfilter/x_tables.c b/net/netfilter/x_tables.c
index 2f685ee1f9c8..fa1655aff8d3 100644
--- a/net/netfilter/x_tables.c
+++ b/net/netfilter/x_tables.c
@@ -434,36 +434,35 @@ int xt_check_match(struct xt_mtchk_param *par,
                  * ebt_among is exempt from centralized matchsize checking
                  * because it uses a dynamic-size data set.
                  */
-                pr_err("%s_tables: %s.%u match: invalid size "
-                       "%u (kernel) != (user) %u\n",
-                       xt_prefix[par->family], par->match->name,
-                       par->match->revision,
-                       XT_ALIGN(par->match->matchsize), size);
+                pr_err_ratelimited("%s_tables: %s.%u match: invalid size %u (kernel) != (user) %u\n",
+                                   xt_prefix[par->family], par->match->name,
+                                   par->match->revision,
+                                   XT_ALIGN(par->match->matchsize), size);
                 return -EINVAL;
         }
         if (par->match->table != NULL &&
             strcmp(par->match->table, par->table) != 0) {
-                pr_err("%s_tables: %s match: only valid in %s table, not %s\n",
-                       xt_prefix[par->family], par->match->name,
-                       par->match->table, par->table);
+                pr_info_ratelimited("%s_tables: %s match: only valid in %s table, not %s\n",
+                                    xt_prefix[par->family], par->match->name,
+                                    par->match->table, par->table);
                 return -EINVAL;
         }
         if (par->match->hooks && (par->hook_mask & ~par->match->hooks) != 0) {
                 char used[64], allow[64];
 
-                pr_err("%s_tables: %s match: used from hooks %s, but only "
-                       "valid from %s\n",
-                       xt_prefix[par->family], par->match->name,
-                       textify_hooks(used, sizeof(used), par->hook_mask,
-                                     par->family),
-                       textify_hooks(allow, sizeof(allow), par->match->hooks,
-                                     par->family));
+                pr_info_ratelimited("%s_tables: %s match: used from hooks %s, but only valid from %s\n",
+                                    xt_prefix[par->family], par->match->name,
+                                    textify_hooks(used, sizeof(used),
+                                                  par->hook_mask, par->family),
+                                    textify_hooks(allow, sizeof(allow),
+                                                  par->match->hooks,
+                                                  par->family));
                 return -EINVAL;
         }
         if (par->match->proto && (par->match->proto != proto || inv_proto)) {
-                pr_err("%s_tables: %s match: only valid for protocol %u\n",
-                       xt_prefix[par->family], par->match->name,
-                       par->match->proto);
+                pr_info_ratelimited("%s_tables: %s match: only valid for protocol %u\n",
+                                    xt_prefix[par->family], par->match->name,
+                                    par->match->proto);
                 return -EINVAL;
         }
         if (par->match->checkentry != NULL) {
@@ -814,36 +813,35 @@ int xt_check_target(struct xt_tgchk_param *par,
         int ret;
 
         if (XT_ALIGN(par->target->targetsize) != size) {
-                pr_err("%s_tables: %s.%u target: invalid size "
-                       "%u (kernel) != (user) %u\n",
-                       xt_prefix[par->family], par->target->name,
-                       par->target->revision,
-                       XT_ALIGN(par->target->targetsize), size);
+                pr_err_ratelimited("%s_tables: %s.%u target: invalid size %u (kernel) != (user) %u\n",
+                                   xt_prefix[par->family], par->target->name,
+                                   par->target->revision,
+                                   XT_ALIGN(par->target->targetsize), size);
                 return -EINVAL;
         }
         if (par->target->table != NULL &&
             strcmp(par->target->table, par->table) != 0) {
-                pr_err("%s_tables: %s target: only valid in %s table, not %s\n",
-                       xt_prefix[par->family], par->target->name,
-                       par->target->table, par->table);
+                pr_info_ratelimited("%s_tables: %s target: only valid in %s table, not %s\n",
+                                    xt_prefix[par->family], par->target->name,
+                                    par->target->table, par->table);
                 return -EINVAL;
         }
         if (par->target->hooks && (par->hook_mask & ~par->target->hooks) != 0) {
                 char used[64], allow[64];
 
-                pr_err("%s_tables: %s target: used from hooks %s, but only "
-                       "usable from %s\n",
-                       xt_prefix[par->family], par->target->name,
-                       textify_hooks(used, sizeof(used), par->hook_mask,
-                                     par->family),
-                       textify_hooks(allow, sizeof(allow), par->target->hooks,
-                                     par->family));
+                pr_info_ratelimited("%s_tables: %s target: used from hooks %s, but only usable from %s\n",
+                                    xt_prefix[par->family], par->target->name,
+                                    textify_hooks(used, sizeof(used),
+                                                  par->hook_mask, par->family),
+                                    textify_hooks(allow, sizeof(allow),
+                                                  par->target->hooks,
+                                                  par->family));
                 return -EINVAL;
         }
         if (par->target->proto && (par->target->proto != proto || inv_proto)) {
-                pr_err("%s_tables: %s target: only valid for protocol %u\n",
-                       xt_prefix[par->family], par->target->name,
-                       par->target->proto);
+                pr_info_ratelimited("%s_tables: %s target: only valid for protocol %u\n",
+                                    xt_prefix[par->family], par->target->name,
+                                    par->target->proto);
                 return -EINVAL;
         }
         if (par->target->checkentry != NULL) {
@@ -1004,10 +1002,6 @@ struct xt_table_info *xt_alloc_table_info(unsigned int size)
         if (sz < sizeof(*info))
                 return NULL;
 
-        /* Pedantry: prevent them from hitting BUG() in vmalloc.c --RR */
-        if ((size >> PAGE_SHIFT) + 2 > totalram_pages)
-                return NULL;
-
         /* __GFP_NORETRY is not fully supported by kvmalloc but it should
          * work reasonably well if sz is too large and bail out rather
          * than shoot all processes down before realizing there is nothing
diff --git a/net/netfilter/xt_AUDIT.c b/net/netfilter/xt_AUDIT.c
index c502419d6306..f368ee6741db 100644
--- a/net/netfilter/xt_AUDIT.c
+++ b/net/netfilter/xt_AUDIT.c
@@ -120,8 +120,8 @@ static int audit_tg_check(const struct xt_tgchk_param *par)
         const struct xt_audit_info *info = par->targinfo;
 
         if (info->type > XT_AUDIT_TYPE_MAX) {
-                pr_info("Audit type out of range (valid range: 0..%hhu)\n",
-                        XT_AUDIT_TYPE_MAX);
+                pr_info_ratelimited("Audit type out of range (valid range: 0..%hhu)\n",
+                                    XT_AUDIT_TYPE_MAX);
                 return -ERANGE;
         }
 
diff --git a/net/netfilter/xt_CHECKSUM.c b/net/netfilter/xt_CHECKSUM.c
index 0f642ef8cd26..9f4151ec3e06 100644
--- a/net/netfilter/xt_CHECKSUM.c
+++ b/net/netfilter/xt_CHECKSUM.c
@@ -36,13 +36,13 @@ static int checksum_tg_check(const struct xt_tgchk_param *par)
         const struct xt_CHECKSUM_info *einfo = par->targinfo;
 
         if (einfo->operation & ~XT_CHECKSUM_OP_FILL) {
-                pr_info("unsupported CHECKSUM operation %x\n", einfo->operation);
+                pr_info_ratelimited("unsupported CHECKSUM operation %x\n",
+                                    einfo->operation);
                 return -EINVAL;
         }
-        if (!einfo->operation) {
-                pr_info("no CHECKSUM operation enabled\n");
+        if (!einfo->operation)
                 return -EINVAL;
-        }
+
         return 0;
 }
 
diff --git a/net/netfilter/xt_CONNSECMARK.c b/net/netfilter/xt_CONNSECMARK.c
index da56c06a443c..f3f1caac949b 100644
--- a/net/netfilter/xt_CONNSECMARK.c
+++ b/net/netfilter/xt_CONNSECMARK.c
@@ -91,8 +91,8 @@ static int connsecmark_tg_check(const struct xt_tgchk_param *par)
 
         if (strcmp(par->table, "mangle") != 0 &&
             strcmp(par->table, "security") != 0) {
-                pr_info("target only valid in the \'mangle\' "
-                        "or \'security\' tables, not \'%s\'.\n", par->table);
+                pr_info_ratelimited("only valid in \'mangle\' or \'security\' table, not \'%s\'\n",
+                                    par->table);
                 return -EINVAL;
         }
 
@@ -102,14 +102,14 @@ static int connsecmark_tg_check(const struct xt_tgchk_param *par)
                 break;
 
         default:
-                pr_info("invalid mode: %hu\n", info->mode);
+                pr_info_ratelimited("invalid mode: %hu\n", info->mode);
                 return -EINVAL;
         }
 
         ret = nf_ct_netns_get(par->net, par->family);
         if (ret < 0)
-                pr_info("cannot load conntrack support for proto=%u\n",
-                        par->family);
+                pr_info_ratelimited("cannot load conntrack support for proto=%u\n",
+                                    par->family);
         return ret;
 }
 
diff --git a/net/netfilter/xt_CT.c b/net/netfilter/xt_CT.c
index 5a152e2acfd5..8790190c6feb 100644
--- a/net/netfilter/xt_CT.c
+++ b/net/netfilter/xt_CT.c
@@ -82,15 +82,14 @@ xt_ct_set_helper(struct nf_conn *ct, const char *helper_name,
 
         proto = xt_ct_find_proto(par);
         if (!proto) {
-                pr_info("You must specify a L4 protocol, and not use "
-                        "inversions on it.\n");
+                pr_info_ratelimited("You must specify a L4 protocol and not use inversions on it\n");
                 return -ENOENT;
         }
 
         helper = nf_conntrack_helper_try_module_get(helper_name, par->family,
                                                     proto);
         if (helper == NULL) {
-                pr_info("No such helper \"%s\"\n", helper_name);
+                pr_info_ratelimited("No such helper \"%s\"\n", helper_name);
                 return -ENOENT;
         }
 
@@ -124,6 +123,7 @@ xt_ct_set_timeout(struct nf_conn *ct, const struct xt_tgchk_param *par,
         const struct nf_conntrack_l4proto *l4proto;
         struct ctnl_timeout *timeout;
         struct nf_conn_timeout *timeout_ext;
+        const char *errmsg = NULL;
         int ret = 0;
         u8 proto;
 
@@ -131,29 +131,29 @@ xt_ct_set_timeout(struct nf_conn *ct, const struct xt_tgchk_param *par,
         timeout_find_get = rcu_dereference(nf_ct_timeout_find_get_hook);
         if (timeout_find_get == NULL) {
                 ret = -ENOENT;
-                pr_info("Timeout policy base is empty\n");
+                errmsg = "Timeout policy base is empty";
                 goto out;
         }
 
         proto = xt_ct_find_proto(par);
         if (!proto) {
                 ret = -EINVAL;
-                pr_info("You must specify a L4 protocol, and not use "
-                        "inversions on it.\n");
+                errmsg = "You must specify a L4 protocol and not use inversions on it";
                 goto out;
         }
 
         timeout = timeout_find_get(par->net, timeout_name);
         if (timeout == NULL) {
                 ret = -ENOENT;
-                pr_info("No such timeout policy \"%s\"\n", timeout_name);
+                pr_info_ratelimited("No such timeout policy \"%s\"\n",
+                                    timeout_name);
                 goto out;
         }
 
         if (timeout->l3num != par->family) {
                 ret = -EINVAL;
-                pr_info("Timeout policy `%s' can only be used by L3 protocol "
-                        "number %d\n", timeout_name, timeout->l3num);
+                pr_info_ratelimited("Timeout policy `%s' can only be used by L%d protocol number %d\n",
+                                    timeout_name, 3, timeout->l3num);
                 goto err_put_timeout;
         }
         /* Make sure the timeout policy matches any existing protocol tracker,
@@ -162,9 +162,8 @@ xt_ct_set_timeout(struct nf_conn *ct, const struct xt_tgchk_param *par,
         l4proto = __nf_ct_l4proto_find(par->family, proto);
         if (timeout->l4proto->l4proto != l4proto->l4proto) {
                 ret = -EINVAL;
-                pr_info("Timeout policy `%s' can only be used by L4 protocol "
-                        "number %d\n",
-                        timeout_name, timeout->l4proto->l4proto);
+                pr_info_ratelimited("Timeout policy `%s' can only be used by L%d protocol number %d\n",
+                                    timeout_name, 4, timeout->l4proto->l4proto);
                 goto err_put_timeout;
         }
         timeout_ext = nf_ct_timeout_ext_add(ct, timeout, GFP_ATOMIC);
@@ -180,6 +179,8 @@ err_put_timeout:
         __xt_ct_tg_timeout_put(timeout);
 out:
         rcu_read_unlock();
+        if (errmsg)
+                pr_info_ratelimited("%s\n", errmsg);
         return ret;
 #else
         return -EOPNOTSUPP;
diff --git a/net/netfilter/xt_DSCP.c b/net/netfilter/xt_DSCP.c
index 3f83d38c4e5b..098ed851b7a7 100644
--- a/net/netfilter/xt_DSCP.c
+++ b/net/netfilter/xt_DSCP.c
@@ -66,10 +66,8 @@ static int dscp_tg_check(const struct xt_tgchk_param *par)
 {
         const struct xt_DSCP_info *info = par->targinfo;
 
-        if (info->dscp > XT_DSCP_MAX) {
-                pr_info("dscp %x out of range\n", info->dscp);
+        if (info->dscp > XT_DSCP_MAX)
                 return -EDOM;
-        }
         return 0;
 }
 
diff --git a/net/netfilter/xt_HL.c b/net/netfilter/xt_HL.c
index 1535e87ed9bd..4653b071bed4 100644
--- a/net/netfilter/xt_HL.c
+++ b/net/netfilter/xt_HL.c
@@ -105,10 +105,8 @@ static int ttl_tg_check(const struct xt_tgchk_param *par)
 {
         const struct ipt_TTL_info *info = par->targinfo;
 
-        if (info->mode > IPT_TTL_MAXMODE) {
-                pr_info("TTL: invalid or unknown mode %u\n", info->mode);
+        if (info->mode > IPT_TTL_MAXMODE)
                 return -EINVAL;
-        }
         if (info->mode != IPT_TTL_SET && info->ttl == 0)
                 return -EINVAL;
         return 0;
@@ -118,15 +116,10 @@ static int hl_tg6_check(const struct xt_tgchk_param *par)
 {
         const struct ip6t_HL_info *info = par->targinfo;
 
-        if (info->mode > IP6T_HL_MAXMODE) {
-                pr_info("invalid or unknown mode %u\n", info->mode);
+        if (info->mode > IP6T_HL_MAXMODE)
                 return -EINVAL;
-        }
-        if (info->mode != IP6T_HL_SET && info->hop_limit == 0) {
-                pr_info("increment/decrement does not "
-                        "make sense with value 0\n");
+        if (info->mode != IP6T_HL_SET && info->hop_limit == 0)
                 return -EINVAL;
-        }
         return 0;
 }
 
diff --git a/net/netfilter/xt_HMARK.c b/net/netfilter/xt_HMARK.c
index 60e6dbe12460..9c75f419cd80 100644
--- a/net/netfilter/xt_HMARK.c
+++ b/net/netfilter/xt_HMARK.c
@@ -9,6 +9,8 @@
  * the Free Software Foundation.
  */
 
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #include <linux/module.h>
 #include <linux/skbuff.h>
 #include <linux/icmp.h>
@@ -312,29 +314,30 @@ hmark_tg_v4(struct sk_buff *skb, const struct xt_action_param *par)
 static int hmark_tg_check(const struct xt_tgchk_param *par)
 {
         const struct xt_hmark_info *info = par->targinfo;
+        const char *errmsg = "proto mask must be zero with L3 mode";
 
-        if (!info->hmodulus) {
-                pr_info("xt_HMARK: hash modulus can't be zero\n");
+        if (!info->hmodulus)
                 return -EINVAL;
-        }
+
         if (info->proto_mask &&
-            (info->flags & XT_HMARK_FLAG(XT_HMARK_METHOD_L3))) {
-                pr_info("xt_HMARK: proto mask must be zero with L3 mode\n");
-                return -EINVAL;
-        }
+            (info->flags & XT_HMARK_FLAG(XT_HMARK_METHOD_L3)))
+                goto err;
+
         if (info->flags & XT_HMARK_FLAG(XT_HMARK_SPI_MASK) &&
             (info->flags & (XT_HMARK_FLAG(XT_HMARK_SPORT_MASK) |
-                             XT_HMARK_FLAG(XT_HMARK_DPORT_MASK)))) {
-                pr_info("xt_HMARK: spi-mask and port-mask can't be combined\n");
+                             XT_HMARK_FLAG(XT_HMARK_DPORT_MASK))))
                 return -EINVAL;
-        }
+
         if (info->flags & XT_HMARK_FLAG(XT_HMARK_SPI) &&
             (info->flags & (XT_HMARK_FLAG(XT_HMARK_SPORT) |
                              XT_HMARK_FLAG(XT_HMARK_DPORT)))) {
-                pr_info("xt_HMARK: spi-set and port-set can't be combined\n");
-                return -EINVAL;
+                errmsg = "spi-set and port-set can't be combined";
+                goto err;
         }
         return 0;
+err:
+        pr_info_ratelimited("%s\n", errmsg);
+        return -EINVAL;
 }
 
 static struct xt_target hmark_tg_reg[] __read_mostly = {
diff --git a/net/netfilter/xt_IDLETIMER.c b/net/netfilter/xt_IDLETIMER.c
index 6c2482b709b1..1ac6600bfafd 100644
--- a/net/netfilter/xt_IDLETIMER.c
+++ b/net/netfilter/xt_IDLETIMER.c
@@ -146,11 +146,11 @@ static int idletimer_tg_create(struct idletimer_tg_info *info)
         timer_setup(&info->timer->timer, idletimer_tg_expired, 0);
         info->timer->refcnt = 1;
 
+        INIT_WORK(&info->timer->work, idletimer_tg_work);
+
         mod_timer(&info->timer->timer,
                   msecs_to_jiffies(info->timeout * 1000) + jiffies);
 
-        INIT_WORK(&info->timer->work, idletimer_tg_work);
-
         return 0;
 
 out_free_attr:
@@ -191,7 +191,10 @@ static int idletimer_tg_checkentry(const struct xt_tgchk_param *par)
                 pr_debug("timeout value is zero\n");
                 return -EINVAL;
         }
-
+        if (info->timeout >= INT_MAX / 1000) {
+                pr_debug("timeout value is too big\n");
+                return -EINVAL;
+        }
         if (info->label[0] == '\0' ||
             strnlen(info->label,
                     MAX_IDLETIMER_LABEL_SIZE) == MAX_IDLETIMER_LABEL_SIZE) {
diff --git a/net/netfilter/xt_LED.c b/net/netfilter/xt_LED.c
index 1dcad893df78..19846445504d 100644
--- a/net/netfilter/xt_LED.c
+++ b/net/netfilter/xt_LED.c
@@ -111,10 +111,8 @@ static int led_tg_check(const struct xt_tgchk_param *par)
         struct xt_led_info_internal *ledinternal;
         int err;
 
-        if (ledinfo->id[0] == '\0') {
-                pr_info("No 'id' parameter given.\n");
+        if (ledinfo->id[0] == '\0')
                 return -EINVAL;
-        }
 
         mutex_lock(&xt_led_mutex);
 
@@ -138,13 +136,14 @@ static int led_tg_check(const struct xt_tgchk_param *par)
 
         err = led_trigger_register(&ledinternal->netfilter_led_trigger);
         if (err) {
-                pr_err("Trigger name is already in use.\n");
+                pr_info_ratelimited("Trigger name is already in use.\n");
                 goto exit_alloc;
         }
 
-        /* See if we need to set up a timer */
-        if (ledinfo->delay > 0)
-                timer_setup(&ledinternal->timer, led_timeout_callback, 0);
+        /* Since the letinternal timer can be shared between multiple targets,
+         * always set it up, even if the current target does not need it
+         */
+        timer_setup(&ledinternal->timer, led_timeout_callback, 0);
 
         list_add_tail(&ledinternal->list, &xt_led_triggers);
 
@@ -181,8 +180,7 @@ static void led_tg_destroy(const struct xt_tgdtor_param *par)
 
         list_del(&ledinternal->list);
 
-        if (ledinfo->delay > 0)
-                del_timer_sync(&ledinternal->timer);
+        del_timer_sync(&ledinternal->timer);
 
         led_trigger_unregister(&ledinternal->netfilter_led_trigger);
 
diff --git a/net/netfilter/xt_NFQUEUE.c b/net/netfilter/xt_NFQUEUE.c
index a360b99a958a..a9aca80a32ae 100644
--- a/net/netfilter/xt_NFQUEUE.c
+++ b/net/netfilter/xt_NFQUEUE.c
@@ -8,6 +8,8 @@
  *
  */
 
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #include <linux/module.h>
 #include <linux/skbuff.h>
 
@@ -67,13 +69,13 @@ static int nfqueue_tg_check(const struct xt_tgchk_param *par)
         init_hashrandom(&jhash_initval);
 
         if (info->queues_total == 0) {
-                pr_err("NFQUEUE: number of total queues is 0\n");
+                pr_info_ratelimited("number of total queues is 0\n");
                 return -EINVAL;
         }
         maxid = info->queues_total - 1 + info->queuenum;
         if (maxid > 0xffff) {
-                pr_err("NFQUEUE: number of queues (%u) out of range (got %u)\n",
-                       info->queues_total, maxid);
+                pr_info_ratelimited("number of queues (%u) out of range (got %u)\n",
+                                    info->queues_total, maxid);
                 return -ERANGE;
         }
         if (par->target->revision == 2 && info->flags > 1)
diff --git a/net/netfilter/xt_SECMARK.c b/net/netfilter/xt_SECMARK.c
index 9faf5e050b79..4ad5fe27e08b 100644
--- a/net/netfilter/xt_SECMARK.c
+++ b/net/netfilter/xt_SECMARK.c
@@ -60,18 +60,20 @@ static int checkentry_lsm(struct xt_secmark_target_info *info)
                                        &info->secid);
         if (err) {
                 if (err == -EINVAL)
-                        pr_info("invalid security context \'%s\'\n", info->secctx);
+                        pr_info_ratelimited("invalid security context \'%s\'\n",
+                                            info->secctx);
                 return err;
         }
 
         if (!info->secid) {
-                pr_info("unable to map security context \'%s\'\n", info->secctx);
+                pr_info_ratelimited("unable to map security context \'%s\'\n",
+                                    info->secctx);
                 return -ENOENT;
         }
 
         err = security_secmark_relabel_packet(info->secid);
         if (err) {
-                pr_info("unable to obtain relabeling permission\n");
+                pr_info_ratelimited("unable to obtain relabeling permission\n");
                 return err;
         }
 
@@ -86,14 +88,14 @@ static int secmark_tg_check(const struct xt_tgchk_param *par)
 
         if (strcmp(par->table, "mangle") != 0 &&
             strcmp(par->table, "security") != 0) {
-                pr_info("target only valid in the \'mangle\' "
-                        "or \'security\' tables, not \'%s\'.\n", par->table);
+                pr_info_ratelimited("only valid in \'mangle\' or \'security\' table, not \'%s\'\n",
+                                    par->table);
                 return -EINVAL;
         }
 
         if (mode && mode != info->mode) {
-                pr_info("mode already set to %hu cannot mix with "
-                        "rules for mode %hu\n", mode, info->mode);
+                pr_info_ratelimited("mode already set to %hu cannot mix with rules for mode %hu\n",
+                                    mode, info->mode);
                 return -EINVAL;
         }
 
@@ -101,7 +103,7 @@ static int secmark_tg_check(const struct xt_tgchk_param *par)
         case SECMARK_MODE_SEL:
                 break;
         default:
-                pr_info("invalid mode: %hu\n", info->mode);
+                pr_info_ratelimited("invalid mode: %hu\n", info->mode);
                 return -EINVAL;
         }
 
diff --git a/net/netfilter/xt_TCPMSS.c b/net/netfilter/xt_TCPMSS.c
index 99bb8e410f22..98efb202f8b4 100644
--- a/net/netfilter/xt_TCPMSS.c
+++ b/net/netfilter/xt_TCPMSS.c
@@ -273,8 +273,7 @@ static int tcpmss_tg4_check(const struct xt_tgchk_param *par)
             (par->hook_mask & ~((1 << NF_INET_FORWARD) |
                            (1 << NF_INET_LOCAL_OUT) |
                            (1 << NF_INET_POST_ROUTING))) != 0) {
-                pr_info("path-MTU clamping only supported in "
-                        "FORWARD, OUTPUT and POSTROUTING hooks\n");
+                pr_info_ratelimited("path-MTU clamping only supported in FORWARD, OUTPUT and POSTROUTING hooks\n");
                 return -EINVAL;
         }
         if (par->nft_compat)
@@ -283,7 +282,7 @@ static int tcpmss_tg4_check(const struct xt_tgchk_param *par)
         xt_ematch_foreach(ematch, e)
                 if (find_syn_match(ematch))
                         return 0;
-        pr_info("Only works on TCP SYN packets\n");
+        pr_info_ratelimited("Only works on TCP SYN packets\n");
         return -EINVAL;
 }
 
@@ -298,8 +297,7 @@ static int tcpmss_tg6_check(const struct xt_tgchk_param *par)
             (par->hook_mask & ~((1 << NF_INET_FORWARD) |
                            (1 << NF_INET_LOCAL_OUT) |
                            (1 << NF_INET_POST_ROUTING))) != 0) {
-                pr_info("path-MTU clamping only supported in "
-                        "FORWARD, OUTPUT and POSTROUTING hooks\n");
+                pr_info_ratelimited("path-MTU clamping only supported in FORWARD, OUTPUT and POSTROUTING hooks\n");
                 return -EINVAL;
         }
         if (par->nft_compat)
@@ -308,7 +306,7 @@ static int tcpmss_tg6_check(const struct xt_tgchk_param *par)
         xt_ematch_foreach(ematch, e)
                 if (find_syn_match(ematch))
                         return 0;
-        pr_info("Only works on TCP SYN packets\n");
+        pr_info_ratelimited("Only works on TCP SYN packets\n");
         return -EINVAL;
 }
 #endif
diff --git a/net/netfilter/xt_TPROXY.c b/net/netfilter/xt_TPROXY.c
index 17d7705e3bd4..8c89323c06af 100644
--- a/net/netfilter/xt_TPROXY.c
+++ b/net/netfilter/xt_TPROXY.c
@@ -540,8 +540,7 @@ static int tproxy_tg6_check(const struct xt_tgchk_param *par)
             !(i->invflags & IP6T_INV_PROTO))
                 return 0;
 
-        pr_info("Can be used only in combination with "
-                "either -p tcp or -p udp\n");
+        pr_info_ratelimited("Can be used only with -p tcp or -p udp\n");
         return -EINVAL;
 }
 #endif
@@ -559,8 +558,7 @@ static int tproxy_tg4_check(const struct xt_tgchk_param *par)
             && !(i->invflags & IPT_INV_PROTO))
                 return 0;
 
-        pr_info("Can be used only in combination with "
-                "either -p tcp or -p udp\n");
+        pr_info_ratelimited("Can be used only with -p tcp or -p udp\n");
         return -EINVAL;
 }
 
diff --git a/net/netfilter/xt_addrtype.c b/net/netfilter/xt_addrtype.c
index 911a7c0da504..89e281b3bfc2 100644
--- a/net/netfilter/xt_addrtype.c
+++ b/net/netfilter/xt_addrtype.c
@@ -164,48 +164,47 @@ addrtype_mt_v1(const struct sk_buff *skb, struct xt_action_param *par)
 
 static int addrtype_mt_checkentry_v1(const struct xt_mtchk_param *par)
 {
+        const char *errmsg = "both incoming and outgoing interface limitation cannot be selected";
         struct xt_addrtype_info_v1 *info = par->matchinfo;
 
         if (info->flags & XT_ADDRTYPE_LIMIT_IFACE_IN &&
-            info->flags & XT_ADDRTYPE_LIMIT_IFACE_OUT) {
-                pr_info("both incoming and outgoing "
-                        "interface limitation cannot be selected\n");
-                return -EINVAL;
-        }
+            info->flags & XT_ADDRTYPE_LIMIT_IFACE_OUT)
+                goto err;
 
         if (par->hook_mask & ((1 << NF_INET_PRE_ROUTING) |
             (1 << NF_INET_LOCAL_IN)) &&
             info->flags & XT_ADDRTYPE_LIMIT_IFACE_OUT) {
-                pr_info("output interface limitation "
-                        "not valid in PREROUTING and INPUT\n");
-                return -EINVAL;
+                errmsg = "output interface limitation not valid in PREROUTING and INPUT";
+                goto err;
         }
 
         if (par->hook_mask & ((1 << NF_INET_POST_ROUTING) |
             (1 << NF_INET_LOCAL_OUT)) &&
             info->flags & XT_ADDRTYPE_LIMIT_IFACE_IN) {
-                pr_info("input interface limitation "
-                        "not valid in POSTROUTING and OUTPUT\n");
-                return -EINVAL;
+                errmsg = "input interface limitation not valid in POSTROUTING and OUTPUT";
+                goto err;
         }
 
 #if IS_ENABLED(CONFIG_IP6_NF_IPTABLES)
         if (par->family == NFPROTO_IPV6) {
                 if ((info->source | info->dest) & XT_ADDRTYPE_BLACKHOLE) {
-                        pr_err("ipv6 BLACKHOLE matching not supported\n");
-                        return -EINVAL;
+                        errmsg = "ipv6 BLACKHOLE matching not supported";
+                        goto err;
                 }
                 if ((info->source | info->dest) >= XT_ADDRTYPE_PROHIBIT) {
-                        pr_err("ipv6 PROHIBIT (THROW, NAT ..) matching not supported\n");
-                        return -EINVAL;
+                        errmsg = "ipv6 PROHIBIT (THROW, NAT ..) matching not supported";
+                        goto err;
                 }
                 if ((info->source | info->dest) & XT_ADDRTYPE_BROADCAST) {
-                        pr_err("ipv6 does not support BROADCAST matching\n");
-                        return -EINVAL;
+                        errmsg = "ipv6 does not support BROADCAST matching";
+                        goto err;
                 }
         }
 #endif
         return 0;
+err:
+        pr_info_ratelimited("%s\n", errmsg);
+        return -EINVAL;
 }
 
 static struct xt_match addrtype_mt_reg[] __read_mostly = {
diff --git a/net/netfilter/xt_bpf.c b/net/netfilter/xt_bpf.c
index 06b090d8e901..a2cf8a6236d6 100644
--- a/net/netfilter/xt_bpf.c
+++ b/net/netfilter/xt_bpf.c
@@ -7,6 +7,8 @@
  * published by the Free Software Foundation.
  */
 
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #include <linux/module.h>
 #include <linux/syscalls.h>
 #include <linux/skbuff.h>
@@ -34,7 +36,7 @@ static int __bpf_mt_check_bytecode(struct sock_filter *insns, __u16 len,
         program.filter = insns;
 
         if (bpf_prog_create(ret, &program)) {
-                pr_info("bpf: check failed: parse error\n");
+                pr_info_ratelimited("check failed: parse error\n");
                 return -EINVAL;
         }
 
diff --git a/net/netfilter/xt_cgroup.c b/net/netfilter/xt_cgroup.c
index 891f4e7e8ea7..7df2dece57d3 100644
--- a/net/netfilter/xt_cgroup.c
+++ b/net/netfilter/xt_cgroup.c
@@ -12,6 +12,8 @@
  * published by the Free Software Foundation.
  */
 
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #include <linux/skbuff.h>
 #include <linux/module.h>
 #include <linux/netfilter/x_tables.h>
@@ -48,7 +50,7 @@ static int cgroup_mt_check_v1(const struct xt_mtchk_param *par)
         }
 
         if (info->has_path && info->has_classid) {
-                pr_info("xt_cgroup: both path and classid specified\n");
+                pr_info_ratelimited("path and classid specified\n");
                 return -EINVAL;
         }
 
@@ -56,8 +58,8 @@ static int cgroup_mt_check_v1(const struct xt_mtchk_param *par)
         if (info->has_path) {
                 cgrp = cgroup_get_from_path(info->path);
                 if (IS_ERR(cgrp)) {
-                        pr_info("xt_cgroup: invalid path, errno=%ld\n",
-                                PTR_ERR(cgrp));
+                        pr_info_ratelimited("invalid path, errno=%ld\n",
+                                            PTR_ERR(cgrp));
                         return -EINVAL;
                 }
                 info->priv = cgrp;
diff --git a/net/netfilter/xt_cluster.c b/net/netfilter/xt_cluster.c
index 57ef175dfbfa..0068688995c8 100644
--- a/net/netfilter/xt_cluster.c
+++ b/net/netfilter/xt_cluster.c
@@ -135,14 +135,12 @@ static int xt_cluster_mt_checkentry(const struct xt_mtchk_param *par)
         struct xt_cluster_match_info *info = par->matchinfo;
 
         if (info->total_nodes > XT_CLUSTER_NODES_MAX) {
-                pr_info("you have exceeded the maximum "
-                        "number of cluster nodes (%u > %u)\n",
-                        info->total_nodes, XT_CLUSTER_NODES_MAX);
+                pr_info_ratelimited("you have exceeded the maximum number of cluster nodes (%u > %u)\n",
+                                    info->total_nodes, XT_CLUSTER_NODES_MAX);
                 return -EINVAL;
         }
         if (info->node_mask >= (1ULL << info->total_nodes)) {
-                pr_info("this node mask cannot be "
-                        "higher than the total number of nodes\n");
+                pr_info_ratelimited("node mask cannot exceed total number of nodes\n");
                 return -EDOM;
         }
         return 0;
diff --git a/net/netfilter/xt_connbytes.c b/net/netfilter/xt_connbytes.c
index cad0b7b5eb35..93cb018c3055 100644
--- a/net/netfilter/xt_connbytes.c
+++ b/net/netfilter/xt_connbytes.c
@@ -112,8 +112,8 @@ static int connbytes_mt_check(const struct xt_mtchk_param *par)
 
         ret = nf_ct_netns_get(par->net, par->family);
         if (ret < 0)
-                pr_info("cannot load conntrack support for proto=%u\n",
-                        par->family);
+                pr_info_ratelimited("cannot load conntrack support for proto=%u\n",
+                                    par->family);
 
         /*
          * This filter cannot function correctly unless connection tracking
diff --git a/net/netfilter/xt_connlabel.c b/net/netfilter/xt_connlabel.c
index 23372879e6e3..4fa4efd24353 100644
--- a/net/netfilter/xt_connlabel.c
+++ b/net/netfilter/xt_connlabel.c
@@ -57,14 +57,15 @@ static int connlabel_mt_check(const struct xt_mtchk_param *par)
         int ret;
 
         if (info->options & ~options) {
-                pr_err("Unknown options in mask %x\n", info->options);
+                pr_info_ratelimited("Unknown options in mask %x\n",
+                                    info->options);
                 return -EINVAL;
         }
 
         ret = nf_ct_netns_get(par->net, par->family);
         if (ret < 0) {
-                pr_info("cannot load conntrack support for proto=%u\n",
-                                                        par->family);
+                pr_info_ratelimited("cannot load conntrack support for proto=%u\n",
+                                    par->family);
                 return ret;
         }
 
diff --git a/net/netfilter/xt_connmark.c b/net/netfilter/xt_connmark.c
index ec377cc6a369..809639ce6f5a 100644
--- a/net/netfilter/xt_connmark.c
+++ b/net/netfilter/xt_connmark.c
@@ -79,8 +79,8 @@ static int connmark_tg_check(const struct xt_tgchk_param *par)
 
         ret = nf_ct_netns_get(par->net, par->family);
         if (ret < 0)
-                pr_info("cannot load conntrack support for proto=%u\n",
-                        par->family);
+                pr_info_ratelimited("cannot load conntrack support for proto=%u\n",
+                                    par->family);
         return ret;
 }
 
@@ -109,8 +109,8 @@ static int connmark_mt_check(const struct xt_mtchk_param *par)
 
         ret = nf_ct_netns_get(par->net, par->family);
         if (ret < 0)
-                pr_info("cannot load conntrack support for proto=%u\n",
-                        par->family);
+                pr_info_ratelimited("cannot load conntrack support for proto=%u\n",
+                                    par->family);
         return ret;
 }
 
diff --git a/net/netfilter/xt_conntrack.c b/net/netfilter/xt_conntrack.c
index 39cf1d019240..df80fe7d391c 100644
--- a/net/netfilter/xt_conntrack.c
+++ b/net/netfilter/xt_conntrack.c
@@ -272,8 +272,8 @@ static int conntrack_mt_check(const struct xt_mtchk_param *par)
 
         ret = nf_ct_netns_get(par->net, par->family);
         if (ret < 0)
-                pr_info("cannot load conntrack support for proto=%u\n",
-                        par->family);
+                pr_info_ratelimited("cannot load conntrack support for proto=%u\n",
+                                    par->family);
         return ret;
 }
 
diff --git a/net/netfilter/xt_dscp.c b/net/netfilter/xt_dscp.c
index 236ac8008909..a4c2b862f820 100644
--- a/net/netfilter/xt_dscp.c
+++ b/net/netfilter/xt_dscp.c
@@ -46,10 +46,8 @@ static int dscp_mt_check(const struct xt_mtchk_param *par)
 {
         const struct xt_dscp_info *info = par->matchinfo;
 
-        if (info->dscp > XT_DSCP_MAX) {
-                pr_info("dscp %x out of range\n", info->dscp);
+        if (info->dscp > XT_DSCP_MAX)
                 return -EDOM;
-        }
 
         return 0;
 }
diff --git a/net/netfilter/xt_ecn.c b/net/netfilter/xt_ecn.c
index 3c831a8efebc..c7ad4afa5fb8 100644
--- a/net/netfilter/xt_ecn.c
+++ b/net/netfilter/xt_ecn.c
@@ -97,7 +97,7 @@ static int ecn_mt_check4(const struct xt_mtchk_param *par)
 
         if (info->operation & (XT_ECN_OP_MATCH_ECE | XT_ECN_OP_MATCH_CWR) &&
             (ip->proto != IPPROTO_TCP || ip->invflags & IPT_INV_PROTO)) {
-                pr_info("cannot match TCP bits in rule for non-tcp packets\n");
+                pr_info_ratelimited("cannot match TCP bits for non-tcp packets\n");
                 return -EINVAL;
         }
 
@@ -139,7 +139,7 @@ static int ecn_mt_check6(const struct xt_mtchk_param *par)
 
         if (info->operation & (XT_ECN_OP_MATCH_ECE | XT_ECN_OP_MATCH_CWR) &&
             (ip->proto != IPPROTO_TCP || ip->invflags & IP6T_INV_PROTO)) {
-                pr_info("cannot match TCP bits in rule for non-tcp packets\n");
+                pr_info_ratelimited("cannot match TCP bits for non-tcp packets\n");
                 return -EINVAL;
         }
 
diff --git a/net/netfilter/xt_hashlimit.c b/net/netfilter/xt_hashlimit.c
index ca6847403ca2..66f5aca62a08 100644
--- a/net/netfilter/xt_hashlimit.c
+++ b/net/netfilter/xt_hashlimit.c
@@ -523,7 +523,8 @@ static u64 user2rate(u64 user)
         if (user != 0) {
                 return div64_u64(XT_HASHLIMIT_SCALE_v2, user);
         } else {
-                pr_warn("invalid rate from userspace: %llu\n", user);
+                pr_info_ratelimited("invalid rate from userspace: %llu\n",
+                                    user);
                 return 0;
         }
 }
@@ -774,7 +775,7 @@ hashlimit_mt_common(const struct sk_buff *skb, struct xt_action_param *par,
                 if (!dh->rateinfo.prev_window &&
                     (dh->rateinfo.current_rate <= dh->rateinfo.burst)) {
                         spin_unlock(&dh->lock);
-                        rcu_read_unlock_bh();
+                        local_bh_enable();
                         return !(cfg->mode & XT_HASHLIMIT_INVERT);
                 } else {
                         goto overlimit;
@@ -865,33 +866,34 @@ static int hashlimit_mt_check_common(const struct xt_mtchk_param *par,
         }
 
         if (cfg->mode & ~XT_HASHLIMIT_ALL) {
-                pr_info("Unknown mode mask %X, kernel too old?\n",
-                                                cfg->mode);
+                pr_info_ratelimited("Unknown mode mask %X, kernel too old?\n",
+                                    cfg->mode);
                 return -EINVAL;
         }
 
         /* Check for overflow. */
         if (revision >= 3 && cfg->mode & XT_HASHLIMIT_RATE_MATCH) {
                 if (cfg->avg == 0 || cfg->avg > U32_MAX) {
-                        pr_info("hashlimit invalid rate\n");
+                        pr_info_ratelimited("invalid rate\n");
                         return -ERANGE;
                 }
 
                 if (cfg->interval == 0) {
-                        pr_info("hashlimit invalid interval\n");
+                        pr_info_ratelimited("invalid interval\n");
                         return -EINVAL;
                 }
         } else if (cfg->mode & XT_HASHLIMIT_BYTES) {
                 if (user2credits_byte(cfg->avg) == 0) {
-                        pr_info("overflow, rate too high: %llu\n", cfg->avg);
+                        pr_info_ratelimited("overflow, rate too high: %llu\n",
+                                            cfg->avg);
                         return -EINVAL;
                 }
         } else if (cfg->burst == 0 ||
-                    user2credits(cfg->avg * cfg->burst, revision) <
-                    user2credits(cfg->avg, revision)) {
-                        pr_info("overflow, try lower: %llu/%llu\n",
-                                cfg->avg, cfg->burst);
-                        return -ERANGE;
+                   user2credits(cfg->avg * cfg->burst, revision) <
+                   user2credits(cfg->avg, revision)) {
+                pr_info_ratelimited("overflow, try lower: %llu/%llu\n",
+                                    cfg->avg, cfg->burst);
+                return -ERANGE;
         }
 
         mutex_lock(&hashlimit_mutex);
diff --git a/net/netfilter/xt_helper.c b/net/netfilter/xt_helper.c
index 38a78151c0e9..fd077aeaaed9 100644
--- a/net/netfilter/xt_helper.c
+++ b/net/netfilter/xt_helper.c
@@ -61,8 +61,8 @@ static int helper_mt_check(const struct xt_mtchk_param *par)
 
         ret = nf_ct_netns_get(par->net, par->family);
         if (ret < 0) {
-                pr_info("cannot load conntrack support for proto=%u\n",
-                        par->family);
+                pr_info_ratelimited("cannot load conntrack support for proto=%u\n",
+                                    par->family);
                 return ret;
         }
         info->name[sizeof(info->name) - 1] = '\0';
diff --git a/net/netfilter/xt_ipcomp.c b/net/netfilter/xt_ipcomp.c
index 7ca64a50db04..57f1df575701 100644
--- a/net/netfilter/xt_ipcomp.c
+++ b/net/netfilter/xt_ipcomp.c
@@ -72,7 +72,7 @@ static int comp_mt_check(const struct xt_mtchk_param *par)
 
         /* Must specify no unknown invflags */
         if (compinfo->invflags & ~XT_IPCOMP_INV_MASK) {
-                pr_err("unknown flags %X\n", compinfo->invflags);
+                pr_info_ratelimited("unknown flags %X\n", compinfo->invflags);
                 return -EINVAL;
         }
         return 0;
diff --git a/net/netfilter/xt_ipvs.c b/net/netfilter/xt_ipvs.c
index 42540d26c2b8..1d950a6100af 100644
--- a/net/netfilter/xt_ipvs.c
+++ b/net/netfilter/xt_ipvs.c
@@ -158,7 +158,8 @@ static int ipvs_mt_check(const struct xt_mtchk_param *par)
             && par->family != NFPROTO_IPV6
 #endif
                 ) {
-                pr_info("protocol family %u not supported\n", par->family);
+                pr_info_ratelimited("protocol family %u not supported\n",
+                                    par->family);
                 return -EINVAL;
         }
 
diff --git a/net/netfilter/xt_l2tp.c b/net/netfilter/xt_l2tp.c
index 8aee572771f2..c43482bf48e6 100644
--- a/net/netfilter/xt_l2tp.c
+++ b/net/netfilter/xt_l2tp.c
@@ -216,7 +216,7 @@ static int l2tp_mt_check(const struct xt_mtchk_param *par)
         /* Check for invalid flags */
         if (info->flags & ~(XT_L2TP_TID | XT_L2TP_SID | XT_L2TP_VERSION |
                             XT_L2TP_TYPE)) {
-                pr_info("unknown flags: %x\n", info->flags);
+                pr_info_ratelimited("unknown flags: %x\n", info->flags);
                 return -EINVAL;
         }
 
@@ -225,7 +225,8 @@ static int l2tp_mt_check(const struct xt_mtchk_param *par)
             (!(info->flags & XT_L2TP_SID)) &&
             ((!(info->flags & XT_L2TP_TYPE)) ||
              (info->type != XT_L2TP_TYPE_CONTROL))) {
-                pr_info("invalid flags combination: %x\n", info->flags);
+                pr_info_ratelimited("invalid flags combination: %x\n",
+                                    info->flags);
                 return -EINVAL;
         }
 
@@ -234,19 +235,22 @@ static int l2tp_mt_check(const struct xt_mtchk_param *par)
          */
         if (info->flags & XT_L2TP_VERSION) {
                 if ((info->version < 2) || (info->version > 3)) {
-                        pr_info("wrong L2TP version: %u\n", info->version);
+                        pr_info_ratelimited("wrong L2TP version: %u\n",
+                                            info->version);
                         return -EINVAL;
                 }
 
                 if (info->version == 2) {
                         if ((info->flags & XT_L2TP_TID) &&
                             (info->tid > 0xffff)) {
-                                pr_info("v2 tid > 0xffff: %u\n", info->tid);
+                                pr_info_ratelimited("v2 tid > 0xffff: %u\n",
+                                                    info->tid);
                                 return -EINVAL;
                         }
                         if ((info->flags & XT_L2TP_SID) &&
                             (info->sid > 0xffff)) {
-                                pr_info("v2 sid > 0xffff: %u\n", info->sid);
+                                pr_info_ratelimited("v2 sid > 0xffff: %u\n",
+                                                    info->sid);
                                 return -EINVAL;
                         }
                 }
@@ -268,13 +272,13 @@ static int l2tp_mt_check4(const struct xt_mtchk_param *par)
 
         if ((ip->proto != IPPROTO_UDP) &&
             (ip->proto != IPPROTO_L2TP)) {
-                pr_info("missing protocol rule (udp|l2tpip)\n");
+                pr_info_ratelimited("missing protocol rule (udp|l2tpip)\n");
                 return -EINVAL;
         }
 
         if ((ip->proto == IPPROTO_L2TP) &&
             (info->version == 2)) {
-                pr_info("v2 doesn't support IP mode\n");
+                pr_info_ratelimited("v2 doesn't support IP mode\n");
                 return -EINVAL;
         }
 
@@ -295,13 +299,13 @@ static int l2tp_mt_check6(const struct xt_mtchk_param *par)
 
         if ((ip->proto != IPPROTO_UDP) &&
             (ip->proto != IPPROTO_L2TP)) {
-                pr_info("missing protocol rule (udp|l2tpip)\n");
+                pr_info_ratelimited("missing protocol rule (udp|l2tpip)\n");
                 return -EINVAL;
         }
 
         if ((ip->proto == IPPROTO_L2TP) &&
             (info->version == 2)) {
-                pr_info("v2 doesn't support IP mode\n");
+                pr_info_ratelimited("v2 doesn't support IP mode\n");
                 return -EINVAL;
         }
 
diff --git a/net/netfilter/xt_limit.c b/net/netfilter/xt_limit.c
index 61403b77361c..55d18cd67635 100644
--- a/net/netfilter/xt_limit.c
+++ b/net/netfilter/xt_limit.c
@@ -106,8 +106,8 @@ static int limit_mt_check(const struct xt_mtchk_param *par)
         /* Check for overflow. */
         if (r->burst == 0
             || user2credits(r->avg * r->burst) < user2credits(r->avg)) {
-                pr_info("Overflow, try lower: %u/%u\n",
-                        r->avg, r->burst);
+                pr_info_ratelimited("Overflow, try lower: %u/%u\n",
+                                    r->avg, r->burst);
                 return -ERANGE;
         }
 
diff --git a/net/netfilter/xt_nat.c b/net/netfilter/xt_nat.c
index 0fd14d1eb09d..bdb689cdc829 100644
--- a/net/netfilter/xt_nat.c
+++ b/net/netfilter/xt_nat.c
@@ -8,6 +8,8 @@
  * published by the Free Software Foundation.
  */
 
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #include <linux/module.h>
 #include <linux/skbuff.h>
 #include <linux/netfilter.h>
@@ -19,8 +21,7 @@ static int xt_nat_checkentry_v0(const struct xt_tgchk_param *par)
         const struct nf_nat_ipv4_multi_range_compat *mr = par->targinfo;
 
         if (mr->rangesize != 1) {
-                pr_info("%s: multiple ranges no longer supported\n",
-                        par->target->name);
+                pr_info_ratelimited("multiple ranges no longer supported\n");
                 return -EINVAL;
         }
         return nf_ct_netns_get(par->net, par->family);
diff --git a/net/netfilter/xt_nfacct.c b/net/netfilter/xt_nfacct.c
index 6f92d25590a8..c8674deed4eb 100644
--- a/net/netfilter/xt_nfacct.c
+++ b/net/netfilter/xt_nfacct.c
@@ -6,6 +6,8 @@
  * it under the terms of the GNU General Public License version 2 (or any
  * later at your option) as published by the Free Software Foundation.
  */
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #include <linux/module.h>
 #include <linux/skbuff.h>
 
@@ -39,8 +41,8 @@ nfacct_mt_checkentry(const struct xt_mtchk_param *par)
 
         nfacct = nfnl_acct_find_get(par->net, info->name);
         if (nfacct == NULL) {
-                pr_info("xt_nfacct: accounting object with name `%s' "
-                        "does not exists\n", info->name);
+                pr_info_ratelimited("accounting object `%s' does not exists\n",
+                                    info->name);
                 return -ENOENT;
         }
         info->nfacct = nfacct;
diff --git a/net/netfilter/xt_physdev.c b/net/netfilter/xt_physdev.c
index bb33598e4530..9d6d67b953ac 100644
--- a/net/netfilter/xt_physdev.c
+++ b/net/netfilter/xt_physdev.c
@@ -107,9 +107,7 @@ static int physdev_mt_check(const struct xt_mtchk_param *par)
              info->invert & XT_PHYSDEV_OP_BRIDGED) &&
             par->hook_mask & ((1 << NF_INET_LOCAL_OUT) |
             (1 << NF_INET_FORWARD) | (1 << NF_INET_POST_ROUTING))) {
-                pr_info("using --physdev-out and --physdev-is-out are only "
-                        "supported in the FORWARD and POSTROUTING chains with "
-                        "bridged traffic.\n");
+                pr_info_ratelimited("--physdev-out and --physdev-is-out only supported in the FORWARD and POSTROUTING chains with bridged traffic\n");
                 if (par->hook_mask & (1 << NF_INET_LOCAL_OUT))
                         return -EINVAL;
         }
diff --git a/net/netfilter/xt_policy.c b/net/netfilter/xt_policy.c
index 5639fb03bdd9..13f8ccf946d6 100644
--- a/net/netfilter/xt_policy.c
+++ b/net/netfilter/xt_policy.c
@@ -132,26 +132,29 @@ policy_mt(const struct sk_buff *skb, struct xt_action_param *par)
 static int policy_mt_check(const struct xt_mtchk_param *par)
 {
         const struct xt_policy_info *info = par->matchinfo;
+        const char *errmsg = "neither incoming nor outgoing policy selected";
+
+        if (!(info->flags & (XT_POLICY_MATCH_IN|XT_POLICY_MATCH_OUT)))
+                goto err;
 
-        if (!(info->flags & (XT_POLICY_MATCH_IN|XT_POLICY_MATCH_OUT))) {
-                pr_info("neither incoming nor outgoing policy selected\n");
-                return -EINVAL;
-        }
         if (par->hook_mask & ((1 << NF_INET_PRE_ROUTING) |
             (1 << NF_INET_LOCAL_IN)) && info->flags & XT_POLICY_MATCH_OUT) {
-                pr_info("output policy not valid in PREROUTING and INPUT\n");
-                return -EINVAL;
+                errmsg = "output policy not valid in PREROUTING and INPUT";
+                goto err;
         }
         if (par->hook_mask & ((1 << NF_INET_POST_ROUTING) |
             (1 << NF_INET_LOCAL_OUT)) && info->flags & XT_POLICY_MATCH_IN) {
-                pr_info("input policy not valid in POSTROUTING and OUTPUT\n");
-                return -EINVAL;
+                errmsg = "input policy not valid in POSTROUTING and OUTPUT";
+                goto err;
         }
         if (info->len > XT_POLICY_MAX_ELEM) {
-                pr_info("too many policy elements\n");
-                return -EINVAL;
+                errmsg = "too many policy elements";
+                goto err;
         }
         return 0;
+err:
+        pr_info_ratelimited("%s\n", errmsg);
+        return -EINVAL;
 }
 
 static struct xt_match policy_mt_reg[] __read_mostly = {
diff --git a/net/netfilter/xt_recent.c b/net/netfilter/xt_recent.c
index 245fa350a7a8..6d232d18faff 100644
--- a/net/netfilter/xt_recent.c
+++ b/net/netfilter/xt_recent.c
@@ -342,8 +342,8 @@ static int recent_mt_check(const struct xt_mtchk_param *par,
         net_get_random_once(&hash_rnd, sizeof(hash_rnd));
 
         if (info->check_set & ~XT_RECENT_VALID_FLAGS) {
-                pr_info("Unsupported user space flags (%08x)\n",
-                        info->check_set);
+                pr_info_ratelimited("Unsupported userspace flags (%08x)\n",
+                                    info->check_set);
                 return -EINVAL;
         }
         if (hweight8(info->check_set &
@@ -357,8 +357,8 @@ static int recent_mt_check(const struct xt_mtchk_param *par,
         if ((info->check_set & XT_RECENT_REAP) && !info->seconds)
                 return -EINVAL;
         if (info->hit_count >= XT_RECENT_MAX_NSTAMPS) {
-                pr_info("hitcount (%u) is larger than allowed maximum (%u)\n",
-                        info->hit_count, XT_RECENT_MAX_NSTAMPS - 1);
+                pr_info_ratelimited("hitcount (%u) is larger than allowed maximum (%u)\n",
+                                    info->hit_count, XT_RECENT_MAX_NSTAMPS - 1);
                 return -EINVAL;
         }
         if (info->name[0] == '\0' ||
@@ -587,7 +587,7 @@ recent_mt_proc_write(struct file *file, const char __user *input,
                 add = true;
                 break;
         default:
-                pr_info("Need \"+ip\", \"-ip\" or \"/\"\n");
+                pr_info_ratelimited("Need \"+ip\", \"-ip\" or \"/\"\n");
                 return -EINVAL;
         }
 
@@ -601,10 +601,8 @@ recent_mt_proc_write(struct file *file, const char __user *input,
                 succ   = in4_pton(c, size, (void *)&addr, '\n', NULL);
         }
 
-        if (!succ) {
-                pr_info("illegal address written to procfs\n");
+        if (!succ)
                 return -EINVAL;
-        }
 
         spin_lock_bh(&recent_lock);
         e = recent_entry_lookup(t, &addr, family, 0);
diff --git a/net/netfilter/xt_set.c b/net/netfilter/xt_set.c
index 16b6b11ee83f..6f4c5217d835 100644
--- a/net/netfilter/xt_set.c
+++ b/net/netfilter/xt_set.c
@@ -92,12 +92,12 @@ set_match_v0_checkentry(const struct xt_mtchk_param *par)
         index = ip_set_nfnl_get_byindex(par->net, info->match_set.index);
 
         if (index == IPSET_INVALID_ID) {
-                pr_warn("Cannot find set identified by id %u to match\n",
-                        info->match_set.index);
+                pr_info_ratelimited("Cannot find set identified by id %u to match\n",
+                                    info->match_set.index);
                 return -ENOENT;
         }
         if (info->match_set.u.flags[IPSET_DIM_MAX - 1] != 0) {
-                pr_warn("Protocol error: set match dimension is over the limit!\n");
+                pr_info_ratelimited("set match dimension is over the limit!\n");
                 ip_set_nfnl_put(par->net, info->match_set.index);
                 return -ERANGE;
         }
@@ -143,12 +143,12 @@ set_match_v1_checkentry(const struct xt_mtchk_param *par)
         index = ip_set_nfnl_get_byindex(par->net, info->match_set.index);
 
         if (index == IPSET_INVALID_ID) {
-                pr_warn("Cannot find set identified by id %u to match\n",
-                        info->match_set.index);
+                pr_info_ratelimited("Cannot find set identified by id %u to match\n",
+                                    info->match_set.index);
                 return -ENOENT;
         }
         if (info->match_set.dim > IPSET_DIM_MAX) {
-                pr_warn("Protocol error: set match dimension is over the limit!\n");
+                pr_info_ratelimited("set match dimension is over the limit!\n");
                 ip_set_nfnl_put(par->net, info->match_set.index);
                 return -ERANGE;
         }
@@ -241,8 +241,8 @@ set_target_v0_checkentry(const struct xt_tgchk_param *par)
         if (info->add_set.index != IPSET_INVALID_ID) {
                 index = ip_set_nfnl_get_byindex(par->net, info->add_set.index);
                 if (index == IPSET_INVALID_ID) {
-                        pr_warn("Cannot find add_set index %u as target\n",
-                                info->add_set.index);
+                        pr_info_ratelimited("Cannot find add_set index %u as target\n",
+                                            info->add_set.index);
                         return -ENOENT;
                 }
         }
@@ -250,8 +250,8 @@ set_target_v0_checkentry(const struct xt_tgchk_param *par)
         if (info->del_set.index != IPSET_INVALID_ID) {
                 index = ip_set_nfnl_get_byindex(par->net, info->del_set.index);
                 if (index == IPSET_INVALID_ID) {
-                        pr_warn("Cannot find del_set index %u as target\n",
-                                info->del_set.index);
+                        pr_info_ratelimited("Cannot find del_set index %u as target\n",
+                                            info->del_set.index);
                         if (info->add_set.index != IPSET_INVALID_ID)
                                 ip_set_nfnl_put(par->net, info->add_set.index);
                         return -ENOENT;
@@ -259,7 +259,7 @@ set_target_v0_checkentry(const struct xt_tgchk_param *par)
         }
         if (info->add_set.u.flags[IPSET_DIM_MAX - 1] != 0 ||
             info->del_set.u.flags[IPSET_DIM_MAX - 1] != 0) {
-                pr_warn("Protocol error: SET target dimension is over the limit!\n");
+                pr_info_ratelimited("SET target dimension over the limit!\n");
                 if (info->add_set.index != IPSET_INVALID_ID)
                         ip_set_nfnl_put(par->net, info->add_set.index);
                 if (info->del_set.index != IPSET_INVALID_ID)
@@ -316,8 +316,8 @@ set_target_v1_checkentry(const struct xt_tgchk_param *par)
         if (info->add_set.index != IPSET_INVALID_ID) {
                 index = ip_set_nfnl_get_byindex(par->net, info->add_set.index);
                 if (index == IPSET_INVALID_ID) {
-                        pr_warn("Cannot find add_set index %u as target\n",
-                                info->add_set.index);
+                        pr_info_ratelimited("Cannot find add_set index %u as target\n",
+                                            info->add_set.index);
                         return -ENOENT;
                 }
         }
@@ -325,8 +325,8 @@ set_target_v1_checkentry(const struct xt_tgchk_param *par)
         if (info->del_set.index != IPSET_INVALID_ID) {
                 index = ip_set_nfnl_get_byindex(par->net, info->del_set.index);
                 if (index == IPSET_INVALID_ID) {
-                        pr_warn("Cannot find del_set index %u as target\n",
-                                info->del_set.index);
+                        pr_info_ratelimited("Cannot find del_set index %u as target\n",
+                                            info->del_set.index);
                         if (info->add_set.index != IPSET_INVALID_ID)
                                 ip_set_nfnl_put(par->net, info->add_set.index);
                         return -ENOENT;
@@ -334,7 +334,7 @@ set_target_v1_checkentry(const struct xt_tgchk_param *par)
         }
         if (info->add_set.dim > IPSET_DIM_MAX ||
             info->del_set.dim > IPSET_DIM_MAX) {
-                pr_warn("Protocol error: SET target dimension is over the limit!\n");
+                pr_info_ratelimited("SET target dimension over the limit!\n");
                 if (info->add_set.index != IPSET_INVALID_ID)
                         ip_set_nfnl_put(par->net, info->add_set.index);
                 if (info->del_set.index != IPSET_INVALID_ID)
@@ -444,8 +444,8 @@ set_target_v3_checkentry(const struct xt_tgchk_param *par)
                 index = ip_set_nfnl_get_byindex(par->net,
                                                 info->add_set.index);
                 if (index == IPSET_INVALID_ID) {
-                        pr_warn("Cannot find add_set index %u as target\n",
-                                info->add_set.index);
+                        pr_info_ratelimited("Cannot find add_set index %u as target\n",
+                                            info->add_set.index);
                         return -ENOENT;
                 }
         }
@@ -454,8 +454,8 @@ set_target_v3_checkentry(const struct xt_tgchk_param *par)
                 index = ip_set_nfnl_get_byindex(par->net,
                                                 info->del_set.index);
                 if (index == IPSET_INVALID_ID) {
-                        pr_warn("Cannot find del_set index %u as target\n",
-                                info->del_set.index);
+                        pr_info_ratelimited("Cannot find del_set index %u as target\n",
+                                            info->del_set.index);
                         if (info->add_set.index != IPSET_INVALID_ID)
                                 ip_set_nfnl_put(par->net,
                                                 info->add_set.index);
@@ -465,7 +465,7 @@ set_target_v3_checkentry(const struct xt_tgchk_param *par)
 
         if (info->map_set.index != IPSET_INVALID_ID) {
                 if (strncmp(par->table, "mangle", 7)) {
-                        pr_warn("--map-set only usable from mangle table\n");
+                        pr_info_ratelimited("--map-set only usable from mangle table\n");
                         return -EINVAL;
                 }
                 if (((info->flags & IPSET_FLAG_MAP_SKBPRIO) |
@@ -473,14 +473,14 @@ set_target_v3_checkentry(const struct xt_tgchk_param *par)
                      !(par->hook_mask & (1 << NF_INET_FORWARD |
                                          1 << NF_INET_LOCAL_OUT |
                                          1 << NF_INET_POST_ROUTING))) {
-                        pr_warn("mapping of prio or/and queue is allowed only from OUTPUT/FORWARD/POSTROUTING chains\n");
+                        pr_info_ratelimited("mapping of prio or/and queue is allowed only from OUTPUT/FORWARD/POSTROUTING chains\n");
                         return -EINVAL;
                 }
                 index = ip_set_nfnl_get_byindex(par->net,
                                                 info->map_set.index);
                 if (index == IPSET_INVALID_ID) {
-                        pr_warn("Cannot find map_set index %u as target\n",
-                                info->map_set.index);
+                        pr_info_ratelimited("Cannot find map_set index %u as target\n",
+                                            info->map_set.index);
                         if (info->add_set.index != IPSET_INVALID_ID)
                                 ip_set_nfnl_put(par->net,
                                                 info->add_set.index);
@@ -494,7 +494,7 @@ set_target_v3_checkentry(const struct xt_tgchk_param *par)
         if (info->add_set.dim > IPSET_DIM_MAX ||
             info->del_set.dim > IPSET_DIM_MAX ||
             info->map_set.dim > IPSET_DIM_MAX) {
-                pr_warn("Protocol error: SET target dimension is over the limit!\n");
+                pr_info_ratelimited("SET target dimension over the limit!\n");
                 if (info->add_set.index != IPSET_INVALID_ID)
                         ip_set_nfnl_put(par->net, info->add_set.index);
                 if (info->del_set.index != IPSET_INVALID_ID)
diff --git a/net/netfilter/xt_socket.c b/net/netfilter/xt_socket.c
index 575d2153e3b8..2ac7f674d19b 100644
--- a/net/netfilter/xt_socket.c
+++ b/net/netfilter/xt_socket.c
@@ -171,7 +171,8 @@ static int socket_mt_v1_check(const struct xt_mtchk_param *par)
                 return err;
 
         if (info->flags & ~XT_SOCKET_FLAGS_V1) {
-                pr_info("unknown flags 0x%x\n", info->flags & ~XT_SOCKET_FLAGS_V1);
+                pr_info_ratelimited("unknown flags 0x%x\n",
+                                    info->flags & ~XT_SOCKET_FLAGS_V1);
                 return -EINVAL;
         }
         return 0;
@@ -187,7 +188,8 @@ static int socket_mt_v2_check(const struct xt_mtchk_param *par)
                 return err;
 
         if (info->flags & ~XT_SOCKET_FLAGS_V2) {
-                pr_info("unknown flags 0x%x\n", info->flags & ~XT_SOCKET_FLAGS_V2);
+                pr_info_ratelimited("unknown flags 0x%x\n",
+                                    info->flags & ~XT_SOCKET_FLAGS_V2);
                 return -EINVAL;
         }
         return 0;
@@ -203,8 +205,8 @@ static int socket_mt_v3_check(const struct xt_mtchk_param *par)
         if (err)
                 return err;
         if (info->flags & ~XT_SOCKET_FLAGS_V3) {
-                pr_info("unknown flags 0x%x\n",
-                        info->flags & ~XT_SOCKET_FLAGS_V3);
+                pr_info_ratelimited("unknown flags 0x%x\n",
+                                    info->flags & ~XT_SOCKET_FLAGS_V3);
                 return -EINVAL;
         }
         return 0;
diff --git a/net/netfilter/xt_state.c b/net/netfilter/xt_state.c
index 5fbd79194d21..0b41c0befe3c 100644
--- a/net/netfilter/xt_state.c
+++ b/net/netfilter/xt_state.c
@@ -44,8 +44,8 @@ static int state_mt_check(const struct xt_mtchk_param *par)
 
         ret = nf_ct_netns_get(par->net, par->family);
         if (ret < 0)
-                pr_info("cannot load conntrack support for proto=%u\n",
-                        par->family);
+                pr_info_ratelimited("cannot load conntrack support for proto=%u\n",
+                                    par->family);
         return ret;
 }
 
diff --git a/net/netfilter/xt_time.c b/net/netfilter/xt_time.c
index 1b01eec1fbda..0160f505e337 100644
--- a/net/netfilter/xt_time.c
+++ b/net/netfilter/xt_time.c
@@ -235,13 +235,13 @@ static int time_mt_check(const struct xt_mtchk_param *par)
 
         if (info->daytime_start > XT_TIME_MAX_DAYTIME ||
             info->daytime_stop > XT_TIME_MAX_DAYTIME) {
-                pr_info("invalid argument - start or "
-                        "stop time greater than 23:59:59\n");
+                pr_info_ratelimited("invalid argument - start or stop time greater than 23:59:59\n");
                 return -EDOM;
         }
 
         if (info->flags & ~XT_TIME_ALL_FLAGS) {
-                pr_info("unknown flags 0x%x\n", info->flags & ~XT_TIME_ALL_FLAGS);
+                pr_info_ratelimited("unknown flags 0x%x\n",
+                                    info->flags & ~XT_TIME_ALL_FLAGS);
                 return -EINVAL;
         }
 
diff --git a/net/netlink/af_netlink.c b/net/netlink/af_netlink.c
index 2ad445c1d27c..07e8478068f0 100644
--- a/net/netlink/af_netlink.c
+++ b/net/netlink/af_netlink.c
@@ -2308,7 +2308,7 @@ int __netlink_dump_start(struct sock *ssk, struct sk_buff *skb,
         if (cb->start) {
                 ret = cb->start(cb);
                 if (ret)
-                        goto error_unlock;
+                        goto error_put;
         }
 
         nlk->cb_running = true;
@@ -2328,6 +2328,8 @@ int __netlink_dump_start(struct sock *ssk, struct sk_buff *skb,
          */
         return -EINTR;
 
+error_put:
+        module_put(control->module);
 error_unlock:
         sock_put(sk);
         mutex_unlock(nlk->cb_mutex);
diff --git a/net/nfc/llcp_commands.c b/net/nfc/llcp_commands.c
index 367d8c027101..2ceefa183cee 100644
--- a/net/nfc/llcp_commands.c
+++ b/net/nfc/llcp_commands.c
@@ -149,6 +149,10 @@ struct nfc_llcp_sdp_tlv *nfc_llcp_build_sdreq_tlv(u8 tid, char *uri,
 
         pr_debug("uri: %s, len: %zu\n", uri, uri_len);
 
+        /* sdreq->tlv_len is u8, takes uri_len, + 3 for header, + 1 for NULL */
+        if (WARN_ON_ONCE(uri_len > U8_MAX - 4))
+                return NULL;
+
         sdreq = kzalloc(sizeof(struct nfc_llcp_sdp_tlv), GFP_KERNEL);
         if (sdreq == NULL)
                 return NULL;
diff --git a/net/nfc/netlink.c b/net/nfc/netlink.c
index c0b83dc9d993..f018eafc2a0d 100644
--- a/net/nfc/netlink.c
+++ b/net/nfc/netlink.c
@@ -61,7 +61,8 @@ static const struct nla_policy nfc_genl_policy[NFC_ATTR_MAX + 1] = {
 };
 
 static const struct nla_policy nfc_sdp_genl_policy[NFC_SDP_ATTR_MAX + 1] = {
-        [NFC_SDP_ATTR_URI] = { .type = NLA_STRING },
+        [NFC_SDP_ATTR_URI] = { .type = NLA_STRING,
+                               .len = U8_MAX - 4 },
         [NFC_SDP_ATTR_SAP] = { .type = NLA_U8 },
 };
 
diff --git a/net/rds/connection.c b/net/rds/connection.c
index 94e190febfdd..2da3176bf792 100644
--- a/net/rds/connection.c
+++ b/net/rds/connection.c
@@ -224,7 +224,7 @@ static struct rds_connection *__rds_conn_create(struct net *net,
         if (rds_destroy_pending(conn))
                 ret = -ENETDOWN;
         else
-                ret = trans->conn_alloc(conn, gfp);
+                ret = trans->conn_alloc(conn, GFP_ATOMIC);
         if (ret) {
                 rcu_read_unlock();
                 kfree(conn->c_path);
diff --git a/net/rxrpc/output.c b/net/rxrpc/output.c
index 42410e910aff..cf73dc006c3b 100644
--- a/net/rxrpc/output.c
+++ b/net/rxrpc/output.c
@@ -445,7 +445,7 @@ send_fragmentable:
                                         (char *)&opt, sizeof(opt));
                 if (ret == 0) {
                         ret = kernel_sendmsg(conn->params.local->socket, &msg,
-                                             iov, 1, iov[0].iov_len);
+                                             iov, 2, len);
 
                         opt = IPV6_PMTUDISC_DO;
                         kernel_setsockopt(conn->params.local->socket,
diff --git a/net/rxrpc/recvmsg.c b/net/rxrpc/recvmsg.c
index cc21e8db25b0..9d45d8b56744 100644
--- a/net/rxrpc/recvmsg.c
+++ b/net/rxrpc/recvmsg.c
@@ -517,9 +517,10 @@ try_again:
                         ret = put_cmsg(msg, SOL_RXRPC, RXRPC_USER_CALL_ID,
                                        sizeof(unsigned int), &id32);
                 } else {
+                        unsigned long idl = call->user_call_ID;
+
                         ret = put_cmsg(msg, SOL_RXRPC, RXRPC_USER_CALL_ID,
-                                       sizeof(unsigned long),
-                                       &call->user_call_ID);
+                                       sizeof(unsigned long), &idl);
                 }
                 if (ret < 0)
                         goto error_unlock_call;
diff --git a/net/sched/cls_api.c b/net/sched/cls_api.c
index 2bc1bc23d42e..247b7cc20c13 100644
--- a/net/sched/cls_api.c
+++ b/net/sched/cls_api.c
@@ -376,17 +376,12 @@ struct tcf_net {
 static unsigned int tcf_net_id;
 
 static int tcf_block_insert(struct tcf_block *block, struct net *net,
-                            u32 block_index, struct netlink_ext_ack *extack)
+                            struct netlink_ext_ack *extack)
 {
         struct tcf_net *tn = net_generic(net, tcf_net_id);
-        int err;
 
-        err = idr_alloc_u32(&tn->idr, block, &block_index, block_index,
-                            GFP_KERNEL);
-        if (err)
-                return err;
-        block->index = block_index;
-        return 0;
+        return idr_alloc_u32(&tn->idr, block, &block->index, block->index,
+                             GFP_KERNEL);
 }
 
 static void tcf_block_remove(struct tcf_block *block, struct net *net)
@@ -397,6 +392,7 @@ static void tcf_block_remove(struct tcf_block *block, struct net *net)
 }
 
 static struct tcf_block *tcf_block_create(struct net *net, struct Qdisc *q,
+                                          u32 block_index,
                                           struct netlink_ext_ack *extack)
 {
         struct tcf_block *block;
@@ -419,10 +415,13 @@ static struct tcf_block *tcf_block_create(struct net *net, struct Qdisc *q,
                 err = -ENOMEM;
                 goto err_chain_create;
         }
-        block->net = qdisc_net(q);
         block->refcnt = 1;
         block->net = net;
-        block->q = q;
+        block->index = block_index;
+
+        /* Don't store q pointer for blocks which are shared */
+        if (!tcf_block_shared(block))
+                block->q = q;
         return block;
 
 err_chain_create:
@@ -518,13 +517,12 @@ int tcf_block_get_ext(struct tcf_block **p_block, struct Qdisc *q,
         }
 
         if (!block) {
-                block = tcf_block_create(net, q, extack);
+                block = tcf_block_create(net, q, ei->block_index, extack);
                 if (IS_ERR(block))
                         return PTR_ERR(block);
                 created = true;
-                if (ei->block_index) {
-                        err = tcf_block_insert(block, net,
-                                               ei->block_index, extack);
+                if (tcf_block_shared(block)) {
+                        err = tcf_block_insert(block, net, extack);
                         if (err)
                                 goto err_block_insert;
                 }
@@ -1399,13 +1397,18 @@ static int tc_dump_tfilter(struct sk_buff *skb, struct netlink_callback *cb)
                     nla_get_u32(tca[TCA_CHAIN]) != chain->index)
                         continue;
                 if (!tcf_chain_dump(chain, q, parent, skb, cb,
-                                    index_start, &index))
+                                    index_start, &index)) {
+                        err = -EMSGSIZE;
                         break;
+                }
         }
 
         cb->args[0] = index;
 
 out:
+        /* If we did no progress, the error (EMSGSIZE) is real */
+        if (skb->len == 0 && err)
+                return err;
         return skb->len;
 }
 
diff --git a/net/sched/cls_u32.c b/net/sched/cls_u32.c
index 6c7601a530e3..ed8b6a24b9e9 100644
--- a/net/sched/cls_u32.c
+++ b/net/sched/cls_u32.c
@@ -96,7 +96,7 @@ struct tc_u_hnode {
 
 struct tc_u_common {
         struct tc_u_hnode __rcu *hlist;
-        struct tcf_block        *block;
+        void                    *ptr;
         int                     refcnt;
         struct idr              handle_idr;
         struct hlist_node       hnode;
@@ -330,9 +330,25 @@ static struct hlist_head *tc_u_common_hash;
 #define U32_HASH_SHIFT 10
 #define U32_HASH_SIZE (1 << U32_HASH_SHIFT)
 
+static void *tc_u_common_ptr(const struct tcf_proto *tp)
+{
+        struct tcf_block *block = tp->chain->block;
+
+        /* The block sharing is currently supported only
+         * for classless qdiscs. In that case we use block
+         * for tc_u_common identification. In case the
+         * block is not shared, block->q is a valid pointer
+         * and we can use that. That works for classful qdiscs.
+         */
+        if (tcf_block_shared(block))
+                return block;
+        else
+                return block->q;
+}
+
 static unsigned int tc_u_hash(const struct tcf_proto *tp)
 {
-        return hash_ptr(tp->chain->block, U32_HASH_SHIFT);
+        return hash_ptr(tc_u_common_ptr(tp), U32_HASH_SHIFT);
 }
 
 static struct tc_u_common *tc_u_common_find(const struct tcf_proto *tp)
@@ -342,7 +358,7 @@ static struct tc_u_common *tc_u_common_find(const struct tcf_proto *tp)
 
         h = tc_u_hash(tp);
         hlist_for_each_entry(tc, &tc_u_common_hash[h], hnode) {
-                if (tc->block == tp->chain->block)
+                if (tc->ptr == tc_u_common_ptr(tp))
                         return tc;
         }
         return NULL;
@@ -371,7 +387,7 @@ static int u32_init(struct tcf_proto *tp)
                         kfree(root_ht);
                         return -ENOBUFS;
                 }
-                tp_c->block = tp->chain->block;
+                tp_c->ptr = tc_u_common_ptr(tp);
                 INIT_HLIST_NODE(&tp_c->hnode);
                 idr_init(&tp_c->handle_idr);
 
diff --git a/net/sctp/debug.c b/net/sctp/debug.c
index 291c97b07058..8f6c2e8c0953 100644
--- a/net/sctp/debug.c
+++ b/net/sctp/debug.c
@@ -81,6 +81,12 @@ const char *sctp_cname(const union sctp_subtype cid)
         case SCTP_CID_RECONF:
                 return "RECONF";
 
+        case SCTP_CID_I_DATA:
+                return "I_DATA";
+
+        case SCTP_CID_I_FWD_TSN:
+                return "I_FWD_TSN";
+
         default:
                 break;
         }
diff --git a/net/sctp/input.c b/net/sctp/input.c
index 141c9c466ec1..0247cc432e02 100644
--- a/net/sctp/input.c
+++ b/net/sctp/input.c
@@ -897,15 +897,12 @@ int sctp_hash_transport(struct sctp_transport *t)
         rhl_for_each_entry_rcu(transport, tmp, list, node)
                 if (transport->asoc->ep == t->asoc->ep) {
                         rcu_read_unlock();
-                        err = -EEXIST;
-                        goto out;
+                        return -EEXIST;
                 }
         rcu_read_unlock();
 
         err = rhltable_insert_key(&sctp_transport_hashtable, &arg,
                                   &t->node, sctp_hash_params);
-
-out:
         if (err)
                 pr_err_once("insert transport fail, errno %d\n", err);
 
diff --git a/net/sctp/stream.c b/net/sctp/stream.c
index cedf672487f9..f799043abec9 100644
--- a/net/sctp/stream.c
+++ b/net/sctp/stream.c
@@ -6,7 +6,7 @@
  *
  * This file is part of the SCTP kernel implementation
  *
- * These functions manipulate sctp tsn mapping array.
+ * This file contains sctp stream maniuplation primitives and helpers.
  *
  * This SCTP implementation is free software;
  * you can redistribute it and/or modify it under the terms of
diff --git a/net/sctp/stream_interleave.c b/net/sctp/stream_interleave.c
index 8c7cf8f08711..d3764c181299 100644
--- a/net/sctp/stream_interleave.c
+++ b/net/sctp/stream_interleave.c
@@ -3,7 +3,8 @@
  *
  * This file is part of the SCTP kernel implementation
  *
- * These functions manipulate sctp stream queue/scheduling.
+ * These functions implement sctp stream message interleaving, mostly
+ * including I-DATA and I-FORWARD-TSN chunks process.
  *
  * This SCTP implementation is free software;
  * you can redistribute it and/or modify it under the terms of
@@ -954,12 +955,8 @@ static void sctp_renege_events(struct sctp_ulpq *ulpq, struct sctp_chunk *chunk,
         __u32 freed = 0;
         __u16 needed;
 
-        if (chunk) {
-                needed = ntohs(chunk->chunk_hdr->length);
-                needed -= sizeof(struct sctp_idata_chunk);
-        } else {
-                needed = SCTP_DEFAULT_MAXWINDOW;
-        }
+        needed = ntohs(chunk->chunk_hdr->length) -
+                 sizeof(struct sctp_idata_chunk);
 
         if (skb_queue_empty(&asoc->base.sk->sk_receive_queue)) {
                 freed = sctp_ulpq_renege_list(ulpq, &ulpq->lobby, needed);
@@ -971,9 +968,8 @@ static void sctp_renege_events(struct sctp_ulpq *ulpq, struct sctp_chunk *chunk,
                                                        needed);
         }
 
-        if (chunk && freed >= needed)
-                if (sctp_ulpevent_idata(ulpq, chunk, gfp) <= 0)
-                        sctp_intl_start_pd(ulpq, gfp);
+        if (freed >= needed && sctp_ulpevent_idata(ulpq, chunk, gfp) <= 0)
+                sctp_intl_start_pd(ulpq, gfp);
 
         sk_mem_reclaim(asoc->base.sk);
 }
diff --git a/net/tipc/bearer.c b/net/tipc/bearer.c
index c8001471da6c..3e3dce3d4c63 100644
--- a/net/tipc/bearer.c
+++ b/net/tipc/bearer.c
@@ -813,7 +813,7 @@ err_out:
         return err;
 }
 
-int tipc_nl_bearer_disable(struct sk_buff *skb, struct genl_info *info)
+int __tipc_nl_bearer_disable(struct sk_buff *skb, struct genl_info *info)
 {
         int err;
         char *name;
@@ -835,20 +835,27 @@ int tipc_nl_bearer_disable(struct sk_buff *skb, struct genl_info *info)
 
         name = nla_data(attrs[TIPC_NLA_BEARER_NAME]);
 
-        rtnl_lock();
         bearer = tipc_bearer_find(net, name);
-        if (!bearer) {
-                rtnl_unlock();
+        if (!bearer)
                 return -EINVAL;
-        }
 
         bearer_disable(net, bearer);
-        rtnl_unlock();
 
         return 0;
 }
 
-int tipc_nl_bearer_enable(struct sk_buff *skb, struct genl_info *info)
+int tipc_nl_bearer_disable(struct sk_buff *skb, struct genl_info *info)
+{
+        int err;
+
+        rtnl_lock();
+        err = __tipc_nl_bearer_disable(skb, info);
+        rtnl_unlock();
+
+        return err;
+}
+
+int __tipc_nl_bearer_enable(struct sk_buff *skb, struct genl_info *info)
 {
         int err;
         char *bearer;
@@ -890,15 +897,18 @@ int tipc_nl_bearer_enable(struct sk_buff *skb, struct genl_info *info)
                         prio = nla_get_u32(props[TIPC_NLA_PROP_PRIO]);
         }
 
+        return tipc_enable_bearer(net, bearer, domain, prio, attrs);
+}
+
+int tipc_nl_bearer_enable(struct sk_buff *skb, struct genl_info *info)
+{
+        int err;
+
         rtnl_lock();
-        err = tipc_enable_bearer(net, bearer, domain, prio, attrs);
-        if (err) {
-                rtnl_unlock();
-                return err;
-        }
+        err = __tipc_nl_bearer_enable(skb, info);
         rtnl_unlock();
 
-        return 0;
+        return err;
 }
 
 int tipc_nl_bearer_add(struct sk_buff *skb, struct genl_info *info)
@@ -944,7 +954,7 @@ int tipc_nl_bearer_add(struct sk_buff *skb, struct genl_info *info)
         return 0;
 }
 
-int tipc_nl_bearer_set(struct sk_buff *skb, struct genl_info *info)
+int __tipc_nl_bearer_set(struct sk_buff *skb, struct genl_info *info)
 {
         int err;
         char *name;
@@ -965,22 +975,17 @@ int tipc_nl_bearer_set(struct sk_buff *skb, struct genl_info *info)
                 return -EINVAL;
         name = nla_data(attrs[TIPC_NLA_BEARER_NAME]);
 
-        rtnl_lock();
         b = tipc_bearer_find(net, name);
-        if (!b) {
-                rtnl_unlock();
+        if (!b)
                 return -EINVAL;
-        }
 
         if (attrs[TIPC_NLA_BEARER_PROP]) {
                 struct nlattr *props[TIPC_NLA_PROP_MAX + 1];
 
                 err = tipc_nl_parse_link_prop(attrs[TIPC_NLA_BEARER_PROP],
                                               props);
-                if (err) {
-                        rtnl_unlock();
+                if (err)
                         return err;
-                }
 
                 if (props[TIPC_NLA_PROP_TOL])
                         b->tolerance = nla_get_u32(props[TIPC_NLA_PROP_TOL]);
@@ -989,11 +994,21 @@ int tipc_nl_bearer_set(struct sk_buff *skb, struct genl_info *info)
                 if (props[TIPC_NLA_PROP_WIN])
                         b->window = nla_get_u32(props[TIPC_NLA_PROP_WIN]);
         }
-        rtnl_unlock();
 
         return 0;
 }
 
+int tipc_nl_bearer_set(struct sk_buff *skb, struct genl_info *info)
+{
+        int err;
+
+        rtnl_lock();
+        err = __tipc_nl_bearer_set(skb, info);
+        rtnl_unlock();
+
+        return err;
+}
+
 static int __tipc_nl_add_media(struct tipc_nl_msg *msg,
                                struct tipc_media *media, int nlflags)
 {
@@ -1115,7 +1130,7 @@ err_out:
         return err;
 }
 
-int tipc_nl_media_set(struct sk_buff *skb, struct genl_info *info)
+int __tipc_nl_media_set(struct sk_buff *skb, struct genl_info *info)
 {
         int err;
         char *name;
@@ -1133,22 +1148,17 @@ int tipc_nl_media_set(struct sk_buff *skb, struct genl_info *info)
                 return -EINVAL;
         name = nla_data(attrs[TIPC_NLA_MEDIA_NAME]);
 
-        rtnl_lock();
         m = tipc_media_find(name);
-        if (!m) {
-                rtnl_unlock();
+        if (!m)
                 return -EINVAL;
-        }
 
         if (attrs[TIPC_NLA_MEDIA_PROP]) {
                 struct nlattr *props[TIPC_NLA_PROP_MAX + 1];
 
                 err = tipc_nl_parse_link_prop(attrs[TIPC_NLA_MEDIA_PROP],
                                               props);
-                if (err) {
-                        rtnl_unlock();
+                if (err)
                         return err;
-                }
 
                 if (props[TIPC_NLA_PROP_TOL])
                         m->tolerance = nla_get_u32(props[TIPC_NLA_PROP_TOL]);
@@ -1157,7 +1167,17 @@ int tipc_nl_media_set(struct sk_buff *skb, struct genl_info *info)
                 if (props[TIPC_NLA_PROP_WIN])
                         m->window = nla_get_u32(props[TIPC_NLA_PROP_WIN]);
         }
-        rtnl_unlock();
 
         return 0;
 }
+
+int tipc_nl_media_set(struct sk_buff *skb, struct genl_info *info)
+{
+        int err;
+
+        rtnl_lock();
+        err = __tipc_nl_media_set(skb, info);
+        rtnl_unlock();
+
+        return err;
+}
diff --git a/net/tipc/bearer.h b/net/tipc/bearer.h
index 42d6eeeb646d..a53613d95bc9 100644
--- a/net/tipc/bearer.h
+++ b/net/tipc/bearer.h
@@ -188,15 +188,19 @@ extern struct tipc_media udp_media_info;
 #endif
 
 int tipc_nl_bearer_disable(struct sk_buff *skb, struct genl_info *info);
+int __tipc_nl_bearer_disable(struct sk_buff *skb, struct genl_info *info);
 int tipc_nl_bearer_enable(struct sk_buff *skb, struct genl_info *info);
+int __tipc_nl_bearer_enable(struct sk_buff *skb, struct genl_info *info);
 int tipc_nl_bearer_dump(struct sk_buff *skb, struct netlink_callback *cb);
 int tipc_nl_bearer_get(struct sk_buff *skb, struct genl_info *info);
 int tipc_nl_bearer_set(struct sk_buff *skb, struct genl_info *info);
+int __tipc_nl_bearer_set(struct sk_buff *skb, struct genl_info *info);
 int tipc_nl_bearer_add(struct sk_buff *skb, struct genl_info *info);
 
 int tipc_nl_media_dump(struct sk_buff *skb, struct netlink_callback *cb);
 int tipc_nl_media_get(struct sk_buff *skb, struct genl_info *info);
 int tipc_nl_media_set(struct sk_buff *skb, struct genl_info *info);
+int __tipc_nl_media_set(struct sk_buff *skb, struct genl_info *info);
 
 int tipc_media_set_priority(const char *name, u32 new_value);
 int tipc_media_set_window(const char *name, u32 new_value);
diff --git a/net/tipc/net.c b/net/tipc/net.c
index 719c5924b638..1a2fde0d6f61 100644
--- a/net/tipc/net.c
+++ b/net/tipc/net.c
@@ -200,7 +200,7 @@ out:
         return skb->len;
 }
 
-int tipc_nl_net_set(struct sk_buff *skb, struct genl_info *info)
+int __tipc_nl_net_set(struct sk_buff *skb, struct genl_info *info)
 {
         struct net *net = sock_net(skb->sk);
         struct tipc_net *tn = net_generic(net, tipc_net_id);
@@ -241,10 +241,19 @@ int tipc_nl_net_set(struct sk_buff *skb, struct genl_info *info)
                 if (!tipc_addr_node_valid(addr))
                         return -EINVAL;
 
-                rtnl_lock();
                 tipc_net_start(net, addr);
-                rtnl_unlock();
         }
 
         return 0;
 }
+
+int tipc_nl_net_set(struct sk_buff *skb, struct genl_info *info)
+{
+        int err;
+
+        rtnl_lock();
+        err = __tipc_nl_net_set(skb, info);
+        rtnl_unlock();
+
+        return err;
+}
diff --git a/net/tipc/net.h b/net/tipc/net.h
index c7c254902873..c0306aa2374b 100644
--- a/net/tipc/net.h
+++ b/net/tipc/net.h
@@ -47,5 +47,6 @@ void tipc_net_stop(struct net *net);
 
 int tipc_nl_net_dump(struct sk_buff *skb, struct netlink_callback *cb);
 int tipc_nl_net_set(struct sk_buff *skb, struct genl_info *info);
+int __tipc_nl_net_set(struct sk_buff *skb, struct genl_info *info);
 
 #endif
diff --git a/net/tipc/netlink_compat.c b/net/tipc/netlink_compat.c
index e48f0b2c01b9..4492cda45566 100644
--- a/net/tipc/netlink_compat.c
+++ b/net/tipc/netlink_compat.c
@@ -285,10 +285,6 @@ static int __tipc_nl_compat_doit(struct tipc_nl_compat_cmd_doit *cmd,
         if (!trans_buf)
                 return -ENOMEM;
 
-        err = (*cmd->transcode)(cmd, trans_buf, msg);
-        if (err)
-                goto trans_out;
-
         attrbuf = kmalloc((tipc_genl_family.maxattr + 1) *
                         sizeof(struct nlattr *), GFP_KERNEL);
         if (!attrbuf) {
@@ -296,27 +292,34 @@ static int __tipc_nl_compat_doit(struct tipc_nl_compat_cmd_doit *cmd,
                 goto trans_out;
         }
 
-        err = nla_parse(attrbuf, tipc_genl_family.maxattr,
-                        (const struct nlattr *)trans_buf->data,
-                        trans_buf->len, NULL, NULL);
-        if (err)
-                goto parse_out;
-
         doit_buf = alloc_skb(NLMSG_GOODSIZE, GFP_KERNEL);
         if (!doit_buf) {
                 err = -ENOMEM;
-                goto parse_out;
+                goto attrbuf_out;
         }
 
-        doit_buf->sk = msg->dst_sk;
-
         memset(&info, 0, sizeof(info));
         info.attrs = attrbuf;
 
+        rtnl_lock();
+        err = (*cmd->transcode)(cmd, trans_buf, msg);
+        if (err)
+                goto doit_out;
+
+        err = nla_parse(attrbuf, tipc_genl_family.maxattr,
+                        (const struct nlattr *)trans_buf->data,
+                        trans_buf->len, NULL, NULL);
+        if (err)
+                goto doit_out;
+
+        doit_buf->sk = msg->dst_sk;
+
         err = (*cmd->doit)(doit_buf, &info);
+doit_out:
+        rtnl_unlock();
 
         kfree_skb(doit_buf);
-parse_out:
+attrbuf_out:
         kfree(attrbuf);
 trans_out:
         kfree_skb(trans_buf);
@@ -722,13 +725,13 @@ static int tipc_nl_compat_link_set(struct tipc_nl_compat_cmd_doit *cmd,
 
         media = tipc_media_find(lc->name);
         if (media) {
-                cmd->doit = &tipc_nl_media_set;
+                cmd->doit = &__tipc_nl_media_set;
                 return tipc_nl_compat_media_set(skb, msg);
         }
 
         bearer = tipc_bearer_find(msg->net, lc->name);
         if (bearer) {
-                cmd->doit = &tipc_nl_bearer_set;
+                cmd->doit = &__tipc_nl_bearer_set;
                 return tipc_nl_compat_bearer_set(skb, msg);
         }
 
@@ -1089,12 +1092,12 @@ static int tipc_nl_compat_handle(struct tipc_nl_compat_msg *msg)
                 return tipc_nl_compat_dumpit(&dump, msg);
         case TIPC_CMD_ENABLE_BEARER:
                 msg->req_type = TIPC_TLV_BEARER_CONFIG;
-                doit.doit = tipc_nl_bearer_enable;
+                doit.doit = __tipc_nl_bearer_enable;
                 doit.transcode = tipc_nl_compat_bearer_enable;
                 return tipc_nl_compat_doit(&doit, msg);
         case TIPC_CMD_DISABLE_BEARER:
                 msg->req_type = TIPC_TLV_BEARER_NAME;
-                doit.doit = tipc_nl_bearer_disable;
+                doit.doit = __tipc_nl_bearer_disable;
                 doit.transcode = tipc_nl_compat_bearer_disable;
                 return tipc_nl_compat_doit(&doit, msg);
         case TIPC_CMD_SHOW_LINK_STATS:
@@ -1148,12 +1151,12 @@ static int tipc_nl_compat_handle(struct tipc_nl_compat_msg *msg)
                 return tipc_nl_compat_dumpit(&dump, msg);
         case TIPC_CMD_SET_NODE_ADDR:
                 msg->req_type = TIPC_TLV_NET_ADDR;
-                doit.doit = tipc_nl_net_set;
+                doit.doit = __tipc_nl_net_set;
                 doit.transcode = tipc_nl_compat_net_set;
                 return tipc_nl_compat_doit(&doit, msg);
         case TIPC_CMD_SET_NETID:
                 msg->req_type = TIPC_TLV_UNSIGNED;
-                doit.doit = tipc_nl_net_set;
+                doit.doit = __tipc_nl_net_set;
                 doit.transcode = tipc_nl_compat_net_set;
                 return tipc_nl_compat_doit(&doit, msg);
         case TIPC_CMD_GET_NETID:
diff --git a/net/tls/tls_main.c b/net/tls/tls_main.c
index b0d5fcea47e7..e9b4b53ab53e 100644
--- a/net/tls/tls_main.c
+++ b/net/tls/tls_main.c
@@ -308,8 +308,11 @@ static int do_tls_getsockopt_tx(struct sock *sk, char __user *optval,
                         goto out;
                 }
                 lock_sock(sk);
-                memcpy(crypto_info_aes_gcm_128->iv, ctx->iv,
+                memcpy(crypto_info_aes_gcm_128->iv,
+                       ctx->iv + TLS_CIPHER_AES_GCM_128_SALT_SIZE,
                        TLS_CIPHER_AES_GCM_128_IV_SIZE);
+                memcpy(crypto_info_aes_gcm_128->rec_seq, ctx->rec_seq,
+                       TLS_CIPHER_AES_GCM_128_REC_SEQ_SIZE);
                 release_sock(sk);
                 if (copy_to_user(optval,
                                  crypto_info_aes_gcm_128,
@@ -375,7 +378,7 @@ static int do_tls_setsockopt_tx(struct sock *sk, char __user *optval,
         rc = copy_from_user(crypto_info, optval, sizeof(*crypto_info));
         if (rc) {
                 rc = -EFAULT;
-                goto out;
+                goto err_crypto_info;
         }
 
         /* check version */
diff --git a/net/unix/af_unix.c b/net/unix/af_unix.c
index d545e1d0dea2..2d465bdeccbc 100644
--- a/net/unix/af_unix.c
+++ b/net/unix/af_unix.c
@@ -1825,7 +1825,7 @@ out:
 }
 
 /* We use paged skbs for stream sockets, and limit occupancy to 32768
- * bytes, and a minimun of a full page.
+ * bytes, and a minimum of a full page.
  */
 #define UNIX_SKB_FRAGS_SZ (PAGE_SIZE << get_order(32768))
 
diff --git a/net/wireless/mesh.c b/net/wireless/mesh.c
index 51aa55618ef7..b12da6ef3c12 100644
--- a/net/wireless/mesh.c
+++ b/net/wireless/mesh.c
@@ -170,9 +170,28 @@ int __cfg80211_join_mesh(struct cfg80211_registered_device *rdev,
                 enum nl80211_bss_scan_width scan_width;
                 struct ieee80211_supported_band *sband =
                                 rdev->wiphy.bands[setup->chandef.chan->band];
-                scan_width = cfg80211_chandef_to_scan_width(&setup->chandef);
-                setup->basic_rates = ieee80211_mandatory_rates(sband,
-                                                               scan_width);
+
+                if (setup->chandef.chan->band == NL80211_BAND_2GHZ) {
+                        int i;
+
+                        /*
+                         * Older versions selected the mandatory rates for
+                         * 2.4 GHz as well, but were broken in that only
+                         * 1 Mbps was regarded as a mandatory rate. Keep
+                         * using just 1 Mbps as the default basic rate for
+                         * mesh to be interoperable with older versions.
+                         */
+                        for (i = 0; i < sband->n_bitrates; i++) {
+                                if (sband->bitrates[i].bitrate == 10) {
+                                        setup->basic_rates = BIT(i);
+                                        break;
+                                }
+                        }
+                } else {
+                        scan_width = cfg80211_chandef_to_scan_width(&setup->chandef);
+                        setup->basic_rates = ieee80211_mandatory_rates(sband,
+                                                                       scan_width);
+                }
         }
 
         err = cfg80211_chandef_dfs_required(&rdev->wiphy,
diff --git a/net/wireless/sme.c b/net/wireless/sme.c
index fdb3646274a5..701cfd7acc1b 100644
--- a/net/wireless/sme.c
+++ b/net/wireless/sme.c
@@ -1032,6 +1032,8 @@ void __cfg80211_disconnected(struct net_device *dev, const u8 *ie,
         wdev->current_bss = NULL;
         wdev->ssid_len = 0;
         wdev->conn_owner_nlportid = 0;
+        kzfree(wdev->connect_keys);
+        wdev->connect_keys = NULL;
 
         nl80211_send_disconnected(rdev, dev, reason, ie, ie_len, from_ap);
 
diff --git a/samples/seccomp/Makefile b/samples/seccomp/Makefile
index 0e349b80686e..ba942e3ead89 100644
--- a/samples/seccomp/Makefile
+++ b/samples/seccomp/Makefile
@@ -1,4 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0
+ifndef CROSS_COMPILE
 hostprogs-$(CONFIG_SAMPLE_SECCOMP) := bpf-fancy dropper bpf-direct
 
 HOSTCFLAGS_bpf-fancy.o += -I$(objtree)/usr/include
@@ -16,7 +17,6 @@ HOSTCFLAGS_bpf-direct.o += -idirafter $(objtree)/include
 bpf-direct-objs := bpf-direct.o
 
 # Try to match the kernel target.
-ifndef CROSS_COMPILE
 ifndef CONFIG_64BIT
 
 # s390 has -m31 flag to build 31 bit binaries
@@ -35,12 +35,4 @@ HOSTLOADLIBES_bpf-fancy += $(MFLAG)
 HOSTLOADLIBES_dropper += $(MFLAG)
 endif
 always := $(hostprogs-m)
-else
-# MIPS system calls are defined based on the -mabi that is passed
-# to the toolchain which may or may not be a valid option
-# for the host toolchain. So disable tests if target architecture
-# is MIPS but the host isn't.
-ifndef CONFIG_MIPS
-always := $(hostprogs-m)
-endif
 endif
diff --git a/scripts/Makefile.build b/scripts/Makefile.build
index 47cddf32aeba..4f2b25d43ec9 100644
--- a/scripts/Makefile.build
+++ b/scripts/Makefile.build
@@ -256,6 +256,8 @@ __objtool_obj := $(objtree)/tools/objtool/objtool
 
 objtool_args = $(if $(CONFIG_UNWINDER_ORC),orc generate,check)
 
+objtool_args += $(if $(part-of-module), --module,)
+
 ifndef CONFIG_FRAME_POINTER
 objtool_args += --no-fp
 endif
@@ -264,6 +266,12 @@ objtool_args += --no-unreachable
 else
 objtool_args += $(call cc-ifversion, -lt, 0405, --no-unreachable)
 endif
+ifdef CONFIG_RETPOLINE
+ifneq ($(RETPOLINE_CFLAGS),)
+  objtool_args += --retpoline
+endif
+endif
+
 
 ifdef CONFIG_MODVERSIONS
 objtool_o = $(@D)/.tmp_$(@F)
diff --git a/scripts/coccinelle/api/memdup.cocci b/scripts/coccinelle/api/memdup.cocci
index 1249b727644b..8fd6437beda8 100644
--- a/scripts/coccinelle/api/memdup.cocci
+++ b/scripts/coccinelle/api/memdup.cocci
@@ -56,10 +56,10 @@ statement S;
 p << r.p;
 @@
 
-coccilib.org.print_todo(p[0], "WARNING opportunity for kmemdep")
+coccilib.org.print_todo(p[0], "WARNING opportunity for kmemdup")
 
 @script:python depends on report@
 p << r.p;
 @@
 
-coccilib.report.print_report(p[0], "WARNING opportunity for kmemdep")
+coccilib.report.print_report(p[0], "WARNING opportunity for kmemdup")
diff --git a/scripts/kallsyms.c b/scripts/kallsyms.c
index 9ee9bf7fd1a2..65792650c630 100644
--- a/scripts/kallsyms.c
+++ b/scripts/kallsyms.c
@@ -595,7 +595,7 @@ static void optimize_result(void)
                  * original char code */
                 if (!best_table_len[i]) {
 
-                        /* find the token with the breates profit value */
+                        /* find the token with the best profit value */
                         best = find_best_token();
                         if (token_profit[best] == 0)
                                 break;
diff --git a/scripts/kconfig/confdata.c b/scripts/kconfig/confdata.c
index 5c12dc91ef34..df26c7b0fe13 100644
--- a/scripts/kconfig/confdata.c
+++ b/scripts/kconfig/confdata.c
@@ -178,7 +178,7 @@ static int conf_set_sym_val(struct symbol *sym, int def, int def_flags, char *p)
         case S_HEX:
         done:
                 if (sym_string_valid(sym, p)) {
-                        sym->def[def].val = strdup(p);
+                        sym->def[def].val = xstrdup(p);
                         sym->flags |= def_flags;
                 } else {
                         if (def != S_DEF_AUTO)
diff --git a/scripts/kconfig/kxgettext.c b/scripts/kconfig/kxgettext.c
index 2858738b22d5..240880a89111 100644
--- a/scripts/kconfig/kxgettext.c
+++ b/scripts/kconfig/kxgettext.c
@@ -101,7 +101,7 @@ static struct message *message__new(const char *msg, char *option,
         if (self->files == NULL)
                 goto out_fail;
 
-        self->msg = strdup(msg);
+        self->msg = xstrdup(msg);
         if (self->msg == NULL)
                 goto out_fail_msg;
 
diff --git a/scripts/kconfig/lkc.h b/scripts/kconfig/lkc.h
index 4e23febbe4b2..2d5ec2d0e952 100644
--- a/scripts/kconfig/lkc.h
+++ b/scripts/kconfig/lkc.h
@@ -115,6 +115,7 @@ int file_write_dep(const char *name);
 void *xmalloc(size_t size);
 void *xcalloc(size_t nmemb, size_t size);
 void *xrealloc(void *p, size_t size);
+char *xstrdup(const char *s);
 
 struct gstr {
         size_t len;
diff --git a/scripts/kconfig/lxdialog/check-lxdialog.sh b/scripts/kconfig/lxdialog/check-lxdialog.sh
index a10bd9d6fafd..6c0bcd9c472d 100755
--- a/scripts/kconfig/lxdialog/check-lxdialog.sh
+++ b/scripts/kconfig/lxdialog/check-lxdialog.sh
@@ -55,7 +55,8 @@ EOF
             echo " *** required header files."                            1>&2
             echo " *** 'make menuconfig' requires the ncurses libraries." 1>&2
             echo " *** "                                                  1>&2
-            echo " *** Install ncurses (ncurses-devel) and try again."    1>&2
+            echo " *** Install ncurses (ncurses-devel or libncurses-dev " 1>&2
+            echo " *** depending on your distribution) and try again."    1>&2
             echo " *** "                                                  1>&2
             exit 1
         fi
diff --git a/scripts/kconfig/menu.c b/scripts/kconfig/menu.c
index 99222855544c..36cd3e1f1c28 100644
--- a/scripts/kconfig/menu.c
+++ b/scripts/kconfig/menu.c
@@ -212,6 +212,7 @@ void menu_add_option(int token, char *arg)
                         sym_defconfig_list = current_entry->sym;
                 else if (sym_defconfig_list != current_entry->sym)
                         zconf_error("trying to redefine defconfig symbol");
+                sym_defconfig_list->flags |= SYMBOL_AUTO;
                 break;
         case T_OPT_ENV:
                 prop_add_env(arg);
diff --git a/scripts/kconfig/symbol.c b/scripts/kconfig/symbol.c
index cca9663be5dd..2220bc4b051b 100644
--- a/scripts/kconfig/symbol.c
+++ b/scripts/kconfig/symbol.c
@@ -183,7 +183,7 @@ static void sym_validate_range(struct symbol *sym)
                 sprintf(str, "%lld", val2);
         else
                 sprintf(str, "0x%llx", val2);
-        sym->curr.val = strdup(str);
+        sym->curr.val = xstrdup(str);
 }
 
 static void sym_set_changed(struct symbol *sym)
@@ -849,7 +849,7 @@ struct symbol *sym_lookup(const char *name, int flags)
                                    : !(symbol->flags & (SYMBOL_CONST|SYMBOL_CHOICE))))
                                 return symbol;
                 }
-                new_name = strdup(name);
+                new_name = xstrdup(name);
         } else {
                 new_name = NULL;
                 hash = 0;
diff --git a/scripts/kconfig/util.c b/scripts/kconfig/util.c
index b98a79e30e04..c6f6e21b809f 100644
--- a/scripts/kconfig/util.c
+++ b/scripts/kconfig/util.c
@@ -154,3 +154,14 @@ void *xrealloc(void *p, size_t size)
         fprintf(stderr, "Out of memory.\n");
         exit(1);
 }
+
+char *xstrdup(const char *s)
+{
+        char *p;
+
+        p = strdup(s);
+        if (p)
+                return p;
+        fprintf(stderr, "Out of memory.\n");
+        exit(1);
+}
diff --git a/scripts/kconfig/zconf.l b/scripts/kconfig/zconf.l
index 02de6fe302a9..88b650eb9cc9 100644
--- a/scripts/kconfig/zconf.l
+++ b/scripts/kconfig/zconf.l
@@ -332,16 +332,12 @@ void zconf_nextfile(const char *name)
                                 "Inclusion path:\n  current file : '%s'\n",
                                 zconf_curname(), zconf_lineno(),
                                 zconf_curname());
-                        iter = current_file->parent;
-                        while (iter && \
-                               strcmp(iter->name,current_file->name)) {
-                                fprintf(stderr, "  included from: '%s:%d'\n",
-                                        iter->name, iter->lineno-1);
+                        iter = current_file;
+                        do {
                                 iter = iter->parent;
-                        }
-                        if (iter)
                                 fprintf(stderr, "  included from: '%s:%d'\n",
-                                        iter->name, iter->lineno+1);
+                                        iter->name, iter->lineno - 1);
+                        } while (strcmp(iter->name, current_file->name));
                         exit(1);
                 }
         }
diff --git a/scripts/kconfig/zconf.y b/scripts/kconfig/zconf.y
index 4be98050b961..ad6305b0f40c 100644
--- a/scripts/kconfig/zconf.y
+++ b/scripts/kconfig/zconf.y
@@ -127,7 +127,7 @@ no_mainmenu_stmt: /* empty */
          * later regardless of whether it comes from the 'prompt' in
          * mainmenu_stmt or here
          */
-        menu_add_prompt(P_MENU, strdup("Linux Kernel Configuration"), NULL);
+        menu_add_prompt(P_MENU, xstrdup("Linux Kernel Configuration"), NULL);
 };
 
 
@@ -276,6 +276,7 @@ choice: T_CHOICE word_opt T_EOL
         sym->flags |= SYMBOL_AUTO;
         menu_add_entry(sym);
         menu_add_expr(P_CHOICE, NULL, NULL);
+        free($2);
         printd(DEBUG_PARSE, "%s:%d:choice\n", zconf_curname(), zconf_lineno());
 };
 
diff --git a/scripts/link-vmlinux.sh b/scripts/link-vmlinux.sh
index c0d129d7f430..be56a1153014 100755
--- a/scripts/link-vmlinux.sh
+++ b/scripts/link-vmlinux.sh
@@ -246,7 +246,7 @@ else
 fi;
 
 # final build of init/
-${MAKE} -f "${srctree}/scripts/Makefile.build" obj=init GCC_PLUGINS_CFLAGS="${GCC_PLUGINS_CFLAGS}"
+${MAKE} -f "${srctree}/scripts/Makefile.build" obj=init
 
 archive_builtin
 
diff --git a/security/integrity/digsig.c b/security/integrity/digsig.c
index 6f9e4ce568cd..9bb0a7f2863e 100644
--- a/security/integrity/digsig.c
+++ b/security/integrity/digsig.c
@@ -18,6 +18,7 @@
 #include <linux/cred.h>
 #include <linux/key-type.h>
 #include <linux/digsig.h>
+#include <linux/vmalloc.h>
 #include <crypto/public_key.h>
 #include <keys/system_keyring.h>
 
diff --git a/security/keys/big_key.c b/security/keys/big_key.c
index 929e14978c42..fa728f662a6f 100644
--- a/security/keys/big_key.c
+++ b/security/keys/big_key.c
@@ -22,6 +22,13 @@
 #include <keys/big_key-type.h>
 #include <crypto/aead.h>
 
+struct big_key_buf {
+        unsigned int            nr_pages;
+        void                    *virt;
+        struct scatterlist      *sg;
+        struct page             *pages[];
+};
+
 /*
  * Layout of key payload words.
  */
@@ -91,10 +98,9 @@ static DEFINE_MUTEX(big_key_aead_lock);
 /*
  * Encrypt/decrypt big_key data
  */
-static int big_key_crypt(enum big_key_op op, u8 *data, size_t datalen, u8 *key)
+static int big_key_crypt(enum big_key_op op, struct big_key_buf *buf, size_t datalen, u8 *key)
 {
         int ret;
-        struct scatterlist sgio;
         struct aead_request *aead_req;
         /* We always use a zero nonce. The reason we can get away with this is
          * because we're using a different randomly generated key for every
@@ -109,8 +115,7 @@ static int big_key_crypt(enum big_key_op op, u8 *data, size_t datalen, u8 *key)
                 return -ENOMEM;
 
         memset(zero_nonce, 0, sizeof(zero_nonce));
-        sg_init_one(&sgio, data, datalen + (op == BIG_KEY_ENC ? ENC_AUTHTAG_SIZE : 0));
-        aead_request_set_crypt(aead_req, &sgio, &sgio, datalen, zero_nonce);
+        aead_request_set_crypt(aead_req, buf->sg, buf->sg, datalen, zero_nonce);
         aead_request_set_callback(aead_req, CRYPTO_TFM_REQ_MAY_SLEEP, NULL, NULL);
         aead_request_set_ad(aead_req, 0);
 
@@ -130,21 +135,81 @@ error:
 }
 
 /*
+ * Free up the buffer.
+ */
+static void big_key_free_buffer(struct big_key_buf *buf)
+{
+        unsigned int i;
+
+        if (buf->virt) {
+                memset(buf->virt, 0, buf->nr_pages * PAGE_SIZE);
+                vunmap(buf->virt);
+        }
+
+        for (i = 0; i < buf->nr_pages; i++)
+                if (buf->pages[i])
+                        __free_page(buf->pages[i]);
+
+        kfree(buf);
+}
+
+/*
+ * Allocate a buffer consisting of a set of pages with a virtual mapping
+ * applied over them.
+ */
+static void *big_key_alloc_buffer(size_t len)
+{
+        struct big_key_buf *buf;
+        unsigned int npg = (len + PAGE_SIZE - 1) >> PAGE_SHIFT;
+        unsigned int i, l;
+
+        buf = kzalloc(sizeof(struct big_key_buf) +
+                      sizeof(struct page) * npg +
+                      sizeof(struct scatterlist) * npg,
+                      GFP_KERNEL);
+        if (!buf)
+                return NULL;
+
+        buf->nr_pages = npg;
+        buf->sg = (void *)(buf->pages + npg);
+        sg_init_table(buf->sg, npg);
+
+        for (i = 0; i < buf->nr_pages; i++) {
+                buf->pages[i] = alloc_page(GFP_KERNEL);
+                if (!buf->pages[i])
+                        goto nomem;
+
+                l = min_t(size_t, len, PAGE_SIZE);
+                sg_set_page(&buf->sg[i], buf->pages[i], l, 0);
+                len -= l;
+        }
+
+        buf->virt = vmap(buf->pages, buf->nr_pages, VM_MAP, PAGE_KERNEL);
+        if (!buf->virt)
+                goto nomem;
+
+        return buf;
+
+nomem:
+        big_key_free_buffer(buf);
+        return NULL;
+}
+
+/*
  * Preparse a big key
  */
 int big_key_preparse(struct key_preparsed_payload *prep)
 {
+        struct big_key_buf *buf;
         struct path *path = (struct path *)&prep->payload.data[big_key_path];
         struct file *file;
         u8 *enckey;
-        u8 *data = NULL;
         ssize_t written;
-        size_t datalen = prep->datalen;
+        size_t datalen = prep->datalen, enclen = datalen + ENC_AUTHTAG_SIZE;
         int ret;
 
-        ret = -EINVAL;
         if (datalen <= 0 || datalen > 1024 * 1024 || !prep->data)
-                goto error;
+                return -EINVAL;
 
         /* Set an arbitrary quota */
         prep->quotalen = 16;
@@ -157,13 +222,12 @@ int big_key_preparse(struct key_preparsed_payload *prep)
                  *
                  * File content is stored encrypted with randomly generated key.
                  */
-                size_t enclen = datalen + ENC_AUTHTAG_SIZE;
                 loff_t pos = 0;
 
-                data = kmalloc(enclen, GFP_KERNEL);
-                if (!data)
+                buf = big_key_alloc_buffer(enclen);
+                if (!buf)
                         return -ENOMEM;
-                memcpy(data, prep->data, datalen);
+                memcpy(buf->virt, prep->data, datalen);
 
                 /* generate random key */
                 enckey = kmalloc(ENC_KEY_SIZE, GFP_KERNEL);
@@ -176,7 +240,7 @@ int big_key_preparse(struct key_preparsed_payload *prep)
                         goto err_enckey;
 
                 /* encrypt aligned data */
-                ret = big_key_crypt(BIG_KEY_ENC, data, datalen, enckey);
+                ret = big_key_crypt(BIG_KEY_ENC, buf, datalen, enckey);
                 if (ret)
                         goto err_enckey;
 
@@ -187,7 +251,7 @@ int big_key_preparse(struct key_preparsed_payload *prep)
                         goto err_enckey;
                 }
 
-                written = kernel_write(file, data, enclen, &pos);
+                written = kernel_write(file, buf->virt, enclen, &pos);
                 if (written != enclen) {
                         ret = written;
                         if (written >= 0)
@@ -202,7 +266,7 @@ int big_key_preparse(struct key_preparsed_payload *prep)
                 *path = file->f_path;
                 path_get(path);
                 fput(file);
-                kzfree(data);
+                big_key_free_buffer(buf);
         } else {
                 /* Just store the data in a buffer */
                 void *data = kmalloc(datalen, GFP_KERNEL);
@@ -220,7 +284,7 @@ err_fput:
 err_enckey:
         kzfree(enckey);
 error:
-        kzfree(data);
+        big_key_free_buffer(buf);
         return ret;
 }
 
@@ -298,15 +362,15 @@ long big_key_read(const struct key *key, char __user *buffer, size_t buflen)
                 return datalen;
 
         if (datalen > BIG_KEY_FILE_THRESHOLD) {
+                struct big_key_buf *buf;
                 struct path *path = (struct path *)&key->payload.data[big_key_path];
                 struct file *file;
-                u8 *data;
                 u8 *enckey = (u8 *)key->payload.data[big_key_data];
                 size_t enclen = datalen + ENC_AUTHTAG_SIZE;
                 loff_t pos = 0;
 
-                data = kmalloc(enclen, GFP_KERNEL);
-                if (!data)
+                buf = big_key_alloc_buffer(enclen);
+                if (!buf)
                         return -ENOMEM;
 
                 file = dentry_open(path, O_RDONLY, current_cred());
@@ -316,26 +380,26 @@ long big_key_read(const struct key *key, char __user *buffer, size_t buflen)
                 }
 
                 /* read file to kernel and decrypt */
-                ret = kernel_read(file, data, enclen, &pos);
+                ret = kernel_read(file, buf->virt, enclen, &pos);
                 if (ret >= 0 && ret != enclen) {
                         ret = -EIO;
                         goto err_fput;
                 }
 
-                ret = big_key_crypt(BIG_KEY_DEC, data, enclen, enckey);
+                ret = big_key_crypt(BIG_KEY_DEC, buf, enclen, enckey);
                 if (ret)
                         goto err_fput;
 
                 ret = datalen;
 
                 /* copy decrypted data to user */
-                if (copy_to_user(buffer, data, datalen) != 0)
+                if (copy_to_user(buffer, buf->virt, datalen) != 0)
                         ret = -EFAULT;
 
 err_fput:
                 fput(file);
 error:
-                kzfree(data);
+                big_key_free_buffer(buf);
         } else {
                 ret = datalen;
                 if (copy_to_user(buffer, key->payload.data[big_key_data],
diff --git a/sound/ac97/Kconfig b/sound/ac97/Kconfig
index f8a64e15e5bf..baa5f8ef89d2 100644
--- a/sound/ac97/Kconfig
+++ b/sound/ac97/Kconfig
@@ -5,7 +5,6 @@
 
 config AC97_BUS_NEW
         tristate
-        select AC97
         help
           This is the new AC97 bus type, successor of AC97_BUS. The ported
           drivers which benefit from the AC97 automatic probing should "select"
diff --git a/sound/core/control.c b/sound/core/control.c
index 0b3026d937b1..8a77620a3854 100644
--- a/sound/core/control.c
+++ b/sound/core/control.c
@@ -889,7 +889,7 @@ static int snd_ctl_elem_read(struct snd_card *card,
 
         index_offset = snd_ctl_get_ioff(kctl, &control->id);
         vd = &kctl->vd[index_offset];
-        if (!(vd->access & SNDRV_CTL_ELEM_ACCESS_READ) && kctl->get == NULL)
+        if (!(vd->access & SNDRV_CTL_ELEM_ACCESS_READ) || kctl->get == NULL)
                 return -EPERM;
 
         snd_ctl_build_ioff(&control->id, kctl, index_offset);
diff --git a/sound/core/seq/seq_clientmgr.c b/sound/core/seq/seq_clientmgr.c
index 60db32785f62..04d4db44fae5 100644
--- a/sound/core/seq/seq_clientmgr.c
+++ b/sound/core/seq/seq_clientmgr.c
@@ -1003,7 +1003,7 @@ static ssize_t snd_seq_write(struct file *file, const char __user *buf,
 {
         struct snd_seq_client *client = file->private_data;
         int written = 0, len;
-        int err = -EINVAL;
+        int err;
         struct snd_seq_event event;
 
         if (!(snd_seq_file_flags(file) & SNDRV_SEQ_LFLG_OUTPUT))
@@ -1018,11 +1018,15 @@ static ssize_t snd_seq_write(struct file *file, const char __user *buf,
 
         /* allocate the pool now if the pool is not allocated yet */ 
         if (client->pool->size > 0 && !snd_seq_write_pool_allocated(client)) {
-                if (snd_seq_pool_init(client->pool) < 0)
+                mutex_lock(&client->ioctl_mutex);
+                err = snd_seq_pool_init(client->pool);
+                mutex_unlock(&client->ioctl_mutex);
+                if (err < 0)
                         return -ENOMEM;
         }
 
         /* only process whole events */
+        err = -EINVAL;
         while (count >= sizeof(struct snd_seq_event)) {
                 /* Read in the event header from the user */
                 len = sizeof(event);
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index c71dcacea807..96143df19b21 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -181,7 +181,7 @@ static const struct kernel_param_ops param_ops_xint = {
 };
 #define param_check_xint param_check_int
 
-static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
+static int power_save = -1;
 module_param(power_save, xint, 0644);
 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
                  "(in second, 0 = disable).");
@@ -2186,6 +2186,24 @@ out_free:
         return err;
 }
 
+#ifdef CONFIG_PM
+/* On some boards setting power_save to a non 0 value leads to clicking /
+ * popping sounds when ever we enter/leave powersaving mode. Ideally we would
+ * figure out how to avoid these sounds, but that is not always feasible.
+ * So we keep a list of devices where we disable powersaving as its known
+ * to causes problems on these devices.
+ */
+static struct snd_pci_quirk power_save_blacklist[] = {
+        /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
+        SND_PCI_QUIRK(0x1849, 0x0c0c, "Asrock B85M-ITX", 0),
+        /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
+        SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
+        /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
+        SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
+        {}
+};
+#endif /* CONFIG_PM */
+
 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
         [AZX_DRIVER_NVIDIA] = 8,
@@ -2198,6 +2216,7 @@ static int azx_probe_continue(struct azx *chip)
         struct hdac_bus *bus = azx_bus(chip);
         struct pci_dev *pci = chip->pci;
         int dev = chip->dev_index;
+        int val;
         int err;
 
         hda->probe_continued = 1;
@@ -2278,7 +2297,22 @@ static int azx_probe_continue(struct azx *chip)
 
         chip->running = 1;
         azx_add_card_list(chip);
-        snd_hda_set_power_save(&chip->bus, power_save * 1000);
+
+        val = power_save;
+#ifdef CONFIG_PM
+        if (val == -1) {
+                const struct snd_pci_quirk *q;
+
+                val = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
+                q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist);
+                if (q && val) {
+                        dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n",
+                                 q->subvendor, q->subdevice);
+                        val = 0;
+                }
+        }
+#endif /* CONFIG_PM */
+        snd_hda_set_power_save(&chip->bus, val * 1000);
         if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
                 pm_runtime_put_autosuspend(&pci->dev);
 
diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c
index 23475888192b..b9c93fa0a51c 100644
--- a/sound/pci/hda/patch_realtek.c
+++ b/sound/pci/hda/patch_realtek.c
@@ -3465,6 +3465,19 @@ static void alc269_fixup_pincfg_no_hp_to_lineout(struct hda_codec *codec,
                 spec->parse_flags = HDA_PINCFG_NO_HP_FIXUP;
 }
 
+static void alc269_fixup_pincfg_U7x7_headset_mic(struct hda_codec *codec,
+                                                 const struct hda_fixup *fix,
+                                                 int action)
+{
+        unsigned int cfg_headphone = snd_hda_codec_get_pincfg(codec, 0x21);
+        unsigned int cfg_headset_mic = snd_hda_codec_get_pincfg(codec, 0x19);
+
+        if (cfg_headphone && cfg_headset_mic == 0x411111f0)
+                snd_hda_codec_set_pincfg(codec, 0x19,
+                        (cfg_headphone & ~AC_DEFCFG_DEVICE) |
+                        (AC_JACK_MIC_IN << AC_DEFCFG_DEVICE_SHIFT));
+}
+
 static void alc269_fixup_hweq(struct hda_codec *codec,
                                const struct hda_fixup *fix, int action)
 {
@@ -4972,6 +4985,29 @@ static void alc_fixup_tpt440_dock(struct hda_codec *codec,
         }
 }
 
+static void alc_fixup_tpt470_dock(struct hda_codec *codec,
+                                  const struct hda_fixup *fix, int action)
+{
+        static const struct hda_pintbl pincfgs[] = {
+                { 0x17, 0x21211010 }, /* dock headphone */
+                { 0x19, 0x21a11010 }, /* dock mic */
+                { }
+        };
+        struct alc_spec *spec = codec->spec;
+
+        if (action == HDA_FIXUP_ACT_PRE_PROBE) {
+                spec->parse_flags = HDA_PINCFG_NO_HP_FIXUP;
+                snd_hda_apply_pincfgs(codec, pincfgs);
+        } else if (action == HDA_FIXUP_ACT_INIT) {
+                /* Enable DOCK device */
+                snd_hda_codec_write(codec, 0x17, 0,
+                            AC_VERB_SET_CONFIG_DEFAULT_BYTES_3, 0);
+                /* Enable DOCK device */
+                snd_hda_codec_write(codec, 0x19, 0,
+                            AC_VERB_SET_CONFIG_DEFAULT_BYTES_3, 0);
+        }
+}
+
 static void alc_shutup_dell_xps13(struct hda_codec *codec)
 {
         struct alc_spec *spec = codec->spec;
@@ -5351,6 +5387,7 @@ enum {
         ALC269_FIXUP_LIFEBOOK_EXTMIC,
         ALC269_FIXUP_LIFEBOOK_HP_PIN,
         ALC269_FIXUP_LIFEBOOK_NO_HP_TO_LINEOUT,
+        ALC255_FIXUP_LIFEBOOK_U7x7_HEADSET_MIC,
         ALC269_FIXUP_AMIC,
         ALC269_FIXUP_DMIC,
         ALC269VB_FIXUP_AMIC,
@@ -5446,6 +5483,7 @@ enum {
         ALC700_FIXUP_INTEL_REFERENCE,
         ALC274_FIXUP_DELL_BIND_DACS,
         ALC274_FIXUP_DELL_AIO_LINEOUT_VERB,
+        ALC298_FIXUP_TPT470_DOCK,
 };
 
 static const struct hda_fixup alc269_fixups[] = {
@@ -5556,6 +5594,10 @@ static const struct hda_fixup alc269_fixups[] = {
                 .type = HDA_FIXUP_FUNC,
                 .v.func = alc269_fixup_pincfg_no_hp_to_lineout,
         },
+        [ALC255_FIXUP_LIFEBOOK_U7x7_HEADSET_MIC] = {
+                .type = HDA_FIXUP_FUNC,
+                .v.func = alc269_fixup_pincfg_U7x7_headset_mic,
+        },
         [ALC269_FIXUP_AMIC] = {
                 .type = HDA_FIXUP_PINS,
                 .v.pins = (const struct hda_pintbl[]) {
@@ -6271,6 +6313,12 @@ static const struct hda_fixup alc269_fixups[] = {
                 .chained = true,
                 .chain_id = ALC274_FIXUP_DELL_BIND_DACS
         },
+        [ALC298_FIXUP_TPT470_DOCK] = {
+                .type = HDA_FIXUP_FUNC,
+                .v.func = alc_fixup_tpt470_dock,
+                .chained = true,
+                .chain_id = ALC293_FIXUP_LENOVO_SPK_NOISE
+        },
 };
 
 static const struct snd_pci_quirk alc269_fixup_tbl[] = {
@@ -6321,6 +6369,8 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = {
         SND_PCI_QUIRK(0x1028, 0x075d, "Dell AIO", ALC298_FIXUP_SPK_VOLUME),
         SND_PCI_QUIRK(0x1028, 0x0798, "Dell Inspiron 17 7000 Gaming", ALC256_FIXUP_DELL_INSPIRON_7559_SUBWOOFER),
         SND_PCI_QUIRK(0x1028, 0x082a, "Dell XPS 13 9360", ALC256_FIXUP_DELL_XPS_13_HEADPHONE_NOISE),
+        SND_PCI_QUIRK(0x1028, 0x084b, "Dell", ALC274_FIXUP_DELL_AIO_LINEOUT_VERB),
+        SND_PCI_QUIRK(0x1028, 0x084e, "Dell", ALC274_FIXUP_DELL_AIO_LINEOUT_VERB),
         SND_PCI_QUIRK(0x1028, 0x164a, "Dell", ALC293_FIXUP_DELL1_MIC_NO_PRESENCE),
         SND_PCI_QUIRK(0x1028, 0x164b, "Dell", ALC293_FIXUP_DELL1_MIC_NO_PRESENCE),
         SND_PCI_QUIRK(0x103c, 0x1586, "HP", ALC269_FIXUP_HP_MUTE_LED_MIC2),
@@ -6422,6 +6472,7 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = {
         SND_PCI_QUIRK(0x10cf, 0x159f, "Lifebook E780", ALC269_FIXUP_LIFEBOOK_NO_HP_TO_LINEOUT),
         SND_PCI_QUIRK(0x10cf, 0x15dc, "Lifebook T731", ALC269_FIXUP_LIFEBOOK_HP_PIN),
         SND_PCI_QUIRK(0x10cf, 0x1757, "Lifebook E752", ALC269_FIXUP_LIFEBOOK_HP_PIN),
+        SND_PCI_QUIRK(0x10cf, 0x1629, "Lifebook U7x7", ALC255_FIXUP_LIFEBOOK_U7x7_HEADSET_MIC),
         SND_PCI_QUIRK(0x10cf, 0x1845, "Lifebook U904", ALC269_FIXUP_LIFEBOOK_EXTMIC),
         SND_PCI_QUIRK(0x10ec, 0x10f2, "Intel Reference board", ALC700_FIXUP_INTEL_REFERENCE),
         SND_PCI_QUIRK(0x144d, 0xc109, "Samsung Ativ book 9 (NP900X3G)", ALC269_FIXUP_INV_DMIC),
@@ -6450,8 +6501,16 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = {
         SND_PCI_QUIRK(0x17aa, 0x2218, "Thinkpad X1 Carbon 2nd", ALC292_FIXUP_TPT440_DOCK),
         SND_PCI_QUIRK(0x17aa, 0x2223, "ThinkPad T550", ALC292_FIXUP_TPT440_DOCK),
         SND_PCI_QUIRK(0x17aa, 0x2226, "ThinkPad X250", ALC292_FIXUP_TPT440_DOCK),
+        SND_PCI_QUIRK(0x17aa, 0x222d, "Thinkpad", ALC298_FIXUP_TPT470_DOCK),
+        SND_PCI_QUIRK(0x17aa, 0x222e, "Thinkpad", ALC298_FIXUP_TPT470_DOCK),
         SND_PCI_QUIRK(0x17aa, 0x2231, "Thinkpad T560", ALC292_FIXUP_TPT460),
         SND_PCI_QUIRK(0x17aa, 0x2233, "Thinkpad", ALC292_FIXUP_TPT460),
+        SND_PCI_QUIRK(0x17aa, 0x2245, "Thinkpad T470", ALC298_FIXUP_TPT470_DOCK),
+        SND_PCI_QUIRK(0x17aa, 0x2246, "Thinkpad", ALC298_FIXUP_TPT470_DOCK),
+        SND_PCI_QUIRK(0x17aa, 0x2247, "Thinkpad", ALC298_FIXUP_TPT470_DOCK),
+        SND_PCI_QUIRK(0x17aa, 0x224b, "Thinkpad", ALC298_FIXUP_TPT470_DOCK),
+        SND_PCI_QUIRK(0x17aa, 0x224c, "Thinkpad", ALC298_FIXUP_TPT470_DOCK),
+        SND_PCI_QUIRK(0x17aa, 0x224d, "Thinkpad", ALC298_FIXUP_TPT470_DOCK),
         SND_PCI_QUIRK(0x17aa, 0x30bb, "ThinkCentre AIO", ALC233_FIXUP_LENOVO_LINE2_MIC_HOTKEY),
         SND_PCI_QUIRK(0x17aa, 0x30e2, "ThinkCentre AIO", ALC233_FIXUP_LENOVO_LINE2_MIC_HOTKEY),
         SND_PCI_QUIRK(0x17aa, 0x310c, "ThinkCentre Station", ALC294_FIXUP_LENOVO_MIC_LOCATION),
@@ -6472,7 +6531,12 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = {
         SND_PCI_QUIRK(0x17aa, 0x5050, "Thinkpad T560p", ALC292_FIXUP_TPT460),
         SND_PCI_QUIRK(0x17aa, 0x5051, "Thinkpad L460", ALC292_FIXUP_TPT460),
         SND_PCI_QUIRK(0x17aa, 0x5053, "Thinkpad T460", ALC292_FIXUP_TPT460),
+        SND_PCI_QUIRK(0x17aa, 0x505d, "Thinkpad", ALC298_FIXUP_TPT470_DOCK),
+        SND_PCI_QUIRK(0x17aa, 0x505f, "Thinkpad", ALC298_FIXUP_TPT470_DOCK),
+        SND_PCI_QUIRK(0x17aa, 0x5062, "Thinkpad", ALC298_FIXUP_TPT470_DOCK),
         SND_PCI_QUIRK(0x17aa, 0x5109, "Thinkpad", ALC269_FIXUP_LIMIT_INT_MIC_BOOST),
+        SND_PCI_QUIRK(0x17aa, 0x511e, "Thinkpad", ALC298_FIXUP_TPT470_DOCK),
+        SND_PCI_QUIRK(0x17aa, 0x511f, "Thinkpad", ALC298_FIXUP_TPT470_DOCK),
         SND_PCI_QUIRK(0x17aa, 0x3bf8, "Quanta FL1", ALC269_FIXUP_PCM_44K),
         SND_PCI_QUIRK(0x17aa, 0x9e54, "LENOVO NB", ALC269_FIXUP_LENOVO_EAPD),
         SND_PCI_QUIRK(0x1b7d, 0xa831, "Ordissimo EVE2 ", ALC269VB_FIXUP_ORDISSIMO_EVE2), /* Also known as Malata PC-B1303 */
@@ -6735,6 +6799,11 @@ static const struct snd_hda_pin_quirk alc269_pin_fixup_tbl[] = {
                 {0x14, 0x90170110},
                 {0x21, 0x02211020}),
         SND_HDA_PIN_QUIRK(0x10ec0256, 0x1028, "Dell", ALC255_FIXUP_DELL1_MIC_NO_PRESENCE,
+                {0x12, 0x90a60130},
+                {0x14, 0x90170110},
+                {0x14, 0x01011020},
+                {0x21, 0x0221101f}),
+        SND_HDA_PIN_QUIRK(0x10ec0256, 0x1028, "Dell", ALC255_FIXUP_DELL1_MIC_NO_PRESENCE,
                 ALC256_STANDARD_PINS),
         SND_HDA_PIN_QUIRK(0x10ec0256, 0x1043, "ASUS", ALC256_FIXUP_ASUS_MIC,
                 {0x14, 0x90170110},
@@ -6803,6 +6872,10 @@ static const struct snd_hda_pin_quirk alc269_pin_fixup_tbl[] = {
                 {0x12, 0x90a60120},
                 {0x14, 0x90170110},
                 {0x21, 0x0321101f}),
+        SND_HDA_PIN_QUIRK(0x10ec0289, 0x1028, "Dell", ALC225_FIXUP_DELL1_MIC_NO_PRESENCE,
+                {0x12, 0xb7a60130},
+                {0x14, 0x90170110},
+                {0x21, 0x04211020}),
         SND_HDA_PIN_QUIRK(0x10ec0290, 0x103c, "HP", ALC269_FIXUP_HP_MUTE_LED_MIC1,
                 ALC290_STANDARD_PINS,
                 {0x15, 0x04211040},
diff --git a/sound/usb/mixer.c b/sound/usb/mixer.c
index 9afb8ab524c7..06b22624ab7a 100644
--- a/sound/usb/mixer.c
+++ b/sound/usb/mixer.c
@@ -347,17 +347,20 @@ static int get_ctl_value_v2(struct usb_mixer_elem_info *cval, int request,
                             int validx, int *value_ret)
 {
         struct snd_usb_audio *chip = cval->head.mixer->chip;
-        unsigned char buf[4 + 3 * sizeof(__u32)]; /* enough space for one range */
+        /* enough space for one range */
+        unsigned char buf[sizeof(__u16) + 3 * sizeof(__u32)];
         unsigned char *val;
-        int idx = 0, ret, size;
+        int idx = 0, ret, val_size, size;
         __u8 bRequest;
 
+        val_size = uac2_ctl_value_size(cval->val_type);
+
         if (request == UAC_GET_CUR) {
                 bRequest = UAC2_CS_CUR;
-                size = uac2_ctl_value_size(cval->val_type);
+                size = val_size;
         } else {
                 bRequest = UAC2_CS_RANGE;
-                size = sizeof(buf);
+                size = sizeof(__u16) + 3 * val_size;
         }
 
         memset(buf, 0, sizeof(buf));
@@ -390,16 +393,17 @@ error:
                 val = buf + sizeof(__u16);
                 break;
         case UAC_GET_MAX:
-                val = buf + sizeof(__u16) * 2;
+                val = buf + sizeof(__u16) + val_size;
                 break;
         case UAC_GET_RES:
-                val = buf + sizeof(__u16) * 3;
+                val = buf + sizeof(__u16) + val_size * 2;
                 break;
         default:
                 return -EINVAL;
         }
 
-        *value_ret = convert_signed_value(cval, snd_usb_combine_bytes(val, sizeof(__u16)));
+        *value_ret = convert_signed_value(cval,
+                                          snd_usb_combine_bytes(val, val_size));
 
         return 0;
 }
diff --git a/sound/usb/pcm.c b/sound/usb/pcm.c
index b9c9a19f9588..3cbfae6604f9 100644
--- a/sound/usb/pcm.c
+++ b/sound/usb/pcm.c
@@ -357,6 +357,15 @@ static int set_sync_ep_implicit_fb_quirk(struct snd_usb_substream *subs,
 
                 alts = &iface->altsetting[1];
                 goto add_sync_ep;
+        case USB_ID(0x1397, 0x0002):
+                ep = 0x81;
+                iface = usb_ifnum_to_if(dev, 1);
+
+                if (!iface || iface->num_altsetting == 0)
+                        return -EINVAL;
+
+                alts = &iface->altsetting[1];
+                goto add_sync_ep;
 
         }
         if (attr == USB_ENDPOINT_SYNC_ASYNC &&
diff --git a/sound/usb/quirks-table.h b/sound/usb/quirks-table.h
index 50252046b01d..754e632a27bd 100644
--- a/sound/usb/quirks-table.h
+++ b/sound/usb/quirks-table.h
@@ -3325,4 +3325,51 @@ AU0828_DEVICE(0x2040, 0x7270, "Hauppauge", "HVR-950Q"),
         }
 },
 
+{
+        /*
+         * Bower's & Wilkins PX headphones only support the 48 kHz sample rate
+         * even though it advertises more. The capture interface doesn't work
+         * even on windows.
+         */
+        USB_DEVICE(0x19b5, 0x0021),
+        .driver_info = (unsigned long) &(const struct snd_usb_audio_quirk) {
+                .ifnum = QUIRK_ANY_INTERFACE,
+                .type = QUIRK_COMPOSITE,
+                .data = (const struct snd_usb_audio_quirk[]) {
+                        {
+                                .ifnum = 0,
+                                .type = QUIRK_AUDIO_STANDARD_MIXER,
+                        },
+                        /* Capture */
+                        {
+                                .ifnum = 1,
+                                .type = QUIRK_IGNORE_INTERFACE,
+                        },
+                        /* Playback */
+                        {
+                                .ifnum = 2,
+                                .type = QUIRK_AUDIO_FIXED_ENDPOINT,
+                                .data = &(const struct audioformat) {
+                                        .formats = SNDRV_PCM_FMTBIT_S16_LE,
+                                        .channels = 2,
+                                        .iface = 2,
+                                        .altsetting = 1,
+                                        .altset_idx = 1,
+                                        .attributes = UAC_EP_CS_ATTR_FILL_MAX |
+                                                UAC_EP_CS_ATTR_SAMPLE_RATE,
+                                        .endpoint = 0x03,
+                                        .ep_attr = USB_ENDPOINT_XFER_ISOC,
+                                        .rates = SNDRV_PCM_RATE_48000,
+                                        .rate_min = 48000,
+                                        .rate_max = 48000,
+                                        .nr_rates = 1,
+                                        .rate_table = (unsigned int[]) {
+                                                48000
+                                        }
+                                }
+                        },
+                }
+        }
+},
+
 #undef USB_DEVICE_VENDOR_SPEC
diff --git a/sound/usb/quirks.c b/sound/usb/quirks.c
index a66ef5777887..ea8f3de92fa4 100644
--- a/sound/usb/quirks.c
+++ b/sound/usb/quirks.c
@@ -1363,8 +1363,11 @@ u64 snd_usb_interface_dsd_format_quirks(struct snd_usb_audio *chip,
                         return SNDRV_PCM_FMTBIT_DSD_U32_BE;
                 break;
 
-        /* Amanero Combo384 USB interface with native DSD support */
-        case USB_ID(0x16d0, 0x071a):
+        /* Amanero Combo384 USB based DACs with native DSD support */
+        case USB_ID(0x16d0, 0x071a):  /* Amanero - Combo384 */
+        case USB_ID(0x2ab6, 0x0004):  /* T+A DAC8DSD-V2.0, MP1000E-V2.0, MP2000R-V2.0, MP2500R-V2.0, MP3100HV-V2.0 */
+        case USB_ID(0x2ab6, 0x0005):  /* T+A USB HD Audio 1 */
+        case USB_ID(0x2ab6, 0x0006):  /* T+A USB HD Audio 2 */
                 if (fp->altsetting == 2) {
                         switch (le16_to_cpu(chip->dev->descriptor.bcdDevice)) {
                         case 0x199:
diff --git a/sound/x86/intel_hdmi_audio.c b/sound/x86/intel_hdmi_audio.c
index a0951505c7f5..4ed9d0c41843 100644
--- a/sound/x86/intel_hdmi_audio.c
+++ b/sound/x86/intel_hdmi_audio.c
@@ -50,6 +50,7 @@
 /*standard module options for ALSA. This module supports only one card*/
 static int hdmi_card_index = SNDRV_DEFAULT_IDX1;
 static char *hdmi_card_id = SNDRV_DEFAULT_STR1;
+static bool single_port;
 
 module_param_named(index, hdmi_card_index, int, 0444);
 MODULE_PARM_DESC(index,
@@ -57,6 +58,9 @@ MODULE_PARM_DESC(index,
 module_param_named(id, hdmi_card_id, charp, 0444);
 MODULE_PARM_DESC(id,
                 "ID string for INTEL Intel HDMI Audio controller.");
+module_param(single_port, bool, 0444);
+MODULE_PARM_DESC(single_port,
+                "Single-port mode (for compatibility)");
 
 /*
  * ELD SA bits in the CEA Speaker Allocation data block
@@ -1579,7 +1583,11 @@ static irqreturn_t display_pipe_interrupt_handler(int irq, void *dev_id)
 static void notify_audio_lpe(struct platform_device *pdev, int port)
 {
         struct snd_intelhad_card *card_ctx = platform_get_drvdata(pdev);
-        struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port];
+        struct snd_intelhad *ctx;
+
+        ctx = &card_ctx->pcm_ctx[single_port ? 0 : port];
+        if (single_port)
+                ctx->port = port;
 
         schedule_work(&ctx->hdmi_audio_wq);
 }
@@ -1743,6 +1751,7 @@ static int hdmi_lpe_audio_probe(struct platform_device *pdev)
 {
         struct snd_card *card;
         struct snd_intelhad_card *card_ctx;
+        struct snd_intelhad *ctx;
         struct snd_pcm *pcm;
         struct intel_hdmi_lpe_audio_pdata *pdata;
         int irq;
@@ -1787,6 +1796,21 @@ static int hdmi_lpe_audio_probe(struct platform_device *pdev)
 
         platform_set_drvdata(pdev, card_ctx);
 
+        card_ctx->num_pipes = pdata->num_pipes;
+        card_ctx->num_ports = single_port ? 1 : pdata->num_ports;
+
+        for_each_port(card_ctx, port) {
+                ctx = &card_ctx->pcm_ctx[port];
+                ctx->card_ctx = card_ctx;
+                ctx->dev = card_ctx->dev;
+                ctx->port = single_port ? -1 : port;
+                ctx->pipe = -1;
+
+                spin_lock_init(&ctx->had_spinlock);
+                mutex_init(&ctx->mutex);
+                INIT_WORK(&ctx->hdmi_audio_wq, had_audio_wq);
+        }
+
         dev_dbg(&pdev->dev, "%s: mmio_start = 0x%x, mmio_end = 0x%x\n",
                 __func__, (unsigned int)res_mmio->start,
                 (unsigned int)res_mmio->end);
@@ -1816,19 +1840,12 @@ static int hdmi_lpe_audio_probe(struct platform_device *pdev)
         init_channel_allocations();
 
         card_ctx->num_pipes = pdata->num_pipes;
-        card_ctx->num_ports = pdata->num_ports;
+        card_ctx->num_ports = single_port ? 1 : pdata->num_ports;
 
         for_each_port(card_ctx, port) {
-                struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port];
                 int i;
 
-                ctx->card_ctx = card_ctx;
-                ctx->dev = card_ctx->dev;
-                ctx->port = port;
-                ctx->pipe = -1;
-
-                INIT_WORK(&ctx->hdmi_audio_wq, had_audio_wq);
-
+                ctx = &card_ctx->pcm_ctx[port];
                 ret = snd_pcm_new(card, INTEL_HAD, port, MAX_PB_STREAMS,
                                   MAX_CAP_STREAMS, &pcm);
                 if (ret)
diff --git a/tools/arch/powerpc/include/uapi/asm/kvm.h b/tools/arch/powerpc/include/uapi/asm/kvm.h
index 637b7263cb86..833ed9a16adf 100644
--- a/tools/arch/powerpc/include/uapi/asm/kvm.h
+++ b/tools/arch/powerpc/include/uapi/asm/kvm.h
@@ -632,6 +632,8 @@ struct kvm_ppc_cpu_char {
 #define KVM_REG_PPC_TIDR        (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbc)
 #define KVM_REG_PPC_PSSCR       (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbd)
 
+#define KVM_REG_PPC_DEC_EXPIRY  (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbe)
+
 /* Transactional Memory checkpointed state:
  * This is all GPRs, all VSX regs and a subset of SPRs
  */
diff --git a/tools/arch/s390/include/uapi/asm/unistd.h b/tools/arch/s390/include/uapi/asm/unistd.h
deleted file mode 100644
index 725120939051..000000000000
--- a/tools/arch/s390/include/uapi/asm/unistd.h
+++ /dev/null
@@ -1,412 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
-/*
- *  S390 version
- *
- *  Derived from "include/asm-i386/unistd.h"
- */
-
-#ifndef _UAPI_ASM_S390_UNISTD_H_
-#define _UAPI_ASM_S390_UNISTD_H_
-
-/*
- * This file contains the system call numbers.
- */
-
-#define __NR_exit                 1
-#define __NR_fork                 2
-#define __NR_read                 3
-#define __NR_write                4
-#define __NR_open                 5
-#define __NR_close                6
-#define __NR_restart_syscall      7
-#define __NR_creat                8
-#define __NR_link                 9
-#define __NR_unlink              10
-#define __NR_execve              11
-#define __NR_chdir               12
-#define __NR_mknod               14
-#define __NR_chmod               15
-#define __NR_lseek               19
-#define __NR_getpid              20
-#define __NR_mount               21
-#define __NR_umount              22
-#define __NR_ptrace              26
-#define __NR_alarm               27
-#define __NR_pause               29
-#define __NR_utime               30
-#define __NR_access              33
-#define __NR_nice                34
-#define __NR_sync                36
-#define __NR_kill                37
-#define __NR_rename              38
-#define __NR_mkdir               39
-#define __NR_rmdir               40
-#define __NR_dup                 41
-#define __NR_pipe                42
-#define __NR_times               43
-#define __NR_brk                 45
-#define __NR_signal              48
-#define __NR_acct                51
-#define __NR_umount2             52
-#define __NR_ioctl               54
-#define __NR_fcntl               55
-#define __NR_setpgid             57
-#define __NR_umask               60
-#define __NR_chroot              61
-#define __NR_ustat               62
-#define __NR_dup2                63
-#define __NR_getppid             64
-#define __NR_getpgrp             65
-#define __NR_setsid              66
-#define __NR_sigaction           67
-#define __NR_sigsuspend          72
-#define __NR_sigpending          73
-#define __NR_sethostname         74
-#define __NR_setrlimit           75
-#define __NR_getrusage           77
-#define __NR_gettimeofday        78
-#define __NR_settimeofday        79
-#define __NR_symlink             83
-#define __NR_readlink            85
-#define __NR_uselib              86
-#define __NR_swapon              87
-#define __NR_reboot              88
-#define __NR_readdir             89
-#define __NR_mmap                90
-#define __NR_munmap              91
-#define __NR_truncate            92
-#define __NR_ftruncate           93
-#define __NR_fchmod              94
-#define __NR_getpriority         96
-#define __NR_setpriority         97
-#define __NR_statfs              99
-#define __NR_fstatfs            100
-#define __NR_socketcall         102
-#define __NR_syslog             103
-#define __NR_setitimer          104
-#define __NR_getitimer          105
-#define __NR_stat               106
-#define __NR_lstat              107
-#define __NR_fstat              108
-#define __NR_lookup_dcookie     110
-#define __NR_vhangup            111
-#define __NR_idle               112
-#define __NR_wait4              114
-#define __NR_swapoff            115
-#define __NR_sysinfo            116
-#define __NR_ipc                117
-#define __NR_fsync              118
-#define __NR_sigreturn          119
-#define __NR_clone              120
-#define __NR_setdomainname      121
-#define __NR_uname              122
-#define __NR_adjtimex           124
-#define __NR_mprotect           125
-#define __NR_sigprocmask        126
-#define __NR_create_module      127
-#define __NR_init_module        128
-#define __NR_delete_module      129
-#define __NR_get_kernel_syms    130
-#define __NR_quotactl           131
-#define __NR_getpgid            132
-#define __NR_fchdir             133
-#define __NR_bdflush            134
-#define __NR_sysfs              135
-#define __NR_personality        136
-#define __NR_afs_syscall        137 /* Syscall for Andrew File System */
-#define __NR_getdents           141
-#define __NR_flock              143
-#define __NR_msync              144
-#define __NR_readv              145
-#define __NR_writev             146
-#define __NR_getsid             147
-#define __NR_fdatasync          148
-#define __NR__sysctl            149
-#define __NR_mlock              150
-#define __NR_munlock            151
-#define __NR_mlockall           152
-#define __NR_munlockall         153
-#define __NR_sched_setparam             154
-#define __NR_sched_getparam             155
-#define __NR_sched_setscheduler         156
-#define __NR_sched_getscheduler         157
-#define __NR_sched_yield                158
-#define __NR_sched_get_priority_max     159
-#define __NR_sched_get_priority_min     160
-#define __NR_sched_rr_get_interval      161
-#define __NR_nanosleep          162
-#define __NR_mremap             163
-#define __NR_query_module       167
-#define __NR_poll               168
-#define __NR_nfsservctl         169
-#define __NR_prctl              172
-#define __NR_rt_sigreturn       173
-#define __NR_rt_sigaction       174
-#define __NR_rt_sigprocmask     175
-#define __NR_rt_sigpending      176
-#define __NR_rt_sigtimedwait    177
-#define __NR_rt_sigqueueinfo    178
-#define __NR_rt_sigsuspend      179
-#define __NR_pread64            180
-#define __NR_pwrite64           181
-#define __NR_getcwd             183
-#define __NR_capget             184
-#define __NR_capset             185
-#define __NR_sigaltstack        186
-#define __NR_sendfile           187
-#define __NR_getpmsg            188
-#define __NR_putpmsg            189
-#define __NR_vfork              190
-#define __NR_pivot_root         217
-#define __NR_mincore            218
-#define __NR_madvise            219
-#define __NR_getdents64         220
-#define __NR_readahead          222
-#define __NR_setxattr           224
-#define __NR_lsetxattr          225
-#define __NR_fsetxattr          226
-#define __NR_getxattr           227
-#define __NR_lgetxattr          228
-#define __NR_fgetxattr          229
-#define __NR_listxattr          230
-#define __NR_llistxattr         231
-#define __NR_flistxattr         232
-#define __NR_removexattr        233
-#define __NR_lremovexattr       234
-#define __NR_fremovexattr       235
-#define __NR_gettid             236
-#define __NR_tkill              237
-#define __NR_futex              238
-#define __NR_sched_setaffinity  239
-#define __NR_sched_getaffinity  240
-#define __NR_tgkill             241
-/* Number 242 is reserved for tux */
-#define __NR_io_setup           243
-#define __NR_io_destroy         244
-#define __NR_io_getevents       245
-#define __NR_io_submit          246
-#define __NR_io_cancel          247
-#define __NR_exit_group         248
-#define __NR_epoll_create       249
-#define __NR_epoll_ctl          250
-#define __NR_epoll_wait         251
-#define __NR_set_tid_address    252
-#define __NR_fadvise64          253
-#define __NR_timer_create       254
-#define __NR_timer_settime      255
-#define __NR_timer_gettime      256
-#define __NR_timer_getoverrun   257
-#define __NR_timer_delete       258
-#define __NR_clock_settime      259
-#define __NR_clock_gettime      260
-#define __NR_clock_getres       261
-#define __NR_clock_nanosleep    262
-/* Number 263 is reserved for vserver */
-#define __NR_statfs64           265
-#define __NR_fstatfs64          266
-#define __NR_remap_file_pages   267
-#define __NR_mbind              268
-#define __NR_get_mempolicy      269
-#define __NR_set_mempolicy      270
-#define __NR_mq_open            271
-#define __NR_mq_unlink          272
-#define __NR_mq_timedsend       273
-#define __NR_mq_timedreceive    274
-#define __NR_mq_notify          275
-#define __NR_mq_getsetattr      276
-#define __NR_kexec_load         277
-#define __NR_add_key            278
-#define __NR_request_key        279
-#define __NR_keyctl             280
-#define __NR_waitid             281
-#define __NR_ioprio_set         282
-#define __NR_ioprio_get         283
-#define __NR_inotify_init       284
-#define __NR_inotify_add_watch  285
-#define __NR_inotify_rm_watch   286
-#define __NR_migrate_pages      287
-#define __NR_openat             288
-#define __NR_mkdirat            289
-#define __NR_mknodat            290
-#define __NR_fchownat           291
-#define __NR_futimesat          292
-#define __NR_unlinkat           294
-#define __NR_renameat           295
-#define __NR_linkat             296
-#define __NR_symlinkat          297
-#define __NR_readlinkat         298
-#define __NR_fchmodat           299
-#define __NR_faccessat          300
-#define __NR_pselect6           301
-#define __NR_ppoll              302
-#define __NR_unshare            303
-#define __NR_set_robust_list    304
-#define __NR_get_robust_list    305
-#define __NR_splice             306
-#define __NR_sync_file_range    307
-#define __NR_tee                308
-#define __NR_vmsplice           309
-#define __NR_move_pages         310
-#define __NR_getcpu             311
-#define __NR_epoll_pwait        312
-#define __NR_utimes             313
-#define __NR_fallocate          314
-#define __NR_utimensat          315
-#define __NR_signalfd           316
-#define __NR_timerfd            317
-#define __NR_eventfd            318
-#define __NR_timerfd_create     319
-#define __NR_timerfd_settime    320
-#define __NR_timerfd_gettime    321
-#define __NR_signalfd4          322
-#define __NR_eventfd2           323
-#define __NR_inotify_init1      324
-#define __NR_pipe2              325
-#define __NR_dup3               326
-#define __NR_epoll_create1      327
-#define __NR_preadv             328
-#define __NR_pwritev            329
-#define __NR_rt_tgsigqueueinfo  330
-#define __NR_perf_event_open    331
-#define __NR_fanotify_init      332
-#define __NR_fanotify_mark      333
-#define __NR_prlimit64          334
-#define __NR_name_to_handle_at  335
-#define __NR_open_by_handle_at  336
-#define __NR_clock_adjtime      337
-#define __NR_syncfs             338
-#define __NR_setns              339
-#define __NR_process_vm_readv   340
-#define __NR_process_vm_writev  341
-#define __NR_s390_runtime_instr 342
-#define __NR_kcmp               343
-#define __NR_finit_module       344
-#define __NR_sched_setattr      345
-#define __NR_sched_getattr      346
-#define __NR_renameat2          347
-#define __NR_seccomp            348
-#define __NR_getrandom          349
-#define __NR_memfd_create       350
-#define __NR_bpf                351
-#define __NR_s390_pci_mmio_write        352
-#define __NR_s390_pci_mmio_read         353
-#define __NR_execveat           354
-#define __NR_userfaultfd        355
-#define __NR_membarrier         356
-#define __NR_recvmmsg           357
-#define __NR_sendmmsg           358
-#define __NR_socket             359
-#define __NR_socketpair         360
-#define __NR_bind               361
-#define __NR_connect            362
-#define __NR_listen             363
-#define __NR_accept4            364
-#define __NR_getsockopt         365
-#define __NR_setsockopt         366
-#define __NR_getsockname        367
-#define __NR_getpeername        368
-#define __NR_sendto             369
-#define __NR_sendmsg            370
-#define __NR_recvfrom           371
-#define __NR_recvmsg            372
-#define __NR_shutdown           373
-#define __NR_mlock2             374
-#define __NR_copy_file_range    375
-#define __NR_preadv2            376
-#define __NR_pwritev2           377
-#define __NR_s390_guarded_storage       378
-#define __NR_statx              379
-#define __NR_s390_sthyi         380
-#define NR_syscalls 381
-
-/* 
- * There are some system calls that are not present on 64 bit, some
- * have a different name although they do the same (e.g. __NR_chown32
- * is __NR_chown on 64 bit).
- */
-#ifndef __s390x__
-
-#define __NR_time                13
-#define __NR_lchown              16
-#define __NR_setuid              23
-#define __NR_getuid              24
-#define __NR_stime               25
-#define __NR_setgid              46
-#define __NR_getgid              47
-#define __NR_geteuid             49
-#define __NR_getegid             50
-#define __NR_setreuid            70
-#define __NR_setregid            71
-#define __NR_getrlimit           76
-#define __NR_getgroups           80
-#define __NR_setgroups           81
-#define __NR_fchown              95
-#define __NR_ioperm             101
-#define __NR_setfsuid           138
-#define __NR_setfsgid           139
-#define __NR__llseek            140
-#define __NR__newselect         142
-#define __NR_setresuid          164
-#define __NR_getresuid          165
-#define __NR_setresgid          170
-#define __NR_getresgid          171
-#define __NR_chown              182
-#define __NR_ugetrlimit         191     /* SuS compliant getrlimit */
-#define __NR_mmap2              192
-#define __NR_truncate64         193
-#define __NR_ftruncate64        194
-#define __NR_stat64             195
-#define __NR_lstat64            196
-#define __NR_fstat64            197
-#define __NR_lchown32           198
-#define __NR_getuid32           199
-#define __NR_getgid32           200
-#define __NR_geteuid32          201
-#define __NR_getegid32          202
-#define __NR_setreuid32         203
-#define __NR_setregid32         204
-#define __NR_getgroups32        205
-#define __NR_setgroups32        206
-#define __NR_fchown32           207
-#define __NR_setresuid32        208
-#define __NR_getresuid32        209
-#define __NR_setresgid32        210
-#define __NR_getresgid32        211
-#define __NR_chown32            212
-#define __NR_setuid32           213
-#define __NR_setgid32           214
-#define __NR_setfsuid32         215
-#define __NR_setfsgid32         216
-#define __NR_fcntl64            221
-#define __NR_sendfile64         223
-#define __NR_fadvise64_64       264
-#define __NR_fstatat64          293
-
-#else
-
-#define __NR_select             142
-#define __NR_getrlimit          191     /* SuS compliant getrlimit */
-#define __NR_lchown             198
-#define __NR_getuid             199
-#define __NR_getgid             200
-#define __NR_geteuid            201
-#define __NR_getegid            202
-#define __NR_setreuid           203
-#define __NR_setregid           204
-#define __NR_getgroups          205
-#define __NR_setgroups          206
-#define __NR_fchown             207
-#define __NR_setresuid          208
-#define __NR_getresuid          209
-#define __NR_setresgid          210
-#define __NR_getresgid          211
-#define __NR_chown              212
-#define __NR_setuid             213
-#define __NR_setgid             214
-#define __NR_setfsuid           215
-#define __NR_setfsgid           216
-#define __NR_newfstatat         293
-
-#endif
-
-#endif /* _UAPI_ASM_S390_UNISTD_H_ */
diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h
index 1d9199e1c2ad..0dfe4d3f74e2 100644
--- a/tools/arch/x86/include/asm/cpufeatures.h
+++ b/tools/arch/x86/include/asm/cpufeatures.h
@@ -210,6 +210,7 @@
 
 #define X86_FEATURE_MBA                 ( 7*32+18) /* Memory Bandwidth Allocation */
 #define X86_FEATURE_RSB_CTXSW           ( 7*32+19) /* "" Fill RSB on context switches */
+#define X86_FEATURE_SEV                 ( 7*32+20) /* AMD Secure Encrypted Virtualization */
 
 #define X86_FEATURE_USE_IBPB            ( 7*32+21) /* "" Indirect Branch Prediction Barrier enabled */
 
diff --git a/tools/bpf/bpftool/main.c b/tools/bpf/bpftool/main.c
index 3a0396d87c42..185acfa229b5 100644
--- a/tools/bpf/bpftool/main.c
+++ b/tools/bpf/bpftool/main.c
@@ -244,7 +244,7 @@ static int do_batch(int argc, char **argv)
         }
 
         if (errno && errno != ENOENT) {
-                perror("reading batch file failed");
+                p_err("reading batch file failed: %s", strerror(errno));
                 err = -1;
         } else {
                 p_info("processed %d lines", lines);
diff --git a/tools/bpf/bpftool/prog.c b/tools/bpf/bpftool/prog.c
index e8e2baaf93c2..e549e329be82 100644
--- a/tools/bpf/bpftool/prog.c
+++ b/tools/bpf/bpftool/prog.c
@@ -774,6 +774,9 @@ static int do_dump(int argc, char **argv)
                               n < 0 ? strerror(errno) : "short write");
                         goto err_free;
                 }
+
+                if (json_output)
+                        jsonw_null(json_wtr);
         } else {
                 if (member_len == &info.jited_prog_len) {
                         const char *name = NULL;
diff --git a/tools/cgroup/Makefile b/tools/cgroup/Makefile
index 860fa151640a..ffca068e4a76 100644
--- a/tools/cgroup/Makefile
+++ b/tools/cgroup/Makefile
@@ -1,7 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 # Makefile for cgroup tools
 
-CC = $(CROSS_COMPILE)gcc
 CFLAGS = -Wall -Wextra
 
 all: cgroup_event_listener
diff --git a/tools/gpio/Makefile b/tools/gpio/Makefile
index 805a2c0cf4cd..240eda014b37 100644
--- a/tools/gpio/Makefile
+++ b/tools/gpio/Makefile
@@ -12,8 +12,6 @@ endif
 # (this improves performance and avoids hard-to-debug behaviour);
 MAKEFLAGS += -r
 
-CC = $(CROSS_COMPILE)gcc
-LD = $(CROSS_COMPILE)ld
 CFLAGS += -O2 -Wall -g -D_GNU_SOURCE -I$(OUTPUT)include
 
 ALL_TARGETS := lsgpio gpio-hammer gpio-event-mon
diff --git a/tools/hv/Makefile b/tools/hv/Makefile
index 1139d71fa0cf..5db5e62cebda 100644
--- a/tools/hv/Makefile
+++ b/tools/hv/Makefile
@@ -1,7 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 # Makefile for Hyper-V tools
 
-CC = $(CROSS_COMPILE)gcc
 WARNINGS = -Wall -Wextra
 CFLAGS = $(WARNINGS) -g $(shell getconf LFS_CFLAGS)
 
diff --git a/tools/iio/Makefile b/tools/iio/Makefile
index a08e7a47d6a3..332ed2f6c2c2 100644
--- a/tools/iio/Makefile
+++ b/tools/iio/Makefile
@@ -12,8 +12,6 @@ endif
 # (this improves performance and avoids hard-to-debug behaviour);
 MAKEFLAGS += -r
 
-CC = $(CROSS_COMPILE)gcc
-LD = $(CROSS_COMPILE)ld
 CFLAGS += -O2 -Wall -g -D_GNU_SOURCE -I$(OUTPUT)include
 
 ALL_TARGETS := iio_event_monitor lsiio iio_generic_buffer
diff --git a/tools/include/uapi/drm/i915_drm.h b/tools/include/uapi/drm/i915_drm.h
index ac3c6503ca27..536ee4febd74 100644
--- a/tools/include/uapi/drm/i915_drm.h
+++ b/tools/include/uapi/drm/i915_drm.h
@@ -86,6 +86,62 @@ enum i915_mocs_table_index {
         I915_MOCS_CACHED,
 };
 
+/*
+ * Different engines serve different roles, and there may be more than one
+ * engine serving each role. enum drm_i915_gem_engine_class provides a
+ * classification of the role of the engine, which may be used when requesting
+ * operations to be performed on a certain subset of engines, or for providing
+ * information about that group.
+ */
+enum drm_i915_gem_engine_class {
+        I915_ENGINE_CLASS_RENDER        = 0,
+        I915_ENGINE_CLASS_COPY          = 1,
+        I915_ENGINE_CLASS_VIDEO         = 2,
+        I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
+
+        I915_ENGINE_CLASS_INVALID       = -1
+};
+
+/**
+ * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915
+ *
+ */
+
+enum drm_i915_pmu_engine_sample {
+        I915_SAMPLE_BUSY = 0,
+        I915_SAMPLE_WAIT = 1,
+        I915_SAMPLE_SEMA = 2
+};
+
+#define I915_PMU_SAMPLE_BITS (4)
+#define I915_PMU_SAMPLE_MASK (0xf)
+#define I915_PMU_SAMPLE_INSTANCE_BITS (8)
+#define I915_PMU_CLASS_SHIFT \
+        (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS)
+
+#define __I915_PMU_ENGINE(class, instance, sample) \
+        ((class) << I915_PMU_CLASS_SHIFT | \
+        (instance) << I915_PMU_SAMPLE_BITS | \
+        (sample))
+
+#define I915_PMU_ENGINE_BUSY(class, instance) \
+        __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY)
+
+#define I915_PMU_ENGINE_WAIT(class, instance) \
+        __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT)
+
+#define I915_PMU_ENGINE_SEMA(class, instance) \
+        __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA)
+
+#define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x))
+
+#define I915_PMU_ACTUAL_FREQUENCY       __I915_PMU_OTHER(0)
+#define I915_PMU_REQUESTED_FREQUENCY    __I915_PMU_OTHER(1)
+#define I915_PMU_INTERRUPTS             __I915_PMU_OTHER(2)
+#define I915_PMU_RC6_RESIDENCY          __I915_PMU_OTHER(3)
+
+#define I915_PMU_LAST I915_PMU_RC6_RESIDENCY
+
 /* Each region is a minimum of 16k, and there are at most 255 of them.
  */
 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
@@ -450,6 +506,27 @@ typedef struct drm_i915_irq_wait {
  */
 #define I915_PARAM_HAS_EXEC_FENCE_ARRAY  49
 
+/*
+ * Query whether every context (both per-file default and user created) is
+ * isolated (insofar as HW supports). If this parameter is not true, then
+ * freshly created contexts may inherit values from an existing context,
+ * rather than default HW values. If true, it also ensures (insofar as HW
+ * supports) that all state set by this context will not leak to any other
+ * context.
+ *
+ * As not every engine across every gen support contexts, the returned
+ * value reports the support of context isolation for individual engines by
+ * returning a bitmask of each engine class set to true if that class supports
+ * isolation.
+ */
+#define I915_PARAM_HAS_CONTEXT_ISOLATION 50
+
+/* Frequency of the command streamer timestamps given by the *_TIMESTAMP
+ * registers. This used to be fixed per platform but from CNL onwards, this
+ * might vary depending on the parts.
+ */
+#define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51
+
 typedef struct drm_i915_getparam {
         __s32 param;
         /*
diff --git a/tools/include/uapi/linux/if_link.h b/tools/include/uapi/linux/if_link.h
index 8616131e2c61..6d9447700e18 100644
--- a/tools/include/uapi/linux/if_link.h
+++ b/tools/include/uapi/linux/if_link.h
@@ -163,6 +163,7 @@ enum {
         IFLA_IF_NETNSID,
         IFLA_CARRIER_UP_COUNT,
         IFLA_CARRIER_DOWN_COUNT,
+        IFLA_NEW_IFINDEX,
         __IFLA_MAX
 };
 
diff --git a/tools/include/uapi/linux/kvm.h b/tools/include/uapi/linux/kvm.h
index 8fb90a0819c3..0fb5ef939732 100644
--- a/tools/include/uapi/linux/kvm.h
+++ b/tools/include/uapi/linux/kvm.h
@@ -1362,6 +1362,96 @@ struct kvm_s390_ucas_mapping {
 /* Available with KVM_CAP_S390_CMMA_MIGRATION */
 #define KVM_S390_GET_CMMA_BITS      _IOWR(KVMIO, 0xb8, struct kvm_s390_cmma_log)
 #define KVM_S390_SET_CMMA_BITS      _IOW(KVMIO, 0xb9, struct kvm_s390_cmma_log)
+/* Memory Encryption Commands */
+#define KVM_MEMORY_ENCRYPT_OP      _IOWR(KVMIO, 0xba, unsigned long)
+
+struct kvm_enc_region {
+        __u64 addr;
+        __u64 size;
+};
+
+#define KVM_MEMORY_ENCRYPT_REG_REGION    _IOR(KVMIO, 0xbb, struct kvm_enc_region)
+#define KVM_MEMORY_ENCRYPT_UNREG_REGION  _IOR(KVMIO, 0xbc, struct kvm_enc_region)
+
+/* Secure Encrypted Virtualization command */
+enum sev_cmd_id {
+        /* Guest initialization commands */
+        KVM_SEV_INIT = 0,
+        KVM_SEV_ES_INIT,
+        /* Guest launch commands */
+        KVM_SEV_LAUNCH_START,
+        KVM_SEV_LAUNCH_UPDATE_DATA,
+        KVM_SEV_LAUNCH_UPDATE_VMSA,
+        KVM_SEV_LAUNCH_SECRET,
+        KVM_SEV_LAUNCH_MEASURE,
+        KVM_SEV_LAUNCH_FINISH,
+        /* Guest migration commands (outgoing) */
+        KVM_SEV_SEND_START,
+        KVM_SEV_SEND_UPDATE_DATA,
+        KVM_SEV_SEND_UPDATE_VMSA,
+        KVM_SEV_SEND_FINISH,
+        /* Guest migration commands (incoming) */
+        KVM_SEV_RECEIVE_START,
+        KVM_SEV_RECEIVE_UPDATE_DATA,
+        KVM_SEV_RECEIVE_UPDATE_VMSA,
+        KVM_SEV_RECEIVE_FINISH,
+        /* Guest status and debug commands */
+        KVM_SEV_GUEST_STATUS,
+        KVM_SEV_DBG_DECRYPT,
+        KVM_SEV_DBG_ENCRYPT,
+        /* Guest certificates commands */
+        KVM_SEV_CERT_EXPORT,
+
+        KVM_SEV_NR_MAX,
+};
+
+struct kvm_sev_cmd {
+        __u32 id;
+        __u64 data;
+        __u32 error;
+        __u32 sev_fd;
+};
+
+struct kvm_sev_launch_start {
+        __u32 handle;
+        __u32 policy;
+        __u64 dh_uaddr;
+        __u32 dh_len;
+        __u64 session_uaddr;
+        __u32 session_len;
+};
+
+struct kvm_sev_launch_update_data {
+        __u64 uaddr;
+        __u32 len;
+};
+
+
+struct kvm_sev_launch_secret {
+        __u64 hdr_uaddr;
+        __u32 hdr_len;
+        __u64 guest_uaddr;
+        __u32 guest_len;
+        __u64 trans_uaddr;
+        __u32 trans_len;
+};
+
+struct kvm_sev_launch_measure {
+        __u64 uaddr;
+        __u32 len;
+};
+
+struct kvm_sev_guest_status {
+        __u32 handle;
+        __u32 policy;
+        __u32 state;
+};
+
+struct kvm_sev_dbg {
+        __u64 src_uaddr;
+        __u64 dst_uaddr;
+        __u32 len;
+};
 
 #define KVM_DEV_ASSIGN_ENABLE_IOMMU     (1 << 0)
 #define KVM_DEV_ASSIGN_PCI_2_3          (1 << 1)
diff --git a/tools/kvm/kvm_stat/kvm_stat b/tools/kvm/kvm_stat/kvm_stat
index a5684d0968b4..5898c22ba310 100755
--- a/tools/kvm/kvm_stat/kvm_stat
+++ b/tools/kvm/kvm_stat/kvm_stat
@@ -33,7 +33,7 @@ import resource
 import struct
 import re
 import subprocess
-from collections import defaultdict
+from collections import defaultdict, namedtuple
 
 VMX_EXIT_REASONS = {
     'EXCEPTION_NMI':        0,
@@ -228,6 +228,7 @@ IOCTL_NUMBERS = {
 }
 
 ENCODING = locale.getpreferredencoding(False)
+TRACE_FILTER = re.compile(r'^[^\(]*$')
 
 
 class Arch(object):
@@ -260,6 +261,11 @@ class Arch(object):
                     return ArchX86(SVM_EXIT_REASONS)
                 return
 
+    def tracepoint_is_child(self, field):
+        if (TRACE_FILTER.match(field)):
+            return None
+        return field.split('(', 1)[0]
+
 
 class ArchX86(Arch):
     def __init__(self, exit_reasons):
@@ -267,6 +273,10 @@ class ArchX86(Arch):
         self.ioctl_numbers = IOCTL_NUMBERS
         self.exit_reasons = exit_reasons
 
+    def debugfs_is_child(self, field):
+        """ Returns name of parent if 'field' is a child, None otherwise """
+        return None
+
 
 class ArchPPC(Arch):
     def __init__(self):
@@ -282,6 +292,10 @@ class ArchPPC(Arch):
         self.ioctl_numbers['SET_FILTER'] = 0x80002406 | char_ptr_size << 16
         self.exit_reasons = {}
 
+    def debugfs_is_child(self, field):
+        """ Returns name of parent if 'field' is a child, None otherwise """
+        return None
+
 
 class ArchA64(Arch):
     def __init__(self):
@@ -289,6 +303,10 @@ class ArchA64(Arch):
         self.ioctl_numbers = IOCTL_NUMBERS
         self.exit_reasons = AARCH64_EXIT_REASONS
 
+    def debugfs_is_child(self, field):
+        """ Returns name of parent if 'field' is a child, None otherwise """
+        return None
+
 
 class ArchS390(Arch):
     def __init__(self):
@@ -296,6 +314,12 @@ class ArchS390(Arch):
         self.ioctl_numbers = IOCTL_NUMBERS
         self.exit_reasons = None
 
+    def debugfs_is_child(self, field):
+        """ Returns name of parent if 'field' is a child, None otherwise """
+        if field.startswith('instruction_'):
+            return 'exit_instruction'
+
+
 ARCH = Arch.get_arch()
 
 
@@ -331,9 +355,6 @@ class perf_event_attr(ctypes.Structure):
 PERF_TYPE_TRACEPOINT = 2
 PERF_FORMAT_GROUP = 1 << 3
 
-PATH_DEBUGFS_TRACING = '/sys/kernel/debug/tracing'
-PATH_DEBUGFS_KVM = '/sys/kernel/debug/kvm'
-
 
 class Group(object):
     """Represents a perf event group."""
@@ -376,8 +397,8 @@ class Event(object):
         self.syscall = self.libc.syscall
         self.name = name
         self.fd = None
-        self.setup_event(group, trace_cpu, trace_pid, trace_point,
-                         trace_filter, trace_set)
+        self._setup_event(group, trace_cpu, trace_pid, trace_point,
+                          trace_filter, trace_set)
 
     def __del__(self):
         """Closes the event's file descriptor.
@@ -390,7 +411,7 @@ class Event(object):
         if self.fd:
             os.close(self.fd)
 
-    def perf_event_open(self, attr, pid, cpu, group_fd, flags):
+    def _perf_event_open(self, attr, pid, cpu, group_fd, flags):
         """Wrapper for the sys_perf_evt_open() syscall.
 
         Used to set up performance events, returns a file descriptor or -1
@@ -409,7 +430,7 @@ class Event(object):
                             ctypes.c_int(pid), ctypes.c_int(cpu),
                             ctypes.c_int(group_fd), ctypes.c_long(flags))
 
-    def setup_event_attribute(self, trace_set, trace_point):
+    def _setup_event_attribute(self, trace_set, trace_point):
         """Returns an initialized ctype perf_event_attr struct."""
 
         id_path = os.path.join(PATH_DEBUGFS_TRACING, 'events', trace_set,
@@ -419,8 +440,8 @@ class Event(object):
         event_attr.config = int(open(id_path).read())
         return event_attr
 
-    def setup_event(self, group, trace_cpu, trace_pid, trace_point,
-                    trace_filter, trace_set):
+    def _setup_event(self, group, trace_cpu, trace_pid, trace_point,
+                     trace_filter, trace_set):
         """Sets up the perf event in Linux.
 
         Issues the syscall to register the event in the kernel and
@@ -428,7 +449,7 @@ class Event(object):
 
         """
 
-        event_attr = self.setup_event_attribute(trace_set, trace_point)
+        event_attr = self._setup_event_attribute(trace_set, trace_point)
 
         # First event will be group leader.
         group_leader = -1
@@ -437,8 +458,8 @@ class Event(object):
         if group.events:
             group_leader = group.events[0].fd
 
-        fd = self.perf_event_open(event_attr, trace_pid,
-                                  trace_cpu, group_leader, 0)
+        fd = self._perf_event_open(event_attr, trace_pid,
+                                   trace_cpu, group_leader, 0)
         if fd == -1:
             err = ctypes.get_errno()
             raise OSError(err, os.strerror(err),
@@ -475,6 +496,10 @@ class Event(object):
 
 class Provider(object):
     """Encapsulates functionalities used by all providers."""
+    def __init__(self, pid):
+        self.child_events = False
+        self.pid = pid
+
     @staticmethod
     def is_field_wanted(fields_filter, field):
         """Indicate whether field is valid according to fields_filter."""
@@ -500,12 +525,12 @@ class TracepointProvider(Provider):
     """
     def __init__(self, pid, fields_filter):
         self.group_leaders = []
-        self.filters = self.get_filters()
+        self.filters = self._get_filters()
         self.update_fields(fields_filter)
-        self.pid = pid
+        super(TracepointProvider, self).__init__(pid)
 
     @staticmethod
-    def get_filters():
+    def _get_filters():
         """Returns a dict of trace events, their filter ids and
         the values that can be filtered.
 
@@ -521,8 +546,8 @@ class TracepointProvider(Provider):
             filters['kvm_exit'] = ('exit_reason', ARCH.exit_reasons)
         return filters
 
-    def get_available_fields(self):
-        """Returns a list of available event's of format 'event name(filter
+    def _get_available_fields(self):
+        """Returns a list of available events of format 'event name(filter
         name)'.
 
         All available events have directories under
@@ -549,11 +574,12 @@ class TracepointProvider(Provider):
 
     def update_fields(self, fields_filter):
         """Refresh fields, applying fields_filter"""
-        self.fields = [field for field in self.get_available_fields()
-                       if self.is_field_wanted(fields_filter, field)]
+        self.fields = [field for field in self._get_available_fields()
+                       if self.is_field_wanted(fields_filter, field) or
+                       ARCH.tracepoint_is_child(field)]
 
     @staticmethod
-    def get_online_cpus():
+    def _get_online_cpus():
         """Returns a list of cpu id integers."""
         def parse_int_list(list_string):
             """Returns an int list from a string of comma separated integers and
@@ -575,17 +601,17 @@ class TracepointProvider(Provider):
             cpu_string = cpu_list.readline()
             return parse_int_list(cpu_string)
 
-    def setup_traces(self):
+    def _setup_traces(self):
         """Creates all event and group objects needed to be able to retrieve
         data."""
-        fields = self.get_available_fields()
+        fields = self._get_available_fields()
         if self._pid > 0:
             # Fetch list of all threads of the monitored pid, as qemu
             # starts a thread for each vcpu.
             path = os.path.join('/proc', str(self._pid), 'task')
             groupids = self.walkdir(path)[1]
         else:
-            groupids = self.get_online_cpus()
+            groupids = self._get_online_cpus()
 
         # The constant is needed as a buffer for python libs, std
         # streams and other files that the script opens.
@@ -663,7 +689,7 @@ class TracepointProvider(Provider):
         # The garbage collector will get rid of all Event/Group
         # objects and open files after removing the references.
         self.group_leaders = []
-        self.setup_traces()
+        self._setup_traces()
         self.fields = self._fields
 
     def read(self, by_guest=0):
@@ -671,8 +697,12 @@ class TracepointProvider(Provider):
         ret = defaultdict(int)
         for group in self.group_leaders:
             for name, val in group.read().items():
-                if name in self._fields:
-                    ret[name] += val
+                if name not in self._fields:
+                    continue
+                parent = ARCH.tracepoint_is_child(name)
+                if parent:
+                    name += ' ' + parent
+                ret[name] += val
         return ret
 
     def reset(self):
@@ -690,11 +720,11 @@ class DebugfsProvider(Provider):
         self._baseline = {}
         self.do_read = True
         self.paths = []
-        self.pid = pid
+        super(DebugfsProvider, self).__init__(pid)
         if include_past:
-            self.restore()
+            self._restore()
 
-    def get_available_fields(self):
+    def _get_available_fields(self):
         """"Returns a list of available fields.
 
         The fields are all available KVM debugfs files
@@ -704,8 +734,9 @@ class DebugfsProvider(Provider):
 
     def update_fields(self, fields_filter):
         """Refresh fields, applying fields_filter"""
-        self._fields = [field for field in self.get_available_fields()
-                        if self.is_field_wanted(fields_filter, field)]
+        self._fields = [field for field in self._get_available_fields()
+                        if self.is_field_wanted(fields_filter, field) or
+                        ARCH.debugfs_is_child(field)]
 
     @property
     def fields(self):
@@ -758,7 +789,7 @@ class DebugfsProvider(Provider):
                     paths.append(dir)
         for path in paths:
             for field in self._fields:
-                value = self.read_field(field, path)
+                value = self._read_field(field, path)
                 key = path + field
                 if reset == 1:
                     self._baseline[key] = value
@@ -766,20 +797,21 @@ class DebugfsProvider(Provider):
                     self._baseline[key] = 0
                 if self._baseline.get(key, -1) == -1:
                     self._baseline[key] = value
-                increment = (results.get(field, 0) + value -
-                             self._baseline.get(key, 0))
-                if by_guest:
-                    pid = key.split('-')[0]
-                    if pid in results:
-                        results[pid] += increment
-                    else:
-                        results[pid] = increment
+                parent = ARCH.debugfs_is_child(field)
+                if parent:
+                    field = field + ' ' + parent
+                else:
+                    if by_guest:
+                        field = key.split('-')[0]    # set 'field' to 'pid'
+                increment = value - self._baseline.get(key, 0)
+                if field in results:
+                    results[field] += increment
                 else:
                     results[field] = increment
 
         return results
 
-    def read_field(self, field, path):
+    def _read_field(self, field, path):
         """Returns the value of a single field from a specific VM."""
         try:
             return int(open(os.path.join(PATH_DEBUGFS_KVM,
@@ -794,12 +826,15 @@ class DebugfsProvider(Provider):
         self._baseline = {}
         self.read(1)
 
-    def restore(self):
+    def _restore(self):
         """Reset field counters"""
         self._baseline = {}
         self.read(2)
 
 
+EventStat = namedtuple('EventStat', ['value', 'delta'])
+
+
 class Stats(object):
     """Manages the data providers and the data they provide.
 
@@ -808,13 +843,13 @@ class Stats(object):
 
     """
     def __init__(self, options):
-        self.providers = self.get_providers(options)
+        self.providers = self._get_providers(options)
         self._pid_filter = options.pid
         self._fields_filter = options.fields
         self.values = {}
+        self._child_events = False
 
-    @staticmethod
-    def get_providers(options):
+    def _get_providers(self, options):
         """Returns a list of data providers depending on the passed options."""
         providers = []
 
@@ -826,7 +861,7 @@ class Stats(object):
 
         return providers
 
-    def update_provider_filters(self):
+    def _update_provider_filters(self):
         """Propagates fields filters to providers."""
         # As we reset the counters when updating the fields we can
         # also clear the cache of old values.
@@ -847,7 +882,7 @@ class Stats(object):
     def fields_filter(self, fields_filter):
         if fields_filter != self._fields_filter:
             self._fields_filter = fields_filter
-            self.update_provider_filters()
+            self._update_provider_filters()
 
     @property
     def pid_filter(self):
@@ -861,16 +896,33 @@ class Stats(object):
             for provider in self.providers:
                 provider.pid = self._pid_filter
 
+    @property
+    def child_events(self):
+        return self._child_events
+
+    @child_events.setter
+    def child_events(self, val):
+        self._child_events = val
+        for provider in self.providers:
+            provider.child_events = val
+
     def get(self, by_guest=0):
         """Returns a dict with field -> (value, delta to last value) of all
-        provider data."""
+        provider data.
+        Key formats:
+          * plain: 'key' is event name
+          * child-parent: 'key' is in format '<child> <parent>'
+          * pid: 'key' is the pid of the guest, and the record contains the
+               aggregated event data
+        These formats are generated by the providers, and handled in class TUI.
+        """
         for provider in self.providers:
             new = provider.read(by_guest=by_guest)
-            for key in new if by_guest else provider.fields:
-                oldval = self.values.get(key, (0, 0))[0]
+            for key in new:
+                oldval = self.values.get(key, EventStat(0, 0)).value
                 newval = new.get(key, 0)
                 newdelta = newval - oldval
-                self.values[key] = (newval, newdelta)
+                self.values[key] = EventStat(newval, newdelta)
         return self.values
 
     def toggle_display_guests(self, to_pid):
@@ -899,10 +951,10 @@ class Stats(object):
         self.get(to_pid)
         return 0
 
+
 DELAY_DEFAULT = 3.0
 MAX_GUEST_NAME_LEN = 48
 MAX_REGEX_LEN = 44
-DEFAULT_REGEX = r'^[^\(]*$'
 SORT_DEFAULT = 0
 
 
@@ -969,7 +1021,7 @@ class Tui(object):
 
         return res
 
-    def print_all_gnames(self, row):
+    def _print_all_gnames(self, row):
         """Print a list of all running guests along with their pids."""
         self.screen.addstr(row, 2, '%8s  %-60s' %
                            ('Pid', 'Guest Name (fuzzy list, might be '
@@ -1032,19 +1084,13 @@ class Tui(object):
 
         return name
 
-    def update_drilldown(self):
-        """Sets or removes a filter that only allows fields without braces."""
-        if not self.stats.fields_filter:
-            self.stats.fields_filter = DEFAULT_REGEX
-
-        elif self.stats.fields_filter == DEFAULT_REGEX:
-            self.stats.fields_filter = None
-
-    def update_pid(self, pid):
+    def _update_pid(self, pid):
         """Propagates pid selection to stats object."""
+        self.screen.addstr(4, 1, 'Updating pid filter...')
+        self.screen.refresh()
         self.stats.pid_filter = pid
 
-    def refresh_header(self, pid=None):
+    def _refresh_header(self, pid=None):
         """Refreshes the header."""
         if pid is None:
             pid = self.stats.pid_filter
@@ -1059,8 +1105,7 @@ class Tui(object):
                                .format(pid, gname), curses.A_BOLD)
         else:
             self.screen.addstr(0, 0, 'kvm statistics - summary', curses.A_BOLD)
-        if self.stats.fields_filter and self.stats.fields_filter \
-           != DEFAULT_REGEX:
+        if self.stats.fields_filter:
             regex = self.stats.fields_filter
             if len(regex) > MAX_REGEX_LEN:
                 regex = regex[:MAX_REGEX_LEN] + '...'
@@ -1075,56 +1120,99 @@ class Tui(object):
         self.screen.addstr(4, 1, 'Collecting data...')
         self.screen.refresh()
 
-    def refresh_body(self, sleeptime):
+    def _refresh_body(self, sleeptime):
+        def is_child_field(field):
+            return field.find('(') != -1
+
+        def insert_child(sorted_items, child, values, parent):
+            num = len(sorted_items)
+            for i in range(0, num):
+                # only add child if parent is present
+                if parent.startswith(sorted_items[i][0]):
+                    sorted_items.insert(i + 1, ('  ' + child, values))
+
+        def get_sorted_events(self, stats):
+            """ separate parent and child events """
+            if self._sorting == SORT_DEFAULT:
+                def sortkey((_k, v)):
+                    # sort by (delta value, overall value)
+                    return (v.delta, v.value)
+            else:
+                def sortkey((_k, v)):
+                    # sort by overall value
+                    return v.value
+
+            childs = []
+            sorted_items = []
+            # we can't rule out child events to appear prior to parents even
+            # when sorted - separate out all children first, and add in later
+            for key, values in sorted(stats.items(), key=sortkey,
+                                      reverse=True):
+                if values == (0, 0):
+                    continue
+                if key.find(' ') != -1:
+                    if not self.stats.child_events:
+                        continue
+                    childs.insert(0, (key, values))
+                else:
+                    sorted_items.append((key, values))
+            if self.stats.child_events:
+                for key, values in childs:
+                    (child, parent) = key.split(' ')
+                    insert_child(sorted_items, child, values, parent)
+
+            return sorted_items
+
         row = 3
         self.screen.move(row, 0)
         self.screen.clrtobot()
         stats = self.stats.get(self._display_guests)
-
-        def sortCurAvg(x):
-            # sort by current events if available
-            if stats[x][1]:
-                return (-stats[x][1], -stats[x][0])
+        total = 0.
+        ctotal = 0.
+        for key, values in stats.items():
+            if self._display_guests:
+                if self.get_gname_from_pid(key):
+                    total += values.value
+                continue
+            if not key.find(' ') != -1:
+                total += values.value
             else:
-                return (0, -stats[x][0])
+                ctotal += values.value
+        if total == 0.:
+            # we don't have any fields, or all non-child events are filtered
+            total = ctotal
 
-        def sortTotal(x):
-            # sort by totals
-            return (0, -stats[x][0])
-        total = 0.
-        for key in stats.keys():
-            if key.find('(') is -1:
-                total += stats[key][0]
-        if self._sorting == SORT_DEFAULT:
-            sortkey = sortCurAvg
-        else:
-            sortkey = sortTotal
+        # print events
         tavg = 0
-        for key in sorted(stats.keys(), key=sortkey):
-            if row >= self.screen.getmaxyx()[0] - 1:
-                break
-            values = stats[key]
-            if not values[0] and not values[1]:
+        tcur = 0
+        for key, values in get_sorted_events(self, stats):
+            if row >= self.screen.getmaxyx()[0] - 1 or values == (0, 0):
                 break
-            if values[0] is not None:
-                cur = int(round(values[1] / sleeptime)) if values[1] else ''
-                if self._display_guests:
-                    key = self.get_gname_from_pid(key)
-                self.screen.addstr(row, 1, '%-40s %10d%7.1f %8s' %
-                                   (key, values[0], values[0] * 100 / total,
-                                    cur))
-                if cur is not '' and key.find('(') is -1:
-                    tavg += cur
+            if self._display_guests:
+                key = self.get_gname_from_pid(key)
+                if not key:
+                    continue
+            cur = int(round(values.delta / sleeptime)) if values.delta else ''
+            if key[0] != ' ':
+                if values.delta:
+                    tcur += values.delta
+                ptotal = values.value
+                ltotal = total
+            else:
+                ltotal = ptotal
+            self.screen.addstr(row, 1, '%-40s %10d%7.1f %8s' % (key,
+                               values.value,
+                               values.value * 100 / float(ltotal), cur))
             row += 1
         if row == 3:
             self.screen.addstr(4, 1, 'No matching events reported yet')
-        else:
+        if row > 4:
+            tavg = int(round(tcur / sleeptime)) if tcur > 0 else ''
             self.screen.addstr(row, 1, '%-40s %10d        %8s' %
-                               ('Total', total, tavg if tavg else ''),
-                               curses.A_BOLD)
+                               ('Total', total, tavg), curses.A_BOLD)
         self.screen.refresh()
 
-    def show_msg(self, text):
+    def _show_msg(self, text):
         """Display message centered text and exit on key press"""
         hint = 'Press any key to continue'
         curses.cbreak()
@@ -1139,16 +1227,16 @@ class Tui(object):
                            curses.A_STANDOUT)
         self.screen.getkey()
 
-    def show_help_interactive(self):
+    def _show_help_interactive(self):
         """Display help with list of interactive commands"""
         msg = ('   b     toggle events by guests (debugfs only, honors'
                ' filters)',
                '   c     clear filter',
                '   f     filter by regular expression',
-               '   g     filter by guest name',
+               '   g     filter by guest name/PID',
                '   h     display interactive commands reference',
                '   o     toggle sorting order (Total vs CurAvg/s)',
-               '   p     filter by PID',
+               '   p     filter by guest name/PID',
                '   q     quit',
                '   r     reset stats',
                '   s     set update interval',
@@ -1165,14 +1253,15 @@ class Tui(object):
             self.screen.addstr(row, 0, line)
             row += 1
         self.screen.getkey()
-        self.refresh_header()
+        self._refresh_header()
 
-    def show_filter_selection(self):
+    def _show_filter_selection(self):
         """Draws filter selection mask.
 
         Asks for a valid regex and sets the fields filter accordingly.
 
         """
+        msg = ''
         while True:
             self.screen.erase()
             self.screen.addstr(0, 0,
@@ -1181,61 +1270,25 @@ class Tui(object):
             self.screen.addstr(2, 0,
                                "Current regex: {0}"
                                .format(self.stats.fields_filter))
+            self.screen.addstr(5, 0, msg)
             self.screen.addstr(3, 0, "New regex: ")
             curses.echo()
             regex = self.screen.getstr().decode(ENCODING)
             curses.noecho()
             if len(regex) == 0:
-                self.stats.fields_filter = DEFAULT_REGEX
-                self.refresh_header()
+                self.stats.fields_filter = ''
+                self._refresh_header()
                 return
             try:
                 re.compile(regex)
                 self.stats.fields_filter = regex
-                self.refresh_header()
+                self._refresh_header()
                 return
             except re.error:
+                msg = '"' + regex + '": Not a valid regular expression'
                 continue
 
-    def show_vm_selection_by_pid(self):
-        """Draws PID selection mask.
-
-        Asks for a pid until a valid pid or 0 has been entered.
-
-        """
-        msg = ''
-        while True:
-            self.screen.erase()
-            self.screen.addstr(0, 0,
-                               'Show statistics for specific pid.',
-                               curses.A_BOLD)
-            self.screen.addstr(1, 0,
-                               'This might limit the shown data to the trace '
-                               'statistics.')
-            self.screen.addstr(5, 0, msg)
-            self.print_all_gnames(7)
-
-            curses.echo()
-            self.screen.addstr(3, 0, "Pid [0 or pid]: ")
-            pid = self.screen.getstr().decode(ENCODING)
-            curses.noecho()
-
-            try:
-                if len(pid) > 0:
-                    pid = int(pid)
-                    if pid != 0 and not os.path.isdir(os.path.join('/proc/',
-                                                                   str(pid))):
-                        msg = '"' + str(pid) + '": Not a running process'
-                        continue
-                else:
-                    pid = 0
-                self.refresh_header(pid)
-                self.update_pid(pid)
-                break
-            except ValueError:
-                msg = '"' + str(pid) + '": Not a valid pid'
-
-    def show_set_update_interval(self):
+    def _show_set_update_interval(self):
         """Draws update interval selection mask."""
         msg = ''
         while True:
@@ -1265,60 +1318,67 @@ class Tui(object):
 
             except ValueError:
                 msg = '"' + str(val) + '": Invalid value'
-        self.refresh_header()
+        self._refresh_header()
 
-    def show_vm_selection_by_guest_name(self):
+    def _show_vm_selection_by_guest(self):
         """Draws guest selection mask.
 
-        Asks for a guest name until a valid guest name or '' is entered.
+        Asks for a guest name or pid until a valid guest name or '' is entered.
 
         """
         msg = ''
         while True:
             self.screen.erase()
             self.screen.addstr(0, 0,
-                               'Show statistics for specific guest.',
+                               'Show statistics for specific guest or pid.',
                                curses.A_BOLD)
             self.screen.addstr(1, 0,
                                'This might limit the shown data to the trace '
                                'statistics.')
             self.screen.addstr(5, 0, msg)
-            self.print_all_gnames(7)
+            self._print_all_gnames(7)
             curses.echo()
-            self.screen.addstr(3, 0, "Guest [ENTER or guest]: ")
-            gname = self.screen.getstr().decode(ENCODING)
+            curses.curs_set(1)
+            self.screen.addstr(3, 0, "Guest or pid [ENTER exits]: ")
+            guest = self.screen.getstr().decode(ENCODING)
             curses.noecho()
 
-            if not gname:
-                self.refresh_header(0)
-                self.update_pid(0)
+            pid = 0
+            if not guest or guest == '0':
                 break
-            else:
-                pids = []
-                try:
-                    pids = self.get_pid_from_gname(gname)
-                except:
-                    msg = '"' + gname + '": Internal error while searching, ' \
-                          'use pid filter instead'
-                    continue
-                if len(pids) == 0:
-                    msg = '"' + gname + '": Not an active guest'
+            if guest.isdigit():
+                if not os.path.isdir(os.path.join('/proc/', guest)):
+                    msg = '"' + guest + '": Not a running process'
                     continue
-                if len(pids) > 1:
-                    msg = '"' + gname + '": Multiple matches found, use pid ' \
-                          'filter instead'
-                    continue
-                self.refresh_header(pids[0])
-                self.update_pid(pids[0])
+                pid = int(guest)
                 break
+            pids = []
+            try:
+                pids = self.get_pid_from_gname(guest)
+            except:
+                msg = '"' + guest + '": Internal error while searching, ' \
+                      'use pid filter instead'
+                continue
+            if len(pids) == 0:
+                msg = '"' + guest + '": Not an active guest'
+                continue
+            if len(pids) > 1:
+                msg = '"' + guest + '": Multiple matches found, use pid ' \
+                      'filter instead'
+                continue
+            pid = pids[0]
+            break
+        curses.curs_set(0)
+        self._refresh_header(pid)
+        self._update_pid(pid)
 
     def show_stats(self):
         """Refreshes the screen and processes user input."""
         sleeptime = self._delay_initial
-        self.refresh_header()
+        self._refresh_header()
         start = 0.0  # result based on init value never appears on screen
         while True:
-            self.refresh_body(time.time() - start)
+            self._refresh_body(time.time() - start)
             curses.halfdelay(int(sleeptime * 10))
             start = time.time()
             sleeptime = self._delay_regular
@@ -1327,47 +1387,39 @@ class Tui(object):
                 if char == 'b':
                     self._display_guests = not self._display_guests
                     if self.stats.toggle_display_guests(self._display_guests):
-                        self.show_msg(['Command not available with tracepoints'
-                                       ' enabled', 'Restart with debugfs only '
-                                       '(see option \'-d\') and try again!'])
+                        self._show_msg(['Command not available with '
+                                        'tracepoints enabled', 'Restart with '
+                                        'debugfs only (see option \'-d\') and '
+                                        'try again!'])
                         self._display_guests = not self._display_guests
-                    self.refresh_header()
+                    self._refresh_header()
                 if char == 'c':
-                    self.stats.fields_filter = DEFAULT_REGEX
-                    self.refresh_header(0)
-                    self.update_pid(0)
+                    self.stats.fields_filter = ''
+                    self._refresh_header(0)
+                    self._update_pid(0)
                 if char == 'f':
                     curses.curs_set(1)
-                    self.show_filter_selection()
+                    self._show_filter_selection()
                     curses.curs_set(0)
                     sleeptime = self._delay_initial
-                if char == 'g':
-                    curses.curs_set(1)
-                    self.show_vm_selection_by_guest_name()
-                    curses.curs_set(0)
+                if char == 'g' or char == 'p':
+                    self._show_vm_selection_by_guest()
                     sleeptime = self._delay_initial
                 if char == 'h':
-                    self.show_help_interactive()
+                    self._show_help_interactive()
                 if char == 'o':
                     self._sorting = not self._sorting
-                if char == 'p':
-                    curses.curs_set(1)
-                    self.show_vm_selection_by_pid()
-                    curses.curs_set(0)
-                    sleeptime = self._delay_initial
                 if char == 'q':
                     break
                 if char == 'r':
                     self.stats.reset()
                 if char == 's':
                     curses.curs_set(1)
-                    self.show_set_update_interval()
+                    self._show_set_update_interval()
                     curses.curs_set(0)
                     sleeptime = self._delay_initial
                 if char == 'x':
-                    self.update_drilldown()
-                    # prevents display of current values on next refresh
-                    self.stats.get(self._display_guests)
+                    self.stats.child_events = not self.stats.child_events
             except KeyboardInterrupt:
                 break
             except curses.error:
@@ -1380,9 +1432,9 @@ def batch(stats):
         s = stats.get()
         time.sleep(1)
         s = stats.get()
-        for key in sorted(s.keys()):
-            values = s[key]
-            print('%-42s%10d%10d' % (key, values[0], values[1]))
+        for key, values in sorted(s.items()):
+            print('%-42s%10d%10d' % (key.split(' ')[0], values.value,
+                  values.delta))
     except KeyboardInterrupt:
         pass
 
@@ -1392,14 +1444,14 @@ def log(stats):
     keys = sorted(stats.get().keys())
 
     def banner():
-        for k in keys:
-            print(k, end=' ')
+        for key in keys:
+            print(key.split(' ')[0], end=' ')
         print()
 
     def statline():
         s = stats.get()
-        for k in keys:
-            print(' %9d' % s[k][1], end=' ')
+        for key in keys:
+            print(' %9d' % s[key].delta, end=' ')
         print()
     line = 0
     banner_repeat = 20
@@ -1504,7 +1556,7 @@ Press any other key to refresh statistics immediately.
                          )
     optparser.add_option('-f', '--fields',
                          action='store',
-                         default=DEFAULT_REGEX,
+                         default='',
                          dest='fields',
                          help='''fields to display (regex)
                                  "-f help" for a list of available events''',
@@ -1539,17 +1591,6 @@ Press any other key to refresh statistics immediately.
 
 def check_access(options):
     """Exits if the current user can't access all needed directories."""
-    if not os.path.exists('/sys/kernel/debug'):
-        sys.stderr.write('Please enable CONFIG_DEBUG_FS in your kernel.')
-        sys.exit(1)
-
-    if not os.path.exists(PATH_DEBUGFS_KVM):
-        sys.stderr.write("Please make sure, that debugfs is mounted and "
-                         "readable by the current user:\n"
-                         "('mount -t debugfs debugfs /sys/kernel/debug')\n"
-                         "Also ensure, that the kvm modules are loaded.\n")
-        sys.exit(1)
-
     if not os.path.exists(PATH_DEBUGFS_TRACING) and (options.tracepoints or
                                                      not options.debugfs):
         sys.stderr.write("Please enable CONFIG_TRACING in your kernel "
@@ -1567,7 +1608,33 @@ def check_access(options):
     return options
 
 
+def assign_globals():
+    global PATH_DEBUGFS_KVM
+    global PATH_DEBUGFS_TRACING
+
+    debugfs = ''
+    for line in file('/proc/mounts'):
+        if line.split(' ')[0] == 'debugfs':
+            debugfs = line.split(' ')[1]
+            break
+    if debugfs == '':
+        sys.stderr.write("Please make sure that CONFIG_DEBUG_FS is enabled in "
+                         "your kernel, mounted and\nreadable by the current "
+                         "user:\n"
+                         "('mount -t debugfs debugfs /sys/kernel/debug')\n")
+        sys.exit(1)
+
+    PATH_DEBUGFS_KVM = os.path.join(debugfs, 'kvm')
+    PATH_DEBUGFS_TRACING = os.path.join(debugfs, 'tracing')
+
+    if not os.path.exists(PATH_DEBUGFS_KVM):
+        sys.stderr.write("Please make sure that CONFIG_KVM is enabled in "
+                         "your kernel and that the modules are loaded.\n")
+        sys.exit(1)
+
+
 def main():
+    assign_globals()
     options = get_options()
     options = check_access(options)
 
diff --git a/tools/kvm/kvm_stat/kvm_stat.txt b/tools/kvm/kvm_stat/kvm_stat.txt
index b5b3810c9e94..0811d860fe75 100644
--- a/tools/kvm/kvm_stat/kvm_stat.txt
+++ b/tools/kvm/kvm_stat/kvm_stat.txt
@@ -35,13 +35,13 @@ INTERACTIVE COMMANDS
 
 *f*::   filter by regular expression
 
-*g*::   filter by guest name
+*g*::   filter by guest name/PID
 
 *h*::   display interactive commands reference
 
 *o*::   toggle sorting order (Total vs CurAvg/s)
 
-*p*::   filter by PID
+*p*::   filter by guest name/PID
 
 *q*::   quit
 
diff --git a/tools/laptop/freefall/Makefile b/tools/laptop/freefall/Makefile
index 5f758c489a20..b572d94255f6 100644
--- a/tools/laptop/freefall/Makefile
+++ b/tools/laptop/freefall/Makefile
@@ -2,7 +2,6 @@
 PREFIX ?= /usr
 SBINDIR ?= sbin
 INSTALL ?= install
-CC = $(CROSS_COMPILE)gcc
 
 TARGET = freefall
 
diff --git a/tools/leds/Makefile b/tools/leds/Makefile
index c379af003807..7b6bed13daaa 100644
--- a/tools/leds/Makefile
+++ b/tools/leds/Makefile
@@ -1,7 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 # Makefile for LEDs tools
 
-CC = $(CROSS_COMPILE)gcc
 CFLAGS = -Wall -Wextra -g -I../../include/uapi
 
 all: uledmon led_hw_brightness_mon
diff --git a/tools/lib/bpf/libbpf.c b/tools/lib/bpf/libbpf.c
index 97073d649c1a..5bbbf285af74 100644
--- a/tools/lib/bpf/libbpf.c
+++ b/tools/lib/bpf/libbpf.c
@@ -1060,11 +1060,12 @@ bpf_program__reloc_text(struct bpf_program *prog, struct bpf_object *obj,
                 prog->insns = new_insn;
                 prog->main_prog_cnt = prog->insns_cnt;
                 prog->insns_cnt = new_cnt;
+                pr_debug("added %zd insn from %s to prog %s\n",
+                         text->insns_cnt, text->section_name,
+                         prog->section_name);
         }
         insn = &prog->insns[relo->insn_idx];
         insn->imm += prog->main_prog_cnt - relo->insn_idx;
-        pr_debug("added %zd insn from %s to prog %s\n",
-                 text->insns_cnt, text->section_name, prog->section_name);
         return 0;
 }
 
diff --git a/tools/objtool/builtin-check.c b/tools/objtool/builtin-check.c
index 57254f5b2779..694abc628e9b 100644
--- a/tools/objtool/builtin-check.c
+++ b/tools/objtool/builtin-check.c
@@ -29,7 +29,7 @@
 #include "builtin.h"
 #include "check.h"
 
-bool no_fp, no_unreachable;
+bool no_fp, no_unreachable, retpoline, module;
 
 static const char * const check_usage[] = {
         "objtool check [<options>] file.o",
@@ -39,6 +39,8 @@ static const char * const check_usage[] = {
 const struct option check_options[] = {
         OPT_BOOLEAN('f', "no-fp", &no_fp, "Skip frame pointer validation"),
         OPT_BOOLEAN('u', "no-unreachable", &no_unreachable, "Skip 'unreachable instruction' warnings"),
+        OPT_BOOLEAN('r', "retpoline", &retpoline, "Validate retpoline assumptions"),
+        OPT_BOOLEAN('m', "module", &module, "Indicates the object will be part of a kernel module"),
         OPT_END(),
 };
 
@@ -53,5 +55,5 @@ int cmd_check(int argc, const char **argv)
 
         objname = argv[0];
 
-        return check(objname, no_fp, no_unreachable, false);
+        return check(objname, false);
 }
diff --git a/tools/objtool/builtin-orc.c b/tools/objtool/builtin-orc.c
index 91e8e19ff5e0..77ea2b97117d 100644
--- a/tools/objtool/builtin-orc.c
+++ b/tools/objtool/builtin-orc.c
@@ -25,7 +25,6 @@
  */
 
 #include <string.h>
-#include <subcmd/parse-options.h>
 #include "builtin.h"
 #include "check.h"
 
@@ -36,9 +35,6 @@ static const char *orc_usage[] = {
         NULL,
 };
 
-extern const struct option check_options[];
-extern bool no_fp, no_unreachable;
-
 int cmd_orc(int argc, const char **argv)
 {
         const char *objname;
@@ -54,7 +50,7 @@ int cmd_orc(int argc, const char **argv)
 
                 objname = argv[0];
 
-                return check(objname, no_fp, no_unreachable, true);
+                return check(objname, true);
         }
 
         if (!strcmp(argv[0], "dump")) {
diff --git a/tools/objtool/builtin.h b/tools/objtool/builtin.h
index dd526067fed5..28ff40e19a14 100644
--- a/tools/objtool/builtin.h
+++ b/tools/objtool/builtin.h
@@ -17,6 +17,11 @@
 #ifndef _BUILTIN_H
 #define _BUILTIN_H
 
+#include <subcmd/parse-options.h>
+
+extern const struct option check_options[];
+extern bool no_fp, no_unreachable, retpoline, module;
+
 extern int cmd_check(int argc, const char **argv);
 extern int cmd_orc(int argc, const char **argv);
 
diff --git a/tools/objtool/check.c b/tools/objtool/check.c
index b00b1896547e..46c1d239cc1b 100644
--- a/tools/objtool/check.c
+++ b/tools/objtool/check.c
@@ -18,6 +18,7 @@
 #include <string.h>
 #include <stdlib.h>
 
+#include "builtin.h"
 #include "check.h"
 #include "elf.h"
 #include "special.h"
@@ -33,7 +34,6 @@ struct alternative {
 };
 
 const char *objname;
-static bool no_fp;
 struct cfi_state initial_func_cfi;
 
 struct instruction *find_insn(struct objtool_file *file,
@@ -497,6 +497,7 @@ static int add_jump_destinations(struct objtool_file *file)
                          * disguise, so convert them accordingly.
                          */
                         insn->type = INSN_JUMP_DYNAMIC;
+                        insn->retpoline_safe = true;
                         continue;
                 } else {
                         /* sibling call */
@@ -548,7 +549,8 @@ static int add_call_destinations(struct objtool_file *file)
                         if (!insn->call_dest && !insn->ignore) {
                                 WARN_FUNC("unsupported intra-function call",
                                           insn->sec, insn->offset);
-                                WARN("If this is a retpoline, please patch it in with alternatives and annotate it with ANNOTATE_NOSPEC_ALTERNATIVE.");
+                                if (retpoline)
+                                        WARN("If this is a retpoline, please patch it in with alternatives and annotate it with ANNOTATE_NOSPEC_ALTERNATIVE.");
                                 return -1;
                         }
 
@@ -852,8 +854,14 @@ static int add_switch_table(struct objtool_file *file, struct symbol *func,
  *    This is a fairly uncommon pattern which is new for GCC 6.  As of this
  *    writing, there are 11 occurrences of it in the allmodconfig kernel.
  *
+ *    As of GCC 7 there are quite a few more of these and the 'in between' code
+ *    is significant. Esp. with KASAN enabled some of the code between the mov
+ *    and jmpq uses .rodata itself, which can confuse things.
+ *
  *    TODO: Once we have DWARF CFI and smarter instruction decoding logic,
  *    ensure the same register is used in the mov and jump instructions.
+ *
+ *    NOTE: RETPOLINE made it harder still to decode dynamic jumps.
  */
 static struct rela *find_switch_table(struct objtool_file *file,
                                       struct symbol *func,
@@ -875,12 +883,25 @@ static struct rela *find_switch_table(struct objtool_file *file,
                                                 text_rela->addend + 4);
                 if (!rodata_rela)
                         return NULL;
+
                 file->ignore_unreachables = true;
                 return rodata_rela;
         }
 
         /* case 3 */
-        func_for_each_insn_continue_reverse(file, func, insn) {
+        /*
+         * Backward search using the @first_jump_src links, these help avoid
+         * much of the 'in between' code. Which avoids us getting confused by
+         * it.
+         */
+        for (insn = list_prev_entry(insn, list);
+
+             &insn->list != &file->insn_list &&
+             insn->sec == func->sec &&
+             insn->offset >= func->offset;
+
+             insn = insn->first_jump_src ?: list_prev_entry(insn, list)) {
+
                 if (insn->type == INSN_JUMP_DYNAMIC)
                         break;
 
@@ -904,20 +925,42 @@ static struct rela *find_switch_table(struct objtool_file *file,
                 if (find_symbol_containing(file->rodata, text_rela->addend))
                         continue;
 
-                return find_rela_by_dest(file->rodata, text_rela->addend);
+                rodata_rela = find_rela_by_dest(file->rodata, text_rela->addend);
+                if (!rodata_rela)
+                        continue;
+
+                return rodata_rela;
         }
 
         return NULL;
 }
 
+
 static int add_func_switch_tables(struct objtool_file *file,
                                   struct symbol *func)
 {
-        struct instruction *insn, *prev_jump = NULL;
+        struct instruction *insn, *last = NULL, *prev_jump = NULL;
         struct rela *rela, *prev_rela = NULL;
         int ret;
 
         func_for_each_insn(file, func, insn) {
+                if (!last)
+                        last = insn;
+
+                /*
+                 * Store back-pointers for unconditional forward jumps such
+                 * that find_switch_table() can back-track using those and
+                 * avoid some potentially confusing code.
+                 */
+                if (insn->type == INSN_JUMP_UNCONDITIONAL && insn->jump_dest &&
+                    insn->offset > last->offset &&
+                    insn->jump_dest->offset > insn->offset &&
+                    !insn->jump_dest->first_jump_src) {
+
+                        insn->jump_dest->first_jump_src = insn;
+                        last = insn->jump_dest;
+                }
+
                 if (insn->type != INSN_JUMP_DYNAMIC)
                         continue;
 
@@ -1071,6 +1114,54 @@ static int read_unwind_hints(struct objtool_file *file)
         return 0;
 }
 
+static int read_retpoline_hints(struct objtool_file *file)
+{
+        struct section *sec, *relasec;
+        struct instruction *insn;
+        struct rela *rela;
+        int i;
+
+        sec = find_section_by_name(file->elf, ".discard.retpoline_safe");
+        if (!sec)
+                return 0;
+
+        relasec = sec->rela;
+        if (!relasec) {
+                WARN("missing .rela.discard.retpoline_safe section");
+                return -1;
+        }
+
+        if (sec->len % sizeof(unsigned long)) {
+                WARN("retpoline_safe size mismatch: %d %ld", sec->len, sizeof(unsigned long));
+                return -1;
+        }
+
+        for (i = 0; i < sec->len / sizeof(unsigned long); i++) {
+                rela = find_rela_by_dest(sec, i * sizeof(unsigned long));
+                if (!rela) {
+                        WARN("can't find rela for retpoline_safe[%d]", i);
+                        return -1;
+                }
+
+                insn = find_insn(file, rela->sym->sec, rela->addend);
+                if (!insn) {
+                        WARN("can't find insn for retpoline_safe[%d]", i);
+                        return -1;
+                }
+
+                if (insn->type != INSN_JUMP_DYNAMIC &&
+                    insn->type != INSN_CALL_DYNAMIC) {
+                        WARN_FUNC("retpoline_safe hint not a indirect jump/call",
+                                  insn->sec, insn->offset);
+                        return -1;
+                }
+
+                insn->retpoline_safe = true;
+        }
+
+        return 0;
+}
+
 static int decode_sections(struct objtool_file *file)
 {
         int ret;
@@ -1109,6 +1200,10 @@ static int decode_sections(struct objtool_file *file)
         if (ret)
                 return ret;
 
+        ret = read_retpoline_hints(file);
+        if (ret)
+                return ret;
+
         return 0;
 }
 
@@ -1854,6 +1949,38 @@ static int validate_unwind_hints(struct objtool_file *file)
         return warnings;
 }
 
+static int validate_retpoline(struct objtool_file *file)
+{
+        struct instruction *insn;
+        int warnings = 0;
+
+        for_each_insn(file, insn) {
+                if (insn->type != INSN_JUMP_DYNAMIC &&
+                    insn->type != INSN_CALL_DYNAMIC)
+                        continue;
+
+                if (insn->retpoline_safe)
+                        continue;
+
+                /*
+                 * .init.text code is ran before userspace and thus doesn't
+                 * strictly need retpolines, except for modules which are
+                 * loaded late, they very much do need retpoline in their
+                 * .init.text
+                 */
+                if (!strcmp(insn->sec->name, ".init.text") && !module)
+                        continue;
+
+                WARN_FUNC("indirect %s found in RETPOLINE build",
+                          insn->sec, insn->offset,
+                          insn->type == INSN_JUMP_DYNAMIC ? "jump" : "call");
+
+                warnings++;
+        }
+
+        return warnings;
+}
+
 static bool is_kasan_insn(struct instruction *insn)
 {
         return (insn->type == INSN_CALL &&
@@ -1899,13 +2026,19 @@ static bool ignore_unreachable_insn(struct instruction *insn)
                 if (is_kasan_insn(insn) || is_ubsan_insn(insn))
                         return true;
 
-                if (insn->type == INSN_JUMP_UNCONDITIONAL && insn->jump_dest) {
-                        insn = insn->jump_dest;
-                        continue;
+                if (insn->type == INSN_JUMP_UNCONDITIONAL) {
+                        if (insn->jump_dest &&
+                            insn->jump_dest->func == insn->func) {
+                                insn = insn->jump_dest;
+                                continue;
+                        }
+
+                        break;
                 }
 
                 if (insn->offset + insn->len >= insn->func->offset + insn->func->len)
                         break;
+
                 insn = list_next_entry(insn, list);
         }
 
@@ -1979,13 +2112,12 @@ static void cleanup(struct objtool_file *file)
         elf_close(file->elf);
 }
 
-int check(const char *_objname, bool _no_fp, bool no_unreachable, bool orc)
+int check(const char *_objname, bool orc)
 {
         struct objtool_file file;
         int ret, warnings = 0;
 
         objname = _objname;
-        no_fp = _no_fp;
 
         file.elf = elf_open(objname, orc ? O_RDWR : O_RDONLY);
         if (!file.elf)
@@ -2009,6 +2141,13 @@ int check(const char *_objname, bool _no_fp, bool no_unreachable, bool orc)
         if (list_empty(&file.insn_list))
                 goto out;
 
+        if (retpoline) {
+                ret = validate_retpoline(&file);
+                if (ret < 0)
+                        return ret;
+                warnings += ret;
+        }
+
         ret = validate_functions(&file);
         if (ret < 0)
                 goto out;
diff --git a/tools/objtool/check.h b/tools/objtool/check.h
index dbadb304a410..c6b68fcb926f 100644
--- a/tools/objtool/check.h
+++ b/tools/objtool/check.h
@@ -45,8 +45,10 @@ struct instruction {
         unsigned char type;
         unsigned long immediate;
         bool alt_group, visited, dead_end, ignore, hint, save, restore, ignore_alts;
+        bool retpoline_safe;
         struct symbol *call_dest;
         struct instruction *jump_dest;
+        struct instruction *first_jump_src;
         struct list_head alts;
         struct symbol *func;
         struct stack_op stack_op;
@@ -62,7 +64,7 @@ struct objtool_file {
         bool ignore_unreachables, c_file, hints;
 };
 
-int check(const char *objname, bool no_fp, bool no_unreachable, bool orc);
+int check(const char *objname, bool orc);
 
 struct instruction *find_insn(struct objtool_file *file,
                               struct section *sec, unsigned long offset);
diff --git a/tools/perf/Documentation/perf-data.txt b/tools/perf/Documentation/perf-data.txt
index f0796a47dfa3..90bb4aabe4f8 100644
--- a/tools/perf/Documentation/perf-data.txt
+++ b/tools/perf/Documentation/perf-data.txt
@@ -30,6 +30,10 @@ OPTIONS for 'convert'
 -i::
         Specify input perf data file path.
 
+-f::
+--force::
+        Don't complain, do it.
+
 -v::
 --verbose::
         Be more verbose (show counter open errors, etc).
diff --git a/tools/perf/Makefile.perf b/tools/perf/Makefile.perf
index 9b0351d3ce34..012328038594 100644
--- a/tools/perf/Makefile.perf
+++ b/tools/perf/Makefile.perf
@@ -146,12 +146,6 @@ define allow-override
     $(eval $(1) = $(2)))
 endef
 
-# Allow setting CC and AR and LD, or setting CROSS_COMPILE as a prefix.
-$(call allow-override,CC,$(CROSS_COMPILE)gcc)
-$(call allow-override,AR,$(CROSS_COMPILE)ar)
-$(call allow-override,LD,$(CROSS_COMPILE)ld)
-$(call allow-override,CXX,$(CROSS_COMPILE)g++)
-
 LD += $(EXTRA_LDFLAGS)
 
 HOSTCC  ?= gcc
diff --git a/tools/perf/arch/s390/Makefile b/tools/perf/arch/s390/Makefile
index 48228de415d0..dfa6e3103437 100644
--- a/tools/perf/arch/s390/Makefile
+++ b/tools/perf/arch/s390/Makefile
@@ -10,15 +10,19 @@ PERF_HAVE_ARCH_REGS_QUERY_REGISTER_OFFSET := 1
 
 out    := $(OUTPUT)arch/s390/include/generated/asm
 header := $(out)/syscalls_64.c
-sysdef := $(srctree)/tools/arch/s390/include/uapi/asm/unistd.h
-sysprf := $(srctree)/tools/perf/arch/s390/entry/syscalls/
+syskrn := $(srctree)/arch/s390/kernel/syscalls/syscall.tbl
+sysprf := $(srctree)/tools/perf/arch/s390/entry/syscalls
+sysdef := $(sysprf)/syscall.tbl
 systbl := $(sysprf)/mksyscalltbl
 
 # Create output directory if not already present
 _dummy := $(shell [ -d '$(out)' ] || mkdir -p '$(out)')
 
 $(header): $(sysdef) $(systbl)
-        $(Q)$(SHELL) '$(systbl)' '$(CC)' $(sysdef) > $@
+        @(test -d ../../kernel -a -d ../../tools -a -d ../perf && ( \
+        (diff -B $(sysdef) $(syskrn) >/dev/null) \
+        || echo "Warning: Kernel ABI header at '$(sysdef)' differs from latest version at '$(syskrn)'" >&2 )) || true
+        $(Q)$(SHELL) '$(systbl)' $(sysdef) > $@
 
 clean::
         $(call QUIET_CLEAN, s390) $(RM) $(header)
diff --git a/tools/perf/arch/s390/entry/syscalls/mksyscalltbl b/tools/perf/arch/s390/entry/syscalls/mksyscalltbl
index 7fa0d0abd419..72ecbb676370 100755
--- a/tools/perf/arch/s390/entry/syscalls/mksyscalltbl
+++ b/tools/perf/arch/s390/entry/syscalls/mksyscalltbl
@@ -3,25 +3,23 @@
 #
 # Generate system call table for perf
 #
-#
-# Copyright IBM Corp. 2017
+# Copyright IBM Corp. 2017, 2018
 # Author(s):  Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
 #
 
-gcc=$1
-input=$2
+SYSCALL_TBL=$1
 
-if ! test -r $input; then
+if ! test -r $SYSCALL_TBL; then
         echo "Could not read input file" >&2
         exit 1
 fi
 
 create_table()
 {
-        local max_nr
+        local max_nr nr abi sc discard
 
         echo 'static const char *syscalltbl_s390_64[] = {'
-        while read sc nr; do
+        while read nr abi sc discard; do
                 printf '\t[%d] = "%s",\n' $nr $sc
                 max_nr=$nr
         done
@@ -29,8 +27,6 @@ create_table()
         echo "#define SYSCALLTBL_S390_64_MAX_ID $max_nr"
 }
 
-
-$gcc -m64 -E -dM -x c  $input          \
-        |sed -ne 's/^#define __NR_//p' \
-        |sort -t' ' -k2 -nu            \
+grep -E "^[[:digit:]]+[[:space:]]+(common|64)" $SYSCALL_TBL     \
+        |sort -k1 -n                                    \
         |create_table
diff --git a/tools/perf/arch/s390/entry/syscalls/syscall.tbl b/tools/perf/arch/s390/entry/syscalls/syscall.tbl
new file mode 100644
index 000000000000..b38d48464368
--- /dev/null
+++ b/tools/perf/arch/s390/entry/syscalls/syscall.tbl
@@ -0,0 +1,390 @@
+# SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
+#
+# System call table for s390
+#
+# Format:
+#
+# <nr> <abi> <syscall> <entry-64bit> <compat-entry>
+#
+# where <abi> can be common, 64, or 32
+
+1    common     exit                    sys_exit                        sys_exit
+2    common     fork                    sys_fork                        sys_fork
+3    common     read                    sys_read                        compat_sys_s390_read
+4    common     write                   sys_write                       compat_sys_s390_write
+5    common     open                    sys_open                        compat_sys_open
+6    common     close                   sys_close                       sys_close
+7    common     restart_syscall         sys_restart_syscall             sys_restart_syscall
+8    common     creat                   sys_creat                       compat_sys_creat
+9    common     link                    sys_link                        compat_sys_link
+10   common     unlink                  sys_unlink                      compat_sys_unlink
+11   common     execve                  sys_execve                      compat_sys_execve
+12   common     chdir                   sys_chdir                       compat_sys_chdir
+13   32         time                    -                               compat_sys_time
+14   common     mknod                   sys_mknod                       compat_sys_mknod
+15   common     chmod                   sys_chmod                       compat_sys_chmod
+16   32         lchown                  -                               compat_sys_s390_lchown16
+19   common     lseek                   sys_lseek                       compat_sys_lseek
+20   common     getpid                  sys_getpid                      sys_getpid
+21   common     mount                   sys_mount                       compat_sys_mount
+22   common     umount                  sys_oldumount                   compat_sys_oldumount
+23   32         setuid                  -                               compat_sys_s390_setuid16
+24   32         getuid                  -                               compat_sys_s390_getuid16
+25   32         stime                   -                               compat_sys_stime
+26   common     ptrace                  sys_ptrace                      compat_sys_ptrace
+27   common     alarm                   sys_alarm                       sys_alarm
+29   common     pause                   sys_pause                       sys_pause
+30   common     utime                   sys_utime                       compat_sys_utime
+33   common     access                  sys_access                      compat_sys_access
+34   common     nice                    sys_nice                        sys_nice
+36   common     sync                    sys_sync                        sys_sync
+37   common     kill                    sys_kill                        sys_kill
+38   common     rename                  sys_rename                      compat_sys_rename
+39   common     mkdir                   sys_mkdir                       compat_sys_mkdir
+40   common     rmdir                   sys_rmdir                       compat_sys_rmdir
+41   common     dup                     sys_dup                         sys_dup
+42   common     pipe                    sys_pipe                        compat_sys_pipe
+43   common     times                   sys_times                       compat_sys_times
+45   common     brk                     sys_brk                         compat_sys_brk
+46   32         setgid                  -                               compat_sys_s390_setgid16
+47   32         getgid                  -                               compat_sys_s390_getgid16
+48   common     signal                  sys_signal                      compat_sys_signal
+49   32         geteuid                 -                               compat_sys_s390_geteuid16
+50   32         getegid                 -                               compat_sys_s390_getegid16
+51   common     acct                    sys_acct                        compat_sys_acct
+52   common     umount2                 sys_umount                      compat_sys_umount
+54   common     ioctl                   sys_ioctl                       compat_sys_ioctl
+55   common     fcntl                   sys_fcntl                       compat_sys_fcntl
+57   common     setpgid                 sys_setpgid                     sys_setpgid
+60   common     umask                   sys_umask                       sys_umask
+61   common     chroot                  sys_chroot                      compat_sys_chroot
+62   common     ustat                   sys_ustat                       compat_sys_ustat
+63   common     dup2                    sys_dup2                        sys_dup2
+64   common     getppid                 sys_getppid                     sys_getppid
+65   common     getpgrp                 sys_getpgrp                     sys_getpgrp
+66   common     setsid                  sys_setsid                      sys_setsid
+67   common     sigaction               sys_sigaction                   compat_sys_sigaction
+70   32         setreuid                -                               compat_sys_s390_setreuid16
+71   32         setregid                -                               compat_sys_s390_setregid16
+72   common     sigsuspend              sys_sigsuspend                  compat_sys_sigsuspend
+73   common     sigpending              sys_sigpending                  compat_sys_sigpending
+74   common     sethostname             sys_sethostname                 compat_sys_sethostname
+75   common     setrlimit               sys_setrlimit                   compat_sys_setrlimit
+76   32         getrlimit               -                               compat_sys_old_getrlimit
+77   common     getrusage               sys_getrusage                   compat_sys_getrusage
+78   common     gettimeofday            sys_gettimeofday                compat_sys_gettimeofday
+79   common     settimeofday            sys_settimeofday                compat_sys_settimeofday
+80   32         getgroups               -                               compat_sys_s390_getgroups16
+81   32         setgroups               -                               compat_sys_s390_setgroups16
+83   common     symlink                 sys_symlink                     compat_sys_symlink
+85   common     readlink                sys_readlink                    compat_sys_readlink
+86   common     uselib                  sys_uselib                      compat_sys_uselib
+87   common     swapon                  sys_swapon                      compat_sys_swapon
+88   common     reboot                  sys_reboot                      compat_sys_reboot
+89   common     readdir                 -                               compat_sys_old_readdir
+90   common     mmap                    sys_old_mmap                    compat_sys_s390_old_mmap
+91   common     munmap                  sys_munmap                      compat_sys_munmap
+92   common     truncate                sys_truncate                    compat_sys_truncate
+93   common     ftruncate               sys_ftruncate                   compat_sys_ftruncate
+94   common     fchmod                  sys_fchmod                      sys_fchmod
+95   32         fchown                  -                               compat_sys_s390_fchown16
+96   common     getpriority             sys_getpriority                 sys_getpriority
+97   common     setpriority             sys_setpriority                 sys_setpriority
+99   common     statfs                  sys_statfs                      compat_sys_statfs
+100  common     fstatfs                 sys_fstatfs                     compat_sys_fstatfs
+101  32         ioperm                  -                               -
+102  common     socketcall              sys_socketcall                  compat_sys_socketcall
+103  common     syslog                  sys_syslog                      compat_sys_syslog
+104  common     setitimer               sys_setitimer                   compat_sys_setitimer
+105  common     getitimer               sys_getitimer                   compat_sys_getitimer
+106  common     stat                    sys_newstat                     compat_sys_newstat
+107  common     lstat                   sys_newlstat                    compat_sys_newlstat
+108  common     fstat                   sys_newfstat                    compat_sys_newfstat
+110  common     lookup_dcookie          sys_lookup_dcookie              compat_sys_lookup_dcookie
+111  common     vhangup                 sys_vhangup                     sys_vhangup
+112  common     idle                    -                               -
+114  common     wait4                   sys_wait4                       compat_sys_wait4
+115  common     swapoff                 sys_swapoff                     compat_sys_swapoff
+116  common     sysinfo                 sys_sysinfo                     compat_sys_sysinfo
+117  common     ipc                     sys_s390_ipc                    compat_sys_s390_ipc
+118  common     fsync                   sys_fsync                       sys_fsync
+119  common     sigreturn               sys_sigreturn                   compat_sys_sigreturn
+120  common     clone                   sys_clone                       compat_sys_clone
+121  common     setdomainname           sys_setdomainname               compat_sys_setdomainname
+122  common     uname                   sys_newuname                    compat_sys_newuname
+124  common     adjtimex                sys_adjtimex                    compat_sys_adjtimex
+125  common     mprotect                sys_mprotect                    compat_sys_mprotect
+126  common     sigprocmask             sys_sigprocmask                 compat_sys_sigprocmask
+127  common     create_module           -                               -
+128  common     init_module             sys_init_module                 compat_sys_init_module
+129  common     delete_module           sys_delete_module               compat_sys_delete_module
+130  common     get_kernel_syms         -                               -
+131  common     quotactl                sys_quotactl                    compat_sys_quotactl
+132  common     getpgid                 sys_getpgid                     sys_getpgid
+133  common     fchdir                  sys_fchdir                      sys_fchdir
+134  common     bdflush                 sys_bdflush                     compat_sys_bdflush
+135  common     sysfs                   sys_sysfs                       compat_sys_sysfs
+136  common     personality             sys_s390_personality            sys_s390_personality
+137  common     afs_syscall             -                               -
+138  32         setfsuid                -                               compat_sys_s390_setfsuid16
+139  32         setfsgid                -                               compat_sys_s390_setfsgid16
+140  32         _llseek                 -                               compat_sys_llseek
+141  common     getdents                sys_getdents                    compat_sys_getdents
+142  32         _newselect              -                               compat_sys_select
+142  64         select                  sys_select                      -
+143  common     flock                   sys_flock                       sys_flock
+144  common     msync                   sys_msync                       compat_sys_msync
+145  common     readv                   sys_readv                       compat_sys_readv
+146  common     writev                  sys_writev                      compat_sys_writev
+147  common     getsid                  sys_getsid                      sys_getsid
+148  common     fdatasync               sys_fdatasync                   sys_fdatasync
+149  common     _sysctl                 sys_sysctl                      compat_sys_sysctl
+150  common     mlock                   sys_mlock                       compat_sys_mlock
+151  common     munlock                 sys_munlock                     compat_sys_munlock
+152  common     mlockall                sys_mlockall                    sys_mlockall
+153  common     munlockall              sys_munlockall                  sys_munlockall
+154  common     sched_setparam          sys_sched_setparam              compat_sys_sched_setparam
+155  common     sched_getparam          sys_sched_getparam              compat_sys_sched_getparam
+156  common     sched_setscheduler      sys_sched_setscheduler          compat_sys_sched_setscheduler
+157  common     sched_getscheduler      sys_sched_getscheduler          sys_sched_getscheduler
+158  common     sched_yield             sys_sched_yield                 sys_sched_yield
+159  common     sched_get_priority_max  sys_sched_get_priority_max      sys_sched_get_priority_max
+160  common     sched_get_priority_min  sys_sched_get_priority_min      sys_sched_get_priority_min
+161  common     sched_rr_get_interval   sys_sched_rr_get_interval       compat_sys_sched_rr_get_interval
+162  common     nanosleep               sys_nanosleep                   compat_sys_nanosleep
+163  common     mremap                  sys_mremap                      compat_sys_mremap
+164  32         setresuid               -                               compat_sys_s390_setresuid16
+165  32         getresuid               -                               compat_sys_s390_getresuid16
+167  common     query_module            -                               -
+168  common     poll                    sys_poll                        compat_sys_poll
+169  common     nfsservctl              -                               -
+170  32         setresgid               -                               compat_sys_s390_setresgid16
+171  32         getresgid               -                               compat_sys_s390_getresgid16
+172  common     prctl                   sys_prctl                       compat_sys_prctl
+173  common     rt_sigreturn            sys_rt_sigreturn                compat_sys_rt_sigreturn
+174  common     rt_sigaction            sys_rt_sigaction                compat_sys_rt_sigaction
+175  common     rt_sigprocmask          sys_rt_sigprocmask              compat_sys_rt_sigprocmask
+176  common     rt_sigpending           sys_rt_sigpending               compat_sys_rt_sigpending
+177  common     rt_sigtimedwait         sys_rt_sigtimedwait             compat_sys_rt_sigtimedwait
+178  common     rt_sigqueueinfo         sys_rt_sigqueueinfo             compat_sys_rt_sigqueueinfo
+179  common     rt_sigsuspend           sys_rt_sigsuspend               compat_sys_rt_sigsuspend
+180  common     pread64                 sys_pread64                     compat_sys_s390_pread64
+181  common     pwrite64                sys_pwrite64                    compat_sys_s390_pwrite64
+182  32         chown                   -                               compat_sys_s390_chown16
+183  common     getcwd                  sys_getcwd                      compat_sys_getcwd
+184  common     capget                  sys_capget                      compat_sys_capget
+185  common     capset                  sys_capset                      compat_sys_capset
+186  common     sigaltstack             sys_sigaltstack                 compat_sys_sigaltstack
+187  common     sendfile                sys_sendfile64                  compat_sys_sendfile
+188  common     getpmsg                 -                               -
+189  common     putpmsg                 -                               -
+190  common     vfork                   sys_vfork                       sys_vfork
+191  32         ugetrlimit              -                               compat_sys_getrlimit
+191  64         getrlimit               sys_getrlimit                   -
+192  32         mmap2                   -                               compat_sys_s390_mmap2
+193  32         truncate64              -                               compat_sys_s390_truncate64
+194  32         ftruncate64             -                               compat_sys_s390_ftruncate64
+195  32         stat64                  -                               compat_sys_s390_stat64
+196  32         lstat64                 -                               compat_sys_s390_lstat64
+197  32         fstat64                 -                               compat_sys_s390_fstat64
+198  32         lchown32                -                               compat_sys_lchown
+198  64         lchown                  sys_lchown                      -
+199  32         getuid32                -                               sys_getuid
+199  64         getuid                  sys_getuid                      -
+200  32         getgid32                -                               sys_getgid
+200  64         getgid                  sys_getgid                      -
+201  32         geteuid32               -                               sys_geteuid
+201  64         geteuid                 sys_geteuid                     -
+202  32         getegid32               -                               sys_getegid
+202  64         getegid                 sys_getegid                     -
+203  32         setreuid32              -                               sys_setreuid
+203  64         setreuid                sys_setreuid                    -
+204  32         setregid32              -                               sys_setregid
+204  64         setregid                sys_setregid                    -
+205  32         getgroups32             -                               compat_sys_getgroups
+205  64         getgroups               sys_getgroups                   -
+206  32         setgroups32             -                               compat_sys_setgroups
+206  64         setgroups               sys_setgroups                   -
+207  32         fchown32                -                               sys_fchown
+207  64         fchown                  sys_fchown                      -
+208  32         setresuid32             -                               sys_setresuid
+208  64         setresuid               sys_setresuid                   -
+209  32         getresuid32             -                               compat_sys_getresuid
+209  64         getresuid               sys_getresuid                   -
+210  32         setresgid32             -                               sys_setresgid
+210  64         setresgid               sys_setresgid                   -
+211  32         getresgid32             -                               compat_sys_getresgid
+211  64         getresgid               sys_getresgid                   -
+212  32         chown32                 -                               compat_sys_chown
+212  64         chown                   sys_chown                       -
+213  32         setuid32                -                               sys_setuid
+213  64         setuid                  sys_setuid                      -
+214  32         setgid32                -                               sys_setgid
+214  64         setgid                  sys_setgid                      -
+215  32         setfsuid32              -                               sys_setfsuid
+215  64         setfsuid                sys_setfsuid                    -
+216  32         setfsgid32              -                               sys_setfsgid
+216  64         setfsgid                sys_setfsgid                    -
+217  common     pivot_root              sys_pivot_root                  compat_sys_pivot_root
+218  common     mincore                 sys_mincore                     compat_sys_mincore
+219  common     madvise                 sys_madvise                     compat_sys_madvise
+220  common     getdents64              sys_getdents64                  compat_sys_getdents64
+221  32         fcntl64                 -                               compat_sys_fcntl64
+222  common     readahead               sys_readahead                   compat_sys_s390_readahead
+223  32         sendfile64              -                               compat_sys_sendfile64
+224  common     setxattr                sys_setxattr                    compat_sys_setxattr
+225  common     lsetxattr               sys_lsetxattr                   compat_sys_lsetxattr
+226  common     fsetxattr               sys_fsetxattr                   compat_sys_fsetxattr
+227  common     getxattr                sys_getxattr                    compat_sys_getxattr
+228  common     lgetxattr               sys_lgetxattr                   compat_sys_lgetxattr
+229  common     fgetxattr               sys_fgetxattr                   compat_sys_fgetxattr
+230  common     listxattr               sys_listxattr                   compat_sys_listxattr
+231  common     llistxattr              sys_llistxattr                  compat_sys_llistxattr
+232  common     flistxattr              sys_flistxattr                  compat_sys_flistxattr
+233  common     removexattr             sys_removexattr                 compat_sys_removexattr
+234  common     lremovexattr            sys_lremovexattr                compat_sys_lremovexattr
+235  common     fremovexattr            sys_fremovexattr                compat_sys_fremovexattr
+236  common     gettid                  sys_gettid                      sys_gettid
+237  common     tkill                   sys_tkill                       sys_tkill
+238  common     futex                   sys_futex                       compat_sys_futex
+239  common     sched_setaffinity       sys_sched_setaffinity           compat_sys_sched_setaffinity
+240  common     sched_getaffinity       sys_sched_getaffinity           compat_sys_sched_getaffinity
+241  common     tgkill                  sys_tgkill                      sys_tgkill
+243  common     io_setup                sys_io_setup                    compat_sys_io_setup
+244  common     io_destroy              sys_io_destroy                  compat_sys_io_destroy
+245  common     io_getevents            sys_io_getevents                compat_sys_io_getevents
+246  common     io_submit               sys_io_submit                   compat_sys_io_submit
+247  common     io_cancel               sys_io_cancel                   compat_sys_io_cancel
+248  common     exit_group              sys_exit_group                  sys_exit_group
+249  common     epoll_create            sys_epoll_create                sys_epoll_create
+250  common     epoll_ctl               sys_epoll_ctl                   compat_sys_epoll_ctl
+251  common     epoll_wait              sys_epoll_wait                  compat_sys_epoll_wait
+252  common     set_tid_address         sys_set_tid_address             compat_sys_set_tid_address
+253  common     fadvise64               sys_fadvise64_64                compat_sys_s390_fadvise64
+254  common     timer_create            sys_timer_create                compat_sys_timer_create
+255  common     timer_settime           sys_timer_settime               compat_sys_timer_settime
+256  common     timer_gettime           sys_timer_gettime               compat_sys_timer_gettime
+257  common     timer_getoverrun        sys_timer_getoverrun            sys_timer_getoverrun
+258  common     timer_delete            sys_timer_delete                sys_timer_delete
+259  common     clock_settime           sys_clock_settime               compat_sys_clock_settime
+260  common     clock_gettime           sys_clock_gettime               compat_sys_clock_gettime
+261  common     clock_getres            sys_clock_getres                compat_sys_clock_getres
+262  common     clock_nanosleep         sys_clock_nanosleep             compat_sys_clock_nanosleep
+264  32         fadvise64_64            -                               compat_sys_s390_fadvise64_64
+265  common     statfs64                sys_statfs64                    compat_sys_statfs64
+266  common     fstatfs64               sys_fstatfs64                   compat_sys_fstatfs64
+267  common     remap_file_pages        sys_remap_file_pages            compat_sys_remap_file_pages
+268  common     mbind                   sys_mbind                       compat_sys_mbind
+269  common     get_mempolicy           sys_get_mempolicy               compat_sys_get_mempolicy
+270  common     set_mempolicy           sys_set_mempolicy               compat_sys_set_mempolicy
+271  common     mq_open                 sys_mq_open                     compat_sys_mq_open
+272  common     mq_unlink               sys_mq_unlink                   compat_sys_mq_unlink
+273  common     mq_timedsend            sys_mq_timedsend                compat_sys_mq_timedsend
+274  common     mq_timedreceive         sys_mq_timedreceive             compat_sys_mq_timedreceive
+275  common     mq_notify               sys_mq_notify                   compat_sys_mq_notify
+276  common     mq_getsetattr           sys_mq_getsetattr               compat_sys_mq_getsetattr
+277  common     kexec_load              sys_kexec_load                  compat_sys_kexec_load
+278  common     add_key                 sys_add_key                     compat_sys_add_key
+279  common     request_key             sys_request_key                 compat_sys_request_key
+280  common     keyctl                  sys_keyctl                      compat_sys_keyctl
+281  common     waitid                  sys_waitid                      compat_sys_waitid
+282  common     ioprio_set              sys_ioprio_set                  sys_ioprio_set
+283  common     ioprio_get              sys_ioprio_get                  sys_ioprio_get
+284  common     inotify_init            sys_inotify_init                sys_inotify_init
+285  common     inotify_add_watch       sys_inotify_add_watch           compat_sys_inotify_add_watch
+286  common     inotify_rm_watch        sys_inotify_rm_watch            sys_inotify_rm_watch
+287  common     migrate_pages           sys_migrate_pages               compat_sys_migrate_pages
+288  common     openat                  sys_openat                      compat_sys_openat
+289  common     mkdirat                 sys_mkdirat                     compat_sys_mkdirat
+290  common     mknodat                 sys_mknodat                     compat_sys_mknodat
+291  common     fchownat                sys_fchownat                    compat_sys_fchownat
+292  common     futimesat               sys_futimesat                   compat_sys_futimesat
+293  32         fstatat64               -                               compat_sys_s390_fstatat64
+293  64         newfstatat              sys_newfstatat                  -
+294  common     unlinkat                sys_unlinkat                    compat_sys_unlinkat
+295  common     renameat                sys_renameat                    compat_sys_renameat
+296  common     linkat                  sys_linkat                      compat_sys_linkat
+297  common     symlinkat               sys_symlinkat                   compat_sys_symlinkat
+298  common     readlinkat              sys_readlinkat                  compat_sys_readlinkat
+299  common     fchmodat                sys_fchmodat                    compat_sys_fchmodat
+300  common     faccessat               sys_faccessat                   compat_sys_faccessat
+301  common     pselect6                sys_pselect6                    compat_sys_pselect6
+302  common     ppoll                   sys_ppoll                       compat_sys_ppoll
+303  common     unshare                 sys_unshare                     compat_sys_unshare
+304  common     set_robust_list         sys_set_robust_list             compat_sys_set_robust_list
+305  common     get_robust_list         sys_get_robust_list             compat_sys_get_robust_list
+306  common     splice                  sys_splice                      compat_sys_splice
+307  common     sync_file_range         sys_sync_file_range             compat_sys_s390_sync_file_range
+308  common     tee                     sys_tee                         compat_sys_tee
+309  common     vmsplice                sys_vmsplice                    compat_sys_vmsplice
+310  common     move_pages              sys_move_pages                  compat_sys_move_pages
+311  common     getcpu                  sys_getcpu                      compat_sys_getcpu
+312  common     epoll_pwait             sys_epoll_pwait                 compat_sys_epoll_pwait
+313  common     utimes                  sys_utimes                      compat_sys_utimes
+314  common     fallocate               sys_fallocate                   compat_sys_s390_fallocate
+315  common     utimensat               sys_utimensat                   compat_sys_utimensat
+316  common     signalfd                sys_signalfd                    compat_sys_signalfd
+317  common     timerfd                 -                               -
+318  common     eventfd                 sys_eventfd                     sys_eventfd
+319  common     timerfd_create          sys_timerfd_create              sys_timerfd_create
+320  common     timerfd_settime         sys_timerfd_settime             compat_sys_timerfd_settime
+321  common     timerfd_gettime         sys_timerfd_gettime             compat_sys_timerfd_gettime
+322  common     signalfd4               sys_signalfd4                   compat_sys_signalfd4
+323  common     eventfd2                sys_eventfd2                    sys_eventfd2
+324  common     inotify_init1           sys_inotify_init1               sys_inotify_init1
+325  common     pipe2                   sys_pipe2                       compat_sys_pipe2
+326  common     dup3                    sys_dup3                        sys_dup3
+327  common     epoll_create1           sys_epoll_create1               sys_epoll_create1
+328  common     preadv                  sys_preadv                      compat_sys_preadv
+329  common     pwritev                 sys_pwritev                     compat_sys_pwritev
+330  common     rt_tgsigqueueinfo       sys_rt_tgsigqueueinfo           compat_sys_rt_tgsigqueueinfo
+331  common     perf_event_open         sys_perf_event_open             compat_sys_perf_event_open
+332  common     fanotify_init           sys_fanotify_init               sys_fanotify_init
+333  common     fanotify_mark           sys_fanotify_mark               compat_sys_fanotify_mark
+334  common     prlimit64               sys_prlimit64                   compat_sys_prlimit64
+335  common     name_to_handle_at       sys_name_to_handle_at           compat_sys_name_to_handle_at
+336  common     open_by_handle_at       sys_open_by_handle_at           compat_sys_open_by_handle_at
+337  common     clock_adjtime           sys_clock_adjtime               compat_sys_clock_adjtime
+338  common     syncfs                  sys_syncfs                      sys_syncfs
+339  common     setns                   sys_setns                       sys_setns
+340  common     process_vm_readv        sys_process_vm_readv            compat_sys_process_vm_readv
+341  common     process_vm_writev       sys_process_vm_writev           compat_sys_process_vm_writev
+342  common     s390_runtime_instr      sys_s390_runtime_instr          sys_s390_runtime_instr
+343  common     kcmp                    sys_kcmp                        compat_sys_kcmp
+344  common     finit_module            sys_finit_module                compat_sys_finit_module
+345  common     sched_setattr           sys_sched_setattr               compat_sys_sched_setattr
+346  common     sched_getattr           sys_sched_getattr               compat_sys_sched_getattr
+347  common     renameat2               sys_renameat2                   compat_sys_renameat2
+348  common     seccomp                 sys_seccomp                     compat_sys_seccomp
+349  common     getrandom               sys_getrandom                   compat_sys_getrandom
+350  common     memfd_create            sys_memfd_create                compat_sys_memfd_create
+351  common     bpf                     sys_bpf                         compat_sys_bpf
+352  common     s390_pci_mmio_write     sys_s390_pci_mmio_write         compat_sys_s390_pci_mmio_write
+353  common     s390_pci_mmio_read      sys_s390_pci_mmio_read          compat_sys_s390_pci_mmio_read
+354  common     execveat                sys_execveat                    compat_sys_execveat
+355  common     userfaultfd             sys_userfaultfd                 sys_userfaultfd
+356  common     membarrier              sys_membarrier                  sys_membarrier
+357  common     recvmmsg                sys_recvmmsg                    compat_sys_recvmmsg
+358  common     sendmmsg                sys_sendmmsg                    compat_sys_sendmmsg
+359  common     socket                  sys_socket                      sys_socket
+360  common     socketpair              sys_socketpair                  compat_sys_socketpair
+361  common     bind                    sys_bind                        compat_sys_bind
+362  common     connect                 sys_connect                     compat_sys_connect
+363  common     listen                  sys_listen                      sys_listen
+364  common     accept4                 sys_accept4                     compat_sys_accept4
+365  common     getsockopt              sys_getsockopt                  compat_sys_getsockopt
+366  common     setsockopt              sys_setsockopt                  compat_sys_setsockopt
+367  common     getsockname             sys_getsockname                 compat_sys_getsockname
+368  common     getpeername             sys_getpeername                 compat_sys_getpeername
+369  common     sendto                  sys_sendto                      compat_sys_sendto
+370  common     sendmsg                 sys_sendmsg                     compat_sys_sendmsg
+371  common     recvfrom                sys_recvfrom                    compat_sys_recvfrom
+372  common     recvmsg                 sys_recvmsg                     compat_sys_recvmsg
+373  common     shutdown                sys_shutdown                    sys_shutdown
+374  common     mlock2                  sys_mlock2                      compat_sys_mlock2
+375  common     copy_file_range         sys_copy_file_range             compat_sys_copy_file_range
+376  common     preadv2                 sys_preadv2                     compat_sys_preadv2
+377  common     pwritev2                sys_pwritev2                    compat_sys_pwritev2
+378  common     s390_guarded_storage    sys_s390_guarded_storage        compat_sys_s390_guarded_storage
+379  common     statx                   sys_statx                       compat_sys_statx
+380  common     s390_sthyi              sys_s390_sthyi                  compat_sys_s390_sthyi
diff --git a/tools/perf/builtin-c2c.c b/tools/perf/builtin-c2c.c
index c0815a37fdb5..539c3d460158 100644
--- a/tools/perf/builtin-c2c.c
+++ b/tools/perf/builtin-c2c.c
@@ -2245,7 +2245,7 @@ static int perf_c2c__browse_cacheline(struct hist_entry *he)
         c2c_browser__update_nr_entries(browser);
 
         while (1) {
-                key = hist_browser__run(browser, "? - help");
+                key = hist_browser__run(browser, "? - help", true);
 
                 switch (key) {
                 case 's':
@@ -2314,7 +2314,7 @@ static int perf_c2c__hists_browse(struct hists *hists)
         c2c_browser__update_nr_entries(browser);
 
         while (1) {
-                key = hist_browser__run(browser, "? - help");
+                key = hist_browser__run(browser, "? - help", true);
 
                 switch (key) {
                 case 'q':
diff --git a/tools/perf/builtin-report.c b/tools/perf/builtin-report.c
index 42a52dcc41cd..4ad5dc649716 100644
--- a/tools/perf/builtin-report.c
+++ b/tools/perf/builtin-report.c
@@ -530,7 +530,8 @@ static int report__browse_hists(struct report *rep)
         case 1:
                 ret = perf_evlist__tui_browse_hists(evlist, help, NULL,
                                                     rep->min_percent,
-                                                    &session->header.env);
+                                                    &session->header.env,
+                                                    true);
                 /*
                  * Usually "ret" is the last pressed key, and we only
                  * care if the key notifies us to switch data file.
diff --git a/tools/perf/builtin-top.c b/tools/perf/builtin-top.c
index c6ccda52117d..b7c823ba8374 100644
--- a/tools/perf/builtin-top.c
+++ b/tools/perf/builtin-top.c
@@ -283,8 +283,9 @@ static void perf_top__print_sym_table(struct perf_top *top)
 
         printf("%-*.*s\n", win_width, win_width, graph_dotted_line);
 
-        if (hists->stats.nr_lost_warned !=
-            hists->stats.nr_events[PERF_RECORD_LOST]) {
+        if (!top->record_opts.overwrite &&
+            (hists->stats.nr_lost_warned !=
+            hists->stats.nr_events[PERF_RECORD_LOST])) {
                 hists->stats.nr_lost_warned =
                               hists->stats.nr_events[PERF_RECORD_LOST];
                 color_fprintf(stdout, PERF_COLOR_RED,
@@ -611,7 +612,8 @@ static void *display_thread_tui(void *arg)
 
         perf_evlist__tui_browse_hists(top->evlist, help, &hbt,
                                       top->min_percent,
-                                      &top->session->header.env);
+                                      &top->session->header.env,
+                                      !top->record_opts.overwrite);
 
         done = 1;
         return NULL;
@@ -807,15 +809,23 @@ static void perf_event__process_sample(struct perf_tool *tool,
 
 static void perf_top__mmap_read_idx(struct perf_top *top, int idx)
 {
+        struct record_opts *opts = &top->record_opts;
+        struct perf_evlist *evlist = top->evlist;
         struct perf_sample sample;
         struct perf_evsel *evsel;
+        struct perf_mmap *md;
         struct perf_session *session = top->session;
         union perf_event *event;
         struct machine *machine;
+        u64 end, start;
         int ret;
 
-        while ((event = perf_evlist__mmap_read(top->evlist, idx)) != NULL) {
-                ret = perf_evlist__parse_sample(top->evlist, event, &sample);
+        md = opts->overwrite ? &evlist->overwrite_mmap[idx] : &evlist->mmap[idx];
+        if (perf_mmap__read_init(md, opts->overwrite, &start, &end) < 0)
+                return;
+
+        while ((event = perf_mmap__read_event(md, opts->overwrite, &start, end)) != NULL) {
+                ret = perf_evlist__parse_sample(evlist, event, &sample);
                 if (ret) {
                         pr_err("Can't parse sample, err = %d\n", ret);
                         goto next_event;
@@ -869,16 +879,120 @@ static void perf_top__mmap_read_idx(struct perf_top *top, int idx)
                 } else
                         ++session->evlist->stats.nr_unknown_events;
 next_event:
-                perf_evlist__mmap_consume(top->evlist, idx);
+                perf_mmap__consume(md, opts->overwrite);
         }
+
+        perf_mmap__read_done(md);
 }
 
 static void perf_top__mmap_read(struct perf_top *top)
 {
+        bool overwrite = top->record_opts.overwrite;
+        struct perf_evlist *evlist = top->evlist;
+        unsigned long long start, end;
         int i;
 
+        start = rdclock();
+        if (overwrite)
+                perf_evlist__toggle_bkw_mmap(evlist, BKW_MMAP_DATA_PENDING);
+
         for (i = 0; i < top->evlist->nr_mmaps; i++)
                 perf_top__mmap_read_idx(top, i);
+
+        if (overwrite) {
+                perf_evlist__toggle_bkw_mmap(evlist, BKW_MMAP_EMPTY);
+                perf_evlist__toggle_bkw_mmap(evlist, BKW_MMAP_RUNNING);
+        }
+        end = rdclock();
+
+        if ((end - start) > (unsigned long long)top->delay_secs * NSEC_PER_SEC)
+                ui__warning("Too slow to read ring buffer.\n"
+                            "Please try increasing the period (-c) or\n"
+                            "decreasing the freq (-F) or\n"
+                            "limiting the number of CPUs (-C)\n");
+}
+
+/*
+ * Check per-event overwrite term.
+ * perf top should support consistent term for all events.
+ * - All events don't have per-event term
+ *   E.g. "cpu/cpu-cycles/,cpu/instructions/"
+ *   Nothing change, return 0.
+ * - All events have same per-event term
+ *   E.g. "cpu/cpu-cycles,no-overwrite/,cpu/instructions,no-overwrite/
+ *   Using the per-event setting to replace the opts->overwrite if
+ *   they are different, then return 0.
+ * - Events have different per-event term
+ *   E.g. "cpu/cpu-cycles,overwrite/,cpu/instructions,no-overwrite/"
+ *   Return -1
+ * - Some of the event set per-event term, but some not.
+ *   E.g. "cpu/cpu-cycles/,cpu/instructions,no-overwrite/"
+ *   Return -1
+ */
+static int perf_top__overwrite_check(struct perf_top *top)
+{
+        struct record_opts *opts = &top->record_opts;
+        struct perf_evlist *evlist = top->evlist;
+        struct perf_evsel_config_term *term;
+        struct list_head *config_terms;
+        struct perf_evsel *evsel;
+        int set, overwrite = -1;
+
+        evlist__for_each_entry(evlist, evsel) {
+                set = -1;
+                config_terms = &evsel->config_terms;
+                list_for_each_entry(term, config_terms, list) {
+                        if (term->type == PERF_EVSEL__CONFIG_TERM_OVERWRITE)
+                                set = term->val.overwrite ? 1 : 0;
+                }
+
+                /* no term for current and previous event (likely) */
+                if ((overwrite < 0) && (set < 0))
+                        continue;
+
+                /* has term for both current and previous event, compare */
+                if ((overwrite >= 0) && (set >= 0) && (overwrite != set))
+                        return -1;
+
+                /* no term for current event but has term for previous one */
+                if ((overwrite >= 0) && (set < 0))
+                        return -1;
+
+                /* has term for current event */
+                if ((overwrite < 0) && (set >= 0)) {
+                        /* if it's first event, set overwrite */
+                        if (evsel == perf_evlist__first(evlist))
+                                overwrite = set;
+                        else
+                                return -1;
+                }
+        }
+
+        if ((overwrite >= 0) && (opts->overwrite != overwrite))
+                opts->overwrite = overwrite;
+
+        return 0;
+}
+
+static int perf_top_overwrite_fallback(struct perf_top *top,
+                                       struct perf_evsel *evsel)
+{
+        struct record_opts *opts = &top->record_opts;
+        struct perf_evlist *evlist = top->evlist;
+        struct perf_evsel *counter;
+
+        if (!opts->overwrite)
+                return 0;
+
+        /* only fall back when first event fails */
+        if (evsel != perf_evlist__first(evlist))
+                return 0;
+
+        evlist__for_each_entry(evlist, counter)
+                counter->attr.write_backward = false;
+        opts->overwrite = false;
+        ui__warning("fall back to non-overwrite mode\n");
+        return 1;
 }
 
 static int perf_top__start_counters(struct perf_top *top)
@@ -888,12 +1002,33 @@ static int perf_top__start_counters(struct perf_top *top)
         struct perf_evlist *evlist = top->evlist;
         struct record_opts *opts = &top->record_opts;
 
+        if (perf_top__overwrite_check(top)) {
+                ui__error("perf top only support consistent per-event "
+                          "overwrite setting for all events\n");
+                goto out_err;
+        }
+
         perf_evlist__config(evlist, opts, &callchain_param);
 
         evlist__for_each_entry(evlist, counter) {
 try_again:
                 if (perf_evsel__open(counter, top->evlist->cpus,
                                      top->evlist->threads) < 0) {
+
+                        /*
+                         * Specially handle overwrite fall back.
+                         * Because perf top is the only tool which has
+                         * overwrite mode by default, support
+                         * both overwrite and non-overwrite mode, and
+                         * require consistent mode for all events.
+                         *
+                         * May move it to generic code with more tools
+                         * have similar attribute.
+                         */
+                        if (perf_missing_features.write_backward &&
+                            perf_top_overwrite_fallback(top, counter))
+                                goto try_again;
+
                         if (perf_evsel__fallback(counter, errno, msg, sizeof(msg))) {
                                 if (verbose > 0)
                                         ui__warning("%s\n", msg);
@@ -1033,7 +1168,7 @@ static int __cmd_top(struct perf_top *top)
 
                 perf_top__mmap_read(top);
 
-                if (hits == top->samples)
+                if (opts->overwrite || (hits == top->samples))
                         ret = perf_evlist__poll(top->evlist, 100);
 
                 if (resize) {
@@ -1127,6 +1262,7 @@ int cmd_top(int argc, const char **argv)
                                 .uses_mmap   = true,
                         },
                         .proc_map_timeout    = 500,
+                        .overwrite      = 1,
                 },
                 .max_stack           = sysctl_perf_event_max_stack,
                 .sym_pcnt_filter     = 5,
diff --git a/tools/perf/check-headers.sh b/tools/perf/check-headers.sh
index 51abdb0a4047..790ec25919a0 100755
--- a/tools/perf/check-headers.sh
+++ b/tools/perf/check-headers.sh
@@ -33,7 +33,6 @@ arch/s390/include/uapi/asm/kvm.h
 arch/s390/include/uapi/asm/kvm_perf.h
 arch/s390/include/uapi/asm/ptrace.h
 arch/s390/include/uapi/asm/sie.h
-arch/s390/include/uapi/asm/unistd.h
 arch/arm/include/uapi/asm/kvm.h
 arch/arm64/include/uapi/asm/kvm.h
 arch/alpha/include/uapi/asm/errno.h
diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/branch.json b/tools/perf/pmu-events/arch/arm64/cortex-a53/branch.json
new file mode 100644
index 000000000000..3b6208763e50
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/cortex-a53/branch.json
@@ -0,0 +1,27 @@
+[
+  {,
+    "EventCode": "0x7A",
+    "EventName": "BR_INDIRECT_SPEC",
+    "BriefDescription": "Branch speculatively executed - Indirect branch"
+  },
+  {,
+    "EventCode": "0xC9",
+    "EventName": "BR_COND",
+    "BriefDescription": "Conditional branch executed"
+  },
+  {,
+    "EventCode": "0xCA",
+    "EventName": "BR_INDIRECT_MISPRED",
+    "BriefDescription": "Indirect branch mispredicted"
+  },
+  {,
+    "EventCode": "0xCB",
+    "EventName": "BR_INDIRECT_MISPRED_ADDR",
+    "BriefDescription": "Indirect branch mispredicted because of address miscompare"
+  },
+  {,
+    "EventCode": "0xCC",
+    "EventName": "BR_COND_MISPRED",
+    "BriefDescription": "Conditional branch mispredicted"
+  }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json b/tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json
new file mode 100644
index 000000000000..480d9f7460ab
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json
@@ -0,0 +1,22 @@
+[
+  {,
+    "EventCode": "0x60",
+    "EventName": "BUS_ACCESS_LD",
+    "BriefDescription": "Bus access - Read"
+  },
+  {,
+    "EventCode": "0x61",
+    "EventName": "BUS_ACCESS_ST",
+    "BriefDescription": "Bus access - Write"
+  },
+  {,
+    "EventCode": "0xC0",
+    "EventName": "EXT_MEM_REQ",
+    "BriefDescription": "External memory request"
+  },
+  {,
+    "EventCode": "0xC1",
+    "EventName": "EXT_MEM_REQ_NC",
+    "BriefDescription": "Non-cacheable external memory request"
+  }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json b/tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json
new file mode 100644
index 000000000000..11baad6344b9
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json
@@ -0,0 +1,27 @@
+[
+  {,
+    "EventCode": "0xC2",
+    "EventName": "PREFETCH_LINEFILL",
+    "BriefDescription": "Linefill because of prefetch"
+  },
+  {,
+    "EventCode": "0xC3",
+    "EventName": "PREFETCH_LINEFILL_DROP",
+    "BriefDescription": "Instruction Cache Throttle occurred"
+  },
+  {,
+    "EventCode": "0xC4",
+    "EventName": "READ_ALLOC_ENTER",
+    "BriefDescription": "Entering read allocate mode"
+  },
+  {,
+    "EventCode": "0xC5",
+    "EventName": "READ_ALLOC",
+    "BriefDescription": "Read allocate mode"
+  },
+  {,
+    "EventCode": "0xC8",
+    "EventName": "EXT_SNOOP",
+    "BriefDescription": "SCU Snooped data from another CPU for this CPU"
+  }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/memory.json b/tools/perf/pmu-events/arch/arm64/cortex-a53/memory.json
new file mode 100644
index 000000000000..480d9f7460ab
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/cortex-a53/memory.json
@@ -0,0 +1,22 @@
+[
+  {,
+    "EventCode": "0x60",
+    "EventName": "BUS_ACCESS_LD",
+    "BriefDescription": "Bus access - Read"
+  },
+  {,
+    "EventCode": "0x61",
+    "EventName": "BUS_ACCESS_ST",
+    "BriefDescription": "Bus access - Write"
+  },
+  {,
+    "EventCode": "0xC0",
+    "EventName": "EXT_MEM_REQ",
+    "BriefDescription": "External memory request"
+  },
+  {,
+    "EventCode": "0xC1",
+    "EventName": "EXT_MEM_REQ_NC",
+    "BriefDescription": "Non-cacheable external memory request"
+  }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/other.json b/tools/perf/pmu-events/arch/arm64/cortex-a53/other.json
new file mode 100644
index 000000000000..73a22402d003
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/cortex-a53/other.json
@@ -0,0 +1,32 @@
+[
+  {,
+    "EventCode": "0x86",
+    "EventName": "EXC_IRQ",
+    "BriefDescription": "Exception taken, IRQ"
+  },
+  {,
+    "EventCode": "0x87",
+    "EventName": "EXC_FIQ",
+    "BriefDescription": "Exception taken, FIQ"
+  },
+  {,
+    "EventCode": "0xC6",
+    "EventName": "PRE_DECODE_ERR",
+    "BriefDescription": "Pre-decode error"
+  },
+  {,
+    "EventCode": "0xD0",
+    "EventName": "L1I_CACHE_ERR",
+    "BriefDescription": "L1 Instruction Cache (data or tag) memory error"
+  },
+  {,
+    "EventCode": "0xD1",
+    "EventName": "L1D_CACHE_ERR",
+    "BriefDescription": "L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable"
+  },
+  {,
+    "EventCode": "0xD2",
+    "EventName": "TLB_ERR",
+    "BriefDescription": "TLB memory error"
+  }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/cortex-a53/pipeline.json b/tools/perf/pmu-events/arch/arm64/cortex-a53/pipeline.json
new file mode 100644
index 000000000000..3149fb90555a
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/cortex-a53/pipeline.json
@@ -0,0 +1,52 @@
+[
+  {,
+    "EventCode": "0xC7",
+    "EventName": "STALL_SB_FULL",
+    "BriefDescription": "Data Write operation that stalls the pipeline because the store buffer is full"
+  },
+  {,
+    "EventCode": "0xE0",
+    "EventName": "OTHER_IQ_DEP_STALL",
+    "BriefDescription": "Cycles that the DPU IQ is empty and that is not because of a recent micro-TLB miss, instruction cache miss or pre-decode error"
+  },
+  {,
+    "EventCode": "0xE1",
+    "EventName": "IC_DEP_STALL",
+    "BriefDescription": "Cycles the DPU IQ is empty and there is an instruction cache miss being processed"
+  },
+  {,
+    "EventCode": "0xE2",
+    "EventName": "IUTLB_DEP_STALL",
+    "BriefDescription": "Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being processed"
+  },
+  {,
+    "EventCode": "0xE3",
+    "EventName": "DECODE_DEP_STALL",
+    "BriefDescription": "Cycles the DPU IQ is empty and there is a pre-decode error being processed"
+  },
+  {,
+    "EventCode": "0xE4",
+    "EventName": "OTHER_INTERLOCK_STALL",
+    "BriefDescription": "Cycles there is an interlock other than  Advanced SIMD/Floating-point instructions or load/store instruction"
+  },
+  {,
+    "EventCode": "0xE5",
+    "EventName": "AGU_DEP_STALL",
+    "BriefDescription": "Cycles there is an interlock for a load/store instruction waiting for data to calculate the address in the AGU"
+  },
+  {,
+    "EventCode": "0xE6",
+    "EventName": "SIMD_DEP_STALL",
+    "BriefDescription": "Cycles there is an interlock for an Advanced SIMD/Floating-point operation."
+  },
+  {,
+    "EventCode": "0xE7",
+    "EventName": "LD_DEP_STALL",
+    "BriefDescription": "Cycles there is a stall in the Wr stage because of a load miss"
+  },
+  {,
+    "EventCode": "0xE8",
+    "EventName": "ST_DEP_STALL",
+    "BriefDescription": "Cycles there is a stall in the Wr stage because of a store"
+  }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
index 219d6756134e..e61c9ca6cf9e 100644
--- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -13,3 +13,4 @@
 #
 #Family-model,Version,Filename,EventType
 0x00000000420f5160,v1,cavium,core
+0x00000000410fd03[[:xdigit:]],v1,cortex-a53,core
diff --git a/tools/perf/tests/backward-ring-buffer.c b/tools/perf/tests/backward-ring-buffer.c
index 4035d43523c3..e0b1b414d466 100644
--- a/tools/perf/tests/backward-ring-buffer.c
+++ b/tools/perf/tests/backward-ring-buffer.c
@@ -31,10 +31,12 @@ static int count_samples(struct perf_evlist *evlist, int *sample_count,
         int i;
 
         for (i = 0; i < evlist->nr_mmaps; i++) {
+                struct perf_mmap *map = &evlist->overwrite_mmap[i];
                 union perf_event *event;
+                u64 start, end;
 
-                perf_mmap__read_catchup(&evlist->overwrite_mmap[i]);
-                while ((event = perf_mmap__read_backward(&evlist->overwrite_mmap[i])) != NULL) {
+                perf_mmap__read_init(map, true, &start, &end);
+                while ((event = perf_mmap__read_event(map, true, &start, end)) != NULL) {
                         const u32 type = event->header.type;
 
                         switch (type) {
@@ -49,6 +51,7 @@ static int count_samples(struct perf_evlist *evlist, int *sample_count,
                                 return TEST_FAIL;
                         }
                 }
+                perf_mmap__read_done(map);
         }
         return TEST_OK;
 }
diff --git a/tools/perf/tests/shell/trace+probe_libc_inet_pton.sh b/tools/perf/tests/shell/trace+probe_libc_inet_pton.sh
index 8b3da21a08f1..c446c894b297 100755
--- a/tools/perf/tests/shell/trace+probe_libc_inet_pton.sh
+++ b/tools/perf/tests/shell/trace+probe_libc_inet_pton.sh
@@ -22,10 +22,23 @@ trace_libc_inet_pton_backtrace() {
         expected[4]="rtt min.*"
         expected[5]="[0-9]+\.[0-9]+[[:space:]]+probe_libc:inet_pton:\([[:xdigit:]]+\)"
         expected[6]=".*inet_pton[[:space:]]\($libc\)$"
-        expected[7]="getaddrinfo[[:space:]]\($libc\)$"
-        expected[8]=".*\(.*/bin/ping.*\)$"
-
-        perf trace --no-syscalls -e probe_libc:inet_pton/max-stack=3/ ping -6 -c 1 ::1 2>&1 | grep -v ^$ | while read line ; do
+        case "$(uname -m)" in
+        s390x)
+                eventattr='call-graph=dwarf'
+                expected[7]="gaih_inet[[:space:]]\(inlined\)$"
+                expected[8]="__GI_getaddrinfo[[:space:]]\(inlined\)$"
+                expected[9]="main[[:space:]]\(.*/bin/ping.*\)$"
+                expected[10]="__libc_start_main[[:space:]]\($libc\)$"
+                expected[11]="_start[[:space:]]\(.*/bin/ping.*\)$"
+                ;;
+        *)
+                eventattr='max-stack=3'
+                expected[7]="getaddrinfo[[:space:]]\($libc\)$"
+                expected[8]=".*\(.*/bin/ping.*\)$"
+                ;;
+        esac
+
+        perf trace --no-syscalls -e probe_libc:inet_pton/$eventattr/ ping -6 -c 1 ::1 2>&1 | grep -v ^$ | while read line ; do
                 echo $line
                 echo "$line" | egrep -q "${expected[$idx]}"
                 if [ $? -ne 0 ] ; then
@@ -33,7 +46,7 @@ trace_libc_inet_pton_backtrace() {
                         exit 1
                 fi
                 let idx+=1
-                [ $idx -eq 9 ] && break
+                [ -z "${expected[$idx]}" ] && break
         done
 }
 
diff --git a/tools/perf/ui/browsers/hists.c b/tools/perf/ui/browsers/hists.c
index 68146f4620a5..6495ee55d9c3 100644
--- a/tools/perf/ui/browsers/hists.c
+++ b/tools/perf/ui/browsers/hists.c
@@ -608,7 +608,8 @@ static int hist_browser__title(struct hist_browser *browser, char *bf, size_t si
         return browser->title ? browser->title(browser, bf, size) : 0;
 }
 
-int hist_browser__run(struct hist_browser *browser, const char *help)
+int hist_browser__run(struct hist_browser *browser, const char *help,
+                      bool warn_lost_event)
 {
         int key;
         char title[160];
@@ -638,8 +639,9 @@ int hist_browser__run(struct hist_browser *browser, const char *help)
                         nr_entries = hist_browser__nr_entries(browser);
                         ui_browser__update_nr_entries(&browser->b, nr_entries);
 
-                        if (browser->hists->stats.nr_lost_warned !=
-                            browser->hists->stats.nr_events[PERF_RECORD_LOST]) {
+                        if (warn_lost_event &&
+                            (browser->hists->stats.nr_lost_warned !=
+                            browser->hists->stats.nr_events[PERF_RECORD_LOST])) {
                                 browser->hists->stats.nr_lost_warned =
                                         browser->hists->stats.nr_events[PERF_RECORD_LOST];
                                 ui_browser__warn_lost_events(&browser->b);
@@ -2763,7 +2765,8 @@ static int perf_evsel__hists_browse(struct perf_evsel *evsel, int nr_events,
                                     bool left_exits,
                                     struct hist_browser_timer *hbt,
                                     float min_pcnt,
-                                    struct perf_env *env)
+                                    struct perf_env *env,
+                                    bool warn_lost_event)
 {
         struct hists *hists = evsel__hists(evsel);
         struct hist_browser *browser = perf_evsel_browser__new(evsel, hbt, env);
@@ -2844,7 +2847,8 @@ static int perf_evsel__hists_browse(struct perf_evsel *evsel, int nr_events,
 
                 nr_options = 0;
 
-                key = hist_browser__run(browser, helpline);
+                key = hist_browser__run(browser, helpline,
+                                        warn_lost_event);
 
                 if (browser->he_selection != NULL) {
                         thread = hist_browser__selected_thread(browser);
@@ -3184,7 +3188,8 @@ static void perf_evsel_menu__write(struct ui_browser *browser,
 
 static int perf_evsel_menu__run(struct perf_evsel_menu *menu,
                                 int nr_events, const char *help,
-                                struct hist_browser_timer *hbt)
+                                struct hist_browser_timer *hbt,
+                                bool warn_lost_event)
 {
         struct perf_evlist *evlist = menu->b.priv;
         struct perf_evsel *pos;
@@ -3203,7 +3208,9 @@ static int perf_evsel_menu__run(struct perf_evsel_menu *menu,
                 case K_TIMER:
                         hbt->timer(hbt->arg);
 
-                        if (!menu->lost_events_warned && menu->lost_events) {
+                        if (!menu->lost_events_warned &&
+                            menu->lost_events &&
+                            warn_lost_event) {
                                 ui_browser__warn_lost_events(&menu->b);
                                 menu->lost_events_warned = true;
                         }
@@ -3224,7 +3231,8 @@ browse_hists:
                         key = perf_evsel__hists_browse(pos, nr_events, help,
                                                        true, hbt,
                                                        menu->min_pcnt,
-                                                       menu->env);
+                                                       menu->env,
+                                                       warn_lost_event);
                         ui_browser__show_title(&menu->b, title);
                         switch (key) {
                         case K_TAB:
@@ -3282,7 +3290,8 @@ static int __perf_evlist__tui_browse_hists(struct perf_evlist *evlist,
                                            int nr_entries, const char *help,
                                            struct hist_browser_timer *hbt,
                                            float min_pcnt,
-                                           struct perf_env *env)
+                                           struct perf_env *env,
+                                           bool warn_lost_event)
 {
         struct perf_evsel *pos;
         struct perf_evsel_menu menu = {
@@ -3309,13 +3318,15 @@ static int __perf_evlist__tui_browse_hists(struct perf_evlist *evlist,
                         menu.b.width = line_len;
         }
 
-        return perf_evsel_menu__run(&menu, nr_entries, help, hbt);
+        return perf_evsel_menu__run(&menu, nr_entries, help,
+                                    hbt, warn_lost_event);
 }
 
 int perf_evlist__tui_browse_hists(struct perf_evlist *evlist, const char *help,
                                   struct hist_browser_timer *hbt,
                                   float min_pcnt,
-                                  struct perf_env *env)
+                                  struct perf_env *env,
+                                  bool warn_lost_event)
 {
         int nr_entries = evlist->nr_entries;
 
@@ -3325,7 +3336,7 @@ single_entry:
 
                 return perf_evsel__hists_browse(first, nr_entries, help,
                                                 false, hbt, min_pcnt,
-                                                env);
+                                                env, warn_lost_event);
         }
 
         if (symbol_conf.event_group) {
@@ -3342,5 +3353,6 @@ single_entry:
         }
 
         return __perf_evlist__tui_browse_hists(evlist, nr_entries, help,
-                                               hbt, min_pcnt, env);
+                                               hbt, min_pcnt, env,
+                                               warn_lost_event);
 }
diff --git a/tools/perf/ui/browsers/hists.h b/tools/perf/ui/browsers/hists.h
index ba431777f559..9428bee076f2 100644
--- a/tools/perf/ui/browsers/hists.h
+++ b/tools/perf/ui/browsers/hists.h
@@ -28,7 +28,8 @@ struct hist_browser {
 
 struct hist_browser *hist_browser__new(struct hists *hists);
 void hist_browser__delete(struct hist_browser *browser);
-int hist_browser__run(struct hist_browser *browser, const char *help);
+int hist_browser__run(struct hist_browser *browser, const char *help,
+                      bool warn_lost_event);
 void hist_browser__init(struct hist_browser *browser,
                         struct hists *hists);
 #endif /* _PERF_UI_BROWSER_HISTS_H_ */
diff --git a/tools/perf/util/evlist.c b/tools/perf/util/evlist.c
index ac35cd214feb..e5fc14e53c05 100644
--- a/tools/perf/util/evlist.c
+++ b/tools/perf/util/evlist.c
@@ -715,28 +715,11 @@ union perf_event *perf_evlist__mmap_read_forward(struct perf_evlist *evlist, int
         return perf_mmap__read_forward(md);
 }
 
-union perf_event *perf_evlist__mmap_read_backward(struct perf_evlist *evlist, int idx)
-{
-        struct perf_mmap *md = &evlist->mmap[idx];
-
-        /*
-         * No need to check messup for backward ring buffer:
-         * We can always read arbitrary long data from a backward
-         * ring buffer unless we forget to pause it before reading.
-         */
-        return perf_mmap__read_backward(md);
-}
-
 union perf_event *perf_evlist__mmap_read(struct perf_evlist *evlist, int idx)
 {
         return perf_evlist__mmap_read_forward(evlist, idx);
 }
 
-void perf_evlist__mmap_read_catchup(struct perf_evlist *evlist, int idx)
-{
-        perf_mmap__read_catchup(&evlist->mmap[idx]);
-}
-
 void perf_evlist__mmap_consume(struct perf_evlist *evlist, int idx)
 {
         perf_mmap__consume(&evlist->mmap[idx], false);
diff --git a/tools/perf/util/evlist.h b/tools/perf/util/evlist.h
index 75f8e0ad5d76..336b838e6957 100644
--- a/tools/perf/util/evlist.h
+++ b/tools/perf/util/evlist.h
@@ -133,10 +133,6 @@ union perf_event *perf_evlist__mmap_read(struct perf_evlist *evlist, int idx);
 
 union perf_event *perf_evlist__mmap_read_forward(struct perf_evlist *evlist,
                                                  int idx);
-union perf_event *perf_evlist__mmap_read_backward(struct perf_evlist *evlist,
-                                                  int idx);
-void perf_evlist__mmap_read_catchup(struct perf_evlist *evlist, int idx);
-
 void perf_evlist__mmap_consume(struct perf_evlist *evlist, int idx);
 
 int perf_evlist__open(struct perf_evlist *evlist);
diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c
index ff359c9ece2e..ef351688b797 100644
--- a/tools/perf/util/evsel.c
+++ b/tools/perf/util/evsel.c
@@ -41,17 +41,7 @@
 
 #include "sane_ctype.h"
 
-static struct {
-        bool sample_id_all;
-        bool exclude_guest;
-        bool mmap2;
-        bool cloexec;
-        bool clockid;
-        bool clockid_wrong;
-        bool lbr_flags;
-        bool write_backward;
-        bool group_read;
-} perf_missing_features;
+struct perf_missing_features perf_missing_features;
 
 static clockid_t clockid;
 
diff --git a/tools/perf/util/evsel.h b/tools/perf/util/evsel.h
index 846e41644525..a7487c6d1866 100644
--- a/tools/perf/util/evsel.h
+++ b/tools/perf/util/evsel.h
@@ -149,6 +149,20 @@ union u64_swap {
         u32 val32[2];
 };
 
+struct perf_missing_features {
+        bool sample_id_all;
+        bool exclude_guest;
+        bool mmap2;
+        bool cloexec;
+        bool clockid;
+        bool clockid_wrong;
+        bool lbr_flags;
+        bool write_backward;
+        bool group_read;
+};
+
+extern struct perf_missing_features perf_missing_features;
+
 struct cpu_map;
 struct target;
 struct thread_map;
diff --git a/tools/perf/util/hist.h b/tools/perf/util/hist.h
index f6630cb95eff..02721b579746 100644
--- a/tools/perf/util/hist.h
+++ b/tools/perf/util/hist.h
@@ -430,7 +430,8 @@ int hist_entry__tui_annotate(struct hist_entry *he, struct perf_evsel *evsel,
 int perf_evlist__tui_browse_hists(struct perf_evlist *evlist, const char *help,
                                   struct hist_browser_timer *hbt,
                                   float min_pcnt,
-                                  struct perf_env *env);
+                                  struct perf_env *env,
+                                  bool warn_lost_event);
 int script_browse(const char *script_opt);
 #else
 static inline
@@ -438,7 +439,8 @@ int perf_evlist__tui_browse_hists(struct perf_evlist *evlist __maybe_unused,
                                   const char *help __maybe_unused,
                                   struct hist_browser_timer *hbt __maybe_unused,
                                   float min_pcnt __maybe_unused,
-                                  struct perf_env *env __maybe_unused)
+                                  struct perf_env *env __maybe_unused,
+                                  bool warn_lost_event __maybe_unused)
 {
         return 0;
 }
diff --git a/tools/perf/util/mmap.c b/tools/perf/util/mmap.c
index 05076e683938..91531a7c8fbf 100644
--- a/tools/perf/util/mmap.c
+++ b/tools/perf/util/mmap.c
@@ -22,29 +22,27 @@ size_t perf_mmap__mmap_len(struct perf_mmap *map)
 
 /* When check_messup is true, 'end' must points to a good entry */
 static union perf_event *perf_mmap__read(struct perf_mmap *map,
-                                         u64 start, u64 end, u64 *prev)
+                                         u64 *startp, u64 end)
 {
         unsigned char *data = map->base + page_size;
         union perf_event *event = NULL;
-        int diff = end - start;
+        int diff = end - *startp;
 
         if (diff >= (int)sizeof(event->header)) {
                 size_t size;
 
-                event = (union perf_event *)&data[start & map->mask];
+                event = (union perf_event *)&data[*startp & map->mask];
                 size = event->header.size;
 
-                if (size < sizeof(event->header) || diff < (int)size) {
-                        event = NULL;
-                        goto broken_event;
-                }
+                if (size < sizeof(event->header) || diff < (int)size)
+                        return NULL;
 
                 /*
                  * Event straddles the mmap boundary -- header should always
                  * be inside due to u64 alignment of output.
                  */
-                if ((start & map->mask) + size != ((start + size) & map->mask)) {
-                        unsigned int offset = start;
+                if ((*startp & map->mask) + size != ((*startp + size) & map->mask)) {
+                        unsigned int offset = *startp;
                         unsigned int len = min(sizeof(*event), size), cpy;
                         void *dst = map->event_copy;
 
@@ -59,20 +57,19 @@ static union perf_event *perf_mmap__read(struct perf_mmap *map,
                         event = (union perf_event *)map->event_copy;
                 }
 
-                start += size;
+                *startp += size;
         }
 
-broken_event:
-        if (prev)
-                *prev = start;
-
         return event;
 }
 
+/*
+ * legacy interface for mmap read.
+ * Don't use it. Use perf_mmap__read_event().
+ */
 union perf_event *perf_mmap__read_forward(struct perf_mmap *map)
 {
         u64 head;
-        u64 old = map->prev;
 
         /*
          * Check if event was unmapped due to a POLLHUP/POLLERR.
@@ -82,13 +79,26 @@ union perf_event *perf_mmap__read_forward(struct perf_mmap *map)
 
         head = perf_mmap__read_head(map);
 
-        return perf_mmap__read(map, old, head, &map->prev);
+        return perf_mmap__read(map, &map->prev, head);
 }
 
-union perf_event *perf_mmap__read_backward(struct perf_mmap *map)
+/*
+ * Read event from ring buffer one by one.
+ * Return one event for each call.
+ *
+ * Usage:
+ * perf_mmap__read_init()
+ * while(event = perf_mmap__read_event()) {
+ *      //process the event
+ *      perf_mmap__consume()
+ * }
+ * perf_mmap__read_done()
+ */
+union perf_event *perf_mmap__read_event(struct perf_mmap *map,
+                                        bool overwrite,
+                                        u64 *startp, u64 end)
 {
-        u64 head, end;
-        u64 start = map->prev;
+        union perf_event *event;
 
         /*
          * Check if event was unmapped due to a POLLHUP/POLLERR.
@@ -96,40 +106,19 @@ union perf_event *perf_mmap__read_backward(struct perf_mmap *map)
         if (!refcount_read(&map->refcnt))
                 return NULL;
 
-        head = perf_mmap__read_head(map);
-        if (!head)
+        if (startp == NULL)
                 return NULL;
 
-        /*
-         * 'head' pointer starts from 0. Kernel minus sizeof(record) form
-         * it each time when kernel writes to it, so in fact 'head' is
-         * negative. 'end' pointer is made manually by adding the size of
-         * the ring buffer to 'head' pointer, means the validate data can
-         * read is the whole ring buffer. If 'end' is positive, the ring
-         * buffer has not fully filled, so we must adjust 'end' to 0.
-         *
-         * However, since both 'head' and 'end' is unsigned, we can't
-         * simply compare 'end' against 0. Here we compare '-head' and
-         * the size of the ring buffer, where -head is the number of bytes
-         * kernel write to the ring buffer.
-         */
-        if (-head < (u64)(map->mask + 1))
-                end = 0;
-        else
-                end = head + map->mask + 1;
-
-        return perf_mmap__read(map, start, end, &map->prev);
-}
+        /* non-overwirte doesn't pause the ringbuffer */
+        if (!overwrite)
+                end = perf_mmap__read_head(map);
 
-void perf_mmap__read_catchup(struct perf_mmap *map)
-{
-        u64 head;
+        event = perf_mmap__read(map, startp, end);
 
-        if (!refcount_read(&map->refcnt))
-                return;
+        if (!overwrite)
+                map->prev = *startp;
 
-        head = perf_mmap__read_head(map);
-        map->prev = head;
+        return event;
 }
 
 static bool perf_mmap__empty(struct perf_mmap *map)
@@ -267,41 +256,60 @@ static int overwrite_rb_find_range(void *buf, int mask, u64 head, u64 *start, u6
         return -1;
 }
 
-int perf_mmap__push(struct perf_mmap *md, bool overwrite,
-                    void *to, int push(void *to, void *buf, size_t size))
+/*
+ * Report the start and end of the available data in ringbuffer
+ */
+int perf_mmap__read_init(struct perf_mmap *md, bool overwrite,
+                         u64 *startp, u64 *endp)
 {
         u64 head = perf_mmap__read_head(md);
         u64 old = md->prev;
-        u64 end = head, start = old;
         unsigned char *data = md->base + page_size;
         unsigned long size;
-        void *buf;
-        int rc = 0;
 
-        start = overwrite ? head : old;
-        end = overwrite ? old : head;
+        *startp = overwrite ? head : old;
+        *endp = overwrite ? old : head;
 
-        if (start == end)
-                return 0;
+        if (*startp == *endp)
+                return -EAGAIN;
 
-        size = end - start;
+        size = *endp - *startp;
         if (size > (unsigned long)(md->mask) + 1) {
                 if (!overwrite) {
                         WARN_ONCE(1, "failed to keep up with mmap data. (warn only once)\n");
 
                         md->prev = head;
                         perf_mmap__consume(md, overwrite);
-                        return 0;
+                        return -EAGAIN;
                 }
 
                 /*
                  * Backward ring buffer is full. We still have a chance to read
                  * most of data from it.
                  */
-                if (overwrite_rb_find_range(data, md->mask, head, &start, &end))
-                        return -1;
+                if (overwrite_rb_find_range(data, md->mask, head, startp, endp))
+                        return -EINVAL;
         }
 
+        return 0;
+}
+
+int perf_mmap__push(struct perf_mmap *md, bool overwrite,
+                    void *to, int push(void *to, void *buf, size_t size))
+{
+        u64 head = perf_mmap__read_head(md);
+        u64 end, start;
+        unsigned char *data = md->base + page_size;
+        unsigned long size;
+        void *buf;
+        int rc = 0;
+
+        rc = perf_mmap__read_init(md, overwrite, &start, &end);
+        if (rc < 0)
+                return (rc == -EAGAIN) ? 0 : -1;
+
+        size = end - start;
+
         if ((start & md->mask) + size != (end & md->mask)) {
                 buf = &data[start & md->mask];
                 size = md->mask + 1 - (start & md->mask);
@@ -327,3 +335,14 @@ int perf_mmap__push(struct perf_mmap *md, bool overwrite,
 out:
         return rc;
 }
+
+/*
+ * Mandatory for overwrite mode
+ * The direction of overwrite mode is backward.
+ * The last perf_mmap__read() will set tail to map->prev.
+ * Need to correct the map->prev to head which is the end of next read.
+ */
+void perf_mmap__read_done(struct perf_mmap *map)
+{
+        map->prev = perf_mmap__read_head(map);
+}
diff --git a/tools/perf/util/mmap.h b/tools/perf/util/mmap.h
index e43d7b55a55f..ec7d3a24e276 100644
--- a/tools/perf/util/mmap.h
+++ b/tools/perf/util/mmap.h
@@ -65,8 +65,6 @@ void perf_mmap__put(struct perf_mmap *map);
 
 void perf_mmap__consume(struct perf_mmap *map, bool overwrite);
 
-void perf_mmap__read_catchup(struct perf_mmap *md);
-
 static inline u64 perf_mmap__read_head(struct perf_mmap *mm)
 {
         struct perf_event_mmap_page *pc = mm->base;
@@ -87,11 +85,17 @@ static inline void perf_mmap__write_tail(struct perf_mmap *md, u64 tail)
 }
 
 union perf_event *perf_mmap__read_forward(struct perf_mmap *map);
-union perf_event *perf_mmap__read_backward(struct perf_mmap *map);
+
+union perf_event *perf_mmap__read_event(struct perf_mmap *map,
+                                        bool overwrite,
+                                        u64 *startp, u64 end);
 
 int perf_mmap__push(struct perf_mmap *md, bool backward,
                     void *to, int push(void *to, void *buf, size_t size));
 
 size_t perf_mmap__mmap_len(struct perf_mmap *map);
 
+int perf_mmap__read_init(struct perf_mmap *md, bool overwrite,
+                         u64 *startp, u64 *endp);
+void perf_mmap__read_done(struct perf_mmap *map);
 #endif /*__PERF_MMAP_H */
diff --git a/tools/perf/util/util.c b/tools/perf/util/util.c
index 443892dabedb..1019bbc5dbd8 100644
--- a/tools/perf/util/util.c
+++ b/tools/perf/util/util.c
@@ -340,35 +340,15 @@ size_t hex_width(u64 v)
         return n;
 }
 
-static int hex(char ch)
-{
-        if ((ch >= '0') && (ch <= '9'))
-                return ch - '0';
-        if ((ch >= 'a') && (ch <= 'f'))
-                return ch - 'a' + 10;
-        if ((ch >= 'A') && (ch <= 'F'))
-                return ch - 'A' + 10;
-        return -1;
-}
-
 /*
  * While we find nice hex chars, build a long_val.
  * Return number of chars processed.
  */
 int hex2u64(const char *ptr, u64 *long_val)
 {
-        const char *p = ptr;
-        *long_val = 0;
-
-        while (*p) {
-                const int hex_val = hex(*p);
+        char *p;
 
-                if (hex_val < 0)
-                        break;
-
-                *long_val = (*long_val << 4) | hex_val;
-                p++;
-        }
+        *long_val = strtoull(ptr, &p, 16);
 
         return p - ptr;
 }
diff --git a/tools/power/acpi/Makefile.config b/tools/power/acpi/Makefile.config
index a1883bbb0144..2cccbba64418 100644
--- a/tools/power/acpi/Makefile.config
+++ b/tools/power/acpi/Makefile.config
@@ -56,9 +56,6 @@ INSTALL_SCRIPT = ${INSTALL_PROGRAM}
 # to compile vs uClibc, that can be done here as well.
 CROSS = #/usr/i386-linux-uclibc/usr/bin/i386-uclibc-
 CROSS_COMPILE ?= $(CROSS)
-CC = $(CROSS_COMPILE)gcc
-LD = $(CROSS_COMPILE)gcc
-STRIP = $(CROSS_COMPILE)strip
 HOSTCC = gcc
 
 # check if compiler option is supported
diff --git a/tools/scripts/Makefile.include b/tools/scripts/Makefile.include
index fcb3ed0be5f8..dd614463d4d6 100644
--- a/tools/scripts/Makefile.include
+++ b/tools/scripts/Makefile.include
@@ -42,6 +42,24 @@ EXTRA_WARNINGS += -Wformat
 
 CC_NO_CLANG := $(shell $(CC) -dM -E -x c /dev/null | grep -Fq "__clang__"; echo $$?)
 
+# Makefiles suck: This macro sets a default value of $(2) for the
+# variable named by $(1), unless the variable has been set by
+# environment or command line. This is necessary for CC and AR
+# because make sets default values, so the simpler ?= approach
+# won't work as expected.
+define allow-override
+  $(if $(or $(findstring environment,$(origin $(1))),\
+            $(findstring command line,$(origin $(1)))),,\
+    $(eval $(1) = $(2)))
+endef
+
+# Allow setting various cross-compile vars or setting CROSS_COMPILE as a prefix.
+$(call allow-override,CC,$(CROSS_COMPILE)gcc)
+$(call allow-override,AR,$(CROSS_COMPILE)ar)
+$(call allow-override,LD,$(CROSS_COMPILE)ld)
+$(call allow-override,CXX,$(CROSS_COMPILE)g++)
+$(call allow-override,STRIP,$(CROSS_COMPILE)strip)
+
 ifeq ($(CC_NO_CLANG), 1)
 EXTRA_WARNINGS += -Wstrict-aliasing=3
 endif
diff --git a/tools/spi/Makefile b/tools/spi/Makefile
index 90615e10c79a..815d15589177 100644
--- a/tools/spi/Makefile
+++ b/tools/spi/Makefile
@@ -11,8 +11,6 @@ endif
 # (this improves performance and avoids hard-to-debug behaviour);
 MAKEFLAGS += -r
 
-CC = $(CROSS_COMPILE)gcc
-LD = $(CROSS_COMPILE)ld
 CFLAGS += -O2 -Wall -g -D_GNU_SOURCE -I$(OUTPUT)include
 
 ALL_TARGETS := spidev_test spidev_fdx
diff --git a/tools/testing/radix-tree/idr-test.c b/tools/testing/radix-tree/idr-test.c
index 44ef9eba5a7a..6c645eb77d42 100644
--- a/tools/testing/radix-tree/idr-test.c
+++ b/tools/testing/radix-tree/idr-test.c
@@ -178,6 +178,55 @@ void idr_get_next_test(int base)
         idr_destroy(&idr);
 }
 
+int idr_u32_cb(int id, void *ptr, void *data)
+{
+        BUG_ON(id < 0);
+        BUG_ON(ptr != DUMMY_PTR);
+        return 0;
+}
+
+void idr_u32_test1(struct idr *idr, u32 handle)
+{
+        static bool warned = false;
+        u32 id = handle;
+        int sid = 0;
+        void *ptr;
+
+        BUG_ON(idr_alloc_u32(idr, DUMMY_PTR, &id, id, GFP_KERNEL));
+        BUG_ON(id != handle);
+        BUG_ON(idr_alloc_u32(idr, DUMMY_PTR, &id, id, GFP_KERNEL) != -ENOSPC);
+        BUG_ON(id != handle);
+        if (!warned && id > INT_MAX)
+                printk("vvv Ignore these warnings\n");
+        ptr = idr_get_next(idr, &sid);
+        if (id > INT_MAX) {
+                BUG_ON(ptr != NULL);
+                BUG_ON(sid != 0);
+        } else {
+                BUG_ON(ptr != DUMMY_PTR);
+                BUG_ON(sid != id);
+        }
+        idr_for_each(idr, idr_u32_cb, NULL);
+        if (!warned && id > INT_MAX) {
+                printk("^^^ Warnings over\n");
+                warned = true;
+        }
+        BUG_ON(idr_remove(idr, id) != DUMMY_PTR);
+        BUG_ON(!idr_is_empty(idr));
+}
+
+void idr_u32_test(int base)
+{
+        DEFINE_IDR(idr);
+        idr_init_base(&idr, base);
+        idr_u32_test1(&idr, 10);
+        idr_u32_test1(&idr, 0x7fffffff);
+        idr_u32_test1(&idr, 0x80000000);
+        idr_u32_test1(&idr, 0x80000001);
+        idr_u32_test1(&idr, 0xffe00000);
+        idr_u32_test1(&idr, 0xffffffff);
+}
+
 void idr_checks(void)
 {
         unsigned long i;
@@ -248,6 +297,9 @@ void idr_checks(void)
         idr_get_next_test(0);
         idr_get_next_test(1);
         idr_get_next_test(4);
+        idr_u32_test(4);
+        idr_u32_test(1);
+        idr_u32_test(0);
 }
 
 /*
diff --git a/tools/testing/radix-tree/linux.c b/tools/testing/radix-tree/linux.c
index 6903ccf35595..44a0d1ad4408 100644
--- a/tools/testing/radix-tree/linux.c
+++ b/tools/testing/radix-tree/linux.c
@@ -29,7 +29,7 @@ void *kmem_cache_alloc(struct kmem_cache *cachep, int flags)
 {
         struct radix_tree_node *node;
 
-        if (flags & __GFP_NOWARN)
+        if (!(flags & __GFP_DIRECT_RECLAIM))
                 return NULL;
 
         pthread_mutex_lock(&cachep->lock);
@@ -73,10 +73,17 @@ void kmem_cache_free(struct kmem_cache *cachep, void *objp)
 
 void *kmalloc(size_t size, gfp_t gfp)
 {
-        void *ret = malloc(size);
+        void *ret;
+
+        if (!(gfp & __GFP_DIRECT_RECLAIM))
+                return NULL;
+
+        ret = malloc(size);
         uatomic_inc(&nr_allocated);
         if (kmalloc_verbose)
                 printf("Allocating %p from malloc\n", ret);
+        if (gfp & __GFP_ZERO)
+                memset(ret, 0, size);
         return ret;
 }
 
diff --git a/tools/testing/radix-tree/linux/compiler_types.h b/tools/testing/radix-tree/linux/compiler_types.h
new file mode 100644
index 000000000000..e69de29bb2d1
--- /dev/null
+++ b/tools/testing/radix-tree/linux/compiler_types.h
diff --git a/tools/testing/radix-tree/linux/gfp.h b/tools/testing/radix-tree/linux/gfp.h
index e9fff59dfd8a..e3201ccf54c3 100644
--- a/tools/testing/radix-tree/linux/gfp.h
+++ b/tools/testing/radix-tree/linux/gfp.h
@@ -11,6 +11,7 @@
 #define __GFP_IO                0x40u
 #define __GFP_FS                0x80u
 #define __GFP_NOWARN            0x200u
+#define __GFP_ZERO              0x8000u
 #define __GFP_ATOMIC            0x80000u
 #define __GFP_ACCOUNT           0x100000u
 #define __GFP_DIRECT_RECLAIM    0x400000u
diff --git a/tools/testing/radix-tree/linux/slab.h b/tools/testing/radix-tree/linux/slab.h
index 979baeec7e70..a037def0dec6 100644
--- a/tools/testing/radix-tree/linux/slab.h
+++ b/tools/testing/radix-tree/linux/slab.h
@@ -3,6 +3,7 @@
 #define SLAB_H
 
 #include <linux/types.h>
+#include <linux/gfp.h>
 
 #define SLAB_HWCACHE_ALIGN 1
 #define SLAB_PANIC 2
@@ -11,6 +12,11 @@
 void *kmalloc(size_t size, gfp_t);
 void kfree(void *);
 
+static inline void *kzalloc(size_t size, gfp_t gfp)
+{
+        return kmalloc(size, gfp | __GFP_ZERO);
+}
+
 void *kmem_cache_alloc(struct kmem_cache *cachep, int flags);
 void kmem_cache_free(struct kmem_cache *cachep, void *objp);
 
diff --git a/tools/testing/selftests/android/Makefile b/tools/testing/selftests/android/Makefile
index 1a7492268993..f6304d2be90c 100644
--- a/tools/testing/selftests/android/Makefile
+++ b/tools/testing/selftests/android/Makefile
@@ -11,11 +11,11 @@ all:
                 BUILD_TARGET=$(OUTPUT)/$$DIR;   \
                 mkdir $$BUILD_TARGET  -p;       \
                 make OUTPUT=$$BUILD_TARGET -C $$DIR $@;\
-                #SUBDIR test prog name should be in the form: SUBDIR_test.sh
+                #SUBDIR test prog name should be in the form: SUBDIR_test.sh \
                 TEST=$$DIR"_test.sh"; \
-                if [ -e $$DIR/$$TEST ]; then
-                        rsync -a $$DIR/$$TEST $$BUILD_TARGET/;
-                fi
+                if [ -e $$DIR/$$TEST ]; then \
+                        rsync -a $$DIR/$$TEST $$BUILD_TARGET/; \
+                fi \
         done
 
 override define RUN_TESTS
diff --git a/tools/testing/selftests/bpf/.gitignore b/tools/testing/selftests/bpf/.gitignore
index cc15af2e54fe..9cf83f895d98 100644
--- a/tools/testing/selftests/bpf/.gitignore
+++ b/tools/testing/selftests/bpf/.gitignore
@@ -11,3 +11,4 @@ test_progs
 test_tcpbpf_user
 test_verifier_log
 feature
+test_libbpf_open
diff --git a/tools/testing/selftests/bpf/test_maps.c b/tools/testing/selftests/bpf/test_maps.c
index 436c4c72414f..9e03a4c356a4 100644
--- a/tools/testing/selftests/bpf/test_maps.c
+++ b/tools/testing/selftests/bpf/test_maps.c
@@ -126,6 +126,8 @@ static void test_hashmap_sizes(int task, void *data)
                         fd = bpf_create_map(BPF_MAP_TYPE_HASH, i, j,
                                             2, map_flags);
                         if (fd < 0) {
+                                if (errno == ENOMEM)
+                                        return;
                                 printf("Failed to create hashmap key=%d value=%d '%s'\n",
                                        i, j, strerror(errno));
                                 exit(1);
diff --git a/tools/testing/selftests/bpf/test_tcpbpf_kern.c b/tools/testing/selftests/bpf/test_tcpbpf_kern.c
index 57119ad57a3f..3e645ee41ed5 100644
--- a/tools/testing/selftests/bpf/test_tcpbpf_kern.c
+++ b/tools/testing/selftests/bpf/test_tcpbpf_kern.c
@@ -5,7 +5,6 @@
 #include <linux/if_ether.h>
 #include <linux/if_packet.h>
 #include <linux/ip.h>
-#include <linux/in6.h>
 #include <linux/types.h>
 #include <linux/socket.h>
 #include <linux/tcp.h>
diff --git a/tools/testing/selftests/bpf/test_verifier.c b/tools/testing/selftests/bpf/test_verifier.c
index c0f16e93f9bd..c73592fa3d41 100644
--- a/tools/testing/selftests/bpf/test_verifier.c
+++ b/tools/testing/selftests/bpf/test_verifier.c
@@ -2587,6 +2587,32 @@ static struct bpf_test tests[] = {
                 .result = ACCEPT,
         },
         {
+                "runtime/jit: pass negative index to tail_call",
+                .insns = {
+                        BPF_MOV64_IMM(BPF_REG_3, -1),
+                        BPF_LD_MAP_FD(BPF_REG_2, 0),
+                        BPF_RAW_INSN(BPF_JMP | BPF_CALL, 0, 0, 0,
+                                     BPF_FUNC_tail_call),
+                        BPF_MOV64_IMM(BPF_REG_0, 0),
+                        BPF_EXIT_INSN(),
+                },
+                .fixup_prog = { 1 },
+                .result = ACCEPT,
+        },
+        {
+                "runtime/jit: pass > 32bit index to tail_call",
+                .insns = {
+                        BPF_LD_IMM64(BPF_REG_3, 0x100000000ULL),
+                        BPF_LD_MAP_FD(BPF_REG_2, 0),
+                        BPF_RAW_INSN(BPF_JMP | BPF_CALL, 0, 0, 0,
+                                     BPF_FUNC_tail_call),
+                        BPF_MOV64_IMM(BPF_REG_0, 0),
+                        BPF_EXIT_INSN(),
+                },
+                .fixup_prog = { 2 },
+                .result = ACCEPT,
+        },
+        {
                 "stack pointer arithmetic",
                 .insns = {
                         BPF_MOV64_IMM(BPF_REG_1, 4),
diff --git a/tools/testing/selftests/futex/Makefile b/tools/testing/selftests/futex/Makefile
index cea4adcd42b8..a63e8453984d 100644
--- a/tools/testing/selftests/futex/Makefile
+++ b/tools/testing/selftests/futex/Makefile
@@ -12,9 +12,9 @@ all:
                 BUILD_TARGET=$(OUTPUT)/$$DIR;   \
                 mkdir $$BUILD_TARGET  -p;       \
                 make OUTPUT=$$BUILD_TARGET -C $$DIR $@;\
-                if [ -e $$DIR/$(TEST_PROGS) ]; then
-                        rsync -a $$DIR/$(TEST_PROGS) $$BUILD_TARGET/;
-                fi
+                if [ -e $$DIR/$(TEST_PROGS) ]; then \
+                        rsync -a $$DIR/$(TEST_PROGS) $$BUILD_TARGET/; \
+                fi \
         done
 
 override define RUN_TESTS
diff --git a/tools/testing/selftests/memfd/Makefile b/tools/testing/selftests/memfd/Makefile
index a5276a91dfbf..0862e6f47a38 100644
--- a/tools/testing/selftests/memfd/Makefile
+++ b/tools/testing/selftests/memfd/Makefile
@@ -5,6 +5,7 @@ CFLAGS += -I../../../../include/
 CFLAGS += -I../../../../usr/include/
 
 TEST_PROGS := run_tests.sh
+TEST_FILES := run_fuse_test.sh
 TEST_GEN_FILES := memfd_test fuse_mnt fuse_test
 
 fuse_mnt.o: CFLAGS += $(shell pkg-config fuse --cflags)
diff --git a/tools/testing/selftests/memfd/config b/tools/testing/selftests/memfd/config
new file mode 100644
index 000000000000..835c7f4dadcd
--- /dev/null
+++ b/tools/testing/selftests/memfd/config
@@ -0,0 +1 @@
+CONFIG_FUSE_FS=m
diff --git a/tools/testing/selftests/memory-hotplug/Makefile b/tools/testing/selftests/memory-hotplug/Makefile
index 86636d207adf..183b46883875 100644
--- a/tools/testing/selftests/memory-hotplug/Makefile
+++ b/tools/testing/selftests/memory-hotplug/Makefile
@@ -4,7 +4,7 @@ all:
 include ../lib.mk
 
 TEST_PROGS := mem-on-off-test.sh
-override RUN_TESTS := ./mem-on-off-test.sh -r 2 && echo "selftests: memory-hotplug [PASS]" || echo "selftests: memory-hotplug [FAIL]"
+override RUN_TESTS := @./mem-on-off-test.sh -r 2 && echo "selftests: memory-hotplug [PASS]" || echo "selftests: memory-hotplug [FAIL]"
 override EMIT_TESTS := echo "$(RUN_TESTS)"
 
 run_full_test:
diff --git a/tools/testing/selftests/powerpc/alignment/alignment_handler.c b/tools/testing/selftests/powerpc/alignment/alignment_handler.c
index 39fd362415cf..0f2698f9fd6d 100644
--- a/tools/testing/selftests/powerpc/alignment/alignment_handler.c
+++ b/tools/testing/selftests/powerpc/alignment/alignment_handler.c
@@ -57,7 +57,7 @@ volatile int gotsig;
 
 void sighandler(int sig, siginfo_t *info, void *ctx)
 {
-        struct ucontext *ucp = ctx;
+        ucontext_t *ucp = ctx;
 
         if (!testing) {
                 signal(sig, SIG_DFL);
diff --git a/tools/testing/selftests/pstore/config b/tools/testing/selftests/pstore/config
index 6a8e5a9bfc10..d148f9f89fb6 100644
--- a/tools/testing/selftests/pstore/config
+++ b/tools/testing/selftests/pstore/config
@@ -2,3 +2,4 @@ CONFIG_MISC_FILESYSTEMS=y
 CONFIG_PSTORE=y
 CONFIG_PSTORE_PMSG=y
 CONFIG_PSTORE_CONSOLE=y
+CONFIG_PSTORE_RAM=m
diff --git a/tools/testing/selftests/seccomp/seccomp_bpf.c b/tools/testing/selftests/seccomp/seccomp_bpf.c
index 0b457e8e0f0c..5df609950a66 100644
--- a/tools/testing/selftests/seccomp/seccomp_bpf.c
+++ b/tools/testing/selftests/seccomp/seccomp_bpf.c
@@ -141,6 +141,15 @@ struct seccomp_data {
 #define SECCOMP_FILTER_FLAG_LOG 2
 #endif
 
+#ifndef PTRACE_SECCOMP_GET_METADATA
+#define PTRACE_SECCOMP_GET_METADATA     0x420d
+
+struct seccomp_metadata {
+        __u64 filter_off;       /* Input: which filter */
+        __u64 flags;             /* Output: filter's flags */
+};
+#endif
+
 #ifndef seccomp
 int seccomp(unsigned int op, unsigned int flags, void *args)
 {
@@ -2845,6 +2854,58 @@ TEST(get_action_avail)
         EXPECT_EQ(errno, EOPNOTSUPP);
 }
 
+TEST(get_metadata)
+{
+        pid_t pid;
+        int pipefd[2];
+        char buf;
+        struct seccomp_metadata md;
+
+        ASSERT_EQ(0, pipe(pipefd));
+
+        pid = fork();
+        ASSERT_GE(pid, 0);
+        if (pid == 0) {
+                struct sock_filter filter[] = {
+                        BPF_STMT(BPF_RET|BPF_K, SECCOMP_RET_ALLOW),
+                };
+                struct sock_fprog prog = {
+                        .len = (unsigned short)ARRAY_SIZE(filter),
+                        .filter = filter,
+                };
+
+                /* one with log, one without */
+                ASSERT_EQ(0, seccomp(SECCOMP_SET_MODE_FILTER,
+                                     SECCOMP_FILTER_FLAG_LOG, &prog));
+                ASSERT_EQ(0, seccomp(SECCOMP_SET_MODE_FILTER, 0, &prog));
+
+                ASSERT_EQ(0, close(pipefd[0]));
+                ASSERT_EQ(1, write(pipefd[1], "1", 1));
+                ASSERT_EQ(0, close(pipefd[1]));
+
+                while (1)
+                        sleep(100);
+        }
+
+        ASSERT_EQ(0, close(pipefd[1]));
+        ASSERT_EQ(1, read(pipefd[0], &buf, 1));
+
+        ASSERT_EQ(0, ptrace(PTRACE_ATTACH, pid));
+        ASSERT_EQ(pid, waitpid(pid, NULL, 0));
+
+        md.filter_off = 0;
+        ASSERT_EQ(sizeof(md), ptrace(PTRACE_SECCOMP_GET_METADATA, pid, sizeof(md), &md));
+        EXPECT_EQ(md.flags, SECCOMP_FILTER_FLAG_LOG);
+        EXPECT_EQ(md.filter_off, 0);
+
+        md.filter_off = 1;
+        ASSERT_EQ(sizeof(md), ptrace(PTRACE_SECCOMP_GET_METADATA, pid, sizeof(md), &md));
+        EXPECT_EQ(md.flags, 0);
+        EXPECT_EQ(md.filter_off, 1);
+
+        ASSERT_EQ(0, kill(pid, SIGKILL));
+}
+
 /*
  * TODO:
  * - add microbenchmarks
diff --git a/tools/testing/selftests/sync/Makefile b/tools/testing/selftests/sync/Makefile
index b3c8ba3cb668..d0121a8a3523 100644
--- a/tools/testing/selftests/sync/Makefile
+++ b/tools/testing/selftests/sync/Makefile
@@ -30,7 +30,7 @@ $(TEST_CUSTOM_PROGS): $(TESTS) $(OBJS)
         $(CC) -o $(TEST_CUSTOM_PROGS) $(OBJS) $(TESTS) $(CFLAGS) $(LDFLAGS)
 
 $(OBJS): $(OUTPUT)/%.o: %.c
-        $(CC) -c $^ -o $@
+        $(CC) -c $^ -o $@ $(CFLAGS)
 
 $(TESTS): $(OUTPUT)/%.o: %.c
         $(CC) -c $^ -o $@
diff --git a/tools/testing/selftests/vDSO/Makefile b/tools/testing/selftests/vDSO/Makefile
index 3d5a62ff7d31..f5d7a7851e21 100644
--- a/tools/testing/selftests/vDSO/Makefile
+++ b/tools/testing/selftests/vDSO/Makefile
@@ -1,4 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
+include ../lib.mk
+
 ifndef CROSS_COMPILE
 CFLAGS := -std=gnu99
 CFLAGS_vdso_standalone_test_x86 := -nostdlib -fno-asynchronous-unwind-tables -fno-stack-protector
@@ -6,16 +8,14 @@ ifeq ($(CONFIG_X86_32),y)
 LDLIBS += -lgcc_s
 endif
 
-TEST_PROGS := vdso_test vdso_standalone_test_x86
+TEST_PROGS := $(OUTPUT)/vdso_test $(OUTPUT)/vdso_standalone_test_x86
 
 all: $(TEST_PROGS)
-vdso_test: parse_vdso.c vdso_test.c
-vdso_standalone_test_x86: vdso_standalone_test_x86.c parse_vdso.c
+$(OUTPUT)/vdso_test: parse_vdso.c vdso_test.c
+$(OUTPUT)/vdso_standalone_test_x86: vdso_standalone_test_x86.c parse_vdso.c
         $(CC) $(CFLAGS) $(CFLAGS_vdso_standalone_test_x86) \
                 vdso_standalone_test_x86.c parse_vdso.c \
-                -o vdso_standalone_test_x86
+                -o $@
 
-include ../lib.mk
-clean:
-        rm -fr $(TEST_PROGS)
+EXTRA_CLEAN := $(TEST_PROGS)
 endif
diff --git a/tools/testing/selftests/vm/.gitignore b/tools/testing/selftests/vm/.gitignore
index 63c94d776e89..342c7bc9dc8c 100644
--- a/tools/testing/selftests/vm/.gitignore
+++ b/tools/testing/selftests/vm/.gitignore
@@ -11,3 +11,4 @@ mlock-intersect-test
 mlock-random-test
 virtual_address_range
 gup_benchmark
+va_128TBswitch
diff --git a/tools/testing/selftests/x86/Makefile b/tools/testing/selftests/x86/Makefile
index 10ca46df1449..d744991c0f4f 100644
--- a/tools/testing/selftests/x86/Makefile
+++ b/tools/testing/selftests/x86/Makefile
@@ -5,16 +5,26 @@ include ../lib.mk
 
 .PHONY: all all_32 all_64 warn_32bit_failure clean
 
-TARGETS_C_BOTHBITS := single_step_syscall sysret_ss_attrs syscall_nt ptrace_syscall test_mremap_vdso \
-                        check_initial_reg_state sigreturn ldt_gdt iopl mpx-mini-test ioperm \
+UNAME_M := $(shell uname -m)
+CAN_BUILD_I386 := $(shell ./check_cc.sh $(CC) trivial_32bit_program.c -m32)
+CAN_BUILD_X86_64 := $(shell ./check_cc.sh $(CC) trivial_64bit_program.c)
+
+TARGETS_C_BOTHBITS := single_step_syscall sysret_ss_attrs syscall_nt test_mremap_vdso \
+                        check_initial_reg_state sigreturn iopl mpx-mini-test ioperm \
                         protection_keys test_vdso test_vsyscall
 TARGETS_C_32BIT_ONLY := entry_from_vm86 syscall_arg_fault test_syscall_vdso unwind_vdso \
                         test_FCMOV test_FCOMI test_FISTTP \
                         vdso_restorer
-TARGETS_C_64BIT_ONLY := fsgsbase sysret_rip 5lvl
+TARGETS_C_64BIT_ONLY := fsgsbase sysret_rip
+# Some selftests require 32bit support enabled also on 64bit systems
+TARGETS_C_32BIT_NEEDED := ldt_gdt ptrace_syscall
 
-TARGETS_C_32BIT_ALL := $(TARGETS_C_BOTHBITS) $(TARGETS_C_32BIT_ONLY)
+TARGETS_C_32BIT_ALL := $(TARGETS_C_BOTHBITS) $(TARGETS_C_32BIT_ONLY) $(TARGETS_C_32BIT_NEEDED)
 TARGETS_C_64BIT_ALL := $(TARGETS_C_BOTHBITS) $(TARGETS_C_64BIT_ONLY)
+ifeq ($(CAN_BUILD_I386)$(CAN_BUILD_X86_64),11)
+TARGETS_C_64BIT_ALL += $(TARGETS_C_32BIT_NEEDED)
+endif
+
 BINARIES_32 := $(TARGETS_C_32BIT_ALL:%=%_32)
 BINARIES_64 := $(TARGETS_C_64BIT_ALL:%=%_64)
 
@@ -23,10 +33,6 @@ BINARIES_64 := $(patsubst %,$(OUTPUT)/%,$(BINARIES_64))
 
 CFLAGS := -O2 -g -std=gnu99 -pthread -Wall -no-pie
 
-UNAME_M := $(shell uname -m)
-CAN_BUILD_I386 := $(shell ./check_cc.sh $(CC) trivial_32bit_program.c -m32)
-CAN_BUILD_X86_64 := $(shell ./check_cc.sh $(CC) trivial_64bit_program.c)
-
 define gen-target-rule-32
 $(1) $(1)_32: $(OUTPUT)/$(1)_32
 .PHONY: $(1) $(1)_32
@@ -40,12 +46,14 @@ endef
 ifeq ($(CAN_BUILD_I386),1)
 all: all_32
 TEST_PROGS += $(BINARIES_32)
+EXTRA_CFLAGS += -DCAN_BUILD_32
 $(foreach t,$(TARGETS_C_32BIT_ALL),$(eval $(call gen-target-rule-32,$(t))))
 endif
 
 ifeq ($(CAN_BUILD_X86_64),1)
 all: all_64
 TEST_PROGS += $(BINARIES_64)
+EXTRA_CFLAGS += -DCAN_BUILD_64
 $(foreach t,$(TARGETS_C_64BIT_ALL),$(eval $(call gen-target-rule-64,$(t))))
 endif
 
diff --git a/tools/testing/selftests/x86/mpx-mini-test.c b/tools/testing/selftests/x86/mpx-mini-test.c
index ec0f6b45ce8b..9c0325e1ea68 100644
--- a/tools/testing/selftests/x86/mpx-mini-test.c
+++ b/tools/testing/selftests/x86/mpx-mini-test.c
@@ -315,11 +315,39 @@ static inline void *__si_bounds_upper(siginfo_t *si)
         return si->si_upper;
 }
 #else
+
+/*
+ * This deals with old version of _sigfault in some distros:
+ *
+
+old _sigfault:
+        struct {
+            void *si_addr;
+        } _sigfault;
+
+new _sigfault:
+        struct {
+                void __user *_addr;
+                int _trapno;
+                short _addr_lsb;
+                union {
+                        struct {
+                                void __user *_lower;
+                                void __user *_upper;
+                        } _addr_bnd;
+                        __u32 _pkey;
+                };
+        } _sigfault;
+ *
+ */
+
 static inline void **__si_bounds_hack(siginfo_t *si)
 {
         void *sigfault = &si->_sifields._sigfault;
         void *end_sigfault = sigfault + sizeof(si->_sifields._sigfault);
-        void **__si_lower = end_sigfault;
+        int *trapno = (int*)end_sigfault;
+        /* skip _trapno and _addr_lsb */
+        void **__si_lower = (void**)(trapno + 2);
 
         return __si_lower;
 }
@@ -331,7 +359,7 @@ static inline void *__si_bounds_lower(siginfo_t *si)
 
 static inline void *__si_bounds_upper(siginfo_t *si)
 {
-        return (*__si_bounds_hack(si)) + sizeof(void *);
+        return *(__si_bounds_hack(si) + 1);
 }
 #endif
 
diff --git a/tools/testing/selftests/x86/protection_keys.c b/tools/testing/selftests/x86/protection_keys.c
index bc1b0735bb50..f15aa5a76fe3 100644
--- a/tools/testing/selftests/x86/protection_keys.c
+++ b/tools/testing/selftests/x86/protection_keys.c
@@ -393,34 +393,6 @@ pid_t fork_lazy_child(void)
         return forkret;
 }
 
-void davecmp(void *_a, void *_b, int len)
-{
-        int i;
-        unsigned long *a = _a;
-        unsigned long *b = _b;
-
-        for (i = 0; i < len / sizeof(*a); i++) {
-                if (a[i] == b[i])
-                        continue;
-
-                dprintf3("[%3d]: a: %016lx b: %016lx\n", i, a[i], b[i]);
-        }
-}
-
-void dumpit(char *f)
-{
-        int fd = open(f, O_RDONLY);
-        char buf[100];
-        int nr_read;
-
-        dprintf2("maps fd: %d\n", fd);
-        do {
-                nr_read = read(fd, &buf[0], sizeof(buf));
-                write(1, buf, nr_read);
-        } while (nr_read > 0);
-        close(fd);
-}
-
 #define PKEY_DISABLE_ACCESS    0x1
 #define PKEY_DISABLE_WRITE     0x2
 
diff --git a/tools/testing/selftests/x86/single_step_syscall.c b/tools/testing/selftests/x86/single_step_syscall.c
index a48da95c18fd..ddfdd635de16 100644
--- a/tools/testing/selftests/x86/single_step_syscall.c
+++ b/tools/testing/selftests/x86/single_step_syscall.c
@@ -119,7 +119,9 @@ static void check_result(void)
 
 int main()
 {
+#ifdef CAN_BUILD_32
         int tmp;
+#endif
 
         sethandler(SIGTRAP, sigtrap, 0);
 
@@ -139,12 +141,13 @@ int main()
                       : : "c" (post_nop) : "r11");
         check_result();
 #endif
-
+#ifdef CAN_BUILD_32
         printf("[RUN]\tSet TF and check int80\n");
         set_eflags(get_eflags() | X86_EFLAGS_TF);
         asm volatile ("int $0x80" : "=a" (tmp) : "a" (SYS_getpid)
                         : INT80_CLOBBERS);
         check_result();
+#endif
 
         /*
          * This test is particularly interesting if fast syscalls use
diff --git a/tools/testing/selftests/x86/test_mremap_vdso.c b/tools/testing/selftests/x86/test_mremap_vdso.c
index bf0d687c7db7..64f11c8d9b76 100644
--- a/tools/testing/selftests/x86/test_mremap_vdso.c
+++ b/tools/testing/selftests/x86/test_mremap_vdso.c
@@ -90,8 +90,12 @@ int main(int argc, char **argv, char **envp)
                         vdso_size += PAGE_SIZE;
                 }
 
+#ifdef __i386__
                 /* Glibc is likely to explode now - exit with raw syscall */
                 asm volatile ("int $0x80" : : "a" (__NR_exit), "b" (!!ret));
+#else /* __x86_64__ */
+                syscall(SYS_exit, ret);
+#endif
         } else {
                 int status;
 
diff --git a/tools/testing/selftests/x86/test_vdso.c b/tools/testing/selftests/x86/test_vdso.c
index 29973cde06d3..235259011704 100644
--- a/tools/testing/selftests/x86/test_vdso.c
+++ b/tools/testing/selftests/x86/test_vdso.c
@@ -26,20 +26,59 @@
 # endif
 #endif
 
+/* max length of lines in /proc/self/maps - anything longer is skipped here */
+#define MAPS_LINE_LEN 128
+
 int nerrs = 0;
 
+typedef long (*getcpu_t)(unsigned *, unsigned *, void *);
+
+getcpu_t vgetcpu;
+getcpu_t vdso_getcpu;
+
+static void *vsyscall_getcpu(void)
+{
 #ifdef __x86_64__
-# define VSYS(x) (x)
+        FILE *maps;
+        char line[MAPS_LINE_LEN];
+        bool found = false;
+
+        maps = fopen("/proc/self/maps", "r");
+        if (!maps) /* might still be present, but ignore it here, as we test vDSO not vsyscall */
+                return NULL;
+
+        while (fgets(line, MAPS_LINE_LEN, maps)) {
+                char r, x;
+                void *start, *end;
+                char name[MAPS_LINE_LEN];
+
+                /* sscanf() is safe here as strlen(name) >= strlen(line) */
+                if (sscanf(line, "%p-%p %c-%cp %*x %*x:%*x %*u %s",
+                           &start, &end, &r, &x, name) != 5)
+                        continue;
+
+                if (strcmp(name, "[vsyscall]"))
+                        continue;
+
+                /* assume entries are OK, as we test vDSO here not vsyscall */
+                found = true;
+                break;
+        }
+
+        fclose(maps);
+
+        if (!found) {
+                printf("Warning: failed to find vsyscall getcpu\n");
+                return NULL;
+        }
+        return (void *) (0xffffffffff600800);
 #else
-# define VSYS(x) 0
+        return NULL;
 #endif
+}
 
-typedef long (*getcpu_t)(unsigned *, unsigned *, void *);
-
-const getcpu_t vgetcpu = (getcpu_t)VSYS(0xffffffffff600800);
-getcpu_t vdso_getcpu;
 
-void fill_function_pointers()
+static void fill_function_pointers()
 {
         void *vdso = dlopen("linux-vdso.so.1",
                             RTLD_LAZY | RTLD_LOCAL | RTLD_NOLOAD);
@@ -54,6 +93,8 @@ void fill_function_pointers()
         vdso_getcpu = (getcpu_t)dlsym(vdso, "__vdso_getcpu");
         if (!vdso_getcpu)
                 printf("Warning: failed to find getcpu in vDSO\n");
+
+        vgetcpu = (getcpu_t) vsyscall_getcpu();
 }
 
 static long sys_getcpu(unsigned * cpu, unsigned * node,
diff --git a/tools/testing/selftests/x86/test_vsyscall.c b/tools/testing/selftests/x86/test_vsyscall.c
index 7a744fa7b786..be81621446f0 100644
--- a/tools/testing/selftests/x86/test_vsyscall.c
+++ b/tools/testing/selftests/x86/test_vsyscall.c
@@ -33,6 +33,9 @@
 # endif
 #endif
 
+/* max length of lines in /proc/self/maps - anything longer is skipped here */
+#define MAPS_LINE_LEN 128
+
 static void sethandler(int sig, void (*handler)(int, siginfo_t *, void *),
                        int flags)
 {
@@ -98,7 +101,7 @@ static int init_vsys(void)
 #ifdef __x86_64__
         int nerrs = 0;
         FILE *maps;
-        char line[128];
+        char line[MAPS_LINE_LEN];
         bool found = false;
 
         maps = fopen("/proc/self/maps", "r");
@@ -108,10 +111,12 @@ static int init_vsys(void)
                 return 0;
         }
 
-        while (fgets(line, sizeof(line), maps)) {
+        while (fgets(line, MAPS_LINE_LEN, maps)) {
                 char r, x;
                 void *start, *end;
-                char name[128];
+                char name[MAPS_LINE_LEN];
+
+                /* sscanf() is safe here as strlen(name) >= strlen(line) */
                 if (sscanf(line, "%p-%p %c-%cp %*x %*x:%*x %*u %s",
                            &start, &end, &r, &x, name) != 5)
                         continue;
diff --git a/tools/usb/Makefile b/tools/usb/Makefile
index 4e6506078494..01d758d73b6d 100644
--- a/tools/usb/Makefile
+++ b/tools/usb/Makefile
@@ -1,7 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 # Makefile for USB tools
 
-CC = $(CROSS_COMPILE)gcc
 PTHREAD_LIBS = -lpthread
 WARNINGS = -Wall -Wextra
 CFLAGS = $(WARNINGS) -g -I../include
diff --git a/tools/vm/Makefile b/tools/vm/Makefile
index be320b905ea7..20f6cf04377f 100644
--- a/tools/vm/Makefile
+++ b/tools/vm/Makefile
@@ -6,7 +6,6 @@ TARGETS=page-types slabinfo page_owner_sort
 LIB_DIR = ../lib/api
 LIBS = $(LIB_DIR)/libapi.a
 
-CC = $(CROSS_COMPILE)gcc
 CFLAGS = -Wall -Wextra -I../lib/
 LDFLAGS = $(LIBS)
 
diff --git a/tools/wmi/Makefile b/tools/wmi/Makefile
index e664f1167388..e0e87239126b 100644
--- a/tools/wmi/Makefile
+++ b/tools/wmi/Makefile
@@ -2,7 +2,6 @@ PREFIX ?= /usr
 SBINDIR ?= sbin
 INSTALL ?= install
 CFLAGS += -D__EXPORTED_HEADERS__ -I../../include/uapi -I../../include
-CC = $(CROSS_COMPILE)gcc
 
 TARGET = dell-smbios-example
 
diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c
index 70268c0bec79..70f4c30918eb 100644
--- a/virt/kvm/arm/arch_timer.c
+++ b/virt/kvm/arm/arch_timer.c
@@ -36,6 +36,8 @@ static struct timecounter *timecounter;
 static unsigned int host_vtimer_irq;
 static u32 host_vtimer_irq_flags;
 
+static DEFINE_STATIC_KEY_FALSE(has_gic_active_state);
+
 static const struct kvm_irq_level default_ptimer_irq = {
         .irq    = 30,
         .level  = 1,
@@ -56,6 +58,12 @@ u64 kvm_phys_timer_read(void)
         return timecounter->cc->read(timecounter->cc);
 }
 
+static inline bool userspace_irqchip(struct kvm *kvm)
+{
+        return static_branch_unlikely(&userspace_irqchip_in_use) &&
+                unlikely(!irqchip_in_kernel(kvm));
+}
+
 static void soft_timer_start(struct hrtimer *hrt, u64 ns)
 {
         hrtimer_start(hrt, ktime_add_ns(ktime_get(), ns),
@@ -69,25 +77,6 @@ static void soft_timer_cancel(struct hrtimer *hrt, struct work_struct *work)
                 cancel_work_sync(work);
 }
 
-static void kvm_vtimer_update_mask_user(struct kvm_vcpu *vcpu)
-{
-        struct arch_timer_context *vtimer = vcpu_vtimer(vcpu);
-
-        /*
-         * When using a userspace irqchip with the architected timers, we must
-         * prevent continuously exiting from the guest, and therefore mask the
-         * physical interrupt by disabling it on the host interrupt controller
-         * when the virtual level is high, such that the guest can make
-         * forward progress.  Once we detect the output level being
-         * de-asserted, we unmask the interrupt again so that we exit from the
-         * guest when the timer fires.
-         */
-        if (vtimer->irq.level)
-                disable_percpu_irq(host_vtimer_irq);
-        else
-                enable_percpu_irq(host_vtimer_irq, 0);
-}
-
 static irqreturn_t kvm_arch_timer_handler(int irq, void *dev_id)
 {
         struct kvm_vcpu *vcpu = *(struct kvm_vcpu **)dev_id;
@@ -106,9 +95,9 @@ static irqreturn_t kvm_arch_timer_handler(int irq, void *dev_id)
         if (kvm_timer_should_fire(vtimer))
                 kvm_timer_update_irq(vcpu, true, vtimer);
 
-        if (static_branch_unlikely(&userspace_irqchip_in_use) &&
-            unlikely(!irqchip_in_kernel(vcpu->kvm)))
-                kvm_vtimer_update_mask_user(vcpu);
+        if (userspace_irqchip(vcpu->kvm) &&
+            !static_branch_unlikely(&has_gic_active_state))
+                disable_percpu_irq(host_vtimer_irq);
 
         return IRQ_HANDLED;
 }
@@ -290,8 +279,7 @@ static void kvm_timer_update_irq(struct kvm_vcpu *vcpu, bool new_level,
         trace_kvm_timer_update_irq(vcpu->vcpu_id, timer_ctx->irq.irq,
                                    timer_ctx->irq.level);
 
-        if (!static_branch_unlikely(&userspace_irqchip_in_use) ||
-            likely(irqchip_in_kernel(vcpu->kvm))) {
+        if (!userspace_irqchip(vcpu->kvm)) {
                 ret = kvm_vgic_inject_irq(vcpu->kvm, vcpu->vcpu_id,
                                           timer_ctx->irq.irq,
                                           timer_ctx->irq.level,
@@ -350,12 +338,6 @@ static void kvm_timer_update_state(struct kvm_vcpu *vcpu)
         phys_timer_emulate(vcpu);
 }
 
-static void __timer_snapshot_state(struct arch_timer_context *timer)
-{
-        timer->cnt_ctl = read_sysreg_el0(cntv_ctl);
-        timer->cnt_cval = read_sysreg_el0(cntv_cval);
-}
-
 static void vtimer_save_state(struct kvm_vcpu *vcpu)
 {
         struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
@@ -367,8 +349,10 @@ static void vtimer_save_state(struct kvm_vcpu *vcpu)
         if (!vtimer->loaded)
                 goto out;
 
-        if (timer->enabled)
-                __timer_snapshot_state(vtimer);
+        if (timer->enabled) {
+                vtimer->cnt_ctl = read_sysreg_el0(cntv_ctl);
+                vtimer->cnt_cval = read_sysreg_el0(cntv_cval);
+        }
 
         /* Disable the virtual timer */
         write_sysreg_el0(0, cntv_ctl);
@@ -460,23 +444,43 @@ static void set_cntvoff(u64 cntvoff)
         kvm_call_hyp(__kvm_timer_set_cntvoff, low, high);
 }
 
-static void kvm_timer_vcpu_load_vgic(struct kvm_vcpu *vcpu)
+static inline void set_vtimer_irq_phys_active(struct kvm_vcpu *vcpu, bool active)
+{
+        int r;
+        r = irq_set_irqchip_state(host_vtimer_irq, IRQCHIP_STATE_ACTIVE, active);
+        WARN_ON(r);
+}
+
+static void kvm_timer_vcpu_load_gic(struct kvm_vcpu *vcpu)
 {
         struct arch_timer_context *vtimer = vcpu_vtimer(vcpu);
         bool phys_active;
-        int ret;
 
-        phys_active = kvm_vgic_map_is_active(vcpu, vtimer->irq.irq);
-
-        ret = irq_set_irqchip_state(host_vtimer_irq,
-                                    IRQCHIP_STATE_ACTIVE,
-                                    phys_active);
-        WARN_ON(ret);
+        if (irqchip_in_kernel(vcpu->kvm))
+                phys_active = kvm_vgic_map_is_active(vcpu, vtimer->irq.irq);
+        else
+                phys_active = vtimer->irq.level;
+        set_vtimer_irq_phys_active(vcpu, phys_active);
 }
 
-static void kvm_timer_vcpu_load_user(struct kvm_vcpu *vcpu)
+static void kvm_timer_vcpu_load_nogic(struct kvm_vcpu *vcpu)
 {
-        kvm_vtimer_update_mask_user(vcpu);
+        struct arch_timer_context *vtimer = vcpu_vtimer(vcpu);
+
+        /*
+         * When using a userspace irqchip with the architected timers and a
+         * host interrupt controller that doesn't support an active state, we
+         * must still prevent continuously exiting from the guest, and
+         * therefore mask the physical interrupt by disabling it on the host
+         * interrupt controller when the virtual level is high, such that the
+         * guest can make forward progress.  Once we detect the output level
+         * being de-asserted, we unmask the interrupt again so that we exit
+         * from the guest when the timer fires.
+         */
+        if (vtimer->irq.level)
+                disable_percpu_irq(host_vtimer_irq);
+        else
+                enable_percpu_irq(host_vtimer_irq, host_vtimer_irq_flags);
 }
 
 void kvm_timer_vcpu_load(struct kvm_vcpu *vcpu)
@@ -487,10 +491,10 @@ void kvm_timer_vcpu_load(struct kvm_vcpu *vcpu)
         if (unlikely(!timer->enabled))
                 return;
 
-        if (unlikely(!irqchip_in_kernel(vcpu->kvm)))
-                kvm_timer_vcpu_load_user(vcpu);
+        if (static_branch_likely(&has_gic_active_state))
+                kvm_timer_vcpu_load_gic(vcpu);
         else
-                kvm_timer_vcpu_load_vgic(vcpu);
+                kvm_timer_vcpu_load_nogic(vcpu);
 
         set_cntvoff(vtimer->cntvoff);
 
@@ -555,18 +559,24 @@ static void unmask_vtimer_irq_user(struct kvm_vcpu *vcpu)
 {
         struct arch_timer_context *vtimer = vcpu_vtimer(vcpu);
 
-        if (unlikely(!irqchip_in_kernel(vcpu->kvm))) {
-                __timer_snapshot_state(vtimer);
-                if (!kvm_timer_should_fire(vtimer)) {
-                        kvm_timer_update_irq(vcpu, false, vtimer);
-                        kvm_vtimer_update_mask_user(vcpu);
-                }
+        if (!kvm_timer_should_fire(vtimer)) {
+                kvm_timer_update_irq(vcpu, false, vtimer);
+                if (static_branch_likely(&has_gic_active_state))
+                        set_vtimer_irq_phys_active(vcpu, false);
+                else
+                        enable_percpu_irq(host_vtimer_irq, host_vtimer_irq_flags);
         }
 }
 
 void kvm_timer_sync_hwstate(struct kvm_vcpu *vcpu)
 {
-        unmask_vtimer_irq_user(vcpu);
+        struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
+
+        if (unlikely(!timer->enabled))
+                return;
+
+        if (unlikely(!irqchip_in_kernel(vcpu->kvm)))
+                unmask_vtimer_irq_user(vcpu);
 }
 
 int kvm_timer_vcpu_reset(struct kvm_vcpu *vcpu)
@@ -753,6 +763,8 @@ int kvm_timer_hyp_init(bool has_gic)
                         kvm_err("kvm_arch_timer: error setting vcpu affinity\n");
                         goto out_free_irq;
                 }
+
+                static_branch_enable(&has_gic_active_state);
         }
 
         kvm_info("virtual timer IRQ%d\n", host_vtimer_irq);
diff --git a/virt/kvm/kvm_main.c b/virt/kvm/kvm_main.c
index 4501e658e8d6..65dea3ffef68 100644
--- a/virt/kvm/kvm_main.c
+++ b/virt/kvm/kvm_main.c
@@ -969,8 +969,7 @@ int __kvm_set_memory_region(struct kvm *kvm,
                 /* Check for overlaps */
                 r = -EEXIST;
                 kvm_for_each_memslot(slot, __kvm_memslots(kvm, as_id)) {
-                        if ((slot->id >= KVM_USER_MEM_SLOTS) ||
-                            (slot->id == id))
+                        if (slot->id == id)
                                 continue;
                         if (!((base_gfn + npages <= slot->base_gfn) ||
                               (base_gfn >= slot->base_gfn + slot->npages)))