1 files changed, 14 insertions, 0 deletions

diff --git a/drivers/clocksource/arc_timer.c b/drivers/clocksource/arc_timer.c
index 471b428d8034..20da9b1d7f7d 100644
--- a/drivers/clocksource/arc_timer.c
+++ b/drivers/clocksource/arc_timer.c
@@ -61,6 +61,20 @@ static u64 arc_read_gfrc(struct clocksource *cs)
         unsigned long flags;
         u32 l, h;
 
+        /*
+         * From a programming model pov, there seems to be just one instance of
+         * MCIP_CMD/MCIP_READBACK however micro-architecturally there's
+         * an instance PER ARC CORE (not per cluster), and there are dedicated
+         * hardware decode logic (per core) inside ARConnect to handle
+         * simultaneous read/write accesses from cores via those two registers.
+         * So several concurrent commands to ARConnect are OK if they are
+         * trying to access two different sub-components (like GFRC,
+         * inter-core interrupt, etc...). HW also supports simultaneously
+         * accessing GFRC by multiple cores.
+         * That's why it is safe to disable hard interrupts on the local CPU
+         * before access to GFRC instead of taking global MCIP spinlock
+         * defined in arch/arc/kernel/mcip.c
+         */
         local_irq_save(flags);
 
         __mcip_cmd(CMD_GFRC_READ_LO, 0);