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-rw-r--r--drivers/net/ethernet/aquantia/atlantic/Makefile1
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_cfg.h8
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_common.h38
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_hw.h46
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c5
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.h3
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_main.c14
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_nic.c263
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_nic.h29
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_pci_func.c418
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/aq_pci_func.h23
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c137
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.h18
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0_internal.h34
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c163
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.h28
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0_internal.h33
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c268
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h73
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c184
-rw-r--r--drivers/net/ethernet/aquantia/atlantic/ver.h6
21 files changed, 1019 insertions, 773 deletions
diff --git a/drivers/net/ethernet/aquantia/atlantic/Makefile b/drivers/net/ethernet/aquantia/atlantic/Makefile
index e4ae696920ef..686f6d8c9e79 100644
--- a/drivers/net/ethernet/aquantia/atlantic/Makefile
+++ b/drivers/net/ethernet/aquantia/atlantic/Makefile
@@ -39,4 +39,5 @@ atlantic-objs := aq_main.o \
39 hw_atl/hw_atl_a0.o \ 39 hw_atl/hw_atl_a0.o \
40 hw_atl/hw_atl_b0.o \ 40 hw_atl/hw_atl_b0.o \
41 hw_atl/hw_atl_utils.o \ 41 hw_atl/hw_atl_utils.o \
42 hw_atl/hw_atl_utils_fw2x.o \
42 hw_atl/hw_atl_llh.o 43 hw_atl/hw_atl_llh.o
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_cfg.h b/drivers/net/ethernet/aquantia/atlantic/aq_cfg.h
index 105fdb958cef..0b49f1aeebd3 100644
--- a/drivers/net/ethernet/aquantia/atlantic/aq_cfg.h
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_cfg.h
@@ -65,7 +65,13 @@
65 65
66/*#define AQ_CFG_MAC_ADDR_PERMANENT {0x30, 0x0E, 0xE3, 0x12, 0x34, 0x56}*/ 66/*#define AQ_CFG_MAC_ADDR_PERMANENT {0x30, 0x0E, 0xE3, 0x12, 0x34, 0x56}*/
67 67
68#define AQ_CFG_FC_MODE 3U 68#define AQ_NIC_FC_OFF 0U
69#define AQ_NIC_FC_TX 1U
70#define AQ_NIC_FC_RX 2U
71#define AQ_NIC_FC_FULL 3U
72#define AQ_NIC_FC_AUTO 4U
73
74#define AQ_CFG_FC_MODE AQ_NIC_FC_FULL
69 75
70#define AQ_CFG_SPEED_MSK 0xFFFFU /* 0xFFFFU==auto_neg */ 76#define AQ_CFG_SPEED_MSK 0xFFFFU /* 0xFFFFU==auto_neg */
71 77
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_common.h b/drivers/net/ethernet/aquantia/atlantic/aq_common.h
index f79da4b5900b..d52b088ff8f0 100644
--- a/drivers/net/ethernet/aquantia/atlantic/aq_common.h
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_common.h
@@ -19,4 +19,42 @@
19#include "aq_cfg.h" 19#include "aq_cfg.h"
20#include "aq_utils.h" 20#include "aq_utils.h"
21 21
22#define PCI_VENDOR_ID_AQUANTIA 0x1D6A
23
24#define AQ_DEVICE_ID_0001 0x0001
25#define AQ_DEVICE_ID_D100 0xD100
26#define AQ_DEVICE_ID_D107 0xD107
27#define AQ_DEVICE_ID_D108 0xD108
28#define AQ_DEVICE_ID_D109 0xD109
29
30#define AQ_DEVICE_ID_AQC100 0x00B1
31#define AQ_DEVICE_ID_AQC107 0x07B1
32#define AQ_DEVICE_ID_AQC108 0x08B1
33#define AQ_DEVICE_ID_AQC109 0x09B1
34#define AQ_DEVICE_ID_AQC111 0x11B1
35#define AQ_DEVICE_ID_AQC112 0x12B1
36
37#define AQ_DEVICE_ID_AQC100S 0x80B1
38#define AQ_DEVICE_ID_AQC107S 0x87B1
39#define AQ_DEVICE_ID_AQC108S 0x88B1
40#define AQ_DEVICE_ID_AQC109S 0x89B1
41#define AQ_DEVICE_ID_AQC111S 0x91B1
42#define AQ_DEVICE_ID_AQC112S 0x92B1
43
44#define AQ_DEVICE_ID_AQC111E 0x51B1
45#define AQ_DEVICE_ID_AQC112E 0x52B1
46
47#define HW_ATL_NIC_NAME "aQuantia AQtion 10Gbit Network Adapter"
48
49#define AQ_HWREV_ANY 0
50#define AQ_HWREV_1 1
51#define AQ_HWREV_2 2
52
53#define AQ_NIC_RATE_10G BIT(0)
54#define AQ_NIC_RATE_5G BIT(1)
55#define AQ_NIC_RATE_5GSR BIT(2)
56#define AQ_NIC_RATE_2GS BIT(3)
57#define AQ_NIC_RATE_1G BIT(4)
58#define AQ_NIC_RATE_100M BIT(5)
59
22#endif /* AQ_COMMON_H */ 60#endif /* AQ_COMMON_H */
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_hw.h b/drivers/net/ethernet/aquantia/atlantic/aq_hw.h
index 5d67f1335f4d..a2d416b24ffc 100644
--- a/drivers/net/ethernet/aquantia/atlantic/aq_hw.h
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_hw.h
@@ -23,6 +23,7 @@ struct aq_hw_caps_s {
23 u64 hw_features; 23 u64 hw_features;
24 u64 link_speed_msk; 24 u64 link_speed_msk;
25 unsigned int hw_priv_flags; 25 unsigned int hw_priv_flags;
26 u32 media_type;
26 u32 rxds; 27 u32 rxds;
27 u32 txds; 28 u32 txds;
28 u32 txhwb_alignment; 29 u32 txhwb_alignment;
@@ -30,7 +31,7 @@ struct aq_hw_caps_s {
30 u32 vecs; 31 u32 vecs;
31 u32 mtu; 32 u32 mtu;
32 u32 mac_regs_count; 33 u32 mac_regs_count;
33 u8 ports; 34 u32 hw_alive_check_addr;
34 u8 msix_irqs; 35 u8 msix_irqs;
35 u8 tcs; 36 u8 tcs;
36 u8 rxd_alignment; 37 u8 rxd_alignment;
@@ -41,7 +42,6 @@ struct aq_hw_caps_s {
41 u8 rx_rings; 42 u8 rx_rings;
42 bool flow_control; 43 bool flow_control;
43 bool is_64_dma; 44 bool is_64_dma;
44 u32 fw_ver_expected;
45}; 45};
46 46
47struct aq_hw_link_status_s { 47struct aq_hw_link_status_s {
@@ -95,12 +95,15 @@ struct aq_stats_s {
95#define AQ_NIC_FLAGS_IS_NOT_TX_READY (AQ_NIC_FLAGS_IS_NOT_READY | \ 95#define AQ_NIC_FLAGS_IS_NOT_TX_READY (AQ_NIC_FLAGS_IS_NOT_READY | \
96 AQ_NIC_LINK_DOWN) 96 AQ_NIC_LINK_DOWN)
97 97
98#define AQ_HW_MEDIA_TYPE_TP 1U
99#define AQ_HW_MEDIA_TYPE_FIBRE 2U
100
98struct aq_hw_s { 101struct aq_hw_s {
99 atomic_t flags; 102 atomic_t flags;
103 u8 rbl_enabled:1;
100 struct aq_nic_cfg_s *aq_nic_cfg; 104 struct aq_nic_cfg_s *aq_nic_cfg;
101 struct aq_pci_func_s *aq_pci_func; 105 const struct aq_fw_ops *aq_fw_ops;
102 void __iomem *mmio; 106 void __iomem *mmio;
103 unsigned int not_ff_addr;
104 struct aq_hw_link_status_s aq_link_status; 107 struct aq_hw_link_status_s aq_link_status;
105 struct hw_aq_atl_utils_mbox mbox; 108 struct hw_aq_atl_utils_mbox mbox;
106 struct hw_atl_stats_s last_stats; 109 struct hw_atl_stats_s last_stats;
@@ -119,19 +122,9 @@ struct aq_hw_s {
119 122
120struct aq_ring_s; 123struct aq_ring_s;
121struct aq_ring_param_s; 124struct aq_ring_param_s;
122struct aq_nic_cfg_s;
123struct sk_buff; 125struct sk_buff;
124 126
125struct aq_hw_ops { 127struct aq_hw_ops {
126 struct aq_hw_s *(*create)(struct aq_pci_func_s *aq_pci_func,
127 unsigned int port);
128
129 void (*destroy)(struct aq_hw_s *self);
130
131 int (*get_hw_caps)(struct aq_hw_s *self,
132 struct aq_hw_caps_s *aq_hw_caps,
133 unsigned short device,
134 unsigned short subsystem_device);
135 128
136 int (*hw_ring_tx_xmit)(struct aq_hw_s *self, struct aq_ring_s *aq_ring, 129 int (*hw_ring_tx_xmit)(struct aq_hw_s *self, struct aq_ring_s *aq_ring,
137 unsigned int frags); 130 unsigned int frags);
@@ -145,15 +138,8 @@ struct aq_hw_ops {
145 int (*hw_ring_tx_head_update)(struct aq_hw_s *self, 138 int (*hw_ring_tx_head_update)(struct aq_hw_s *self,
146 struct aq_ring_s *aq_ring); 139 struct aq_ring_s *aq_ring);
147 140
148 int (*hw_get_mac_permanent)(struct aq_hw_s *self,
149 u8 *mac);
150
151 int (*hw_set_mac_address)(struct aq_hw_s *self, u8 *mac_addr); 141 int (*hw_set_mac_address)(struct aq_hw_s *self, u8 *mac_addr);
152 142
153 int (*hw_get_link_status)(struct aq_hw_s *self);
154
155 int (*hw_set_link_speed)(struct aq_hw_s *self, u32 speed);
156
157 int (*hw_reset)(struct aq_hw_s *self); 143 int (*hw_reset)(struct aq_hw_s *self);
158 144
159 int (*hw_init)(struct aq_hw_s *self, u8 *mac_addr); 145 int (*hw_init)(struct aq_hw_s *self, u8 *mac_addr);
@@ -207,8 +193,6 @@ struct aq_hw_ops {
207 const struct aq_hw_caps_s *aq_hw_caps, 193 const struct aq_hw_caps_s *aq_hw_caps,
208 u32 *regs_buff); 194 u32 *regs_buff);
209 195
210 int (*hw_update_stats)(struct aq_hw_s *self);
211
212 struct aq_stats_s *(*hw_get_hw_stats)(struct aq_hw_s *self); 196 struct aq_stats_s *(*hw_get_hw_stats)(struct aq_hw_s *self);
213 197
214 int (*hw_get_fw_version)(struct aq_hw_s *self, u32 *fw_version); 198 int (*hw_get_fw_version)(struct aq_hw_s *self, u32 *fw_version);
@@ -218,4 +202,20 @@ struct aq_hw_ops {
218 int (*hw_set_power)(struct aq_hw_s *self, unsigned int power_state); 202 int (*hw_set_power)(struct aq_hw_s *self, unsigned int power_state);
219}; 203};
220 204
205struct aq_fw_ops {
206 int (*init)(struct aq_hw_s *self);
207
208 int (*reset)(struct aq_hw_s *self);
209
210 int (*get_mac_permanent)(struct aq_hw_s *self, u8 *mac);
211
212 int (*set_link_speed)(struct aq_hw_s *self, u32 speed);
213
214 int (*set_state)(struct aq_hw_s *self, enum hal_atl_utils_fw_state_e state);
215
216 int (*update_link_status)(struct aq_hw_s *self);
217
218 int (*update_stats)(struct aq_hw_s *self);
219};
220
221#endif /* AQ_HW_H */ 221#endif /* AQ_HW_H */
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c b/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c
index 27e250d61da7..d526c4f19d34 100644
--- a/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.c
@@ -13,6 +13,7 @@
13 13
14#include "aq_hw_utils.h" 14#include "aq_hw_utils.h"
15#include "aq_hw.h" 15#include "aq_hw.h"
16#include "aq_nic.h"
16 17
17void aq_hw_write_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk, 18void aq_hw_write_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk,
18 u32 shift, u32 val) 19 u32 shift, u32 val)
@@ -39,7 +40,9 @@ u32 aq_hw_read_reg(struct aq_hw_s *hw, u32 reg)
39{ 40{
40 u32 value = readl(hw->mmio + reg); 41 u32 value = readl(hw->mmio + reg);
41 42
42 if ((~0U) == value && (~0U) == readl(hw->mmio + hw->not_ff_addr)) 43 if ((~0U) == value &&
44 (~0U) == readl(hw->mmio +
45 hw->aq_nic_cfg->aq_hw_caps->hw_alive_check_addr))
43 aq_utils_obj_set(&hw->flags, AQ_HW_FLAG_ERR_UNPLUG); 46 aq_utils_obj_set(&hw->flags, AQ_HW_FLAG_ERR_UNPLUG);
44 47
45 return value; 48 return value;
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.h b/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.h
index 03b72ddbffb9..dc88a1221f1d 100644
--- a/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.h
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.h
@@ -35,6 +35,9 @@ do { \
35 } \ 35 } \
36} while (0) 36} while (0)
37 37
38#define aq_pr_err(...) pr_err(AQ_CFG_DRV_NAME ": " __VA_ARGS__)
39#define aq_pr_trace(...) pr_info(AQ_CFG_DRV_NAME ": " __VA_ARGS__)
40
38struct aq_hw_s; 41struct aq_hw_s;
39 42
40void aq_hw_write_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk, 43void aq_hw_write_reg_bit(struct aq_hw_s *aq_hw, u32 addr, u32 msk,
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_main.c b/drivers/net/ethernet/aquantia/atlantic/aq_main.c
index 887bc846375a..ba5fe8c4125d 100644
--- a/drivers/net/ethernet/aquantia/atlantic/aq_main.c
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_main.c
@@ -43,14 +43,9 @@ struct net_device *aq_ndev_alloc(void)
43 43
44static int aq_ndev_open(struct net_device *ndev) 44static int aq_ndev_open(struct net_device *ndev)
45{ 45{
46 struct aq_nic_s *aq_nic = NULL;
47 int err = 0; 46 int err = 0;
47 struct aq_nic_s *aq_nic = netdev_priv(ndev);
48 48
49 aq_nic = aq_nic_alloc_hot(ndev);
50 if (!aq_nic) {
51 err = -ENOMEM;
52 goto err_exit;
53 }
54 err = aq_nic_init(aq_nic); 49 err = aq_nic_init(aq_nic);
55 if (err < 0) 50 if (err < 0)
56 goto err_exit; 51 goto err_exit;
@@ -73,7 +68,6 @@ static int aq_ndev_close(struct net_device *ndev)
73 if (err < 0) 68 if (err < 0)
74 goto err_exit; 69 goto err_exit;
75 aq_nic_deinit(aq_nic); 70 aq_nic_deinit(aq_nic);
76 aq_nic_free_hot_resources(aq_nic);
77 71
78err_exit: 72err_exit:
79 return err; 73 return err;
@@ -145,15 +139,13 @@ static void aq_ndev_set_multicast_settings(struct net_device *ndev)
145 139
146 err = aq_nic_set_packet_filter(aq_nic, ndev->flags); 140 err = aq_nic_set_packet_filter(aq_nic, ndev->flags);
147 if (err < 0) 141 if (err < 0)
148 goto err_exit; 142 return;
149 143
150 if (netdev_mc_count(ndev)) { 144 if (netdev_mc_count(ndev)) {
151 err = aq_nic_set_multicast_list(aq_nic, ndev); 145 err = aq_nic_set_multicast_list(aq_nic, ndev);
152 if (err < 0) 146 if (err < 0)
153 goto err_exit; 147 return;
154 } 148 }
155
156err_exit:;
157} 149}
158 150
159static const struct net_device_ops aq_ndev_ops = { 151static const struct net_device_ops aq_ndev_ops = {
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_nic.c b/drivers/net/ethernet/aquantia/atlantic/aq_nic.c
index d98251371ee4..ebbaf63eaf47 100644
--- a/drivers/net/ethernet/aquantia/atlantic/aq_nic.c
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_nic.c
@@ -14,7 +14,6 @@
14#include "aq_vec.h" 14#include "aq_vec.h"
15#include "aq_hw.h" 15#include "aq_hw.h"
16#include "aq_pci_func.h" 16#include "aq_pci_func.h"
17#include "aq_main.h"
18 17
19#include <linux/moduleparam.h> 18#include <linux/moduleparam.h>
20#include <linux/netdevice.h> 19#include <linux/netdevice.h>
@@ -61,19 +60,13 @@ static void aq_nic_rss_init(struct aq_nic_s *self, unsigned int num_rss_queues)
61 rss_params->indirection_table[i] = i & (num_rss_queues - 1); 60 rss_params->indirection_table[i] = i & (num_rss_queues - 1);
62} 61}
63 62
64/* Fills aq_nic_cfg with valid defaults */ 63/* Checks hw_caps and 'corrects' aq_nic_cfg in runtime */
65static void aq_nic_cfg_init_defaults(struct aq_nic_s *self) 64void aq_nic_cfg_start(struct aq_nic_s *self)
66{ 65{
67 struct aq_nic_cfg_s *cfg = &self->aq_nic_cfg; 66 struct aq_nic_cfg_s *cfg = &self->aq_nic_cfg;
68 67
69 cfg->aq_hw_caps = &self->aq_hw_caps;
70
71 cfg->vecs = AQ_CFG_VECS_DEF;
72 cfg->tcs = AQ_CFG_TCS_DEF; 68 cfg->tcs = AQ_CFG_TCS_DEF;
73 69
74 cfg->rxds = AQ_CFG_RXDS_DEF;
75 cfg->txds = AQ_CFG_TXDS_DEF;
76
77 cfg->is_polling = AQ_CFG_IS_POLLING_DEF; 70 cfg->is_polling = AQ_CFG_IS_POLLING_DEF;
78 71
79 cfg->itr = aq_itr; 72 cfg->itr = aq_itr;
@@ -94,19 +87,13 @@ static void aq_nic_cfg_init_defaults(struct aq_nic_s *self)
94 cfg->vlan_id = 0U; 87 cfg->vlan_id = 0U;
95 88
96 aq_nic_rss_init(self, cfg->num_rss_queues); 89 aq_nic_rss_init(self, cfg->num_rss_queues);
97}
98
99/* Checks hw_caps and 'corrects' aq_nic_cfg in runtime */
100int aq_nic_cfg_start(struct aq_nic_s *self)
101{
102 struct aq_nic_cfg_s *cfg = &self->aq_nic_cfg;
103 90
104 /*descriptors */ 91 /*descriptors */
105 cfg->rxds = min(cfg->rxds, cfg->aq_hw_caps->rxds); 92 cfg->rxds = min(cfg->aq_hw_caps->rxds, AQ_CFG_RXDS_DEF);
106 cfg->txds = min(cfg->txds, cfg->aq_hw_caps->txds); 93 cfg->txds = min(cfg->aq_hw_caps->txds, AQ_CFG_TXDS_DEF);
107 94
108 /*rss rings */ 95 /*rss rings */
109 cfg->vecs = min(cfg->vecs, cfg->aq_hw_caps->vecs); 96 cfg->vecs = min(cfg->aq_hw_caps->vecs, AQ_CFG_VECS_DEF);
110 cfg->vecs = min(cfg->vecs, num_online_cpus()); 97 cfg->vecs = min(cfg->vecs, num_online_cpus());
111 /* cfg->vecs should be power of 2 for RSS */ 98 /* cfg->vecs should be power of 2 for RSS */
112 if (cfg->vecs >= 8U) 99 if (cfg->vecs >= 8U)
@@ -120,23 +107,22 @@ int aq_nic_cfg_start(struct aq_nic_s *self)
120 107
121 cfg->num_rss_queues = min(cfg->vecs, AQ_CFG_NUM_RSS_QUEUES_DEF); 108 cfg->num_rss_queues = min(cfg->vecs, AQ_CFG_NUM_RSS_QUEUES_DEF);
122 109
123 cfg->irq_type = aq_pci_func_get_irq_type(self->aq_pci_func); 110 cfg->irq_type = aq_pci_func_get_irq_type(self);
124 111
125 if ((cfg->irq_type == AQ_HW_IRQ_LEGACY) || 112 if ((cfg->irq_type == AQ_HW_IRQ_LEGACY) ||
126 (self->aq_hw_caps.vecs == 1U) || 113 (cfg->aq_hw_caps->vecs == 1U) ||
127 (cfg->vecs == 1U)) { 114 (cfg->vecs == 1U)) {
128 cfg->is_rss = 0U; 115 cfg->is_rss = 0U;
129 cfg->vecs = 1U; 116 cfg->vecs = 1U;
130 } 117 }
131 118
132 cfg->link_speed_msk &= self->aq_hw_caps.link_speed_msk; 119 cfg->link_speed_msk &= cfg->aq_hw_caps->link_speed_msk;
133 cfg->hw_features = self->aq_hw_caps.hw_features; 120 cfg->hw_features = cfg->aq_hw_caps->hw_features;
134 return 0;
135} 121}
136 122
137static int aq_nic_update_link_status(struct aq_nic_s *self) 123static int aq_nic_update_link_status(struct aq_nic_s *self)
138{ 124{
139 int err = self->aq_hw_ops.hw_get_link_status(self->aq_hw); 125 int err = self->aq_fw_ops->update_link_status(self->aq_hw);
140 126
141 if (err) 127 if (err)
142 return err; 128 return err;
@@ -178,8 +164,8 @@ static void aq_nic_service_timer_cb(struct timer_list *t)
178 if (err) 164 if (err)
179 goto err_exit; 165 goto err_exit;
180 166
181 if (self->aq_hw_ops.hw_update_stats) 167 if (self->aq_fw_ops->update_stats)
182 self->aq_hw_ops.hw_update_stats(self->aq_hw); 168 self->aq_fw_ops->update_stats(self->aq_hw);
183 169
184 aq_nic_update_ndev_stats(self); 170 aq_nic_update_ndev_stats(self);
185 171
@@ -205,51 +191,6 @@ static void aq_nic_polling_timer_cb(struct timer_list *t)
205 AQ_CFG_POLLING_TIMER_INTERVAL); 191 AQ_CFG_POLLING_TIMER_INTERVAL);
206} 192}
207 193
208struct aq_nic_s *aq_nic_alloc_cold(struct pci_dev *pdev,
209 struct aq_pci_func_s *aq_pci_func,
210 unsigned int port,
211 const struct aq_hw_ops *aq_hw_ops)
212{
213 struct net_device *ndev = NULL;
214 struct aq_nic_s *self = NULL;
215 int err = 0;
216
217 ndev = aq_ndev_alloc();
218 if (!ndev) {
219 err = -ENOMEM;
220 goto err_exit;
221 }
222
223 self = netdev_priv(ndev);
224
225 SET_NETDEV_DEV(ndev, &pdev->dev);
226
227 ndev->if_port = port;
228 self->ndev = ndev;
229
230 self->aq_pci_func = aq_pci_func;
231
232 self->aq_hw_ops = *aq_hw_ops;
233 self->port = (u8)port;
234
235 self->aq_hw = self->aq_hw_ops.create(aq_pci_func, self->port);
236 self->aq_hw->aq_nic_cfg = &self->aq_nic_cfg;
237
238 err = self->aq_hw_ops.get_hw_caps(self->aq_hw, &self->aq_hw_caps,
239 pdev->device, pdev->subsystem_device);
240 if (err < 0)
241 goto err_exit;
242
243 aq_nic_cfg_init_defaults(self);
244
245err_exit:
246 if (err < 0) {
247 aq_nic_free_hot_resources(self);
248 self = NULL;
249 }
250 return self;
251}
252
253int aq_nic_ndev_register(struct aq_nic_s *self) 194int aq_nic_ndev_register(struct aq_nic_s *self)
254{ 195{
255 int err = 0; 196 int err = 0;
@@ -258,9 +199,14 @@ int aq_nic_ndev_register(struct aq_nic_s *self)
258 err = -EINVAL; 199 err = -EINVAL;
259 goto err_exit; 200 goto err_exit;
260 } 201 }
261 err = self->aq_hw_ops.hw_get_mac_permanent(self->aq_hw, 202
203 err = hw_atl_utils_initfw(self->aq_hw, &self->aq_fw_ops);
204 if (err)
205 goto err_exit;
206
207 err = self->aq_fw_ops->get_mac_permanent(self->aq_hw,
262 self->ndev->dev_addr); 208 self->ndev->dev_addr);
263 if (err < 0) 209 if (err)
264 goto err_exit; 210 goto err_exit;
265 211
266#if defined(AQ_CFG_MAC_ADDR_PERMANENT) 212#if defined(AQ_CFG_MAC_ADDR_PERMANENT)
@@ -271,19 +217,29 @@ int aq_nic_ndev_register(struct aq_nic_s *self)
271 } 217 }
272#endif 218#endif
273 219
220 for (self->aq_vecs = 0; self->aq_vecs < aq_nic_get_cfg(self)->vecs;
221 self->aq_vecs++) {
222 self->aq_vec[self->aq_vecs] =
223 aq_vec_alloc(self, self->aq_vecs, aq_nic_get_cfg(self));
224 if (!self->aq_vec[self->aq_vecs]) {
225 err = -ENOMEM;
226 goto err_exit;
227 }
228 }
229
274 netif_carrier_off(self->ndev); 230 netif_carrier_off(self->ndev);
275 231
276 netif_tx_disable(self->ndev); 232 netif_tx_disable(self->ndev);
277 233
278 err = register_netdev(self->ndev); 234 err = register_netdev(self->ndev);
279 if (err < 0) 235 if (err)
280 goto err_exit; 236 goto err_exit;
281 237
282err_exit: 238err_exit:
283 return err; 239 return err;
284} 240}
285 241
286int aq_nic_ndev_init(struct aq_nic_s *self) 242void aq_nic_ndev_init(struct aq_nic_s *self)
287{ 243{
288 const struct aq_hw_caps_s *aq_hw_caps = self->aq_nic_cfg.aq_hw_caps; 244 const struct aq_hw_caps_s *aq_hw_caps = self->aq_nic_cfg.aq_hw_caps;
289 struct aq_nic_cfg_s *aq_nic_cfg = &self->aq_nic_cfg; 245 struct aq_nic_cfg_s *aq_nic_cfg = &self->aq_nic_cfg;
@@ -292,62 +248,8 @@ int aq_nic_ndev_init(struct aq_nic_s *self)
292 self->ndev->features = aq_hw_caps->hw_features; 248 self->ndev->features = aq_hw_caps->hw_features;
293 self->ndev->priv_flags = aq_hw_caps->hw_priv_flags; 249 self->ndev->priv_flags = aq_hw_caps->hw_priv_flags;
294 self->ndev->mtu = aq_nic_cfg->mtu - ETH_HLEN; 250 self->ndev->mtu = aq_nic_cfg->mtu - ETH_HLEN;
295 self->ndev->max_mtu = self->aq_hw_caps.mtu - ETH_FCS_LEN - ETH_HLEN; 251 self->ndev->max_mtu = aq_hw_caps->mtu - ETH_FCS_LEN - ETH_HLEN;
296 252
297 return 0;
298}
299
300void aq_nic_ndev_free(struct aq_nic_s *self)
301{
302 if (!self->ndev)
303 goto err_exit;
304
305 if (self->ndev->reg_state == NETREG_REGISTERED)
306 unregister_netdev(self->ndev);
307
308 if (self->aq_hw)
309 self->aq_hw_ops.destroy(self->aq_hw);
310
311 free_netdev(self->ndev);
312
313err_exit:;
314}
315
316struct aq_nic_s *aq_nic_alloc_hot(struct net_device *ndev)
317{
318 struct aq_nic_s *self = NULL;
319 int err = 0;
320
321 if (!ndev) {
322 err = -EINVAL;
323 goto err_exit;
324 }
325 self = netdev_priv(ndev);
326
327 if (!self) {
328 err = -EINVAL;
329 goto err_exit;
330 }
331 if (netif_running(ndev))
332 netif_tx_disable(ndev);
333 netif_carrier_off(self->ndev);
334
335 for (self->aq_vecs = 0; self->aq_vecs < self->aq_nic_cfg.vecs;
336 self->aq_vecs++) {
337 self->aq_vec[self->aq_vecs] =
338 aq_vec_alloc(self, self->aq_vecs, &self->aq_nic_cfg);
339 if (!self->aq_vec[self->aq_vecs]) {
340 err = -ENOMEM;
341 goto err_exit;
342 }
343 }
344
345err_exit:
346 if (err < 0) {
347 aq_nic_free_hot_resources(self);
348 self = NULL;
349 }
350 return self;
351} 253}
352 254
353void aq_nic_set_tx_ring(struct aq_nic_s *self, unsigned int idx, 255void aq_nic_set_tx_ring(struct aq_nic_s *self, unsigned int idx,
@@ -368,18 +270,20 @@ int aq_nic_init(struct aq_nic_s *self)
368 unsigned int i = 0U; 270 unsigned int i = 0U;
369 271
370 self->power_state = AQ_HW_POWER_STATE_D0; 272 self->power_state = AQ_HW_POWER_STATE_D0;
371 err = self->aq_hw_ops.hw_reset(self->aq_hw); 273 err = self->aq_hw_ops->hw_reset(self->aq_hw);
372 if (err < 0) 274 if (err < 0)
373 goto err_exit; 275 goto err_exit;
374 276
375 err = self->aq_hw_ops.hw_init(self->aq_hw, 277 err = self->aq_hw_ops->hw_init(self->aq_hw,
376 aq_nic_get_ndev(self)->dev_addr); 278 aq_nic_get_ndev(self)->dev_addr);
377 if (err < 0) 279 if (err < 0)
378 goto err_exit; 280 goto err_exit;
379 281
380 for (i = 0U, aq_vec = self->aq_vec[0]; 282 for (i = 0U, aq_vec = self->aq_vec[0];
381 self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i]) 283 self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i])
382 aq_vec_init(aq_vec, &self->aq_hw_ops, self->aq_hw); 284 aq_vec_init(aq_vec, self->aq_hw_ops, self->aq_hw);
285
286 netif_carrier_off(self->ndev);
383 287
384err_exit: 288err_exit:
385 return err; 289 return err;
@@ -391,13 +295,13 @@ int aq_nic_start(struct aq_nic_s *self)
391 int err = 0; 295 int err = 0;
392 unsigned int i = 0U; 296 unsigned int i = 0U;
393 297
394 err = self->aq_hw_ops.hw_multicast_list_set(self->aq_hw, 298 err = self->aq_hw_ops->hw_multicast_list_set(self->aq_hw,
395 self->mc_list.ar, 299 self->mc_list.ar,
396 self->mc_list.count); 300 self->mc_list.count);
397 if (err < 0) 301 if (err < 0)
398 goto err_exit; 302 goto err_exit;
399 303
400 err = self->aq_hw_ops.hw_packet_filter_set(self->aq_hw, 304 err = self->aq_hw_ops->hw_packet_filter_set(self->aq_hw,
401 self->packet_filter); 305 self->packet_filter);
402 if (err < 0) 306 if (err < 0)
403 goto err_exit; 307 goto err_exit;
@@ -409,7 +313,7 @@ int aq_nic_start(struct aq_nic_s *self)
409 goto err_exit; 313 goto err_exit;
410 } 314 }
411 315
412 err = self->aq_hw_ops.hw_start(self->aq_hw); 316 err = self->aq_hw_ops->hw_start(self->aq_hw);
413 if (err < 0) 317 if (err < 0)
414 goto err_exit; 318 goto err_exit;
415 319
@@ -427,14 +331,14 @@ int aq_nic_start(struct aq_nic_s *self)
427 } else { 331 } else {
428 for (i = 0U, aq_vec = self->aq_vec[0]; 332 for (i = 0U, aq_vec = self->aq_vec[0];
429 self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i]) { 333 self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i]) {
430 err = aq_pci_func_alloc_irq(self->aq_pci_func, i, 334 err = aq_pci_func_alloc_irq(self, i,
431 self->ndev->name, aq_vec, 335 self->ndev->name, aq_vec,
432 aq_vec_get_affinity_mask(aq_vec)); 336 aq_vec_get_affinity_mask(aq_vec));
433 if (err < 0) 337 if (err < 0)
434 goto err_exit; 338 goto err_exit;
435 } 339 }
436 340
437 err = self->aq_hw_ops.hw_irq_enable(self->aq_hw, 341 err = self->aq_hw_ops->hw_irq_enable(self->aq_hw,
438 AQ_CFG_IRQ_MASK); 342 AQ_CFG_IRQ_MASK);
439 if (err < 0) 343 if (err < 0)
440 goto err_exit; 344 goto err_exit;
@@ -619,9 +523,8 @@ int aq_nic_xmit(struct aq_nic_s *self, struct sk_buff *skb)
619 frags = aq_nic_map_skb(self, skb, ring); 523 frags = aq_nic_map_skb(self, skb, ring);
620 524
621 if (likely(frags)) { 525 if (likely(frags)) {
622 err = self->aq_hw_ops.hw_ring_tx_xmit(self->aq_hw, 526 err = self->aq_hw_ops->hw_ring_tx_xmit(self->aq_hw,
623 ring, 527 ring, frags);
624 frags);
625 if (err >= 0) { 528 if (err >= 0) {
626 ++ring->stats.tx.packets; 529 ++ring->stats.tx.packets;
627 ring->stats.tx.bytes += skb->len; 530 ring->stats.tx.bytes += skb->len;
@@ -636,14 +539,14 @@ err_exit:
636 539
637int aq_nic_update_interrupt_moderation_settings(struct aq_nic_s *self) 540int aq_nic_update_interrupt_moderation_settings(struct aq_nic_s *self)
638{ 541{
639 return self->aq_hw_ops.hw_interrupt_moderation_set(self->aq_hw); 542 return self->aq_hw_ops->hw_interrupt_moderation_set(self->aq_hw);
640} 543}
641 544
642int aq_nic_set_packet_filter(struct aq_nic_s *self, unsigned int flags) 545int aq_nic_set_packet_filter(struct aq_nic_s *self, unsigned int flags)
643{ 546{
644 int err = 0; 547 int err = 0;
645 548
646 err = self->aq_hw_ops.hw_packet_filter_set(self->aq_hw, flags); 549 err = self->aq_hw_ops->hw_packet_filter_set(self->aq_hw, flags);
647 if (err < 0) 550 if (err < 0)
648 goto err_exit; 551 goto err_exit;
649 552
@@ -675,11 +578,11 @@ int aq_nic_set_multicast_list(struct aq_nic_s *self, struct net_device *ndev)
675 * multicast mask 578 * multicast mask
676 */ 579 */
677 self->packet_filter |= IFF_ALLMULTI; 580 self->packet_filter |= IFF_ALLMULTI;
678 self->aq_hw->aq_nic_cfg->mc_list_count = 0; 581 self->aq_nic_cfg.mc_list_count = 0;
679 return self->aq_hw_ops.hw_packet_filter_set(self->aq_hw, 582 return self->aq_hw_ops->hw_packet_filter_set(self->aq_hw,
680 self->packet_filter); 583 self->packet_filter);
681 } else { 584 } else {
682 return self->aq_hw_ops.hw_multicast_list_set(self->aq_hw, 585 return self->aq_hw_ops->hw_multicast_list_set(self->aq_hw,
683 self->mc_list.ar, 586 self->mc_list.ar,
684 self->mc_list.count); 587 self->mc_list.count);
685 } 588 }
@@ -694,7 +597,7 @@ int aq_nic_set_mtu(struct aq_nic_s *self, int new_mtu)
694 597
695int aq_nic_set_mac(struct aq_nic_s *self, struct net_device *ndev) 598int aq_nic_set_mac(struct aq_nic_s *self, struct net_device *ndev)
696{ 599{
697 return self->aq_hw_ops.hw_set_mac_address(self->aq_hw, ndev->dev_addr); 600 return self->aq_hw_ops->hw_set_mac_address(self->aq_hw, ndev->dev_addr);
698} 601}
699 602
700unsigned int aq_nic_get_link_speed(struct aq_nic_s *self) 603unsigned int aq_nic_get_link_speed(struct aq_nic_s *self)
@@ -709,8 +612,9 @@ int aq_nic_get_regs(struct aq_nic_s *self, struct ethtool_regs *regs, void *p)
709 612
710 regs->version = 1; 613 regs->version = 1;
711 614
712 err = self->aq_hw_ops.hw_get_regs(self->aq_hw, 615 err = self->aq_hw_ops->hw_get_regs(self->aq_hw,
713 &self->aq_hw_caps, regs_buff); 616 self->aq_nic_cfg.aq_hw_caps,
617 regs_buff);
714 if (err < 0) 618 if (err < 0)
715 goto err_exit; 619 goto err_exit;
716 620
@@ -720,7 +624,7 @@ err_exit:
720 624
721int aq_nic_get_regs_count(struct aq_nic_s *self) 625int aq_nic_get_regs_count(struct aq_nic_s *self)
722{ 626{
723 return self->aq_hw_caps.mac_regs_count; 627 return self->aq_nic_cfg.aq_hw_caps->mac_regs_count;
724} 628}
725 629
726void aq_nic_get_stats(struct aq_nic_s *self, u64 *data) 630void aq_nic_get_stats(struct aq_nic_s *self, u64 *data)
@@ -728,7 +632,7 @@ void aq_nic_get_stats(struct aq_nic_s *self, u64 *data)
728 unsigned int i = 0U; 632 unsigned int i = 0U;
729 unsigned int count = 0U; 633 unsigned int count = 0U;
730 struct aq_vec_s *aq_vec = NULL; 634 struct aq_vec_s *aq_vec = NULL;
731 struct aq_stats_s *stats = self->aq_hw_ops.hw_get_hw_stats(self->aq_hw); 635 struct aq_stats_s *stats = self->aq_hw_ops->hw_get_hw_stats(self->aq_hw);
732 636
733 if (!stats) 637 if (!stats)
734 goto err_exit; 638 goto err_exit;
@@ -759,7 +663,6 @@ void aq_nic_get_stats(struct aq_nic_s *self, u64 *data)
759 i++; 663 i++;
760 664
761 data += i; 665 data += i;
762 count = 0U;
763 666
764 for (i = 0U, aq_vec = self->aq_vec[0]; 667 for (i = 0U, aq_vec = self->aq_vec[0];
765 aq_vec && self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i]) { 668 aq_vec && self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i]) {
@@ -773,7 +676,7 @@ err_exit:;
773static void aq_nic_update_ndev_stats(struct aq_nic_s *self) 676static void aq_nic_update_ndev_stats(struct aq_nic_s *self)
774{ 677{
775 struct net_device *ndev = self->ndev; 678 struct net_device *ndev = self->ndev;
776 struct aq_stats_s *stats = self->aq_hw_ops.hw_get_hw_stats(self->aq_hw); 679 struct aq_stats_s *stats = self->aq_hw_ops->hw_get_hw_stats(self->aq_hw);
777 680
778 ndev->stats.rx_packets = stats->uprc + stats->mprc + stats->bprc; 681 ndev->stats.rx_packets = stats->uprc + stats->mprc + stats->bprc;
779 ndev->stats.rx_bytes = stats->ubrc + stats->mbrc + stats->bbrc; 682 ndev->stats.rx_bytes = stats->ubrc + stats->mbrc + stats->bbrc;
@@ -787,39 +690,46 @@ static void aq_nic_update_ndev_stats(struct aq_nic_s *self)
787void aq_nic_get_link_ksettings(struct aq_nic_s *self, 690void aq_nic_get_link_ksettings(struct aq_nic_s *self,
788 struct ethtool_link_ksettings *cmd) 691 struct ethtool_link_ksettings *cmd)
789{ 692{
790 cmd->base.port = PORT_TP; 693 if (self->aq_nic_cfg.aq_hw_caps->media_type == AQ_HW_MEDIA_TYPE_FIBRE)
694 cmd->base.port = PORT_FIBRE;
695 else
696 cmd->base.port = PORT_TP;
791 /* This driver supports only 10G capable adapters, so DUPLEX_FULL */ 697 /* This driver supports only 10G capable adapters, so DUPLEX_FULL */
792 cmd->base.duplex = DUPLEX_FULL; 698 cmd->base.duplex = DUPLEX_FULL;
793 cmd->base.autoneg = self->aq_nic_cfg.is_autoneg; 699 cmd->base.autoneg = self->aq_nic_cfg.is_autoneg;
794 700
795 ethtool_link_ksettings_zero_link_mode(cmd, supported); 701 ethtool_link_ksettings_zero_link_mode(cmd, supported);
796 702
797 if (self->aq_hw_caps.link_speed_msk & AQ_NIC_RATE_10G) 703 if (self->aq_nic_cfg.aq_hw_caps->link_speed_msk & AQ_NIC_RATE_10G)
798 ethtool_link_ksettings_add_link_mode(cmd, supported, 704 ethtool_link_ksettings_add_link_mode(cmd, supported,
799 10000baseT_Full); 705 10000baseT_Full);
800 706
801 if (self->aq_hw_caps.link_speed_msk & AQ_NIC_RATE_5G) 707 if (self->aq_nic_cfg.aq_hw_caps->link_speed_msk & AQ_NIC_RATE_5G)
802 ethtool_link_ksettings_add_link_mode(cmd, supported, 708 ethtool_link_ksettings_add_link_mode(cmd, supported,
803 5000baseT_Full); 709 5000baseT_Full);
804 710
805 if (self->aq_hw_caps.link_speed_msk & AQ_NIC_RATE_2GS) 711 if (self->aq_nic_cfg.aq_hw_caps->link_speed_msk & AQ_NIC_RATE_2GS)
806 ethtool_link_ksettings_add_link_mode(cmd, supported, 712 ethtool_link_ksettings_add_link_mode(cmd, supported,
807 2500baseT_Full); 713 2500baseT_Full);
808 714
809 if (self->aq_hw_caps.link_speed_msk & AQ_NIC_RATE_1G) 715 if (self->aq_nic_cfg.aq_hw_caps->link_speed_msk & AQ_NIC_RATE_1G)
810 ethtool_link_ksettings_add_link_mode(cmd, supported, 716 ethtool_link_ksettings_add_link_mode(cmd, supported,
811 1000baseT_Full); 717 1000baseT_Full);
812 718
813 if (self->aq_hw_caps.link_speed_msk & AQ_NIC_RATE_100M) 719 if (self->aq_nic_cfg.aq_hw_caps->link_speed_msk & AQ_NIC_RATE_100M)
814 ethtool_link_ksettings_add_link_mode(cmd, supported, 720 ethtool_link_ksettings_add_link_mode(cmd, supported,
815 100baseT_Full); 721 100baseT_Full);
816 722
817 if (self->aq_hw_caps.flow_control) 723 if (self->aq_nic_cfg.aq_hw_caps->flow_control)
818 ethtool_link_ksettings_add_link_mode(cmd, supported, 724 ethtool_link_ksettings_add_link_mode(cmd, supported,
819 Pause); 725 Pause);
820 726
821 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg); 727 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
822 ethtool_link_ksettings_add_link_mode(cmd, supported, TP); 728
729 if (self->aq_nic_cfg.aq_hw_caps->media_type == AQ_HW_MEDIA_TYPE_FIBRE)
730 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
731 else
732 ethtool_link_ksettings_add_link_mode(cmd, supported, TP);
823 733
824 ethtool_link_ksettings_zero_link_mode(cmd, advertising); 734 ethtool_link_ksettings_zero_link_mode(cmd, advertising);
825 735
@@ -850,7 +760,10 @@ void aq_nic_get_link_ksettings(struct aq_nic_s *self,
850 ethtool_link_ksettings_add_link_mode(cmd, advertising, 760 ethtool_link_ksettings_add_link_mode(cmd, advertising,
851 Pause); 761 Pause);
852 762
853 ethtool_link_ksettings_add_link_mode(cmd, advertising, TP); 763 if (self->aq_nic_cfg.aq_hw_caps->media_type == AQ_HW_MEDIA_TYPE_FIBRE)
764 ethtool_link_ksettings_add_link_mode(cmd, advertising, FIBRE);
765 else
766 ethtool_link_ksettings_add_link_mode(cmd, advertising, TP);
854} 767}
855 768
856int aq_nic_set_link_ksettings(struct aq_nic_s *self, 769int aq_nic_set_link_ksettings(struct aq_nic_s *self,
@@ -861,7 +774,7 @@ int aq_nic_set_link_ksettings(struct aq_nic_s *self,
861 int err = 0; 774 int err = 0;
862 775
863 if (cmd->base.autoneg == AUTONEG_ENABLE) { 776 if (cmd->base.autoneg == AUTONEG_ENABLE) {
864 rate = self->aq_hw_caps.link_speed_msk; 777 rate = self->aq_nic_cfg.aq_hw_caps->link_speed_msk;
865 self->aq_nic_cfg.is_autoneg = true; 778 self->aq_nic_cfg.is_autoneg = true;
866 } else { 779 } else {
867 speed = cmd->base.speed; 780 speed = cmd->base.speed;
@@ -892,7 +805,7 @@ int aq_nic_set_link_ksettings(struct aq_nic_s *self,
892 goto err_exit; 805 goto err_exit;
893 break; 806 break;
894 } 807 }
895 if (!(self->aq_hw_caps.link_speed_msk & rate)) { 808 if (!(self->aq_nic_cfg.aq_hw_caps->link_speed_msk & rate)) {
896 err = -1; 809 err = -1;
897 goto err_exit; 810 goto err_exit;
898 } 811 }
@@ -900,7 +813,7 @@ int aq_nic_set_link_ksettings(struct aq_nic_s *self,
900 self->aq_nic_cfg.is_autoneg = false; 813 self->aq_nic_cfg.is_autoneg = false;
901 } 814 }
902 815
903 err = self->aq_hw_ops.hw_set_link_speed(self->aq_hw, rate); 816 err = self->aq_fw_ops->set_link_speed(self->aq_hw, rate);
904 if (err < 0) 817 if (err < 0)
905 goto err_exit; 818 goto err_exit;
906 819
@@ -919,7 +832,7 @@ u32 aq_nic_get_fw_version(struct aq_nic_s *self)
919{ 832{
920 u32 fw_version = 0U; 833 u32 fw_version = 0U;
921 834
922 self->aq_hw_ops.hw_get_fw_version(self->aq_hw, &fw_version); 835 self->aq_hw_ops->hw_get_fw_version(self->aq_hw, &fw_version);
923 836
924 return fw_version; 837 return fw_version;
925} 838}
@@ -934,18 +847,18 @@ int aq_nic_stop(struct aq_nic_s *self)
934 847
935 del_timer_sync(&self->service_timer); 848 del_timer_sync(&self->service_timer);
936 849
937 self->aq_hw_ops.hw_irq_disable(self->aq_hw, AQ_CFG_IRQ_MASK); 850 self->aq_hw_ops->hw_irq_disable(self->aq_hw, AQ_CFG_IRQ_MASK);
938 851
939 if (self->aq_nic_cfg.is_polling) 852 if (self->aq_nic_cfg.is_polling)
940 del_timer_sync(&self->polling_timer); 853 del_timer_sync(&self->polling_timer);
941 else 854 else
942 aq_pci_func_free_irqs(self->aq_pci_func); 855 aq_pci_func_free_irqs(self);
943 856
944 for (i = 0U, aq_vec = self->aq_vec[0]; 857 for (i = 0U, aq_vec = self->aq_vec[0];
945 self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i]) 858 self->aq_vecs > i; ++i, aq_vec = self->aq_vec[i])
946 aq_vec_stop(aq_vec); 859 aq_vec_stop(aq_vec);
947 860
948 return self->aq_hw_ops.hw_stop(self->aq_hw); 861 return self->aq_hw_ops->hw_stop(self->aq_hw);
949} 862}
950 863
951void aq_nic_deinit(struct aq_nic_s *self) 864void aq_nic_deinit(struct aq_nic_s *self)
@@ -961,16 +874,16 @@ void aq_nic_deinit(struct aq_nic_s *self)
961 aq_vec_deinit(aq_vec); 874 aq_vec_deinit(aq_vec);
962 875
963 if (self->power_state == AQ_HW_POWER_STATE_D0) { 876 if (self->power_state == AQ_HW_POWER_STATE_D0) {
964 (void)self->aq_hw_ops.hw_deinit(self->aq_hw); 877 (void)self->aq_hw_ops->hw_deinit(self->aq_hw);
965 } else { 878 } else {
966 (void)self->aq_hw_ops.hw_set_power(self->aq_hw, 879 (void)self->aq_hw_ops->hw_set_power(self->aq_hw,
967 self->power_state); 880 self->power_state);
968 } 881 }
969 882
970err_exit:; 883err_exit:;
971} 884}
972 885
973void aq_nic_free_hot_resources(struct aq_nic_s *self) 886void aq_nic_free_vectors(struct aq_nic_s *self)
974{ 887{
975 unsigned int i = 0U; 888 unsigned int i = 0U;
976 889
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_nic.h b/drivers/net/ethernet/aquantia/atlantic/aq_nic.h
index 1cd7d728e91b..d16b0f1a95aa 100644
--- a/drivers/net/ethernet/aquantia/atlantic/aq_nic.h
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_nic.h
@@ -17,24 +17,10 @@
17#include "aq_hw.h" 17#include "aq_hw.h"
18 18
19struct aq_ring_s; 19struct aq_ring_s;
20struct aq_pci_func_s;
21struct aq_hw_ops; 20struct aq_hw_ops;
22struct aq_fw_s; 21struct aq_fw_s;
23struct aq_vec_s; 22struct aq_vec_s;
24 23
25#define AQ_NIC_FC_OFF 0U
26#define AQ_NIC_FC_TX 1U
27#define AQ_NIC_FC_RX 2U
28#define AQ_NIC_FC_FULL 3U
29#define AQ_NIC_FC_AUTO 4U
30
31#define AQ_NIC_RATE_10G BIT(0)
32#define AQ_NIC_RATE_5G BIT(1)
33#define AQ_NIC_RATE_5GSR BIT(2)
34#define AQ_NIC_RATE_2GS BIT(3)
35#define AQ_NIC_RATE_1G BIT(4)
36#define AQ_NIC_RATE_100M BIT(5)
37
38struct aq_nic_cfg_s { 24struct aq_nic_cfg_s {
39 const struct aq_hw_caps_s *aq_hw_caps; 25 const struct aq_hw_caps_s *aq_hw_caps;
40 u64 hw_features; 26 u64 hw_features;
@@ -77,13 +63,12 @@ struct aq_nic_s {
77 struct aq_ring_s *aq_ring_tx[AQ_CFG_VECS_MAX * AQ_CFG_TCS_MAX]; 63 struct aq_ring_s *aq_ring_tx[AQ_CFG_VECS_MAX * AQ_CFG_TCS_MAX];
78 struct aq_hw_s *aq_hw; 64 struct aq_hw_s *aq_hw;
79 struct net_device *ndev; 65 struct net_device *ndev;
80 struct aq_pci_func_s *aq_pci_func;
81 unsigned int aq_vecs; 66 unsigned int aq_vecs;
82 unsigned int packet_filter; 67 unsigned int packet_filter;
83 unsigned int power_state; 68 unsigned int power_state;
84 u8 port; 69 u8 port;
85 struct aq_hw_ops aq_hw_ops; 70 const struct aq_hw_ops *aq_hw_ops;
86 struct aq_hw_caps_s aq_hw_caps; 71 const struct aq_fw_ops *aq_fw_ops;
87 struct aq_nic_cfg_s aq_nic_cfg; 72 struct aq_nic_cfg_s aq_nic_cfg;
88 struct timer_list service_timer; 73 struct timer_list service_timer;
89 struct timer_list polling_timer; 74 struct timer_list polling_timer;
@@ -102,18 +87,13 @@ static inline struct device *aq_nic_get_dev(struct aq_nic_s *self)
102 return self->ndev->dev.parent; 87 return self->ndev->dev.parent;
103} 88}
104 89
105struct aq_nic_s *aq_nic_alloc_cold(struct pci_dev *pdev, 90void aq_nic_ndev_init(struct aq_nic_s *self);
106 struct aq_pci_func_s *aq_pci_func,
107 unsigned int port,
108 const struct aq_hw_ops *aq_hw_ops);
109int aq_nic_ndev_init(struct aq_nic_s *self);
110struct aq_nic_s *aq_nic_alloc_hot(struct net_device *ndev); 91struct aq_nic_s *aq_nic_alloc_hot(struct net_device *ndev);
111void aq_nic_set_tx_ring(struct aq_nic_s *self, unsigned int idx, 92void aq_nic_set_tx_ring(struct aq_nic_s *self, unsigned int idx,
112 struct aq_ring_s *ring); 93 struct aq_ring_s *ring);
113struct device *aq_nic_get_dev(struct aq_nic_s *self);
114struct net_device *aq_nic_get_ndev(struct aq_nic_s *self); 94struct net_device *aq_nic_get_ndev(struct aq_nic_s *self);
115int aq_nic_init(struct aq_nic_s *self); 95int aq_nic_init(struct aq_nic_s *self);
116int aq_nic_cfg_start(struct aq_nic_s *self); 96void aq_nic_cfg_start(struct aq_nic_s *self);
117int aq_nic_ndev_register(struct aq_nic_s *self); 97int aq_nic_ndev_register(struct aq_nic_s *self);
118void aq_nic_ndev_free(struct aq_nic_s *self); 98void aq_nic_ndev_free(struct aq_nic_s *self);
119int aq_nic_start(struct aq_nic_s *self); 99int aq_nic_start(struct aq_nic_s *self);
@@ -124,6 +104,7 @@ void aq_nic_get_stats(struct aq_nic_s *self, u64 *data);
124int aq_nic_stop(struct aq_nic_s *self); 104int aq_nic_stop(struct aq_nic_s *self);
125void aq_nic_deinit(struct aq_nic_s *self); 105void aq_nic_deinit(struct aq_nic_s *self);
126void aq_nic_free_hot_resources(struct aq_nic_s *self); 106void aq_nic_free_hot_resources(struct aq_nic_s *self);
107void aq_nic_free_vectors(struct aq_nic_s *self);
127int aq_nic_set_mtu(struct aq_nic_s *self, int new_mtu); 108int aq_nic_set_mtu(struct aq_nic_s *self, int new_mtu);
128int aq_nic_set_mac(struct aq_nic_s *self, struct net_device *ndev); 109int aq_nic_set_mac(struct aq_nic_s *self, struct net_device *ndev);
129int aq_nic_set_packet_filter(struct aq_nic_s *self, unsigned int flags); 110int aq_nic_set_packet_filter(struct aq_nic_s *self, unsigned int flags);
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_pci_func.c b/drivers/net/ethernet/aquantia/atlantic/aq_pci_func.c
index 78ef7d2deffe..f5dd5f75a40f 100644
--- a/drivers/net/ethernet/aquantia/atlantic/aq_pci_func.c
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_pci_func.c
@@ -12,201 +12,132 @@
12#include <linux/interrupt.h> 12#include <linux/interrupt.h>
13#include <linux/module.h> 13#include <linux/module.h>
14 14
15#include "aq_pci_func.h" 15#include "aq_main.h"
16#include "aq_nic.h" 16#include "aq_nic.h"
17#include "aq_vec.h" 17#include "aq_vec.h"
18#include "aq_hw.h" 18#include "aq_hw.h"
19#include "aq_pci_func.h"
19#include "hw_atl/hw_atl_a0.h" 20#include "hw_atl/hw_atl_a0.h"
20#include "hw_atl/hw_atl_b0.h" 21#include "hw_atl/hw_atl_b0.h"
21 22
22struct aq_pci_func_s {
23 struct pci_dev *pdev;
24 struct aq_nic_s *port[AQ_CFG_PCI_FUNC_PORTS];
25 void __iomem *mmio;
26 void *aq_vec[AQ_CFG_PCI_FUNC_MSIX_IRQS];
27 resource_size_t mmio_pa;
28 unsigned int msix_entry_mask;
29 unsigned int ports;
30 bool is_pci_enabled;
31 bool is_regions;
32 bool is_pci_using_dac;
33 struct aq_hw_caps_s aq_hw_caps;
34};
35
36static const struct pci_device_id aq_pci_tbl[] = { 23static const struct pci_device_id aq_pci_tbl[] = {
37 { PCI_VDEVICE(AQUANTIA, HW_ATL_DEVICE_ID_0001), }, 24 { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_0001), },
38 { PCI_VDEVICE(AQUANTIA, HW_ATL_DEVICE_ID_D100), }, 25 { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_D100), },
39 { PCI_VDEVICE(AQUANTIA, HW_ATL_DEVICE_ID_D107), }, 26 { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_D107), },
40 { PCI_VDEVICE(AQUANTIA, HW_ATL_DEVICE_ID_D108), }, 27 { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_D108), },
41 { PCI_VDEVICE(AQUANTIA, HW_ATL_DEVICE_ID_D109), }, 28 { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_D109), },
29
30 { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC100), },
31 { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC107), },
32 { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC108), },
33 { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC109), },
34 { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC111), },
35 { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC112), },
36
37 { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC100S), },
38 { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC107S), },
39 { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC108S), },
40 { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC109S), },
41 { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC111S), },
42 { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC112S), },
43
44 { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC111E), },
45 { PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC112E), },
46
42 {} 47 {}
43}; 48};
44 49
45MODULE_DEVICE_TABLE(pci, aq_pci_tbl); 50const struct aq_board_revision_s hw_atl_boards[] = {
46 51 { AQ_DEVICE_ID_0001, AQ_HWREV_1, &hw_atl_ops_a0, &hw_atl_a0_caps_aqc107, },
47static const struct aq_hw_ops *aq_pci_probe_get_hw_ops_by_id(struct pci_dev *pdev) 52 { AQ_DEVICE_ID_D100, AQ_HWREV_1, &hw_atl_ops_a0, &hw_atl_a0_caps_aqc100, },
48{ 53 { AQ_DEVICE_ID_D107, AQ_HWREV_1, &hw_atl_ops_a0, &hw_atl_a0_caps_aqc107, },
49 const struct aq_hw_ops *ops = NULL; 54 { AQ_DEVICE_ID_D108, AQ_HWREV_1, &hw_atl_ops_a0, &hw_atl_a0_caps_aqc108, },
50 55 { AQ_DEVICE_ID_D109, AQ_HWREV_1, &hw_atl_ops_a0, &hw_atl_a0_caps_aqc109, },
51 ops = hw_atl_a0_get_ops_by_id(pdev); 56
52 if (!ops) 57 { AQ_DEVICE_ID_0001, AQ_HWREV_2, &hw_atl_ops_b0, &hw_atl_b0_caps_aqc107, },
53 ops = hw_atl_b0_get_ops_by_id(pdev); 58 { AQ_DEVICE_ID_D100, AQ_HWREV_2, &hw_atl_ops_b0, &hw_atl_b0_caps_aqc100, },
59 { AQ_DEVICE_ID_D107, AQ_HWREV_2, &hw_atl_ops_b0, &hw_atl_b0_caps_aqc107, },
60 { AQ_DEVICE_ID_D108, AQ_HWREV_2, &hw_atl_ops_b0, &hw_atl_b0_caps_aqc108, },
61 { AQ_DEVICE_ID_D109, AQ_HWREV_2, &hw_atl_ops_b0, &hw_atl_b0_caps_aqc109, },
62
63 { AQ_DEVICE_ID_AQC100, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc107, },
64 { AQ_DEVICE_ID_AQC107, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc107, },
65 { AQ_DEVICE_ID_AQC108, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc108, },
66 { AQ_DEVICE_ID_AQC109, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc109, },
67 { AQ_DEVICE_ID_AQC111, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc111, },
68 { AQ_DEVICE_ID_AQC112, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc112, },
69
70 { AQ_DEVICE_ID_AQC100S, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc100s, },
71 { AQ_DEVICE_ID_AQC107S, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc107s, },
72 { AQ_DEVICE_ID_AQC108S, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc108s, },
73 { AQ_DEVICE_ID_AQC109S, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc109s, },
74 { AQ_DEVICE_ID_AQC111S, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc111s, },
75 { AQ_DEVICE_ID_AQC112S, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc112s, },
76
77 { AQ_DEVICE_ID_AQC111E, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc111e, },
78 { AQ_DEVICE_ID_AQC112E, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc112e, },
79};
54 80
55 return ops; 81MODULE_DEVICE_TABLE(pci, aq_pci_tbl);
56}
57 82
58struct aq_pci_func_s *aq_pci_func_alloc(const struct aq_hw_ops *aq_hw_ops, 83static int aq_pci_probe_get_hw_by_id(struct pci_dev *pdev,
59 struct pci_dev *pdev) 84 const struct aq_hw_ops **ops,
85 const struct aq_hw_caps_s **caps)
60{ 86{
61 struct aq_pci_func_s *self = NULL; 87 int i = 0;
62 int err = 0;
63 unsigned int port = 0U;
64
65 if (!aq_hw_ops) {
66 err = -EFAULT;
67 goto err_exit;
68 }
69 self = kzalloc(sizeof(*self), GFP_KERNEL);
70 if (!self) {
71 err = -ENOMEM;
72 goto err_exit;
73 }
74
75 pci_set_drvdata(pdev, self);
76 self->pdev = pdev;
77
78 err = aq_hw_ops->get_hw_caps(NULL, &self->aq_hw_caps, pdev->device,
79 pdev->subsystem_device);
80 if (err < 0)
81 goto err_exit;
82
83 self->ports = self->aq_hw_caps.ports;
84 88
85 for (port = 0; port < self->ports; ++port) { 89 if (pdev->vendor != PCI_VENDOR_ID_AQUANTIA)
86 struct aq_nic_s *aq_nic = aq_nic_alloc_cold(pdev, self, 90 return -EINVAL;
87 port, aq_hw_ops);
88 91
89 if (!aq_nic) { 92 for (i = 0; i < ARRAY_SIZE(hw_atl_boards); i++) {
90 err = -ENOMEM; 93 if (hw_atl_boards[i].devid == pdev->device &&
91 goto err_exit; 94 (hw_atl_boards[i].revision == AQ_HWREV_ANY ||
95 hw_atl_boards[i].revision == pdev->revision)) {
96 *ops = hw_atl_boards[i].ops;
97 *caps = hw_atl_boards[i].caps;
98 break;
92 } 99 }
93 self->port[port] = aq_nic;
94 } 100 }
95 101
96err_exit: 102 if (i == ARRAY_SIZE(hw_atl_boards))
97 if (err < 0) { 103 return -EINVAL;
98 if (self)
99 aq_pci_func_free(self);
100 self = NULL;
101 }
102 104
103 (void)err; 105 return 0;
104 return self;
105} 106}
106 107
107int aq_pci_func_init(struct aq_pci_func_s *self) 108int aq_pci_func_init(struct pci_dev *pdev)
108{ 109{
109 int err = 0; 110 int err = 0;
110 unsigned int bar = 0U;
111 unsigned int port = 0U;
112 unsigned int numvecs = 0U;
113
114 err = pci_enable_device(self->pdev);
115 if (err < 0)
116 goto err_exit;
117
118 self->is_pci_enabled = true;
119 111
120 err = pci_set_dma_mask(self->pdev, DMA_BIT_MASK(64)); 112 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
121 if (!err) { 113 if (!err) {
122 err = pci_set_consistent_dma_mask(self->pdev, DMA_BIT_MASK(64)); 114 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
123 self->is_pci_using_dac = 1; 115
124 } 116 }
125 if (err) { 117 if (err) {
126 err = pci_set_dma_mask(self->pdev, DMA_BIT_MASK(32)); 118 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
127 if (!err) 119 if (!err)
128 err = pci_set_consistent_dma_mask(self->pdev, 120 err = pci_set_consistent_dma_mask(pdev,
129 DMA_BIT_MASK(32)); 121 DMA_BIT_MASK(32));
130 self->is_pci_using_dac = 0;
131 } 122 }
132 if (err != 0) { 123 if (err != 0) {
133 err = -ENOSR; 124 err = -ENOSR;
134 goto err_exit; 125 goto err_exit;
135 } 126 }
136 127
137 err = pci_request_regions(self->pdev, AQ_CFG_DRV_NAME "_mmio"); 128 err = pci_request_regions(pdev, AQ_CFG_DRV_NAME "_mmio");
138 if (err < 0) 129 if (err < 0)
139 goto err_exit; 130 goto err_exit;
140 131
141 self->is_regions = true; 132 pci_set_master(pdev);
142
143 pci_set_master(self->pdev);
144
145 for (bar = 0; bar < 4; ++bar) {
146 if (IORESOURCE_MEM & pci_resource_flags(self->pdev, bar)) {
147 resource_size_t reg_sz;
148 133
149 self->mmio_pa = pci_resource_start(self->pdev, bar); 134 return 0;
150 if (self->mmio_pa == 0U) {
151 err = -EIO;
152 goto err_exit;
153 }
154
155 reg_sz = pci_resource_len(self->pdev, bar);
156 if ((reg_sz <= 24 /*ATL_REGS_SIZE*/)) {
157 err = -EIO;
158 goto err_exit;
159 }
160
161 self->mmio = ioremap_nocache(self->mmio_pa, reg_sz);
162 if (!self->mmio) {
163 err = -EIO;
164 goto err_exit;
165 }
166 break;
167 }
168 }
169
170 numvecs = min((u8)AQ_CFG_VECS_DEF, self->aq_hw_caps.msix_irqs);
171 numvecs = min(numvecs, num_online_cpus());
172
173 /* enable interrupts */
174#if !AQ_CFG_FORCE_LEGACY_INT
175 err = pci_alloc_irq_vectors(self->pdev, numvecs, numvecs, PCI_IRQ_MSIX);
176
177 if (err < 0) {
178 err = pci_alloc_irq_vectors(self->pdev, 1, 1,
179 PCI_IRQ_MSI | PCI_IRQ_LEGACY);
180 if (err < 0)
181 goto err_exit;
182 }
183#endif /* AQ_CFG_FORCE_LEGACY_INT */
184
185 /* net device init */
186 for (port = 0; port < self->ports; ++port) {
187 if (!self->port[port])
188 continue;
189
190 err = aq_nic_cfg_start(self->port[port]);
191 if (err < 0)
192 goto err_exit;
193
194 err = aq_nic_ndev_init(self->port[port]);
195 if (err < 0)
196 goto err_exit;
197
198 err = aq_nic_ndev_register(self->port[port]);
199 if (err < 0)
200 goto err_exit;
201 }
202 135
203err_exit: 136err_exit:
204 if (err < 0)
205 aq_pci_func_deinit(self);
206 return err; 137 return err;
207} 138}
208 139
209int aq_pci_func_alloc_irq(struct aq_pci_func_s *self, unsigned int i, 140int aq_pci_func_alloc_irq(struct aq_nic_s *self, unsigned int i,
210 char *name, void *aq_vec, cpumask_t *affinity_mask) 141 char *name, void *aq_vec, cpumask_t *affinity_mask)
211{ 142{
212 struct pci_dev *pdev = self->pdev; 143 struct pci_dev *pdev = self->pdev;
@@ -227,11 +158,10 @@ int aq_pci_func_alloc_irq(struct aq_pci_func_s *self, unsigned int i,
227 irq_set_affinity_hint(pci_irq_vector(pdev, i), 158 irq_set_affinity_hint(pci_irq_vector(pdev, i),
228 affinity_mask); 159 affinity_mask);
229 } 160 }
230
231 return err; 161 return err;
232} 162}
233 163
234void aq_pci_func_free_irqs(struct aq_pci_func_s *self) 164void aq_pci_func_free_irqs(struct aq_nic_s *self)
235{ 165{
236 struct pci_dev *pdev = self->pdev; 166 struct pci_dev *pdev = self->pdev;
237 unsigned int i = 0U; 167 unsigned int i = 0U;
@@ -247,12 +177,7 @@ void aq_pci_func_free_irqs(struct aq_pci_func_s *self)
247 } 177 }
248} 178}
249 179
250void __iomem *aq_pci_func_get_mmio(struct aq_pci_func_s *self) 180unsigned int aq_pci_func_get_irq_type(struct aq_nic_s *self)
251{
252 return self->mmio;
253}
254
255unsigned int aq_pci_func_get_irq_type(struct aq_pci_func_s *self)
256{ 181{
257 if (self->pdev->msix_enabled) 182 if (self->pdev->msix_enabled)
258 return AQ_HW_IRQ_MSIX; 183 return AQ_HW_IRQ_MSIX;
@@ -261,115 +186,148 @@ unsigned int aq_pci_func_get_irq_type(struct aq_pci_func_s *self)
261 return AQ_HW_IRQ_LEGACY; 186 return AQ_HW_IRQ_LEGACY;
262} 187}
263 188
264void aq_pci_func_deinit(struct aq_pci_func_s *self) 189static void aq_pci_free_irq_vectors(struct aq_nic_s *self)
265{ 190{
266 if (!self)
267 goto err_exit;
268
269 aq_pci_func_free_irqs(self);
270 pci_free_irq_vectors(self->pdev); 191 pci_free_irq_vectors(self->pdev);
192}
271 193
272 if (self->is_regions) 194static int aq_pci_probe(struct pci_dev *pdev,
273 pci_release_regions(self->pdev); 195 const struct pci_device_id *pci_id)
196{
197 struct aq_nic_s *self = NULL;
198 int err = 0;
199 struct net_device *ndev;
200 resource_size_t mmio_pa;
201 u32 bar;
202 u32 numvecs;
274 203
275 if (self->is_pci_enabled) 204 err = pci_enable_device(pdev);
276 pci_disable_device(self->pdev); 205 if (err)
206 return err;
277 207
278err_exit:; 208 err = aq_pci_func_init(pdev);
279} 209 if (err)
210 goto err_pci_func;
280 211
281void aq_pci_func_free(struct aq_pci_func_s *self) 212 ndev = aq_ndev_alloc();
282{ 213 if (!ndev)
283 unsigned int port = 0U; 214 goto err_ndev;
284 215
285 if (!self) 216 self = netdev_priv(ndev);
286 goto err_exit; 217 self->pdev = pdev;
218 SET_NETDEV_DEV(ndev, &pdev->dev);
219 pci_set_drvdata(pdev, self);
287 220
288 for (port = 0; port < self->ports; ++port) { 221 err = aq_pci_probe_get_hw_by_id(pdev, &self->aq_hw_ops,
289 if (!self->port[port]) 222 &aq_nic_get_cfg(self)->aq_hw_caps);
290 continue; 223 if (err)
224 goto err_ioremap;
291 225
292 aq_nic_ndev_free(self->port[port]); 226 self->aq_hw = kzalloc(sizeof(*self->aq_hw), GFP_KERNEL);
293 } 227 self->aq_hw->aq_nic_cfg = aq_nic_get_cfg(self);
294 228
295 if (self->mmio) 229 for (bar = 0; bar < 4; ++bar) {
296 iounmap(self->mmio); 230 if (IORESOURCE_MEM & pci_resource_flags(pdev, bar)) {
231 resource_size_t reg_sz;
297 232
298 kfree(self); 233 mmio_pa = pci_resource_start(pdev, bar);
234 if (mmio_pa == 0U) {
235 err = -EIO;
236 goto err_ioremap;
237 }
299 238
300err_exit:; 239 reg_sz = pci_resource_len(pdev, bar);
301} 240 if ((reg_sz <= 24 /*ATL_REGS_SIZE*/)) {
241 err = -EIO;
242 goto err_ioremap;
243 }
302 244
303int aq_pci_func_change_pm_state(struct aq_pci_func_s *self, 245 self->aq_hw->mmio = ioremap_nocache(mmio_pa, reg_sz);
304 pm_message_t *pm_msg) 246 if (!self->aq_hw->mmio) {
305{ 247 err = -EIO;
306 int err = 0; 248 goto err_ioremap;
307 unsigned int port = 0U; 249 }
250 break;
251 }
252 }
308 253
309 if (!self) { 254 if (bar == 4) {
310 err = -EFAULT; 255 err = -EIO;
311 goto err_exit; 256 goto err_ioremap;
312 } 257 }
313 for (port = 0; port < self->ports; ++port) {
314 if (!self->port[port])
315 continue;
316 258
317 (void)aq_nic_change_pm_state(self->port[port], pm_msg); 259 numvecs = min((u8)AQ_CFG_VECS_DEF,
260 aq_nic_get_cfg(self)->aq_hw_caps->msix_irqs);
261 numvecs = min(numvecs, num_online_cpus());
262 /*enable interrupts */
263#if !AQ_CFG_FORCE_LEGACY_INT
264 err = pci_alloc_irq_vectors(self->pdev, numvecs, numvecs,
265 PCI_IRQ_MSIX);
266
267 if (err < 0) {
268 err = pci_alloc_irq_vectors(self->pdev, 1, 1,
269 PCI_IRQ_MSI | PCI_IRQ_LEGACY);
270 if (err < 0)
271 goto err_hwinit;
318 } 272 }
273#endif
319 274
320err_exit: 275 /* net device init */
321 return err; 276 aq_nic_cfg_start(self);
322}
323 277
324static int aq_pci_probe(struct pci_dev *pdev, 278 aq_nic_ndev_init(self);
325 const struct pci_device_id *pci_id)
326{
327 const struct aq_hw_ops *aq_hw_ops = NULL;
328 struct aq_pci_func_s *aq_pci_func = NULL;
329 int err = 0;
330 279
331 err = pci_enable_device(pdev); 280 err = aq_nic_ndev_register(self);
332 if (err < 0)
333 goto err_exit;
334 aq_hw_ops = aq_pci_probe_get_hw_ops_by_id(pdev);
335 aq_pci_func = aq_pci_func_alloc(aq_hw_ops, pdev);
336 if (!aq_pci_func) {
337 err = -ENOMEM;
338 goto err_exit;
339 }
340 err = aq_pci_func_init(aq_pci_func);
341 if (err < 0) 281 if (err < 0)
342 goto err_exit; 282 goto err_register;
343 283
344err_exit: 284 return 0;
345 if (err < 0) { 285
346 if (aq_pci_func) 286err_register:
347 aq_pci_func_free(aq_pci_func); 287 aq_nic_free_vectors(self);
348 } 288 aq_pci_free_irq_vectors(self);
289err_hwinit:
290 iounmap(self->aq_hw->mmio);
291err_ioremap:
292 free_netdev(ndev);
293err_pci_func:
294 pci_release_regions(pdev);
295err_ndev:
296 pci_disable_device(pdev);
349 return err; 297 return err;
350} 298}
351 299
352static void aq_pci_remove(struct pci_dev *pdev) 300static void aq_pci_remove(struct pci_dev *pdev)
353{ 301{
354 struct aq_pci_func_s *aq_pci_func = pci_get_drvdata(pdev); 302 struct aq_nic_s *self = pci_get_drvdata(pdev);
303
304 if (self->ndev) {
305 if (self->ndev->reg_state == NETREG_REGISTERED)
306 unregister_netdev(self->ndev);
307 aq_nic_free_vectors(self);
308 aq_pci_free_irq_vectors(self);
309 iounmap(self->aq_hw->mmio);
310 kfree(self->aq_hw);
311 pci_release_regions(pdev);
312 free_netdev(self->ndev);
313 }
355 314
356 aq_pci_func_deinit(aq_pci_func); 315 pci_disable_device(pdev);
357 aq_pci_func_free(aq_pci_func);
358} 316}
359 317
360static int aq_pci_suspend(struct pci_dev *pdev, pm_message_t pm_msg) 318static int aq_pci_suspend(struct pci_dev *pdev, pm_message_t pm_msg)
361{ 319{
362 struct aq_pci_func_s *aq_pci_func = pci_get_drvdata(pdev); 320 struct aq_nic_s *self = pci_get_drvdata(pdev);
363 321
364 return aq_pci_func_change_pm_state(aq_pci_func, &pm_msg); 322 return aq_nic_change_pm_state(self, &pm_msg);
365} 323}
366 324
367static int aq_pci_resume(struct pci_dev *pdev) 325static int aq_pci_resume(struct pci_dev *pdev)
368{ 326{
369 struct aq_pci_func_s *aq_pci_func = pci_get_drvdata(pdev); 327 struct aq_nic_s *self = pci_get_drvdata(pdev);
370 pm_message_t pm_msg = PMSG_RESTORE; 328 pm_message_t pm_msg = PMSG_RESTORE;
371 329
372 return aq_pci_func_change_pm_state(aq_pci_func, &pm_msg); 330 return aq_nic_change_pm_state(self, &pm_msg);
373} 331}
374 332
375static struct pci_driver aq_pci_ops = { 333static struct pci_driver aq_pci_ops = {
diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_pci_func.h b/drivers/net/ethernet/aquantia/atlantic/aq_pci_func.h
index 5f100ea1b0d6..aeee67bf69fa 100644
--- a/drivers/net/ethernet/aquantia/atlantic/aq_pci_func.h
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_pci_func.h
@@ -15,19 +15,18 @@
15#include "aq_common.h" 15#include "aq_common.h"
16#include "aq_nic.h" 16#include "aq_nic.h"
17 17
18struct aq_pci_func_s *aq_pci_func_alloc(const struct aq_hw_ops *hw_ops, 18struct aq_board_revision_s {
19 struct pci_dev *pdev); 19 unsigned short devid;
20int aq_pci_func_init(struct aq_pci_func_s *self); 20 unsigned short revision;
21int aq_pci_func_alloc_irq(struct aq_pci_func_s *self, unsigned int i, 21 const struct aq_hw_ops *ops;
22 const struct aq_hw_caps_s *caps;
23};
24
25int aq_pci_func_init(struct pci_dev *pdev);
26int aq_pci_func_alloc_irq(struct aq_nic_s *self, unsigned int i,
22 char *name, void *aq_vec, 27 char *name, void *aq_vec,
23 cpumask_t *affinity_mask); 28 cpumask_t *affinity_mask);
24void aq_pci_func_free_irqs(struct aq_pci_func_s *self); 29void aq_pci_func_free_irqs(struct aq_nic_s *self);
25int aq_pci_func_start(struct aq_pci_func_s *self); 30unsigned int aq_pci_func_get_irq_type(struct aq_nic_s *self);
26void __iomem *aq_pci_func_get_mmio(struct aq_pci_func_s *self);
27unsigned int aq_pci_func_get_irq_type(struct aq_pci_func_s *self);
28void aq_pci_func_deinit(struct aq_pci_func_s *self);
29void aq_pci_func_free(struct aq_pci_func_s *self);
30int aq_pci_func_change_pm_state(struct aq_pci_func_s *self,
31 pm_message_t *pm_msg);
32 31
33#endif /* AQ_PCI_FUNC_H */ 32#endif /* AQ_PCI_FUNC_H */
diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c
index 4a1c1b96b8b6..67e2f9fb9402 100644
--- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c
+++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c
@@ -18,45 +18,67 @@
18#include "hw_atl_llh.h" 18#include "hw_atl_llh.h"
19#include "hw_atl_a0_internal.h" 19#include "hw_atl_a0_internal.h"
20 20
21static int hw_atl_a0_get_hw_caps(struct aq_hw_s *self, 21#define DEFAULT_A0_BOARD_BASIC_CAPABILITIES \
22 struct aq_hw_caps_s *aq_hw_caps, 22 .is_64_dma = true, \
23 unsigned short device, 23 .msix_irqs = 4U, \
24 unsigned short subsystem_device) 24 .irq_mask = ~0U, \
25{ 25 .vecs = HW_ATL_A0_RSS_MAX, \
26 memcpy(aq_hw_caps, &hw_atl_a0_hw_caps_, sizeof(*aq_hw_caps)); 26 .tcs = HW_ATL_A0_TC_MAX, \
27 27 .rxd_alignment = 1U, \
28 if (device == HW_ATL_DEVICE_ID_D108 && subsystem_device == 0x0001) 28 .rxd_size = HW_ATL_A0_RXD_SIZE, \
29 aq_hw_caps->link_speed_msk &= ~HW_ATL_A0_RATE_10G; 29 .rxds = 248U, \
30 30 .txd_alignment = 1U, \
31 if (device == HW_ATL_DEVICE_ID_D109 && subsystem_device == 0x0001) { 31 .txd_size = HW_ATL_A0_TXD_SIZE, \
32 aq_hw_caps->link_speed_msk &= ~HW_ATL_A0_RATE_10G; 32 .txds = 8U * 1024U, \
33 aq_hw_caps->link_speed_msk &= ~HW_ATL_A0_RATE_5G; 33 .txhwb_alignment = 4096U, \
34 } 34 .tx_rings = HW_ATL_A0_TX_RINGS, \
35 35 .rx_rings = HW_ATL_A0_RX_RINGS, \
36 return 0; 36 .hw_features = NETIF_F_HW_CSUM | \
37} 37 NETIF_F_RXHASH | \
38 38 NETIF_F_RXCSUM | \
39static struct aq_hw_s *hw_atl_a0_create(struct aq_pci_func_s *aq_pci_func, 39 NETIF_F_SG | \
40 unsigned int port) 40 NETIF_F_TSO, \
41{ 41 .hw_priv_flags = IFF_UNICAST_FLT, \
42 struct aq_hw_s *self = NULL; 42 .flow_control = true, \
43 43 .mtu = HW_ATL_A0_MTU_JUMBO, \
44 self = kzalloc(sizeof(*self), GFP_KERNEL); 44 .mac_regs_count = 88, \
45 if (!self) 45 .hw_alive_check_addr = 0x10U
46 goto err_exit; 46
47 47const struct aq_hw_caps_s hw_atl_a0_caps_aqc100 = {
48 self->aq_pci_func = aq_pci_func; 48 DEFAULT_A0_BOARD_BASIC_CAPABILITIES,
49 .media_type = AQ_HW_MEDIA_TYPE_FIBRE,
50 .link_speed_msk = HW_ATL_A0_RATE_5G |
51 HW_ATL_A0_RATE_2G5 |
52 HW_ATL_A0_RATE_1G |
53 HW_ATL_A0_RATE_100M,
54};
49 55
50 self->not_ff_addr = 0x10U; 56const struct aq_hw_caps_s hw_atl_a0_caps_aqc107 = {
57 DEFAULT_A0_BOARD_BASIC_CAPABILITIES,
58 .media_type = AQ_HW_MEDIA_TYPE_TP,
59 .link_speed_msk = HW_ATL_A0_RATE_10G |
60 HW_ATL_A0_RATE_5G |
61 HW_ATL_A0_RATE_2G5 |
62 HW_ATL_A0_RATE_1G |
63 HW_ATL_A0_RATE_100M,
64};
51 65
52err_exit: 66const struct aq_hw_caps_s hw_atl_a0_caps_aqc108 = {
53 return self; 67 DEFAULT_A0_BOARD_BASIC_CAPABILITIES,
54} 68 .media_type = AQ_HW_MEDIA_TYPE_TP,
69 .link_speed_msk = HW_ATL_A0_RATE_5G |
70 HW_ATL_A0_RATE_2G5 |
71 HW_ATL_A0_RATE_1G |
72 HW_ATL_A0_RATE_100M,
73};
55 74
56static void hw_atl_a0_destroy(struct aq_hw_s *self) 75const struct aq_hw_caps_s hw_atl_a0_caps_aqc109 = {
57{ 76 DEFAULT_A0_BOARD_BASIC_CAPABILITIES,
58 kfree(self); 77 .media_type = AQ_HW_MEDIA_TYPE_TP,
59} 78 .link_speed_msk = HW_ATL_A0_RATE_2G5 |
79 HW_ATL_A0_RATE_1G |
80 HW_ATL_A0_RATE_100M,
81};
60 82
61static int hw_atl_a0_hw_reset(struct aq_hw_s *self) 83static int hw_atl_a0_hw_reset(struct aq_hw_s *self)
62{ 84{
@@ -83,7 +105,7 @@ static int hw_atl_a0_hw_reset(struct aq_hw_s *self)
83 if (err < 0) 105 if (err < 0)
84 goto err_exit; 106 goto err_exit;
85 107
86 hw_atl_utils_mpi_set(self, MPI_RESET, 0x0U); 108 self->aq_fw_ops->set_state(self, MPI_RESET);
87 109
88 err = aq_hw_err_from_flags(self); 110 err = aq_hw_err_from_flags(self);
89 111
@@ -332,7 +354,8 @@ static int hw_atl_a0_hw_init(struct aq_hw_s *self, u8 *mac_addr)
332 354
333 hw_atl_a0_hw_mac_addr_set(self, mac_addr); 355 hw_atl_a0_hw_mac_addr_set(self, mac_addr);
334 356
335 hw_atl_utils_mpi_set(self, MPI_INIT, aq_nic_cfg->link_speed_msk); 357 self->aq_fw_ops->set_link_speed(self, aq_nic_cfg->link_speed_msk);
358 self->aq_fw_ops->set_state(self, MPI_INIT);
336 359
337 hw_atl_reg_tx_dma_debug_ctl_set(self, 0x800000b8U); 360 hw_atl_reg_tx_dma_debug_ctl_set(self, 0x800000b8U);
338 hw_atl_reg_tx_dma_debug_ctl_set(self, 0x000000b8U); 361 hw_atl_reg_tx_dma_debug_ctl_set(self, 0x000000b8U);
@@ -343,7 +366,7 @@ static int hw_atl_a0_hw_init(struct aq_hw_s *self, u8 *mac_addr)
343 366
344 /* Reset link status and read out initial hardware counters */ 367 /* Reset link status and read out initial hardware counters */
345 self->aq_link_status.mbps = 0; 368 self->aq_link_status.mbps = 0;
346 hw_atl_utils_update_stats(self); 369 self->aq_fw_ops->update_stats(self);
347 370
348 err = aq_hw_err_from_flags(self); 371 err = aq_hw_err_from_flags(self);
349 if (err < 0) 372 if (err < 0)
@@ -849,27 +872,8 @@ static int hw_atl_a0_hw_ring_rx_stop(struct aq_hw_s *self,
849 return aq_hw_err_from_flags(self); 872 return aq_hw_err_from_flags(self);
850} 873}
851 874
852static int hw_atl_a0_hw_set_speed(struct aq_hw_s *self, u32 speed) 875const struct aq_hw_ops hw_atl_ops_a0 = {
853{
854 int err = 0;
855
856 err = hw_atl_utils_mpi_set_speed(self, speed, MPI_INIT);
857 if (err < 0)
858 goto err_exit;
859
860err_exit:
861 return err;
862}
863
864static const struct aq_hw_ops hw_atl_ops_ = {
865 .create = hw_atl_a0_create,
866 .destroy = hw_atl_a0_destroy,
867 .get_hw_caps = hw_atl_a0_get_hw_caps,
868
869 .hw_get_mac_permanent = hw_atl_utils_get_mac_permanent,
870 .hw_set_mac_address = hw_atl_a0_hw_mac_addr_set, 876 .hw_set_mac_address = hw_atl_a0_hw_mac_addr_set,
871 .hw_get_link_status = hw_atl_utils_mpi_get_link_status,
872 .hw_set_link_speed = hw_atl_a0_hw_set_speed,
873 .hw_init = hw_atl_a0_hw_init, 877 .hw_init = hw_atl_a0_hw_init,
874 .hw_deinit = hw_atl_utils_hw_deinit, 878 .hw_deinit = hw_atl_utils_hw_deinit,
875 .hw_set_power = hw_atl_utils_hw_set_power, 879 .hw_set_power = hw_atl_utils_hw_set_power,
@@ -899,21 +903,6 @@ static const struct aq_hw_ops hw_atl_ops_ = {
899 .hw_rss_set = hw_atl_a0_hw_rss_set, 903 .hw_rss_set = hw_atl_a0_hw_rss_set,
900 .hw_rss_hash_set = hw_atl_a0_hw_rss_hash_set, 904 .hw_rss_hash_set = hw_atl_a0_hw_rss_hash_set,
901 .hw_get_regs = hw_atl_utils_hw_get_regs, 905 .hw_get_regs = hw_atl_utils_hw_get_regs,
902 .hw_update_stats = hw_atl_utils_update_stats,
903 .hw_get_hw_stats = hw_atl_utils_get_hw_stats, 906 .hw_get_hw_stats = hw_atl_utils_get_hw_stats,
904 .hw_get_fw_version = hw_atl_utils_get_fw_version, 907 .hw_get_fw_version = hw_atl_utils_get_fw_version,
905}; 908};
906
907const struct aq_hw_ops *hw_atl_a0_get_ops_by_id(struct pci_dev *pdev)
908{
909 bool is_vid_ok = (pdev->vendor == PCI_VENDOR_ID_AQUANTIA);
910 bool is_did_ok = ((pdev->device == HW_ATL_DEVICE_ID_0001) ||
911 (pdev->device == HW_ATL_DEVICE_ID_D100) ||
912 (pdev->device == HW_ATL_DEVICE_ID_D107) ||
913 (pdev->device == HW_ATL_DEVICE_ID_D108) ||
914 (pdev->device == HW_ATL_DEVICE_ID_D109));
915
916 bool is_rev_ok = (pdev->revision == 1U);
917
918 return (is_vid_ok && is_did_ok && is_rev_ok) ? &hw_atl_ops_ : NULL;
919}
diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.h
index 4fdd51b67097..25fe954def03 100644
--- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.h
+++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.h
@@ -16,19 +16,11 @@
16 16
17#include "../aq_common.h" 17#include "../aq_common.h"
18 18
19#ifndef PCI_VENDOR_ID_AQUANTIA 19extern const struct aq_hw_caps_s hw_atl_a0_caps_aqc100;
20extern const struct aq_hw_caps_s hw_atl_a0_caps_aqc107;
21extern const struct aq_hw_caps_s hw_atl_a0_caps_aqc108;
22extern const struct aq_hw_caps_s hw_atl_a0_caps_aqc109;
20 23
21#define PCI_VENDOR_ID_AQUANTIA 0x1D6A 24extern const struct aq_hw_ops hw_atl_ops_a0;
22#define HW_ATL_DEVICE_ID_0001 0x0001
23#define HW_ATL_DEVICE_ID_D100 0xD100
24#define HW_ATL_DEVICE_ID_D107 0xD107
25#define HW_ATL_DEVICE_ID_D108 0xD108
26#define HW_ATL_DEVICE_ID_D109 0xD109
27
28#define HW_ATL_NIC_NAME "aQuantia AQtion 5Gbit Network Adapter"
29
30#endif
31
32const struct aq_hw_ops *hw_atl_a0_get_ops_by_id(struct pci_dev *pdev);
33 25
34#endif /* HW_ATL_A0_H */ 26#endif /* HW_ATL_A0_H */
diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0_internal.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0_internal.h
index 7a71330252bd..1d8855558d74 100644
--- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0_internal.h
+++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0_internal.h
@@ -88,38 +88,4 @@
88 88
89#define HW_ATL_A0_FW_VER_EXPECTED 0x01050006U 89#define HW_ATL_A0_FW_VER_EXPECTED 0x01050006U
90 90
91/* HW layer capabilities */
92static struct aq_hw_caps_s hw_atl_a0_hw_caps_ = {
93 .ports = 1U,
94 .is_64_dma = true,
95 .msix_irqs = 4U,
96 .irq_mask = ~0U,
97 .vecs = HW_ATL_A0_RSS_MAX,
98 .tcs = HW_ATL_A0_TC_MAX,
99 .rxd_alignment = 1U,
100 .rxd_size = HW_ATL_A0_RXD_SIZE,
101 .rxds = 248U,
102 .txd_alignment = 1U,
103 .txd_size = HW_ATL_A0_TXD_SIZE,
104 .txds = 8U * 1024U,
105 .txhwb_alignment = 4096U,
106 .tx_rings = HW_ATL_A0_TX_RINGS,
107 .rx_rings = HW_ATL_A0_RX_RINGS,
108 .hw_features = NETIF_F_HW_CSUM |
109 NETIF_F_RXCSUM |
110 NETIF_F_RXHASH |
111 NETIF_F_SG |
112 NETIF_F_TSO,
113 .hw_priv_flags = IFF_UNICAST_FLT,
114 .link_speed_msk = (HW_ATL_A0_RATE_10G |
115 HW_ATL_A0_RATE_5G |
116 HW_ATL_A0_RATE_2G5 |
117 HW_ATL_A0_RATE_1G |
118 HW_ATL_A0_RATE_100M),
119 .flow_control = true,
120 .mtu = HW_ATL_A0_MTU_JUMBO,
121 .mac_regs_count = 88,
122 .fw_ver_expected = HW_ATL_A0_FW_VER_EXPECTED,
123};
124
125#endif /* HW_ATL_A0_INTERNAL_H */ 91#endif /* HW_ATL_A0_INTERNAL_H */
diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c
index 0b090161ed79..819f6bcf9b4e 100644
--- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c
+++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c
@@ -19,76 +19,82 @@
19#include "hw_atl_b0_internal.h" 19#include "hw_atl_b0_internal.h"
20#include "hw_atl_llh_internal.h" 20#include "hw_atl_llh_internal.h"
21 21
22static int hw_atl_b0_get_hw_caps(struct aq_hw_s *self, 22#define DEFAULT_B0_BOARD_BASIC_CAPABILITIES \
23 struct aq_hw_caps_s *aq_hw_caps, 23 .is_64_dma = true, \
24 unsigned short device, 24 .msix_irqs = 4U, \
25 unsigned short subsystem_device) 25 .irq_mask = ~0U, \
26{ 26 .vecs = HW_ATL_B0_RSS_MAX, \
27 memcpy(aq_hw_caps, &hw_atl_b0_hw_caps_, sizeof(*aq_hw_caps)); 27 .tcs = HW_ATL_B0_TC_MAX, \
28 28 .rxd_alignment = 1U, \
29 if (device == HW_ATL_DEVICE_ID_D108 && subsystem_device == 0x0001) 29 .rxd_size = HW_ATL_B0_RXD_SIZE, \
30 aq_hw_caps->link_speed_msk &= ~HW_ATL_B0_RATE_10G; 30 .rxds = 4U * 1024U, \
31 31 .txd_alignment = 1U, \
32 if (device == HW_ATL_DEVICE_ID_D109 && subsystem_device == 0x0001) { 32 .txd_size = HW_ATL_B0_TXD_SIZE, \
33 aq_hw_caps->link_speed_msk &= ~HW_ATL_B0_RATE_10G; 33 .txds = 8U * 1024U, \
34 aq_hw_caps->link_speed_msk &= ~HW_ATL_B0_RATE_5G; 34 .txhwb_alignment = 4096U, \
35 } 35 .tx_rings = HW_ATL_B0_TX_RINGS, \
36 36 .rx_rings = HW_ATL_B0_RX_RINGS, \
37 return 0; 37 .hw_features = NETIF_F_HW_CSUM | \
38} 38 NETIF_F_RXCSUM | \
39 39 NETIF_F_RXHASH | \
40static struct aq_hw_s *hw_atl_b0_create(struct aq_pci_func_s *aq_pci_func, 40 NETIF_F_SG | \
41 unsigned int port) 41 NETIF_F_TSO | \
42{ 42 NETIF_F_LRO, \
43 struct aq_hw_s *self = NULL; 43 .hw_priv_flags = IFF_UNICAST_FLT, \
44 44 .flow_control = true, \
45 self = kzalloc(sizeof(*self), GFP_KERNEL); 45 .mtu = HW_ATL_B0_MTU_JUMBO, \
46 if (!self) 46 .mac_regs_count = 88, \
47 goto err_exit; 47 .hw_alive_check_addr = 0x10U
48 48
49 self->aq_pci_func = aq_pci_func; 49const struct aq_hw_caps_s hw_atl_b0_caps_aqc100 = {
50 DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
51 .media_type = AQ_HW_MEDIA_TYPE_FIBRE,
52 .link_speed_msk = HW_ATL_B0_RATE_10G |
53 HW_ATL_B0_RATE_5G |
54 HW_ATL_B0_RATE_2G5 |
55 HW_ATL_B0_RATE_1G |
56 HW_ATL_B0_RATE_100M,
57};
50 58
51 self->not_ff_addr = 0x10U; 59const struct aq_hw_caps_s hw_atl_b0_caps_aqc107 = {
60 DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
61 .media_type = AQ_HW_MEDIA_TYPE_TP,
62 .link_speed_msk = HW_ATL_B0_RATE_10G |
63 HW_ATL_B0_RATE_5G |
64 HW_ATL_B0_RATE_2G5 |
65 HW_ATL_B0_RATE_1G |
66 HW_ATL_B0_RATE_100M,
67};
52 68
53err_exit: 69const struct aq_hw_caps_s hw_atl_b0_caps_aqc108 = {
54 return self; 70 DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
55} 71 .media_type = AQ_HW_MEDIA_TYPE_TP,
72 .link_speed_msk = HW_ATL_B0_RATE_5G |
73 HW_ATL_B0_RATE_2G5 |
74 HW_ATL_B0_RATE_1G |
75 HW_ATL_B0_RATE_100M,
76};
56 77
57static void hw_atl_b0_destroy(struct aq_hw_s *self) 78const struct aq_hw_caps_s hw_atl_b0_caps_aqc109 = {
58{ 79 DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
59 kfree(self); 80 .media_type = AQ_HW_MEDIA_TYPE_TP,
60} 81 .link_speed_msk = HW_ATL_B0_RATE_2G5 |
82 HW_ATL_B0_RATE_1G |
83 HW_ATL_B0_RATE_100M,
84};
61 85
62static int hw_atl_b0_hw_reset(struct aq_hw_s *self) 86static int hw_atl_b0_hw_reset(struct aq_hw_s *self)
63{ 87{
64 int err = 0; 88 int err = 0;
65 89
66 hw_atl_glb_glb_reg_res_dis_set(self, 1U); 90 err = hw_atl_utils_soft_reset(self);
67 hw_atl_pci_pci_reg_res_dis_set(self, 0U); 91 if (err)
68 hw_atl_rx_rx_reg_res_dis_set(self, 0U); 92 return err;
69 hw_atl_tx_tx_reg_res_dis_set(self, 0U);
70
71 HW_ATL_FLUSH();
72 hw_atl_glb_soft_res_set(self, 1);
73 93
74 /* check 10 times by 1ms */ 94 self->aq_fw_ops->set_state(self, MPI_RESET);
75 AQ_HW_WAIT_FOR(hw_atl_glb_soft_res_get(self) == 0, 1000U, 10U);
76 if (err < 0)
77 goto err_exit;
78
79 hw_atl_itr_irq_reg_res_dis_set(self, 0U);
80 hw_atl_itr_res_irq_set(self, 1U);
81
82 /* check 10 times by 1ms */
83 AQ_HW_WAIT_FOR(hw_atl_itr_res_irq_get(self) == 0, 1000U, 10U);
84 if (err < 0)
85 goto err_exit;
86
87 hw_atl_utils_mpi_set(self, MPI_RESET, 0x0U);
88 95
89 err = aq_hw_err_from_flags(self); 96 err = aq_hw_err_from_flags(self);
90 97
91err_exit:
92 return err; 98 return err;
93} 99}
94 100
@@ -379,7 +385,8 @@ static int hw_atl_b0_hw_init(struct aq_hw_s *self, u8 *mac_addr)
379 385
380 hw_atl_b0_hw_mac_addr_set(self, mac_addr); 386 hw_atl_b0_hw_mac_addr_set(self, mac_addr);
381 387
382 hw_atl_utils_mpi_set(self, MPI_INIT, aq_nic_cfg->link_speed_msk); 388 self->aq_fw_ops->set_link_speed(self, aq_nic_cfg->link_speed_msk);
389 self->aq_fw_ops->set_state(self, MPI_INIT);
383 390
384 hw_atl_b0_hw_qos_set(self); 391 hw_atl_b0_hw_qos_set(self);
385 hw_atl_b0_hw_rss_set(self, &aq_nic_cfg->aq_rss); 392 hw_atl_b0_hw_rss_set(self, &aq_nic_cfg->aq_rss);
@@ -398,7 +405,7 @@ static int hw_atl_b0_hw_init(struct aq_hw_s *self, u8 *mac_addr)
398 405
399 /* Reset link status and read out initial hardware counters */ 406 /* Reset link status and read out initial hardware counters */
400 self->aq_link_status.mbps = 0; 407 self->aq_link_status.mbps = 0;
401 hw_atl_utils_update_stats(self); 408 self->aq_fw_ops->update_stats(self);
402 409
403 err = aq_hw_err_from_flags(self); 410 err = aq_hw_err_from_flags(self);
404 if (err < 0) 411 if (err < 0)
@@ -923,27 +930,8 @@ static int hw_atl_b0_hw_ring_rx_stop(struct aq_hw_s *self,
923 return aq_hw_err_from_flags(self); 930 return aq_hw_err_from_flags(self);
924} 931}
925 932
926static int hw_atl_b0_hw_set_speed(struct aq_hw_s *self, u32 speed) 933const struct aq_hw_ops hw_atl_ops_b0 = {
927{
928 int err = 0;
929
930 err = hw_atl_utils_mpi_set_speed(self, speed, MPI_INIT);
931 if (err < 0)
932 goto err_exit;
933
934err_exit:
935 return err;
936}
937
938static const struct aq_hw_ops hw_atl_ops_ = {
939 .create = hw_atl_b0_create,
940 .destroy = hw_atl_b0_destroy,
941 .get_hw_caps = hw_atl_b0_get_hw_caps,
942
943 .hw_get_mac_permanent = hw_atl_utils_get_mac_permanent,
944 .hw_set_mac_address = hw_atl_b0_hw_mac_addr_set, 934 .hw_set_mac_address = hw_atl_b0_hw_mac_addr_set,
945 .hw_get_link_status = hw_atl_utils_mpi_get_link_status,
946 .hw_set_link_speed = hw_atl_b0_hw_set_speed,
947 .hw_init = hw_atl_b0_hw_init, 935 .hw_init = hw_atl_b0_hw_init,
948 .hw_deinit = hw_atl_utils_hw_deinit, 936 .hw_deinit = hw_atl_utils_hw_deinit,
949 .hw_set_power = hw_atl_utils_hw_set_power, 937 .hw_set_power = hw_atl_utils_hw_set_power,
@@ -973,21 +961,6 @@ static const struct aq_hw_ops hw_atl_ops_ = {
973 .hw_rss_set = hw_atl_b0_hw_rss_set, 961 .hw_rss_set = hw_atl_b0_hw_rss_set,
974 .hw_rss_hash_set = hw_atl_b0_hw_rss_hash_set, 962 .hw_rss_hash_set = hw_atl_b0_hw_rss_hash_set,
975 .hw_get_regs = hw_atl_utils_hw_get_regs, 963 .hw_get_regs = hw_atl_utils_hw_get_regs,
976 .hw_update_stats = hw_atl_utils_update_stats,
977 .hw_get_hw_stats = hw_atl_utils_get_hw_stats, 964 .hw_get_hw_stats = hw_atl_utils_get_hw_stats,
978 .hw_get_fw_version = hw_atl_utils_get_fw_version, 965 .hw_get_fw_version = hw_atl_utils_get_fw_version,
979}; 966};
980
981const struct aq_hw_ops *hw_atl_b0_get_ops_by_id(struct pci_dev *pdev)
982{
983 bool is_vid_ok = (pdev->vendor == PCI_VENDOR_ID_AQUANTIA);
984 bool is_did_ok = ((pdev->device == HW_ATL_DEVICE_ID_0001) ||
985 (pdev->device == HW_ATL_DEVICE_ID_D100) ||
986 (pdev->device == HW_ATL_DEVICE_ID_D107) ||
987 (pdev->device == HW_ATL_DEVICE_ID_D108) ||
988 (pdev->device == HW_ATL_DEVICE_ID_D109));
989
990 bool is_rev_ok = (pdev->revision == 2U);
991
992 return (is_vid_ok && is_did_ok && is_rev_ok) ? &hw_atl_ops_ : NULL;
993}
diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.h
index 3e10969c1df5..2cc8dacfdc27 100644
--- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.h
+++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.h
@@ -16,19 +16,27 @@
16 16
17#include "../aq_common.h" 17#include "../aq_common.h"
18 18
19#ifndef PCI_VENDOR_ID_AQUANTIA 19extern const struct aq_hw_caps_s hw_atl_b0_caps_aqc100;
20extern const struct aq_hw_caps_s hw_atl_b0_caps_aqc107;
21extern const struct aq_hw_caps_s hw_atl_b0_caps_aqc108;
22extern const struct aq_hw_caps_s hw_atl_b0_caps_aqc109;
20 23
21#define PCI_VENDOR_ID_AQUANTIA 0x1D6A 24#define hw_atl_b0_caps_aqc111 hw_atl_b0_caps_aqc108
22#define HW_ATL_DEVICE_ID_0001 0x0001 25#define hw_atl_b0_caps_aqc112 hw_atl_b0_caps_aqc109
23#define HW_ATL_DEVICE_ID_D100 0xD100
24#define HW_ATL_DEVICE_ID_D107 0xD107
25#define HW_ATL_DEVICE_ID_D108 0xD108
26#define HW_ATL_DEVICE_ID_D109 0xD109
27 26
28#define HW_ATL_NIC_NAME "aQuantia AQtion 5Gbit Network Adapter" 27#define hw_atl_b0_caps_aqc100s hw_atl_b0_caps_aqc100
28#define hw_atl_b0_caps_aqc107s hw_atl_b0_caps_aqc107
29#define hw_atl_b0_caps_aqc108s hw_atl_b0_caps_aqc108
30#define hw_atl_b0_caps_aqc109s hw_atl_b0_caps_aqc109
29 31
30#endif 32#define hw_atl_b0_caps_aqc111s hw_atl_b0_caps_aqc108
33#define hw_atl_b0_caps_aqc112s hw_atl_b0_caps_aqc109
31 34
32const struct aq_hw_ops *hw_atl_b0_get_ops_by_id(struct pci_dev *pdev); 35#define hw_atl_b0_caps_aqc111e hw_atl_b0_caps_aqc108
36#define hw_atl_b0_caps_aqc112e hw_atl_b0_caps_aqc109
37
38extern const struct aq_hw_ops hw_atl_ops_b0;
39
40#define hw_atl_ops_b1 hw_atl_ops_b0
33 41
34#endif /* HW_ATL_B0_H */ 42#endif /* HW_ATL_B0_H */
diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0_internal.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0_internal.h
index 740ff73c6d67..405d1455c222 100644
--- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0_internal.h
+++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0_internal.h
@@ -143,38 +143,5 @@
143#define HW_ATL_INTR_MODER_MIN 0xFF 143#define HW_ATL_INTR_MODER_MIN 0xFF
144 144
145/* HW layer capabilities */ 145/* HW layer capabilities */
146static struct aq_hw_caps_s hw_atl_b0_hw_caps_ = {
147 .ports = 1U,
148 .is_64_dma = true,
149 .msix_irqs = 4U,
150 .irq_mask = ~0U,
151 .vecs = HW_ATL_B0_RSS_MAX,
152 .tcs = HW_ATL_B0_TC_MAX,
153 .rxd_alignment = 1U,
154 .rxd_size = HW_ATL_B0_RXD_SIZE,
155 .rxds = 8U * 1024U,
156 .txd_alignment = 1U,
157 .txd_size = HW_ATL_B0_TXD_SIZE,
158 .txds = 8U * 1024U,
159 .txhwb_alignment = 4096U,
160 .tx_rings = HW_ATL_B0_TX_RINGS,
161 .rx_rings = HW_ATL_B0_RX_RINGS,
162 .hw_features = NETIF_F_HW_CSUM |
163 NETIF_F_RXCSUM |
164 NETIF_F_RXHASH |
165 NETIF_F_SG |
166 NETIF_F_TSO |
167 NETIF_F_LRO,
168 .hw_priv_flags = IFF_UNICAST_FLT,
169 .link_speed_msk = (HW_ATL_B0_RATE_10G |
170 HW_ATL_B0_RATE_5G |
171 HW_ATL_B0_RATE_2G5 |
172 HW_ATL_B0_RATE_1G |
173 HW_ATL_B0_RATE_100M),
174 .flow_control = true,
175 .mtu = HW_ATL_B0_MTU_JUMBO,
176 .mac_regs_count = 88,
177 .fw_ver_expected = HW_ATL_B0_FW_VER_EXPECTED,
178};
179 146
180#endif /* HW_ATL_B0_INTERNAL_H */ 147#endif /* HW_ATL_B0_INTERNAL_H */
diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c
index 9c7e9161b4db..967f0fd07fcf 100644
--- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c
+++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c
@@ -13,25 +13,230 @@
13 13
14#include "../aq_nic.h" 14#include "../aq_nic.h"
15#include "../aq_hw_utils.h" 15#include "../aq_hw_utils.h"
16#include "../aq_pci_func.h"
17#include "hw_atl_utils.h" 16#include "hw_atl_utils.h"
18#include "hw_atl_llh.h" 17#include "hw_atl_llh.h"
18#include "hw_atl_llh_internal.h"
19 19
20#include <linux/random.h> 20#include <linux/random.h>
21 21
22#define HW_ATL_UCP_0X370_REG 0x0370U 22#define HW_ATL_UCP_0X370_REG 0x0370U
23 23
24#define HW_ATL_FW_SM_RAM 0x2U 24#define HW_ATL_FW_SM_RAM 0x2U
25#define HW_ATL_MPI_FW_VERSION 0x18
25#define HW_ATL_MPI_CONTROL_ADR 0x0368U 26#define HW_ATL_MPI_CONTROL_ADR 0x0368U
26#define HW_ATL_MPI_STATE_ADR 0x036CU 27#define HW_ATL_MPI_STATE_ADR 0x036CU
27 28
28#define HW_ATL_MPI_STATE_MSK 0x00FFU 29#define HW_ATL_MPI_STATE_MSK 0x00FFU
29#define HW_ATL_MPI_STATE_SHIFT 0U 30#define HW_ATL_MPI_STATE_SHIFT 0U
30#define HW_ATL_MPI_SPEED_MSK 0xFFFFU 31#define HW_ATL_MPI_SPEED_MSK 0xFFFF0000U
31#define HW_ATL_MPI_SPEED_SHIFT 16U 32#define HW_ATL_MPI_SPEED_SHIFT 16U
32 33
33static int hw_atl_utils_fw_downld_dwords(struct aq_hw_s *self, u32 a, 34#define HW_ATL_MPI_DAISY_CHAIN_STATUS 0x704
34 u32 *p, u32 cnt) 35#define HW_ATL_MPI_BOOT_EXIT_CODE 0x388
36
37#define HW_ATL_MAC_PHY_CONTROL 0x4000
38#define HW_ATL_MAC_PHY_MPI_RESET_BIT 0x1D
39
40#define HW_ATL_FW_VER_1X 0x01050006U
41#define HW_ATL_FW_VER_2X 0x02000000U
42#define HW_ATL_FW_VER_3X 0x03000000U
43
44#define FORCE_FLASHLESS 0
45
46static int hw_atl_utils_ver_match(u32 ver_expected, u32 ver_actual);
47
48int hw_atl_utils_initfw(struct aq_hw_s *self, const struct aq_fw_ops **fw_ops)
49{
50 int err = 0;
51
52 err = hw_atl_utils_soft_reset(self);
53 if (err)
54 return err;
55
56 hw_atl_utils_hw_chip_features_init(self,
57 &self->chip_features);
58
59 hw_atl_utils_get_fw_version(self, &self->fw_ver_actual);
60
61 if (hw_atl_utils_ver_match(HW_ATL_FW_VER_1X,
62 self->fw_ver_actual) == 0) {
63 *fw_ops = &aq_fw_1x_ops;
64 } else if (hw_atl_utils_ver_match(HW_ATL_FW_VER_2X,
65 self->fw_ver_actual) == 0) {
66 *fw_ops = &aq_fw_2x_ops;
67 } else if (hw_atl_utils_ver_match(HW_ATL_FW_VER_3X,
68 self->fw_ver_actual) == 0) {
69 *fw_ops = &aq_fw_2x_ops;
70 } else {
71 aq_pr_err("Bad FW version detected: %x\n",
72 self->fw_ver_actual);
73 return -EOPNOTSUPP;
74 }
75 self->aq_fw_ops = *fw_ops;
76 err = self->aq_fw_ops->init(self);
77 return err;
78}
79
80static int hw_atl_utils_soft_reset_flb(struct aq_hw_s *self)
81{
82 int k = 0;
83 u32 gsr;
84
85 aq_hw_write_reg(self, 0x404, 0x40e1);
86 AQ_HW_SLEEP(50);
87
88 /* Cleanup SPI */
89 aq_hw_write_reg(self, 0x534, 0xA0);
90 aq_hw_write_reg(self, 0x100, 0x9F);
91 aq_hw_write_reg(self, 0x100, 0x809F);
92
93 gsr = aq_hw_read_reg(self, HW_ATL_GLB_SOFT_RES_ADR);
94 aq_hw_write_reg(self, HW_ATL_GLB_SOFT_RES_ADR, (gsr & 0xBFFF) | 0x8000);
95
96 /* Kickstart MAC */
97 aq_hw_write_reg(self, 0x404, 0x80e0);
98 aq_hw_write_reg(self, 0x32a8, 0x0);
99 aq_hw_write_reg(self, 0x520, 0x1);
100 AQ_HW_SLEEP(10);
101 aq_hw_write_reg(self, 0x404, 0x180e0);
102
103 for (k = 0; k < 1000; k++) {
104 u32 flb_status = aq_hw_read_reg(self,
105 HW_ATL_MPI_DAISY_CHAIN_STATUS);
106
107 flb_status = flb_status & 0x10;
108 if (flb_status)
109 break;
110 AQ_HW_SLEEP(10);
111 }
112 if (k == 1000) {
113 aq_pr_err("MAC kickstart failed\n");
114 return -EIO;
115 }
116
117 /* FW reset */
118 aq_hw_write_reg(self, 0x404, 0x80e0);
119 AQ_HW_SLEEP(50);
120 aq_hw_write_reg(self, 0x3a0, 0x1);
121
122 /* Kickstart PHY - skipped */
123
124 /* Global software reset*/
125 hw_atl_rx_rx_reg_res_dis_set(self, 0U);
126 hw_atl_tx_tx_reg_res_dis_set(self, 0U);
127 aq_hw_write_reg_bit(self, HW_ATL_MAC_PHY_CONTROL,
128 BIT(HW_ATL_MAC_PHY_MPI_RESET_BIT),
129 HW_ATL_MAC_PHY_MPI_RESET_BIT, 0x0);
130 gsr = aq_hw_read_reg(self, HW_ATL_GLB_SOFT_RES_ADR);
131 aq_hw_write_reg(self, HW_ATL_GLB_SOFT_RES_ADR, (gsr & 0xBFFF) | 0x8000);
132
133 for (k = 0; k < 1000; k++) {
134 u32 fw_state = aq_hw_read_reg(self, HW_ATL_MPI_FW_VERSION);
135
136 if (fw_state)
137 break;
138 AQ_HW_SLEEP(10);
139 }
140 if (k == 1000) {
141 aq_pr_err("FW kickstart failed\n");
142 return -EIO;
143 }
144
145 return 0;
146}
147
148static int hw_atl_utils_soft_reset_rbl(struct aq_hw_s *self)
149{
150 u32 gsr, rbl_status;
151 int k;
152
153 aq_hw_write_reg(self, 0x404, 0x40e1);
154 aq_hw_write_reg(self, 0x3a0, 0x1);
155 aq_hw_write_reg(self, 0x32a8, 0x0);
156
157 /* Alter RBL status */
158 aq_hw_write_reg(self, 0x388, 0xDEAD);
159
160 /* Global software reset*/
161 hw_atl_rx_rx_reg_res_dis_set(self, 0U);
162 hw_atl_tx_tx_reg_res_dis_set(self, 0U);
163 aq_hw_write_reg_bit(self, HW_ATL_MAC_PHY_CONTROL,
164 BIT(HW_ATL_MAC_PHY_MPI_RESET_BIT),
165 HW_ATL_MAC_PHY_MPI_RESET_BIT, 0x0);
166 gsr = aq_hw_read_reg(self, HW_ATL_GLB_SOFT_RES_ADR);
167 aq_hw_write_reg(self, HW_ATL_GLB_SOFT_RES_ADR,
168 (gsr & 0xFFFFBFFF) | 0x8000);
169
170 if (FORCE_FLASHLESS)
171 aq_hw_write_reg(self, 0x534, 0x0);
172
173 aq_hw_write_reg(self, 0x404, 0x40e0);
174
175 /* Wait for RBL boot */
176 for (k = 0; k < 1000; k++) {
177 rbl_status = aq_hw_read_reg(self, 0x388) & 0xFFFF;
178 if (rbl_status && rbl_status != 0xDEAD)
179 break;
180 AQ_HW_SLEEP(10);
181 }
182 if (!rbl_status || rbl_status == 0xDEAD) {
183 aq_pr_err("RBL Restart failed");
184 return -EIO;
185 }
186
187 /* Restore NVR */
188 if (FORCE_FLASHLESS)
189 aq_hw_write_reg(self, 0x534, 0xA0);
190
191 if (rbl_status == 0xF1A7) {
192 aq_pr_err("No FW detected. Dynamic FW load not implemented\n");
193 return -ENOTSUPP;
194 }
195
196 for (k = 0; k < 1000; k++) {
197 u32 fw_state = aq_hw_read_reg(self, HW_ATL_MPI_FW_VERSION);
198
199 if (fw_state)
200 break;
201 AQ_HW_SLEEP(10);
202 }
203 if (k == 1000) {
204 aq_pr_err("FW kickstart failed\n");
205 return -EIO;
206 }
207
208 return 0;
209}
210
211int hw_atl_utils_soft_reset(struct aq_hw_s *self)
212{
213 int k;
214 u32 boot_exit_code = 0;
215
216 for (k = 0; k < 1000; ++k) {
217 u32 flb_status = aq_hw_read_reg(self,
218 HW_ATL_MPI_DAISY_CHAIN_STATUS);
219 boot_exit_code = aq_hw_read_reg(self,
220 HW_ATL_MPI_BOOT_EXIT_CODE);
221 if (flb_status != 0x06000000 || boot_exit_code != 0)
222 break;
223 }
224
225 if (k == 1000) {
226 aq_pr_err("Neither RBL nor FLB firmware started\n");
227 return -EOPNOTSUPP;
228 }
229
230 self->rbl_enabled = (boot_exit_code != 0);
231
232 if (self->rbl_enabled)
233 return hw_atl_utils_soft_reset_rbl(self);
234 else
235 return hw_atl_utils_soft_reset_flb(self);
236}
237
238int hw_atl_utils_fw_downld_dwords(struct aq_hw_s *self, u32 a,
239 u32 *p, u32 cnt)
35{ 240{
36 int err = 0; 241 int err = 0;
37 242
@@ -137,14 +342,6 @@ static int hw_atl_utils_init_ucp(struct aq_hw_s *self,
137 AQ_HW_WAIT_FOR(0U != (self->mbox_addr = 342 AQ_HW_WAIT_FOR(0U != (self->mbox_addr =
138 aq_hw_read_reg(self, 0x360U)), 1000U, 10U); 343 aq_hw_read_reg(self, 0x360U)), 1000U, 10U);
139 344
140 err = hw_atl_utils_ver_match(aq_hw_caps->fw_ver_expected,
141 aq_hw_read_reg(self, 0x18U));
142
143 if (err < 0)
144 pr_err("%s: Bad FW version detected: expected=%x, actual=%x\n",
145 AQ_CFG_DRV_NAME,
146 aq_hw_caps->fw_ver_expected,
147 aq_hw_read_reg(self, 0x18U));
148 return err; 345 return err;
149} 346}
150 347
@@ -286,19 +483,19 @@ void hw_atl_utils_mpi_read_stats(struct aq_hw_s *self,
286err_exit:; 483err_exit:;
287} 484}
288 485
289int hw_atl_utils_mpi_set_speed(struct aq_hw_s *self, u32 speed, 486int hw_atl_utils_mpi_set_speed(struct aq_hw_s *self, u32 speed)
290 enum hal_atl_utils_fw_state_e state)
291{ 487{
292 u32 ucp_0x368 = 0; 488 u32 val = aq_hw_read_reg(self, HW_ATL_MPI_CONTROL_ADR);
293 489
294 ucp_0x368 = (speed << HW_ATL_MPI_SPEED_SHIFT) | state; 490 val = (val & HW_ATL_MPI_STATE_MSK) | (speed << HW_ATL_MPI_SPEED_SHIFT);
295 aq_hw_write_reg(self, HW_ATL_MPI_CONTROL_ADR, ucp_0x368); 491 aq_hw_write_reg(self, HW_ATL_MPI_CONTROL_ADR, val);
296 492
297 return 0; 493 return 0;
298} 494}
299 495
300void hw_atl_utils_mpi_set(struct aq_hw_s *self, 496void hw_atl_utils_mpi_set(struct aq_hw_s *self,
301 enum hal_atl_utils_fw_state_e state, u32 speed) 497 enum hal_atl_utils_fw_state_e state,
498 u32 speed)
302{ 499{
303 int err = 0; 500 int err = 0;
304 u32 transaction_id = 0; 501 u32 transaction_id = 0;
@@ -317,11 +514,22 @@ void hw_atl_utils_mpi_set(struct aq_hw_s *self,
317 goto err_exit; 514 goto err_exit;
318 } 515 }
319 516
320 err = hw_atl_utils_mpi_set_speed(self, speed, state); 517 aq_hw_write_reg(self, HW_ATL_MPI_CONTROL_ADR,
518 (speed << HW_ATL_MPI_SPEED_SHIFT) | state);
321 519
322err_exit:; 520err_exit:;
323} 521}
324 522
523static int hw_atl_utils_mpi_set_state(struct aq_hw_s *self,
524 enum hal_atl_utils_fw_state_e state)
525{
526 u32 val = aq_hw_read_reg(self, HW_ATL_MPI_CONTROL_ADR);
527
528 val = state | (val & HW_ATL_MPI_SPEED_MSK);
529 aq_hw_write_reg(self, HW_ATL_MPI_CONTROL_ADR, val);
530 return 0;
531}
532
325int hw_atl_utils_mpi_get_link_status(struct aq_hw_s *self) 533int hw_atl_utils_mpi_get_link_status(struct aq_hw_s *self)
326{ 534{
327 u32 cp0x036C = aq_hw_read_reg(self, HW_ATL_MPI_STATE_ADR); 535 u32 cp0x036C = aq_hw_read_reg(self, HW_ATL_MPI_STATE_ADR);
@@ -369,15 +577,6 @@ int hw_atl_utils_get_mac_permanent(struct aq_hw_s *self,
369 u32 l = 0U; 577 u32 l = 0U;
370 u32 mac_addr[2]; 578 u32 mac_addr[2];
371 579
372 self->mmio = aq_pci_func_get_mmio(self->aq_pci_func);
373
374 hw_atl_utils_hw_chip_features_init(self,
375 &self->chip_features);
376
377 err = hw_atl_utils_mpi_create(self);
378 if (err < 0)
379 goto err_exit;
380
381 if (!aq_hw_read_reg(self, HW_ATL_UCP_0X370_REG)) { 580 if (!aq_hw_read_reg(self, HW_ATL_UCP_0X370_REG)) {
382 unsigned int rnd = 0; 581 unsigned int rnd = 0;
383 unsigned int ucp_0x370 = 0; 582 unsigned int ucp_0x370 = 0;
@@ -423,7 +622,6 @@ int hw_atl_utils_get_mac_permanent(struct aq_hw_s *self,
423 mac[0] = (u8)(0xFFU & h); 622 mac[0] = (u8)(0xFFU & h);
424 } 623 }
425 624
426err_exit:
427 return err; 625 return err;
428} 626}
429 627
@@ -571,7 +769,7 @@ int hw_atl_utils_hw_get_regs(struct aq_hw_s *self,
571 769
572 for (i = 0; i < aq_hw_caps->mac_regs_count; i++) 770 for (i = 0; i < aq_hw_caps->mac_regs_count; i++)
573 regs_buff[i] = aq_hw_read_reg(self, 771 regs_buff[i] = aq_hw_read_reg(self,
574 hw_atl_utils_hw_mac_regs[i]); 772 hw_atl_utils_hw_mac_regs[i]);
575 return 0; 773 return 0;
576} 774}
577 775
@@ -580,3 +778,13 @@ int hw_atl_utils_get_fw_version(struct aq_hw_s *self, u32 *fw_version)
580 *fw_version = aq_hw_read_reg(self, 0x18U); 778 *fw_version = aq_hw_read_reg(self, 0x18U);
581 return 0; 779 return 0;
582} 780}
781
782const struct aq_fw_ops aq_fw_1x_ops = {
783 .init = hw_atl_utils_mpi_create,
784 .reset = NULL,
785 .get_mac_permanent = hw_atl_utils_get_mac_permanent,
786 .set_link_speed = hw_atl_utils_mpi_set_speed,
787 .set_state = hw_atl_utils_mpi_set_state,
788 .update_link_status = hw_atl_utils_mpi_get_link_status,
789 .update_stats = hw_atl_utils_update_stats,
790};
diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h
index 40e2319c65d5..2c690947910a 100644
--- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h
+++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.h
@@ -163,7 +163,7 @@ struct __packed hw_aq_atl_utils_mbox {
163#define HAL_ATLANTIC_UTILS_CHIP_REVISION_B0 0x02000000U 163#define HAL_ATLANTIC_UTILS_CHIP_REVISION_B0 0x02000000U
164 164
165#define IS_CHIP_FEATURE(_F_) (HAL_ATLANTIC_UTILS_CHIP_##_F_ & \ 165#define IS_CHIP_FEATURE(_F_) (HAL_ATLANTIC_UTILS_CHIP_##_F_ & \
166 self->chip_features) 166 self->chip_features)
167 167
168enum hal_atl_utils_fw_state_e { 168enum hal_atl_utils_fw_state_e {
169 MPI_DEINIT = 0, 169 MPI_DEINIT = 0,
@@ -180,10 +180,73 @@ enum hal_atl_utils_fw_state_e {
180#define HAL_ATLANTIC_RATE_100M BIT(5) 180#define HAL_ATLANTIC_RATE_100M BIT(5)
181#define HAL_ATLANTIC_RATE_INVALID BIT(6) 181#define HAL_ATLANTIC_RATE_INVALID BIT(6)
182 182
183enum hw_atl_fw2x_rate {
184 FW2X_RATE_100M = 0x20,
185 FW2X_RATE_1G = 0x100,
186 FW2X_RATE_2G5 = 0x200,
187 FW2X_RATE_5G = 0x400,
188 FW2X_RATE_10G = 0x800,
189};
190
191enum hw_atl_fw2x_caps_lo {
192 CAPS_LO_10BASET_HD = 0x00,
193 CAPS_LO_10BASET_FD,
194 CAPS_LO_100BASETX_HD,
195 CAPS_LO_100BASET4_HD,
196 CAPS_LO_100BASET2_HD,
197 CAPS_LO_100BASETX_FD,
198 CAPS_LO_100BASET2_FD,
199 CAPS_LO_1000BASET_HD,
200 CAPS_LO_1000BASET_FD,
201 CAPS_LO_2P5GBASET_FD,
202 CAPS_LO_5GBASET_FD,
203 CAPS_LO_10GBASET_FD,
204};
205
206enum hw_atl_fw2x_caps_hi {
207 CAPS_HI_RESERVED1 = 0x00,
208 CAPS_HI_10BASET_EEE,
209 CAPS_HI_RESERVED2,
210 CAPS_HI_PAUSE,
211 CAPS_HI_ASYMMETRIC_PAUSE,
212 CAPS_HI_100BASETX_EEE,
213 CAPS_HI_RESERVED3,
214 CAPS_HI_RESERVED4,
215 CAPS_HI_1000BASET_FD_EEE,
216 CAPS_HI_2P5GBASET_FD_EEE,
217 CAPS_HI_5GBASET_FD_EEE,
218 CAPS_HI_10GBASET_FD_EEE,
219 CAPS_HI_RESERVED5,
220 CAPS_HI_RESERVED6,
221 CAPS_HI_RESERVED7,
222 CAPS_HI_RESERVED8,
223 CAPS_HI_RESERVED9,
224 CAPS_HI_CABLE_DIAG,
225 CAPS_HI_TEMPERATURE,
226 CAPS_HI_DOWNSHIFT,
227 CAPS_HI_PTP_AVB_EN,
228 CAPS_HI_MEDIA_DETECT,
229 CAPS_HI_LINK_DROP,
230 CAPS_HI_SLEEP_PROXY,
231 CAPS_HI_WOL,
232 CAPS_HI_MAC_STOP,
233 CAPS_HI_EXT_LOOPBACK,
234 CAPS_HI_INT_LOOPBACK,
235 CAPS_HI_EFUSE_AGENT,
236 CAPS_HI_WOL_TIMER,
237 CAPS_HI_STATISTICS,
238 CAPS_HI_TRANSACTION_ID,
239};
240
183struct aq_hw_s; 241struct aq_hw_s;
242struct aq_fw_ops;
184struct aq_hw_caps_s; 243struct aq_hw_caps_s;
185struct aq_hw_link_status_s; 244struct aq_hw_link_status_s;
186 245
246int hw_atl_utils_initfw(struct aq_hw_s *self, const struct aq_fw_ops **fw_ops);
247
248int hw_atl_utils_soft_reset(struct aq_hw_s *self);
249
187void hw_atl_utils_hw_chip_features_init(struct aq_hw_s *self, u32 *p); 250void hw_atl_utils_hw_chip_features_init(struct aq_hw_s *self, u32 *p);
188 251
189int hw_atl_utils_mpi_read_mbox(struct aq_hw_s *self, 252int hw_atl_utils_mpi_read_mbox(struct aq_hw_s *self,
@@ -196,9 +259,6 @@ void hw_atl_utils_mpi_set(struct aq_hw_s *self,
196 enum hal_atl_utils_fw_state_e state, 259 enum hal_atl_utils_fw_state_e state,
197 u32 speed); 260 u32 speed);
198 261
199int hw_atl_utils_mpi_set_speed(struct aq_hw_s *self, u32 speed,
200 enum hal_atl_utils_fw_state_e state);
201
202int hw_atl_utils_mpi_get_link_status(struct aq_hw_s *self); 262int hw_atl_utils_mpi_get_link_status(struct aq_hw_s *self);
203 263
204int hw_atl_utils_get_mac_permanent(struct aq_hw_s *self, 264int hw_atl_utils_get_mac_permanent(struct aq_hw_s *self,
@@ -220,5 +280,10 @@ int hw_atl_utils_get_fw_version(struct aq_hw_s *self, u32 *fw_version);
220int hw_atl_utils_update_stats(struct aq_hw_s *self); 280int hw_atl_utils_update_stats(struct aq_hw_s *self);
221 281
222struct aq_stats_s *hw_atl_utils_get_hw_stats(struct aq_hw_s *self); 282struct aq_stats_s *hw_atl_utils_get_hw_stats(struct aq_hw_s *self);
283int hw_atl_utils_fw_downld_dwords(struct aq_hw_s *self, u32 a,
284 u32 *p, u32 cnt);
285
286extern const struct aq_fw_ops aq_fw_1x_ops;
287extern const struct aq_fw_ops aq_fw_2x_ops;
223 288
224#endif /* HW_ATL_UTILS_H */ 289#endif /* HW_ATL_UTILS_H */
diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c
new file mode 100644
index 000000000000..8cfce95c82fc
--- /dev/null
+++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c
@@ -0,0 +1,184 @@
1/*
2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10/* File hw_atl_utils_fw2x.c: Definition of firmware 2.x functions for
11 * Atlantic hardware abstraction layer.
12 */
13
14#include "../aq_hw.h"
15#include "../aq_hw_utils.h"
16#include "../aq_pci_func.h"
17#include "../aq_ring.h"
18#include "../aq_vec.h"
19#include "hw_atl_utils.h"
20#include "hw_atl_llh.h"
21
22#define HW_ATL_FW2X_MPI_EFUSE_ADDR 0x364
23#define HW_ATL_FW2X_MPI_MBOX_ADDR 0x360
24
25#define HW_ATL_FW2X_MPI_CONTROL_ADDR 0x368
26#define HW_ATL_FW2X_MPI_CONTROL2_ADDR 0x36C
27
28#define HW_ATL_FW2X_MPI_STATE_ADDR 0x370
29#define HW_ATL_FW2X_MPI_STATE2_ADDR 0x374
30
31static int aq_fw2x_init(struct aq_hw_s *self)
32{
33 int err = 0;
34
35 /* check 10 times by 1ms */
36 AQ_HW_WAIT_FOR(0U != (self->mbox_addr =
37 aq_hw_read_reg(self, HW_ATL_FW2X_MPI_MBOX_ADDR)),
38 1000U, 10U);
39 return err;
40}
41
42static enum hw_atl_fw2x_rate link_speed_mask_2fw2x_ratemask(u32 speed)
43{
44 enum hw_atl_fw2x_rate rate = 0;
45
46 if (speed & AQ_NIC_RATE_10G)
47 rate |= FW2X_RATE_10G;
48
49 if (speed & AQ_NIC_RATE_5G)
50 rate |= FW2X_RATE_5G;
51
52 if (speed & AQ_NIC_RATE_5GSR)
53 rate |= FW2X_RATE_5G;
54
55 if (speed & AQ_NIC_RATE_2GS)
56 rate |= FW2X_RATE_2G5;
57
58 if (speed & AQ_NIC_RATE_1G)
59 rate |= FW2X_RATE_1G;
60
61 if (speed & AQ_NIC_RATE_100M)
62 rate |= FW2X_RATE_100M;
63
64 return rate;
65}
66
67static int aq_fw2x_set_link_speed(struct aq_hw_s *self, u32 speed)
68{
69 u32 val = link_speed_mask_2fw2x_ratemask(speed);
70
71 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR, val);
72
73 return 0;
74}
75
76static int aq_fw2x_set_state(struct aq_hw_s *self,
77 enum hal_atl_utils_fw_state_e state)
78{
79 /* No explicit state in 2x fw */
80 return 0;
81}
82
83static int aq_fw2x_update_link_status(struct aq_hw_s *self)
84{
85 u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE_ADDR);
86 u32 speed = mpi_state & (FW2X_RATE_100M | FW2X_RATE_1G |
87 FW2X_RATE_2G5 | FW2X_RATE_5G | FW2X_RATE_10G);
88 struct aq_hw_link_status_s *link_status = &self->aq_link_status;
89
90 if (speed) {
91 if (speed & FW2X_RATE_10G)
92 link_status->mbps = 10000;
93 else if (speed & FW2X_RATE_5G)
94 link_status->mbps = 5000;
95 else if (speed & FW2X_RATE_2G5)
96 link_status->mbps = 2500;
97 else if (speed & FW2X_RATE_1G)
98 link_status->mbps = 1000;
99 else if (speed & FW2X_RATE_100M)
100 link_status->mbps = 100;
101 else
102 link_status->mbps = 10000;
103 } else {
104 link_status->mbps = 0;
105 }
106
107 return 0;
108}
109
110int aq_fw2x_get_mac_permanent(struct aq_hw_s *self, u8 *mac)
111{
112 int err = 0;
113 u32 h = 0U;
114 u32 l = 0U;
115 u32 mac_addr[2] = { 0 };
116 u32 efuse_addr = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_EFUSE_ADDR);
117
118 if (efuse_addr != 0) {
119 err = hw_atl_utils_fw_downld_dwords(self,
120 efuse_addr + (40U * 4U),
121 mac_addr,
122 ARRAY_SIZE(mac_addr));
123 if (err)
124 return err;
125 mac_addr[0] = __swab32(mac_addr[0]);
126 mac_addr[1] = __swab32(mac_addr[1]);
127 }
128
129 ether_addr_copy(mac, (u8 *)mac_addr);
130
131 if ((mac[0] & 0x01U) || ((mac[0] | mac[1] | mac[2]) == 0x00U)) {
132 unsigned int rnd = 0;
133
134 get_random_bytes(&rnd, sizeof(unsigned int));
135
136 l = 0xE3000000U
137 | (0xFFFFU & rnd)
138 | (0x00 << 16);
139 h = 0x8001300EU;
140
141 mac[5] = (u8)(0xFFU & l);
142 l >>= 8;
143 mac[4] = (u8)(0xFFU & l);
144 l >>= 8;
145 mac[3] = (u8)(0xFFU & l);
146 l >>= 8;
147 mac[2] = (u8)(0xFFU & l);
148 mac[1] = (u8)(0xFFU & h);
149 h >>= 8;
150 mac[0] = (u8)(0xFFU & h);
151 }
152 return err;
153}
154
155static int aq_fw2x_update_stats(struct aq_hw_s *self)
156{
157 int err = 0;
158 u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
159 u32 orig_stats_val = mpi_opts & BIT(CAPS_HI_STATISTICS);
160
161 /* Toggle statistics bit for FW to update */
162 mpi_opts = mpi_opts ^ BIT(CAPS_HI_STATISTICS);
163 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
164
165 /* Wait FW to report back */
166 AQ_HW_WAIT_FOR(orig_stats_val !=
167 (aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) &
168 BIT(CAPS_HI_STATISTICS)),
169 1U, 10000U);
170 if (err)
171 return err;
172
173 return hw_atl_utils_update_stats(self);
174}
175
176const struct aq_fw_ops aq_fw_2x_ops = {
177 .init = aq_fw2x_init,
178 .reset = NULL,
179 .get_mac_permanent = aq_fw2x_get_mac_permanent,
180 .set_link_speed = aq_fw2x_set_link_speed,
181 .set_state = aq_fw2x_set_state,
182 .update_link_status = aq_fw2x_update_link_status,
183 .update_stats = aq_fw2x_update_stats,
184};
diff --git a/drivers/net/ethernet/aquantia/atlantic/ver.h b/drivers/net/ethernet/aquantia/atlantic/ver.h
index 9009f2651e70..5265b937677b 100644
--- a/drivers/net/ethernet/aquantia/atlantic/ver.h
+++ b/drivers/net/ethernet/aquantia/atlantic/ver.h
@@ -10,9 +10,9 @@
10#ifndef VER_H 10#ifndef VER_H
11#define VER_H 11#define VER_H
12 12
13#define NIC_MAJOR_DRIVER_VERSION 1 13#define NIC_MAJOR_DRIVER_VERSION 2
14#define NIC_MINOR_DRIVER_VERSION 6 14#define NIC_MINOR_DRIVER_VERSION 0
15#define NIC_BUILD_DRIVER_VERSION 13 15#define NIC_BUILD_DRIVER_VERSION 2
16#define NIC_REVISION_DRIVER_VERSION 0 16#define NIC_REVISION_DRIVER_VERSION 0
17 17
18#define AQ_CFG_DRV_VERSION_SUFFIX "-kern" 18#define AQ_CFG_DRV_VERSION_SUFFIX "-kern"
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-15 16:19:44 -0400