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-rw-r--r--drivers/pci/controller/dwc/pci-imx6.c6
-rw-r--r--drivers/pci/controller/dwc/pcie-designware.c12
-rw-r--r--drivers/pci/controller/dwc/pcie-designware.h3
3 files changed, 8 insertions, 13 deletions
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index c0867df090f5..eeacdebd9b50 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -103,8 +103,6 @@ struct imx6_pcie {
103 103
104/* PCIe Port Logic registers (memory-mapped) */ 104/* PCIe Port Logic registers (memory-mapped) */
105#define PL_OFFSET 0x700 105#define PL_OFFSET 0x700
106#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
107#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
108 106
109#define PCIE_PHY_CTRL (PL_OFFSET + 0x114) 107#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
110#define PCIE_PHY_CTRL_DATA_LOC 0 108#define PCIE_PHY_CTRL_DATA_LOC 0
@@ -831,8 +829,8 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
831 829
832err_reset_phy: 830err_reset_phy:
833 dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n", 831 dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
834 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0), 832 dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0),
835 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1)); 833 dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1));
836 imx6_pcie_reset_phy(imx6_pcie); 834 imx6_pcie_reset_phy(imx6_pcie);
837 return ret; 835 return ret;
838} 836}
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 31f6331ca46f..086e87a40316 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -14,12 +14,6 @@
14 14
15#include "pcie-designware.h" 15#include "pcie-designware.h"
16 16
17/* PCIe Port Logic registers */
18#define PLR_OFFSET 0x700
19#define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c)
20#define PCIE_PHY_DEBUG_R1_LINK_UP (0x1 << 4)
21#define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (0x1 << 29)
22
23int dw_pcie_read(void __iomem *addr, int size, u32 *val) 17int dw_pcie_read(void __iomem *addr, int size, u32 *val)
24{ 18{
25 if (!IS_ALIGNED((uintptr_t)addr, size)) { 19 if (!IS_ALIGNED((uintptr_t)addr, size)) {
@@ -334,9 +328,9 @@ int dw_pcie_link_up(struct dw_pcie *pci)
334 if (pci->ops->link_up) 328 if (pci->ops->link_up)
335 return pci->ops->link_up(pci); 329 return pci->ops->link_up(pci);
336 330
337 val = readl(pci->dbi_base + PCIE_PHY_DEBUG_R1); 331 val = readl(pci->dbi_base + PCIE_PORT_DEBUG1);
338 return ((val & PCIE_PHY_DEBUG_R1_LINK_UP) && 332 return ((val & PCIE_PORT_DEBUG1_LINK_UP) &&
339 (!(val & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING))); 333 (!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING)));
340} 334}
341 335
342void dw_pcie_setup(struct dw_pcie *pci) 336void dw_pcie_setup(struct dw_pcie *pci)
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 377f4c0b52da..b33ae13194be 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -41,6 +41,9 @@
41#define PCIE_PORT_DEBUG0 0x728 41#define PCIE_PORT_DEBUG0 0x728
42#define PORT_LOGIC_LTSSM_STATE_MASK 0x1f 42#define PORT_LOGIC_LTSSM_STATE_MASK 0x1f
43#define PORT_LOGIC_LTSSM_STATE_L0 0x11 43#define PORT_LOGIC_LTSSM_STATE_L0 0x11
44#define PCIE_PORT_DEBUG1 0x72C
45#define PCIE_PORT_DEBUG1_LINK_UP BIT(4)
46#define PCIE_PORT_DEBUG1_LINK_IN_TRAINING BIT(29)
44 47
45#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C 48#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
46#define PORT_LOGIC_SPEED_CHANGE BIT(17) 49#define PORT_LOGIC_SPEED_CHANGE BIT(17)