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-rw-r--r--arch/arm/mach-shmobile/clock-r7s72100.c4
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7779.c20
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7790.c140
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7791.c81
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7790.h25
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7790.c90
-rw-r--r--drivers/sh/clk/cpg.c38
-rw-r--r--include/linux/sh_clk.h19
8 files changed, 325 insertions, 92 deletions
diff --git a/arch/arm/mach-shmobile/clock-r7s72100.c b/arch/arm/mach-shmobile/clock-r7s72100.c
index e6ab0cd5b286..dd8ce87596de 100644
--- a/arch/arm/mach-shmobile/clock-r7s72100.c
+++ b/arch/arm/mach-shmobile/clock-r7s72100.c
@@ -176,6 +176,10 @@ static struct clk_lookup lookups[] = {
176 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), 176 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
177 177
178 /* MSTP clocks */ 178 /* MSTP clocks */
179 CLKDEV_DEV_ID("fcfee000.i2c", &mstp_clks[MSTP97]),
180 CLKDEV_DEV_ID("fcfee400.i2c", &mstp_clks[MSTP96]),
181 CLKDEV_DEV_ID("fcfee800.i2c", &mstp_clks[MSTP95]),
182 CLKDEV_DEV_ID("fcfeec00.i2c", &mstp_clks[MSTP94]),
179 CLKDEV_CON_ID("mtu2_fck", &mstp_clks[MSTP33]), 183 CLKDEV_CON_ID("mtu2_fck", &mstp_clks[MSTP33]),
180 184
181 /* ICK */ 185 /* ICK */
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index f1fb89b76786..93a562531d53 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -127,16 +127,16 @@ static struct clk mstp_clks[MSTP_NR] = {
127 [MSTP322] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 22, 0), /* SDHI1 */ 127 [MSTP322] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 22, 0), /* SDHI1 */
128 [MSTP321] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 21, 0), /* SDHI2 */ 128 [MSTP321] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 21, 0), /* SDHI2 */
129 [MSTP320] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 20, 0), /* SDHI3 */ 129 [MSTP320] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 20, 0), /* SDHI3 */
130 [MSTP120] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 20, 0), /* VIN3 */ 130 [MSTP120] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 20, MSTPSR1, 0), /* VIN3 */
131 [MSTP116] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 16, 0), /* PCIe */ 131 [MSTP116] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 16, MSTPSR1, 0), /* PCIe */
132 [MSTP115] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 15, 0), /* SATA */ 132 [MSTP115] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 15, MSTPSR1, 0), /* SATA */
133 [MSTP114] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 14, 0), /* Ether */ 133 [MSTP114] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 14, MSTPSR1, 0), /* Ether */
134 [MSTP110] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 10, 0), /* VIN0 */ 134 [MSTP110] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 10, MSTPSR1, 0), /* VIN0 */
135 [MSTP109] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 9, 0), /* VIN1 */ 135 [MSTP109] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 9, MSTPSR1, 0), /* VIN1 */
136 [MSTP108] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 8, 0), /* VIN2 */ 136 [MSTP108] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 8, MSTPSR1, 0), /* VIN2 */
137 [MSTP103] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 3, 0), /* DU */ 137 [MSTP103] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 3, MSTPSR1, 0), /* DU */
138 [MSTP101] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 1, 0), /* USB2 */ 138 [MSTP101] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 1, MSTPSR1, 0), /* USB2 */
139 [MSTP100] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 0, 0), /* USB0/1 */ 139 [MSTP100] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 0, MSTPSR1, 0), /* USB0/1 */
140 [MSTP030] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 30, 0), /* I2C0 */ 140 [MSTP030] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 30, 0), /* I2C0 */
141 [MSTP029] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 29, 0), /* I2C1 */ 141 [MSTP029] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 29, 0), /* I2C1 */
142 [MSTP028] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 28, 0), /* I2C2 */ 142 [MSTP028] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 28, 0), /* I2C2 */
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index f44987a92ad4..507073e9d455 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -43,17 +43,26 @@
43 * see "p1 / 2" on R8A7790_CLOCK_ROOT() below 43 * see "p1 / 2" on R8A7790_CLOCK_ROOT() below
44 */ 44 */
45 45
46#define CPG_BASE 0xe6150000 46#define CPG_BASE 0xe6150000
47#define CPG_LEN 0x1000 47#define CPG_LEN 0x1000
48 48
49#define SMSTPCR1 0xe6150134 49#define SMSTPCR1 0xe6150134
50#define SMSTPCR2 0xe6150138 50#define SMSTPCR2 0xe6150138
51#define SMSTPCR3 0xe615013c 51#define SMSTPCR3 0xe615013c
52#define SMSTPCR5 0xe6150144 52#define SMSTPCR5 0xe6150144
53#define SMSTPCR7 0xe615014c 53#define SMSTPCR7 0xe615014c
54#define SMSTPCR8 0xe6150990 54#define SMSTPCR8 0xe6150990
55#define SMSTPCR9 0xe6150994 55#define SMSTPCR9 0xe6150994
56#define SMSTPCR10 0xe6150998 56#define SMSTPCR10 0xe6150998
57
58#define MSTPSR1 IOMEM(0xe6150038)
59#define MSTPSR2 IOMEM(0xe6150040)
60#define MSTPSR3 IOMEM(0xe6150048)
61#define MSTPSR5 IOMEM(0xe615003c)
62#define MSTPSR7 IOMEM(0xe61501c4)
63#define MSTPSR8 IOMEM(0xe61509a0)
64#define MSTPSR9 IOMEM(0xe61509a4)
65#define MSTPSR10 IOMEM(0xe61509a8)
57 66
58#define SDCKCR 0xE6150074 67#define SDCKCR 0xE6150074
59#define SD2CKCR 0xE6150078 68#define SD2CKCR 0xE6150078
@@ -187,11 +196,14 @@ enum {
187 MSTP1009, MSTP1008, MSTP1007, MSTP1006, MSTP1005, 196 MSTP1009, MSTP1008, MSTP1007, MSTP1006, MSTP1005,
188 MSTP931, MSTP930, MSTP929, MSTP928, 197 MSTP931, MSTP930, MSTP929, MSTP928,
189 MSTP917, 198 MSTP917,
199 MSTP815, MSTP814,
190 MSTP813, 200 MSTP813,
201 MSTP811, MSTP810, MSTP809, MSTP808,
191 MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720, 202 MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720,
192 MSTP717, MSTP716, 203 MSTP717, MSTP716,
193 MSTP704, 204 MSTP704, MSTP703,
194 MSTP522, 205 MSTP522,
206 MSTP502, MSTP501,
195 MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304, 207 MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304,
196 MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, 208 MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,
197 MSTP124, 209 MSTP124,
@@ -199,48 +211,57 @@ enum {
199}; 211};
200 212
201static struct clk mstp_clks[MSTP_NR] = { 213static struct clk mstp_clks[MSTP_NR] = {
202 [MSTP1015] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 15, 0), /* SSI0 */ 214 [MSTP1015] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 15, MSTPSR10, 0), /* SSI0 */
203 [MSTP1014] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 14, 0), /* SSI1 */ 215 [MSTP1014] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 14, MSTPSR10, 0), /* SSI1 */
204 [MSTP1013] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 13, 0), /* SSI2 */ 216 [MSTP1013] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 13, MSTPSR10, 0), /* SSI2 */
205 [MSTP1012] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 12, 0), /* SSI3 */ 217 [MSTP1012] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 12, MSTPSR10, 0), /* SSI3 */
206 [MSTP1011] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 11, 0), /* SSI4 */ 218 [MSTP1011] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 11, MSTPSR10, 0), /* SSI4 */
207 [MSTP1010] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 10, 0), /* SSI5 */ 219 [MSTP1010] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 10, MSTPSR10, 0), /* SSI5 */
208 [MSTP1009] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 9, 0), /* SSI6 */ 220 [MSTP1009] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 9, MSTPSR10, 0), /* SSI6 */
209 [MSTP1008] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 8, 0), /* SSI7 */ 221 [MSTP1008] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 8, MSTPSR10, 0), /* SSI7 */
210 [MSTP1007] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 7, 0), /* SSI8 */ 222 [MSTP1007] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 7, MSTPSR10, 0), /* SSI8 */
211 [MSTP1006] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 6, 0), /* SSI9 */ 223 [MSTP1006] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 6, MSTPSR10, 0), /* SSI9 */
212 [MSTP1005] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 5, 0), /* SSI ALL */ 224 [MSTP1005] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 5, MSTPSR10, 0), /* SSI ALL */
213 [MSTP931] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 31, 0), /* I2C0 */ 225 [MSTP931] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 31, MSTPSR9, 0), /* I2C0 */
214 [MSTP930] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 30, 0), /* I2C1 */ 226 [MSTP930] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 30, MSTPSR9, 0), /* I2C1 */
215 [MSTP929] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 29, 0), /* I2C2 */ 227 [MSTP929] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */
216 [MSTP928] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 28, 0), /* I2C3 */ 228 [MSTP928] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
217 [MSTP917] = SH_CLK_MSTP32(&qspi_clk, SMSTPCR9, 17, 0), /* QSPI */ 229 [MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), /* QSPI */
218 [MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */ 230 [MSTP815] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 15, MSTPSR8, 0), /* SATA0 */
219 [MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */ 231 [MSTP814] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 14, MSTPSR8, 0), /* SATA1 */
220 [MSTP725] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 25, 0), /* LVDS1 */ 232 [MSTP813] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR8, 13, MSTPSR8, 0), /* Ether */
221 [MSTP724] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 24, 0), /* DU0 */ 233 [MSTP811] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 11, MSTPSR8, 0), /* VIN0 */
222 [MSTP723] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 23, 0), /* DU1 */ 234 [MSTP810] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 10, MSTPSR8, 0), /* VIN1 */
223 [MSTP722] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 22, 0), /* DU2 */ 235 [MSTP809] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 9, MSTPSR8, 0), /* VIN2 */
224 [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */ 236 [MSTP808] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 8, MSTPSR8, 0), /* VIN3 */
225 [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ 237 [MSTP726] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 26, MSTPSR7, 0), /* LVDS0 */
226 [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */ 238 [MSTP725] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 25, MSTPSR7, 0), /* LVDS1 */
227 [MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */ 239 [MSTP724] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 24, MSTPSR7, 0), /* DU0 */
228 [MSTP704] = SH_CLK_MSTP32(&mp_clk, SMSTPCR7, 4, 0), /* HSUSB */ 240 [MSTP723] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 23, MSTPSR7, 0), /* DU1 */
229 [MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */ 241 [MSTP722] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 22, MSTPSR7, 0), /* DU2 */
230 [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, 0), /* MMC0 */ 242 [MSTP721] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 21, MSTPSR7, 0), /* SCIF0 */
231 [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_SD0], SMSTPCR3, 14, 0), /* SDHI0 */ 243 [MSTP720] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 20, MSTPSR7, 0), /* SCIF1 */
232 [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_SD1], SMSTPCR3, 13, 0), /* SDHI1 */ 244 [MSTP717] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR7, 17, MSTPSR7, 0), /* HSCIF0 */
233 [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SD2], SMSTPCR3, 12, 0), /* SDHI2 */ 245 [MSTP716] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR7, 16, MSTPSR7, 0), /* HSCIF1 */
234 [MSTP311] = SH_CLK_MSTP32(&div6_clks[DIV6_SD3], SMSTPCR3, 11, 0), /* SDHI3 */ 246 [MSTP704] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR7, 4, MSTPSR7, 0), /* HSUSB */
235 [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1], SMSTPCR3, 5, 0), /* MMC1 */ 247 [MSTP703] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR7, 3, MSTPSR7, 0), /* EHCI */
236 [MSTP304] = SH_CLK_MSTP32(&cp_clk, SMSTPCR3, 4, 0), /* TPU0 */ 248 [MSTP522] = SH_CLK_MSTP32_STS(&extal_clk, SMSTPCR5, 22, MSTPSR5, 0), /* Thermal */
237 [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */ 249 [MSTP502] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR5, 2, MSTPSR5, 0), /* Audio-DMAC low */
238 [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */ 250 [MSTP501] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR5, 1, MSTPSR5, 0), /* Audio-DMAC hi */
239 [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */ 251 [MSTP315] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, MSTPSR3, 0), /* MMC0 */
240 [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */ 252 [MSTP314] = SH_CLK_MSTP32_STS(&div4_clks[DIV4_SD0], SMSTPCR3, 14, MSTPSR3, 0), /* SDHI0 */
241 [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */ 253 [MSTP313] = SH_CLK_MSTP32_STS(&div4_clks[DIV4_SD1], SMSTPCR3, 13, MSTPSR3, 0), /* SDHI1 */
242 [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */ 254 [MSTP312] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD2], SMSTPCR3, 12, MSTPSR3, 0), /* SDHI2 */
243 [MSTP124] = SH_CLK_MSTP32(&rclk_clk, SMSTPCR1, 24, 0), /* CMT0 */ 255 [MSTP311] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD3], SMSTPCR3, 11, MSTPSR3, 0), /* SDHI3 */
256 [MSTP305] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_MMC1], SMSTPCR3, 5, MSTPSR3, 0), /* MMC1 */
257 [MSTP304] = SH_CLK_MSTP32_STS(&cp_clk, SMSTPCR3, 4, MSTPSR3, 0), /* TPU0 */
258 [MSTP216] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 16, MSTPSR2, 0), /* SCIFB2 */
259 [MSTP207] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 7, MSTPSR2, 0), /* SCIFB1 */
260 [MSTP206] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 6, MSTPSR2, 0), /* SCIFB0 */
261 [MSTP204] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 4, MSTPSR2, 0), /* SCIFA0 */
262 [MSTP203] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 3, MSTPSR2, 0), /* SCIFA1 */
263 [MSTP202] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 2, MSTPSR2, 0), /* SCIFA2 */
264 [MSTP124] = SH_CLK_MSTP32_STS(&rclk_clk, SMSTPCR1, 24, MSTPSR1, 0), /* CMT0 */
244}; 265};
245 266
246static struct clk_lookup lookups[] = { 267static struct clk_lookup lookups[] = {
@@ -300,8 +321,14 @@ static struct clk_lookup lookups[] = {
300 CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP928]), 321 CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP928]),
301 CLKDEV_DEV_ID("i2c-rcar_gen2.3", &mstp_clks[MSTP928]), 322 CLKDEV_DEV_ID("i2c-rcar_gen2.3", &mstp_clks[MSTP928]),
302 CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]), 323 CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
324 CLKDEV_DEV_ID("r8a7790-vin.0", &mstp_clks[MSTP811]),
325 CLKDEV_DEV_ID("r8a7790-vin.1", &mstp_clks[MSTP810]),
326 CLKDEV_DEV_ID("r8a7790-vin.2", &mstp_clks[MSTP809]),
327 CLKDEV_DEV_ID("r8a7790-vin.3", &mstp_clks[MSTP808]),
303 CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]), 328 CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
304 CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), 329 CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
330 CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP502]),
331 CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP501]),
305 CLKDEV_DEV_ID("ee200000.mmc", &mstp_clks[MSTP315]), 332 CLKDEV_DEV_ID("ee200000.mmc", &mstp_clks[MSTP315]),
306 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]), 333 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
307 CLKDEV_DEV_ID("ee100000.sd", &mstp_clks[MSTP314]), 334 CLKDEV_DEV_ID("ee100000.sd", &mstp_clks[MSTP314]),
@@ -317,6 +344,11 @@ static struct clk_lookup lookups[] = {
317 CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]), 344 CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
318 CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]), 345 CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
319 CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP704]), 346 CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP704]),
347 CLKDEV_DEV_ID("pci-rcar-gen2.0", &mstp_clks[MSTP703]),
348 CLKDEV_DEV_ID("pci-rcar-gen2.1", &mstp_clks[MSTP703]),
349 CLKDEV_DEV_ID("pci-rcar-gen2.2", &mstp_clks[MSTP703]),
350 CLKDEV_DEV_ID("sata-r8a7790.0", &mstp_clks[MSTP815]),
351 CLKDEV_DEV_ID("sata-r8a7790.1", &mstp_clks[MSTP814]),
320 352
321 /* ICK */ 353 /* ICK */
322 CLKDEV_ICK_ID("usbhs", "usb_phy_rcar_gen2", &mstp_clks[MSTP704]), 354 CLKDEV_ICK_ID("usbhs", "usb_phy_rcar_gen2", &mstp_clks[MSTP704]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c
index f5461262ee25..e4e4dfac85e9 100644
--- a/arch/arm/mach-shmobile/clock-r8a7791.c
+++ b/arch/arm/mach-shmobile/clock-r8a7791.c
@@ -59,6 +59,14 @@
59#define SMSTPCR10 0xE6150998 59#define SMSTPCR10 0xE6150998
60#define SMSTPCR11 0xE615099C 60#define SMSTPCR11 0xE615099C
61 61
62#define MSTPSR1 IOMEM(0xe6150038)
63#define MSTPSR2 IOMEM(0xe6150040)
64#define MSTPSR5 IOMEM(0xe615003c)
65#define MSTPSR7 IOMEM(0xe61501c4)
66#define MSTPSR8 IOMEM(0xe61509a0)
67#define MSTPSR9 IOMEM(0xe61509a4)
68#define MSTPSR11 IOMEM(0xe61509ac)
69
62#define MODEMR 0xE6160060 70#define MODEMR 0xE6160060
63#define SDCKCR 0xE6150074 71#define SDCKCR 0xE6150074
64#define SD2CKCR 0xE6150078 72#define SD2CKCR 0xE6150078
@@ -103,7 +111,9 @@ SH_FIXED_RATIO_CLK_SET(hp_clk, pll1_clk, 1, 12);
103SH_FIXED_RATIO_CLK_SET(p_clk, pll1_clk, 1, 24); 111SH_FIXED_RATIO_CLK_SET(p_clk, pll1_clk, 1, 24);
104SH_FIXED_RATIO_CLK_SET(rclk_clk, pll1_clk, 1, (48 * 1024)); 112SH_FIXED_RATIO_CLK_SET(rclk_clk, pll1_clk, 1, (48 * 1024));
105SH_FIXED_RATIO_CLK_SET(mp_clk, pll1_div2_clk, 1, 15); 113SH_FIXED_RATIO_CLK_SET(mp_clk, pll1_div2_clk, 1, 15);
114SH_FIXED_RATIO_CLK_SET(zg_clk, pll1_clk, 1, 3);
106SH_FIXED_RATIO_CLK_SET(zx_clk, pll1_clk, 1, 3); 115SH_FIXED_RATIO_CLK_SET(zx_clk, pll1_clk, 1, 3);
116SH_FIXED_RATIO_CLK_SET(zs_clk, pll1_clk, 1, 6);
107 117
108static struct clk *main_clks[] = { 118static struct clk *main_clks[] = {
109 &extal_clk, 119 &extal_clk,
@@ -117,12 +127,17 @@ static struct clk *main_clks[] = {
117 &rclk_clk, 127 &rclk_clk,
118 &mp_clk, 128 &mp_clk,
119 &cp_clk, 129 &cp_clk,
130 &zg_clk,
120 &zx_clk, 131 &zx_clk,
132 &zs_clk,
121}; 133};
122 134
123/* MSTP */ 135/* MSTP */
124enum { 136enum {
137 MSTP931, MSTP930, MSTP929, MSTP928, MSTP927, MSTP925,
138 MSTP815, MSTP814,
125 MSTP813, 139 MSTP813,
140 MSTP811, MSTP810, MSTP809,
126 MSTP726, MSTP724, MSTP723, MSTP721, MSTP720, 141 MSTP726, MSTP724, MSTP723, MSTP721, MSTP720,
127 MSTP719, MSTP718, MSTP715, MSTP714, 142 MSTP719, MSTP718, MSTP715, MSTP714,
128 MSTP522, 143 MSTP522,
@@ -133,27 +148,38 @@ enum {
133}; 148};
134 149
135static struct clk mstp_clks[MSTP_NR] = { 150static struct clk mstp_clks[MSTP_NR] = {
136 [MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */ 151 [MSTP931] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 31, MSTPSR9, 0), /* I2C0 */
137 [MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */ 152 [MSTP930] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 30, MSTPSR9, 0), /* I2C1 */
138 [MSTP724] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 24, 0), /* DU0 */ 153 [MSTP929] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */
139 [MSTP723] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 23, 0), /* DU1 */ 154 [MSTP928] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
140 [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */ 155 [MSTP927] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 27, MSTPSR9, 0), /* I2C4 */
141 [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ 156 [MSTP925] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 25, MSTPSR9, 0), /* I2C5 */
142 [MSTP719] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 19, 0), /* SCIF2 */ 157 [MSTP815] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 15, MSTPSR8, 0), /* SATA0 */
143 [MSTP718] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 18, 0), /* SCIF3 */ 158 [MSTP814] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 14, MSTPSR8, 0), /* SATA1 */
144 [MSTP715] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 15, 0), /* SCIF4 */ 159 [MSTP813] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR8, 13, MSTPSR8, 0), /* Ether */
145 [MSTP714] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 14, 0), /* SCIF5 */ 160 [MSTP811] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 11, MSTPSR8, 0), /* VIN0 */
146 [MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */ 161 [MSTP810] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 10, MSTPSR8, 0), /* VIN1 */
147 [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */ 162 [MSTP809] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 9, MSTPSR8, 0), /* VIN2 */
148 [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */ 163 [MSTP726] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 26, MSTPSR7, 0), /* LVDS0 */
149 [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */ 164 [MSTP724] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 24, MSTPSR7, 0), /* DU0 */
150 [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */ 165 [MSTP723] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 23, MSTPSR7, 0), /* DU1 */
151 [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */ 166 [MSTP721] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 21, MSTPSR7, 0), /* SCIF0 */
152 [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */ 167 [MSTP720] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 20, MSTPSR7, 0), /* SCIF1 */
153 [MSTP1105] = SH_CLK_MSTP32(&mp_clk, SMSTPCR11, 5, 0), /* SCIFA3 */ 168 [MSTP719] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 19, MSTPSR7, 0), /* SCIF2 */
154 [MSTP1106] = SH_CLK_MSTP32(&mp_clk, SMSTPCR11, 6, 0), /* SCIFA4 */ 169 [MSTP718] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 18, MSTPSR7, 0), /* SCIF3 */
155 [MSTP1107] = SH_CLK_MSTP32(&mp_clk, SMSTPCR11, 7, 0), /* SCIFA5 */ 170 [MSTP715] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 15, MSTPSR7, 0), /* SCIF4 */
156 [MSTP124] = SH_CLK_MSTP32(&rclk_clk, SMSTPCR1, 24, 0), /* CMT0 */ 171 [MSTP714] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 14, MSTPSR7, 0), /* SCIF5 */
172 [MSTP522] = SH_CLK_MSTP32_STS(&extal_clk, SMSTPCR5, 22, MSTPSR5, 0), /* Thermal */
173 [MSTP216] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 16, MSTPSR2, 0), /* SCIFB2 */
174 [MSTP207] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 7, MSTPSR2, 0), /* SCIFB1 */
175 [MSTP206] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 6, MSTPSR2, 0), /* SCIFB0 */
176 [MSTP204] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 4, MSTPSR2, 0), /* SCIFA0 */
177 [MSTP203] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 3, MSTPSR2, 0), /* SCIFA1 */
178 [MSTP202] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 2, MSTPSR2, 0), /* SCIFA2 */
179 [MSTP1105] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 5, MSTPSR11, 0), /* SCIFA3 */
180 [MSTP1106] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 6, MSTPSR11, 0), /* SCIFA4 */
181 [MSTP1107] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 7, MSTPSR11, 0), /* SCIFA5 */
182 [MSTP124] = SH_CLK_MSTP32_STS(&rclk_clk, SMSTPCR1, 24, MSTPSR1, 0), /* CMT0 */
157}; 183};
158 184
159static struct clk_lookup lookups[] = { 185static struct clk_lookup lookups[] = {
@@ -165,6 +191,8 @@ static struct clk_lookup lookups[] = {
165 CLKDEV_CON_ID("pll1", &pll1_clk), 191 CLKDEV_CON_ID("pll1", &pll1_clk),
166 CLKDEV_CON_ID("pll1_div2", &pll1_div2_clk), 192 CLKDEV_CON_ID("pll1_div2", &pll1_div2_clk),
167 CLKDEV_CON_ID("pll3", &pll3_clk), 193 CLKDEV_CON_ID("pll3", &pll3_clk),
194 CLKDEV_CON_ID("zg", &zg_clk),
195 CLKDEV_CON_ID("zs", &zs_clk),
168 CLKDEV_CON_ID("hp", &hp_clk), 196 CLKDEV_CON_ID("hp", &hp_clk),
169 CLKDEV_CON_ID("p", &p_clk), 197 CLKDEV_CON_ID("p", &p_clk),
170 CLKDEV_CON_ID("rclk", &rclk_clk), 198 CLKDEV_CON_ID("rclk", &rclk_clk),
@@ -194,7 +222,18 @@ static struct clk_lookup lookups[] = {
194 CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]), 222 CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
195 CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]), 223 CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
196 CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), 224 CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
225 CLKDEV_DEV_ID("i2c-rcar_gen2.0", &mstp_clks[MSTP931]),
226 CLKDEV_DEV_ID("i2c-rcar_gen2.1", &mstp_clks[MSTP930]),
227 CLKDEV_DEV_ID("i2c-rcar_gen2.2", &mstp_clks[MSTP929]),
228 CLKDEV_DEV_ID("i2c-rcar_gen2.3", &mstp_clks[MSTP928]),
229 CLKDEV_DEV_ID("i2c-rcar_gen2.4", &mstp_clks[MSTP927]),
230 CLKDEV_DEV_ID("i2c-rcar_gen2.5", &mstp_clks[MSTP925]),
197 CLKDEV_DEV_ID("r8a7791-ether", &mstp_clks[MSTP813]), /* Ether */ 231 CLKDEV_DEV_ID("r8a7791-ether", &mstp_clks[MSTP813]), /* Ether */
232 CLKDEV_DEV_ID("r8a7791-vin.0", &mstp_clks[MSTP811]),
233 CLKDEV_DEV_ID("r8a7791-vin.1", &mstp_clks[MSTP810]),
234 CLKDEV_DEV_ID("r8a7791-vin.2", &mstp_clks[MSTP809]),
235 CLKDEV_DEV_ID("sata-r8a7791.0", &mstp_clks[MSTP815]),
236 CLKDEV_DEV_ID("sata-r8a7791.1", &mstp_clks[MSTP814]),
198}; 237};
199 238
200#define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31) \ 239#define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31) \
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h b/arch/arm/mach-shmobile/include/mach/r8a7790.h
index 5fbfa28b40b6..2177325af22f 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7790.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7790.h
@@ -3,6 +3,31 @@
3 3
4#include <mach/rcar-gen2.h> 4#include <mach/rcar-gen2.h>
5 5
6/* DMA slave IDs */
7enum {
8 RCAR_DMA_SLAVE_INVALID,
9 AUDIO_DMAC_SLAVE_SSI0_TX,
10 AUDIO_DMAC_SLAVE_SSI0_RX,
11 AUDIO_DMAC_SLAVE_SSI1_TX,
12 AUDIO_DMAC_SLAVE_SSI1_RX,
13 AUDIO_DMAC_SLAVE_SSI2_TX,
14 AUDIO_DMAC_SLAVE_SSI2_RX,
15 AUDIO_DMAC_SLAVE_SSI3_TX,
16 AUDIO_DMAC_SLAVE_SSI3_RX,
17 AUDIO_DMAC_SLAVE_SSI4_TX,
18 AUDIO_DMAC_SLAVE_SSI4_RX,
19 AUDIO_DMAC_SLAVE_SSI5_TX,
20 AUDIO_DMAC_SLAVE_SSI5_RX,
21 AUDIO_DMAC_SLAVE_SSI6_TX,
22 AUDIO_DMAC_SLAVE_SSI6_RX,
23 AUDIO_DMAC_SLAVE_SSI7_TX,
24 AUDIO_DMAC_SLAVE_SSI7_RX,
25 AUDIO_DMAC_SLAVE_SSI8_TX,
26 AUDIO_DMAC_SLAVE_SSI8_RX,
27 AUDIO_DMAC_SLAVE_SSI9_TX,
28 AUDIO_DMAC_SLAVE_SSI9_RX,
29};
30
6void r8a7790_add_standard_devices(void); 31void r8a7790_add_standard_devices(void);
7void r8a7790_add_dt_devices(void); 32void r8a7790_add_dt_devices(void);
8void r8a7790_clock_init(void); 33void r8a7790_clock_init(void);
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index 6ab37aa1e919..c4616f0698c6 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -24,12 +24,100 @@
24#include <linux/platform_data/gpio-rcar.h> 24#include <linux/platform_data/gpio-rcar.h>
25#include <linux/platform_data/irq-renesas-irqc.h> 25#include <linux/platform_data/irq-renesas-irqc.h>
26#include <linux/serial_sci.h> 26#include <linux/serial_sci.h>
27#include <linux/sh_dma.h>
27#include <linux/sh_timer.h> 28#include <linux/sh_timer.h>
28#include <mach/common.h> 29#include <mach/common.h>
30#include <mach/dma-register.h>
29#include <mach/irqs.h> 31#include <mach/irqs.h>
30#include <mach/r8a7790.h> 32#include <mach/r8a7790.h>
31#include <asm/mach/arch.h> 33#include <asm/mach/arch.h>
32 34
35/* Audio-DMAC */
36#define AUDIO_DMAC_SLAVE(_id, _addr, t, r) \
37{ \
38 .slave_id = AUDIO_DMAC_SLAVE_## _id ##_TX, \
39 .addr = _addr + 0x8, \
40 .chcr = CHCR_TX(XMIT_SZ_32BIT), \
41 .mid_rid = t, \
42}, { \
43 .slave_id = AUDIO_DMAC_SLAVE_## _id ##_RX, \
44 .addr = _addr + 0xc, \
45 .chcr = CHCR_RX(XMIT_SZ_32BIT), \
46 .mid_rid = r, \
47}
48
49static const struct sh_dmae_slave_config r8a7790_audio_dmac_slaves[] = {
50 AUDIO_DMAC_SLAVE(SSI0, 0xec241000, 0x01, 0x02),
51 AUDIO_DMAC_SLAVE(SSI1, 0xec241040, 0x03, 0x04),
52 AUDIO_DMAC_SLAVE(SSI2, 0xec241080, 0x05, 0x06),
53 AUDIO_DMAC_SLAVE(SSI3, 0xec2410c0, 0x07, 0x08),
54 AUDIO_DMAC_SLAVE(SSI4, 0xec241100, 0x09, 0x0a),
55 AUDIO_DMAC_SLAVE(SSI5, 0xec241140, 0x0b, 0x0c),
56 AUDIO_DMAC_SLAVE(SSI6, 0xec241180, 0x0d, 0x0e),
57 AUDIO_DMAC_SLAVE(SSI7, 0xec2411c0, 0x0f, 0x10),
58 AUDIO_DMAC_SLAVE(SSI8, 0xec241200, 0x11, 0x12),
59 AUDIO_DMAC_SLAVE(SSI9, 0xec241240, 0x13, 0x14),
60};
61
62#define DMAE_CHANNEL(a, b) \
63{ \
64 .offset = (a) - 0x20, \
65 .dmars = (a) - 0x20 + 0x40, \
66 .chclr_bit = (b), \
67 .chclr_offset = 0x80 - 0x20, \
68}
69
70static const struct sh_dmae_channel r8a7790_audio_dmac_channels[] = {
71 DMAE_CHANNEL(0x8000, 0),
72 DMAE_CHANNEL(0x8080, 1),
73 DMAE_CHANNEL(0x8100, 2),
74 DMAE_CHANNEL(0x8180, 3),
75 DMAE_CHANNEL(0x8200, 4),
76 DMAE_CHANNEL(0x8280, 5),
77 DMAE_CHANNEL(0x8300, 6),
78 DMAE_CHANNEL(0x8380, 7),
79 DMAE_CHANNEL(0x8400, 8),
80 DMAE_CHANNEL(0x8480, 9),
81 DMAE_CHANNEL(0x8500, 10),
82 DMAE_CHANNEL(0x8580, 11),
83 DMAE_CHANNEL(0x8600, 12),
84};
85
86static struct sh_dmae_pdata r8a7790_audio_dmac_platform_data = {
87 .slave = r8a7790_audio_dmac_slaves,
88 .slave_num = ARRAY_SIZE(r8a7790_audio_dmac_slaves),
89 .channel = r8a7790_audio_dmac_channels,
90 .channel_num = ARRAY_SIZE(r8a7790_audio_dmac_channels),
91 .ts_low_shift = TS_LOW_SHIFT,
92 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
93 .ts_high_shift = TS_HI_SHIFT,
94 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
95 .ts_shift = dma_ts_shift,
96 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
97 .dmaor_init = DMAOR_DME,
98 .chclr_present = 1,
99 .chclr_bitwise = 1,
100};
101
102static struct resource r8a7790_audio_dmac_resources[] = {
103 /* Channel registers and DMAOR for low */
104 DEFINE_RES_MEM(0xec700020, 0x8663 - 0x20),
105 DEFINE_RES_IRQ(gic_spi(346)),
106 DEFINE_RES_NAMED(gic_spi(320), 13, NULL, IORESOURCE_IRQ),
107
108 /* Channel registers and DMAOR for hi */
109 DEFINE_RES_MEM(0xec720020, 0x8663 - 0x20), /* hi */
110 DEFINE_RES_IRQ(gic_spi(347)),
111 DEFINE_RES_NAMED(gic_spi(333), 13, NULL, IORESOURCE_IRQ),
112};
113
114#define r8a7790_register_audio_dmac(id) \
115 platform_device_register_resndata( \
116 &platform_bus, "sh-dma-engine", id, \
117 &r8a7790_audio_dmac_resources[id * 3], 3, \
118 &r8a7790_audio_dmac_platform_data, \
119 sizeof(r8a7790_audio_dmac_platform_data))
120
33static const struct resource pfc_resources[] __initconst = { 121static const struct resource pfc_resources[] __initconst = {
34 DEFINE_RES_MEM(0xe6060000, 0x250), 122 DEFINE_RES_MEM(0xe6060000, 0x250),
35}; 123};
@@ -101,6 +189,8 @@ void __init r8a7790_pinmux_init(void)
101 r8a7790_register_i2c(1); 189 r8a7790_register_i2c(1);
102 r8a7790_register_i2c(2); 190 r8a7790_register_i2c(2);
103 r8a7790_register_i2c(3); 191 r8a7790_register_i2c(3);
192 r8a7790_register_audio_dmac(0);
193 r8a7790_register_audio_dmac(1);
104} 194}
105 195
106#define __R8A7790_SCIF(scif_type, _scscr, index, baseaddr, irq) \ 196#define __R8A7790_SCIF(scif_type, _scscr, index, baseaddr, irq) \
diff --git a/drivers/sh/clk/cpg.c b/drivers/sh/clk/cpg.c
index 1ebe67cd1833..7442bc130055 100644
--- a/drivers/sh/clk/cpg.c
+++ b/drivers/sh/clk/cpg.c
@@ -36,9 +36,47 @@ static void sh_clk_write(int value, struct clk *clk)
36 iowrite32(value, clk->mapped_reg); 36 iowrite32(value, clk->mapped_reg);
37} 37}
38 38
39static unsigned int r8(const void __iomem *addr)
40{
41 return ioread8(addr);
42}
43
44static unsigned int r16(const void __iomem *addr)
45{
46 return ioread16(addr);
47}
48
49static unsigned int r32(const void __iomem *addr)
50{
51 return ioread32(addr);
52}
53
39static int sh_clk_mstp_enable(struct clk *clk) 54static int sh_clk_mstp_enable(struct clk *clk)
40{ 55{
41 sh_clk_write(sh_clk_read(clk) & ~(1 << clk->enable_bit), clk); 56 sh_clk_write(sh_clk_read(clk) & ~(1 << clk->enable_bit), clk);
57 if (clk->status_reg) {
58 unsigned int (*read)(const void __iomem *addr);
59 int i;
60 void __iomem *mapped_status = (phys_addr_t)clk->status_reg -
61 (phys_addr_t)clk->enable_reg + clk->mapped_reg;
62
63 if (clk->flags & CLK_ENABLE_REG_8BIT)
64 read = r8;
65 else if (clk->flags & CLK_ENABLE_REG_16BIT)
66 read = r16;
67 else
68 read = r32;
69
70 for (i = 1000;
71 (read(mapped_status) & (1 << clk->enable_bit)) && i;
72 i--)
73 cpu_relax();
74 if (!i) {
75 pr_err("cpg: failed to enable %p[%d]\n",
76 clk->enable_reg, clk->enable_bit);
77 return -ETIMEDOUT;
78 }
79 }
42 return 0; 80 return 0;
43} 81}
44 82
diff --git a/include/linux/sh_clk.h b/include/linux/sh_clk.h
index 60c72395ec6b..1f208b2a1ed6 100644
--- a/include/linux/sh_clk.h
+++ b/include/linux/sh_clk.h
@@ -52,6 +52,7 @@ struct clk {
52 unsigned long flags; 52 unsigned long flags;
53 53
54 void __iomem *enable_reg; 54 void __iomem *enable_reg;
55 void __iomem *status_reg;
55 unsigned int enable_bit; 56 unsigned int enable_bit;
56 void __iomem *mapped_reg; 57 void __iomem *mapped_reg;
57 58
@@ -116,22 +117,26 @@ long clk_round_parent(struct clk *clk, unsigned long target,
116 unsigned long *best_freq, unsigned long *parent_freq, 117 unsigned long *best_freq, unsigned long *parent_freq,
117 unsigned int div_min, unsigned int div_max); 118 unsigned int div_min, unsigned int div_max);
118 119
119#define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _flags) \ 120#define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _status_reg, _flags) \
120{ \ 121{ \
121 .parent = _parent, \ 122 .parent = _parent, \
122 .enable_reg = (void __iomem *)_enable_reg, \ 123 .enable_reg = (void __iomem *)_enable_reg, \
123 .enable_bit = _enable_bit, \ 124 .enable_bit = _enable_bit, \
125 .status_reg = _status_reg, \
124 .flags = _flags, \ 126 .flags = _flags, \
125} 127}
126 128
127#define SH_CLK_MSTP32(_p, _r, _b, _f) \ 129#define SH_CLK_MSTP32(_p, _r, _b, _f) \
128 SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_32BIT) 130 SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_32BIT)
129 131
130#define SH_CLK_MSTP16(_p, _r, _b, _f) \ 132#define SH_CLK_MSTP32_STS(_p, _r, _b, _s, _f) \
131 SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_16BIT) 133 SH_CLK_MSTP(_p, _r, _b, _s, _f | CLK_ENABLE_REG_32BIT)
132 134
133#define SH_CLK_MSTP8(_p, _r, _b, _f) \ 135#define SH_CLK_MSTP16(_p, _r, _b, _f) \
134 SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_8BIT) 136 SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_16BIT)
137
138#define SH_CLK_MSTP8(_p, _r, _b, _f) \
139 SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_8BIT)
135 140
136int sh_clk_mstp_register(struct clk *clks, int nr); 141int sh_clk_mstp_register(struct clk *clks, int nr);
137 142
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-15 19:59:22 -0400