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-rw-r--r--arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi4
-rw-r--r--arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi8
-rw-r--r--arch/powerpc/boot/dts/fsl/b4si-post.dtsi15
-rw-r--r--arch/powerpc/boot/dts/fsl/p2041si-post.dtsi18
-rw-r--r--arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi8
-rw-r--r--arch/powerpc/boot/dts/fsl/p3041si-post.dtsi18
-rw-r--r--arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi8
-rw-r--r--arch/powerpc/boot/dts/fsl/p4080si-post.dtsi70
-rw-r--r--arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi16
-rw-r--r--arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi4
-rw-r--r--arch/powerpc/boot/dts/fsl/p5040si-post.dtsi18
-rw-r--r--arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi8
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi47
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi30
-rw-r--r--arch/powerpc/boot/dts/fsl/t1023si-post.dtsi16
-rw-r--r--arch/powerpc/boot/dts/fsl/t102xsi-pre.dtsi4
-rw-r--r--arch/powerpc/boot/dts/fsl/t1040si-post.dtsi44
-rw-r--r--arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi8
-rw-r--r--arch/powerpc/boot/dts/fsl/t2081si-post.dtsi22
-rw-r--r--arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi8
-rw-r--r--arch/powerpc/boot/dts/fsl/t4240si-post.dtsi61
-rw-r--r--arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi24
22 files changed, 50 insertions, 409 deletions
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
index 88d8423f8ac5..bb7b9b9f3f5f 100644
--- a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
@@ -70,14 +70,14 @@
70 cpu0: PowerPC,e6500@0 { 70 cpu0: PowerPC,e6500@0 {
71 device_type = "cpu"; 71 device_type = "cpu";
72 reg = <0 1>; 72 reg = <0 1>;
73 clocks = <&mux0>; 73 clocks = <&clockgen 1 0>;
74 next-level-cache = <&L2_1>; 74 next-level-cache = <&L2_1>;
75 fsl,portid-mapping = <0x80000000>; 75 fsl,portid-mapping = <0x80000000>;
76 }; 76 };
77 cpu1: PowerPC,e6500@2 { 77 cpu1: PowerPC,e6500@2 {
78 device_type = "cpu"; 78 device_type = "cpu";
79 reg = <2 3>; 79 reg = <2 3>;
80 clocks = <&mux0>; 80 clocks = <&clockgen 1 0>;
81 next-level-cache = <&L2_1>; 81 next-level-cache = <&L2_1>;
82 fsl,portid-mapping = <0x80000000>; 82 fsl,portid-mapping = <0x80000000>;
83 }; 83 };
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
index f3f968c51f4b..388ba1b15f8c 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
@@ -75,28 +75,28 @@
75 cpu0: PowerPC,e6500@0 { 75 cpu0: PowerPC,e6500@0 {
76 device_type = "cpu"; 76 device_type = "cpu";
77 reg = <0 1>; 77 reg = <0 1>;
78 clocks = <&mux0>; 78 clocks = <&clockgen 1 0>;
79 next-level-cache = <&L2_1>; 79 next-level-cache = <&L2_1>;
80 fsl,portid-mapping = <0x80000000>; 80 fsl,portid-mapping = <0x80000000>;
81 }; 81 };
82 cpu1: PowerPC,e6500@2 { 82 cpu1: PowerPC,e6500@2 {
83 device_type = "cpu"; 83 device_type = "cpu";
84 reg = <2 3>; 84 reg = <2 3>;
85 clocks = <&mux0>; 85 clocks = <&clockgen 1 0>;
86 next-level-cache = <&L2_1>; 86 next-level-cache = <&L2_1>;
87 fsl,portid-mapping = <0x80000000>; 87 fsl,portid-mapping = <0x80000000>;
88 }; 88 };
89 cpu2: PowerPC,e6500@4 { 89 cpu2: PowerPC,e6500@4 {
90 device_type = "cpu"; 90 device_type = "cpu";
91 reg = <4 5>; 91 reg = <4 5>;
92 clocks = <&mux0>; 92 clocks = <&clockgen 1 0>;
93 next-level-cache = <&L2_1>; 93 next-level-cache = <&L2_1>;
94 fsl,portid-mapping = <0x80000000>; 94 fsl,portid-mapping = <0x80000000>;
95 }; 95 };
96 cpu3: PowerPC,e6500@6 { 96 cpu3: PowerPC,e6500@6 {
97 device_type = "cpu"; 97 device_type = "cpu";
98 reg = <6 7>; 98 reg = <6 7>;
99 clocks = <&mux0>; 99 clocks = <&clockgen 1 0>;
100 next-level-cache = <&L2_1>; 100 next-level-cache = <&L2_1>;
101 fsl,portid-mapping = <0x80000000>; 101 fsl,portid-mapping = <0x80000000>;
102 }; 102 };
diff --git a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
index 1b33f5157c8a..4f044b41a776 100644
--- a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
@@ -398,21 +398,6 @@
398 }; 398 };
399 399
400/include/ "qoriq-clockgen2.dtsi" 400/include/ "qoriq-clockgen2.dtsi"
401 clockgen: global-utilities@e1000 {
402 compatible = "fsl,b4-clockgen", "fsl,qoriq-clockgen-2.0";
403 reg = <0xe1000 0x1000>;
404
405 mux0: mux0@0 {
406 #clock-cells = <0>;
407 reg = <0x0 0x4>;
408 compatible = "fsl,qoriq-core-mux-2.0";
409 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
410 <&pll1 0>, <&pll1 1>, <&pll1 2>;
411 clock-names = "pll0", "pll0-div2", "pll0-div4",
412 "pll1", "pll1-div2", "pll1-div4";
413 clock-output-names = "cmux0";
414 };
415 };
416 401
417 rcpm: global-utilities@e2000 { 402 rcpm: global-utilities@e2000 {
418 compatible = "fsl,b4-rcpm", "fsl,qoriq-rcpm-2.0"; 403 compatible = "fsl,b4-rcpm", "fsl,qoriq-rcpm-2.0";
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
index 51e975d7631a..872e4485dc3f 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
@@ -327,24 +327,6 @@
327/include/ "qoriq-clockgen1.dtsi" 327/include/ "qoriq-clockgen1.dtsi"
328 global-utilities@e1000 { 328 global-utilities@e1000 {
329 compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0"; 329 compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0";
330
331 mux2: mux2@40 {
332 #clock-cells = <0>;
333 reg = <0x40 0x4>;
334 compatible = "fsl,qoriq-core-mux-1.0";
335 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
336 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
337 clock-output-names = "cmux2";
338 };
339
340 mux3: mux3@60 {
341 #clock-cells = <0>;
342 reg = <0x60 0x4>;
343 compatible = "fsl,qoriq-core-mux-1.0";
344 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
345 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
346 clock-output-names = "cmux3";
347 };
348 }; 330 };
349 331
350 rcpm: global-utilities@e2000 { 332 rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
index 941274c41f21..6318962e8d14 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
@@ -89,7 +89,7 @@
89 cpu0: PowerPC,e500mc@0 { 89 cpu0: PowerPC,e500mc@0 {
90 device_type = "cpu"; 90 device_type = "cpu";
91 reg = <0>; 91 reg = <0>;
92 clocks = <&mux0>; 92 clocks = <&clockgen 1 0>;
93 next-level-cache = <&L2_0>; 93 next-level-cache = <&L2_0>;
94 fsl,portid-mapping = <0x80000000>; 94 fsl,portid-mapping = <0x80000000>;
95 L2_0: l2-cache { 95 L2_0: l2-cache {
@@ -99,7 +99,7 @@
99 cpu1: PowerPC,e500mc@1 { 99 cpu1: PowerPC,e500mc@1 {
100 device_type = "cpu"; 100 device_type = "cpu";
101 reg = <1>; 101 reg = <1>;
102 clocks = <&mux1>; 102 clocks = <&clockgen 1 1>;
103 next-level-cache = <&L2_1>; 103 next-level-cache = <&L2_1>;
104 fsl,portid-mapping = <0x40000000>; 104 fsl,portid-mapping = <0x40000000>;
105 L2_1: l2-cache { 105 L2_1: l2-cache {
@@ -109,7 +109,7 @@
109 cpu2: PowerPC,e500mc@2 { 109 cpu2: PowerPC,e500mc@2 {
110 device_type = "cpu"; 110 device_type = "cpu";
111 reg = <2>; 111 reg = <2>;
112 clocks = <&mux2>; 112 clocks = <&clockgen 1 2>;
113 next-level-cache = <&L2_2>; 113 next-level-cache = <&L2_2>;
114 fsl,portid-mapping = <0x20000000>; 114 fsl,portid-mapping = <0x20000000>;
115 L2_2: l2-cache { 115 L2_2: l2-cache {
@@ -119,7 +119,7 @@
119 cpu3: PowerPC,e500mc@3 { 119 cpu3: PowerPC,e500mc@3 {
120 device_type = "cpu"; 120 device_type = "cpu";
121 reg = <3>; 121 reg = <3>;
122 clocks = <&mux3>; 122 clocks = <&clockgen 1 3>;
123 next-level-cache = <&L2_3>; 123 next-level-cache = <&L2_3>;
124 fsl,portid-mapping = <0x10000000>; 124 fsl,portid-mapping = <0x10000000>;
125 L2_3: l2-cache { 125 L2_3: l2-cache {
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
index 187676fa8d83..81bc75aca2e0 100644
--- a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
@@ -354,24 +354,6 @@
354/include/ "qoriq-clockgen1.dtsi" 354/include/ "qoriq-clockgen1.dtsi"
355 global-utilities@e1000 { 355 global-utilities@e1000 {
356 compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0"; 356 compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0";
357
358 mux2: mux2@40 {
359 #clock-cells = <0>;
360 reg = <0x40 0x4>;
361 compatible = "fsl,qoriq-core-mux-1.0";
362 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
363 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
364 clock-output-names = "cmux2";
365 };
366
367 mux3: mux3@60 {
368 #clock-cells = <0>;
369 reg = <0x60 0x4>;
370 compatible = "fsl,qoriq-core-mux-1.0";
371 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
372 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
373 clock-output-names = "cmux3";
374 };
375 }; 357 };
376 358
377 rcpm: global-utilities@e2000 { 359 rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
index 50b73e8e638f..db92f1151a48 100644
--- a/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
@@ -90,7 +90,7 @@
90 cpu0: PowerPC,e500mc@0 { 90 cpu0: PowerPC,e500mc@0 {
91 device_type = "cpu"; 91 device_type = "cpu";
92 reg = <0>; 92 reg = <0>;
93 clocks = <&mux0>; 93 clocks = <&clockgen 1 0>;
94 next-level-cache = <&L2_0>; 94 next-level-cache = <&L2_0>;
95 fsl,portid-mapping = <0x80000000>; 95 fsl,portid-mapping = <0x80000000>;
96 L2_0: l2-cache { 96 L2_0: l2-cache {
@@ -100,7 +100,7 @@
100 cpu1: PowerPC,e500mc@1 { 100 cpu1: PowerPC,e500mc@1 {
101 device_type = "cpu"; 101 device_type = "cpu";
102 reg = <1>; 102 reg = <1>;
103 clocks = <&mux1>; 103 clocks = <&clockgen 1 1>;
104 next-level-cache = <&L2_1>; 104 next-level-cache = <&L2_1>;
105 fsl,portid-mapping = <0x40000000>; 105 fsl,portid-mapping = <0x40000000>;
106 L2_1: l2-cache { 106 L2_1: l2-cache {
@@ -110,7 +110,7 @@
110 cpu2: PowerPC,e500mc@2 { 110 cpu2: PowerPC,e500mc@2 {
111 device_type = "cpu"; 111 device_type = "cpu";
112 reg = <2>; 112 reg = <2>;
113 clocks = <&mux2>; 113 clocks = <&clockgen 1 2>;
114 next-level-cache = <&L2_2>; 114 next-level-cache = <&L2_2>;
115 fsl,portid-mapping = <0x20000000>; 115 fsl,portid-mapping = <0x20000000>;
116 L2_2: l2-cache { 116 L2_2: l2-cache {
@@ -120,7 +120,7 @@
120 cpu3: PowerPC,e500mc@3 { 120 cpu3: PowerPC,e500mc@3 {
121 device_type = "cpu"; 121 device_type = "cpu";
122 reg = <3>; 122 reg = <3>;
123 clocks = <&mux3>; 123 clocks = <&clockgen 1 3>;
124 next-level-cache = <&L2_3>; 124 next-level-cache = <&L2_3>;
125 fsl,portid-mapping = <0x10000000>; 125 fsl,portid-mapping = <0x10000000>;
126 L2_3: l2-cache { 126 L2_3: l2-cache {
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
index a0252085f858..4da49b6dd3f5 100644
--- a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
@@ -374,76 +374,6 @@
374/include/ "qoriq-clockgen1.dtsi" 374/include/ "qoriq-clockgen1.dtsi"
375 global-utilities@e1000 { 375 global-utilities@e1000 {
376 compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0"; 376 compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
377
378 pll2: pll2@840 {
379 #clock-cells = <1>;
380 reg = <0x840 0x4>;
381 compatible = "fsl,qoriq-core-pll-1.0";
382 clocks = <&sysclk>;
383 clock-output-names = "pll2", "pll2-div2";
384 };
385
386 pll3: pll3@860 {
387 #clock-cells = <1>;
388 reg = <0x860 0x4>;
389 compatible = "fsl,qoriq-core-pll-1.0";
390 clocks = <&sysclk>;
391 clock-output-names = "pll3", "pll3-div2";
392 };
393
394 mux2: mux2@40 {
395 #clock-cells = <0>;
396 reg = <0x40 0x4>;
397 compatible = "fsl,qoriq-core-mux-1.0";
398 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
399 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
400 clock-output-names = "cmux2";
401 };
402
403 mux3: mux3@60 {
404 #clock-cells = <0>;
405 reg = <0x60 0x4>;
406 compatible = "fsl,qoriq-core-mux-1.0";
407 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
408 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
409 clock-output-names = "cmux3";
410 };
411
412 mux4: mux4@80 {
413 #clock-cells = <0>;
414 reg = <0x80 0x4>;
415 compatible = "fsl,qoriq-core-mux-1.0";
416 clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
417 clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
418 clock-output-names = "cmux4";
419 };
420
421 mux5: mux5@a0 {
422 #clock-cells = <0>;
423 reg = <0xa0 0x4>;
424 compatible = "fsl,qoriq-core-mux-1.0";
425 clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
426 clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
427 clock-output-names = "cmux5";
428 };
429
430 mux6: mux6@c0 {
431 #clock-cells = <0>;
432 reg = <0xc0 0x4>;
433 compatible = "fsl,qoriq-core-mux-1.0";
434 clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
435 clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
436 clock-output-names = "cmux6";
437 };
438
439 mux7: mux7@e0 {
440 #clock-cells = <0>;
441 reg = <0xe0 0x4>;
442 compatible = "fsl,qoriq-core-mux-1.0";
443 clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
444 clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
445 clock-output-names = "cmux7";
446 };
447 }; 377 };
448 378
449 rcpm: global-utilities@e2000 { 379 rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
index d56a546b73e6..0a7c65a00e5e 100644
--- a/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
@@ -94,7 +94,7 @@
94 cpu0: PowerPC,e500mc@0 { 94 cpu0: PowerPC,e500mc@0 {
95 device_type = "cpu"; 95 device_type = "cpu";
96 reg = <0>; 96 reg = <0>;
97 clocks = <&mux0>; 97 clocks = <&clockgen 1 0>;
98 next-level-cache = <&L2_0>; 98 next-level-cache = <&L2_0>;
99 fsl,portid-mapping = <0x80000000>; 99 fsl,portid-mapping = <0x80000000>;
100 L2_0: l2-cache { 100 L2_0: l2-cache {
@@ -104,7 +104,7 @@
104 cpu1: PowerPC,e500mc@1 { 104 cpu1: PowerPC,e500mc@1 {
105 device_type = "cpu"; 105 device_type = "cpu";
106 reg = <1>; 106 reg = <1>;
107 clocks = <&mux1>; 107 clocks = <&clockgen 1 1>;
108 next-level-cache = <&L2_1>; 108 next-level-cache = <&L2_1>;
109 fsl,portid-mapping = <0x40000000>; 109 fsl,portid-mapping = <0x40000000>;
110 L2_1: l2-cache { 110 L2_1: l2-cache {
@@ -114,7 +114,7 @@
114 cpu2: PowerPC,e500mc@2 { 114 cpu2: PowerPC,e500mc@2 {
115 device_type = "cpu"; 115 device_type = "cpu";
116 reg = <2>; 116 reg = <2>;
117 clocks = <&mux2>; 117 clocks = <&clockgen 1 2>;
118 next-level-cache = <&L2_2>; 118 next-level-cache = <&L2_2>;
119 fsl,portid-mapping = <0x20000000>; 119 fsl,portid-mapping = <0x20000000>;
120 L2_2: l2-cache { 120 L2_2: l2-cache {
@@ -124,7 +124,7 @@
124 cpu3: PowerPC,e500mc@3 { 124 cpu3: PowerPC,e500mc@3 {
125 device_type = "cpu"; 125 device_type = "cpu";
126 reg = <3>; 126 reg = <3>;
127 clocks = <&mux3>; 127 clocks = <&clockgen 1 3>;
128 next-level-cache = <&L2_3>; 128 next-level-cache = <&L2_3>;
129 fsl,portid-mapping = <0x10000000>; 129 fsl,portid-mapping = <0x10000000>;
130 L2_3: l2-cache { 130 L2_3: l2-cache {
@@ -134,7 +134,7 @@
134 cpu4: PowerPC,e500mc@4 { 134 cpu4: PowerPC,e500mc@4 {
135 device_type = "cpu"; 135 device_type = "cpu";
136 reg = <4>; 136 reg = <4>;
137 clocks = <&mux4>; 137 clocks = <&clockgen 1 4>;
138 next-level-cache = <&L2_4>; 138 next-level-cache = <&L2_4>;
139 fsl,portid-mapping = <0x08000000>; 139 fsl,portid-mapping = <0x08000000>;
140 L2_4: l2-cache { 140 L2_4: l2-cache {
@@ -144,7 +144,7 @@
144 cpu5: PowerPC,e500mc@5 { 144 cpu5: PowerPC,e500mc@5 {
145 device_type = "cpu"; 145 device_type = "cpu";
146 reg = <5>; 146 reg = <5>;
147 clocks = <&mux5>; 147 clocks = <&clockgen 1 5>;
148 next-level-cache = <&L2_5>; 148 next-level-cache = <&L2_5>;
149 fsl,portid-mapping = <0x04000000>; 149 fsl,portid-mapping = <0x04000000>;
150 L2_5: l2-cache { 150 L2_5: l2-cache {
@@ -154,7 +154,7 @@
154 cpu6: PowerPC,e500mc@6 { 154 cpu6: PowerPC,e500mc@6 {
155 device_type = "cpu"; 155 device_type = "cpu";
156 reg = <6>; 156 reg = <6>;
157 clocks = <&mux6>; 157 clocks = <&clockgen 1 6>;
158 next-level-cache = <&L2_6>; 158 next-level-cache = <&L2_6>;
159 fsl,portid-mapping = <0x02000000>; 159 fsl,portid-mapping = <0x02000000>;
160 L2_6: l2-cache { 160 L2_6: l2-cache {
@@ -164,7 +164,7 @@
164 cpu7: PowerPC,e500mc@7 { 164 cpu7: PowerPC,e500mc@7 {
165 device_type = "cpu"; 165 device_type = "cpu";
166 reg = <7>; 166 reg = <7>;
167 clocks = <&mux7>; 167 clocks = <&clockgen 1 7>;
168 next-level-cache = <&L2_7>; 168 next-level-cache = <&L2_7>;
169 fsl,portid-mapping = <0x01000000>; 169 fsl,portid-mapping = <0x01000000>;
170 L2_7: l2-cache { 170 L2_7: l2-cache {
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
index bfba0b4f1cbb..2d74ea85e5df 100644
--- a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
@@ -96,7 +96,7 @@
96 cpu0: PowerPC,e5500@0 { 96 cpu0: PowerPC,e5500@0 {
97 device_type = "cpu"; 97 device_type = "cpu";
98 reg = <0>; 98 reg = <0>;
99 clocks = <&mux0>; 99 clocks = <&clockgen 1 0>;
100 next-level-cache = <&L2_0>; 100 next-level-cache = <&L2_0>;
101 fsl,portid-mapping = <0x80000000>; 101 fsl,portid-mapping = <0x80000000>;
102 L2_0: l2-cache { 102 L2_0: l2-cache {
@@ -106,7 +106,7 @@
106 cpu1: PowerPC,e5500@1 { 106 cpu1: PowerPC,e5500@1 {
107 device_type = "cpu"; 107 device_type = "cpu";
108 reg = <1>; 108 reg = <1>;
109 clocks = <&mux1>; 109 clocks = <&clockgen 1 1>;
110 next-level-cache = <&L2_1>; 110 next-level-cache = <&L2_1>;
111 fsl,portid-mapping = <0x40000000>; 111 fsl,portid-mapping = <0x40000000>;
112 L2_1: l2-cache { 112 L2_1: l2-cache {
diff --git a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
index e2bd9313e632..16b454b504e2 100644
--- a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
@@ -319,24 +319,6 @@
319/include/ "qoriq-clockgen1.dtsi" 319/include/ "qoriq-clockgen1.dtsi"
320 global-utilities@e1000 { 320 global-utilities@e1000 {
321 compatible = "fsl,p5040-clockgen", "fsl,qoriq-clockgen-1.0"; 321 compatible = "fsl,p5040-clockgen", "fsl,qoriq-clockgen-1.0";
322
323 mux2: mux2@40 {
324 #clock-cells = <0>;
325 reg = <0x40 0x4>;
326 compatible = "fsl,qoriq-core-mux-1.0";
327 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
328 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
329 clock-output-names = "cmux2";
330 };
331
332 mux3: mux3@60 {
333 #clock-cells = <0>;
334 reg = <0x60 0x4>;
335 compatible = "fsl,qoriq-core-mux-1.0";
336 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
337 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
338 clock-output-names = "cmux3";
339 };
340 }; 322 };
341 323
342 rcpm: global-utilities@e2000 { 324 rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
index dbd57750fc02..ed89dbbdacf0 100644
--- a/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
@@ -102,7 +102,7 @@
102 cpu0: PowerPC,e5500@0 { 102 cpu0: PowerPC,e5500@0 {
103 device_type = "cpu"; 103 device_type = "cpu";
104 reg = <0>; 104 reg = <0>;
105 clocks = <&mux0>; 105 clocks = <&clockgen 1 0>;
106 next-level-cache = <&L2_0>; 106 next-level-cache = <&L2_0>;
107 fsl,portid-mapping = <0x80000000>; 107 fsl,portid-mapping = <0x80000000>;
108 L2_0: l2-cache { 108 L2_0: l2-cache {
@@ -112,7 +112,7 @@
112 cpu1: PowerPC,e5500@1 { 112 cpu1: PowerPC,e5500@1 {
113 device_type = "cpu"; 113 device_type = "cpu";
114 reg = <1>; 114 reg = <1>;
115 clocks = <&mux1>; 115 clocks = <&clockgen 1 1>;
116 next-level-cache = <&L2_1>; 116 next-level-cache = <&L2_1>;
117 fsl,portid-mapping = <0x40000000>; 117 fsl,portid-mapping = <0x40000000>;
118 L2_1: l2-cache { 118 L2_1: l2-cache {
@@ -122,7 +122,7 @@
122 cpu2: PowerPC,e5500@2 { 122 cpu2: PowerPC,e5500@2 {
123 device_type = "cpu"; 123 device_type = "cpu";
124 reg = <2>; 124 reg = <2>;
125 clocks = <&mux2>; 125 clocks = <&clockgen 1 2>;
126 next-level-cache = <&L2_2>; 126 next-level-cache = <&L2_2>;
127 fsl,portid-mapping = <0x20000000>; 127 fsl,portid-mapping = <0x20000000>;
128 L2_2: l2-cache { 128 L2_2: l2-cache {
@@ -132,7 +132,7 @@
132 cpu3: PowerPC,e5500@3 { 132 cpu3: PowerPC,e5500@3 {
133 device_type = "cpu"; 133 device_type = "cpu";
134 reg = <3>; 134 reg = <3>;
135 clocks = <&mux3>; 135 clocks = <&clockgen 1 3>;
136 next-level-cache = <&L2_3>; 136 next-level-cache = <&L2_3>;
137 fsl,portid-mapping = <0x10000000>; 137 fsl,portid-mapping = <0x10000000>;
138 L2_3: l2-cache { 138 L2_3: l2-cache {
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi
index 88cd70de4f86..463c1ed9ffdd 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi
@@ -34,53 +34,6 @@
34 34
35clockgen: global-utilities@e1000 { 35clockgen: global-utilities@e1000 {
36 compatible = "fsl,qoriq-clockgen-1.0"; 36 compatible = "fsl,qoriq-clockgen-1.0";
37 ranges = <0x0 0xe1000 0x1000>;
38 reg = <0xe1000 0x1000>; 37 reg = <0xe1000 0x1000>;
39 clock-frequency = <0>;
40 #address-cells = <1>;
41 #size-cells = <1>;
42 #clock-cells = <2>; 38 #clock-cells = <2>;
43
44 sysclk: sysclk {
45 #clock-cells = <0>;
46 compatible = "fsl,qoriq-sysclk-1.0", "fixed-clock";
47 clock-output-names = "sysclk";
48 };
49 pll0: pll0@800 {
50 #clock-cells = <1>;
51 reg = <0x800 0x4>;
52 compatible = "fsl,qoriq-core-pll-1.0";
53 clocks = <&sysclk>;
54 clock-output-names = "pll0", "pll0-div2";
55 };
56 pll1: pll1@820 {
57 #clock-cells = <1>;
58 reg = <0x820 0x4>;
59 compatible = "fsl,qoriq-core-pll-1.0";
60 clocks = <&sysclk>;
61 clock-output-names = "pll1", "pll1-div2";
62 };
63 mux0: mux0@0 {
64 #clock-cells = <0>;
65 reg = <0x0 0x4>;
66 compatible = "fsl,qoriq-core-mux-1.0";
67 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
68 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
69 clock-output-names = "cmux0";
70 };
71 mux1: mux1@20 {
72 #clock-cells = <0>;
73 reg = <0x20 0x4>;
74 compatible = "fsl,qoriq-core-mux-1.0";
75 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
76 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
77 clock-output-names = "cmux1";
78 };
79 platform_pll: platform-pll@c00 {
80 #clock-cells = <1>;
81 reg = <0xc00 0x4>;
82 compatible = "fsl,qoriq-platform-pll-1.0";
83 clocks = <&sysclk>;
84 clock-output-names = "platform-pll", "platform-pll-div2";
85 };
86}; 39};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi
index 6dfd7c5357ab..0361050bb56a 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi
@@ -34,36 +34,6 @@
34 34
35clockgen: global-utilities@e1000 { 35clockgen: global-utilities@e1000 {
36 compatible = "fsl,qoriq-clockgen-2.0"; 36 compatible = "fsl,qoriq-clockgen-2.0";
37 ranges = <0x0 0xe1000 0x1000>;
38 reg = <0xe1000 0x1000>; 37 reg = <0xe1000 0x1000>;
39 #address-cells = <1>;
40 #size-cells = <1>;
41 #clock-cells = <2>; 38 #clock-cells = <2>;
42
43 sysclk: sysclk {
44 #clock-cells = <0>;
45 compatible = "fsl,qoriq-sysclk-2.0", "fixed-clock";
46 clock-output-names = "sysclk";
47 };
48 pll0: pll0@800 {
49 #clock-cells = <1>;
50 reg = <0x800 0x4>;
51 compatible = "fsl,qoriq-core-pll-2.0";
52 clocks = <&sysclk>;
53 clock-output-names = "pll0", "pll0-div2", "pll0-div4";
54 };
55 pll1: pll1@820 {
56 #clock-cells = <1>;
57 reg = <0x820 0x4>;
58 compatible = "fsl,qoriq-core-pll-2.0";
59 clocks = <&sysclk>;
60 clock-output-names = "pll1", "pll1-div2", "pll1-div4";
61 };
62 platform_pll: platform-pll@c00 {
63 #clock-cells = <1>;
64 reg = <0xc00 0x4>;
65 compatible = "fsl,qoriq-platform-pll-2.0";
66 clocks = <&sysclk>;
67 clock-output-names = "platform-pll", "platform-pll-div2";
68 };
69}; 39};
diff --git a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
index 4908af501098..d552044c5afc 100644
--- a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
@@ -345,22 +345,6 @@
345/include/ "qoriq-clockgen2.dtsi" 345/include/ "qoriq-clockgen2.dtsi"
346 global-utilities@e1000 { 346 global-utilities@e1000 {
347 compatible = "fsl,t1023-clockgen", "fsl,qoriq-clockgen-2.0"; 347 compatible = "fsl,t1023-clockgen", "fsl,qoriq-clockgen-2.0";
348 mux0: mux0@0 {
349 #clock-cells = <0>;
350 reg = <0x0 4>;
351 compatible = "fsl,core-mux-clock";
352 clocks = <&pll0 0>, <&pll0 1>;
353 clock-names = "pll0_0", "pll0_1";
354 clock-output-names = "cmux0";
355 };
356 mux1: mux1@20 {
357 #clock-cells = <0>;
358 reg = <0x20 4>;
359 compatible = "fsl,core-mux-clock";
360 clocks = <&pll0 0>, <&pll0 1>;
361 clock-names = "pll0_0", "pll0_1";
362 clock-output-names = "cmux1";
363 };
364 }; 348 };
365 349
366 rcpm: global-utilities@e2000 { 350 rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/t102xsi-pre.dtsi b/arch/powerpc/boot/dts/fsl/t102xsi-pre.dtsi
index 9d08a363bab3..d87ea13164f2 100644
--- a/arch/powerpc/boot/dts/fsl/t102xsi-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t102xsi-pre.dtsi
@@ -74,7 +74,7 @@
74 cpu0: PowerPC,e5500@0 { 74 cpu0: PowerPC,e5500@0 {
75 device_type = "cpu"; 75 device_type = "cpu";
76 reg = <0>; 76 reg = <0>;
77 clocks = <&mux0>; 77 clocks = <&clockgen 1 0>;
78 next-level-cache = <&L2_1>; 78 next-level-cache = <&L2_1>;
79 #cooling-cells = <2>; 79 #cooling-cells = <2>;
80 L2_1: l2-cache { 80 L2_1: l2-cache {
@@ -84,7 +84,7 @@
84 cpu1: PowerPC,e5500@1 { 84 cpu1: PowerPC,e5500@1 {
85 device_type = "cpu"; 85 device_type = "cpu";
86 reg = <1>; 86 reg = <1>;
87 clocks = <&mux1>; 87 clocks = <&clockgen 1 1>;
88 next-level-cache = <&L2_2>; 88 next-level-cache = <&L2_2>;
89 #cooling-cells = <2>; 89 #cooling-cells = <2>;
90 L2_2: l2-cache { 90 L2_2: l2-cache {
diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
index 145c7f43b5b6..315d0557eefc 100644
--- a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
@@ -425,50 +425,6 @@
425/include/ "qoriq-clockgen2.dtsi" 425/include/ "qoriq-clockgen2.dtsi"
426 global-utilities@e1000 { 426 global-utilities@e1000 {
427 compatible = "fsl,t1040-clockgen", "fsl,qoriq-clockgen-2.0"; 427 compatible = "fsl,t1040-clockgen", "fsl,qoriq-clockgen-2.0";
428
429 mux0: mux0@0 {
430 #clock-cells = <0>;
431 reg = <0x0 4>;
432 compatible = "fsl,qoriq-core-mux-2.0";
433 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
434 <&pll1 0>, <&pll1 1>, <&pll1 2>;
435 clock-names = "pll0", "pll0-div2", "pll1-div4",
436 "pll1", "pll1-div2", "pll1-div4";
437 clock-output-names = "cmux0";
438 };
439
440 mux1: mux1@20 {
441 #clock-cells = <0>;
442 reg = <0x20 4>;
443 compatible = "fsl,qoriq-core-mux-2.0";
444 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
445 <&pll1 0>, <&pll1 1>, <&pll1 2>;
446 clock-names = "pll0", "pll0-div2", "pll1-div4",
447 "pll1", "pll1-div2", "pll1-div4";
448 clock-output-names = "cmux1";
449 };
450
451 mux2: mux2@40 {
452 #clock-cells = <0>;
453 reg = <0x40 4>;
454 compatible = "fsl,qoriq-core-mux-2.0";
455 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
456 <&pll1 0>, <&pll1 1>, <&pll1 2>;
457 clock-names = "pll0", "pll0-div2", "pll1-div4",
458 "pll1", "pll1-div2", "pll1-div4";
459 clock-output-names = "cmux2";
460 };
461
462 mux3: mux3@60 {
463 #clock-cells = <0>;
464 reg = <0x60 4>;
465 compatible = "fsl,qoriq-core-mux-2.0";
466 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
467 <&pll1 0>, <&pll1 1>, <&pll1 2>;
468 clock-names = "pll0_0", "pll0_1", "pll0_2",
469 "pll1_0", "pll1_1", "pll1_2";
470 clock-output-names = "cmux3";
471 };
472 }; 428 };
473 429
474 rcpm: global-utilities@e2000 { 430 rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi b/arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi
index 6db0ee8b1384..dd59e4b69480 100644
--- a/arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi
@@ -74,7 +74,7 @@
74 cpu0: PowerPC,e5500@0 { 74 cpu0: PowerPC,e5500@0 {
75 device_type = "cpu"; 75 device_type = "cpu";
76 reg = <0>; 76 reg = <0>;
77 clocks = <&mux0>; 77 clocks = <&clockgen 1 0>;
78 next-level-cache = <&L2_1>; 78 next-level-cache = <&L2_1>;
79 #cooling-cells = <2>; 79 #cooling-cells = <2>;
80 L2_1: l2-cache { 80 L2_1: l2-cache {
@@ -84,7 +84,7 @@
84 cpu1: PowerPC,e5500@1 { 84 cpu1: PowerPC,e5500@1 {
85 device_type = "cpu"; 85 device_type = "cpu";
86 reg = <1>; 86 reg = <1>;
87 clocks = <&mux1>; 87 clocks = <&clockgen 1 1>;
88 next-level-cache = <&L2_2>; 88 next-level-cache = <&L2_2>;
89 #cooling-cells = <2>; 89 #cooling-cells = <2>;
90 L2_2: l2-cache { 90 L2_2: l2-cache {
@@ -94,7 +94,7 @@
94 cpu2: PowerPC,e5500@2 { 94 cpu2: PowerPC,e5500@2 {
95 device_type = "cpu"; 95 device_type = "cpu";
96 reg = <2>; 96 reg = <2>;
97 clocks = <&mux2>; 97 clocks = <&clockgen 1 2>;
98 next-level-cache = <&L2_3>; 98 next-level-cache = <&L2_3>;
99 #cooling-cells = <2>; 99 #cooling-cells = <2>;
100 L2_3: l2-cache { 100 L2_3: l2-cache {
@@ -104,7 +104,7 @@
104 cpu3: PowerPC,e5500@3 { 104 cpu3: PowerPC,e5500@3 {
105 device_type = "cpu"; 105 device_type = "cpu";
106 reg = <3>; 106 reg = <3>;
107 clocks = <&mux3>; 107 clocks = <&clockgen 1 3>;
108 next-level-cache = <&L2_4>; 108 next-level-cache = <&L2_4>;
109 #cooling-cells = <2>; 109 #cooling-cells = <2>;
110 L2_4: l2-cache { 110 L2_4: l2-cache {
diff --git a/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
index a97296c64eb2..ecbb447920bc 100644
--- a/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
@@ -535,28 +535,6 @@
535/include/ "qoriq-clockgen2.dtsi" 535/include/ "qoriq-clockgen2.dtsi"
536 global-utilities@e1000 { 536 global-utilities@e1000 {
537 compatible = "fsl,t2080-clockgen", "fsl,qoriq-clockgen-2.0"; 537 compatible = "fsl,t2080-clockgen", "fsl,qoriq-clockgen-2.0";
538
539 mux0: mux0@0 {
540 #clock-cells = <0>;
541 reg = <0x0 4>;
542 compatible = "fsl,qoriq-core-mux-2.0";
543 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
544 <&pll1 0>, <&pll1 1>, <&pll1 2>;
545 clock-names = "pll0", "pll0-div2", "pll0-div4",
546 "pll1", "pll1-div2", "pll1-div4";
547 clock-output-names = "cmux0";
548 };
549
550 mux1: mux1@20 {
551 #clock-cells = <0>;
552 reg = <0x20 4>;
553 compatible = "fsl,qoriq-core-mux-2.0";
554 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
555 <&pll1 0>, <&pll1 1>, <&pll1 2>;
556 clock-names = "pll0", "pll0-div2", "pll0-div4",
557 "pll1", "pll1-div2", "pll1-div4";
558 clock-output-names = "cmux1";
559 };
560 }; 538 };
561 539
562 rcpm: global-utilities@e2000 { 540 rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi b/arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
index c2e57203910d..3f745de44284 100644
--- a/arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
@@ -81,28 +81,28 @@
81 cpu0: PowerPC,e6500@0 { 81 cpu0: PowerPC,e6500@0 {
82 device_type = "cpu"; 82 device_type = "cpu";
83 reg = <0 1>; 83 reg = <0 1>;
84 clocks = <&mux0>; 84 clocks = <&clockgen 1 0>;
85 next-level-cache = <&L2_1>; 85 next-level-cache = <&L2_1>;
86 fsl,portid-mapping = <0x80000000>; 86 fsl,portid-mapping = <0x80000000>;
87 }; 87 };
88 cpu1: PowerPC,e6500@2 { 88 cpu1: PowerPC,e6500@2 {
89 device_type = "cpu"; 89 device_type = "cpu";
90 reg = <2 3>; 90 reg = <2 3>;
91 clocks = <&mux0>; 91 clocks = <&clockgen 1 0>;
92 next-level-cache = <&L2_1>; 92 next-level-cache = <&L2_1>;
93 fsl,portid-mapping = <0x80000000>; 93 fsl,portid-mapping = <0x80000000>;
94 }; 94 };
95 cpu2: PowerPC,e6500@4 { 95 cpu2: PowerPC,e6500@4 {
96 device_type = "cpu"; 96 device_type = "cpu";
97 reg = <4 5>; 97 reg = <4 5>;
98 clocks = <&mux0>; 98 clocks = <&clockgen 1 0>;
99 next-level-cache = <&L2_1>; 99 next-level-cache = <&L2_1>;
100 fsl,portid-mapping = <0x80000000>; 100 fsl,portid-mapping = <0x80000000>;
101 }; 101 };
102 cpu3: PowerPC,e6500@6 { 102 cpu3: PowerPC,e6500@6 {
103 device_type = "cpu"; 103 device_type = "cpu";
104 reg = <6 7>; 104 reg = <6 7>;
105 clocks = <&mux0>; 105 clocks = <&clockgen 1 0>;
106 next-level-cache = <&L2_1>; 106 next-level-cache = <&L2_1>;
107 fsl,portid-mapping = <0x80000000>; 107 fsl,portid-mapping = <0x80000000>;
108 }; 108 };
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
index 68c4eadc19e3..fcac73486d48 100644
--- a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
@@ -950,67 +950,6 @@
950/include/ "qoriq-clockgen2.dtsi" 950/include/ "qoriq-clockgen2.dtsi"
951 global-utilities@e1000 { 951 global-utilities@e1000 {
952 compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0"; 952 compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0";
953
954 pll2: pll2@840 {
955 #clock-cells = <1>;
956 reg = <0x840 0x4>;
957 compatible = "fsl,qoriq-core-pll-2.0";
958 clocks = <&sysclk>;
959 clock-output-names = "pll2", "pll2-div2", "pll2-div4";
960 };
961
962 pll3: pll3@860 {
963 #clock-cells = <1>;
964 reg = <0x860 0x4>;
965 compatible = "fsl,qoriq-core-pll-2.0";
966 clocks = <&sysclk>;
967 clock-output-names = "pll3", "pll3-div2", "pll3-div4";
968 };
969
970 pll4: pll4@880 {
971 #clock-cells = <1>;
972 reg = <0x880 0x4>;
973 compatible = "fsl,qoriq-core-pll-2.0";
974 clocks = <&sysclk>;
975 clock-output-names = "pll4", "pll4-div2", "pll4-div4";
976 };
977
978 mux0: mux0@0 {
979 #clock-cells = <0>;
980 reg = <0x0 0x4>;
981 compatible = "fsl,qoriq-core-mux-2.0";
982 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
983 <&pll1 0>, <&pll1 1>, <&pll1 2>,
984 <&pll2 0>, <&pll2 1>, <&pll2 2>;
985 clock-names = "pll0", "pll0-div2", "pll0-div4",
986 "pll1", "pll1-div2", "pll1-div4",
987 "pll2", "pll2-div2", "pll2-div4";
988 clock-output-names = "cmux0";
989 };
990
991 mux1: mux1@20 {
992 #clock-cells = <0>;
993 reg = <0x20 0x4>;
994 compatible = "fsl,qoriq-core-mux-2.0";
995 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
996 <&pll1 0>, <&pll1 1>, <&pll1 2>,
997 <&pll2 0>, <&pll2 1>, <&pll2 2>;
998 clock-names = "pll0", "pll0-div2", "pll0-div4",
999 "pll1", "pll1-div2", "pll1-div4",
1000 "pll2", "pll2-div2", "pll2-div4";
1001 clock-output-names = "cmux1";
1002 };
1003
1004 mux2: mux2@40 {
1005 #clock-cells = <0>;
1006 reg = <0x40 0x4>;
1007 compatible = "fsl,qoriq-core-mux-2.0";
1008 clocks = <&pll3 0>, <&pll3 1>, <&pll3 2>,
1009 <&pll4 0>, <&pll4 1>, <&pll4 2>;
1010 clock-names = "pll3", "pll3-div2", "pll3-div4",
1011 "pll4", "pll4-div2", "pll4-div4";
1012 clock-output-names = "cmux2";
1013 };
1014 }; 953 };
1015 954
1016 rcpm: global-utilities@e2000 { 955 rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
index 038cf8fadee4..632314c6faa9 100644
--- a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
@@ -90,84 +90,84 @@
90 cpu0: PowerPC,e6500@0 { 90 cpu0: PowerPC,e6500@0 {
91 device_type = "cpu"; 91 device_type = "cpu";
92 reg = <0 1>; 92 reg = <0 1>;
93 clocks = <&mux0>; 93 clocks = <&clockgen 1 0>;
94 next-level-cache = <&L2_1>; 94 next-level-cache = <&L2_1>;
95 fsl,portid-mapping = <0x80000000>; 95 fsl,portid-mapping = <0x80000000>;
96 }; 96 };
97 cpu1: PowerPC,e6500@2 { 97 cpu1: PowerPC,e6500@2 {
98 device_type = "cpu"; 98 device_type = "cpu";
99 reg = <2 3>; 99 reg = <2 3>;
100 clocks = <&mux0>; 100 clocks = <&clockgen 1 0>;
101 next-level-cache = <&L2_1>; 101 next-level-cache = <&L2_1>;
102 fsl,portid-mapping = <0x80000000>; 102 fsl,portid-mapping = <0x80000000>;
103 }; 103 };
104 cpu2: PowerPC,e6500@4 { 104 cpu2: PowerPC,e6500@4 {
105 device_type = "cpu"; 105 device_type = "cpu";
106 reg = <4 5>; 106 reg = <4 5>;
107 clocks = <&mux0>; 107 clocks = <&clockgen 1 0>;
108 next-level-cache = <&L2_1>; 108 next-level-cache = <&L2_1>;
109 fsl,portid-mapping = <0x80000000>; 109 fsl,portid-mapping = <0x80000000>;
110 }; 110 };
111 cpu3: PowerPC,e6500@6 { 111 cpu3: PowerPC,e6500@6 {
112 device_type = "cpu"; 112 device_type = "cpu";
113 reg = <6 7>; 113 reg = <6 7>;
114 clocks = <&mux0>; 114 clocks = <&clockgen 1 0>;
115 next-level-cache = <&L2_1>; 115 next-level-cache = <&L2_1>;
116 fsl,portid-mapping = <0x80000000>; 116 fsl,portid-mapping = <0x80000000>;
117 }; 117 };
118 cpu4: PowerPC,e6500@8 { 118 cpu4: PowerPC,e6500@8 {
119 device_type = "cpu"; 119 device_type = "cpu";
120 reg = <8 9>; 120 reg = <8 9>;
121 clocks = <&mux1>; 121 clocks = <&clockgen 1 1>;
122 next-level-cache = <&L2_2>; 122 next-level-cache = <&L2_2>;
123 fsl,portid-mapping = <0x40000000>; 123 fsl,portid-mapping = <0x40000000>;
124 }; 124 };
125 cpu5: PowerPC,e6500@10 { 125 cpu5: PowerPC,e6500@10 {
126 device_type = "cpu"; 126 device_type = "cpu";
127 reg = <10 11>; 127 reg = <10 11>;
128 clocks = <&mux1>; 128 clocks = <&clockgen 1 1>;
129 next-level-cache = <&L2_2>; 129 next-level-cache = <&L2_2>;
130 fsl,portid-mapping = <0x40000000>; 130 fsl,portid-mapping = <0x40000000>;
131 }; 131 };
132 cpu6: PowerPC,e6500@12 { 132 cpu6: PowerPC,e6500@12 {
133 device_type = "cpu"; 133 device_type = "cpu";
134 reg = <12 13>; 134 reg = <12 13>;
135 clocks = <&mux1>; 135 clocks = <&clockgen 1 1>;
136 next-level-cache = <&L2_2>; 136 next-level-cache = <&L2_2>;
137 fsl,portid-mapping = <0x40000000>; 137 fsl,portid-mapping = <0x40000000>;
138 }; 138 };
139 cpu7: PowerPC,e6500@14 { 139 cpu7: PowerPC,e6500@14 {
140 device_type = "cpu"; 140 device_type = "cpu";
141 reg = <14 15>; 141 reg = <14 15>;
142 clocks = <&mux1>; 142 clocks = <&clockgen 1 1>;
143 next-level-cache = <&L2_2>; 143 next-level-cache = <&L2_2>;
144 fsl,portid-mapping = <0x40000000>; 144 fsl,portid-mapping = <0x40000000>;
145 }; 145 };
146 cpu8: PowerPC,e6500@16 { 146 cpu8: PowerPC,e6500@16 {
147 device_type = "cpu"; 147 device_type = "cpu";
148 reg = <16 17>; 148 reg = <16 17>;
149 clocks = <&mux2>; 149 clocks = <&clockgen 1 2>;
150 next-level-cache = <&L2_3>; 150 next-level-cache = <&L2_3>;
151 fsl,portid-mapping = <0x20000000>; 151 fsl,portid-mapping = <0x20000000>;
152 }; 152 };
153 cpu9: PowerPC,e6500@18 { 153 cpu9: PowerPC,e6500@18 {
154 device_type = "cpu"; 154 device_type = "cpu";
155 reg = <18 19>; 155 reg = <18 19>;
156 clocks = <&mux2>; 156 clocks = <&clockgen 1 2>;
157 next-level-cache = <&L2_3>; 157 next-level-cache = <&L2_3>;
158 fsl,portid-mapping = <0x20000000>; 158 fsl,portid-mapping = <0x20000000>;
159 }; 159 };
160 cpu10: PowerPC,e6500@20 { 160 cpu10: PowerPC,e6500@20 {
161 device_type = "cpu"; 161 device_type = "cpu";
162 reg = <20 21>; 162 reg = <20 21>;
163 clocks = <&mux2>; 163 clocks = <&clockgen 1 2>;
164 next-level-cache = <&L2_3>; 164 next-level-cache = <&L2_3>;
165 fsl,portid-mapping = <0x20000000>; 165 fsl,portid-mapping = <0x20000000>;
166 }; 166 };
167 cpu11: PowerPC,e6500@22 { 167 cpu11: PowerPC,e6500@22 {
168 device_type = "cpu"; 168 device_type = "cpu";
169 reg = <22 23>; 169 reg = <22 23>;
170 clocks = <&mux2>; 170 clocks = <&clockgen 1 2>;
171 next-level-cache = <&L2_3>; 171 next-level-cache = <&L2_3>;
172 fsl,portid-mapping = <0x20000000>; 172 fsl,portid-mapping = <0x20000000>;
173 }; 173 };
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-08 22:04:58 -0500