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-rw-r--r--arch/arm64/boot/dts/nvidia/tegra194.dtsi344
-rw-r--r--include/dt-bindings/clock/tegra194-clock.h321
-rw-r--r--include/dt-bindings/gpio/tegra194-gpio.h61
-rw-r--r--include/dt-bindings/power/tegra194-powergate.h35
-rw-r--r--include/dt-bindings/reset/tegra194-reset.h152
5 files changed, 913 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
new file mode 100644
index 000000000000..6322ef265c2f
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -0,0 +1,344 @@
1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/tegra194-clock.h>
3#include <dt-bindings/gpio/tegra194-gpio.h>
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/mailbox/tegra186-hsp.h>
6#include <dt-bindings/reset/tegra194-reset.h>
7
8/ {
9 compatible = "nvidia,tegra194";
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
13
14 /* control backbone */
15 cbb {
16 compatible = "simple-bus";
17 #address-cells = <1>;
18 #size-cells = <1>;
19 ranges = <0x0 0x0 0x0 0x40000000>;
20
21 uarta: serial@3100000 {
22 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
23 reg = <0x03100000 0x40>;
24 reg-shift = <2>;
25 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
26 clocks = <&bpmp TEGRA194_CLK_UARTA>;
27 clock-names = "serial";
28 resets = <&bpmp TEGRA194_RESET_UARTA>;
29 reset-names = "serial";
30 status = "disabled";
31 };
32
33 uartb: serial@3110000 {
34 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
35 reg = <0x03110000 0x40>;
36 reg-shift = <2>;
37 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
38 clocks = <&bpmp TEGRA194_CLK_UARTB>;
39 clock-names = "serial";
40 resets = <&bpmp TEGRA194_RESET_UARTB>;
41 reset-names = "serial";
42 status = "disabled";
43 };
44
45 uartd: serial@3130000 {
46 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
47 reg = <0x03130000 0x40>;
48 reg-shift = <2>;
49 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
50 clocks = <&bpmp TEGRA194_CLK_UARTD>;
51 clock-names = "serial";
52 resets = <&bpmp TEGRA194_RESET_UARTD>;
53 reset-names = "serial";
54 status = "disabled";
55 };
56
57 uarte: serial@3140000 {
58 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
59 reg = <0x03140000 0x40>;
60 reg-shift = <2>;
61 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
62 clocks = <&bpmp TEGRA194_CLK_UARTE>;
63 clock-names = "serial";
64 resets = <&bpmp TEGRA194_RESET_UARTE>;
65 reset-names = "serial";
66 status = "disabled";
67 };
68
69 uartf: serial@3150000 {
70 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
71 reg = <0x03150000 0x40>;
72 reg-shift = <2>;
73 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
74 clocks = <&bpmp TEGRA194_CLK_UARTF>;
75 clock-names = "serial";
76 resets = <&bpmp TEGRA194_RESET_UARTF>;
77 reset-names = "serial";
78 status = "disabled";
79 };
80
81 gen1_i2c: i2c@3160000 {
82 compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
83 reg = <0x03160000 0x10000>;
84 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
85 #address-cells = <1>;
86 #size-cells = <0>;
87 clocks = <&bpmp TEGRA194_CLK_I2C1>;
88 clock-names = "div-clk";
89 resets = <&bpmp TEGRA194_RESET_I2C1>;
90 reset-names = "i2c";
91 status = "disabled";
92 };
93
94 uarth: serial@3170000 {
95 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
96 reg = <0x03170000 0x40>;
97 reg-shift = <2>;
98 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
99 clocks = <&bpmp TEGRA194_CLK_UARTH>;
100 clock-names = "serial";
101 resets = <&bpmp TEGRA194_RESET_UARTH>;
102 reset-names = "serial";
103 status = "disabled";
104 };
105
106 cam_i2c: i2c@3180000 {
107 compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
108 reg = <0x03180000 0x10000>;
109 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
110 #address-cells = <1>;
111 #size-cells = <0>;
112 clocks = <&bpmp TEGRA194_CLK_I2C3>;
113 clock-names = "div-clk";
114 resets = <&bpmp TEGRA194_RESET_I2C3>;
115 reset-names = "i2c";
116 status = "disabled";
117 };
118
119 /* shares pads with dpaux1 */
120 dp_aux_ch1_i2c: i2c@3190000 {
121 compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
122 reg = <0x03190000 0x10000>;
123 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
124 #address-cells = <1>;
125 #size-cells = <0>;
126 clocks = <&bpmp TEGRA194_CLK_I2C4>;
127 clock-names = "div-clk";
128 resets = <&bpmp TEGRA194_RESET_I2C4>;
129 reset-names = "i2c";
130 status = "disabled";
131 };
132
133 /* shares pads with dpaux0 */
134 dp_aux_ch0_i2c: i2c@31b0000 {
135 compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
136 reg = <0x031b0000 0x10000>;
137 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
138 #address-cells = <1>;
139 #size-cells = <0>;
140 clocks = <&bpmp TEGRA194_CLK_I2C6>;
141 clock-names = "div-clk";
142 resets = <&bpmp TEGRA194_RESET_I2C6>;
143 reset-names = "i2c";
144 status = "disabled";
145 };
146
147 gen7_i2c: i2c@31c0000 {
148 compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
149 reg = <0x031c0000 0x10000>;
150 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
151 #address-cells = <1>;
152 #size-cells = <0>;
153 clocks = <&bpmp TEGRA194_CLK_I2C7>;
154 clock-names = "div-clk";
155 resets = <&bpmp TEGRA194_RESET_I2C7>;
156 reset-names = "i2c";
157 status = "disabled";
158 };
159
160 gen9_i2c: i2c@31e0000 {
161 compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
162 reg = <0x031e0000 0x10000>;
163 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
164 #address-cells = <1>;
165 #size-cells = <0>;
166 clocks = <&bpmp TEGRA194_CLK_I2C9>;
167 clock-names = "div-clk";
168 resets = <&bpmp TEGRA194_RESET_I2C9>;
169 reset-names = "i2c";
170 status = "disabled";
171 };
172
173 sdmmc1: sdhci@3400000 {
174 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
175 reg = <0x03400000 0x10000>;
176 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
177 clocks = <&bpmp TEGRA194_CLK_SDMMC1>;
178 clock-names = "sdhci";
179 resets = <&bpmp TEGRA194_RESET_SDMMC1>;
180 reset-names = "sdhci";
181 status = "disabled";
182 };
183
184 sdmmc3: sdhci@3440000 {
185 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
186 reg = <0x03440000 0x10000>;
187 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
188 clocks = <&bpmp TEGRA194_CLK_SDMMC3>;
189 clock-names = "sdhci";
190 resets = <&bpmp TEGRA194_RESET_SDMMC3>;
191 reset-names = "sdhci";
192 status = "disabled";
193 };
194
195 sdmmc4: sdhci@3460000 {
196 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
197 reg = <0x03460000 0x10000>;
198 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
199 clocks = <&bpmp TEGRA194_CLK_SDMMC4>;
200 clock-names = "sdhci";
201 resets = <&bpmp TEGRA194_RESET_SDMMC4>;
202 reset-names = "sdhci";
203 status = "disabled";
204 };
205
206 gic: interrupt-controller@3881000 {
207 compatible = "arm,gic-400";
208 #interrupt-cells = <3>;
209 interrupt-controller;
210 reg = <0x03881000 0x1000>,
211 <0x03882000 0x2000>,
212 <0x03884000 0x2000>,
213 <0x03886000 0x2000>;
214 interrupts = <GIC_PPI 9
215 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
216 interrupt-parent = <&gic>;
217 };
218
219 hsp_top0: hsp@3c00000 {
220 compatible = "nvidia,tegra186-hsp";
221 reg = <0x03c00000 0xa0000>;
222 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
223 interrupt-names = "doorbell";
224 #mbox-cells = <2>;
225 };
226
227 gen2_i2c: i2c@c240000 {
228 compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
229 reg = <0x0c240000 0x10000>;
230 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
231 #address-cells = <1>;
232 #size-cells = <0>;
233 clocks = <&bpmp TEGRA194_CLK_I2C2>;
234 clock-names = "div-clk";
235 resets = <&bpmp TEGRA194_RESET_I2C2>;
236 reset-names = "i2c";
237 status = "disabled";
238 };
239
240 gen8_i2c: i2c@c250000 {
241 compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
242 reg = <0x0c250000 0x10000>;
243 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
244 #address-cells = <1>;
245 #size-cells = <0>;
246 clocks = <&bpmp TEGRA194_CLK_I2C8>;
247 clock-names = "div-clk";
248 resets = <&bpmp TEGRA194_RESET_I2C8>;
249 reset-names = "i2c";
250 status = "disabled";
251 };
252
253 uartc: serial@c280000 {
254 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
255 reg = <0x0c280000 0x40>;
256 reg-shift = <2>;
257 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&bpmp TEGRA194_CLK_UARTC>;
259 clock-names = "serial";
260 resets = <&bpmp TEGRA194_RESET_UARTC>;
261 reset-names = "serial";
262 status = "disabled";
263 };
264
265 uartg: serial@c290000 {
266 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
267 reg = <0x0c290000 0x40>;
268 reg-shift = <2>;
269 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&bpmp TEGRA194_CLK_UARTG>;
271 clock-names = "serial";
272 resets = <&bpmp TEGRA194_RESET_UARTG>;
273 reset-names = "serial";
274 status = "disabled";
275 };
276
277 pmc@c360000 {
278 compatible = "nvidia,tegra194-pmc";
279 reg = <0x0c360000 0x10000>,
280 <0x0c370000 0x10000>,
281 <0x0c380000 0x10000>,
282 <0x0c390000 0x10000>,
283 <0x0c3a0000 0x10000>;
284 reg-names = "pmc", "wake", "aotag", "scratch", "misc";
285 };
286 };
287
288 sysram@40000000 {
289 compatible = "nvidia,tegra194-sysram", "mmio-sram";
290 reg = <0x0 0x40000000 0x0 0x50000>;
291 #address-cells = <1>;
292 #size-cells = <1>;
293 ranges = <0x0 0x0 0x40000000 0x50000>;
294
295 cpu_bpmp_tx: shmem@4e000 {
296 compatible = "nvidia,tegra194-bpmp-shmem";
297 reg = <0x4e000 0x1000>;
298 label = "cpu-bpmp-tx";
299 pool;
300 };
301
302 cpu_bpmp_rx: shmem@4f000 {
303 compatible = "nvidia,tegra194-bpmp-shmem";
304 reg = <0x4f000 0x1000>;
305 label = "cpu-bpmp-rx";
306 pool;
307 };
308 };
309
310 bpmp: bpmp {
311 compatible = "nvidia,tegra186-bpmp";
312 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
313 TEGRA_HSP_DB_MASTER_BPMP>;
314 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
315 #clock-cells = <1>;
316 #reset-cells = <1>;
317 #power-domain-cells = <1>;
318
319 bpmp_i2c: i2c {
320 compatible = "nvidia,tegra186-bpmp-i2c";
321 nvidia,bpmp-bus-id = <5>;
322 #address-cells = <1>;
323 #size-cells = <0>;
324 };
325
326 bpmp_thermal: thermal {
327 compatible = "nvidia,tegra186-bpmp-thermal";
328 #thermal-sensor-cells = <1>;
329 };
330 };
331
332 timer {
333 compatible = "arm,armv8-timer";
334 interrupts = <GIC_PPI 13
335 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
336 <GIC_PPI 14
337 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
338 <GIC_PPI 11
339 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
340 <GIC_PPI 10
341 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
342 interrupt-parent = <&gic>;
343 };
344};
diff --git a/include/dt-bindings/clock/tegra194-clock.h b/include/dt-bindings/clock/tegra194-clock.h
new file mode 100644
index 000000000000..a2ff66342d69
--- /dev/null
+++ b/include/dt-bindings/clock/tegra194-clock.h
@@ -0,0 +1,321 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */
3
4#ifndef __ABI_MACH_T194_CLOCK_H
5#define __ABI_MACH_T194_CLOCK_H
6
7#define TEGRA194_CLK_ACTMON 1
8#define TEGRA194_CLK_ADSP 2
9#define TEGRA194_CLK_ADSPNEON 3
10#define TEGRA194_CLK_AHUB 4
11#define TEGRA194_CLK_APB2APE 5
12#define TEGRA194_CLK_APE 6
13#define TEGRA194_CLK_AUD_MCLK 7
14#define TEGRA194_CLK_AXI_CBB 8
15#define TEGRA194_CLK_CAN1 9
16#define TEGRA194_CLK_CAN1_HOST 10
17#define TEGRA194_CLK_CAN2 11
18#define TEGRA194_CLK_CAN2_HOST 12
19#define TEGRA194_CLK_CEC 13
20#define TEGRA194_CLK_CLK_M 14
21#define TEGRA194_CLK_DMIC1 15
22#define TEGRA194_CLK_DMIC2 16
23#define TEGRA194_CLK_DMIC3 17
24#define TEGRA194_CLK_DMIC4 18
25#define TEGRA194_CLK_DPAUX 19
26#define TEGRA194_CLK_DPAUX1 20
27#define TEGRA194_CLK_ACLK 21
28#define TEGRA194_CLK_MSS_ENCRYPT 22
29#define TEGRA194_CLK_EQOS_RX_INPUT 23
30#define TEGRA194_CLK_IQC2 24
31#define TEGRA194_CLK_AON_APB 25
32#define TEGRA194_CLK_AON_NIC 26
33#define TEGRA194_CLK_AON_CPU_NIC 27
34#define TEGRA194_CLK_PLLA1 28
35#define TEGRA194_CLK_DSPK1 29
36#define TEGRA194_CLK_DSPK2 30
37#define TEGRA194_CLK_EMC 31
38#define TEGRA194_CLK_EQOS_AXI 32
39#define TEGRA194_CLK_EQOS_PTP_REF 33
40#define TEGRA194_CLK_EQOS_RX 34
41#define TEGRA194_CLK_EQOS_TX 35
42#define TEGRA194_CLK_EXTPERIPH1 36
43#define TEGRA194_CLK_EXTPERIPH2 37
44#define TEGRA194_CLK_EXTPERIPH3 38
45#define TEGRA194_CLK_EXTPERIPH4 39
46#define TEGRA194_CLK_FUSE 40
47#define TEGRA194_CLK_GPCCLK 41
48#define TEGRA194_CLK_GPU_PWR 42
49#define TEGRA194_CLK_HDA 43
50#define TEGRA194_CLK_HDA2CODEC_2X 44
51#define TEGRA194_CLK_HDA2HDMICODEC 45
52#define TEGRA194_CLK_HOST1X 46
53#define TEGRA194_CLK_HSIC_TRK 47
54#define TEGRA194_CLK_I2C1 48
55#define TEGRA194_CLK_I2C2 49
56#define TEGRA194_CLK_I2C3 50
57#define TEGRA194_CLK_I2C4 51
58#define TEGRA194_CLK_I2C6 52
59#define TEGRA194_CLK_I2C7 53
60#define TEGRA194_CLK_I2C8 54
61#define TEGRA194_CLK_I2C9 55
62#define TEGRA194_CLK_I2S1 56
63#define TEGRA194_CLK_I2S1_SYNC_INPUT 57
64#define TEGRA194_CLK_I2S2 58
65#define TEGRA194_CLK_I2S2_SYNC_INPUT 59
66#define TEGRA194_CLK_I2S3 60
67#define TEGRA194_CLK_I2S3_SYNC_INPUT 61
68#define TEGRA194_CLK_I2S4 62
69#define TEGRA194_CLK_I2S4_SYNC_INPUT 63
70#define TEGRA194_CLK_I2S5 64
71#define TEGRA194_CLK_I2S5_SYNC_INPUT 65
72#define TEGRA194_CLK_I2S6 66
73#define TEGRA194_CLK_I2S6_SYNC_INPUT 67
74#define TEGRA194_CLK_IQC1 68
75#define TEGRA194_CLK_ISP 69
76#define TEGRA194_CLK_KFUSE 70
77#define TEGRA194_CLK_MAUD 71
78#define TEGRA194_CLK_MIPI_CAL 72
79#define TEGRA194_CLK_MPHY_CORE_PLL_FIXED 73
80#define TEGRA194_CLK_MPHY_L0_RX_ANA 74
81#define TEGRA194_CLK_MPHY_L0_RX_LS_BIT 75
82#define TEGRA194_CLK_MPHY_L0_RX_SYMB 76
83#define TEGRA194_CLK_MPHY_L0_TX_LS_3XBIT 77
84#define TEGRA194_CLK_MPHY_L0_TX_SYMB 78
85#define TEGRA194_CLK_MPHY_L1_RX_ANA 79
86#define TEGRA194_CLK_MPHY_TX_1MHZ_REF 80
87#define TEGRA194_CLK_NVCSI 81
88#define TEGRA194_CLK_NVCSILP 82
89#define TEGRA194_CLK_NVDEC 83
90#define TEGRA194_CLK_NVDISPLAYHUB 84
91#define TEGRA194_CLK_NVDISPLAY_DISP 85
92#define TEGRA194_CLK_NVDISPLAY_P0 86
93#define TEGRA194_CLK_NVDISPLAY_P1 87
94#define TEGRA194_CLK_NVDISPLAY_P2 88
95#define TEGRA194_CLK_NVENC 89
96#define TEGRA194_CLK_NVJPG 90
97#define TEGRA194_CLK_OSC 91
98#define TEGRA194_CLK_AON_TOUCH 92
99#define TEGRA194_CLK_PLLA 93
100#define TEGRA194_CLK_PLLAON 94
101#define TEGRA194_CLK_PLLD 95
102#define TEGRA194_CLK_PLLD2 96
103#define TEGRA194_CLK_PLLD3 97
104#define TEGRA194_CLK_PLLDP 98
105#define TEGRA194_CLK_PLLD4 99
106#define TEGRA194_CLK_PLLE 100
107#define TEGRA194_CLK_PLLP 101
108#define TEGRA194_CLK_PLLP_OUT0 102
109#define TEGRA194_CLK_UTMIPLL 103
110#define TEGRA194_CLK_PLLA_OUT0 104
111#define TEGRA194_CLK_PWM1 105
112#define TEGRA194_CLK_PWM2 106
113#define TEGRA194_CLK_PWM3 107
114#define TEGRA194_CLK_PWM4 108
115#define TEGRA194_CLK_PWM5 109
116#define TEGRA194_CLK_PWM6 110
117#define TEGRA194_CLK_PWM7 111
118#define TEGRA194_CLK_PWM8 112
119#define TEGRA194_CLK_RCE_CPU_NIC 113
120#define TEGRA194_CLK_RCE_NIC 114
121#define TEGRA194_CLK_SATA 115
122#define TEGRA194_CLK_SATA_OOB 116
123#define TEGRA194_CLK_AON_I2C_SLOW 117
124#define TEGRA194_CLK_SCE_CPU_NIC 118
125#define TEGRA194_CLK_SCE_NIC 119
126#define TEGRA194_CLK_SDMMC1 120
127#define TEGRA194_CLK_UPHY_PLL3 121
128#define TEGRA194_CLK_SDMMC3 122
129#define TEGRA194_CLK_SDMMC4 123
130#define TEGRA194_CLK_SE 124
131#define TEGRA194_CLK_SOR0_OUT 125
132#define TEGRA194_CLK_SOR0_REF 126
133#define TEGRA194_CLK_SOR0_PAD_CLKOUT 127
134#define TEGRA194_CLK_SOR1_OUT 128
135#define TEGRA194_CLK_SOR1_REF 129
136#define TEGRA194_CLK_SOR1_PAD_CLKOUT 130
137#define TEGRA194_CLK_SOR_SAFE 131
138#define TEGRA194_CLK_IQC1_IN 132
139#define TEGRA194_CLK_IQC2_IN 133
140#define TEGRA194_CLK_DMIC5 134
141#define TEGRA194_CLK_SPI1 135
142#define TEGRA194_CLK_SPI2 136
143#define TEGRA194_CLK_SPI3 137
144#define TEGRA194_CLK_I2C_SLOW 138
145#define TEGRA194_CLK_SYNC_DMIC1 139
146#define TEGRA194_CLK_SYNC_DMIC2 140
147#define TEGRA194_CLK_SYNC_DMIC3 141
148#define TEGRA194_CLK_SYNC_DMIC4 142
149#define TEGRA194_CLK_SYNC_DSPK1 143
150#define TEGRA194_CLK_SYNC_DSPK2 144
151#define TEGRA194_CLK_SYNC_I2S1 145
152#define TEGRA194_CLK_SYNC_I2S2 146
153#define TEGRA194_CLK_SYNC_I2S3 147
154#define TEGRA194_CLK_SYNC_I2S4 148
155#define TEGRA194_CLK_SYNC_I2S5 149
156#define TEGRA194_CLK_SYNC_I2S6 150
157#define TEGRA194_CLK_MPHY_FORCE_LS_MODE 151
158#define TEGRA194_CLK_TACH 152
159#define TEGRA194_CLK_TSEC 153
160#define TEGRA194_CLK_TSECB 154
161#define TEGRA194_CLK_UARTA 155
162#define TEGRA194_CLK_UARTB 156
163#define TEGRA194_CLK_UARTC 157
164#define TEGRA194_CLK_UARTD 158
165#define TEGRA194_CLK_UARTE 159
166#define TEGRA194_CLK_UARTF 160
167#define TEGRA194_CLK_UARTG 161
168#define TEGRA194_CLK_UART_FST_MIPI_CAL 162
169#define TEGRA194_CLK_UFSDEV_REF 163
170#define TEGRA194_CLK_UFSHC 164
171#define TEGRA194_CLK_USB2_TRK 165
172#define TEGRA194_CLK_VI 166
173#define TEGRA194_CLK_VIC 167
174#define TEGRA194_CLK_PVA0_AXI 168
175#define TEGRA194_CLK_PVA0_VPS0 169
176#define TEGRA194_CLK_PVA0_VPS1 170
177#define TEGRA194_CLK_PVA1_AXI 171
178#define TEGRA194_CLK_PVA1_VPS0 172
179#define TEGRA194_CLK_PVA1_VPS1 173
180#define TEGRA194_CLK_DLA0_FALCON 174
181#define TEGRA194_CLK_DLA0_CORE 175
182#define TEGRA194_CLK_DLA1_FALCON 176
183#define TEGRA194_CLK_DLA1_CORE 177
184#define TEGRA194_CLK_SOR2_OUT 178
185#define TEGRA194_CLK_SOR2_REF 179
186#define TEGRA194_CLK_SOR2_PAD_CLKOUT 180
187#define TEGRA194_CLK_SOR3_OUT 181
188#define TEGRA194_CLK_SOR3_REF 182
189#define TEGRA194_CLK_SOR3_PAD_CLKOUT 183
190#define TEGRA194_CLK_NVDISPLAY_P3 184
191#define TEGRA194_CLK_DPAUX2 185
192#define TEGRA194_CLK_DPAUX3 186
193#define TEGRA194_CLK_NVDEC1 187
194#define TEGRA194_CLK_NVENC1 188
195#define TEGRA194_CLK_SE_FREE 189
196#define TEGRA194_CLK_UARTH 190
197#define TEGRA194_CLK_FUSE_SERIAL 191
198#define TEGRA194_CLK_QSPI0 192
199#define TEGRA194_CLK_QSPI1 193
200#define TEGRA194_CLK_QSPI0_PM 194
201#define TEGRA194_CLK_QSPI1_PM 195
202#define TEGRA194_CLK_VI_CONST 196
203#define TEGRA194_CLK_NAFLL_BPMP 197
204#define TEGRA194_CLK_NAFLL_SCE 198
205#define TEGRA194_CLK_NAFLL_NVDEC 199
206#define TEGRA194_CLK_NAFLL_NVJPG 200
207#define TEGRA194_CLK_NAFLL_TSEC 201
208#define TEGRA194_CLK_NAFLL_TSECB 202
209#define TEGRA194_CLK_NAFLL_VI 203
210#define TEGRA194_CLK_NAFLL_SE 204
211#define TEGRA194_CLK_NAFLL_NVENC 205
212#define TEGRA194_CLK_NAFLL_ISP 206
213#define TEGRA194_CLK_NAFLL_VIC 207
214#define TEGRA194_CLK_NAFLL_NVDISPLAYHUB 208
215#define TEGRA194_CLK_NAFLL_AXICBB 209
216#define TEGRA194_CLK_NAFLL_DLA 210
217#define TEGRA194_CLK_NAFLL_PVA_CORE 211
218#define TEGRA194_CLK_NAFLL_PVA_VPS 212
219#define TEGRA194_CLK_NAFLL_CVNAS 213
220#define TEGRA194_CLK_NAFLL_RCE 214
221#define TEGRA194_CLK_NAFLL_NVENC1 215
222#define TEGRA194_CLK_NAFLL_DLA_FALCON 216
223#define TEGRA194_CLK_NAFLL_NVDEC1 217
224#define TEGRA194_CLK_NAFLL_GPU 218
225#define TEGRA194_CLK_SDMMC_LEGACY_TM 219
226#define TEGRA194_CLK_PEX0_CORE_0 220
227#define TEGRA194_CLK_PEX0_CORE_1 221
228#define TEGRA194_CLK_PEX0_CORE_2 222
229#define TEGRA194_CLK_PEX0_CORE_3 223
230#define TEGRA194_CLK_PEX0_CORE_4 224
231#define TEGRA194_CLK_PEX1_CORE_5 225
232#define TEGRA194_CLK_PEX_REF1 226
233#define TEGRA194_CLK_PEX_REF2 227
234#define TEGRA194_CLK_CSI_A 229
235#define TEGRA194_CLK_CSI_B 230
236#define TEGRA194_CLK_CSI_C 231
237#define TEGRA194_CLK_CSI_D 232
238#define TEGRA194_CLK_CSI_E 233
239#define TEGRA194_CLK_CSI_F 234
240#define TEGRA194_CLK_CSI_G 235
241#define TEGRA194_CLK_CSI_H 236
242#define TEGRA194_CLK_PLLC4 237
243#define TEGRA194_CLK_PLLC4_OUT 238
244#define TEGRA194_CLK_PLLC4_OUT1 239
245#define TEGRA194_CLK_PLLC4_OUT2 240
246#define TEGRA194_CLK_PLLC4_MUXED 241
247#define TEGRA194_CLK_PLLC4_VCO_DIV2 242
248#define TEGRA194_CLK_CSI_A_PAD 244
249#define TEGRA194_CLK_CSI_B_PAD 245
250#define TEGRA194_CLK_CSI_C_PAD 246
251#define TEGRA194_CLK_CSI_D_PAD 247
252#define TEGRA194_CLK_CSI_E_PAD 248
253#define TEGRA194_CLK_CSI_F_PAD 249
254#define TEGRA194_CLK_CSI_G_PAD 250
255#define TEGRA194_CLK_CSI_H_PAD 251
256#define TEGRA194_CLK_PEX_SATA_USB_RX_BYP 254
257#define TEGRA194_CLK_PEX_USB_PAD_PLL0_MGMT 255
258#define TEGRA194_CLK_PEX_USB_PAD_PLL1_MGMT 256
259#define TEGRA194_CLK_PEX_USB_PAD_PLL2_MGMT 257
260#define TEGRA194_CLK_PEX_USB_PAD_PLL3_MGMT 258
261#define TEGRA194_CLK_XUSB_CORE_DEV 265
262#define TEGRA194_CLK_XUSB_CORE_MUX 266
263#define TEGRA194_CLK_XUSB_CORE_HOST 267
264#define TEGRA194_CLK_XUSB_CORE_SS 268
265#define TEGRA194_CLK_XUSB_FALCON 269
266#define TEGRA194_CLK_XUSB_FALCON_HOST 270
267#define TEGRA194_CLK_XUSB_FALCON_SS 271
268#define TEGRA194_CLK_XUSB_FS 272
269#define TEGRA194_CLK_XUSB_FS_HOST 273
270#define TEGRA194_CLK_XUSB_FS_DEV 274
271#define TEGRA194_CLK_XUSB_SS 275
272#define TEGRA194_CLK_XUSB_SS_DEV 276
273#define TEGRA194_CLK_XUSB_SS_SUPERSPEED 277
274#define TEGRA194_CLK_PLLDISPHUB 278
275#define TEGRA194_CLK_PLLDISPHUB_DIV 279
276#define TEGRA194_CLK_NAFLL_CLUSTER0 280
277#define TEGRA194_CLK_NAFLL_CLUSTER1 281
278#define TEGRA194_CLK_NAFLL_CLUSTER2 282
279#define TEGRA194_CLK_NAFLL_CLUSTER3 283
280#define TEGRA194_CLK_CAN1_CORE 284
281#define TEGRA194_CLK_CAN2_CORE 285
282#define TEGRA194_CLK_PLLA1_OUT1 286
283#define TEGRA194_CLK_PLLREFE_VCOOUT 288
284#define TEGRA194_CLK_CLK_32K 289
285#define TEGRA194_CLK_SPDIFIN_SYNC_INPUT 290
286#define TEGRA194_CLK_UTMIPLL_CLKOUT48 291
287#define TEGRA194_CLK_UTMIPLL_CLKOUT480 292
288#define TEGRA194_CLK_CVNAS 293
289#define TEGRA194_CLK_PLLNVCSI 294
290#define TEGRA194_CLK_PVA0_CPU_AXI 295
291#define TEGRA194_CLK_PVA1_CPU_AXI 296
292#define TEGRA194_CLK_PVA0_VPS 297
293#define TEGRA194_CLK_PVA1_VPS 298
294#define TEGRA194_CLK_DLA0_FALCON_MUX 299
295#define TEGRA194_CLK_DLA1_FALCON_MUX 300
296#define TEGRA194_CLK_DLA0_CORE_MUX 301
297#define TEGRA194_CLK_DLA1_CORE_MUX 302
298#define TEGRA194_CLK_UTMIPLL_HPS 304
299#define TEGRA194_CLK_I2C5 305
300#define TEGRA194_CLK_I2C10 306
301#define TEGRA194_CLK_BPMP_CPU_NIC 307
302#define TEGRA194_CLK_BPMP_APB 308
303#define TEGRA194_CLK_TSC 309
304#define TEGRA194_CLK_EMCSA 310
305#define TEGRA194_CLK_EMCSB 311
306#define TEGRA194_CLK_EMCSC 312
307#define TEGRA194_CLK_EMCSD 313
308#define TEGRA194_CLK_PLLC 314
309#define TEGRA194_CLK_PLLC2 315
310#define TEGRA194_CLK_PLLC3 316
311#define TEGRA194_CLK_TSC_REF 317
312#define TEGRA194_CLK_FUSE_BURN 318
313#define TEGRA194_CLK_PEX0_CORE_0M 319
314#define TEGRA194_CLK_PEX0_CORE_1M 320
315#define TEGRA194_CLK_PEX0_CORE_2M 321
316#define TEGRA194_CLK_PEX0_CORE_3M 322
317#define TEGRA194_CLK_PEX0_CORE_4M 323
318#define TEGRA194_CLK_PEX1_CORE_5M 324
319#define TEGRA194_CLK_PLLE_HPS 326
320
321#endif
diff --git a/include/dt-bindings/gpio/tegra194-gpio.h b/include/dt-bindings/gpio/tegra194-gpio.h
new file mode 100644
index 000000000000..ede860225f6b
--- /dev/null
+++ b/include/dt-bindings/gpio/tegra194-gpio.h
@@ -0,0 +1,61 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */
3
4/*
5 * This header provides constants for binding nvidia,tegra194-gpio*.
6 *
7 * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
8 * provide names for this.
9 *
10 * The second cell contains standard flag values specified in gpio.h.
11 */
12
13#ifndef _DT_BINDINGS_GPIO_TEGRA194_GPIO_H
14#define _DT_BINDINGS_GPIO_TEGRA194_GPIO_H
15
16#include <dt-bindings/gpio/gpio.h>
17
18/* GPIOs implemented by main GPIO controller */
19#define TEGRA194_MAIN_GPIO_PORT_A 0
20#define TEGRA194_MAIN_GPIO_PORT_B 1
21#define TEGRA194_MAIN_GPIO_PORT_C 2
22#define TEGRA194_MAIN_GPIO_PORT_D 3
23#define TEGRA194_MAIN_GPIO_PORT_E 4
24#define TEGRA194_MAIN_GPIO_PORT_F 5
25#define TEGRA194_MAIN_GPIO_PORT_G 6
26#define TEGRA194_MAIN_GPIO_PORT_H 7
27#define TEGRA194_MAIN_GPIO_PORT_I 8
28#define TEGRA194_MAIN_GPIO_PORT_J 9
29#define TEGRA194_MAIN_GPIO_PORT_K 10
30#define TEGRA194_MAIN_GPIO_PORT_L 11
31#define TEGRA194_MAIN_GPIO_PORT_M 12
32#define TEGRA194_MAIN_GPIO_PORT_N 13
33#define TEGRA194_MAIN_GPIO_PORT_O 14
34#define TEGRA194_MAIN_GPIO_PORT_P 15
35#define TEGRA194_MAIN_GPIO_PORT_Q 16
36#define TEGRA194_MAIN_GPIO_PORT_R 17
37#define TEGRA194_MAIN_GPIO_PORT_S 18
38#define TEGRA194_MAIN_GPIO_PORT_T 19
39#define TEGRA194_MAIN_GPIO_PORT_U 20
40#define TEGRA194_MAIN_GPIO_PORT_V 21
41#define TEGRA194_MAIN_GPIO_PORT_W 22
42#define TEGRA194_MAIN_GPIO_PORT_X 23
43#define TEGRA194_MAIN_GPIO_PORT_Y 24
44#define TEGRA194_MAIN_GPIO_PORT_Z 25
45#define TEGRA194_MAIN_GPIO_PORT_FF 26
46#define TEGRA194_MAIN_GPIO_PORT_GG 27
47
48#define TEGRA194_MAIN_GPIO(port, offset) \
49 ((TEGRA194_MAIN_GPIO_PORT_##port * 8) + offset)
50
51/* GPIOs implemented by AON GPIO controller */
52#define TEGRA194_AON_GPIO_PORT_AA 0
53#define TEGRA194_AON_GPIO_PORT_BB 1
54#define TEGRA194_AON_GPIO_PORT_CC 2
55#define TEGRA194_AON_GPIO_PORT_DD 3
56#define TEGRA194_AON_GPIO_PORT_EE 4
57
58#define TEGRA194_AON_GPIO(port, offset) \
59 ((TEGRA194_AON_GPIO_PORT_##port * 8) + offset)
60
61#endif
diff --git a/include/dt-bindings/power/tegra194-powergate.h b/include/dt-bindings/power/tegra194-powergate.h
new file mode 100644
index 000000000000..82253742a493
--- /dev/null
+++ b/include/dt-bindings/power/tegra194-powergate.h
@@ -0,0 +1,35 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */
3
4#ifndef __ABI_MACH_T194_POWERGATE_T194_H_
5#define __ABI_MACH_T194_POWERGATE_T194_H_
6
7#define TEGRA194_POWER_DOMAIN_AUD 1
8#define TEGRA194_POWER_DOMAIN_DISP 2
9#define TEGRA194_POWER_DOMAIN_DISPB 3
10#define TEGRA194_POWER_DOMAIN_DISPC 4
11#define TEGRA194_POWER_DOMAIN_ISPA 5
12#define TEGRA194_POWER_DOMAIN_NVDECA 6
13#define TEGRA194_POWER_DOMAIN_NVJPG 7
14#define TEGRA194_POWER_DOMAIN_NVENCA 8
15#define TEGRA194_POWER_DOMAIN_NVENCB 9
16#define TEGRA194_POWER_DOMAIN_NVDECB 10
17#define TEGRA194_POWER_DOMAIN_SAX 11
18#define TEGRA194_POWER_DOMAIN_VE 12
19#define TEGRA194_POWER_DOMAIN_VIC 13
20#define TEGRA194_POWER_DOMAIN_XUSBA 14
21#define TEGRA194_POWER_DOMAIN_XUSBB 15
22#define TEGRA194_POWER_DOMAIN_XUSBC 16
23#define TEGRA194_POWER_DOMAIN_PCIEX8A 17
24#define TEGRA194_POWER_DOMAIN_PCIEX4A 18
25#define TEGRA194_POWER_DOMAIN_PCIEX1A 19
26#define TEGRA194_POWER_DOMAIN_PCIEX8B 21
27#define TEGRA194_POWER_DOMAIN_PVAA 22
28#define TEGRA194_POWER_DOMAIN_PVAB 23
29#define TEGRA194_POWER_DOMAIN_DLAA 24
30#define TEGRA194_POWER_DOMAIN_DLAB 25
31#define TEGRA194_POWER_DOMAIN_CV 26
32#define TEGRA194_POWER_DOMAIN_GPU 27
33#define TEGRA194_POWER_DOMAIN_MAX 27
34
35#endif
diff --git a/include/dt-bindings/reset/tegra194-reset.h b/include/dt-bindings/reset/tegra194-reset.h
new file mode 100644
index 000000000000..473afaa25bfb
--- /dev/null
+++ b/include/dt-bindings/reset/tegra194-reset.h
@@ -0,0 +1,152 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */
3
4#ifndef __ABI_MACH_T194_RESET_H
5#define __ABI_MACH_T194_RESET_H
6
7#define TEGRA194_RESET_ACTMON 1
8#define TEGRA194_RESET_ADSP_ALL 2
9#define TEGRA194_RESET_AFI 3
10#define TEGRA194_RESET_CAN1 4
11#define TEGRA194_RESET_CAN2 5
12#define TEGRA194_RESET_DLA0 6
13#define TEGRA194_RESET_DLA1 7
14#define TEGRA194_RESET_DPAUX 8
15#define TEGRA194_RESET_DPAUX1 9
16#define TEGRA194_RESET_DPAUX2 10
17#define TEGRA194_RESET_DPAUX3 11
18#define TEGRA194_RESET_EQOS 17
19#define TEGRA194_RESET_GPCDMA 18
20#define TEGRA194_RESET_GPU 19
21#define TEGRA194_RESET_HDA 20
22#define TEGRA194_RESET_HDA2CODEC_2X 21
23#define TEGRA194_RESET_HDA2HDMICODEC 22
24#define TEGRA194_RESET_HOST1X 23
25#define TEGRA194_RESET_I2C1 24
26#define TEGRA194_RESET_I2C10 25
27#define TEGRA194_RESET_RSVD_26 26
28#define TEGRA194_RESET_RSVD_27 27
29#define TEGRA194_RESET_RSVD_28 28
30#define TEGRA194_RESET_I2C2 29
31#define TEGRA194_RESET_I2C3 30
32#define TEGRA194_RESET_I2C4 31
33#define TEGRA194_RESET_I2C6 32
34#define TEGRA194_RESET_I2C7 33
35#define TEGRA194_RESET_I2C8 34
36#define TEGRA194_RESET_I2C9 35
37#define TEGRA194_RESET_ISP 36
38#define TEGRA194_RESET_MIPI_CAL 37
39#define TEGRA194_RESET_MPHY_CLK_CTL 38
40#define TEGRA194_RESET_MPHY_L0_RX 39
41#define TEGRA194_RESET_MPHY_L0_TX 40
42#define TEGRA194_RESET_MPHY_L1_RX 41
43#define TEGRA194_RESET_MPHY_L1_TX 42
44#define TEGRA194_RESET_NVCSI 43
45#define TEGRA194_RESET_NVDEC 44
46#define TEGRA194_RESET_NVDISPLAY0_HEAD0 45
47#define TEGRA194_RESET_NVDISPLAY0_HEAD1 46
48#define TEGRA194_RESET_NVDISPLAY0_HEAD2 47
49#define TEGRA194_RESET_NVDISPLAY0_HEAD3 48
50#define TEGRA194_RESET_NVDISPLAY0_MISC 49
51#define TEGRA194_RESET_NVDISPLAY0_WGRP0 50
52#define TEGRA194_RESET_NVDISPLAY0_WGRP1 51
53#define TEGRA194_RESET_NVDISPLAY0_WGRP2 52
54#define TEGRA194_RESET_NVDISPLAY0_WGRP3 53
55#define TEGRA194_RESET_NVDISPLAY0_WGRP4 54
56#define TEGRA194_RESET_NVDISPLAY0_WGRP5 55
57#define TEGRA194_RESET_RSVD_56 56
58#define TEGRA194_RESET_RSVD_57 57
59#define TEGRA194_RESET_RSVD_58 58
60#define TEGRA194_RESET_NVENC 59
61#define TEGRA194_RESET_NVENC1 60
62#define TEGRA194_RESET_NVJPG 61
63#define TEGRA194_RESET_PCIE 62
64#define TEGRA194_RESET_PCIEXCLK 63
65#define TEGRA194_RESET_RSVD_64 64
66#define TEGRA194_RESET_RSVD_65 65
67#define TEGRA194_RESET_PVA0_ALL 66
68#define TEGRA194_RESET_PVA1_ALL 67
69#define TEGRA194_RESET_PWM1 68
70#define TEGRA194_RESET_PWM2 69
71#define TEGRA194_RESET_PWM3 70
72#define TEGRA194_RESET_PWM4 71
73#define TEGRA194_RESET_PWM5 72
74#define TEGRA194_RESET_PWM6 73
75#define TEGRA194_RESET_PWM7 74
76#define TEGRA194_RESET_PWM8 75
77#define TEGRA194_RESET_QSPI0 76
78#define TEGRA194_RESET_QSPI1 77
79#define TEGRA194_RESET_SATA 78
80#define TEGRA194_RESET_SATACOLD 79
81#define TEGRA194_RESET_SCE_ALL 80
82#define TEGRA194_RESET_RCE_ALL 81
83#define TEGRA194_RESET_SDMMC1 82
84#define TEGRA194_RESET_RSVD_83 83
85#define TEGRA194_RESET_SDMMC3 84
86#define TEGRA194_RESET_SDMMC4 85
87#define TEGRA194_RESET_SE 86
88#define TEGRA194_RESET_SOR0 87
89#define TEGRA194_RESET_SOR1 88
90#define TEGRA194_RESET_SOR2 89
91#define TEGRA194_RESET_SOR3 90
92#define TEGRA194_RESET_SPI1 91
93#define TEGRA194_RESET_SPI2 92
94#define TEGRA194_RESET_SPI3 93
95#define TEGRA194_RESET_SPI4 94
96#define TEGRA194_RESET_TACH 95
97#define TEGRA194_RESET_RSVD_96 96
98#define TEGRA194_RESET_TSCTNVI 97
99#define TEGRA194_RESET_TSEC 98
100#define TEGRA194_RESET_TSECB 99
101#define TEGRA194_RESET_UARTA 100
102#define TEGRA194_RESET_UARTB 101
103#define TEGRA194_RESET_UARTC 102
104#define TEGRA194_RESET_UARTD 103
105#define TEGRA194_RESET_UARTE 104
106#define TEGRA194_RESET_UARTF 105
107#define TEGRA194_RESET_UARTG 106
108#define TEGRA194_RESET_UARTH 107
109#define TEGRA194_RESET_UFSHC 108
110#define TEGRA194_RESET_UFSHC_AXI_M 109
111#define TEGRA194_RESET_UFSHC_LP_SEQ 110
112#define TEGRA194_RESET_RSVD_111 111
113#define TEGRA194_RESET_VI 112
114#define TEGRA194_RESET_VIC 113
115#define TEGRA194_RESET_XUSB_PADCTL 114
116#define TEGRA194_RESET_NVDEC1 115
117#define TEGRA194_RESET_PEX0_CORE_0 116
118#define TEGRA194_RESET_PEX0_CORE_1 117
119#define TEGRA194_RESET_PEX0_CORE_2 118
120#define TEGRA194_RESET_PEX0_CORE_3 119
121#define TEGRA194_RESET_PEX0_CORE_4 120
122#define TEGRA194_RESET_PEX0_CORE_0_APB 121
123#define TEGRA194_RESET_PEX0_CORE_1_APB 122
124#define TEGRA194_RESET_PEX0_CORE_2_APB 123
125#define TEGRA194_RESET_PEX0_CORE_3_APB 124
126#define TEGRA194_RESET_PEX0_CORE_4_APB 125
127#define TEGRA194_RESET_PEX0_COMMON_APB 126
128#define TEGRA194_RESET_PEX1_CORE_5 129
129#define TEGRA194_RESET_PEX1_CORE_5_APB 130
130#define TEGRA194_RESET_CVNAS 131
131#define TEGRA194_RESET_CVNAS_FCM 132
132#define TEGRA194_RESET_DMIC5 144
133#define TEGRA194_RESET_APE 145
134#define TEGRA194_RESET_PEX_USB_UPHY 146
135#define TEGRA194_RESET_PEX_USB_UPHY_L0 147
136#define TEGRA194_RESET_PEX_USB_UPHY_L1 148
137#define TEGRA194_RESET_PEX_USB_UPHY_L2 149
138#define TEGRA194_RESET_PEX_USB_UPHY_L3 150
139#define TEGRA194_RESET_PEX_USB_UPHY_L4 151
140#define TEGRA194_RESET_PEX_USB_UPHY_L5 152
141#define TEGRA194_RESET_PEX_USB_UPHY_L6 153
142#define TEGRA194_RESET_PEX_USB_UPHY_L7 154
143#define TEGRA194_RESET_PEX_USB_UPHY_L8 155
144#define TEGRA194_RESET_PEX_USB_UPHY_L9 156
145#define TEGRA194_RESET_PEX_USB_UPHY_L10 157
146#define TEGRA194_RESET_PEX_USB_UPHY_L11 158
147#define TEGRA194_RESET_PEX_USB_UPHY_PLL0 159
148#define TEGRA194_RESET_PEX_USB_UPHY_PLL1 160
149#define TEGRA194_RESET_PEX_USB_UPHY_PLL2 161
150#define TEGRA194_RESET_PEX_USB_UPHY_PLL3 162
151
152#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-24 17:41:49 -0400