aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--arch/arm/kernel/smp.c2
-rw-r--r--arch/s390/Kconfig1
-rw-r--r--arch/s390/include/asm/ftrace.h12
-rw-r--r--arch/s390/include/asm/page.h20
-rw-r--r--arch/s390/include/asm/pgtable.h4
-rw-r--r--arch/s390/kernel/dis.c2
-rw-r--r--arch/s390/kernel/ftrace.c9
-rw-r--r--arch/s390/kernel/mcount.S2
-rw-r--r--arch/s390/kernel/mcount64.S2
-rw-r--r--arch/s390/kernel/smp.c2
-rw-r--r--arch/s390/mm/pgtable.c3
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/nvc0.c2
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c2
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c10
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c3
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/bios/init.c4
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/ltcg/nvc0.c17
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drm.c25
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c6
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c31
-rw-r--r--drivers/gpu/drm/radeon/evergreen_hdmi.c7
-rw-r--r--drivers/gpu/drm/radeon/r600_hdmi.c9
-rw-r--r--drivers/gpu/drm/radeon/radeon.h2
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.c22
-rw-r--r--drivers/gpu/drm/radeon/radeon_bios.c28
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c1
-rw-r--r--drivers/gpu/drm/radeon/radeon_family.h1
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_crtc.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h1
-rw-r--r--drivers/gpu/drm/radeon/radeon_ttm.c2
-rw-r--r--drivers/gpu/drm/radeon/si.c370
-rw-r--r--drivers/gpu/drm/radeon/sid.h1
-rw-r--r--drivers/i2c/busses/i2c-designware-core.c14
-rw-r--r--drivers/i2c/busses/i2c-designware-core.h2
-rw-r--r--drivers/i2c/busses/i2c-designware-platdrv.c1
-rw-r--r--drivers/i2c/busses/i2c-i801.c6
-rw-r--r--drivers/i2c/busses/i2c-mv64xxx.c8
-rw-r--r--drivers/i2c/i2c-core.c3
-rw-r--r--drivers/s390/block/xpram.c1
-rw-r--r--drivers/s390/cio/chp.c36
-rw-r--r--drivers/s390/cio/chsc.h4
-rw-r--r--include/drm/drm_pciids.h6
42 files changed, 515 insertions, 173 deletions
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 47ab90563bf4..550d63cef68e 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -251,7 +251,7 @@ void __ref cpu_die(void)
251 * this returns, power and/or clocks can be removed at any point 251 * this returns, power and/or clocks can be removed at any point
252 * from this CPU and its cache by platform_cpu_kill(). 252 * from this CPU and its cache by platform_cpu_kill().
253 */ 253 */
254 RCU_NONIDLE(complete(&cpu_died)); 254 complete(&cpu_died);
255 255
256 /* 256 /*
257 * Ensure that the cache lines associated with that completion are 257 * Ensure that the cache lines associated with that completion are
diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
index 2c9789da0e24..da183c5a103c 100644
--- a/arch/s390/Kconfig
+++ b/arch/s390/Kconfig
@@ -98,7 +98,6 @@ config S390
98 select CLONE_BACKWARDS2 98 select CLONE_BACKWARDS2
99 select GENERIC_CLOCKEVENTS 99 select GENERIC_CLOCKEVENTS
100 select GENERIC_CPU_DEVICES if !SMP 100 select GENERIC_CPU_DEVICES if !SMP
101 select GENERIC_KERNEL_THREAD
102 select GENERIC_SMP_IDLE_THREAD 101 select GENERIC_SMP_IDLE_THREAD
103 select GENERIC_TIME_VSYSCALL_OLD 102 select GENERIC_TIME_VSYSCALL_OLD
104 select HAVE_ALIGNED_STRUCT_PAGE if SLUB 103 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
diff --git a/arch/s390/include/asm/ftrace.h b/arch/s390/include/asm/ftrace.h
index b7931faaef6d..bf246dae1367 100644
--- a/arch/s390/include/asm/ftrace.h
+++ b/arch/s390/include/asm/ftrace.h
@@ -9,11 +9,6 @@ struct dyn_arch_ftrace { };
9 9
10#define MCOUNT_ADDR ((long)_mcount) 10#define MCOUNT_ADDR ((long)_mcount)
11 11
12#ifdef CONFIG_64BIT
13#define MCOUNT_INSN_SIZE 12
14#else
15#define MCOUNT_INSN_SIZE 20
16#endif
17 12
18static inline unsigned long ftrace_call_adjust(unsigned long addr) 13static inline unsigned long ftrace_call_adjust(unsigned long addr)
19{ 14{
@@ -21,4 +16,11 @@ static inline unsigned long ftrace_call_adjust(unsigned long addr)
21} 16}
22 17
23#endif /* __ASSEMBLY__ */ 18#endif /* __ASSEMBLY__ */
19
20#ifdef CONFIG_64BIT
21#define MCOUNT_INSN_SIZE 12
22#else
23#define MCOUNT_INSN_SIZE 22
24#endif
25
24#endif /* _ASM_S390_FTRACE_H */ 26#endif /* _ASM_S390_FTRACE_H */
diff --git a/arch/s390/include/asm/page.h b/arch/s390/include/asm/page.h
index 75ce9b065f9f..5d64fb7619cc 100644
--- a/arch/s390/include/asm/page.h
+++ b/arch/s390/include/asm/page.h
@@ -32,7 +32,7 @@
32 32
33void storage_key_init_range(unsigned long start, unsigned long end); 33void storage_key_init_range(unsigned long start, unsigned long end);
34 34
35static unsigned long pfmf(unsigned long function, unsigned long address) 35static inline unsigned long pfmf(unsigned long function, unsigned long address)
36{ 36{
37 asm volatile( 37 asm volatile(
38 " .insn rre,0xb9af0000,%[function],%[address]" 38 " .insn rre,0xb9af0000,%[function],%[address]"
@@ -44,17 +44,13 @@ static unsigned long pfmf(unsigned long function, unsigned long address)
44 44
45static inline void clear_page(void *page) 45static inline void clear_page(void *page)
46{ 46{
47 if (MACHINE_HAS_PFMF) { 47 register unsigned long reg1 asm ("1") = 0;
48 pfmf(0x10000, (unsigned long)page); 48 register void *reg2 asm ("2") = page;
49 } else { 49 register unsigned long reg3 asm ("3") = 4096;
50 register unsigned long reg1 asm ("1") = 0; 50 asm volatile(
51 register void *reg2 asm ("2") = page; 51 " mvcl 2,0"
52 register unsigned long reg3 asm ("3") = 4096; 52 : "+d" (reg2), "+d" (reg3) : "d" (reg1)
53 asm volatile( 53 : "memory", "cc");
54 " mvcl 2,0"
55 : "+d" (reg2), "+d" (reg3) : "d" (reg1)
56 : "memory", "cc");
57 }
58} 54}
59 55
60static inline void copy_page(void *to, void *from) 56static inline void copy_page(void *to, void *from)
diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h
index 4105b8221fdd..0f0de30e3e3f 100644
--- a/arch/s390/include/asm/pgtable.h
+++ b/arch/s390/include/asm/pgtable.h
@@ -306,7 +306,7 @@ extern unsigned long MODULES_END;
306#define RCP_HC_BIT 0x00200000UL 306#define RCP_HC_BIT 0x00200000UL
307#define RCP_GR_BIT 0x00040000UL 307#define RCP_GR_BIT 0x00040000UL
308#define RCP_GC_BIT 0x00020000UL 308#define RCP_GC_BIT 0x00020000UL
309#define RCP_IN_BIT 0x00008000UL /* IPTE notify bit */ 309#define RCP_IN_BIT 0x00002000UL /* IPTE notify bit */
310 310
311/* User dirty / referenced bit for KVM's migration feature */ 311/* User dirty / referenced bit for KVM's migration feature */
312#define KVM_UR_BIT 0x00008000UL 312#define KVM_UR_BIT 0x00008000UL
@@ -374,7 +374,7 @@ extern unsigned long MODULES_END;
374#define RCP_HC_BIT 0x0020000000000000UL 374#define RCP_HC_BIT 0x0020000000000000UL
375#define RCP_GR_BIT 0x0004000000000000UL 375#define RCP_GR_BIT 0x0004000000000000UL
376#define RCP_GC_BIT 0x0002000000000000UL 376#define RCP_GC_BIT 0x0002000000000000UL
377#define RCP_IN_BIT 0x0000800000000000UL /* IPTE notify bit */ 377#define RCP_IN_BIT 0x0000200000000000UL /* IPTE notify bit */
378 378
379/* User dirty / referenced bit for KVM's migration feature */ 379/* User dirty / referenced bit for KVM's migration feature */
380#define KVM_UR_BIT 0x0000800000000000UL 380#define KVM_UR_BIT 0x0000800000000000UL
diff --git a/arch/s390/kernel/dis.c b/arch/s390/kernel/dis.c
index 7f4a4a8c847c..be87d3e05a5b 100644
--- a/arch/s390/kernel/dis.c
+++ b/arch/s390/kernel/dis.c
@@ -1862,6 +1862,8 @@ void print_fn_code(unsigned char *code, unsigned long len)
1862 while (len) { 1862 while (len) {
1863 ptr = buffer; 1863 ptr = buffer;
1864 opsize = insn_length(*code); 1864 opsize = insn_length(*code);
1865 if (opsize > len)
1866 break;
1865 ptr += sprintf(ptr, "%p: ", code); 1867 ptr += sprintf(ptr, "%p: ", code);
1866 for (i = 0; i < opsize; i++) 1868 for (i = 0; i < opsize; i++)
1867 ptr += sprintf(ptr, "%02x", code[i]); 1869 ptr += sprintf(ptr, "%02x", code[i]);
diff --git a/arch/s390/kernel/ftrace.c b/arch/s390/kernel/ftrace.c
index 78bdf0e5dff7..e3043aef87a9 100644
--- a/arch/s390/kernel/ftrace.c
+++ b/arch/s390/kernel/ftrace.c
@@ -16,12 +16,6 @@
16#include <trace/syscall.h> 16#include <trace/syscall.h>
17#include <asm/asm-offsets.h> 17#include <asm/asm-offsets.h>
18 18
19#ifdef CONFIG_64BIT
20#define MCOUNT_OFFSET_RET 12
21#else
22#define MCOUNT_OFFSET_RET 22
23#endif
24
25#ifdef CONFIG_DYNAMIC_FTRACE 19#ifdef CONFIG_DYNAMIC_FTRACE
26 20
27void ftrace_disable_code(void); 21void ftrace_disable_code(void);
@@ -155,9 +149,10 @@ unsigned long __kprobes prepare_ftrace_return(unsigned long parent,
155 149
156 if (unlikely(atomic_read(&current->tracing_graph_pause))) 150 if (unlikely(atomic_read(&current->tracing_graph_pause)))
157 goto out; 151 goto out;
152 ip = (ip & PSW_ADDR_INSN) - MCOUNT_INSN_SIZE;
158 if (ftrace_push_return_trace(parent, ip, &trace.depth, 0) == -EBUSY) 153 if (ftrace_push_return_trace(parent, ip, &trace.depth, 0) == -EBUSY)
159 goto out; 154 goto out;
160 trace.func = (ip & PSW_ADDR_INSN) - MCOUNT_OFFSET_RET; 155 trace.func = ip;
161 /* Only trace if the calling function expects to. */ 156 /* Only trace if the calling function expects to. */
162 if (!ftrace_graph_entry(&trace)) { 157 if (!ftrace_graph_entry(&trace)) {
163 current->curr_ret_stack--; 158 current->curr_ret_stack--;
diff --git a/arch/s390/kernel/mcount.S b/arch/s390/kernel/mcount.S
index 4567ce20d900..08dcf21cb8df 100644
--- a/arch/s390/kernel/mcount.S
+++ b/arch/s390/kernel/mcount.S
@@ -7,6 +7,7 @@
7 7
8#include <linux/linkage.h> 8#include <linux/linkage.h>
9#include <asm/asm-offsets.h> 9#include <asm/asm-offsets.h>
10#include <asm/ftrace.h>
10 11
11 .section .kprobes.text, "ax" 12 .section .kprobes.text, "ax"
12 13
@@ -33,6 +34,7 @@ ENTRY(ftrace_caller)
33 la %r2,0(%r14) 34 la %r2,0(%r14)
34 st %r0,__SF_BACKCHAIN(%r15) 35 st %r0,__SF_BACKCHAIN(%r15)
35 la %r3,0(%r3) 36 la %r3,0(%r3)
37 ahi %r2,-MCOUNT_INSN_SIZE
36 l %r14,0b-0b(%r1) 38 l %r14,0b-0b(%r1)
37 l %r14,0(%r14) 39 l %r14,0(%r14)
38 basr %r14,%r14 40 basr %r14,%r14
diff --git a/arch/s390/kernel/mcount64.S b/arch/s390/kernel/mcount64.S
index 11332193db30..1c52eae3396a 100644
--- a/arch/s390/kernel/mcount64.S
+++ b/arch/s390/kernel/mcount64.S
@@ -7,6 +7,7 @@
7 7
8#include <linux/linkage.h> 8#include <linux/linkage.h>
9#include <asm/asm-offsets.h> 9#include <asm/asm-offsets.h>
10#include <asm/ftrace.h>
10 11
11 .section .kprobes.text, "ax" 12 .section .kprobes.text, "ax"
12 13
@@ -29,6 +30,7 @@ ENTRY(ftrace_caller)
29 stg %r1,__SF_BACKCHAIN(%r15) 30 stg %r1,__SF_BACKCHAIN(%r15)
30 lgr %r2,%r14 31 lgr %r2,%r14
31 lg %r3,168(%r15) 32 lg %r3,168(%r15)
33 aghi %r2,-MCOUNT_INSN_SIZE
32 larl %r14,ftrace_trace_function 34 larl %r14,ftrace_trace_function
33 lg %r14,0(%r14) 35 lg %r14,0(%r14)
34 basr %r14,%r14 36 basr %r14,%r14
diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c
index 8074cb4b7cbf..05674b669001 100644
--- a/arch/s390/kernel/smp.c
+++ b/arch/s390/kernel/smp.c
@@ -645,7 +645,7 @@ static int __cpuinit __smp_rescan_cpus(struct sclp_cpu_info *info,
645 continue; 645 continue;
646 pcpu = pcpu_devices + cpu; 646 pcpu = pcpu_devices + cpu;
647 pcpu->address = info->cpu[i].address; 647 pcpu->address = info->cpu[i].address;
648 pcpu->state = (cpu >= info->configured) ? 648 pcpu->state = (i >= info->configured) ?
649 CPU_STATE_STANDBY : CPU_STATE_CONFIGURED; 649 CPU_STATE_STANDBY : CPU_STATE_CONFIGURED;
650 smp_cpu_set_polarization(cpu, POLARIZATION_UNKNOWN); 650 smp_cpu_set_polarization(cpu, POLARIZATION_UNKNOWN);
651 set_cpu_present(cpu, true); 651 set_cpu_present(cpu, true);
diff --git a/arch/s390/mm/pgtable.c b/arch/s390/mm/pgtable.c
index 7805ddca833d..18dc417aaf79 100644
--- a/arch/s390/mm/pgtable.c
+++ b/arch/s390/mm/pgtable.c
@@ -677,8 +677,7 @@ int gmap_ipte_notify(struct gmap *gmap, unsigned long start, unsigned long len)
677 break; 677 break;
678 } 678 }
679 /* Get the page mapped */ 679 /* Get the page mapped */
680 if (get_user_pages(current, gmap->mm, addr, 1, 1, 0, 680 if (fixup_user_fault(current, gmap->mm, addr, FAULT_FLAG_WRITE)) {
681 NULL, NULL) != 1) {
682 rc = -EFAULT; 681 rc = -EFAULT;
683 break; 682 break;
684 } 683 }
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
index 955af122c3a6..a36e64e98ef3 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
@@ -138,7 +138,6 @@ nvc0_identify(struct nouveau_device *device)
138 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; 138 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
139 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; 139 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
140 device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; 140 device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
141 device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
142 device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass; 141 device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
143 break; 142 break;
144 case 0xce: 143 case 0xce:
@@ -225,7 +224,6 @@ nvc0_identify(struct nouveau_device *device)
225 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; 224 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
226 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; 225 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
227 device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; 226 device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
228 device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
229 device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass; 227 device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
230 break; 228 break;
231 case 0xc8: 229 case 0xc8:
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c
index ddaeb5572903..89bf459d584b 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c
@@ -47,6 +47,7 @@ nv50_fifo_playlist_update(struct nv50_fifo_priv *priv)
47 struct nouveau_gpuobj *cur; 47 struct nouveau_gpuobj *cur;
48 int i, p; 48 int i, p;
49 49
50 mutex_lock(&nv_subdev(priv)->mutex);
50 cur = priv->playlist[priv->cur_playlist]; 51 cur = priv->playlist[priv->cur_playlist];
51 priv->cur_playlist = !priv->cur_playlist; 52 priv->cur_playlist = !priv->cur_playlist;
52 53
@@ -60,6 +61,7 @@ nv50_fifo_playlist_update(struct nv50_fifo_priv *priv)
60 nv_wr32(priv, 0x0032f4, cur->addr >> 12); 61 nv_wr32(priv, 0x0032f4, cur->addr >> 12);
61 nv_wr32(priv, 0x0032ec, p); 62 nv_wr32(priv, 0x0032ec, p);
62 nv_wr32(priv, 0x002500, 0x00000101); 63 nv_wr32(priv, 0x002500, 0x00000101);
64 mutex_unlock(&nv_subdev(priv)->mutex);
63} 65}
64 66
65static int 67static int
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c
index 4d4a6b905370..46dfa68c47bb 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c
@@ -71,6 +71,7 @@ nvc0_fifo_playlist_update(struct nvc0_fifo_priv *priv)
71 struct nouveau_gpuobj *cur; 71 struct nouveau_gpuobj *cur;
72 int i, p; 72 int i, p;
73 73
74 mutex_lock(&nv_subdev(priv)->mutex);
74 cur = priv->playlist[priv->cur_playlist]; 75 cur = priv->playlist[priv->cur_playlist];
75 priv->cur_playlist = !priv->cur_playlist; 76 priv->cur_playlist = !priv->cur_playlist;
76 77
@@ -87,6 +88,7 @@ nvc0_fifo_playlist_update(struct nvc0_fifo_priv *priv)
87 nv_wr32(priv, 0x002274, 0x01f00000 | (p >> 3)); 88 nv_wr32(priv, 0x002274, 0x01f00000 | (p >> 3));
88 if (!nv_wait(priv, 0x00227c, 0x00100000, 0x00000000)) 89 if (!nv_wait(priv, 0x00227c, 0x00100000, 0x00000000))
89 nv_error(priv, "playlist update failed\n"); 90 nv_error(priv, "playlist update failed\n");
91 mutex_unlock(&nv_subdev(priv)->mutex);
90} 92}
91 93
92static int 94static int
@@ -248,9 +250,17 @@ nvc0_fifo_chan_fini(struct nouveau_object *object, bool suspend)
248 struct nvc0_fifo_priv *priv = (void *)object->engine; 250 struct nvc0_fifo_priv *priv = (void *)object->engine;
249 struct nvc0_fifo_chan *chan = (void *)object; 251 struct nvc0_fifo_chan *chan = (void *)object;
250 u32 chid = chan->base.chid; 252 u32 chid = chan->base.chid;
253 u32 mask, engine;
251 254
252 nv_mask(priv, 0x003004 + (chid * 8), 0x00000001, 0x00000000); 255 nv_mask(priv, 0x003004 + (chid * 8), 0x00000001, 0x00000000);
253 nvc0_fifo_playlist_update(priv); 256 nvc0_fifo_playlist_update(priv);
257 mask = nv_rd32(priv, 0x0025a4);
258 for (engine = 0; mask && engine < 16; engine++) {
259 if (!(mask & (1 << engine)))
260 continue;
261 nv_mask(priv, 0x0025a8 + (engine * 4), 0x00000000, 0x00000000);
262 mask &= ~(1 << engine);
263 }
254 nv_wr32(priv, 0x003000 + (chid * 8), 0x00000000); 264 nv_wr32(priv, 0x003000 + (chid * 8), 0x00000000);
255 265
256 return nouveau_fifo_channel_fini(&chan->base, suspend); 266 return nouveau_fifo_channel_fini(&chan->base, suspend);
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
index 9151919fb831..56192a7242ae 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
@@ -94,11 +94,13 @@ nve0_fifo_playlist_update(struct nve0_fifo_priv *priv, u32 engine)
94 u32 match = (engine << 16) | 0x00000001; 94 u32 match = (engine << 16) | 0x00000001;
95 int i, p; 95 int i, p;
96 96
97 mutex_lock(&nv_subdev(priv)->mutex);
97 cur = engn->playlist[engn->cur_playlist]; 98 cur = engn->playlist[engn->cur_playlist];
98 if (unlikely(cur == NULL)) { 99 if (unlikely(cur == NULL)) {
99 int ret = nouveau_gpuobj_new(nv_object(priv), NULL, 100 int ret = nouveau_gpuobj_new(nv_object(priv), NULL,
100 0x8000, 0x1000, 0, &cur); 101 0x8000, 0x1000, 0, &cur);
101 if (ret) { 102 if (ret) {
103 mutex_unlock(&nv_subdev(priv)->mutex);
102 nv_error(priv, "playlist alloc failed\n"); 104 nv_error(priv, "playlist alloc failed\n");
103 return; 105 return;
104 } 106 }
@@ -122,6 +124,7 @@ nve0_fifo_playlist_update(struct nve0_fifo_priv *priv, u32 engine)
122 nv_wr32(priv, 0x002274, (engine << 20) | (p >> 3)); 124 nv_wr32(priv, 0x002274, (engine << 20) | (p >> 3));
123 if (!nv_wait(priv, 0x002284 + (engine * 4), 0x00100000, 0x00000000)) 125 if (!nv_wait(priv, 0x002284 + (engine * 4), 0x00100000, 0x00000000))
124 nv_error(priv, "playlist %d update timeout\n", engine); 126 nv_error(priv, "playlist %d update timeout\n", engine);
127 mutex_unlock(&nv_subdev(priv)->mutex);
125} 128}
126 129
127static int 130static int
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/init.c b/drivers/gpu/drm/nouveau/core/subdev/bios/init.c
index c300b5e7b670..c434d398d16f 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/init.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/bios/init.c
@@ -1940,8 +1940,8 @@ init_zm_mask_add(struct nvbios_init *init)
1940 trace("ZM_MASK_ADD\tR[0x%06x] &= 0x%08x += 0x%08x\n", addr, mask, add); 1940 trace("ZM_MASK_ADD\tR[0x%06x] &= 0x%08x += 0x%08x\n", addr, mask, add);
1941 init->offset += 13; 1941 init->offset += 13;
1942 1942
1943 data = init_rd32(init, addr) & mask; 1943 data = init_rd32(init, addr);
1944 data |= ((data + add) & ~mask); 1944 data = (data & mask) | ((data + add) & ~mask);
1945 init_wr32(init, addr, data); 1945 init_wr32(init, addr, data);
1946} 1946}
1947 1947
diff --git a/drivers/gpu/drm/nouveau/core/subdev/ltcg/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/ltcg/nvc0.c
index e4940fb166e8..fb794e997fbc 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/ltcg/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/ltcg/nvc0.c
@@ -29,7 +29,6 @@
29struct nvc0_ltcg_priv { 29struct nvc0_ltcg_priv {
30 struct nouveau_ltcg base; 30 struct nouveau_ltcg base;
31 u32 part_nr; 31 u32 part_nr;
32 u32 part_mask;
33 u32 subp_nr; 32 u32 subp_nr;
34 struct nouveau_mm tags; 33 struct nouveau_mm tags;
35 u32 num_tags; 34 u32 num_tags;
@@ -105,8 +104,6 @@ nvc0_ltcg_tags_clear(struct nouveau_ltcg *ltcg, u32 first, u32 count)
105 104
106 /* wait until it's finished with clearing */ 105 /* wait until it's finished with clearing */
107 for (p = 0; p < priv->part_nr; ++p) { 106 for (p = 0; p < priv->part_nr; ++p) {
108 if (!(priv->part_mask & (1 << p)))
109 continue;
110 for (i = 0; i < priv->subp_nr; ++i) 107 for (i = 0; i < priv->subp_nr; ++i)
111 nv_wait(priv, 0x1410c8 + p * 0x2000 + i * 0x400, ~0, 0); 108 nv_wait(priv, 0x1410c8 + p * 0x2000 + i * 0x400, ~0, 0);
112 } 109 }
@@ -121,6 +118,8 @@ nvc0_ltcg_init_tag_ram(struct nouveau_fb *pfb, struct nvc0_ltcg_priv *priv)
121 int ret; 118 int ret;
122 119
123 nv_wr32(priv, 0x17e8d8, priv->part_nr); 120 nv_wr32(priv, 0x17e8d8, priv->part_nr);
121 if (nv_device(pfb)->card_type >= NV_E0)
122 nv_wr32(priv, 0x17e000, priv->part_nr);
124 123
125 /* tags for 1/4 of VRAM should be enough (8192/4 per GiB of VRAM) */ 124 /* tags for 1/4 of VRAM should be enough (8192/4 per GiB of VRAM) */
126 priv->num_tags = (pfb->ram.size >> 17) / 4; 125 priv->num_tags = (pfb->ram.size >> 17) / 4;
@@ -167,16 +166,20 @@ nvc0_ltcg_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
167{ 166{
168 struct nvc0_ltcg_priv *priv; 167 struct nvc0_ltcg_priv *priv;
169 struct nouveau_fb *pfb = nouveau_fb(parent); 168 struct nouveau_fb *pfb = nouveau_fb(parent);
170 int ret; 169 u32 parts, mask;
170 int ret, i;
171 171
172 ret = nouveau_ltcg_create(parent, engine, oclass, &priv); 172 ret = nouveau_ltcg_create(parent, engine, oclass, &priv);
173 *pobject = nv_object(priv); 173 *pobject = nv_object(priv);
174 if (ret) 174 if (ret)
175 return ret; 175 return ret;
176 176
177 priv->part_nr = nv_rd32(priv, 0x022438); 177 parts = nv_rd32(priv, 0x022438);
178 priv->part_mask = nv_rd32(priv, 0x022554); 178 mask = nv_rd32(priv, 0x022554);
179 179 for (i = 0; i < parts; i++) {
180 if (!(mask & (1 << i)))
181 priv->part_nr++;
182 }
180 priv->subp_nr = nv_rd32(priv, 0x17e8dc) >> 28; 183 priv->subp_nr = nv_rd32(priv, 0x17e8dc) >> 28;
181 184
182 nv_mask(priv, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */ 185 nv_mask(priv, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c
index 46c152ff0a80..383f4e6ea9d1 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@ -453,18 +453,32 @@ nouveau_do_suspend(struct drm_device *dev)
453 NV_INFO(drm, "evicting buffers...\n"); 453 NV_INFO(drm, "evicting buffers...\n");
454 ttm_bo_evict_mm(&drm->ttm.bdev, TTM_PL_VRAM); 454 ttm_bo_evict_mm(&drm->ttm.bdev, TTM_PL_VRAM);
455 455
456 NV_INFO(drm, "waiting for kernel channels to go idle...\n");
457 if (drm->cechan) {
458 ret = nouveau_channel_idle(drm->cechan);
459 if (ret)
460 return ret;
461 }
462
463 if (drm->channel) {
464 ret = nouveau_channel_idle(drm->channel);
465 if (ret)
466 return ret;
467 }
468
469 NV_INFO(drm, "suspending client object trees...\n");
456 if (drm->fence && nouveau_fence(drm)->suspend) { 470 if (drm->fence && nouveau_fence(drm)->suspend) {
457 if (!nouveau_fence(drm)->suspend(drm)) 471 if (!nouveau_fence(drm)->suspend(drm))
458 return -ENOMEM; 472 return -ENOMEM;
459 } 473 }
460 474
461 NV_INFO(drm, "suspending client object trees...\n");
462 list_for_each_entry(cli, &drm->clients, head) { 475 list_for_each_entry(cli, &drm->clients, head) {
463 ret = nouveau_client_fini(&cli->base, true); 476 ret = nouveau_client_fini(&cli->base, true);
464 if (ret) 477 if (ret)
465 goto fail_client; 478 goto fail_client;
466 } 479 }
467 480
481 NV_INFO(drm, "suspending kernel object tree...\n");
468 ret = nouveau_client_fini(&drm->client.base, true); 482 ret = nouveau_client_fini(&drm->client.base, true);
469 if (ret) 483 if (ret)
470 goto fail_client; 484 goto fail_client;
@@ -514,17 +528,18 @@ nouveau_do_resume(struct drm_device *dev)
514 528
515 nouveau_agp_reset(drm); 529 nouveau_agp_reset(drm);
516 530
517 NV_INFO(drm, "resuming client object trees...\n"); 531 NV_INFO(drm, "resuming kernel object tree...\n");
518 nouveau_client_init(&drm->client.base); 532 nouveau_client_init(&drm->client.base);
519 nouveau_agp_init(drm); 533 nouveau_agp_init(drm);
520 534
535 NV_INFO(drm, "resuming client object trees...\n");
536 if (drm->fence && nouveau_fence(drm)->resume)
537 nouveau_fence(drm)->resume(drm);
538
521 list_for_each_entry(cli, &drm->clients, head) { 539 list_for_each_entry(cli, &drm->clients, head) {
522 nouveau_client_init(&cli->base); 540 nouveau_client_init(&cli->base);
523 } 541 }
524 542
525 if (drm->fence && nouveau_fence(drm)->resume)
526 nouveau_fence(drm)->resume(drm);
527
528 nouveau_run_vbios_init(dev); 543 nouveau_run_vbios_init(dev);
529 nouveau_pm_resume(dev); 544 nouveau_pm_resume(dev);
530 545
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 6d6fdb3ba0d0..d5df8fd10217 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1811,12 +1811,9 @@ static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1811 1811
1812static void atombios_crtc_prepare(struct drm_crtc *crtc) 1812static void atombios_crtc_prepare(struct drm_crtc *crtc)
1813{ 1813{
1814 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1815 struct drm_device *dev = crtc->dev; 1814 struct drm_device *dev = crtc->dev;
1816 struct radeon_device *rdev = dev->dev_private; 1815 struct radeon_device *rdev = dev->dev_private;
1817 1816
1818 radeon_crtc->in_mode_set = true;
1819
1820 /* disable crtc pair power gating before programming */ 1817 /* disable crtc pair power gating before programming */
1821 if (ASIC_IS_DCE6(rdev)) 1818 if (ASIC_IS_DCE6(rdev))
1822 atombios_powergate_crtc(crtc, ATOM_DISABLE); 1819 atombios_powergate_crtc(crtc, ATOM_DISABLE);
@@ -1827,11 +1824,8 @@ static void atombios_crtc_prepare(struct drm_crtc *crtc)
1827 1824
1828static void atombios_crtc_commit(struct drm_crtc *crtc) 1825static void atombios_crtc_commit(struct drm_crtc *crtc)
1829{ 1826{
1830 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1831
1832 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 1827 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1833 atombios_lock_crtc(crtc, ATOM_DISABLE); 1828 atombios_lock_crtc(crtc, ATOM_DISABLE);
1834 radeon_crtc->in_mode_set = false;
1835} 1829}
1836 1830
1837static void atombios_crtc_disable(struct drm_crtc *crtc) 1831static void atombios_crtc_disable(struct drm_crtc *crtc)
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 105bafb6c29d..8f9e2d31b255 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -2343,11 +2343,13 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
2343 u32 crtc_enabled, tmp, frame_count, blackout; 2343 u32 crtc_enabled, tmp, frame_count, blackout;
2344 int i, j; 2344 int i, j;
2345 2345
2346 save->vga_render_control = RREG32(VGA_RENDER_CONTROL); 2346 if (!ASIC_IS_NODCE(rdev)) {
2347 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL); 2347 save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
2348 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
2348 2349
2349 /* disable VGA render */ 2350 /* disable VGA render */
2350 WREG32(VGA_RENDER_CONTROL, 0); 2351 WREG32(VGA_RENDER_CONTROL, 0);
2352 }
2351 /* blank the display controllers */ 2353 /* blank the display controllers */
2352 for (i = 0; i < rdev->num_crtc; i++) { 2354 for (i = 0; i < rdev->num_crtc; i++) {
2353 crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN; 2355 crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN;
@@ -2438,8 +2440,11 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s
2438 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], 2440 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
2439 (u32)rdev->mc.vram_start); 2441 (u32)rdev->mc.vram_start);
2440 } 2442 }
2441 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start)); 2443
2442 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); 2444 if (!ASIC_IS_NODCE(rdev)) {
2445 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
2446 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
2447 }
2443 2448
2444 /* unlock regs and wait for update */ 2449 /* unlock regs and wait for update */
2445 for (i = 0; i < rdev->num_crtc; i++) { 2450 for (i = 0; i < rdev->num_crtc; i++) {
@@ -2499,10 +2504,12 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s
2499 } 2504 }
2500 } 2505 }
2501 } 2506 }
2502 /* Unlock vga access */ 2507 if (!ASIC_IS_NODCE(rdev)) {
2503 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control); 2508 /* Unlock vga access */
2504 mdelay(1); 2509 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
2505 WREG32(VGA_RENDER_CONTROL, save->vga_render_control); 2510 mdelay(1);
2511 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
2512 }
2506} 2513}
2507 2514
2508void evergreen_mc_program(struct radeon_device *rdev) 2515void evergreen_mc_program(struct radeon_device *rdev)
@@ -3405,8 +3412,8 @@ int evergreen_mc_init(struct radeon_device *rdev)
3405 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 3412 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
3406 } else { 3413 } else {
3407 /* size in MB on evergreen/cayman/tn */ 3414 /* size in MB on evergreen/cayman/tn */
3408 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; 3415 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
3409 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; 3416 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
3410 } 3417 }
3411 rdev->mc.visible_vram_size = rdev->mc.aper_size; 3418 rdev->mc.visible_vram_size = rdev->mc.aper_size;
3412 r700_vram_gtt_location(rdev, &rdev->mc); 3419 r700_vram_gtt_location(rdev, &rdev->mc);
diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c
index b4ab8ceb1654..ed7c8a768092 100644
--- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
+++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
@@ -154,19 +154,18 @@ static void evergreen_audio_set_dto(struct drm_encoder *encoder, u32 clock)
154 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 154 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
155 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 155 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
156 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 156 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
157 u32 base_rate = 48000; 157 u32 base_rate = 24000;
158 158
159 if (!dig || !dig->afmt) 159 if (!dig || !dig->afmt)
160 return; 160 return;
161 161
162 /* XXX: properly calculate this */
163 /* XXX two dtos; generally use dto0 for hdmi */ 162 /* XXX two dtos; generally use dto0 for hdmi */
164 /* Express [24MHz / target pixel clock] as an exact rational 163 /* Express [24MHz / target pixel clock] as an exact rational
165 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 164 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
166 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 165 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
167 */ 166 */
168 WREG32(DCCG_AUDIO_DTO0_PHASE, (base_rate*50) & 0xffffff); 167 WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100);
169 WREG32(DCCG_AUDIO_DTO0_MODULE, (clock*100) & 0xffffff); 168 WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);
170 WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id)); 169 WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id));
171} 170}
172 171
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
index 47f180a79352..456750a0daa5 100644
--- a/drivers/gpu/drm/radeon/r600_hdmi.c
+++ b/drivers/gpu/drm/radeon/r600_hdmi.c
@@ -232,7 +232,7 @@ void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)
232 struct radeon_device *rdev = dev->dev_private; 232 struct radeon_device *rdev = dev->dev_private;
233 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 233 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
234 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 234 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
235 u32 base_rate = 48000; 235 u32 base_rate = 24000;
236 236
237 if (!dig || !dig->afmt) 237 if (!dig || !dig->afmt)
238 return; 238 return;
@@ -240,7 +240,6 @@ void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)
240 /* there are two DTOs selected by DCCG_AUDIO_DTO_SELECT. 240 /* there are two DTOs selected by DCCG_AUDIO_DTO_SELECT.
241 * doesn't matter which one you use. Just use the first one. 241 * doesn't matter which one you use. Just use the first one.
242 */ 242 */
243 /* XXX: properly calculate this */
244 /* XXX two dtos; generally use dto0 for hdmi */ 243 /* XXX two dtos; generally use dto0 for hdmi */
245 /* Express [24MHz / target pixel clock] as an exact rational 244 /* Express [24MHz / target pixel clock] as an exact rational
246 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 245 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
@@ -250,13 +249,13 @@ void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)
250 /* according to the reg specs, this should DCE3.2 only, but in 249 /* according to the reg specs, this should DCE3.2 only, but in
251 * practice it seems to cover DCE3.0 as well. 250 * practice it seems to cover DCE3.0 as well.
252 */ 251 */
253 WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 50); 252 WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100);
254 WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100); 253 WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);
255 WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */ 254 WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
256 } else { 255 } else {
257 /* according to the reg specs, this should be DCE2.0 and DCE3.0 */ 256 /* according to the reg specs, this should be DCE2.0 and DCE3.0 */
258 WREG32(AUDIO_DTO, AUDIO_DTO_PHASE(base_rate * 50) | 257 WREG32(AUDIO_DTO, AUDIO_DTO_PHASE(base_rate / 10) |
259 AUDIO_DTO_MODULE(clock * 100)); 258 AUDIO_DTO_MODULE(clock / 10));
260 } 259 }
261} 260}
262 261
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 1442ce765d48..142ce6cc69f5 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1694,6 +1694,7 @@ struct radeon_device {
1694 int num_crtc; /* number of crtcs */ 1694 int num_crtc; /* number of crtcs */
1695 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 1695 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1696 bool audio_enabled; 1696 bool audio_enabled;
1697 bool has_uvd;
1697 struct r600_audio audio_status; /* audio stuff */ 1698 struct r600_audio audio_status; /* audio stuff */
1698 struct notifier_block acpi_nb; 1699 struct notifier_block acpi_nb;
1699 /* only one userspace can use Hyperz features or CMASK at a time */ 1700 /* only one userspace can use Hyperz features or CMASK at a time */
@@ -1838,6 +1839,7 @@ void r100_pll_errata_after_index(struct radeon_device *rdev);
1838#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 1839#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
1839 (rdev->flags & RADEON_IS_IGP)) 1840 (rdev->flags & RADEON_IS_IGP))
1840#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) 1841#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
1842#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
1841 1843
1842/* 1844/*
1843 * BIOS helpers. 1845 * BIOS helpers.
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index 6417132c50cf..06b8c19ab19e 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -1935,6 +1935,8 @@ int radeon_asic_init(struct radeon_device *rdev)
1935 else 1935 else
1936 rdev->num_crtc = 2; 1936 rdev->num_crtc = 2;
1937 1937
1938 rdev->has_uvd = false;
1939
1938 switch (rdev->family) { 1940 switch (rdev->family) {
1939 case CHIP_R100: 1941 case CHIP_R100:
1940 case CHIP_RV100: 1942 case CHIP_RV100:
@@ -1999,16 +2001,22 @@ int radeon_asic_init(struct radeon_device *rdev)
1999 case CHIP_RV635: 2001 case CHIP_RV635:
2000 case CHIP_RV670: 2002 case CHIP_RV670:
2001 rdev->asic = &r600_asic; 2003 rdev->asic = &r600_asic;
2004 if (rdev->family == CHIP_R600)
2005 rdev->has_uvd = false;
2006 else
2007 rdev->has_uvd = true;
2002 break; 2008 break;
2003 case CHIP_RS780: 2009 case CHIP_RS780:
2004 case CHIP_RS880: 2010 case CHIP_RS880:
2005 rdev->asic = &rs780_asic; 2011 rdev->asic = &rs780_asic;
2012 rdev->has_uvd = true;
2006 break; 2013 break;
2007 case CHIP_RV770: 2014 case CHIP_RV770:
2008 case CHIP_RV730: 2015 case CHIP_RV730:
2009 case CHIP_RV710: 2016 case CHIP_RV710:
2010 case CHIP_RV740: 2017 case CHIP_RV740:
2011 rdev->asic = &rv770_asic; 2018 rdev->asic = &rv770_asic;
2019 rdev->has_uvd = true;
2012 break; 2020 break;
2013 case CHIP_CEDAR: 2021 case CHIP_CEDAR:
2014 case CHIP_REDWOOD: 2022 case CHIP_REDWOOD:
@@ -2021,11 +2029,13 @@ int radeon_asic_init(struct radeon_device *rdev)
2021 else 2029 else
2022 rdev->num_crtc = 6; 2030 rdev->num_crtc = 6;
2023 rdev->asic = &evergreen_asic; 2031 rdev->asic = &evergreen_asic;
2032 rdev->has_uvd = true;
2024 break; 2033 break;
2025 case CHIP_PALM: 2034 case CHIP_PALM:
2026 case CHIP_SUMO: 2035 case CHIP_SUMO:
2027 case CHIP_SUMO2: 2036 case CHIP_SUMO2:
2028 rdev->asic = &sumo_asic; 2037 rdev->asic = &sumo_asic;
2038 rdev->has_uvd = true;
2029 break; 2039 break;
2030 case CHIP_BARTS: 2040 case CHIP_BARTS:
2031 case CHIP_TURKS: 2041 case CHIP_TURKS:
@@ -2036,27 +2046,37 @@ int radeon_asic_init(struct radeon_device *rdev)
2036 else 2046 else
2037 rdev->num_crtc = 6; 2047 rdev->num_crtc = 6;
2038 rdev->asic = &btc_asic; 2048 rdev->asic = &btc_asic;
2049 rdev->has_uvd = true;
2039 break; 2050 break;
2040 case CHIP_CAYMAN: 2051 case CHIP_CAYMAN:
2041 rdev->asic = &cayman_asic; 2052 rdev->asic = &cayman_asic;
2042 /* set num crtcs */ 2053 /* set num crtcs */
2043 rdev->num_crtc = 6; 2054 rdev->num_crtc = 6;
2055 rdev->has_uvd = true;
2044 break; 2056 break;
2045 case CHIP_ARUBA: 2057 case CHIP_ARUBA:
2046 rdev->asic = &trinity_asic; 2058 rdev->asic = &trinity_asic;
2047 /* set num crtcs */ 2059 /* set num crtcs */
2048 rdev->num_crtc = 4; 2060 rdev->num_crtc = 4;
2061 rdev->has_uvd = true;
2049 break; 2062 break;
2050 case CHIP_TAHITI: 2063 case CHIP_TAHITI:
2051 case CHIP_PITCAIRN: 2064 case CHIP_PITCAIRN:
2052 case CHIP_VERDE: 2065 case CHIP_VERDE:
2053 case CHIP_OLAND: 2066 case CHIP_OLAND:
2067 case CHIP_HAINAN:
2054 rdev->asic = &si_asic; 2068 rdev->asic = &si_asic;
2055 /* set num crtcs */ 2069 /* set num crtcs */
2056 if (rdev->family == CHIP_OLAND) 2070 if (rdev->family == CHIP_HAINAN)
2071 rdev->num_crtc = 0;
2072 else if (rdev->family == CHIP_OLAND)
2057 rdev->num_crtc = 2; 2073 rdev->num_crtc = 2;
2058 else 2074 else
2059 rdev->num_crtc = 6; 2075 rdev->num_crtc = 6;
2076 if (rdev->family == CHIP_HAINAN)
2077 rdev->has_uvd = false;
2078 else
2079 rdev->has_uvd = true;
2060 break; 2080 break;
2061 default: 2081 default:
2062 /* FIXME: not supported yet */ 2082 /* FIXME: not supported yet */
diff --git a/drivers/gpu/drm/radeon/radeon_bios.c b/drivers/gpu/drm/radeon/radeon_bios.c
index fa3c56fba294..061b227dae0c 100644
--- a/drivers/gpu/drm/radeon/radeon_bios.c
+++ b/drivers/gpu/drm/radeon/radeon_bios.c
@@ -244,24 +244,28 @@ static bool ni_read_disabled_bios(struct radeon_device *rdev)
244 244
245 /* enable the rom */ 245 /* enable the rom */
246 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 246 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
247 /* Disable VGA mode */ 247 if (!ASIC_IS_NODCE(rdev)) {
248 WREG32(AVIVO_D1VGA_CONTROL, 248 /* Disable VGA mode */
249 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 249 WREG32(AVIVO_D1VGA_CONTROL,
250 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 250 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
251 WREG32(AVIVO_D2VGA_CONTROL, 251 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
252 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 252 WREG32(AVIVO_D2VGA_CONTROL,
253 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 253 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
254 WREG32(AVIVO_VGA_RENDER_CONTROL, 254 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
255 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 255 WREG32(AVIVO_VGA_RENDER_CONTROL,
256 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
257 }
256 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); 258 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
257 259
258 r = radeon_read_bios(rdev); 260 r = radeon_read_bios(rdev);
259 261
260 /* restore regs */ 262 /* restore regs */
261 WREG32(R600_BUS_CNTL, bus_cntl); 263 WREG32(R600_BUS_CNTL, bus_cntl);
262 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 264 if (!ASIC_IS_NODCE(rdev)) {
263 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 265 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
264 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 266 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
267 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
268 }
265 WREG32(R600_ROM_CNTL, rom_cntl); 269 WREG32(R600_ROM_CNTL, rom_cntl);
266 return r; 270 return r;
267} 271}
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index a8f608903989..c2c59fb1ea01 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -94,6 +94,7 @@ static const char radeon_family_name[][16] = {
94 "PITCAIRN", 94 "PITCAIRN",
95 "VERDE", 95 "VERDE",
96 "OLAND", 96 "OLAND",
97 "HAINAN",
97 "LAST", 98 "LAST",
98}; 99};
99 100
diff --git a/drivers/gpu/drm/radeon/radeon_family.h b/drivers/gpu/drm/radeon/radeon_family.h
index 2d91123f2759..36e9803b077d 100644
--- a/drivers/gpu/drm/radeon/radeon_family.h
+++ b/drivers/gpu/drm/radeon/radeon_family.h
@@ -92,6 +92,7 @@ enum radeon_family {
92 CHIP_PITCAIRN, 92 CHIP_PITCAIRN,
93 CHIP_VERDE, 93 CHIP_VERDE,
94 CHIP_OLAND, 94 CHIP_OLAND,
95 CHIP_HAINAN,
95 CHIP_LAST, 96 CHIP_LAST,
96}; 97};
97 98
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index 6857cb4efb76..7cb178a34a0f 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -1031,11 +1031,9 @@ static int radeon_crtc_mode_set(struct drm_crtc *crtc,
1031 1031
1032static void radeon_crtc_prepare(struct drm_crtc *crtc) 1032static void radeon_crtc_prepare(struct drm_crtc *crtc)
1033{ 1033{
1034 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1035 struct drm_device *dev = crtc->dev; 1034 struct drm_device *dev = crtc->dev;
1036 struct drm_crtc *crtci; 1035 struct drm_crtc *crtci;
1037 1036
1038 radeon_crtc->in_mode_set = true;
1039 /* 1037 /*
1040 * The hardware wedges sometimes if you reconfigure one CRTC 1038 * The hardware wedges sometimes if you reconfigure one CRTC
1041 * whilst another is running (see fdo bug #24611). 1039 * whilst another is running (see fdo bug #24611).
@@ -1046,7 +1044,6 @@ static void radeon_crtc_prepare(struct drm_crtc *crtc)
1046 1044
1047static void radeon_crtc_commit(struct drm_crtc *crtc) 1045static void radeon_crtc_commit(struct drm_crtc *crtc)
1048{ 1046{
1049 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1050 struct drm_device *dev = crtc->dev; 1047 struct drm_device *dev = crtc->dev;
1051 struct drm_crtc *crtci; 1048 struct drm_crtc *crtci;
1052 1049
@@ -1057,7 +1054,6 @@ static void radeon_crtc_commit(struct drm_crtc *crtc)
1057 if (crtci->enabled) 1054 if (crtci->enabled)
1058 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON); 1055 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON);
1059 } 1056 }
1060 radeon_crtc->in_mode_set = false;
1061} 1057}
1062 1058
1063static const struct drm_crtc_helper_funcs legacy_helper_funcs = { 1059static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 44e579e75fd0..69ad4fe224c1 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -302,7 +302,6 @@ struct radeon_crtc {
302 u16 lut_r[256], lut_g[256], lut_b[256]; 302 u16 lut_r[256], lut_g[256], lut_b[256];
303 bool enabled; 303 bool enabled;
304 bool can_tile; 304 bool can_tile;
305 bool in_mode_set;
306 uint32_t crtc_offset; 305 uint32_t crtc_offset;
307 struct drm_gem_object *cursor_bo; 306 struct drm_gem_object *cursor_bo;
308 uint64_t cursor_addr; 307 uint64_t cursor_addr;
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
index 93f760e27a92..6c0ce8915fac 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -726,7 +726,7 @@ int radeon_ttm_init(struct radeon_device *rdev)
726 return r; 726 return r;
727 } 727 }
728 DRM_INFO("radeon: %uM of VRAM memory ready\n", 728 DRM_INFO("radeon: %uM of VRAM memory ready\n",
729 (unsigned)rdev->mc.real_vram_size / (1024 * 1024)); 729 (unsigned) (rdev->mc.real_vram_size / (1024 * 1024)));
730 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, 730 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT,
731 rdev->mc.gtt_size >> PAGE_SHIFT); 731 rdev->mc.gtt_size >> PAGE_SHIFT);
732 if (r) { 732 if (r) {
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index f0b6c2f87c4d..5ffade69af25 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -60,6 +60,11 @@ MODULE_FIRMWARE("radeon/OLAND_me.bin");
60MODULE_FIRMWARE("radeon/OLAND_ce.bin"); 60MODULE_FIRMWARE("radeon/OLAND_ce.bin");
61MODULE_FIRMWARE("radeon/OLAND_mc.bin"); 61MODULE_FIRMWARE("radeon/OLAND_mc.bin");
62MODULE_FIRMWARE("radeon/OLAND_rlc.bin"); 62MODULE_FIRMWARE("radeon/OLAND_rlc.bin");
63MODULE_FIRMWARE("radeon/HAINAN_pfp.bin");
64MODULE_FIRMWARE("radeon/HAINAN_me.bin");
65MODULE_FIRMWARE("radeon/HAINAN_ce.bin");
66MODULE_FIRMWARE("radeon/HAINAN_mc.bin");
67MODULE_FIRMWARE("radeon/HAINAN_rlc.bin");
63 68
64extern int r600_ih_ring_alloc(struct radeon_device *rdev); 69extern int r600_ih_ring_alloc(struct radeon_device *rdev);
65extern void r600_ih_ring_fini(struct radeon_device *rdev); 70extern void r600_ih_ring_fini(struct radeon_device *rdev);
@@ -265,6 +270,40 @@ static const u32 oland_golden_registers[] =
265 0x15c0, 0x000c0fc0, 0x000c0400 270 0x15c0, 0x000c0fc0, 0x000c0400
266}; 271};
267 272
273static const u32 hainan_golden_registers[] =
274{
275 0x9a10, 0x00010000, 0x00018208,
276 0x9830, 0xffffffff, 0x00000000,
277 0x9834, 0xf00fffff, 0x00000400,
278 0x9838, 0x0002021c, 0x00020200,
279 0xd0c0, 0xff000fff, 0x00000100,
280 0xd030, 0x000300c0, 0x00800040,
281 0xd8c0, 0xff000fff, 0x00000100,
282 0xd830, 0x000300c0, 0x00800040,
283 0x2ae4, 0x00073ffe, 0x000022a2,
284 0x240c, 0x000007ff, 0x00000000,
285 0x8a14, 0xf000001f, 0x00000007,
286 0x8b24, 0xffffffff, 0x00ffffff,
287 0x8b10, 0x0000ff0f, 0x00000000,
288 0x28a4c, 0x07ffffff, 0x4e000000,
289 0x28350, 0x3f3f3fff, 0x00000000,
290 0x30, 0x000000ff, 0x0040,
291 0x34, 0x00000040, 0x00004040,
292 0x9100, 0x03e00000, 0x03600000,
293 0x9060, 0x0000007f, 0x00000020,
294 0x9508, 0x00010000, 0x00010000,
295 0xac14, 0x000003ff, 0x000000f1,
296 0xac10, 0xffffffff, 0x00000000,
297 0xac0c, 0xffffffff, 0x00003210,
298 0x88d4, 0x0000001f, 0x00000010,
299 0x15c0, 0x000c0fc0, 0x000c0400
300};
301
302static const u32 hainan_golden_registers2[] =
303{
304 0x98f8, 0xffffffff, 0x02010001
305};
306
268static const u32 tahiti_mgcg_cgcg_init[] = 307static const u32 tahiti_mgcg_cgcg_init[] =
269{ 308{
270 0xc400, 0xffffffff, 0xfffffffc, 309 0xc400, 0xffffffff, 0xfffffffc,
@@ -673,6 +712,83 @@ static const u32 oland_mgcg_cgcg_init[] =
673 0xd8c0, 0xfffffff0, 0x00000100 712 0xd8c0, 0xfffffff0, 0x00000100
674}; 713};
675 714
715static const u32 hainan_mgcg_cgcg_init[] =
716{
717 0xc400, 0xffffffff, 0xfffffffc,
718 0x802c, 0xffffffff, 0xe0000000,
719 0x9a60, 0xffffffff, 0x00000100,
720 0x92a4, 0xffffffff, 0x00000100,
721 0xc164, 0xffffffff, 0x00000100,
722 0x9774, 0xffffffff, 0x00000100,
723 0x8984, 0xffffffff, 0x06000100,
724 0x8a18, 0xffffffff, 0x00000100,
725 0x92a0, 0xffffffff, 0x00000100,
726 0xc380, 0xffffffff, 0x00000100,
727 0x8b28, 0xffffffff, 0x00000100,
728 0x9144, 0xffffffff, 0x00000100,
729 0x8d88, 0xffffffff, 0x00000100,
730 0x8d8c, 0xffffffff, 0x00000100,
731 0x9030, 0xffffffff, 0x00000100,
732 0x9034, 0xffffffff, 0x00000100,
733 0x9038, 0xffffffff, 0x00000100,
734 0x903c, 0xffffffff, 0x00000100,
735 0xad80, 0xffffffff, 0x00000100,
736 0xac54, 0xffffffff, 0x00000100,
737 0x897c, 0xffffffff, 0x06000100,
738 0x9868, 0xffffffff, 0x00000100,
739 0x9510, 0xffffffff, 0x00000100,
740 0xaf04, 0xffffffff, 0x00000100,
741 0xae04, 0xffffffff, 0x00000100,
742 0x949c, 0xffffffff, 0x00000100,
743 0x802c, 0xffffffff, 0xe0000000,
744 0x9160, 0xffffffff, 0x00010000,
745 0x9164, 0xffffffff, 0x00030002,
746 0x9168, 0xffffffff, 0x00040007,
747 0x916c, 0xffffffff, 0x00060005,
748 0x9170, 0xffffffff, 0x00090008,
749 0x9174, 0xffffffff, 0x00020001,
750 0x9178, 0xffffffff, 0x00040003,
751 0x917c, 0xffffffff, 0x00000007,
752 0x9180, 0xffffffff, 0x00060005,
753 0x9184, 0xffffffff, 0x00090008,
754 0x9188, 0xffffffff, 0x00030002,
755 0x918c, 0xffffffff, 0x00050004,
756 0x9190, 0xffffffff, 0x00000008,
757 0x9194, 0xffffffff, 0x00070006,
758 0x9198, 0xffffffff, 0x000a0009,
759 0x919c, 0xffffffff, 0x00040003,
760 0x91a0, 0xffffffff, 0x00060005,
761 0x91a4, 0xffffffff, 0x00000009,
762 0x91a8, 0xffffffff, 0x00080007,
763 0x91ac, 0xffffffff, 0x000b000a,
764 0x91b0, 0xffffffff, 0x00050004,
765 0x91b4, 0xffffffff, 0x00070006,
766 0x91b8, 0xffffffff, 0x0008000b,
767 0x91bc, 0xffffffff, 0x000a0009,
768 0x91c0, 0xffffffff, 0x000d000c,
769 0x91c4, 0xffffffff, 0x00060005,
770 0x91c8, 0xffffffff, 0x00080007,
771 0x91cc, 0xffffffff, 0x0000000b,
772 0x91d0, 0xffffffff, 0x000a0009,
773 0x91d4, 0xffffffff, 0x000d000c,
774 0x9150, 0xffffffff, 0x96940200,
775 0x8708, 0xffffffff, 0x00900100,
776 0xc478, 0xffffffff, 0x00000080,
777 0xc404, 0xffffffff, 0x0020003f,
778 0x30, 0xffffffff, 0x0000001c,
779 0x34, 0x000f0000, 0x000f0000,
780 0x160c, 0xffffffff, 0x00000100,
781 0x1024, 0xffffffff, 0x00000100,
782 0x20a8, 0xffffffff, 0x00000104,
783 0x264c, 0x000c0000, 0x000c0000,
784 0x2648, 0x000c0000, 0x000c0000,
785 0x2f50, 0x00000001, 0x00000001,
786 0x30cc, 0xc0000fff, 0x00000104,
787 0xc1e4, 0x00000001, 0x00000001,
788 0xd0c0, 0xfffffff0, 0x00000100,
789 0xd8c0, 0xfffffff0, 0x00000100
790};
791
676static u32 verde_pg_init[] = 792static u32 verde_pg_init[] =
677{ 793{
678 0x353c, 0xffffffff, 0x40000, 794 0x353c, 0xffffffff, 0x40000,
@@ -853,6 +969,17 @@ static void si_init_golden_registers(struct radeon_device *rdev)
853 oland_mgcg_cgcg_init, 969 oland_mgcg_cgcg_init,
854 (const u32)ARRAY_SIZE(oland_mgcg_cgcg_init)); 970 (const u32)ARRAY_SIZE(oland_mgcg_cgcg_init));
855 break; 971 break;
972 case CHIP_HAINAN:
973 radeon_program_register_sequence(rdev,
974 hainan_golden_registers,
975 (const u32)ARRAY_SIZE(hainan_golden_registers));
976 radeon_program_register_sequence(rdev,
977 hainan_golden_registers2,
978 (const u32)ARRAY_SIZE(hainan_golden_registers2));
979 radeon_program_register_sequence(rdev,
980 hainan_mgcg_cgcg_init,
981 (const u32)ARRAY_SIZE(hainan_mgcg_cgcg_init));
982 break;
856 default: 983 default:
857 break; 984 break;
858 } 985 }
@@ -1062,6 +1189,45 @@ static const u32 oland_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
1062 {0x0000009f, 0x00a17730} 1189 {0x0000009f, 0x00a17730}
1063}; 1190};
1064 1191
1192static const u32 hainan_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
1193 {0x0000006f, 0x03044000},
1194 {0x00000070, 0x0480c018},
1195 {0x00000071, 0x00000040},
1196 {0x00000072, 0x01000000},
1197 {0x00000074, 0x000000ff},
1198 {0x00000075, 0x00143400},
1199 {0x00000076, 0x08ec0800},
1200 {0x00000077, 0x040000cc},
1201 {0x00000079, 0x00000000},
1202 {0x0000007a, 0x21000409},
1203 {0x0000007c, 0x00000000},
1204 {0x0000007d, 0xe8000000},
1205 {0x0000007e, 0x044408a8},
1206 {0x0000007f, 0x00000003},
1207 {0x00000080, 0x00000000},
1208 {0x00000081, 0x01000000},
1209 {0x00000082, 0x02000000},
1210 {0x00000083, 0x00000000},
1211 {0x00000084, 0xe3f3e4f4},
1212 {0x00000085, 0x00052024},
1213 {0x00000087, 0x00000000},
1214 {0x00000088, 0x66036603},
1215 {0x00000089, 0x01000000},
1216 {0x0000008b, 0x1c0a0000},
1217 {0x0000008c, 0xff010000},
1218 {0x0000008e, 0xffffefff},
1219 {0x0000008f, 0xfff3efff},
1220 {0x00000090, 0xfff3efbf},
1221 {0x00000094, 0x00101101},
1222 {0x00000095, 0x00000fff},
1223 {0x00000096, 0x00116fff},
1224 {0x00000097, 0x60010000},
1225 {0x00000098, 0x10010000},
1226 {0x00000099, 0x00006000},
1227 {0x0000009a, 0x00001000},
1228 {0x0000009f, 0x00a07730}
1229};
1230
1065/* ucode loading */ 1231/* ucode loading */
1066static int si_mc_load_microcode(struct radeon_device *rdev) 1232static int si_mc_load_microcode(struct radeon_device *rdev)
1067{ 1233{
@@ -1095,6 +1261,11 @@ static int si_mc_load_microcode(struct radeon_device *rdev)
1095 ucode_size = OLAND_MC_UCODE_SIZE; 1261 ucode_size = OLAND_MC_UCODE_SIZE;
1096 regs_size = TAHITI_IO_MC_REGS_SIZE; 1262 regs_size = TAHITI_IO_MC_REGS_SIZE;
1097 break; 1263 break;
1264 case CHIP_HAINAN:
1265 io_mc_regs = (u32 *)&hainan_io_mc_regs;
1266 ucode_size = OLAND_MC_UCODE_SIZE;
1267 regs_size = TAHITI_IO_MC_REGS_SIZE;
1268 break;
1098 } 1269 }
1099 1270
1100 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; 1271 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
@@ -1198,6 +1369,15 @@ static int si_init_microcode(struct radeon_device *rdev)
1198 rlc_req_size = SI_RLC_UCODE_SIZE * 4; 1369 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1199 mc_req_size = OLAND_MC_UCODE_SIZE * 4; 1370 mc_req_size = OLAND_MC_UCODE_SIZE * 4;
1200 break; 1371 break;
1372 case CHIP_HAINAN:
1373 chip_name = "HAINAN";
1374 rlc_chip_name = "HAINAN";
1375 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
1376 me_req_size = SI_PM4_UCODE_SIZE * 4;
1377 ce_req_size = SI_CE_UCODE_SIZE * 4;
1378 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1379 mc_req_size = OLAND_MC_UCODE_SIZE * 4;
1380 break;
1201 default: BUG(); 1381 default: BUG();
1202 } 1382 }
1203 1383
@@ -2003,7 +2183,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
2003 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); 2183 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
2004 } 2184 }
2005 } else if ((rdev->family == CHIP_VERDE) || 2185 } else if ((rdev->family == CHIP_VERDE) ||
2006 (rdev->family == CHIP_OLAND)) { 2186 (rdev->family == CHIP_OLAND) ||
2187 (rdev->family == CHIP_HAINAN)) {
2007 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { 2188 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
2008 switch (reg_offset) { 2189 switch (reg_offset) {
2009 case 0: /* non-AA compressed depth or any compressed stencil */ 2190 case 0: /* non-AA compressed depth or any compressed stencil */
@@ -2466,6 +2647,23 @@ static void si_gpu_init(struct radeon_device *rdev)
2466 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; 2647 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
2467 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; 2648 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
2468 break; 2649 break;
2650 case CHIP_HAINAN:
2651 rdev->config.si.max_shader_engines = 1;
2652 rdev->config.si.max_tile_pipes = 4;
2653 rdev->config.si.max_cu_per_sh = 5;
2654 rdev->config.si.max_sh_per_se = 1;
2655 rdev->config.si.max_backends_per_se = 1;
2656 rdev->config.si.max_texture_channel_caches = 2;
2657 rdev->config.si.max_gprs = 256;
2658 rdev->config.si.max_gs_threads = 16;
2659 rdev->config.si.max_hw_contexts = 8;
2660
2661 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
2662 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
2663 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
2664 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
2665 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN;
2666 break;
2469 } 2667 }
2470 2668
2471 /* Initialize HDP */ 2669 /* Initialize HDP */
@@ -2559,9 +2757,11 @@ static void si_gpu_init(struct radeon_device *rdev)
2559 WREG32(HDP_ADDR_CONFIG, gb_addr_config); 2757 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
2560 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); 2758 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
2561 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); 2759 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
2562 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config); 2760 if (rdev->has_uvd) {
2563 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); 2761 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
2564 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); 2762 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
2763 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
2764 }
2565 2765
2566 si_tiling_mode_table_init(rdev); 2766 si_tiling_mode_table_init(rdev);
2567 2767
@@ -3304,8 +3504,9 @@ static void si_mc_program(struct radeon_device *rdev)
3304 if (radeon_mc_wait_for_idle(rdev)) { 3504 if (radeon_mc_wait_for_idle(rdev)) {
3305 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 3505 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3306 } 3506 }
3307 /* Lockout access through VGA aperture*/ 3507 if (!ASIC_IS_NODCE(rdev))
3308 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 3508 /* Lockout access through VGA aperture*/
3509 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
3309 /* Update configuration */ 3510 /* Update configuration */
3310 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 3511 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
3311 rdev->mc.vram_start >> 12); 3512 rdev->mc.vram_start >> 12);
@@ -3327,9 +3528,11 @@ static void si_mc_program(struct radeon_device *rdev)
3327 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 3528 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3328 } 3529 }
3329 evergreen_mc_resume(rdev, &save); 3530 evergreen_mc_resume(rdev, &save);
3330 /* we need to own VRAM, so turn off the VGA renderer here 3531 if (!ASIC_IS_NODCE(rdev)) {
3331 * to stop it overwriting our objects */ 3532 /* we need to own VRAM, so turn off the VGA renderer here
3332 rv515_vga_render_disable(rdev); 3533 * to stop it overwriting our objects */
3534 rv515_vga_render_disable(rdev);
3535 }
3333} 3536}
3334 3537
3335static void si_vram_gtt_location(struct radeon_device *rdev, 3538static void si_vram_gtt_location(struct radeon_device *rdev,
@@ -3397,8 +3600,8 @@ static int si_mc_init(struct radeon_device *rdev)
3397 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 3600 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
3398 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 3601 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
3399 /* size in MB on si */ 3602 /* size in MB on si */
3400 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; 3603 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
3401 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; 3604 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
3402 rdev->mc.visible_vram_size = rdev->mc.aper_size; 3605 rdev->mc.visible_vram_size = rdev->mc.aper_size;
3403 si_vram_gtt_location(rdev, &rdev->mc); 3606 si_vram_gtt_location(rdev, &rdev->mc);
3404 radeon_update_bandwidth_info(rdev); 3607 radeon_update_bandwidth_info(rdev);
@@ -4251,8 +4454,10 @@ static void si_disable_interrupt_state(struct radeon_device *rdev)
4251 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; 4454 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
4252 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp); 4455 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp);
4253 WREG32(GRBM_INT_CNTL, 0); 4456 WREG32(GRBM_INT_CNTL, 0);
4254 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 4457 if (rdev->num_crtc >= 2) {
4255 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 4458 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
4459 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
4460 }
4256 if (rdev->num_crtc >= 4) { 4461 if (rdev->num_crtc >= 4) {
4257 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 4462 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
4258 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 4463 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
@@ -4262,8 +4467,10 @@ static void si_disable_interrupt_state(struct radeon_device *rdev)
4262 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 4467 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
4263 } 4468 }
4264 4469
4265 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 4470 if (rdev->num_crtc >= 2) {
4266 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 4471 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
4472 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
4473 }
4267 if (rdev->num_crtc >= 4) { 4474 if (rdev->num_crtc >= 4) {
4268 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 4475 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
4269 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 4476 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
@@ -4273,21 +4480,22 @@ static void si_disable_interrupt_state(struct radeon_device *rdev)
4273 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 4480 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
4274 } 4481 }
4275 4482
4276 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); 4483 if (!ASIC_IS_NODCE(rdev)) {
4277 4484 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
4278 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
4279 WREG32(DC_HPD1_INT_CONTROL, tmp);
4280 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
4281 WREG32(DC_HPD2_INT_CONTROL, tmp);
4282 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
4283 WREG32(DC_HPD3_INT_CONTROL, tmp);
4284 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
4285 WREG32(DC_HPD4_INT_CONTROL, tmp);
4286 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
4287 WREG32(DC_HPD5_INT_CONTROL, tmp);
4288 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
4289 WREG32(DC_HPD6_INT_CONTROL, tmp);
4290 4485
4486 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
4487 WREG32(DC_HPD1_INT_CONTROL, tmp);
4488 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
4489 WREG32(DC_HPD2_INT_CONTROL, tmp);
4490 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
4491 WREG32(DC_HPD3_INT_CONTROL, tmp);
4492 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
4493 WREG32(DC_HPD4_INT_CONTROL, tmp);
4494 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
4495 WREG32(DC_HPD5_INT_CONTROL, tmp);
4496 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
4497 WREG32(DC_HPD6_INT_CONTROL, tmp);
4498 }
4291} 4499}
4292 4500
4293static int si_irq_init(struct radeon_device *rdev) 4501static int si_irq_init(struct radeon_device *rdev)
@@ -4366,7 +4574,7 @@ int si_irq_set(struct radeon_device *rdev)
4366 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; 4574 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
4367 u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0; 4575 u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
4368 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; 4576 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
4369 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; 4577 u32 hpd1 = 0, hpd2 = 0, hpd3 = 0, hpd4 = 0, hpd5 = 0, hpd6 = 0;
4370 u32 grbm_int_cntl = 0; 4578 u32 grbm_int_cntl = 0;
4371 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0; 4579 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
4372 u32 dma_cntl, dma_cntl1; 4580 u32 dma_cntl, dma_cntl1;
@@ -4383,12 +4591,14 @@ int si_irq_set(struct radeon_device *rdev)
4383 return 0; 4591 return 0;
4384 } 4592 }
4385 4593
4386 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; 4594 if (!ASIC_IS_NODCE(rdev)) {
4387 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; 4595 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
4388 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; 4596 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
4389 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; 4597 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
4390 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; 4598 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
4391 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; 4599 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
4600 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
4601 }
4392 4602
4393 dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; 4603 dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
4394 dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; 4604 dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
@@ -4479,8 +4689,10 @@ int si_irq_set(struct radeon_device *rdev)
4479 4689
4480 WREG32(GRBM_INT_CNTL, grbm_int_cntl); 4690 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
4481 4691
4482 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); 4692 if (rdev->num_crtc >= 2) {
4483 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); 4693 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
4694 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
4695 }
4484 if (rdev->num_crtc >= 4) { 4696 if (rdev->num_crtc >= 4) {
4485 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); 4697 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
4486 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); 4698 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
@@ -4490,8 +4702,10 @@ int si_irq_set(struct radeon_device *rdev)
4490 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); 4702 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
4491 } 4703 }
4492 4704
4493 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1); 4705 if (rdev->num_crtc >= 2) {
4494 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2); 4706 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
4707 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
4708 }
4495 if (rdev->num_crtc >= 4) { 4709 if (rdev->num_crtc >= 4) {
4496 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3); 4710 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
4497 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4); 4711 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
@@ -4501,12 +4715,14 @@ int si_irq_set(struct radeon_device *rdev)
4501 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6); 4715 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
4502 } 4716 }
4503 4717
4504 WREG32(DC_HPD1_INT_CONTROL, hpd1); 4718 if (!ASIC_IS_NODCE(rdev)) {
4505 WREG32(DC_HPD2_INT_CONTROL, hpd2); 4719 WREG32(DC_HPD1_INT_CONTROL, hpd1);
4506 WREG32(DC_HPD3_INT_CONTROL, hpd3); 4720 WREG32(DC_HPD2_INT_CONTROL, hpd2);
4507 WREG32(DC_HPD4_INT_CONTROL, hpd4); 4721 WREG32(DC_HPD3_INT_CONTROL, hpd3);
4508 WREG32(DC_HPD5_INT_CONTROL, hpd5); 4722 WREG32(DC_HPD4_INT_CONTROL, hpd4);
4509 WREG32(DC_HPD6_INT_CONTROL, hpd6); 4723 WREG32(DC_HPD5_INT_CONTROL, hpd5);
4724 WREG32(DC_HPD6_INT_CONTROL, hpd6);
4725 }
4510 4726
4511 return 0; 4727 return 0;
4512} 4728}
@@ -4515,6 +4731,9 @@ static inline void si_irq_ack(struct radeon_device *rdev)
4515{ 4731{
4516 u32 tmp; 4732 u32 tmp;
4517 4733
4734 if (ASIC_IS_NODCE(rdev))
4735 return;
4736
4518 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS); 4737 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
4519 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); 4738 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
4520 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2); 4739 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
@@ -5118,15 +5337,17 @@ static int si_startup(struct radeon_device *rdev)
5118 return r; 5337 return r;
5119 } 5338 }
5120 5339
5121 r = rv770_uvd_resume(rdev); 5340 if (rdev->has_uvd) {
5122 if (!r) { 5341 r = rv770_uvd_resume(rdev);
5123 r = radeon_fence_driver_start_ring(rdev, 5342 if (!r) {
5124 R600_RING_TYPE_UVD_INDEX); 5343 r = radeon_fence_driver_start_ring(rdev,
5344 R600_RING_TYPE_UVD_INDEX);
5345 if (r)
5346 dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
5347 }
5125 if (r) 5348 if (r)
5126 dev_err(rdev->dev, "UVD fences init error (%d).\n", r); 5349 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
5127 } 5350 }
5128 if (r)
5129 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
5130 5351
5131 /* Enable IRQ */ 5352 /* Enable IRQ */
5132 r = si_irq_init(rdev); 5353 r = si_irq_init(rdev);
@@ -5185,16 +5406,18 @@ static int si_startup(struct radeon_device *rdev)
5185 if (r) 5406 if (r)
5186 return r; 5407 return r;
5187 5408
5188 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; 5409 if (rdev->has_uvd) {
5189 if (ring->ring_size) { 5410 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
5190 r = radeon_ring_init(rdev, ring, ring->ring_size, 5411 if (ring->ring_size) {
5191 R600_WB_UVD_RPTR_OFFSET, 5412 r = radeon_ring_init(rdev, ring, ring->ring_size,
5192 UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR, 5413 R600_WB_UVD_RPTR_OFFSET,
5193 0, 0xfffff, RADEON_CP_PACKET2); 5414 UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
5194 if (!r) 5415 0, 0xfffff, RADEON_CP_PACKET2);
5195 r = r600_uvd_init(rdev); 5416 if (!r)
5196 if (r) 5417 r = r600_uvd_init(rdev);
5197 DRM_ERROR("radeon: failed initializing UVD (%d).\n", r); 5418 if (r)
5419 DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
5420 }
5198 } 5421 }
5199 5422
5200 r = radeon_ib_pool_init(rdev); 5423 r = radeon_ib_pool_init(rdev);
@@ -5243,8 +5466,10 @@ int si_suspend(struct radeon_device *rdev)
5243 radeon_vm_manager_fini(rdev); 5466 radeon_vm_manager_fini(rdev);
5244 si_cp_enable(rdev, false); 5467 si_cp_enable(rdev, false);
5245 cayman_dma_stop(rdev); 5468 cayman_dma_stop(rdev);
5246 r600_uvd_rbc_stop(rdev); 5469 if (rdev->has_uvd) {
5247 radeon_uvd_suspend(rdev); 5470 r600_uvd_rbc_stop(rdev);
5471 radeon_uvd_suspend(rdev);
5472 }
5248 si_irq_suspend(rdev); 5473 si_irq_suspend(rdev);
5249 radeon_wb_disable(rdev); 5474 radeon_wb_disable(rdev);
5250 si_pcie_gart_disable(rdev); 5475 si_pcie_gart_disable(rdev);
@@ -5332,11 +5557,13 @@ int si_init(struct radeon_device *rdev)
5332 ring->ring_obj = NULL; 5557 ring->ring_obj = NULL;
5333 r600_ring_init(rdev, ring, 64 * 1024); 5558 r600_ring_init(rdev, ring, 64 * 1024);
5334 5559
5335 r = radeon_uvd_init(rdev); 5560 if (rdev->has_uvd) {
5336 if (!r) { 5561 r = radeon_uvd_init(rdev);
5337 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; 5562 if (!r) {
5338 ring->ring_obj = NULL; 5563 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
5339 r600_ring_init(rdev, ring, 4096); 5564 ring->ring_obj = NULL;
5565 r600_ring_init(rdev, ring, 4096);
5566 }
5340 } 5567 }
5341 5568
5342 rdev->ih.ring_obj = NULL; 5569 rdev->ih.ring_obj = NULL;
@@ -5384,7 +5611,8 @@ void si_fini(struct radeon_device *rdev)
5384 radeon_vm_manager_fini(rdev); 5611 radeon_vm_manager_fini(rdev);
5385 radeon_ib_pool_fini(rdev); 5612 radeon_ib_pool_fini(rdev);
5386 radeon_irq_kms_fini(rdev); 5613 radeon_irq_kms_fini(rdev);
5387 radeon_uvd_fini(rdev); 5614 if (rdev->has_uvd)
5615 radeon_uvd_fini(rdev);
5388 si_pcie_gart_fini(rdev); 5616 si_pcie_gart_fini(rdev);
5389 r600_vram_scratch_fini(rdev); 5617 r600_vram_scratch_fini(rdev);
5390 radeon_gem_fini(rdev); 5618 radeon_gem_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
index 222877ba6cf5..8f2d7d4f9b28 100644
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -28,6 +28,7 @@
28 28
29#define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003 29#define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003
30#define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002 30#define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002
31#define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02010001
31 32
32/* discrete uvd clocks */ 33/* discrete uvd clocks */
33#define CG_UPLL_FUNC_CNTL 0x634 34#define CG_UPLL_FUNC_CNTL 0x634
diff --git a/drivers/i2c/busses/i2c-designware-core.c b/drivers/i2c/busses/i2c-designware-core.c
index 21fbb340ad66..c41ca6354fc5 100644
--- a/drivers/i2c/busses/i2c-designware-core.c
+++ b/drivers/i2c/busses/i2c-designware-core.c
@@ -383,7 +383,8 @@ static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
383 /* Enable the adapter */ 383 /* Enable the adapter */
384 __i2c_dw_enable(dev, true); 384 __i2c_dw_enable(dev, true);
385 385
386 /* Enable interrupts */ 386 /* Clear and enable interrupts */
387 i2c_dw_clear_int(dev);
387 dw_writel(dev, DW_IC_INTR_DEFAULT_MASK, DW_IC_INTR_MASK); 388 dw_writel(dev, DW_IC_INTR_DEFAULT_MASK, DW_IC_INTR_MASK);
388} 389}
389 390
@@ -448,8 +449,14 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
448 cmd |= BIT(9); 449 cmd |= BIT(9);
449 450
450 if (msgs[dev->msg_write_idx].flags & I2C_M_RD) { 451 if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
452
453 /* avoid rx buffer overrun */
454 if (rx_limit - dev->rx_outstanding <= 0)
455 break;
456
451 dw_writel(dev, cmd | 0x100, DW_IC_DATA_CMD); 457 dw_writel(dev, cmd | 0x100, DW_IC_DATA_CMD);
452 rx_limit--; 458 rx_limit--;
459 dev->rx_outstanding++;
453 } else 460 } else
454 dw_writel(dev, cmd | *buf++, DW_IC_DATA_CMD); 461 dw_writel(dev, cmd | *buf++, DW_IC_DATA_CMD);
455 tx_limit--; buf_len--; 462 tx_limit--; buf_len--;
@@ -502,8 +509,10 @@ i2c_dw_read(struct dw_i2c_dev *dev)
502 509
503 rx_valid = dw_readl(dev, DW_IC_RXFLR); 510 rx_valid = dw_readl(dev, DW_IC_RXFLR);
504 511
505 for (; len > 0 && rx_valid > 0; len--, rx_valid--) 512 for (; len > 0 && rx_valid > 0; len--, rx_valid--) {
506 *buf++ = dw_readl(dev, DW_IC_DATA_CMD); 513 *buf++ = dw_readl(dev, DW_IC_DATA_CMD);
514 dev->rx_outstanding--;
515 }
507 516
508 if (len > 0) { 517 if (len > 0) {
509 dev->status |= STATUS_READ_IN_PROGRESS; 518 dev->status |= STATUS_READ_IN_PROGRESS;
@@ -561,6 +570,7 @@ i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
561 dev->msg_err = 0; 570 dev->msg_err = 0;
562 dev->status = STATUS_IDLE; 571 dev->status = STATUS_IDLE;
563 dev->abort_source = 0; 572 dev->abort_source = 0;
573 dev->rx_outstanding = 0;
564 574
565 ret = i2c_dw_wait_bus_not_busy(dev); 575 ret = i2c_dw_wait_bus_not_busy(dev);
566 if (ret < 0) 576 if (ret < 0)
diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/i2c-designware-core.h
index 9c1840ee09c7..e761ad18dd61 100644
--- a/drivers/i2c/busses/i2c-designware-core.h
+++ b/drivers/i2c/busses/i2c-designware-core.h
@@ -60,6 +60,7 @@
60 * @adapter: i2c subsystem adapter node 60 * @adapter: i2c subsystem adapter node
61 * @tx_fifo_depth: depth of the hardware tx fifo 61 * @tx_fifo_depth: depth of the hardware tx fifo
62 * @rx_fifo_depth: depth of the hardware rx fifo 62 * @rx_fifo_depth: depth of the hardware rx fifo
63 * @rx_outstanding: current master-rx elements in tx fifo
63 */ 64 */
64struct dw_i2c_dev { 65struct dw_i2c_dev {
65 struct device *dev; 66 struct device *dev;
@@ -88,6 +89,7 @@ struct dw_i2c_dev {
88 u32 master_cfg; 89 u32 master_cfg;
89 unsigned int tx_fifo_depth; 90 unsigned int tx_fifo_depth;
90 unsigned int rx_fifo_depth; 91 unsigned int rx_fifo_depth;
92 int rx_outstanding;
91}; 93};
92 94
93#define ACCESS_SWAP 0x00000001 95#define ACCESS_SWAP 0x00000001
diff --git a/drivers/i2c/busses/i2c-designware-platdrv.c b/drivers/i2c/busses/i2c-designware-platdrv.c
index 8ec91335d95a..35b70a1edf57 100644
--- a/drivers/i2c/busses/i2c-designware-platdrv.c
+++ b/drivers/i2c/busses/i2c-designware-platdrv.c
@@ -69,6 +69,7 @@ static int dw_i2c_acpi_configure(struct platform_device *pdev)
69static const struct acpi_device_id dw_i2c_acpi_match[] = { 69static const struct acpi_device_id dw_i2c_acpi_match[] = {
70 { "INT33C2", 0 }, 70 { "INT33C2", 0 },
71 { "INT33C3", 0 }, 71 { "INT33C3", 0 },
72 { "80860F41", 0 },
72 { } 73 { }
73}; 74};
74MODULE_DEVICE_TABLE(acpi, dw_i2c_acpi_match); 75MODULE_DEVICE_TABLE(acpi, dw_i2c_acpi_match);
diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c
index e1cf2e0e1f23..3a6903f63913 100644
--- a/drivers/i2c/busses/i2c-i801.c
+++ b/drivers/i2c/busses/i2c-i801.c
@@ -231,7 +231,11 @@ static const char *i801_feature_names[] = {
231 231
232static unsigned int disable_features; 232static unsigned int disable_features;
233module_param(disable_features, uint, S_IRUGO | S_IWUSR); 233module_param(disable_features, uint, S_IRUGO | S_IWUSR);
234MODULE_PARM_DESC(disable_features, "Disable selected driver features"); 234MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
235 "\t\t 0x01 disable SMBus PEC\n"
236 "\t\t 0x02 disable the block buffer\n"
237 "\t\t 0x08 disable the I2C block read functionality\n"
238 "\t\t 0x10 don't use interrupts ");
235 239
236/* Make sure the SMBus host is ready to start transmitting. 240/* Make sure the SMBus host is ready to start transmitting.
237 Return 0 if it is, -EBUSY if it is not. */ 241 Return 0 if it is, -EBUSY if it is not. */
diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c
index 3bbd65d35a5e..1a3abd6a0bfc 100644
--- a/drivers/i2c/busses/i2c-mv64xxx.c
+++ b/drivers/i2c/busses/i2c-mv64xxx.c
@@ -252,7 +252,7 @@ mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
252 writel(drv_data->cntl_bits, 252 writel(drv_data->cntl_bits,
253 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 253 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
254 drv_data->block = 0; 254 drv_data->block = 0;
255 wake_up_interruptible(&drv_data->waitq); 255 wake_up(&drv_data->waitq);
256 break; 256 break;
257 257
258 case MV64XXX_I2C_ACTION_CONTINUE: 258 case MV64XXX_I2C_ACTION_CONTINUE:
@@ -300,7 +300,7 @@ mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
300 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP, 300 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
301 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 301 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
302 drv_data->block = 0; 302 drv_data->block = 0;
303 wake_up_interruptible(&drv_data->waitq); 303 wake_up(&drv_data->waitq);
304 break; 304 break;
305 305
306 case MV64XXX_I2C_ACTION_INVALID: 306 case MV64XXX_I2C_ACTION_INVALID:
@@ -315,7 +315,7 @@ mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
315 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP, 315 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
316 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 316 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
317 drv_data->block = 0; 317 drv_data->block = 0;
318 wake_up_interruptible(&drv_data->waitq); 318 wake_up(&drv_data->waitq);
319 break; 319 break;
320 } 320 }
321} 321}
@@ -381,7 +381,7 @@ mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data)
381 unsigned long flags; 381 unsigned long flags;
382 char abort = 0; 382 char abort = 0;
383 383
384 time_left = wait_event_interruptible_timeout(drv_data->waitq, 384 time_left = wait_event_timeout(drv_data->waitq,
385 !drv_data->block, drv_data->adapter.timeout); 385 !drv_data->block, drv_data->adapter.timeout);
386 386
387 spin_lock_irqsave(&drv_data->lock, flags); 387 spin_lock_irqsave(&drv_data->lock, flags);
diff --git a/drivers/i2c/i2c-core.c b/drivers/i2c/i2c-core.c
index 6b63cc7eb71e..48e31ed69dbf 100644
--- a/drivers/i2c/i2c-core.c
+++ b/drivers/i2c/i2c-core.c
@@ -892,7 +892,8 @@ i2c_sysfs_delete_device(struct device *dev, struct device_attribute *attr,
892} 892}
893 893
894static DEVICE_ATTR(new_device, S_IWUSR, NULL, i2c_sysfs_new_device); 894static DEVICE_ATTR(new_device, S_IWUSR, NULL, i2c_sysfs_new_device);
895static DEVICE_ATTR(delete_device, S_IWUSR, NULL, i2c_sysfs_delete_device); 895static DEVICE_ATTR_IGNORE_LOCKDEP(delete_device, S_IWUSR, NULL,
896 i2c_sysfs_delete_device);
896 897
897static struct attribute *i2c_adapter_attrs[] = { 898static struct attribute *i2c_adapter_attrs[] = {
898 &dev_attr_name.attr, 899 &dev_attr_name.attr,
diff --git a/drivers/s390/block/xpram.c b/drivers/s390/block/xpram.c
index 690c3338a8ae..464dd29d06c0 100644
--- a/drivers/s390/block/xpram.c
+++ b/drivers/s390/block/xpram.c
@@ -343,6 +343,7 @@ static int __init xpram_setup_blkdev(void)
343 put_disk(xpram_disks[i]); 343 put_disk(xpram_disks[i]);
344 goto out; 344 goto out;
345 } 345 }
346 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, xpram_queues[i]);
346 blk_queue_make_request(xpram_queues[i], xpram_make_request); 347 blk_queue_make_request(xpram_queues[i], xpram_make_request);
347 blk_queue_logical_block_size(xpram_queues[i], 4096); 348 blk_queue_logical_block_size(xpram_queues[i], 4096);
348 } 349 }
diff --git a/drivers/s390/cio/chp.c b/drivers/s390/cio/chp.c
index 21fabc6d5a9c..6c440d4349d4 100644
--- a/drivers/s390/cio/chp.c
+++ b/drivers/s390/cio/chp.c
@@ -352,12 +352,48 @@ static ssize_t chp_shared_show(struct device *dev,
352 352
353static DEVICE_ATTR(shared, 0444, chp_shared_show, NULL); 353static DEVICE_ATTR(shared, 0444, chp_shared_show, NULL);
354 354
355static ssize_t chp_chid_show(struct device *dev, struct device_attribute *attr,
356 char *buf)
357{
358 struct channel_path *chp = to_channelpath(dev);
359 ssize_t rc;
360
361 mutex_lock(&chp->lock);
362 if (chp->desc_fmt1.flags & 0x10)
363 rc = sprintf(buf, "%04x\n", chp->desc_fmt1.chid);
364 else
365 rc = 0;
366 mutex_unlock(&chp->lock);
367
368 return rc;
369}
370static DEVICE_ATTR(chid, 0444, chp_chid_show, NULL);
371
372static ssize_t chp_chid_external_show(struct device *dev,
373 struct device_attribute *attr, char *buf)
374{
375 struct channel_path *chp = to_channelpath(dev);
376 ssize_t rc;
377
378 mutex_lock(&chp->lock);
379 if (chp->desc_fmt1.flags & 0x10)
380 rc = sprintf(buf, "%x\n", chp->desc_fmt1.flags & 0x8 ? 1 : 0);
381 else
382 rc = 0;
383 mutex_unlock(&chp->lock);
384
385 return rc;
386}
387static DEVICE_ATTR(chid_external, 0444, chp_chid_external_show, NULL);
388
355static struct attribute *chp_attrs[] = { 389static struct attribute *chp_attrs[] = {
356 &dev_attr_status.attr, 390 &dev_attr_status.attr,
357 &dev_attr_configure.attr, 391 &dev_attr_configure.attr,
358 &dev_attr_type.attr, 392 &dev_attr_type.attr,
359 &dev_attr_cmg.attr, 393 &dev_attr_cmg.attr,
360 &dev_attr_shared.attr, 394 &dev_attr_shared.attr,
395 &dev_attr_chid.attr,
396 &dev_attr_chid_external.attr,
361 NULL, 397 NULL,
362}; 398};
363static struct attribute_group chp_attr_group = { 399static struct attribute_group chp_attr_group = {
diff --git a/drivers/s390/cio/chsc.h b/drivers/s390/cio/chsc.h
index 349d5fc47196..e7ef2a683b8f 100644
--- a/drivers/s390/cio/chsc.h
+++ b/drivers/s390/cio/chsc.h
@@ -43,7 +43,9 @@ struct channel_path_desc_fmt1 {
43 u8 chpid; 43 u8 chpid;
44 u32:24; 44 u32:24;
45 u8 chpp; 45 u8 chpp;
46 u32 unused[3]; 46 u32 unused[2];
47 u16 chid;
48 u32:16;
47 u16 mdc; 49 u16 mdc;
48 u16:13; 50 u16:13;
49 u8 r:1; 51 u8 r:1;
diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h
index c2af598f701d..bb1bc485390b 100644
--- a/include/drm/drm_pciids.h
+++ b/include/drm/drm_pciids.h
@@ -152,6 +152,12 @@
152 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 152 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
153 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 153 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
154 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_NEW_MEMMAP}, \ 154 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_NEW_MEMMAP}, \
155 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
156 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
157 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
158 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
159 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
160 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
155 {0x1002, 0x6700, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \ 161 {0x1002, 0x6700, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
156 {0x1002, 0x6701, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \ 162 {0x1002, 0x6701, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
157 {0x1002, 0x6702, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \ 163 {0x1002, 0x6702, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-18 23:48:15 -0400