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-rw-r--r--arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi187
-rw-r--r--arch/arm/boot/dts/nuvoton-npcm750-evb.dts2
-rw-r--r--arch/arm/boot/dts/nuvoton-npcm750.dtsi179
3 files changed, 190 insertions, 178 deletions
diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
new file mode 100644
index 000000000000..d2d0761295a4
--- /dev/null
+++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
@@ -0,0 +1,187 @@
1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com
3// Copyright 2018 Google, Inc.
4
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6
7/ {
8 #address-cells = <1>;
9 #size-cells = <1>;
10 interrupt-parent = <&gic>;
11
12 /* external reference clock */
13 clk_refclk: clk_refclk {
14 compatible = "fixed-clock";
15 #clock-cells = <0>;
16 clock-frequency = <25000000>;
17 clock-output-names = "refclk";
18 };
19
20 /* external reference clock for cpu. float in normal operation */
21 clk_sysbypck: clk_sysbypck {
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <800000000>;
25 clock-output-names = "sysbypck";
26 };
27
28 /* external reference clock for MC. float in normal operation */
29 clk_mcbypck: clk_mcbypck {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <800000000>;
33 clock-output-names = "mcbypck";
34 };
35
36 /* external clock signal rg1refck, supplied by the phy */
37 clk_rg1refck: clk_rg1refck {
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
40 clock-frequency = <125000000>;
41 clock-output-names = "clk_rg1refck";
42 };
43
44 /* external clock signal rg2refck, supplied by the phy */
45 clk_rg2refck: clk_rg2refck {
46 compatible = "fixed-clock";
47 #clock-cells = <0>;
48 clock-frequency = <125000000>;
49 clock-output-names = "clk_rg2refck";
50 };
51
52 clk_xin: clk_xin {
53 compatible = "fixed-clock";
54 #clock-cells = <0>;
55 clock-frequency = <50000000>;
56 clock-output-names = "clk_xin";
57 };
58
59 soc {
60 #address-cells = <1>;
61 #size-cells = <1>;
62 compatible = "simple-bus";
63 interrupt-parent = <&gic>;
64 ranges = <0x0 0xf0000000 0x00900000>;
65
66 gcr: gcr@800000 {
67 compatible = "nuvoton,npcm750-gcr", "syscon",
68 "simple-mfd";
69 reg = <0x800000 0x1000>;
70 };
71
72 scu: scu@3fe000 {
73 compatible = "arm,cortex-a9-scu";
74 reg = <0x3fe000 0x1000>;
75 };
76
77 l2: cache-controller@3fc000 {
78 compatible = "arm,pl310-cache";
79 reg = <0x3fc000 0x1000>;
80 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
81 cache-unified;
82 cache-level = <2>;
83 clocks = <&clk 10>;
84 arm,shared-override;
85 };
86
87 gic: interrupt-controller@3ff000 {
88 compatible = "arm,cortex-a9-gic";
89 interrupt-controller;
90 #interrupt-cells = <3>;
91 reg = <0x3ff000 0x1000>,
92 <0x3fe100 0x100>;
93 };
94 };
95
96 ahb {
97 #address-cells = <1>;
98 #size-cells = <1>;
99 compatible = "simple-bus";
100 interrupt-parent = <&gic>;
101 ranges;
102
103 clk: clock-controller@f0801000 {
104 compatible = "nuvoton,npcm750-clk", "syscon";
105 #clock-cells = <1>;
106 clock-controller;
107 reg = <0xf0801000 0x1000>;
108 clock-names = "refclk", "sysbypck", "mcbypck";
109 clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>;
110 };
111
112 apb {
113 #address-cells = <1>;
114 #size-cells = <1>;
115 compatible = "simple-bus";
116 interrupt-parent = <&gic>;
117 ranges = <0x0 0xf0000000 0x00300000>;
118
119 timer0: timer@8000 {
120 compatible = "nuvoton,npcm750-timer";
121 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
122 reg = <0x8000 0x50>;
123 clocks = <&clk 5>;
124 };
125
126 watchdog0: watchdog@801C {
127 compatible = "nuvoton,npcm750-wdt";
128 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
129 reg = <0x801C 0x4>;
130 status = "disabled";
131 clocks = <&clk 5>;
132 };
133
134 watchdog1: watchdog@901C {
135 compatible = "nuvoton,npcm750-wdt";
136 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
137 reg = <0x901C 0x4>;
138 status = "disabled";
139 clocks = <&clk 5>;
140 };
141
142 watchdog2: watchdog@a01C {
143 compatible = "nuvoton,npcm750-wdt";
144 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
145 reg = <0xa01C 0x4>;
146 status = "disabled";
147 clocks = <&clk 5>;
148 };
149
150 serial0: serial@1000 {
151 compatible = "nuvoton,npcm750-uart";
152 reg = <0x1000 0x1000>;
153 clocks = <&clk 6>;
154 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
155 reg-shift = <2>;
156 status = "disabled";
157 };
158
159 serial1: serial@2000 {
160 compatible = "nuvoton,npcm750-uart";
161 reg = <0x2000 0x1000>;
162 clocks = <&clk 6>;
163 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
164 reg-shift = <2>;
165 status = "disabled";
166 };
167
168 serial2: serial@3000 {
169 compatible = "nuvoton,npcm750-uart";
170 reg = <0x3000 0x1000>;
171 clocks = <&clk 6>;
172 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
173 reg-shift = <2>;
174 status = "disabled";
175 };
176
177 serial3: serial@4000 {
178 compatible = "nuvoton,npcm750-uart";
179 reg = <0x4000 0x1000>;
180 clocks = <&clk 6>;
181 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
182 reg-shift = <2>;
183 status = "disabled";
184 };
185 };
186 };
187};
diff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
index 4416dd6c7c17..15f744f1beea 100644
--- a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
+++ b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
@@ -1,5 +1,5 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2018 Nuvoton Technology corporation. 2// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com
3// Copyright 2018 Google, Inc. 3// Copyright 2018 Google, Inc.
4 4
5/dts-v1/; 5/dts-v1/;
diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
index d53eccfe44cb..6ac340533587 100644
--- a/arch/arm/boot/dts/nuvoton-npcm750.dtsi
+++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
@@ -1,8 +1,8 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2018 Nuvoton Technology corporation. 2// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com
3// Copyright 2018 Google, Inc. 3// Copyright 2018 Google, Inc.
4 4
5#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include "nuvoton-common-npcm7xx.dtsi"
6 6
7/ { 7/ {
8 #address-cells = <1>; 8 #address-cells = <1>;
@@ -32,90 +32,7 @@
32 next-level-cache = <&l2>; 32 next-level-cache = <&l2>;
33 }; 33 };
34 }; 34 };
35
36 /* external reference clock */
37 clk-refclk: clk-refclk {
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
40 clock-frequency = <25000000>;
41 clock-output-names = "refclk";
42 };
43
44 /* external reference clock for cpu. float in normal operation */
45 clk-sysbypck: clk-sysbypck {
46 compatible = "fixed-clock";
47 #clock-cells = <0>;
48 clock-frequency = <800000000>;
49 clock-output-names = "sysbypck";
50 };
51
52 /* external reference clock for MC. float in normal operation */
53 clk-mcbypck: clk-mcbypck {
54 compatible = "fixed-clock";
55 #clock-cells = <0>;
56 clock-frequency = <800000000>;
57 clock-output-names = "mcbypck";
58 };
59
60 /* external clock signal rg1refck, supplied by the phy */
61 clk-rg1refck: clk-rg1refck {
62 compatible = "fixed-clock";
63 #clock-cells = <0>;
64 clock-frequency = <125000000>;
65 clock-output-names = "clk-rg1refck";
66 };
67
68 /* external clock signal rg2refck, supplied by the phy */
69 clk-rg2refck: clk-rg2refck {
70 compatible = "fixed-clock";
71 #clock-cells = <0>;
72 clock-frequency = <125000000>;
73 clock-output-names = "clk-rg2refck";
74 };
75
76 clk-xin: clk-xin {
77 compatible = "fixed-clock";
78 #clock-cells = <0>;
79 clock-frequency = <50000000>;
80 clock-output-names = "clk-xin";
81 };
82
83 soc { 35 soc {
84 #address-cells = <1>;
85 #size-cells = <1>;
86 compatible = "simple-bus";
87 interrupt-parent = <&gic>;
88 ranges = <0x0 0xf0000000 0x00900000>;
89
90 gcr: gcr@800000 {
91 compatible = "nuvoton,npcm750-gcr", "syscon",
92 "simple-mfd";
93 reg = <0x800000 0x1000>;
94 };
95
96 scu: scu@3fe000 {
97 compatible = "arm,cortex-a9-scu";
98 reg = <0x3fe000 0x1000>;
99 };
100
101 l2: cache-controller@3fc000 {
102 compatible = "arm,pl310-cache";
103 reg = <0x3fc000 0x1000>;
104 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
105 cache-unified;
106 cache-level = <2>;
107 clocks = <&clk 10>;
108 arm,shared-override;
109 };
110
111 gic: interrupt-controller@3ff000 {
112 compatible = "arm,cortex-a9-gic";
113 interrupt-controller;
114 #interrupt-cells = <3>;
115 reg = <0x3ff000 0x1000>,
116 <0x3fe100 0x100>;
117 };
118
119 timer@3fe600 { 36 timer@3fe600 {
120 compatible = "arm,cortex-a9-twd-timer"; 37 compatible = "arm,cortex-a9-twd-timer";
121 reg = <0x3fe600 0x20>; 38 reg = <0x3fe600 0x20>;
@@ -124,96 +41,4 @@
124 clocks = <&clk 5>; 41 clocks = <&clk 5>;
125 }; 42 };
126 }; 43 };
127
128 ahb {
129 #address-cells = <1>;
130 #size-cells = <1>;
131 compatible = "simple-bus";
132 interrupt-parent = <&gic>;
133 ranges;
134
135 clk: clock-controller@f0801000 {
136 compatible = "nuvoton,npcm750-clk", "syscon";
137 #clock-cells = <1>;
138 clock-controller;
139 reg = <0xf0801000 0x1000>;
140 clock-names = "refclk", "sysbypck", "mcbypck";
141 clocks = <&clk-refclk>, <&clk-sysbypck>, <&clk-mcbypck>;
142 };
143
144 apb {
145 #address-cells = <1>;
146 #size-cells = <1>;
147 compatible = "simple-bus";
148 interrupt-parent = <&gic>;
149 ranges = <0x0 0xf0000000 0x00300000>;
150
151 timer0: timer@8000 {
152 compatible = "nuvoton,npcm750-timer";
153 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
154 reg = <0x8000 0x50>;
155 clocks = <&clk 5>;
156 };
157
158 watchdog0: watchdog@801C {
159 compatible = "nuvoton,npcm750-wdt";
160 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
161 reg = <0x801C 0x4>;
162 status = "disabled";
163 clocks = <&clk 5>;
164 };
165
166 watchdog1: watchdog@901C {
167 compatible = "nuvoton,npcm750-wdt";
168 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
169 reg = <0x901C 0x4>;
170 status = "disabled";
171 clocks = <&clk 5>;
172 };
173
174 watchdog2: watchdog@a01C {
175 compatible = "nuvoton,npcm750-wdt";
176 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
177 reg = <0xa01C 0x4>;
178 status = "disabled";
179 clocks = <&clk 5>;
180 };
181
182 serial0: serial@1000 {
183 compatible = "nuvoton,npcm750-uart";
184 reg = <0x1000 0x1000>;
185 clocks = <&clk 6>;
186 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
187 reg-shift = <2>;
188 status = "disabled";
189 };
190
191 serial1: serial@2000 {
192 compatible = "nuvoton,npcm750-uart";
193 reg = <0x2000 0x1000>;
194 clocks = <&clk 6>;
195 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
196 reg-shift = <2>;
197 status = "disabled";
198 };
199
200 serial2: serial@3000 {
201 compatible = "nuvoton,npcm750-uart";
202 reg = <0x3000 0x1000>;
203 clocks = <&clk 6>;
204 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
205 reg-shift = <2>;
206 status = "disabled";
207 };
208
209 serial3: serial@4000 {
210 compatible = "nuvoton,npcm750-uart";
211 reg = <0x4000 0x1000>;
212 clocks = <&clk 6>;
213 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
214 reg-shift = <2>;
215 status = "disabled";
216 };
217 };
218 };
219}; 44};
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-28 10:14:20 -0400