2 files changed, 7 insertions, 0 deletions

diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h
index 6516e9da5133..b196825a1de9 100644
--- a/arch/mips/include/asm/mips-cm.h
+++ b/arch/mips/include/asm/mips-cm.h
@@ -243,6 +243,10 @@ BUILD_CM_Cx_R_(tcid_8_priority,	0x80)
 #define  CM_GCR_BASE_CMDEFTGT_IOCU0             2
 #define  CM_GCR_BASE_CMDEFTGT_IOCU1             3
 
+/* GCR_RESET_EXT_BASE register fields */
+#define CM_GCR_RESET_EXT_BASE_EVARESET          BIT(31)
+#define CM_GCR_RESET_EXT_BASE_UEB               BIT(30)
+
 /* GCR_ACCESS register fields */
 #define CM_GCR_ACCESS_ACCESSEN_SHF              0
 #define CM_GCR_ACCESS_ACCESSEN_MSK              (_ULCAST_(0xff) << 0)
diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
index e04c8057b882..2ad4e4c96d61 100644
--- a/arch/mips/kernel/smp-cps.c
+++ b/arch/mips/kernel/smp-cps.c
@@ -202,6 +202,9 @@ static void boot_core(unsigned core)
         /* Ensure its coherency is disabled */
         write_gcr_co_coherence(0);
 
+        /* Start it with the legacy memory map and exception base */
+        write_gcr_co_reset_ext_base(CM_GCR_RESET_EXT_BASE_UEB);
+
         /* Ensure the core can access the GCRs */
         access = read_gcr_access();
         access |= 1 << (CM_GCR_ACCESS_ACCESSEN_SHF + core);