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-rw-r--r--drivers/gpu/drm/exynos/exynos_mixer.c34
1 files changed, 25 insertions, 9 deletions
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
index bf148dc3623c..b5fbc1cbf024 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -516,7 +516,6 @@ static void vp_video_buffer(struct mixer_context *ctx,
516 } 516 }
517 517
518 spin_lock_irqsave(&res->reg_slock, flags); 518 spin_lock_irqsave(&res->reg_slock, flags);
519 mixer_vsync_set_update(ctx, false);
520 519
521 /* interlace or progressive scan mode */ 520 /* interlace or progressive scan mode */
522 val = (ctx->interlace ? ~0 : 0); 521 val = (ctx->interlace ? ~0 : 0);
@@ -567,7 +566,6 @@ static void vp_video_buffer(struct mixer_context *ctx,
567 mixer_cfg_vp_blend(ctx); 566 mixer_cfg_vp_blend(ctx);
568 mixer_run(ctx); 567 mixer_run(ctx);
569 568
570 mixer_vsync_set_update(ctx, true);
571 spin_unlock_irqrestore(&res->reg_slock, flags); 569 spin_unlock_irqrestore(&res->reg_slock, flags);
572 570
573 mixer_regs_dump(ctx); 571 mixer_regs_dump(ctx);
@@ -642,7 +640,6 @@ static void mixer_graph_buffer(struct mixer_context *ctx,
642 ctx->interlace = false; 640 ctx->interlace = false;
643 641
644 spin_lock_irqsave(&res->reg_slock, flags); 642 spin_lock_irqsave(&res->reg_slock, flags);
645 mixer_vsync_set_update(ctx, false);
646 643
647 /* setup format */ 644 /* setup format */
648 mixer_reg_writemask(res, MXR_GRAPHIC_CFG(win), 645 mixer_reg_writemask(res, MXR_GRAPHIC_CFG(win),
@@ -691,7 +688,6 @@ static void mixer_graph_buffer(struct mixer_context *ctx,
691 688
692 mixer_run(ctx); 689 mixer_run(ctx);
693 690
694 mixer_vsync_set_update(ctx, true);
695 spin_unlock_irqrestore(&res->reg_slock, flags); 691 spin_unlock_irqrestore(&res->reg_slock, flags);
696 692
697 mixer_regs_dump(ctx); 693 mixer_regs_dump(ctx);
@@ -718,7 +714,6 @@ static void mixer_win_reset(struct mixer_context *ctx)
718 unsigned long flags; 714 unsigned long flags;
719 715
720 spin_lock_irqsave(&res->reg_slock, flags); 716 spin_lock_irqsave(&res->reg_slock, flags);
721 mixer_vsync_set_update(ctx, false);
722 717
723 mixer_reg_writemask(res, MXR_CFG, MXR_CFG_DST_HDMI, MXR_CFG_DST_MASK); 718 mixer_reg_writemask(res, MXR_CFG, MXR_CFG_DST_HDMI, MXR_CFG_DST_MASK);
724 719
@@ -749,7 +744,6 @@ static void mixer_win_reset(struct mixer_context *ctx)
749 if (ctx->vp_enabled) 744 if (ctx->vp_enabled)
750 mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_VP_ENABLE); 745 mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_VP_ENABLE);
751 746
752 mixer_vsync_set_update(ctx, true);
753 spin_unlock_irqrestore(&res->reg_slock, flags); 747 spin_unlock_irqrestore(&res->reg_slock, flags);
754} 748}
755 749
@@ -980,6 +974,16 @@ static void mixer_disable_vblank(struct exynos_drm_crtc *crtc)
980 mixer_reg_writemask(res, MXR_INT_EN, 0, MXR_INT_EN_VSYNC); 974 mixer_reg_writemask(res, MXR_INT_EN, 0, MXR_INT_EN_VSYNC);
981} 975}
982 976
977static void mixer_atomic_begin(struct exynos_drm_crtc *crtc)
978{
979 struct mixer_context *mixer_ctx = crtc->ctx;
980
981 if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags))
982 return;
983
984 mixer_vsync_set_update(mixer_ctx, false);
985}
986
983static void mixer_update_plane(struct exynos_drm_crtc *crtc, 987static void mixer_update_plane(struct exynos_drm_crtc *crtc,
984 struct exynos_drm_plane *plane) 988 struct exynos_drm_plane *plane)
985{ 989{
@@ -1009,12 +1013,18 @@ static void mixer_disable_plane(struct exynos_drm_crtc *crtc,
1009 return; 1013 return;
1010 1014
1011 spin_lock_irqsave(&res->reg_slock, flags); 1015 spin_lock_irqsave(&res->reg_slock, flags);
1012 mixer_vsync_set_update(mixer_ctx, false);
1013
1014 mixer_cfg_layer(mixer_ctx, plane->index, 0, false); 1016 mixer_cfg_layer(mixer_ctx, plane->index, 0, false);
1017 spin_unlock_irqrestore(&res->reg_slock, flags);
1018}
1019
1020static void mixer_atomic_flush(struct exynos_drm_crtc *crtc)
1021{
1022 struct mixer_context *mixer_ctx = crtc->ctx;
1023
1024 if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags))
1025 return;
1015 1026
1016 mixer_vsync_set_update(mixer_ctx, true); 1027 mixer_vsync_set_update(mixer_ctx, true);
1017 spin_unlock_irqrestore(&res->reg_slock, flags);
1018} 1028}
1019 1029
1020static void mixer_wait_for_vblank(struct exynos_drm_crtc *crtc) 1030static void mixer_wait_for_vblank(struct exynos_drm_crtc *crtc)
@@ -1055,6 +1065,8 @@ static void mixer_enable(struct exynos_drm_crtc *crtc)
1055 1065
1056 pm_runtime_get_sync(ctx->dev); 1066 pm_runtime_get_sync(ctx->dev);
1057 1067
1068 mixer_vsync_set_update(ctx, false);
1069
1058 mixer_reg_writemask(res, MXR_STATUS, ~0, MXR_STATUS_SOFT_RESET); 1070 mixer_reg_writemask(res, MXR_STATUS, ~0, MXR_STATUS_SOFT_RESET);
1059 1071
1060 if (test_bit(MXR_BIT_VSYNC, &ctx->flags)) { 1072 if (test_bit(MXR_BIT_VSYNC, &ctx->flags)) {
@@ -1063,6 +1075,8 @@ static void mixer_enable(struct exynos_drm_crtc *crtc)
1063 } 1075 }
1064 mixer_win_reset(ctx); 1076 mixer_win_reset(ctx);
1065 1077
1078 mixer_vsync_set_update(ctx, true);
1079
1066 set_bit(MXR_BIT_POWERED, &ctx->flags); 1080 set_bit(MXR_BIT_POWERED, &ctx->flags);
1067} 1081}
1068 1082
@@ -1113,8 +1127,10 @@ static const struct exynos_drm_crtc_ops mixer_crtc_ops = {
1113 .enable_vblank = mixer_enable_vblank, 1127 .enable_vblank = mixer_enable_vblank,
1114 .disable_vblank = mixer_disable_vblank, 1128 .disable_vblank = mixer_disable_vblank,
1115 .wait_for_vblank = mixer_wait_for_vblank, 1129 .wait_for_vblank = mixer_wait_for_vblank,
1130 .atomic_begin = mixer_atomic_begin,
1116 .update_plane = mixer_update_plane, 1131 .update_plane = mixer_update_plane,
1117 .disable_plane = mixer_disable_plane, 1132 .disable_plane = mixer_disable_plane,
1133 .atomic_flush = mixer_atomic_flush,
1118 .atomic_check = mixer_atomic_check, 1134 .atomic_check = mixer_atomic_check,
1119}; 1135};
1120 1136