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-rw-r--r--sound/soc/atmel/sam9x5_wm8731.c12
-rw-r--r--sound/soc/codecs/sgtl5000.c7
-rw-r--r--sound/soc/sunxi/sun8i-codec.c82
3 files changed, 90 insertions, 11 deletions
diff --git a/sound/soc/atmel/sam9x5_wm8731.c b/sound/soc/atmel/sam9x5_wm8731.c
index ccdf547f4d8c..e6c303ab869d 100644
--- a/sound/soc/atmel/sam9x5_wm8731.c
+++ b/sound/soc/atmel/sam9x5_wm8731.c
@@ -49,13 +49,13 @@ static int sam9x5_wm8731_init(struct snd_soc_pcm_runtime *rtd)
49 struct device *dev = rtd->dev; 49 struct device *dev = rtd->dev;
50 int ret; 50 int ret;
51 51
52 dev_dbg(dev, "ASoC: %s called\n", __func__); 52 dev_dbg(dev, "%s called\n", __func__);
53 53
54 /* set the codec system clock for DAC and ADC */ 54 /* set the codec system clock for DAC and ADC */
55 ret = snd_soc_dai_set_sysclk(codec_dai, WM8731_SYSCLK_XTAL, 55 ret = snd_soc_dai_set_sysclk(codec_dai, WM8731_SYSCLK_XTAL,
56 MCLK_RATE, SND_SOC_CLOCK_IN); 56 MCLK_RATE, SND_SOC_CLOCK_IN);
57 if (ret < 0) { 57 if (ret < 0) {
58 dev_err(dev, "ASoC: Failed to set WM8731 SYSCLK: %d\n", ret); 58 dev_err(dev, "Failed to set WM8731 SYSCLK: %d\n", ret);
59 return ret; 59 return ret;
60 } 60 }
61 61
@@ -146,8 +146,7 @@ static int sam9x5_wm8731_driver_probe(struct platform_device *pdev)
146 146
147 ret = atmel_ssc_set_audio(priv->ssc_id); 147 ret = atmel_ssc_set_audio(priv->ssc_id);
148 if (ret != 0) { 148 if (ret != 0) {
149 dev_err(&pdev->dev, 149 dev_err(&pdev->dev, "Failed to set SSC %d for audio: %d\n",
150 "ASoC: Failed to set SSC %d for audio: %d\n",
151 ret, priv->ssc_id); 150 ret, priv->ssc_id);
152 goto out; 151 goto out;
153 } 152 }
@@ -157,12 +156,11 @@ static int sam9x5_wm8731_driver_probe(struct platform_device *pdev)
157 156
158 ret = snd_soc_register_card(card); 157 ret = snd_soc_register_card(card);
159 if (ret) { 158 if (ret) {
160 dev_err(&pdev->dev, 159 dev_err(&pdev->dev, "Platform device allocation failed\n");
161 "ASoC: Platform device allocation failed\n");
162 goto out_put_audio; 160 goto out_put_audio;
163 } 161 }
164 162
165 dev_dbg(&pdev->dev, "ASoC: %s ok\n", __func__); 163 dev_dbg(&pdev->dev, "%s ok\n", __func__);
166 164
167 return ret; 165 return ret;
168 166
diff --git a/sound/soc/codecs/sgtl5000.c b/sound/soc/codecs/sgtl5000.c
index f2bb4feba3b6..e1ab5537d27a 100644
--- a/sound/soc/codecs/sgtl5000.c
+++ b/sound/soc/codecs/sgtl5000.c
@@ -1332,10 +1332,13 @@ static int sgtl5000_i2c_probe(struct i2c_client *client,
1332 sgtl5000->mclk = devm_clk_get(&client->dev, NULL); 1332 sgtl5000->mclk = devm_clk_get(&client->dev, NULL);
1333 if (IS_ERR(sgtl5000->mclk)) { 1333 if (IS_ERR(sgtl5000->mclk)) {
1334 ret = PTR_ERR(sgtl5000->mclk); 1334 ret = PTR_ERR(sgtl5000->mclk);
1335 dev_err(&client->dev, "Failed to get mclock: %d\n", ret);
1336 /* Defer the probe to see if the clk will be provided later */ 1335 /* Defer the probe to see if the clk will be provided later */
1337 if (ret == -ENOENT) 1336 if (ret == -ENOENT)
1338 ret = -EPROBE_DEFER; 1337 ret = -EPROBE_DEFER;
1338
1339 if (ret != -EPROBE_DEFER)
1340 dev_err(&client->dev, "Failed to get mclock: %d\n",
1341 ret);
1339 goto disable_regs; 1342 goto disable_regs;
1340 } 1343 }
1341 1344
@@ -1389,7 +1392,7 @@ static int sgtl5000_i2c_probe(struct i2c_client *client,
1389 1392
1390 ana_pwr |= SGTL5000_LINEREG_D_POWERUP; 1393 ana_pwr |= SGTL5000_LINEREG_D_POWERUP;
1391 dev_info(&client->dev, 1394 dev_info(&client->dev,
1392 "Using internal LDO instead of VDDD: check ER1\n"); 1395 "Using internal LDO instead of VDDD: check ER1 erratum\n");
1393 } else { 1396 } else {
1394 /* using external LDO for VDDD 1397 /* using external LDO for VDDD
1395 * Clear startup powerup and simple powerup 1398 * Clear startup powerup and simple powerup
diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c
index 3dd183be08a4..7a15df924316 100644
--- a/sound/soc/sunxi/sun8i-codec.c
+++ b/sound/soc/sunxi/sun8i-codec.c
@@ -37,9 +37,11 @@
37#define SUN8I_SYSCLK_CTL_SYSCLK_SRC 0 37#define SUN8I_SYSCLK_CTL_SYSCLK_SRC 0
38#define SUN8I_MOD_CLK_ENA 0x010 38#define SUN8I_MOD_CLK_ENA 0x010
39#define SUN8I_MOD_CLK_ENA_AIF1 15 39#define SUN8I_MOD_CLK_ENA_AIF1 15
40#define SUN8I_MOD_CLK_ENA_ADC 3
40#define SUN8I_MOD_CLK_ENA_DAC 2 41#define SUN8I_MOD_CLK_ENA_DAC 2
41#define SUN8I_MOD_RST_CTL 0x014 42#define SUN8I_MOD_RST_CTL 0x014
42#define SUN8I_MOD_RST_CTL_AIF1 15 43#define SUN8I_MOD_RST_CTL_AIF1 15
44#define SUN8I_MOD_RST_CTL_ADC 3
43#define SUN8I_MOD_RST_CTL_DAC 2 45#define SUN8I_MOD_RST_CTL_DAC 2
44#define SUN8I_SYS_SR_CTRL 0x018 46#define SUN8I_SYS_SR_CTRL 0x018
45#define SUN8I_SYS_SR_CTRL_AIF1_FS 12 47#define SUN8I_SYS_SR_CTRL_AIF1_FS 12
@@ -54,9 +56,25 @@
54#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ 4 56#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ 4
55#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16 (1 << 4) 57#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16 (1 << 4)
56#define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT 2 58#define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT 2
59#define SUN8I_AIF1_ADCDAT_CTRL 0x044
60#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_DA0L_ENA 15
61#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_DA0R_ENA 14
57#define SUN8I_AIF1_DACDAT_CTRL 0x048 62#define SUN8I_AIF1_DACDAT_CTRL 0x048
58#define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA 15 63#define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA 15
59#define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA 14 64#define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA 14
65#define SUN8I_AIF1_MXR_SRC 0x04c
66#define SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF1DA0L 15
67#define SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF2DACL 14
68#define SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_ADCL 13
69#define SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF2DACR 12
70#define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF1DA0R 11
71#define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACR 10
72#define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_ADCR 9
73#define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACL 8
74#define SUN8I_ADC_DIG_CTRL 0x100
75#define SUN8I_ADC_DIG_CTRL_ENDA 15
76#define SUN8I_ADC_DIG_CTRL_ADOUT_DTS 2
77#define SUN8I_ADC_DIG_CTRL_ADOUT_DLY 1
60#define SUN8I_DAC_DIG_CTRL 0x120 78#define SUN8I_DAC_DIG_CTRL 0x120
61#define SUN8I_DAC_DIG_CTRL_ENDA 15 79#define SUN8I_DAC_DIG_CTRL_ENDA 15
62#define SUN8I_DAC_MXR_SRC 0x130 80#define SUN8I_DAC_MXR_SRC 0x130
@@ -338,10 +356,30 @@ static const struct snd_kcontrol_new sun8i_dac_mixer_controls[] = {
338 SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR, 1, 0), 356 SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR, 1, 0),
339}; 357};
340 358
359static const struct snd_kcontrol_new sun8i_input_mixer_controls[] = {
360 SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital ADC Capture Switch",
361 SUN8I_AIF1_MXR_SRC,
362 SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF1DA0L,
363 SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF1DA0R, 1, 0),
364 SOC_DAPM_DOUBLE("AIF2 Digital ADC Capture Switch", SUN8I_AIF1_MXR_SRC,
365 SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF2DACL,
366 SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACR, 1, 0),
367 SOC_DAPM_DOUBLE("AIF1 Data Digital ADC Capture Switch",
368 SUN8I_AIF1_MXR_SRC,
369 SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_ADCL,
370 SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_ADCR, 1, 0),
371 SOC_DAPM_DOUBLE("AIF2 Inv Digital ADC Capture Switch",
372 SUN8I_AIF1_MXR_SRC,
373 SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF2DACR,
374 SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACL, 1, 0),
375};
376
341static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { 377static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = {
342 /* Digital parts of the DACs */ 378 /* Digital parts of the DACs and ADC */
343 SND_SOC_DAPM_SUPPLY("DAC", SUN8I_DAC_DIG_CTRL, SUN8I_DAC_DIG_CTRL_ENDA, 379 SND_SOC_DAPM_SUPPLY("DAC", SUN8I_DAC_DIG_CTRL, SUN8I_DAC_DIG_CTRL_ENDA,
344 0, NULL, 0), 380 0, NULL, 0),
381 SND_SOC_DAPM_SUPPLY("ADC", SUN8I_ADC_DIG_CTRL, SUN8I_ADC_DIG_CTRL_ENDA,
382 0, NULL, 0),
345 383
346 /* Analog DAC AIF */ 384 /* Analog DAC AIF */
347 SND_SOC_DAPM_AIF_IN("AIF1 Slot 0 Left", "Playback", 0, 385 SND_SOC_DAPM_AIF_IN("AIF1 Slot 0 Left", "Playback", 0,
@@ -351,17 +389,31 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = {
351 SUN8I_AIF1_DACDAT_CTRL, 389 SUN8I_AIF1_DACDAT_CTRL,
352 SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA, 0), 390 SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA, 0),
353 391
354 /* DAC Mixers */ 392 /* Analog ADC AIF */
393 SND_SOC_DAPM_AIF_IN("AIF1 Slot 0 Left ADC", "Capture", 0,
394 SUN8I_AIF1_ADCDAT_CTRL,
395 SUN8I_AIF1_ADCDAT_CTRL_AIF1_DA0L_ENA, 0),
396 SND_SOC_DAPM_AIF_IN("AIF1 Slot 0 Right ADC", "Capture", 0,
397 SUN8I_AIF1_ADCDAT_CTRL,
398 SUN8I_AIF1_ADCDAT_CTRL_AIF1_DA0R_ENA, 0),
399
400 /* DAC and ADC Mixers */
355 SOC_MIXER_ARRAY("Left Digital DAC Mixer", SND_SOC_NOPM, 0, 0, 401 SOC_MIXER_ARRAY("Left Digital DAC Mixer", SND_SOC_NOPM, 0, 0,
356 sun8i_dac_mixer_controls), 402 sun8i_dac_mixer_controls),
357 SOC_MIXER_ARRAY("Right Digital DAC Mixer", SND_SOC_NOPM, 0, 0, 403 SOC_MIXER_ARRAY("Right Digital DAC Mixer", SND_SOC_NOPM, 0, 0,
358 sun8i_dac_mixer_controls), 404 sun8i_dac_mixer_controls),
405 SOC_MIXER_ARRAY("Left Digital ADC Mixer", SND_SOC_NOPM, 0, 0,
406 sun8i_input_mixer_controls),
407 SOC_MIXER_ARRAY("Right Digital ADC Mixer", SND_SOC_NOPM, 0, 0,
408 sun8i_input_mixer_controls),
359 409
360 /* Clocks */ 410 /* Clocks */
361 SND_SOC_DAPM_SUPPLY("MODCLK AFI1", SUN8I_MOD_CLK_ENA, 411 SND_SOC_DAPM_SUPPLY("MODCLK AFI1", SUN8I_MOD_CLK_ENA,
362 SUN8I_MOD_CLK_ENA_AIF1, 0, NULL, 0), 412 SUN8I_MOD_CLK_ENA_AIF1, 0, NULL, 0),
363 SND_SOC_DAPM_SUPPLY("MODCLK DAC", SUN8I_MOD_CLK_ENA, 413 SND_SOC_DAPM_SUPPLY("MODCLK DAC", SUN8I_MOD_CLK_ENA,
364 SUN8I_MOD_CLK_ENA_DAC, 0, NULL, 0), 414 SUN8I_MOD_CLK_ENA_DAC, 0, NULL, 0),
415 SND_SOC_DAPM_SUPPLY("MODCLK ADC", SUN8I_MOD_CLK_ENA,
416 SUN8I_MOD_CLK_ENA_ADC, 0, NULL, 0),
365 SND_SOC_DAPM_SUPPLY("AIF1", SUN8I_SYSCLK_CTL, 417 SND_SOC_DAPM_SUPPLY("AIF1", SUN8I_SYSCLK_CTL,
366 SUN8I_SYSCLK_CTL_AIF1CLK_ENA, 0, NULL, 0), 418 SUN8I_SYSCLK_CTL_AIF1CLK_ENA, 0, NULL, 0),
367 SND_SOC_DAPM_SUPPLY("SYSCLK", SUN8I_SYSCLK_CTL, 419 SND_SOC_DAPM_SUPPLY("SYSCLK", SUN8I_SYSCLK_CTL,
@@ -378,6 +430,12 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = {
378 SUN8I_MOD_RST_CTL_AIF1, 0, NULL, 0), 430 SUN8I_MOD_RST_CTL_AIF1, 0, NULL, 0),
379 SND_SOC_DAPM_SUPPLY("RST DAC", SUN8I_MOD_RST_CTL, 431 SND_SOC_DAPM_SUPPLY("RST DAC", SUN8I_MOD_RST_CTL,
380 SUN8I_MOD_RST_CTL_DAC, 0, NULL, 0), 432 SUN8I_MOD_RST_CTL_DAC, 0, NULL, 0),
433 SND_SOC_DAPM_SUPPLY("RST ADC", SUN8I_MOD_RST_CTL,
434 SUN8I_MOD_RST_CTL_ADC, 0, NULL, 0),
435
436 SND_SOC_DAPM_MIC("Headset Mic", NULL),
437 SND_SOC_DAPM_MIC("Mic", NULL),
438
381}; 439};
382 440
383static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = { 441static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = {
@@ -387,11 +445,16 @@ static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = {
387 { "RST AIF1", NULL, "AIF1 PLL" }, 445 { "RST AIF1", NULL, "AIF1 PLL" },
388 { "MODCLK AFI1", NULL, "RST AIF1" }, 446 { "MODCLK AFI1", NULL, "RST AIF1" },
389 { "DAC", NULL, "MODCLK AFI1" }, 447 { "DAC", NULL, "MODCLK AFI1" },
448 { "ADC", NULL, "MODCLK AFI1" },
390 449
391 { "RST DAC", NULL, "SYSCLK" }, 450 { "RST DAC", NULL, "SYSCLK" },
392 { "MODCLK DAC", NULL, "RST DAC" }, 451 { "MODCLK DAC", NULL, "RST DAC" },
393 { "DAC", NULL, "MODCLK DAC" }, 452 { "DAC", NULL, "MODCLK DAC" },
394 453
454 { "RST ADC", NULL, "SYSCLK" },
455 { "MODCLK ADC", NULL, "RST ADC" },
456 { "ADC", NULL, "MODCLK ADC" },
457
395 /* DAC Routes */ 458 /* DAC Routes */
396 { "AIF1 Slot 0 Right", NULL, "DAC" }, 459 { "AIF1 Slot 0 Right", NULL, "DAC" },
397 { "AIF1 Slot 0 Left", NULL, "DAC" }, 460 { "AIF1 Slot 0 Left", NULL, "DAC" },
@@ -401,6 +464,12 @@ static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = {
401 "AIF1 Slot 0 Left"}, 464 "AIF1 Slot 0 Left"},
402 { "Right Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Playback Switch", 465 { "Right Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Playback Switch",
403 "AIF1 Slot 0 Right"}, 466 "AIF1 Slot 0 Right"},
467
468 /* ADC routes */
469 { "Left Digital ADC Mixer", "AIF1 Data Digital ADC Capture Switch",
470 "AIF1 Slot 0 Left ADC" },
471 { "Right Digital ADC Mixer", "AIF1 Data Digital ADC Capture Switch",
472 "AIF1 Slot 0 Right ADC" },
404}; 473};
405 474
406static const struct snd_soc_dai_ops sun8i_codec_dai_ops = { 475static const struct snd_soc_dai_ops sun8i_codec_dai_ops = {
@@ -418,6 +487,15 @@ static struct snd_soc_dai_driver sun8i_codec_dai = {
418 .rates = SNDRV_PCM_RATE_8000_192000, 487 .rates = SNDRV_PCM_RATE_8000_192000,
419 .formats = SNDRV_PCM_FMTBIT_S16_LE, 488 .formats = SNDRV_PCM_FMTBIT_S16_LE,
420 }, 489 },
490 /* capture capabilities */
491 .capture = {
492 .stream_name = "Capture",
493 .channels_min = 1,
494 .channels_max = 2,
495 .rates = SNDRV_PCM_RATE_8000_192000,
496 .formats = SNDRV_PCM_FMTBIT_S16_LE,
497 .sig_bits = 24,
498 },
421 /* pcm operations */ 499 /* pcm operations */
422 .ops = &sun8i_codec_dai_ops, 500 .ops = &sun8i_codec_dai_ops,
423}; 501};