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-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/dport.c10
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/disp/dport.h6
2 files changed, 16 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dport.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dport.c
index 74e2f7c6c07e..9688970eca47 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dport.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dport.c
@@ -328,6 +328,7 @@ nvkm_dp_train(struct work_struct *w)
328 .outp = outp, 328 .outp = outp,
329 }, *dp = &_dp; 329 }, *dp = &_dp;
330 u32 datarate = 0; 330 u32 datarate = 0;
331 u8 pwr;
331 int ret; 332 int ret;
332 333
333 if (!outp->base.info.location && disp->func->sor.magic) 334 if (!outp->base.info.location && disp->func->sor.magic)
@@ -355,6 +356,15 @@ nvkm_dp_train(struct work_struct *w)
355 /* disable link interrupt handling during link training */ 356 /* disable link interrupt handling during link training */
356 nvkm_notify_put(&outp->irq); 357 nvkm_notify_put(&outp->irq);
357 358
359 /* ensure sink is not in a low-power state */
360 if (!nvkm_rdaux(outp->aux, DPCD_SC00, &pwr, 1)) {
361 if ((pwr & DPCD_SC00_SET_POWER) != DPCD_SC00_SET_POWER_D0) {
362 pwr &= ~DPCD_SC00_SET_POWER;
363 pwr |= DPCD_SC00_SET_POWER_D0;
364 nvkm_wraux(outp->aux, DPCD_SC00, &pwr, 1);
365 }
366 }
367
358 /* enable down-spreading and execute pre-train script from vbios */ 368 /* enable down-spreading and execute pre-train script from vbios */
359 dp_link_train_init(dp, outp->dpcd[3] & 0x01); 369 dp_link_train_init(dp, outp->dpcd[3] & 0x01);
360 370
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dport.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dport.h
index 9596290329c7..6e10c5e0ef11 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dport.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dport.h
@@ -71,5 +71,11 @@
71#define DPCD_LS0C_LANE1_POST_CURSOR2 0x0c 71#define DPCD_LS0C_LANE1_POST_CURSOR2 0x0c
72#define DPCD_LS0C_LANE0_POST_CURSOR2 0x03 72#define DPCD_LS0C_LANE0_POST_CURSOR2 0x03
73 73
74/* DPCD Sink Control */
75#define DPCD_SC00 0x00600
76#define DPCD_SC00_SET_POWER 0x03
77#define DPCD_SC00_SET_POWER_D0 0x01
78#define DPCD_SC00_SET_POWER_D3 0x03
79
74void nvkm_dp_train(struct work_struct *); 80void nvkm_dp_train(struct work_struct *);
75#endif 81#endif