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-rw-r--r--Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt38
-rw-r--r--arch/arm/boot/dts/meson8.dtsi57
-rw-r--r--arch/arm/boot/dts/meson8b.dtsi12
-rw-r--r--arch/arm/configs/u8500_defconfig3
-rw-r--r--arch/arm/mach-uniphier/platsmp.c2
-rw-r--r--arch/arm64/boot/dts/broadcom/vulcan.dtsi15
-rw-r--r--drivers/bus/uniphier-system-bus.c2
7 files changed, 63 insertions, 66 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
index 3f6a524cc5ff..32f4a2d6d0b3 100644
--- a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
@@ -1,13 +1,16 @@
1== Amlogic Meson pinmux controller == 1== Amlogic Meson pinmux controller ==
2 2
3Required properties for the root node: 3Required properties for the root node:
4 - compatible: "amlogic,meson8-pinctrl" or "amlogic,meson8b-pinctrl" 4 - compatible: one of "amlogic,meson8-cbus-pinctrl"
5 "amlogic,meson8b-cbus-pinctrl"
6 "amlogic,meson8-aobus-pinctrl"
7 "amlogic,meson8b-aobus-pinctrl"
5 - reg: address and size of registers controlling irq functionality 8 - reg: address and size of registers controlling irq functionality
6 9
7=== GPIO sub-nodes === 10=== GPIO sub-nodes ===
8 11
9The 2 power domains of the controller (regular and always-on) are 12The GPIO bank for the controller is represented as a sub-node and it acts as a
10represented as sub-nodes and each of them acts as a GPIO controller. 13GPIO controller.
11 14
12Required properties for sub-nodes are: 15Required properties for sub-nodes are:
13 - reg: should contain address and size for mux, pull-enable, pull and 16 - reg: should contain address and size for mux, pull-enable, pull and
@@ -18,10 +21,6 @@ Required properties for sub-nodes are:
18 - gpio-controller: identifies the node as a gpio controller 21 - gpio-controller: identifies the node as a gpio controller
19 - #gpio-cells: must be 2 22 - #gpio-cells: must be 2
20 23
21Valid sub-node names are:
22 - "banks" for the regular domain
23 - "ao-bank" for the always-on domain
24
25=== Other sub-nodes === 24=== Other sub-nodes ===
26 25
27Child nodes without the "gpio-controller" represent some desired 26Child nodes without the "gpio-controller" represent some desired
@@ -45,7 +44,7 @@ pinctrl-bindings.txt
45=== Example === 44=== Example ===
46 45
47 pinctrl: pinctrl@c1109880 { 46 pinctrl: pinctrl@c1109880 {
48 compatible = "amlogic,meson8-pinctrl"; 47 compatible = "amlogic,meson8-cbus-pinctrl";
49 reg = <0xc1109880 0x10>; 48 reg = <0xc1109880 0x10>;
50 #address-cells = <1>; 49 #address-cells = <1>;
51 #size-cells = <1>; 50 #size-cells = <1>;
@@ -61,15 +60,6 @@ pinctrl-bindings.txt
61 #gpio-cells = <2>; 60 #gpio-cells = <2>;
62 }; 61 };
63 62
64 gpio_ao: ao-bank@c1108030 {
65 reg = <0xc8100014 0x4>,
66 <0xc810002c 0x4>,
67 <0xc8100024 0x8>;
68 reg-names = "mux", "pull", "gpio";
69 gpio-controller;
70 #gpio-cells = <2>;
71 };
72
73 nand { 63 nand {
74 mux { 64 mux {
75 groups = "nand_io", "nand_io_ce0", "nand_io_ce1", 65 groups = "nand_io", "nand_io_ce0", "nand_io_ce1",
@@ -79,18 +69,4 @@ pinctrl-bindings.txt
79 function = "nand"; 69 function = "nand";
80 }; 70 };
81 }; 71 };
82
83 uart_ao_a {
84 mux {
85 groups = "uart_tx_ao_a", "uart_rx_ao_a",
86 "uart_cts_ao_a", "uart_rts_ao_a";
87 function = "uart_ao";
88 };
89
90 conf {
91 pins = "GPIOAO_0", "GPIOAO_1",
92 "GPIOAO_2", "GPIOAO_3";
93 bias-disable;
94 };
95 };
96 }; 72 };
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index a2ddcb8c545a..45619f6162c5 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -91,8 +91,8 @@
91 clock-frequency = <141666666>; 91 clock-frequency = <141666666>;
92 }; 92 };
93 93
94 pinctrl: pinctrl@c1109880 { 94 pinctrl_cbus: pinctrl@c1109880 {
95 compatible = "amlogic,meson8-pinctrl"; 95 compatible = "amlogic,meson8-cbus-pinctrl";
96 reg = <0xc1109880 0x10>; 96 reg = <0xc1109880 0x10>;
97 #address-cells = <1>; 97 #address-cells = <1>;
98 #size-cells = <1>; 98 #size-cells = <1>;
@@ -108,29 +108,6 @@
108 #gpio-cells = <2>; 108 #gpio-cells = <2>;
109 }; 109 };
110 110
111 gpio_ao: ao-bank@c1108030 {
112 reg = <0xc8100014 0x4>,
113 <0xc810002c 0x4>,
114 <0xc8100024 0x8>;
115 reg-names = "mux", "pull", "gpio";
116 gpio-controller;
117 #gpio-cells = <2>;
118 };
119
120 uart_ao_a_pins: uart_ao_a {
121 mux {
122 groups = "uart_tx_ao_a", "uart_rx_ao_a";
123 function = "uart_ao";
124 };
125 };
126
127 i2c_ao_pins: i2c_mst_ao {
128 mux {
129 groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao";
130 function = "i2c_mst_ao";
131 };
132 };
133
134 spi_nor_pins: nor { 111 spi_nor_pins: nor {
135 mux { 112 mux {
136 groups = "nor_d", "nor_q", "nor_c", "nor_cs"; 113 groups = "nor_d", "nor_q", "nor_c", "nor_cs";
@@ -157,4 +134,34 @@
157 }; 134 };
158 }; 135 };
159 136
137 pinctrl_aobus: pinctrl@c8100084 {
138 compatible = "amlogic,meson8-aobus-pinctrl";
139 reg = <0xc8100084 0xc>;
140 #address-cells = <1>;
141 #size-cells = <1>;
142 ranges;
143
144 gpio_ao: ao-bank@c1108030 {
145 reg = <0xc8100014 0x4>,
146 <0xc810002c 0x4>,
147 <0xc8100024 0x8>;
148 reg-names = "mux", "pull", "gpio";
149 gpio-controller;
150 #gpio-cells = <2>;
151 };
152
153 uart_ao_a_pins: uart_ao_a {
154 mux {
155 groups = "uart_tx_ao_a", "uart_rx_ao_a";
156 function = "uart_ao";
157 };
158 };
159
160 i2c_ao_pins: i2c_mst_ao {
161 mux {
162 groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao";
163 function = "i2c_mst_ao";
164 };
165 };
166 };
160}; /* end of / */ 167}; /* end of / */
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 8bad5571af46..2bfe401a4da9 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -155,8 +155,8 @@
155 reg = <0xc1108000 0x4>, <0xc1104000 0x460>; 155 reg = <0xc1108000 0x4>, <0xc1104000 0x460>;
156 }; 156 };
157 157
158 pinctrl: pinctrl@c1109880 { 158 pinctrl_cbus: pinctrl@c1109880 {
159 compatible = "amlogic,meson8b-pinctrl"; 159 compatible = "amlogic,meson8b-cbus-pinctrl";
160 reg = <0xc1109880 0x10>; 160 reg = <0xc1109880 0x10>;
161 #address-cells = <1>; 161 #address-cells = <1>;
162 #size-cells = <1>; 162 #size-cells = <1>;
@@ -171,6 +171,14 @@
171 gpio-controller; 171 gpio-controller;
172 #gpio-cells = <2>; 172 #gpio-cells = <2>;
173 }; 173 };
174 };
175
176 pinctrl_aobus: pinctrl@c8100084 {
177 compatible = "amlogic,meson8b-aobus-pinctrl";
178 reg = <0xc8100084 0xc>;
179 #address-cells = <1>;
180 #size-cells = <1>;
181 ranges;
174 182
175 gpio_ao: ao-bank@c1108030 { 183 gpio_ao: ao-bank@c1108030 {
176 reg = <0xc8100014 0x4>, 184 reg = <0xc8100014 0x4>,
diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig
index 07055eacbb0f..a691d590fbd1 100644
--- a/arch/arm/configs/u8500_defconfig
+++ b/arch/arm/configs/u8500_defconfig
@@ -63,6 +63,9 @@ CONFIG_INPUT_TOUCHSCREEN=y
63CONFIG_TOUCHSCREEN_BU21013=y 63CONFIG_TOUCHSCREEN_BU21013=y
64CONFIG_INPUT_MISC=y 64CONFIG_INPUT_MISC=y
65CONFIG_INPUT_AB8500_PONKEY=y 65CONFIG_INPUT_AB8500_PONKEY=y
66CONFIG_RMI4_CORE=y
67CONFIG_RMI4_I2C=y
68CONFIG_RMI4_F11=y
66# CONFIG_SERIO is not set 69# CONFIG_SERIO is not set
67CONFIG_VT_HW_CONSOLE_BINDING=y 70CONFIG_VT_HW_CONSOLE_BINDING=y
68# CONFIG_LEGACY_PTYS is not set 71# CONFIG_LEGACY_PTYS is not set
diff --git a/arch/arm/mach-uniphier/platsmp.c b/arch/arm/mach-uniphier/platsmp.c
index 69141357afe8..db04142f88bc 100644
--- a/arch/arm/mach-uniphier/platsmp.c
+++ b/arch/arm/mach-uniphier/platsmp.c
@@ -120,7 +120,7 @@ static int __init uniphier_smp_prepare_trampoline(unsigned int max_cpus)
120 if (ret) 120 if (ret)
121 return ret; 121 return ret;
122 122
123 uniphier_smp_rom_boot_rsv2 = ioremap(rom_rsv2_phys, sizeof(SZ_4)); 123 uniphier_smp_rom_boot_rsv2 = ioremap(rom_rsv2_phys, SZ_4);
124 if (!uniphier_smp_rom_boot_rsv2) { 124 if (!uniphier_smp_rom_boot_rsv2) {
125 pr_err("failed to map ROM_BOOT_RSV2 register\n"); 125 pr_err("failed to map ROM_BOOT_RSV2 register\n");
126 return -ENOMEM; 126 return -ENOMEM;
diff --git a/arch/arm64/boot/dts/broadcom/vulcan.dtsi b/arch/arm64/boot/dts/broadcom/vulcan.dtsi
index c49b5a85809c..85820e2bca9d 100644
--- a/arch/arm64/boot/dts/broadcom/vulcan.dtsi
+++ b/arch/arm64/boot/dts/broadcom/vulcan.dtsi
@@ -108,12 +108,15 @@
108 reg = <0x0 0x30000000 0x0 0x10000000>; 108 reg = <0x0 0x30000000 0x0 0x10000000>;
109 reg-names = "PCI ECAM"; 109 reg-names = "PCI ECAM";
110 110
111 /* IO 0x4000_0000 - 0x4001_0000 */ 111 /*
112 ranges = <0x01000000 0 0x40000000 0 0x40000000 0 0x00010000 112 * PCI ranges:
113 /* MEM 0x4800_0000 - 0x5000_0000 */ 113 * IO no supported
114 0x02000000 0 0x48000000 0 0x48000000 0 0x08000000 114 * MEM 0x4000_0000 - 0x6000_0000
115 /* MEM64 pref 0x6_0000_0000 - 0x7_0000_0000 */ 115 * MEM64 pref 0x40_0000_0000 - 0x60_0000_0000
116 0x43000000 6 0x00000000 6 0x00000000 1 0x00000000>; 116 */
117 ranges =
118 <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000
119 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>;
117 interrupt-map-mask = <0 0 0 7>; 120 interrupt-map-mask = <0 0 0 7>;
118 interrupt-map = 121 interrupt-map =
119 /* addr pin ic icaddr icintr */ 122 /* addr pin ic icaddr icintr */
diff --git a/drivers/bus/uniphier-system-bus.c b/drivers/bus/uniphier-system-bus.c
index 834a2aeaf27a..350b7309c26d 100644
--- a/drivers/bus/uniphier-system-bus.c
+++ b/drivers/bus/uniphier-system-bus.c
@@ -108,7 +108,7 @@ static int uniphier_system_bus_check_overlap(
108 108
109 for (i = 0; i < ARRAY_SIZE(priv->bank); i++) { 109 for (i = 0; i < ARRAY_SIZE(priv->bank); i++) {
110 for (j = i + 1; j < ARRAY_SIZE(priv->bank); j++) { 110 for (j = i + 1; j < ARRAY_SIZE(priv->bank); j++) {
111 if (priv->bank[i].end > priv->bank[j].base || 111 if (priv->bank[i].end > priv->bank[j].base &&
112 priv->bank[i].base < priv->bank[j].end) { 112 priv->bank[i].base < priv->bank[j].end) {
113 dev_err(priv->dev, 113 dev_err(priv->dev,
114 "region overlap between bank%d and bank%d\n", 114 "region overlap between bank%d and bank%d\n",
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-24 17:00:44 -0400