diff options
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 15 |
1 files changed, 6 insertions, 9 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c index aadc3e66ebd7..f3f5938430d4 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | |||
| @@ -382,6 +382,7 @@ static int vce_v4_0_start(struct amdgpu_device *adev) | |||
| 382 | static int vce_v4_0_stop(struct amdgpu_device *adev) | 382 | static int vce_v4_0_stop(struct amdgpu_device *adev) |
| 383 | { | 383 | { |
| 384 | 384 | ||
| 385 | /* Disable VCPU */ | ||
| 385 | WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL), 0, ~0x200001); | 386 | WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL), 0, ~0x200001); |
| 386 | 387 | ||
| 387 | /* hold on ECPU */ | 388 | /* hold on ECPU */ |
| @@ -389,8 +390,8 @@ static int vce_v4_0_stop(struct amdgpu_device *adev) | |||
| 389 | VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK, | 390 | VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK, |
| 390 | ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); | 391 | ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); |
| 391 | 392 | ||
| 392 | /* clear BUSY flag */ | 393 | /* clear VCE_STATUS */ |
| 393 | WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), 0, ~VCE_STATUS__JOB_BUSY_MASK); | 394 | WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), 0); |
| 394 | 395 | ||
| 395 | /* Set Clock-Gating off */ | 396 | /* Set Clock-Gating off */ |
| 396 | /* if (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG) | 397 | /* if (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG) |
| @@ -922,6 +923,7 @@ static int vce_v4_0_set_clockgating_state(void *handle, | |||
| 922 | 923 | ||
| 923 | return 0; | 924 | return 0; |
| 924 | } | 925 | } |
| 926 | #endif | ||
| 925 | 927 | ||
| 926 | static int vce_v4_0_set_powergating_state(void *handle, | 928 | static int vce_v4_0_set_powergating_state(void *handle, |
| 927 | enum amd_powergating_state state) | 929 | enum amd_powergating_state state) |
| @@ -935,16 +937,11 @@ static int vce_v4_0_set_powergating_state(void *handle, | |||
| 935 | */ | 937 | */ |
| 936 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | 938 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 937 | 939 | ||
| 938 | if (!(adev->pg_flags & AMD_PG_SUPPORT_VCE)) | ||
| 939 | return 0; | ||
| 940 | |||
| 941 | if (state == AMD_PG_STATE_GATE) | 940 | if (state == AMD_PG_STATE_GATE) |
| 942 | /* XXX do we need a vce_v4_0_stop()? */ | 941 | return vce_v4_0_stop(adev); |
| 943 | return 0; | ||
| 944 | else | 942 | else |
| 945 | return vce_v4_0_start(adev); | 943 | return vce_v4_0_start(adev); |
| 946 | } | 944 | } |
| 947 | #endif | ||
| 948 | 945 | ||
| 949 | static void vce_v4_0_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job, | 946 | static void vce_v4_0_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job, |
| 950 | struct amdgpu_ib *ib, uint32_t flags) | 947 | struct amdgpu_ib *ib, uint32_t flags) |
| @@ -1059,7 +1056,7 @@ const struct amd_ip_funcs vce_v4_0_ip_funcs = { | |||
| 1059 | .soft_reset = NULL /* vce_v4_0_soft_reset */, | 1056 | .soft_reset = NULL /* vce_v4_0_soft_reset */, |
| 1060 | .post_soft_reset = NULL /* vce_v4_0_post_soft_reset */, | 1057 | .post_soft_reset = NULL /* vce_v4_0_post_soft_reset */, |
| 1061 | .set_clockgating_state = vce_v4_0_set_clockgating_state, | 1058 | .set_clockgating_state = vce_v4_0_set_clockgating_state, |
| 1062 | .set_powergating_state = NULL /* vce_v4_0_set_powergating_state */, | 1059 | .set_powergating_state = vce_v4_0_set_powergating_state, |
| 1063 | }; | 1060 | }; |
| 1064 | 1061 | ||
| 1065 | static const struct amdgpu_ring_funcs vce_v4_0_ring_vm_funcs = { | 1062 | static const struct amdgpu_ring_funcs vce_v4_0_ring_vm_funcs = { |
