3 files changed, 87 insertions, 21 deletions

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 56002a52936d..243224aeabf8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3509,6 +3509,8 @@ extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
 
 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
+int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
+                      u32 reply_mask, u32 reply, int timeout_base_ms);
 
 /* intel_sideband.c */
 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4ef5a39acc69..7d234043822d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6244,35 +6244,24 @@ skl_dpll0_disable(struct drm_i915_private *dev_priv)
         dev_priv->cdclk_pll.vco = 0;
 }
 
-static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
-{
-        int ret;
-        u32 val;
-
-        /* inform PCU we want to change CDCLK */
-        val = SKL_CDCLK_PREPARE_FOR_CHANGE;
-        mutex_lock(&dev_priv->rps.hw_lock);
-        ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
-        mutex_unlock(&dev_priv->rps.hw_lock);
-
-        return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
-}
-
-static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
-{
-        return _wait_for(skl_cdclk_pcu_ready(dev_priv), 3000, 10) == 0;
-}
-
 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
 {
         u32 freq_select, pcu_ack;
+        int ret;
 
         WARN_ON((cdclk == 24000) != (vco == 0));
 
         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
 
-        if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
-                DRM_ERROR("failed to inform PCU about cdclk change\n");
+        mutex_lock(&dev_priv->rps.hw_lock);
+        ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
+                                SKL_CDCLK_PREPARE_FOR_CHANGE,
+                                SKL_CDCLK_READY_FOR_CHANGE,
+                                SKL_CDCLK_READY_FOR_CHANGE, 3);
+        mutex_unlock(&dev_priv->rps.hw_lock);
+        if (ret) {
+                DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
+                          ret);
                 return;
         }
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index cbd0f3269b2d..90e42e094b13 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7890,6 +7890,81 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
         return 0;
 }
 
+static bool skl_pcode_try_request(struct drm_i915_private *dev_priv, u32 mbox,
+                                  u32 request, u32 reply_mask, u32 reply,
+                                  u32 *status)
+{
+        u32 val = request;
+
+        *status = sandybridge_pcode_read(dev_priv, mbox, &val);
+
+        return *status || ((val & reply_mask) == reply);
+}
+
+/**
+ * skl_pcode_request - send PCODE request until acknowledgment
+ * @dev_priv: device private
+ * @mbox: PCODE mailbox ID the request is targeted for
+ * @request: request ID
+ * @reply_mask: mask used to check for request acknowledgment
+ * @reply: value used to check for request acknowledgment
+ * @timeout_base_ms: timeout for polling with preemption enabled
+ *
+ * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE
+ * reports an error or an overall timeout of @timeout_base_ms+10 ms expires.
+ * The request is acknowledged once the PCODE reply dword equals @reply after
+ * applying @reply_mask. Polling is first attempted with preemption enabled
+ * for @timeout_base_ms and if this times out for another 10 ms with
+ * preemption disabled.
+ *
+ * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
+ * other error as reported by PCODE.
+ */
+int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
+                      u32 reply_mask, u32 reply, int timeout_base_ms)
+{
+        u32 status;
+        int ret;
+
+        WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+
+#define COND skl_pcode_try_request(dev_priv, mbox, request, reply_mask, reply, \
+                                   &status)
+
+        /*
+         * Prime the PCODE by doing a request first. Normally it guarantees
+         * that a subsequent request, at most @timeout_base_ms later, succeeds.
+         * _wait_for() doesn't guarantee when its passed condition is evaluated
+         * first, so send the first request explicitly.
+         */
+        if (COND) {
+                ret = 0;
+                goto out;
+        }
+        ret = _wait_for(COND, timeout_base_ms * 1000, 10);
+        if (!ret)
+                goto out;
+
+        /*
+         * The above can time out if the number of requests was low (2 in the
+         * worst case) _and_ PCODE was busy for some reason even after a
+         * (queued) request and @timeout_base_ms delay. As a workaround retry
+         * the poll with preemption disabled to maximize the number of
+         * requests. Increase the timeout from @timeout_base_ms to 10ms to
+         * account for interrupts that could reduce the number of these
+         * requests.
+         */
+        DRM_DEBUG_KMS("PCODE timeout, retrying with preemption disabled\n");
+        WARN_ON_ONCE(timeout_base_ms > 3);
+        preempt_disable();
+        ret = wait_for_atomic(COND, 10);
+        preempt_enable();
+
+out:
+        return ret ? ret : status;
+#undef COND
+}
+
 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
 {
         /*