108 files changed, 3528 insertions, 1097 deletions
diff --git a/Documentation/devicetree/bindings/display/etnaviv/etnaviv-drm.txt b/Documentation/devicetree/bindings/display/etnaviv/etnaviv-drm.txt
index 05176f1ae108..8def11b16a24 100644
--- a/Documentation/devicetree/bindings/display/etnaviv/etnaviv-drm.txt
+++ b/Documentation/devicetree/bindings/display/etnaviv/etnaviv-drm.txt
@@ -1,23 +1,3 @@
-Etnaviv DRM master device
-=========================
-The Etnaviv DRM master device is a virtual device needed to list all
-Vivante GPU cores that comprise the GPU subsystem.
-Required properties:
- compatible: Should be one of
-    "fsl,imx-gpu-subsystem"
-    "marvell,dove-gpu-subsystem"
- cores: Should contain a list of phandles pointing to Vivante GPU devices
-example:
-gpu-subsystem {
-        compatible = "fsl,imx-gpu-subsystem";
-        cores = <&gpu_2d>, <&gpu_3d>;
-};
 Vivante GPU core devices
 ========================
@@ -32,7 +12,9 @@ Required properties:
 - clocks: should contain one clock for entry in clock-names
  see Documentation/devicetree/bindings/clock/clock-bindings.txt
 - clock-names:
-   - "bus":    AXI/register clock
+   - "bus":    AXI/master interface clock
+   - "reg":    AHB/slave interface clock
+               (only required if GPU can gate slave interface independently)
   - "core":   GPU core clock
   - "shader": Shader clock (only required if GPU has feature PIPE_3D)
diff --git a/Documentation/devicetree/bindings/display/panel/auo,g104sn02.txt b/Documentation/devicetree/bindings/display/panel/auo,g104sn02.txt
new file mode 100644
index 000000000000..85626edf63e5
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/auo,g104sn02.txt
@@ -0,0 +1,12 @@
+AU Optronics Corporation 10.4" (800x600) color TFT LCD panel
+Required properties:
+- compatible: should be "auo,g104sn02"
+- power-supply: as specified in the base binding
+Optional properties:
+- backlight: as specified in the base binding
+- enable-gpios: as specified in the base binding
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/Documentation/devicetree/bindings/display/panel/display-timing.txt b/Documentation/devicetree/bindings/display/panel/display-timing.txt
index 58fa3e48481d..78222ced1874 100644
--- a/Documentation/devicetree/bindings/display/panel/display-timing.txt
+++ b/Documentation/devicetree/bindings/display/panel/display-timing.txt
@@ -80,6 +80,11 @@ The parameters are defined as:
  |          |        v                            |          |       |
  +----------+-------------------------------------+----------+-------+
+Note: In addition to being used as subnode(s) of display-timings, the timing
+      subnode may also be used on its own. This is appropriate if only one mode
+      need be conveyed. In this case, the node should be named 'panel-timing'.
 Example:
        display-timings {
diff --git a/Documentation/devicetree/bindings/display/panel/koe,tx31d200vm0baa.txt b/Documentation/devicetree/bindings/display/panel/koe,tx31d200vm0baa.txt
new file mode 100644
index 000000000000..6a036ede3e28
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/koe,tx31d200vm0baa.txt
@@ -0,0 +1,25 @@
+Kaohsiung Opto-Electronics. TX31D200VM0BAA 12.3" HSXGA LVDS panel
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
+Required properties:
+- compatible: should be "koe,tx31d200vm0baa"
+Optional properties:
+- backlight: phandle of the backlight device attached to the panel
+Optional nodes:
+- Video port for LVDS panel input.
+Example:
+        panel {
+                compatible = "koe,tx31d200vm0baa";
+                backlight = <&backlight_lvds>;
+                port {
+                        panel_in: endpoint {
+                                remote-endpoint = <&lvds0_out>;
+                        };
+                };
+        };
diff --git a/Documentation/devicetree/bindings/display/panel/orisetech,otm8009a.txt b/Documentation/devicetree/bindings/display/panel/orisetech,otm8009a.txt
index 6862028e7b2e..203b03eefb68 100644
--- a/Documentation/devicetree/bindings/display/panel/orisetech,otm8009a.txt
+++ b/Documentation/devicetree/bindings/display/panel/orisetech,otm8009a.txt
@@ -9,6 +9,7 @@ Required properties:
 Optional properties:
  - reset-gpios: a GPIO spec for the reset pin (active low).
+  - power-supply: phandle of the regulator that provides the supply voltage.
 Example:
 &dsi {
@@ -17,5 +18,6 @@ Example:
                compatible = "orisetech,otm8009a";
                reg = <0>;
                reset-gpios = <&gpioh 7 GPIO_ACTIVE_LOW>;
+                power-supply = <&v1v8>;
        };
 };
diff --git a/Documentation/devicetree/bindings/display/panel/raydium,rm68200.txt b/Documentation/devicetree/bindings/display/panel/raydium,rm68200.txt
new file mode 100644
index 000000000000..cbb79ef3bfc9
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/raydium,rm68200.txt
@@ -0,0 +1,25 @@
+Raydium Semiconductor Corporation RM68200 5.5" 720p MIPI-DSI TFT LCD panel
+The Raydium Semiconductor Corporation RM68200 is a 5.5" 720x1280 TFT LCD
+panel connected using a MIPI-DSI video interface.
+Required properties:
+  - compatible: "raydium,rm68200"
+  - reg: the virtual channel number of a DSI peripheral
+Optional properties:
+  - reset-gpios: a GPIO spec for the reset pin (active low).
+  - power-supply: phandle of the regulator that provides the supply voltage.
+  - backlight: phandle of the backlight device attached to the panel.
+Example:
+&dsi {
+        ...
+        panel@0 {
+                compatible = "raydium,rm68200";
+                reg = <0>;
+                reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
+                power-supply = <&v1v8>;
+                backlight = <&pwm_backlight>;
+        };
+};
diff --git a/Documentation/devicetree/bindings/display/panel/simple-panel.txt b/Documentation/devicetree/bindings/display/panel/simple-panel.txt
index 16d8ff088b7d..45a457ad38f0 100644
--- a/Documentation/devicetree/bindings/display/panel/simple-panel.txt
+++ b/Documentation/devicetree/bindings/display/panel/simple-panel.txt
@@ -1,4 +1,8 @@
 Simple display panel
+====================
+panel node
+----------
 Required properties:
 - power-supply: See panel-common.txt
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index 8bdef4920edc..3346c1e2a7a0 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -146,13 +146,16 @@ Required properties:
   * allwinner,sun8i-a83t-tcon-lcd
   * allwinner,sun8i-a83t-tcon-tv
   * allwinner,sun8i-v3s-tcon
+   * allwinner,sun9i-a80-tcon-lcd
+   * allwinner,sun9i-a80-tcon-tv
 - reg: base address and size of memory-mapped region
 - interrupts: interrupt associated to this IP
 - clocks: phandles to the clocks feeding the TCON.
   - 'ahb': the interface clocks
-   - 'tcon-ch0': The clock driving the TCON channel 0, except for A83T TV TCON
+   - 'tcon-ch0': The clock driving the TCON channel 0, if supported
 - resets: phandles to the reset controllers driving the encoder
-   - "lcd": the reset line for the TCON channel 0
+   - "lcd": the reset line for the TCON
+   - "edp": the reset line for the eDP block (A80 only)
 - clock-names: the clock names mentioned above
 - reset-names: the reset names mentioned above
@@ -171,7 +174,9 @@ Required properties:
  channel the endpoint is associated to. If that property is not
  present, the endpoint number will be used as the channel number.
-On SoCs other than the A33 and V3s, there is one more clock required:
+For TCONs with channel 0, there is one more clock required:
+   - 'tcon-ch0': The clock driving the TCON channel 0
+For TCONs with channel 1, there is one more clock required:
   - 'tcon-ch1': The clock driving the TCON channel 1
 When TCON support LVDS (all TCONs except TV TCON on A83T and those found
@@ -186,7 +191,7 @@ DRC
 ---
 The DRC (Dynamic Range Controller), found in the latest Allwinner SoCs
-(A31, A23, A33), allows to dynamically adjust pixel
+(A31, A23, A33, A80), allows to dynamically adjust pixel
 brightness/contrast based on histogram measurements for LCD content
 adaptive backlight control.
@@ -196,6 +201,7 @@ Required properties:
    * allwinner,sun6i-a31-drc
    * allwinner,sun6i-a31s-drc
    * allwinner,sun8i-a33-drc
+    * allwinner,sun9i-a80-drc
  - reg: base address and size of the memory-mapped region.
  - interrupts: interrupt associated to this IP
  - clocks: phandles to the clocks feeding the DRC
@@ -222,6 +228,7 @@ Required properties:
    * allwinner,sun6i-a31-display-backend
    * allwinner,sun7i-a20-display-backend
    * allwinner,sun8i-a33-display-backend
+    * allwinner,sun9i-a80-display-backend
  - reg: base address and size of the memory-mapped region.
  - interrupts: interrupt associated to this IP
  - clocks: phandles to the clocks feeding the frontend and backend
@@ -243,6 +250,28 @@ On the A33, some additional properties are required:
  - resets and reset-names need to have a phandle to the SAT bus
    resets, whose name will be "sat"
+DEU
+---
+The DEU (Detail Enhancement Unit), found in the Allwinner A80 SoC,
+can sharpen the display content in both luma and chroma channels.
+Required properties:
+  - compatible: value must be one of:
+    * allwinner,sun9i-a80-deu
+  - reg: base address and size of the memory-mapped region.
+  - interrupts: interrupt associated to this IP
+  - clocks: phandles to the clocks feeding the DEU
+    * ahb: the DEU interface clock
+    * mod: the DEU module clock
+    * ram: the DEU DRAM clock
+  - clock-names: the clock names mentioned above
+  - resets: phandles to the reset line driving the DEU
+- ports: A ports node with endpoint definitions as defined in
+  Documentation/devicetree/bindings/media/video-interfaces.txt. The
+  first port should be the input endpoints, the second one the outputs
 Display Engine Frontend
 -----------------------
@@ -256,6 +285,7 @@ Required properties:
    * allwinner,sun6i-a31-display-frontend
    * allwinner,sun7i-a20-display-frontend
    * allwinner,sun8i-a33-display-frontend
+    * allwinner,sun9i-a80-display-frontend
  - reg: base address and size of the memory-mapped region.
  - interrupts: interrupt associated to this IP
  - clocks: phandles to the clocks feeding the frontend and backend
@@ -312,6 +342,7 @@ Required properties:
    * allwinner,sun8i-a83t-display-engine
    * allwinner,sun8i-h3-display-engine
    * allwinner,sun8i-v3s-display-engine
+    * allwinner,sun9i-a80-display-engine
  - allwinner,pipelines: list of phandle to the display engine
    frontends (DE 1.0) or mixers (DE 2.0) available.
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index ae850d6c0ad3..12e8b3e576b0 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -104,6 +104,7 @@ eeti	eGalax_eMPIA Technology Inc
 elan    Elan Microelectronic Corp.
 embest  Shenzhen Embest Technology Co., Ltd.
 emmicro EM Microelectronic
+emtrion emtrion GmbH
 energymicro     Silicon Laboratories (formerly Energy Micro AS)
 engicam Engicam S.r.l.
 epcos   EPCOS AG
diff --git a/Documentation/gpu/drivers.rst b/Documentation/gpu/drivers.rst
new file mode 100644
index 000000000000..e8c84419a2a1
--- /dev/null
+++ b/Documentation/gpu/drivers.rst
@@ -0,0 +1,21 @@
+========================
+GPU Driver Documentation
+========================
+.. toctree::
+   i915
+   meson
+   pl111
+   tegra
+   tinydrm
+   tve200
+   vc4
+   bridge/dw-hdmi
+.. only::  subproject and html
+   Indices
+   =======
+   * :ref:`genindex`
diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst
index 56a3780e39b8..1dffd1ac4cd4 100644
--- a/Documentation/gpu/drm-kms.rst
+++ b/Documentation/gpu/drm-kms.rst
@@ -286,6 +286,9 @@ Atomic Mode Setting Function Reference
 .. kernel-doc:: drivers/gpu/drm/drm_atomic.c
   :export:
+.. kernel-doc:: drivers/gpu/drm/drm_atomic.c
+   :internal:
 CRTC Abstraction
 ================
diff --git a/Documentation/gpu/index.rst b/Documentation/gpu/index.rst
index c36586dad29d..00288f34c5a6 100644
--- a/Documentation/gpu/index.rst
+++ b/Documentation/gpu/index.rst
@@ -10,16 +10,9 @@ Linux GPU Driver Developer's Guide
   drm-kms
   drm-kms-helpers
   drm-uapi
-   i915
+   drivers
-   meson
-   pl111
-   tegra
-   tinydrm
-   tve200
-   vc4
   vga-switcheroo
   vgaarbiter
-   bridge/dw-hdmi
   todo
 .. only::  subproject and html
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index e6709362994a..2337d4bfd85c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -738,7 +738,6 @@ static int amdgpu_pmops_runtime_suspend(struct device *dev)
        drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
        drm_kms_helper_poll_disable(drm_dev);
-        vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
        ret = amdgpu_device_suspend(drm_dev, false, false);
        pci_save_state(pdev);
@@ -775,7 +774,6 @@ static int amdgpu_pmops_runtime_resume(struct device *dev)
        ret = amdgpu_device_resume(drm_dev, false, false);
        drm_kms_helper_poll_enable(drm_dev);
-        vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
        drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
        return 0;
 }
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index a693ab3078f0..5c52307146c7 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -15,6 +15,7 @@
 #include <linux/err.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/iopoll.h>
 #include <linux/interrupt.h>
 #include <linux/of.h>
 #include <linux/of_gpio.h>
@@ -35,6 +36,8 @@
 #define to_dp(nm)       container_of(nm, struct analogix_dp_device, nm)
+static const bool verify_fast_training;
 struct bridge_init {
        struct i2c_client *client;
        struct device_node *node;
@@ -98,18 +101,18 @@ static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
        return 0;
 }
-int analogix_dp_psr_supported(struct analogix_dp_device *dp)
+int analogix_dp_psr_enabled(struct analogix_dp_device *dp)
 {
-        return dp->psr_support;
+        return dp->psr_enable;
 }
-EXPORT_SYMBOL_GPL(analogix_dp_psr_supported);
+EXPORT_SYMBOL_GPL(analogix_dp_psr_enabled);
 int analogix_dp_enable_psr(struct analogix_dp_device *dp)
 {
        struct edp_vsc_psr psr_vsc;
-        if (!dp->psr_support)
+        if (!dp->psr_enable)
                return 0;
        /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */
@@ -122,8 +125,7 @@ int analogix_dp_enable_psr(struct analogix_dp_device *dp)
        psr_vsc.DB0 = 0;
        psr_vsc.DB1 = EDP_VSC_PSR_STATE_ACTIVE | EDP_VSC_PSR_CRC_VALUES_VALID;
-        analogix_dp_send_psr_spd(dp, &psr_vsc);
+        return analogix_dp_send_psr_spd(dp, &psr_vsc, true);
-        return 0;
 }
 EXPORT_SYMBOL_GPL(analogix_dp_enable_psr);
@@ -132,7 +134,7 @@ int analogix_dp_disable_psr(struct analogix_dp_device *dp)
        struct edp_vsc_psr psr_vsc;
        int ret;
-        if (!dp->psr_support)
+        if (!dp->psr_enable)
                return 0;
        /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */
@@ -149,8 +151,7 @@ int analogix_dp_disable_psr(struct analogix_dp_device *dp)
        if (ret != 1)
                dev_err(dp->dev, "Failed to set DP Power0 %d\n", ret);
-        analogix_dp_send_psr_spd(dp, &psr_vsc);
+        return analogix_dp_send_psr_spd(dp, &psr_vsc, false);
-        return 0;
 }
 EXPORT_SYMBOL_GPL(analogix_dp_disable_psr);
@@ -530,7 +531,7 @@ static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
 {
        int lane, lane_count, retval;
        u32 reg;
-        u8 link_align, link_status[2], adjust_request[2];
+        u8 link_align, link_status[2], adjust_request[2], spread;
        usleep_range(400, 401);
@@ -573,6 +574,20 @@ static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
                dev_dbg(dp->dev, "final lane count = %.2x\n",
                        dp->link_train.lane_count);
+                retval = drm_dp_dpcd_readb(&dp->aux, DP_MAX_DOWNSPREAD,
+                                           &spread);
+                if (retval != 1) {
+                        dev_err(dp->dev, "failed to read downspread %d\n",
+                                retval);
+                        dp->fast_train_support = false;
+                } else {
+                        dp->fast_train_support =
+                                (spread & DP_NO_AUX_HANDSHAKE_LINK_TRAINING) ?
+                                        true : false;
+                }
+                dev_dbg(dp->dev, "fast link training %s\n",
+                        dp->fast_train_support ? "supported" : "unsupported");
                /* set enhanced mode if available */
                analogix_dp_set_enhanced_mode(dp);
                dp->link_train.lt_state = FINISHED;
@@ -629,10 +644,12 @@ static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
        *lane_count = DPCD_MAX_LANE_COUNT(data);
 }
-static void analogix_dp_init_training(struct analogix_dp_device *dp,
+static int analogix_dp_full_link_train(struct analogix_dp_device *dp,
-                                      enum link_lane_count_type max_lane,
+                                       u32 max_lanes, u32 max_rate)
-                                      int max_rate)
 {
+        int retval = 0;
+        bool training_finished = false;
        /*
         * MACRO_RST must be applied after the PLL_LOCK to avoid
         * the DP inter pair skew issue for at least 10 us
@@ -658,18 +675,13 @@ static void analogix_dp_init_training(struct analogix_dp_device *dp,
        }
        /* Setup TX lane count & rate */
-        if (dp->link_train.lane_count > max_lane)
+        if (dp->link_train.lane_count > max_lanes)
-                dp->link_train.lane_count = max_lane;
+                dp->link_train.lane_count = max_lanes;
        if (dp->link_train.link_rate > max_rate)
                dp->link_train.link_rate = max_rate;
        /* All DP analog module power up */
        analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
-}
-static int analogix_dp_sw_link_training(struct analogix_dp_device *dp)
-{
-        int retval = 0, training_finished = 0;
        dp->link_train.lt_state = START;
@@ -704,22 +716,88 @@ static int analogix_dp_sw_link_training(struct analogix_dp_device *dp)
        return retval;
 }
-static int analogix_dp_set_link_train(struct analogix_dp_device *dp,
+static int analogix_dp_fast_link_train(struct analogix_dp_device *dp)
-                                      u32 count, u32 bwtype)
 {
-        int i;
+        int i, ret;
-        int retval;
+        u8 link_align, link_status[2];
+        enum pll_status status;
-        for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) {
+        analogix_dp_reset_macro(dp);
-                analogix_dp_init_training(dp, count, bwtype);
-                retval = analogix_dp_sw_link_training(dp);
+        analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
-                if (retval == 0)
+        analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
-                        break;
-                usleep_range(100, 110);
+        for (i = 0; i < dp->link_train.lane_count; i++) {
+                analogix_dp_set_lane_link_training(dp,
+                        dp->link_train.training_lane[i], i);
        }
-        return retval;
+        ret = readx_poll_timeout(analogix_dp_get_pll_lock_status, dp, status,
+                                 status != PLL_UNLOCKED, 120,
+                                 120 * DP_TIMEOUT_LOOP_COUNT);
+        if (ret) {
+                DRM_DEV_ERROR(dp->dev, "Wait for pll lock failed %d\n", ret);
+                return ret;
+        }
+        /* source Set training pattern 1 */
+        analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
+        /* From DP spec, pattern must be on-screen for a minimum 500us */
+        usleep_range(500, 600);
+        analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
+        /* From DP spec, pattern must be on-screen for a minimum 500us */
+        usleep_range(500, 600);
+        /* TODO: enhanced_mode?*/
+        analogix_dp_set_training_pattern(dp, DP_NONE);
+        /*
+         * Useful for debugging issues with fast link training, disable for more
+         * speed
+         */
+        if (verify_fast_training) {
+                ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED,
+                                        &link_align);
+                if (ret < 0) {
+                        DRM_DEV_ERROR(dp->dev, "Read align status failed %d\n",
+                                      ret);
+                        return ret;
+                }
+                ret = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status,
+                                       2);
+                if (ret < 0) {
+                        DRM_DEV_ERROR(dp->dev, "Read link status failed %d\n",
+                                      ret);
+                        return ret;
+                }
+                if (analogix_dp_clock_recovery_ok(link_status,
+                                                  dp->link_train.lane_count)) {
+                        DRM_DEV_ERROR(dp->dev, "Clock recovery failed\n");
+                        analogix_dp_reduce_link_rate(dp);
+                        return -EIO;
+                }
+                if (analogix_dp_channel_eq_ok(link_status, link_align,
+                                              dp->link_train.lane_count)) {
+                        DRM_DEV_ERROR(dp->dev, "Channel EQ failed\n");
+                        analogix_dp_reduce_link_rate(dp);
+                        return -EIO;
+                }
+        }
+        return 0;
+}
+static int analogix_dp_train_link(struct analogix_dp_device *dp)
+{
+        if (dp->fast_train_support)
+                return analogix_dp_fast_link_train(dp);
+        return analogix_dp_full_link_train(dp, dp->video_info.max_lane_count,
+                                           dp->video_info.max_link_rate);
 }
 static int analogix_dp_config_video(struct analogix_dp_device *dp)
@@ -848,10 +926,10 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
                        DRM_ERROR("failed to disable the panel\n");
        }
-        ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count,
+        ret = readx_poll_timeout(analogix_dp_train_link, dp, ret, !ret, 100,
-                                         dp->video_info.max_link_rate);
+                                 DP_TIMEOUT_TRAINING_US * 5);
        if (ret) {
-                dev_err(dp->dev, "unable to do link train\n");
+                dev_err(dp->dev, "unable to do link train, ret=%d\n", ret);
                return;
        }
@@ -873,8 +951,8 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
        /* Enable video */
        analogix_dp_start_video(dp);
-        dp->psr_support = analogix_dp_detect_sink_psr(dp);
+        dp->psr_enable = analogix_dp_detect_sink_psr(dp);
-        if (dp->psr_support)
+        if (dp->psr_enable)
                analogix_dp_enable_sink_psr(dp);
 }
@@ -1119,6 +1197,7 @@ static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
        if (ret)
                DRM_ERROR("failed to setup the panel ret = %d\n", ret);
+        dp->psr_enable = false;
        dp->dpms_mode = DRM_MODE_DPMS_OFF;
 }
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 5c6a28806129..6a96ef7e6934 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -20,6 +20,10 @@
 #define MAX_CR_LOOP 5
 #define MAX_EQ_LOOP 5
+/* Training takes 22ms if AUX channel comm fails. Use this as retry interval */
+#define DP_TIMEOUT_TRAINING_US                  22000
+#define DP_TIMEOUT_PSR_LOOP_MS                  300
 /* DP_MAX_LANE_COUNT */
 #define DPCD_ENHANCED_FRAME_CAP(x)              (((x) >> 7) & 0x1)
 #define DPCD_MAX_LANE_COUNT(x)                  ((x) & 0x1f)
@@ -168,7 +172,8 @@ struct analogix_dp_device {
        int                     dpms_mode;
        int                     hpd_gpio;
        bool                    force_hpd;
-        bool                    psr_support;
+        bool                    psr_enable;
+        bool                    fast_train_support;
        struct mutex            panel_lock;
        bool                    panel_is_modeset;
@@ -247,8 +252,8 @@ void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp);
 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp);
 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp);
 void analogix_dp_enable_psr_crc(struct analogix_dp_device *dp);
-void analogix_dp_send_psr_spd(struct analogix_dp_device *dp,
+int analogix_dp_send_psr_spd(struct analogix_dp_device *dp,
-                              struct edp_vsc_psr *vsc);
+                             struct edp_vsc_psr *vsc, bool blocking);
 ssize_t analogix_dp_transfer(struct analogix_dp_device *dp,
                             struct drm_dp_aux_msg *msg);
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index 303083ad28e3..9df2f3ef000c 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -10,10 +10,11 @@
 * option) any later version.
 */
-#include <linux/device.h>
-#include <linux/io.h>
 #include <linux/delay.h>
+#include <linux/device.h>
 #include <linux/gpio.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
 #include <drm/bridge/analogix_dp.h>
@@ -992,10 +993,25 @@ void analogix_dp_enable_psr_crc(struct analogix_dp_device *dp)
        writel(PSR_VID_CRC_ENABLE, dp->reg_base + ANALOGIX_DP_CRC_CON);
 }
-void analogix_dp_send_psr_spd(struct analogix_dp_device *dp,
+static ssize_t analogix_dp_get_psr_status(struct analogix_dp_device *dp)
-                              struct edp_vsc_psr *vsc)
+{
+        ssize_t val;
+        u8 status;
+        val = drm_dp_dpcd_readb(&dp->aux, DP_PSR_STATUS, &status);
+        if (val < 0) {
+                dev_err(dp->dev, "PSR_STATUS read failed ret=%zd", val);
+                return val;
+        }
+        return status;
+}
+int analogix_dp_send_psr_spd(struct analogix_dp_device *dp,
+                             struct edp_vsc_psr *vsc, bool blocking)
 {
        unsigned int val;
+        int ret;
+        ssize_t psr_status;
        /* don't send info frame */
        val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
@@ -1036,6 +1052,20 @@ void analogix_dp_send_psr_spd(struct analogix_dp_device *dp,
        val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
        val |= IF_EN;
        writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
+        if (!blocking)
+                return 0;
+        ret = readx_poll_timeout(analogix_dp_get_psr_status, dp, psr_status,
+                psr_status >= 0 &&
+                ((vsc->DB1 && psr_status == DP_PSR_SINK_ACTIVE_RFB) ||
+                (!vsc->DB1 && psr_status == DP_PSR_SINK_INACTIVE)), 1500,
+                DP_TIMEOUT_PSR_LOOP_MS * 1000);
+        if (ret) {
+                dev_warn(dp->dev, "Failed to apply PSR %d\n", ret);
+                return ret;
+        }
+        return 0;
 }
 ssize_t analogix_dp_transfer(struct analogix_dp_device *dp,
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index 53ebbe2904b6..ec8d0006ef7c 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -147,7 +147,6 @@ struct dw_hdmi {
        int vic;
        u8 edid[HDMI_EDID_LEN];
-        bool cable_plugin;
        struct {
                const struct dw_hdmi_phy_ops *ops;
@@ -1679,12 +1678,6 @@ static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
                hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
 }
-static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
-{
-        hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
-        hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
-}
 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
 {
        hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
@@ -1774,8 +1767,6 @@ static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
        hdmi_tx_hdcp_config(hdmi);
        dw_hdmi_clear_overflow(hdmi);
-        if (hdmi->cable_plugin && hdmi->sink_is_hdmi)
-                hdmi_enable_overflow_interrupts(hdmi);
        return 0;
 }
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 34b7d420e555..7d25c42f22db 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -391,8 +391,7 @@ int drm_atomic_set_mode_prop_for_crtc(struct drm_crtc_state *state,
        if (blob) {
                if (blob->length != sizeof(struct drm_mode_modeinfo) ||
                    drm_mode_convert_umode(state->crtc->dev, &state->mode,
-                                           (const struct drm_mode_modeinfo *)
+                                           blob->data))
-                                            blob->data))
                        return -EINVAL;
                state->mode_blob = drm_property_blob_get(blob);
@@ -409,11 +408,36 @@ int drm_atomic_set_mode_prop_for_crtc(struct drm_crtc_state *state,
 }
 EXPORT_SYMBOL(drm_atomic_set_mode_prop_for_crtc);
+/**
+ * drm_atomic_replace_property_blob_from_id - lookup the new blob and replace the old one with it
+ * @dev: DRM device
+ * @blob: a pointer to the member blob to be replaced
+ * @blob_id: ID of the new blob
+ * @expected_size: total expected size of the blob data (in bytes)
+ * @expected_elem_size: expected element size of the blob data (in bytes)
+ * @replaced: did the blob get replaced?
+ *
+ * Replace @blob with another blob with the ID @blob_id. If @blob_id is zero
+ * @blob becomes NULL.
+ *
+ * If @expected_size is positive the new blob length is expected to be equal
+ * to @expected_size bytes. If @expected_elem_size is positive the new blob
+ * length is expected to be a multiple of @expected_elem_size bytes. Otherwise
+ * an error is returned.
+ *
+ * @replaced will indicate to the caller whether the blob was replaced or not.
+ * If the old and new blobs were in fact the same blob @replaced will be false
+ * otherwise it will be true.
+ *
+ * RETURNS:
+ * Zero on success, error code on failure.
+ */
 static int
 drm_atomic_replace_property_blob_from_id(struct drm_device *dev,
                                         struct drm_property_blob **blob,
                                         uint64_t blob_id,
                                         ssize_t expected_size,
+                                         ssize_t expected_elem_size,
                                         bool *replaced)
 {
        struct drm_property_blob *new_blob = NULL;
@@ -423,7 +447,13 @@ drm_atomic_replace_property_blob_from_id(struct drm_device *dev,
                if (new_blob == NULL)
                        return -EINVAL;
-                if (expected_size > 0 && expected_size != new_blob->length) {
+                if (expected_size > 0 &&
+                    new_blob->length != expected_size) {
+                        drm_property_blob_put(new_blob);
+                        return -EINVAL;
+                }
+                if (expected_elem_size > 0 &&
+                    new_blob->length % expected_elem_size != 0) {
                        drm_property_blob_put(new_blob);
                        return -EINVAL;
                }
@@ -471,7 +501,7 @@ int drm_atomic_crtc_set_property(struct drm_crtc *crtc,
                ret = drm_atomic_replace_property_blob_from_id(dev,
                                        &state->degamma_lut,
                                        val,
-                                        -1,
+                                        -1, sizeof(struct drm_color_lut),
                                        &replaced);
                state->color_mgmt_changed |= replaced;
                return ret;
@@ -479,7 +509,7 @@ int drm_atomic_crtc_set_property(struct drm_crtc *crtc,
                ret = drm_atomic_replace_property_blob_from_id(dev,
                                        &state->ctm,
                                        val,
-                                        sizeof(struct drm_color_ctm),
+                                        sizeof(struct drm_color_ctm), -1,
                                        &replaced);
                state->color_mgmt_changed |= replaced;
                return ret;
@@ -487,7 +517,7 @@ int drm_atomic_crtc_set_property(struct drm_crtc *crtc,
                ret = drm_atomic_replace_property_blob_from_id(dev,
                                        &state->gamma_lut,
                                        val,
-                                        -1,
+                                        -1, sizeof(struct drm_color_lut),
                                        &replaced);
                state->color_mgmt_changed |= replaced;
                return ret;
diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c
index 00c78c1c9681..c35654591c12 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -3818,7 +3818,7 @@ int drm_atomic_helper_legacy_gamma_set(struct drm_crtc *crtc,
        }
        /* Prepare GAMMA_LUT with the legacy values. */
-        blob_data = (struct drm_color_lut *) blob->data;
+        blob_data = blob->data;
        for (i = 0; i < size; i++) {
                blob_data[i].red = red[i];
                blob_data[i].green = green[i];
diff --git a/drivers/gpu/drm/drm_bufs.c b/drivers/gpu/drm/drm_bufs.c
index 1ee84dd802d4..ba8cfe65c65b 100644
--- a/drivers/gpu/drm/drm_bufs.c
+++ b/drivers/gpu/drm/drm_bufs.c
@@ -129,10 +129,10 @@ static int drm_map_handle(struct drm_device *dev, struct drm_hash_item *hash,
 * type.  Adds the map to the map list drm_device::maplist. Adds MTRR's where
 * applicable and if supported by the kernel.
 */
-static int drm_addmap_core(struct drm_device * dev, resource_size_t offset,
+static int drm_addmap_core(struct drm_device *dev, resource_size_t offset,
                           unsigned int size, enum drm_map_type type,
                           enum drm_map_flags flags,
-                           struct drm_map_list ** maplist)
+                           struct drm_map_list **maplist)
 {
        struct drm_local_map *map;
        struct drm_map_list *list;
@@ -224,7 +224,7 @@ static int drm_addmap_core(struct drm_device * dev, resource_size_t offset,
        case _DRM_SHM:
                list = drm_find_matching_map(dev, map);
                if (list != NULL) {
-                        if(list->map->size != map->size) {
+                        if (list->map->size != map->size) {
                                DRM_DEBUG("Matching maps of type %d with "
                                          "mismatched sizes, (%ld vs %ld)\n",
                                          map->type, map->size, list->map->size);
@@ -361,7 +361,7 @@ static int drm_addmap_core(struct drm_device * dev, resource_size_t offset,
        return 0;
 }
-int drm_legacy_addmap(struct drm_device * dev, resource_size_t offset,
+int drm_legacy_addmap(struct drm_device *dev, resource_size_t offset,
                      unsigned int size, enum drm_map_type type,
                      enum drm_map_flags flags, struct drm_local_map **map_ptr)
 {
@@ -637,8 +637,8 @@ int drm_legacy_rmmap_ioctl(struct drm_device *dev, void *data,
 *
 * Frees any pages and buffers associated with the given entry.
 */
-static void drm_cleanup_buf_error(struct drm_device * dev,
+static void drm_cleanup_buf_error(struct drm_device *dev,
-                                  struct drm_buf_entry * entry)
+                                  struct drm_buf_entry *entry)
 {
        int i;
@@ -1446,8 +1446,8 @@ int drm_legacy_freebufs(struct drm_device *dev, void *data,
 int __drm_legacy_mapbufs(struct drm_device *dev, void *data, int *p,
                         void __user **v,
                         int (*f)(void *, int, unsigned long,
-                                  struct drm_buf *),
+                                 struct drm_buf *),
-                         struct drm_file *file_priv)
+                                 struct drm_file *file_priv)
 {
        struct drm_device_dma *dma = dev->dma;
        int retcode = 0;
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index a797bbf1cab8..49147b2aa288 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1554,8 +1554,7 @@ struct edid *drm_do_get_edid(struct drm_connector *connector,
        struct edid *override = NULL;
        if (connector->override_edid)
-                override = drm_edid_duplicate((const struct edid *)
+                override = drm_edid_duplicate(connector->edid_blob_ptr->data);
-                                              connector->edid_blob_ptr->data);
        if (!override)
                override = drm_load_edid_firmware(connector);
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 035784ddd133..0646b108030b 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -1351,7 +1351,7 @@ static struct drm_property_blob *setcmap_new_gamma_lut(struct drm_crtc *crtc,
        if (IS_ERR(gamma_lut))
                return gamma_lut;
-        lut = (struct drm_color_lut *)gamma_lut->data;
+        lut = gamma_lut->data;
        if (cmap->start || cmap->len != size) {
                u16 *r = crtc->gamma_store;
                u16 *g = r + crtc->gamma_size;
diff --git a/drivers/gpu/drm/drm_framebuffer.c b/drivers/gpu/drm/drm_framebuffer.c
index 5a13ff29f4f0..0eebe8ba8a2c 100644
--- a/drivers/gpu/drm/drm_framebuffer.c
+++ b/drivers/gpu/drm/drm_framebuffer.c
@@ -158,9 +158,10 @@ static int framebuffer_check(struct drm_device *dev,
        info = __drm_format_info(r->pixel_format & ~DRM_FORMAT_BIG_ENDIAN);
        if (!info) {
                struct drm_format_name_buf format_name;
                DRM_DEBUG_KMS("bad framebuffer format %s\n",
-                              drm_get_format_name(r->pixel_format,
+                              drm_get_format_name(r->pixel_format,
-                                                  &format_name));
+                                                  &format_name));
                return -EINVAL;
        }
diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index 5a8033fda4e3..f6b7c0e36a1a 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -773,24 +773,23 @@ EXPORT_SYMBOL(drm_mode_hsync);
 int drm_mode_vrefresh(const struct drm_display_mode *mode)
 {
        int refresh = 0;
-        unsigned int calc_val;
        if (mode->vrefresh > 0)
                refresh = mode->vrefresh;
        else if (mode->htotal > 0 && mode->vtotal > 0) {
-                int vtotal;
+                unsigned int num, den;
-                vtotal = mode->vtotal;
-                /* work out vrefresh the value will be x1000 */
+                num = mode->clock * 1000;
-                calc_val = (mode->clock * 1000);
+                den = mode->htotal * mode->vtotal;
-                calc_val /= mode->htotal;
-                refresh = (calc_val + vtotal / 2) / vtotal;
                if (mode->flags & DRM_MODE_FLAG_INTERLACE)
-                        refresh *= 2;
+                        num *= 2;
                if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
-                        refresh /= 2;
+                        den *= 2;
                if (mode->vscan > 1)
-                        refresh /= mode->vscan;
+                        den *= mode->vscan;
+                refresh = DIV_ROUND_CLOSEST(num, den);
        }
        return refresh;
 }
@@ -1596,12 +1595,8 @@ int drm_mode_convert_umode(struct drm_device *dev,
                           struct drm_display_mode *out,
                           const struct drm_mode_modeinfo *in)
 {
-        int ret = -EINVAL;
+        if (in->clock > INT_MAX || in->vrefresh > INT_MAX)
+                return -ERANGE;
-        if (in->clock > INT_MAX || in->vrefresh > INT_MAX) {
-                ret = -ERANGE;
-                goto out;
-        }
        out->clock = in->clock;
        out->hdisplay = in->hdisplay;
@@ -1622,14 +1617,11 @@ int drm_mode_convert_umode(struct drm_device *dev,
        out->status = drm_mode_validate_driver(dev, out);
        if (out->status != MODE_OK)
-                goto out;
+                return -EINVAL;
        drm_mode_set_crtcinfo(out, CRTC_INTERLACE_HALVE_V);
-        ret = 0;
+        return 0;
-out:
-        return ret;
 }
 /**
diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c
index a5d1fc7e8a37..6d2a6e428a3e 100644
--- a/drivers/gpu/drm/drm_plane.c
+++ b/drivers/gpu/drm/drm_plane.c
@@ -104,7 +104,7 @@ static int create_in_format_blob(struct drm_device *dev, struct drm_plane *plane
        if (IS_ERR(blob))
                return -1;
-        blob_data = (struct drm_format_modifier_blob *)blob->data;
+        blob_data = blob->data;
        blob_data->version = FORMAT_BLOB_CURRENT;
        blob_data->count_formats = plane->format_count;
        blob_data->formats_offset = sizeof(struct drm_format_modifier_blob);
diff --git a/drivers/gpu/drm/drm_print.c b/drivers/gpu/drm/drm_print.c
index 781518fd88e3..b25f98f33f6c 100644
--- a/drivers/gpu/drm/drm_print.c
+++ b/drivers/gpu/drm/drm_print.c
@@ -63,16 +63,34 @@ void drm_printf(struct drm_printer *p, const char *f, ...)
 }
 EXPORT_SYMBOL(drm_printf);
-#define DRM_PRINTK_FMT "[" DRM_NAME ":%s]%s %pV"
 void drm_dev_printk(const struct device *dev, const char *level,
-                    unsigned int category, const char *function_name,
+                    const char *format, ...)
-                    const char *prefix, const char *format, ...)
 {
        struct va_format vaf;
        va_list args;
-        if (category != DRM_UT_NONE && !(drm_debug & category))
+        va_start(args, format);
+        vaf.fmt = format;
+        vaf.va = &args;
+        if (dev)
+                dev_printk(level, dev, "[" DRM_NAME ":%ps] %pV",
+                           __builtin_return_address(0), &vaf);
+        else
+                printk("%s" "[" DRM_NAME ":%ps] %pV",
+                       level, __builtin_return_address(0), &vaf);
+        va_end(args);
+}
+EXPORT_SYMBOL(drm_dev_printk);
+void drm_dev_dbg(const struct device *dev, unsigned int category,
+                 const char *format, ...)
+{
+        struct va_format vaf;
+        va_list args;
+        if (!(drm_debug & category))
                return;
        va_start(args, format);
@@ -80,32 +98,47 @@ void drm_dev_printk(const struct device *dev, const char *level,
        vaf.va = &args;
        if (dev)
-                dev_printk(level, dev, DRM_PRINTK_FMT, function_name, prefix,
+                dev_printk(KERN_DEBUG, dev, "[" DRM_NAME ":%ps] %pV",
-                           &vaf);
+                           __builtin_return_address(0), &vaf);
        else
-                printk("%s" DRM_PRINTK_FMT, level, function_name, prefix, &vaf);
+                printk(KERN_DEBUG "[" DRM_NAME ":%ps] %pV",
+                       __builtin_return_address(0), &vaf);
        va_end(args);
 }
-EXPORT_SYMBOL(drm_dev_printk);
+EXPORT_SYMBOL(drm_dev_dbg);
-void drm_printk(const char *level, unsigned int category,
+void drm_dbg(unsigned int category, const char *format, ...)
-                const char *format, ...)
 {
        struct va_format vaf;
        va_list args;
-        if (category != DRM_UT_NONE && !(drm_debug & category))
+        if (!(drm_debug & category))
                return;
        va_start(args, format);
        vaf.fmt = format;
        vaf.va = &args;
-        printk("%s" "[" DRM_NAME ":%ps]%s %pV",
+        printk(KERN_DEBUG "[" DRM_NAME ":%ps] %pV",
-               level, __builtin_return_address(0),
+               __builtin_return_address(0), &vaf);
-               strcmp(level, KERN_ERR) == 0 ? " *ERROR*" : "", &vaf);
+        va_end(args);
+}
+EXPORT_SYMBOL(drm_dbg);
+void drm_err(const char *format, ...)
+{
+        struct va_format vaf;
+        va_list args;
+        va_start(args, format);
+        vaf.fmt = format;
+        vaf.va = &args;
+        printk(KERN_ERR "[" DRM_NAME ":%ps] *ERROR* %pV",
+               __builtin_return_address(0), &vaf);
        va_end(args);
 }
-EXPORT_SYMBOL(drm_printk);
+EXPORT_SYMBOL(drm_err);
diff --git a/drivers/gpu/drm/drm_property.c b/drivers/gpu/drm/drm_property.c
index 6ac6ee41a6a3..8f4672daac7f 100644
--- a/drivers/gpu/drm/drm_property.c
+++ b/drivers/gpu/drm/drm_property.c
@@ -567,6 +567,7 @@ drm_property_create_blob(struct drm_device *dev, size_t length,
        /* This must be explicitly initialised, so we can safely call list_del
         * on it in the removal handler, even if it isn't in a file list. */
        INIT_LIST_HEAD(&blob->head_file);
+        blob->data = (void *)blob + sizeof(*blob);
        blob->length = length;
        blob->dev = dev;
diff --git a/drivers/gpu/drm/etnaviv/Kconfig b/drivers/gpu/drm/etnaviv/Kconfig
index 3f58b4077767..e5bfeca361bd 100644
--- a/drivers/gpu/drm/etnaviv/Kconfig
+++ b/drivers/gpu/drm/etnaviv/Kconfig
@@ -11,6 +11,7 @@ config DRM_ETNAVIV
        select WANT_DEV_COREDUMP
        select CMA if HAVE_DMA_CONTIGUOUS
        select DMA_CMA if HAVE_DMA_CONTIGUOUS
+        select DRM_SCHED
        help
          DRM driver for Vivante GPUs.
diff --git a/drivers/gpu/drm/etnaviv/Makefile b/drivers/gpu/drm/etnaviv/Makefile
index 1281c8d4fae5..46e5ffad69a6 100644
--- a/drivers/gpu/drm/etnaviv/Makefile
+++ b/drivers/gpu/drm/etnaviv/Makefile
@@ -9,9 +9,11 @@ etnaviv-y := \
        etnaviv_gem_submit.o \
        etnaviv_gem.o \
        etnaviv_gpu.o \
+        etnaviv_hwdb.o \
        etnaviv_iommu_v2.o \
        etnaviv_iommu.o \
        etnaviv_mmu.o \
-        etnaviv_perfmon.o
+        etnaviv_perfmon.o \
+        etnaviv_sched.o
 obj-$(CONFIG_DRM_ETNAVIV)       += etnaviv.o
diff --git a/drivers/gpu/drm/etnaviv/common.xml.h b/drivers/gpu/drm/etnaviv/common.xml.h
index 207f45c999c3..001faea80fef 100644
--- a/drivers/gpu/drm/etnaviv/common.xml.h
+++ b/drivers/gpu/drm/etnaviv/common.xml.h
@@ -8,15 +8,12 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
 git clone git://0x04.net/rules-ng-ng
 The rules-ng-ng source files this header was generated from are:
- state.xml     (  19930 bytes, from 2017-03-09 15:43:43)
+- texdesc_3d.xml (   3183 bytes, from 2017-12-18 16:51:59)
- common.xml    (  23473 bytes, from 2017-03-09 15:43:43)
+- copyright.xml  (   1597 bytes, from 2016-12-08 16:37:56)
- state_hi.xml  (  26403 bytes, from 2017-03-09 15:43:43)
+- common.xml     (  35468 bytes, from 2018-01-22 13:48:54)
- copyright.xml (   1597 bytes, from 2016-12-08 16:37:56)
+- common_3d.xml  (  14615 bytes, from 2017-12-18 16:51:59)
- state_2d.xml  (  51552 bytes, from 2016-12-08 16:37:56)
- state_3d.xml  (  66957 bytes, from 2017-03-09 15:43:43)
- state_vg.xml  (   5975 bytes, from 2016-12-08 16:37:56)
-Copyright (C) 2012-2017 by the following authors:
+Copyright (C) 2012-2018 by the following authors:
 - Wladimir J. van der Laan <laanwj@gmail.com>
 - Christian Gmeiner <christian.gmeiner@gmail.com>
 - Lucas Stach <l.stach@pengutronix.de>
@@ -49,12 +46,7 @@ DEALINGS IN THE SOFTWARE.
 #define SYNC_RECIPIENT_RA                                       0x00000005
 #define SYNC_RECIPIENT_PE                                       0x00000007
 #define SYNC_RECIPIENT_DE                                       0x0000000b
-#define SYNC_RECIPIENT_VG                                       0x0000000f
+#define SYNC_RECIPIENT_BLT                                      0x00000010
-#define SYNC_RECIPIENT_TESSELATOR                               0x00000010
-#define SYNC_RECIPIENT_VG2                                      0x00000011
-#define SYNC_RECIPIENT_TESSELATOR2                              0x00000012
-#define SYNC_RECIPIENT_VG3                                      0x00000013
-#define SYNC_RECIPIENT_TESSELATOR3                              0x00000014
 #define ENDIAN_MODE_NO_SWAP                                     0x00000000
 #define ENDIAN_MODE_SWAP_16                                     0x00000001
 #define ENDIAN_MODE_SWAP_32                                     0x00000002
@@ -77,6 +69,7 @@ DEALINGS IN THE SOFTWARE.
 #define chipModel_GC800                                         0x00000800
 #define chipModel_GC860                                         0x00000860
 #define chipModel_GC880                                         0x00000880
+#define chipModel_GC900                                         0x00000900
 #define chipModel_GC1000                                        0x00001000
 #define chipModel_GC1500                                        0x00001500
 #define chipModel_GC2000                                        0x00002000
@@ -88,6 +81,12 @@ DEALINGS IN THE SOFTWARE.
 #define chipModel_GC5000                                        0x00005000
 #define chipModel_GC5200                                        0x00005200
 #define chipModel_GC6400                                        0x00006400
+#define chipModel_GC7000                                        0x00007000
+#define chipModel_GC7400                                        0x00007400
+#define chipModel_GC8000                                        0x00008000
+#define chipModel_GC8100                                        0x00008100
+#define chipModel_GC8200                                        0x00008200
+#define chipModel_GC8400                                        0x00008400
 #define RGBA_BITS_R                                             0x00000001
 #define RGBA_BITS_G                                             0x00000002
 #define RGBA_BITS_B                                             0x00000004
@@ -203,7 +202,7 @@ DEALINGS IN THE SOFTWARE.
 #define chipMinorFeatures2_RGB888                               0x00001000
 #define chipMinorFeatures2_TX__YUV_ASSEMBLER                    0x00002000
 #define chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING            0x00004000
-#define chipMinorFeatures2_EXTRA_TEXTURE_STATE                  0x00008000
+#define chipMinorFeatures2_TX_FILTER                            0x00008000
 #define chipMinorFeatures2_FULL_DIRECTFB                        0x00010000
 #define chipMinorFeatures2_2D_TILING                            0x00020000
 #define chipMinorFeatures2_THREAD_WALKER_IN_PS                  0x00040000
@@ -242,36 +241,36 @@ DEALINGS IN THE SOFTWARE.
 #define chipMinorFeatures3_TX_ENHANCEMENTS1                     0x00080000
 #define chipMinorFeatures3_SH_ENHANCEMENTS1                     0x00100000
 #define chipMinorFeatures3_SH_ENHANCEMENTS2                     0x00200000
-#define chipMinorFeatures3_UNK22                                0x00400000
+#define chipMinorFeatures3_PE_ENHANCEMENTS1                     0x00400000
 #define chipMinorFeatures3_2D_FC_SOURCE                         0x00800000
-#define chipMinorFeatures3_UNK24                                0x01000000
+#define chipMinorFeatures3_BUG_FIXES_14                         0x01000000
-#define chipMinorFeatures3_UNK25                                0x02000000
+#define chipMinorFeatures3_POWER_OPTIMIZATIONS_0                0x02000000
 #define chipMinorFeatures3_NEW_HZ                               0x04000000
-#define chipMinorFeatures3_UNK27                                0x08000000
+#define chipMinorFeatures3_PE_DITHER_FIX                        0x08000000
-#define chipMinorFeatures3_UNK28                                0x10000000
+#define chipMinorFeatures3_DE_ENHANCEMENTS3                     0x10000000
 #define chipMinorFeatures3_SH_ENHANCEMENTS3                     0x20000000
-#define chipMinorFeatures3_UNK30                                0x40000000
+#define chipMinorFeatures3_SH_ENHANCEMENTS4                     0x40000000
-#define chipMinorFeatures3_UNK31                                0x80000000
+#define chipMinorFeatures3_TX_ENHANCEMENTS2                     0x80000000
-#define chipMinorFeatures4_UNK0                                 0x00000001
+#define chipMinorFeatures4_FE_ENHANCEMENTS1                     0x00000001
 #define chipMinorFeatures4_PE_ENHANCEMENTS2                     0x00000002
 #define chipMinorFeatures4_FRUSTUM_CLIP_FIX                     0x00000004
-#define chipMinorFeatures4_UNK3                                 0x00000008
+#define chipMinorFeatures4_DE_NO_GAMMA                          0x00000008
-#define chipMinorFeatures4_UNK4                                 0x00000010
+#define chipMinorFeatures4_PA_ENHANCEMENTS_2                    0x00000010
 #define chipMinorFeatures4_2D_GAMMA                             0x00000020
 #define chipMinorFeatures4_SINGLE_BUFFER                        0x00000040
-#define chipMinorFeatures4_UNK7                                 0x00000080
+#define chipMinorFeatures4_HI_ENHANCEMENTS_1                    0x00000080
-#define chipMinorFeatures4_UNK8                                 0x00000100
+#define chipMinorFeatures4_TX_ENHANCEMENTS_3                    0x00000100
-#define chipMinorFeatures4_UNK9                                 0x00000200
+#define chipMinorFeatures4_SH_ENHANCEMENTS_5                    0x00000200
-#define chipMinorFeatures4_UNK10                                0x00000400
+#define chipMinorFeatures4_FE_ENHANCEMENTS_2                    0x00000400
 #define chipMinorFeatures4_TX_LERP_PRECISION_FIX                0x00000800
 #define chipMinorFeatures4_2D_COLOR_SPACE_CONVERSION            0x00001000
 #define chipMinorFeatures4_TEXTURE_ASTC                         0x00002000
-#define chipMinorFeatures4_UNK14                                0x00004000
+#define chipMinorFeatures4_PE_ENHANCEMENTS_4                    0x00004000
-#define chipMinorFeatures4_UNK15                                0x00008000
+#define chipMinorFeatures4_MC_ENHANCEMENTS_1                    0x00008000
 #define chipMinorFeatures4_HALTI2                               0x00010000
-#define chipMinorFeatures4_UNK17                                0x00020000
+#define chipMinorFeatures4_2D_MIRROR_EXTENSION                  0x00020000
 #define chipMinorFeatures4_SMALL_MSAA                           0x00040000
-#define chipMinorFeatures4_UNK19                                0x00080000
+#define chipMinorFeatures4_BUG_FIXES_17                         0x00080000
 #define chipMinorFeatures4_NEW_RA                               0x00100000
 #define chipMinorFeatures4_2D_OPF_YUV_OUTPUT                    0x00200000
 #define chipMinorFeatures4_2D_MULTI_SOURCE_BLT_EX2              0x00400000
@@ -280,41 +279,207 @@ DEALINGS IN THE SOFTWARE.
 #define chipMinorFeatures4_BUG_FIXES18                          0x02000000
 #define chipMinorFeatures4_2D_COMPRESSION                       0x04000000
 #define chipMinorFeatures4_PROBE                                0x08000000
-#define chipMinorFeatures4_UNK28                                0x10000000
+#define chipMinorFeatures4_MEDIUM_PRECISION                     0x10000000
 #define chipMinorFeatures4_2D_SUPER_TILE_VERSION                0x20000000
-#define chipMinorFeatures4_UNK30                                0x40000000
+#define chipMinorFeatures4_BUG_FIXES19                          0x40000000
-#define chipMinorFeatures4_UNK31                                0x80000000
+#define chipMinorFeatures4_SH_ENHANCEMENTS6                     0x80000000
-#define chipMinorFeatures5_UNK0                                 0x00000001
+#define chipMinorFeatures5_SH_ENHANCEMENTS7                     0x00000001
-#define chipMinorFeatures5_UNK1                                 0x00000002
+#define chipMinorFeatures5_BUG_FIXES20                          0x00000002
-#define chipMinorFeatures5_UNK2                                 0x00000004
+#define chipMinorFeatures5_DE_ADDRESS_40                        0x00000004
-#define chipMinorFeatures5_UNK3                                 0x00000008
+#define chipMinorFeatures5_MINI_MMU_FIX                         0x00000008
 #define chipMinorFeatures5_EEZ                                  0x00000010
-#define chipMinorFeatures5_UNK5                                 0x00000020
+#define chipMinorFeatures5_BUG_FIXES21                          0x00000020
-#define chipMinorFeatures5_UNK6                                 0x00000040
+#define chipMinorFeatures5_EXTRA_VG_CAPS                        0x00000040
-#define chipMinorFeatures5_UNK7                                 0x00000080
+#define chipMinorFeatures5_MULTI_SRC_V15                        0x00000080
-#define chipMinorFeatures5_UNK8                                 0x00000100
+#define chipMinorFeatures5_BUG_FIXES22                          0x00000100
 #define chipMinorFeatures5_HALTI3                               0x00000200
-#define chipMinorFeatures5_UNK10                                0x00000400
+#define chipMinorFeatures5_TESSELATION_SHADERS                  0x00000400
 #define chipMinorFeatures5_2D_ONE_PASS_FILTER_TAP               0x00000800
-#define chipMinorFeatures5_UNK12                                0x00001000
+#define chipMinorFeatures5_MULTI_SRC_V2_STR_QUAD                0x00001000
 #define chipMinorFeatures5_SEPARATE_SRC_DST                     0x00002000
 #define chipMinorFeatures5_HALTI4                               0x00004000
-#define chipMinorFeatures5_UNK15                                0x00008000
+#define chipMinorFeatures5_RA_WRITE_DEPTH                       0x00008000
 #define chipMinorFeatures5_ANDROID_ONLY                         0x00010000
 #define chipMinorFeatures5_HAS_PRODUCTID                        0x00020000
-#define chipMinorFeatures5_UNK18                                0x00040000
+#define chipMinorFeatures5_TX_SUPPORT_DEC                       0x00040000
-#define chipMinorFeatures5_UNK19                                0x00080000
+#define chipMinorFeatures5_S8_MSAA_COMPRESSION                  0x00080000
 #define chipMinorFeatures5_PE_DITHER_FIX2                       0x00100000
-#define chipMinorFeatures5_UNK21                                0x00200000
+#define chipMinorFeatures5_L2_CACHE_REMOVE                      0x00200000
-#define chipMinorFeatures5_UNK22                                0x00400000
+#define chipMinorFeatures5_FE_ALLOW_RND_VTX_CNT                 0x00400000
-#define chipMinorFeatures5_UNK23                                0x00800000
+#define chipMinorFeatures5_CUBE_MAP_FL28                        0x00800000
-#define chipMinorFeatures5_UNK24                                0x01000000
+#define chipMinorFeatures5_TX_6BIT_FRAC                         0x01000000
-#define chipMinorFeatures5_UNK25                                0x02000000
+#define chipMinorFeatures5_FE_ALLOW_STALL_PREFETCH_ENG          0x02000000
-#define chipMinorFeatures5_UNK26                                0x04000000
+#define chipMinorFeatures5_THIRD_PARTY_COMPRESSION              0x04000000
 #define chipMinorFeatures5_RS_DEPTHSTENCIL_NATIVE_SUPPORT       0x08000000
 #define chipMinorFeatures5_V2_MSAA_COMP_FIX                     0x10000000
-#define chipMinorFeatures5_UNK29                                0x20000000
+#define chipMinorFeatures5_HALTI5                               0x20000000
-#define chipMinorFeatures5_UNK30                                0x40000000
+#define chipMinorFeatures5_EVIS                                 0x40000000
-#define chipMinorFeatures5_UNK31                                0x80000000
+#define chipMinorFeatures5_BLT_ENGINE                           0x80000000
+#define chipMinorFeatures6_BUG_FIXES_23                         0x00000001
+#define chipMinorFeatures6_BUG_FIXES_24                         0x00000002
+#define chipMinorFeatures6_DEC                                  0x00000004
+#define chipMinorFeatures6_VS_TILE_NV12                         0x00000008
+#define chipMinorFeatures6_VS_TILE_NV12_10BIT                   0x00000010
+#define chipMinorFeatures6_RENDER_TARGET_8                      0x00000020
+#define chipMinorFeatures6_TEX_LOD_FLOW_CORR                    0x00000040
+#define chipMinorFeatures6_FACE_LOD                             0x00000080
+#define chipMinorFeatures6_MULTI_CORE_SEMAPHORE_STALL_V2        0x00000100
+#define chipMinorFeatures6_VMSAA                                0x00000200
+#define chipMinorFeatures6_CHIP_ENABLE_LINK                     0x00000400
+#define chipMinorFeatures6_MULTI_SRC_BLT_1_5_ENHANCEMENT        0x00000800
+#define chipMinorFeatures6_MULTI_SRC_BLT_BILINEAR_FILTER        0x00001000
+#define chipMinorFeatures6_RA_HZEZ_CLOCK_CONTROL                0x00002000
+#define chipMinorFeatures6_CACHE128B256BPERLINE                 0x00004000
+#define chipMinorFeatures6_V4_COMPRESSION                       0x00008000
+#define chipMinorFeatures6_PE2D_MAJOR_SUPER_TILE                0x00010000
+#define chipMinorFeatures6_PE_32BPC_COLORMASK_FIX               0x00020000
+#define chipMinorFeatures6_ALPHA_BLENDING_OPT                   0x00040000
+#define chipMinorFeatures6_NEW_GPIPE                            0x00080000
+#define chipMinorFeatures6_PIPELINE_32_ATTRIBUTES               0x00100000
+#define chipMinorFeatures6_MSAA_SHADING                         0x00200000
+#define chipMinorFeatures6_NO_ANISTRO_FILTER                    0x00400000
+#define chipMinorFeatures6_NO_ASTC                              0x00800000
+#define chipMinorFeatures6_NO_DXT                               0x01000000
+#define chipMinorFeatures6_HWTFB                                0x02000000
+#define chipMinorFeatures6_RA_DEPTH_WRITE_MSAA1X_FIX            0x04000000
+#define chipMinorFeatures6_EZHZ_CLOCKGATE_FIX                   0x08000000
+#define chipMinorFeatures6_SH_SNAP2PAGE_FIX                     0x10000000
+#define chipMinorFeatures6_SH_HALFDEPENDENCY_FIX                0x20000000
+#define chipMinorFeatures6_USC_MCFILL_FIX                       0x40000000
+#define chipMinorFeatures6_TPG_TCPERF_FIX                       0x80000000
+#define chipMinorFeatures7_USC_MDFIFO_OVERFLOW_FIX              0x00000001
+#define chipMinorFeatures7_SH_TEXLD_BARRIER_IN_CS_FIX           0x00000002
+#define chipMinorFeatures7_RS_NEW_BASEADDR                      0x00000004
+#define chipMinorFeatures7_PE_8BPP_DUALPIPE_FIX                 0x00000008
+#define chipMinorFeatures7_SH_ADVANCED_INSTR                    0x00000010
+#define chipMinorFeatures7_SH_FLAT_INTERPOLATION_DUAL16_FIX     0x00000020
+#define chipMinorFeatures7_USC_CONTINUOUS_FLUS_FIX              0x00000040
+#define chipMinorFeatures7_SH_SUPPORT_V4                        0x00000080
+#define chipMinorFeatures7_SH_SUPPORT_ALPHA_KILL                0x00000100
+#define chipMinorFeatures7_PE_NO_ALPHA_TEST                     0x00000200
+#define chipMinorFeatures7_TX_LOD_NEAREST_SELECT                0x00000400
+#define chipMinorFeatures7_SH_FIX_LDEXP                         0x00000800
+#define chipMinorFeatures7_SUPPORT_MOVAI                        0x00001000
+#define chipMinorFeatures7_SH_SNAP2PAGE_MAXPAGES_FIX            0x00002000
+#define chipMinorFeatures7_PE_RGBA16I_FIX                       0x00004000
+#define chipMinorFeatures7_BLT_8bpp_256TILE_FC_FIX              0x00008000
+#define chipMinorFeatures7_PE_64BIT_FENCE_FIX                   0x00010000
+#define chipMinorFeatures7_USC_FULL_CACHE_FIX                   0x00020000
+#define chipMinorFeatures7_TX_YUV_ASSEMBLER_10BIT               0x00040000
+#define chipMinorFeatures7_FE_32BIT_INDEX_FIX                   0x00080000
+#define chipMinorFeatures7_BLT_64BPP_MASKED_CLEAR_FIX           0x00100000
+#define chipMinorFeatures7_BIT_SECURITY                         0x00200000
+#define chipMinorFeatures7_BIT_ROBUSTNESS                       0x00400000
+#define chipMinorFeatures7_USC_ATOMIC_FIX                       0x00800000
+#define chipMinorFeatures7_SH_PSO_MSAA1x_FIX                    0x01000000
+#define chipMinorFeatures7_BIT_USC_VX_PERF_FIX                  0x02000000
+#define chipMinorFeatures7_EVIS_NO_ABSDIFF                      0x04000000
+#define chipMinorFeatures7_EVIS_NO_BITREPLACE                   0x08000000
+#define chipMinorFeatures7_EVIS_NO_BOXFILTER                    0x10000000
+#define chipMinorFeatures7_EVIS_NO_CORDIAC                      0x20000000
+#define chipMinorFeatures7_EVIS_NO_DP32                         0x40000000
+#define chipMinorFeatures7_EVIS_NO_FILTER                       0x80000000
+#define chipMinorFeatures8_EVIS_NO_IADD                         0x00000001
+#define chipMinorFeatures8_EVIS_NO_SELECTADD                    0x00000002
+#define chipMinorFeatures8_EVIS_LERP_7OUTPUT                    0x00000004
+#define chipMinorFeatures8_EVIS_ACCSQ_8OUTPUT                   0x00000008
+#define chipMinorFeatures8_USC_GOS_ADDR_FIX                     0x00000010
+#define chipMinorFeatures8_TX_8BIT_UVFRAC                       0x00000020
+#define chipMinorFeatures8_TX_DESC_CACHE_CLOCKGATE_FIX          0x00000040
+#define chipMinorFeatures8_RSBLT_MSAA_DECOMPRESSION             0x00000080
+#define chipMinorFeatures8_TX_INTEGER_COORDINATE                0x00000100
+#define chipMinorFeatures8_DRAWID                               0x00000200
+#define chipMinorFeatures8_PSIO_SAMPLEMASK_IN_R0ZW_FIX          0x00000400
+#define chipMinorFeatures8_TX_INTEGER_COORDINATE_V2             0x00000800
+#define chipMinorFeatures8_MULTI_CORE_BLOCK_SET_CONFIG          0x00001000
+#define chipMinorFeatures8_VG_RESOLVE_ENGINE                    0x00002000
+#define chipMinorFeatures8_VG_PE_COLOR_KEY                      0x00004000
+#define chipMinorFeatures8_VG_IM_INDEX_FORMAT                   0x00008000
+#define chipMinorFeatures8_SNAPPAGE_CMD                         0x00010000
+#define chipMinorFeatures8_SH_NO_INDEX_CONST_ON_A0              0x00020000
+#define chipMinorFeatures8_SH_NO_ONECONST_LIMIT                 0x00040000
+#define chipMinorFeatures8_SH_IMG_LDST_ON_TEMP                  0x00080000
+#define chipMinorFeatures8_COMPUTE_ONLY                         0x00100000
+#define chipMinorFeatures8_SH_IMG_LDST_CLAMP                    0x00200000
+#define chipMinorFeatures8_SH_ICACHE_ALLOC_COUNT_FIX            0x00400000
+#define chipMinorFeatures8_SH_ICACHE_PREFETCH                   0x00800000
+#define chipMinorFeatures8_PE2D_SEPARATE_CACHE                  0x01000000
+#define chipMinorFeatures8_VG_AYUV_INPUT_OUTPUT                 0x02000000
+#define chipMinorFeatures8_VG_DOUBLE_IMAGE                      0x04000000
+#define chipMinorFeatures8_VG_RECTANGLE_STRIPE_MODE             0x08000000
+#define chipMinorFeatures8_VG_MMU                               0x10000000
+#define chipMinorFeatures8_VG_IM_FILTER                         0x20000000
+#define chipMinorFeatures8_VG_IM_YUV_PACKET                     0x40000000
+#define chipMinorFeatures8_VG_IM_YUV_PLANAR                     0x80000000
+#define chipMinorFeatures9_VG_PE_YUV_PACKET                     0x00000001
+#define chipMinorFeatures9_VG_COLOR_PRECISION_8_BIT             0x00000002
+#define chipMinorFeatures9_PE_MSAA_OQ_FIX                       0x00000004
+#define chipMinorFeatures9_PSIO_MSAA_CL_FIX                     0x00000008
+#define chipMinorFeatures9_USC_DEFER_FILL_FIX                   0x00000010
+#define chipMinorFeatures9_SH_CLOCK_GATE_FIX                    0x00000020
+#define chipMinorFeatures9_FE_NEED_DUMMYDRAW                    0x00000040
+#define chipMinorFeatures9_PE2D_LINEAR_YUV420_OUTPUT            0x00000080
+#define chipMinorFeatures9_PE2D_LINEAR_YUV420_10BIT             0x00000100
+#define chipMinorFeatures9_MULTI_CLUSTER                        0x00000200
+#define chipMinorFeatures9_VG_TS_CULLING                        0x00000400
+#define chipMinorFeatures9_VG_FP25                              0x00000800
+#define chipMinorFeatures9_SH_MULTI_WG_PACK                     0x00001000
+#define chipMinorFeatures9_SH_DUAL16_SAMPLEMASK_ZW              0x00002000
+#define chipMinorFeatures9_TPG_TRIVIAL_MODE_FIX                 0x00004000
+#define chipMinorFeatures9_TX_ASTC_MULTISLICE_FIX               0x00008000
+#define chipMinorFeatures9_FE_ROBUST_FIX                        0x00010000
+#define chipMinorFeatures9_SH_GPIPE_ACCESS_FULLTEMPS            0x00020000
+#define chipMinorFeatures9_PSIO_INTERLOCK                       0x00040000
+#define chipMinorFeatures9_PA_WIDELINE_FIX                      0x00080000
+#define chipMinorFeatures9_WIDELINE_HELPER_FIX                  0x00100000
+#define chipMinorFeatures9_G2D_3RD_PARTY_COMPRESSION_1_1        0x00200000
+#define chipMinorFeatures9_TX_FLUSH_L1CACHE                     0x00400000
+#define chipMinorFeatures9_PE_DITHER_FIX2                       0x00800000
+#define chipMinorFeatures9_G2D_DEC400                           0x01000000
+#define chipMinorFeatures9_SH_TEXLD_U_FIX                       0x02000000
+#define chipMinorFeatures9_MC_FCCACHE_BYTEMASK                  0x04000000
+#define chipMinorFeatures9_SH_MULTI_WG_PACK_FIX                 0x08000000
+#define chipMinorFeatures9_DC_OVERLAY_SCALING                   0x10000000
+#define chipMinorFeatures9_DC_SOURCE_ROTATION                   0x20000000
+#define chipMinorFeatures9_DC_TILED                             0x40000000
+#define chipMinorFeatures9_DC_YUV_L1                            0x80000000
+#define chipMinorFeatures10_DC_D30_OUTPUT                       0x00000001
+#define chipMinorFeatures10_DC_MMU                              0x00000002
+#define chipMinorFeatures10_DC_COMPRESSION                      0x00000004
+#define chipMinorFeatures10_DC_QOS                              0x00000008
+#define chipMinorFeatures10_PE_ADVANCE_BLEND_PART0              0x00000010
+#define chipMinorFeatures10_FE_PATCHLIST_FETCH_FIX              0x00000020
+#define chipMinorFeatures10_RA_CG_FIX                           0x00000040
+#define chipMinorFeatures10_EVIS_VX2                            0x00000080
+#define chipMinorFeatures10_NN_FLOAT                            0x00000100
+#define chipMinorFeatures10_DEC400                              0x00000200
+#define chipMinorFeatures10_LS_SUPPORT_PERCOMP_DEPENDENCY       0x00000400
+#define chipMinorFeatures10_TP_ENGINE                           0x00000800
+#define chipMinorFeatures10_MULTI_CORE_BLOCK_SET_CONFIG2        0x00001000
+#define chipMinorFeatures10_PE_VMSAA_COVERAGE_CACHE_FIX         0x00002000
+#define chipMinorFeatures10_SECURITY_AHB                        0x00004000
+#define chipMinorFeatures10_MULTICORE_SEMAPHORESTALL_V3         0x00008000
+#define chipMinorFeatures10_SMALLBATCH                          0x00010000
+#define chipMinorFeatures10_SH_CMPLX                            0x00020000
+#define chipMinorFeatures10_SH_IDIV0_SWZL_EHS                   0x00040000
+#define chipMinorFeatures10_TX_LERP_LESS_BIT                    0x00080000
+#define chipMinorFeatures10_SH_GM_ENDIAN                        0x00100000
+#define chipMinorFeatures10_SH_GM_USC_UNALLOC                   0x00200000
+#define chipMinorFeatures10_SH_END_OF_BB                        0x00400000
+#define chipMinorFeatures10_VIP_V7                              0x00800000
+#define chipMinorFeatures10_TX_BORDER_CLAMP_FIX                 0x01000000
+#define chipMinorFeatures10_SH_IMG_LD_LASTPIXEL_FIX             0x02000000
+#define chipMinorFeatures10_ASYNC_BLT                           0x04000000
+#define chipMinorFeatures10_ASYNC_FE_FENCE_FIX                  0x08000000
+#define chipMinorFeatures10_PSCS_THROTTLE                       0x10000000
+#define chipMinorFeatures10_SEPARATE_LS                         0x20000000
+#define chipMinorFeatures10_MCFE                                0x40000000
+#define chipMinorFeatures10_WIDELINE_TRIANGLE_EMU               0x80000000
+#define chipMinorFeatures11_VG_RESOLUTION_8K                    0x00000001
+#define chipMinorFeatures11_FENCE_32BIT                         0x00000002
+#define chipMinorFeatures11_FENCE_64BIT                         0x00000004
+#define chipMinorFeatures11_NN_INTERLEVE8                       0x00000008
+#define chipMinorFeatures11_TP_REORDER                          0x00000010
+#define chipMinorFeatures11_PE_DEPTH_ONLY_OQFIX                 0x00000020
 #endif /* COMMON_XML */
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_buffer.c b/drivers/gpu/drm/etnaviv/etnaviv_buffer.c
index 99ad2f073c6e..bfc6d4aa3b7c 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_buffer.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_buffer.c
@@ -215,6 +215,24 @@ u16 etnaviv_buffer_config_mmuv2(struct etnaviv_gpu *gpu, u32 mtlb_addr, u32 safe
        return buffer->user_size / 8;
 }
+u16 etnaviv_buffer_config_pta(struct etnaviv_gpu *gpu)
+{
+        struct etnaviv_cmdbuf *buffer = &gpu->buffer;
+        lockdep_assert_held(&gpu->lock);
+        buffer->user_size = 0;
+        CMD_LOAD_STATE(buffer, VIVS_MMUv2_PTA_CONFIG,
+                       VIVS_MMUv2_PTA_CONFIG_INDEX(0));
+        CMD_END(buffer);
+        buffer->user_size = ALIGN(buffer->user_size, 8);
+        return buffer->user_size / 8;
+}
 void etnaviv_buffer_end(struct etnaviv_gpu *gpu)
 {
        struct etnaviv_cmdbuf *buffer = &gpu->buffer;
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.c b/drivers/gpu/drm/etnaviv/etnaviv_drv.c
index 6faf4042db23..ab50090d066c 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_drv.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.c
@@ -101,12 +101,25 @@ static void load_gpu(struct drm_device *dev)
 static int etnaviv_open(struct drm_device *dev, struct drm_file *file)
 {
+        struct etnaviv_drm_private *priv = dev->dev_private;
        struct etnaviv_file_private *ctx;
+        int i;
        ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
        if (!ctx)
                return -ENOMEM;
+        for (i = 0; i < ETNA_MAX_PIPES; i++) {
+                struct etnaviv_gpu *gpu = priv->gpu[i];
+                if (gpu) {
+                        drm_sched_entity_init(&gpu->sched,
+                                &ctx->sched_entity[i],
+                                &gpu->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL],
+                                32, NULL);
+                        }
+        }
        file->driver_priv = ctx;
        return 0;
@@ -126,6 +139,9 @@ static void etnaviv_postclose(struct drm_device *dev, struct drm_file *file)
                        if (gpu->lastctx == ctx)
                                gpu->lastctx = NULL;
                        mutex_unlock(&gpu->lock);
+                        drm_sched_entity_fini(&gpu->sched,
+                                              &ctx->sched_entity[i]);
                }
        }
@@ -637,25 +653,21 @@ static int compare_str(struct device *dev, void *data)
 static int etnaviv_pdev_probe(struct platform_device *pdev)
 {
        struct device *dev = &pdev->dev;
-        struct device_node *node = dev->of_node;
        struct component_match *match = NULL;
        dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
-        if (node) {
+        if (!dev->platform_data) {
                struct device_node *core_node;
-                int i;
-                for (i = 0; ; i++) {
+                for_each_compatible_node(core_node, NULL, "vivante,gc") {
-                        core_node = of_parse_phandle(node, "cores", i);
+                        if (!of_device_is_available(core_node))
-                        if (!core_node)
+                                continue;
-                                break;
                        drm_of_component_match_add(&pdev->dev, &match,
                                                   compare_of, core_node);
-                        of_node_put(core_node);
                }
-        } else if (dev->platform_data) {
+        } else {
                char **names = dev->platform_data;
                unsigned i;
@@ -673,25 +685,18 @@ static int etnaviv_pdev_remove(struct platform_device *pdev)
        return 0;
 }
-static const struct of_device_id dt_match[] = {
-        { .compatible = "fsl,imx-gpu-subsystem" },
-        { .compatible = "marvell,dove-gpu-subsystem" },
-        {}
-};
-MODULE_DEVICE_TABLE(of, dt_match);
 static struct platform_driver etnaviv_platform_driver = {
        .probe      = etnaviv_pdev_probe,
        .remove     = etnaviv_pdev_remove,
        .driver     = {
                .name   = "etnaviv",
-                .of_match_table = dt_match,
        },
 };
 static int __init etnaviv_init(void)
 {
        int ret;
+        struct device_node *np;
        etnaviv_validate_init();
@@ -703,6 +708,19 @@ static int __init etnaviv_init(void)
        if (ret != 0)
                platform_driver_unregister(&etnaviv_gpu_driver);
+        /*
+         * If the DT contains at least one available GPU device, instantiate
+         * the DRM platform device.
+         */
+        for_each_compatible_node(np, NULL, "vivante,gc") {
+                if (!of_device_is_available(np))
+                        continue;
+                platform_device_register_simple("etnaviv", -1, NULL, 0);
+                of_node_put(np);
+                break;
+        }
        return ret;
 }
 module_init(etnaviv_init);
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.h b/drivers/gpu/drm/etnaviv/etnaviv_drv.h
index a54f0b758a5c..ddb17ee565e9 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_drv.h
+++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.h
@@ -34,6 +34,7 @@
 #include <drm/drm_fb_helper.h>
 #include <drm/drm_gem.h>
 #include <drm/etnaviv_drm.h>
+#include <drm/gpu_scheduler.h>
 struct etnaviv_cmdbuf;
 struct etnaviv_gpu;
@@ -42,11 +43,11 @@ struct etnaviv_gem_object;
 struct etnaviv_gem_submit;
 struct etnaviv_file_private {
-        /* currently we don't do anything useful with this.. but when
+        /*
-         * per-context address spaces are supported we'd keep track of
+         * When per-context address spaces are supported we'd keep track of
         * the context's page-tables here.
         */
-        int dummy;
+        struct drm_sched_entity         sched_entity[ETNA_MAX_PIPES];
 };
 struct etnaviv_drm_private {
@@ -85,6 +86,7 @@ int etnaviv_gem_new_userptr(struct drm_device *dev, struct drm_file *file,
        uintptr_t ptr, u32 size, u32 flags, u32 *handle);
 u16 etnaviv_buffer_init(struct etnaviv_gpu *gpu);
 u16 etnaviv_buffer_config_mmuv2(struct etnaviv_gpu *gpu, u32 mtlb_addr, u32 safe_addr);
+u16 etnaviv_buffer_config_pta(struct etnaviv_gpu *gpu);
 void etnaviv_buffer_end(struct etnaviv_gpu *gpu);
 void etnaviv_sync_point_queue(struct etnaviv_gpu *gpu, unsigned int event);
 void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32 exec_state,
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_dump.c b/drivers/gpu/drm/etnaviv/etnaviv_dump.c
index 6d0909c589d1..48aef6cf6a42 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_dump.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_dump.c
@@ -20,9 +20,13 @@
 #include "etnaviv_gem.h"
 #include "etnaviv_gpu.h"
 #include "etnaviv_mmu.h"
+#include "etnaviv_sched.h"
 #include "state.xml.h"
 #include "state_hi.xml.h"
+static bool etnaviv_dump_core = true;
+module_param_named(dump_core, etnaviv_dump_core, bool, 0600);
 struct core_dump_iterator {
        void *start;
        struct etnaviv_dump_object_header *hdr;
@@ -121,10 +125,16 @@ void etnaviv_core_dump(struct etnaviv_gpu *gpu)
        struct etnaviv_vram_mapping *vram;
        struct etnaviv_gem_object *obj;
        struct etnaviv_gem_submit *submit;
+        struct drm_sched_job *s_job;
        unsigned int n_obj, n_bomap_pages;
        size_t file_size, mmu_size;
        __le64 *bomap, *bomap_start;
+        /* Only catch the first event, or when manually re-armed */
+        if (!etnaviv_dump_core)
+                return;
+        etnaviv_dump_core = false;
        mmu_size = etnaviv_iommu_dump_size(gpu->mmu);
        /* We always dump registers, mmu, ring and end marker */
@@ -135,10 +145,13 @@ void etnaviv_core_dump(struct etnaviv_gpu *gpu)
                    mmu_size + gpu->buffer.size;
        /* Add in the active command buffers */
-        list_for_each_entry(submit, &gpu->active_submit_list, node) {
+        spin_lock(&gpu->sched.job_list_lock);
+        list_for_each_entry(s_job, &gpu->sched.ring_mirror_list, node) {
+                submit = to_etnaviv_submit(s_job);
                file_size += submit->cmdbuf.size;
                n_obj++;
        }
+        spin_unlock(&gpu->sched.job_list_lock);
        /* Add in the active buffer objects */
        list_for_each_entry(vram, &gpu->mmu->mappings, mmu_node) {
@@ -180,10 +193,14 @@ void etnaviv_core_dump(struct etnaviv_gpu *gpu)
                              gpu->buffer.size,
                              etnaviv_cmdbuf_get_va(&gpu->buffer));
-        list_for_each_entry(submit, &gpu->active_submit_list, node)
+        spin_lock(&gpu->sched.job_list_lock);
+        list_for_each_entry(s_job, &gpu->sched.ring_mirror_list, node) {
+                submit = to_etnaviv_submit(s_job);
                etnaviv_core_dump_mem(&iter, ETDUMP_BUF_CMD,
                                      submit->cmdbuf.vaddr, submit->cmdbuf.size,
                                      etnaviv_cmdbuf_get_va(&submit->cmdbuf));
+        }
+        spin_unlock(&gpu->sched.job_list_lock);
        /* Reserve space for the bomap */
        if (n_bomap_pages) {
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem.h b/drivers/gpu/drm/etnaviv/etnaviv_gem.h
index be72a9833f2b..93e696fcc14f 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gem.h
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gem.h
@@ -94,6 +94,9 @@ struct etnaviv_gem_submit_bo {
        u32 flags;
        struct etnaviv_gem_object *obj;
        struct etnaviv_vram_mapping *mapping;
+        struct dma_fence *excl;
+        unsigned int nr_shared;
+        struct dma_fence **shared;
 };
 /* Created per submit-ioctl, to track bo's and cmdstream bufs, etc,
@@ -101,9 +104,11 @@ struct etnaviv_gem_submit_bo {
 * make it easier to unwind when things go wrong, etc).
 */
 struct etnaviv_gem_submit {
+        struct drm_sched_job sched_job;
        struct kref refcount;
        struct etnaviv_gpu *gpu;
        struct dma_fence *out_fence, *in_fence;
+        int out_fence_id;
        struct list_head node; /* GPU active submit list */
        struct etnaviv_cmdbuf cmdbuf;
        bool runtime_resumed;
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c b/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c
index 1f8202bca061..46ecd3e66ac9 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c
@@ -22,6 +22,7 @@
 #include "etnaviv_gpu.h"
 #include "etnaviv_gem.h"
 #include "etnaviv_perfmon.h"
+#include "etnaviv_sched.h"
 /*
 * Cmdstream submission:
@@ -169,29 +170,33 @@ fail:
        return ret;
 }
-static int submit_fence_sync(const struct etnaviv_gem_submit *submit)
+static int submit_fence_sync(struct etnaviv_gem_submit *submit)
 {
-        unsigned int context = submit->gpu->fence_context;
        int i, ret = 0;
        for (i = 0; i < submit->nr_bos; i++) {
-                struct etnaviv_gem_object *etnaviv_obj = submit->bos[i].obj;
+                struct etnaviv_gem_submit_bo *bo = &submit->bos[i];
-                bool write = submit->bos[i].flags & ETNA_SUBMIT_BO_WRITE;
+                struct reservation_object *robj = bo->obj->resv;
-                bool explicit = !!(submit->flags & ETNA_SUBMIT_NO_IMPLICIT);
-                ret = etnaviv_gpu_fence_sync_obj(etnaviv_obj, context, write,
+                if (!(bo->flags & ETNA_SUBMIT_BO_WRITE)) {
-                                                 explicit);
+                        ret = reservation_object_reserve_shared(robj);
-                if (ret)
+                        if (ret)
-                        break;
+                                return ret;
-        }
+                }
+                if (submit->flags & ETNA_SUBMIT_NO_IMPLICIT)
+                        continue;
+                if (bo->flags & ETNA_SUBMIT_BO_WRITE) {
+                        ret = reservation_object_get_fences_rcu(robj, &bo->excl,
+                                                                &bo->nr_shared,
+                                                                &bo->shared);
+                        if (ret)
+                                return ret;
+                } else {
+                        bo->excl = reservation_object_get_excl_rcu(robj);
+                }
-        if (submit->flags & ETNA_SUBMIT_FENCE_FD_IN) {
-                /*
-                 * Wait if the fence is from a foreign context, or if the fence
-                 * array contains any fence from a foreign context.
-                 */
-                if (!dma_fence_match_context(submit->in_fence, context))
-                        ret = dma_fence_wait(submit->in_fence, true);
        }
        return ret;
@@ -381,8 +386,13 @@ static void submit_cleanup(struct kref *kref)
        if (submit->in_fence)
                dma_fence_put(submit->in_fence);
-        if (submit->out_fence)
+        if (submit->out_fence) {
+                /* first remove from IDR, so fence can not be found anymore */
+                mutex_lock(&submit->gpu->fence_idr_lock);
+                idr_remove(&submit->gpu->fence_idr, submit->out_fence_id);
+                mutex_unlock(&submit->gpu->fence_idr_lock);
                dma_fence_put(submit->out_fence);
+        }
        kfree(submit->pmrs);
        kfree(submit);
 }
@@ -395,6 +405,7 @@ void etnaviv_submit_put(struct etnaviv_gem_submit *submit)
 int etnaviv_ioctl_gem_submit(struct drm_device *dev, void *data,
                struct drm_file *file)
 {
+        struct etnaviv_file_private *ctx = file->driver_priv;
        struct etnaviv_drm_private *priv = dev->dev_private;
        struct drm_etnaviv_gem_submit *args = data;
        struct drm_etnaviv_gem_submit_reloc *relocs;
@@ -503,10 +514,6 @@ int etnaviv_ioctl_gem_submit(struct drm_device *dev, void *data,
        if (ret)
                goto err_submit_objects;
-        ret = submit_lock_objects(submit, &ticket);
-        if (ret)
-                goto err_submit_objects;
        if (!etnaviv_cmd_validate_one(gpu, stream, args->stream_size / 4,
                                      relocs, args->nr_relocs)) {
                ret = -EINVAL;
@@ -521,10 +528,6 @@ int etnaviv_ioctl_gem_submit(struct drm_device *dev, void *data,
                }
        }
-        ret = submit_fence_sync(submit);
-        if (ret)
-                goto err_submit_objects;
        ret = submit_pin_objects(submit);
        if (ret)
                goto err_submit_objects;
@@ -539,9 +542,16 @@ int etnaviv_ioctl_gem_submit(struct drm_device *dev, void *data,
                goto err_submit_objects;
        memcpy(submit->cmdbuf.vaddr, stream, args->stream_size);
-        submit->cmdbuf.user_size = ALIGN(args->stream_size, 8);
-        ret = etnaviv_gpu_submit(gpu, submit);
+        ret = submit_lock_objects(submit, &ticket);
+        if (ret)
+                goto err_submit_objects;
+        ret = submit_fence_sync(submit);
+        if (ret)
+                goto err_submit_objects;
+        ret = etnaviv_sched_push_job(&ctx->sched_entity[args->pipe], submit);
        if (ret)
                goto err_submit_objects;
@@ -563,7 +573,7 @@ int etnaviv_ioctl_gem_submit(struct drm_device *dev, void *data,
        }
        args->fence_fd = out_fence_fd;
-        args->fence = submit->out_fence->seqno;
+        args->fence = submit->out_fence_id;
 err_submit_objects:
        etnaviv_submit_put(submit);
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
index 21d0d22f1168..8a88799bf79b 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
@@ -26,19 +26,21 @@
 #include "etnaviv_gem.h"
 #include "etnaviv_mmu.h"
 #include "etnaviv_perfmon.h"
+#include "etnaviv_sched.h"
 #include "common.xml.h"
 #include "state.xml.h"
 #include "state_hi.xml.h"
 #include "cmdstream.xml.h"
+#ifndef PHYS_OFFSET
+#define PHYS_OFFSET 0
+#endif
 static const struct platform_device_id gpu_ids[] = {
        { .name = "etnaviv-gpu,2d" },
        { },
 };
-static bool etnaviv_dump_core = true;
-module_param_named(dump_core, etnaviv_dump_core, bool, 0600);
 /*
 * Driver functions:
 */
@@ -82,6 +84,30 @@ int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
                *value = gpu->identity.minor_features5;
                break;
+        case ETNAVIV_PARAM_GPU_FEATURES_7:
+                *value = gpu->identity.minor_features6;
+                break;
+        case ETNAVIV_PARAM_GPU_FEATURES_8:
+                *value = gpu->identity.minor_features7;
+                break;
+        case ETNAVIV_PARAM_GPU_FEATURES_9:
+                *value = gpu->identity.minor_features8;
+                break;
+        case ETNAVIV_PARAM_GPU_FEATURES_10:
+                *value = gpu->identity.minor_features9;
+                break;
+        case ETNAVIV_PARAM_GPU_FEATURES_11:
+                *value = gpu->identity.minor_features10;
+                break;
+        case ETNAVIV_PARAM_GPU_FEATURES_12:
+                *value = gpu->identity.minor_features11;
+                break;
        case ETNAVIV_PARAM_GPU_STREAM_COUNT:
                *value = gpu->identity.stream_count;
                break;
@@ -348,6 +374,13 @@ static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
        dev_info(gpu->dev, "model: GC%x, revision: %x\n",
                 gpu->identity.model, gpu->identity.revision);
+        /*
+         * If there is a match in the HWDB, we aren't interested in the
+         * remaining register values, as they might be wrong.
+         */
+        if (etnaviv_fill_identity_from_hwdb(gpu))
+                return;
        gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE);
        /* Disable fast clear on GC700. */
@@ -448,9 +481,14 @@ static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
                control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
                gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
-                /* set soft reset. */
+                if (gpu->sec_mode == ETNA_SEC_KERNEL) {
-                control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
+                        gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL,
-                gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
+                                  VIVS_MMUv2_AHB_CONTROL_RESET);
+                } else {
+                        /* set soft reset. */
+                        control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
+                        gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
+                }
                /* wait for reset. */
                usleep_range(10, 20);
@@ -561,6 +599,12 @@ void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch)
        gpu_write(gpu, VIVS_FE_COMMAND_CONTROL,
                  VIVS_FE_COMMAND_CONTROL_ENABLE |
                  VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch));
+        if (gpu->sec_mode == ETNA_SEC_KERNEL) {
+                gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL,
+                          VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE |
+                          VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(prefetch));
+        }
 }
 static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu)
@@ -634,6 +678,12 @@ static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
                gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);
        }
+        if (gpu->sec_mode == ETNA_SEC_KERNEL) {
+                u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL);
+                val |= VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS;
+                gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val);
+        }
        /* setup the pulse eater */
        etnaviv_gpu_setup_pulse_eater(gpu);
@@ -696,6 +746,14 @@ int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
                gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
        }
+        /*
+         * On cores with security features supported, we claim control over the
+         * security states.
+         */
+        if ((gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) &&
+            (gpu->identity.minor_features10 & chipMinorFeatures10_SECURITY_AHB))
+                gpu->sec_mode = ETNA_SEC_KERNEL;
        ret = etnaviv_hw_reset(gpu);
        if (ret) {
                dev_err(gpu->dev, "GPU reset failed\n");
@@ -807,6 +865,8 @@ int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
        verify_dma(gpu, &debug);
        seq_puts(m, "\tfeatures\n");
+        seq_printf(m, "\t major_features: 0x%08x\n",
+                   gpu->identity.features);
        seq_printf(m, "\t minor_features0: 0x%08x\n",
                   gpu->identity.minor_features0);
        seq_printf(m, "\t minor_features1: 0x%08x\n",
@@ -819,6 +879,18 @@ int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
                   gpu->identity.minor_features4);
        seq_printf(m, "\t minor_features5: 0x%08x\n",
                   gpu->identity.minor_features5);
+        seq_printf(m, "\t minor_features6: 0x%08x\n",
+                   gpu->identity.minor_features6);
+        seq_printf(m, "\t minor_features7: 0x%08x\n",
+                   gpu->identity.minor_features7);
+        seq_printf(m, "\t minor_features8: 0x%08x\n",
+                   gpu->identity.minor_features8);
+        seq_printf(m, "\t minor_features9: 0x%08x\n",
+                   gpu->identity.minor_features9);
+        seq_printf(m, "\t minor_features10: 0x%08x\n",
+                   gpu->identity.minor_features10);
+        seq_printf(m, "\t minor_features11: 0x%08x\n",
+                   gpu->identity.minor_features11);
        seq_puts(m, "\tspecs\n");
        seq_printf(m, "\t stream_count:  %d\n",
@@ -912,38 +984,24 @@ int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
 }
 #endif
-/*
+void etnaviv_gpu_recover_hang(struct etnaviv_gpu *gpu)
- * Hangcheck detection for locked gpu:
- */
-static void recover_worker(struct work_struct *work)
 {
-        struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
-                                               recover_work);
        unsigned long flags;
        unsigned int i = 0;
-        dev_err(gpu->dev, "hangcheck recover!\n");
+        dev_err(gpu->dev, "recover hung GPU!\n");
        if (pm_runtime_get_sync(gpu->dev) < 0)
                return;
        mutex_lock(&gpu->lock);
-        /* Only catch the first event, or when manually re-armed */
-        if (etnaviv_dump_core) {
-                etnaviv_core_dump(gpu);
-                etnaviv_dump_core = false;
-        }
        etnaviv_hw_reset(gpu);
        /* complete all events, the GPU won't do it after the reset */
        spin_lock_irqsave(&gpu->event_spinlock, flags);
-        for_each_set_bit_from(i, gpu->event_bitmap, ETNA_NR_EVENTS) {
+        for_each_set_bit_from(i, gpu->event_bitmap, ETNA_NR_EVENTS)
-                dma_fence_signal(gpu->event[i].fence);
-                gpu->event[i].fence = NULL;
                complete(&gpu->event_free);
-        }
        bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
        spin_unlock_irqrestore(&gpu->event_spinlock, flags);
        gpu->completed_fence = gpu->active_fence;
@@ -955,56 +1013,6 @@ static void recover_worker(struct work_struct *work)
        mutex_unlock(&gpu->lock);
        pm_runtime_mark_last_busy(gpu->dev);
        pm_runtime_put_autosuspend(gpu->dev);
-        /* Retire the buffer objects in a work */
-        queue_work(gpu->wq, &gpu->retire_work);
-}
-static void hangcheck_timer_reset(struct etnaviv_gpu *gpu)
-{
-        DBG("%s", dev_name(gpu->dev));
-        mod_timer(&gpu->hangcheck_timer,
-                  round_jiffies_up(jiffies + DRM_ETNAVIV_HANGCHECK_JIFFIES));
-}
-static void hangcheck_handler(struct timer_list *t)
-{
-        struct etnaviv_gpu *gpu = from_timer(gpu, t, hangcheck_timer);
-        u32 fence = gpu->completed_fence;
-        bool progress = false;
-        if (fence != gpu->hangcheck_fence) {
-                gpu->hangcheck_fence = fence;
-                progress = true;
-        }
-        if (!progress) {
-                u32 dma_addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
-                int change = dma_addr - gpu->hangcheck_dma_addr;
-                if (change < 0 || change > 16) {
-                        gpu->hangcheck_dma_addr = dma_addr;
-                        progress = true;
-                }
-        }
-        if (!progress && fence_after(gpu->active_fence, fence)) {
-                dev_err(gpu->dev, "hangcheck detected gpu lockup!\n");
-                dev_err(gpu->dev, "     completed fence: %u\n", fence);
-                dev_err(gpu->dev, "     active fence: %u\n",
-                        gpu->active_fence);
-                queue_work(gpu->wq, &gpu->recover_work);
-        }
-        /* if still more pending work, reset the hangcheck timer: */
-        if (fence_after(gpu->active_fence, gpu->hangcheck_fence))
-                hangcheck_timer_reset(gpu);
-}
-static void hangcheck_disable(struct etnaviv_gpu *gpu)
-{
-        del_timer_sync(&gpu->hangcheck_timer);
-        cancel_work_sync(&gpu->recover_work);
 }
 /* fence object management */
@@ -1080,54 +1088,6 @@ static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu)
        return &f->base;
 }
-int etnaviv_gpu_fence_sync_obj(struct etnaviv_gem_object *etnaviv_obj,
-        unsigned int context, bool exclusive, bool explicit)
-{
-        struct reservation_object *robj = etnaviv_obj->resv;
-        struct reservation_object_list *fobj;
-        struct dma_fence *fence;
-        int i, ret;
-        if (!exclusive) {
-                ret = reservation_object_reserve_shared(robj);
-                if (ret)
-                        return ret;
-        }
-        if (explicit)
-                return 0;
-        /*
-         * If we have any shared fences, then the exclusive fence
-         * should be ignored as it will already have been signalled.
-         */
-        fobj = reservation_object_get_list(robj);
-        if (!fobj || fobj->shared_count == 0) {
-                /* Wait on any existing exclusive fence which isn't our own */
-                fence = reservation_object_get_excl(robj);
-                if (fence && fence->context != context) {
-                        ret = dma_fence_wait(fence, true);
-                        if (ret)
-                                return ret;
-                }
-        }
-        if (!exclusive || !fobj)
-                return 0;
-        for (i = 0; i < fobj->shared_count; i++) {
-                fence = rcu_dereference_protected(fobj->shared[i],
-                                                reservation_object_held(robj));
-                if (fence->context != context) {
-                        ret = dma_fence_wait(fence, true);
-                        if (ret)
-                                return ret;
-                }
-        }
-        return 0;
-}
 /*
 * event management:
 */
@@ -1194,67 +1154,47 @@ static void event_free(struct etnaviv_gpu *gpu, unsigned int event)
 /*
 * Cmdstream submission/retirement:
 */
-static void retire_worker(struct work_struct *work)
-{
-        struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
-                                               retire_work);
-        u32 fence = gpu->completed_fence;
-        struct etnaviv_gem_submit *submit, *tmp;
-        LIST_HEAD(retire_list);
-        mutex_lock(&gpu->lock);
-        list_for_each_entry_safe(submit, tmp, &gpu->active_submit_list, node) {
-                if (!dma_fence_is_signaled(submit->out_fence))
-                        break;
-                list_move(&submit->node, &retire_list);
-        }
-        gpu->retired_fence = fence;
-        mutex_unlock(&gpu->lock);
-        list_for_each_entry_safe(submit, tmp, &retire_list, node)
-                etnaviv_submit_put(submit);
-}
 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
-        u32 fence, struct timespec *timeout)
+        u32 id, struct timespec *timeout)
 {
+        struct dma_fence *fence;
        int ret;
-        if (fence_after(fence, gpu->next_fence)) {
+        /*
-                DRM_ERROR("waiting on invalid fence: %u (of %u)\n",
+         * Look up the fence and take a reference. We might still find a fence
-                                fence, gpu->next_fence);
+         * whose refcount has already dropped to zero. dma_fence_get_rcu
-                return -EINVAL;
+         * pretends we didn't find a fence in that case.
-        }
+         */
+        rcu_read_lock();
+        fence = idr_find(&gpu->fence_idr, id);
+        if (fence)
+                fence = dma_fence_get_rcu(fence);
+        rcu_read_unlock();
+        if (!fence)
+                return 0;
        if (!timeout) {
                /* No timeout was requested: just test for completion */
-                ret = fence_completed(gpu, fence) ? 0 : -EBUSY;
+                ret = dma_fence_is_signaled(fence) ? 0 : -EBUSY;
        } else {
                unsigned long remaining = etnaviv_timeout_to_jiffies(timeout);
-                ret = wait_event_interruptible_timeout(gpu->fence_event,
+                ret = dma_fence_wait_timeout(fence, true, remaining);
-                                                fence_completed(gpu, fence),
+                if (ret == 0)
-                                                remaining);
-                if (ret == 0) {
-                        DBG("timeout waiting for fence: %u (retired: %u completed: %u)",
-                                fence, gpu->retired_fence,
-                                gpu->completed_fence);
                        ret = -ETIMEDOUT;
-                } else if (ret != -ERESTARTSYS) {
+                else if (ret != -ERESTARTSYS)
                        ret = 0;
-                }
        }
+        dma_fence_put(fence);
        return ret;
 }
 /*
 * Wait for an object to become inactive.  This, on it's own, is not race
- * free: the object is moved by the retire worker off the active list, and
+ * free: the object is moved by the scheduler off the active list, and
 * then the iova is put.  Moreover, the object could be re-submitted just
 * after we notice that it's become inactive.
 *
@@ -1343,16 +1283,19 @@ static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu,
 /* add bo's to gpu's ring, and kick gpu: */
-int etnaviv_gpu_submit(struct etnaviv_gpu *gpu,
+struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit)
-        struct etnaviv_gem_submit *submit)
 {
+        struct etnaviv_gpu *gpu = submit->gpu;
+        struct dma_fence *gpu_fence;
        unsigned int i, nr_events = 1, event[3];
        int ret;
-        ret = pm_runtime_get_sync(gpu->dev);
+        if (!submit->runtime_resumed) {
-        if (ret < 0)
+                ret = pm_runtime_get_sync(gpu->dev);
-                return ret;
+                if (ret < 0)
-        submit->runtime_resumed = true;
+                        return NULL;
+                submit->runtime_resumed = true;
+        }
        /*
         * if there are performance monitor requests we need to have
@@ -1367,21 +1310,20 @@ int etnaviv_gpu_submit(struct etnaviv_gpu *gpu,
        ret = event_alloc(gpu, nr_events, event);
        if (ret) {
                DRM_ERROR("no free events\n");
-                return ret;
+                return NULL;
        }
        mutex_lock(&gpu->lock);
-        submit->out_fence = etnaviv_gpu_fence_alloc(gpu);
+        gpu_fence = etnaviv_gpu_fence_alloc(gpu);
-        if (!submit->out_fence) {
+        if (!gpu_fence) {
                for (i = 0; i < nr_events; i++)
                        event_free(gpu, event[i]);
-                ret = -ENOMEM;
                goto out_unlock;
        }
-        gpu->active_fence = submit->out_fence->seqno;
+        gpu->active_fence = gpu_fence->seqno;
        if (submit->nr_pmrs) {
                gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre;
@@ -1390,8 +1332,8 @@ int etnaviv_gpu_submit(struct etnaviv_gpu *gpu,
                etnaviv_sync_point_queue(gpu, event[1]);
        }
-        kref_get(&submit->refcount);
+        gpu->event[event[0]].fence = gpu_fence;
-        gpu->event[event[0]].fence = submit->out_fence;
+        submit->cmdbuf.user_size = submit->cmdbuf.size - 8;
        etnaviv_buffer_queue(gpu, submit->exec_state, event[0],
                             &submit->cmdbuf);
@@ -1402,15 +1344,10 @@ int etnaviv_gpu_submit(struct etnaviv_gpu *gpu,
                etnaviv_sync_point_queue(gpu, event[2]);
        }
-        list_add_tail(&submit->node, &gpu->active_submit_list);
-        hangcheck_timer_reset(gpu);
-        ret = 0;
 out_unlock:
        mutex_unlock(&gpu->lock);
-        return ret;
+        return gpu_fence;
 }
 static void sync_point_worker(struct work_struct *work)
@@ -1428,9 +1365,35 @@ static void sync_point_worker(struct work_struct *work)
        etnaviv_gpu_start_fe(gpu, addr + 2, 2);
 }
-/*
+static void dump_mmu_fault(struct etnaviv_gpu *gpu)
- * Init/Cleanup:
+{
- */
+        u32 status_reg, status;
+        int i;
+        if (gpu->sec_mode == ETNA_SEC_NONE)
+                status_reg = VIVS_MMUv2_STATUS;
+        else
+                status_reg = VIVS_MMUv2_SEC_STATUS;
+        status = gpu_read(gpu, status_reg);
+        dev_err_ratelimited(gpu->dev, "MMU fault status 0x%08x\n", status);
+        for (i = 0; i < 4; i++) {
+                u32 address_reg;
+                if (!(status & (VIVS_MMUv2_STATUS_EXCEPTION0__MASK << (i * 4))))
+                        continue;
+                if (gpu->sec_mode == ETNA_SEC_NONE)
+                        address_reg = VIVS_MMUv2_EXCEPTION_ADDR(i);
+                else
+                        address_reg = VIVS_MMUv2_SEC_EXCEPTION_ADDR;
+                dev_err_ratelimited(gpu->dev, "MMU %d fault addr 0x%08x\n", i,
+                                    gpu_read(gpu, address_reg));
+        }
+}
 static irqreturn_t irq_handler(int irq, void *data)
 {
        struct etnaviv_gpu *gpu = data;
@@ -1451,17 +1414,7 @@ static irqreturn_t irq_handler(int irq, void *data)
                }
                if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) {
-                        int i;
+                        dump_mmu_fault(gpu);
-                        dev_err_ratelimited(gpu->dev,
-                                "MMU fault status 0x%08x\n",
-                                gpu_read(gpu, VIVS_MMUv2_STATUS));
-                        for (i = 0; i < 4; i++) {
-                                dev_err_ratelimited(gpu->dev,
-                                        "MMU %d fault addr 0x%08x\n",
-                                        i, gpu_read(gpu,
-                                        VIVS_MMUv2_EXCEPTION_ADDR(i)));
-                        }
                        intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION;
                }
@@ -1484,7 +1437,6 @@ static irqreturn_t irq_handler(int irq, void *data)
                                continue;
                        gpu->event[event].fence = NULL;
-                        dma_fence_signal(fence);
                        /*
                         * Events can be processed out of order.  Eg,
@@ -1497,13 +1449,11 @@ static irqreturn_t irq_handler(int irq, void *data)
                         */
                        if (fence_after(fence->seqno, gpu->completed_fence))
                                gpu->completed_fence = fence->seqno;
+                        dma_fence_signal(fence);
                        event_free(gpu, event);
                }
-                /* Retire the buffer objects in a work */
-                queue_work(gpu->wq, &gpu->retire_work);
                ret = IRQ_HANDLED;
        }
@@ -1514,6 +1464,12 @@ static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
 {
        int ret;
+        if (gpu->clk_reg) {
+                ret = clk_prepare_enable(gpu->clk_reg);
+                if (ret)
+                        return ret;
+        }
        if (gpu->clk_bus) {
                ret = clk_prepare_enable(gpu->clk_bus);
                if (ret)
@@ -1552,6 +1508,8 @@ static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
                clk_disable_unprepare(gpu->clk_core);
        if (gpu->clk_bus)
                clk_disable_unprepare(gpu->clk_bus);
+        if (gpu->clk_reg)
+                clk_disable_unprepare(gpu->clk_reg);
        return 0;
 }
@@ -1675,41 +1633,49 @@ static int etnaviv_gpu_bind(struct device *dev, struct device *master,
        gpu->wq = alloc_ordered_workqueue(dev_name(dev), 0);
        if (!gpu->wq) {
-                if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
+                ret = -ENOMEM;
-                        thermal_cooling_device_unregister(gpu->cooling);
+                goto out_thermal;
-                return -ENOMEM;
        }
+        ret = etnaviv_sched_init(gpu);
+        if (ret)
+                goto out_workqueue;
 #ifdef CONFIG_PM
        ret = pm_runtime_get_sync(gpu->dev);
 #else
        ret = etnaviv_gpu_clk_enable(gpu);
 #endif
-        if (ret < 0) {
+        if (ret < 0)
-                destroy_workqueue(gpu->wq);
+                goto out_sched;
-                if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
-                        thermal_cooling_device_unregister(gpu->cooling);
-                return ret;
-        }
        gpu->drm = drm;
        gpu->fence_context = dma_fence_context_alloc(1);
+        idr_init(&gpu->fence_idr);
        spin_lock_init(&gpu->fence_spinlock);
-        INIT_LIST_HEAD(&gpu->active_submit_list);
-        INIT_WORK(&gpu->retire_work, retire_worker);
        INIT_WORK(&gpu->sync_point_work, sync_point_worker);
-        INIT_WORK(&gpu->recover_work, recover_worker);
        init_waitqueue_head(&gpu->fence_event);
-        timer_setup(&gpu->hangcheck_timer, hangcheck_handler, TIMER_DEFERRABLE);
        priv->gpu[priv->num_gpus++] = gpu;
        pm_runtime_mark_last_busy(gpu->dev);
        pm_runtime_put_autosuspend(gpu->dev);
        return 0;
+out_sched:
+        etnaviv_sched_fini(gpu);
+out_workqueue:
+        destroy_workqueue(gpu->wq);
+out_thermal:
+        if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
+                thermal_cooling_device_unregister(gpu->cooling);
+        return ret;
 }
 static void etnaviv_gpu_unbind(struct device *dev, struct device *master,
@@ -1719,11 +1685,11 @@ static void etnaviv_gpu_unbind(struct device *dev, struct device *master,
        DBG("%s", dev_name(gpu->dev));
-        hangcheck_disable(gpu);
        flush_workqueue(gpu->wq);
        destroy_workqueue(gpu->wq);
+        etnaviv_sched_fini(gpu);
 #ifdef CONFIG_PM
        pm_runtime_get_sync(gpu->dev);
        pm_runtime_put_sync_suspend(gpu->dev);
@@ -1745,6 +1711,7 @@ static void etnaviv_gpu_unbind(struct device *dev, struct device *master,
        }
        gpu->drm = NULL;
+        idr_destroy(&gpu->fence_idr);
        if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
                thermal_cooling_device_unregister(gpu->cooling);
@@ -1762,6 +1729,7 @@ static const struct of_device_id etnaviv_gpu_match[] = {
        },
        { /* sentinel */ }
 };
+MODULE_DEVICE_TABLE(of, etnaviv_gpu_match);
 static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
 {
@@ -1775,6 +1743,7 @@ static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
        gpu->dev = &pdev->dev;
        mutex_init(&gpu->lock);
+        mutex_init(&gpu->fence_idr_lock);
        /* Map registers: */
        gpu->mmio = etnaviv_ioremap(pdev, NULL, dev_name(gpu->dev));
@@ -1796,6 +1765,11 @@ static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
        }
        /* Get Clocks: */
+        gpu->clk_reg = devm_clk_get(&pdev->dev, "reg");
+        DBG("clk_reg: %p", gpu->clk_reg);
+        if (IS_ERR(gpu->clk_reg))
+                gpu->clk_reg = NULL;
        gpu->clk_bus = devm_clk_get(&pdev->dev, "bus");
        DBG("clk_bus: %p", gpu->clk_bus);
        if (IS_ERR(gpu->clk_bus))
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.h b/drivers/gpu/drm/etnaviv/etnaviv_gpu.h
index 7623905210dc..3c3005501846 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.h
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.h
@@ -38,21 +38,17 @@ struct etnaviv_chip_identity {
        /* Supported minor feature fields. */
        u32 minor_features0;
-        /* Supported minor feature 1 fields. */
        u32 minor_features1;
-        /* Supported minor feature 2 fields. */
        u32 minor_features2;
-        /* Supported minor feature 3 fields. */
        u32 minor_features3;
-        /* Supported minor feature 4 fields. */
        u32 minor_features4;
-        /* Supported minor feature 5 fields. */
        u32 minor_features5;
+        u32 minor_features6;
+        u32 minor_features7;
+        u32 minor_features8;
+        u32 minor_features9;
+        u32 minor_features10;
+        u32 minor_features11;
        /* Number of streams supported. */
        u32 stream_count;
@@ -88,6 +84,12 @@ struct etnaviv_chip_identity {
        u8 varyings_count;
 };
+enum etnaviv_sec_mode {
+        ETNA_SEC_NONE = 0,
+        ETNA_SEC_KERNEL,
+        ETNA_SEC_TZ
+};
 struct etnaviv_event {
        struct dma_fence *fence;
        struct etnaviv_gem_submit *submit;
@@ -106,8 +108,10 @@ struct etnaviv_gpu {
        struct device *dev;
        struct mutex lock;
        struct etnaviv_chip_identity identity;
+        enum etnaviv_sec_mode sec_mode;
        struct etnaviv_file_private *lastctx;
        struct workqueue_struct *wq;
+        struct drm_gpu_scheduler sched;
        /* 'ring'-buffer: */
        struct etnaviv_cmdbuf buffer;
@@ -122,23 +126,18 @@ struct etnaviv_gpu {
        struct completion event_free;
        spinlock_t event_spinlock;
-        /* list of currently in-flight command buffers */
-        struct list_head active_submit_list;
        u32 idle_mask;
        /* Fencing support */
+        struct mutex fence_idr_lock;
+        struct idr fence_idr;
        u32 next_fence;
        u32 active_fence;
        u32 completed_fence;
-        u32 retired_fence;
        wait_queue_head_t fence_event;
        u64 fence_context;
        spinlock_t fence_spinlock;
-        /* worker for handling active-list retiring: */
-        struct work_struct retire_work;
        /* worker for handling 'sync' points: */
        struct work_struct sync_point_work;
        int sync_point_event;
@@ -151,16 +150,10 @@ struct etnaviv_gpu {
        /* Power Control: */
        struct clk *clk_bus;
+        struct clk *clk_reg;
        struct clk *clk_core;
        struct clk *clk_shader;
-        /* Hang Detction: */
-#define DRM_ETNAVIV_HANGCHECK_PERIOD 500 /* in ms */
-#define DRM_ETNAVIV_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_ETNAVIV_HANGCHECK_PERIOD)
-        struct timer_list hangcheck_timer;
-        u32 hangcheck_fence;
-        u32 hangcheck_dma_addr;
-        struct work_struct recover_work;
        unsigned int freq_scale;
        unsigned long base_rate_core;
        unsigned long base_rate_shader;
@@ -181,29 +174,22 @@ static inline bool fence_completed(struct etnaviv_gpu *gpu, u32 fence)
        return fence_after_eq(gpu->completed_fence, fence);
 }
-static inline bool fence_retired(struct etnaviv_gpu *gpu, u32 fence)
-{
-        return fence_after_eq(gpu->retired_fence, fence);
-}
 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value);
 int etnaviv_gpu_init(struct etnaviv_gpu *gpu);
+bool etnaviv_fill_identity_from_hwdb(struct etnaviv_gpu *gpu);
 #ifdef CONFIG_DEBUG_FS
 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m);
 #endif
-int etnaviv_gpu_fence_sync_obj(struct etnaviv_gem_object *etnaviv_obj,
+void etnaviv_gpu_recover_hang(struct etnaviv_gpu *gpu);
-        unsigned int context, bool exclusive, bool implicit);
 void etnaviv_gpu_retire(struct etnaviv_gpu *gpu);
 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
        u32 fence, struct timespec *timeout);
 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
        struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout);
-int etnaviv_gpu_submit(struct etnaviv_gpu *gpu,
+struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit);
-        struct etnaviv_gem_submit *submit);
 int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu);
 void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu);
 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms);
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c b/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
new file mode 100644
index 000000000000..ea08bb38caaf
--- /dev/null
+++ b/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2018 Etnaviv Project
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include "etnaviv_gpu.h"
+static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
+        {
+                .model = 0x7000,
+                .revision = 0x6214,
+                .stream_count = 16,
+                .register_max = 64,
+                .thread_count = 1024,
+                .shader_core_count = 4,
+                .vertex_cache_size = 16,
+                .vertex_output_buffer_size = 1024,
+                .pixel_pipes = 2,
+                .instruction_count = 512,
+                .num_constants = 320,
+                .buffer_size = 0,
+                .varyings_count = 16,
+                .features = 0xe0287cad,
+                .minor_features0 = 0xc1799eff,
+                .minor_features1 = 0xfefbfad9,
+                .minor_features2 = 0xeb9d4fbf,
+                .minor_features3 = 0xedfffced,
+                .minor_features4 = 0xdb0dafc7,
+                .minor_features5 = 0xbb5ac333,
+                .minor_features6 = 0xfc8ee200,
+                .minor_features7 = 0x03fbfa6f,
+                .minor_features8 = 0x00ef0ef0,
+                .minor_features9 = 0x0edbf03c,
+                .minor_features10 = 0x90044250,
+                .minor_features11 = 0x00000024,
+        },
+};
+bool etnaviv_fill_identity_from_hwdb(struct etnaviv_gpu *gpu)
+{
+        struct etnaviv_chip_identity *ident = &gpu->identity;
+        int i;
+        for (i = 0; i < ARRAY_SIZE(etnaviv_chip_identities); i++) {
+                if (etnaviv_chip_identities[i].model == ident->model &&
+                    etnaviv_chip_identities[i].revision == ident->revision) {
+                        memcpy(ident, &etnaviv_chip_identities[i],
+                               sizeof(*ident));
+                        return true;
+                }
+        }
+        return false;
+}
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_iommu.c b/drivers/gpu/drm/etnaviv/etnaviv_iommu.c
index 7a8c94731748..4b9b11ca6f03 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_iommu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_iommu.c
@@ -158,7 +158,7 @@ void etnaviv_iommuv1_restore(struct etnaviv_gpu *gpu)
        gpu_write(gpu, VIVS_MC_MMU_RA_PAGE_TABLE, pgtable);
 }
-const struct etnaviv_iommu_domain_ops etnaviv_iommuv1_ops = {
+static const struct etnaviv_iommu_domain_ops etnaviv_iommuv1_ops = {
        .free = etnaviv_iommuv1_domain_free,
        .map = etnaviv_iommuv1_map,
        .unmap = etnaviv_iommuv1_unmap,
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c b/drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c
index 1e956e266aa3..9752dbd5d28b 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c
@@ -40,6 +40,9 @@
 struct etnaviv_iommuv2_domain {
        struct etnaviv_iommu_domain base;
+        /* P(age) T(able) A(rray) */
+        u64 *pta_cpu;
+        dma_addr_t pta_dma;
        /* M(aster) TLB aka first level pagetable */
        u32 *mtlb_cpu;
        dma_addr_t mtlb_dma;
@@ -114,6 +117,15 @@ static int etnaviv_iommuv2_init(struct etnaviv_iommuv2_domain *etnaviv_domain)
        for (i = 0; i < SZ_4K / 4; i++)
                *p++ = 0xdead55aa;
+        etnaviv_domain->pta_cpu = dma_alloc_coherent(etnaviv_domain->base.dev,
+                                                     SZ_4K,
+                                                     &etnaviv_domain->pta_dma,
+                                                     GFP_KERNEL);
+        if (!etnaviv_domain->pta_cpu) {
+                ret = -ENOMEM;
+                goto fail_mem;
+        }
        etnaviv_domain->mtlb_cpu = dma_alloc_coherent(etnaviv_domain->base.dev,
                                                  SZ_4K,
                                                  &etnaviv_domain->mtlb_dma,
@@ -150,6 +162,11 @@ fail_mem:
                                  etnaviv_domain->base.bad_page_cpu,
                                  etnaviv_domain->base.bad_page_dma);
+        if (etnaviv_domain->pta_cpu)
+                dma_free_coherent(etnaviv_domain->base.dev, SZ_4K,
+                                  etnaviv_domain->pta_cpu,
+                                  etnaviv_domain->pta_dma);
        if (etnaviv_domain->mtlb_cpu)
                dma_free_coherent(etnaviv_domain->base.dev, SZ_4K,
                                  etnaviv_domain->mtlb_cpu,
@@ -176,6 +193,10 @@ static void etnaviv_iommuv2_domain_free(struct etnaviv_iommu_domain *domain)
                          etnaviv_domain->base.bad_page_dma);
        dma_free_coherent(etnaviv_domain->base.dev, SZ_4K,
+                          etnaviv_domain->pta_cpu,
+                          etnaviv_domain->pta_dma);
+        dma_free_coherent(etnaviv_domain->base.dev, SZ_4K,
                          etnaviv_domain->mtlb_cpu,
                          etnaviv_domain->mtlb_dma);
@@ -216,7 +237,7 @@ static void etnaviv_iommuv2_dump(struct etnaviv_iommu_domain *domain, void *buf)
                        memcpy(buf, etnaviv_domain->stlb_cpu[i], SZ_4K);
 }
-void etnaviv_iommuv2_restore(struct etnaviv_gpu *gpu)
+static void etnaviv_iommuv2_restore_nonsec(struct etnaviv_gpu *gpu)
 {
        struct etnaviv_iommuv2_domain *etnaviv_domain =
                        to_etnaviv_domain(gpu->mmu->domain);
@@ -236,7 +257,60 @@ void etnaviv_iommuv2_restore(struct etnaviv_gpu *gpu)
        gpu_write(gpu, VIVS_MMUv2_CONTROL, VIVS_MMUv2_CONTROL_ENABLE);
 }
-const struct etnaviv_iommu_domain_ops etnaviv_iommuv2_ops = {
+static void etnaviv_iommuv2_restore_sec(struct etnaviv_gpu *gpu)
+{
+        struct etnaviv_iommuv2_domain *etnaviv_domain =
+                                to_etnaviv_domain(gpu->mmu->domain);
+        u16 prefetch;
+        /* If the MMU is already enabled the state is still there. */
+        if (gpu_read(gpu, VIVS_MMUv2_SEC_CONTROL) & VIVS_MMUv2_SEC_CONTROL_ENABLE)
+                return;
+        gpu_write(gpu, VIVS_MMUv2_PTA_ADDRESS_LOW,
+                  lower_32_bits(etnaviv_domain->pta_dma));
+        gpu_write(gpu, VIVS_MMUv2_PTA_ADDRESS_HIGH,
+                  upper_32_bits(etnaviv_domain->pta_dma));
+        gpu_write(gpu, VIVS_MMUv2_PTA_CONTROL, VIVS_MMUv2_PTA_CONTROL_ENABLE);
+        gpu_write(gpu, VIVS_MMUv2_NONSEC_SAFE_ADDR_LOW,
+                  lower_32_bits(etnaviv_domain->base.bad_page_dma));
+        gpu_write(gpu, VIVS_MMUv2_SEC_SAFE_ADDR_LOW,
+                  lower_32_bits(etnaviv_domain->base.bad_page_dma));
+        gpu_write(gpu, VIVS_MMUv2_SAFE_ADDRESS_CONFIG,
+                  VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH(
+                  upper_32_bits(etnaviv_domain->base.bad_page_dma)) |
+                  VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH(
+                  upper_32_bits(etnaviv_domain->base.bad_page_dma)));
+        etnaviv_domain->pta_cpu[0] = etnaviv_domain->mtlb_dma |
+                                     VIVS_MMUv2_CONFIGURATION_MODE_MODE4_K;
+        /* trigger a PTA load through the FE */
+        prefetch = etnaviv_buffer_config_pta(gpu);
+        etnaviv_gpu_start_fe(gpu, (u32)etnaviv_cmdbuf_get_pa(&gpu->buffer),
+                             prefetch);
+        etnaviv_gpu_wait_idle(gpu, 100);
+        gpu_write(gpu, VIVS_MMUv2_SEC_CONTROL, VIVS_MMUv2_SEC_CONTROL_ENABLE);
+}
+void etnaviv_iommuv2_restore(struct etnaviv_gpu *gpu)
+{
+        switch (gpu->sec_mode) {
+        case ETNA_SEC_NONE:
+                etnaviv_iommuv2_restore_nonsec(gpu);
+                break;
+        case ETNA_SEC_KERNEL:
+                etnaviv_iommuv2_restore_sec(gpu);
+                break;
+        default:
+                WARN(1, "unhandled GPU security mode\n");
+                break;
+        }
+}
+static const struct etnaviv_iommu_domain_ops etnaviv_iommuv2_ops = {
        .free = etnaviv_iommuv2_domain_free,
        .map = etnaviv_iommuv2_map,
        .unmap = etnaviv_iommuv2_unmap,
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_mmu.c b/drivers/gpu/drm/etnaviv/etnaviv_mmu.c
index d113fe06e6b5..49e049713a52 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_mmu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_mmu.c
@@ -29,7 +29,7 @@ static void etnaviv_domain_unmap(struct etnaviv_iommu_domain *domain,
        size_t pgsize = SZ_4K;
        if (!IS_ALIGNED(iova | size, pgsize)) {
-                pr_err("unaligned: iova 0x%lx size 0x%zx min_pagesz 0x%x\n",
+                pr_err("unaligned: iova 0x%lx size 0x%zx min_pagesz 0x%zx\n",
                       iova, size, pgsize);
                return;
        }
@@ -54,7 +54,7 @@ static int etnaviv_domain_map(struct etnaviv_iommu_domain *domain,
        int ret = 0;
        if (!IS_ALIGNED(iova | paddr | size, pgsize)) {
-                pr_err("unaligned: iova 0x%lx pa %pa size 0x%zx min_pagesz 0x%x\n",
+                pr_err("unaligned: iova 0x%lx pa %pa size 0x%zx min_pagesz 0x%zx\n",
                       iova, &paddr, size, pgsize);
                return -EINVAL;
        }
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_sched.c b/drivers/gpu/drm/etnaviv/etnaviv_sched.c
new file mode 100644
index 000000000000..6cf0775dbcd7
--- /dev/null
+++ b/drivers/gpu/drm/etnaviv/etnaviv_sched.c
@@ -0,0 +1,170 @@
+/*
+ * Copyright (C) 2017 Etnaviv Project
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/kthread.h>
+#include "etnaviv_drv.h"
+#include "etnaviv_dump.h"
+#include "etnaviv_gem.h"
+#include "etnaviv_gpu.h"
+#include "etnaviv_sched.h"
+static int etnaviv_job_hang_limit = 0;
+module_param_named(job_hang_limit, etnaviv_job_hang_limit, int , 0444);
+static int etnaviv_hw_jobs_limit = 4;
+module_param_named(hw_job_limit, etnaviv_hw_jobs_limit, int , 0444);
+static struct dma_fence *
+etnaviv_sched_dependency(struct drm_sched_job *sched_job,
+                         struct drm_sched_entity *entity)
+{
+        struct etnaviv_gem_submit *submit = to_etnaviv_submit(sched_job);
+        struct dma_fence *fence;
+        int i;
+        if (unlikely(submit->in_fence)) {
+                fence = submit->in_fence;
+                submit->in_fence = NULL;
+                if (!dma_fence_is_signaled(fence))
+                        return fence;
+                dma_fence_put(fence);
+        }
+        for (i = 0; i < submit->nr_bos; i++) {
+                struct etnaviv_gem_submit_bo *bo = &submit->bos[i];
+                int j;
+                if (bo->excl) {
+                        fence = bo->excl;
+                        bo->excl = NULL;
+                        if (!dma_fence_is_signaled(fence))
+                                return fence;
+                        dma_fence_put(fence);
+                }
+                for (j = 0; j < bo->nr_shared; j++) {
+                        if (!bo->shared[j])
+                                continue;
+                        fence = bo->shared[j];
+                        bo->shared[j] = NULL;
+                        if (!dma_fence_is_signaled(fence))
+                                return fence;
+                        dma_fence_put(fence);
+                }
+                kfree(bo->shared);
+                bo->nr_shared = 0;
+                bo->shared = NULL;
+        }
+        return NULL;
+}
+static struct dma_fence *etnaviv_sched_run_job(struct drm_sched_job *sched_job)
+{
+        struct etnaviv_gem_submit *submit = to_etnaviv_submit(sched_job);
+        struct dma_fence *fence = NULL;
+        if (likely(!sched_job->s_fence->finished.error))
+                fence = etnaviv_gpu_submit(submit);
+        else
+                dev_dbg(submit->gpu->dev, "skipping bad job\n");
+        return fence;
+}
+static void etnaviv_sched_timedout_job(struct drm_sched_job *sched_job)
+{
+        struct etnaviv_gem_submit *submit = to_etnaviv_submit(sched_job);
+        struct etnaviv_gpu *gpu = submit->gpu;
+        /* block scheduler */
+        kthread_park(gpu->sched.thread);
+        drm_sched_hw_job_reset(&gpu->sched, sched_job);
+        /* get the GPU back into the init state */
+        etnaviv_core_dump(gpu);
+        etnaviv_gpu_recover_hang(gpu);
+        /* restart scheduler after GPU is usable again */
+        drm_sched_job_recovery(&gpu->sched);
+        kthread_unpark(gpu->sched.thread);
+}
+static void etnaviv_sched_free_job(struct drm_sched_job *sched_job)
+{
+        struct etnaviv_gem_submit *submit = to_etnaviv_submit(sched_job);
+        etnaviv_submit_put(submit);
+}
+static const struct drm_sched_backend_ops etnaviv_sched_ops = {
+        .dependency = etnaviv_sched_dependency,
+        .run_job = etnaviv_sched_run_job,
+        .timedout_job = etnaviv_sched_timedout_job,
+        .free_job = etnaviv_sched_free_job,
+};
+int etnaviv_sched_push_job(struct drm_sched_entity *sched_entity,
+                           struct etnaviv_gem_submit *submit)
+{
+        int ret;
+        ret = drm_sched_job_init(&submit->sched_job, &submit->gpu->sched,
+                                 sched_entity, submit->cmdbuf.ctx);
+        if (ret)
+                return ret;
+        submit->out_fence = dma_fence_get(&submit->sched_job.s_fence->finished);
+        mutex_lock(&submit->gpu->fence_idr_lock);
+        submit->out_fence_id = idr_alloc_cyclic(&submit->gpu->fence_idr,
+                                                submit->out_fence, 0,
+                                                INT_MAX, GFP_KERNEL);
+        mutex_unlock(&submit->gpu->fence_idr_lock);
+        if (submit->out_fence_id < 0)
+                return -ENOMEM;
+        /* the scheduler holds on to the job now */
+        kref_get(&submit->refcount);
+        drm_sched_entity_push_job(&submit->sched_job, sched_entity);
+        return 0;
+}
+int etnaviv_sched_init(struct etnaviv_gpu *gpu)
+{
+        int ret;
+        ret = drm_sched_init(&gpu->sched, &etnaviv_sched_ops,
+                             etnaviv_hw_jobs_limit, etnaviv_job_hang_limit,
+                             msecs_to_jiffies(500), dev_name(gpu->dev));
+        if (ret)
+                return ret;
+        return 0;
+}
+void etnaviv_sched_fini(struct etnaviv_gpu *gpu)
+{
+        drm_sched_fini(&gpu->sched);
+}
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_sched.h b/drivers/gpu/drm/etnaviv/etnaviv_sched.h
new file mode 100644
index 000000000000..097635fa78ae
--- /dev/null
+++ b/drivers/gpu/drm/etnaviv/etnaviv_sched.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2017 Etnaviv Project
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __ETNAVIV_SCHED_H__
+#define __ETNAVIV_SCHED_H__
+#include <drm/gpu_scheduler.h>
+struct etnaviv_gpu;
+static inline
+struct etnaviv_gem_submit *to_etnaviv_submit(struct drm_sched_job *sched_job)
+{
+        return container_of(sched_job, struct etnaviv_gem_submit, sched_job);
+}
+int etnaviv_sched_init(struct etnaviv_gpu *gpu);
+void etnaviv_sched_fini(struct etnaviv_gpu *gpu);
+int etnaviv_sched_push_job(struct drm_sched_entity *sched_entity,
+                           struct etnaviv_gem_submit *submit);
+#endif /* __ETNAVIV_SCHED_H__ */
diff --git a/drivers/gpu/drm/etnaviv/state.xml.h b/drivers/gpu/drm/etnaviv/state.xml.h
index c27c1484cfa9..421cb7cc0053 100644
--- a/drivers/gpu/drm/etnaviv/state.xml.h
+++ b/drivers/gpu/drm/etnaviv/state.xml.h
@@ -1,4 +1,3 @@
-/* SPDX-License-Identifier: GPL-2.0 */
 #ifndef STATE_XML
 #define STATE_XML
@@ -9,14 +8,40 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
 git clone git://0x04.net/rules-ng-ng
 The rules-ng-ng source files this header was generated from are:
- state.xml    (  18882 bytes, from 2015-03-25 11:42:32)
+- state.xml     (  26087 bytes, from 2017-12-18 16:51:59)
- common.xml   (  18437 bytes, from 2015-03-25 11:27:41)
+- common.xml    (  35468 bytes, from 2018-01-22 13:48:54)
- state_hi.xml (  23420 bytes, from 2015-03-25 11:47:21)
+- common_3d.xml (  14615 bytes, from 2017-12-18 16:51:59)
- state_2d.xml (  51549 bytes, from 2015-03-25 11:25:06)
+- state_hi.xml  (  30232 bytes, from 2018-02-15 15:48:01)
- state_3d.xml (  54600 bytes, from 2015-03-25 11:25:19)
+- copyright.xml (   1597 bytes, from 2016-12-08 16:37:56)
- state_vg.xml (   5973 bytes, from 2015-03-25 11:26:01)
+- state_2d.xml  (  51552 bytes, from 2016-12-08 16:37:56)
+- state_3d.xml  (  79992 bytes, from 2017-12-18 16:51:59)
-Copyright (C) 2015
+- state_blt.xml (  13405 bytes, from 2017-12-18 16:51:59)
+- state_vg.xml  (   5975 bytes, from 2016-12-08 16:37:56)
+Copyright (C) 2012-2017 by the following authors:
+- Wladimir J. van der Laan <laanwj@gmail.com>
+- Christian Gmeiner <christian.gmeiner@gmail.com>
+- Lucas Stach <l.stach@pengutronix.de>
+- Russell King <rmk@arm.linux.org.uk>
+Permission is hereby granted, free of charge, to any person obtaining a
+copy of this software and associated documentation files (the "Software"),
+to deal in the Software without restriction, including without limitation
+the rights to use, copy, modify, merge, publish, distribute, sub license,
+and/or sell copies of the Software, and to permit persons to whom the
+Software is furnished to do so, subject to the following conditions:
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial portions
+of the Software.
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+DEALINGS IN THE SOFTWARE.
 */
@@ -24,9 +49,25 @@ Copyright (C) 2015
 #define VARYING_COMPONENT_USE_USED                              0x00000001
 #define VARYING_COMPONENT_USE_POINTCOORD_X                      0x00000002
 #define VARYING_COMPONENT_USE_POINTCOORD_Y                      0x00000003
+#define FE_DATA_TYPE_BYTE                                       0x00000000
+#define FE_DATA_TYPE_UNSIGNED_BYTE                              0x00000001
+#define FE_DATA_TYPE_SHORT                                      0x00000002
+#define FE_DATA_TYPE_UNSIGNED_SHORT                             0x00000003
+#define FE_DATA_TYPE_INT                                        0x00000004
+#define FE_DATA_TYPE_UNSIGNED_INT                               0x00000005
+#define FE_DATA_TYPE_FLOAT                                      0x00000008
+#define FE_DATA_TYPE_HALF_FLOAT                                 0x00000009
+#define FE_DATA_TYPE_FIXED                                      0x0000000b
+#define FE_DATA_TYPE_INT_10_10_10_2                             0x0000000c
+#define FE_DATA_TYPE_UNSIGNED_INT_10_10_10_2                    0x0000000d
+#define FE_DATA_TYPE_BYTE_I                                     0x0000000e
+#define FE_DATA_TYPE_SHORT_I                                    0x0000000f
 #define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__MASK            0x000000ff
 #define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__SHIFT           0
 #define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE(x)               (((x) << FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__SHIFT) & FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__MASK)
+#define FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__MASK           0x00ff0000
+#define FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__SHIFT          16
+#define FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR(x)              (((x) << FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__SHIFT) & FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__MASK)
 #define VIVS_FE                                                 0x00000000
 #define VIVS_FE_VERTEX_ELEMENT_CONFIG(i0)                      (0x00000600 + 0x4*(i0))
@@ -34,17 +75,7 @@ Copyright (C) 2015
 #define VIVS_FE_VERTEX_ELEMENT_CONFIG__LEN                      0x00000010
 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__MASK                0x0000000f
 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__SHIFT               0
-#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_BYTE                 0x00000000
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE(x)                   (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__MASK)
-#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_UNSIGNED_BYTE        0x00000001
-#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_SHORT                0x00000002
-#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_UNSIGNED_SHORT       0x00000003
-#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_INT                  0x00000004
-#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_UNSIGNED_INT         0x00000005
-#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_FLOAT                0x00000008
-#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_HALF_FLOAT           0x00000009
-#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_FIXED                0x0000000b
-#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_INT_10_10_10_2       0x0000000c
-#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_UNSIGNED_INT_10_10_10_2      0x0000000d
 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__MASK              0x00000030
 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT             4
 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN(x)                 (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__MASK)
@@ -76,6 +107,7 @@ Copyright (C) 2015
 #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_CHAR         0x00000000
 #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_SHORT        0x00000001
 #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_INT          0x00000002
+#define VIVS_FE_INDEX_STREAM_CONTROL_PRIMITIVE_RESTART          0x00000100
 #define VIVS_FE_VERTEX_STREAM_BASE_ADDR                         0x0000064c
@@ -151,6 +183,8 @@ Copyright (C) 2015
 #define VIVS_FE_AUTO_FLUSH                                      0x00000670
+#define VIVS_FE_PRIMITIVE_RESTART_INDEX                         0x00000674
 #define VIVS_FE_UNK00678                                        0x00000678
 #define VIVS_FE_UNK0067C                                        0x0000067c
@@ -163,17 +197,40 @@ Copyright (C) 2015
 #define VIVS_FE_VERTEX_STREAMS_CONTROL(i0)                     (0x000006a0 + 0x4*(i0))
-#define VIVS_FE_UNK00700(i0)                                   (0x00000700 + 0x4*(i0))
+#define VIVS_FE_GENERIC_ATTRIB(i0)                             (0x00000000 + 0x4*(i0))
-#define VIVS_FE_UNK00700__ESIZE                                 0x00000004
+#define VIVS_FE_GENERIC_ATTRIB__ESIZE                           0x00000004
-#define VIVS_FE_UNK00700__LEN                                   0x00000010
+#define VIVS_FE_GENERIC_ATTRIB__LEN                             0x00000010
+#define VIVS_FE_GENERIC_ATTRIB_UNK006C0(i0)                    (0x000006c0 + 0x4*(i0))
+#define VIVS_FE_GENERIC_ATTRIB_UNK00700(i0)                    (0x00000700 + 0x4*(i0))
+#define VIVS_FE_GENERIC_ATTRIB_UNK00740(i0)                    (0x00000740 + 0x4*(i0))
+#define VIVS_FE_GENERIC_ATTRIB_SCALE(i0)                       (0x00000780 + 0x4*(i0))
+#define VIVS_FE_HALTI5_UNK007C4                                 0x000007c4
+#define VIVS_FE_HALTI5_UNK007D0(i0)                            (0x000007d0 + 0x4*(i0))
+#define VIVS_FE_HALTI5_UNK007D0__ESIZE                          0x00000004
+#define VIVS_FE_HALTI5_UNK007D0__LEN                            0x00000002
+#define VIVS_FE_HALTI5_UNK007D8                                 0x000007d8
+#define VIVS_FE_DESC_START                                      0x000007dc
+#define VIVS_FE_DESC_END                                        0x000007e0
+#define VIVS_FE_DESC_AVAIL                                      0x000007e4
+#define VIVS_FE_DESC_AVAIL_COUNT__MASK                          0x0000007f
+#define VIVS_FE_DESC_AVAIL_COUNT__SHIFT                         0
+#define VIVS_FE_DESC_AVAIL_COUNT(x)                             (((x) << VIVS_FE_DESC_AVAIL_COUNT__SHIFT) & VIVS_FE_DESC_AVAIL_COUNT__MASK)
+#define VIVS_FE_FENCE_WAIT_DATA_LOW                             0x000007e8
-#define VIVS_FE_UNK00740(i0)                                   (0x00000740 + 0x4*(i0))
+#define VIVS_FE_FENCE_WAIT_DATA_HIGH                            0x000007f4
-#define VIVS_FE_UNK00740__ESIZE                                 0x00000004
-#define VIVS_FE_UNK00740__LEN                                   0x00000010
-#define VIVS_FE_UNK00780(i0)                                   (0x00000780 + 0x4*(i0))
+#define VIVS_FE_ROBUSTNESS_UNK007F8                             0x000007f8
-#define VIVS_FE_UNK00780__ESIZE                                 0x00000004
-#define VIVS_FE_UNK00780__LEN                                   0x00000010
 #define VIVS_GL                                                 0x00000000
@@ -188,6 +245,7 @@ Copyright (C) 2015
 #define VIVS_GL_EVENT_EVENT_ID(x)                               (((x) << VIVS_GL_EVENT_EVENT_ID__SHIFT) & VIVS_GL_EVENT_EVENT_ID__MASK)
 #define VIVS_GL_EVENT_FROM_FE                                   0x00000020
 #define VIVS_GL_EVENT_FROM_PE                                   0x00000040
+#define VIVS_GL_EVENT_FROM_BLT                                  0x00000080
 #define VIVS_GL_EVENT_SOURCE__MASK                              0x00001f00
 #define VIVS_GL_EVENT_SOURCE__SHIFT                             8
 #define VIVS_GL_EVENT_SOURCE(x)                                 (((x) << VIVS_GL_EVENT_SOURCE__SHIFT) & VIVS_GL_EVENT_SOURCE__MASK)
@@ -199,6 +257,9 @@ Copyright (C) 2015
 #define VIVS_GL_SEMAPHORE_TOKEN_TO__MASK                        0x00001f00
 #define VIVS_GL_SEMAPHORE_TOKEN_TO__SHIFT                       8
 #define VIVS_GL_SEMAPHORE_TOKEN_TO(x)                           (((x) << VIVS_GL_SEMAPHORE_TOKEN_TO__SHIFT) & VIVS_GL_SEMAPHORE_TOKEN_TO__MASK)
+#define VIVS_GL_SEMAPHORE_TOKEN_UNK28__MASK                     0x30000000
+#define VIVS_GL_SEMAPHORE_TOKEN_UNK28__SHIFT                    28
+#define VIVS_GL_SEMAPHORE_TOKEN_UNK28(x)                        (((x) << VIVS_GL_SEMAPHORE_TOKEN_UNK28__SHIFT) & VIVS_GL_SEMAPHORE_TOKEN_UNK28__MASK)
 #define VIVS_GL_FLUSH_CACHE                                     0x0000380c
 #define VIVS_GL_FLUSH_CACHE_DEPTH                               0x00000001
@@ -208,6 +269,10 @@ Copyright (C) 2015
 #define VIVS_GL_FLUSH_CACHE_TEXTUREVS                           0x00000010
 #define VIVS_GL_FLUSH_CACHE_SHADER_L1                           0x00000020
 #define VIVS_GL_FLUSH_CACHE_SHADER_L2                           0x00000040
+#define VIVS_GL_FLUSH_CACHE_UNK10                               0x00000400
+#define VIVS_GL_FLUSH_CACHE_UNK11                               0x00000800
+#define VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK12                    0x00001000
+#define VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK13                    0x00002000
 #define VIVS_GL_FLUSH_MMU                                       0x00003810
 #define VIVS_GL_FLUSH_MMU_FLUSH_FEMMU                           0x00000001
@@ -244,30 +309,8 @@ Copyright (C) 2015
 #define VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM(x)                 (((x) << VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__SHIFT) & VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__MASK)
 #define VIVS_GL_VARYING_NUM_COMPONENTS                          0x00003820
-#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR0__MASK               0x00000007
-#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR0__SHIFT              0
+#define VIVS_GL_OCCLUSION_QUERY_ADDR                            0x00003824
-#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR0(x)                  (((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR0__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR0__MASK)
-#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR1__MASK               0x00000070
-#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR1__SHIFT              4
-#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR1(x)                  (((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR1__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR1__MASK)
-#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR2__MASK               0x00000700
-#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR2__SHIFT              8
-#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR2(x)                  (((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR2__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR2__MASK)
-#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR3__MASK               0x00007000
-#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR3__SHIFT              12
-#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR3(x)                  (((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR3__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR3__MASK)
-#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR4__MASK               0x00070000
-#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR4__SHIFT              16
-#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR4(x)                  (((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR4__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR4__MASK)
-#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR5__MASK               0x00700000
-#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR5__SHIFT              20
-#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR5(x)                  (((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR5__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR5__MASK)
-#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR6__MASK               0x07000000
-#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR6__SHIFT              24
-#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR6(x)                  (((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR6__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR6__MASK)
-#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR7__MASK               0x70000000
-#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR7__SHIFT              28
-#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR7(x)                  (((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR7__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR7__MASK)
 #define VIVS_GL_VARYING_COMPONENT_USE(i0)                      (0x00003828 + 0x4*(i0))
 #define VIVS_GL_VARYING_COMPONENT_USE__ESIZE                    0x00000004
@@ -321,6 +364,10 @@ Copyright (C) 2015
 #define VIVS_GL_VARYING_COMPONENT_USE_COMP15__SHIFT             30
 #define VIVS_GL_VARYING_COMPONENT_USE_COMP15(x)                 (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP15__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP15__MASK)
+#define VIVS_GL_UNK0382C                                        0x0000382c
+#define VIVS_GL_OCCLUSION_QUERY_CONTROL                         0x00003830
 #define VIVS_GL_UNK03834                                        0x00003834
 #define VIVS_GL_UNK03838                                        0x00003838
@@ -332,8 +379,58 @@ Copyright (C) 2015
 #define VIVS_GL_CONTEXT_POINTER                                 0x00003850
+#define VIVS_GL_UNK03854                                        0x00003854
+#define VIVS_GL_BUG_FIXES                                       0x00003860
+#define VIVS_GL_FENCE_OUT_ADDRESS                               0x00003868
+#define VIVS_GL_FENCE_OUT_DATA_LOW                              0x0000386c
+#define VIVS_GL_HALTI5_UNK03884                                 0x00003884
+#define VIVS_GL_HALTI5_SH_SPECIALS                              0x00003888
+#define VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__MASK           0x0000007f
+#define VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__SHIFT          0
+#define VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT(x)              (((x) << VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__MASK)
+#define VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__MASK           0x00007f00
+#define VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__SHIFT          8
+#define VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN(x)              (((x) << VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__MASK)
+#define VIVS_GL_HALTI5_SH_SPECIALS_UNK16__MASK                  0x007f0000
+#define VIVS_GL_HALTI5_SH_SPECIALS_UNK16__SHIFT                 16
+#define VIVS_GL_HALTI5_SH_SPECIALS_UNK16(x)                     (((x) << VIVS_GL_HALTI5_SH_SPECIALS_UNK16__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_UNK16__MASK)
+#define VIVS_GL_HALTI5_SH_SPECIALS_UNK24__MASK                  0xff000000
+#define VIVS_GL_HALTI5_SH_SPECIALS_UNK24__SHIFT                 24
+#define VIVS_GL_HALTI5_SH_SPECIALS_UNK24(x)                     (((x) << VIVS_GL_HALTI5_SH_SPECIALS_UNK24__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_UNK24__MASK)
+#define VIVS_GL_GS_UNK0388C                                     0x0000388c
+#define VIVS_GL_FENCE_OUT_DATA_HIGH                             0x00003898
+#define VIVS_GL_SHADER_INDEX                                    0x0000389c
+#define VIVS_GL_GS_UNK038A0(i0)                                (0x000038a0 + 0x4*(i0))
+#define VIVS_GL_GS_UNK038A0__ESIZE                              0x00000004
+#define VIVS_GL_GS_UNK038A0__LEN                                0x00000008
+#define VIVS_GL_HALTI5_UNK038C0(i0)                            (0x000038c0 + 0x4*(i0))
+#define VIVS_GL_HALTI5_UNK038C0__ESIZE                          0x00000004
+#define VIVS_GL_HALTI5_UNK038C0__LEN                            0x00000010
+#define VIVS_GL_SECURITY_UNK3900                                0x00003900
+#define VIVS_GL_SECURITY_UNK3904                                0x00003904
 #define VIVS_GL_UNK03A00                                        0x00003a00
+#define VIVS_GL_UNK03A04                                        0x00003a04
+#define VIVS_GL_UNK03A08                                        0x00003a08
+#define VIVS_GL_UNK03A0C                                        0x00003a0c
+#define VIVS_GL_UNK03A10                                        0x00003a10
 #define VIVS_GL_STALL_TOKEN                                     0x00003c00
 #define VIVS_GL_STALL_TOKEN_FROM__MASK                          0x0000001f
 #define VIVS_GL_STALL_TOKEN_FROM__SHIFT                         0
@@ -344,6 +441,59 @@ Copyright (C) 2015
 #define VIVS_GL_STALL_TOKEN_FLIP0                               0x40000000
 #define VIVS_GL_STALL_TOKEN_FLIP1                               0x80000000
+#define VIVS_NFE                                                0x00000000
+#define VIVS_NFE_VERTEX_STREAMS(i0)                            (0x00000000 + 0x4*(i0))
+#define VIVS_NFE_VERTEX_STREAMS__ESIZE                          0x00000004
+#define VIVS_NFE_VERTEX_STREAMS__LEN                            0x00000010
+#define VIVS_NFE_VERTEX_STREAMS_BASE_ADDR(i0)                  (0x00014600 + 0x4*(i0))
+#define VIVS_NFE_VERTEX_STREAMS_CONTROL(i0)                    (0x00014640 + 0x4*(i0))
+#define VIVS_NFE_VERTEX_STREAMS_UNK14680(i0)                   (0x00014680 + 0x4*(i0))
+#define VIVS_NFE_VERTEX_STREAMS_ROBUSTNESS_UNK146C0(i0)        (0x000146c0 + 0x4*(i0))
+#define VIVS_NFE_GENERIC_ATTRIB(i0)                            (0x00000000 + 0x4*(i0))
+#define VIVS_NFE_GENERIC_ATTRIB__ESIZE                          0x00000004
+#define VIVS_NFE_GENERIC_ATTRIB__LEN                            0x00000020
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0(i0)                    (0x00017800 + 0x4*(i0))
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__MASK              0x0000000f
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__SHIFT             0
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE(x)                 (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__MASK)
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__MASK            0x00000030
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__SHIFT           4
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN(x)               (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__MASK)
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__MASK            0x00000700
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__SHIFT           8
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM(x)               (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__MASK)
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__MASK               0x00003000
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__SHIFT              12
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM(x)                  (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__MASK)
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE__MASK         0x0000c000
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE__SHIFT        14
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE_OFF           0x00000000
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE_ON            0x00008000
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__MASK             0x00ff0000
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__SHIFT            16
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START(x)                (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__MASK)
+#define VIVS_NFE_GENERIC_ATTRIB_UNK17880(i0)                   (0x00017880 + 0x4*(i0))
+#define VIVS_NFE_GENERIC_ATTRIB_UNK17900(i0)                   (0x00017900 + 0x4*(i0))
+#define VIVS_NFE_GENERIC_ATTRIB_UNK17980(i0)                   (0x00017980 + 0x4*(i0))
+#define VIVS_NFE_GENERIC_ATTRIB_SCALE(i0)                      (0x00017a00 + 0x4*(i0))
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG1(i0)                    (0x00017a80 + 0x4*(i0))
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__MASK               0x000000ff
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__SHIFT              0
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END(x)                  (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__MASK)
+#define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_NONCONSECUTIVE          0x00000800
 #define VIVS_DUMMY                                              0x00000000
 #define VIVS_DUMMY_DUMMY                                        0x0003fffc
diff --git a/drivers/gpu/drm/etnaviv/state_3d.xml.h b/drivers/gpu/drm/etnaviv/state_3d.xml.h
index 73a97d35c51b..ebbd4fcf3096 100644
--- a/drivers/gpu/drm/etnaviv/state_3d.xml.h
+++ b/drivers/gpu/drm/etnaviv/state_3d.xml.h
@@ -7,4 +7,9 @@
 #define VIVS_TS_FLUSH_CACHE                                     0x00001650
 #define VIVS_TS_FLUSH_CACHE_FLUSH                               0x00000001
+#define VIVS_NTE_DESCRIPTOR_FLUSH                               0x00014c44
+#define VIVS_NTE_DESCRIPTOR_FLUSH_UNK28__MASK                   0xf0000000
+#define VIVS_NTE_DESCRIPTOR_FLUSH_UNK28__SHIFT                  28
+#define VIVS_NTE_DESCRIPTOR_FLUSH_UNK28(x)                      (((x) << VIVS_NTE_DESCRIPTOR_FLUSH_UNK28__SHIFT) & VIVS_NTE_DESCRIPTOR_FLUSH_UNK28__MASK)
 #endif /* STATE_3D_XML */
diff --git a/drivers/gpu/drm/etnaviv/state_blt.xml.h b/drivers/gpu/drm/etnaviv/state_blt.xml.h
new file mode 100644
index 000000000000..daae55995def
--- /dev/null
+++ b/drivers/gpu/drm/etnaviv/state_blt.xml.h
@@ -0,0 +1,52 @@
+#ifndef STATE_BLT_XML
+#define STATE_BLT_XML
+/* Autogenerated file, DO NOT EDIT manually!
+This file was generated by the rules-ng-ng headergen tool in this git repository:
+http://0x04.net/cgit/index.cgi/rules-ng-ng
+git clone git://0x04.net/rules-ng-ng
+The rules-ng-ng source files this header was generated from are:
+- state.xml     (  26087 bytes, from 2017-12-18 16:51:59)
+- common.xml    (  35468 bytes, from 2018-01-22 13:48:54)
+- common_3d.xml (  14615 bytes, from 2017-12-18 16:51:59)
+- state_hi.xml  (  30232 bytes, from 2018-02-15 15:48:01)
+- copyright.xml (   1597 bytes, from 2016-12-08 16:37:56)
+- state_2d.xml  (  51552 bytes, from 2016-12-08 16:37:56)
+- state_3d.xml  (  79992 bytes, from 2017-12-18 16:51:59)
+- state_blt.xml (  13405 bytes, from 2017-12-18 16:51:59)
+- state_vg.xml  (   5975 bytes, from 2016-12-08 16:37:56)
+Copyright (C) 2012-2017 by the following authors:
+- Wladimir J. van der Laan <laanwj@gmail.com>
+- Christian Gmeiner <christian.gmeiner@gmail.com>
+- Lucas Stach <l.stach@pengutronix.de>
+- Russell King <rmk@arm.linux.org.uk>
+Permission is hereby granted, free of charge, to any person obtaining a
+copy of this software and associated documentation files (the "Software"),
+to deal in the Software without restriction, including without limitation
+the rights to use, copy, modify, merge, publish, distribute, sub license,
+and/or sell copies of the Software, and to permit persons to whom the
+Software is furnished to do so, subject to the following conditions:
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial portions
+of the Software.
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+DEALINGS IN THE SOFTWARE.
+*/
+/* This is a cut-down version of the state_blt.xml.h file */
+#define VIVS_BLT_ENABLE                                         0x000140b8
+#define VIVS_BLT_ENABLE_ENABLE                                  0x00000001
+#endif /* STATE_BLT_XML */
diff --git a/drivers/gpu/drm/etnaviv/state_hi.xml.h b/drivers/gpu/drm/etnaviv/state_hi.xml.h
index 60808daf7e8d..41d8da2b6f4f 100644
--- a/drivers/gpu/drm/etnaviv/state_hi.xml.h
+++ b/drivers/gpu/drm/etnaviv/state_hi.xml.h
@@ -1,4 +1,3 @@
-/* SPDX-License-Identifier: GPL-2.0 */
 #ifndef STATE_HI_XML
 #define STATE_HI_XML
@@ -9,10 +8,40 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
 git clone git://0x04.net/rules-ng-ng
 The rules-ng-ng source files this header was generated from are:
- state_hi.xml (  25620 bytes, from 2016-08-19 22:07:37)
+- state.xml     (  26087 bytes, from 2017-12-18 16:51:59)
- common.xml   (  20583 bytes, from 2016-06-07 05:22:38)
+- common.xml    (  35468 bytes, from 2018-01-22 13:48:54)
+- common_3d.xml (  14615 bytes, from 2017-12-18 16:51:59)
-Copyright (C) 2016
+- state_hi.xml  (  30232 bytes, from 2018-02-15 15:48:01)
+- copyright.xml (   1597 bytes, from 2016-12-08 16:37:56)
+- state_2d.xml  (  51552 bytes, from 2016-12-08 16:37:56)
+- state_3d.xml  (  79992 bytes, from 2017-12-18 16:51:59)
+- state_blt.xml (  13405 bytes, from 2017-12-18 16:51:59)
+- state_vg.xml  (   5975 bytes, from 2016-12-08 16:37:56)
+Copyright (C) 2012-2018 by the following authors:
+- Wladimir J. van der Laan <laanwj@gmail.com>
+- Christian Gmeiner <christian.gmeiner@gmail.com>
+- Lucas Stach <l.stach@pengutronix.de>
+- Russell King <rmk@arm.linux.org.uk>
+Permission is hereby granted, free of charge, to any person obtaining a
+copy of this software and associated documentation files (the "Software"),
+to deal in the Software without restriction, including without limitation
+the rights to use, copy, modify, merge, publish, distribute, sub license,
+and/or sell copies of the Software, and to permit persons to whom the
+Software is furnished to do so, subject to the following conditions:
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial portions
+of the Software.
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+DEALINGS IN THE SOFTWARE.
 */
@@ -192,6 +221,9 @@ Copyright (C) 2016
 #define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__SHIFT              0
 #define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT(x)                  (((x) << VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__MASK)
+#define VIVS_HI_COMPRESSION_FLAGS                               0x00000090
+#define VIVS_HI_COMPRESSION_FLAGS_DEC300                        0x00000040
 #define VIVS_HI_CHIP_MINOR_FEATURE_4                            0x00000094
 #define VIVS_HI_CHIP_SPECS_4                                    0x0000009c
@@ -203,6 +235,10 @@ Copyright (C) 2016
 #define VIVS_HI_CHIP_PRODUCT_ID                                 0x000000a8
+#define VIVS_HI_BLT_INTR                                        0x000000d4
+#define VIVS_HI_AUXBIT                                          0x000000ec
 #define VIVS_PM                                                 0x00000000
 #define VIVS_PM_POWER_CONTROLS                                  0x00000100
@@ -239,6 +275,17 @@ Copyright (C) 2016
 #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_TX             0x00000080
 #define VIVS_PM_PULSE_EATER                                     0x0000010c
+#define VIVS_PM_PULSE_EATER_DISABLE                             0x00000001
+#define VIVS_PM_PULSE_EATER_DVFS_PERIOD__MASK                   0x0000ff00
+#define VIVS_PM_PULSE_EATER_DVFS_PERIOD__SHIFT                  8
+#define VIVS_PM_PULSE_EATER_DVFS_PERIOD(x)                      (((x) << VIVS_PM_PULSE_EATER_DVFS_PERIOD__SHIFT) & VIVS_PM_PULSE_EATER_DVFS_PERIOD__MASK)
+#define VIVS_PM_PULSE_EATER_UNK16                               0x00010000
+#define VIVS_PM_PULSE_EATER_UNK17                               0x00020000
+#define VIVS_PM_PULSE_EATER_INTERNAL_DFS                        0x00040000
+#define VIVS_PM_PULSE_EATER_UNK19                               0x00080000
+#define VIVS_PM_PULSE_EATER_UNK20                               0x00100000
+#define VIVS_PM_PULSE_EATER_UNK22                               0x00400000
+#define VIVS_PM_PULSE_EATER_UNK23                               0x00800000
 #define VIVS_MMUv2                                              0x00000000
@@ -280,6 +327,68 @@ Copyright (C) 2016
 #define VIVS_MMUv2_EXCEPTION_ADDR__ESIZE                        0x00000004
 #define VIVS_MMUv2_EXCEPTION_ADDR__LEN                          0x00000004
+#define VIVS_MMUv2_PROFILE_BLT_READ                             0x000001a4
+#define VIVS_MMUv2_PTA_CONFIG                                   0x000001ac
+#define VIVS_MMUv2_PTA_CONFIG_INDEX__MASK                       0x0000ffff
+#define VIVS_MMUv2_PTA_CONFIG_INDEX__SHIFT                      0
+#define VIVS_MMUv2_PTA_CONFIG_INDEX(x)                          (((x) << VIVS_MMUv2_PTA_CONFIG_INDEX__SHIFT) & VIVS_MMUv2_PTA_CONFIG_INDEX__MASK)
+#define VIVS_MMUv2_PTA_CONFIG_UNK16                             0x00010000
+#define VIVS_MMUv2_AXI_POLICY(i0)                              (0x000001c0 + 0x4*(i0))
+#define VIVS_MMUv2_AXI_POLICY__ESIZE                            0x00000004
+#define VIVS_MMUv2_AXI_POLICY__LEN                              0x00000008
+#define VIVS_MMUv2_SEC_EXCEPTION_ADDR                           0x00000380
+#define VIVS_MMUv2_SEC_STATUS                                   0x00000384
+#define VIVS_MMUv2_SEC_STATUS_EXCEPTION0__MASK                  0x00000003
+#define VIVS_MMUv2_SEC_STATUS_EXCEPTION0__SHIFT                 0
+#define VIVS_MMUv2_SEC_STATUS_EXCEPTION0(x)                     (((x) << VIVS_MMUv2_SEC_STATUS_EXCEPTION0__SHIFT) & VIVS_MMUv2_SEC_STATUS_EXCEPTION0__MASK)
+#define VIVS_MMUv2_SEC_STATUS_EXCEPTION1__MASK                  0x00000030
+#define VIVS_MMUv2_SEC_STATUS_EXCEPTION1__SHIFT                 4
+#define VIVS_MMUv2_SEC_STATUS_EXCEPTION1(x)                     (((x) << VIVS_MMUv2_SEC_STATUS_EXCEPTION1__SHIFT) & VIVS_MMUv2_SEC_STATUS_EXCEPTION1__MASK)
+#define VIVS_MMUv2_SEC_STATUS_EXCEPTION2__MASK                  0x00000300
+#define VIVS_MMUv2_SEC_STATUS_EXCEPTION2__SHIFT                 8
+#define VIVS_MMUv2_SEC_STATUS_EXCEPTION2(x)                     (((x) << VIVS_MMUv2_SEC_STATUS_EXCEPTION2__SHIFT) & VIVS_MMUv2_SEC_STATUS_EXCEPTION2__MASK)
+#define VIVS_MMUv2_SEC_STATUS_EXCEPTION3__MASK                  0x00003000
+#define VIVS_MMUv2_SEC_STATUS_EXCEPTION3__SHIFT                 12
+#define VIVS_MMUv2_SEC_STATUS_EXCEPTION3(x)                     (((x) << VIVS_MMUv2_SEC_STATUS_EXCEPTION3__SHIFT) & VIVS_MMUv2_SEC_STATUS_EXCEPTION3__MASK)
+#define VIVS_MMUv2_SEC_CONTROL                                  0x00000388
+#define VIVS_MMUv2_SEC_CONTROL_ENABLE                           0x00000001
+#define VIVS_MMUv2_PTA_ADDRESS_LOW                              0x0000038c
+#define VIVS_MMUv2_PTA_ADDRESS_HIGH                             0x00000390
+#define VIVS_MMUv2_PTA_CONTROL                                  0x00000394
+#define VIVS_MMUv2_PTA_CONTROL_ENABLE                           0x00000001
+#define VIVS_MMUv2_NONSEC_SAFE_ADDR_LOW                         0x00000398
+#define VIVS_MMUv2_SEC_SAFE_ADDR_LOW                            0x0000039c
+#define VIVS_MMUv2_SAFE_ADDRESS_CONFIG                          0x000003a0
+#define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__MASK     0x000000ff
+#define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__SHIFT    0
+#define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH(x)        (((x) << VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__SHIFT) & VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__MASK)
+#define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_UNK15                    0x00008000
+#define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__MASK 0x00ff0000
+#define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__SHIFT        16
+#define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH(x)    (((x) << VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__SHIFT) & VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__MASK)
+#define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_UNK31                    0x80000000
+#define VIVS_MMUv2_SEC_COMMAND_CONTROL                          0x000003a4
+#define VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__MASK           0x0000ffff
+#define VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__SHIFT          0
+#define VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(x)              (((x) << VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__SHIFT) & VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__MASK)
+#define VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE                   0x00010000
+#define VIVS_MMUv2_AHB_CONTROL                                  0x000003a8
+#define VIVS_MMUv2_AHB_CONTROL_RESET                            0x00000001
+#define VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS                    0x00000002
 #define VIVS_MC                                                 0x00000000
 #define VIVS_MC_MMU_FE_PAGE_TABLE                               0x00000400
@@ -340,13 +449,13 @@ Copyright (C) 2016
 #define VIVS_MC_PROFILE_HI_READ                                 0x0000046c
 #define VIVS_MC_PROFILE_CONFIG0                                 0x00000470
-#define VIVS_MC_PROFILE_CONFIG0_FE__MASK                        0x0000000f
+#define VIVS_MC_PROFILE_CONFIG0_FE__MASK                        0x000000ff
 #define VIVS_MC_PROFILE_CONFIG0_FE__SHIFT                       0
 #define VIVS_MC_PROFILE_CONFIG0_FE_RESET                        0x0000000f
-#define VIVS_MC_PROFILE_CONFIG0_DE__MASK                        0x00000f00
+#define VIVS_MC_PROFILE_CONFIG0_DE__MASK                        0x0000ff00
 #define VIVS_MC_PROFILE_CONFIG0_DE__SHIFT                       8
 #define VIVS_MC_PROFILE_CONFIG0_DE_RESET                        0x00000f00
-#define VIVS_MC_PROFILE_CONFIG0_PE__MASK                        0x000f0000
+#define VIVS_MC_PROFILE_CONFIG0_PE__MASK                        0x00ff0000
 #define VIVS_MC_PROFILE_CONFIG0_PE__SHIFT                       16
 #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_COLOR_PIPE     0x00000000
 #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_DEPTH_PIPE     0x00010000
@@ -354,7 +463,7 @@ Copyright (C) 2016
 #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_DEPTH_PIPE      0x00030000
 #define VIVS_MC_PROFILE_CONFIG0_PE_PIXELS_RENDERED_2D           0x000b0000
 #define VIVS_MC_PROFILE_CONFIG0_PE_RESET                        0x000f0000
-#define VIVS_MC_PROFILE_CONFIG0_SH__MASK                        0x0f000000
+#define VIVS_MC_PROFILE_CONFIG0_SH__MASK                        0xff000000
 #define VIVS_MC_PROFILE_CONFIG0_SH__SHIFT                       24
 #define VIVS_MC_PROFILE_CONFIG0_SH_SHADER_CYCLES                0x04000000
 #define VIVS_MC_PROFILE_CONFIG0_SH_PS_INST_COUNTER              0x07000000
@@ -368,7 +477,7 @@ Copyright (C) 2016
 #define VIVS_MC_PROFILE_CONFIG0_SH_RESET                        0x0f000000
 #define VIVS_MC_PROFILE_CONFIG1                                 0x00000474
-#define VIVS_MC_PROFILE_CONFIG1_PA__MASK                        0x0000000f
+#define VIVS_MC_PROFILE_CONFIG1_PA__MASK                        0x000000ff
 #define VIVS_MC_PROFILE_CONFIG1_PA__SHIFT                       0
 #define VIVS_MC_PROFILE_CONFIG1_PA_INPUT_VTX_COUNTER            0x00000003
 #define VIVS_MC_PROFILE_CONFIG1_PA_INPUT_PRIM_COUNTER           0x00000004
@@ -377,12 +486,12 @@ Copyright (C) 2016
 #define VIVS_MC_PROFILE_CONFIG1_PA_TRIVIAL_REJECTED_COUNTER     0x00000007
 #define VIVS_MC_PROFILE_CONFIG1_PA_CULLED_COUNTER               0x00000008
 #define VIVS_MC_PROFILE_CONFIG1_PA_RESET                        0x0000000f
-#define VIVS_MC_PROFILE_CONFIG1_SE__MASK                        0x00000f00
+#define VIVS_MC_PROFILE_CONFIG1_SE__MASK                        0x0000ff00
 #define VIVS_MC_PROFILE_CONFIG1_SE__SHIFT                       8
 #define VIVS_MC_PROFILE_CONFIG1_SE_CULLED_TRIANGLE_COUNT        0x00000000
 #define VIVS_MC_PROFILE_CONFIG1_SE_CULLED_LINES_COUNT           0x00000100
 #define VIVS_MC_PROFILE_CONFIG1_SE_RESET                        0x00000f00
-#define VIVS_MC_PROFILE_CONFIG1_RA__MASK                        0x000f0000
+#define VIVS_MC_PROFILE_CONFIG1_RA__MASK                        0x00ff0000
 #define VIVS_MC_PROFILE_CONFIG1_RA__SHIFT                       16
 #define VIVS_MC_PROFILE_CONFIG1_RA_VALID_PIXEL_COUNT            0x00000000
 #define VIVS_MC_PROFILE_CONFIG1_RA_TOTAL_QUAD_COUNT             0x00010000
@@ -392,7 +501,7 @@ Copyright (C) 2016
 #define VIVS_MC_PROFILE_CONFIG1_RA_PREFETCH_CACHE_MISS_COUNTER  0x000a0000
 #define VIVS_MC_PROFILE_CONFIG1_RA_CULLED_QUAD_COUNT            0x000b0000
 #define VIVS_MC_PROFILE_CONFIG1_RA_RESET                        0x000f0000
-#define VIVS_MC_PROFILE_CONFIG1_TX__MASK                        0x0f000000
+#define VIVS_MC_PROFILE_CONFIG1_TX__MASK                        0xff000000
 #define VIVS_MC_PROFILE_CONFIG1_TX__SHIFT                       24
 #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_BILINEAR_REQUESTS      0x00000000
 #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_TRILINEAR_REQUESTS     0x01000000
@@ -407,18 +516,21 @@ Copyright (C) 2016
 #define VIVS_MC_PROFILE_CONFIG1_TX_RESET                        0x0f000000
 #define VIVS_MC_PROFILE_CONFIG2                                 0x00000478
-#define VIVS_MC_PROFILE_CONFIG2_MC__MASK                        0x0000000f
+#define VIVS_MC_PROFILE_CONFIG2_MC__MASK                        0x000000ff
 #define VIVS_MC_PROFILE_CONFIG2_MC__SHIFT                       0
 #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_PIPELINE      0x00000001
 #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_IP    0x00000002
 #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_8B_FROM_PIPELINE     0x00000003
 #define VIVS_MC_PROFILE_CONFIG2_MC_RESET                        0x0000000f
-#define VIVS_MC_PROFILE_CONFIG2_HI__MASK                        0x00000f00
+#define VIVS_MC_PROFILE_CONFIG2_HI__MASK                        0x0000ff00
 #define VIVS_MC_PROFILE_CONFIG2_HI__SHIFT                       8
 #define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_READ_REQUEST_STALLED      0x00000000
 #define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_REQUEST_STALLED     0x00000100
 #define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_DATA_STALLED        0x00000200
 #define VIVS_MC_PROFILE_CONFIG2_HI_RESET                        0x00000f00
+#define VIVS_MC_PROFILE_CONFIG2_BLT__MASK                       0xff000000
+#define VIVS_MC_PROFILE_CONFIG2_BLT__SHIFT                      24
+#define VIVS_MC_PROFILE_CONFIG2_BLT_UNK0                        0x00000000
 #define VIVS_MC_PROFILE_CONFIG3                                 0x0000047c
@@ -432,7 +544,13 @@ Copyright (C) 2016
 #define VIVS_MC_START_COMPOSITION                               0x00000554
-#define VIVS_MC_128B_MERGE                                      0x00000558
+#define VIVS_MC_FLAGS                                           0x00000558
+#define VIVS_MC_FLAGS_128B_MERGE                                0x00000001
+#define VIVS_MC_FLAGS_TPCV11_COMPRESSION                        0x08000000
+#define VIVS_MC_L2_CACHE_CONFIG                                 0x0000055c
+#define VIVS_MC_PROFILE_L2_READ                                 0x00000564
 #endif /* STATE_HI_XML */
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 89ab0f70aa22..c6a7beabd58d 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -39,7 +39,7 @@
 #define CTM_COEFF_NEGATIVE(coeff)       (((coeff) & CTM_COEFF_SIGN) != 0)
 #define CTM_COEFF_ABS(coeff)            ((coeff) & (CTM_COEFF_SIGN - 1))
-#define LEGACY_LUT_LENGTH               (sizeof(struct drm_color_lut) * 256)
+#define LEGACY_LUT_LENGTH               256
 /* Post offset values for RGB->YCBCR conversion */
 #define POSTOFF_RGB_TO_YUV_HI 0x800
@@ -79,7 +79,7 @@ static bool crtc_state_is_legacy_gamma(struct drm_crtc_state *state)
        return !state->degamma_lut &&
                !state->ctm &&
                state->gamma_lut &&
-                state->gamma_lut->length == LEGACY_LUT_LENGTH;
+                drm_color_lut_size(state->gamma_lut) == LEGACY_LUT_LENGTH;
 }
 /*
@@ -153,8 +153,7 @@ static void ilk_load_csc_matrix(struct drm_crtc_state *crtc_state)
                ilk_load_ycbcr_conversion_matrix(intel_crtc);
                return;
        } else if (crtc_state->ctm) {
-                struct drm_color_ctm *ctm =
+                struct drm_color_ctm *ctm = crtc_state->ctm->data;
-                        (struct drm_color_ctm *)crtc_state->ctm->data;
                const u64 *input;
                u64 temp[9];
@@ -262,8 +261,7 @@ static void cherryview_load_csc_matrix(struct drm_crtc_state *state)
        uint32_t mode;
        if (state->ctm) {
-                struct drm_color_ctm *ctm =
+                struct drm_color_ctm *ctm = state->ctm->data;
-                        (struct drm_color_ctm *) state->ctm->data;
                uint16_t coeffs[9] = { 0, };
                int i;
@@ -330,7 +328,7 @@ static void i9xx_load_luts_internal(struct drm_crtc *crtc,
        }
        if (blob) {
-                struct drm_color_lut *lut = (struct drm_color_lut *) blob->data;
+                struct drm_color_lut *lut = blob->data;
                for (i = 0; i < 256; i++) {
                        uint32_t word =
                                (drm_color_lut_extract(lut[i].red, 8) << 16) |
@@ -400,8 +398,7 @@ static void bdw_load_degamma_lut(struct drm_crtc_state *state)
                   PAL_PREC_SPLIT_MODE | PAL_PREC_AUTO_INCREMENT);
        if (state->degamma_lut) {
-                struct drm_color_lut *lut =
+                struct drm_color_lut *lut = state->degamma_lut->data;
-                        (struct drm_color_lut *) state->degamma_lut->data;
                for (i = 0; i < lut_size; i++) {
                        uint32_t word =
@@ -435,8 +432,7 @@ static void bdw_load_gamma_lut(struct drm_crtc_state *state, u32 offset)
                   offset);
        if (state->gamma_lut) {
-                struct drm_color_lut *lut =
+                struct drm_color_lut *lut = state->gamma_lut->data;
-                        (struct drm_color_lut *) state->gamma_lut->data;
                for (i = 0; i < lut_size; i++) {
                        uint32_t word =
@@ -568,7 +564,7 @@ static void cherryview_load_luts(struct drm_crtc_state *state)
        }
        if (state->degamma_lut) {
-                lut = (struct drm_color_lut *) state->degamma_lut->data;
+                lut = state->degamma_lut->data;
                lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
                for (i = 0; i < lut_size; i++) {
                        /* Write LUT in U0.14 format. */
@@ -583,7 +579,7 @@ static void cherryview_load_luts(struct drm_crtc_state *state)
        }
        if (state->gamma_lut) {
-                lut = (struct drm_color_lut *) state->gamma_lut->data;
+                lut = state->gamma_lut->data;
                lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
                for (i = 0; i < lut_size; i++) {
                        /* Write LUT in U0.10 format. */
@@ -623,19 +619,17 @@ int intel_color_check(struct drm_crtc *crtc,
        struct drm_i915_private *dev_priv = to_i915(crtc->dev);
        size_t gamma_length, degamma_length;
-        degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size *
+        degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
-                sizeof(struct drm_color_lut);
+        gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
-        gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size *
-                sizeof(struct drm_color_lut);
        /*
         * We allow both degamma & gamma luts at the right size or
         * NULL.
         */
        if ((!crtc_state->degamma_lut ||
-             crtc_state->degamma_lut->length == degamma_length) &&
+             drm_color_lut_size(crtc_state->degamma_lut) == degamma_length) &&
            (!crtc_state->gamma_lut ||
-             crtc_state->gamma_lut->length == gamma_length))
+             drm_color_lut_size(crtc_state->gamma_lut) == gamma_length))
                return 0;
        /*
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 331084082545..3b48fd2561fe 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11059,24 +11059,17 @@ intel_compare_link_m_n(const struct intel_link_m_n *m_n,
 static void __printf(3, 4)
 pipe_config_err(bool adjust, const char *name, const char *format, ...)
 {
-        char *level;
-        unsigned int category;
        struct va_format vaf;
        va_list args;
-        if (adjust) {
-                level = KERN_DEBUG;
-                category = DRM_UT_KMS;
-        } else {
-                level = KERN_ERR;
-                category = DRM_UT_NONE;
-        }
        va_start(args, format);
        vaf.fmt = format;
        vaf.va = &args;
-        drm_printk(level, category, "mismatch in %s %pV", name, &vaf);
+        if (adjust)
+                drm_dbg(DRM_UT_KMS, "mismatch in %s %pV", name, &vaf);
+        else
+                drm_err("mismatch in %s %pV", name, &vaf);
        va_end(args);
 }
diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c
index f9ad0e960263..32b1a6cdecfc 100644
--- a/drivers/gpu/drm/meson/meson_drv.c
+++ b/drivers/gpu/drm/meson/meson_drv.c
@@ -189,40 +189,55 @@ static int meson_drv_bind_master(struct device *dev, bool has_components)
        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vpu");
        regs = devm_ioremap_resource(dev, res);
-        if (IS_ERR(regs))
+        if (IS_ERR(regs)) {
-                return PTR_ERR(regs);
+                ret = PTR_ERR(regs);
+                goto free_drm;
+        }
        priv->io_base = regs;
        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hhi");
+        if (!res)
+                return -EINVAL;
        /* Simply ioremap since it may be a shared register zone */
        regs = devm_ioremap(dev, res->start, resource_size(res));
-        if (!regs)
+        if (!regs) {
-                return -EADDRNOTAVAIL;
+                ret = -EADDRNOTAVAIL;
+                goto free_drm;
+        }
        priv->hhi = devm_regmap_init_mmio(dev, regs,
                                          &meson_regmap_config);
        if (IS_ERR(priv->hhi)) {
                dev_err(&pdev->dev, "Couldn't create the HHI regmap\n");
-                return PTR_ERR(priv->hhi);
+                ret = PTR_ERR(priv->hhi);
+                goto free_drm;
        }
        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dmc");
+        if (!res)
+                return -EINVAL;
        /* Simply ioremap since it may be a shared register zone */
        regs = devm_ioremap(dev, res->start, resource_size(res));
-        if (!regs)
+        if (!regs) {
-                return -EADDRNOTAVAIL;
+                ret = -EADDRNOTAVAIL;
+                goto free_drm;
+        }
        priv->dmc = devm_regmap_init_mmio(dev, regs,
                                          &meson_regmap_config);
        if (IS_ERR(priv->dmc)) {
                dev_err(&pdev->dev, "Couldn't create the DMC regmap\n");
-                return PTR_ERR(priv->dmc);
+                ret = PTR_ERR(priv->dmc);
+                goto free_drm;
        }
        priv->vsync_irq = platform_get_irq(pdev, 0);
-        drm_vblank_init(drm, 1);
+        ret = drm_vblank_init(drm, 1);
+        if (ret)
+                goto free_drm;
        drm_mode_config_init(drm);
        drm->mode_config.max_width = 3840;
        drm->mode_config.max_height = 2160;
@@ -281,7 +296,7 @@ static int meson_drv_bind_master(struct device *dev, bool has_components)
        return 0;
 free_drm:
-        drm_dev_unref(drm);
+        drm_dev_put(drm);
        return ret;
 }
@@ -300,7 +315,7 @@ static void meson_drv_unbind(struct device *dev)
        drm_kms_helper_poll_fini(drm);
        drm_fbdev_cma_fini(priv->fbdev);
        drm_mode_config_cleanup(drm);
-        drm_dev_unref(drm);
+        drm_dev_put(drm);
 }
diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c
index d49af17310c9..a393095aac1a 100644
--- a/drivers/gpu/drm/meson/meson_dw_hdmi.c
+++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c
@@ -538,7 +538,6 @@ static irqreturn_t dw_hdmi_top_thread_irq(int irq, void *dev_id)
        return IRQ_HANDLED;
 }
-/* TOFIX Enable support for non-vic modes */
 static enum drm_mode_status
 dw_hdmi_mode_valid(struct drm_connector *connector,
                   const struct drm_display_mode *mode)
@@ -555,12 +554,12 @@ dw_hdmi_mode_valid(struct drm_connector *connector,
                mode->vdisplay, mode->vsync_start,
                mode->vsync_end, mode->vtotal, mode->type, mode->flags);
-        /* For now, only accept VIC modes */
+        /* Check against non-VIC supported modes */
-        if (!vic)
+        if (!vic) {
-                return MODE_BAD;
+                if (!meson_venc_hdmi_supported_mode(mode))
+                        return MODE_BAD;
-        /* For now, filter by supported VIC modes */
+        /* Check against supported VIC modes */
-        if (!meson_venc_hdmi_supported_vic(vic))
+        } else if (!meson_venc_hdmi_supported_vic(vic))
                return MODE_BAD;
        vclk_freq = mode->clock;
@@ -586,9 +585,14 @@ dw_hdmi_mode_valid(struct drm_connector *connector,
        /* Finally filter by configurable vclk frequencies */
        switch (vclk_freq) {
+        case 25175:
+        case 40000:
        case 54000:
+        case 65000:
        case 74250:
+        case 108000:
        case 148500:
+        case 162000:
        case 297000:
        case 594000:
                return MODE_OK;
@@ -653,10 +657,6 @@ static void meson_venc_hdmi_encoder_mode_set(struct drm_encoder *encoder,
        DRM_DEBUG_DRIVER("%d:\"%s\" vic %d\n",
                         mode->base.id, mode->name, vic);
-        /* Should have been filtered */
-        if (!vic)
-                return;
        /* VENC + VENC-DVI Mode setup */
        meson_venc_hdmi_mode_set(priv, vic, mode);
diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c
index 47677047e42d..f0511220317f 100644
--- a/drivers/gpu/drm/meson/meson_vclk.c
+++ b/drivers/gpu/drm/meson/meson_vclk.c
@@ -328,14 +328,24 @@ static void meson_venci_cvbs_clock_config(struct meson_drm *priv)
 #define MESON_VCLK_HDMI_DDR_54000       2
 /* 2970 /4 /1 /1 /5 /1  => /1 /2 */
 #define MESON_VCLK_HDMI_DDR_148500      3
+/* 4028 /4 /4 /1 /5 /2  => /1 /1 */
+#define MESON_VCLK_HDMI_25175           4
+/* 3200 /4 /2 /1 /5 /2  => /1 /1 */
+#define MESON_VCLK_HDMI_40000           5
+/* 5200 /4 /2 /1 /5 /2  => /1 /1 */
+#define MESON_VCLK_HDMI_65000           6
 /* 2970 /2 /2 /2 /5 /1  => /1 /1 */
-#define MESON_VCLK_HDMI_74250           4
+#define MESON_VCLK_HDMI_74250           7
+/* 4320 /4 /1 /1 /5 /2  => /1 /1 */
+#define MESON_VCLK_HDMI_108000          8
 /* 2970 /1 /2 /2 /5 /1  => /1 /1 */
-#define MESON_VCLK_HDMI_148500          5
+#define MESON_VCLK_HDMI_148500          9
+/* 3240 /2 /1 /1 /5 /2  => /1 /1 */
+#define MESON_VCLK_HDMI_162000          10
 /* 2970 /1 /1 /1 /5 /2  => /1 /1 */
-#define MESON_VCLK_HDMI_297000          6
+#define MESON_VCLK_HDMI_297000          11
 /* 5940 /1 /1 /2 /5 /1  => /1 /1 */
-#define MESON_VCLK_HDMI_594000          7
+#define MESON_VCLK_HDMI_594000          12
 struct meson_vclk_params {
        unsigned int pll_base_freq;
@@ -401,6 +411,46 @@ struct meson_vclk_params {
                .vid_pll_div = VID_PLL_DIV_5,
                .vclk_div = 1,
        },
+        [MESON_VCLK_HDMI_25175] = {
+                .pll_base_freq = 4028000,
+                .pll_od1 = 4,
+                .pll_od2 = 4,
+                .pll_od3 = 1,
+                .vid_pll_div = VID_PLL_DIV_5,
+                .vclk_div = 2,
+        },
+        [MESON_VCLK_HDMI_40000] = {
+                .pll_base_freq = 3200000,
+                .pll_od1 = 4,
+                .pll_od2 = 2,
+                .pll_od3 = 1,
+                .vid_pll_div = VID_PLL_DIV_5,
+                .vclk_div = 2,
+        },
+        [MESON_VCLK_HDMI_65000] = {
+                .pll_base_freq = 5200000,
+                .pll_od1 = 4,
+                .pll_od2 = 2,
+                .pll_od3 = 1,
+                .vid_pll_div = VID_PLL_DIV_5,
+                .vclk_div = 2,
+        },
+        [MESON_VCLK_HDMI_108000] = {
+                .pll_base_freq = 4320000,
+                .pll_od1 = 4,
+                .pll_od2 = 1,
+                .pll_od3 = 1,
+                .vid_pll_div = VID_PLL_DIV_5,
+                .vclk_div = 2,
+        },
+        [MESON_VCLK_HDMI_162000] = {
+                .pll_base_freq = 3240000,
+                .pll_od1 = 2,
+                .pll_od2 = 1,
+                .pll_od3 = 1,
+                .vid_pll_div = VID_PLL_DIV_5,
+                .vclk_div = 2,
+        },
 };
 static inline unsigned int pll_od_to_reg(unsigned int od)
@@ -451,6 +501,90 @@ void meson_hdmi_pll_set(struct meson_drm *priv,
                                                0xFFFF,  0x4e00);
                        break;
+                case 3200000:
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x58000242);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00000000);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55);
+                        /* unreset */
+                        regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
+                                                BIT(28), 0);
+                        /* Poll for lock bit */
+                        regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL,
+                                        val, (val & HDMI_PLL_LOCK), 10, 0);
+                        /* div_frac */
+                        regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
+                                                0xFFFF,  0x4aab);
+                        break;
+                case 3240000:
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x58000243);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00000000);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55);
+                        /* unreset */
+                        regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
+                                                BIT(28), 0);
+                        /* Poll for lock bit */
+                        regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL,
+                                        val, (val & HDMI_PLL_LOCK), 10, 0);
+                        /* div_frac */
+                        regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
+                                                0xFFFF,  0x4800);
+                        break;
+                case 3865000:
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x58000250);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00000000);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55);
+                        /* unreset */
+                        regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
+                                                BIT(28), 0);
+                        /* Poll for lock bit */
+                        regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL,
+                                        val, (val & HDMI_PLL_LOCK), 10, 0);
+                        /* div_frac */
+                        regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
+                                                0xFFFF,  0x4855);
+                        break;
+                case 4028000:
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x58000253);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00000000);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55);
+                        /* unreset */
+                        regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
+                                                BIT(28), 0);
+                        /* Poll for lock bit */
+                        regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL,
+                                        val, (val & HDMI_PLL_LOCK), 10, 0);
+                        /* div_frac */
+                        regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
+                                                0xFFFF,  0x4eab);
+                        break;
                case 4320000:
                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x5800025a);
                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00000000);
@@ -485,6 +619,23 @@ void meson_hdmi_pll_set(struct meson_drm *priv,
                        regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL,
                                        val, (val & HDMI_PLL_LOCK), 10, 0);
                        break;
+                case 5200000:
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x5800026c);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00000000);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x135c5091);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55);
+                        /* unreset */
+                        regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
+                                                BIT(28), 0);
+                        /* Poll for lock bit */
+                        regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL,
+                                        val, (val & HDMI_PLL_LOCK), 10, 0);
+                        break;
                };
        } else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
                   meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) {
@@ -498,6 +649,42 @@ void meson_hdmi_pll_set(struct meson_drm *priv,
                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500);
                        break;
+                case 3200000:
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x40000285);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb155);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c8e0000);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500);
+                        break;
+                case 3240000:
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x40000287);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb000);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c8e0000);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500);
+                        break;
+                case 3865000:
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x400002a1);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb02b);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c8e0000);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500);
+                        break;
+                case 4028000:
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x400002a7);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb355);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c8e0000);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500);
+                        break;
                case 4320000:
                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x400002b4);
                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb000);
@@ -516,6 +703,15 @@ void meson_hdmi_pll_set(struct meson_drm *priv,
                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500);
                        break;
+                case 5200000:
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x400002d8);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb2ab);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c8e0000);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729);
+                        regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500);
+                        break;
                };
                /* Reset PLL */
@@ -590,15 +786,30 @@ void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
                else
                        freq = MESON_VCLK_HDMI_DDR_54000;
                break;
+        case 25175:
+                freq = MESON_VCLK_HDMI_25175;
+                break;
+        case 40000:
+                freq = MESON_VCLK_HDMI_40000;
+                break;
+        case 65000:
+                freq = MESON_VCLK_HDMI_65000;
+                break;
        case 74250:
                freq = MESON_VCLK_HDMI_74250;
                break;
+        case 108000:
+                freq = MESON_VCLK_HDMI_108000;
+                break;
        case 148500:
                if (dac_freq != 148500)
                        freq = MESON_VCLK_HDMI_DDR_148500;
                else
                        freq = MESON_VCLK_HDMI_148500;
                break;
+        case 162000:
+                freq = MESON_VCLK_HDMI_162000;
+                break;
        case 297000:
                freq = MESON_VCLK_HDMI_297000;
                break;
diff --git a/drivers/gpu/drm/meson/meson_venc.c b/drivers/gpu/drm/meson/meson_venc.c
index 9509017dbded..6e2701389801 100644
--- a/drivers/gpu/drm/meson/meson_venc.c
+++ b/drivers/gpu/drm/meson/meson_venc.c
@@ -697,6 +697,314 @@ union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p60 = {
        },
 };
+union meson_hdmi_venc_mode meson_hdmi_encp_mode_640x480_60 = {
+        .encp = {
+                .dvi_settings = 0x21,
+                .video_mode = 0x4040,
+                .video_mode_adv = 0x18,
+                /* video_prog_mode */
+                /* video_sync_mode */
+                /* video_yc_dly */
+                /* video_rgb_ctrl */
+                /* video_filt_ctrl */
+                /* video_ofld_voav_ofst */
+                /* yfp1_htime */
+                /* yfp2_htime */
+                .max_pxcnt = 0x31f,
+                /* hspuls_begin */
+                /* hspuls_end */
+                /* hspuls_switch */
+                /* vspuls_begin */
+                /* vspuls_end */
+                /* vspuls_bline */
+                /* vspuls_eline */
+                .havon_begin = 0x90,
+                .havon_end = 0x30f,
+                .vavon_bline = 0x23,
+                .vavon_eline = 0x202,
+                /* eqpuls_begin */
+                /* eqpuls_end */
+                /* eqpuls_bline */
+                /* eqpuls_eline */
+                .hso_begin = 0,
+                .hso_end = 0x60,
+                .vso_begin = 0x1e,
+                .vso_end = 0x32,
+                .vso_bline = 0,
+                .vso_eline = 2,
+                .vso_eline_present = true,
+                /* sy_val */
+                /* sy2_val */
+                .max_lncnt = 0x20c,
+        },
+};
+union meson_hdmi_venc_mode meson_hdmi_encp_mode_800x600_60 = {
+        .encp = {
+                .dvi_settings = 0x21,
+                .video_mode = 0x4040,
+                .video_mode_adv = 0x18,
+                /* video_prog_mode */
+                /* video_sync_mode */
+                /* video_yc_dly */
+                /* video_rgb_ctrl */
+                /* video_filt_ctrl */
+                /* video_ofld_voav_ofst */
+                /* yfp1_htime */
+                /* yfp2_htime */
+                .max_pxcnt = 0x41f,
+                /* hspuls_begin */
+                /* hspuls_end */
+                /* hspuls_switch */
+                /* vspuls_begin */
+                /* vspuls_end */
+                /* vspuls_bline */
+                /* vspuls_eline */
+                .havon_begin = 0xD8,
+                .havon_end = 0x3f7,
+                .vavon_bline = 0x1b,
+                .vavon_eline = 0x272,
+                /* eqpuls_begin */
+                /* eqpuls_end */
+                /* eqpuls_bline */
+                /* eqpuls_eline */
+                .hso_begin = 0,
+                .hso_end = 0x80,
+                .vso_begin = 0x1e,
+                .vso_end = 0x32,
+                .vso_bline = 0,
+                .vso_eline = 4,
+                .vso_eline_present = true,
+                /* sy_val */
+                /* sy2_val */
+                .max_lncnt = 0x273,
+        },
+};
+union meson_hdmi_venc_mode meson_hdmi_encp_mode_1024x768_60 = {
+        .encp = {
+                .dvi_settings = 0x21,
+                .video_mode = 0x4040,
+                .video_mode_adv = 0x18,
+                /* video_prog_mode */
+                /* video_sync_mode */
+                /* video_yc_dly */
+                /* video_rgb_ctrl */
+                /* video_filt_ctrl */
+                /* video_ofld_voav_ofst */
+                /* yfp1_htime */
+                /* yfp2_htime */
+                .max_pxcnt = 1343,
+                /* hspuls_begin */
+                /* hspuls_end */
+                /* hspuls_switch */
+                /* vspuls_begin */
+                /* vspuls_end */
+                /* vspuls_bline */
+                /* vspuls_eline */
+                .havon_begin = 296,
+                .havon_end = 1319,
+                .vavon_bline = 35,
+                .vavon_eline = 802,
+                /* eqpuls_begin */
+                /* eqpuls_end */
+                /* eqpuls_bline */
+                /* eqpuls_eline */
+                .hso_begin = 0,
+                .hso_end = 136,
+                .vso_begin = 30,
+                .vso_end = 50,
+                .vso_bline = 0,
+                .vso_eline = 6,
+                .vso_eline_present = true,
+                /* sy_val */
+                /* sy2_val */
+                .max_lncnt = 805,
+        },
+};
+union meson_hdmi_venc_mode meson_hdmi_encp_mode_1152x864_75 = {
+        .encp = {
+                .dvi_settings = 0x21,
+                .video_mode = 0x4040,
+                .video_mode_adv = 0x18,
+                /* video_prog_mode */
+                /* video_sync_mode */
+                /* video_yc_dly */
+                /* video_rgb_ctrl */
+                /* video_filt_ctrl */
+                /* video_ofld_voav_ofst */
+                /* yfp1_htime */
+                /* yfp2_htime */
+                .max_pxcnt = 0x63f,
+                /* hspuls_begin */
+                /* hspuls_end */
+                /* hspuls_switch */
+                /* vspuls_begin */
+                /* vspuls_end */
+                /* vspuls_bline */
+                /* vspuls_eline */
+                .havon_begin = 0x180,
+                .havon_end = 0x5ff,
+                .vavon_bline = 0x23,
+                .vavon_eline = 0x382,
+                /* eqpuls_begin */
+                /* eqpuls_end */
+                /* eqpuls_bline */
+                /* eqpuls_eline */
+                .hso_begin = 0,
+                .hso_end = 0x80,
+                .vso_begin = 0x1e,
+                .vso_end = 0x32,
+                .vso_bline = 0,
+                .vso_eline = 3,
+                .vso_eline_present = true,
+                /* sy_val */
+                /* sy2_val */
+                .max_lncnt = 0x383,
+        },
+};
+union meson_hdmi_venc_mode meson_hdmi_encp_mode_1280x1024_60 = {
+        .encp = {
+                .dvi_settings = 0x21,
+                .video_mode = 0x4040,
+                .video_mode_adv = 0x18,
+                /* video_prog_mode */
+                /* video_sync_mode */
+                /* video_yc_dly */
+                /* video_rgb_ctrl */
+                /* video_filt_ctrl */
+                /* video_ofld_voav_ofst */
+                /* yfp1_htime */
+                /* yfp2_htime */
+                .max_pxcnt = 0x697,
+                /* hspuls_begin */
+                /* hspuls_end */
+                /* hspuls_switch */
+                /* vspuls_begin */
+                /* vspuls_end */
+                /* vspuls_bline */
+                /* vspuls_eline */
+                .havon_begin = 0x168,
+                .havon_end = 0x667,
+                .vavon_bline = 0x29,
+                .vavon_eline = 0x428,
+                /* eqpuls_begin */
+                /* eqpuls_end */
+                /* eqpuls_bline */
+                /* eqpuls_eline */
+                .hso_begin = 0,
+                .hso_end = 0x70,
+                .vso_begin = 0x1e,
+                .vso_end = 0x32,
+                .vso_bline = 0,
+                .vso_eline = 3,
+                .vso_eline_present = true,
+                /* sy_val */
+                /* sy2_val */
+                .max_lncnt = 0x429,
+        },
+};
+union meson_hdmi_venc_mode meson_hdmi_encp_mode_1600x1200_60 = {
+        .encp = {
+                .dvi_settings = 0x21,
+                .video_mode = 0x4040,
+                .video_mode_adv = 0x18,
+                /* video_prog_mode */
+                /* video_sync_mode */
+                /* video_yc_dly */
+                /* video_rgb_ctrl */
+                /* video_filt_ctrl */
+                /* video_ofld_voav_ofst */
+                /* yfp1_htime */
+                /* yfp2_htime */
+                .max_pxcnt = 0x86f,
+                /* hspuls_begin */
+                /* hspuls_end */
+                /* hspuls_switch */
+                /* vspuls_begin */
+                /* vspuls_end */
+                /* vspuls_bline */
+                /* vspuls_eline */
+                .havon_begin = 0x1f0,
+                .havon_end = 0x82f,
+                .vavon_bline = 0x31,
+                .vavon_eline = 0x4e0,
+                /* eqpuls_begin */
+                /* eqpuls_end */
+                /* eqpuls_bline */
+                /* eqpuls_eline */
+                .hso_begin = 0,
+                .hso_end = 0xc0,
+                .vso_begin = 0x1e,
+                .vso_end = 0x32,
+                .vso_bline = 0,
+                .vso_eline = 3,
+                .vso_eline_present = true,
+                /* sy_val */
+                /* sy2_val */
+                .max_lncnt = 0x4e1,
+        },
+};
+struct meson_hdmi_venc_dmt_mode {
+        struct drm_display_mode drm_mode;
+        union meson_hdmi_venc_mode *mode;
+} meson_hdmi_venc_dmt_modes[] = {
+        /* 640x480@60Hz */
+        {
+                { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
+                  752, 800, 0, 480, 490, 492, 525, 0,
+                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
+                &meson_hdmi_encp_mode_640x480_60,
+        },
+        /* 800x600@60Hz */
+        {
+                { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
+                  968, 1056, 0, 600, 601, 605, 628, 0,
+                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+                &meson_hdmi_encp_mode_800x600_60,
+        },
+        /* 1024x768@60Hz */
+        {
+                { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024,
+                  1048, 1184, 1344, 0, 768, 771, 777, 806, 0,
+                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
+                &meson_hdmi_encp_mode_1024x768_60,
+        },
+        /* 1152x864@75Hz */
+        {
+                { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152,
+                  1216, 1344, 1600, 0, 864, 865, 868, 900, 0,
+                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+                &meson_hdmi_encp_mode_1152x864_75,
+        },
+        /* 1280x1024@60Hz */
+        {
+                { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280,
+                  1328, 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
+                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+                &meson_hdmi_encp_mode_1280x1024_60,
+        },
+        /* 1600x1200@60Hz */
+        {
+                { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600,
+                  1664, 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
+                  DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
+                &meson_hdmi_encp_mode_1600x1200_60,
+        },
+        /* 1920x1080@60Hz */
+        {
+                { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920,
+                  2008, 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
+                  DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
+                &meson_hdmi_encp_mode_1080p60
+        },
+        { }, /* sentinel */
+};
 struct meson_hdmi_venc_vic_mode {
        unsigned int vic;
        union meson_hdmi_venc_mode *mode;
@@ -736,6 +1044,20 @@ static unsigned long modulo(unsigned long a, unsigned long b)
                return a;
 }
+bool meson_venc_hdmi_supported_mode(const struct drm_display_mode *mode)
+{
+        struct meson_hdmi_venc_dmt_mode *vmode = meson_hdmi_venc_dmt_modes;
+        while (vmode->mode) {
+                if (drm_mode_equal(&vmode->drm_mode, mode))
+                        return true;
+                vmode++;
+        }
+        return false;
+}
+EXPORT_SYMBOL_GPL(meson_venc_hdmi_supported_mode);
 bool meson_venc_hdmi_supported_vic(int vic)
 {
        struct meson_hdmi_venc_vic_mode *vmode = meson_hdmi_venc_vic_modes;
@@ -750,6 +1072,20 @@ bool meson_venc_hdmi_supported_vic(int vic)
 }
 EXPORT_SYMBOL_GPL(meson_venc_hdmi_supported_vic);
+static union meson_hdmi_venc_mode
+*meson_venc_hdmi_get_dmt_vmode(const struct drm_display_mode *mode)
+{
+        struct meson_hdmi_venc_dmt_mode *vmode = meson_hdmi_venc_dmt_modes;
+        while (vmode->mode) {
+                if (drm_mode_equal(&vmode->drm_mode, mode))
+                        return vmode->mode;
+                vmode++;
+        }
+        return NULL;
+}
 static union meson_hdmi_venc_mode *meson_venc_hdmi_get_vic_vmode(int vic)
 {
        struct meson_hdmi_venc_vic_mode *vmode = meson_hdmi_venc_vic_modes;
@@ -811,10 +1147,13 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
        unsigned int sof_lines;
        unsigned int vsync_lines;
-        vmode = meson_venc_hdmi_get_vic_vmode(vic);
+        if (meson_venc_hdmi_supported_vic(vic))
+                vmode = meson_venc_hdmi_get_vic_vmode(vic);
+        else
+                vmode = meson_venc_hdmi_get_dmt_vmode(mode);
        if (!vmode) {
-                dev_err(priv->dev, "%s: Fatal Error, unsupported vic %d\n",
+                dev_err(priv->dev, "%s: Fatal Error, unsupported mode "
-                        __func__, vic);
+                        DRM_MODE_FMT "\n", __func__, DRM_MODE_ARG(mode));
                return;
        }
@@ -864,7 +1203,7 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
                hsync_pixels_venc *= 2;
        /* Disable VDACs */
-        writel_bits_relaxed(0x1f, 0x1f,
+        writel_bits_relaxed(0xff, 0xff,
                        priv->io_base + _REG(VENC_VDAC_SETTING));
        writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN));
diff --git a/drivers/gpu/drm/meson/meson_venc.h b/drivers/gpu/drm/meson/meson_venc.h
index a1b96e898c14..7c18a36a0dd0 100644
--- a/drivers/gpu/drm/meson/meson_venc.h
+++ b/drivers/gpu/drm/meson/meson_venc.h
@@ -58,6 +58,7 @@ struct meson_cvbs_enci_mode {
 };
 /* HDMI Clock parameters */
+bool meson_venc_hdmi_supported_mode(const struct drm_display_mode *mode);
 bool meson_venc_hdmi_supported_vic(int vic);
 bool meson_venc_hdmi_venc_repeat(int vic);
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c
index 3e293029e3a6..bbbf353682e1 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@ -510,37 +510,6 @@ static int nouveau_drm_probe(struct pci_dev *pdev,
        return 0;
 }
-#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
-static void
-nouveau_get_hdmi_dev(struct nouveau_drm *drm)
-{
-        struct pci_dev *pdev = drm->dev->pdev;
-        if (!pdev) {
-                NV_DEBUG(drm, "not a PCI device; no HDMI\n");
-                drm->hdmi_device = NULL;
-                return;
-        }
-        /* subfunction one is a hdmi audio device? */
-        drm->hdmi_device = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
-                                                (unsigned int)pdev->bus->number,
-                                                PCI_DEVFN(PCI_SLOT(pdev->devfn), 1));
-        if (!drm->hdmi_device) {
-                NV_DEBUG(drm, "hdmi device not found %d %d %d\n", pdev->bus->number, PCI_SLOT(pdev->devfn), 1);
-                return;
-        }
-        if ((drm->hdmi_device->class >> 8) != PCI_CLASS_MULTIMEDIA_HD_AUDIO) {
-                NV_DEBUG(drm, "possible hdmi device not audio %d\n", drm->hdmi_device->class);
-                pci_dev_put(drm->hdmi_device);
-                drm->hdmi_device = NULL;
-                return;
-        }
-}
 static int
 nouveau_drm_load(struct drm_device *dev, unsigned long flags)
 {
@@ -568,8 +537,6 @@ nouveau_drm_load(struct drm_device *dev, unsigned long flags)
        INIT_LIST_HEAD(&drm->clients);
        spin_lock_init(&drm->tile.lock);
-        nouveau_get_hdmi_dev(drm);
        /* workaround an odd issue on nvc1 by disabling the device's
         * nosnoop capability.  hopefully won't cause issues until a
         * better fix is found - assuming there is one...
@@ -655,8 +622,6 @@ nouveau_drm_unload(struct drm_device *dev)
        nouveau_ttm_fini(drm);
        nouveau_vga_fini(drm);
-        if (drm->hdmi_device)
-                pci_dev_put(drm->hdmi_device);
        nouveau_cli_fini(&drm->client);
        nouveau_cli_fini(&drm->master);
        kfree(drm);
@@ -856,7 +821,6 @@ nouveau_pmops_runtime_suspend(struct device *dev)
        }
        drm_kms_helper_poll_disable(drm_dev);
-        vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
        nouveau_switcheroo_optimus_dsm();
        ret = nouveau_do_suspend(drm_dev, true);
        pci_save_state(pdev);
@@ -891,7 +855,6 @@ nouveau_pmops_runtime_resume(struct device *dev)
        /* do magic */
        nvif_mask(&device->object, 0x088488, (1 << 25), (1 << 25));
-        vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
        drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
        /* Monitors may have been connected / disconnected during suspend */
@@ -913,15 +876,6 @@ nouveau_pmops_runtime_idle(struct device *dev)
                return -EBUSY;
        }
-        /* if we have a hdmi audio device - make sure it has a driver loaded */
-        if (drm->hdmi_device) {
-                if (!drm->hdmi_device->driver) {
-                        DRM_DEBUG_DRIVER("failing to power off - no HDMI audio driver loaded\n");
-                        pm_runtime_mark_last_busy(dev);
-                        return -EBUSY;
-                }
-        }
        list_for_each_entry(crtc, &drm->dev->mode_config.crtc_list, head) {
                if (crtc->enabled) {
                        DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
index 96f6bd8aee5d..881b44b89a01 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -208,7 +208,6 @@ struct nouveau_drm {
        bool have_disp_power_ref;
        struct dev_pm_domain vga_pm_domain;
-        struct pci_dev *hdmi_device;
 };
 static inline struct nouveau_drm *
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index 988048ebcc22..25682ff3449a 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -108,6 +108,15 @@ config DRM_PANEL_RASPBERRYPI_TOUCHSCREEN
          Pi 7" Touchscreen.  To compile this driver as a module,
          choose M here.
+config DRM_PANEL_RAYDIUM_RM68200
+        tristate "Raydium RM68200 720x1280 DSI video mode panel"
+        depends on OF
+        depends on DRM_MIPI_DSI
+        depends on BACKLIGHT_CLASS_DEVICE
+        help
+          Say Y here if you want to enable support for Raydium RM68200
+          720x1280 DSI video mode panel.
 config DRM_PANEL_SAMSUNG_S6E3HA2
        tristate "Samsung S6E3HA2 DSI video mode panel"
        depends on OF
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 3d2a88d0e965..f26efc11d746 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_DRM_PANEL_LG_LG4573) += panel-lg-lg4573.o
 obj-$(CONFIG_DRM_PANEL_ORISETECH_OTM8009A) += panel-orisetech-otm8009a.o
 obj-$(CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00) += panel-panasonic-vvx10f034n00.o
 obj-$(CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN) += panel-raspberrypi-touchscreen.o
+obj-$(CONFIG_DRM_PANEL_RAYDIUM_RM68200) += panel-raydium-rm68200.o
 obj-$(CONFIG_DRM_PANEL_SAMSUNG_LD9040) += panel-samsung-ld9040.o
 obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2) += panel-samsung-s6e3ha2.o
 obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03) += panel-samsung-s6e63j0x03.o
diff --git a/drivers/gpu/drm/panel/panel-ilitek-ili9322.c b/drivers/gpu/drm/panel/panel-ilitek-ili9322.c
index b4ec0ecff807..bd38bf4f1ba6 100644
--- a/drivers/gpu/drm/panel/panel-ilitek-ili9322.c
+++ b/drivers/gpu/drm/panel/panel-ilitek-ili9322.c
@@ -179,7 +179,7 @@ enum ili9322_input {
        ILI9322_INPUT_UNKNOWN = 0xc,
 };
-const char *ili9322_inputs[] = {
+static const char * const ili9322_inputs[] = {
        "8 bit serial RGB through",
        "8 bit serial RGB aligned",
        "8 bit serial RGB dummy 320x240",
@@ -340,7 +340,7 @@ static bool ili9322_writeable_reg(struct device *dev, unsigned int reg)
        return true;
 }
-const struct regmap_config ili9322_regmap_config = {
+static const struct regmap_config ili9322_regmap_config = {
        .reg_bits = 8,
        .val_bits = 8,
        .max_register = 0x44,
diff --git a/drivers/gpu/drm/panel/panel-lvds.c b/drivers/gpu/drm/panel/panel-lvds.c
index b5e3994f0aa8..5185819c5b79 100644
--- a/drivers/gpu/drm/panel/panel-lvds.c
+++ b/drivers/gpu/drm/panel/panel-lvds.c
@@ -1,5 +1,5 @@
 /*
- * rcar_du_crtc.c  --  R-Car Display Unit CRTCs
+ * Generic LVDS panel driver
 *
 * Copyright (C) 2016 Laurent Pinchart
 * Copyright (C) 2016 Renesas Electronics Corporation
diff --git a/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c b/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c
index c189cd6329c8..90f1ae4af93c 100644
--- a/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c
+++ b/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c
@@ -1,16 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
 * Copyright (C) STMicroelectronics SA 2017
 *
 * Authors: Philippe Cornu <philippe.cornu@st.com>
 *          Yannick Fertre <yannick.fertre@st.com>
- *
- * License terms:  GNU General Public License (GPL), version 2
 */
 #include <drm/drmP.h>
 #include <drm/drm_mipi_dsi.h>
 #include <drm/drm_panel.h>
 #include <linux/backlight.h>
 #include <linux/gpio/consumer.h>
+#include <linux/regulator/consumer.h>
 #include <video/mipi_display.h>
 #define DRV_NAME "orisetech_otm8009a"
@@ -62,6 +63,7 @@ struct otm8009a {
        struct drm_panel panel;
        struct backlight_device *bl_dev;
        struct gpio_desc *reset_gpio;
+        struct regulator *supply;
        bool prepared;
        bool enabled;
 };
@@ -279,6 +281,8 @@ static int otm8009a_unprepare(struct drm_panel *panel)
                msleep(20);
        }
+        regulator_disable(ctx->supply);
        ctx->prepared = false;
        return 0;
@@ -292,6 +296,12 @@ static int otm8009a_prepare(struct drm_panel *panel)
        if (ctx->prepared)
                return 0;
+        ret = regulator_enable(ctx->supply);
+        if (ret < 0) {
+                DRM_ERROR("failed to enable supply: %d\n", ret);
+                return ret;
+        }
        if (ctx->reset_gpio) {
                gpiod_set_value_cansleep(ctx->reset_gpio, 0);
                gpiod_set_value_cansleep(ctx->reset_gpio, 1);
@@ -414,6 +424,13 @@ static int otm8009a_probe(struct mipi_dsi_device *dsi)
                return PTR_ERR(ctx->reset_gpio);
        }
+        ctx->supply = devm_regulator_get(dev, "power");
+        if (IS_ERR(ctx->supply)) {
+                ret = PTR_ERR(ctx->supply);
+                dev_err(dev, "failed to request regulator: %d\n", ret);
+                return ret;
+        }
        mipi_dsi_set_drvdata(dsi, ctx);
        ctx->dev = dev;
diff --git a/drivers/gpu/drm/panel/panel-raydium-rm68200.c b/drivers/gpu/drm/panel/panel-raydium-rm68200.c
new file mode 100644
index 000000000000..77593533abcd
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-raydium-rm68200.c
@@ -0,0 +1,448 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ *
+ * Authors: Philippe Cornu <philippe.cornu@st.com>
+ *          Yannick Fertre <yannick.fertre@st.com>
+ */
+#include <linux/backlight.h>
+#include <linux/gpio/consumer.h>
+#include <linux/regulator/consumer.h>
+#include <video/mipi_display.h>
+#include <drm/drmP.h>
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_panel.h>
+/*** Manufacturer Command Set ***/
+#define MCS_CMD_MODE_SW         0xFE /* CMD Mode Switch */
+#define MCS_CMD1_UCS            0x00 /* User Command Set (UCS = CMD1) */
+#define MCS_CMD2_P0             0x01 /* Manufacture Command Set Page0 (CMD2 P0) */
+#define MCS_CMD2_P1             0x02 /* Manufacture Command Set Page1 (CMD2 P1) */
+#define MCS_CMD2_P2             0x03 /* Manufacture Command Set Page2 (CMD2 P2) */
+#define MCS_CMD2_P3             0x04 /* Manufacture Command Set Page3 (CMD2 P3) */
+/* CMD2 P0 commands (Display Options and Power) */
+#define MCS_STBCTR              0x12 /* TE1 Output Setting Zig-Zag Connection */
+#define MCS_SGOPCTR             0x16 /* Source Bias Current */
+#define MCS_SDCTR               0x1A /* Source Output Delay Time */
+#define MCS_INVCTR              0x1B /* Inversion Type */
+#define MCS_EXT_PWR_IC          0x24 /* External PWR IC Control */
+#define MCS_SETAVDD             0x27 /* PFM Control for AVDD Output */
+#define MCS_SETAVEE             0x29 /* PFM Control for AVEE Output */
+#define MCS_BT2CTR              0x2B /* DDVDL Charge Pump Control */
+#define MCS_BT3CTR              0x2F /* VGH Charge Pump Control */
+#define MCS_BT4CTR              0x34 /* VGL Charge Pump Control */
+#define MCS_VCMCTR              0x46 /* VCOM Output Level Control */
+#define MCS_SETVGN              0x52 /* VG M/S N Control */
+#define MCS_SETVGP              0x54 /* VG M/S P Control */
+#define MCS_SW_CTRL             0x5F /* Interface Control for PFM and MIPI */
+/* CMD2 P2 commands (GOA Timing Control) - no description in datasheet */
+#define GOA_VSTV1               0x00
+#define GOA_VSTV2               0x07
+#define GOA_VCLK1               0x0E
+#define GOA_VCLK2               0x17
+#define GOA_VCLK_OPT1           0x20
+#define GOA_BICLK1              0x2A
+#define GOA_BICLK2              0x37
+#define GOA_BICLK3              0x44
+#define GOA_BICLK4              0x4F
+#define GOA_BICLK_OPT1          0x5B
+#define GOA_BICLK_OPT2          0x60
+#define MCS_GOA_GPO1            0x6D
+#define MCS_GOA_GPO2            0x71
+#define MCS_GOA_EQ              0x74
+#define MCS_GOA_CLK_GALLON      0x7C
+#define MCS_GOA_FS_SEL0         0x7E
+#define MCS_GOA_FS_SEL1         0x87
+#define MCS_GOA_FS_SEL2         0x91
+#define MCS_GOA_FS_SEL3         0x9B
+#define MCS_GOA_BS_SEL0         0xAC
+#define MCS_GOA_BS_SEL1         0xB5
+#define MCS_GOA_BS_SEL2         0xBF
+#define MCS_GOA_BS_SEL3         0xC9
+#define MCS_GOA_BS_SEL4         0xD3
+/* CMD2 P3 commands (Gamma) */
+#define MCS_GAMMA_VP            0x60 /* Gamma VP1~VP16 */
+#define MCS_GAMMA_VN            0x70 /* Gamma VN1~VN16 */
+struct rm68200 {
+        struct device *dev;
+        struct drm_panel panel;
+        struct gpio_desc *reset_gpio;
+        struct regulator *supply;
+        struct backlight_device *backlight;
+        bool prepared;
+        bool enabled;
+};
+static const struct drm_display_mode default_mode = {
+        .clock = 52582,
+        .hdisplay = 720,
+        .hsync_start = 720 + 38,
+        .hsync_end = 720 + 38 + 8,
+        .htotal = 720 + 38 + 8 + 38,
+        .vdisplay = 1280,
+        .vsync_start = 1280 + 12,
+        .vsync_end = 1280 + 12 + 4,
+        .vtotal = 1280 + 12 + 4 + 12,
+        .vrefresh = 50,
+        .flags = 0,
+        .width_mm = 68,
+        .height_mm = 122,
+};
+static inline struct rm68200 *panel_to_rm68200(struct drm_panel *panel)
+{
+        return container_of(panel, struct rm68200, panel);
+}
+static void rm68200_dcs_write_buf(struct rm68200 *ctx, const void *data,
+                                  size_t len)
+{
+        struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+        int err;
+        err = mipi_dsi_dcs_write_buffer(dsi, data, len);
+        if (err < 0)
+                DRM_ERROR_RATELIMITED("MIPI DSI DCS write buffer failed: %d\n",
+                                      err);
+}
+static void rm68200_dcs_write_cmd(struct rm68200 *ctx, u8 cmd, u8 value)
+{
+        struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+        int err;
+        err = mipi_dsi_dcs_write(dsi, cmd, &value, 1);
+        if (err < 0)
+                DRM_ERROR_RATELIMITED("MIPI DSI DCS write failed: %d\n", err);
+}
+#define dcs_write_seq(ctx, seq...)                              \
+({                                                              \
+        static const u8 d[] = { seq };                          \
+                                                                \
+        rm68200_dcs_write_buf(ctx, d, ARRAY_SIZE(d));           \
+})
+/*
+ * This panel is not able to auto-increment all cmd addresses so for some of
+ * them, we need to send them one by one...
+ */
+#define dcs_write_cmd_seq(ctx, cmd, seq...)                     \
+({                                                              \
+        static const u8 d[] = { seq };                          \
+        unsigned int i;                                         \
+                                                                \
+        for (i = 0; i < ARRAY_SIZE(d) ; i++)                    \
+                rm68200_dcs_write_cmd(ctx, cmd + i, d[i]);      \
+})
+static void rm68200_init_sequence(struct rm68200 *ctx)
+{
+        /* Enter CMD2 with page 0 */
+        dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD2_P0);
+        dcs_write_cmd_seq(ctx, MCS_EXT_PWR_IC, 0xC0, 0x53, 0x00);
+        dcs_write_seq(ctx, MCS_BT2CTR, 0xE5);
+        dcs_write_seq(ctx, MCS_SETAVDD, 0x0A);
+        dcs_write_seq(ctx, MCS_SETAVEE, 0x0A);
+        dcs_write_seq(ctx, MCS_SGOPCTR, 0x52);
+        dcs_write_seq(ctx, MCS_BT3CTR, 0x53);
+        dcs_write_seq(ctx, MCS_BT4CTR, 0x5A);
+        dcs_write_seq(ctx, MCS_INVCTR, 0x00);
+        dcs_write_seq(ctx, MCS_STBCTR, 0x0A);
+        dcs_write_seq(ctx, MCS_SDCTR, 0x06);
+        dcs_write_seq(ctx, MCS_VCMCTR, 0x56);
+        dcs_write_seq(ctx, MCS_SETVGN, 0xA0, 0x00);
+        dcs_write_seq(ctx, MCS_SETVGP, 0xA0, 0x00);
+        dcs_write_seq(ctx, MCS_SW_CTRL, 0x11); /* 2 data lanes, see doc */
+        dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD2_P2);
+        dcs_write_seq(ctx, GOA_VSTV1, 0x05);
+        dcs_write_seq(ctx, 0x02, 0x0B);
+        dcs_write_seq(ctx, 0x03, 0x0F);
+        dcs_write_seq(ctx, 0x04, 0x7D, 0x00, 0x50);
+        dcs_write_cmd_seq(ctx, GOA_VSTV2, 0x05, 0x16, 0x0D, 0x11, 0x7D, 0x00,
+                          0x50);
+        dcs_write_cmd_seq(ctx, GOA_VCLK1, 0x07, 0x08, 0x01, 0x02, 0x00, 0x7D,
+                          0x00, 0x85, 0x08);
+        dcs_write_cmd_seq(ctx, GOA_VCLK2, 0x03, 0x04, 0x05, 0x06, 0x00, 0x7D,
+                          0x00, 0x85, 0x08);
+        dcs_write_seq(ctx, GOA_VCLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+                      0x00, 0x00, 0x00, 0x00);
+        dcs_write_cmd_seq(ctx, GOA_BICLK1, 0x07, 0x08);
+        dcs_write_seq(ctx, 0x2D, 0x01);
+        dcs_write_seq(ctx, 0x2F, 0x02, 0x00, 0x40, 0x05, 0x08, 0x54, 0x7D,
+                      0x00);
+        dcs_write_cmd_seq(ctx, GOA_BICLK2, 0x03, 0x04, 0x05, 0x06, 0x00);
+        dcs_write_seq(ctx, 0x3D, 0x40);
+        dcs_write_seq(ctx, 0x3F, 0x05, 0x08, 0x54, 0x7D, 0x00);
+        dcs_write_seq(ctx, GOA_BICLK3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+                      0x00, 0x00, 0x00, 0x00, 0x00);
+        dcs_write_seq(ctx, GOA_BICLK4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+                      0x00, 0x00);
+        dcs_write_seq(ctx, 0x58, 0x00, 0x00, 0x00);
+        dcs_write_seq(ctx, GOA_BICLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00);
+        dcs_write_seq(ctx, GOA_BICLK_OPT2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+                      0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
+        dcs_write_seq(ctx, MCS_GOA_GPO1, 0x00, 0x00, 0x00, 0x00);
+        dcs_write_seq(ctx, MCS_GOA_GPO2, 0x00, 0x20, 0x00);
+        dcs_write_seq(ctx, MCS_GOA_EQ, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
+                      0x00, 0x00);
+        dcs_write_seq(ctx, MCS_GOA_CLK_GALLON, 0x00, 0x00);
+        dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL0, 0xBF, 0x02, 0x06, 0x14, 0x10,
+                          0x16, 0x12, 0x08, 0x3F);
+        dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0C,
+                          0x0A, 0x0E, 0x3F, 0x3F, 0x00);
+        dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL2, 0x04, 0x3F, 0x3F, 0x3F, 0x3F,
+                          0x05, 0x01, 0x3F, 0x3F, 0x0F);
+        dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL3, 0x0B, 0x0D, 0x3F, 0x3F, 0x3F,
+                          0x3F);
+        dcs_write_cmd_seq(ctx, 0xA2, 0x3F, 0x09, 0x13, 0x17, 0x11, 0x15);
+        dcs_write_cmd_seq(ctx, 0xA9, 0x07, 0x03, 0x3F);
+        dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL0, 0x3F, 0x05, 0x01, 0x17, 0x13,
+                          0x15, 0x11, 0x0F, 0x3F);
+        dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0B,
+                          0x0D, 0x09, 0x3F, 0x3F, 0x07);
+        dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL2, 0x03, 0x3F, 0x3F, 0x3F, 0x3F,
+                          0x02, 0x06, 0x3F, 0x3F, 0x08);
+        dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL3, 0x0C, 0x0A, 0x3F, 0x3F, 0x3F,
+                          0x3F, 0x3F, 0x0E, 0x10, 0x14);
+        dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL4, 0x12, 0x16, 0x00, 0x04, 0x3F);
+        dcs_write_seq(ctx, 0xDC, 0x02);
+        dcs_write_seq(ctx, 0xDE, 0x12);
+        dcs_write_seq(ctx, MCS_CMD_MODE_SW, 0x0E); /* No documentation */
+        dcs_write_seq(ctx, 0x01, 0x75);
+        dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD2_P3);
+        dcs_write_cmd_seq(ctx, MCS_GAMMA_VP, 0x00, 0x0C, 0x12, 0x0E, 0x06,
+                          0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F,
+                          0x12, 0x0C, 0x00);
+        dcs_write_cmd_seq(ctx, MCS_GAMMA_VN, 0x00, 0x0C, 0x12, 0x0E, 0x06,
+                          0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F,
+                          0x12, 0x0C, 0x00);
+        /* Exit CMD2 */
+        dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD1_UCS);
+}
+static int rm68200_disable(struct drm_panel *panel)
+{
+        struct rm68200 *ctx = panel_to_rm68200(panel);
+        if (!ctx->enabled)
+                return 0;
+        backlight_disable(ctx->backlight);
+        ctx->enabled = false;
+        return 0;
+}
+static int rm68200_unprepare(struct drm_panel *panel)
+{
+        struct rm68200 *ctx = panel_to_rm68200(panel);
+        struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+        int ret;
+        if (!ctx->prepared)
+                return 0;
+        ret = mipi_dsi_dcs_set_display_off(dsi);
+        if (ret)
+                DRM_WARN("failed to set display off: %d\n", ret);
+        ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
+        if (ret)
+                DRM_WARN("failed to enter sleep mode: %d\n", ret);
+        msleep(120);
+        if (ctx->reset_gpio) {
+                gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+                msleep(20);
+        }
+        regulator_disable(ctx->supply);
+        ctx->prepared = false;
+        return 0;
+}
+static int rm68200_prepare(struct drm_panel *panel)
+{
+        struct rm68200 *ctx = panel_to_rm68200(panel);
+        struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+        int ret;
+        if (ctx->prepared)
+                return 0;
+        ret = regulator_enable(ctx->supply);
+        if (ret < 0) {
+                DRM_ERROR("failed to enable supply: %d\n", ret);
+                return ret;
+        }
+        if (ctx->reset_gpio) {
+                gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+                msleep(20);
+                gpiod_set_value_cansleep(ctx->reset_gpio, 0);
+                msleep(100);
+        }
+        rm68200_init_sequence(ctx);
+        ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
+        if (ret)
+                return ret;
+        msleep(125);
+        ret = mipi_dsi_dcs_set_display_on(dsi);
+        if (ret)
+                return ret;
+        msleep(20);
+        ctx->prepared = true;
+        return 0;
+}
+static int rm68200_enable(struct drm_panel *panel)
+{
+        struct rm68200 *ctx = panel_to_rm68200(panel);
+        if (ctx->enabled)
+                return 0;
+        backlight_enable(ctx->backlight);
+        ctx->enabled = true;
+        return 0;
+}
+static int rm68200_get_modes(struct drm_panel *panel)
+{
+        struct drm_display_mode *mode;
+        mode = drm_mode_duplicate(panel->drm, &default_mode);
+        if (!mode) {
+                DRM_ERROR("failed to add mode %ux%ux@%u\n",
+                          default_mode.hdisplay, default_mode.vdisplay,
+                          default_mode.vrefresh);
+                return -ENOMEM;
+        }
+        drm_mode_set_name(mode);
+        mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
+        drm_mode_probed_add(panel->connector, mode);
+        panel->connector->display_info.width_mm = mode->width_mm;
+        panel->connector->display_info.height_mm = mode->height_mm;
+        return 1;
+}
+static const struct drm_panel_funcs rm68200_drm_funcs = {
+        .disable = rm68200_disable,
+        .unprepare = rm68200_unprepare,
+        .prepare = rm68200_prepare,
+        .enable = rm68200_enable,
+        .get_modes = rm68200_get_modes,
+};
+static int rm68200_probe(struct mipi_dsi_device *dsi)
+{
+        struct device *dev = &dsi->dev;
+        struct rm68200 *ctx;
+        int ret;
+        ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
+        if (!ctx)
+                return -ENOMEM;
+        ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
+        if (IS_ERR(ctx->reset_gpio)) {
+                ret = PTR_ERR(ctx->reset_gpio);
+                dev_err(dev, "cannot get reset GPIO: %d\n", ret);
+                return ret;
+        }
+        ctx->supply = devm_regulator_get(dev, "power");
+        if (IS_ERR(ctx->supply)) {
+                ret = PTR_ERR(ctx->supply);
+                dev_err(dev, "cannot get regulator: %d\n", ret);
+                return ret;
+        }
+        ctx->backlight = devm_of_find_backlight(dev);
+        if (IS_ERR(ctx->backlight))
+                return PTR_ERR(ctx->backlight);
+        mipi_dsi_set_drvdata(dsi, ctx);
+        ctx->dev = dev;
+        dsi->lanes = 2;
+        dsi->format = MIPI_DSI_FMT_RGB888;
+        dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
+                          MIPI_DSI_MODE_LPM;
+        drm_panel_init(&ctx->panel);
+        ctx->panel.dev = dev;
+        ctx->panel.funcs = &rm68200_drm_funcs;
+        drm_panel_add(&ctx->panel);
+        ret = mipi_dsi_attach(dsi);
+        if (ret < 0) {
+                dev_err(dev, "mipi_dsi_attach() failed: %d\n", ret);
+                drm_panel_remove(&ctx->panel);
+                return ret;
+        }
+        return 0;
+}
+static int rm68200_remove(struct mipi_dsi_device *dsi)
+{
+        struct rm68200 *ctx = mipi_dsi_get_drvdata(dsi);
+        mipi_dsi_detach(dsi);
+        drm_panel_remove(&ctx->panel);
+        return 0;
+}
+static const struct of_device_id raydium_rm68200_of_match[] = {
+        { .compatible = "raydium,rm68200" },
+        { }
+};
+MODULE_DEVICE_TABLE(of, raydium_rm68200_of_match);
+static struct mipi_dsi_driver raydium_rm68200_driver = {
+        .probe = rm68200_probe,
+        .remove = rm68200_remove,
+        .driver = {
+                .name = "panel-raydium-rm68200",
+                .of_match_table = raydium_rm68200_of_match,
+        },
+};
+module_mipi_dsi_driver(raydium_rm68200_driver);
+MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
+MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
+MODULE_DESCRIPTION("DRM Driver for Raydium RM68200 MIPI DSI panel");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
index 5591984a392b..cbf1ab404ee7 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -581,6 +581,29 @@ static const struct panel_desc auo_b133htn01 = {
        },
 };
+static const struct drm_display_mode auo_g104sn02_mode = {
+        .clock = 40000,
+        .hdisplay = 800,
+        .hsync_start = 800 + 40,
+        .hsync_end = 800 + 40 + 216,
+        .htotal = 800 + 40 + 216 + 128,
+        .vdisplay = 600,
+        .vsync_start = 600 + 10,
+        .vsync_end = 600 + 10 + 35,
+        .vtotal = 600 + 10 + 35 + 2,
+        .vrefresh = 60,
+};
+static const struct panel_desc auo_g104sn02 = {
+        .modes = &auo_g104sn02_mode,
+        .num_modes = 1,
+        .bpc = 8,
+        .size = {
+                .width = 211,
+                .height = 158,
+        },
+};
 static const struct display_timing auo_g133han01_timings = {
        .pixelclock = { 134000000, 141200000, 149000000 },
        .hactive = { 1920, 1920, 1920 },
@@ -1217,6 +1240,30 @@ static const struct panel_desc innolux_zj070na_01p = {
        },
 };
+static const struct display_timing koe_tx31d200vm0baa_timing = {
+        .pixelclock = { 39600000, 43200000, 48000000 },
+        .hactive = { 1280, 1280, 1280 },
+        .hfront_porch = { 16, 36, 56 },
+        .hback_porch = { 16, 36, 56 },
+        .hsync_len = { 8, 8, 8 },
+        .vactive = { 480, 480, 480 },
+        .vfront_porch = { 6, 21, 33.5 },
+        .vback_porch = { 6, 21, 33.5 },
+        .vsync_len = { 8, 8, 8 },
+        .flags = DISPLAY_FLAGS_DE_HIGH,
+};
+static const struct panel_desc koe_tx31d200vm0baa = {
+        .timings = &koe_tx31d200vm0baa_timing,
+        .num_timings = 1,
+        .bpc = 6,
+        .size = {
+                .width = 292,
+                .height = 109,
+        },
+        .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
+};
 static const struct display_timing kyo_tcg121xglp_timing = {
        .pixelclock = { 52000000, 65000000, 71000000 },
        .hactive = { 1024, 1024, 1024 },
@@ -1597,7 +1644,7 @@ static const struct panel_desc ontat_yx700wv03 = {
                .width = 154,
                .height = 83,
        },
-        .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
+        .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
 };
 static const struct drm_display_mode ortustech_com43h4m85ulc_mode  = {
@@ -1741,23 +1788,22 @@ static const struct panel_desc sharp_lq101k1ly04 = {
        .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
 };
-static const struct drm_display_mode sharp_lq123p1jx31_mode = {
+static const struct display_timing sharp_lq123p1jx31_timing = {
-        .clock = 252750,
+        .pixelclock = { 252750000, 252750000, 266604720 },
-        .hdisplay = 2400,
+        .hactive = { 2400, 2400, 2400 },
-        .hsync_start = 2400 + 48,
+        .hfront_porch = { 48, 48, 48 },
-        .hsync_end = 2400 + 48 + 32,
+        .hback_porch = { 80, 80, 84 },
-        .htotal = 2400 + 48 + 32 + 80,
+        .hsync_len = { 32, 32, 32 },
-        .vdisplay = 1600,
+        .vactive = { 1600, 1600, 1600 },
-        .vsync_start = 1600 + 3,
+        .vfront_porch = { 3, 3, 3 },
-        .vsync_end = 1600 + 3 + 10,
+        .vback_porch = { 33, 33, 120 },
-        .vtotal = 1600 + 3 + 10 + 33,
+        .vsync_len = { 10, 10, 10 },
-        .vrefresh = 60,
+        .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
-        .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
 };
 static const struct panel_desc sharp_lq123p1jx31 = {
-        .modes = &sharp_lq123p1jx31_mode,
+        .timings = &sharp_lq123p1jx31_timing,
-        .num_modes = 1,
+        .num_timings = 1,
        .bpc = 8,
        .size = {
                .width = 259,
@@ -2049,6 +2095,9 @@ static const struct of_device_id platform_of_match[] = {
                .compatible = "auo,b133xtn01",
                .data = &auo_b133xtn01,
        }, {
+                .compatible = "auo,g104sn02",
+                .data = &auo_g104sn02,
+        }, {
                .compatible = "auo,g133han01",
                .data = &auo_g133han01,
        }, {
@@ -2124,6 +2173,9 @@ static const struct of_device_id platform_of_match[] = {
                .compatible = "innolux,zj070na-01p",
                .data = &innolux_zj070na_01p,
        }, {
+                .compatible = "koe,tx31d200vm0baa",
+                .data = &koe_tx31d200vm0baa,
+        }, {
                .compatible = "kyo,tcg121xglp",
                .data = &kyo_tcg121xglp,
        }, {
diff --git a/drivers/gpu/drm/qxl/qxl_display.c b/drivers/gpu/drm/qxl/qxl_display.c
index 9a9214ae0fb5..ecb35ed0eac8 100644
--- a/drivers/gpu/drm/qxl/qxl_display.c
+++ b/drivers/gpu/drm/qxl/qxl_display.c
@@ -309,7 +309,7 @@ void qxl_user_framebuffer_destroy(struct drm_framebuffer *fb)
        struct qxl_bo *bo = gem_to_qxl_bo(qxl_fb->obj);
        WARN_ON(bo->shadow);
-        drm_gem_object_unreference_unlocked(qxl_fb->obj);
+        drm_gem_object_put_unlocked(qxl_fb->obj);
        drm_framebuffer_cleanup(fb);
        kfree(qxl_fb);
 }
@@ -1215,7 +1215,7 @@ qxl_user_framebuffer_create(struct drm_device *dev,
        ret = qxl_framebuffer_init(dev, qxl_fb, mode_cmd, obj, &qxl_fb_funcs);
        if (ret) {
                kfree(qxl_fb);
-                drm_gem_object_unreference_unlocked(obj);
+                drm_gem_object_put_unlocked(obj);
                return NULL;
        }
diff --git a/drivers/gpu/drm/qxl/qxl_dumb.c b/drivers/gpu/drm/qxl/qxl_dumb.c
index 11085ab01374..c666b89eed5d 100644
--- a/drivers/gpu/drm/qxl/qxl_dumb.c
+++ b/drivers/gpu/drm/qxl/qxl_dumb.c
@@ -82,6 +82,6 @@ int qxl_mode_dumb_mmap(struct drm_file *file_priv,
                return -ENOENT;
        qobj = gem_to_qxl_bo(gobj);
        *offset_p = qxl_bo_mmap_offset(qobj);
-        drm_gem_object_unreference_unlocked(gobj);
+        drm_gem_object_put_unlocked(gobj);
        return 0;
 }
diff --git a/drivers/gpu/drm/qxl/qxl_fb.c b/drivers/gpu/drm/qxl/qxl_fb.c
index 23af3e352673..338891401f35 100644
--- a/drivers/gpu/drm/qxl/qxl_fb.c
+++ b/drivers/gpu/drm/qxl/qxl_fb.c
@@ -95,7 +95,7 @@ static void qxlfb_destroy_pinned_object(struct drm_gem_object *gobj)
        qxl_bo_kunmap(qbo);
        qxl_bo_unpin(qbo);
-        drm_gem_object_unreference_unlocked(gobj);
+        drm_gem_object_put_unlocked(gobj);
 }
 int qxl_get_handle_for_primary_fb(struct qxl_device *qdev,
@@ -316,11 +316,11 @@ out_unref:
                qxl_bo_unpin(qbo);
        }
        if (fb && ret) {
-                drm_gem_object_unreference_unlocked(gobj);
+                drm_gem_object_put_unlocked(gobj);
                drm_framebuffer_cleanup(fb);
                kfree(fb);
        }
-        drm_gem_object_unreference_unlocked(gobj);
+        drm_gem_object_put_unlocked(gobj);
        return ret;
 }
diff --git a/drivers/gpu/drm/qxl/qxl_gem.c b/drivers/gpu/drm/qxl/qxl_gem.c
index 85f546719adb..f5c1e7872e92 100644
--- a/drivers/gpu/drm/qxl/qxl_gem.c
+++ b/drivers/gpu/drm/qxl/qxl_gem.c
@@ -98,7 +98,7 @@ int qxl_gem_object_create_with_handle(struct qxl_device *qdev,
                return r;
        /* drop reference from allocate - handle holds it now */
        *qobj = gem_to_qxl_bo(gobj);
-        drm_gem_object_unreference_unlocked(gobj);
+        drm_gem_object_put_unlocked(gobj);
        return 0;
 }
diff --git a/drivers/gpu/drm/qxl/qxl_ioctl.c b/drivers/gpu/drm/qxl/qxl_ioctl.c
index e8c0b1037230..e238a1a2eca1 100644
--- a/drivers/gpu/drm/qxl/qxl_ioctl.c
+++ b/drivers/gpu/drm/qxl/qxl_ioctl.c
@@ -121,7 +121,7 @@ static int qxlhw_handle_to_bo(struct drm_file *file_priv, uint64_t handle,
        qobj = gem_to_qxl_bo(gobj);
        ret = qxl_release_list_add(release, qobj);
-        drm_gem_object_unreference_unlocked(gobj);
+        drm_gem_object_put_unlocked(gobj);
        if (ret)
                return ret;
@@ -343,7 +343,7 @@ out2:
        qxl_bo_unreserve(qobj);
 out:
-        drm_gem_object_unreference_unlocked(gobj);
+        drm_gem_object_put_unlocked(gobj);
        return ret;
 }
diff --git a/drivers/gpu/drm/qxl/qxl_object.c b/drivers/gpu/drm/qxl/qxl_object.c
index af62824ed4cc..6a30196e9d6c 100644
--- a/drivers/gpu/drm/qxl/qxl_object.c
+++ b/drivers/gpu/drm/qxl/qxl_object.c
@@ -211,13 +211,13 @@ void qxl_bo_unref(struct qxl_bo **bo)
        if ((*bo) == NULL)
                return;
-        drm_gem_object_unreference_unlocked(&(*bo)->gem_base);
+        drm_gem_object_put_unlocked(&(*bo)->gem_base);
        *bo = NULL;
 }
 struct qxl_bo *qxl_bo_ref(struct qxl_bo *bo)
 {
-        drm_gem_object_reference(&bo->gem_base);
+        drm_gem_object_get(&bo->gem_base);
        return bo;
 }
@@ -318,7 +318,7 @@ void qxl_bo_force_delete(struct qxl_device *qdev)
                list_del_init(&bo->list);
                mutex_unlock(&qdev->gem.mutex);
                /* this should unref the ttm bo */
-                drm_gem_object_unreference_unlocked(&bo->gem_base);
+                drm_gem_object_put_unlocked(&bo->gem_base);
        }
 }
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index 31dd04f6baa1..b28288a781ef 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -415,7 +415,6 @@ static int radeon_pmops_runtime_suspend(struct device *dev)
        drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
        drm_kms_helper_poll_disable(drm_dev);
-        vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
        ret = radeon_suspend_kms(drm_dev, false, false, false);
        pci_save_state(pdev);
@@ -452,7 +451,6 @@ static int radeon_pmops_runtime_resume(struct device *dev)
        ret = radeon_resume_kms(drm_dev, false, false);
        drm_kms_helper_poll_enable(drm_dev);
-        vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
        drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
        return 0;
 }
diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
index 7d76ff47028d..3e8bf79bea58 100644
--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -71,10 +71,6 @@ struct rockchip_dp_device {
        struct regmap            *grf;
        struct reset_control     *rst;
-        struct work_struct       psr_work;
-        struct mutex             psr_lock;
-        unsigned int             psr_state;
        const struct rockchip_dp_chip_data *data;
        struct analogix_dp_device *adp;
@@ -84,28 +80,13 @@ struct rockchip_dp_device {
 static void analogix_dp_psr_set(struct drm_encoder *encoder, bool enabled)
 {
        struct rockchip_dp_device *dp = to_dp(encoder);
+        int ret;
-        if (!analogix_dp_psr_supported(dp->adp))
+        if (!analogix_dp_psr_enabled(dp->adp))
                return;
        DRM_DEV_DEBUG(dp->dev, "%s PSR...\n", enabled ? "Entry" : "Exit");
-        mutex_lock(&dp->psr_lock);
-        if (enabled)
-                dp->psr_state = EDP_VSC_PSR_STATE_ACTIVE;
-        else
-                dp->psr_state = ~EDP_VSC_PSR_STATE_ACTIVE;
-        schedule_work(&dp->psr_work);
-        mutex_unlock(&dp->psr_lock);
-}
-static void analogix_dp_psr_work(struct work_struct *work)
-{
-        struct rockchip_dp_device *dp =
-                                container_of(work, typeof(*dp), psr_work);
-        int ret;
        ret = rockchip_drm_wait_vact_end(dp->encoder.crtc,
                                         PSR_WAIT_LINE_FLAG_TIMEOUT_MS);
        if (ret) {
@@ -113,12 +94,10 @@ static void analogix_dp_psr_work(struct work_struct *work)
                return;
        }
-        mutex_lock(&dp->psr_lock);
+        if (enabled)
-        if (dp->psr_state == EDP_VSC_PSR_STATE_ACTIVE)
                analogix_dp_enable_psr(dp->adp);
        else
                analogix_dp_disable_psr(dp->adp);
-        mutex_unlock(&dp->psr_lock);
 }
 static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
@@ -135,8 +114,6 @@ static int rockchip_dp_poweron(struct analogix_dp_plat_data *plat_data)
        struct rockchip_dp_device *dp = to_dp(plat_data);
        int ret;
-        cancel_work_sync(&dp->psr_work);
        ret = clk_prepare_enable(dp->pclk);
        if (ret < 0) {
                DRM_DEV_ERROR(dp->dev, "failed to enable pclk %d\n", ret);
@@ -355,10 +332,6 @@ static int rockchip_dp_bind(struct device *dev, struct device *master,
        dp->plat_data.power_off = rockchip_dp_powerdown;
        dp->plat_data.get_modes = rockchip_dp_get_modes;
-        mutex_init(&dp->psr_lock);
-        dp->psr_state = ~EDP_VSC_PSR_STATE_ACTIVE;
-        INIT_WORK(&dp->psr_work, analogix_dp_psr_work);
        ret = rockchip_drm_psr_register(&dp->encoder, analogix_dp_psr_set);
        if (ret < 0)
                goto err_cleanup_encoder;
diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c b/drivers/gpu/drm/rockchip/cdn-dp-core.c
index ec999d9f15f6..c6fbdcd87c16 100644
--- a/drivers/gpu/drm/rockchip/cdn-dp-core.c
+++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c
@@ -43,8 +43,6 @@
 #define GRF_SOC_CON9            0x6224
 #define DP_SEL_VOP_LIT          BIT(12)
 #define GRF_SOC_CON26           0x6268
-#define UPHY_SEL_BIT            3
-#define UPHY_SEL_MASK           BIT(19)
 #define DPTX_HPD_SEL            (3 << 12)
 #define DPTX_HPD_DEL            (2 << 12)
 #define DPTX_HPD_SEL_MASK       (3 << 28)
@@ -394,11 +392,6 @@ static int cdn_dp_enable_phy(struct cdn_dp_device *dp, struct cdn_dp_port *port)
        union extcon_property_value property;
        int ret;
-        ret = cdn_dp_grf_write(dp, GRF_SOC_CON26,
-                               (port->id << UPHY_SEL_BIT) | UPHY_SEL_MASK);
-        if (ret)
-                return ret;
        if (!port->phy_enabled) {
                ret = phy_power_on(port->phy);
                if (ret) {
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 158e79e5062e..53d4afe15278 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -117,6 +117,8 @@ struct vop {
        spinlock_t reg_lock;
        /* lock vop irq reg */
        spinlock_t irq_lock;
+        /* protects crtc enable/disable */
+        struct mutex vop_lock;
        unsigned int irq;
@@ -517,7 +519,10 @@ static int vop_enable(struct drm_crtc *crtc)
                goto err_disable_aclk;
        }
-        memcpy(vop->regs, vop->regsbak, vop->len);
+        spin_lock(&vop->reg_lock);
+        for (i = 0; i < vop->len; i += 4)
+                writel_relaxed(vop->regsbak[i / 4], vop->regs + i);
        /*
         * We need to make sure that all windows are disabled before we
         * enable the crtc. Otherwise we might try to scan from a destroyed
@@ -527,10 +532,9 @@ static int vop_enable(struct drm_crtc *crtc)
                struct vop_win *vop_win = &vop->win[i];
                const struct vop_win_data *win = vop_win->data;
-                spin_lock(&vop->reg_lock);
                VOP_WIN_SET(vop, win, enable, 0);
-                spin_unlock(&vop->reg_lock);
        }
+        spin_unlock(&vop->reg_lock);
        vop_cfg_done(vop);
@@ -569,6 +573,7 @@ static void vop_crtc_atomic_disable(struct drm_crtc *crtc,
        WARN_ON(vop->event);
+        mutex_lock(&vop->vop_lock);
        drm_crtc_vblank_off(crtc);
        /*
@@ -604,6 +609,7 @@ static void vop_crtc_atomic_disable(struct drm_crtc *crtc,
        clk_disable(vop->aclk);
        clk_disable(vop->hclk);
        pm_runtime_put(vop->dev);
+        mutex_unlock(&vop->vop_lock);
        if (crtc->state->event && !crtc->state->active) {
                spin_lock_irq(&crtc->dev->event_lock);
@@ -868,10 +874,13 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
        uint32_t pin_pol, val;
        int ret;
+        mutex_lock(&vop->vop_lock);
        WARN_ON(vop->event);
        ret = vop_enable(crtc);
        if (ret) {
+                mutex_unlock(&vop->vop_lock);
                DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret);
                return;
        }
@@ -935,6 +944,7 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
        clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
        VOP_REG_SET(vop, common, standby, 0);
+        mutex_unlock(&vop->vop_lock);
 }
 static bool vop_fs_irq_is_pending(struct vop *vop)
@@ -1137,15 +1147,14 @@ static void vop_handle_vblank(struct vop *vop)
 {
        struct drm_device *drm = vop->drm_dev;
        struct drm_crtc *crtc = &vop->crtc;
-        unsigned long flags;
-        spin_lock_irqsave(&drm->event_lock, flags);
+        spin_lock(&drm->event_lock);
        if (vop->event) {
                drm_crtc_send_vblank_event(crtc, vop->event);
                drm_crtc_vblank_put(crtc);
                vop->event = NULL;
        }
-        spin_unlock_irqrestore(&drm->event_lock, flags);
+        spin_unlock(&drm->event_lock);
        if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending))
                drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq);
@@ -1156,21 +1165,20 @@ static irqreturn_t vop_isr(int irq, void *data)
        struct vop *vop = data;
        struct drm_crtc *crtc = &vop->crtc;
        uint32_t active_irqs;
-        unsigned long flags;
        int ret = IRQ_NONE;
        /*
         * interrupt register has interrupt status, enable and clear bits, we
         * must hold irq_lock to avoid a race with enable/disable_vblank().
        */
-        spin_lock_irqsave(&vop->irq_lock, flags);
+        spin_lock(&vop->irq_lock);
        active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
        /* Clear all active interrupt sources */
        if (active_irqs)
                VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
-        spin_unlock_irqrestore(&vop->irq_lock, flags);
+        spin_unlock(&vop->irq_lock);
        /* This is expected for vop iommu irqs, since the irq is shared */
        if (!active_irqs)
@@ -1393,7 +1401,11 @@ static int vop_initial(struct vop *vop)
        usleep_range(10, 20);
        reset_control_deassert(ahb_rst);
-        memcpy(vop->regsbak, vop->regs, vop->len);
+        VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1);
+        VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0);
+        for (i = 0; i < vop->len; i += sizeof(u32))
+                vop->regsbak[i / 4] = readl_relaxed(vop->regs + i);
        VOP_REG_SET(vop, misc, global_regdone_en, 1);
        VOP_REG_SET(vop, common, dsp_blank, 0);
@@ -1473,15 +1485,21 @@ int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout)
 {
        struct vop *vop = to_vop(crtc);
        unsigned long jiffies_left;
+        int ret = 0;
        if (!crtc || !vop->is_enabled)
                return -ENODEV;
-        if (mstimeout <= 0)
+        mutex_lock(&vop->vop_lock);
-                return -EINVAL;
+        if (mstimeout <= 0) {
+                ret = -EINVAL;
+                goto out;
+        }
-        if (vop_line_flag_irq_is_enabled(vop))
+        if (vop_line_flag_irq_is_enabled(vop)) {
-                return -EBUSY;
+                ret = -EBUSY;
+                goto out;
+        }
        reinit_completion(&vop->line_flag_completion);
        vop_line_flag_irq_enable(vop);
@@ -1492,10 +1510,13 @@ int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout)
        if (jiffies_left == 0) {
                DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n");
-                return -ETIMEDOUT;
+                ret = -ETIMEDOUT;
+                goto out;
        }
-        return 0;
+out:
+        mutex_unlock(&vop->vop_lock);
+        return ret;
 }
 EXPORT_SYMBOL(rockchip_drm_wait_vact_end);
@@ -1545,18 +1566,11 @@ static int vop_bind(struct device *dev, struct device *master, void *data)
        spin_lock_init(&vop->reg_lock);
        spin_lock_init(&vop->irq_lock);
+        mutex_init(&vop->vop_lock);
-        ret = devm_request_irq(dev, vop->irq, vop_isr,
-                               IRQF_SHARED, dev_name(dev), vop);
-        if (ret)
-                return ret;
-        /* IRQ is initially disabled; it gets enabled in power_on */
-        disable_irq(vop->irq);
        ret = vop_create_crtc(vop);
        if (ret)
-                goto err_enable_irq;
+                return ret;
        pm_runtime_enable(&pdev->dev);
@@ -1567,13 +1581,19 @@ static int vop_bind(struct device *dev, struct device *master, void *data)
                goto err_disable_pm_runtime;
        }
+        ret = devm_request_irq(dev, vop->irq, vop_isr,
+                               IRQF_SHARED, dev_name(dev), vop);
+        if (ret)
+                goto err_disable_pm_runtime;
+        /* IRQ is initially disabled; it gets enabled in power_on */
+        disable_irq(vop->irq);
        return 0;
 err_disable_pm_runtime:
        pm_runtime_disable(&pdev->dev);
        vop_destroy_crtc(vop);
-err_enable_irq:
-        enable_irq(vop->irq); /* To balance out the disable_irq above */
        return ret;
 }
diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c b/drivers/gpu/drm/sun4i/sun4i_backend.c
index 092ade4ff6a5..9bad54f3de38 100644
--- a/drivers/gpu/drm/sun4i/sun4i_backend.c
+++ b/drivers/gpu/drm/sun4i/sun4i_backend.c
@@ -42,6 +42,56 @@ static const u32 sunxi_rgb2yuv_coef[12] = {
        0x000001c1, 0x00003e88, 0x00003fb8, 0x00000808
 };
+/*
+ * These coefficients are taken from the A33 BSP from Allwinner.
+ *
+ * The formula is for each component, each coefficient being multiplied by
+ * 1024 and each constant being multiplied by 16:
+ * G = 1.164 * Y - 0.391 * U - 0.813 * V + 135
+ * R = 1.164 * Y + 1.596 * V - 222
+ * B = 1.164 * Y + 2.018 * U + 276
+ *
+ * This seems to be a conversion from Y[16:235] UV[16:240] to RGB[0:255],
+ * following the BT601 spec.
+ */
+static const u32 sunxi_bt601_yuv2rgb_coef[12] = {
+        0x000004a7, 0x00001e6f, 0x00001cbf, 0x00000877,
+        0x000004a7, 0x00000000, 0x00000662, 0x00003211,
+        0x000004a7, 0x00000812, 0x00000000, 0x00002eb1,
+};
+static inline bool sun4i_backend_format_is_planar_yuv(uint32_t format)
+{
+        switch (format) {
+        case DRM_FORMAT_YUV411:
+        case DRM_FORMAT_YUV422:
+        case DRM_FORMAT_YUV444:
+                return true;
+        default:
+                return false;
+        }
+}
+static inline bool sun4i_backend_format_is_packed_yuv422(uint32_t format)
+{
+        switch (format) {
+        case DRM_FORMAT_YUYV:
+        case DRM_FORMAT_YVYU:
+        case DRM_FORMAT_UYVY:
+        case DRM_FORMAT_VYUY:
+                return true;
+        default:
+                return false;
+        }
+}
+static inline bool sun4i_backend_format_is_yuv(uint32_t format)
+{
+        return sun4i_backend_format_is_planar_yuv(format) ||
+                sun4i_backend_format_is_packed_yuv422(format);
+}
 static void sun4i_backend_apply_color_correction(struct sunxi_engine *engine)
 {
        int i;
@@ -166,6 +216,61 @@ int sun4i_backend_update_layer_coord(struct sun4i_backend *backend,
        return 0;
 }
+static int sun4i_backend_update_yuv_format(struct sun4i_backend *backend,
+                                           int layer, struct drm_plane *plane)
+{
+        struct drm_plane_state *state = plane->state;
+        struct drm_framebuffer *fb = state->fb;
+        uint32_t format = fb->format->format;
+        u32 val = SUN4I_BACKEND_IYUVCTL_EN;
+        int i;
+        for (i = 0; i < ARRAY_SIZE(sunxi_bt601_yuv2rgb_coef); i++)
+                regmap_write(backend->engine.regs,
+                             SUN4I_BACKEND_YGCOEF_REG(i),
+                             sunxi_bt601_yuv2rgb_coef[i]);
+        /*
+         * We should do that only for a single plane, but the
+         * framebuffer's atomic_check has our back on this.
+         */
+        regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer),
+                           SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN,
+                           SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN);
+        /* TODO: Add support for the multi-planar YUV formats */
+        if (sun4i_backend_format_is_packed_yuv422(format))
+                val |= SUN4I_BACKEND_IYUVCTL_FBFMT_PACKED_YUV422;
+        else
+                DRM_DEBUG_DRIVER("Unsupported YUV format (0x%x)\n", format);
+        /*
+         * Allwinner seems to list the pixel sequence from right to left, while
+         * DRM lists it from left to right.
+         */
+        switch (format) {
+        case DRM_FORMAT_YUYV:
+                val |= SUN4I_BACKEND_IYUVCTL_FBPS_VYUY;
+                break;
+        case DRM_FORMAT_YVYU:
+                val |= SUN4I_BACKEND_IYUVCTL_FBPS_UYVY;
+                break;
+        case DRM_FORMAT_UYVY:
+                val |= SUN4I_BACKEND_IYUVCTL_FBPS_YVYU;
+                break;
+        case DRM_FORMAT_VYUY:
+                val |= SUN4I_BACKEND_IYUVCTL_FBPS_YUYV;
+                break;
+        default:
+                DRM_DEBUG_DRIVER("Unsupported YUV pixel sequence (0x%x)\n",
+                                 format);
+        }
+        regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVCTL_REG, val);
+        return 0;
+}
 int sun4i_backend_update_layer_formats(struct sun4i_backend *backend,
                                       int layer, struct drm_plane *plane)
 {
@@ -175,6 +280,10 @@ int sun4i_backend_update_layer_formats(struct sun4i_backend *backend,
        u32 val;
        int ret;
+        /* Clear the YUV mode */
+        regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer),
+                           SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN, 0);
        if (plane->state->crtc)
                interlaced = plane->state->crtc->state->adjusted_mode.flags
                        & DRM_MODE_FLAG_INTERLACE;
@@ -186,6 +295,9 @@ int sun4i_backend_update_layer_formats(struct sun4i_backend *backend,
        DRM_DEBUG_DRIVER("Switching display backend interlaced mode %s\n",
                         interlaced ? "on" : "off");
+        if (sun4i_backend_format_is_yuv(fb->format->format))
+                return sun4i_backend_update_yuv_format(backend, layer, plane);
        ret = sun4i_backend_drm_format_to_layer(fb->format->format, &val);
        if (ret) {
                DRM_DEBUG_DRIVER("Invalid format\n");
@@ -223,6 +335,21 @@ int sun4i_backend_update_layer_frontend(struct sun4i_backend *backend,
        return 0;
 }
+static int sun4i_backend_update_yuv_buffer(struct sun4i_backend *backend,
+                                           struct drm_framebuffer *fb,
+                                           dma_addr_t paddr)
+{
+        /* TODO: Add support for the multi-planar YUV formats */
+        DRM_DEBUG_DRIVER("Setting packed YUV buffer address to %pad\n", &paddr);
+        regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVADD_REG(0), paddr);
+        DRM_DEBUG_DRIVER("Layer line width: %d bits\n", fb->pitches[0] * 8);
+        regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVLINEWIDTH_REG(0),
+                     fb->pitches[0] * 8);
+        return 0;
+}
 int sun4i_backend_update_layer_buffer(struct sun4i_backend *backend,
                                      int layer, struct drm_plane *plane)
 {
@@ -248,6 +375,9 @@ int sun4i_backend_update_layer_buffer(struct sun4i_backend *backend,
         */
        paddr -= PHYS_OFFSET;
+        if (sun4i_backend_format_is_yuv(fb->format->format))
+                return sun4i_backend_update_yuv_buffer(backend, fb, paddr);
        /* Write the 32 lower bits of the address (in bits) */
        lo_paddr = paddr << 3;
        DRM_DEBUG_DRIVER("Setting address lower bits to 0x%x\n", lo_paddr);
@@ -330,6 +460,7 @@ static int sun4i_backend_atomic_check(struct sunxi_engine *engine,
        unsigned int num_planes = 0;
        unsigned int num_alpha_planes = 0;
        unsigned int num_frontend_planes = 0;
+        unsigned int num_yuv_planes = 0;
        unsigned int current_pipe = 0;
        unsigned int i;
@@ -362,6 +493,11 @@ static int sun4i_backend_atomic_check(struct sunxi_engine *engine,
                if (fb->format->has_alpha)
                        num_alpha_planes++;
+                if (sun4i_backend_format_is_yuv(fb->format->format)) {
+                        DRM_DEBUG_DRIVER("Plane FB format is YUV\n");
+                        num_yuv_planes++;
+                }
                DRM_DEBUG_DRIVER("Plane zpos is %d\n",
                                 plane_state->normalized_zpos);
@@ -430,13 +566,20 @@ static int sun4i_backend_atomic_check(struct sunxi_engine *engine,
                s_state->pipe = current_pipe;
        }
+        /* We can only have a single YUV plane at a time */
+        if (num_yuv_planes > SUN4I_BACKEND_NUM_YUV_PLANES) {
+                DRM_DEBUG_DRIVER("Too many planes with YUV, rejecting...\n");
+                return -EINVAL;
+        }
        if (num_frontend_planes > SUN4I_BACKEND_NUM_FRONTEND_LAYERS) {
                DRM_DEBUG_DRIVER("Too many planes going through the frontend, rejecting\n");
                return -EINVAL;
        }
-        DRM_DEBUG_DRIVER("State valid with %u planes, %u alpha, %u video\n",
+        DRM_DEBUG_DRIVER("State valid with %u planes, %u alpha, %u video, %u YUV\n",
-                         num_planes, num_alpha_planes, num_frontend_planes);
+                         num_planes, num_alpha_planes, num_frontend_planes,
+                         num_yuv_planes);
        return 0;
 }
@@ -793,6 +936,9 @@ static const struct sun4i_backend_quirks sun7i_backend_quirks = {
 static const struct sun4i_backend_quirks sun8i_a33_backend_quirks = {
 };
+static const struct sun4i_backend_quirks sun9i_backend_quirks = {
+};
 static const struct of_device_id sun4i_backend_of_table[] = {
        {
                .compatible = "allwinner,sun4i-a10-display-backend",
@@ -814,6 +960,10 @@ static const struct of_device_id sun4i_backend_of_table[] = {
                .compatible = "allwinner,sun8i-a33-display-backend",
                .data = &sun8i_a33_backend_quirks,
        },
+        {
+                .compatible = "allwinner,sun9i-a80-display-backend",
+                .data = &sun9i_backend_quirks,
+        },
        { }
 };
 MODULE_DEVICE_TABLE(of, sun4i_backend_of_table);
diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.h b/drivers/gpu/drm/sun4i/sun4i_backend.h
index 52e77591186a..316f2179e9e1 100644
--- a/drivers/gpu/drm/sun4i/sun4i_backend.h
+++ b/drivers/gpu/drm/sun4i/sun4i_backend.h
@@ -72,6 +72,7 @@
 #define SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL(x)                ((x) << 15)
 #define SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL_MASK       GENMASK(11, 10)
 #define SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL(x)                 ((x) << 10)
+#define SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN             BIT(2)
 #define SUN4I_BACKEND_ATTCTL_REG0_LAY_VDOEN             BIT(1)
 #define SUN4I_BACKEND_ATTCTL_REG1(l)            (0x8a0 + (0x4 * (l)))
@@ -110,7 +111,23 @@
 #define SUN4I_BACKEND_SPREN_REG                 0x900
 #define SUN4I_BACKEND_SPRFMTCTL_REG             0x908
 #define SUN4I_BACKEND_SPRALPHACTL_REG           0x90c
 #define SUN4I_BACKEND_IYUVCTL_REG               0x920
+#define SUN4I_BACKEND_IYUVCTL_FBFMT_MASK                GENMASK(14, 12)
+#define SUN4I_BACKEND_IYUVCTL_FBFMT_PACKED_YUV444               (4 << 12)
+#define SUN4I_BACKEND_IYUVCTL_FBFMT_PACKED_YUV422               (3 << 12)
+#define SUN4I_BACKEND_IYUVCTL_FBFMT_PLANAR_YUV444               (2 << 12)
+#define SUN4I_BACKEND_IYUVCTL_FBFMT_PLANAR_YUV222               (1 << 12)
+#define SUN4I_BACKEND_IYUVCTL_FBFMT_PLANAR_YUV111               (0 << 12)
+#define SUN4I_BACKEND_IYUVCTL_FBPS_MASK                 GENMASK(9, 8)
+#define SUN4I_BACKEND_IYUVCTL_FBPS_YVYU                         (3 << 8)
+#define SUN4I_BACKEND_IYUVCTL_FBPS_VYUY                         (2 << 8)
+#define SUN4I_BACKEND_IYUVCTL_FBPS_YUYV                         (1 << 8)
+#define SUN4I_BACKEND_IYUVCTL_FBPS_UYVY                         (0 << 8)
+#define SUN4I_BACKEND_IYUVCTL_FBPS_VUYA                         (1 << 8)
+#define SUN4I_BACKEND_IYUVCTL_FBPS_AYUV                         (0 << 8)
+#define SUN4I_BACKEND_IYUVCTL_EN                        BIT(0)
 #define SUN4I_BACKEND_IYUVADD_REG(c)            (0x930 + (0x4 * (c)))
 #define SUN4I_BACKEND_IYUVLINEWIDTH_REG(c)      (0x940 + (0x4 * (c)))
@@ -149,6 +166,7 @@
 #define SUN4I_BACKEND_NUM_LAYERS                4
 #define SUN4I_BACKEND_NUM_ALPHA_LAYERS          1
 #define SUN4I_BACKEND_NUM_FRONTEND_LAYERS       1
+#define SUN4I_BACKEND_NUM_YUV_PLANES            1
 struct sun4i_backend {
        struct sunxi_engine     engine;
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c
index a0f43b81c64c..7f0705ef9f4e 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -176,7 +176,13 @@ static bool sun4i_drv_node_is_frontend(struct device_node *node)
                of_device_is_compatible(node, "allwinner,sun5i-a13-display-frontend") ||
                of_device_is_compatible(node, "allwinner,sun6i-a31-display-frontend") ||
                of_device_is_compatible(node, "allwinner,sun7i-a20-display-frontend") ||
-                of_device_is_compatible(node, "allwinner,sun8i-a33-display-frontend");
+                of_device_is_compatible(node, "allwinner,sun8i-a33-display-frontend") ||
+                of_device_is_compatible(node, "allwinner,sun9i-a80-display-frontend");
+}
+static bool sun4i_drv_node_is_deu(struct device_node *node)
+{
+        return of_device_is_compatible(node, "allwinner,sun9i-a80-deu");
 }
 static bool sun4i_drv_node_is_supported_frontend(struct device_node *node)
@@ -257,7 +263,8 @@ static int sun4i_drv_add_endpoints(struct device *dev,
         * enabled frontend supported by the driver, we add it to our
         * component list.
         */
-        if (!sun4i_drv_node_is_frontend(node) ||
+        if (!(sun4i_drv_node_is_frontend(node) ||
+              sun4i_drv_node_is_deu(node)) ||
            (sun4i_drv_node_is_supported_frontend(node) &&
             of_device_is_available(node))) {
                /* Add current component */
@@ -361,6 +368,7 @@ static const struct of_device_id sun4i_drv_of_table[] = {
        { .compatible = "allwinner,sun8i-a83t-display-engine" },
        { .compatible = "allwinner,sun8i-h3-display-engine" },
        { .compatible = "allwinner,sun8i-v3s-display-engine" },
+        { .compatible = "allwinner,sun9i-a80-display-engine" },
        { }
 };
 MODULE_DEVICE_TABLE(of, sun4i_drv_of_table);
diff --git a/drivers/gpu/drm/sun4i/sun4i_layer.c b/drivers/gpu/drm/sun4i/sun4i_layer.c
index 33ad377569ec..2949a3c912c1 100644
--- a/drivers/gpu/drm/sun4i/sun4i_layer.c
+++ b/drivers/gpu/drm/sun4i/sun4i_layer.c
@@ -134,7 +134,11 @@ static const uint32_t sun4i_backend_layer_formats[] = {
        DRM_FORMAT_RGBA4444,
        DRM_FORMAT_RGB888,
        DRM_FORMAT_RGB565,
+        DRM_FORMAT_UYVY,
+        DRM_FORMAT_VYUY,
        DRM_FORMAT_XRGB8888,
+        DRM_FORMAT_YUYV,
+        DRM_FORMAT_YVYU,
 };
 static struct sun4i_layer *sun4i_layer_init_one(struct drm_device *drm,
diff --git a/drivers/gpu/drm/sun4i/sun4i_lvds.c b/drivers/gpu/drm/sun4i/sun4i_lvds.c
index be3f14d7746d..bffff4c9fbf5 100644
--- a/drivers/gpu/drm/sun4i/sun4i_lvds.c
+++ b/drivers/gpu/drm/sun4i/sun4i_lvds.c
@@ -94,9 +94,64 @@ static void sun4i_lvds_encoder_disable(struct drm_encoder *encoder)
        }
 }
+static enum drm_mode_status sun4i_lvds_encoder_mode_valid(struct drm_encoder *crtc,
+                                                          const struct drm_display_mode *mode)
+{
+        struct sun4i_lvds *lvds = drm_encoder_to_sun4i_lvds(crtc);
+        struct sun4i_tcon *tcon = lvds->tcon;
+        u32 hsync = mode->hsync_end - mode->hsync_start;
+        u32 vsync = mode->vsync_end - mode->vsync_start;
+        unsigned long rate = mode->clock * 1000;
+        long rounded_rate;
+        DRM_DEBUG_DRIVER("Validating modes...\n");
+        if (hsync < 1)
+                return MODE_HSYNC_NARROW;
+        if (hsync > 0x3ff)
+                return MODE_HSYNC_WIDE;
+        if ((mode->hdisplay < 1) || (mode->htotal < 1))
+                return MODE_H_ILLEGAL;
+        if ((mode->hdisplay > 0x7ff) || (mode->htotal > 0xfff))
+                return MODE_BAD_HVALUE;
+        DRM_DEBUG_DRIVER("Horizontal parameters OK\n");
+        if (vsync < 1)
+                return MODE_VSYNC_NARROW;
+        if (vsync > 0x3ff)
+                return MODE_VSYNC_WIDE;
+        if ((mode->vdisplay < 1) || (mode->vtotal < 1))
+                return MODE_V_ILLEGAL;
+        if ((mode->vdisplay > 0x7ff) || (mode->vtotal > 0xfff))
+                return MODE_BAD_VVALUE;
+        DRM_DEBUG_DRIVER("Vertical parameters OK\n");
+        tcon->dclk_min_div = 7;
+        tcon->dclk_max_div = 7;
+        rounded_rate = clk_round_rate(tcon->dclk, rate);
+        if (rounded_rate < rate)
+                return MODE_CLOCK_LOW;
+        if (rounded_rate > rate)
+                return MODE_CLOCK_HIGH;
+        DRM_DEBUG_DRIVER("Clock rate OK\n");
+        return MODE_OK;
+}
 static const struct drm_encoder_helper_funcs sun4i_lvds_enc_helper_funcs = {
        .disable        = sun4i_lvds_encoder_disable,
        .enable         = sun4i_lvds_encoder_enable,
+        .mode_valid     = sun4i_lvds_encoder_mode_valid,
 };
 static const struct drm_encoder_funcs sun4i_lvds_enc_funcs = {
diff --git a/drivers/gpu/drm/sun4i/sun4i_rgb.c b/drivers/gpu/drm/sun4i/sun4i_rgb.c
index 832f8f9bc47f..a2a697a099e6 100644
--- a/drivers/gpu/drm/sun4i/sun4i_rgb.c
+++ b/drivers/gpu/drm/sun4i/sun4i_rgb.c
@@ -52,10 +52,10 @@ static int sun4i_rgb_get_modes(struct drm_connector *connector)
        return drm_panel_get_modes(tcon->panel);
 }
-static int sun4i_rgb_mode_valid(struct drm_connector *connector,
+static enum drm_mode_status sun4i_rgb_mode_valid(struct drm_encoder *crtc,
-                                struct drm_display_mode *mode)
+                                                 const struct drm_display_mode *mode)
 {
-        struct sun4i_rgb *rgb = drm_connector_to_sun4i_rgb(connector);
+        struct sun4i_rgb *rgb = drm_encoder_to_sun4i_rgb(crtc);
        struct sun4i_tcon *tcon = rgb->tcon;
        u32 hsync = mode->hsync_end - mode->hsync_start;
        u32 vsync = mode->vsync_end - mode->vsync_start;
@@ -106,7 +106,6 @@ static int sun4i_rgb_mode_valid(struct drm_connector *connector,
 static struct drm_connector_helper_funcs sun4i_rgb_con_helper_funcs = {
        .get_modes      = sun4i_rgb_get_modes,
-        .mode_valid     = sun4i_rgb_mode_valid,
 };
 static void
@@ -156,6 +155,7 @@ static void sun4i_rgb_encoder_disable(struct drm_encoder *encoder)
 static struct drm_encoder_helper_funcs sun4i_rgb_enc_helper_funcs = {
        .disable        = sun4i_rgb_encoder_disable,
        .enable         = sun4i_rgb_encoder_enable,
+        .mode_valid     = sun4i_rgb_mode_valid,
 };
 static void sun4i_rgb_enc_destroy(struct drm_encoder *encoder)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index 0d6c5ed44795..1a114e380f13 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -17,6 +17,7 @@
 #include <drm/drm_encoder.h>
 #include <drm/drm_modes.h>
 #include <drm/drm_of.h>
+#include <drm/drm_panel.h>
 #include <uapi/drm/drm_mode.h>
@@ -343,6 +344,9 @@ static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon,
 static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
                                     const struct drm_display_mode *mode)
 {
+        struct drm_panel *panel = tcon->panel;
+        struct drm_connector *connector = panel->connector;
+        struct drm_display_info display_info = connector->display_info;
        unsigned int bp, hsync, vsync;
        u8 clk_delay;
        u32 val = 0;
@@ -400,6 +404,27 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
        if (mode->flags & DRM_MODE_FLAG_PVSYNC)
                val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
+        /*
+         * On A20 and similar SoCs, the only way to achieve Positive Edge
+         * (Rising Edge), is setting dclk clock phase to 2/3(240°).
+         * By default TCON works in Negative Edge(Falling Edge),
+         * this is why phase is set to 0 in that case.
+         * Unfortunately there's no way to logically invert dclk through
+         * IO_POL register.
+         * The only acceptable way to work, triple checked with scope,
+         * is using clock phase set to 0° for Negative Edge and set to 240°
+         * for Positive Edge.
+         * On A33 and similar SoCs there would be a 90° phase option,
+         * but it divides also dclk by 2.
+         * Following code is a way to avoid quirks all around TCON
+         * and DOTCLOCK drivers.
+         */
+        if (display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_POSEDGE)
+                clk_set_phase(tcon->dclk, 240);
+        if (display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_NEGEDGE)
+                clk_set_phase(tcon->dclk, 0);
        regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG,
                           SUN4I_TCON0_IO_POL_HSYNC_POSITIVE | SUN4I_TCON0_IO_POL_VSYNC_POSITIVE,
                           val);
@@ -850,6 +875,7 @@ static int sun4i_tcon_bind(struct device *dev, struct device *master,
        struct sunxi_engine *engine;
        struct device_node *remote;
        struct sun4i_tcon *tcon;
+        struct reset_control *edp_rstc;
        bool has_lvds_rst, has_lvds_alt, can_lvds;
        int ret;
@@ -874,6 +900,20 @@ static int sun4i_tcon_bind(struct device *dev, struct device *master,
                return PTR_ERR(tcon->lcd_rst);
        }
+        if (tcon->quirks->needs_edp_reset) {
+                edp_rstc = devm_reset_control_get_shared(dev, "edp");
+                if (IS_ERR(edp_rstc)) {
+                        dev_err(dev, "Couldn't get edp reset line\n");
+                        return PTR_ERR(edp_rstc);
+                }
+                ret = reset_control_deassert(edp_rstc);
+                if (ret) {
+                        dev_err(dev, "Couldn't deassert edp reset line\n");
+                        return ret;
+                }
+        }
        /* Make sure our TCON is reset */
        ret = reset_control_reset(tcon->lcd_rst);
        if (ret) {
@@ -1166,6 +1206,16 @@ static const struct sun4i_tcon_quirks sun8i_v3s_quirks = {
        .has_channel_0          = true,
 };
+static const struct sun4i_tcon_quirks sun9i_a80_tcon_lcd_quirks = {
+        .has_channel_0  = true,
+        .needs_edp_reset = true,
+};
+static const struct sun4i_tcon_quirks sun9i_a80_tcon_tv_quirks = {
+        .has_channel_1  = true,
+        .needs_edp_reset = true,
+};
 /* sun4i_drv uses this list to check if a device node is a TCON */
 const struct of_device_id sun4i_tcon_of_table[] = {
        { .compatible = "allwinner,sun4i-a10-tcon", .data = &sun4i_a10_quirks },
@@ -1177,6 +1227,8 @@ const struct of_device_id sun4i_tcon_of_table[] = {
        { .compatible = "allwinner,sun8i-a83t-tcon-lcd", .data = &sun8i_a83t_lcd_quirks },
        { .compatible = "allwinner,sun8i-a83t-tcon-tv", .data = &sun8i_a83t_tv_quirks },
        { .compatible = "allwinner,sun8i-v3s-tcon", .data = &sun8i_v3s_quirks },
+        { .compatible = "allwinner,sun9i-a80-tcon-lcd", .data = &sun9i_a80_tcon_lcd_quirks },
+        { .compatible = "allwinner,sun9i-a80-tcon-tv", .data = &sun9i_a80_tcon_tv_quirks },
        { }
 };
 MODULE_DEVICE_TABLE(of, sun4i_tcon_of_table);
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h
index 78d55e7cd2b3..d3a945b7bb60 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
@@ -176,6 +176,7 @@ struct sun4i_tcon_quirks {
        bool    has_channel_1;  /* a33 does not have channel 1 */
        bool    has_lvds_alt;   /* Does the LVDS clock have a parent other than the TCON clock? */
        bool    needs_de_be_mux; /* sun6i needs mux to select backend */
+        bool    needs_edp_reset; /* a80 edp reset needed for tcon0 access */
        /* callback to handle tcon muxing options */
        int     (*set_mux)(struct sun4i_tcon *, const struct drm_encoder *);
diff --git a/drivers/gpu/drm/sun4i/sun6i_drc.c b/drivers/gpu/drm/sun4i/sun6i_drc.c
index 09bba853e2a4..b5e071a49045 100644
--- a/drivers/gpu/drm/sun4i/sun6i_drc.c
+++ b/drivers/gpu/drm/sun4i/sun6i_drc.c
@@ -101,6 +101,7 @@ static const struct of_device_id sun6i_drc_of_table[] = {
        { .compatible = "allwinner,sun6i-a31-drc" },
        { .compatible = "allwinner,sun6i-a31s-drc" },
        { .compatible = "allwinner,sun8i-a33-drc" },
+        { .compatible = "allwinner,sun9i-a80-drc" },
        { }
 };
 MODULE_DEVICE_TABLE(of, sun6i_drc_of_table);
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index ce1e3b9e14c9..bf4667481935 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -643,9 +643,12 @@ static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
 {
        struct drm_device *dev = crtc->dev;
        struct vc4_dev *vc4 = to_vc4_dev(dev);
+        struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
        struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
        struct drm_plane *plane;
+        struct vc4_plane_state *vc4_plane_state;
        bool debug_dump_regs = false;
+        bool enable_bg_fill = false;
        u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
        u32 __iomem *dlist_next = dlist_start;
@@ -656,6 +659,20 @@ static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
        /* Copy all the active planes' dlist contents to the hardware dlist. */
        drm_atomic_crtc_for_each_plane(plane, crtc) {
+                /* Is this the first active plane? */
+                if (dlist_next == dlist_start) {
+                        /* We need to enable background fill when a plane
+                         * could be alpha blending from the background, i.e.
+                         * where no other plane is underneath. It suffices to
+                         * consider the first active plane here since we set
+                         * needs_bg_fill such that either the first plane
+                         * already needs it or all planes on top blend from
+                         * the first or a lower plane.
+                         */
+                        vc4_plane_state = to_vc4_plane_state(plane->state);
+                        enable_bg_fill = vc4_plane_state->needs_bg_fill;
+                }
                dlist_next += vc4_plane_write_dlist(plane, dlist_next);
        }
@@ -664,6 +681,14 @@ static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
        WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
+        if (enable_bg_fill)
+                /* This sets a black background color fill, as is the case
+                 * with other DRM drivers.
+                 */
+                HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
+                          HVS_READ(SCALER_DISPBKGNDX(vc4_crtc->channel)) |
+                          SCALER_DISPBKGND_FILL);
        /* Only update DISPLIST if the CRTC was already running and is not
         * being disabled.
         * vc4_crtc_enable() takes care of updating the dlist just after
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index fefa1664a9f5..1b4cd1fabf56 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -310,6 +310,66 @@ to_vc4_plane(struct drm_plane *plane)
        return (struct vc4_plane *)plane;
 }
+enum vc4_scaling_mode {
+        VC4_SCALING_NONE,
+        VC4_SCALING_TPZ,
+        VC4_SCALING_PPF,
+};
+struct vc4_plane_state {
+        struct drm_plane_state base;
+        /* System memory copy of the display list for this element, computed
+         * at atomic_check time.
+         */
+        u32 *dlist;
+        u32 dlist_size; /* Number of dwords allocated for the display list */
+        u32 dlist_count; /* Number of used dwords in the display list. */
+        /* Offset in the dlist to various words, for pageflip or
+         * cursor updates.
+         */
+        u32 pos0_offset;
+        u32 pos2_offset;
+        u32 ptr0_offset;
+        /* Offset where the plane's dlist was last stored in the
+         * hardware at vc4_crtc_atomic_flush() time.
+         */
+        u32 __iomem *hw_dlist;
+        /* Clipped coordinates of the plane on the display. */
+        int crtc_x, crtc_y, crtc_w, crtc_h;
+        /* Clipped area being scanned from in the FB. */
+        u32 src_x, src_y;
+        u32 src_w[2], src_h[2];
+        /* Scaling selection for the RGB/Y plane and the Cb/Cr planes. */
+        enum vc4_scaling_mode x_scaling[2], y_scaling[2];
+        bool is_unity;
+        bool is_yuv;
+        /* Offset to start scanning out from the start of the plane's
+         * BO.
+         */
+        u32 offsets[3];
+        /* Our allocation in LBM for temporary storage during scaling. */
+        struct drm_mm_node lbm;
+        /* Set when the plane has per-pixel alpha content or does not cover
+         * the entire screen. This is a hint to the CRTC that it might need
+         * to enable background color fill.
+         */
+        bool needs_bg_fill;
+};
+static inline struct vc4_plane_state *
+to_vc4_plane_state(struct drm_plane_state *state)
+{
+        return (struct vc4_plane_state *)state;
+}
 enum vc4_encoder_type {
        VC4_ENCODER_TYPE_NONE,
        VC4_ENCODER_TYPE_HDMI,
diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
index c4c7af11fec5..ce39390be389 100644
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
@@ -27,60 +27,6 @@
 #include "vc4_drv.h"
 #include "vc4_regs.h"
-enum vc4_scaling_mode {
-        VC4_SCALING_NONE,
-        VC4_SCALING_TPZ,
-        VC4_SCALING_PPF,
-};
-struct vc4_plane_state {
-        struct drm_plane_state base;
-        /* System memory copy of the display list for this element, computed
-         * at atomic_check time.
-         */
-        u32 *dlist;
-        u32 dlist_size; /* Number of dwords allocated for the display list */
-        u32 dlist_count; /* Number of used dwords in the display list. */
-        /* Offset in the dlist to various words, for pageflip or
-         * cursor updates.
-         */
-        u32 pos0_offset;
-        u32 pos2_offset;
-        u32 ptr0_offset;
-        /* Offset where the plane's dlist was last stored in the
-         * hardware at vc4_crtc_atomic_flush() time.
-         */
-        u32 __iomem *hw_dlist;
-        /* Clipped coordinates of the plane on the display. */
-        int crtc_x, crtc_y, crtc_w, crtc_h;
-        /* Clipped area being scanned from in the FB. */
-        u32 src_x, src_y;
-        u32 src_w[2], src_h[2];
-        /* Scaling selection for the RGB/Y plane and the Cb/Cr planes. */
-        enum vc4_scaling_mode x_scaling[2], y_scaling[2];
-        bool is_unity;
-        bool is_yuv;
-        /* Offset to start scanning out from the start of the plane's
-         * BO.
-         */
-        u32 offsets[3];
-        /* Our allocation in LBM for temporary storage during scaling. */
-        struct drm_mm_node lbm;
-};
-static inline struct vc4_plane_state *
-to_vc4_plane_state(struct drm_plane_state *state)
-{
-        return (struct vc4_plane_state *)state;
-}
 static const struct hvs_format {
        u32 drm; /* DRM_FORMAT_* */
        u32 hvs; /* HVS_FORMAT_* */
@@ -521,6 +467,7 @@ static int vc4_plane_mode_set(struct drm_plane *plane,
        u32 ctl0_offset = vc4_state->dlist_count;
        const struct hvs_format *format = vc4_get_hvs_format(fb->format->format);
        int num_planes = drm_format_num_planes(format->drm);
+        bool covers_screen;
        u32 scl0, scl1, pitch0;
        u32 lbm_size, tiling;
        unsigned long irqflags;
@@ -618,13 +565,14 @@ static int vc4_plane_mode_set(struct drm_plane *plane,
                                              SCALER_POS1_SCL_HEIGHT));
        }
-        /* Position Word 2: Source Image Size, Alpha Mode */
+        /* Position Word 2: Source Image Size, Alpha */
        vc4_state->pos2_offset = vc4_state->dlist_count;
        vc4_dlist_write(vc4_state,
                        VC4_SET_FIELD(fb->format->has_alpha ?
                                      SCALER_POS2_ALPHA_MODE_PIPELINE :
                                      SCALER_POS2_ALPHA_MODE_FIXED,
                                      SCALER_POS2_ALPHA_MODE) |
+                        (fb->format->has_alpha ? SCALER_POS2_ALPHA_PREMULT : 0) |
                        VC4_SET_FIELD(vc4_state->src_w[0], SCALER_POS2_WIDTH) |
                        VC4_SET_FIELD(vc4_state->src_h[0], SCALER_POS2_HEIGHT));
@@ -700,6 +648,16 @@ static int vc4_plane_mode_set(struct drm_plane *plane,
        vc4_state->dlist[ctl0_offset] |=
                VC4_SET_FIELD(vc4_state->dlist_count, SCALER_CTL0_SIZE);
+        /* crtc_* are already clipped coordinates. */
+        covers_screen = vc4_state->crtc_x == 0 && vc4_state->crtc_y == 0 &&
+                        vc4_state->crtc_w == state->crtc->mode.hdisplay &&
+                        vc4_state->crtc_h == state->crtc->mode.vdisplay;
+        /* Background fill might be necessary when the plane has per-pixel
+         * alpha content and blends from the background or does not cover
+         * the entire screen.
+         */
+        vc4_state->needs_bg_fill = fb->format->has_alpha || !covers_screen;
        return 0;
 }
diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h
index b9749cb24063..a141496104a6 100644
--- a/drivers/gpu/drm/vc4/vc4_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_regs.h
@@ -848,6 +848,7 @@ enum hvs_pixel_format {
 #define SCALER_POS2_ALPHA_MODE_FIXED            1
 #define SCALER_POS2_ALPHA_MODE_FIXED_NONZERO    2
 #define SCALER_POS2_ALPHA_MODE_FIXED_OVER_0x07  3
+#define SCALER_POS2_ALPHA_PREMULT               BIT(29)
 #define SCALER_POS2_HEIGHT_MASK                 VC4_MASK(27, 16)
 #define SCALER_POS2_HEIGHT_SHIFT                16
diff --git a/drivers/gpu/drm/vc4/vc4_validate.c b/drivers/gpu/drm/vc4/vc4_validate.c
index 2db485abb186..eec76af49f04 100644
--- a/drivers/gpu/drm/vc4/vc4_validate.c
+++ b/drivers/gpu/drm/vc4/vc4_validate.c
@@ -753,7 +753,7 @@ validate_gl_shader_rec(struct drm_device *dev,
                28, /* cs */
        };
        uint32_t shader_reloc_count = ARRAY_SIZE(shader_reloc_offsets);
-        struct drm_gem_cma_object *bo[shader_reloc_count + 8];
+        struct drm_gem_cma_object *bo[ARRAY_SIZE(shader_reloc_offsets) + 8];
        uint32_t nr_attributes, nr_relocs, packet_size;
        int i;
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c b/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c
index be40cff3e1f6..2582ffd36bb5 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c
@@ -518,7 +518,7 @@ static int vmw_fb_kms_detach(struct vmw_fb_par *par,
        }
        if (cur_fb) {
-                drm_framebuffer_unreference(cur_fb);
+                drm_framebuffer_put(cur_fb);
                par->set_fb = NULL;
        }
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c b/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
index 67f844678ac8..c5e8eae0dbe2 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
@@ -316,7 +316,7 @@ int vmw_present_ioctl(struct drm_device *dev, void *data,
 out_no_surface:
        ttm_read_unlock(&dev_priv->reservation_sem);
 out_no_ttm_lock:
-        drm_framebuffer_unreference(fb);
+        drm_framebuffer_put(fb);
 out_no_fb:
        drm_modeset_unlock_all(dev);
 out_no_copy:
@@ -393,7 +393,7 @@ int vmw_present_readback_ioctl(struct drm_device *dev, void *data,
        ttm_read_unlock(&dev_priv->reservation_sem);
 out_no_ttm_lock:
-        drm_framebuffer_unreference(fb);
+        drm_framebuffer_put(fb);
 out_no_fb:
        drm_modeset_unlock_all(dev);
 out_no_copy:
diff --git a/drivers/gpu/vga/vga_switcheroo.c b/drivers/gpu/vga/vga_switcheroo.c
index 3cd153c6d271..fc4adf3d34e8 100644
--- a/drivers/gpu/vga/vga_switcheroo.c
+++ b/drivers/gpu/vga/vga_switcheroo.c
@@ -92,7 +92,8 @@
 * struct vga_switcheroo_client - registered client
 * @pdev: client pci device
 * @fb_info: framebuffer to which console is remapped on switching
- * @pwr_state: current power state
+ * @pwr_state: current power state if manual power control is used.
+ *      For driver power control, call vga_switcheroo_pwr_state().
 * @ops: client callbacks
 * @id: client identifier. Determining the id requires the handler,
 *      so gpus are initially assigned VGA_SWITCHEROO_UNKNOWN_ID
@@ -104,8 +105,7 @@
 * @list: client list
 *
 * Registered client. A client can be either a GPU or an audio device on a GPU.
- * For audio clients, the @fb_info, @active and @driver_power_control members
+ * For audio clients, the @fb_info and @active members are bogus.
- * are bogus.
 */
 struct vga_switcheroo_client {
        struct pci_dev *pdev;
@@ -331,8 +331,8 @@ EXPORT_SYMBOL(vga_switcheroo_register_client);
 * @ops: client callbacks
 * @id: client identifier
 *
- * Register audio client (audio device on a GPU). The power state of the
+ * Register audio client (audio device on a GPU). The client is assumed
- * client is assumed to be ON. Beforehand, vga_switcheroo_client_probe_defer()
+ * to use runtime PM. Beforehand, vga_switcheroo_client_probe_defer()
 * shall be called to ensure that all prerequisites are met.
 *
 * Return: 0 on success, -ENOMEM on memory allocation error.
@@ -341,7 +341,7 @@ int vga_switcheroo_register_audio_client(struct pci_dev *pdev,
                        const struct vga_switcheroo_client_ops *ops,
                        enum vga_switcheroo_client_id id)
 {
-        return register_client(pdev, ops, id | ID_BIT_AUDIO, false, false);
+        return register_client(pdev, ops, id | ID_BIT_AUDIO, false, true);
 }
 EXPORT_SYMBOL(vga_switcheroo_register_audio_client);
@@ -406,6 +406,19 @@ bool vga_switcheroo_client_probe_defer(struct pci_dev *pdev)
 }
 EXPORT_SYMBOL(vga_switcheroo_client_probe_defer);
+static enum vga_switcheroo_state
+vga_switcheroo_pwr_state(struct vga_switcheroo_client *client)
+{
+        if (client->driver_power_control)
+                if (pm_runtime_enabled(&client->pdev->dev) &&
+                    pm_runtime_active(&client->pdev->dev))
+                        return VGA_SWITCHEROO_ON;
+                else
+                        return VGA_SWITCHEROO_OFF;
+        else
+                return client->pwr_state;
+}
 /**
 * vga_switcheroo_get_client_state() - obtain power state of a given client
 * @pdev: client pci device
@@ -425,7 +438,7 @@ enum vga_switcheroo_state vga_switcheroo_get_client_state(struct pci_dev *pdev)
        if (!client)
                ret = VGA_SWITCHEROO_NOT_FOUND;
        else
-                ret = client->pwr_state;
+                ret = vga_switcheroo_pwr_state(client);
        mutex_unlock(&vgasr_mutex);
        return ret;
 }
@@ -598,7 +611,7 @@ static int vga_switcheroo_show(struct seq_file *m, void *v)
                           client_is_vga(client) ? "" : "-Audio",
                           client->active ? '+' : ' ',
                           client->driver_power_control ? "Dyn" : "",
-                           client->pwr_state ? "Pwr" : "Off",
+                           vga_switcheroo_pwr_state(client) ? "Pwr" : "Off",
                           pci_name(client->pdev));
                i++;
        }
@@ -641,10 +654,8 @@ static void set_audio_state(enum vga_switcheroo_client_id id,
        struct vga_switcheroo_client *client;
        client = find_client_from_id(&vgasr_priv.clients, id | ID_BIT_AUDIO);
-        if (client && client->pwr_state != state) {
+        if (client)
                client->ops->set_gpu_state(client->pdev, state);
-                client->pwr_state = state;
-        }
 }
 /* stage one happens before delay */
@@ -656,7 +667,7 @@ static int vga_switchto_stage1(struct vga_switcheroo_client *new_client)
        if (!active)
                return 0;
-        if (new_client->pwr_state == VGA_SWITCHEROO_OFF)
+        if (vga_switcheroo_pwr_state(new_client) == VGA_SWITCHEROO_OFF)
                vga_switchon(new_client);
        vga_set_default_device(new_client->pdev);
@@ -675,7 +686,9 @@ static int vga_switchto_stage2(struct vga_switcheroo_client *new_client)
        active->active = false;
-        set_audio_state(active->id, VGA_SWITCHEROO_OFF);
+        /* let HDA controller autosuspend if GPU uses driver power control */
+        if (!active->driver_power_control)
+                set_audio_state(active->id, VGA_SWITCHEROO_OFF);
        if (new_client->fb_info) {
                struct fb_event event;
@@ -695,10 +708,12 @@ static int vga_switchto_stage2(struct vga_switcheroo_client *new_client)
        if (new_client->ops->reprobe)
                new_client->ops->reprobe(new_client->pdev);
-        if (active->pwr_state == VGA_SWITCHEROO_ON)
+        if (vga_switcheroo_pwr_state(active) == VGA_SWITCHEROO_ON)
                vga_switchoff(active);
-        set_audio_state(new_client->id, VGA_SWITCHEROO_ON);
+        /* let HDA controller autoresume if GPU uses driver power control */
+        if (!new_client->driver_power_control)
+                set_audio_state(new_client->id, VGA_SWITCHEROO_ON);
        new_client->active = true;
        return 0;
@@ -939,11 +954,6 @@ EXPORT_SYMBOL(vga_switcheroo_process_delayed_switch);
 * Specifying nouveau.runpm=0, radeon.runpm=0 or amdgpu.runpm=0 on the kernel
 * command line disables it.
 *
- * When the driver decides to power up or down, it notifies vga_switcheroo
- * thereof so that it can (a) power the audio device on the GPU up or down,
- * and (b) update its internal power state representation for the device.
- * This is achieved by vga_switcheroo_set_dynamic_switch().
- *
 * After the GPU has been suspended, the handler needs to be called to cut
 * power to the GPU. Likewise it needs to reinstate power before the GPU
 * can resume. This is achieved by vga_switcheroo_init_domain_pm_ops(),
@@ -951,8 +961,9 @@ EXPORT_SYMBOL(vga_switcheroo_process_delayed_switch);
 * calls to the handler.
 *
 * When the audio device resumes, the GPU needs to be woken. This is achieved
- * by vga_switcheroo_init_domain_pm_optimus_hdmi_audio(), which augments the
+ * by a PCI quirk which calls device_link_add() to declare a dependency on the
- * audio device's resume function.
+ * GPU. That way, the GPU is kept awake whenever and as long as the audio
+ * device is in use.
 *
 * On muxed machines, if the mux is initially switched to the discrete GPU,
 * the user ends up with a black screen when the GPU powers down after boot.
@@ -978,35 +989,6 @@ static void vga_switcheroo_power_switch(struct pci_dev *pdev,
        vgasr_priv.handler->power_state(client->id, state);
 }
-/**
- * vga_switcheroo_set_dynamic_switch() - helper for driver power control
- * @pdev: client pci device
- * @dynamic: new power state
- *
- * Helper for GPUs whose power state is controlled by the driver's runtime pm.
- * When the driver decides to power up or down, it notifies vga_switcheroo
- * thereof using this helper so that it can (a) power the audio device on
- * the GPU up or down, and (b) update its internal power state representation
- * for the device.
- */
-void vga_switcheroo_set_dynamic_switch(struct pci_dev *pdev,
-                                       enum vga_switcheroo_state dynamic)
-{
-        struct vga_switcheroo_client *client;
-        mutex_lock(&vgasr_mutex);
-        client = find_client_from_pci(&vgasr_priv.clients, pdev);
-        if (!client || !client->driver_power_control) {
-                mutex_unlock(&vgasr_mutex);
-                return;
-        }
-        client->pwr_state = dynamic;
-        set_audio_state(client->id, dynamic);
-        mutex_unlock(&vgasr_mutex);
-}
-EXPORT_SYMBOL(vga_switcheroo_set_dynamic_switch);
 /* switcheroo power domain */
 static int vga_switcheroo_runtime_suspend(struct device *dev)
 {
@@ -1022,6 +1004,7 @@ static int vga_switcheroo_runtime_suspend(struct device *dev)
                vgasr_priv.handler->switchto(VGA_SWITCHEROO_IGD);
                mutex_unlock(&vgasr_priv.mux_hw_lock);
        }
+        pci_bus_set_current_state(pdev->bus, PCI_D3cold);
        vga_switcheroo_power_switch(pdev, VGA_SWITCHEROO_OFF);
        mutex_unlock(&vgasr_mutex);
        return 0;
@@ -1035,6 +1018,7 @@ static int vga_switcheroo_runtime_resume(struct device *dev)
        mutex_lock(&vgasr_mutex);
        vga_switcheroo_power_switch(pdev, VGA_SWITCHEROO_ON);
        mutex_unlock(&vgasr_mutex);
+        pci_wakeup_bus(pdev->bus);
        ret = dev->bus->pm->runtime_resume(dev);
        if (ret)
                return ret;
@@ -1076,69 +1060,3 @@ void vga_switcheroo_fini_domain_pm_ops(struct device *dev)
        dev_pm_domain_set(dev, NULL);
 }
 EXPORT_SYMBOL(vga_switcheroo_fini_domain_pm_ops);
-static int vga_switcheroo_runtime_resume_hdmi_audio(struct device *dev)
-{
-        struct pci_dev *pdev = to_pci_dev(dev);
-        struct vga_switcheroo_client *client;
-        struct device *video_dev = NULL;
-        int ret;
-        /* we need to check if we have to switch back on the video
-         * device so the audio device can come back
-         */
-        mutex_lock(&vgasr_mutex);
-        list_for_each_entry(client, &vgasr_priv.clients, list) {
-                if (PCI_SLOT(client->pdev->devfn) == PCI_SLOT(pdev->devfn) &&
-                    client_is_vga(client)) {
-                        video_dev = &client->pdev->dev;
-                        break;
-                }
-        }
-        mutex_unlock(&vgasr_mutex);
-        if (video_dev) {
-                ret = pm_runtime_get_sync(video_dev);
-                if (ret && ret != 1)
-                        return ret;
-        }
-        ret = dev->bus->pm->runtime_resume(dev);
-        /* put the reference for the gpu */
-        if (video_dev) {
-                pm_runtime_mark_last_busy(video_dev);
-                pm_runtime_put_autosuspend(video_dev);
-        }
-        return ret;
-}
-/**
- * vga_switcheroo_init_domain_pm_optimus_hdmi_audio() - helper for driver
- *      power control
- * @dev: audio client device
- * @domain: power domain
- *
- * Helper for GPUs whose power state is controlled by the driver's runtime pm.
- * When the audio device resumes, the GPU needs to be woken. This helper
- * augments the audio device's resume function to do that.
- *
- * Return: 0 on success, -EINVAL if no power management operations are
- * defined for this device.
- */
-int
-vga_switcheroo_init_domain_pm_optimus_hdmi_audio(struct device *dev,
-                                                 struct dev_pm_domain *domain)
-{
-        /* copy over all the bus versions */
-        if (dev->bus && dev->bus->pm) {
-                domain->ops = *dev->bus->pm;
-                domain->ops.runtime_resume =
-                        vga_switcheroo_runtime_resume_hdmi_audio;
-                dev_pm_domain_set(dev, domain);
-                return 0;
-        }
-        dev_pm_domain_set(dev, NULL);
-        return -EINVAL;
-}
-EXPORT_SYMBOL(vga_switcheroo_init_domain_pm_optimus_hdmi_audio);
diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c
index 3bed6beda051..6a67cdbd0e6a 100644
--- a/drivers/pci/pci-driver.c
+++ b/drivers/pci/pci-driver.c
@@ -1224,11 +1224,14 @@ static int pci_pm_runtime_suspend(struct device *dev)
        int error;
        /*
-         * If pci_dev->driver is not set (unbound), the device should
+         * If pci_dev->driver is not set (unbound), we leave the device in D0,
-         * always remain in D0 regardless of the runtime PM status
+         * but it may go to D3cold when the bridge above it runtime suspends.
+         * Save its config space in case that happens.
         */
-        if (!pci_dev->driver)
+        if (!pci_dev->driver) {
+                pci_save_state(pci_dev);
                return 0;
+        }
        if (!pm || !pm->runtime_suspend)
                return -ENOSYS;
@@ -1276,16 +1279,18 @@ static int pci_pm_runtime_resume(struct device *dev)
        const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
        /*
-         * If pci_dev->driver is not set (unbound), the device should
+         * Restoring config space is necessary even if the device is not bound
-         * always remain in D0 regardless of the runtime PM status
+         * to a driver because although we left it in D0, it may have gone to
+         * D3cold when the bridge above it runtime suspended.
         */
+        pci_restore_standard_config(pci_dev);
        if (!pci_dev->driver)
                return 0;
        if (!pm || !pm->runtime_resume)
                return -ENOSYS;
-        pci_restore_standard_config(pci_dev);
        pci_fixup_device(pci_fixup_resume_early, pci_dev);
        pci_enable_wake(pci_dev, PCI_D0, false);
        pci_fixup_device(pci_fixup_resume, pci_dev);
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index f6a4dd10d9b0..bd6f156dc3cf 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -800,7 +800,7 @@ static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
 * pci_wakeup_bus - Walk given bus and wake up devices on it
 * @bus: Top bus of the subtree to walk.
 */
-static void pci_wakeup_bus(struct pci_bus *bus)
+void pci_wakeup_bus(struct pci_bus *bus)
 {
        if (bus)
                pci_walk_bus(bus, pci_wakeup, NULL);
@@ -850,11 +850,11 @@ static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
 }
 /**
- * __pci_bus_set_current_state - Walk given bus and set current state of devices
+ * pci_bus_set_current_state - Walk given bus and set current state of devices
 * @bus: Top bus of the subtree to walk.
 * @state: state to be set
 */
-static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
+void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
 {
        if (bus)
                pci_walk_bus(bus, __pci_dev_set_current_state, &state);
@@ -876,7 +876,7 @@ int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
        ret = pci_platform_power_transition(dev, state);
        /* Power off the bridge may power off the whole hierarchy */
        if (!ret && state == PCI_D3cold)
-                __pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
+                pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
        return ret;
 }
 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index fc734014206f..ec582d37c189 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -26,6 +26,7 @@
 #include <linux/ktime.h>
 #include <linux/mm.h>
 #include <linux/platform_data/x86/apple.h>
+#include <linux/pm_runtime.h>
 #include <asm/dma.h>    /* isa_dma_bridge_buggy */
 #include "pci.h"
@@ -4832,3 +4833,41 @@ static void quirk_fsl_no_msi(struct pci_dev *pdev)
                pdev->no_msi = 1;
 }
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi);
+/*
+ * GPUs with integrated HDA controller for streaming audio to attached displays
+ * need a device link from the HDA controller (consumer) to the GPU (supplier)
+ * so that the GPU is powered up whenever the HDA controller is accessed.
+ * The GPU and HDA controller are functions 0 and 1 of the same PCI device.
+ * The device link stays in place until shutdown (or removal of the PCI device
+ * if it's hotplugged).  Runtime PM is allowed by default on the HDA controller
+ * to prevent it from permanently keeping the GPU awake.
+ */
+static void quirk_gpu_hda(struct pci_dev *hda)
+{
+        struct pci_dev *gpu;
+        if (PCI_FUNC(hda->devfn) != 1)
+                return;
+        gpu = pci_get_domain_bus_and_slot(pci_domain_nr(hda->bus),
+                                          hda->bus->number,
+                                          PCI_DEVFN(PCI_SLOT(hda->devfn), 0));
+        if (!gpu || (gpu->class >> 16) != PCI_BASE_CLASS_DISPLAY) {
+                pci_dev_put(gpu);
+                return;
+        }
+        if (!device_link_add(&hda->dev, &gpu->dev,
+                             DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME))
+                pci_err(hda, "cannot link HDA to GPU %s\n", pci_name(gpu));
+        pm_runtime_allow(&hda->dev);
+        pci_dev_put(gpu);
+}
+DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
+                              PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
+DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID,
+                              PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
+DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
+                              PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
diff --git a/include/drm/bridge/analogix_dp.h b/include/drm/bridge/analogix_dp.h
index 711fff9b6803..e9a1116d2f8e 100644
--- a/include/drm/bridge/analogix_dp.h
+++ b/include/drm/bridge/analogix_dp.h
@@ -41,7 +41,7 @@ struct analogix_dp_plat_data {
                         struct drm_connector *);
 };
-int analogix_dp_psr_supported(struct analogix_dp_device *dp);
+int analogix_dp_psr_enabled(struct analogix_dp_device *dp);
 int analogix_dp_enable_psr(struct analogix_dp_device *dp);
 int analogix_dp_disable_psr(struct analogix_dp_device *dp);
diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h
index b3b6d302ca8c..44f04233e3db 100644
--- a/include/drm/drm_color_mgmt.h
+++ b/include/drm/drm_color_mgmt.h
@@ -38,6 +38,18 @@ void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc,
 int drm_mode_crtc_set_gamma_size(struct drm_crtc *crtc,
                                 int gamma_size);
+/**
+ * drm_color_lut_size - calculate the number of entries in the LUT
+ * @blob: blob containing the LUT
+ *
+ * Returns:
+ * The number of entries in the color LUT stored in @blob.
+ */
+static inline int drm_color_lut_size(const struct drm_property_blob *blob)
+{
+        return blob->length / sizeof(struct drm_color_lut);
+}
 enum drm_color_encoding {
        DRM_COLOR_YCBCR_BT601,
        DRM_COLOR_YCBCR_BT709,
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 4de97e94ef9d..62903bae0221 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -288,6 +288,7 @@
 #define DP_PSR_SUPPORT                      0x070   /* XXX 1.2? */
 # define DP_PSR_IS_SUPPORTED                1
 # define DP_PSR2_IS_SUPPORTED               2       /* eDP 1.4 */
+# define DP_PSR2_WITH_Y_COORD_IS_SUPPORTED  3       /* eDP 1.4a */
 #define DP_PSR_CAPS                         0x071   /* XXX 1.2? */
 # define DP_PSR_NO_TRAIN_ON_EXIT            1
diff --git a/include/drm/drm_mode_object.h b/include/drm/drm_mode_object.h
index 7ba3913f30b5..c34a3e8030e1 100644
--- a/include/drm/drm_mode_object.h
+++ b/include/drm/drm_mode_object.h
@@ -120,30 +120,6 @@ struct drm_mode_object *drm_mode_object_find(struct drm_device *dev,
 void drm_mode_object_get(struct drm_mode_object *obj);
 void drm_mode_object_put(struct drm_mode_object *obj);
-/**
- * drm_mode_object_reference - acquire a mode object reference
- * @obj: DRM mode object
- *
- * This is a compatibility alias for drm_mode_object_get() and should not be
- * used by new code.
- */
-static inline void drm_mode_object_reference(struct drm_mode_object *obj)
-{
-        drm_mode_object_get(obj);
-}
-/**
- * drm_mode_object_unreference - release a mode object reference
- * @obj: DRM mode object
- *
- * This is a compatibility alias for drm_mode_object_put() and should not be
- * used by new code.
- */
-static inline void drm_mode_object_unreference(struct drm_mode_object *obj)
-{
-        drm_mode_object_put(obj);
-}
 int drm_object_property_set_value(struct drm_mode_object *obj,
                                  struct drm_property *property,
                                  uint64_t val);
diff --git a/include/drm/drm_print.h b/include/drm/drm_print.h
index 2a4a42e59a47..e1a46e9991cc 100644
--- a/include/drm/drm_print.h
+++ b/include/drm/drm_print.h
@@ -196,21 +196,22 @@ static inline struct drm_printer drm_debug_printer(const char *prefix)
 #define DRM_UT_STATE            0x40
 #define DRM_UT_LEASE            0x80
-__printf(6, 7)
+__printf(3, 4)
 void drm_dev_printk(const struct device *dev, const char *level,
-                    unsigned int category, const char *function_name,
+                    const char *format, ...);
-                    const char *prefix, const char *format, ...);
 __printf(3, 4)
-void drm_printk(const char *level, unsigned int category,
+void drm_dev_dbg(const struct device *dev, unsigned int category,
-                const char *format, ...);
+                 const char *format, ...);
+__printf(2, 3)
+void drm_dbg(unsigned int category, const char *format, ...);
+__printf(1, 2)
+void drm_err(const char *format, ...);
 /* Macros to make printk easier */
 #define _DRM_PRINTK(once, level, fmt, ...)                              \
-        do {                                                            \
+        printk##once(KERN_##level "[" DRM_NAME "] " fmt, ##__VA_ARGS__)
-                printk##once(KERN_##level "[" DRM_NAME "] " fmt,        \
-                             ##__VA_ARGS__);                            \
-        } while (0)
 #define DRM_INFO(fmt, ...)                                              \
        _DRM_PRINTK(, INFO, fmt, ##__VA_ARGS__)
@@ -233,10 +234,9 @@ void drm_printk(const char *level, unsigned int category,
 * @fmt: printf() like format string.
 */
 #define DRM_DEV_ERROR(dev, fmt, ...)                                    \
-        drm_dev_printk(dev, KERN_ERR, DRM_UT_NONE, __func__, " *ERROR*",\
+        drm_dev_printk(dev, KERN_ERR, "*ERROR* " fmt, ##__VA_ARGS__)
-                       fmt, ##__VA_ARGS__)
 #define DRM_ERROR(fmt, ...)                                             \
-        drm_printk(KERN_ERR, DRM_UT_NONE, fmt,  ##__VA_ARGS__)
+        drm_err(fmt, ##__VA_ARGS__)
 /**
 * Rate limited error output.  Like DRM_ERROR() but won't flood the log.
@@ -257,8 +257,7 @@ void drm_printk(const char *level, unsigned int category,
        DRM_DEV_ERROR_RATELIMITED(NULL, fmt, ##__VA_ARGS__)
 #define DRM_DEV_INFO(dev, fmt, ...)                                     \
-        drm_dev_printk(dev, KERN_INFO, DRM_UT_NONE, __func__, "", fmt,  \
+        drm_dev_printk(dev, KERN_INFO, fmt, ##__VA_ARGS__)
-                       ##__VA_ARGS__)
 #define DRM_DEV_INFO_ONCE(dev, fmt, ...)                                \
 ({                                                                      \
@@ -275,53 +274,46 @@ void drm_printk(const char *level, unsigned int category,
 * @dev: device pointer
 * @fmt: printf() like format string.
 */
-#define DRM_DEV_DEBUG(dev, fmt, args...)                                \
+#define DRM_DEV_DEBUG(dev, fmt, ...)                                    \
-        drm_dev_printk(dev, KERN_DEBUG, DRM_UT_CORE, __func__, "", fmt, \
+        drm_dev_dbg(dev, DRM_UT_CORE, fmt, ##__VA_ARGS__)
-                       ##args)
 #define DRM_DEBUG(fmt, ...)                                             \
-        drm_printk(KERN_DEBUG, DRM_UT_CORE, fmt, ##__VA_ARGS__)
+        drm_dbg(DRM_UT_CORE, fmt, ##__VA_ARGS__)
-#define DRM_DEV_DEBUG_DRIVER(dev, fmt, args...)                         \
+#define DRM_DEV_DEBUG_DRIVER(dev, fmt, ...)                             \
-        drm_dev_printk(dev, KERN_DEBUG, DRM_UT_DRIVER, __func__, "",    \
+        drm_dev_dbg(dev, DRM_UT_DRIVER, fmt, ##__VA_ARGS__)
-                       fmt, ##args)
 #define DRM_DEBUG_DRIVER(fmt, ...)                                      \
-        drm_printk(KERN_DEBUG, DRM_UT_DRIVER, fmt, ##__VA_ARGS__)
+        drm_dbg(DRM_UT_DRIVER, fmt, ##__VA_ARGS__)
-#define DRM_DEV_DEBUG_KMS(dev, fmt, args...)                            \
+#define DRM_DEV_DEBUG_KMS(dev, fmt, ...)                                \
-        drm_dev_printk(dev, KERN_DEBUG, DRM_UT_KMS, __func__, "", fmt,  \
+        drm_dev_dbg(dev, DRM_UT_KMS, fmt, ##__VA_ARGS__)
-                       ##args)
+#define DRM_DEBUG_KMS(fmt, ...)                                         \
-#define DRM_DEBUG_KMS(fmt, ...)                                 \
+        drm_dbg(DRM_UT_KMS, fmt, ##__VA_ARGS__)
-        drm_printk(KERN_DEBUG, DRM_UT_KMS, fmt, ##__VA_ARGS__)
-#define DRM_DEV_DEBUG_PRIME(dev, fmt, args...)                          \
+#define DRM_DEV_DEBUG_PRIME(dev, fmt, ...)                              \
-        drm_dev_printk(dev, KERN_DEBUG, DRM_UT_PRIME, __func__, "",     \
+        drm_dev_dbg(dev, DRM_UT_PRIME, fmt, ##__VA_ARGS__)
-                       fmt, ##args)
 #define DRM_DEBUG_PRIME(fmt, ...)                                       \
-        drm_printk(KERN_DEBUG, DRM_UT_PRIME, fmt, ##__VA_ARGS__)
+        drm_dbg(DRM_UT_PRIME, fmt, ##__VA_ARGS__)
-#define DRM_DEV_DEBUG_ATOMIC(dev, fmt, args...)                         \
+#define DRM_DEV_DEBUG_ATOMIC(dev, fmt, ...)                             \
-        drm_dev_printk(dev, KERN_DEBUG, DRM_UT_ATOMIC, __func__, "",    \
+        drm_dev_dbg(dev, DRM_UT_ATOMIC, fmt, ##__VA_ARGS__)
-                       fmt, ##args)
 #define DRM_DEBUG_ATOMIC(fmt, ...)                                      \
-        drm_printk(KERN_DEBUG, DRM_UT_ATOMIC, fmt, ##__VA_ARGS__)
+        drm_dbg(DRM_UT_ATOMIC, fmt, ##__VA_ARGS__)
-#define DRM_DEV_DEBUG_VBL(dev, fmt, args...)                            \
+#define DRM_DEV_DEBUG_VBL(dev, fmt, ...)                                \
-        drm_dev_printk(dev, KERN_DEBUG, DRM_UT_VBL, __func__, "", fmt,  \
+        drm_dev_dbg(dev, DRM_UT_VBL, fmt, ##__VA_ARGS__)
-                       ##args)
+#define DRM_DEBUG_VBL(fmt, ...)                                         \
-#define DRM_DEBUG_VBL(fmt, ...)                                 \
+        drm_dbg(DRM_UT_VBL, fmt, ##__VA_ARGS__)
-        drm_printk(KERN_DEBUG, DRM_UT_VBL, fmt, ##__VA_ARGS__)
 #define DRM_DEBUG_LEASE(fmt, ...)                                       \
-        drm_printk(KERN_DEBUG, DRM_UT_LEASE, fmt, ##__VA_ARGS__)
+        drm_dbg(DRM_UT_LEASE, fmt, ##__VA_ARGS__)
-#define _DRM_DEV_DEFINE_DEBUG_RATELIMITED(dev, level, fmt, args...)     \
+#define _DRM_DEV_DEFINE_DEBUG_RATELIMITED(dev, category, fmt, ...)      \
 ({                                                                      \
        static DEFINE_RATELIMIT_STATE(_rs,                              \
                                      DEFAULT_RATELIMIT_INTERVAL,       \
                                      DEFAULT_RATELIMIT_BURST);         \
        if (__ratelimit(&_rs))                                          \
-                drm_dev_printk(dev, KERN_DEBUG, DRM_UT_ ## level,       \
+                drm_dev_dbg(dev, category, fmt, ##__VA_ARGS__);         \
-                               __func__, "", fmt, ##args);              \
 })
 /**
@@ -330,21 +322,28 @@ void drm_printk(const char *level, unsigned int category,
 * @dev: device pointer
 * @fmt: printf() like format string.
 */
-#define DRM_DEV_DEBUG_RATELIMITED(dev, fmt, args...)                    \
+#define DRM_DEV_DEBUG_RATELIMITED(dev, fmt, ...)                        \
-        DEV__DRM_DEFINE_DEBUG_RATELIMITED(dev, CORE, fmt, ##args)
+        _DEV_DRM_DEFINE_DEBUG_RATELIMITED(dev, DRM_UT_CORE,             \
-#define DRM_DEBUG_RATELIMITED(fmt, args...)                             \
+                                          fmt, ##__VA_ARGS__)
-        DRM_DEV_DEBUG_RATELIMITED(NULL, fmt, ##args)
+#define DRM_DEBUG_RATELIMITED(fmt, ...)                                 \
-#define DRM_DEV_DEBUG_DRIVER_RATELIMITED(dev, fmt, args...)             \
+        DRM_DEV_DEBUG_RATELIMITED(NULL, fmt, ##__VA_ARGS__)
-        _DRM_DEV_DEFINE_DEBUG_RATELIMITED(dev, DRIVER, fmt, ##args)
-#define DRM_DEBUG_DRIVER_RATELIMITED(fmt, args...)                      \
+#define DRM_DEV_DEBUG_DRIVER_RATELIMITED(dev, fmt, ...)                 \
-        DRM_DEV_DEBUG_DRIVER_RATELIMITED(NULL, fmt, ##args)
+        _DRM_DEV_DEFINE_DEBUG_RATELIMITED(dev, DRM_UT_DRIVER,           \
-#define DRM_DEV_DEBUG_KMS_RATELIMITED(dev, fmt, args...)                \
+                                          fmt, ##__VA_ARGS__)
-        _DRM_DEV_DEFINE_DEBUG_RATELIMITED(dev, KMS, fmt, ##args)
+#define DRM_DEBUG_DRIVER_RATELIMITED(fmt, ...)                          \
-#define DRM_DEBUG_KMS_RATELIMITED(fmt, args...)                         \
+        DRM_DEV_DEBUG_DRIVER_RATELIMITED(NULL, fmt, ##__VA_ARGS__)
-        DRM_DEV_DEBUG_KMS_RATELIMITED(NULL, fmt, ##args)
-#define DRM_DEV_DEBUG_PRIME_RATELIMITED(dev, fmt, args...)              \
+#define DRM_DEV_DEBUG_KMS_RATELIMITED(dev, fmt, ...)                    \
-        _DRM_DEV_DEFINE_DEBUG_RATELIMITED(dev, PRIME, fmt, ##args)
+        _DRM_DEV_DEFINE_DEBUG_RATELIMITED(dev, DRM_UT_KMS,              \
-#define DRM_DEBUG_PRIME_RATELIMITED(fmt, args...)                       \
+                                          fmt, ##__VA_ARGS__)
-        DRM_DEV_DEBUG_PRIME_RATELIMITED(NULL, fmt, ##args)
+#define DRM_DEBUG_KMS_RATELIMITED(fmt, ...)                             \
+        DRM_DEV_DEBUG_KMS_RATELIMITED(NULL, fmt, ##__VA_ARGS__)
+#define DRM_DEV_DEBUG_PRIME_RATELIMITED(dev, fmt, ...)                  \
+        _DRM_DEV_DEFINE_DEBUG_RATELIMITED(dev, DRM_UT_PRIME,            \
+                                          fmt, ##__VA_ARGS__)
+#define DRM_DEBUG_PRIME_RATELIMITED(fmt, ...)                           \
+        DRM_DEV_DEBUG_PRIME_RATELIMITED(NULL, fmt, ##__VA_ARGS__)
 #endif /* DRM_PRINT_H_ */
diff --git a/include/drm/drm_property.h b/include/drm/drm_property.h
index 937757a8a568..d1423c7f3c73 100644
--- a/include/drm/drm_property.h
+++ b/include/drm/drm_property.h
@@ -209,7 +209,7 @@ struct drm_property_blob {
        struct list_head head_global;
        struct list_head head_file;
        size_t length;
-        unsigned char data[];
+        void *data;
 };
 struct drm_prop_enum_list {
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 024a1beda008..ae42289662df 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -1147,6 +1147,8 @@ void pci_pme_wakeup_bus(struct pci_bus *bus);
 void pci_d3cold_enable(struct pci_dev *dev);
 void pci_d3cold_disable(struct pci_dev *dev);
 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
+void pci_wakeup_bus(struct pci_bus *bus);
+void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
 /* PCI Virtual Channel */
 int pci_save_vc_state(struct pci_dev *dev);
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index a6b30667a331..a637a7d8ce5b 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -45,6 +45,7 @@
 #define PCI_CLASS_MULTIMEDIA_VIDEO      0x0400
 #define PCI_CLASS_MULTIMEDIA_AUDIO      0x0401
 #define PCI_CLASS_MULTIMEDIA_PHONE      0x0402
+#define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
 #define PCI_CLASS_MULTIMEDIA_OTHER      0x0480
 #define PCI_BASE_CLASS_MEMORY           0x05
diff --git a/include/linux/vga_switcheroo.h b/include/linux/vga_switcheroo.h
index 960bedbdec87..77f0f0af3a71 100644
--- a/include/linux/vga_switcheroo.h
+++ b/include/linux/vga_switcheroo.h
@@ -168,11 +168,8 @@ int vga_switcheroo_process_delayed_switch(void);
 bool vga_switcheroo_client_probe_defer(struct pci_dev *pdev);
 enum vga_switcheroo_state vga_switcheroo_get_client_state(struct pci_dev *dev);
-void vga_switcheroo_set_dynamic_switch(struct pci_dev *pdev, enum vga_switcheroo_state dynamic);
 int vga_switcheroo_init_domain_pm_ops(struct device *dev, struct dev_pm_domain *domain);
 void vga_switcheroo_fini_domain_pm_ops(struct device *dev);
-int vga_switcheroo_init_domain_pm_optimus_hdmi_audio(struct device *dev, struct dev_pm_domain *domain);
 #else
 static inline void vga_switcheroo_unregister_client(struct pci_dev *dev) {}
@@ -192,11 +189,8 @@ static inline int vga_switcheroo_process_delayed_switch(void) { return 0; }
 static inline bool vga_switcheroo_client_probe_defer(struct pci_dev *pdev) { return false; }
 static inline enum vga_switcheroo_state vga_switcheroo_get_client_state(struct pci_dev *dev) { return VGA_SWITCHEROO_ON; }
-static inline void vga_switcheroo_set_dynamic_switch(struct pci_dev *pdev, enum vga_switcheroo_state dynamic) {}
 static inline int vga_switcheroo_init_domain_pm_ops(struct device *dev, struct dev_pm_domain *domain) { return -EINVAL; }
 static inline void vga_switcheroo_fini_domain_pm_ops(struct device *dev) {}
-static inline int vga_switcheroo_init_domain_pm_optimus_hdmi_audio(struct device *dev, struct dev_pm_domain *domain) { return -EINVAL; }
 #endif
 #endif /* _LINUX_VGA_SWITCHEROO_H_ */
diff --git a/include/sound/hdaudio.h b/include/sound/hdaudio.h
index 68169e3749de..5b2ed12f58ce 100644
--- a/include/sound/hdaudio.h
+++ b/include/sound/hdaudio.h
@@ -227,9 +227,6 @@ struct hdac_io_ops {
 #define HDA_UNSOL_QUEUE_SIZE    64
 #define HDA_MAX_CODECS          8       /* limit by controller side */
-/* HD Audio class code */
-#define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
 /*
 * CORB/RIRB
 *
diff --git a/include/uapi/drm/etnaviv_drm.h b/include/uapi/drm/etnaviv_drm.h
index e9b997a0ef27..0d5c49dc478c 100644
--- a/include/uapi/drm/etnaviv_drm.h
+++ b/include/uapi/drm/etnaviv_drm.h
@@ -55,6 +55,12 @@ struct drm_etnaviv_timespec {
 #define ETNAVIV_PARAM_GPU_FEATURES_4                0x07
 #define ETNAVIV_PARAM_GPU_FEATURES_5                0x08
 #define ETNAVIV_PARAM_GPU_FEATURES_6                0x09
+#define ETNAVIV_PARAM_GPU_FEATURES_7                0x0a
+#define ETNAVIV_PARAM_GPU_FEATURES_8                0x0b
+#define ETNAVIV_PARAM_GPU_FEATURES_9                0x0c
+#define ETNAVIV_PARAM_GPU_FEATURES_10               0x0d
+#define ETNAVIV_PARAM_GPU_FEATURES_11               0x0e
+#define ETNAVIV_PARAM_GPU_FEATURES_12               0x0f
 #define ETNAVIV_PARAM_GPU_STREAM_COUNT              0x10
 #define ETNAVIV_PARAM_GPU_REGISTER_MAX              0x11
diff --git a/scripts/coccinelle/api/drm-get-put.cocci b/scripts/coccinelle/api/drm-get-put.cocci
index 91fceb8f1fa2..ceb71ea7f61c 100644
--- a/scripts/coccinelle/api/drm-get-put.cocci
+++ b/scripts/coccinelle/api/drm-get-put.cocci
@@ -16,12 +16,6 @@ expression object;
 @@
 (
- drm_mode_object_reference(object)
-+ drm_mode_object_get(object)
-|
- drm_mode_object_unreference(object)
-+ drm_mode_object_put(object)
-|
 - drm_connector_reference(object)
 + drm_connector_get(object)
 |
@@ -62,10 +56,6 @@ position p;
 @@
 (
-drm_mode_object_unreference@p(object)
-|
-drm_mode_object_reference@p(object)
-|
 drm_connector_unreference@p(object)
 |
 drm_connector_reference@p(object)
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index c71dcacea807..ec4e6b829ee2 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -1227,6 +1227,7 @@ static void azx_vs_set_state(struct pci_dev *pci,
        struct snd_card *card = pci_get_drvdata(pci);
        struct azx *chip = card->private_data;
        struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
+        struct hda_codec *codec;
        bool disabled;
        wait_for_completion(&hda->probe_wait);
@@ -1251,8 +1252,12 @@ static void azx_vs_set_state(struct pci_dev *pci,
                dev_info(chip->card->dev, "%s via vga_switcheroo\n",
                         disabled ? "Disabling" : "Enabling");
                if (disabled) {
-                        pm_runtime_put_sync_suspend(card->dev);
+                        list_for_each_codec(codec, &chip->bus) {
-                        azx_suspend(card->dev);
+                                pm_runtime_suspend(hda_codec_dev(codec));
+                                pm_runtime_disable(hda_codec_dev(codec));
+                        }
+                        pm_runtime_suspend(card->dev);
+                        pm_runtime_disable(card->dev);
                        /* when we get suspended by vga_switcheroo we end up in D3cold,
                         * however we have no ACPI handle, so pci/acpi can't put us there,
                         * put ourselves there */
@@ -1263,9 +1268,12 @@ static void azx_vs_set_state(struct pci_dev *pci,
                                         "Cannot lock devices!\n");
                } else {
                        snd_hda_unlock_devices(&chip->bus);
-                        pm_runtime_get_noresume(card->dev);
                        chip->disabled = false;
-                        azx_resume(card->dev);
+                        pm_runtime_enable(card->dev);
+                        list_for_each_codec(codec, &chip->bus) {
+                                pm_runtime_enable(hda_codec_dev(codec));
+                                pm_runtime_resume(hda_codec_dev(codec));
+                        }
                }
        }
 }
@@ -1295,6 +1303,7 @@ static void init_vga_switcheroo(struct azx *chip)
                dev_info(chip->card->dev,
                         "Handle vga_switcheroo audio client\n");
                hda->use_vga_switcheroo = 1;
+                chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
                pci_dev_put(p);
        }
 }
@@ -1320,9 +1329,6 @@ static int register_vga_switcheroo(struct azx *chip)
                return err;
        hda->vga_switcheroo_registered = 1;
-        /* register as an optimus hdmi audio power domain */
-        vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
-                                                         &hda->hdmi_pm_domain);
        return 0;
 }
 #else
@@ -1351,10 +1357,8 @@ static int azx_free(struct azx *chip)
        if (use_vga_switcheroo(hda)) {
                if (chip->disabled && hda->probe_continued)
                        snd_hda_unlock_devices(&chip->bus);
-                if (hda->vga_switcheroo_registered) {
+                if (hda->vga_switcheroo_registered)
                        vga_switcheroo_unregister_client(chip->pci);
-                        vga_switcheroo_fini_domain_pm_ops(chip->card->dev);
-                }
        }
        if (bus->chip_init) {
@@ -2197,6 +2201,7 @@ static int azx_probe_continue(struct azx *chip)
        struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
        struct hdac_bus *bus = azx_bus(chip);
        struct pci_dev *pci = chip->pci;
+        struct hda_codec *codec;
        int dev = chip->dev_index;
        int err;
@@ -2278,8 +2283,17 @@ static int azx_probe_continue(struct azx *chip)
        chip->running = 1;
        azx_add_card_list(chip);
+        /*
+         * The discrete GPU cannot power down unless the HDA controller runtime
+         * suspends, so activate runtime PM on codecs even if power_save == 0.
+         */
+        if (use_vga_switcheroo(hda))
+                list_for_each_codec(codec, &chip->bus)
+                        codec->auto_runtime_pm = 1;
        snd_hda_set_power_save(&chip->bus, power_save * 1000);
-        if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
+        if (azx_has_pm_runtime(chip))
                pm_runtime_put_autosuspend(&pci->dev);
 out_free:
diff --git a/sound/pci/hda/hda_intel.h b/sound/pci/hda/hda_intel.h
index ff0c4d617bc1..e3a3d318d2e5 100644
--- a/sound/pci/hda/hda_intel.h
+++ b/sound/pci/hda/hda_intel.h
@@ -40,9 +40,6 @@ struct hda_intel {
        unsigned int vga_switcheroo_registered:1;
        unsigned int init_failed:1; /* delayed init failed */
-        /* secondary power domain for hdmi audio under vga device */
-        struct dev_pm_domain hdmi_pm_domain;
        bool need_i915_power:1; /* the hda controller needs i915 power */
 };