diff options
| -rw-r--r-- | drivers/gpu/drm/tegra/sor.c | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index 2afe478ded3b..59b8aec1aeae 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c | |||
| @@ -68,13 +68,12 @@ static inline struct tegra_sor *to_sor(struct tegra_output *output) | |||
| 68 | return container_of(output, struct tegra_sor, output); | 68 | return container_of(output, struct tegra_sor, output); |
| 69 | } | 69 | } |
| 70 | 70 | ||
| 71 | static inline unsigned long tegra_sor_readl(struct tegra_sor *sor, | 71 | static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned long offset) |
| 72 | unsigned long offset) | ||
| 73 | { | 72 | { |
| 74 | return readl(sor->regs + (offset << 2)); | 73 | return readl(sor->regs + (offset << 2)); |
| 75 | } | 74 | } |
| 76 | 75 | ||
| 77 | static inline void tegra_sor_writel(struct tegra_sor *sor, unsigned long value, | 76 | static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, |
| 78 | unsigned long offset) | 77 | unsigned long offset) |
| 79 | { | 78 | { |
| 80 | writel(value, sor->regs + (offset << 2)); | 79 | writel(value, sor->regs + (offset << 2)); |
| @@ -83,9 +82,9 @@ static inline void tegra_sor_writel(struct tegra_sor *sor, unsigned long value, | |||
| 83 | static int tegra_sor_dp_train_fast(struct tegra_sor *sor, | 82 | static int tegra_sor_dp_train_fast(struct tegra_sor *sor, |
| 84 | struct drm_dp_link *link) | 83 | struct drm_dp_link *link) |
| 85 | { | 84 | { |
| 86 | unsigned long value; | ||
| 87 | unsigned int i; | 85 | unsigned int i; |
| 88 | u8 pattern; | 86 | u8 pattern; |
| 87 | u32 value; | ||
| 89 | int err; | 88 | int err; |
| 90 | 89 | ||
| 91 | /* setup lane parameters */ | 90 | /* setup lane parameters */ |
| @@ -202,7 +201,7 @@ static void tegra_sor_update(struct tegra_sor *sor) | |||
| 202 | 201 | ||
| 203 | static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout) | 202 | static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout) |
| 204 | { | 203 | { |
| 205 | unsigned long value; | 204 | u32 value; |
| 206 | 205 | ||
| 207 | value = tegra_sor_readl(sor, SOR_PWM_DIV); | 206 | value = tegra_sor_readl(sor, SOR_PWM_DIV); |
| 208 | value &= ~SOR_PWM_DIV_MASK; | 207 | value &= ~SOR_PWM_DIV_MASK; |
| @@ -281,7 +280,7 @@ static int tegra_sor_wakeup(struct tegra_sor *sor) | |||
| 281 | 280 | ||
| 282 | static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout) | 281 | static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout) |
| 283 | { | 282 | { |
| 284 | unsigned long value; | 283 | u32 value; |
| 285 | 284 | ||
| 286 | value = tegra_sor_readl(sor, SOR_PWR); | 285 | value = tegra_sor_readl(sor, SOR_PWR); |
| 287 | value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU; | 286 | value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU; |
| @@ -791,8 +790,8 @@ static void tegra_sor_encoder_mode_set(struct drm_encoder *encoder, | |||
| 791 | struct tegra_sor_config config; | 790 | struct tegra_sor_config config; |
| 792 | struct drm_dp_link link; | 791 | struct drm_dp_link link; |
| 793 | struct drm_dp_aux *aux; | 792 | struct drm_dp_aux *aux; |
| 794 | unsigned long value; | ||
| 795 | int err = 0; | 793 | int err = 0; |
| 794 | u32 value; | ||
| 796 | 795 | ||
| 797 | mutex_lock(&sor->lock); | 796 | mutex_lock(&sor->lock); |
| 798 | 797 | ||
