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-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-at91.txt30
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-brcmstb.txt28
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-mt6577.txt41
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-xgene-slimpro.txt15
-rw-r--r--Documentation/i2c/slave-interface25
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7740.c55
-rw-r--r--drivers/i2c/algos/i2c-algo-pca.c2
-rw-r--r--drivers/i2c/busses/Kconfig32
-rw-r--r--drivers/i2c/busses/Makefile3
-rw-r--r--drivers/i2c/busses/i2c-at91.c362
-rw-r--r--drivers/i2c/busses/i2c-axxia.c41
-rw-r--r--drivers/i2c/busses/i2c-bcm-iproc.c57
-rw-r--r--drivers/i2c/busses/i2c-bcm2835.c11
-rw-r--r--drivers/i2c/busses/i2c-brcmstb.c694
-rw-r--r--drivers/i2c/busses/i2c-davinci.c80
-rw-r--r--drivers/i2c/busses/i2c-designware-platdrv.c35
-rw-r--r--drivers/i2c/busses/i2c-imx.c2
-rw-r--r--drivers/i2c/busses/i2c-mt65xx.c731
-rw-r--r--drivers/i2c/busses/i2c-mxs.c2
-rw-r--r--drivers/i2c/busses/i2c-octeon.c7
-rw-r--r--drivers/i2c/busses/i2c-omap.c74
-rw-r--r--drivers/i2c/busses/i2c-rcar.c10
-rw-r--r--drivers/i2c/busses/i2c-rk3x.c2
-rw-r--r--drivers/i2c/busses/i2c-s3c2410.c2
-rw-r--r--drivers/i2c/busses/i2c-sh_mobile.c49
-rw-r--r--drivers/i2c/busses/i2c-tegra.c11
-rw-r--r--drivers/i2c/busses/i2c-xgene-slimpro.c469
-rw-r--r--drivers/i2c/busses/i2c-xiic.c1
-rw-r--r--drivers/i2c/i2c-core.c63
-rw-r--r--drivers/i2c/i2c-mux.c3
-rw-r--r--drivers/i2c/i2c-smbus.c2
-rw-r--r--drivers/i2c/muxes/Kconfig5
-rw-r--r--drivers/i2c/muxes/i2c-mux-pca9541.c4
-rw-r--r--drivers/i2c/muxes/i2c-mux-pca954x.c2
-rw-r--r--include/uapi/linux/i2c.h1
35 files changed, 2730 insertions, 221 deletions
diff --git a/Documentation/devicetree/bindings/i2c/i2c-at91.txt b/Documentation/devicetree/bindings/i2c/i2c-at91.txt
index 388f0a275fba..6e81dc153f3b 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-at91.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-at91.txt
@@ -2,8 +2,8 @@ I2C for Atmel platforms
2 2
3Required properties : 3Required properties :
4- compatible : Must be "atmel,at91rm9200-i2c", "atmel,at91sam9261-i2c", 4- compatible : Must be "atmel,at91rm9200-i2c", "atmel,at91sam9261-i2c",
5 "atmel,at91sam9260-i2c", "atmel,at91sam9g20-i2c", "atmel,at91sam9g10-i2c" 5 "atmel,at91sam9260-i2c", "atmel,at91sam9g20-i2c", "atmel,at91sam9g10-i2c",
6 or "atmel,at91sam9x5-i2c" 6 "atmel,at91sam9x5-i2c" or "atmel,sama5d2-i2c"
7- reg: physical base address of the controller and length of memory mapped 7- reg: physical base address of the controller and length of memory mapped
8 region. 8 region.
9- interrupts: interrupt number to the cpu. 9- interrupts: interrupt number to the cpu.
@@ -13,6 +13,10 @@ Required properties :
13 13
14Optional properties: 14Optional properties:
15- clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 100000 15- clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 100000
16- dmas: A list of two dma specifiers, one for each entry in dma-names.
17- dma-names: should contain "tx" and "rx".
18- atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO
19 capable I2C controllers.
16- Child nodes conforming to i2c bus binding 20- Child nodes conforming to i2c bus binding
17 21
18Examples : 22Examples :
@@ -32,3 +36,25 @@ i2c0: i2c@fff84000 {
32 pagesize = <128>; 36 pagesize = <128>;
33 } 37 }
34} 38}
39
40i2c0: i2c@f8034600 {
41 compatible = "atmel,sama5d2-i2c";
42 reg = <0xf8034600 0x100>;
43 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
44 dmas = <&dma0
45 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
46 AT91_XDMAC_DT_PERID(11)>,
47 <&dma0
48 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
49 AT91_XDMAC_DT_PERID(12)>;
50 dma-names = "tx", "rx";
51 #address-cells = <1>;
52 #size-cells = <0>;
53 clocks = <&flx0>;
54 atmel,fifo-size = <16>;
55
56 wm8731: wm8731@1a {
57 compatible = "wm8731";
58 reg = <0x1a>;
59 };
60};
diff --git a/Documentation/devicetree/bindings/i2c/i2c-brcmstb.txt b/Documentation/devicetree/bindings/i2c/i2c-brcmstb.txt
new file mode 100644
index 000000000000..d6f724efdcf2
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-brcmstb.txt
@@ -0,0 +1,28 @@
1Broadcom stb bsc iic master controller
2
3Required properties:
4
5- compatible: should be "brcm,brcmstb-i2c"
6- clock-frequency: 32-bit decimal value of iic master clock freqency in Hz
7 valid values are 375000, 390000, 187500, 200000
8 93750, 97500, 46875 and 50000
9- reg: specifies the base physical address and size of the registers
10
11Optional properties :
12
13- interrupt-parent: specifies the phandle to the parent interrupt controller
14 this one is cascaded from
15- interrupts: specifies the interrupt number, the irq line to be used
16- interrupt-names: Interrupt name string
17
18Example:
19
20bsca: i2c@f0406200 {
21 clock-frequency = <390000>;
22 compatible = "brcm,brcmstb-i2c";
23 interrupt-parent = <&irq0_intc>;
24 reg = <0xf0406200 0x58>;
25 interrupts = <0x18>;
26 interrupt-names = "upg_bsca";
27};
28
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mt6577.txt b/Documentation/devicetree/bindings/i2c/i2c-mt6577.txt
new file mode 100644
index 000000000000..0ce6fa3242f0
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-mt6577.txt
@@ -0,0 +1,41 @@
1* Mediatek's I2C controller
2
3The Mediatek's I2C controller is used to interface with I2C devices.
4
5Required properties:
6 - compatible: value should be either of the following.
7 (a) "mediatek,mt6577-i2c", for i2c compatible with mt6577 i2c.
8 (b) "mediatek,mt6589-i2c", for i2c compatible with mt6589 i2c.
9 (c) "mediatek,mt8127-i2c", for i2c compatible with mt8127 i2c.
10 (d) "mediatek,mt8135-i2c", for i2c compatible with mt8135 i2c.
11 (e) "mediatek,mt8173-i2c", for i2c compatible with mt8173 i2c.
12 - reg: physical base address of the controller and dma base, length of memory
13 mapped region.
14 - interrupts: interrupt number to the cpu.
15 - clock-div: the fixed value for frequency divider of clock source in i2c
16 module. Each IC may be different.
17 - clocks: clock name from clock manager
18 - clock-names: Must include "main" and "dma", if enable have-pmic need include
19 "pmic" extra.
20
21Optional properties:
22 - clock-frequency: Frequency in Hz of the bus when transfer, the default value
23 is 100000.
24 - mediatek,have-pmic: platform can control i2c form special pmic side.
25 Only mt6589 and mt8135 support this feature.
26 - mediatek,use-push-pull: IO config use push-pull mode.
27
28Example:
29
30 i2c0: i2c@1100d000 {
31 compatible = "mediatek,mt6577-i2c";
32 reg = <0x1100d000 0x70>,
33 <0x11000300 0x80>;
34 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
35 clock-frequency = <400000>;
36 mediatek,have-pmic;
37 clock-div = <16>;
38 clocks = <&i2c0_ck>, <&ap_dma_ck>;
39 clock-names = "main", "dma";
40 };
41
diff --git a/Documentation/devicetree/bindings/i2c/i2c-xgene-slimpro.txt b/Documentation/devicetree/bindings/i2c/i2c-xgene-slimpro.txt
new file mode 100644
index 000000000000..f6b2c20cfbf6
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-xgene-slimpro.txt
@@ -0,0 +1,15 @@
1APM X-Gene SLIMpro Mailbox I2C Driver
2
3An I2C controller accessed over the "SLIMpro" mailbox.
4
5Required properties :
6
7 - compatible : should be "apm,xgene-slimpro-i2c"
8 - mboxes : use the label reference for the mailbox as the first parameter.
9 The second parameter is the channel number.
10
11Example :
12 i2cslimpro {
13 compatible = "apm,xgene-slimpro-i2c";
14 mboxes = <&mailbox 0>;
15 };
diff --git a/Documentation/i2c/slave-interface b/Documentation/i2c/slave-interface
index b228ca54bcf4..2dee4e2d62df 100644
--- a/Documentation/i2c/slave-interface
+++ b/Documentation/i2c/slave-interface
@@ -3,16 +3,16 @@ Linux I2C slave interface description
3 3
4by Wolfram Sang <wsa@sang-engineering.com> in 2014-15 4by Wolfram Sang <wsa@sang-engineering.com> in 2014-15
5 5
6Linux can also be an I2C slave in case I2C controllers have slave support. 6Linux can also be an I2C slave if the I2C controller in use has slave
7Besides this HW requirement, one also needs a software backend providing the 7functionality. For that to work, one needs slave support in the bus driver plus
8actual functionality. An example for this is the slave-eeprom driver, which 8a hardware independent software backend providing the actual functionality. An
9acts as a dual memory driver. While another I2C master on the bus can access it 9example for the latter is the slave-eeprom driver, which acts as a dual memory
10like a regular EEPROM, the Linux I2C slave can access the content via sysfs and 10driver. While another I2C master on the bus can access it like a regular
11retrieve/provide information as needed. The software backend driver and the I2C 11EEPROM, the Linux I2C slave can access the content via sysfs and handle data as
12bus driver communicate via events. Here is a small graph visualizing the data 12needed. The backend driver and the I2C bus driver communicate via events. Here
13flow and the means by which data is transported. The dotted line marks only one 13is a small graph visualizing the data flow and the means by which data is
14example. The backend could also use e.g. a character device, be in-kernel 14transported. The dotted line marks only one example. The backend could also
15only, or something completely different: 15use a character device, be in-kernel only, or something completely different:
16 16
17 17
18 e.g. sysfs I2C slave events I/O registers 18 e.g. sysfs I2C slave events I/O registers
@@ -43,6 +43,11 @@ behaviour and setup.
43Developer manual 43Developer manual
44================ 44================
45 45
46First, the events which are used by the bus driver and the backend will be
47described in detail. After that, some implementation hints for extending bus
48drivers and writing backends will be given.
49
50
46I2C slave events 51I2C slave events
47---------------- 52----------------
48 53
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 9832e48396a4..00291cc1772d 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -13,7 +13,6 @@
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 */ 15 */
16#include <linux/delay.h>
17#include <linux/dma-mapping.h> 16#include <linux/dma-mapping.h>
18#include <linux/kernel.h> 17#include <linux/kernel.h>
19#include <linux/init.h> 18#include <linux/init.h>
@@ -690,56 +689,6 @@ void __init r8a7740_meram_workaround(void)
690 } 689 }
691} 690}
692 691
693#define ICCR 0x0004
694#define ICSTART 0x0070
695
696#define i2c_read(reg, offset) ioread8(reg + offset)
697#define i2c_write(reg, offset, data) iowrite8(data, reg + offset)
698
699/*
700 * r8a7740 chip has lasting errata on I2C I/O pad reset.
701 * this is work-around for it.
702 */
703static void r8a7740_i2c_workaround(struct platform_device *pdev)
704{
705 struct resource *res;
706 void __iomem *reg;
707
708 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
709 if (unlikely(!res)) {
710 pr_err("r8a7740 i2c workaround fail (cannot find resource)\n");
711 return;
712 }
713
714 reg = ioremap(res->start, resource_size(res));
715 if (unlikely(!reg)) {
716 pr_err("r8a7740 i2c workaround fail (cannot map IO)\n");
717 return;
718 }
719
720 i2c_write(reg, ICCR, i2c_read(reg, ICCR) | 0x80);
721 i2c_read(reg, ICCR); /* dummy read */
722
723 i2c_write(reg, ICSTART, i2c_read(reg, ICSTART) | 0x10);
724 i2c_read(reg, ICSTART); /* dummy read */
725
726 udelay(10);
727
728 i2c_write(reg, ICCR, 0x01);
729 i2c_write(reg, ICSTART, 0x00);
730
731 udelay(10);
732
733 i2c_write(reg, ICCR, 0x10);
734 udelay(10);
735 i2c_write(reg, ICCR, 0x00);
736 udelay(10);
737 i2c_write(reg, ICCR, 0x10);
738 udelay(10);
739
740 iounmap(reg);
741}
742
743void __init r8a7740_add_standard_devices(void) 692void __init r8a7740_add_standard_devices(void)
744{ 693{
745 static struct pm_domain_device domain_devices[] __initdata = { 694 static struct pm_domain_device domain_devices[] __initdata = {
@@ -766,10 +715,6 @@ void __init r8a7740_add_standard_devices(void)
766 { "A3SP", &usb_dma_device }, 715 { "A3SP", &usb_dma_device },
767 }; 716 };
768 717
769 /* I2C work-around */
770 r8a7740_i2c_workaround(&i2c0_device);
771 r8a7740_i2c_workaround(&i2c1_device);
772
773 r8a7740_init_pm_domains(); 718 r8a7740_init_pm_domains();
774 719
775 /* add devices */ 720 /* add devices */
diff --git a/drivers/i2c/algos/i2c-algo-pca.c b/drivers/i2c/algos/i2c-algo-pca.c
index 580dbf05c148..e370804ec8bc 100644
--- a/drivers/i2c/algos/i2c-algo-pca.c
+++ b/drivers/i2c/algos/i2c-algo-pca.c
@@ -521,7 +521,7 @@ static int pca_init(struct i2c_adapter *adap)
521 521
522 pca_set_con(pca_data, I2C_PCA_CON_ENSIO); 522 pca_set_con(pca_data, I2C_PCA_CON_ENSIO);
523 } 523 }
524 udelay(500); /* 500 us for oscilator to stabilise */ 524 udelay(500); /* 500 us for oscillator to stabilise */
525 525
526 return 0; 526 return 0;
527} 527}
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 5f1c1c4f5d87..35ac23768ce9 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -392,6 +392,16 @@ config I2C_BCM_KONA
392 392
393 If you do not need KONA I2C interface, say N. 393 If you do not need KONA I2C interface, say N.
394 394
395config I2C_BRCMSTB
396 tristate "BRCM Settop I2C controller"
397 depends on ARCH_BRCMSTB || COMPILE_TEST
398 default y
399 help
400 If you say yes to this option, support will be included for the
401 I2C interface on the Broadcom Settop SoCs.
402
403 If you do not need I2C interface, say N.
404
395config I2C_BLACKFIN_TWI 405config I2C_BLACKFIN_TWI
396 tristate "Blackfin TWI I2C support" 406 tristate "Blackfin TWI I2C support"
397 depends on BLACKFIN 407 depends on BLACKFIN
@@ -419,7 +429,7 @@ config I2C_CADENCE
419 429
420config I2C_CBUS_GPIO 430config I2C_CBUS_GPIO
421 tristate "CBUS I2C driver" 431 tristate "CBUS I2C driver"
422 depends on GPIOLIB 432 depends on GPIOLIB || COMPILE_TEST
423 help 433 help
424 Support for CBUS access using I2C API. Mostly relevant for Nokia 434 Support for CBUS access using I2C API. Mostly relevant for Nokia
425 Internet Tablets (770, N800 and N810). 435 Internet Tablets (770, N800 and N810).
@@ -525,7 +535,7 @@ config I2C_EXYNOS5
525 535
526config I2C_GPIO 536config I2C_GPIO
527 tristate "GPIO-based bitbanging I2C" 537 tristate "GPIO-based bitbanging I2C"
528 depends on GPIOLIB 538 depends on GPIOLIB || COMPILE_TEST
529 select I2C_ALGOBIT 539 select I2C_ALGOBIT
530 help 540 help
531 This is a very simple bitbanging I2C driver utilizing the 541 This is a very simple bitbanging I2C driver utilizing the
@@ -620,6 +630,15 @@ config I2C_MPC
620 This driver can also be built as a module. If so, the module 630 This driver can also be built as a module. If so, the module
621 will be called i2c-mpc. 631 will be called i2c-mpc.
622 632
633config I2C_MT65XX
634 tristate "MediaTek I2C adapter"
635 depends on ARCH_MEDIATEK || COMPILE_TEST
636 help
637 This selects the MediaTek(R) Integrated Inter Circuit bus driver
638 for MT65xx and MT81xx.
639 If you want to use MediaTek(R) I2C interface, say Y or M here.
640 If unsure, say N.
641
623config I2C_MV64XXX 642config I2C_MV64XXX
624 tristate "Marvell mv64xxx I2C Controller" 643 tristate "Marvell mv64xxx I2C Controller"
625 depends on MV64X60 || PLAT_ORION || ARCH_SUNXI 644 depends on MV64X60 || PLAT_ORION || ARCH_SUNXI
@@ -1110,6 +1129,15 @@ config I2C_CROS_EC_TUNNEL
1110 connected there. This will work whatever the interface used to 1129 connected there. This will work whatever the interface used to
1111 talk to the EC (SPI, I2C or LPC). 1130 talk to the EC (SPI, I2C or LPC).
1112 1131
1132config I2C_XGENE_SLIMPRO
1133 tristate "APM X-Gene SoC I2C SLIMpro devices support"
1134 depends on ARCH_XGENE && MAILBOX
1135 help
1136 Enable I2C bus access using the APM X-Gene SoC SLIMpro
1137 co-processor. The I2C device access the I2C bus via the X-Gene
1138 to SLIMpro (On chip coprocessor) mailbox mechanism.
1139 If unsure, say N.
1140
1113config SCx200_ACB 1141config SCx200_ACB
1114 tristate "Geode ACCESS.bus support" 1142 tristate "Geode ACCESS.bus support"
1115 depends on X86_32 && PCI 1143 depends on X86_32 && PCI
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index cdf941da91c6..e5f537c80da0 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -60,6 +60,7 @@ obj-$(CONFIG_I2C_JZ4780) += i2c-jz4780.o
60obj-$(CONFIG_I2C_KEMPLD) += i2c-kempld.o 60obj-$(CONFIG_I2C_KEMPLD) += i2c-kempld.o
61obj-$(CONFIG_I2C_MESON) += i2c-meson.o 61obj-$(CONFIG_I2C_MESON) += i2c-meson.o
62obj-$(CONFIG_I2C_MPC) += i2c-mpc.o 62obj-$(CONFIG_I2C_MPC) += i2c-mpc.o
63obj-$(CONFIG_I2C_MT65XX) += i2c-mt65xx.o
63obj-$(CONFIG_I2C_MV64XXX) += i2c-mv64xxx.o 64obj-$(CONFIG_I2C_MV64XXX) += i2c-mv64xxx.o
64obj-$(CONFIG_I2C_MXS) += i2c-mxs.o 65obj-$(CONFIG_I2C_MXS) += i2c-mxs.o
65obj-$(CONFIG_I2C_NOMADIK) += i2c-nomadik.o 66obj-$(CONFIG_I2C_NOMADIK) += i2c-nomadik.o
@@ -105,11 +106,13 @@ obj-$(CONFIG_I2C_VIPERBOARD) += i2c-viperboard.o
105# Other I2C/SMBus bus drivers 106# Other I2C/SMBus bus drivers
106obj-$(CONFIG_I2C_ACORN) += i2c-acorn.o 107obj-$(CONFIG_I2C_ACORN) += i2c-acorn.o
107obj-$(CONFIG_I2C_BCM_KONA) += i2c-bcm-kona.o 108obj-$(CONFIG_I2C_BCM_KONA) += i2c-bcm-kona.o
109obj-$(CONFIG_I2C_BRCMSTB) += i2c-brcmstb.o
108obj-$(CONFIG_I2C_CROS_EC_TUNNEL) += i2c-cros-ec-tunnel.o 110obj-$(CONFIG_I2C_CROS_EC_TUNNEL) += i2c-cros-ec-tunnel.o
109obj-$(CONFIG_I2C_ELEKTOR) += i2c-elektor.o 111obj-$(CONFIG_I2C_ELEKTOR) += i2c-elektor.o
110obj-$(CONFIG_I2C_OPAL) += i2c-opal.o 112obj-$(CONFIG_I2C_OPAL) += i2c-opal.o
111obj-$(CONFIG_I2C_PCA_ISA) += i2c-pca-isa.o 113obj-$(CONFIG_I2C_PCA_ISA) += i2c-pca-isa.o
112obj-$(CONFIG_I2C_SIBYTE) += i2c-sibyte.o 114obj-$(CONFIG_I2C_SIBYTE) += i2c-sibyte.o
115obj-$(CONFIG_I2C_XGENE_SLIMPRO) += i2c-xgene-slimpro.o
113obj-$(CONFIG_SCx200_ACB) += scx200_acb.o 116obj-$(CONFIG_SCx200_ACB) += scx200_acb.o
114 117
115ccflags-$(CONFIG_I2C_DEBUG_BUS) := -DDEBUG 118ccflags-$(CONFIG_I2C_DEBUG_BUS) := -DDEBUG
diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
index ff23d1bdd230..1c758cd1e1ba 100644
--- a/drivers/i2c/busses/i2c-at91.c
+++ b/drivers/i2c/busses/i2c-at91.c
@@ -41,29 +41,41 @@
41 41
42/* AT91 TWI register definitions */ 42/* AT91 TWI register definitions */
43#define AT91_TWI_CR 0x0000 /* Control Register */ 43#define AT91_TWI_CR 0x0000 /* Control Register */
44#define AT91_TWI_START 0x0001 /* Send a Start Condition */ 44#define AT91_TWI_START BIT(0) /* Send a Start Condition */
45#define AT91_TWI_STOP 0x0002 /* Send a Stop Condition */ 45#define AT91_TWI_STOP BIT(1) /* Send a Stop Condition */
46#define AT91_TWI_MSEN 0x0004 /* Master Transfer Enable */ 46#define AT91_TWI_MSEN BIT(2) /* Master Transfer Enable */
47#define AT91_TWI_SVDIS 0x0020 /* Slave Transfer Disable */ 47#define AT91_TWI_MSDIS BIT(3) /* Master Transfer Disable */
48#define AT91_TWI_QUICK 0x0040 /* SMBus quick command */ 48#define AT91_TWI_SVEN BIT(4) /* Slave Transfer Enable */
49#define AT91_TWI_SWRST 0x0080 /* Software Reset */ 49#define AT91_TWI_SVDIS BIT(5) /* Slave Transfer Disable */
50#define AT91_TWI_QUICK BIT(6) /* SMBus quick command */
51#define AT91_TWI_SWRST BIT(7) /* Software Reset */
52#define AT91_TWI_ACMEN BIT(16) /* Alternative Command Mode Enable */
53#define AT91_TWI_ACMDIS BIT(17) /* Alternative Command Mode Disable */
54#define AT91_TWI_THRCLR BIT(24) /* Transmit Holding Register Clear */
55#define AT91_TWI_RHRCLR BIT(25) /* Receive Holding Register Clear */
56#define AT91_TWI_LOCKCLR BIT(26) /* Lock Clear */
57#define AT91_TWI_FIFOEN BIT(28) /* FIFO Enable */
58#define AT91_TWI_FIFODIS BIT(29) /* FIFO Disable */
50 59
51#define AT91_TWI_MMR 0x0004 /* Master Mode Register */ 60#define AT91_TWI_MMR 0x0004 /* Master Mode Register */
52#define AT91_TWI_IADRSZ_1 0x0100 /* Internal Device Address Size */ 61#define AT91_TWI_IADRSZ_1 0x0100 /* Internal Device Address Size */
53#define AT91_TWI_MREAD 0x1000 /* Master Read Direction */ 62#define AT91_TWI_MREAD BIT(12) /* Master Read Direction */
54 63
55#define AT91_TWI_IADR 0x000c /* Internal Address Register */ 64#define AT91_TWI_IADR 0x000c /* Internal Address Register */
56 65
57#define AT91_TWI_CWGR 0x0010 /* Clock Waveform Generator Reg */ 66#define AT91_TWI_CWGR 0x0010 /* Clock Waveform Generator Reg */
58 67
59#define AT91_TWI_SR 0x0020 /* Status Register */ 68#define AT91_TWI_SR 0x0020 /* Status Register */
60#define AT91_TWI_TXCOMP 0x0001 /* Transmission Complete */ 69#define AT91_TWI_TXCOMP BIT(0) /* Transmission Complete */
61#define AT91_TWI_RXRDY 0x0002 /* Receive Holding Register Ready */ 70#define AT91_TWI_RXRDY BIT(1) /* Receive Holding Register Ready */
62#define AT91_TWI_TXRDY 0x0004 /* Transmit Holding Register Ready */ 71#define AT91_TWI_TXRDY BIT(2) /* Transmit Holding Register Ready */
72#define AT91_TWI_OVRE BIT(6) /* Overrun Error */
73#define AT91_TWI_UNRE BIT(7) /* Underrun Error */
74#define AT91_TWI_NACK BIT(8) /* Not Acknowledged */
75#define AT91_TWI_LOCK BIT(23) /* TWI Lock due to Frame Errors */
63 76
64#define AT91_TWI_OVRE 0x0040 /* Overrun Error */ 77#define AT91_TWI_INT_MASK \
65#define AT91_TWI_UNRE 0x0080 /* Underrun Error */ 78 (AT91_TWI_TXCOMP | AT91_TWI_RXRDY | AT91_TWI_TXRDY | AT91_TWI_NACK)
66#define AT91_TWI_NACK 0x0100 /* Not Acknowledged */
67 79
68#define AT91_TWI_IER 0x0024 /* Interrupt Enable Register */ 80#define AT91_TWI_IER 0x0024 /* Interrupt Enable Register */
69#define AT91_TWI_IDR 0x0028 /* Interrupt Disable Register */ 81#define AT91_TWI_IDR 0x0028 /* Interrupt Disable Register */
@@ -71,17 +83,40 @@
71#define AT91_TWI_RHR 0x0030 /* Receive Holding Register */ 83#define AT91_TWI_RHR 0x0030 /* Receive Holding Register */
72#define AT91_TWI_THR 0x0034 /* Transmit Holding Register */ 84#define AT91_TWI_THR 0x0034 /* Transmit Holding Register */
73 85
86#define AT91_TWI_ACR 0x0040 /* Alternative Command Register */
87#define AT91_TWI_ACR_DATAL(len) ((len) & 0xff)
88#define AT91_TWI_ACR_DIR BIT(8)
89
90#define AT91_TWI_FMR 0x0050 /* FIFO Mode Register */
91#define AT91_TWI_FMR_TXRDYM(mode) (((mode) & 0x3) << 0)
92#define AT91_TWI_FMR_TXRDYM_MASK (0x3 << 0)
93#define AT91_TWI_FMR_RXRDYM(mode) (((mode) & 0x3) << 4)
94#define AT91_TWI_FMR_RXRDYM_MASK (0x3 << 4)
95#define AT91_TWI_ONE_DATA 0x0
96#define AT91_TWI_TWO_DATA 0x1
97#define AT91_TWI_FOUR_DATA 0x2
98
99#define AT91_TWI_FLR 0x0054 /* FIFO Level Register */
100
101#define AT91_TWI_FSR 0x0060 /* FIFO Status Register */
102#define AT91_TWI_FIER 0x0064 /* FIFO Interrupt Enable Register */
103#define AT91_TWI_FIDR 0x0068 /* FIFO Interrupt Disable Register */
104#define AT91_TWI_FIMR 0x006c /* FIFO Interrupt Mask Register */
105
106#define AT91_TWI_VER 0x00fc /* Version Register */
107
74struct at91_twi_pdata { 108struct at91_twi_pdata {
75 unsigned clk_max_div; 109 unsigned clk_max_div;
76 unsigned clk_offset; 110 unsigned clk_offset;
77 bool has_unre_flag; 111 bool has_unre_flag;
112 bool has_alt_cmd;
78 struct at_dma_slave dma_slave; 113 struct at_dma_slave dma_slave;
79}; 114};
80 115
81struct at91_twi_dma { 116struct at91_twi_dma {
82 struct dma_chan *chan_rx; 117 struct dma_chan *chan_rx;
83 struct dma_chan *chan_tx; 118 struct dma_chan *chan_tx;
84 struct scatterlist sg; 119 struct scatterlist sg[2];
85 struct dma_async_tx_descriptor *data_desc; 120 struct dma_async_tx_descriptor *data_desc;
86 enum dma_data_direction direction; 121 enum dma_data_direction direction;
87 bool buf_mapped; 122 bool buf_mapped;
@@ -104,6 +139,7 @@ struct at91_twi_dev {
104 struct at91_twi_pdata *pdata; 139 struct at91_twi_pdata *pdata;
105 bool use_dma; 140 bool use_dma;
106 bool recv_len_abort; 141 bool recv_len_abort;
142 u32 fifo_size;
107 struct at91_twi_dma dma; 143 struct at91_twi_dma dma;
108}; 144};
109 145
@@ -119,13 +155,12 @@ static void at91_twi_write(struct at91_twi_dev *dev, unsigned reg, unsigned val)
119 155
120static void at91_disable_twi_interrupts(struct at91_twi_dev *dev) 156static void at91_disable_twi_interrupts(struct at91_twi_dev *dev)
121{ 157{
122 at91_twi_write(dev, AT91_TWI_IDR, 158 at91_twi_write(dev, AT91_TWI_IDR, AT91_TWI_INT_MASK);
123 AT91_TWI_TXCOMP | AT91_TWI_RXRDY | AT91_TWI_TXRDY);
124} 159}
125 160
126static void at91_twi_irq_save(struct at91_twi_dev *dev) 161static void at91_twi_irq_save(struct at91_twi_dev *dev)
127{ 162{
128 dev->imr = at91_twi_read(dev, AT91_TWI_IMR) & 0x7; 163 dev->imr = at91_twi_read(dev, AT91_TWI_IMR) & AT91_TWI_INT_MASK;
129 at91_disable_twi_interrupts(dev); 164 at91_disable_twi_interrupts(dev);
130} 165}
131 166
@@ -138,6 +173,9 @@ static void at91_init_twi_bus(struct at91_twi_dev *dev)
138{ 173{
139 at91_disable_twi_interrupts(dev); 174 at91_disable_twi_interrupts(dev);
140 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SWRST); 175 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SWRST);
176 /* FIFO should be enabled immediately after the software reset */
177 if (dev->fifo_size)
178 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_FIFOEN);
141 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_MSEN); 179 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_MSEN);
142 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SVDIS); 180 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SVDIS);
143 at91_twi_write(dev, AT91_TWI_CWGR, dev->twi_cwgr_reg); 181 at91_twi_write(dev, AT91_TWI_CWGR, dev->twi_cwgr_reg);
@@ -184,7 +222,7 @@ static void at91_twi_dma_cleanup(struct at91_twi_dev *dev)
184 dma->xfer_in_progress = false; 222 dma->xfer_in_progress = false;
185 } 223 }
186 if (dma->buf_mapped) { 224 if (dma->buf_mapped) {
187 dma_unmap_single(dev->dev, sg_dma_address(&dma->sg), 225 dma_unmap_single(dev->dev, sg_dma_address(&dma->sg[0]),
188 dev->buf_len, dma->direction); 226 dev->buf_len, dma->direction);
189 dma->buf_mapped = false; 227 dma->buf_mapped = false;
190 } 228 }
@@ -194,14 +232,16 @@ static void at91_twi_dma_cleanup(struct at91_twi_dev *dev)
194 232
195static void at91_twi_write_next_byte(struct at91_twi_dev *dev) 233static void at91_twi_write_next_byte(struct at91_twi_dev *dev)
196{ 234{
197 if (dev->buf_len <= 0) 235 if (!dev->buf_len)
198 return; 236 return;
199 237
200 at91_twi_write(dev, AT91_TWI_THR, *dev->buf); 238 /* 8bit write works with and without FIFO */
239 writeb_relaxed(*dev->buf, dev->base + AT91_TWI_THR);
201 240
202 /* send stop when last byte has been written */ 241 /* send stop when last byte has been written */
203 if (--dev->buf_len == 0) 242 if (--dev->buf_len == 0)
204 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP); 243 if (!dev->pdata->has_alt_cmd)
244 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
205 245
206 dev_dbg(dev->dev, "wrote 0x%x, to go %d\n", *dev->buf, dev->buf_len); 246 dev_dbg(dev->dev, "wrote 0x%x, to go %d\n", *dev->buf, dev->buf_len);
207 247
@@ -212,10 +252,19 @@ static void at91_twi_write_data_dma_callback(void *data)
212{ 252{
213 struct at91_twi_dev *dev = (struct at91_twi_dev *)data; 253 struct at91_twi_dev *dev = (struct at91_twi_dev *)data;
214 254
215 dma_unmap_single(dev->dev, sg_dma_address(&dev->dma.sg), 255 dma_unmap_single(dev->dev, sg_dma_address(&dev->dma.sg[0]),
216 dev->buf_len, DMA_TO_DEVICE); 256 dev->buf_len, DMA_TO_DEVICE);
217 257
218 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP); 258 /*
259 * When this callback is called, THR/TX FIFO is likely not to be empty
260 * yet. So we have to wait for TXCOMP or NACK bits to be set into the
261 * Status Register to be sure that the STOP bit has been sent and the
262 * transfer is completed. The NACK interrupt has already been enabled,
263 * we just have to enable TXCOMP one.
264 */
265 at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
266 if (!dev->pdata->has_alt_cmd)
267 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
219} 268}
220 269
221static void at91_twi_write_data_dma(struct at91_twi_dev *dev) 270static void at91_twi_write_data_dma(struct at91_twi_dev *dev)
@@ -224,8 +273,9 @@ static void at91_twi_write_data_dma(struct at91_twi_dev *dev)
224 struct dma_async_tx_descriptor *txdesc; 273 struct dma_async_tx_descriptor *txdesc;
225 struct at91_twi_dma *dma = &dev->dma; 274 struct at91_twi_dma *dma = &dev->dma;
226 struct dma_chan *chan_tx = dma->chan_tx; 275 struct dma_chan *chan_tx = dma->chan_tx;
276 unsigned int sg_len = 1;
227 277
228 if (dev->buf_len <= 0) 278 if (!dev->buf_len)
229 return; 279 return;
230 280
231 dma->direction = DMA_TO_DEVICE; 281 dma->direction = DMA_TO_DEVICE;
@@ -239,10 +289,43 @@ static void at91_twi_write_data_dma(struct at91_twi_dev *dev)
239 } 289 }
240 dma->buf_mapped = true; 290 dma->buf_mapped = true;
241 at91_twi_irq_restore(dev); 291 at91_twi_irq_restore(dev);
242 sg_dma_len(&dma->sg) = dev->buf_len;
243 sg_dma_address(&dma->sg) = dma_addr;
244 292
245 txdesc = dmaengine_prep_slave_sg(chan_tx, &dma->sg, 1, DMA_MEM_TO_DEV, 293 if (dev->fifo_size) {
294 size_t part1_len, part2_len;
295 struct scatterlist *sg;
296 unsigned fifo_mr;
297
298 sg_len = 0;
299
300 part1_len = dev->buf_len & ~0x3;
301 if (part1_len) {
302 sg = &dma->sg[sg_len++];
303 sg_dma_len(sg) = part1_len;
304 sg_dma_address(sg) = dma_addr;
305 }
306
307 part2_len = dev->buf_len & 0x3;
308 if (part2_len) {
309 sg = &dma->sg[sg_len++];
310 sg_dma_len(sg) = part2_len;
311 sg_dma_address(sg) = dma_addr + part1_len;
312 }
313
314 /*
315 * DMA controller is triggered when at least 4 data can be
316 * written into the TX FIFO
317 */
318 fifo_mr = at91_twi_read(dev, AT91_TWI_FMR);
319 fifo_mr &= ~AT91_TWI_FMR_TXRDYM_MASK;
320 fifo_mr |= AT91_TWI_FMR_TXRDYM(AT91_TWI_FOUR_DATA);
321 at91_twi_write(dev, AT91_TWI_FMR, fifo_mr);
322 } else {
323 sg_dma_len(&dma->sg[0]) = dev->buf_len;
324 sg_dma_address(&dma->sg[0]) = dma_addr;
325 }
326
327 txdesc = dmaengine_prep_slave_sg(chan_tx, dma->sg, sg_len,
328 DMA_MEM_TO_DEV,
246 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 329 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
247 if (!txdesc) { 330 if (!txdesc) {
248 dev_err(dev->dev, "dma prep slave sg failed\n"); 331 dev_err(dev->dev, "dma prep slave sg failed\n");
@@ -264,10 +347,11 @@ error:
264 347
265static void at91_twi_read_next_byte(struct at91_twi_dev *dev) 348static void at91_twi_read_next_byte(struct at91_twi_dev *dev)
266{ 349{
267 if (dev->buf_len <= 0) 350 if (!dev->buf_len)
268 return; 351 return;
269 352
270 *dev->buf = at91_twi_read(dev, AT91_TWI_RHR) & 0xff; 353 /* 8bit read works with and without FIFO */
354 *dev->buf = readb_relaxed(dev->base + AT91_TWI_RHR);
271 --dev->buf_len; 355 --dev->buf_len;
272 356
273 /* return if aborting, we only needed to read RHR to clear RXRDY*/ 357 /* return if aborting, we only needed to read RHR to clear RXRDY*/
@@ -291,7 +375,7 @@ static void at91_twi_read_next_byte(struct at91_twi_dev *dev)
291 } 375 }
292 376
293 /* send stop if second but last byte has been read */ 377 /* send stop if second but last byte has been read */
294 if (dev->buf_len == 1) 378 if (!dev->pdata->has_alt_cmd && dev->buf_len == 1)
295 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP); 379 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
296 380
297 dev_dbg(dev->dev, "read 0x%x, to go %d\n", *dev->buf, dev->buf_len); 381 dev_dbg(dev->dev, "read 0x%x, to go %d\n", *dev->buf, dev->buf_len);
@@ -302,14 +386,18 @@ static void at91_twi_read_next_byte(struct at91_twi_dev *dev)
302static void at91_twi_read_data_dma_callback(void *data) 386static void at91_twi_read_data_dma_callback(void *data)
303{ 387{
304 struct at91_twi_dev *dev = (struct at91_twi_dev *)data; 388 struct at91_twi_dev *dev = (struct at91_twi_dev *)data;
389 unsigned ier = AT91_TWI_TXCOMP;
305 390
306 dma_unmap_single(dev->dev, sg_dma_address(&dev->dma.sg), 391 dma_unmap_single(dev->dev, sg_dma_address(&dev->dma.sg[0]),
307 dev->buf_len, DMA_FROM_DEVICE); 392 dev->buf_len, DMA_FROM_DEVICE);
308 393
309 /* The last two bytes have to be read without using dma */ 394 if (!dev->pdata->has_alt_cmd) {
310 dev->buf += dev->buf_len - 2; 395 /* The last two bytes have to be read without using dma */
311 dev->buf_len = 2; 396 dev->buf += dev->buf_len - 2;
312 at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_RXRDY); 397 dev->buf_len = 2;
398 ier |= AT91_TWI_RXRDY;
399 }
400 at91_twi_write(dev, AT91_TWI_IER, ier);
313} 401}
314 402
315static void at91_twi_read_data_dma(struct at91_twi_dev *dev) 403static void at91_twi_read_data_dma(struct at91_twi_dev *dev)
@@ -318,23 +406,38 @@ static void at91_twi_read_data_dma(struct at91_twi_dev *dev)
318 struct dma_async_tx_descriptor *rxdesc; 406 struct dma_async_tx_descriptor *rxdesc;
319 struct at91_twi_dma *dma = &dev->dma; 407 struct at91_twi_dma *dma = &dev->dma;
320 struct dma_chan *chan_rx = dma->chan_rx; 408 struct dma_chan *chan_rx = dma->chan_rx;
409 size_t buf_len;
321 410
411 buf_len = (dev->pdata->has_alt_cmd) ? dev->buf_len : dev->buf_len - 2;
322 dma->direction = DMA_FROM_DEVICE; 412 dma->direction = DMA_FROM_DEVICE;
323 413
324 /* Keep in mind that we won't use dma to read the last two bytes */ 414 /* Keep in mind that we won't use dma to read the last two bytes */
325 at91_twi_irq_save(dev); 415 at91_twi_irq_save(dev);
326 dma_addr = dma_map_single(dev->dev, dev->buf, dev->buf_len - 2, 416 dma_addr = dma_map_single(dev->dev, dev->buf, buf_len, DMA_FROM_DEVICE);
327 DMA_FROM_DEVICE);
328 if (dma_mapping_error(dev->dev, dma_addr)) { 417 if (dma_mapping_error(dev->dev, dma_addr)) {
329 dev_err(dev->dev, "dma map failed\n"); 418 dev_err(dev->dev, "dma map failed\n");
330 return; 419 return;
331 } 420 }
332 dma->buf_mapped = true; 421 dma->buf_mapped = true;
333 at91_twi_irq_restore(dev); 422 at91_twi_irq_restore(dev);
334 dma->sg.dma_address = dma_addr;
335 sg_dma_len(&dma->sg) = dev->buf_len - 2;
336 423
337 rxdesc = dmaengine_prep_slave_sg(chan_rx, &dma->sg, 1, DMA_DEV_TO_MEM, 424 if (dev->fifo_size && IS_ALIGNED(buf_len, 4)) {
425 unsigned fifo_mr;
426
427 /*
428 * DMA controller is triggered when at least 4 data can be
429 * read from the RX FIFO
430 */
431 fifo_mr = at91_twi_read(dev, AT91_TWI_FMR);
432 fifo_mr &= ~AT91_TWI_FMR_RXRDYM_MASK;
433 fifo_mr |= AT91_TWI_FMR_RXRDYM(AT91_TWI_FOUR_DATA);
434 at91_twi_write(dev, AT91_TWI_FMR, fifo_mr);
435 }
436
437 sg_dma_len(&dma->sg[0]) = buf_len;
438 sg_dma_address(&dma->sg[0]) = dma_addr;
439
440 rxdesc = dmaengine_prep_slave_sg(chan_rx, dma->sg, 1, DMA_DEV_TO_MEM,
338 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 441 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
339 if (!rxdesc) { 442 if (!rxdesc) {
340 dev_err(dev->dev, "dma prep slave sg failed\n"); 443 dev_err(dev->dev, "dma prep slave sg failed\n");
@@ -370,7 +473,7 @@ static irqreturn_t atmel_twi_interrupt(int irq, void *dev_id)
370 /* catch error flags */ 473 /* catch error flags */
371 dev->transfer_status |= status; 474 dev->transfer_status |= status;
372 475
373 if (irqstatus & AT91_TWI_TXCOMP) { 476 if (irqstatus & (AT91_TWI_TXCOMP | AT91_TWI_NACK)) {
374 at91_disable_twi_interrupts(dev); 477 at91_disable_twi_interrupts(dev);
375 complete(&dev->cmd_complete); 478 complete(&dev->cmd_complete);
376 } 479 }
@@ -383,6 +486,50 @@ static int at91_do_twi_transfer(struct at91_twi_dev *dev)
383 int ret; 486 int ret;
384 unsigned long time_left; 487 unsigned long time_left;
385 bool has_unre_flag = dev->pdata->has_unre_flag; 488 bool has_unre_flag = dev->pdata->has_unre_flag;
489 bool has_alt_cmd = dev->pdata->has_alt_cmd;
490
491 /*
492 * WARNING: the TXCOMP bit in the Status Register is NOT a clear on
493 * read flag but shows the state of the transmission at the time the
494 * Status Register is read. According to the programmer datasheet,
495 * TXCOMP is set when both holding register and internal shifter are
496 * empty and STOP condition has been sent.
497 * Consequently, we should enable NACK interrupt rather than TXCOMP to
498 * detect transmission failure.
499 * Indeed let's take the case of an i2c write command using DMA.
500 * Whenever the slave doesn't acknowledge a byte, the LOCK, NACK and
501 * TXCOMP bits are set together into the Status Register.
502 * LOCK is a clear on write bit, which is set to prevent the DMA
503 * controller from sending new data on the i2c bus after a NACK
504 * condition has happened. Once locked, this i2c peripheral stops
505 * triggering the DMA controller for new data but it is more than
506 * likely that a new DMA transaction is already in progress, writing
507 * into the Transmit Holding Register. Since the peripheral is locked,
508 * these new data won't be sent to the i2c bus but they will remain
509 * into the Transmit Holding Register, so TXCOMP bit is cleared.
510 * Then when the interrupt handler is called, the Status Register is
511 * read: the TXCOMP bit is clear but NACK bit is still set. The driver
512 * manage the error properly, without waiting for timeout.
513 * This case can be reproduced easyly when writing into an at24 eeprom.
514 *
515 * Besides, the TXCOMP bit is already set before the i2c transaction
516 * has been started. For read transactions, this bit is cleared when
517 * writing the START bit into the Control Register. So the
518 * corresponding interrupt can safely be enabled just after.
519 * However for write transactions managed by the CPU, we first write
520 * into THR, so TXCOMP is cleared. Then we can safely enable TXCOMP
521 * interrupt. If TXCOMP interrupt were enabled before writing into THR,
522 * the interrupt handler would be called immediately and the i2c command
523 * would be reported as completed.
524 * Also when a write transaction is managed by the DMA controller,
525 * enabling the TXCOMP interrupt in this function may lead to a race
526 * condition since we don't know whether the TXCOMP interrupt is enabled
527 * before or after the DMA has started to write into THR. So the TXCOMP
528 * interrupt is enabled later by at91_twi_write_data_dma_callback().
529 * Immediately after in that DMA callback, if the alternative command
530 * mode is not used, we still need to send the STOP condition manually
531 * writing the corresponding bit into the Control Register.
532 */
386 533
387 dev_dbg(dev->dev, "transfer: %s %d bytes.\n", 534 dev_dbg(dev->dev, "transfer: %s %d bytes.\n",
388 (dev->msg->flags & I2C_M_RD) ? "read" : "write", dev->buf_len); 535 (dev->msg->flags & I2C_M_RD) ? "read" : "write", dev->buf_len);
@@ -390,6 +537,21 @@ static int at91_do_twi_transfer(struct at91_twi_dev *dev)
390 reinit_completion(&dev->cmd_complete); 537 reinit_completion(&dev->cmd_complete);
391 dev->transfer_status = 0; 538 dev->transfer_status = 0;
392 539
540 if (dev->fifo_size) {
541 unsigned fifo_mr = at91_twi_read(dev, AT91_TWI_FMR);
542
543 /* Reset FIFO mode register */
544 fifo_mr &= ~(AT91_TWI_FMR_TXRDYM_MASK |
545 AT91_TWI_FMR_RXRDYM_MASK);
546 fifo_mr |= AT91_TWI_FMR_TXRDYM(AT91_TWI_ONE_DATA);
547 fifo_mr |= AT91_TWI_FMR_RXRDYM(AT91_TWI_ONE_DATA);
548 at91_twi_write(dev, AT91_TWI_FMR, fifo_mr);
549
550 /* Flush FIFOs */
551 at91_twi_write(dev, AT91_TWI_CR,
552 AT91_TWI_THRCLR | AT91_TWI_RHRCLR);
553 }
554
393 if (!dev->buf_len) { 555 if (!dev->buf_len) {
394 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_QUICK); 556 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_QUICK);
395 at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP); 557 at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
@@ -402,44 +564,45 @@ static int at91_do_twi_transfer(struct at91_twi_dev *dev)
402 } 564 }
403 565
404 /* if only one byte is to be read, immediately stop transfer */ 566 /* if only one byte is to be read, immediately stop transfer */
405 if (dev->buf_len <= 1 && !(dev->msg->flags & I2C_M_RECV_LEN)) 567 if (!has_alt_cmd && dev->buf_len <= 1 &&
568 !(dev->msg->flags & I2C_M_RECV_LEN))
406 start_flags |= AT91_TWI_STOP; 569 start_flags |= AT91_TWI_STOP;
407 at91_twi_write(dev, AT91_TWI_CR, start_flags); 570 at91_twi_write(dev, AT91_TWI_CR, start_flags);
408 /* 571 /*
409 * When using dma, the last byte has to be read manually in 572 * When using dma without alternative command mode, the last
410 * order to not send the stop command too late and then 573 * byte has to be read manually in order to not send the stop
411 * to receive extra data. In practice, there are some issues 574 * command too late and then to receive extra data.
412 * if you use the dma to read n-1 bytes because of latency. 575 * In practice, there are some issues if you use the dma to
576 * read n-1 bytes because of latency.
413 * Reading n-2 bytes with dma and the two last ones manually 577 * Reading n-2 bytes with dma and the two last ones manually
414 * seems to be the best solution. 578 * seems to be the best solution.
415 */ 579 */
416 if (dev->use_dma && (dev->buf_len > AT91_I2C_DMA_THRESHOLD)) { 580 if (dev->use_dma && (dev->buf_len > AT91_I2C_DMA_THRESHOLD)) {
581 at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_NACK);
417 at91_twi_read_data_dma(dev); 582 at91_twi_read_data_dma(dev);
418 /* 583 } else {
419 * It is important to enable TXCOMP irq here because
420 * doing it only when transferring the last two bytes
421 * will mask NACK errors since TXCOMP is set when a
422 * NACK occurs.
423 */
424 at91_twi_write(dev, AT91_TWI_IER,
425 AT91_TWI_TXCOMP);
426 } else
427 at91_twi_write(dev, AT91_TWI_IER, 584 at91_twi_write(dev, AT91_TWI_IER,
428 AT91_TWI_TXCOMP | AT91_TWI_RXRDY); 585 AT91_TWI_TXCOMP |
586 AT91_TWI_NACK |
587 AT91_TWI_RXRDY);
588 }
429 } else { 589 } else {
430 if (dev->use_dma && (dev->buf_len > AT91_I2C_DMA_THRESHOLD)) { 590 if (dev->use_dma && (dev->buf_len > AT91_I2C_DMA_THRESHOLD)) {
591 at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_NACK);
431 at91_twi_write_data_dma(dev); 592 at91_twi_write_data_dma(dev);
432 at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
433 } else { 593 } else {
434 at91_twi_write_next_byte(dev); 594 at91_twi_write_next_byte(dev);
435 at91_twi_write(dev, AT91_TWI_IER, 595 at91_twi_write(dev, AT91_TWI_IER,
436 AT91_TWI_TXCOMP | AT91_TWI_TXRDY); 596 AT91_TWI_TXCOMP |
597 AT91_TWI_NACK |
598 AT91_TWI_TXRDY);
437 } 599 }
438 } 600 }
439 601
440 time_left = wait_for_completion_timeout(&dev->cmd_complete, 602 time_left = wait_for_completion_timeout(&dev->cmd_complete,
441 dev->adapter.timeout); 603 dev->adapter.timeout);
442 if (time_left == 0) { 604 if (time_left == 0) {
605 dev->transfer_status |= at91_twi_read(dev, AT91_TWI_SR);
443 dev_err(dev->dev, "controller timed out\n"); 606 dev_err(dev->dev, "controller timed out\n");
444 at91_init_twi_bus(dev); 607 at91_init_twi_bus(dev);
445 ret = -ETIMEDOUT; 608 ret = -ETIMEDOUT;
@@ -460,6 +623,12 @@ static int at91_do_twi_transfer(struct at91_twi_dev *dev)
460 ret = -EIO; 623 ret = -EIO;
461 goto error; 624 goto error;
462 } 625 }
626 if ((has_alt_cmd || dev->fifo_size) &&
627 (dev->transfer_status & AT91_TWI_LOCK)) {
628 dev_err(dev->dev, "tx locked\n");
629 ret = -EIO;
630 goto error;
631 }
463 if (dev->recv_len_abort) { 632 if (dev->recv_len_abort) {
464 dev_err(dev->dev, "invalid smbus block length recvd\n"); 633 dev_err(dev->dev, "invalid smbus block length recvd\n");
465 ret = -EPROTO; 634 ret = -EPROTO;
@@ -471,7 +640,15 @@ static int at91_do_twi_transfer(struct at91_twi_dev *dev)
471 return 0; 640 return 0;
472 641
473error: 642error:
643 /* first stop DMA transfer if still in progress */
474 at91_twi_dma_cleanup(dev); 644 at91_twi_dma_cleanup(dev);
645 /* then flush THR/FIFO and unlock TX if locked */
646 if ((has_alt_cmd || dev->fifo_size) &&
647 (dev->transfer_status & AT91_TWI_LOCK)) {
648 dev_dbg(dev->dev, "unlock tx\n");
649 at91_twi_write(dev, AT91_TWI_CR,
650 AT91_TWI_THRCLR | AT91_TWI_LOCKCLR);
651 }
475 return ret; 652 return ret;
476} 653}
477 654
@@ -481,6 +658,7 @@ static int at91_twi_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, int num)
481 int ret; 658 int ret;
482 unsigned int_addr_flag = 0; 659 unsigned int_addr_flag = 0;
483 struct i2c_msg *m_start = msg; 660 struct i2c_msg *m_start = msg;
661 bool is_read, use_alt_cmd = false;
484 662
485 dev_dbg(&adap->dev, "at91_xfer: processing %d messages:\n", num); 663 dev_dbg(&adap->dev, "at91_xfer: processing %d messages:\n", num);
486 664
@@ -503,8 +681,23 @@ static int at91_twi_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, int num)
503 at91_twi_write(dev, AT91_TWI_IADR, internal_address); 681 at91_twi_write(dev, AT91_TWI_IADR, internal_address);
504 } 682 }
505 683
506 at91_twi_write(dev, AT91_TWI_MMR, (m_start->addr << 16) | int_addr_flag 684 is_read = (m_start->flags & I2C_M_RD);
507 | ((m_start->flags & I2C_M_RD) ? AT91_TWI_MREAD : 0)); 685 if (dev->pdata->has_alt_cmd) {
686 if (m_start->len > 0) {
687 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_ACMEN);
688 at91_twi_write(dev, AT91_TWI_ACR,
689 AT91_TWI_ACR_DATAL(m_start->len) |
690 ((is_read) ? AT91_TWI_ACR_DIR : 0));
691 use_alt_cmd = true;
692 } else {
693 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_ACMDIS);
694 }
695 }
696
697 at91_twi_write(dev, AT91_TWI_MMR,
698 (m_start->addr << 16) |
699 int_addr_flag |
700 ((!use_alt_cmd && is_read) ? AT91_TWI_MREAD : 0));
508 701
509 dev->buf_len = m_start->len; 702 dev->buf_len = m_start->len;
510 dev->buf = m_start->buf; 703 dev->buf = m_start->buf;
@@ -545,30 +738,35 @@ static struct at91_twi_pdata at91rm9200_config = {
545 .clk_max_div = 5, 738 .clk_max_div = 5,
546 .clk_offset = 3, 739 .clk_offset = 3,
547 .has_unre_flag = true, 740 .has_unre_flag = true,
741 .has_alt_cmd = false,
548}; 742};
549 743
550static struct at91_twi_pdata at91sam9261_config = { 744static struct at91_twi_pdata at91sam9261_config = {
551 .clk_max_div = 5, 745 .clk_max_div = 5,
552 .clk_offset = 4, 746 .clk_offset = 4,
553 .has_unre_flag = false, 747 .has_unre_flag = false,
748 .has_alt_cmd = false,
554}; 749};
555 750
556static struct at91_twi_pdata at91sam9260_config = { 751static struct at91_twi_pdata at91sam9260_config = {
557 .clk_max_div = 7, 752 .clk_max_div = 7,
558 .clk_offset = 4, 753 .clk_offset = 4,
559 .has_unre_flag = false, 754 .has_unre_flag = false,
755 .has_alt_cmd = false,
560}; 756};
561 757
562static struct at91_twi_pdata at91sam9g20_config = { 758static struct at91_twi_pdata at91sam9g20_config = {
563 .clk_max_div = 7, 759 .clk_max_div = 7,
564 .clk_offset = 4, 760 .clk_offset = 4,
565 .has_unre_flag = false, 761 .has_unre_flag = false,
762 .has_alt_cmd = false,
566}; 763};
567 764
568static struct at91_twi_pdata at91sam9g10_config = { 765static struct at91_twi_pdata at91sam9g10_config = {
569 .clk_max_div = 7, 766 .clk_max_div = 7,
570 .clk_offset = 4, 767 .clk_offset = 4,
571 .has_unre_flag = false, 768 .has_unre_flag = false,
769 .has_alt_cmd = false,
572}; 770};
573 771
574static const struct platform_device_id at91_twi_devtypes[] = { 772static const struct platform_device_id at91_twi_devtypes[] = {
@@ -597,6 +795,14 @@ static struct at91_twi_pdata at91sam9x5_config = {
597 .clk_max_div = 7, 795 .clk_max_div = 7,
598 .clk_offset = 4, 796 .clk_offset = 4,
599 .has_unre_flag = false, 797 .has_unre_flag = false,
798 .has_alt_cmd = false,
799};
800
801static struct at91_twi_pdata sama5d2_config = {
802 .clk_max_div = 7,
803 .clk_offset = 4,
804 .has_unre_flag = true,
805 .has_alt_cmd = true,
600}; 806};
601 807
602static const struct of_device_id atmel_twi_dt_ids[] = { 808static const struct of_device_id atmel_twi_dt_ids[] = {
@@ -619,6 +825,9 @@ static const struct of_device_id atmel_twi_dt_ids[] = {
619 .compatible = "atmel,at91sam9x5-i2c", 825 .compatible = "atmel,at91sam9x5-i2c",
620 .data = &at91sam9x5_config, 826 .data = &at91sam9x5_config,
621 }, { 827 }, {
828 .compatible = "atmel,sama5d2-i2c",
829 .data = &sama5d2_config,
830 }, {
622 /* sentinel */ 831 /* sentinel */
623 } 832 }
624}; 833};
@@ -630,13 +839,32 @@ static int at91_twi_configure_dma(struct at91_twi_dev *dev, u32 phy_addr)
630 int ret = 0; 839 int ret = 0;
631 struct dma_slave_config slave_config; 840 struct dma_slave_config slave_config;
632 struct at91_twi_dma *dma = &dev->dma; 841 struct at91_twi_dma *dma = &dev->dma;
842 enum dma_slave_buswidth addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
843
844 /*
845 * The actual width of the access will be chosen in
846 * dmaengine_prep_slave_sg():
847 * for each buffer in the scatter-gather list, if its size is aligned
848 * to addr_width then addr_width accesses will be performed to transfer
849 * the buffer. On the other hand, if the buffer size is not aligned to
850 * addr_width then the buffer is transferred using single byte accesses.
851 * Please refer to the Atmel eXtended DMA controller driver.
852 * When FIFOs are used, the TXRDYM threshold can always be set to
853 * trigger the XDMAC when at least 4 data can be written into the TX
854 * FIFO, even if single byte accesses are performed.
855 * However the RXRDYM threshold must be set to fit the access width,
856 * deduced from buffer length, so the XDMAC is triggered properly to
857 * read data from the RX FIFO.
858 */
859 if (dev->fifo_size)
860 addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
633 861
634 memset(&slave_config, 0, sizeof(slave_config)); 862 memset(&slave_config, 0, sizeof(slave_config));
635 slave_config.src_addr = (dma_addr_t)phy_addr + AT91_TWI_RHR; 863 slave_config.src_addr = (dma_addr_t)phy_addr + AT91_TWI_RHR;
636 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 864 slave_config.src_addr_width = addr_width;
637 slave_config.src_maxburst = 1; 865 slave_config.src_maxburst = 1;
638 slave_config.dst_addr = (dma_addr_t)phy_addr + AT91_TWI_THR; 866 slave_config.dst_addr = (dma_addr_t)phy_addr + AT91_TWI_THR;
639 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 867 slave_config.dst_addr_width = addr_width;
640 slave_config.dst_maxburst = 1; 868 slave_config.dst_maxburst = 1;
641 slave_config.device_fc = false; 869 slave_config.device_fc = false;
642 870
@@ -668,7 +896,7 @@ static int at91_twi_configure_dma(struct at91_twi_dev *dev, u32 phy_addr)
668 goto error; 896 goto error;
669 } 897 }
670 898
671 sg_init_table(&dma->sg, 1); 899 sg_init_table(dma->sg, 2);
672 dma->buf_mapped = false; 900 dma->buf_mapped = false;
673 dma->xfer_in_progress = false; 901 dma->xfer_in_progress = false;
674 dev->use_dma = true; 902 dev->use_dma = true;
@@ -754,6 +982,11 @@ static int at91_twi_probe(struct platform_device *pdev)
754 return rc; 982 return rc;
755 } 983 }
756 984
985 if (!of_property_read_u32(pdev->dev.of_node, "atmel,fifo-size",
986 &dev->fifo_size)) {
987 dev_info(dev->dev, "Using FIFO (%u data)\n", dev->fifo_size);
988 }
989
757 rc = of_property_read_u32(dev->dev->of_node, "clock-frequency", 990 rc = of_property_read_u32(dev->dev->of_node, "clock-frequency",
758 &bus_clk_rate); 991 &bus_clk_rate);
759 if (rc) 992 if (rc)
@@ -790,7 +1023,8 @@ static int at91_twi_probe(struct platform_device *pdev)
790 return rc; 1023 return rc;
791 } 1024 }
792 1025
793 dev_info(dev->dev, "AT91 i2c bus driver.\n"); 1026 dev_info(dev->dev, "AT91 i2c bus driver (hw version: %#x).\n",
1027 at91_twi_read(dev, AT91_TWI_VER));
794 return 0; 1028 return 0;
795} 1029}
796 1030
diff --git a/drivers/i2c/busses/i2c-axxia.c b/drivers/i2c/busses/i2c-axxia.c
index 32d883490863..c335cc7852f9 100644
--- a/drivers/i2c/busses/i2c-axxia.c
+++ b/drivers/i2c/busses/i2c-axxia.c
@@ -42,6 +42,10 @@
42#define IBML_LOW_SEXT 0x18 42#define IBML_LOW_SEXT 0x18
43#define TIMER_CLOCK_DIV 0x1c 43#define TIMER_CLOCK_DIV 0x1c
44#define I2C_BUS_MONITOR 0x20 44#define I2C_BUS_MONITOR 0x20
45#define BM_SDAC BIT(3)
46#define BM_SCLC BIT(2)
47#define BM_SDAS BIT(1)
48#define BM_SCLS BIT(0)
45#define SOFT_RESET 0x24 49#define SOFT_RESET 0x24
46#define MST_COMMAND 0x28 50#define MST_COMMAND 0x28
47#define CMD_BUSY (1<<3) 51#define CMD_BUSY (1<<3)
@@ -394,6 +398,9 @@ static int axxia_i2c_xfer_msg(struct axxia_i2c_dev *idev, struct i2c_msg *msg)
394 if (time_left == 0) 398 if (time_left == 0)
395 idev->msg_err = -ETIMEDOUT; 399 idev->msg_err = -ETIMEDOUT;
396 400
401 if (idev->msg_err == -ETIMEDOUT)
402 i2c_recover_bus(&idev->adapter);
403
397 if (unlikely(idev->msg_err) && idev->msg_err != -ENXIO) 404 if (unlikely(idev->msg_err) && idev->msg_err != -ENXIO)
398 axxia_i2c_init(idev); 405 axxia_i2c_init(idev);
399 406
@@ -437,6 +444,39 @@ axxia_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
437 return ret ? : i; 444 return ret ? : i;
438} 445}
439 446
447static int axxia_i2c_get_scl(struct i2c_adapter *adap)
448{
449 struct axxia_i2c_dev *idev = i2c_get_adapdata(adap);
450
451 return !!(readl(idev->base + I2C_BUS_MONITOR) & BM_SCLS);
452}
453
454static void axxia_i2c_set_scl(struct i2c_adapter *adap, int val)
455{
456 struct axxia_i2c_dev *idev = i2c_get_adapdata(adap);
457 u32 tmp;
458
459 /* Preserve SDA Control */
460 tmp = readl(idev->base + I2C_BUS_MONITOR) & BM_SDAC;
461 if (!val)
462 tmp |= BM_SCLC;
463 writel(tmp, idev->base + I2C_BUS_MONITOR);
464}
465
466static int axxia_i2c_get_sda(struct i2c_adapter *adap)
467{
468 struct axxia_i2c_dev *idev = i2c_get_adapdata(adap);
469
470 return !!(readl(idev->base + I2C_BUS_MONITOR) & BM_SDAS);
471}
472
473static struct i2c_bus_recovery_info axxia_i2c_recovery_info = {
474 .recover_bus = i2c_generic_scl_recovery,
475 .get_scl = axxia_i2c_get_scl,
476 .set_scl = axxia_i2c_set_scl,
477 .get_sda = axxia_i2c_get_sda,
478};
479
440static u32 axxia_i2c_func(struct i2c_adapter *adap) 480static u32 axxia_i2c_func(struct i2c_adapter *adap)
441{ 481{
442 u32 caps = (I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | 482 u32 caps = (I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR |
@@ -511,6 +551,7 @@ static int axxia_i2c_probe(struct platform_device *pdev)
511 strlcpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name)); 551 strlcpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name));
512 idev->adapter.owner = THIS_MODULE; 552 idev->adapter.owner = THIS_MODULE;
513 idev->adapter.algo = &axxia_i2c_algo; 553 idev->adapter.algo = &axxia_i2c_algo;
554 idev->adapter.bus_recovery_info = &axxia_i2c_recovery_info;
514 idev->adapter.quirks = &axxia_i2c_quirks; 555 idev->adapter.quirks = &axxia_i2c_quirks;
515 idev->adapter.dev.parent = &pdev->dev; 556 idev->adapter.dev.parent = &pdev->dev;
516 idev->adapter.dev.of_node = pdev->dev.of_node; 557 idev->adapter.dev.of_node = pdev->dev.of_node;
diff --git a/drivers/i2c/busses/i2c-bcm-iproc.c b/drivers/i2c/busses/i2c-bcm-iproc.c
index f9f2c2082151..0419f5284609 100644
--- a/drivers/i2c/busses/i2c-bcm-iproc.c
+++ b/drivers/i2c/busses/i2c-bcm-iproc.c
@@ -91,6 +91,7 @@ struct bcm_iproc_i2c_dev {
91 void __iomem *base; 91 void __iomem *base;
92 92
93 struct i2c_adapter adapter; 93 struct i2c_adapter adapter;
94 unsigned int bus_speed;
94 95
95 struct completion done; 96 struct completion done;
96 int xfer_is_done; 97 int xfer_is_done;
@@ -309,6 +310,7 @@ static int bcm_iproc_i2c_cfg_speed(struct bcm_iproc_i2c_dev *iproc_i2c)
309 bus_speed = 400000; 310 bus_speed = 400000;
310 } 311 }
311 312
313 iproc_i2c->bus_speed = bus_speed;
312 val = readl(iproc_i2c->base + TIM_CFG_OFFSET); 314 val = readl(iproc_i2c->base + TIM_CFG_OFFSET);
313 val &= ~(1 << TIM_CFG_MODE_400_SHIFT); 315 val &= ~(1 << TIM_CFG_MODE_400_SHIFT);
314 val |= (bus_speed == 400000) << TIM_CFG_MODE_400_SHIFT; 316 val |= (bus_speed == 400000) << TIM_CFG_MODE_400_SHIFT;
@@ -439,6 +441,60 @@ static int bcm_iproc_i2c_remove(struct platform_device *pdev)
439 return 0; 441 return 0;
440} 442}
441 443
444#ifdef CONFIG_PM_SLEEP
445
446static int bcm_iproc_i2c_suspend(struct device *dev)
447{
448 struct platform_device *pdev = to_platform_device(dev);
449 struct bcm_iproc_i2c_dev *iproc_i2c = platform_get_drvdata(pdev);
450
451 /* make sure there's no pending interrupt when we go into suspend */
452 writel(0, iproc_i2c->base + IE_OFFSET);
453 readl(iproc_i2c->base + IE_OFFSET);
454 synchronize_irq(iproc_i2c->irq);
455
456 /* now disable the controller */
457 bcm_iproc_i2c_enable_disable(iproc_i2c, false);
458
459 return 0;
460}
461
462static int bcm_iproc_i2c_resume(struct device *dev)
463{
464 struct platform_device *pdev = to_platform_device(dev);
465 struct bcm_iproc_i2c_dev *iproc_i2c = platform_get_drvdata(pdev);
466 int ret;
467 u32 val;
468
469 /*
470 * Power domain could have been shut off completely in system deep
471 * sleep, so re-initialize the block here
472 */
473 ret = bcm_iproc_i2c_init(iproc_i2c);
474 if (ret)
475 return ret;
476
477 /* configure to the desired bus speed */
478 val = readl(iproc_i2c->base + TIM_CFG_OFFSET);
479 val &= ~(1 << TIM_CFG_MODE_400_SHIFT);
480 val |= (iproc_i2c->bus_speed == 400000) << TIM_CFG_MODE_400_SHIFT;
481 writel(val, iproc_i2c->base + TIM_CFG_OFFSET);
482
483 bcm_iproc_i2c_enable_disable(iproc_i2c, true);
484
485 return 0;
486}
487
488static const struct dev_pm_ops bcm_iproc_i2c_pm_ops = {
489 .suspend_late = &bcm_iproc_i2c_suspend,
490 .resume_early = &bcm_iproc_i2c_resume
491};
492
493#define BCM_IPROC_I2C_PM_OPS (&bcm_iproc_i2c_pm_ops)
494#else
495#define BCM_IPROC_I2C_PM_OPS NULL
496#endif /* CONFIG_PM_SLEEP */
497
442static const struct of_device_id bcm_iproc_i2c_of_match[] = { 498static const struct of_device_id bcm_iproc_i2c_of_match[] = {
443 { .compatible = "brcm,iproc-i2c" }, 499 { .compatible = "brcm,iproc-i2c" },
444 { /* sentinel */ } 500 { /* sentinel */ }
@@ -449,6 +505,7 @@ static struct platform_driver bcm_iproc_i2c_driver = {
449 .driver = { 505 .driver = {
450 .name = "bcm-iproc-i2c", 506 .name = "bcm-iproc-i2c",
451 .of_match_table = bcm_iproc_i2c_of_match, 507 .of_match_table = bcm_iproc_i2c_of_match,
508 .pm = BCM_IPROC_I2C_PM_OPS,
452 }, 509 },
453 .probe = bcm_iproc_i2c_probe, 510 .probe = bcm_iproc_i2c_probe,
454 .remove = bcm_iproc_i2c_remove, 511 .remove = bcm_iproc_i2c_remove,
diff --git a/drivers/i2c/busses/i2c-bcm2835.c b/drivers/i2c/busses/i2c-bcm2835.c
index c9336a3202d5..3032b89ac60b 100644
--- a/drivers/i2c/busses/i2c-bcm2835.c
+++ b/drivers/i2c/busses/i2c-bcm2835.c
@@ -50,6 +50,11 @@
50#define BCM2835_I2C_S_CLKT BIT(9) 50#define BCM2835_I2C_S_CLKT BIT(9)
51#define BCM2835_I2C_S_LEN BIT(10) /* Fake bit for SW error reporting */ 51#define BCM2835_I2C_S_LEN BIT(10) /* Fake bit for SW error reporting */
52 52
53#define BCM2835_I2C_BITMSK_S 0x03FF
54
55#define BCM2835_I2C_CDIV_MIN 0x0002
56#define BCM2835_I2C_CDIV_MAX 0xFFFE
57
53#define BCM2835_I2C_TIMEOUT (msecs_to_jiffies(1000)) 58#define BCM2835_I2C_TIMEOUT (msecs_to_jiffies(1000))
54 59
55struct bcm2835_i2c_dev { 60struct bcm2835_i2c_dev {
@@ -111,6 +116,7 @@ static irqreturn_t bcm2835_i2c_isr(int this_irq, void *data)
111 u32 val, err; 116 u32 val, err;
112 117
113 val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S); 118 val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);
119 val &= BCM2835_I2C_BITMSK_S;
114 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_S, val); 120 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_S, val);
115 121
116 err = val & (BCM2835_I2C_S_CLKT | BCM2835_I2C_S_ERR); 122 err = val & (BCM2835_I2C_S_CLKT | BCM2835_I2C_S_ERR);
@@ -258,6 +264,11 @@ static int bcm2835_i2c_probe(struct platform_device *pdev)
258 */ 264 */
259 if (divider & 1) 265 if (divider & 1)
260 divider++; 266 divider++;
267 if ((divider < BCM2835_I2C_CDIV_MIN) ||
268 (divider > BCM2835_I2C_CDIV_MAX)) {
269 dev_err(&pdev->dev, "Invalid clock-frequency\n");
270 return -ENODEV;
271 }
261 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DIV, divider); 272 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DIV, divider);
262 273
263 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 274 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
diff --git a/drivers/i2c/busses/i2c-brcmstb.c b/drivers/i2c/busses/i2c-brcmstb.c
new file mode 100644
index 000000000000..8e9637eea512
--- /dev/null
+++ b/drivers/i2c/busses/i2c-brcmstb.c
@@ -0,0 +1,694 @@
1/*
2 * Copyright (C) 2014 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/clk.h>
15#include <linux/delay.h>
16#include <linux/device.h>
17#include <linux/i2c.h>
18#include <linux/interrupt.h>
19#include <linux/io.h>
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/platform_device.h>
23#include <linux/sched.h>
24#include <linux/slab.h>
25#include <linux/version.h>
26
27#define N_DATA_REGS 8
28#define N_DATA_BYTES (N_DATA_REGS * 4)
29
30/* BSC count register field definitions */
31#define BSC_CNT_REG1_MASK 0x0000003f
32#define BSC_CNT_REG1_SHIFT 0
33#define BSC_CNT_REG2_MASK 0x00000fc0
34#define BSC_CNT_REG2_SHIFT 6
35
36/* BSC CTL register field definitions */
37#define BSC_CTL_REG_DTF_MASK 0x00000003
38#define BSC_CTL_REG_SCL_SEL_MASK 0x00000030
39#define BSC_CTL_REG_SCL_SEL_SHIFT 4
40#define BSC_CTL_REG_INT_EN_MASK 0x00000040
41#define BSC_CTL_REG_INT_EN_SHIFT 6
42#define BSC_CTL_REG_DIV_CLK_MASK 0x00000080
43
44/* BSC_IIC_ENABLE r/w enable and interrupt field defintions */
45#define BSC_IIC_EN_RESTART_MASK 0x00000040
46#define BSC_IIC_EN_NOSTART_MASK 0x00000020
47#define BSC_IIC_EN_NOSTOP_MASK 0x00000010
48#define BSC_IIC_EN_NOACK_MASK 0x00000004
49#define BSC_IIC_EN_INTRP_MASK 0x00000002
50#define BSC_IIC_EN_ENABLE_MASK 0x00000001
51
52/* BSC_CTLHI control register field definitions */
53#define BSC_CTLHI_REG_INPUT_SWITCHING_LEVEL_MASK 0x00000080
54#define BSC_CTLHI_REG_DATAREG_SIZE_MASK 0x00000040
55#define BSC_CTLHI_REG_IGNORE_ACK_MASK 0x00000002
56#define BSC_CTLHI_REG_WAIT_DIS_MASK 0x00000001
57
58#define I2C_TIMEOUT 100 /* msecs */
59
60/* Condition mask used for non combined transfer */
61#define COND_RESTART BSC_IIC_EN_RESTART_MASK
62#define COND_NOSTART BSC_IIC_EN_NOSTART_MASK
63#define COND_NOSTOP BSC_IIC_EN_NOSTOP_MASK
64#define COND_START_STOP (COND_RESTART | COND_NOSTART | COND_NOSTOP)
65
66/* BSC data transfer direction */
67#define DTF_WR_MASK 0x00000000
68#define DTF_RD_MASK 0x00000001
69/* BSC data transfer direction combined format */
70#define DTF_RD_WR_MASK 0x00000002
71#define DTF_WR_RD_MASK 0x00000003
72
73#define INT_ENABLE true
74#define INT_DISABLE false
75
76/* BSC block register map structure to cache fields to be written */
77struct bsc_regs {
78 u32 chip_address; /* slave address */
79 u32 data_in[N_DATA_REGS]; /* tx data buffer*/
80 u32 cnt_reg; /* rx/tx data length */
81 u32 ctl_reg; /* control register */
82 u32 iic_enable; /* xfer enable and status */
83 u32 data_out[N_DATA_REGS]; /* rx data buffer */
84 u32 ctlhi_reg; /* more control fields */
85 u32 scl_param; /* reserved */
86};
87
88struct bsc_clk_param {
89 u32 hz;
90 u32 scl_mask;
91 u32 div_mask;
92};
93
94enum bsc_xfer_cmd {
95 CMD_WR,
96 CMD_RD,
97 CMD_WR_NOACK,
98 CMD_RD_NOACK,
99};
100
101static char const *cmd_string[] = {
102 [CMD_WR] = "WR",
103 [CMD_RD] = "RD",
104 [CMD_WR_NOACK] = "WR NOACK",
105 [CMD_RD_NOACK] = "RD NOACK",
106};
107
108enum bus_speeds {
109 SPD_375K,
110 SPD_390K,
111 SPD_187K,
112 SPD_200K,
113 SPD_93K,
114 SPD_97K,
115 SPD_46K,
116 SPD_50K
117};
118
119static const struct bsc_clk_param bsc_clk[] = {
120 [SPD_375K] = {
121 .hz = 375000,
122 .scl_mask = SPD_375K << BSC_CTL_REG_SCL_SEL_SHIFT,
123 .div_mask = 0
124 },
125 [SPD_390K] = {
126 .hz = 390000,
127 .scl_mask = SPD_390K << BSC_CTL_REG_SCL_SEL_SHIFT,
128 .div_mask = 0
129 },
130 [SPD_187K] = {
131 .hz = 187500,
132 .scl_mask = SPD_187K << BSC_CTL_REG_SCL_SEL_SHIFT,
133 .div_mask = 0
134 },
135 [SPD_200K] = {
136 .hz = 200000,
137 .scl_mask = SPD_200K << BSC_CTL_REG_SCL_SEL_SHIFT,
138 .div_mask = 0
139 },
140 [SPD_93K] = {
141 .hz = 93750,
142 .scl_mask = SPD_375K << BSC_CTL_REG_SCL_SEL_SHIFT,
143 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
144 },
145 [SPD_97K] = {
146 .hz = 97500,
147 .scl_mask = SPD_390K << BSC_CTL_REG_SCL_SEL_SHIFT,
148 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
149 },
150 [SPD_46K] = {
151 .hz = 46875,
152 .scl_mask = SPD_187K << BSC_CTL_REG_SCL_SEL_SHIFT,
153 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
154 },
155 [SPD_50K] = {
156 .hz = 50000,
157 .scl_mask = SPD_200K << BSC_CTL_REG_SCL_SEL_SHIFT,
158 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
159 }
160};
161
162struct brcmstb_i2c_dev {
163 struct device *device;
164 void __iomem *base;
165 void __iomem *irq_base;
166 int irq;
167 struct bsc_regs *bsc_regmap;
168 struct i2c_adapter adapter;
169 struct completion done;
170 bool is_suspended;
171 u32 clk_freq_hz;
172};
173
174/* register accessors for both be and le cpu arch */
175#ifdef CONFIG_CPU_BIG_ENDIAN
176#define __bsc_readl(_reg) ioread32be(_reg)
177#define __bsc_writel(_val, _reg) iowrite32be(_val, _reg)
178#else
179#define __bsc_readl(_reg) ioread32(_reg)
180#define __bsc_writel(_val, _reg) iowrite32(_val, _reg)
181#endif
182
183#define bsc_readl(_dev, _reg) \
184 __bsc_readl(_dev->base + offsetof(struct bsc_regs, _reg))
185
186#define bsc_writel(_dev, _val, _reg) \
187 __bsc_writel(_val, _dev->base + offsetof(struct bsc_regs, _reg))
188
189static void brcmstb_i2c_enable_disable_irq(struct brcmstb_i2c_dev *dev,
190 bool int_en)
191{
192
193 if (int_en)
194 /* Enable BSC CTL interrupt line */
195 dev->bsc_regmap->ctl_reg |= BSC_CTL_REG_INT_EN_MASK;
196 else
197 /* Disable BSC CTL interrupt line */
198 dev->bsc_regmap->ctl_reg &= ~BSC_CTL_REG_INT_EN_MASK;
199
200 barrier();
201 bsc_writel(dev, dev->bsc_regmap->ctl_reg, ctl_reg);
202}
203
204static irqreturn_t brcmstb_i2c_isr(int irq, void *devid)
205{
206 struct brcmstb_i2c_dev *dev = devid;
207 u32 status_bsc_ctl = bsc_readl(dev, ctl_reg);
208 u32 status_iic_intrp = bsc_readl(dev, iic_enable);
209
210 dev_dbg(dev->device, "isr CTL_REG %x IIC_EN %x\n",
211 status_bsc_ctl, status_iic_intrp);
212
213 if (!(status_bsc_ctl & BSC_CTL_REG_INT_EN_MASK))
214 return IRQ_NONE;
215
216 brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE);
217 complete_all(&dev->done);
218
219 dev_dbg(dev->device, "isr handled");
220 return IRQ_HANDLED;
221}
222
223/* Wait for device to be ready */
224static int brcmstb_i2c_wait_if_busy(struct brcmstb_i2c_dev *dev)
225{
226 unsigned long timeout = jiffies + msecs_to_jiffies(I2C_TIMEOUT);
227
228 while ((bsc_readl(dev, iic_enable) & BSC_IIC_EN_INTRP_MASK)) {
229 if (time_after(jiffies, timeout))
230 return -ETIMEDOUT;
231 cpu_relax();
232 }
233 return 0;
234}
235
236/* i2c xfer completion function, handles both irq and polling mode */
237static int brcmstb_i2c_wait_for_completion(struct brcmstb_i2c_dev *dev)
238{
239 int ret = 0;
240 unsigned long timeout = msecs_to_jiffies(I2C_TIMEOUT);
241
242 if (dev->irq >= 0) {
243 if (!wait_for_completion_timeout(&dev->done, timeout))
244 ret = -ETIMEDOUT;
245 } else {
246 /* we are in polling mode */
247 u32 bsc_intrp;
248 unsigned long time_left = jiffies + timeout;
249
250 do {
251 bsc_intrp = bsc_readl(dev, iic_enable) &
252 BSC_IIC_EN_INTRP_MASK;
253 if (time_after(jiffies, time_left)) {
254 ret = -ETIMEDOUT;
255 break;
256 }
257 cpu_relax();
258 } while (!bsc_intrp);
259 }
260
261 if (dev->irq < 0 || ret == -ETIMEDOUT)
262 brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE);
263
264 return ret;
265}
266
267/* Set xfer START/STOP conditions for subsequent transfer */
268static void brcmstb_set_i2c_start_stop(struct brcmstb_i2c_dev *dev,
269 u32 cond_flag)
270{
271 u32 regval = dev->bsc_regmap->iic_enable;
272
273 dev->bsc_regmap->iic_enable = (regval & ~COND_START_STOP) | cond_flag;
274}
275
276/* Send I2C request check completion */
277static int brcmstb_send_i2c_cmd(struct brcmstb_i2c_dev *dev,
278 enum bsc_xfer_cmd cmd)
279{
280 int rc = 0;
281 struct bsc_regs *pi2creg = dev->bsc_regmap;
282
283 /* Make sure the hardware is ready */
284 rc = brcmstb_i2c_wait_if_busy(dev);
285 if (rc < 0)
286 return rc;
287
288 /* only if we are in interrupt mode */
289 if (dev->irq >= 0)
290 reinit_completion(&dev->done);
291
292 /* enable BSC CTL interrupt line */
293 brcmstb_i2c_enable_disable_irq(dev, INT_ENABLE);
294
295 /* initiate transfer by setting iic_enable */
296 pi2creg->iic_enable |= BSC_IIC_EN_ENABLE_MASK;
297 bsc_writel(dev, pi2creg->iic_enable, iic_enable);
298
299 /* Wait for transaction to finish or timeout */
300 rc = brcmstb_i2c_wait_for_completion(dev);
301 if (rc) {
302 dev_dbg(dev->device, "intr timeout for cmd %s\n",
303 cmd_string[cmd]);
304 goto cmd_out;
305 }
306
307 if ((CMD_RD || CMD_WR) &&
308 bsc_readl(dev, iic_enable) & BSC_IIC_EN_NOACK_MASK) {
309 rc = -EREMOTEIO;
310 dev_dbg(dev->device, "controller received NOACK intr for %s\n",
311 cmd_string[cmd]);
312 }
313
314cmd_out:
315 bsc_writel(dev, 0, cnt_reg);
316 bsc_writel(dev, 0, iic_enable);
317
318 return rc;
319}
320
321/* Actual data transfer through the BSC master */
322static int brcmstb_i2c_xfer_bsc_data(struct brcmstb_i2c_dev *dev,
323 u8 *buf, unsigned int len,
324 struct i2c_msg *pmsg)
325{
326 int cnt, byte, rc;
327 enum bsc_xfer_cmd cmd;
328 u32 ctl_reg;
329 struct bsc_regs *pi2creg = dev->bsc_regmap;
330 int no_ack = pmsg->flags & I2C_M_IGNORE_NAK;
331
332 /* see if the transaction needs to check NACK conditions */
333 if (no_ack || len <= N_DATA_BYTES) {
334 cmd = (pmsg->flags & I2C_M_RD) ? CMD_RD_NOACK
335 : CMD_WR_NOACK;
336 pi2creg->ctlhi_reg |= BSC_CTLHI_REG_IGNORE_ACK_MASK;
337 } else {
338 cmd = (pmsg->flags & I2C_M_RD) ? CMD_RD : CMD_WR;
339 pi2creg->ctlhi_reg &= ~BSC_CTLHI_REG_IGNORE_ACK_MASK;
340 }
341 bsc_writel(dev, pi2creg->ctlhi_reg, ctlhi_reg);
342
343 /* set data transfer direction */
344 ctl_reg = pi2creg->ctl_reg & ~BSC_CTL_REG_DTF_MASK;
345 if (cmd == CMD_WR || cmd == CMD_WR_NOACK)
346 pi2creg->ctl_reg = ctl_reg | DTF_WR_MASK;
347 else
348 pi2creg->ctl_reg = ctl_reg | DTF_RD_MASK;
349
350 /* set the read/write length */
351 bsc_writel(dev, BSC_CNT_REG1_MASK & (len << BSC_CNT_REG1_SHIFT),
352 cnt_reg);
353
354 /* Write data into data_in register */
355 if (cmd == CMD_WR || cmd == CMD_WR_NOACK) {
356 for (cnt = 0; cnt < len; cnt += 4) {
357 u32 word = 0;
358
359 for (byte = 0; byte < 4; byte++) {
360 word >>= 8;
361 if ((cnt + byte) < len)
362 word |= buf[cnt + byte] << 24;
363 }
364 bsc_writel(dev, word, data_in[cnt >> 2]);
365 }
366 }
367
368 /* Initiate xfer, the function will return on completion */
369 rc = brcmstb_send_i2c_cmd(dev, cmd);
370
371 if (rc != 0) {
372 dev_dbg(dev->device, "%s failure", cmd_string[cmd]);
373 return rc;
374 }
375
376 if (cmd == CMD_RD || cmd == CMD_RD_NOACK) {
377 for (cnt = 0; cnt < len; cnt += 4) {
378 u32 data = bsc_readl(dev, data_out[cnt >> 2]);
379
380 for (byte = 0; byte < 4 &&
381 (byte + cnt) < len; byte++) {
382 buf[cnt + byte] = data & 0xff;
383 data >>= 8;
384 }
385 }
386 }
387
388 return 0;
389}
390
391/* Write a single byte of data to the i2c bus */
392static int brcmstb_i2c_write_data_byte(struct brcmstb_i2c_dev *dev,
393 u8 *buf, unsigned int nak_expected)
394{
395 enum bsc_xfer_cmd cmd = nak_expected ? CMD_WR : CMD_WR_NOACK;
396
397 bsc_writel(dev, 1, cnt_reg);
398 bsc_writel(dev, *buf, data_in);
399
400 return brcmstb_send_i2c_cmd(dev, cmd);
401}
402
403/* Send i2c address */
404static int brcmstb_i2c_do_addr(struct brcmstb_i2c_dev *dev,
405 struct i2c_msg *msg)
406{
407 unsigned char addr;
408
409 if (msg->flags & I2C_M_TEN) {
410 /* First byte is 11110XX0 where XX is upper 2 bits */
411 addr = 0xF0 | ((msg->addr & 0x300) >> 7);
412 bsc_writel(dev, addr, chip_address);
413
414 /* Second byte is the remaining 8 bits */
415 addr = msg->addr & 0xFF;
416 if (brcmstb_i2c_write_data_byte(dev, &addr, 0) < 0)
417 return -EREMOTEIO;
418
419 if (msg->flags & I2C_M_RD) {
420 /* For read, send restart without stop condition */
421 brcmstb_set_i2c_start_stop(dev, COND_RESTART
422 | COND_NOSTOP);
423 /* Then re-send the first byte with the read bit set */
424 addr = 0xF0 | ((msg->addr & 0x300) >> 7) | 0x01;
425 if (brcmstb_i2c_write_data_byte(dev, &addr, 0) < 0)
426 return -EREMOTEIO;
427
428 }
429 } else {
430 addr = msg->addr << 1;
431 if (msg->flags & I2C_M_RD)
432 addr |= 1;
433
434 bsc_writel(dev, addr, chip_address);
435 }
436
437 return 0;
438}
439
440/* Master transfer function */
441static int brcmstb_i2c_xfer(struct i2c_adapter *adapter,
442 struct i2c_msg msgs[], int num)
443{
444 struct brcmstb_i2c_dev *dev = i2c_get_adapdata(adapter);
445 struct i2c_msg *pmsg;
446 int rc = 0;
447 int i;
448 int bytes_to_xfer;
449 u8 *tmp_buf;
450 int len = 0;
451
452 if (dev->is_suspended)
453 return -EBUSY;
454
455 /* Loop through all messages */
456 for (i = 0; i < num; i++) {
457 pmsg = &msgs[i];
458 len = pmsg->len;
459 tmp_buf = pmsg->buf;
460
461 dev_dbg(dev->device,
462 "msg# %d/%d flg %x buf %x len %d\n", i,
463 num - 1, pmsg->flags,
464 pmsg->buf ? pmsg->buf[0] : '0', pmsg->len);
465
466 if (i < (num - 1) && (msgs[i + 1].flags & I2C_M_NOSTART))
467 brcmstb_set_i2c_start_stop(dev, ~(COND_START_STOP));
468 else
469 brcmstb_set_i2c_start_stop(dev,
470 COND_RESTART | COND_NOSTOP);
471
472 /* Send slave address */
473 if (!(pmsg->flags & I2C_M_NOSTART)) {
474 rc = brcmstb_i2c_do_addr(dev, pmsg);
475 if (rc < 0) {
476 dev_dbg(dev->device,
477 "NACK for addr %2.2x msg#%d rc = %d\n",
478 pmsg->addr, i, rc);
479 goto out;
480 }
481 }
482
483 /* Perform data transfer */
484 while (len) {
485 bytes_to_xfer = min(len, N_DATA_BYTES);
486
487 if (len <= N_DATA_BYTES && i == (num - 1))
488 brcmstb_set_i2c_start_stop(dev,
489 ~(COND_START_STOP));
490
491 rc = brcmstb_i2c_xfer_bsc_data(dev, tmp_buf,
492 bytes_to_xfer, pmsg);
493 if (rc < 0)
494 goto out;
495
496 len -= bytes_to_xfer;
497 tmp_buf += bytes_to_xfer;
498 }
499 }
500
501 rc = num;
502out:
503 return rc;
504
505}
506
507static u32 brcmstb_i2c_functionality(struct i2c_adapter *adap)
508{
509 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR
510 | I2C_FUNC_NOSTART | I2C_FUNC_PROTOCOL_MANGLING;
511}
512
513static const struct i2c_algorithm brcmstb_i2c_algo = {
514 .master_xfer = brcmstb_i2c_xfer,
515 .functionality = brcmstb_i2c_functionality,
516};
517
518static void brcmstb_i2c_set_bus_speed(struct brcmstb_i2c_dev *dev)
519{
520 int i = 0, num_speeds = ARRAY_SIZE(bsc_clk);
521 u32 clk_freq_hz = dev->clk_freq_hz;
522
523 for (i = 0; i < num_speeds; i++) {
524 if (bsc_clk[i].hz == clk_freq_hz) {
525 dev->bsc_regmap->ctl_reg &= ~(BSC_CTL_REG_SCL_SEL_MASK
526 | BSC_CTL_REG_DIV_CLK_MASK);
527 dev->bsc_regmap->ctl_reg |= (bsc_clk[i].scl_mask |
528 bsc_clk[i].div_mask);
529 bsc_writel(dev, dev->bsc_regmap->ctl_reg, ctl_reg);
530 break;
531 }
532 }
533
534 /* in case we did not get find a valid speed */
535 if (i == num_speeds) {
536 i = (bsc_readl(dev, ctl_reg) & BSC_CTL_REG_SCL_SEL_MASK) >>
537 BSC_CTL_REG_SCL_SEL_SHIFT;
538 dev_warn(dev->device, "leaving current clock-frequency @ %dHz\n",
539 bsc_clk[i].hz);
540 }
541}
542
543static void brcmstb_i2c_set_bsc_reg_defaults(struct brcmstb_i2c_dev *dev)
544{
545 /* 4 byte data register */
546 dev->bsc_regmap->ctlhi_reg = BSC_CTLHI_REG_DATAREG_SIZE_MASK;
547 bsc_writel(dev, dev->bsc_regmap->ctlhi_reg, ctlhi_reg);
548 /* set bus speed */
549 brcmstb_i2c_set_bus_speed(dev);
550}
551
552static int brcmstb_i2c_probe(struct platform_device *pdev)
553{
554 int rc = 0;
555 struct brcmstb_i2c_dev *dev;
556 struct i2c_adapter *adap;
557 struct resource *iomem;
558 const char *int_name;
559
560 /* Allocate memory for private data structure */
561 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
562 if (!dev)
563 return -ENOMEM;
564
565 dev->bsc_regmap = devm_kzalloc(&pdev->dev, sizeof(struct bsc_regs *),
566 GFP_KERNEL);
567 if (!dev->bsc_regmap)
568 return -ENOMEM;
569
570 platform_set_drvdata(pdev, dev);
571 dev->device = &pdev->dev;
572 init_completion(&dev->done);
573
574 /* Map hardware registers */
575 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
576 dev->base = devm_ioremap_resource(dev->device, iomem);
577 if (IS_ERR(dev->base)) {
578 rc = -ENOMEM;
579 goto probe_errorout;
580 }
581
582 rc = of_property_read_string(dev->device->of_node, "interrupt-names",
583 &int_name);
584 if (rc < 0)
585 int_name = NULL;
586
587 /* Get the interrupt number */
588 dev->irq = platform_get_irq(pdev, 0);
589
590 /* disable the bsc interrupt line */
591 brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE);
592
593 /* register the ISR handler */
594 rc = devm_request_irq(&pdev->dev, dev->irq, brcmstb_i2c_isr,
595 IRQF_SHARED,
596 int_name ? int_name : pdev->name,
597 dev);
598
599 if (rc) {
600 dev_dbg(dev->device, "falling back to polling mode");
601 dev->irq = -1;
602 }
603
604 if (of_property_read_u32(dev->device->of_node,
605 "clock-frequency", &dev->clk_freq_hz)) {
606 dev_warn(dev->device, "setting clock-frequency@%dHz\n",
607 bsc_clk[0].hz);
608 dev->clk_freq_hz = bsc_clk[0].hz;
609 }
610
611 brcmstb_i2c_set_bsc_reg_defaults(dev);
612
613 /* Add the i2c adapter */
614 adap = &dev->adapter;
615 i2c_set_adapdata(adap, dev);
616 adap->owner = THIS_MODULE;
617 strlcpy(adap->name, "Broadcom STB : ", sizeof(adap->name));
618 if (int_name)
619 strlcat(adap->name, int_name, sizeof(adap->name));
620 adap->algo = &brcmstb_i2c_algo;
621 adap->dev.parent = &pdev->dev;
622 adap->dev.of_node = pdev->dev.of_node;
623 rc = i2c_add_adapter(adap);
624 if (rc) {
625 dev_err(dev->device, "failed to add adapter\n");
626 goto probe_errorout;
627 }
628
629 dev_info(dev->device, "%s@%dhz registered in %s mode\n",
630 int_name ? int_name : " ", dev->clk_freq_hz,
631 (dev->irq >= 0) ? "interrupt" : "polling");
632
633 return 0;
634
635probe_errorout:
636 return rc;
637}
638
639static int brcmstb_i2c_remove(struct platform_device *pdev)
640{
641 struct brcmstb_i2c_dev *dev = platform_get_drvdata(pdev);
642
643 i2c_del_adapter(&dev->adapter);
644 return 0;
645}
646
647#ifdef CONFIG_PM_SLEEP
648static int brcmstb_i2c_suspend(struct device *dev)
649{
650 struct brcmstb_i2c_dev *i2c_dev = dev_get_drvdata(dev);
651
652 i2c_lock_adapter(&i2c_dev->adapter);
653 i2c_dev->is_suspended = true;
654 i2c_unlock_adapter(&i2c_dev->adapter);
655
656 return 0;
657}
658
659static int brcmstb_i2c_resume(struct device *dev)
660{
661 struct brcmstb_i2c_dev *i2c_dev = dev_get_drvdata(dev);
662
663 i2c_lock_adapter(&i2c_dev->adapter);
664 brcmstb_i2c_set_bsc_reg_defaults(i2c_dev);
665 i2c_dev->is_suspended = false;
666 i2c_unlock_adapter(&i2c_dev->adapter);
667
668 return 0;
669}
670#endif
671
672static SIMPLE_DEV_PM_OPS(brcmstb_i2c_pm, brcmstb_i2c_suspend,
673 brcmstb_i2c_resume);
674
675static const struct of_device_id brcmstb_i2c_of_match[] = {
676 {.compatible = "brcm,brcmstb-i2c"},
677 {},
678};
679MODULE_DEVICE_TABLE(of, brcmstb_i2c_of_match);
680
681static struct platform_driver brcmstb_i2c_driver = {
682 .driver = {
683 .name = "brcmstb-i2c",
684 .of_match_table = brcmstb_i2c_of_match,
685 .pm = &brcmstb_i2c_pm,
686 },
687 .probe = brcmstb_i2c_probe,
688 .remove = brcmstb_i2c_remove,
689};
690module_platform_driver(brcmstb_i2c_driver);
691
692MODULE_AUTHOR("Kamal Dasu <kdasu@broadcom.com>");
693MODULE_DESCRIPTION("Broadcom Settop I2C Driver");
694MODULE_LICENSE("GPL v2");
diff --git a/drivers/i2c/busses/i2c-davinci.c b/drivers/i2c/busses/i2c-davinci.c
index 4788a32afb86..3fbb9a035532 100644
--- a/drivers/i2c/busses/i2c-davinci.c
+++ b/drivers/i2c/busses/i2c-davinci.c
@@ -41,8 +41,8 @@
41 41
42#define DAVINCI_I2C_TIMEOUT (1*HZ) 42#define DAVINCI_I2C_TIMEOUT (1*HZ)
43#define DAVINCI_I2C_MAX_TRIES 2 43#define DAVINCI_I2C_MAX_TRIES 2
44#define I2C_DAVINCI_INTR_ALL (DAVINCI_I2C_IMR_AAS | \ 44#define DAVINCI_I2C_OWN_ADDRESS 0x08
45 DAVINCI_I2C_IMR_SCD | \ 45#define I2C_DAVINCI_INTR_ALL (DAVINCI_I2C_IMR_SCD | \
46 DAVINCI_I2C_IMR_ARDY | \ 46 DAVINCI_I2C_IMR_ARDY | \
47 DAVINCI_I2C_IMR_NACK | \ 47 DAVINCI_I2C_IMR_NACK | \
48 DAVINCI_I2C_IMR_AL) 48 DAVINCI_I2C_IMR_AL)
@@ -204,9 +204,30 @@ static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev)
204 psc++; /* better to run under spec than over */ 204 psc++; /* better to run under spec than over */
205 d = (psc >= 2) ? 5 : 7 - psc; 205 d = (psc >= 2) ? 5 : 7 - psc;
206 206
207 clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000)) - (d << 1); 207 clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000));
208 clkh = clk >> 1; 208 /* Avoid driving the bus too fast because of rounding errors above */
209 clkl = clk - clkh; 209 if (input_clock / (psc + 1) / clk > pdata->bus_freq * 1000)
210 clk++;
211 /*
212 * According to I2C-BUS Spec 2.1, in FAST-MODE LOW period should be at
213 * least 1.3uS, which is not the case with 50% duty cycle. Driving HIGH
214 * to LOW ratio as 1 to 2 is more safe.
215 */
216 if (pdata->bus_freq > 100)
217 clkl = (clk << 1) / 3;
218 else
219 clkl = (clk >> 1);
220 /*
221 * It's not always possible to have 1 to 2 ratio when d=7, so fall back
222 * to minimal possible clkh in this case.
223 */
224 if (clk >= clkl + d) {
225 clkh = clk - clkl - d;
226 clkl -= d;
227 } else {
228 clkh = 0;
229 clkl = clk - (d << 1);
230 }
210 231
211 davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc); 232 davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc);
212 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh); 233 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh);
@@ -233,7 +254,7 @@ static int i2c_davinci_init(struct davinci_i2c_dev *dev)
233 /* Respond at reserved "SMBus Host" slave address" (and zero); 254 /* Respond at reserved "SMBus Host" slave address" (and zero);
234 * we seem to have no option to not respond... 255 * we seem to have no option to not respond...
235 */ 256 */
236 davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, 0x08); 257 davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, DAVINCI_I2C_OWN_ADDRESS);
237 258
238 dev_dbg(dev->dev, "PSC = %d\n", 259 dev_dbg(dev->dev, "PSC = %d\n",
239 davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG)); 260 davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG));
@@ -350,29 +371,25 @@ static struct i2c_bus_recovery_info davinci_i2c_scl_recovery_info = {
350/* 371/*
351 * Waiting for bus not busy 372 * Waiting for bus not busy
352 */ 373 */
353static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev, 374static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev)
354 char allow_sleep)
355{ 375{
356 unsigned long timeout; 376 unsigned long timeout = jiffies + dev->adapter.timeout;
357 static u16 to_cnt; 377
358 378 do {
359 timeout = jiffies + dev->adapter.timeout; 379 if (!(davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) & DAVINCI_I2C_STR_BB))
360 while (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) 380 return 0;
361 & DAVINCI_I2C_STR_BB) { 381 schedule_timeout_uninterruptible(1);
362 if (to_cnt <= DAVINCI_I2C_MAX_TRIES) { 382 } while (time_before_eq(jiffies, timeout));
363 if (time_after(jiffies, timeout)) { 383
364 dev_warn(dev->dev, 384 dev_warn(dev->dev, "timeout waiting for bus ready\n");
365 "timeout waiting for bus ready\n"); 385 i2c_recover_bus(&dev->adapter);
366 to_cnt++; 386
367 return -ETIMEDOUT; 387 /*
368 } else { 388 * if bus is still "busy" here, it's most probably a HW problem like
369 to_cnt = 0; 389 * short-circuit
370 i2c_recover_bus(&dev->adapter); 390 */
371 } 391 if (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) & DAVINCI_I2C_STR_BB)
372 } 392 return -EIO;
373 if (allow_sleep)
374 schedule_timeout(1);
375 }
376 393
377 return 0; 394 return 0;
378} 395}
@@ -390,6 +407,11 @@ i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
390 u16 w; 407 u16 w;
391 unsigned long time_left; 408 unsigned long time_left;
392 409
410 if (msg->addr == DAVINCI_I2C_OWN_ADDRESS) {
411 dev_warn(dev->dev, "transfer to own address aborted\n");
412 return -EADDRNOTAVAIL;
413 }
414
393 /* Introduce a delay, required for some boards (e.g Davinci EVM) */ 415 /* Introduce a delay, required for some boards (e.g Davinci EVM) */
394 if (pdata->bus_delay) 416 if (pdata->bus_delay)
395 udelay(pdata->bus_delay); 417 udelay(pdata->bus_delay);
@@ -505,7 +527,7 @@ i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
505 527
506 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); 528 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
507 529
508 ret = i2c_davinci_wait_bus_not_busy(dev, 1); 530 ret = i2c_davinci_wait_bus_not_busy(dev);
509 if (ret < 0) { 531 if (ret < 0) {
510 dev_warn(dev->dev, "timeout waiting for bus ready\n"); 532 dev_warn(dev->dev, "timeout waiting for bus ready\n");
511 return ret; 533 return ret;
diff --git a/drivers/i2c/busses/i2c-designware-platdrv.c b/drivers/i2c/busses/i2c-designware-platdrv.c
index 0a80e4aabaed..3dd2de31a2f8 100644
--- a/drivers/i2c/busses/i2c-designware-platdrv.c
+++ b/drivers/i2c/busses/i2c-designware-platdrv.c
@@ -281,7 +281,8 @@ static int dw_i2c_remove(struct platform_device *pdev)
281 281
282 i2c_dw_disable(dev); 282 i2c_dw_disable(dev);
283 283
284 pm_runtime_put(&pdev->dev); 284 pm_runtime_dont_use_autosuspend(&pdev->dev);
285 pm_runtime_put_sync(&pdev->dev);
285 pm_runtime_disable(&pdev->dev); 286 pm_runtime_disable(&pdev->dev);
286 287
287 if (has_acpi_companion(&pdev->dev)) 288 if (has_acpi_companion(&pdev->dev))
@@ -298,6 +299,22 @@ static const struct of_device_id dw_i2c_of_match[] = {
298MODULE_DEVICE_TABLE(of, dw_i2c_of_match); 299MODULE_DEVICE_TABLE(of, dw_i2c_of_match);
299#endif 300#endif
300 301
302#ifdef CONFIG_PM_SLEEP
303static int dw_i2c_prepare(struct device *dev)
304{
305 return pm_runtime_suspended(dev);
306}
307
308static void dw_i2c_complete(struct device *dev)
309{
310 if (dev->power.direct_complete)
311 pm_request_resume(dev);
312}
313#else
314#define dw_i2c_prepare NULL
315#define dw_i2c_complete NULL
316#endif
317
301#ifdef CONFIG_PM 318#ifdef CONFIG_PM
302static int dw_i2c_suspend(struct device *dev) 319static int dw_i2c_suspend(struct device *dev)
303{ 320{
@@ -322,10 +339,18 @@ static int dw_i2c_resume(struct device *dev)
322 339
323 return 0; 340 return 0;
324} 341}
325#endif
326 342
327static UNIVERSAL_DEV_PM_OPS(dw_i2c_dev_pm_ops, dw_i2c_suspend, 343static const struct dev_pm_ops dw_i2c_dev_pm_ops = {
328 dw_i2c_resume, NULL); 344 .prepare = dw_i2c_prepare,
345 .complete = dw_i2c_complete,
346 SET_SYSTEM_SLEEP_PM_OPS(dw_i2c_suspend, dw_i2c_resume)
347 SET_RUNTIME_PM_OPS(dw_i2c_suspend, dw_i2c_resume, NULL)
348};
349
350#define DW_I2C_DEV_PMOPS (&dw_i2c_dev_pm_ops)
351#else
352#define DW_I2C_DEV_PMOPS NULL
353#endif
329 354
330/* work with hotplug and coldplug */ 355/* work with hotplug and coldplug */
331MODULE_ALIAS("platform:i2c_designware"); 356MODULE_ALIAS("platform:i2c_designware");
@@ -337,7 +362,7 @@ static struct platform_driver dw_i2c_driver = {
337 .name = "i2c_designware", 362 .name = "i2c_designware",
338 .of_match_table = of_match_ptr(dw_i2c_of_match), 363 .of_match_table = of_match_ptr(dw_i2c_of_match),
339 .acpi_match_table = ACPI_PTR(dw_i2c_acpi_match), 364 .acpi_match_table = ACPI_PTR(dw_i2c_acpi_match),
340 .pm = &dw_i2c_dev_pm_ops, 365 .pm = DW_I2C_DEV_PMOPS,
341 }, 366 },
342}; 367};
343 368
diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index a53a7dd66945..785aa674a4da 100644
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -241,7 +241,7 @@ static struct imx_i2c_hwdata vf610_i2c_hwdata = {
241 241
242}; 242};
243 243
244static struct platform_device_id imx_i2c_devtype[] = { 244static const struct platform_device_id imx_i2c_devtype[] = {
245 { 245 {
246 .name = "imx1-i2c", 246 .name = "imx1-i2c",
247 .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata, 247 .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata,
diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
new file mode 100644
index 000000000000..9920eef74672
--- /dev/null
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -0,0 +1,731 @@
1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Xudong Chen <xudong.chen@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/clk.h>
16#include <linux/completion.h>
17#include <linux/delay.h>
18#include <linux/device.h>
19#include <linux/dma-mapping.h>
20#include <linux/err.h>
21#include <linux/errno.h>
22#include <linux/i2c.h>
23#include <linux/init.h>
24#include <linux/interrupt.h>
25#include <linux/io.h>
26#include <linux/kernel.h>
27#include <linux/mm.h>
28#include <linux/module.h>
29#include <linux/of_address.h>
30#include <linux/of_irq.h>
31#include <linux/platform_device.h>
32#include <linux/scatterlist.h>
33#include <linux/sched.h>
34#include <linux/slab.h>
35
36#define I2C_RS_TRANSFER (1 << 4)
37#define I2C_HS_NACKERR (1 << 2)
38#define I2C_ACKERR (1 << 1)
39#define I2C_TRANSAC_COMP (1 << 0)
40#define I2C_TRANSAC_START (1 << 0)
41#define I2C_RS_MUL_CNFG (1 << 15)
42#define I2C_RS_MUL_TRIG (1 << 14)
43#define I2C_DCM_DISABLE 0x0000
44#define I2C_IO_CONFIG_OPEN_DRAIN 0x0003
45#define I2C_IO_CONFIG_PUSH_PULL 0x0000
46#define I2C_SOFT_RST 0x0001
47#define I2C_FIFO_ADDR_CLR 0x0001
48#define I2C_DELAY_LEN 0x0002
49#define I2C_ST_START_CON 0x8001
50#define I2C_FS_START_CON 0x1800
51#define I2C_TIME_CLR_VALUE 0x0000
52#define I2C_TIME_DEFAULT_VALUE 0x0003
53#define I2C_FS_TIME_INIT_VALUE 0x1303
54#define I2C_WRRD_TRANAC_VALUE 0x0002
55#define I2C_RD_TRANAC_VALUE 0x0001
56
57#define I2C_DMA_CON_TX 0x0000
58#define I2C_DMA_CON_RX 0x0001
59#define I2C_DMA_START_EN 0x0001
60#define I2C_DMA_INT_FLAG_NONE 0x0000
61#define I2C_DMA_CLR_FLAG 0x0000
62
63#define I2C_DEFAULT_SPEED 100000 /* hz */
64#define MAX_FS_MODE_SPEED 400000
65#define MAX_HS_MODE_SPEED 3400000
66#define MAX_SAMPLE_CNT_DIV 8
67#define MAX_STEP_CNT_DIV 64
68#define MAX_HS_STEP_CNT_DIV 8
69
70#define I2C_CONTROL_RS (0x1 << 1)
71#define I2C_CONTROL_DMA_EN (0x1 << 2)
72#define I2C_CONTROL_CLK_EXT_EN (0x1 << 3)
73#define I2C_CONTROL_DIR_CHANGE (0x1 << 4)
74#define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5)
75#define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6)
76#define I2C_CONTROL_WRAPPER (0x1 << 0)
77
78#define I2C_DRV_NAME "i2c-mt65xx"
79
80enum DMA_REGS_OFFSET {
81 OFFSET_INT_FLAG = 0x0,
82 OFFSET_INT_EN = 0x04,
83 OFFSET_EN = 0x08,
84 OFFSET_CON = 0x18,
85 OFFSET_TX_MEM_ADDR = 0x1c,
86 OFFSET_RX_MEM_ADDR = 0x20,
87 OFFSET_TX_LEN = 0x24,
88 OFFSET_RX_LEN = 0x28,
89};
90
91enum i2c_trans_st_rs {
92 I2C_TRANS_STOP = 0,
93 I2C_TRANS_REPEATED_START,
94};
95
96enum mtk_trans_op {
97 I2C_MASTER_WR = 1,
98 I2C_MASTER_RD,
99 I2C_MASTER_WRRD,
100};
101
102enum I2C_REGS_OFFSET {
103 OFFSET_DATA_PORT = 0x0,
104 OFFSET_SLAVE_ADDR = 0x04,
105 OFFSET_INTR_MASK = 0x08,
106 OFFSET_INTR_STAT = 0x0c,
107 OFFSET_CONTROL = 0x10,
108 OFFSET_TRANSFER_LEN = 0x14,
109 OFFSET_TRANSAC_LEN = 0x18,
110 OFFSET_DELAY_LEN = 0x1c,
111 OFFSET_TIMING = 0x20,
112 OFFSET_START = 0x24,
113 OFFSET_EXT_CONF = 0x28,
114 OFFSET_FIFO_STAT = 0x30,
115 OFFSET_FIFO_THRESH = 0x34,
116 OFFSET_FIFO_ADDR_CLR = 0x38,
117 OFFSET_IO_CONFIG = 0x40,
118 OFFSET_RSV_DEBUG = 0x44,
119 OFFSET_HS = 0x48,
120 OFFSET_SOFTRESET = 0x50,
121 OFFSET_DCM_EN = 0x54,
122 OFFSET_PATH_DIR = 0x60,
123 OFFSET_DEBUGSTAT = 0x64,
124 OFFSET_DEBUGCTRL = 0x68,
125 OFFSET_TRANSFER_LEN_AUX = 0x6c,
126};
127
128struct mtk_i2c_compatible {
129 const struct i2c_adapter_quirks *quirks;
130 unsigned char pmic_i2c: 1;
131 unsigned char dcm: 1;
132 unsigned char auto_restart: 1;
133};
134
135struct mtk_i2c {
136 struct i2c_adapter adap; /* i2c host adapter */
137 struct device *dev;
138 struct completion msg_complete;
139
140 /* set in i2c probe */
141 void __iomem *base; /* i2c base addr */
142 void __iomem *pdmabase; /* dma base address*/
143 struct clk *clk_main; /* main clock for i2c bus */
144 struct clk *clk_dma; /* DMA clock for i2c via DMA */
145 struct clk *clk_pmic; /* PMIC clock for i2c from PMIC */
146 bool have_pmic; /* can use i2c pins from PMIC */
147 bool use_push_pull; /* IO config push-pull mode */
148
149 u16 irq_stat; /* interrupt status */
150 unsigned int speed_hz; /* The speed in transfer */
151 enum mtk_trans_op op;
152 u16 timing_reg;
153 u16 high_speed_reg;
154 const struct mtk_i2c_compatible *dev_comp;
155};
156
157static const struct i2c_adapter_quirks mt6577_i2c_quirks = {
158 .flags = I2C_AQ_COMB_WRITE_THEN_READ,
159 .max_num_msgs = 1,
160 .max_write_len = 255,
161 .max_read_len = 255,
162 .max_comb_1st_msg_len = 255,
163 .max_comb_2nd_msg_len = 31,
164};
165
166static const struct i2c_adapter_quirks mt8173_i2c_quirks = {
167 .max_num_msgs = 65535,
168 .max_write_len = 65535,
169 .max_read_len = 65535,
170 .max_comb_1st_msg_len = 65535,
171 .max_comb_2nd_msg_len = 65535,
172};
173
174static const struct mtk_i2c_compatible mt6577_compat = {
175 .quirks = &mt6577_i2c_quirks,
176 .pmic_i2c = 0,
177 .dcm = 1,
178 .auto_restart = 0,
179};
180
181static const struct mtk_i2c_compatible mt6589_compat = {
182 .quirks = &mt6577_i2c_quirks,
183 .pmic_i2c = 1,
184 .dcm = 0,
185 .auto_restart = 0,
186};
187
188static const struct mtk_i2c_compatible mt8173_compat = {
189 .quirks = &mt8173_i2c_quirks,
190 .pmic_i2c = 0,
191 .dcm = 1,
192 .auto_restart = 1,
193};
194
195static const struct of_device_id mtk_i2c_of_match[] = {
196 { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
197 { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
198 { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
199 {}
200};
201MODULE_DEVICE_TABLE(of, mtk_i2c_of_match);
202
203static int mtk_i2c_clock_enable(struct mtk_i2c *i2c)
204{
205 int ret;
206
207 ret = clk_prepare_enable(i2c->clk_dma);
208 if (ret)
209 return ret;
210
211 ret = clk_prepare_enable(i2c->clk_main);
212 if (ret)
213 goto err_main;
214
215 if (i2c->have_pmic) {
216 ret = clk_prepare_enable(i2c->clk_pmic);
217 if (ret)
218 goto err_pmic;
219 }
220 return 0;
221
222err_pmic:
223 clk_disable_unprepare(i2c->clk_main);
224err_main:
225 clk_disable_unprepare(i2c->clk_dma);
226
227 return ret;
228}
229
230static void mtk_i2c_clock_disable(struct mtk_i2c *i2c)
231{
232 if (i2c->have_pmic)
233 clk_disable_unprepare(i2c->clk_pmic);
234
235 clk_disable_unprepare(i2c->clk_main);
236 clk_disable_unprepare(i2c->clk_dma);
237}
238
239static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
240{
241 u16 control_reg;
242
243 writew(I2C_SOFT_RST, i2c->base + OFFSET_SOFTRESET);
244
245 /* Set ioconfig */
246 if (i2c->use_push_pull)
247 writew(I2C_IO_CONFIG_PUSH_PULL, i2c->base + OFFSET_IO_CONFIG);
248 else
249 writew(I2C_IO_CONFIG_OPEN_DRAIN, i2c->base + OFFSET_IO_CONFIG);
250
251 if (i2c->dev_comp->dcm)
252 writew(I2C_DCM_DISABLE, i2c->base + OFFSET_DCM_EN);
253
254 writew(i2c->timing_reg, i2c->base + OFFSET_TIMING);
255 writew(i2c->high_speed_reg, i2c->base + OFFSET_HS);
256
257 /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */
258 if (i2c->have_pmic)
259 writew(I2C_CONTROL_WRAPPER, i2c->base + OFFSET_PATH_DIR);
260
261 control_reg = I2C_CONTROL_ACKERR_DET_EN |
262 I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN;
263 writew(control_reg, i2c->base + OFFSET_CONTROL);
264 writew(I2C_DELAY_LEN, i2c->base + OFFSET_DELAY_LEN);
265}
266
267/*
268 * Calculate i2c port speed
269 *
270 * Hardware design:
271 * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt)
272 * clock_div: fixed in hardware, but may be various in different SoCs
273 *
274 * The calculation want to pick the highest bus frequency that is still
275 * less than or equal to i2c->speed_hz. The calculation try to get
276 * sample_cnt and step_cn
277 */
278static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk,
279 unsigned int clock_div)
280{
281 unsigned int clk_src;
282 unsigned int step_cnt;
283 unsigned int sample_cnt;
284 unsigned int max_step_cnt;
285 unsigned int target_speed;
286 unsigned int base_sample_cnt = MAX_SAMPLE_CNT_DIV;
287 unsigned int base_step_cnt;
288 unsigned int opt_div;
289 unsigned int best_mul;
290 unsigned int cnt_mul;
291
292 clk_src = parent_clk / clock_div;
293 target_speed = i2c->speed_hz;
294
295 if (target_speed > MAX_HS_MODE_SPEED)
296 target_speed = MAX_HS_MODE_SPEED;
297
298 if (target_speed > MAX_FS_MODE_SPEED)
299 max_step_cnt = MAX_HS_STEP_CNT_DIV;
300 else
301 max_step_cnt = MAX_STEP_CNT_DIV;
302
303 base_step_cnt = max_step_cnt;
304 /* Find the best combination */
305 opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed);
306 best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt;
307
308 /* Search for the best pair (sample_cnt, step_cnt) with
309 * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV
310 * 0 < step_cnt < max_step_cnt
311 * sample_cnt * step_cnt >= opt_div
312 * optimizing for sample_cnt * step_cnt being minimal
313 */
314 for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) {
315 step_cnt = DIV_ROUND_UP(opt_div, sample_cnt);
316 cnt_mul = step_cnt * sample_cnt;
317 if (step_cnt > max_step_cnt)
318 continue;
319
320 if (cnt_mul < best_mul) {
321 best_mul = cnt_mul;
322 base_sample_cnt = sample_cnt;
323 base_step_cnt = step_cnt;
324 if (best_mul == opt_div)
325 break;
326 }
327 }
328
329 sample_cnt = base_sample_cnt;
330 step_cnt = base_step_cnt;
331
332 if ((clk_src / (2 * sample_cnt * step_cnt)) > target_speed) {
333 /* In this case, hardware can't support such
334 * low i2c_bus_freq
335 */
336 dev_dbg(i2c->dev, "Unsupported speed (%uhz)\n", target_speed);
337 return -EINVAL;
338 }
339
340 step_cnt--;
341 sample_cnt--;
342
343 if (target_speed > MAX_FS_MODE_SPEED) {
344 /* Set the high speed mode register */
345 i2c->timing_reg = I2C_FS_TIME_INIT_VALUE;
346 i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE |
347 (sample_cnt << 12) | (step_cnt << 8);
348 } else {
349 i2c->timing_reg = (sample_cnt << 8) | (step_cnt << 0);
350 /* Disable the high speed transaction */
351 i2c->high_speed_reg = I2C_TIME_CLR_VALUE;
352 }
353
354 return 0;
355}
356
357static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
358 int num, int left_num)
359{
360 u16 addr_reg;
361 u16 start_reg;
362 u16 control_reg;
363 u16 restart_flag = 0;
364 dma_addr_t rpaddr = 0;
365 dma_addr_t wpaddr = 0;
366 int ret;
367
368 i2c->irq_stat = 0;
369
370 if (i2c->dev_comp->auto_restart)
371 restart_flag = I2C_RS_TRANSFER;
372
373 reinit_completion(&i2c->msg_complete);
374
375 control_reg = readw(i2c->base + OFFSET_CONTROL) &
376 ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
377 if ((i2c->speed_hz > 400000) || (left_num >= 1))
378 control_reg |= I2C_CONTROL_RS;
379
380 if (i2c->op == I2C_MASTER_WRRD)
381 control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS;
382
383 writew(control_reg, i2c->base + OFFSET_CONTROL);
384
385 /* set start condition */
386 if (i2c->speed_hz <= 100000)
387 writew(I2C_ST_START_CON, i2c->base + OFFSET_EXT_CONF);
388 else
389 writew(I2C_FS_START_CON, i2c->base + OFFSET_EXT_CONF);
390
391 addr_reg = msgs->addr << 1;
392 if (i2c->op == I2C_MASTER_RD)
393 addr_reg |= 0x1;
394
395 writew(addr_reg, i2c->base + OFFSET_SLAVE_ADDR);
396
397 /* Clear interrupt status */
398 writew(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
399 I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_STAT);
400 writew(I2C_FIFO_ADDR_CLR, i2c->base + OFFSET_FIFO_ADDR_CLR);
401
402 /* Enable interrupt */
403 writew(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
404 I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_MASK);
405
406 /* Set transfer and transaction len */
407 if (i2c->op == I2C_MASTER_WRRD) {
408 writew(msgs->len | ((msgs + 1)->len) << 8,
409 i2c->base + OFFSET_TRANSFER_LEN);
410 writew(I2C_WRRD_TRANAC_VALUE, i2c->base + OFFSET_TRANSAC_LEN);
411 } else {
412 writew(msgs->len, i2c->base + OFFSET_TRANSFER_LEN);
413 writew(num, i2c->base + OFFSET_TRANSAC_LEN);
414 }
415
416 /* Prepare buffer data to start transfer */
417 if (i2c->op == I2C_MASTER_RD) {
418 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
419 writel(I2C_DMA_CON_RX, i2c->pdmabase + OFFSET_CON);
420 rpaddr = dma_map_single(i2c->dev, msgs->buf,
421 msgs->len, DMA_FROM_DEVICE);
422 if (dma_mapping_error(i2c->dev, rpaddr))
423 return -ENOMEM;
424 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
425 writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN);
426 } else if (i2c->op == I2C_MASTER_WR) {
427 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
428 writel(I2C_DMA_CON_TX, i2c->pdmabase + OFFSET_CON);
429 wpaddr = dma_map_single(i2c->dev, msgs->buf,
430 msgs->len, DMA_TO_DEVICE);
431 if (dma_mapping_error(i2c->dev, wpaddr))
432 return -ENOMEM;
433 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
434 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
435 } else {
436 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG);
437 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_CON);
438 wpaddr = dma_map_single(i2c->dev, msgs->buf,
439 msgs->len, DMA_TO_DEVICE);
440 if (dma_mapping_error(i2c->dev, wpaddr))
441 return -ENOMEM;
442 rpaddr = dma_map_single(i2c->dev, (msgs + 1)->buf,
443 (msgs + 1)->len,
444 DMA_FROM_DEVICE);
445 if (dma_mapping_error(i2c->dev, rpaddr)) {
446 dma_unmap_single(i2c->dev, wpaddr,
447 msgs->len, DMA_TO_DEVICE);
448 return -ENOMEM;
449 }
450 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
451 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
452 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
453 writel((msgs + 1)->len, i2c->pdmabase + OFFSET_RX_LEN);
454 }
455
456 writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN);
457
458 if (!i2c->dev_comp->auto_restart) {
459 start_reg = I2C_TRANSAC_START;
460 } else {
461 start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG;
462 if (left_num >= 1)
463 start_reg |= I2C_RS_MUL_CNFG;
464 }
465 writew(start_reg, i2c->base + OFFSET_START);
466
467 ret = wait_for_completion_timeout(&i2c->msg_complete,
468 i2c->adap.timeout);
469
470 /* Clear interrupt mask */
471 writew(~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
472 I2C_TRANSAC_COMP), i2c->base + OFFSET_INTR_MASK);
473
474 if (i2c->op == I2C_MASTER_WR) {
475 dma_unmap_single(i2c->dev, wpaddr,
476 msgs->len, DMA_TO_DEVICE);
477 } else if (i2c->op == I2C_MASTER_RD) {
478 dma_unmap_single(i2c->dev, rpaddr,
479 msgs->len, DMA_FROM_DEVICE);
480 } else {
481 dma_unmap_single(i2c->dev, wpaddr, msgs->len,
482 DMA_TO_DEVICE);
483 dma_unmap_single(i2c->dev, rpaddr, (msgs + 1)->len,
484 DMA_FROM_DEVICE);
485 }
486
487 if (ret == 0) {
488 dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr);
489 mtk_i2c_init_hw(i2c);
490 return -ETIMEDOUT;
491 }
492
493 completion_done(&i2c->msg_complete);
494
495 if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) {
496 dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr);
497 mtk_i2c_init_hw(i2c);
498 return -ENXIO;
499 }
500
501 return 0;
502}
503
504static int mtk_i2c_transfer(struct i2c_adapter *adap,
505 struct i2c_msg msgs[], int num)
506{
507 int ret;
508 int left_num = num;
509 struct mtk_i2c *i2c = i2c_get_adapdata(adap);
510
511 ret = mtk_i2c_clock_enable(i2c);
512 if (ret)
513 return ret;
514
515 while (left_num--) {
516 if (!msgs->buf) {
517 dev_dbg(i2c->dev, "data buffer is NULL.\n");
518 ret = -EINVAL;
519 goto err_exit;
520 }
521
522 if (msgs->flags & I2C_M_RD)
523 i2c->op = I2C_MASTER_RD;
524 else
525 i2c->op = I2C_MASTER_WR;
526
527 if (!i2c->dev_comp->auto_restart) {
528 if (num > 1) {
529 /* combined two messages into one transaction */
530 i2c->op = I2C_MASTER_WRRD;
531 left_num--;
532 }
533 }
534
535 /* always use DMA mode. */
536 ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num);
537 if (ret < 0)
538 goto err_exit;
539
540 msgs++;
541 }
542 /* the return value is number of executed messages */
543 ret = num;
544
545err_exit:
546 mtk_i2c_clock_disable(i2c);
547 return ret;
548}
549
550static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id)
551{
552 struct mtk_i2c *i2c = dev_id;
553 u16 restart_flag = 0;
554
555 if (i2c->dev_comp->auto_restart)
556 restart_flag = I2C_RS_TRANSFER;
557
558 i2c->irq_stat = readw(i2c->base + OFFSET_INTR_STAT);
559 writew(restart_flag | I2C_HS_NACKERR | I2C_ACKERR
560 | I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_STAT);
561
562 complete(&i2c->msg_complete);
563
564 return IRQ_HANDLED;
565}
566
567static u32 mtk_i2c_functionality(struct i2c_adapter *adap)
568{
569 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
570}
571
572static const struct i2c_algorithm mtk_i2c_algorithm = {
573 .master_xfer = mtk_i2c_transfer,
574 .functionality = mtk_i2c_functionality,
575};
576
577static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c,
578 unsigned int *clk_src_div)
579{
580 int ret;
581
582 ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz);
583 if (ret < 0)
584 i2c->speed_hz = I2C_DEFAULT_SPEED;
585
586 ret = of_property_read_u32(np, "clock-div", clk_src_div);
587 if (ret < 0)
588 return ret;
589
590 if (*clk_src_div == 0)
591 return -EINVAL;
592
593 i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic");
594 i2c->use_push_pull =
595 of_property_read_bool(np, "mediatek,use-push-pull");
596
597 return 0;
598}
599
600static int mtk_i2c_probe(struct platform_device *pdev)
601{
602 const struct of_device_id *of_id;
603 int ret = 0;
604 struct mtk_i2c *i2c;
605 struct clk *clk;
606 unsigned int clk_src_div;
607 struct resource *res;
608 int irq;
609
610 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
611 if (!i2c)
612 return -ENOMEM;
613
614 ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c, &clk_src_div);
615 if (ret)
616 return -EINVAL;
617
618 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
619 i2c->base = devm_ioremap_resource(&pdev->dev, res);
620 if (IS_ERR(i2c->base))
621 return PTR_ERR(i2c->base);
622
623 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
624 i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res);
625 if (IS_ERR(i2c->pdmabase))
626 return PTR_ERR(i2c->pdmabase);
627
628 irq = platform_get_irq(pdev, 0);
629 if (irq <= 0)
630 return irq;
631
632 init_completion(&i2c->msg_complete);
633
634 of_id = of_match_node(mtk_i2c_of_match, pdev->dev.of_node);
635 if (!of_id)
636 return -EINVAL;
637
638 i2c->dev_comp = of_id->data;
639 i2c->adap.dev.of_node = pdev->dev.of_node;
640 i2c->dev = &pdev->dev;
641 i2c->adap.dev.parent = &pdev->dev;
642 i2c->adap.owner = THIS_MODULE;
643 i2c->adap.algo = &mtk_i2c_algorithm;
644 i2c->adap.quirks = i2c->dev_comp->quirks;
645 i2c->adap.timeout = 2 * HZ;
646 i2c->adap.retries = 1;
647
648 if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c)
649 return -EINVAL;
650
651 i2c->clk_main = devm_clk_get(&pdev->dev, "main");
652 if (IS_ERR(i2c->clk_main)) {
653 dev_err(&pdev->dev, "cannot get main clock\n");
654 return PTR_ERR(i2c->clk_main);
655 }
656
657 i2c->clk_dma = devm_clk_get(&pdev->dev, "dma");
658 if (IS_ERR(i2c->clk_dma)) {
659 dev_err(&pdev->dev, "cannot get dma clock\n");
660 return PTR_ERR(i2c->clk_dma);
661 }
662
663 clk = i2c->clk_main;
664 if (i2c->have_pmic) {
665 i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic");
666 if (IS_ERR(i2c->clk_pmic)) {
667 dev_err(&pdev->dev, "cannot get pmic clock\n");
668 return PTR_ERR(i2c->clk_pmic);
669 }
670 clk = i2c->clk_pmic;
671 }
672
673 strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name));
674
675 ret = mtk_i2c_set_speed(i2c, clk_get_rate(clk), clk_src_div);
676 if (ret) {
677 dev_err(&pdev->dev, "Failed to set the speed.\n");
678 return -EINVAL;
679 }
680
681 ret = mtk_i2c_clock_enable(i2c);
682 if (ret) {
683 dev_err(&pdev->dev, "clock enable failed!\n");
684 return ret;
685 }
686 mtk_i2c_init_hw(i2c);
687 mtk_i2c_clock_disable(i2c);
688
689 ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq,
690 IRQF_TRIGGER_NONE, I2C_DRV_NAME, i2c);
691 if (ret < 0) {
692 dev_err(&pdev->dev,
693 "Request I2C IRQ %d fail\n", irq);
694 return ret;
695 }
696
697 i2c_set_adapdata(&i2c->adap, i2c);
698 ret = i2c_add_adapter(&i2c->adap);
699 if (ret) {
700 dev_err(&pdev->dev, "Failed to add i2c bus to i2c core\n");
701 return ret;
702 }
703
704 platform_set_drvdata(pdev, i2c);
705
706 return 0;
707}
708
709static int mtk_i2c_remove(struct platform_device *pdev)
710{
711 struct mtk_i2c *i2c = platform_get_drvdata(pdev);
712
713 i2c_del_adapter(&i2c->adap);
714
715 return 0;
716}
717
718static struct platform_driver mtk_i2c_driver = {
719 .probe = mtk_i2c_probe,
720 .remove = mtk_i2c_remove,
721 .driver = {
722 .name = I2C_DRV_NAME,
723 .of_match_table = of_match_ptr(mtk_i2c_of_match),
724 },
725};
726
727module_platform_driver(mtk_i2c_driver);
728
729MODULE_LICENSE("GPL v2");
730MODULE_DESCRIPTION("MediaTek I2C Bus Driver");
731MODULE_AUTHOR("Xudong Chen <xudong.chen@mediatek.com>");
diff --git a/drivers/i2c/busses/i2c-mxs.c b/drivers/i2c/busses/i2c-mxs.c
index 3e84f6c090a5..033846cdf266 100644
--- a/drivers/i2c/busses/i2c-mxs.c
+++ b/drivers/i2c/busses/i2c-mxs.c
@@ -784,7 +784,7 @@ static int mxs_i2c_get_ofdata(struct mxs_i2c_dev *i2c)
784 return 0; 784 return 0;
785} 785}
786 786
787static struct platform_device_id mxs_i2c_devtype[] = { 787static const struct platform_device_id mxs_i2c_devtype[] = {
788 { 788 {
789 .name = "imx23-i2c", 789 .name = "imx23-i2c",
790 .driver_data = MXS_I2C_V1, 790 .driver_data = MXS_I2C_V1,
diff --git a/drivers/i2c/busses/i2c-octeon.c b/drivers/i2c/busses/i2c-octeon.c
index 6e75e016bffc..32914ab42a19 100644
--- a/drivers/i2c/busses/i2c-octeon.c
+++ b/drivers/i2c/busses/i2c-octeon.c
@@ -200,7 +200,7 @@ static int octeon_i2c_test_iflg(struct octeon_i2c *i2c)
200 */ 200 */
201static int octeon_i2c_wait(struct octeon_i2c *i2c) 201static int octeon_i2c_wait(struct octeon_i2c *i2c)
202{ 202{
203 int result; 203 long result;
204 204
205 octeon_i2c_int_enable(i2c); 205 octeon_i2c_int_enable(i2c);
206 206
@@ -210,10 +210,7 @@ static int octeon_i2c_wait(struct octeon_i2c *i2c)
210 210
211 octeon_i2c_int_disable(i2c); 211 octeon_i2c_int_disable(i2c);
212 212
213 if (result < 0) { 213 if (result == 0) {
214 dev_dbg(i2c->dev, "%s: wait interrupted\n", __func__);
215 return result;
216 } else if (result == 0) {
217 dev_dbg(i2c->dev, "%s: timeout\n", __func__); 214 dev_dbg(i2c->dev, "%s: timeout\n", __func__);
218 return -ETIMEDOUT; 215 return -ETIMEDOUT;
219 } 216 }
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 0e894193accf..d1c22e3fdd14 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -38,6 +38,7 @@
38#include <linux/slab.h> 38#include <linux/slab.h>
39#include <linux/i2c-omap.h> 39#include <linux/i2c-omap.h>
40#include <linux/pm_runtime.h> 40#include <linux/pm_runtime.h>
41#include <linux/pinctrl/consumer.h>
41 42
42/* I2C controller revisions */ 43/* I2C controller revisions */
43#define OMAP_I2C_OMAP1_REV_2 0x20 44#define OMAP_I2C_OMAP1_REV_2 0x20
@@ -481,10 +482,8 @@ static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
481 482
482 timeout = jiffies + OMAP_I2C_TIMEOUT; 483 timeout = jiffies + OMAP_I2C_TIMEOUT;
483 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) { 484 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
484 if (time_after(jiffies, timeout)) { 485 if (time_after(jiffies, timeout))
485 dev_warn(dev->dev, "timeout waiting for bus ready\n"); 486 return i2c_recover_bus(&dev->adapter);
486 return -ETIMEDOUT;
487 }
488 msleep(1); 487 msleep(1);
489 } 488 }
490 489
@@ -1209,6 +1208,68 @@ MODULE_DEVICE_TABLE(of, omap_i2c_of_match);
1209#define OMAP_I2C_SCHEME_0 0 1208#define OMAP_I2C_SCHEME_0 0
1210#define OMAP_I2C_SCHEME_1 1 1209#define OMAP_I2C_SCHEME_1 1
1211 1210
1211static int omap_i2c_get_scl(struct i2c_adapter *adap)
1212{
1213 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1214 u32 reg;
1215
1216 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1217
1218 return reg & OMAP_I2C_SYSTEST_SCL_I_FUNC;
1219}
1220
1221static int omap_i2c_get_sda(struct i2c_adapter *adap)
1222{
1223 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1224 u32 reg;
1225
1226 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1227
1228 return reg & OMAP_I2C_SYSTEST_SDA_I_FUNC;
1229}
1230
1231static void omap_i2c_set_scl(struct i2c_adapter *adap, int val)
1232{
1233 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1234 u32 reg;
1235
1236 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1237 if (val)
1238 reg |= OMAP_I2C_SYSTEST_SCL_O;
1239 else
1240 reg &= ~OMAP_I2C_SYSTEST_SCL_O;
1241 omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg);
1242}
1243
1244static void omap_i2c_prepare_recovery(struct i2c_adapter *adap)
1245{
1246 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1247 u32 reg;
1248
1249 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1250 reg |= OMAP_I2C_SYSTEST_ST_EN;
1251 omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg);
1252}
1253
1254static void omap_i2c_unprepare_recovery(struct i2c_adapter *adap)
1255{
1256 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1257 u32 reg;
1258
1259 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1260 reg &= ~OMAP_I2C_SYSTEST_ST_EN;
1261 omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg);
1262}
1263
1264static struct i2c_bus_recovery_info omap_i2c_bus_recovery_info = {
1265 .get_scl = omap_i2c_get_scl,
1266 .get_sda = omap_i2c_get_sda,
1267 .set_scl = omap_i2c_set_scl,
1268 .prepare_recovery = omap_i2c_prepare_recovery,
1269 .unprepare_recovery = omap_i2c_unprepare_recovery,
1270 .recover_bus = i2c_generic_scl_recovery,
1271};
1272
1212static int 1273static int
1213omap_i2c_probe(struct platform_device *pdev) 1274omap_i2c_probe(struct platform_device *pdev)
1214{ 1275{
@@ -1358,6 +1419,7 @@ omap_i2c_probe(struct platform_device *pdev)
1358 adap->algo = &omap_i2c_algo; 1419 adap->algo = &omap_i2c_algo;
1359 adap->dev.parent = &pdev->dev; 1420 adap->dev.parent = &pdev->dev;
1360 adap->dev.of_node = pdev->dev.of_node; 1421 adap->dev.of_node = pdev->dev.of_node;
1422 adap->bus_recovery_info = &omap_i2c_bus_recovery_info;
1361 1423
1362 /* i2c device drivers may be active on return from add_adapter() */ 1424 /* i2c device drivers may be active on return from add_adapter() */
1363 adap->nr = pdev->id; 1425 adap->nr = pdev->id;
@@ -1423,6 +1485,8 @@ static int omap_i2c_runtime_suspend(struct device *dev)
1423 omap_i2c_read_reg(_dev, OMAP_I2C_STAT_REG); 1485 omap_i2c_read_reg(_dev, OMAP_I2C_STAT_REG);
1424 } 1486 }
1425 1487
1488 pinctrl_pm_select_sleep_state(dev);
1489
1426 return 0; 1490 return 0;
1427} 1491}
1428 1492
@@ -1431,6 +1495,8 @@ static int omap_i2c_runtime_resume(struct device *dev)
1431 struct platform_device *pdev = to_platform_device(dev); 1495 struct platform_device *pdev = to_platform_device(dev);
1432 struct omap_i2c_dev *_dev = platform_get_drvdata(pdev); 1496 struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
1433 1497
1498 pinctrl_pm_select_default_state(dev);
1499
1434 if (!_dev->regs) 1500 if (!_dev->regs)
1435 return 0; 1501 return 0;
1436 1502
diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c
index 5a84bea5b845..d8361dada584 100644
--- a/drivers/i2c/busses/i2c-rcar.c
+++ b/drivers/i2c/busses/i2c-rcar.c
@@ -490,7 +490,8 @@ static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
490 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); 490 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
491 struct device *dev = rcar_i2c_priv_to_dev(priv); 491 struct device *dev = rcar_i2c_priv_to_dev(priv);
492 unsigned long flags; 492 unsigned long flags;
493 int i, ret, timeout; 493 int i, ret;
494 long timeout;
494 495
495 pm_runtime_get_sync(dev); 496 pm_runtime_get_sync(dev);
496 497
@@ -532,7 +533,7 @@ static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
532 533
533 timeout = wait_event_timeout(priv->wait, 534 timeout = wait_event_timeout(priv->wait,
534 rcar_i2c_flags_has(priv, ID_DONE), 535 rcar_i2c_flags_has(priv, ID_DONE),
535 5 * HZ); 536 adap->timeout);
536 if (!timeout) { 537 if (!timeout) {
537 ret = -ETIMEDOUT; 538 ret = -ETIMEDOUT;
538 break; 539 break;
@@ -604,7 +605,8 @@ static int rcar_unreg_slave(struct i2c_client *slave)
604static u32 rcar_i2c_func(struct i2c_adapter *adap) 605static u32 rcar_i2c_func(struct i2c_adapter *adap)
605{ 606{
606 /* This HW can't do SMBUS_QUICK and NOSTART */ 607 /* This HW can't do SMBUS_QUICK and NOSTART */
607 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 608 return I2C_FUNC_I2C | I2C_FUNC_SLAVE |
609 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
608} 610}
609 611
610static const struct i2c_algorithm rcar_i2c_algo = { 612static const struct i2c_algorithm rcar_i2c_algo = {
@@ -713,7 +715,7 @@ static int rcar_i2c_remove(struct platform_device *pdev)
713 return 0; 715 return 0;
714} 716}
715 717
716static struct platform_device_id rcar_i2c_id_table[] = { 718static const struct platform_device_id rcar_i2c_id_table[] = {
717 { "i2c-rcar", I2C_RCAR_GEN1 }, 719 { "i2c-rcar", I2C_RCAR_GEN1 },
718 { "i2c-rcar_gen1", I2C_RCAR_GEN1 }, 720 { "i2c-rcar_gen1", I2C_RCAR_GEN1 },
719 { "i2c-rcar_gen2", I2C_RCAR_GEN2 }, 721 { "i2c-rcar_gen2", I2C_RCAR_GEN2 },
diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c
index 019d5426fe52..72e97e306bd9 100644
--- a/drivers/i2c/busses/i2c-rk3x.c
+++ b/drivers/i2c/busses/i2c-rk3x.c
@@ -72,7 +72,7 @@ enum {
72#define REG_INT_ALL 0x7f 72#define REG_INT_ALL 0x7f
73 73
74/* Constants */ 74/* Constants */
75#define WAIT_TIMEOUT 200 /* ms */ 75#define WAIT_TIMEOUT 1000 /* ms */
76#define DEFAULT_SCL_RATE (100 * 1000) /* Hz */ 76#define DEFAULT_SCL_RATE (100 * 1000) /* Hz */
77 77
78enum rk3x_i2c_state { 78enum rk3x_i2c_state {
diff --git a/drivers/i2c/busses/i2c-s3c2410.c b/drivers/i2c/busses/i2c-s3c2410.c
index 297e9c9ac943..50bfd8cef5f2 100644
--- a/drivers/i2c/busses/i2c-s3c2410.c
+++ b/drivers/i2c/busses/i2c-s3c2410.c
@@ -132,7 +132,7 @@ struct s3c24xx_i2c {
132 unsigned int sys_i2c_cfg; 132 unsigned int sys_i2c_cfg;
133}; 133};
134 134
135static struct platform_device_id s3c24xx_driver_ids[] = { 135static const struct platform_device_id s3c24xx_driver_ids[] = {
136 { 136 {
137 .name = "s3c2410-i2c", 137 .name = "s3c2410-i2c",
138 .driver_data = 0, 138 .driver_data = 0,
diff --git a/drivers/i2c/busses/i2c-sh_mobile.c b/drivers/i2c/busses/i2c-sh_mobile.c
index 007818b3e174..47659a925e09 100644
--- a/drivers/i2c/busses/i2c-sh_mobile.c
+++ b/drivers/i2c/busses/i2c-sh_mobile.c
@@ -150,6 +150,7 @@ struct sh_mobile_i2c_data {
150 150
151struct sh_mobile_dt_config { 151struct sh_mobile_dt_config {
152 int clks_per_count; 152 int clks_per_count;
153 void (*setup)(struct sh_mobile_i2c_data *pd);
153}; 154};
154 155
155#define IIC_FLAG_HAS_ICIC67 (1 << 0) 156#define IIC_FLAG_HAS_ICIC67 (1 << 0)
@@ -164,6 +165,7 @@ struct sh_mobile_dt_config {
164#define ICIC 0x0c 165#define ICIC 0x0c
165#define ICCL 0x10 166#define ICCL 0x10
166#define ICCH 0x14 167#define ICCH 0x14
168#define ICSTART 0x70
167 169
168/* Register bits */ 170/* Register bits */
169#define ICCR_ICE 0x80 171#define ICCR_ICE 0x80
@@ -190,6 +192,8 @@ struct sh_mobile_dt_config {
190#define ICIC_WAITE 0x02 192#define ICIC_WAITE 0x02
191#define ICIC_DTEE 0x01 193#define ICIC_DTEE 0x01
192 194
195#define ICSTART_ICSTART 0x10
196
193static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data) 197static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data)
194{ 198{
195 if (offs == ICIC) 199 if (offs == ICIC)
@@ -726,7 +730,8 @@ static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
726 struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter); 730 struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter);
727 struct i2c_msg *msg; 731 struct i2c_msg *msg;
728 int err = 0; 732 int err = 0;
729 int i, k; 733 int i;
734 long timeout;
730 735
731 activate_ch(pd); 736 activate_ch(pd);
732 737
@@ -745,10 +750,10 @@ static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
745 i2c_op(pd, OP_START, 0); 750 i2c_op(pd, OP_START, 0);
746 751
747 /* The interrupt handler takes care of the rest... */ 752 /* The interrupt handler takes care of the rest... */
748 k = wait_event_timeout(pd->wait, 753 timeout = wait_event_timeout(pd->wait,
749 pd->sr & (ICSR_TACK | SW_DONE), 754 pd->sr & (ICSR_TACK | SW_DONE),
750 5 * HZ); 755 adapter->timeout);
751 if (!k) { 756 if (!timeout) {
752 dev_err(pd->dev, "Transfer request timed out\n"); 757 dev_err(pd->dev, "Transfer request timed out\n");
753 if (pd->dma_direction != DMA_NONE) 758 if (pd->dma_direction != DMA_NONE)
754 sh_mobile_i2c_cleanup_dma(pd); 759 sh_mobile_i2c_cleanup_dma(pd);
@@ -782,6 +787,33 @@ static struct i2c_algorithm sh_mobile_i2c_algorithm = {
782 .master_xfer = sh_mobile_i2c_xfer, 787 .master_xfer = sh_mobile_i2c_xfer,
783}; 788};
784 789
790/*
791 * r8a7740 chip has lasting errata on I2C I/O pad reset.
792 * this is work-around for it.
793 */
794static void sh_mobile_i2c_r8a7740_workaround(struct sh_mobile_i2c_data *pd)
795{
796 iic_set_clr(pd, ICCR, ICCR_ICE, 0);
797 iic_rd(pd, ICCR); /* dummy read */
798
799 iic_set_clr(pd, ICSTART, ICSTART_ICSTART, 0);
800 iic_rd(pd, ICSTART); /* dummy read */
801
802 udelay(10);
803
804 iic_wr(pd, ICCR, ICCR_SCP);
805 iic_wr(pd, ICSTART, 0);
806
807 udelay(10);
808
809 iic_wr(pd, ICCR, ICCR_TRS);
810 udelay(10);
811 iic_wr(pd, ICCR, 0);
812 udelay(10);
813 iic_wr(pd, ICCR, ICCR_TRS);
814 udelay(10);
815}
816
785static const struct sh_mobile_dt_config default_dt_config = { 817static const struct sh_mobile_dt_config default_dt_config = {
786 .clks_per_count = 1, 818 .clks_per_count = 1,
787}; 819};
@@ -790,9 +822,15 @@ static const struct sh_mobile_dt_config fast_clock_dt_config = {
790 .clks_per_count = 2, 822 .clks_per_count = 2,
791}; 823};
792 824
825static const struct sh_mobile_dt_config r8a7740_dt_config = {
826 .clks_per_count = 1,
827 .setup = sh_mobile_i2c_r8a7740_workaround,
828};
829
793static const struct of_device_id sh_mobile_i2c_dt_ids[] = { 830static const struct of_device_id sh_mobile_i2c_dt_ids[] = {
794 { .compatible = "renesas,rmobile-iic", .data = &default_dt_config }, 831 { .compatible = "renesas,rmobile-iic", .data = &default_dt_config },
795 { .compatible = "renesas,iic-r8a73a4", .data = &fast_clock_dt_config }, 832 { .compatible = "renesas,iic-r8a73a4", .data = &fast_clock_dt_config },
833 { .compatible = "renesas,iic-r8a7740", .data = &r8a7740_dt_config },
796 { .compatible = "renesas,iic-r8a7790", .data = &fast_clock_dt_config }, 834 { .compatible = "renesas,iic-r8a7790", .data = &fast_clock_dt_config },
797 { .compatible = "renesas,iic-r8a7791", .data = &fast_clock_dt_config }, 835 { .compatible = "renesas,iic-r8a7791", .data = &fast_clock_dt_config },
798 { .compatible = "renesas,iic-r8a7792", .data = &fast_clock_dt_config }, 836 { .compatible = "renesas,iic-r8a7792", .data = &fast_clock_dt_config },
@@ -885,6 +923,9 @@ static int sh_mobile_i2c_probe(struct platform_device *dev)
885 923
886 config = match->data; 924 config = match->data;
887 pd->clks_per_count = config->clks_per_count; 925 pd->clks_per_count = config->clks_per_count;
926
927 if (config->setup)
928 config->setup(pd);
888 } 929 }
889 } else { 930 } else {
890 if (pdata && pdata->bus_speed) 931 if (pdata && pdata->bus_speed)
diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index 1bcd75ea0b4c..78a366814696 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -656,8 +656,8 @@ static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
656static u32 tegra_i2c_func(struct i2c_adapter *adap) 656static u32 tegra_i2c_func(struct i2c_adapter *adap)
657{ 657{
658 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 658 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
659 u32 ret = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR | 659 u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
660 I2C_FUNC_PROTOCOL_MANGLING; 660 I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING;
661 661
662 if (i2c_dev->hw->has_continue_xfer_support) 662 if (i2c_dev->hw->has_continue_xfer_support)
663 ret |= I2C_FUNC_NOSTART; 663 ret |= I2C_FUNC_NOSTART;
@@ -669,6 +669,12 @@ static const struct i2c_algorithm tegra_i2c_algo = {
669 .functionality = tegra_i2c_func, 669 .functionality = tegra_i2c_func,
670}; 670};
671 671
672/* payload size is only 12 bit */
673static struct i2c_adapter_quirks tegra_i2c_quirks = {
674 .max_read_len = 4096,
675 .max_write_len = 4096,
676};
677
672static const struct tegra_i2c_hw_feature tegra20_i2c_hw = { 678static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
673 .has_continue_xfer_support = false, 679 .has_continue_xfer_support = false,
674 .has_per_pkt_xfer_complete_irq = false, 680 .has_per_pkt_xfer_complete_irq = false,
@@ -739,6 +745,7 @@ static int tegra_i2c_probe(struct platform_device *pdev)
739 i2c_dev->base = base; 745 i2c_dev->base = base;
740 i2c_dev->div_clk = div_clk; 746 i2c_dev->div_clk = div_clk;
741 i2c_dev->adapter.algo = &tegra_i2c_algo; 747 i2c_dev->adapter.algo = &tegra_i2c_algo;
748 i2c_dev->adapter.quirks = &tegra_i2c_quirks;
742 i2c_dev->irq = irq; 749 i2c_dev->irq = irq;
743 i2c_dev->cont_id = pdev->id; 750 i2c_dev->cont_id = pdev->id;
744 i2c_dev->dev = &pdev->dev; 751 i2c_dev->dev = &pdev->dev;
diff --git a/drivers/i2c/busses/i2c-xgene-slimpro.c b/drivers/i2c/busses/i2c-xgene-slimpro.c
new file mode 100644
index 000000000000..dcca7076231e
--- /dev/null
+++ b/drivers/i2c/busses/i2c-xgene-slimpro.c
@@ -0,0 +1,469 @@
1/*
2 * X-Gene SLIMpro I2C Driver
3 *
4 * Copyright (c) 2014, Applied Micro Circuits Corporation
5 * Author: Feng Kan <fkan@apm.com>
6 * Author: Hieu Le <hnle@apm.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, see <http://www.gnu.org/licenses/>.
20 *
21 * This driver provides support for X-Gene SLIMpro I2C device access
22 * using the APM X-Gene SLIMpro mailbox driver.
23 *
24 */
25#include <linux/acpi.h>
26#include <linux/dma-mapping.h>
27#include <linux/i2c.h>
28#include <linux/interrupt.h>
29#include <linux/mailbox_client.h>
30#include <linux/module.h>
31#include <linux/of.h>
32#include <linux/platform_device.h>
33#include <linux/version.h>
34
35#define MAILBOX_OP_TIMEOUT 1000 /* Operation time out in ms */
36#define MAILBOX_I2C_INDEX 0
37#define SLIMPRO_IIC_BUS 1 /* Use I2C bus 1 only */
38
39#define SMBUS_CMD_LEN 1
40#define BYTE_DATA 1
41#define WORD_DATA 2
42#define BLOCK_DATA 3
43
44#define SLIMPRO_IIC_I2C_PROTOCOL 0
45#define SLIMPRO_IIC_SMB_PROTOCOL 1
46
47#define SLIMPRO_IIC_READ 0
48#define SLIMPRO_IIC_WRITE 1
49
50#define IIC_SMB_WITHOUT_DATA_LEN 0
51#define IIC_SMB_WITH_DATA_LEN 1
52
53#define SLIMPRO_DEBUG_MSG 0
54#define SLIMPRO_MSG_TYPE_SHIFT 28
55#define SLIMPRO_DBG_SUBTYPE_I2C1READ 4
56#define SLIMPRO_DBGMSG_TYPE_SHIFT 24
57#define SLIMPRO_DBGMSG_TYPE_MASK 0x0F000000U
58#define SLIMPRO_IIC_DEV_SHIFT 23
59#define SLIMPRO_IIC_DEV_MASK 0x00800000U
60#define SLIMPRO_IIC_DEVID_SHIFT 13
61#define SLIMPRO_IIC_DEVID_MASK 0x007FE000U
62#define SLIMPRO_IIC_RW_SHIFT 12
63#define SLIMPRO_IIC_RW_MASK 0x00001000U
64#define SLIMPRO_IIC_PROTO_SHIFT 11
65#define SLIMPRO_IIC_PROTO_MASK 0x00000800U
66#define SLIMPRO_IIC_ADDRLEN_SHIFT 8
67#define SLIMPRO_IIC_ADDRLEN_MASK 0x00000700U
68#define SLIMPRO_IIC_DATALEN_SHIFT 0
69#define SLIMPRO_IIC_DATALEN_MASK 0x000000FFU
70
71/*
72 * SLIMpro I2C message encode
73 *
74 * dev - Controller number (0-based)
75 * chip - I2C chip address
76 * op - SLIMPRO_IIC_READ or SLIMPRO_IIC_WRITE
77 * proto - SLIMPRO_IIC_SMB_PROTOCOL or SLIMPRO_IIC_I2C_PROTOCOL
78 * addrlen - Length of the address field
79 * datalen - Length of the data field
80 */
81#define SLIMPRO_IIC_ENCODE_MSG(dev, chip, op, proto, addrlen, datalen) \
82 ((SLIMPRO_DEBUG_MSG << SLIMPRO_MSG_TYPE_SHIFT) | \
83 ((SLIMPRO_DBG_SUBTYPE_I2C1READ << SLIMPRO_DBGMSG_TYPE_SHIFT) & \
84 SLIMPRO_DBGMSG_TYPE_MASK) | \
85 ((dev << SLIMPRO_IIC_DEV_SHIFT) & SLIMPRO_IIC_DEV_MASK) | \
86 ((chip << SLIMPRO_IIC_DEVID_SHIFT) & SLIMPRO_IIC_DEVID_MASK) | \
87 ((op << SLIMPRO_IIC_RW_SHIFT) & SLIMPRO_IIC_RW_MASK) | \
88 ((proto << SLIMPRO_IIC_PROTO_SHIFT) & SLIMPRO_IIC_PROTO_MASK) | \
89 ((addrlen << SLIMPRO_IIC_ADDRLEN_SHIFT) & SLIMPRO_IIC_ADDRLEN_MASK) | \
90 ((datalen << SLIMPRO_IIC_DATALEN_SHIFT) & SLIMPRO_IIC_DATALEN_MASK))
91
92/*
93 * Encode for upper address for block data
94 */
95#define SLIMPRO_IIC_ENCODE_FLAG_BUFADDR 0x80000000
96#define SLIMPRO_IIC_ENCODE_FLAG_WITH_DATA_LEN(a) ((u32) (((a) << 30) \
97 & 0x40000000))
98#define SLIMPRO_IIC_ENCODE_UPPER_BUFADDR(a) ((u32) (((a) >> 12) \
99 & 0x3FF00000))
100#define SLIMPRO_IIC_ENCODE_ADDR(a) ((a) & 0x000FFFFF)
101
102struct slimpro_i2c_dev {
103 struct i2c_adapter adapter;
104 struct device *dev;
105 struct mbox_chan *mbox_chan;
106 struct mbox_client mbox_client;
107 struct completion rd_complete;
108 u8 dma_buffer[I2C_SMBUS_BLOCK_MAX];
109 u32 *resp_msg;
110};
111
112#define to_slimpro_i2c_dev(cl) \
113 container_of(cl, struct slimpro_i2c_dev, mbox_client)
114
115static void slimpro_i2c_rx_cb(struct mbox_client *cl, void *mssg)
116{
117 struct slimpro_i2c_dev *ctx = to_slimpro_i2c_dev(cl);
118
119 /*
120 * Response message format:
121 * mssg[0] is the return code of the operation
122 * mssg[1] is the first data word
123 * mssg[2] is NOT used
124 */
125 if (ctx->resp_msg)
126 *ctx->resp_msg = ((u32 *)mssg)[1];
127
128 if (ctx->mbox_client.tx_block)
129 complete(&ctx->rd_complete);
130}
131
132static int start_i2c_msg_xfer(struct slimpro_i2c_dev *ctx)
133{
134 if (ctx->mbox_client.tx_block) {
135 if (!wait_for_completion_timeout(&ctx->rd_complete,
136 msecs_to_jiffies(MAILBOX_OP_TIMEOUT)))
137 return -ETIMEDOUT;
138 }
139
140 /* Check of invalid data or no device */
141 if (*ctx->resp_msg == 0xffffffff)
142 return -ENODEV;
143
144 return 0;
145}
146
147static int slimpro_i2c_rd(struct slimpro_i2c_dev *ctx, u32 chip,
148 u32 addr, u32 addrlen, u32 protocol,
149 u32 readlen, u32 *data)
150{
151 u32 msg[3];
152 int rc;
153
154 msg[0] = SLIMPRO_IIC_ENCODE_MSG(SLIMPRO_IIC_BUS, chip,
155 SLIMPRO_IIC_READ, protocol, addrlen, readlen);
156 msg[1] = SLIMPRO_IIC_ENCODE_ADDR(addr);
157 msg[2] = 0;
158 ctx->resp_msg = data;
159 rc = mbox_send_message(ctx->mbox_chan, &msg);
160 if (rc < 0)
161 goto err;
162
163 rc = start_i2c_msg_xfer(ctx);
164err:
165 ctx->resp_msg = NULL;
166 return rc;
167}
168
169static int slimpro_i2c_wr(struct slimpro_i2c_dev *ctx, u32 chip,
170 u32 addr, u32 addrlen, u32 protocol, u32 writelen,
171 u32 data)
172{
173 u32 msg[3];
174 int rc;
175
176 msg[0] = SLIMPRO_IIC_ENCODE_MSG(SLIMPRO_IIC_BUS, chip,
177 SLIMPRO_IIC_WRITE, protocol, addrlen, writelen);
178 msg[1] = SLIMPRO_IIC_ENCODE_ADDR(addr);
179 msg[2] = data;
180 ctx->resp_msg = msg;
181
182 rc = mbox_send_message(ctx->mbox_chan, &msg);
183 if (rc < 0)
184 goto err;
185
186 rc = start_i2c_msg_xfer(ctx);
187err:
188 ctx->resp_msg = NULL;
189 return rc;
190}
191
192static int slimpro_i2c_blkrd(struct slimpro_i2c_dev *ctx, u32 chip, u32 addr,
193 u32 addrlen, u32 protocol, u32 readlen,
194 u32 with_data_len, void *data)
195{
196 dma_addr_t paddr;
197 u32 msg[3];
198 int rc;
199
200 paddr = dma_map_single(ctx->dev, ctx->dma_buffer, readlen, DMA_FROM_DEVICE);
201 rc = dma_mapping_error(ctx->dev, paddr);
202 if (rc) {
203 dev_err(&ctx->adapter.dev, "Error in mapping dma buffer %p\n",
204 ctx->dma_buffer);
205 goto err;
206 }
207
208 msg[0] = SLIMPRO_IIC_ENCODE_MSG(SLIMPRO_IIC_BUS, chip, SLIMPRO_IIC_READ,
209 protocol, addrlen, readlen);
210 msg[1] = SLIMPRO_IIC_ENCODE_FLAG_BUFADDR |
211 SLIMPRO_IIC_ENCODE_FLAG_WITH_DATA_LEN(with_data_len) |
212 SLIMPRO_IIC_ENCODE_UPPER_BUFADDR(paddr) |
213 SLIMPRO_IIC_ENCODE_ADDR(addr);
214 msg[2] = (u32)paddr;
215 ctx->resp_msg = msg;
216
217 rc = mbox_send_message(ctx->mbox_chan, &msg);
218 if (rc < 0)
219 goto err_unmap;
220
221 rc = start_i2c_msg_xfer(ctx);
222
223 /* Copy to destination */
224 memcpy(data, ctx->dma_buffer, readlen);
225
226err_unmap:
227 dma_unmap_single(ctx->dev, paddr, readlen, DMA_FROM_DEVICE);
228err:
229 ctx->resp_msg = NULL;
230 return rc;
231}
232
233static int slimpro_i2c_blkwr(struct slimpro_i2c_dev *ctx, u32 chip,
234 u32 addr, u32 addrlen, u32 protocol, u32 writelen,
235 void *data)
236{
237 dma_addr_t paddr;
238 u32 msg[3];
239 int rc;
240
241 memcpy(ctx->dma_buffer, data, writelen);
242 paddr = dma_map_single(ctx->dev, ctx->dma_buffer, writelen,
243 DMA_TO_DEVICE);
244 rc = dma_mapping_error(ctx->dev, paddr);
245 if (rc) {
246 dev_err(&ctx->adapter.dev, "Error in mapping dma buffer %p\n",
247 ctx->dma_buffer);
248 goto err;
249 }
250
251 msg[0] = SLIMPRO_IIC_ENCODE_MSG(SLIMPRO_IIC_BUS, chip, SLIMPRO_IIC_WRITE,
252 protocol, addrlen, writelen);
253 msg[1] = SLIMPRO_IIC_ENCODE_FLAG_BUFADDR |
254 SLIMPRO_IIC_ENCODE_UPPER_BUFADDR(paddr) |
255 SLIMPRO_IIC_ENCODE_ADDR(addr);
256 msg[2] = (u32)paddr;
257 ctx->resp_msg = msg;
258
259 if (ctx->mbox_client.tx_block)
260 reinit_completion(&ctx->rd_complete);
261
262 rc = mbox_send_message(ctx->mbox_chan, &msg);
263 if (rc < 0)
264 goto err_unmap;
265
266 rc = start_i2c_msg_xfer(ctx);
267
268err_unmap:
269 dma_unmap_single(ctx->dev, paddr, writelen, DMA_TO_DEVICE);
270err:
271 ctx->resp_msg = NULL;
272 return rc;
273}
274
275static int xgene_slimpro_i2c_xfer(struct i2c_adapter *adap, u16 addr,
276 unsigned short flags, char read_write,
277 u8 command, int size,
278 union i2c_smbus_data *data)
279{
280 struct slimpro_i2c_dev *ctx = i2c_get_adapdata(adap);
281 int ret = -EOPNOTSUPP;
282 u32 val;
283
284 switch (size) {
285 case I2C_SMBUS_BYTE:
286 if (read_write == I2C_SMBUS_READ) {
287 ret = slimpro_i2c_rd(ctx, addr, 0, 0,
288 SLIMPRO_IIC_SMB_PROTOCOL,
289 BYTE_DATA, &val);
290 data->byte = val;
291 } else {
292 ret = slimpro_i2c_wr(ctx, addr, command, SMBUS_CMD_LEN,
293 SLIMPRO_IIC_SMB_PROTOCOL,
294 0, 0);
295 }
296 break;
297 case I2C_SMBUS_BYTE_DATA:
298 if (read_write == I2C_SMBUS_READ) {
299 ret = slimpro_i2c_rd(ctx, addr, command, SMBUS_CMD_LEN,
300 SLIMPRO_IIC_SMB_PROTOCOL,
301 BYTE_DATA, &val);
302 data->byte = val;
303 } else {
304 val = data->byte;
305 ret = slimpro_i2c_wr(ctx, addr, command, SMBUS_CMD_LEN,
306 SLIMPRO_IIC_SMB_PROTOCOL,
307 BYTE_DATA, val);
308 }
309 break;
310 case I2C_SMBUS_WORD_DATA:
311 if (read_write == I2C_SMBUS_READ) {
312 ret = slimpro_i2c_rd(ctx, addr, command, SMBUS_CMD_LEN,
313 SLIMPRO_IIC_SMB_PROTOCOL,
314 WORD_DATA, &val);
315 data->word = val;
316 } else {
317 val = data->word;
318 ret = slimpro_i2c_wr(ctx, addr, command, SMBUS_CMD_LEN,
319 SLIMPRO_IIC_SMB_PROTOCOL,
320 WORD_DATA, val);
321 }
322 break;
323 case I2C_SMBUS_BLOCK_DATA:
324 if (read_write == I2C_SMBUS_READ) {
325 ret = slimpro_i2c_blkrd(ctx, addr, command,
326 SMBUS_CMD_LEN,
327 SLIMPRO_IIC_SMB_PROTOCOL,
328 I2C_SMBUS_BLOCK_MAX + 1,
329 IIC_SMB_WITH_DATA_LEN,
330 &data->block[0]);
331
332 } else {
333 ret = slimpro_i2c_blkwr(ctx, addr, command,
334 SMBUS_CMD_LEN,
335 SLIMPRO_IIC_SMB_PROTOCOL,
336 data->block[0] + 1,
337 &data->block[0]);
338 }
339 break;
340 case I2C_SMBUS_I2C_BLOCK_DATA:
341 if (read_write == I2C_SMBUS_READ) {
342 ret = slimpro_i2c_blkrd(ctx, addr,
343 command,
344 SMBUS_CMD_LEN,
345 SLIMPRO_IIC_I2C_PROTOCOL,
346 I2C_SMBUS_BLOCK_MAX,
347 IIC_SMB_WITHOUT_DATA_LEN,
348 &data->block[1]);
349 } else {
350 ret = slimpro_i2c_blkwr(ctx, addr, command,
351 SMBUS_CMD_LEN,
352 SLIMPRO_IIC_I2C_PROTOCOL,
353 data->block[0],
354 &data->block[1]);
355 }
356 break;
357 default:
358 break;
359 }
360 return ret;
361}
362
363/*
364* Return list of supported functionality.
365*/
366static u32 xgene_slimpro_i2c_func(struct i2c_adapter *adapter)
367{
368 return I2C_FUNC_SMBUS_BYTE |
369 I2C_FUNC_SMBUS_BYTE_DATA |
370 I2C_FUNC_SMBUS_WORD_DATA |
371 I2C_FUNC_SMBUS_BLOCK_DATA |
372 I2C_FUNC_SMBUS_I2C_BLOCK;
373}
374
375static struct i2c_algorithm xgene_slimpro_i2c_algorithm = {
376 .smbus_xfer = xgene_slimpro_i2c_xfer,
377 .functionality = xgene_slimpro_i2c_func,
378};
379
380static int xgene_slimpro_i2c_probe(struct platform_device *pdev)
381{
382 struct slimpro_i2c_dev *ctx;
383 struct i2c_adapter *adapter;
384 struct mbox_client *cl;
385 int rc;
386
387 ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
388 if (!ctx)
389 return -ENOMEM;
390
391 ctx->dev = &pdev->dev;
392 platform_set_drvdata(pdev, ctx);
393 cl = &ctx->mbox_client;
394
395 /* Request mailbox channel */
396 cl->dev = &pdev->dev;
397 cl->rx_callback = slimpro_i2c_rx_cb;
398 cl->tx_block = true;
399 init_completion(&ctx->rd_complete);
400 cl->tx_tout = MAILBOX_OP_TIMEOUT;
401 cl->knows_txdone = false;
402 ctx->mbox_chan = mbox_request_channel(cl, MAILBOX_I2C_INDEX);
403 if (IS_ERR(ctx->mbox_chan)) {
404 dev_err(&pdev->dev, "i2c mailbox channel request failed\n");
405 return PTR_ERR(ctx->mbox_chan);
406 }
407
408 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
409 if (rc)
410 dev_warn(&pdev->dev, "Unable to set dma mask\n");
411
412 /* Setup I2C adapter */
413 adapter = &ctx->adapter;
414 snprintf(adapter->name, sizeof(adapter->name), "MAILBOX I2C");
415 adapter->algo = &xgene_slimpro_i2c_algorithm;
416 adapter->class = I2C_CLASS_HWMON;
417 adapter->dev.parent = &pdev->dev;
418 i2c_set_adapdata(adapter, ctx);
419 rc = i2c_add_adapter(adapter);
420 if (rc) {
421 dev_err(&pdev->dev, "Adapter registeration failed\n");
422 return rc;
423 }
424
425 dev_info(&pdev->dev, "Mailbox I2C Adapter registered\n");
426 return 0;
427}
428
429static int xgene_slimpro_i2c_remove(struct platform_device *pdev)
430{
431 struct slimpro_i2c_dev *ctx = platform_get_drvdata(pdev);
432
433 i2c_del_adapter(&ctx->adapter);
434
435 mbox_free_channel(ctx->mbox_chan);
436
437 return 0;
438}
439
440static const struct of_device_id xgene_slimpro_i2c_dt_ids[] = {
441 {.compatible = "apm,xgene-slimpro-i2c" },
442 {},
443};
444MODULE_DEVICE_TABLE(of, xgene_slimpro_i2c_dt_ids);
445
446#ifdef CONFIG_ACPI
447static const struct acpi_device_id xgene_slimpro_i2c_acpi_ids[] = {
448 {"APMC0D40", 0},
449 {}
450};
451MODULE_DEVICE_TABLE(acpi, xgene_slimpro_i2c_acpi_ids);
452#endif
453
454static struct platform_driver xgene_slimpro_i2c_driver = {
455 .probe = xgene_slimpro_i2c_probe,
456 .remove = xgene_slimpro_i2c_remove,
457 .driver = {
458 .name = "xgene-slimpro-i2c",
459 .of_match_table = of_match_ptr(xgene_slimpro_i2c_dt_ids),
460 .acpi_match_table = ACPI_PTR(xgene_slimpro_i2c_acpi_ids)
461 },
462};
463
464module_platform_driver(xgene_slimpro_i2c_driver);
465
466MODULE_DESCRIPTION("APM X-Gene SLIMpro I2C driver");
467MODULE_AUTHOR("Feng Kan <fkan@apm.com>");
468MODULE_AUTHOR("Hieu Le <hnle@apm.com>");
469MODULE_LICENSE("GPL");
diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c
index e8400042b358..4dda23f22a67 100644
--- a/drivers/i2c/busses/i2c-xiic.c
+++ b/drivers/i2c/busses/i2c-xiic.c
@@ -63,6 +63,7 @@ enum xiic_endian {
63 * @state: See STATE_ 63 * @state: See STATE_
64 * @rx_msg: Current RX message 64 * @rx_msg: Current RX message
65 * @rx_pos: Position within current RX message 65 * @rx_pos: Position within current RX message
66 * @endianness: big/little-endian byte order
66 */ 67 */
67struct xiic_i2c { 68struct xiic_i2c {
68 void __iomem *base; 69 void __iomem *base;
diff --git a/drivers/i2c/i2c-core.c b/drivers/i2c/i2c-core.c
index fc2ee8213fb6..069a41f116dd 100644
--- a/drivers/i2c/i2c-core.c
+++ b/drivers/i2c/i2c-core.c
@@ -257,7 +257,7 @@ acpi_i2c_space_handler(u32 function, acpi_physical_address command,
257 struct acpi_connection_info *info = &data->info; 257 struct acpi_connection_info *info = &data->info;
258 struct acpi_resource_i2c_serialbus *sb; 258 struct acpi_resource_i2c_serialbus *sb;
259 struct i2c_adapter *adapter = data->adapter; 259 struct i2c_adapter *adapter = data->adapter;
260 struct i2c_client client; 260 struct i2c_client *client;
261 struct acpi_resource *ares; 261 struct acpi_resource *ares;
262 u32 accessor_type = function >> 16; 262 u32 accessor_type = function >> 16;
263 u8 action = function & ACPI_IO_MASK; 263 u8 action = function & ACPI_IO_MASK;
@@ -268,6 +268,12 @@ acpi_i2c_space_handler(u32 function, acpi_physical_address command,
268 if (ACPI_FAILURE(ret)) 268 if (ACPI_FAILURE(ret))
269 return ret; 269 return ret;
270 270
271 client = kzalloc(sizeof(*client), GFP_KERNEL);
272 if (!client) {
273 ret = AE_NO_MEMORY;
274 goto err;
275 }
276
271 if (!value64 || ares->type != ACPI_RESOURCE_TYPE_SERIAL_BUS) { 277 if (!value64 || ares->type != ACPI_RESOURCE_TYPE_SERIAL_BUS) {
272 ret = AE_BAD_PARAMETER; 278 ret = AE_BAD_PARAMETER;
273 goto err; 279 goto err;
@@ -279,75 +285,73 @@ acpi_i2c_space_handler(u32 function, acpi_physical_address command,
279 goto err; 285 goto err;
280 } 286 }
281 287
282 memset(&client, 0, sizeof(client)); 288 client->adapter = adapter;
283 client.adapter = adapter; 289 client->addr = sb->slave_address;
284 client.addr = sb->slave_address;
285 client.flags = 0;
286 290
287 if (sb->access_mode == ACPI_I2C_10BIT_MODE) 291 if (sb->access_mode == ACPI_I2C_10BIT_MODE)
288 client.flags |= I2C_CLIENT_TEN; 292 client->flags |= I2C_CLIENT_TEN;
289 293
290 switch (accessor_type) { 294 switch (accessor_type) {
291 case ACPI_GSB_ACCESS_ATTRIB_SEND_RCV: 295 case ACPI_GSB_ACCESS_ATTRIB_SEND_RCV:
292 if (action == ACPI_READ) { 296 if (action == ACPI_READ) {
293 status = i2c_smbus_read_byte(&client); 297 status = i2c_smbus_read_byte(client);
294 if (status >= 0) { 298 if (status >= 0) {
295 gsb->bdata = status; 299 gsb->bdata = status;
296 status = 0; 300 status = 0;
297 } 301 }
298 } else { 302 } else {
299 status = i2c_smbus_write_byte(&client, gsb->bdata); 303 status = i2c_smbus_write_byte(client, gsb->bdata);
300 } 304 }
301 break; 305 break;
302 306
303 case ACPI_GSB_ACCESS_ATTRIB_BYTE: 307 case ACPI_GSB_ACCESS_ATTRIB_BYTE:
304 if (action == ACPI_READ) { 308 if (action == ACPI_READ) {
305 status = i2c_smbus_read_byte_data(&client, command); 309 status = i2c_smbus_read_byte_data(client, command);
306 if (status >= 0) { 310 if (status >= 0) {
307 gsb->bdata = status; 311 gsb->bdata = status;
308 status = 0; 312 status = 0;
309 } 313 }
310 } else { 314 } else {
311 status = i2c_smbus_write_byte_data(&client, command, 315 status = i2c_smbus_write_byte_data(client, command,
312 gsb->bdata); 316 gsb->bdata);
313 } 317 }
314 break; 318 break;
315 319
316 case ACPI_GSB_ACCESS_ATTRIB_WORD: 320 case ACPI_GSB_ACCESS_ATTRIB_WORD:
317 if (action == ACPI_READ) { 321 if (action == ACPI_READ) {
318 status = i2c_smbus_read_word_data(&client, command); 322 status = i2c_smbus_read_word_data(client, command);
319 if (status >= 0) { 323 if (status >= 0) {
320 gsb->wdata = status; 324 gsb->wdata = status;
321 status = 0; 325 status = 0;
322 } 326 }
323 } else { 327 } else {
324 status = i2c_smbus_write_word_data(&client, command, 328 status = i2c_smbus_write_word_data(client, command,
325 gsb->wdata); 329 gsb->wdata);
326 } 330 }
327 break; 331 break;
328 332
329 case ACPI_GSB_ACCESS_ATTRIB_BLOCK: 333 case ACPI_GSB_ACCESS_ATTRIB_BLOCK:
330 if (action == ACPI_READ) { 334 if (action == ACPI_READ) {
331 status = i2c_smbus_read_block_data(&client, command, 335 status = i2c_smbus_read_block_data(client, command,
332 gsb->data); 336 gsb->data);
333 if (status >= 0) { 337 if (status >= 0) {
334 gsb->len = status; 338 gsb->len = status;
335 status = 0; 339 status = 0;
336 } 340 }
337 } else { 341 } else {
338 status = i2c_smbus_write_block_data(&client, command, 342 status = i2c_smbus_write_block_data(client, command,
339 gsb->len, gsb->data); 343 gsb->len, gsb->data);
340 } 344 }
341 break; 345 break;
342 346
343 case ACPI_GSB_ACCESS_ATTRIB_MULTIBYTE: 347 case ACPI_GSB_ACCESS_ATTRIB_MULTIBYTE:
344 if (action == ACPI_READ) { 348 if (action == ACPI_READ) {
345 status = acpi_gsb_i2c_read_bytes(&client, command, 349 status = acpi_gsb_i2c_read_bytes(client, command,
346 gsb->data, info->access_length); 350 gsb->data, info->access_length);
347 if (status > 0) 351 if (status > 0)
348 status = 0; 352 status = 0;
349 } else { 353 } else {
350 status = acpi_gsb_i2c_write_bytes(&client, command, 354 status = acpi_gsb_i2c_write_bytes(client, command,
351 gsb->data, info->access_length); 355 gsb->data, info->access_length);
352 } 356 }
353 break; 357 break;
@@ -361,6 +365,7 @@ acpi_i2c_space_handler(u32 function, acpi_physical_address command,
361 gsb->status = status; 365 gsb->status = status;
362 366
363 err: 367 err:
368 kfree(client);
364 ACPI_FREE(ares); 369 ACPI_FREE(ares);
365 return ret; 370 return ret;
366} 371}
@@ -1276,7 +1281,7 @@ static struct i2c_client *of_i2c_register_device(struct i2c_adapter *adap,
1276 } 1281 }
1277 1282
1278 addr = of_get_property(node, "reg", &len); 1283 addr = of_get_property(node, "reg", &len);
1279 if (!addr || (len < sizeof(int))) { 1284 if (!addr || (len < sizeof(*addr))) {
1280 dev_err(&adap->dev, "of_i2c: invalid reg on %s\n", 1285 dev_err(&adap->dev, "of_i2c: invalid reg on %s\n",
1281 node->full_name); 1286 node->full_name);
1282 return ERR_PTR(-EINVAL); 1287 return ERR_PTR(-EINVAL);
@@ -1677,7 +1682,7 @@ void i2c_del_adapter(struct i2c_adapter *adap)
1677 * FIXME: This is old code and should ideally be replaced by an 1682 * FIXME: This is old code and should ideally be replaced by an
1678 * alternative which results in decoupling the lifetime of the struct 1683 * alternative which results in decoupling the lifetime of the struct
1679 * device from the i2c_adapter, like spi or netdev do. Any solution 1684 * device from the i2c_adapter, like spi or netdev do. Any solution
1680 * should be throughly tested with DEBUG_KOBJECT_RELEASE enabled! 1685 * should be thoroughly tested with DEBUG_KOBJECT_RELEASE enabled!
1681 */ 1686 */
1682 init_completion(&adap->dev_released); 1687 init_completion(&adap->dev_released);
1683 device_unregister(&adap->dev); 1688 device_unregister(&adap->dev);
@@ -2918,18 +2923,24 @@ int i2c_slave_register(struct i2c_client *client, i2c_slave_cb_t slave_cb)
2918{ 2923{
2919 int ret; 2924 int ret;
2920 2925
2921 if (!client || !slave_cb) 2926 if (!client || !slave_cb) {
2927 WARN(1, "insufficent data\n");
2922 return -EINVAL; 2928 return -EINVAL;
2929 }
2923 2930
2924 if (!(client->flags & I2C_CLIENT_TEN)) { 2931 if (!(client->flags & I2C_CLIENT_TEN)) {
2925 /* Enforce stricter address checking */ 2932 /* Enforce stricter address checking */
2926 ret = i2c_check_addr_validity(client->addr); 2933 ret = i2c_check_addr_validity(client->addr);
2927 if (ret) 2934 if (ret) {
2935 dev_err(&client->dev, "%s: invalid address\n", __func__);
2928 return ret; 2936 return ret;
2937 }
2929 } 2938 }
2930 2939
2931 if (!client->adapter->algo->reg_slave) 2940 if (!client->adapter->algo->reg_slave) {
2941 dev_err(&client->dev, "%s: not supported by adapter\n", __func__);
2932 return -EOPNOTSUPP; 2942 return -EOPNOTSUPP;
2943 }
2933 2944
2934 client->slave_cb = slave_cb; 2945 client->slave_cb = slave_cb;
2935 2946
@@ -2937,8 +2948,10 @@ int i2c_slave_register(struct i2c_client *client, i2c_slave_cb_t slave_cb)
2937 ret = client->adapter->algo->reg_slave(client); 2948 ret = client->adapter->algo->reg_slave(client);
2938 i2c_unlock_adapter(client->adapter); 2949 i2c_unlock_adapter(client->adapter);
2939 2950
2940 if (ret) 2951 if (ret) {
2941 client->slave_cb = NULL; 2952 client->slave_cb = NULL;
2953 dev_err(&client->dev, "%s: adapter returned error %d\n", __func__, ret);
2954 }
2942 2955
2943 return ret; 2956 return ret;
2944} 2957}
@@ -2948,8 +2961,10 @@ int i2c_slave_unregister(struct i2c_client *client)
2948{ 2961{
2949 int ret; 2962 int ret;
2950 2963
2951 if (!client->adapter->algo->unreg_slave) 2964 if (!client->adapter->algo->unreg_slave) {
2965 dev_err(&client->dev, "%s: not supported by adapter\n", __func__);
2952 return -EOPNOTSUPP; 2966 return -EOPNOTSUPP;
2967 }
2953 2968
2954 i2c_lock_adapter(client->adapter); 2969 i2c_lock_adapter(client->adapter);
2955 ret = client->adapter->algo->unreg_slave(client); 2970 ret = client->adapter->algo->unreg_slave(client);
@@ -2957,6 +2972,8 @@ int i2c_slave_unregister(struct i2c_client *client)
2957 2972
2958 if (ret == 0) 2973 if (ret == 0)
2959 client->slave_cb = NULL; 2974 client->slave_cb = NULL;
2975 else
2976 dev_err(&client->dev, "%s: adapter returned error %d\n", __func__, ret);
2960 2977
2961 return ret; 2978 return ret;
2962} 2979}
diff --git a/drivers/i2c/i2c-mux.c b/drivers/i2c/i2c-mux.c
index 06cc1ff088f1..2ba7c0fbc615 100644
--- a/drivers/i2c/i2c-mux.c
+++ b/drivers/i2c/i2c-mux.c
@@ -51,7 +51,7 @@ static int i2c_mux_master_xfer(struct i2c_adapter *adap,
51 51
52 ret = priv->select(parent, priv->mux_priv, priv->chan_id); 52 ret = priv->select(parent, priv->mux_priv, priv->chan_id);
53 if (ret >= 0) 53 if (ret >= 0)
54 ret = parent->algo->master_xfer(parent, msgs, num); 54 ret = __i2c_transfer(parent, msgs, num);
55 if (priv->deselect) 55 if (priv->deselect)
56 priv->deselect(parent, priv->mux_priv, priv->chan_id); 56 priv->deselect(parent, priv->mux_priv, priv->chan_id);
57 57
@@ -144,6 +144,7 @@ struct i2c_adapter *i2c_add_mux_adapter(struct i2c_adapter *parent,
144 priv->adap.dev.parent = &parent->dev; 144 priv->adap.dev.parent = &parent->dev;
145 priv->adap.retries = parent->retries; 145 priv->adap.retries = parent->retries;
146 priv->adap.timeout = parent->timeout; 146 priv->adap.timeout = parent->timeout;
147 priv->adap.quirks = parent->quirks;
147 148
148 /* Sanity check on class */ 149 /* Sanity check on class */
149 if (i2c_mux_parent_classes(parent) & class) 150 if (i2c_mux_parent_classes(parent) & class)
diff --git a/drivers/i2c/i2c-smbus.c b/drivers/i2c/i2c-smbus.c
index 9ebf9cb4ad7a..94765a81970d 100644
--- a/drivers/i2c/i2c-smbus.c
+++ b/drivers/i2c/i2c-smbus.c
@@ -89,7 +89,7 @@ static void smbus_alert(struct work_struct *work)
89 * to high, because of slave transmit arbitration. After 89 * to high, because of slave transmit arbitration. After
90 * responding, an SMBus device stops asserting SMBALERT#. 90 * responding, an SMBus device stops asserting SMBALERT#.
91 * 91 *
92 * Note that SMBus 2.0 reserves 10-bit addresess for future 92 * Note that SMBus 2.0 reserves 10-bit addresses for future
93 * use. We neither handle them, nor try to use PEC here. 93 * use. We neither handle them, nor try to use PEC here.
94 */ 94 */
95 status = i2c_smbus_read_byte(ara); 95 status = i2c_smbus_read_byte(ara);
diff --git a/drivers/i2c/muxes/Kconfig b/drivers/i2c/muxes/Kconfig
index f6d313e528de..fdd0769c84a3 100644
--- a/drivers/i2c/muxes/Kconfig
+++ b/drivers/i2c/muxes/Kconfig
@@ -7,7 +7,8 @@ menu "Multiplexer I2C Chip support"
7 7
8config I2C_ARB_GPIO_CHALLENGE 8config I2C_ARB_GPIO_CHALLENGE
9 tristate "GPIO-based I2C arbitration" 9 tristate "GPIO-based I2C arbitration"
10 depends on GPIOLIB && OF 10 depends on GPIOLIB || COMPILE_TEST
11 depends on OF
11 help 12 help
12 If you say yes to this option, support will be included for an 13 If you say yes to this option, support will be included for an
13 I2C multimaster arbitration scheme using GPIOs and a challenge & 14 I2C multimaster arbitration scheme using GPIOs and a challenge &
@@ -40,7 +41,7 @@ config I2C_MUX_PCA9541
40 41
41config I2C_MUX_PCA954x 42config I2C_MUX_PCA954x
42 tristate "Philips PCA954x I2C Mux/switches" 43 tristate "Philips PCA954x I2C Mux/switches"
43 depends on GPIOLIB 44 depends on GPIOLIB || COMPILE_TEST
44 help 45 help
45 If you say yes here you get support for the Philips PCA954x 46 If you say yes here you get support for the Philips PCA954x
46 I2C mux/switch devices. 47 I2C mux/switch devices.
diff --git a/drivers/i2c/muxes/i2c-mux-pca9541.c b/drivers/i2c/muxes/i2c-mux-pca9541.c
index cb772775da43..0c8d4d2cbdaf 100644
--- a/drivers/i2c/muxes/i2c-mux-pca9541.c
+++ b/drivers/i2c/muxes/i2c-mux-pca9541.c
@@ -104,7 +104,7 @@ static int pca9541_reg_write(struct i2c_client *client, u8 command, u8 val)
104 buf[0] = command; 104 buf[0] = command;
105 buf[1] = val; 105 buf[1] = val;
106 msg.buf = buf; 106 msg.buf = buf;
107 ret = adap->algo->master_xfer(adap, &msg, 1); 107 ret = __i2c_transfer(adap, &msg, 1);
108 } else { 108 } else {
109 union i2c_smbus_data data; 109 union i2c_smbus_data data;
110 110
@@ -144,7 +144,7 @@ static int pca9541_reg_read(struct i2c_client *client, u8 command)
144 .buf = &val 144 .buf = &val
145 } 145 }
146 }; 146 };
147 ret = adap->algo->master_xfer(adap, msg, 2); 147 ret = __i2c_transfer(adap, msg, 2);
148 if (ret == 2) 148 if (ret == 2)
149 ret = val; 149 ret = val;
150 else if (ret >= 0) 150 else if (ret >= 0)
diff --git a/drivers/i2c/muxes/i2c-mux-pca954x.c b/drivers/i2c/muxes/i2c-mux-pca954x.c
index bea0d2de2993..ea4aa9dfcea9 100644
--- a/drivers/i2c/muxes/i2c-mux-pca954x.c
+++ b/drivers/i2c/muxes/i2c-mux-pca954x.c
@@ -134,7 +134,7 @@ static int pca954x_reg_write(struct i2c_adapter *adap,
134 msg.len = 1; 134 msg.len = 1;
135 buf[0] = val; 135 buf[0] = val;
136 msg.buf = buf; 136 msg.buf = buf;
137 ret = adap->algo->master_xfer(adap, &msg, 1); 137 ret = __i2c_transfer(adap, &msg, 1);
138 } else { 138 } else {
139 union i2c_smbus_data data; 139 union i2c_smbus_data data;
140 ret = adap->algo->smbus_xfer(adap, client->addr, 140 ret = adap->algo->smbus_xfer(adap, client->addr,
diff --git a/include/uapi/linux/i2c.h b/include/uapi/linux/i2c.h
index 0e949cbfd333..b0a7dd61eb35 100644
--- a/include/uapi/linux/i2c.h
+++ b/include/uapi/linux/i2c.h
@@ -87,6 +87,7 @@ struct i2c_msg {
87#define I2C_FUNC_PROTOCOL_MANGLING 0x00000004 /* I2C_M_IGNORE_NAK etc. */ 87#define I2C_FUNC_PROTOCOL_MANGLING 0x00000004 /* I2C_M_IGNORE_NAK etc. */
88#define I2C_FUNC_SMBUS_PEC 0x00000008 88#define I2C_FUNC_SMBUS_PEC 0x00000008
89#define I2C_FUNC_NOSTART 0x00000010 /* I2C_M_NOSTART */ 89#define I2C_FUNC_NOSTART 0x00000010 /* I2C_M_NOSTART */
90#define I2C_FUNC_SLAVE 0x00000020
90#define I2C_FUNC_SMBUS_BLOCK_PROC_CALL 0x00008000 /* SMBus 2.0 */ 91#define I2C_FUNC_SMBUS_BLOCK_PROC_CALL 0x00008000 /* SMBus 2.0 */
91#define I2C_FUNC_SMBUS_QUICK 0x00010000 92#define I2C_FUNC_SMBUS_QUICK 0x00010000
92#define I2C_FUNC_SMBUS_READ_BYTE 0x00020000 93#define I2C_FUNC_SMBUS_READ_BYTE 0x00020000
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-12 19:31:24 -0400