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-rw-r--r--Documentation/devicetree/bindings/mtd/gpmc-nand.txt2
-rw-r--r--MAINTAINERS5
-rw-r--r--arch/arm/boot/dts/dra7.dtsi16
-rw-r--r--arch/arm/boot/dts/imx53-qsrb.dts8
-rw-r--r--arch/arm/boot/dts/imx6dl-hummingboard.dts4
-rw-r--r--arch/arm/boot/dts/imx6qdl-cubox-i.dtsi19
-rw-r--r--arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi2
-rw-r--r--arch/arm/boot/dts/omap3-beagle.dts1
-rw-r--r--arch/arm/boot/dts/omap3430-sdp.dts2
-rw-r--r--arch/arm/boot/dts/omap54xx-clocks.dtsi16
-rw-r--r--arch/arm/boot/dts/twl6030.dtsi4
-rw-r--r--arch/arm/mach-bcm/Makefile1
-rw-r--r--arch/arm/mach-bcm/brcmstb.h19
-rw-r--r--arch/arm/mach-bcm/headsmp-brcmstb.S33
-rw-r--r--arch/arm/mach-bcm/platsmp-brcmstb.c363
-rw-r--r--arch/arm/mach-omap2/board-flash.c2
-rw-r--r--arch/arm/mach-omap2/gpmc-nand.c3
-rw-r--r--arch/arm/mach-omap2/gpmc.c7
-rw-r--r--arch/arm/mach-omap2/id.c2
-rw-r--r--arch/arm/mach-omap2/omap_device.c2
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c7
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_7xx_data.c22
-rw-r--r--arch/arm/mach-omap2/soc.h6
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7790.c4
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7791.c2
-rw-r--r--arch/arm/mach-shmobile/clock-sh73a0.c2
-rw-r--r--arch/arm/mach-vexpress/spc.c14
-rw-r--r--drivers/mtd/nand/omap2.c16
-rw-r--r--include/linux/platform_data/mtd-nand-omap2.h13
29 files changed, 133 insertions, 464 deletions
diff --git a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
index 65f4f7c43136..ee654e95d8ad 100644
--- a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
@@ -22,7 +22,7 @@ Optional properties:
22 width of 8 is assumed. 22 width of 8 is assumed.
23 23
24 - ti,nand-ecc-opt: A string setting the ECC layout to use. One of: 24 - ti,nand-ecc-opt: A string setting the ECC layout to use. One of:
25 "sw" <deprecated> use "ham1" instead 25 "sw" 1-bit Hamming ecc code via software
26 "hw" <deprecated> use "ham1" instead 26 "hw" <deprecated> use "ham1" instead
27 "hw-romcode" <deprecated> use "ham1" instead 27 "hw-romcode" <deprecated> use "ham1" instead
28 "ham1" 1-bit Hamming ecc code 28 "ham1" 1-bit Hamming ecc code
diff --git a/MAINTAINERS b/MAINTAINERS
index 217dc542e808..cf24bb56bab9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1279,8 +1279,13 @@ M: Heiko Stuebner <heiko@sntech.de>
1279L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 1279L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1280L: linux-rockchip@lists.infradead.org 1280L: linux-rockchip@lists.infradead.org
1281S: Maintained 1281S: Maintained
1282F: arch/arm/boot/dts/rk3*
1282F: arch/arm/mach-rockchip/ 1283F: arch/arm/mach-rockchip/
1284F: drivers/clk/rockchip/
1285F: drivers/i2c/busses/i2c-rk3x.c
1283F: drivers/*/*rockchip* 1286F: drivers/*/*rockchip*
1287F: drivers/*/*/*rockchip*
1288F: sound/soc/rockchip/
1284 1289
1285ARM/SAMSUNG ARM ARCHITECTURES 1290ARM/SAMSUNG ARM ARCHITECTURES
1286M: Ben Dooks <ben-linux@fluff.org> 1291M: Ben Dooks <ben-linux@fluff.org>
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 97f603c4483d..d678152db4cb 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -245,7 +245,7 @@
245 gpio-controller; 245 gpio-controller;
246 #gpio-cells = <2>; 246 #gpio-cells = <2>;
247 interrupt-controller; 247 interrupt-controller;
248 #interrupt-cells = <1>; 248 #interrupt-cells = <2>;
249 }; 249 };
250 250
251 gpio2: gpio@48055000 { 251 gpio2: gpio@48055000 {
@@ -256,7 +256,7 @@
256 gpio-controller; 256 gpio-controller;
257 #gpio-cells = <2>; 257 #gpio-cells = <2>;
258 interrupt-controller; 258 interrupt-controller;
259 #interrupt-cells = <1>; 259 #interrupt-cells = <2>;
260 }; 260 };
261 261
262 gpio3: gpio@48057000 { 262 gpio3: gpio@48057000 {
@@ -267,7 +267,7 @@
267 gpio-controller; 267 gpio-controller;
268 #gpio-cells = <2>; 268 #gpio-cells = <2>;
269 interrupt-controller; 269 interrupt-controller;
270 #interrupt-cells = <1>; 270 #interrupt-cells = <2>;
271 }; 271 };
272 272
273 gpio4: gpio@48059000 { 273 gpio4: gpio@48059000 {
@@ -278,7 +278,7 @@
278 gpio-controller; 278 gpio-controller;
279 #gpio-cells = <2>; 279 #gpio-cells = <2>;
280 interrupt-controller; 280 interrupt-controller;
281 #interrupt-cells = <1>; 281 #interrupt-cells = <2>;
282 }; 282 };
283 283
284 gpio5: gpio@4805b000 { 284 gpio5: gpio@4805b000 {
@@ -289,7 +289,7 @@
289 gpio-controller; 289 gpio-controller;
290 #gpio-cells = <2>; 290 #gpio-cells = <2>;
291 interrupt-controller; 291 interrupt-controller;
292 #interrupt-cells = <1>; 292 #interrupt-cells = <2>;
293 }; 293 };
294 294
295 gpio6: gpio@4805d000 { 295 gpio6: gpio@4805d000 {
@@ -300,7 +300,7 @@
300 gpio-controller; 300 gpio-controller;
301 #gpio-cells = <2>; 301 #gpio-cells = <2>;
302 interrupt-controller; 302 interrupt-controller;
303 #interrupt-cells = <1>; 303 #interrupt-cells = <2>;
304 }; 304 };
305 305
306 gpio7: gpio@48051000 { 306 gpio7: gpio@48051000 {
@@ -311,7 +311,7 @@
311 gpio-controller; 311 gpio-controller;
312 #gpio-cells = <2>; 312 #gpio-cells = <2>;
313 interrupt-controller; 313 interrupt-controller;
314 #interrupt-cells = <1>; 314 #interrupt-cells = <2>;
315 }; 315 };
316 316
317 gpio8: gpio@48053000 { 317 gpio8: gpio@48053000 {
@@ -322,7 +322,7 @@
322 gpio-controller; 322 gpio-controller;
323 #gpio-cells = <2>; 323 #gpio-cells = <2>;
324 interrupt-controller; 324 interrupt-controller;
325 #interrupt-cells = <1>; 325 #interrupt-cells = <2>;
326 }; 326 };
327 327
328 uart1: serial@4806a000 { 328 uart1: serial@4806a000 {
diff --git a/arch/arm/boot/dts/imx53-qsrb.dts b/arch/arm/boot/dts/imx53-qsrb.dts
index f1bbf9a32991..82d623d05915 100644
--- a/arch/arm/boot/dts/imx53-qsrb.dts
+++ b/arch/arm/boot/dts/imx53-qsrb.dts
@@ -28,6 +28,12 @@
28 MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec 28 MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec
29 >; 29 >;
30 }; 30 };
31
32 pinctrl_pmic: pmicgrp {
33 fsl,pins = <
34 MX53_PAD_CSI0_DAT5__GPIO5_23 0x1e4 /* IRQ */
35 >;
36 };
31 }; 37 };
32}; 38};
33 39
@@ -38,6 +44,8 @@
38 44
39 pmic: mc34708@8 { 45 pmic: mc34708@8 {
40 compatible = "fsl,mc34708"; 46 compatible = "fsl,mc34708";
47 pinctrl-names = "default";
48 pinctrl-0 = <&pinctrl_pmic>;
41 reg = <0x08>; 49 reg = <0x08>;
42 interrupt-parent = <&gpio5>; 50 interrupt-parent = <&gpio5>;
43 interrupts = <23 0x8>; 51 interrupts = <23 0x8>;
diff --git a/arch/arm/boot/dts/imx6dl-hummingboard.dts b/arch/arm/boot/dts/imx6dl-hummingboard.dts
index c8e51dd41b8f..71598546087f 100644
--- a/arch/arm/boot/dts/imx6dl-hummingboard.dts
+++ b/arch/arm/boot/dts/imx6dl-hummingboard.dts
@@ -58,7 +58,7 @@
58 58
59 sound-spdif { 59 sound-spdif {
60 compatible = "fsl,imx-audio-spdif"; 60 compatible = "fsl,imx-audio-spdif";
61 model = "imx-spdif"; 61 model = "On-board SPDIF";
62 /* IMX6 doesn't implement this yet */ 62 /* IMX6 doesn't implement this yet */
63 spdif-controller = <&spdif>; 63 spdif-controller = <&spdif>;
64 spdif-out; 64 spdif-out;
@@ -181,11 +181,13 @@
181}; 181};
182 182
183&usbh1 { 183&usbh1 {
184 disable-over-current;
184 vbus-supply = <&reg_usbh1_vbus>; 185 vbus-supply = <&reg_usbh1_vbus>;
185 status = "okay"; 186 status = "okay";
186}; 187};
187 188
188&usbotg { 189&usbotg {
190 disable-over-current;
189 pinctrl-names = "default"; 191 pinctrl-names = "default";
190 pinctrl-0 = <&pinctrl_hummingboard_usbotg_id>; 192 pinctrl-0 = <&pinctrl_hummingboard_usbotg_id>;
191 vbus-supply = <&reg_usbotg_vbus>; 193 vbus-supply = <&reg_usbotg_vbus>;
diff --git a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
index e8e781656b3f..6a524ca011e7 100644
--- a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
@@ -61,7 +61,7 @@
61 61
62 sound-spdif { 62 sound-spdif {
63 compatible = "fsl,imx-audio-spdif"; 63 compatible = "fsl,imx-audio-spdif";
64 model = "imx-spdif"; 64 model = "Integrated SPDIF";
65 /* IMX6 doesn't implement this yet */ 65 /* IMX6 doesn't implement this yet */
66 spdif-controller = <&spdif>; 66 spdif-controller = <&spdif>;
67 spdif-out; 67 spdif-out;
@@ -130,16 +130,23 @@
130 fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>; 130 fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>;
131 }; 131 };
132 132
133 pinctrl_cubox_i_usbh1: cubox-i-usbh1 {
134 fsl,pins = <MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1b0b0>;
135 };
136
133 pinctrl_cubox_i_usbh1_vbus: cubox-i-usbh1-vbus { 137 pinctrl_cubox_i_usbh1_vbus: cubox-i-usbh1-vbus {
134 fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x4001b0b0>; 138 fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x4001b0b0>;
135 }; 139 };
136 140
137 pinctrl_cubox_i_usbotg_id: cubox-i-usbotg-id { 141 pinctrl_cubox_i_usbotg: cubox-i-usbotg {
138 /* 142 /*
139 * The Cubox-i pulls this low, but as it's pointless 143 * The Cubox-i pulls ID low, but as it's pointless
140 * leaving it as a pull-up, even if it is just 10uA. 144 * leaving it as a pull-up, even if it is just 10uA.
141 */ 145 */
142 fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>; 146 fsl,pins = <
147 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
148 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
149 >;
143 }; 150 };
144 151
145 pinctrl_cubox_i_usbotg_vbus: cubox-i-usbotg-vbus { 152 pinctrl_cubox_i_usbotg_vbus: cubox-i-usbotg-vbus {
@@ -173,13 +180,15 @@
173}; 180};
174 181
175&usbh1 { 182&usbh1 {
183 pinctrl-names = "default";
184 pinctrl-0 = <&pinctrl_cubox_i_usbh1>;
176 vbus-supply = <&reg_usbh1_vbus>; 185 vbus-supply = <&reg_usbh1_vbus>;
177 status = "okay"; 186 status = "okay";
178}; 187};
179 188
180&usbotg { 189&usbotg {
181 pinctrl-names = "default"; 190 pinctrl-names = "default";
182 pinctrl-0 = <&pinctrl_cubox_i_usbotg_id>; 191 pinctrl-0 = <&pinctrl_cubox_i_usbotg>;
183 vbus-supply = <&reg_usbotg_vbus>; 192 vbus-supply = <&reg_usbotg_vbus>;
184 status = "okay"; 193 status = "okay";
185}; 194};
diff --git a/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi b/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
index d16066608e21..db9f45b2c573 100644
--- a/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
@@ -17,7 +17,7 @@
17 enet { 17 enet {
18 pinctrl_microsom_enet_ar8035: microsom-enet-ar8035 { 18 pinctrl_microsom_enet_ar8035: microsom-enet-ar8035 {
19 fsl,pins = < 19 fsl,pins = <
20 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 20 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0
21 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 21 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
22 /* AR8035 reset */ 22 /* AR8035 reset */
23 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0 23 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index 3c3e6da1deac..a9aae88b74f5 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -292,6 +292,7 @@
292&uart3 { 292&uart3 {
293 pinctrl-names = "default"; 293 pinctrl-names = "default";
294 pinctrl-0 = <&uart3_pins>; 294 pinctrl-0 = <&uart3_pins>;
295 interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
295}; 296};
296 297
297&gpio1 { 298&gpio1 {
diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts
index 02f69f4a8fd3..9bad94efe1c8 100644
--- a/arch/arm/boot/dts/omap3430-sdp.dts
+++ b/arch/arm/boot/dts/omap3430-sdp.dts
@@ -107,7 +107,7 @@
107 #address-cells = <1>; 107 #address-cells = <1>;
108 #size-cells = <1>; 108 #size-cells = <1>;
109 reg = <1 0 0x08000000>; 109 reg = <1 0 0x08000000>;
110 ti,nand-ecc-opt = "ham1"; 110 ti,nand-ecc-opt = "sw";
111 nand-bus-width = <8>; 111 nand-bus-width = <8>;
112 gpmc,cs-on-ns = <0>; 112 gpmc,cs-on-ns = <0>;
113 gpmc,cs-rd-off-ns = <36>; 113 gpmc,cs-rd-off-ns = <36>;
diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi
index e67a23b5d788..58c27466f012 100644
--- a/arch/arm/boot/dts/omap54xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi
@@ -367,10 +367,12 @@
367 367
368 l3_iclk_div: l3_iclk_div { 368 l3_iclk_div: l3_iclk_div {
369 #clock-cells = <0>; 369 #clock-cells = <0>;
370 compatible = "fixed-factor-clock"; 370 compatible = "ti,divider-clock";
371 ti,max-div = <2>;
372 ti,bit-shift = <4>;
373 reg = <0x100>;
371 clocks = <&dpll_core_h12x2_ck>; 374 clocks = <&dpll_core_h12x2_ck>;
372 clock-mult = <1>; 375 ti,index-power-of-two;
373 clock-div = <1>;
374 }; 376 };
375 377
376 gpu_l3_iclk: gpu_l3_iclk { 378 gpu_l3_iclk: gpu_l3_iclk {
@@ -383,10 +385,12 @@
383 385
384 l4_root_clk_div: l4_root_clk_div { 386 l4_root_clk_div: l4_root_clk_div {
385 #clock-cells = <0>; 387 #clock-cells = <0>;
386 compatible = "fixed-factor-clock"; 388 compatible = "ti,divider-clock";
389 ti,max-div = <2>;
390 ti,bit-shift = <8>;
391 reg = <0x100>;
387 clocks = <&l3_iclk_div>; 392 clocks = <&l3_iclk_div>;
388 clock-mult = <1>; 393 ti,index-power-of-two;
389 clock-div = <1>;
390 }; 394 };
391 395
392 slimbus1_slimbus_clk: slimbus1_slimbus_clk { 396 slimbus1_slimbus_clk: slimbus1_slimbus_clk {
diff --git a/arch/arm/boot/dts/twl6030.dtsi b/arch/arm/boot/dts/twl6030.dtsi
index 2e3bd3172b23..55eb35f068fb 100644
--- a/arch/arm/boot/dts/twl6030.dtsi
+++ b/arch/arm/boot/dts/twl6030.dtsi
@@ -83,10 +83,6 @@
83 regulator-always-on; 83 regulator-always-on;
84 }; 84 };
85 85
86 clk32kg: regulator-clk32kg {
87 compatible = "ti,twl6030-clk32kg";
88 };
89
90 twl_usb_comparator: usb-comparator { 86 twl_usb_comparator: usb-comparator {
91 compatible = "ti,twl6030-usb"; 87 compatible = "ti,twl6030-usb";
92 interrupts = <4>, <10>; 88 interrupts = <4>, <10>;
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index 67c492aabf4d..b19a39652545 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -36,5 +36,4 @@ obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o
36 36
37ifeq ($(CONFIG_ARCH_BRCMSTB),y) 37ifeq ($(CONFIG_ARCH_BRCMSTB),y)
38obj-y += brcmstb.o 38obj-y += brcmstb.o
39obj-$(CONFIG_SMP) += headsmp-brcmstb.o platsmp-brcmstb.o
40endif 39endif
diff --git a/arch/arm/mach-bcm/brcmstb.h b/arch/arm/mach-bcm/brcmstb.h
deleted file mode 100644
index ec0c3d112b36..000000000000
--- a/arch/arm/mach-bcm/brcmstb.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * Copyright (C) 2013-2014 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef __BRCMSTB_H__
15#define __BRCMSTB_H__
16
17void brcmstb_secondary_startup(void);
18
19#endif /* __BRCMSTB_H__ */
diff --git a/arch/arm/mach-bcm/headsmp-brcmstb.S b/arch/arm/mach-bcm/headsmp-brcmstb.S
deleted file mode 100644
index 199c1ea58248..000000000000
--- a/arch/arm/mach-bcm/headsmp-brcmstb.S
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * SMP boot code for secondary CPUs
3 * Based on arch/arm/mach-tegra/headsmp.S
4 *
5 * Copyright (C) 2010 NVIDIA, Inc.
6 * Copyright (C) 2013-2014 Broadcom Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation version 2.
11 *
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <asm/assembler.h>
19#include <linux/linkage.h>
20#include <linux/init.h>
21
22 .section ".text.head", "ax"
23
24ENTRY(brcmstb_secondary_startup)
25 /*
26 * Ensure CPU is in a sane state by disabling all IRQs and switching
27 * into SVC mode.
28 */
29 setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r0
30
31 bl v7_invalidate_l1
32 b secondary_startup
33ENDPROC(brcmstb_secondary_startup)
diff --git a/arch/arm/mach-bcm/platsmp-brcmstb.c b/arch/arm/mach-bcm/platsmp-brcmstb.c
deleted file mode 100644
index af780e9c23a6..000000000000
--- a/arch/arm/mach-bcm/platsmp-brcmstb.c
+++ /dev/null
@@ -1,363 +0,0 @@
1/*
2 * Broadcom STB CPU SMP and hotplug support for ARM
3 *
4 * Copyright (C) 2013-2014 Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/delay.h>
17#include <linux/errno.h>
18#include <linux/init.h>
19#include <linux/io.h>
20#include <linux/of_address.h>
21#include <linux/of_platform.h>
22#include <linux/printk.h>
23#include <linux/regmap.h>
24#include <linux/smp.h>
25#include <linux/mfd/syscon.h>
26#include <linux/spinlock.h>
27
28#include <asm/cacheflush.h>
29#include <asm/cp15.h>
30#include <asm/mach-types.h>
31#include <asm/smp_plat.h>
32
33#include "brcmstb.h"
34
35enum {
36 ZONE_MAN_CLKEN_MASK = BIT(0),
37 ZONE_MAN_RESET_CNTL_MASK = BIT(1),
38 ZONE_MAN_MEM_PWR_MASK = BIT(4),
39 ZONE_RESERVED_1_MASK = BIT(5),
40 ZONE_MAN_ISO_CNTL_MASK = BIT(6),
41 ZONE_MANUAL_CONTROL_MASK = BIT(7),
42 ZONE_PWR_DN_REQ_MASK = BIT(9),
43 ZONE_PWR_UP_REQ_MASK = BIT(10),
44 ZONE_BLK_RST_ASSERT_MASK = BIT(12),
45 ZONE_PWR_OFF_STATE_MASK = BIT(25),
46 ZONE_PWR_ON_STATE_MASK = BIT(26),
47 ZONE_DPG_PWR_STATE_MASK = BIT(28),
48 ZONE_MEM_PWR_STATE_MASK = BIT(29),
49 ZONE_RESET_STATE_MASK = BIT(31),
50 CPU0_PWR_ZONE_CTRL_REG = 1,
51 CPU_RESET_CONFIG_REG = 2,
52};
53
54static void __iomem *cpubiuctrl_block;
55static void __iomem *hif_cont_block;
56static u32 cpu0_pwr_zone_ctrl_reg;
57static u32 cpu_rst_cfg_reg;
58static u32 hif_cont_reg;
59
60#ifdef CONFIG_HOTPLUG_CPU
61static DEFINE_PER_CPU_ALIGNED(int, per_cpu_sw_state);
62
63static int per_cpu_sw_state_rd(u32 cpu)
64{
65 sync_cache_r(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu)));
66 return per_cpu(per_cpu_sw_state, cpu);
67}
68
69static void per_cpu_sw_state_wr(u32 cpu, int val)
70{
71 per_cpu(per_cpu_sw_state, cpu) = val;
72 dmb();
73 sync_cache_w(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu)));
74 dsb_sev();
75}
76#else
77static inline void per_cpu_sw_state_wr(u32 cpu, int val) { }
78#endif
79
80static void __iomem *pwr_ctrl_get_base(u32 cpu)
81{
82 void __iomem *base = cpubiuctrl_block + cpu0_pwr_zone_ctrl_reg;
83 base += (cpu_logical_map(cpu) * 4);
84 return base;
85}
86
87static u32 pwr_ctrl_rd(u32 cpu)
88{
89 void __iomem *base = pwr_ctrl_get_base(cpu);
90 return readl_relaxed(base);
91}
92
93static void pwr_ctrl_wr(u32 cpu, u32 val)
94{
95 void __iomem *base = pwr_ctrl_get_base(cpu);
96 writel(val, base);
97}
98
99static void cpu_rst_cfg_set(u32 cpu, int set)
100{
101 u32 val;
102 val = readl_relaxed(cpubiuctrl_block + cpu_rst_cfg_reg);
103 if (set)
104 val |= BIT(cpu_logical_map(cpu));
105 else
106 val &= ~BIT(cpu_logical_map(cpu));
107 writel_relaxed(val, cpubiuctrl_block + cpu_rst_cfg_reg);
108}
109
110static void cpu_set_boot_addr(u32 cpu, unsigned long boot_addr)
111{
112 const int reg_ofs = cpu_logical_map(cpu) * 8;
113 writel_relaxed(0, hif_cont_block + hif_cont_reg + reg_ofs);
114 writel_relaxed(boot_addr, hif_cont_block + hif_cont_reg + 4 + reg_ofs);
115}
116
117static void brcmstb_cpu_boot(u32 cpu)
118{
119 pr_info("SMP: Booting CPU%d...\n", cpu);
120
121 /*
122 * set the reset vector to point to the secondary_startup
123 * routine
124 */
125 cpu_set_boot_addr(cpu, virt_to_phys(brcmstb_secondary_startup));
126
127 /* unhalt the cpu */
128 cpu_rst_cfg_set(cpu, 0);
129}
130
131static void brcmstb_cpu_power_on(u32 cpu)
132{
133 /*
134 * The secondary cores power was cut, so we must go through
135 * power-on initialization.
136 */
137 u32 tmp;
138
139 pr_info("SMP: Powering up CPU%d...\n", cpu);
140
141 /* Request zone power up */
142 pwr_ctrl_wr(cpu, ZONE_PWR_UP_REQ_MASK);
143
144 /* Wait for the power up FSM to complete */
145 do {
146 tmp = pwr_ctrl_rd(cpu);
147 } while (!(tmp & ZONE_PWR_ON_STATE_MASK));
148
149 per_cpu_sw_state_wr(cpu, 1);
150}
151
152static int brcmstb_cpu_get_power_state(u32 cpu)
153{
154 int tmp = pwr_ctrl_rd(cpu);
155 return (tmp & ZONE_RESET_STATE_MASK) ? 0 : 1;
156}
157
158#ifdef CONFIG_HOTPLUG_CPU
159
160static void brcmstb_cpu_die(u32 cpu)
161{
162 v7_exit_coherency_flush(all);
163
164 /* Prevent all interrupts from reaching this CPU. */
165 arch_local_irq_disable();
166
167 /*
168 * Final full barrier to ensure everything before this instruction has
169 * quiesced.
170 */
171 isb();
172 dsb();
173
174 per_cpu_sw_state_wr(cpu, 0);
175
176 /* Sit and wait to die */
177 wfi();
178
179 /* We should never get here... */
180 panic("Spurious interrupt on CPU %d received!\n", cpu);
181}
182
183static int brcmstb_cpu_kill(u32 cpu)
184{
185 u32 tmp;
186
187 pr_info("SMP: Powering down CPU%d...\n", cpu);
188
189 while (per_cpu_sw_state_rd(cpu))
190 ;
191
192 /* Program zone reset */
193 pwr_ctrl_wr(cpu, ZONE_RESET_STATE_MASK | ZONE_BLK_RST_ASSERT_MASK |
194 ZONE_PWR_DN_REQ_MASK);
195
196 /* Verify zone reset */
197 tmp = pwr_ctrl_rd(cpu);
198 if (!(tmp & ZONE_RESET_STATE_MASK))
199 pr_err("%s: Zone reset bit for CPU %d not asserted!\n",
200 __func__, cpu);
201
202 /* Wait for power down */
203 do {
204 tmp = pwr_ctrl_rd(cpu);
205 } while (!(tmp & ZONE_PWR_OFF_STATE_MASK));
206
207 /* Settle-time from Broadcom-internal DVT reference code */
208 udelay(7);
209
210 /* Assert reset on the CPU */
211 cpu_rst_cfg_set(cpu, 1);
212
213 return 1;
214}
215
216#endif /* CONFIG_HOTPLUG_CPU */
217
218static int __init setup_hifcpubiuctrl_regs(struct device_node *np)
219{
220 int rc = 0;
221 char *name;
222 struct device_node *syscon_np = NULL;
223
224 name = "syscon-cpu";
225
226 syscon_np = of_parse_phandle(np, name, 0);
227 if (!syscon_np) {
228 pr_err("can't find phandle %s\n", name);
229 rc = -EINVAL;
230 goto cleanup;
231 }
232
233 cpubiuctrl_block = of_iomap(syscon_np, 0);
234 if (!cpubiuctrl_block) {
235 pr_err("iomap failed for cpubiuctrl_block\n");
236 rc = -EINVAL;
237 goto cleanup;
238 }
239
240 rc = of_property_read_u32_index(np, name, CPU0_PWR_ZONE_CTRL_REG,
241 &cpu0_pwr_zone_ctrl_reg);
242 if (rc) {
243 pr_err("failed to read 1st entry from %s property (%d)\n", name,
244 rc);
245 rc = -EINVAL;
246 goto cleanup;
247 }
248
249 rc = of_property_read_u32_index(np, name, CPU_RESET_CONFIG_REG,
250 &cpu_rst_cfg_reg);
251 if (rc) {
252 pr_err("failed to read 2nd entry from %s property (%d)\n", name,
253 rc);
254 rc = -EINVAL;
255 goto cleanup;
256 }
257
258cleanup:
259 if (syscon_np)
260 of_node_put(syscon_np);
261
262 return rc;
263}
264
265static int __init setup_hifcont_regs(struct device_node *np)
266{
267 int rc = 0;
268 char *name;
269 struct device_node *syscon_np = NULL;
270
271 name = "syscon-cont";
272
273 syscon_np = of_parse_phandle(np, name, 0);
274 if (!syscon_np) {
275 pr_err("can't find phandle %s\n", name);
276 rc = -EINVAL;
277 goto cleanup;
278 }
279
280 hif_cont_block = of_iomap(syscon_np, 0);
281 if (!hif_cont_block) {
282 pr_err("iomap failed for hif_cont_block\n");
283 rc = -EINVAL;
284 goto cleanup;
285 }
286
287 /* offset is at top of hif_cont_block */
288 hif_cont_reg = 0;
289
290cleanup:
291 if (syscon_np)
292 of_node_put(syscon_np);
293
294 return rc;
295}
296
297static void __init brcmstb_cpu_ctrl_setup(unsigned int max_cpus)
298{
299 int rc;
300 struct device_node *np;
301 char *name;
302
303 name = "brcm,brcmstb-smpboot";
304 np = of_find_compatible_node(NULL, NULL, name);
305 if (!np) {
306 pr_err("can't find compatible node %s\n", name);
307 return;
308 }
309
310 rc = setup_hifcpubiuctrl_regs(np);
311 if (rc)
312 return;
313
314 rc = setup_hifcont_regs(np);
315 if (rc)
316 return;
317}
318
319static DEFINE_SPINLOCK(boot_lock);
320
321static void brcmstb_secondary_init(unsigned int cpu)
322{
323 /*
324 * Synchronise with the boot thread.
325 */
326 spin_lock(&boot_lock);
327 spin_unlock(&boot_lock);
328}
329
330static int brcmstb_boot_secondary(unsigned int cpu, struct task_struct *idle)
331{
332 /*
333 * set synchronisation state between this boot processor
334 * and the secondary one
335 */
336 spin_lock(&boot_lock);
337
338 /* Bring up power to the core if necessary */
339 if (brcmstb_cpu_get_power_state(cpu) == 0)
340 brcmstb_cpu_power_on(cpu);
341
342 brcmstb_cpu_boot(cpu);
343
344 /*
345 * now the secondary core is starting up let it run its
346 * calibrations, then wait for it to finish
347 */
348 spin_unlock(&boot_lock);
349
350 return 0;
351}
352
353static struct smp_operations brcmstb_smp_ops __initdata = {
354 .smp_prepare_cpus = brcmstb_cpu_ctrl_setup,
355 .smp_secondary_init = brcmstb_secondary_init,
356 .smp_boot_secondary = brcmstb_boot_secondary,
357#ifdef CONFIG_HOTPLUG_CPU
358 .cpu_kill = brcmstb_cpu_kill,
359 .cpu_die = brcmstb_cpu_die,
360#endif
361};
362
363CPU_METHOD_OF_DECLARE(brcmstb_smp, "brcm,brahma-b15", &brcmstb_smp_ops);
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index e87f2a83d6bf..2d245c2e641c 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -142,7 +142,7 @@ __init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs,
142 board_nand_data.nr_parts = nr_parts; 142 board_nand_data.nr_parts = nr_parts;
143 board_nand_data.devsize = nand_type; 143 board_nand_data.devsize = nand_type;
144 144
145 board_nand_data.ecc_opt = OMAP_ECC_HAM1_CODE_HW; 145 board_nand_data.ecc_opt = OMAP_ECC_HAM1_CODE_SW;
146 gpmc_nand_init(&board_nand_data, gpmc_t); 146 gpmc_nand_init(&board_nand_data, gpmc_t);
147} 147}
148#endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */ 148#endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 8897ad7035fd..cb7764314f17 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -49,7 +49,8 @@ static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
49 return 0; 49 return 0;
50 50
51 /* legacy platforms support only HAM1 (1-bit Hamming) ECC scheme */ 51 /* legacy platforms support only HAM1 (1-bit Hamming) ECC scheme */
52 if (ecc_opt == OMAP_ECC_HAM1_CODE_HW) 52 if (ecc_opt == OMAP_ECC_HAM1_CODE_HW ||
53 ecc_opt == OMAP_ECC_HAM1_CODE_SW)
53 return 1; 54 return 1;
54 else 55 else
55 return 0; 56 return 0;
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 8bc13380f0a0..9f42d5437fcc 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -1403,8 +1403,11 @@ static int gpmc_probe_nand_child(struct platform_device *pdev,
1403 pr_err("%s: ti,nand-ecc-opt not found\n", __func__); 1403 pr_err("%s: ti,nand-ecc-opt not found\n", __func__);
1404 return -ENODEV; 1404 return -ENODEV;
1405 } 1405 }
1406 if (!strcmp(s, "ham1") || !strcmp(s, "sw") || 1406
1407 !strcmp(s, "hw") || !strcmp(s, "hw-romcode")) 1407 if (!strcmp(s, "sw"))
1408 gpmc_nand_data->ecc_opt = OMAP_ECC_HAM1_CODE_SW;
1409 else if (!strcmp(s, "ham1") ||
1410 !strcmp(s, "hw") || !strcmp(s, "hw-romcode"))
1408 gpmc_nand_data->ecc_opt = 1411 gpmc_nand_data->ecc_opt =
1409 OMAP_ECC_HAM1_CODE_HW; 1412 OMAP_ECC_HAM1_CODE_HW;
1410 else if (!strcmp(s, "bch4")) 1413 else if (!strcmp(s, "bch4"))
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index d42022f2a71e..53841dea80ea 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -663,7 +663,7 @@ void __init dra7xxx_check_revision(void)
663 663
664 default: 664 default:
665 /* Unknown default to latest silicon rev as default*/ 665 /* Unknown default to latest silicon rev as default*/
666 pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%d)\n", 666 pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%x)\n",
667 __func__, idcode, hawkeye, rev); 667 __func__, idcode, hawkeye, rev);
668 omap_revision = DRA752_REV_ES1_1; 668 omap_revision = DRA752_REV_ES1_1;
669 } 669 }
diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c
index 01ef59def44b..d22c30d3ccfa 100644
--- a/arch/arm/mach-omap2/omap_device.c
+++ b/arch/arm/mach-omap2/omap_device.c
@@ -56,7 +56,7 @@ static void _add_clkdev(struct omap_device *od, const char *clk_alias,
56 56
57 r = clk_get_sys(dev_name(&od->pdev->dev), clk_alias); 57 r = clk_get_sys(dev_name(&od->pdev->dev), clk_alias);
58 if (!IS_ERR(r)) { 58 if (!IS_ERR(r)) {
59 dev_warn(&od->pdev->dev, 59 dev_dbg(&od->pdev->dev,
60 "alias %s already exists\n", clk_alias); 60 "alias %s already exists\n", clk_alias);
61 clk_put(r); 61 clk_put(r);
62 return; 62 return;
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 6c074f37cdd2..8fd87a3055bf 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -2185,6 +2185,8 @@ static int _enable(struct omap_hwmod *oh)
2185 oh->mux->pads_dynamic))) { 2185 oh->mux->pads_dynamic))) {
2186 omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED); 2186 omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
2187 _reconfigure_io_chain(); 2187 _reconfigure_io_chain();
2188 } else if (oh->flags & HWMOD_FORCE_MSTANDBY) {
2189 _reconfigure_io_chain();
2188 } 2190 }
2189 2191
2190 _add_initiator_dep(oh, mpu_oh); 2192 _add_initiator_dep(oh, mpu_oh);
@@ -2291,6 +2293,8 @@ static int _idle(struct omap_hwmod *oh)
2291 if (oh->mux && oh->mux->pads_dynamic) { 2293 if (oh->mux && oh->mux->pads_dynamic) {
2292 omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE); 2294 omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE);
2293 _reconfigure_io_chain(); 2295 _reconfigure_io_chain();
2296 } else if (oh->flags & HWMOD_FORCE_MSTANDBY) {
2297 _reconfigure_io_chain();
2294 } 2298 }
2295 2299
2296 oh->_state = _HWMOD_STATE_IDLE; 2300 oh->_state = _HWMOD_STATE_IDLE;
@@ -3345,6 +3349,9 @@ int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois)
3345 if (!ois) 3349 if (!ois)
3346 return 0; 3350 return 0;
3347 3351
3352 if (ois[0] == NULL) /* Empty list */
3353 return 0;
3354
3348 if (!linkspace) { 3355 if (!linkspace) {
3349 if (_alloc_linkspace(ois)) { 3356 if (_alloc_linkspace(ois)) {
3350 pr_err("omap_hwmod: could not allocate link space\n"); 3357 pr_err("omap_hwmod: could not allocate link space\n");
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 2757abf87fbc..5684f112654b 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -35,6 +35,7 @@
35#include "i2c.h" 35#include "i2c.h"
36#include "mmc.h" 36#include "mmc.h"
37#include "wd_timer.h" 37#include "wd_timer.h"
38#include "soc.h"
38 39
39/* Base offset for all DRA7XX interrupts external to MPUSS */ 40/* Base offset for all DRA7XX interrupts external to MPUSS */
40#define DRA7XX_IRQ_GIC_START 32 41#define DRA7XX_IRQ_GIC_START 32
@@ -3261,7 +3262,6 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
3261 &dra7xx_l4_per3__usb_otg_ss1, 3262 &dra7xx_l4_per3__usb_otg_ss1,
3262 &dra7xx_l4_per3__usb_otg_ss2, 3263 &dra7xx_l4_per3__usb_otg_ss2,
3263 &dra7xx_l4_per3__usb_otg_ss3, 3264 &dra7xx_l4_per3__usb_otg_ss3,
3264 &dra7xx_l4_per3__usb_otg_ss4,
3265 &dra7xx_l3_main_1__vcp1, 3265 &dra7xx_l3_main_1__vcp1,
3266 &dra7xx_l4_per2__vcp1, 3266 &dra7xx_l4_per2__vcp1,
3267 &dra7xx_l3_main_1__vcp2, 3267 &dra7xx_l3_main_1__vcp2,
@@ -3270,8 +3270,26 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
3270 NULL, 3270 NULL,
3271}; 3271};
3272 3272
3273static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
3274 &dra7xx_l4_per3__usb_otg_ss4,
3275 NULL,
3276};
3277
3278static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
3279 NULL,
3280};
3281
3273int __init dra7xx_hwmod_init(void) 3282int __init dra7xx_hwmod_init(void)
3274{ 3283{
3284 int ret;
3285
3275 omap_hwmod_init(); 3286 omap_hwmod_init();
3276 return omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs); 3287 ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
3288
3289 if (!ret && soc_is_dra74x())
3290 return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
3291 else if (!ret && soc_is_dra72x())
3292 return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
3293
3294 return ret;
3277} 3295}
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index 01ca8086fb6c..4376f59626d1 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -245,6 +245,8 @@ IS_AM_SUBCLASS(437x, 0x437)
245#define soc_is_omap54xx() 0 245#define soc_is_omap54xx() 0
246#define soc_is_omap543x() 0 246#define soc_is_omap543x() 0
247#define soc_is_dra7xx() 0 247#define soc_is_dra7xx() 0
248#define soc_is_dra74x() 0
249#define soc_is_dra72x() 0
248 250
249#if defined(MULTI_OMAP2) 251#if defined(MULTI_OMAP2)
250# if defined(CONFIG_ARCH_OMAP2) 252# if defined(CONFIG_ARCH_OMAP2)
@@ -393,7 +395,11 @@ IS_OMAP_TYPE(3430, 0x3430)
393 395
394#if defined(CONFIG_SOC_DRA7XX) 396#if defined(CONFIG_SOC_DRA7XX)
395#undef soc_is_dra7xx 397#undef soc_is_dra7xx
398#undef soc_is_dra74x
399#undef soc_is_dra72x
396#define soc_is_dra7xx() (of_machine_is_compatible("ti,dra7")) 400#define soc_is_dra7xx() (of_machine_is_compatible("ti,dra7"))
401#define soc_is_dra74x() (of_machine_is_compatible("ti,dra74"))
402#define soc_is_dra72x() (of_machine_is_compatible("ti,dra72"))
397#endif 403#endif
398 404
399/* Various silicon revisions for omap2 */ 405/* Various silicon revisions for omap2 */
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index 17435c1aa2fe..126ddafad526 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -183,8 +183,8 @@ enum {
183 183
184static struct clk div4_clks[DIV4_NR] = { 184static struct clk div4_clks[DIV4_NR] = {
185 [DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT), 185 [DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
186 [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT), 186 [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1df0, CLK_ENABLE_ON_INIT),
187 [DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1de0, CLK_ENABLE_ON_INIT), 187 [DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1df0, CLK_ENABLE_ON_INIT),
188}; 188};
189 189
190/* DIV6 clocks */ 190/* DIV6 clocks */
diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c
index 10e193d707f5..453b23129cfa 100644
--- a/arch/arm/mach-shmobile/clock-r8a7791.c
+++ b/arch/arm/mach-shmobile/clock-r8a7791.c
@@ -152,7 +152,7 @@ enum {
152 152
153static struct clk div4_clks[DIV4_NR] = { 153static struct clk div4_clks[DIV4_NR] = {
154 [DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT), 154 [DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
155 [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT), 155 [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1df0, CLK_ENABLE_ON_INIT),
156}; 156};
157 157
158/* DIV6 clocks */ 158/* DIV6 clocks */
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index d8c4048b9e33..02a6f45a0b9e 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -644,7 +644,7 @@ static struct clk_lookup lookups[] = {
644 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */ 644 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
645 CLKDEV_DEV_ID("e6cb0000.serial", &mstp_clks[MSTP207]), /* SCIFA5 */ 645 CLKDEV_DEV_ID("e6cb0000.serial", &mstp_clks[MSTP207]), /* SCIFA5 */
646 CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */ 646 CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */
647 CLKDEV_DEV_ID("0xe6c3000.serial", &mstp_clks[MSTP206]), /* SCIFB */ 647 CLKDEV_DEV_ID("e6c3000.serial", &mstp_clks[MSTP206]), /* SCIFB */
648 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */ 648 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
649 CLKDEV_DEV_ID("e6c40000.serial", &mstp_clks[MSTP204]), /* SCIFA0 */ 649 CLKDEV_DEV_ID("e6c40000.serial", &mstp_clks[MSTP204]), /* SCIFA0 */
650 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */ 650 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
diff --git a/arch/arm/mach-vexpress/spc.c b/arch/arm/mach-vexpress/spc.c
index 2c2754e79cb3..f61158c6ce71 100644
--- a/arch/arm/mach-vexpress/spc.c
+++ b/arch/arm/mach-vexpress/spc.c
@@ -426,9 +426,15 @@ static int ve_spc_populate_opps(uint32_t cluster)
426 426
427static int ve_init_opp_table(struct device *cpu_dev) 427static int ve_init_opp_table(struct device *cpu_dev)
428{ 428{
429 int cluster = topology_physical_package_id(cpu_dev->id); 429 int cluster;
430 int idx, ret = 0, max_opp = info->num_opps[cluster]; 430 int idx, ret = 0, max_opp;
431 struct ve_spc_opp *opps = info->opps[cluster]; 431 struct ve_spc_opp *opps;
432
433 cluster = topology_physical_package_id(cpu_dev->id);
434 cluster = cluster < 0 ? 0 : cluster;
435
436 max_opp = info->num_opps[cluster];
437 opps = info->opps[cluster];
432 438
433 for (idx = 0; idx < max_opp; idx++, opps++) { 439 for (idx = 0; idx < max_opp; idx++, opps++) {
434 ret = dev_pm_opp_add(cpu_dev, opps->freq * 1000, opps->u_volt); 440 ret = dev_pm_opp_add(cpu_dev, opps->freq * 1000, opps->u_volt);
@@ -537,6 +543,8 @@ static struct clk *ve_spc_clk_register(struct device *cpu_dev)
537 spc->hw.init = &init; 543 spc->hw.init = &init;
538 spc->cluster = topology_physical_package_id(cpu_dev->id); 544 spc->cluster = topology_physical_package_id(cpu_dev->id);
539 545
546 spc->cluster = spc->cluster < 0 ? 0 : spc->cluster;
547
540 init.name = dev_name(cpu_dev); 548 init.name = dev_name(cpu_dev);
541 init.ops = &clk_spc_ops; 549 init.ops = &clk_spc_ops;
542 init.flags = CLK_IS_ROOT | CLK_GET_RATE_NOCACHE; 550 init.flags = CLK_IS_ROOT | CLK_GET_RATE_NOCACHE;
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index f0ed92e210a1..5967b385141b 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -931,7 +931,7 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
931 u32 val; 931 u32 val;
932 932
933 val = readl(info->reg.gpmc_ecc_config); 933 val = readl(info->reg.gpmc_ecc_config);
934 if (((val >> ECC_CONFIG_CS_SHIFT) & ~CS_MASK) != info->gpmc_cs) 934 if (((val >> ECC_CONFIG_CS_SHIFT) & CS_MASK) != info->gpmc_cs)
935 return -EINVAL; 935 return -EINVAL;
936 936
937 /* read ecc result */ 937 /* read ecc result */
@@ -1794,9 +1794,12 @@ static int omap_nand_probe(struct platform_device *pdev)
1794 } 1794 }
1795 1795
1796 /* populate MTD interface based on ECC scheme */ 1796 /* populate MTD interface based on ECC scheme */
1797 nand_chip->ecc.layout = &omap_oobinfo;
1798 ecclayout = &omap_oobinfo; 1797 ecclayout = &omap_oobinfo;
1799 switch (info->ecc_opt) { 1798 switch (info->ecc_opt) {
1799 case OMAP_ECC_HAM1_CODE_SW:
1800 nand_chip->ecc.mode = NAND_ECC_SOFT;
1801 break;
1802
1800 case OMAP_ECC_HAM1_CODE_HW: 1803 case OMAP_ECC_HAM1_CODE_HW:
1801 pr_info("nand: using OMAP_ECC_HAM1_CODE_HW\n"); 1804 pr_info("nand: using OMAP_ECC_HAM1_CODE_HW\n");
1802 nand_chip->ecc.mode = NAND_ECC_HW; 1805 nand_chip->ecc.mode = NAND_ECC_HW;
@@ -1848,7 +1851,7 @@ static int omap_nand_probe(struct platform_device *pdev)
1848 nand_chip->ecc.priv = nand_bch_init(mtd, 1851 nand_chip->ecc.priv = nand_bch_init(mtd,
1849 nand_chip->ecc.size, 1852 nand_chip->ecc.size,
1850 nand_chip->ecc.bytes, 1853 nand_chip->ecc.bytes,
1851 &nand_chip->ecc.layout); 1854 &ecclayout);
1852 if (!nand_chip->ecc.priv) { 1855 if (!nand_chip->ecc.priv) {
1853 pr_err("nand: error: unable to use s/w BCH library\n"); 1856 pr_err("nand: error: unable to use s/w BCH library\n");
1854 err = -EINVAL; 1857 err = -EINVAL;
@@ -1923,7 +1926,7 @@ static int omap_nand_probe(struct platform_device *pdev)
1923 nand_chip->ecc.priv = nand_bch_init(mtd, 1926 nand_chip->ecc.priv = nand_bch_init(mtd,
1924 nand_chip->ecc.size, 1927 nand_chip->ecc.size,
1925 nand_chip->ecc.bytes, 1928 nand_chip->ecc.bytes,
1926 &nand_chip->ecc.layout); 1929 &ecclayout);
1927 if (!nand_chip->ecc.priv) { 1930 if (!nand_chip->ecc.priv) {
1928 pr_err("nand: error: unable to use s/w BCH library\n"); 1931 pr_err("nand: error: unable to use s/w BCH library\n");
1929 err = -EINVAL; 1932 err = -EINVAL;
@@ -2012,6 +2015,9 @@ static int omap_nand_probe(struct platform_device *pdev)
2012 goto return_error; 2015 goto return_error;
2013 } 2016 }
2014 2017
2018 if (info->ecc_opt == OMAP_ECC_HAM1_CODE_SW)
2019 goto scan_tail;
2020
2015 /* all OOB bytes from oobfree->offset till end off OOB are free */ 2021 /* all OOB bytes from oobfree->offset till end off OOB are free */
2016 ecclayout->oobfree->length = mtd->oobsize - ecclayout->oobfree->offset; 2022 ecclayout->oobfree->length = mtd->oobsize - ecclayout->oobfree->offset;
2017 /* check if NAND device's OOB is enough to store ECC signatures */ 2023 /* check if NAND device's OOB is enough to store ECC signatures */
@@ -2021,7 +2027,9 @@ static int omap_nand_probe(struct platform_device *pdev)
2021 err = -EINVAL; 2027 err = -EINVAL;
2022 goto return_error; 2028 goto return_error;
2023 } 2029 }
2030 nand_chip->ecc.layout = ecclayout;
2024 2031
2032scan_tail:
2025 /* second phase scan */ 2033 /* second phase scan */
2026 if (nand_scan_tail(mtd)) { 2034 if (nand_scan_tail(mtd)) {
2027 err = -ENXIO; 2035 err = -ENXIO;
diff --git a/include/linux/platform_data/mtd-nand-omap2.h b/include/linux/platform_data/mtd-nand-omap2.h
index 660c029d694f..16ec262dfcc8 100644
--- a/include/linux/platform_data/mtd-nand-omap2.h
+++ b/include/linux/platform_data/mtd-nand-omap2.h
@@ -21,8 +21,17 @@ enum nand_io {
21}; 21};
22 22
23enum omap_ecc { 23enum omap_ecc {
24 /* 1-bit ECC calculation by GPMC, Error detection by Software */ 24 /*
25 OMAP_ECC_HAM1_CODE_HW = 0, 25 * 1-bit ECC: calculation and correction by SW
26 * ECC stored at end of spare area
27 */
28 OMAP_ECC_HAM1_CODE_SW = 0,
29
30 /*
31 * 1-bit ECC: calculation by GPMC, Error detection by Software
32 * ECC layout compatible with ROM code layout
33 */
34 OMAP_ECC_HAM1_CODE_HW,
26 /* 4-bit ECC calculation by GPMC, Error detection by Software */ 35 /* 4-bit ECC calculation by GPMC, Error detection by Software */
27 OMAP_ECC_BCH4_CODE_HW_DETECTION_SW, 36 OMAP_ECC_BCH4_CODE_HW_DETECTION_SW,
28 /* 4-bit ECC calculation by GPMC, Error detection by ELM */ 37 /* 4-bit ECC calculation by GPMC, Error detection by ELM */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-28 01:51:07 -0400