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-rw-r--r--Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c7
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_device.c43
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c15
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c3
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c3
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c5
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c10
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h3
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c5
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c8
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c9
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c27
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c15
-rw-r--r--drivers/gpu/drm/amd/include/amd_shared.h29
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c2
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c4
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c2
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c27
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h1
-rw-r--r--drivers/gpu/drm/drm_connector.c17
-rw-r--r--drivers/gpu/drm/drm_edid.c11
-rw-r--r--drivers/gpu/drm/drm_fb_helper.c6
-rw-r--r--drivers/gpu/drm/drm_framebuffer.c1
-rw-r--r--drivers/gpu/drm/drm_mode_object.c1
-rw-r--r--drivers/gpu/drm/drm_modeset_lock.c2
-rw-r--r--drivers/gpu/drm/drm_plane.c1
-rw-r--r--drivers/gpu/drm/drm_vblank.c4
-rw-r--r--drivers/gpu/drm/exynos/Kconfig1
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_crtc.c15
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_drv.h3
-rw-r--r--drivers/gpu/drm/exynos/exynos_hdmi.c310
-rw-r--r--drivers/gpu/drm/exynos/exynos_mixer.c460
-rw-r--r--drivers/gpu/drm/exynos/regs-hdmi.h8
-rw-r--r--drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c3
-rw-r--r--drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c5
-rw-r--r--drivers/gpu/drm/imx/ipuv3-crtc.c2
-rw-r--r--drivers/gpu/drm/imx/parallel-display.c2
-rw-r--r--drivers/gpu/drm/qxl/qxl_cmd.c22
-rw-r--r--drivers/gpu/drm/qxl/qxl_display.c49
-rw-r--r--drivers/gpu/drm/qxl/qxl_drv.h28
-rw-r--r--drivers/gpu/drm/qxl/qxl_dumb.c1
-rw-r--r--drivers/gpu/drm/qxl/qxl_fb.c13
-rw-r--r--drivers/gpu/drm/qxl/qxl_release.c5
-rw-r--r--drivers/gpu/drm/qxl/qxl_ttm.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_fb.c1
-rw-r--r--drivers/gpu/drm/rockchip/Kconfig2
-rw-r--r--drivers/gpu/drm/rockchip/analogix_dp-rockchip.c14
-rw-r--r--drivers/gpu/drm/tegra/sor.c157
-rw-r--r--drivers/gpu/drm/tilcdc/Kconfig11
-rw-r--r--drivers/gpu/drm/tilcdc/Makefile3
-rw-r--r--drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c269
-rw-r--r--drivers/gpu/drm/tilcdc/tilcdc_slave_compat.dts72
-rw-r--r--drivers/gpu/drm/tilcdc/tilcdc_slave_compat.h25
-rw-r--r--drivers/gpu/drm/ttm/ttm_page_alloc.c36
-rw-r--r--drivers/gpu/drm/vc4/vc4_bo.c4
-rw-r--r--drivers/gpu/ipu-v3/ipu-dc.c3
-rw-r--r--include/drm/amd_asic_type.h52
-rw-r--r--include/drm/drm_connector.h6
-rw-r--r--include/drm/drm_crtc.h1
-rw-r--r--include/drm/drm_encoder.h1
-rw-r--r--include/drm/drm_mode_config.h7
-rw-r--r--include/drm/drm_plane.h1
-rw-r--r--include/drm/drm_property.h3
-rw-r--r--include/dt-bindings/msm/msm-bus-ids.h887
-rw-r--r--sound/soc/amd/acp-pcm-dma.c8
-rw-r--r--sound/soc/amd/acp.h7
75 files changed, 947 insertions, 1847 deletions
diff --git a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt
index f79854783c2c..5bf77f6dd19d 100644
--- a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt
+++ b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt
@@ -129,7 +129,7 @@ Optional properties:
129 129
130example: 130example:
131 131
132display@di0 { 132disp0 {
133 compatible = "fsl,imx-parallel-display"; 133 compatible = "fsl,imx-parallel-display";
134 edid = [edid-data]; 134 edid = [edid-data];
135 interface-pix-fmt = "rgb24"; 135 interface-pix-fmt = "rgb24";
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index 023bfdb3e63f..c04f44a90392 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -382,6 +382,8 @@ static int acp_hw_init(void *handle)
382 adev->acp.acp_cell[0].name = "acp_audio_dma"; 382 adev->acp.acp_cell[0].name = "acp_audio_dma";
383 adev->acp.acp_cell[0].num_resources = 4; 383 adev->acp.acp_cell[0].num_resources = 4;
384 adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0]; 384 adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0];
385 adev->acp.acp_cell[0].platform_data = &adev->asic_type;
386 adev->acp.acp_cell[0].pdata_size = sizeof(adev->asic_type);
385 387
386 adev->acp.acp_cell[1].name = "designware-i2s"; 388 adev->acp.acp_cell[1].name = "designware-i2s";
387 adev->acp.acp_cell[1].num_resources = 1; 389 adev->acp.acp_cell[1].num_resources = 1;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
index c21adf60a7f2..057e1ecd83ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
@@ -59,12 +59,6 @@ static bool check_atom_bios(uint8_t *bios, size_t size)
59 return false; 59 return false;
60 } 60 }
61 61
62 tmp = bios[0x18] | (bios[0x19] << 8);
63 if (bios[tmp + 0x14] != 0x0) {
64 DRM_INFO("Not an x86 BIOS ROM\n");
65 return false;
66 }
67
68 bios_header_start = bios[0x48] | (bios[0x49] << 8); 62 bios_header_start = bios[0x48] | (bios[0x49] << 8);
69 if (!bios_header_start) { 63 if (!bios_header_start) {
70 DRM_INFO("Can't locate bios header\n"); 64 DRM_INFO("Can't locate bios header\n");
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index f7fceb63413c..bdef497a6a26 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1497,8 +1497,11 @@ out:
1497 memset(wait, 0, sizeof(*wait)); 1497 memset(wait, 0, sizeof(*wait));
1498 wait->out.status = (r > 0); 1498 wait->out.status = (r > 0);
1499 wait->out.first_signaled = first; 1499 wait->out.first_signaled = first;
1500 /* set return value 0 to indicate success */ 1500
1501 r = array[first]->error; 1501 if (first < fence_count && array[first])
1502 r = array[first]->error;
1503 else
1504 r = 0;
1502 1505
1503err_free_fence_array: 1506err_free_fence_array:
1504 for (i = 0; i < fence_count; i++) 1507 for (i = 0; i < fence_count; i++)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index efcacb827de7..2c85e0a98608 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1836,6 +1836,9 @@ static int amdgpu_fini(struct amdgpu_device *adev)
1836 adev->ip_blocks[i].status.hw = false; 1836 adev->ip_blocks[i].status.hw = false;
1837 } 1837 }
1838 1838
1839 if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
1840 amdgpu_ucode_fini_bo(adev);
1841
1839 for (i = adev->num_ip_blocks - 1; i >= 0; i--) { 1842 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1840 if (!adev->ip_blocks[i].status.sw) 1843 if (!adev->ip_blocks[i].status.sw)
1841 continue; 1844 continue;
@@ -3188,9 +3191,9 @@ static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
3188 pm_pg_lock = (*pos >> 23) & 1; 3191 pm_pg_lock = (*pos >> 23) & 1;
3189 3192
3190 if (*pos & (1ULL << 62)) { 3193 if (*pos & (1ULL << 62)) {
3191 se_bank = (*pos >> 24) & 0x3FF; 3194 se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;
3192 sh_bank = (*pos >> 34) & 0x3FF; 3195 sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;
3193 instance_bank = (*pos >> 44) & 0x3FF; 3196 instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;
3194 3197
3195 if (se_bank == 0x3FF) 3198 if (se_bank == 0x3FF)
3196 se_bank = 0xFFFFFFFF; 3199 se_bank = 0xFFFFFFFF;
@@ -3264,9 +3267,9 @@ static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
3264 pm_pg_lock = (*pos >> 23) & 1; 3267 pm_pg_lock = (*pos >> 23) & 1;
3265 3268
3266 if (*pos & (1ULL << 62)) { 3269 if (*pos & (1ULL << 62)) {
3267 se_bank = (*pos >> 24) & 0x3FF; 3270 se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;
3268 sh_bank = (*pos >> 34) & 0x3FF; 3271 sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;
3269 instance_bank = (*pos >> 44) & 0x3FF; 3272 instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;
3270 3273
3271 if (se_bank == 0x3FF) 3274 if (se_bank == 0x3FF)
3272 se_bank = 0xFFFFFFFF; 3275 se_bank = 0xFFFFFFFF;
@@ -3614,12 +3617,12 @@ static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
3614 return -EINVAL; 3617 return -EINVAL;
3615 3618
3616 /* decode offset */ 3619 /* decode offset */
3617 offset = (*pos & 0x7F); 3620 offset = (*pos & GENMASK_ULL(6, 0));
3618 se = ((*pos >> 7) & 0xFF); 3621 se = (*pos & GENMASK_ULL(14, 7)) >> 7;
3619 sh = ((*pos >> 15) & 0xFF); 3622 sh = (*pos & GENMASK_ULL(22, 15)) >> 15;
3620 cu = ((*pos >> 23) & 0xFF); 3623 cu = (*pos & GENMASK_ULL(30, 23)) >> 23;
3621 wave = ((*pos >> 31) & 0xFF); 3624 wave = (*pos & GENMASK_ULL(36, 31)) >> 31;
3622 simd = ((*pos >> 37) & 0xFF); 3625 simd = (*pos & GENMASK_ULL(44, 37)) >> 37;
3623 3626
3624 /* switch to the specific se/sh/cu */ 3627 /* switch to the specific se/sh/cu */
3625 mutex_lock(&adev->grbm_idx_mutex); 3628 mutex_lock(&adev->grbm_idx_mutex);
@@ -3664,14 +3667,14 @@ static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,
3664 return -EINVAL; 3667 return -EINVAL;
3665 3668
3666 /* decode offset */ 3669 /* decode offset */
3667 offset = (*pos & 0xFFF); /* in dwords */ 3670 offset = *pos & GENMASK_ULL(11, 0);
3668 se = ((*pos >> 12) & 0xFF); 3671 se = (*pos & GENMASK_ULL(19, 12)) >> 12;
3669 sh = ((*pos >> 20) & 0xFF); 3672 sh = (*pos & GENMASK_ULL(27, 20)) >> 20;
3670 cu = ((*pos >> 28) & 0xFF); 3673 cu = (*pos & GENMASK_ULL(35, 28)) >> 28;
3671 wave = ((*pos >> 36) & 0xFF); 3674 wave = (*pos & GENMASK_ULL(43, 36)) >> 36;
3672 simd = ((*pos >> 44) & 0xFF); 3675 simd = (*pos & GENMASK_ULL(51, 44)) >> 44;
3673 thread = ((*pos >> 52) & 0xFF); 3676 thread = (*pos & GENMASK_ULL(59, 52)) >> 52;
3674 bank = ((*pos >> 60) & 1); 3677 bank = (*pos & GENMASK_ULL(61, 60)) >> 60;
3675 3678
3676 data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL); 3679 data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL);
3677 if (!data) 3680 if (!data)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index fb72edc4c026..14aff2f15a94 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -63,6 +63,11 @@ retry:
63 flags, NULL, resv, 0, &bo); 63 flags, NULL, resv, 0, &bo);
64 if (r) { 64 if (r) {
65 if (r != -ERESTARTSYS) { 65 if (r != -ERESTARTSYS) {
66 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
67 flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
68 goto retry;
69 }
70
66 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) { 71 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
67 initial_domain |= AMDGPU_GEM_DOMAIN_GTT; 72 initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
68 goto retry; 73 goto retry;
@@ -323,7 +328,7 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
323 r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm, 328 r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm,
324 bo->tbo.ttm->pages); 329 bo->tbo.ttm->pages);
325 if (r) 330 if (r)
326 goto unlock_mmap_sem; 331 goto release_object;
327 332
328 r = amdgpu_bo_reserve(bo, true); 333 r = amdgpu_bo_reserve(bo, true);
329 if (r) 334 if (r)
@@ -348,9 +353,6 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
348free_pages: 353free_pages:
349 release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages, false); 354 release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages, false);
350 355
351unlock_mmap_sem:
352 up_read(&current->mm->mmap_sem);
353
354release_object: 356release_object:
355 drm_gem_object_put_unlocked(gobj); 357 drm_gem_object_put_unlocked(gobj);
356 358
@@ -556,9 +558,8 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
556 558
557 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) { 559 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
558 dev_err(&dev->pdev->dev, 560 dev_err(&dev->pdev->dev,
559 "va_address 0x%lX is in reserved area 0x%X\n", 561 "va_address 0x%LX is in reserved area 0x%LX\n",
560 (unsigned long)args->va_address, 562 args->va_address, AMDGPU_VA_RESERVED_SIZE);
561 AMDGPU_VA_RESERVED_SIZE);
562 return -EINVAL; 563 return -EINVAL;
563 } 564 }
564 565
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
index 33535d347734..00e0ce10862f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
@@ -71,12 +71,6 @@ static int amdgpu_gtt_mgr_fini(struct ttm_mem_type_manager *man)
71{ 71{
72 struct amdgpu_gtt_mgr *mgr = man->priv; 72 struct amdgpu_gtt_mgr *mgr = man->priv;
73 73
74 spin_lock(&mgr->lock);
75 if (!drm_mm_clean(&mgr->mm)) {
76 spin_unlock(&mgr->lock);
77 return -EBUSY;
78 }
79
80 drm_mm_takedown(&mgr->mm); 74 drm_mm_takedown(&mgr->mm);
81 spin_unlock(&mgr->lock); 75 spin_unlock(&mgr->lock);
82 kfree(mgr); 76 kfree(mgr);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index a59e04f3eeba..ce00f629dcce 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -946,6 +946,10 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
946 struct amdgpu_device *adev = dev_get_drvdata(dev); 946 struct amdgpu_device *adev = dev_get_drvdata(dev);
947 umode_t effective_mode = attr->mode; 947 umode_t effective_mode = attr->mode;
948 948
949 /* no skipping for powerplay */
950 if (adev->powerplay.cgs_device)
951 return effective_mode;
952
949 /* Skip limit attributes if DPM is not enabled */ 953 /* Skip limit attributes if DPM is not enabled */
950 if (!adev->pm.dpm_enabled && 954 if (!adev->pm.dpm_enabled &&
951 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || 955 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
index 5f5aa5fddc16..033fba2def6f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
@@ -164,9 +164,6 @@ static int amdgpu_pp_hw_fini(void *handle)
164 ret = adev->powerplay.ip_funcs->hw_fini( 164 ret = adev->powerplay.ip_funcs->hw_fini(
165 adev->powerplay.pp_handle); 165 adev->powerplay.pp_handle);
166 166
167 if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
168 amdgpu_ucode_fini_bo(adev);
169
170 return ret; 167 return ret;
171} 168}
172 169
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
index 90af8e82b16a..ae9c106979d7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
@@ -169,10 +169,14 @@ struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
169 int flags) 169 int flags)
170{ 170{
171 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); 171 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
172 struct dma_buf *buf;
172 173
173 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) || 174 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) ||
174 bo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) 175 bo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
175 return ERR_PTR(-EPERM); 176 return ERR_PTR(-EPERM);
176 177
177 return drm_gem_prime_export(dev, gobj, flags); 178 buf = drm_gem_prime_export(dev, gobj, flags);
179 if (!IS_ERR(buf))
180 buf->file->f_mapping = dev->anon_inode->i_mapping;
181 return buf;
178} 182}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 447d446b5015..7714f4a6c8b0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -442,8 +442,6 @@ static int psp_hw_fini(void *handle)
442 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 442 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
443 return 0; 443 return 0;
444 444
445 amdgpu_ucode_fini_bo(adev);
446
447 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 445 psp_ring_destroy(psp, PSP_RING_TYPE__KM);
448 446
449 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf); 447 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index e5ece1fae149..a98fbbb4739f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -136,7 +136,8 @@ void amdgpu_ring_commit(struct amdgpu_ring *ring)
136 if (ring->funcs->end_use) 136 if (ring->funcs->end_use)
137 ring->funcs->end_use(ring); 137 ring->funcs->end_use(ring);
138 138
139 amdgpu_ring_lru_touch(ring->adev, ring); 139 if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ)
140 amdgpu_ring_lru_touch(ring->adev, ring);
140} 141}
141 142
142/** 143/**
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index b577b717caa0..1f036af85ba6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1193,9 +1193,6 @@ static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1193 unsigned long num_pages = bo->mem.num_pages; 1193 unsigned long num_pages = bo->mem.num_pages;
1194 struct drm_mm_node *node = bo->mem.mm_node; 1194 struct drm_mm_node *node = bo->mem.mm_node;
1195 1195
1196 if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1197 return ttm_bo_eviction_valuable(bo, place);
1198
1199 switch (bo->mem.mem_type) { 1196 switch (bo->mem.mem_type) {
1200 case TTM_PL_TT: 1197 case TTM_PL_TT:
1201 return true; 1198 return true;
@@ -1210,7 +1207,7 @@ static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1210 num_pages -= node->size; 1207 num_pages -= node->size;
1211 ++node; 1208 ++node;
1212 } 1209 }
1213 break; 1210 return false;
1214 1211
1215 default: 1212 default:
1216 break; 1213 break;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index b46280c1279f..2918de2f39ec 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -648,7 +648,7 @@ int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
648 uint32_t allocated = 0; 648 uint32_t allocated = 0;
649 uint32_t tmp, handle = 0; 649 uint32_t tmp, handle = 0;
650 uint32_t *size = &tmp; 650 uint32_t *size = &tmp;
651 int i, r, idx = 0; 651 int i, r = 0, idx = 0;
652 652
653 p->job->vm = NULL; 653 p->job->vm = NULL;
654 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); 654 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 4e4a476593e8..6738df836a70 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -114,18 +114,19 @@ void amdgpu_virt_init_setting(struct amdgpu_device *adev)
114uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg) 114uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
115{ 115{
116 signed long r; 116 signed long r;
117 unsigned long flags;
117 uint32_t val, seq; 118 uint32_t val, seq;
118 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 119 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
119 struct amdgpu_ring *ring = &kiq->ring; 120 struct amdgpu_ring *ring = &kiq->ring;
120 121
121 BUG_ON(!ring->funcs->emit_rreg); 122 BUG_ON(!ring->funcs->emit_rreg);
122 123
123 spin_lock(&kiq->ring_lock); 124 spin_lock_irqsave(&kiq->ring_lock, flags);
124 amdgpu_ring_alloc(ring, 32); 125 amdgpu_ring_alloc(ring, 32);
125 amdgpu_ring_emit_rreg(ring, reg); 126 amdgpu_ring_emit_rreg(ring, reg);
126 amdgpu_fence_emit_polling(ring, &seq); 127 amdgpu_fence_emit_polling(ring, &seq);
127 amdgpu_ring_commit(ring); 128 amdgpu_ring_commit(ring);
128 spin_unlock(&kiq->ring_lock); 129 spin_unlock_irqrestore(&kiq->ring_lock, flags);
129 130
130 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 131 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
131 if (r < 1) { 132 if (r < 1) {
@@ -140,18 +141,19 @@ uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
140void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) 141void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
141{ 142{
142 signed long r; 143 signed long r;
144 unsigned long flags;
143 uint32_t seq; 145 uint32_t seq;
144 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 146 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
145 struct amdgpu_ring *ring = &kiq->ring; 147 struct amdgpu_ring *ring = &kiq->ring;
146 148
147 BUG_ON(!ring->funcs->emit_wreg); 149 BUG_ON(!ring->funcs->emit_wreg);
148 150
149 spin_lock(&kiq->ring_lock); 151 spin_lock_irqsave(&kiq->ring_lock, flags);
150 amdgpu_ring_alloc(ring, 32); 152 amdgpu_ring_alloc(ring, 32);
151 amdgpu_ring_emit_wreg(ring, reg, v); 153 amdgpu_ring_emit_wreg(ring, reg, v);
152 amdgpu_fence_emit_polling(ring, &seq); 154 amdgpu_fence_emit_polling(ring, &seq);
153 amdgpu_ring_commit(ring); 155 amdgpu_ring_commit(ring);
154 spin_unlock(&kiq->ring_lock); 156 spin_unlock_irqrestore(&kiq->ring_lock, flags);
155 157
156 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 158 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
157 if (r < 1) 159 if (r < 1)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 010d14195a5e..c8c26f21993c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1244,7 +1244,7 @@ static void amdgpu_vm_invalidate_level(struct amdgpu_vm *vm,
1244int amdgpu_vm_update_directories(struct amdgpu_device *adev, 1244int amdgpu_vm_update_directories(struct amdgpu_device *adev,
1245 struct amdgpu_vm *vm) 1245 struct amdgpu_vm *vm)
1246{ 1246{
1247 int r; 1247 int r = 0;
1248 1248
1249 spin_lock(&vm->status_lock); 1249 spin_lock(&vm->status_lock);
1250 while (!list_empty(&vm->relocated)) { 1250 while (!list_empty(&vm->relocated)) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index aa914256b4bc..bae77353447b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -94,7 +94,8 @@ struct amdgpu_bo_list_entry;
94#define AMDGPU_MMHUB 1 94#define AMDGPU_MMHUB 1
95 95
96/* hardcode that limit for now */ 96/* hardcode that limit for now */
97#define AMDGPU_VA_RESERVED_SIZE (8 << 20) 97#define AMDGPU_VA_RESERVED_SIZE (8ULL << 20)
98
98/* max vmids dedicated for process */ 99/* max vmids dedicated for process */
99#define AMDGPU_VM_MAX_RESERVED_VMID 1 100#define AMDGPU_VM_MAX_RESERVED_VMID 1
100 101
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
index 26e900627971..4acca92f6a52 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
@@ -68,11 +68,6 @@ static int amdgpu_vram_mgr_fini(struct ttm_mem_type_manager *man)
68 struct amdgpu_vram_mgr *mgr = man->priv; 68 struct amdgpu_vram_mgr *mgr = man->priv;
69 69
70 spin_lock(&mgr->lock); 70 spin_lock(&mgr->lock);
71 if (!drm_mm_clean(&mgr->mm)) {
72 spin_unlock(&mgr->lock);
73 return -EBUSY;
74 }
75
76 drm_mm_takedown(&mgr->mm); 71 drm_mm_takedown(&mgr->mm);
77 spin_unlock(&mgr->lock); 72 spin_unlock(&mgr->lock);
78 kfree(mgr); 73 kfree(mgr);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 00868764a0dd..5c8a7a48a4ad 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -4670,6 +4670,14 @@ static int gfx_v7_0_sw_fini(void *handle)
4670 gfx_v7_0_cp_compute_fini(adev); 4670 gfx_v7_0_cp_compute_fini(adev);
4671 gfx_v7_0_rlc_fini(adev); 4671 gfx_v7_0_rlc_fini(adev);
4672 gfx_v7_0_mec_fini(adev); 4672 gfx_v7_0_mec_fini(adev);
4673 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4674 &adev->gfx.rlc.clear_state_gpu_addr,
4675 (void **)&adev->gfx.rlc.cs_ptr);
4676 if (adev->gfx.rlc.cp_table_size) {
4677 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4678 &adev->gfx.rlc.cp_table_gpu_addr,
4679 (void **)&adev->gfx.rlc.cp_table_ptr);
4680 }
4673 gfx_v7_0_free_microcode(adev); 4681 gfx_v7_0_free_microcode(adev);
4674 4682
4675 return 0; 4683 return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index b8002ac3e536..9ecdf621a74a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -2118,6 +2118,15 @@ static int gfx_v8_0_sw_fini(void *handle)
2118 2118
2119 gfx_v8_0_mec_fini(adev); 2119 gfx_v8_0_mec_fini(adev);
2120 gfx_v8_0_rlc_fini(adev); 2120 gfx_v8_0_rlc_fini(adev);
2121 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
2122 &adev->gfx.rlc.clear_state_gpu_addr,
2123 (void **)&adev->gfx.rlc.cs_ptr);
2124 if ((adev->asic_type == CHIP_CARRIZO) ||
2125 (adev->asic_type == CHIP_STONEY)) {
2126 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
2127 &adev->gfx.rlc.cp_table_gpu_addr,
2128 (void **)&adev->gfx.rlc.cp_table_ptr);
2129 }
2121 gfx_v8_0_free_microcode(adev); 2130 gfx_v8_0_free_microcode(adev);
2122 2131
2123 return 0; 2132 return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 7f15bb2c5233..da43813d67a4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -207,6 +207,12 @@ static const u32 golden_settings_gc_9_1_rv1[] =
207 SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x01bd9f33, 0x00000800 207 SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x01bd9f33, 0x00000800
208}; 208};
209 209
210static const u32 golden_settings_gc_9_x_common[] =
211{
212 SOC15_REG_OFFSET(GC, 0, mmGRBM_CAM_INDEX), 0xffffffff, 0x00000000,
213 SOC15_REG_OFFSET(GC, 0, mmGRBM_CAM_DATA), 0xffffffff, 0x2544c382
214};
215
210#define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042 216#define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
211#define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042 217#define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
212 218
@@ -242,6 +248,9 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
242 default: 248 default:
243 break; 249 break;
244 } 250 }
251
252 amdgpu_program_register_sequence(adev, golden_settings_gc_9_x_common,
253 (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));
245} 254}
246 255
247static void gfx_v9_0_scratch_init(struct amdgpu_device *adev) 256static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
@@ -988,12 +997,22 @@ static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
988 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 997 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
989} 998}
990 999
1000static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
1001 uint32_t wave, uint32_t thread,
1002 uint32_t start, uint32_t size,
1003 uint32_t *dst)
1004{
1005 wave_read_regs(
1006 adev, simd, wave, thread,
1007 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
1008}
991 1009
992static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = { 1010static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
993 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter, 1011 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
994 .select_se_sh = &gfx_v9_0_select_se_sh, 1012 .select_se_sh = &gfx_v9_0_select_se_sh,
995 .read_wave_data = &gfx_v9_0_read_wave_data, 1013 .read_wave_data = &gfx_v9_0_read_wave_data,
996 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs, 1014 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
1015 .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs,
997}; 1016};
998 1017
999static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev) 1018static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
@@ -1449,6 +1468,14 @@ static int gfx_v9_0_sw_fini(void *handle)
1449 1468
1450 gfx_v9_0_mec_fini(adev); 1469 gfx_v9_0_mec_fini(adev);
1451 gfx_v9_0_ngg_fini(adev); 1470 gfx_v9_0_ngg_fini(adev);
1471 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
1472 &adev->gfx.rlc.clear_state_gpu_addr,
1473 (void **)&adev->gfx.rlc.cs_ptr);
1474 if (adev->asic_type == CHIP_RAVEN) {
1475 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
1476 &adev->gfx.rlc.cp_table_gpu_addr,
1477 (void **)&adev->gfx.rlc.cp_table_ptr);
1478 }
1452 gfx_v9_0_free_microcode(adev); 1479 gfx_v9_0_free_microcode(adev);
1453 1480
1454 return 0; 1481 return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 621699331e09..c8f1aebeac7a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -392,7 +392,16 @@ static int gmc_v9_0_early_init(void *handle)
392static int gmc_v9_0_late_init(void *handle) 392static int gmc_v9_0_late_init(void *handle)
393{ 393{
394 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 394 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
395 unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 3, 3 }; 395 /*
396 * The latest engine allocation on gfx9 is:
397 * Engine 0, 1: idle
398 * Engine 2, 3: firmware
399 * Engine 4~13: amdgpu ring, subject to change when ring number changes
400 * Engine 14~15: idle
401 * Engine 16: kfd tlb invalidation
402 * Engine 17: Gart flushes
403 */
404 unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 4, 4 };
396 unsigned i; 405 unsigned i;
397 406
398 for(i = 0; i < adev->num_rings; ++i) { 407 for(i = 0; i < adev->num_rings; ++i) {
@@ -405,9 +414,9 @@ static int gmc_v9_0_late_init(void *handle)
405 ring->funcs->vmhub); 414 ring->funcs->vmhub);
406 } 415 }
407 416
408 /* Engine 17 is used for GART flushes */ 417 /* Engine 16 is used for KFD and 17 for GART flushes */
409 for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i) 418 for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i)
410 BUG_ON(vm_inv_eng[i] > 17); 419 BUG_ON(vm_inv_eng[i] > 16);
411 420
412 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0); 421 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
413} 422}
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
index de6fc2731b98..b72f8a43d86b 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -23,36 +23,11 @@
23#ifndef __AMD_SHARED_H__ 23#ifndef __AMD_SHARED_H__
24#define __AMD_SHARED_H__ 24#define __AMD_SHARED_H__
25 25
26#define AMD_MAX_USEC_TIMEOUT 200000 /* 200 ms */ 26#include <drm/amd_asic_type.h>
27 27
28struct seq_file; 28struct seq_file;
29 29
30/* 30#define AMD_MAX_USEC_TIMEOUT 200000 /* 200 ms */
31 * Supported ASIC types
32 */
33enum amd_asic_type {
34 CHIP_TAHITI = 0,
35 CHIP_PITCAIRN,
36 CHIP_VERDE,
37 CHIP_OLAND,
38 CHIP_HAINAN,
39 CHIP_BONAIRE,
40 CHIP_KAVERI,
41 CHIP_KABINI,
42 CHIP_HAWAII,
43 CHIP_MULLINS,
44 CHIP_TOPAZ,
45 CHIP_TONGA,
46 CHIP_FIJI,
47 CHIP_CARRIZO,
48 CHIP_STONEY,
49 CHIP_POLARIS10,
50 CHIP_POLARIS11,
51 CHIP_POLARIS12,
52 CHIP_VEGA10,
53 CHIP_RAVEN,
54 CHIP_LAST,
55};
56 31
57/* 32/*
58 * Chip flags 33 * Chip flags
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
index a129bc5b1844..c6febbf0bf69 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
@@ -1486,7 +1486,7 @@ int atomctrl_get_leakage_vddc_base_on_leakage(struct pp_hwmgr *hwmgr,
1486 if (vddci_id_buf[i] == virtual_voltage_id) { 1486 if (vddci_id_buf[i] == virtual_voltage_id) {
1487 for (j = 0; j < profile->ucLeakageBinNum; j++) { 1487 for (j = 0; j < profile->ucLeakageBinNum; j++) {
1488 if (efuse_voltage_id <= leakage_bin[j]) { 1488 if (efuse_voltage_id <= leakage_bin[j]) {
1489 *vddci = vddci_buf[j * profile->ucElbVDDC_Num + i]; 1489 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
1490 break; 1490 break;
1491 } 1491 }
1492 } 1492 }
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
index d1af1483c69b..a651ebcf44fd 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
@@ -830,9 +830,9 @@ static int init_over_drive_limits(
830 const ATOM_Tonga_POWERPLAYTABLE *powerplay_table) 830 const ATOM_Tonga_POWERPLAYTABLE *powerplay_table)
831{ 831{
832 hwmgr->platform_descriptor.overdriveLimit.engineClock = 832 hwmgr->platform_descriptor.overdriveLimit.engineClock =
833 le16_to_cpu(powerplay_table->ulMaxODEngineClock); 833 le32_to_cpu(powerplay_table->ulMaxODEngineClock);
834 hwmgr->platform_descriptor.overdriveLimit.memoryClock = 834 hwmgr->platform_descriptor.overdriveLimit.memoryClock =
835 le16_to_cpu(powerplay_table->ulMaxODMemoryClock); 835 le32_to_cpu(powerplay_table->ulMaxODMemoryClock);
836 836
837 hwmgr->platform_descriptor.minOverdriveVDDC = 0; 837 hwmgr->platform_descriptor.minOverdriveVDDC = 0;
838 hwmgr->platform_descriptor.maxOverdriveVDDC = 0; 838 hwmgr->platform_descriptor.maxOverdriveVDDC = 0;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 4466469cf8ab..e33ec7fc5d09 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -3778,7 +3778,7 @@ static int smu7_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
3778 "Trying to Unfreeze MCLK DPM when DPM is disabled", 3778 "Trying to Unfreeze MCLK DPM when DPM is disabled",
3779 ); 3779 );
3780 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr, 3780 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
3781 PPSMC_MSG_SCLKDPM_UnfreezeLevel), 3781 PPSMC_MSG_MCLKDPM_UnfreezeLevel),
3782 "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!", 3782 "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
3783 return -EINVAL); 3783 return -EINVAL);
3784 } 3784 }
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 4239b98cf6db..f8d838c2c8ee 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -753,6 +753,7 @@ static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
753 uint32_t config_telemetry = 0; 753 uint32_t config_telemetry = 0;
754 struct pp_atomfwctrl_voltage_table vol_table; 754 struct pp_atomfwctrl_voltage_table vol_table;
755 struct cgs_system_info sys_info = {0}; 755 struct cgs_system_info sys_info = {0};
756 uint32_t reg;
756 757
757 data = kzalloc(sizeof(struct vega10_hwmgr), GFP_KERNEL); 758 data = kzalloc(sizeof(struct vega10_hwmgr), GFP_KERNEL);
758 if (data == NULL) 759 if (data == NULL)
@@ -859,6 +860,16 @@ static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
859 advanceFanControlParameters.usFanPWMMinLimit * 860 advanceFanControlParameters.usFanPWMMinLimit *
860 hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100; 861 hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100;
861 862
863 reg = soc15_get_register_offset(DF_HWID, 0,
864 mmDF_CS_AON0_DramBaseAddress0_BASE_IDX,
865 mmDF_CS_AON0_DramBaseAddress0);
866 data->mem_channels = (cgs_read_register(hwmgr->device, reg) &
867 DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK) >>
868 DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
869 PP_ASSERT_WITH_CODE(data->mem_channels < ARRAY_SIZE(channel_number),
870 "Mem Channel Index Exceeded maximum!",
871 return -EINVAL);
872
862 return result; 873 return result;
863} 874}
864 875
@@ -1777,7 +1788,7 @@ static int vega10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1777 struct vega10_single_dpm_table *dpm_table = 1788 struct vega10_single_dpm_table *dpm_table =
1778 &(data->dpm_table.mem_table); 1789 &(data->dpm_table.mem_table);
1779 int result = 0; 1790 int result = 0;
1780 uint32_t i, j, reg, mem_channels; 1791 uint32_t i, j;
1781 1792
1782 for (i = 0; i < dpm_table->count; i++) { 1793 for (i = 0; i < dpm_table->count; i++) {
1783 result = vega10_populate_single_memory_level(hwmgr, 1794 result = vega10_populate_single_memory_level(hwmgr,
@@ -1801,16 +1812,10 @@ static int vega10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1801 i++; 1812 i++;
1802 } 1813 }
1803 1814
1804 reg = soc15_get_register_offset(DF_HWID, 0, 1815 pp_table->NumMemoryChannels = (uint16_t)(data->mem_channels);
1805 mmDF_CS_AON0_DramBaseAddress0_BASE_IDX,
1806 mmDF_CS_AON0_DramBaseAddress0);
1807 mem_channels = (cgs_read_register(hwmgr->device, reg) &
1808 DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK) >>
1809 DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
1810 pp_table->NumMemoryChannels = cpu_to_le16(mem_channels);
1811 pp_table->MemoryChannelWidth = 1816 pp_table->MemoryChannelWidth =
1812 cpu_to_le16(HBM_MEMORY_CHANNEL_WIDTH * 1817 (uint16_t)(HBM_MEMORY_CHANNEL_WIDTH *
1813 channel_number[mem_channels]); 1818 channel_number[data->mem_channels]);
1814 1819
1815 pp_table->LowestUclkReservedForUlv = 1820 pp_table->LowestUclkReservedForUlv =
1816 (uint8_t)(data->lowest_uclk_reserved_for_ulv); 1821 (uint8_t)(data->lowest_uclk_reserved_for_ulv);
@@ -3134,6 +3139,8 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
3134 minimum_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock; 3139 minimum_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock;
3135 3140
3136 if (PP_CAP(PHM_PlatformCaps_StablePState)) { 3141 if (PP_CAP(PHM_PlatformCaps_StablePState)) {
3142 stable_pstate_sclk_dpm_percentage =
3143 data->registry_data.stable_pstate_sclk_dpm_percentage;
3137 PP_ASSERT_WITH_CODE( 3144 PP_ASSERT_WITH_CODE(
3138 data->registry_data.stable_pstate_sclk_dpm_percentage >= 1 && 3145 data->registry_data.stable_pstate_sclk_dpm_percentage >= 1 &&
3139 data->registry_data.stable_pstate_sclk_dpm_percentage <= 100, 3146 data->registry_data.stable_pstate_sclk_dpm_percentage <= 100,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
index b4b461c3b8ee..8f7358cc3327 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
@@ -389,6 +389,7 @@ struct vega10_hwmgr {
389 uint32_t config_telemetry; 389 uint32_t config_telemetry;
390 uint32_t smu_version; 390 uint32_t smu_version;
391 uint32_t acg_loop_state; 391 uint32_t acg_loop_state;
392 uint32_t mem_channels;
392}; 393};
393 394
394#define VEGA10_DPM2_NEAR_TDP_DEC 10 395#define VEGA10_DPM2_NEAR_TDP_DEC 10
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 704fc8934616..25f4b2e9a44f 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -234,6 +234,10 @@ int drm_connector_init(struct drm_device *dev,
234 config->link_status_property, 234 config->link_status_property,
235 0); 235 0);
236 236
237 drm_object_attach_property(&connector->base,
238 config->non_desktop_property,
239 0);
240
237 if (drm_core_check_feature(dev, DRIVER_ATOMIC)) { 241 if (drm_core_check_feature(dev, DRIVER_ATOMIC)) {
238 drm_object_attach_property(&connector->base, config->prop_crtc_id, 0); 242 drm_object_attach_property(&connector->base, config->prop_crtc_id, 0);
239 } 243 }
@@ -763,6 +767,10 @@ DRM_ENUM_NAME_FN(drm_get_tv_subconnector_name,
763 * value of link-status is "GOOD". If something fails during or after modeset, 767 * value of link-status is "GOOD". If something fails during or after modeset,
764 * the kernel driver may set this to "BAD" and issue a hotplug uevent. Drivers 768 * the kernel driver may set this to "BAD" and issue a hotplug uevent. Drivers
765 * should update this value using drm_mode_connector_set_link_status_property(). 769 * should update this value using drm_mode_connector_set_link_status_property().
770 * non_desktop:
771 * Indicates the output should be ignored for purposes of displaying a
772 * standard desktop environment or console. This is most likely because
773 * the output device is not rectilinear.
766 * 774 *
767 * Connectors also have one standardized atomic property: 775 * Connectors also have one standardized atomic property:
768 * 776 *
@@ -811,6 +819,11 @@ int drm_connector_create_standard_properties(struct drm_device *dev)
811 return -ENOMEM; 819 return -ENOMEM;
812 dev->mode_config.link_status_property = prop; 820 dev->mode_config.link_status_property = prop;
813 821
822 prop = drm_property_create_bool(dev, DRM_MODE_PROP_IMMUTABLE, "non-desktop");
823 if (!prop)
824 return -ENOMEM;
825 dev->mode_config.non_desktop_property = prop;
826
814 return 0; 827 return 0;
815} 828}
816 829
@@ -1194,6 +1207,10 @@ int drm_mode_connector_update_edid_property(struct drm_connector *connector,
1194 if (edid) 1207 if (edid)
1195 size = EDID_LENGTH * (1 + edid->extensions); 1208 size = EDID_LENGTH * (1 + edid->extensions);
1196 1209
1210 drm_object_property_set_value(&connector->base,
1211 dev->mode_config.non_desktop_property,
1212 connector->display_info.non_desktop);
1213
1197 ret = drm_property_replace_global_blob(dev, 1214 ret = drm_property_replace_global_blob(dev,
1198 &connector->edid_blob_ptr, 1215 &connector->edid_blob_ptr,
1199 size, 1216 size,
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 00ddabfbf980..2e8fb51282ef 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -82,6 +82,8 @@
82#define EDID_QUIRK_FORCE_6BPC (1 << 10) 82#define EDID_QUIRK_FORCE_6BPC (1 << 10)
83/* Force 10bpc */ 83/* Force 10bpc */
84#define EDID_QUIRK_FORCE_10BPC (1 << 11) 84#define EDID_QUIRK_FORCE_10BPC (1 << 11)
85/* Non desktop display (i.e. HMD) */
86#define EDID_QUIRK_NON_DESKTOP (1 << 12)
85 87
86struct detailed_mode_closure { 88struct detailed_mode_closure {
87 struct drm_connector *connector; 89 struct drm_connector *connector;
@@ -157,6 +159,9 @@ static const struct edid_quirk {
157 159
158 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 160 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
159 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 161 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
162
163 /* HTC Vive VR Headset */
164 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
160}; 165};
161 166
162/* 167/*
@@ -4393,7 +4398,7 @@ static void drm_parse_cea_ext(struct drm_connector *connector,
4393} 4398}
4394 4399
4395static void drm_add_display_info(struct drm_connector *connector, 4400static void drm_add_display_info(struct drm_connector *connector,
4396 struct edid *edid) 4401 struct edid *edid, u32 quirks)
4397{ 4402{
4398 struct drm_display_info *info = &connector->display_info; 4403 struct drm_display_info *info = &connector->display_info;
4399 4404
@@ -4407,6 +4412,8 @@ static void drm_add_display_info(struct drm_connector *connector,
4407 info->max_tmds_clock = 0; 4412 info->max_tmds_clock = 0;
4408 info->dvi_dual = false; 4413 info->dvi_dual = false;
4409 4414
4415 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
4416
4410 if (edid->revision < 3) 4417 if (edid->revision < 3)
4411 return; 4418 return;
4412 4419
@@ -4627,7 +4634,7 @@ int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
4627 * To avoid multiple parsing of same block, lets parse that map 4634 * To avoid multiple parsing of same block, lets parse that map
4628 * from sink info, before parsing CEA modes. 4635 * from sink info, before parsing CEA modes.
4629 */ 4636 */
4630 drm_add_display_info(connector, edid); 4637 drm_add_display_info(connector, edid, quirks);
4631 4638
4632 /* 4639 /*
4633 * EDID spec says modes should be preferred in this order: 4640 * EDID spec says modes should be preferred in this order:
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 116d1f1337c7..07374008f146 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -2033,6 +2033,9 @@ static bool drm_connector_enabled(struct drm_connector *connector, bool strict)
2033{ 2033{
2034 bool enable; 2034 bool enable;
2035 2035
2036 if (connector->display_info.non_desktop)
2037 return false;
2038
2036 if (strict) 2039 if (strict)
2037 enable = connector->status == connector_status_connected; 2040 enable = connector->status == connector_status_connected;
2038 else 2041 else
@@ -2052,7 +2055,8 @@ static void drm_enable_connectors(struct drm_fb_helper *fb_helper,
2052 connector = fb_helper->connector_info[i]->connector; 2055 connector = fb_helper->connector_info[i]->connector;
2053 enabled[i] = drm_connector_enabled(connector, true); 2056 enabled[i] = drm_connector_enabled(connector, true);
2054 DRM_DEBUG_KMS("connector %d enabled? %s\n", connector->base.id, 2057 DRM_DEBUG_KMS("connector %d enabled? %s\n", connector->base.id,
2055 enabled[i] ? "yes" : "no"); 2058 connector->display_info.non_desktop ? "non desktop" : enabled[i] ? "yes" : "no");
2059
2056 any_enabled |= enabled[i]; 2060 any_enabled |= enabled[i];
2057 } 2061 }
2058 2062
diff --git a/drivers/gpu/drm/drm_framebuffer.c b/drivers/gpu/drm/drm_framebuffer.c
index 2affe53f3fda..279c1035c12d 100644
--- a/drivers/gpu/drm/drm_framebuffer.c
+++ b/drivers/gpu/drm/drm_framebuffer.c
@@ -681,6 +681,7 @@ EXPORT_SYMBOL(drm_framebuffer_init);
681/** 681/**
682 * drm_framebuffer_lookup - look up a drm framebuffer and grab a reference 682 * drm_framebuffer_lookup - look up a drm framebuffer and grab a reference
683 * @dev: drm device 683 * @dev: drm device
684 * @file_priv: drm file to check for lease against.
684 * @id: id of the fb object 685 * @id: id of the fb object
685 * 686 *
686 * If successful, this grabs an additional reference to the framebuffer - 687 * If successful, this grabs an additional reference to the framebuffer -
diff --git a/drivers/gpu/drm/drm_mode_object.c b/drivers/gpu/drm/drm_mode_object.c
index 7c8b2698c6a7..ce4d2fb32810 100644
--- a/drivers/gpu/drm/drm_mode_object.c
+++ b/drivers/gpu/drm/drm_mode_object.c
@@ -151,6 +151,7 @@ struct drm_mode_object *__drm_mode_object_find(struct drm_device *dev,
151 151
152/** 152/**
153 * drm_mode_object_find - look up a drm object with static lifetime 153 * drm_mode_object_find - look up a drm object with static lifetime
154 * @dev: drm device
154 * @file_priv: drm file 155 * @file_priv: drm file
155 * @id: id of the mode object 156 * @id: id of the mode object
156 * @type: type of the mode object 157 * @type: type of the mode object
diff --git a/drivers/gpu/drm/drm_modeset_lock.c b/drivers/gpu/drm/drm_modeset_lock.c
index e123497da0ca..963e23db0fe7 100644
--- a/drivers/gpu/drm/drm_modeset_lock.c
+++ b/drivers/gpu/drm/drm_modeset_lock.c
@@ -93,7 +93,7 @@ void drm_modeset_lock_all(struct drm_device *dev)
93 struct drm_modeset_acquire_ctx *ctx; 93 struct drm_modeset_acquire_ctx *ctx;
94 int ret; 94 int ret;
95 95
96 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 96 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL | __GFP_NOFAIL);
97 if (WARN_ON(!ctx)) 97 if (WARN_ON(!ctx))
98 return; 98 return;
99 99
diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c
index 19404e34cd59..37a93cdffb4a 100644
--- a/drivers/gpu/drm/drm_plane.c
+++ b/drivers/gpu/drm/drm_plane.c
@@ -1030,6 +1030,7 @@ retry:
1030 e->event.base.type = DRM_EVENT_FLIP_COMPLETE; 1030 e->event.base.type = DRM_EVENT_FLIP_COMPLETE;
1031 e->event.base.length = sizeof(e->event); 1031 e->event.base.length = sizeof(e->event);
1032 e->event.vbl.user_data = page_flip->user_data; 1032 e->event.vbl.user_data = page_flip->user_data;
1033 e->event.vbl.crtc_id = crtc->base.id;
1033 ret = drm_event_reserve_init(dev, file_priv, &e->base, &e->event.base); 1034 ret = drm_event_reserve_init(dev, file_priv, &e->base, &e->event.base);
1034 if (ret) { 1035 if (ret) {
1035 kfree(e); 1036 kfree(e);
diff --git a/drivers/gpu/drm/drm_vblank.c b/drivers/gpu/drm/drm_vblank.c
index 57cc6e37c810..09c1c4ff93ca 100644
--- a/drivers/gpu/drm/drm_vblank.c
+++ b/drivers/gpu/drm/drm_vblank.c
@@ -299,8 +299,8 @@ u32 drm_crtc_accurate_vblank_count(struct drm_crtc *crtc)
299 u32 vblank; 299 u32 vblank;
300 unsigned long flags; 300 unsigned long flags;
301 301
302 WARN(!dev->driver->get_vblank_timestamp, 302 WARN_ONCE(drm_debug & DRM_UT_VBL && !dev->driver->get_vblank_timestamp,
303 "This function requires support for accurate vblank timestamps."); 303 "This function requires support for accurate vblank timestamps.");
304 304
305 spin_lock_irqsave(&dev->vblank_time_lock, flags); 305 spin_lock_irqsave(&dev->vblank_time_lock, flags);
306 306
diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig
index 305dc3d4ff77..5a7c9d8abd6b 100644
--- a/drivers/gpu/drm/exynos/Kconfig
+++ b/drivers/gpu/drm/exynos/Kconfig
@@ -3,6 +3,7 @@ config DRM_EXYNOS
3 depends on OF && DRM && (ARCH_S3C64XX || ARCH_EXYNOS || ARCH_MULTIPLATFORM) 3 depends on OF && DRM && (ARCH_S3C64XX || ARCH_EXYNOS || ARCH_MULTIPLATFORM)
4 select DRM_KMS_HELPER 4 select DRM_KMS_HELPER
5 select VIDEOMODE_HELPERS 5 select VIDEOMODE_HELPERS
6 select SND_SOC_HDMI_CODEC if SND_SOC
6 help 7 help
7 Choose this option if you have a Samsung SoC EXYNOS chipset. 8 Choose this option if you have a Samsung SoC EXYNOS chipset.
8 If M is selected the module will be called exynosdrm. 9 If M is selected the module will be called exynosdrm.
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index 6ce0821590df..dc01342e759a 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -95,8 +95,23 @@ static enum drm_mode_status exynos_crtc_mode_valid(struct drm_crtc *crtc,
95 return MODE_OK; 95 return MODE_OK;
96} 96}
97 97
98static bool exynos_crtc_mode_fixup(struct drm_crtc *crtc,
99 const struct drm_display_mode *mode,
100 struct drm_display_mode *adjusted_mode)
101{
102 struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc);
103
104 if (exynos_crtc->ops->mode_fixup)
105 return exynos_crtc->ops->mode_fixup(exynos_crtc, mode,
106 adjusted_mode);
107
108 return true;
109}
110
111
98static const struct drm_crtc_helper_funcs exynos_crtc_helper_funcs = { 112static const struct drm_crtc_helper_funcs exynos_crtc_helper_funcs = {
99 .mode_valid = exynos_crtc_mode_valid, 113 .mode_valid = exynos_crtc_mode_valid,
114 .mode_fixup = exynos_crtc_mode_fixup,
100 .atomic_check = exynos_crtc_atomic_check, 115 .atomic_check = exynos_crtc_atomic_check,
101 .atomic_begin = exynos_crtc_atomic_begin, 116 .atomic_begin = exynos_crtc_atomic_begin,
102 .atomic_flush = exynos_crtc_atomic_flush, 117 .atomic_flush = exynos_crtc_atomic_flush,
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h
index f8bae4cb4823..c6847fa708fa 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h
@@ -136,6 +136,9 @@ struct exynos_drm_crtc_ops {
136 u32 (*get_vblank_counter)(struct exynos_drm_crtc *crtc); 136 u32 (*get_vblank_counter)(struct exynos_drm_crtc *crtc);
137 enum drm_mode_status (*mode_valid)(struct exynos_drm_crtc *crtc, 137 enum drm_mode_status (*mode_valid)(struct exynos_drm_crtc *crtc,
138 const struct drm_display_mode *mode); 138 const struct drm_display_mode *mode);
139 bool (*mode_fixup)(struct exynos_drm_crtc *crtc,
140 const struct drm_display_mode *mode,
141 struct drm_display_mode *adjusted_mode);
139 int (*atomic_check)(struct exynos_drm_crtc *crtc, 142 int (*atomic_check)(struct exynos_drm_crtc *crtc,
140 struct drm_crtc_state *state); 143 struct drm_crtc_state *state);
141 void (*atomic_begin)(struct exynos_drm_crtc *crtc); 144 void (*atomic_begin)(struct exynos_drm_crtc *crtc);
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 0109ff40b1db..82d1b7e2febe 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -40,7 +40,7 @@
40#include <linux/component.h> 40#include <linux/component.h>
41#include <linux/mfd/syscon.h> 41#include <linux/mfd/syscon.h>
42#include <linux/regmap.h> 42#include <linux/regmap.h>
43 43#include <sound/hdmi-codec.h>
44#include <drm/exynos_drm.h> 44#include <drm/exynos_drm.h>
45 45
46#include <media/cec-notifier.h> 46#include <media/cec-notifier.h>
@@ -111,15 +111,20 @@ struct hdmi_driver_data {
111 struct string_array_spec clk_muxes; 111 struct string_array_spec clk_muxes;
112}; 112};
113 113
114struct hdmi_audio {
115 struct platform_device *pdev;
116 struct hdmi_audio_infoframe infoframe;
117 struct hdmi_codec_params params;
118 bool mute;
119};
120
114struct hdmi_context { 121struct hdmi_context {
115 struct drm_encoder encoder; 122 struct drm_encoder encoder;
116 struct device *dev; 123 struct device *dev;
117 struct drm_device *drm_dev; 124 struct drm_device *drm_dev;
118 struct drm_connector connector; 125 struct drm_connector connector;
119 bool powered;
120 bool dvi_mode; 126 bool dvi_mode;
121 struct delayed_work hotplug_work; 127 struct delayed_work hotplug_work;
122 struct drm_display_mode current_mode;
123 struct cec_notifier *notifier; 128 struct cec_notifier *notifier;
124 const struct hdmi_driver_data *drv_data; 129 const struct hdmi_driver_data *drv_data;
125 130
@@ -137,6 +142,11 @@ struct hdmi_context {
137 struct regulator *reg_hdmi_en; 142 struct regulator *reg_hdmi_en;
138 struct exynos_drm_clk phy_clk; 143 struct exynos_drm_clk phy_clk;
139 struct drm_bridge *bridge; 144 struct drm_bridge *bridge;
145
146 /* mutex protecting subsequent fields below */
147 struct mutex mutex;
148 struct hdmi_audio audio;
149 bool powered;
140}; 150};
141 151
142static inline struct hdmi_context *encoder_to_hdmi(struct drm_encoder *e) 152static inline struct hdmi_context *encoder_to_hdmi(struct drm_encoder *e)
@@ -298,6 +308,15 @@ static const struct hdmiphy_config hdmiphy_v14_configs[] = {
298 }, 308 },
299 }, 309 },
300 { 310 {
311 .pixel_clock = 85500000,
312 .conf = {
313 0x01, 0xd1, 0x24, 0x11, 0x40, 0x40, 0xd0, 0x08,
314 0x84, 0xa0, 0xd6, 0xd8, 0x45, 0xa0, 0xac, 0x80,
315 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
316 0x54, 0x90, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
317 },
318 },
319 {
301 .pixel_clock = 106500000, 320 .pixel_clock = 106500000,
302 .conf = { 321 .conf = {
303 0x01, 0xd1, 0x2c, 0x12, 0x40, 0x0c, 0x09, 0x08, 322 0x01, 0xd1, 0x2c, 0x12, 0x40, 0x0c, 0x09, 0x08,
@@ -768,8 +787,25 @@ static int hdmi_clk_set_parents(struct hdmi_context *hdata, bool to_phy)
768 return ret; 787 return ret;
769} 788}
770 789
790static int hdmi_audio_infoframe_apply(struct hdmi_context *hdata)
791{
792 struct hdmi_audio_infoframe *infoframe = &hdata->audio.infoframe;
793 u8 buf[HDMI_INFOFRAME_SIZE(AUDIO)];
794 int len;
795
796 len = hdmi_audio_infoframe_pack(infoframe, buf, sizeof(buf));
797 if (len < 0)
798 return len;
799
800 hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_EVERY_VSYNC);
801 hdmi_reg_write_buf(hdata, HDMI_AUI_HEADER0, buf, len);
802
803 return 0;
804}
805
771static void hdmi_reg_infoframes(struct hdmi_context *hdata) 806static void hdmi_reg_infoframes(struct hdmi_context *hdata)
772{ 807{
808 struct drm_display_mode *m = &hdata->encoder.crtc->state->mode;
773 union hdmi_infoframe frm; 809 union hdmi_infoframe frm;
774 u8 buf[25]; 810 u8 buf[25];
775 int ret; 811 int ret;
@@ -783,8 +819,7 @@ static void hdmi_reg_infoframes(struct hdmi_context *hdata)
783 return; 819 return;
784 } 820 }
785 821
786 ret = drm_hdmi_avi_infoframe_from_display_mode(&frm.avi, 822 ret = drm_hdmi_avi_infoframe_from_display_mode(&frm.avi, m, false);
787 &hdata->current_mode, false);
788 if (!ret) 823 if (!ret)
789 ret = hdmi_avi_infoframe_pack(&frm.avi, buf, sizeof(buf)); 824 ret = hdmi_avi_infoframe_pack(&frm.avi, buf, sizeof(buf));
790 if (ret > 0) { 825 if (ret > 0) {
@@ -794,8 +829,7 @@ static void hdmi_reg_infoframes(struct hdmi_context *hdata)
794 DRM_INFO("%s: invalid AVI infoframe (%d)\n", __func__, ret); 829 DRM_INFO("%s: invalid AVI infoframe (%d)\n", __func__, ret);
795 } 830 }
796 831
797 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frm.vendor.hdmi, 832 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frm.vendor.hdmi, m);
798 &hdata->current_mode);
799 if (!ret) 833 if (!ret)
800 ret = hdmi_vendor_infoframe_pack(&frm.vendor.hdmi, buf, 834 ret = hdmi_vendor_infoframe_pack(&frm.vendor.hdmi, buf,
801 sizeof(buf)); 835 sizeof(buf));
@@ -805,15 +839,7 @@ static void hdmi_reg_infoframes(struct hdmi_context *hdata)
805 hdmi_reg_write_buf(hdata, HDMI_VSI_DATA(0), buf + 3, ret - 3); 839 hdmi_reg_write_buf(hdata, HDMI_VSI_DATA(0), buf + 3, ret - 3);
806 } 840 }
807 841
808 ret = hdmi_audio_infoframe_init(&frm.audio); 842 hdmi_audio_infoframe_apply(hdata);
809 if (!ret) {
810 frm.audio.channels = 2;
811 ret = hdmi_audio_infoframe_pack(&frm.audio, buf, sizeof(buf));
812 }
813 if (ret > 0) {
814 hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_EVERY_VSYNC);
815 hdmi_reg_write_buf(hdata, HDMI_AUI_HEADER0, buf, ret);
816 }
817} 843}
818 844
819static enum drm_connector_status hdmi_detect(struct drm_connector *connector, 845static enum drm_connector_status hdmi_detect(struct drm_connector *connector,
@@ -1003,23 +1029,18 @@ static void hdmi_reg_acr(struct hdmi_context *hdata, u32 freq)
1003 hdmi_reg_writeb(hdata, HDMI_ACR_CON, 4); 1029 hdmi_reg_writeb(hdata, HDMI_ACR_CON, 4);
1004} 1030}
1005 1031
1006static void hdmi_audio_init(struct hdmi_context *hdata) 1032static void hdmi_audio_config(struct hdmi_context *hdata)
1007{ 1033{
1008 u32 sample_rate, bits_per_sample; 1034 u32 bit_ch = 1;
1009 u32 data_num, bit_ch, sample_frq; 1035 u32 data_num, val;
1010 u32 val; 1036 int i;
1011
1012 sample_rate = 44100;
1013 bits_per_sample = 16;
1014 1037
1015 switch (bits_per_sample) { 1038 switch (hdata->audio.params.sample_width) {
1016 case 20: 1039 case 20:
1017 data_num = 2; 1040 data_num = 2;
1018 bit_ch = 1;
1019 break; 1041 break;
1020 case 24: 1042 case 24:
1021 data_num = 3; 1043 data_num = 3;
1022 bit_ch = 1;
1023 break; 1044 break;
1024 default: 1045 default:
1025 data_num = 1; 1046 data_num = 1;
@@ -1027,7 +1048,7 @@ static void hdmi_audio_init(struct hdmi_context *hdata)
1027 break; 1048 break;
1028 } 1049 }
1029 1050
1030 hdmi_reg_acr(hdata, sample_rate); 1051 hdmi_reg_acr(hdata, hdata->audio.params.sample_rate);
1031 1052
1032 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CON, HDMI_I2S_IN_DISABLE 1053 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CON, HDMI_I2S_IN_DISABLE
1033 | HDMI_I2S_AUD_I2S | HDMI_I2S_CUV_I2S_ENABLE 1054 | HDMI_I2S_AUD_I2S | HDMI_I2S_CUV_I2S_ENABLE
@@ -1037,12 +1058,6 @@ static void hdmi_audio_init(struct hdmi_context *hdata)
1037 | HDMI_I2S_CH1_EN | HDMI_I2S_CH2_EN); 1058 | HDMI_I2S_CH1_EN | HDMI_I2S_CH2_EN);
1038 1059
1039 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CUV, HDMI_I2S_CUV_RL_EN); 1060 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CUV, HDMI_I2S_CUV_RL_EN);
1040
1041 sample_frq = (sample_rate == 44100) ? 0 :
1042 (sample_rate == 48000) ? 2 :
1043 (sample_rate == 32000) ? 3 :
1044 (sample_rate == 96000) ? 0xa : 0x0;
1045
1046 hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_DIS); 1061 hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_DIS);
1047 hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_EN); 1062 hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_EN);
1048 1063
@@ -1066,39 +1081,33 @@ static void hdmi_audio_init(struct hdmi_context *hdata)
1066 | HDMI_I2S_SET_SDATA_BIT(data_num) 1081 | HDMI_I2S_SET_SDATA_BIT(data_num)
1067 | HDMI_I2S_BASIC_FORMAT); 1082 | HDMI_I2S_BASIC_FORMAT);
1068 1083
1069 /* Configure register related to CUV information */ 1084 /* Configuration of the audio channel status registers */
1070 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_0, HDMI_I2S_CH_STATUS_MODE_0 1085 for (i = 0; i < HDMI_I2S_CH_ST_MAXNUM; i++)
1071 | HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH 1086 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST(i),
1072 | HDMI_I2S_COPYRIGHT 1087 hdata->audio.params.iec.status[i]);
1073 | HDMI_I2S_LINEAR_PCM
1074 | HDMI_I2S_CONSUMER_FORMAT);
1075 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_1, HDMI_I2S_CD_PLAYER);
1076 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_2, HDMI_I2S_SET_SOURCE_NUM(0));
1077 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_3, HDMI_I2S_CLK_ACCUR_LEVEL_2
1078 | HDMI_I2S_SET_SMP_FREQ(sample_frq));
1079 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_4,
1080 HDMI_I2S_ORG_SMP_FREQ_44_1
1081 | HDMI_I2S_WORD_LEN_MAX24_24BITS
1082 | HDMI_I2S_WORD_LEN_MAX_24BITS);
1083 1088
1084 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_CON, HDMI_I2S_CH_STATUS_RELOAD); 1089 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_CON, HDMI_I2S_CH_STATUS_RELOAD);
1085} 1090}
1086 1091
1087static void hdmi_audio_control(struct hdmi_context *hdata, bool onoff) 1092static void hdmi_audio_control(struct hdmi_context *hdata)
1088{ 1093{
1094 bool enable = !hdata->audio.mute;
1095
1089 if (hdata->dvi_mode) 1096 if (hdata->dvi_mode)
1090 return; 1097 return;
1091 1098
1092 hdmi_reg_writeb(hdata, HDMI_AUI_CON, onoff ? 2 : 0); 1099 hdmi_reg_writeb(hdata, HDMI_AUI_CON, enable ?
1093 hdmi_reg_writemask(hdata, HDMI_CON_0, onoff ? 1100 HDMI_AVI_CON_EVERY_VSYNC : HDMI_AUI_CON_NO_TRAN);
1101 hdmi_reg_writemask(hdata, HDMI_CON_0, enable ?
1094 HDMI_ASP_EN : HDMI_ASP_DIS, HDMI_ASP_MASK); 1102 HDMI_ASP_EN : HDMI_ASP_DIS, HDMI_ASP_MASK);
1095} 1103}
1096 1104
1097static void hdmi_start(struct hdmi_context *hdata, bool start) 1105static void hdmi_start(struct hdmi_context *hdata, bool start)
1098{ 1106{
1107 struct drm_display_mode *m = &hdata->encoder.crtc->state->mode;
1099 u32 val = start ? HDMI_TG_EN : 0; 1108 u32 val = start ? HDMI_TG_EN : 0;
1100 1109
1101 if (hdata->current_mode.flags & DRM_MODE_FLAG_INTERLACE) 1110 if (m->flags & DRM_MODE_FLAG_INTERLACE)
1102 val |= HDMI_FIELD_EN; 1111 val |= HDMI_FIELD_EN;
1103 1112
1104 hdmi_reg_writemask(hdata, HDMI_CON_0, val, HDMI_EN); 1113 hdmi_reg_writemask(hdata, HDMI_CON_0, val, HDMI_EN);
@@ -1168,7 +1177,7 @@ static void hdmiphy_wait_for_pll(struct hdmi_context *hdata)
1168 1177
1169static void hdmi_v13_mode_apply(struct hdmi_context *hdata) 1178static void hdmi_v13_mode_apply(struct hdmi_context *hdata)
1170{ 1179{
1171 struct drm_display_mode *m = &hdata->current_mode; 1180 struct drm_display_mode *m = &hdata->encoder.crtc->state->mode;
1172 unsigned int val; 1181 unsigned int val;
1173 1182
1174 hdmi_reg_writev(hdata, HDMI_H_BLANK_0, 2, m->htotal - m->hdisplay); 1183 hdmi_reg_writev(hdata, HDMI_H_BLANK_0, 2, m->htotal - m->hdisplay);
@@ -1247,7 +1256,19 @@ static void hdmi_v13_mode_apply(struct hdmi_context *hdata)
1247 1256
1248static void hdmi_v14_mode_apply(struct hdmi_context *hdata) 1257static void hdmi_v14_mode_apply(struct hdmi_context *hdata)
1249{ 1258{
1250 struct drm_display_mode *m = &hdata->current_mode; 1259 struct drm_display_mode *m = &hdata->encoder.crtc->state->mode;
1260 struct drm_display_mode *am =
1261 &hdata->encoder.crtc->state->adjusted_mode;
1262 int hquirk = 0;
1263
1264 /*
1265 * In case video mode coming from CRTC differs from requested one HDMI
1266 * sometimes is able to almost properly perform conversion - only
1267 * first line is distorted.
1268 */
1269 if ((m->vdisplay != am->vdisplay) &&
1270 (m->hdisplay == 1280 || m->hdisplay == 1024 || m->hdisplay == 1366))
1271 hquirk = 258;
1251 1272
1252 hdmi_reg_writev(hdata, HDMI_H_BLANK_0, 2, m->htotal - m->hdisplay); 1273 hdmi_reg_writev(hdata, HDMI_H_BLANK_0, 2, m->htotal - m->hdisplay);
1253 hdmi_reg_writev(hdata, HDMI_V_LINE_0, 2, m->vtotal); 1274 hdmi_reg_writev(hdata, HDMI_V_LINE_0, 2, m->vtotal);
@@ -1341,8 +1362,9 @@ static void hdmi_v14_mode_apply(struct hdmi_context *hdata)
1341 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_0, 2, 0xffff); 1362 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_0, 2, 0xffff);
1342 1363
1343 hdmi_reg_writev(hdata, HDMI_TG_H_FSZ_L, 2, m->htotal); 1364 hdmi_reg_writev(hdata, HDMI_TG_H_FSZ_L, 2, m->htotal);
1344 hdmi_reg_writev(hdata, HDMI_TG_HACT_ST_L, 2, m->htotal - m->hdisplay); 1365 hdmi_reg_writev(hdata, HDMI_TG_HACT_ST_L, 2,
1345 hdmi_reg_writev(hdata, HDMI_TG_HACT_SZ_L, 2, m->hdisplay); 1366 m->htotal - m->hdisplay - hquirk);
1367 hdmi_reg_writev(hdata, HDMI_TG_HACT_SZ_L, 2, m->hdisplay + hquirk);
1346 hdmi_reg_writev(hdata, HDMI_TG_V_FSZ_L, 2, m->vtotal); 1368 hdmi_reg_writev(hdata, HDMI_TG_V_FSZ_L, 2, m->vtotal);
1347 if (hdata->drv_data == &exynos5433_hdmi_driver_data) 1369 if (hdata->drv_data == &exynos5433_hdmi_driver_data)
1348 hdmi_reg_writeb(hdata, HDMI_TG_DECON_EN, 1); 1370 hdmi_reg_writeb(hdata, HDMI_TG_DECON_EN, 1);
@@ -1380,10 +1402,11 @@ static void hdmiphy_enable_mode_set(struct hdmi_context *hdata, bool enable)
1380 1402
1381static void hdmiphy_conf_apply(struct hdmi_context *hdata) 1403static void hdmiphy_conf_apply(struct hdmi_context *hdata)
1382{ 1404{
1405 struct drm_display_mode *m = &hdata->encoder.crtc->state->mode;
1383 int ret; 1406 int ret;
1384 const u8 *phy_conf; 1407 const u8 *phy_conf;
1385 1408
1386 ret = hdmi_find_phy_conf(hdata, hdata->current_mode.clock * 1000); 1409 ret = hdmi_find_phy_conf(hdata, m->clock * 1000);
1387 if (ret < 0) { 1410 if (ret < 0) {
1388 DRM_ERROR("failed to find hdmiphy conf\n"); 1411 DRM_ERROR("failed to find hdmiphy conf\n");
1389 return; 1412 return;
@@ -1406,28 +1429,14 @@ static void hdmiphy_conf_apply(struct hdmi_context *hdata)
1406 hdmiphy_wait_for_pll(hdata); 1429 hdmiphy_wait_for_pll(hdata);
1407} 1430}
1408 1431
1432/* Should be called with hdata->mutex mutex held */
1409static void hdmi_conf_apply(struct hdmi_context *hdata) 1433static void hdmi_conf_apply(struct hdmi_context *hdata)
1410{ 1434{
1411 hdmi_start(hdata, false); 1435 hdmi_start(hdata, false);
1412 hdmi_conf_init(hdata); 1436 hdmi_conf_init(hdata);
1413 hdmi_audio_init(hdata); 1437 hdmi_audio_config(hdata);
1414 hdmi_mode_apply(hdata); 1438 hdmi_mode_apply(hdata);
1415 hdmi_audio_control(hdata, true); 1439 hdmi_audio_control(hdata);
1416}
1417
1418static void hdmi_mode_set(struct drm_encoder *encoder,
1419 struct drm_display_mode *mode,
1420 struct drm_display_mode *adjusted_mode)
1421{
1422 struct hdmi_context *hdata = encoder_to_hdmi(encoder);
1423 struct drm_display_mode *m = adjusted_mode;
1424
1425 DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%s\n",
1426 m->hdisplay, m->vdisplay,
1427 m->vrefresh, (m->flags & DRM_MODE_FLAG_INTERLACE) ?
1428 "INTERLACED" : "PROGRESSIVE");
1429
1430 drm_mode_copy(&hdata->current_mode, m);
1431} 1440}
1432 1441
1433static void hdmi_set_refclk(struct hdmi_context *hdata, bool on) 1442static void hdmi_set_refclk(struct hdmi_context *hdata, bool on)
@@ -1439,6 +1448,7 @@ static void hdmi_set_refclk(struct hdmi_context *hdata, bool on)
1439 SYSREG_HDMI_REFCLK_INT_CLK, on ? ~0 : 0); 1448 SYSREG_HDMI_REFCLK_INT_CLK, on ? ~0 : 0);
1440} 1449}
1441 1450
1451/* Should be called with hdata->mutex mutex held. */
1442static void hdmiphy_enable(struct hdmi_context *hdata) 1452static void hdmiphy_enable(struct hdmi_context *hdata)
1443{ 1453{
1444 if (hdata->powered) 1454 if (hdata->powered)
@@ -1461,6 +1471,7 @@ static void hdmiphy_enable(struct hdmi_context *hdata)
1461 hdata->powered = true; 1471 hdata->powered = true;
1462} 1472}
1463 1473
1474/* Should be called with hdata->mutex mutex held. */
1464static void hdmiphy_disable(struct hdmi_context *hdata) 1475static void hdmiphy_disable(struct hdmi_context *hdata)
1465{ 1476{
1466 if (!hdata->powered) 1477 if (!hdata->powered)
@@ -1486,33 +1497,42 @@ static void hdmi_enable(struct drm_encoder *encoder)
1486{ 1497{
1487 struct hdmi_context *hdata = encoder_to_hdmi(encoder); 1498 struct hdmi_context *hdata = encoder_to_hdmi(encoder);
1488 1499
1500 mutex_lock(&hdata->mutex);
1501
1489 hdmiphy_enable(hdata); 1502 hdmiphy_enable(hdata);
1490 hdmi_conf_apply(hdata); 1503 hdmi_conf_apply(hdata);
1504
1505 mutex_unlock(&hdata->mutex);
1491} 1506}
1492 1507
1493static void hdmi_disable(struct drm_encoder *encoder) 1508static void hdmi_disable(struct drm_encoder *encoder)
1494{ 1509{
1495 struct hdmi_context *hdata = encoder_to_hdmi(encoder); 1510 struct hdmi_context *hdata = encoder_to_hdmi(encoder);
1496 1511
1497 if (!hdata->powered) 1512 mutex_lock(&hdata->mutex);
1513
1514 if (hdata->powered) {
1515 /*
1516 * The SFRs of VP and Mixer are updated by Vertical Sync of
1517 * Timing generator which is a part of HDMI so the sequence
1518 * to disable TV Subsystem should be as following,
1519 * VP -> Mixer -> HDMI
1520 *
1521 * To achieve such sequence HDMI is disabled together with
1522 * HDMI PHY, via pipe clock callback.
1523 */
1524 mutex_unlock(&hdata->mutex);
1525 cancel_delayed_work(&hdata->hotplug_work);
1526 cec_notifier_set_phys_addr(hdata->notifier,
1527 CEC_PHYS_ADDR_INVALID);
1498 return; 1528 return;
1529 }
1499 1530
1500 /* 1531 mutex_unlock(&hdata->mutex);
1501 * The SFRs of VP and Mixer are updated by Vertical Sync of
1502 * Timing generator which is a part of HDMI so the sequence
1503 * to disable TV Subsystem should be as following,
1504 * VP -> Mixer -> HDMI
1505 *
1506 * To achieve such sequence HDMI is disabled together with HDMI PHY, via
1507 * pipe clock callback.
1508 */
1509 cancel_delayed_work(&hdata->hotplug_work);
1510 cec_notifier_set_phys_addr(hdata->notifier, CEC_PHYS_ADDR_INVALID);
1511} 1532}
1512 1533
1513static const struct drm_encoder_helper_funcs exynos_hdmi_encoder_helper_funcs = { 1534static const struct drm_encoder_helper_funcs exynos_hdmi_encoder_helper_funcs = {
1514 .mode_fixup = hdmi_mode_fixup, 1535 .mode_fixup = hdmi_mode_fixup,
1515 .mode_set = hdmi_mode_set,
1516 .enable = hdmi_enable, 1536 .enable = hdmi_enable,
1517 .disable = hdmi_disable, 1537 .disable = hdmi_disable,
1518}; 1538};
@@ -1521,6 +1541,99 @@ static const struct drm_encoder_funcs exynos_hdmi_encoder_funcs = {
1521 .destroy = drm_encoder_cleanup, 1541 .destroy = drm_encoder_cleanup,
1522}; 1542};
1523 1543
1544static void hdmi_audio_shutdown(struct device *dev, void *data)
1545{
1546 struct hdmi_context *hdata = dev_get_drvdata(dev);
1547
1548 mutex_lock(&hdata->mutex);
1549
1550 hdata->audio.mute = true;
1551
1552 if (hdata->powered)
1553 hdmi_audio_control(hdata);
1554
1555 mutex_unlock(&hdata->mutex);
1556}
1557
1558static int hdmi_audio_hw_params(struct device *dev, void *data,
1559 struct hdmi_codec_daifmt *daifmt,
1560 struct hdmi_codec_params *params)
1561{
1562 struct hdmi_context *hdata = dev_get_drvdata(dev);
1563
1564 if (daifmt->fmt != HDMI_I2S || daifmt->bit_clk_inv ||
1565 daifmt->frame_clk_inv || daifmt->bit_clk_master ||
1566 daifmt->frame_clk_master) {
1567 dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__,
1568 daifmt->bit_clk_inv, daifmt->frame_clk_inv,
1569 daifmt->bit_clk_master,
1570 daifmt->frame_clk_master);
1571 return -EINVAL;
1572 }
1573
1574 mutex_lock(&hdata->mutex);
1575
1576 hdata->audio.params = *params;
1577
1578 if (hdata->powered) {
1579 hdmi_audio_config(hdata);
1580 hdmi_audio_infoframe_apply(hdata);
1581 }
1582
1583 mutex_unlock(&hdata->mutex);
1584
1585 return 0;
1586}
1587
1588static int hdmi_audio_digital_mute(struct device *dev, void *data, bool mute)
1589{
1590 struct hdmi_context *hdata = dev_get_drvdata(dev);
1591
1592 mutex_lock(&hdata->mutex);
1593
1594 hdata->audio.mute = mute;
1595
1596 if (hdata->powered)
1597 hdmi_audio_control(hdata);
1598
1599 mutex_unlock(&hdata->mutex);
1600
1601 return 0;
1602}
1603
1604static int hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf,
1605 size_t len)
1606{
1607 struct hdmi_context *hdata = dev_get_drvdata(dev);
1608 struct drm_connector *connector = &hdata->connector;
1609
1610 memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
1611
1612 return 0;
1613}
1614
1615static const struct hdmi_codec_ops audio_codec_ops = {
1616 .hw_params = hdmi_audio_hw_params,
1617 .audio_shutdown = hdmi_audio_shutdown,
1618 .digital_mute = hdmi_audio_digital_mute,
1619 .get_eld = hdmi_audio_get_eld,
1620};
1621
1622static int hdmi_register_audio_device(struct hdmi_context *hdata)
1623{
1624 struct hdmi_codec_pdata codec_data = {
1625 .ops = &audio_codec_ops,
1626 .max_i2s_channels = 6,
1627 .i2s = 1,
1628 };
1629
1630 hdata->audio.pdev = platform_device_register_data(
1631 hdata->dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO,
1632 &codec_data, sizeof(codec_data));
1633
1634 return PTR_ERR_OR_ZERO(hdata->audio.pdev);
1635}
1636
1524static void hdmi_hotplug_work_func(struct work_struct *work) 1637static void hdmi_hotplug_work_func(struct work_struct *work)
1525{ 1638{
1526 struct hdmi_context *hdata; 1639 struct hdmi_context *hdata;
@@ -1596,11 +1709,14 @@ static void hdmiphy_clk_enable(struct exynos_drm_clk *clk, bool enable)
1596{ 1709{
1597 struct hdmi_context *hdata = container_of(clk, struct hdmi_context, 1710 struct hdmi_context *hdata = container_of(clk, struct hdmi_context,
1598 phy_clk); 1711 phy_clk);
1712 mutex_lock(&hdata->mutex);
1599 1713
1600 if (enable) 1714 if (enable)
1601 hdmiphy_enable(hdata); 1715 hdmiphy_enable(hdata);
1602 else 1716 else
1603 hdmiphy_disable(hdata); 1717 hdmiphy_disable(hdata);
1718
1719 mutex_unlock(&hdata->mutex);
1604} 1720}
1605 1721
1606static int hdmi_bridge_init(struct hdmi_context *hdata) 1722static int hdmi_bridge_init(struct hdmi_context *hdata)
@@ -1811,6 +1927,7 @@ out:
1811 1927
1812static int hdmi_probe(struct platform_device *pdev) 1928static int hdmi_probe(struct platform_device *pdev)
1813{ 1929{
1930 struct hdmi_audio_infoframe *audio_infoframe;
1814 struct device *dev = &pdev->dev; 1931 struct device *dev = &pdev->dev;
1815 struct hdmi_context *hdata; 1932 struct hdmi_context *hdata;
1816 struct resource *res; 1933 struct resource *res;
@@ -1826,6 +1943,8 @@ static int hdmi_probe(struct platform_device *pdev)
1826 1943
1827 hdata->dev = dev; 1944 hdata->dev = dev;
1828 1945
1946 mutex_init(&hdata->mutex);
1947
1829 ret = hdmi_resources_init(hdata); 1948 ret = hdmi_resources_init(hdata);
1830 if (ret) { 1949 if (ret) {
1831 if (ret != -EPROBE_DEFER) 1950 if (ret != -EPROBE_DEFER)
@@ -1885,12 +2004,26 @@ static int hdmi_probe(struct platform_device *pdev)
1885 2004
1886 pm_runtime_enable(dev); 2005 pm_runtime_enable(dev);
1887 2006
1888 ret = component_add(&pdev->dev, &hdmi_component_ops); 2007 audio_infoframe = &hdata->audio.infoframe;
2008 hdmi_audio_infoframe_init(audio_infoframe);
2009 audio_infoframe->coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
2010 audio_infoframe->sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
2011 audio_infoframe->sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
2012 audio_infoframe->channels = 2;
2013
2014 ret = hdmi_register_audio_device(hdata);
1889 if (ret) 2015 if (ret)
1890 goto err_notifier_put; 2016 goto err_notifier_put;
1891 2017
2018 ret = component_add(&pdev->dev, &hdmi_component_ops);
2019 if (ret)
2020 goto err_unregister_audio;
2021
1892 return ret; 2022 return ret;
1893 2023
2024err_unregister_audio:
2025 platform_device_unregister(hdata->audio.pdev);
2026
1894err_notifier_put: 2027err_notifier_put:
1895 cec_notifier_put(hdata->notifier); 2028 cec_notifier_put(hdata->notifier);
1896 pm_runtime_disable(dev); 2029 pm_runtime_disable(dev);
@@ -1914,6 +2047,7 @@ static int hdmi_remove(struct platform_device *pdev)
1914 cec_notifier_set_phys_addr(hdata->notifier, CEC_PHYS_ADDR_INVALID); 2047 cec_notifier_set_phys_addr(hdata->notifier, CEC_PHYS_ADDR_INVALID);
1915 2048
1916 component_del(&pdev->dev, &hdmi_component_ops); 2049 component_del(&pdev->dev, &hdmi_component_ops);
2050 platform_device_unregister(hdata->audio.pdev);
1917 2051
1918 cec_notifier_put(hdata->notifier); 2052 cec_notifier_put(hdata->notifier);
1919 pm_runtime_disable(&pdev->dev); 2053 pm_runtime_disable(&pdev->dev);
@@ -1929,6 +2063,8 @@ static int hdmi_remove(struct platform_device *pdev)
1929 2063
1930 put_device(&hdata->ddc_adpt->dev); 2064 put_device(&hdata->ddc_adpt->dev);
1931 2065
2066 mutex_destroy(&hdata->mutex);
2067
1932 return 0; 2068 return 0;
1933} 2069}
1934 2070
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
index 002755415e00..dc5d79465f9b 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -67,19 +67,6 @@
67#define MXR_FORMAT_ARGB4444 6 67#define MXR_FORMAT_ARGB4444 6
68#define MXR_FORMAT_ARGB8888 7 68#define MXR_FORMAT_ARGB8888 7
69 69
70struct mixer_resources {
71 int irq;
72 void __iomem *mixer_regs;
73 void __iomem *vp_regs;
74 spinlock_t reg_slock;
75 struct clk *mixer;
76 struct clk *vp;
77 struct clk *hdmi;
78 struct clk *sclk_mixer;
79 struct clk *sclk_hdmi;
80 struct clk *mout_mixer;
81};
82
83enum mixer_version_id { 70enum mixer_version_id {
84 MXR_VER_0_0_0_16, 71 MXR_VER_0_0_0_16,
85 MXR_VER_16_0_33_0, 72 MXR_VER_16_0_33_0,
@@ -117,8 +104,18 @@ struct mixer_context {
117 struct exynos_drm_plane planes[MIXER_WIN_NR]; 104 struct exynos_drm_plane planes[MIXER_WIN_NR];
118 unsigned long flags; 105 unsigned long flags;
119 106
120 struct mixer_resources mixer_res; 107 int irq;
108 void __iomem *mixer_regs;
109 void __iomem *vp_regs;
110 spinlock_t reg_slock;
111 struct clk *mixer;
112 struct clk *vp;
113 struct clk *hdmi;
114 struct clk *sclk_mixer;
115 struct clk *sclk_hdmi;
116 struct clk *mout_mixer;
121 enum mixer_version_id mxr_ver; 117 enum mixer_version_id mxr_ver;
118 int scan_value;
122}; 119};
123 120
124struct mixer_drv_data { 121struct mixer_drv_data {
@@ -194,44 +191,44 @@ static inline bool is_alpha_format(unsigned int pixel_format)
194 } 191 }
195} 192}
196 193
197static inline u32 vp_reg_read(struct mixer_resources *res, u32 reg_id) 194static inline u32 vp_reg_read(struct mixer_context *ctx, u32 reg_id)
198{ 195{
199 return readl(res->vp_regs + reg_id); 196 return readl(ctx->vp_regs + reg_id);
200} 197}
201 198
202static inline void vp_reg_write(struct mixer_resources *res, u32 reg_id, 199static inline void vp_reg_write(struct mixer_context *ctx, u32 reg_id,
203 u32 val) 200 u32 val)
204{ 201{
205 writel(val, res->vp_regs + reg_id); 202 writel(val, ctx->vp_regs + reg_id);
206} 203}
207 204
208static inline void vp_reg_writemask(struct mixer_resources *res, u32 reg_id, 205static inline void vp_reg_writemask(struct mixer_context *ctx, u32 reg_id,
209 u32 val, u32 mask) 206 u32 val, u32 mask)
210{ 207{
211 u32 old = vp_reg_read(res, reg_id); 208 u32 old = vp_reg_read(ctx, reg_id);
212 209
213 val = (val & mask) | (old & ~mask); 210 val = (val & mask) | (old & ~mask);
214 writel(val, res->vp_regs + reg_id); 211 writel(val, ctx->vp_regs + reg_id);
215} 212}
216 213
217static inline u32 mixer_reg_read(struct mixer_resources *res, u32 reg_id) 214static inline u32 mixer_reg_read(struct mixer_context *ctx, u32 reg_id)
218{ 215{
219 return readl(res->mixer_regs + reg_id); 216 return readl(ctx->mixer_regs + reg_id);
220} 217}
221 218
222static inline void mixer_reg_write(struct mixer_resources *res, u32 reg_id, 219static inline void mixer_reg_write(struct mixer_context *ctx, u32 reg_id,
223 u32 val) 220 u32 val)
224{ 221{
225 writel(val, res->mixer_regs + reg_id); 222 writel(val, ctx->mixer_regs + reg_id);
226} 223}
227 224
228static inline void mixer_reg_writemask(struct mixer_resources *res, 225static inline void mixer_reg_writemask(struct mixer_context *ctx,
229 u32 reg_id, u32 val, u32 mask) 226 u32 reg_id, u32 val, u32 mask)
230{ 227{
231 u32 old = mixer_reg_read(res, reg_id); 228 u32 old = mixer_reg_read(ctx, reg_id);
232 229
233 val = (val & mask) | (old & ~mask); 230 val = (val & mask) | (old & ~mask);
234 writel(val, res->mixer_regs + reg_id); 231 writel(val, ctx->mixer_regs + reg_id);
235} 232}
236 233
237static void mixer_regs_dump(struct mixer_context *ctx) 234static void mixer_regs_dump(struct mixer_context *ctx)
@@ -239,7 +236,7 @@ static void mixer_regs_dump(struct mixer_context *ctx)
239#define DUMPREG(reg_id) \ 236#define DUMPREG(reg_id) \
240do { \ 237do { \
241 DRM_DEBUG_KMS(#reg_id " = %08x\n", \ 238 DRM_DEBUG_KMS(#reg_id " = %08x\n", \
242 (u32)readl(ctx->mixer_res.mixer_regs + reg_id)); \ 239 (u32)readl(ctx->mixer_regs + reg_id)); \
243} while (0) 240} while (0)
244 241
245 DUMPREG(MXR_STATUS); 242 DUMPREG(MXR_STATUS);
@@ -271,7 +268,7 @@ static void vp_regs_dump(struct mixer_context *ctx)
271#define DUMPREG(reg_id) \ 268#define DUMPREG(reg_id) \
272do { \ 269do { \
273 DRM_DEBUG_KMS(#reg_id " = %08x\n", \ 270 DRM_DEBUG_KMS(#reg_id " = %08x\n", \
274 (u32) readl(ctx->mixer_res.vp_regs + reg_id)); \ 271 (u32) readl(ctx->vp_regs + reg_id)); \
275} while (0) 272} while (0)
276 273
277 DUMPREG(VP_ENABLE); 274 DUMPREG(VP_ENABLE);
@@ -301,7 +298,7 @@ do { \
301#undef DUMPREG 298#undef DUMPREG
302} 299}
303 300
304static inline void vp_filter_set(struct mixer_resources *res, 301static inline void vp_filter_set(struct mixer_context *ctx,
305 int reg_id, const u8 *data, unsigned int size) 302 int reg_id, const u8 *data, unsigned int size)
306{ 303{
307 /* assure 4-byte align */ 304 /* assure 4-byte align */
@@ -309,24 +306,23 @@ static inline void vp_filter_set(struct mixer_resources *res,
309 for (; size; size -= 4, reg_id += 4, data += 4) { 306 for (; size; size -= 4, reg_id += 4, data += 4) {
310 u32 val = (data[0] << 24) | (data[1] << 16) | 307 u32 val = (data[0] << 24) | (data[1] << 16) |
311 (data[2] << 8) | data[3]; 308 (data[2] << 8) | data[3];
312 vp_reg_write(res, reg_id, val); 309 vp_reg_write(ctx, reg_id, val);
313 } 310 }
314} 311}
315 312
316static void vp_default_filter(struct mixer_resources *res) 313static void vp_default_filter(struct mixer_context *ctx)
317{ 314{
318 vp_filter_set(res, VP_POLY8_Y0_LL, 315 vp_filter_set(ctx, VP_POLY8_Y0_LL,
319 filter_y_horiz_tap8, sizeof(filter_y_horiz_tap8)); 316 filter_y_horiz_tap8, sizeof(filter_y_horiz_tap8));
320 vp_filter_set(res, VP_POLY4_Y0_LL, 317 vp_filter_set(ctx, VP_POLY4_Y0_LL,
321 filter_y_vert_tap4, sizeof(filter_y_vert_tap4)); 318 filter_y_vert_tap4, sizeof(filter_y_vert_tap4));
322 vp_filter_set(res, VP_POLY4_C0_LL, 319 vp_filter_set(ctx, VP_POLY4_C0_LL,
323 filter_cr_horiz_tap4, sizeof(filter_cr_horiz_tap4)); 320 filter_cr_horiz_tap4, sizeof(filter_cr_horiz_tap4));
324} 321}
325 322
326static void mixer_cfg_gfx_blend(struct mixer_context *ctx, unsigned int win, 323static void mixer_cfg_gfx_blend(struct mixer_context *ctx, unsigned int win,
327 bool alpha) 324 bool alpha)
328{ 325{
329 struct mixer_resources *res = &ctx->mixer_res;
330 u32 val; 326 u32 val;
331 327
332 val = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */ 328 val = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */
@@ -335,13 +331,12 @@ static void mixer_cfg_gfx_blend(struct mixer_context *ctx, unsigned int win,
335 val |= MXR_GRP_CFG_BLEND_PRE_MUL; 331 val |= MXR_GRP_CFG_BLEND_PRE_MUL;
336 val |= MXR_GRP_CFG_PIXEL_BLEND_EN; 332 val |= MXR_GRP_CFG_PIXEL_BLEND_EN;
337 } 333 }
338 mixer_reg_writemask(res, MXR_GRAPHIC_CFG(win), 334 mixer_reg_writemask(ctx, MXR_GRAPHIC_CFG(win),
339 val, MXR_GRP_CFG_MISC_MASK); 335 val, MXR_GRP_CFG_MISC_MASK);
340} 336}
341 337
342static void mixer_cfg_vp_blend(struct mixer_context *ctx) 338static void mixer_cfg_vp_blend(struct mixer_context *ctx)
343{ 339{
344 struct mixer_resources *res = &ctx->mixer_res;
345 u32 val; 340 u32 val;
346 341
347 /* 342 /*
@@ -351,51 +346,39 @@ static void mixer_cfg_vp_blend(struct mixer_context *ctx)
351 * support blending of the video layer through this. 346 * support blending of the video layer through this.
352 */ 347 */
353 val = 0; 348 val = 0;
354 mixer_reg_write(res, MXR_VIDEO_CFG, val); 349 mixer_reg_write(ctx, MXR_VIDEO_CFG, val);
355} 350}
356 351
357static void mixer_vsync_set_update(struct mixer_context *ctx, bool enable) 352static void mixer_vsync_set_update(struct mixer_context *ctx, bool enable)
358{ 353{
359 struct mixer_resources *res = &ctx->mixer_res;
360
361 /* block update on vsync */ 354 /* block update on vsync */
362 mixer_reg_writemask(res, MXR_STATUS, enable ? 355 mixer_reg_writemask(ctx, MXR_STATUS, enable ?
363 MXR_STATUS_SYNC_ENABLE : 0, MXR_STATUS_SYNC_ENABLE); 356 MXR_STATUS_SYNC_ENABLE : 0, MXR_STATUS_SYNC_ENABLE);
364 357
365 if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) 358 if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags))
366 vp_reg_write(res, VP_SHADOW_UPDATE, enable ? 359 vp_reg_write(ctx, VP_SHADOW_UPDATE, enable ?
367 VP_SHADOW_UPDATE_ENABLE : 0); 360 VP_SHADOW_UPDATE_ENABLE : 0);
368} 361}
369 362
370static void mixer_cfg_scan(struct mixer_context *ctx, unsigned int height) 363static void mixer_cfg_scan(struct mixer_context *ctx, int width, int height)
371{ 364{
372 struct mixer_resources *res = &ctx->mixer_res;
373 u32 val; 365 u32 val;
374 366
375 /* choosing between interlace and progressive mode */ 367 /* choosing between interlace and progressive mode */
376 val = test_bit(MXR_BIT_INTERLACE, &ctx->flags) ? 368 val = test_bit(MXR_BIT_INTERLACE, &ctx->flags) ?
377 MXR_CFG_SCAN_INTERLACE : MXR_CFG_SCAN_PROGRESSIVE; 369 MXR_CFG_SCAN_INTERLACE : MXR_CFG_SCAN_PROGRESSIVE;
378 370
379 if (ctx->mxr_ver != MXR_VER_128_0_0_184) { 371 if (ctx->mxr_ver == MXR_VER_128_0_0_184)
380 /* choosing between proper HD and SD mode */ 372 mixer_reg_write(ctx, MXR_RESOLUTION,
381 if (height <= 480) 373 MXR_MXR_RES_HEIGHT(height) | MXR_MXR_RES_WIDTH(width));
382 val |= MXR_CFG_SCAN_NTSC | MXR_CFG_SCAN_SD; 374 else
383 else if (height <= 576) 375 val |= ctx->scan_value;
384 val |= MXR_CFG_SCAN_PAL | MXR_CFG_SCAN_SD;
385 else if (height <= 720)
386 val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD;
387 else if (height <= 1080)
388 val |= MXR_CFG_SCAN_HD_1080 | MXR_CFG_SCAN_HD;
389 else
390 val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD;
391 }
392 376
393 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_SCAN_MASK); 377 mixer_reg_writemask(ctx, MXR_CFG, val, MXR_CFG_SCAN_MASK);
394} 378}
395 379
396static void mixer_cfg_rgb_fmt(struct mixer_context *ctx, unsigned int height) 380static void mixer_cfg_rgb_fmt(struct mixer_context *ctx, unsigned int height)
397{ 381{
398 struct mixer_resources *res = &ctx->mixer_res;
399 u32 val; 382 u32 val;
400 383
401 switch (height) { 384 switch (height) {
@@ -408,45 +391,44 @@ static void mixer_cfg_rgb_fmt(struct mixer_context *ctx, unsigned int height)
408 default: 391 default:
409 val = MXR_CFG_RGB709_16_235; 392 val = MXR_CFG_RGB709_16_235;
410 /* Configure the BT.709 CSC matrix for full range RGB. */ 393 /* Configure the BT.709 CSC matrix for full range RGB. */
411 mixer_reg_write(res, MXR_CM_COEFF_Y, 394 mixer_reg_write(ctx, MXR_CM_COEFF_Y,
412 MXR_CSC_CT( 0.184, 0.614, 0.063) | 395 MXR_CSC_CT( 0.184, 0.614, 0.063) |
413 MXR_CM_COEFF_RGB_FULL); 396 MXR_CM_COEFF_RGB_FULL);
414 mixer_reg_write(res, MXR_CM_COEFF_CB, 397 mixer_reg_write(ctx, MXR_CM_COEFF_CB,
415 MXR_CSC_CT(-0.102, -0.338, 0.440)); 398 MXR_CSC_CT(-0.102, -0.338, 0.440));
416 mixer_reg_write(res, MXR_CM_COEFF_CR, 399 mixer_reg_write(ctx, MXR_CM_COEFF_CR,
417 MXR_CSC_CT( 0.440, -0.399, -0.040)); 400 MXR_CSC_CT( 0.440, -0.399, -0.040));
418 break; 401 break;
419 } 402 }
420 403
421 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK); 404 mixer_reg_writemask(ctx, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK);
422} 405}
423 406
424static void mixer_cfg_layer(struct mixer_context *ctx, unsigned int win, 407static void mixer_cfg_layer(struct mixer_context *ctx, unsigned int win,
425 unsigned int priority, bool enable) 408 unsigned int priority, bool enable)
426{ 409{
427 struct mixer_resources *res = &ctx->mixer_res;
428 u32 val = enable ? ~0 : 0; 410 u32 val = enable ? ~0 : 0;
429 411
430 switch (win) { 412 switch (win) {
431 case 0: 413 case 0:
432 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP0_ENABLE); 414 mixer_reg_writemask(ctx, MXR_CFG, val, MXR_CFG_GRP0_ENABLE);
433 mixer_reg_writemask(res, MXR_LAYER_CFG, 415 mixer_reg_writemask(ctx, MXR_LAYER_CFG,
434 MXR_LAYER_CFG_GRP0_VAL(priority), 416 MXR_LAYER_CFG_GRP0_VAL(priority),
435 MXR_LAYER_CFG_GRP0_MASK); 417 MXR_LAYER_CFG_GRP0_MASK);
436 break; 418 break;
437 case 1: 419 case 1:
438 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP1_ENABLE); 420 mixer_reg_writemask(ctx, MXR_CFG, val, MXR_CFG_GRP1_ENABLE);
439 mixer_reg_writemask(res, MXR_LAYER_CFG, 421 mixer_reg_writemask(ctx, MXR_LAYER_CFG,
440 MXR_LAYER_CFG_GRP1_VAL(priority), 422 MXR_LAYER_CFG_GRP1_VAL(priority),
441 MXR_LAYER_CFG_GRP1_MASK); 423 MXR_LAYER_CFG_GRP1_MASK);
442 424
443 break; 425 break;
444 case VP_DEFAULT_WIN: 426 case VP_DEFAULT_WIN:
445 if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) { 427 if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) {
446 vp_reg_writemask(res, VP_ENABLE, val, VP_ENABLE_ON); 428 vp_reg_writemask(ctx, VP_ENABLE, val, VP_ENABLE_ON);
447 mixer_reg_writemask(res, MXR_CFG, val, 429 mixer_reg_writemask(ctx, MXR_CFG, val,
448 MXR_CFG_VP_ENABLE); 430 MXR_CFG_VP_ENABLE);
449 mixer_reg_writemask(res, MXR_LAYER_CFG, 431 mixer_reg_writemask(ctx, MXR_LAYER_CFG,
450 MXR_LAYER_CFG_VP_VAL(priority), 432 MXR_LAYER_CFG_VP_VAL(priority),
451 MXR_LAYER_CFG_VP_MASK); 433 MXR_LAYER_CFG_VP_MASK);
452 } 434 }
@@ -456,30 +438,34 @@ static void mixer_cfg_layer(struct mixer_context *ctx, unsigned int win,
456 438
457static void mixer_run(struct mixer_context *ctx) 439static void mixer_run(struct mixer_context *ctx)
458{ 440{
459 struct mixer_resources *res = &ctx->mixer_res; 441 mixer_reg_writemask(ctx, MXR_STATUS, ~0, MXR_STATUS_REG_RUN);
460
461 mixer_reg_writemask(res, MXR_STATUS, ~0, MXR_STATUS_REG_RUN);
462} 442}
463 443
464static void mixer_stop(struct mixer_context *ctx) 444static void mixer_stop(struct mixer_context *ctx)
465{ 445{
466 struct mixer_resources *res = &ctx->mixer_res;
467 int timeout = 20; 446 int timeout = 20;
468 447
469 mixer_reg_writemask(res, MXR_STATUS, 0, MXR_STATUS_REG_RUN); 448 mixer_reg_writemask(ctx, MXR_STATUS, 0, MXR_STATUS_REG_RUN);
470 449
471 while (!(mixer_reg_read(res, MXR_STATUS) & MXR_STATUS_REG_IDLE) && 450 while (!(mixer_reg_read(ctx, MXR_STATUS) & MXR_STATUS_REG_IDLE) &&
472 --timeout) 451 --timeout)
473 usleep_range(10000, 12000); 452 usleep_range(10000, 12000);
474} 453}
475 454
455static void mixer_commit(struct mixer_context *ctx)
456{
457 struct drm_display_mode *mode = &ctx->crtc->base.state->adjusted_mode;
458
459 mixer_cfg_scan(ctx, mode->hdisplay, mode->vdisplay);
460 mixer_cfg_rgb_fmt(ctx, mode->vdisplay);
461 mixer_run(ctx);
462}
463
476static void vp_video_buffer(struct mixer_context *ctx, 464static void vp_video_buffer(struct mixer_context *ctx,
477 struct exynos_drm_plane *plane) 465 struct exynos_drm_plane *plane)
478{ 466{
479 struct exynos_drm_plane_state *state = 467 struct exynos_drm_plane_state *state =
480 to_exynos_plane_state(plane->base.state); 468 to_exynos_plane_state(plane->base.state);
481 struct drm_display_mode *mode = &state->base.crtc->state->adjusted_mode;
482 struct mixer_resources *res = &ctx->mixer_res;
483 struct drm_framebuffer *fb = state->base.fb; 469 struct drm_framebuffer *fb = state->base.fb;
484 unsigned int priority = state->base.normalized_zpos + 1; 470 unsigned int priority = state->base.normalized_zpos + 1;
485 unsigned long flags; 471 unsigned long flags;
@@ -493,8 +479,7 @@ static void vp_video_buffer(struct mixer_context *ctx,
493 luma_addr[0] = exynos_drm_fb_dma_addr(fb, 0); 479 luma_addr[0] = exynos_drm_fb_dma_addr(fb, 0);
494 chroma_addr[0] = exynos_drm_fb_dma_addr(fb, 1); 480 chroma_addr[0] = exynos_drm_fb_dma_addr(fb, 1);
495 481
496 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 482 if (test_bit(MXR_BIT_INTERLACE, &ctx->flags)) {
497 __set_bit(MXR_BIT_INTERLACE, &ctx->flags);
498 if (is_tiled) { 483 if (is_tiled) {
499 luma_addr[1] = luma_addr[0] + 0x40; 484 luma_addr[1] = luma_addr[0] + 0x40;
500 chroma_addr[1] = chroma_addr[0] + 0x40; 485 chroma_addr[1] = chroma_addr[0] + 0x40;
@@ -503,63 +488,59 @@ static void vp_video_buffer(struct mixer_context *ctx,
503 chroma_addr[1] = chroma_addr[0] + fb->pitches[0]; 488 chroma_addr[1] = chroma_addr[0] + fb->pitches[0];
504 } 489 }
505 } else { 490 } else {
506 __clear_bit(MXR_BIT_INTERLACE, &ctx->flags);
507 luma_addr[1] = 0; 491 luma_addr[1] = 0;
508 chroma_addr[1] = 0; 492 chroma_addr[1] = 0;
509 } 493 }
510 494
511 spin_lock_irqsave(&res->reg_slock, flags); 495 spin_lock_irqsave(&ctx->reg_slock, flags);
512 496
513 /* interlace or progressive scan mode */ 497 /* interlace or progressive scan mode */
514 val = (test_bit(MXR_BIT_INTERLACE, &ctx->flags) ? ~0 : 0); 498 val = (test_bit(MXR_BIT_INTERLACE, &ctx->flags) ? ~0 : 0);
515 vp_reg_writemask(res, VP_MODE, val, VP_MODE_LINE_SKIP); 499 vp_reg_writemask(ctx, VP_MODE, val, VP_MODE_LINE_SKIP);
516 500
517 /* setup format */ 501 /* setup format */
518 val = (is_nv21 ? VP_MODE_NV21 : VP_MODE_NV12); 502 val = (is_nv21 ? VP_MODE_NV21 : VP_MODE_NV12);
519 val |= (is_tiled ? VP_MODE_MEM_TILED : VP_MODE_MEM_LINEAR); 503 val |= (is_tiled ? VP_MODE_MEM_TILED : VP_MODE_MEM_LINEAR);
520 vp_reg_writemask(res, VP_MODE, val, VP_MODE_FMT_MASK); 504 vp_reg_writemask(ctx, VP_MODE, val, VP_MODE_FMT_MASK);
521 505
522 /* setting size of input image */ 506 /* setting size of input image */
523 vp_reg_write(res, VP_IMG_SIZE_Y, VP_IMG_HSIZE(fb->pitches[0]) | 507 vp_reg_write(ctx, VP_IMG_SIZE_Y, VP_IMG_HSIZE(fb->pitches[0]) |
524 VP_IMG_VSIZE(fb->height)); 508 VP_IMG_VSIZE(fb->height));
525 /* chroma plane for NV12/NV21 is half the height of the luma plane */ 509 /* chroma plane for NV12/NV21 is half the height of the luma plane */
526 vp_reg_write(res, VP_IMG_SIZE_C, VP_IMG_HSIZE(fb->pitches[0]) | 510 vp_reg_write(ctx, VP_IMG_SIZE_C, VP_IMG_HSIZE(fb->pitches[0]) |
527 VP_IMG_VSIZE(fb->height / 2)); 511 VP_IMG_VSIZE(fb->height / 2));
528 512
529 vp_reg_write(res, VP_SRC_WIDTH, state->src.w); 513 vp_reg_write(ctx, VP_SRC_WIDTH, state->src.w);
530 vp_reg_write(res, VP_SRC_HEIGHT, state->src.h); 514 vp_reg_write(ctx, VP_SRC_HEIGHT, state->src.h);
531 vp_reg_write(res, VP_SRC_H_POSITION, 515 vp_reg_write(ctx, VP_SRC_H_POSITION,
532 VP_SRC_H_POSITION_VAL(state->src.x)); 516 VP_SRC_H_POSITION_VAL(state->src.x));
533 vp_reg_write(res, VP_SRC_V_POSITION, state->src.y); 517 vp_reg_write(ctx, VP_SRC_V_POSITION, state->src.y);
534 518
535 vp_reg_write(res, VP_DST_WIDTH, state->crtc.w); 519 vp_reg_write(ctx, VP_DST_WIDTH, state->crtc.w);
536 vp_reg_write(res, VP_DST_H_POSITION, state->crtc.x); 520 vp_reg_write(ctx, VP_DST_H_POSITION, state->crtc.x);
537 if (test_bit(MXR_BIT_INTERLACE, &ctx->flags)) { 521 if (test_bit(MXR_BIT_INTERLACE, &ctx->flags)) {
538 vp_reg_write(res, VP_DST_HEIGHT, state->crtc.h / 2); 522 vp_reg_write(ctx, VP_DST_HEIGHT, state->crtc.h / 2);
539 vp_reg_write(res, VP_DST_V_POSITION, state->crtc.y / 2); 523 vp_reg_write(ctx, VP_DST_V_POSITION, state->crtc.y / 2);
540 } else { 524 } else {
541 vp_reg_write(res, VP_DST_HEIGHT, state->crtc.h); 525 vp_reg_write(ctx, VP_DST_HEIGHT, state->crtc.h);
542 vp_reg_write(res, VP_DST_V_POSITION, state->crtc.y); 526 vp_reg_write(ctx, VP_DST_V_POSITION, state->crtc.y);
543 } 527 }
544 528
545 vp_reg_write(res, VP_H_RATIO, state->h_ratio); 529 vp_reg_write(ctx, VP_H_RATIO, state->h_ratio);
546 vp_reg_write(res, VP_V_RATIO, state->v_ratio); 530 vp_reg_write(ctx, VP_V_RATIO, state->v_ratio);
547 531
548 vp_reg_write(res, VP_ENDIAN_MODE, VP_ENDIAN_MODE_LITTLE); 532 vp_reg_write(ctx, VP_ENDIAN_MODE, VP_ENDIAN_MODE_LITTLE);
549 533
550 /* set buffer address to vp */ 534 /* set buffer address to vp */
551 vp_reg_write(res, VP_TOP_Y_PTR, luma_addr[0]); 535 vp_reg_write(ctx, VP_TOP_Y_PTR, luma_addr[0]);
552 vp_reg_write(res, VP_BOT_Y_PTR, luma_addr[1]); 536 vp_reg_write(ctx, VP_BOT_Y_PTR, luma_addr[1]);
553 vp_reg_write(res, VP_TOP_C_PTR, chroma_addr[0]); 537 vp_reg_write(ctx, VP_TOP_C_PTR, chroma_addr[0]);
554 vp_reg_write(res, VP_BOT_C_PTR, chroma_addr[1]); 538 vp_reg_write(ctx, VP_BOT_C_PTR, chroma_addr[1]);
555 539
556 mixer_cfg_scan(ctx, mode->vdisplay);
557 mixer_cfg_rgb_fmt(ctx, mode->vdisplay);
558 mixer_cfg_layer(ctx, plane->index, priority, true); 540 mixer_cfg_layer(ctx, plane->index, priority, true);
559 mixer_cfg_vp_blend(ctx); 541 mixer_cfg_vp_blend(ctx);
560 mixer_run(ctx);
561 542
562 spin_unlock_irqrestore(&res->reg_slock, flags); 543 spin_unlock_irqrestore(&ctx->reg_slock, flags);
563 544
564 mixer_regs_dump(ctx); 545 mixer_regs_dump(ctx);
565 vp_regs_dump(ctx); 546 vp_regs_dump(ctx);
@@ -567,9 +548,7 @@ static void vp_video_buffer(struct mixer_context *ctx,
567 548
568static void mixer_layer_update(struct mixer_context *ctx) 549static void mixer_layer_update(struct mixer_context *ctx)
569{ 550{
570 struct mixer_resources *res = &ctx->mixer_res; 551 mixer_reg_writemask(ctx, MXR_CFG, ~0, MXR_CFG_LAYER_UPDATE);
571
572 mixer_reg_writemask(res, MXR_CFG, ~0, MXR_CFG_LAYER_UPDATE);
573} 552}
574 553
575static void mixer_graph_buffer(struct mixer_context *ctx, 554static void mixer_graph_buffer(struct mixer_context *ctx,
@@ -577,8 +556,6 @@ static void mixer_graph_buffer(struct mixer_context *ctx,
577{ 556{
578 struct exynos_drm_plane_state *state = 557 struct exynos_drm_plane_state *state =
579 to_exynos_plane_state(plane->base.state); 558 to_exynos_plane_state(plane->base.state);
580 struct drm_display_mode *mode = &state->base.crtc->state->adjusted_mode;
581 struct mixer_resources *res = &ctx->mixer_res;
582 struct drm_framebuffer *fb = state->base.fb; 559 struct drm_framebuffer *fb = state->base.fb;
583 unsigned int priority = state->base.normalized_zpos + 1; 560 unsigned int priority = state->base.normalized_zpos + 1;
584 unsigned long flags; 561 unsigned long flags;
@@ -623,45 +600,30 @@ static void mixer_graph_buffer(struct mixer_context *ctx,
623 + (state->src.x * fb->format->cpp[0]) 600 + (state->src.x * fb->format->cpp[0])
624 + (state->src.y * fb->pitches[0]); 601 + (state->src.y * fb->pitches[0]);
625 602
626 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 603 spin_lock_irqsave(&ctx->reg_slock, flags);
627 __set_bit(MXR_BIT_INTERLACE, &ctx->flags);
628 else
629 __clear_bit(MXR_BIT_INTERLACE, &ctx->flags);
630
631 spin_lock_irqsave(&res->reg_slock, flags);
632 604
633 /* setup format */ 605 /* setup format */
634 mixer_reg_writemask(res, MXR_GRAPHIC_CFG(win), 606 mixer_reg_writemask(ctx, MXR_GRAPHIC_CFG(win),
635 MXR_GRP_CFG_FORMAT_VAL(fmt), MXR_GRP_CFG_FORMAT_MASK); 607 MXR_GRP_CFG_FORMAT_VAL(fmt), MXR_GRP_CFG_FORMAT_MASK);
636 608
637 /* setup geometry */ 609 /* setup geometry */
638 mixer_reg_write(res, MXR_GRAPHIC_SPAN(win), 610 mixer_reg_write(ctx, MXR_GRAPHIC_SPAN(win),
639 fb->pitches[0] / fb->format->cpp[0]); 611 fb->pitches[0] / fb->format->cpp[0]);
640 612
641 /* setup display size */
642 if (ctx->mxr_ver == MXR_VER_128_0_0_184 &&
643 win == DEFAULT_WIN) {
644 val = MXR_MXR_RES_HEIGHT(mode->vdisplay);
645 val |= MXR_MXR_RES_WIDTH(mode->hdisplay);
646 mixer_reg_write(res, MXR_RESOLUTION, val);
647 }
648
649 val = MXR_GRP_WH_WIDTH(state->src.w); 613 val = MXR_GRP_WH_WIDTH(state->src.w);
650 val |= MXR_GRP_WH_HEIGHT(state->src.h); 614 val |= MXR_GRP_WH_HEIGHT(state->src.h);
651 val |= MXR_GRP_WH_H_SCALE(x_ratio); 615 val |= MXR_GRP_WH_H_SCALE(x_ratio);
652 val |= MXR_GRP_WH_V_SCALE(y_ratio); 616 val |= MXR_GRP_WH_V_SCALE(y_ratio);
653 mixer_reg_write(res, MXR_GRAPHIC_WH(win), val); 617 mixer_reg_write(ctx, MXR_GRAPHIC_WH(win), val);
654 618
655 /* setup offsets in display image */ 619 /* setup offsets in display image */
656 val = MXR_GRP_DXY_DX(dst_x_offset); 620 val = MXR_GRP_DXY_DX(dst_x_offset);
657 val |= MXR_GRP_DXY_DY(dst_y_offset); 621 val |= MXR_GRP_DXY_DY(dst_y_offset);
658 mixer_reg_write(res, MXR_GRAPHIC_DXY(win), val); 622 mixer_reg_write(ctx, MXR_GRAPHIC_DXY(win), val);
659 623
660 /* set buffer address to mixer */ 624 /* set buffer address to mixer */
661 mixer_reg_write(res, MXR_GRAPHIC_BASE(win), dma_addr); 625 mixer_reg_write(ctx, MXR_GRAPHIC_BASE(win), dma_addr);
662 626
663 mixer_cfg_scan(ctx, mode->vdisplay);
664 mixer_cfg_rgb_fmt(ctx, mode->vdisplay);
665 mixer_cfg_layer(ctx, win, priority, true); 627 mixer_cfg_layer(ctx, win, priority, true);
666 mixer_cfg_gfx_blend(ctx, win, is_alpha_format(fb->format->format)); 628 mixer_cfg_gfx_blend(ctx, win, is_alpha_format(fb->format->format));
667 629
@@ -670,22 +632,19 @@ static void mixer_graph_buffer(struct mixer_context *ctx,
670 ctx->mxr_ver == MXR_VER_128_0_0_184) 632 ctx->mxr_ver == MXR_VER_128_0_0_184)
671 mixer_layer_update(ctx); 633 mixer_layer_update(ctx);
672 634
673 mixer_run(ctx); 635 spin_unlock_irqrestore(&ctx->reg_slock, flags);
674
675 spin_unlock_irqrestore(&res->reg_slock, flags);
676 636
677 mixer_regs_dump(ctx); 637 mixer_regs_dump(ctx);
678} 638}
679 639
680static void vp_win_reset(struct mixer_context *ctx) 640static void vp_win_reset(struct mixer_context *ctx)
681{ 641{
682 struct mixer_resources *res = &ctx->mixer_res;
683 unsigned int tries = 100; 642 unsigned int tries = 100;
684 643
685 vp_reg_write(res, VP_SRESET, VP_SRESET_PROCESSING); 644 vp_reg_write(ctx, VP_SRESET, VP_SRESET_PROCESSING);
686 while (--tries) { 645 while (--tries) {
687 /* waiting until VP_SRESET_PROCESSING is 0 */ 646 /* waiting until VP_SRESET_PROCESSING is 0 */
688 if (~vp_reg_read(res, VP_SRESET) & VP_SRESET_PROCESSING) 647 if (~vp_reg_read(ctx, VP_SRESET) & VP_SRESET_PROCESSING)
689 break; 648 break;
690 mdelay(10); 649 mdelay(10);
691 } 650 }
@@ -694,57 +653,55 @@ static void vp_win_reset(struct mixer_context *ctx)
694 653
695static void mixer_win_reset(struct mixer_context *ctx) 654static void mixer_win_reset(struct mixer_context *ctx)
696{ 655{
697 struct mixer_resources *res = &ctx->mixer_res;
698 unsigned long flags; 656 unsigned long flags;
699 657
700 spin_lock_irqsave(&res->reg_slock, flags); 658 spin_lock_irqsave(&ctx->reg_slock, flags);
701 659
702 mixer_reg_writemask(res, MXR_CFG, MXR_CFG_DST_HDMI, MXR_CFG_DST_MASK); 660 mixer_reg_writemask(ctx, MXR_CFG, MXR_CFG_DST_HDMI, MXR_CFG_DST_MASK);
703 661
704 /* set output in RGB888 mode */ 662 /* set output in RGB888 mode */
705 mixer_reg_writemask(res, MXR_CFG, MXR_CFG_OUT_RGB888, MXR_CFG_OUT_MASK); 663 mixer_reg_writemask(ctx, MXR_CFG, MXR_CFG_OUT_RGB888, MXR_CFG_OUT_MASK);
706 664
707 /* 16 beat burst in DMA */ 665 /* 16 beat burst in DMA */
708 mixer_reg_writemask(res, MXR_STATUS, MXR_STATUS_16_BURST, 666 mixer_reg_writemask(ctx, MXR_STATUS, MXR_STATUS_16_BURST,
709 MXR_STATUS_BURST_MASK); 667 MXR_STATUS_BURST_MASK);
710 668
711 /* reset default layer priority */ 669 /* reset default layer priority */
712 mixer_reg_write(res, MXR_LAYER_CFG, 0); 670 mixer_reg_write(ctx, MXR_LAYER_CFG, 0);
713 671
714 /* set all background colors to RGB (0,0,0) */ 672 /* set all background colors to RGB (0,0,0) */
715 mixer_reg_write(res, MXR_BG_COLOR0, MXR_YCBCR_VAL(0, 128, 128)); 673 mixer_reg_write(ctx, MXR_BG_COLOR0, MXR_YCBCR_VAL(0, 128, 128));
716 mixer_reg_write(res, MXR_BG_COLOR1, MXR_YCBCR_VAL(0, 128, 128)); 674 mixer_reg_write(ctx, MXR_BG_COLOR1, MXR_YCBCR_VAL(0, 128, 128));
717 mixer_reg_write(res, MXR_BG_COLOR2, MXR_YCBCR_VAL(0, 128, 128)); 675 mixer_reg_write(ctx, MXR_BG_COLOR2, MXR_YCBCR_VAL(0, 128, 128));
718 676
719 if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) { 677 if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) {
720 /* configuration of Video Processor Registers */ 678 /* configuration of Video Processor Registers */
721 vp_win_reset(ctx); 679 vp_win_reset(ctx);
722 vp_default_filter(res); 680 vp_default_filter(ctx);
723 } 681 }
724 682
725 /* disable all layers */ 683 /* disable all layers */
726 mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP0_ENABLE); 684 mixer_reg_writemask(ctx, MXR_CFG, 0, MXR_CFG_GRP0_ENABLE);
727 mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP1_ENABLE); 685 mixer_reg_writemask(ctx, MXR_CFG, 0, MXR_CFG_GRP1_ENABLE);
728 if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) 686 if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags))
729 mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_VP_ENABLE); 687 mixer_reg_writemask(ctx, MXR_CFG, 0, MXR_CFG_VP_ENABLE);
730 688
731 /* set all source image offsets to zero */ 689 /* set all source image offsets to zero */
732 mixer_reg_write(res, MXR_GRAPHIC_SXY(0), 0); 690 mixer_reg_write(ctx, MXR_GRAPHIC_SXY(0), 0);
733 mixer_reg_write(res, MXR_GRAPHIC_SXY(1), 0); 691 mixer_reg_write(ctx, MXR_GRAPHIC_SXY(1), 0);
734 692
735 spin_unlock_irqrestore(&res->reg_slock, flags); 693 spin_unlock_irqrestore(&ctx->reg_slock, flags);
736} 694}
737 695
738static irqreturn_t mixer_irq_handler(int irq, void *arg) 696static irqreturn_t mixer_irq_handler(int irq, void *arg)
739{ 697{
740 struct mixer_context *ctx = arg; 698 struct mixer_context *ctx = arg;
741 struct mixer_resources *res = &ctx->mixer_res;
742 u32 val, base, shadow; 699 u32 val, base, shadow;
743 700
744 spin_lock(&res->reg_slock); 701 spin_lock(&ctx->reg_slock);
745 702
746 /* read interrupt status for handling and clearing flags for VSYNC */ 703 /* read interrupt status for handling and clearing flags for VSYNC */
747 val = mixer_reg_read(res, MXR_INT_STATUS); 704 val = mixer_reg_read(ctx, MXR_INT_STATUS);
748 705
749 /* handling VSYNC */ 706 /* handling VSYNC */
750 if (val & MXR_INT_STATUS_VSYNC) { 707 if (val & MXR_INT_STATUS_VSYNC) {
@@ -754,13 +711,13 @@ static irqreturn_t mixer_irq_handler(int irq, void *arg)
754 711
755 /* interlace scan need to check shadow register */ 712 /* interlace scan need to check shadow register */
756 if (test_bit(MXR_BIT_INTERLACE, &ctx->flags)) { 713 if (test_bit(MXR_BIT_INTERLACE, &ctx->flags)) {
757 base = mixer_reg_read(res, MXR_GRAPHIC_BASE(0)); 714 base = mixer_reg_read(ctx, MXR_GRAPHIC_BASE(0));
758 shadow = mixer_reg_read(res, MXR_GRAPHIC_BASE_S(0)); 715 shadow = mixer_reg_read(ctx, MXR_GRAPHIC_BASE_S(0));
759 if (base != shadow) 716 if (base != shadow)
760 goto out; 717 goto out;
761 718
762 base = mixer_reg_read(res, MXR_GRAPHIC_BASE(1)); 719 base = mixer_reg_read(ctx, MXR_GRAPHIC_BASE(1));
763 shadow = mixer_reg_read(res, MXR_GRAPHIC_BASE_S(1)); 720 shadow = mixer_reg_read(ctx, MXR_GRAPHIC_BASE_S(1));
764 if (base != shadow) 721 if (base != shadow)
765 goto out; 722 goto out;
766 } 723 }
@@ -770,9 +727,9 @@ static irqreturn_t mixer_irq_handler(int irq, void *arg)
770 727
771out: 728out:
772 /* clear interrupts */ 729 /* clear interrupts */
773 mixer_reg_write(res, MXR_INT_STATUS, val); 730 mixer_reg_write(ctx, MXR_INT_STATUS, val);
774 731
775 spin_unlock(&res->reg_slock); 732 spin_unlock(&ctx->reg_slock);
776 733
777 return IRQ_HANDLED; 734 return IRQ_HANDLED;
778} 735}
@@ -780,26 +737,25 @@ out:
780static int mixer_resources_init(struct mixer_context *mixer_ctx) 737static int mixer_resources_init(struct mixer_context *mixer_ctx)
781{ 738{
782 struct device *dev = &mixer_ctx->pdev->dev; 739 struct device *dev = &mixer_ctx->pdev->dev;
783 struct mixer_resources *mixer_res = &mixer_ctx->mixer_res;
784 struct resource *res; 740 struct resource *res;
785 int ret; 741 int ret;
786 742
787 spin_lock_init(&mixer_res->reg_slock); 743 spin_lock_init(&mixer_ctx->reg_slock);
788 744
789 mixer_res->mixer = devm_clk_get(dev, "mixer"); 745 mixer_ctx->mixer = devm_clk_get(dev, "mixer");
790 if (IS_ERR(mixer_res->mixer)) { 746 if (IS_ERR(mixer_ctx->mixer)) {
791 dev_err(dev, "failed to get clock 'mixer'\n"); 747 dev_err(dev, "failed to get clock 'mixer'\n");
792 return -ENODEV; 748 return -ENODEV;
793 } 749 }
794 750
795 mixer_res->hdmi = devm_clk_get(dev, "hdmi"); 751 mixer_ctx->hdmi = devm_clk_get(dev, "hdmi");
796 if (IS_ERR(mixer_res->hdmi)) { 752 if (IS_ERR(mixer_ctx->hdmi)) {
797 dev_err(dev, "failed to get clock 'hdmi'\n"); 753 dev_err(dev, "failed to get clock 'hdmi'\n");
798 return PTR_ERR(mixer_res->hdmi); 754 return PTR_ERR(mixer_ctx->hdmi);
799 } 755 }
800 756
801 mixer_res->sclk_hdmi = devm_clk_get(dev, "sclk_hdmi"); 757 mixer_ctx->sclk_hdmi = devm_clk_get(dev, "sclk_hdmi");
802 if (IS_ERR(mixer_res->sclk_hdmi)) { 758 if (IS_ERR(mixer_ctx->sclk_hdmi)) {
803 dev_err(dev, "failed to get clock 'sclk_hdmi'\n"); 759 dev_err(dev, "failed to get clock 'sclk_hdmi'\n");
804 return -ENODEV; 760 return -ENODEV;
805 } 761 }
@@ -809,9 +765,9 @@ static int mixer_resources_init(struct mixer_context *mixer_ctx)
809 return -ENXIO; 765 return -ENXIO;
810 } 766 }
811 767
812 mixer_res->mixer_regs = devm_ioremap(dev, res->start, 768 mixer_ctx->mixer_regs = devm_ioremap(dev, res->start,
813 resource_size(res)); 769 resource_size(res));
814 if (mixer_res->mixer_regs == NULL) { 770 if (mixer_ctx->mixer_regs == NULL) {
815 dev_err(dev, "register mapping failed.\n"); 771 dev_err(dev, "register mapping failed.\n");
816 return -ENXIO; 772 return -ENXIO;
817 } 773 }
@@ -828,7 +784,7 @@ static int mixer_resources_init(struct mixer_context *mixer_ctx)
828 dev_err(dev, "request interrupt failed.\n"); 784 dev_err(dev, "request interrupt failed.\n");
829 return ret; 785 return ret;
830 } 786 }
831 mixer_res->irq = res->start; 787 mixer_ctx->irq = res->start;
832 788
833 return 0; 789 return 0;
834} 790}
@@ -836,30 +792,29 @@ static int mixer_resources_init(struct mixer_context *mixer_ctx)
836static int vp_resources_init(struct mixer_context *mixer_ctx) 792static int vp_resources_init(struct mixer_context *mixer_ctx)
837{ 793{
838 struct device *dev = &mixer_ctx->pdev->dev; 794 struct device *dev = &mixer_ctx->pdev->dev;
839 struct mixer_resources *mixer_res = &mixer_ctx->mixer_res;
840 struct resource *res; 795 struct resource *res;
841 796
842 mixer_res->vp = devm_clk_get(dev, "vp"); 797 mixer_ctx->vp = devm_clk_get(dev, "vp");
843 if (IS_ERR(mixer_res->vp)) { 798 if (IS_ERR(mixer_ctx->vp)) {
844 dev_err(dev, "failed to get clock 'vp'\n"); 799 dev_err(dev, "failed to get clock 'vp'\n");
845 return -ENODEV; 800 return -ENODEV;
846 } 801 }
847 802
848 if (test_bit(MXR_BIT_HAS_SCLK, &mixer_ctx->flags)) { 803 if (test_bit(MXR_BIT_HAS_SCLK, &mixer_ctx->flags)) {
849 mixer_res->sclk_mixer = devm_clk_get(dev, "sclk_mixer"); 804 mixer_ctx->sclk_mixer = devm_clk_get(dev, "sclk_mixer");
850 if (IS_ERR(mixer_res->sclk_mixer)) { 805 if (IS_ERR(mixer_ctx->sclk_mixer)) {
851 dev_err(dev, "failed to get clock 'sclk_mixer'\n"); 806 dev_err(dev, "failed to get clock 'sclk_mixer'\n");
852 return -ENODEV; 807 return -ENODEV;
853 } 808 }
854 mixer_res->mout_mixer = devm_clk_get(dev, "mout_mixer"); 809 mixer_ctx->mout_mixer = devm_clk_get(dev, "mout_mixer");
855 if (IS_ERR(mixer_res->mout_mixer)) { 810 if (IS_ERR(mixer_ctx->mout_mixer)) {
856 dev_err(dev, "failed to get clock 'mout_mixer'\n"); 811 dev_err(dev, "failed to get clock 'mout_mixer'\n");
857 return -ENODEV; 812 return -ENODEV;
858 } 813 }
859 814
860 if (mixer_res->sclk_hdmi && mixer_res->mout_mixer) 815 if (mixer_ctx->sclk_hdmi && mixer_ctx->mout_mixer)
861 clk_set_parent(mixer_res->mout_mixer, 816 clk_set_parent(mixer_ctx->mout_mixer,
862 mixer_res->sclk_hdmi); 817 mixer_ctx->sclk_hdmi);
863 } 818 }
864 819
865 res = platform_get_resource(mixer_ctx->pdev, IORESOURCE_MEM, 1); 820 res = platform_get_resource(mixer_ctx->pdev, IORESOURCE_MEM, 1);
@@ -868,9 +823,9 @@ static int vp_resources_init(struct mixer_context *mixer_ctx)
868 return -ENXIO; 823 return -ENXIO;
869 } 824 }
870 825
871 mixer_res->vp_regs = devm_ioremap(dev, res->start, 826 mixer_ctx->vp_regs = devm_ioremap(dev, res->start,
872 resource_size(res)); 827 resource_size(res));
873 if (mixer_res->vp_regs == NULL) { 828 if (mixer_ctx->vp_regs == NULL) {
874 dev_err(dev, "register mapping failed.\n"); 829 dev_err(dev, "register mapping failed.\n");
875 return -ENXIO; 830 return -ENXIO;
876 } 831 }
@@ -914,15 +869,14 @@ static void mixer_ctx_remove(struct mixer_context *mixer_ctx)
914static int mixer_enable_vblank(struct exynos_drm_crtc *crtc) 869static int mixer_enable_vblank(struct exynos_drm_crtc *crtc)
915{ 870{
916 struct mixer_context *mixer_ctx = crtc->ctx; 871 struct mixer_context *mixer_ctx = crtc->ctx;
917 struct mixer_resources *res = &mixer_ctx->mixer_res;
918 872
919 __set_bit(MXR_BIT_VSYNC, &mixer_ctx->flags); 873 __set_bit(MXR_BIT_VSYNC, &mixer_ctx->flags);
920 if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags)) 874 if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags))
921 return 0; 875 return 0;
922 876
923 /* enable vsync interrupt */ 877 /* enable vsync interrupt */
924 mixer_reg_writemask(res, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC); 878 mixer_reg_writemask(mixer_ctx, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC);
925 mixer_reg_writemask(res, MXR_INT_EN, ~0, MXR_INT_EN_VSYNC); 879 mixer_reg_writemask(mixer_ctx, MXR_INT_EN, ~0, MXR_INT_EN_VSYNC);
926 880
927 return 0; 881 return 0;
928} 882}
@@ -930,7 +884,6 @@ static int mixer_enable_vblank(struct exynos_drm_crtc *crtc)
930static void mixer_disable_vblank(struct exynos_drm_crtc *crtc) 884static void mixer_disable_vblank(struct exynos_drm_crtc *crtc)
931{ 885{
932 struct mixer_context *mixer_ctx = crtc->ctx; 886 struct mixer_context *mixer_ctx = crtc->ctx;
933 struct mixer_resources *res = &mixer_ctx->mixer_res;
934 887
935 __clear_bit(MXR_BIT_VSYNC, &mixer_ctx->flags); 888 __clear_bit(MXR_BIT_VSYNC, &mixer_ctx->flags);
936 889
@@ -938,8 +891,8 @@ static void mixer_disable_vblank(struct exynos_drm_crtc *crtc)
938 return; 891 return;
939 892
940 /* disable vsync interrupt */ 893 /* disable vsync interrupt */
941 mixer_reg_writemask(res, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC); 894 mixer_reg_writemask(mixer_ctx, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC);
942 mixer_reg_writemask(res, MXR_INT_EN, 0, MXR_INT_EN_VSYNC); 895 mixer_reg_writemask(mixer_ctx, MXR_INT_EN, 0, MXR_INT_EN_VSYNC);
943} 896}
944 897
945static void mixer_atomic_begin(struct exynos_drm_crtc *crtc) 898static void mixer_atomic_begin(struct exynos_drm_crtc *crtc)
@@ -972,7 +925,6 @@ static void mixer_disable_plane(struct exynos_drm_crtc *crtc,
972 struct exynos_drm_plane *plane) 925 struct exynos_drm_plane *plane)
973{ 926{
974 struct mixer_context *mixer_ctx = crtc->ctx; 927 struct mixer_context *mixer_ctx = crtc->ctx;
975 struct mixer_resources *res = &mixer_ctx->mixer_res;
976 unsigned long flags; 928 unsigned long flags;
977 929
978 DRM_DEBUG_KMS("win: %d\n", plane->index); 930 DRM_DEBUG_KMS("win: %d\n", plane->index);
@@ -980,9 +932,9 @@ static void mixer_disable_plane(struct exynos_drm_crtc *crtc,
980 if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags)) 932 if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags))
981 return; 933 return;
982 934
983 spin_lock_irqsave(&res->reg_slock, flags); 935 spin_lock_irqsave(&mixer_ctx->reg_slock, flags);
984 mixer_cfg_layer(mixer_ctx, plane->index, 0, false); 936 mixer_cfg_layer(mixer_ctx, plane->index, 0, false);
985 spin_unlock_irqrestore(&res->reg_slock, flags); 937 spin_unlock_irqrestore(&mixer_ctx->reg_slock, flags);
986} 938}
987 939
988static void mixer_atomic_flush(struct exynos_drm_crtc *crtc) 940static void mixer_atomic_flush(struct exynos_drm_crtc *crtc)
@@ -999,7 +951,6 @@ static void mixer_atomic_flush(struct exynos_drm_crtc *crtc)
999static void mixer_enable(struct exynos_drm_crtc *crtc) 951static void mixer_enable(struct exynos_drm_crtc *crtc)
1000{ 952{
1001 struct mixer_context *ctx = crtc->ctx; 953 struct mixer_context *ctx = crtc->ctx;
1002 struct mixer_resources *res = &ctx->mixer_res;
1003 954
1004 if (test_bit(MXR_BIT_POWERED, &ctx->flags)) 955 if (test_bit(MXR_BIT_POWERED, &ctx->flags))
1005 return; 956 return;
@@ -1010,14 +961,17 @@ static void mixer_enable(struct exynos_drm_crtc *crtc)
1010 961
1011 mixer_vsync_set_update(ctx, false); 962 mixer_vsync_set_update(ctx, false);
1012 963
1013 mixer_reg_writemask(res, MXR_STATUS, ~0, MXR_STATUS_SOFT_RESET); 964 mixer_reg_writemask(ctx, MXR_STATUS, ~0, MXR_STATUS_SOFT_RESET);
1014 965
1015 if (test_bit(MXR_BIT_VSYNC, &ctx->flags)) { 966 if (test_bit(MXR_BIT_VSYNC, &ctx->flags)) {
1016 mixer_reg_writemask(res, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC); 967 mixer_reg_writemask(ctx, MXR_INT_STATUS, ~0,
1017 mixer_reg_writemask(res, MXR_INT_EN, ~0, MXR_INT_EN_VSYNC); 968 MXR_INT_CLEAR_VSYNC);
969 mixer_reg_writemask(ctx, MXR_INT_EN, ~0, MXR_INT_EN_VSYNC);
1018 } 970 }
1019 mixer_win_reset(ctx); 971 mixer_win_reset(ctx);
1020 972
973 mixer_commit(ctx);
974
1021 mixer_vsync_set_update(ctx, true); 975 mixer_vsync_set_update(ctx, true);
1022 976
1023 set_bit(MXR_BIT_POWERED, &ctx->flags); 977 set_bit(MXR_BIT_POWERED, &ctx->flags);
@@ -1044,26 +998,75 @@ static void mixer_disable(struct exynos_drm_crtc *crtc)
1044 clear_bit(MXR_BIT_POWERED, &ctx->flags); 998 clear_bit(MXR_BIT_POWERED, &ctx->flags);
1045} 999}
1046 1000
1047/* Only valid for Mixer version 16.0.33.0 */ 1001static int mixer_mode_valid(struct exynos_drm_crtc *crtc,
1048static int mixer_atomic_check(struct exynos_drm_crtc *crtc, 1002 const struct drm_display_mode *mode)
1049 struct drm_crtc_state *state)
1050{ 1003{
1051 struct drm_display_mode *mode = &state->adjusted_mode; 1004 struct mixer_context *ctx = crtc->ctx;
1052 u32 w, h; 1005 u32 w = mode->hdisplay, h = mode->vdisplay;
1053 1006
1054 w = mode->hdisplay; 1007 DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%d\n", w, h,
1055 h = mode->vdisplay; 1008 mode->vrefresh, !!(mode->flags & DRM_MODE_FLAG_INTERLACE));
1056 1009
1057 DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%d\n", 1010 if (ctx->mxr_ver == MXR_VER_128_0_0_184)
1058 mode->hdisplay, mode->vdisplay, mode->vrefresh, 1011 return MODE_OK;
1059 (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0);
1060 1012
1061 if ((w >= 464 && w <= 720 && h >= 261 && h <= 576) || 1013 if ((w >= 464 && w <= 720 && h >= 261 && h <= 576) ||
1062 (w >= 1024 && w <= 1280 && h >= 576 && h <= 720) || 1014 (w >= 1024 && w <= 1280 && h >= 576 && h <= 720) ||
1063 (w >= 1664 && w <= 1920 && h >= 936 && h <= 1080)) 1015 (w >= 1664 && w <= 1920 && h >= 936 && h <= 1080))
1064 return 0; 1016 return MODE_OK;
1017
1018 if ((w == 1024 && h == 768) ||
1019 (w == 1366 && h == 768) ||
1020 (w == 1280 && h == 1024))
1021 return MODE_OK;
1022
1023 return MODE_BAD;
1024}
1025
1026static bool mixer_mode_fixup(struct exynos_drm_crtc *crtc,
1027 const struct drm_display_mode *mode,
1028 struct drm_display_mode *adjusted_mode)
1029{
1030 struct mixer_context *ctx = crtc->ctx;
1031 int width = mode->hdisplay, height = mode->vdisplay, i;
1032
1033 struct {
1034 int hdisplay, vdisplay, htotal, vtotal, scan_val;
1035 } static const modes[] = {
1036 { 720, 480, 858, 525, MXR_CFG_SCAN_NTSC | MXR_CFG_SCAN_SD },
1037 { 720, 576, 864, 625, MXR_CFG_SCAN_PAL | MXR_CFG_SCAN_SD },
1038 { 1280, 720, 1650, 750, MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD },
1039 { 1920, 1080, 2200, 1125, MXR_CFG_SCAN_HD_1080 |
1040 MXR_CFG_SCAN_HD }
1041 };
1042
1043 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1044 __set_bit(MXR_BIT_INTERLACE, &ctx->flags);
1045 else
1046 __clear_bit(MXR_BIT_INTERLACE, &ctx->flags);
1047
1048 if (ctx->mxr_ver == MXR_VER_128_0_0_184)
1049 return true;
1050
1051 for (i = 0; i < ARRAY_SIZE(modes); ++i)
1052 if (width <= modes[i].hdisplay && height <= modes[i].vdisplay) {
1053 ctx->scan_value = modes[i].scan_val;
1054 if (width < modes[i].hdisplay ||
1055 height < modes[i].vdisplay) {
1056 adjusted_mode->hdisplay = modes[i].hdisplay;
1057 adjusted_mode->hsync_start = modes[i].hdisplay;
1058 adjusted_mode->hsync_end = modes[i].htotal;
1059 adjusted_mode->htotal = modes[i].htotal;
1060 adjusted_mode->vdisplay = modes[i].vdisplay;
1061 adjusted_mode->vsync_start = modes[i].vdisplay;
1062 adjusted_mode->vsync_end = modes[i].vtotal;
1063 adjusted_mode->vtotal = modes[i].vtotal;
1064 }
1065
1066 return true;
1067 }
1065 1068
1066 return -EINVAL; 1069 return false;
1067} 1070}
1068 1071
1069static const struct exynos_drm_crtc_ops mixer_crtc_ops = { 1072static const struct exynos_drm_crtc_ops mixer_crtc_ops = {
@@ -1075,7 +1078,8 @@ static const struct exynos_drm_crtc_ops mixer_crtc_ops = {
1075 .update_plane = mixer_update_plane, 1078 .update_plane = mixer_update_plane,
1076 .disable_plane = mixer_disable_plane, 1079 .disable_plane = mixer_disable_plane,
1077 .atomic_flush = mixer_atomic_flush, 1080 .atomic_flush = mixer_atomic_flush,
1078 .atomic_check = mixer_atomic_check, 1081 .mode_valid = mixer_mode_valid,
1082 .mode_fixup = mixer_mode_fixup,
1079}; 1083};
1080 1084
1081static const struct mixer_drv_data exynos5420_mxr_drv_data = { 1085static const struct mixer_drv_data exynos5420_mxr_drv_data = {
@@ -1217,14 +1221,13 @@ static int mixer_remove(struct platform_device *pdev)
1217static int __maybe_unused exynos_mixer_suspend(struct device *dev) 1221static int __maybe_unused exynos_mixer_suspend(struct device *dev)
1218{ 1222{
1219 struct mixer_context *ctx = dev_get_drvdata(dev); 1223 struct mixer_context *ctx = dev_get_drvdata(dev);
1220 struct mixer_resources *res = &ctx->mixer_res;
1221 1224
1222 clk_disable_unprepare(res->hdmi); 1225 clk_disable_unprepare(ctx->hdmi);
1223 clk_disable_unprepare(res->mixer); 1226 clk_disable_unprepare(ctx->mixer);
1224 if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) { 1227 if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) {
1225 clk_disable_unprepare(res->vp); 1228 clk_disable_unprepare(ctx->vp);
1226 if (test_bit(MXR_BIT_HAS_SCLK, &ctx->flags)) 1229 if (test_bit(MXR_BIT_HAS_SCLK, &ctx->flags))
1227 clk_disable_unprepare(res->sclk_mixer); 1230 clk_disable_unprepare(ctx->sclk_mixer);
1228 } 1231 }
1229 1232
1230 return 0; 1233 return 0;
@@ -1233,28 +1236,27 @@ static int __maybe_unused exynos_mixer_suspend(struct device *dev)
1233static int __maybe_unused exynos_mixer_resume(struct device *dev) 1236static int __maybe_unused exynos_mixer_resume(struct device *dev)
1234{ 1237{
1235 struct mixer_context *ctx = dev_get_drvdata(dev); 1238 struct mixer_context *ctx = dev_get_drvdata(dev);
1236 struct mixer_resources *res = &ctx->mixer_res;
1237 int ret; 1239 int ret;
1238 1240
1239 ret = clk_prepare_enable(res->mixer); 1241 ret = clk_prepare_enable(ctx->mixer);
1240 if (ret < 0) { 1242 if (ret < 0) {
1241 DRM_ERROR("Failed to prepare_enable the mixer clk [%d]\n", ret); 1243 DRM_ERROR("Failed to prepare_enable the mixer clk [%d]\n", ret);
1242 return ret; 1244 return ret;
1243 } 1245 }
1244 ret = clk_prepare_enable(res->hdmi); 1246 ret = clk_prepare_enable(ctx->hdmi);
1245 if (ret < 0) { 1247 if (ret < 0) {
1246 DRM_ERROR("Failed to prepare_enable the hdmi clk [%d]\n", ret); 1248 DRM_ERROR("Failed to prepare_enable the hdmi clk [%d]\n", ret);
1247 return ret; 1249 return ret;
1248 } 1250 }
1249 if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) { 1251 if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) {
1250 ret = clk_prepare_enable(res->vp); 1252 ret = clk_prepare_enable(ctx->vp);
1251 if (ret < 0) { 1253 if (ret < 0) {
1252 DRM_ERROR("Failed to prepare_enable the vp clk [%d]\n", 1254 DRM_ERROR("Failed to prepare_enable the vp clk [%d]\n",
1253 ret); 1255 ret);
1254 return ret; 1256 return ret;
1255 } 1257 }
1256 if (test_bit(MXR_BIT_HAS_SCLK, &ctx->flags)) { 1258 if (test_bit(MXR_BIT_HAS_SCLK, &ctx->flags)) {
1257 ret = clk_prepare_enable(res->sclk_mixer); 1259 ret = clk_prepare_enable(ctx->sclk_mixer);
1258 if (ret < 0) { 1260 if (ret < 0) {
1259 DRM_ERROR("Failed to prepare_enable the " \ 1261 DRM_ERROR("Failed to prepare_enable the " \
1260 "sclk_mixer clk [%d]\n", 1262 "sclk_mixer clk [%d]\n",
diff --git a/drivers/gpu/drm/exynos/regs-hdmi.h b/drivers/gpu/drm/exynos/regs-hdmi.h
index a0507dc18d9e..04be0f7e8193 100644
--- a/drivers/gpu/drm/exynos/regs-hdmi.h
+++ b/drivers/gpu/drm/exynos/regs-hdmi.h
@@ -419,11 +419,9 @@
419#define HDMI_I2S_DSD_CON HDMI_I2S_BASE(0x01c) 419#define HDMI_I2S_DSD_CON HDMI_I2S_BASE(0x01c)
420#define HDMI_I2S_MUX_CON HDMI_I2S_BASE(0x020) 420#define HDMI_I2S_MUX_CON HDMI_I2S_BASE(0x020)
421#define HDMI_I2S_CH_ST_CON HDMI_I2S_BASE(0x024) 421#define HDMI_I2S_CH_ST_CON HDMI_I2S_BASE(0x024)
422#define HDMI_I2S_CH_ST_0 HDMI_I2S_BASE(0x028) 422/* n must be within range 0...(HDMI_I2S_CH_ST_MAXNUM - 1) */
423#define HDMI_I2S_CH_ST_1 HDMI_I2S_BASE(0x02c) 423#define HDMI_I2S_CH_ST_MAXNUM 5
424#define HDMI_I2S_CH_ST_2 HDMI_I2S_BASE(0x030) 424#define HDMI_I2S_CH_ST(n) HDMI_I2S_BASE(0x028 + 4 * (n))
425#define HDMI_I2S_CH_ST_3 HDMI_I2S_BASE(0x034)
426#define HDMI_I2S_CH_ST_4 HDMI_I2S_BASE(0x038)
427#define HDMI_I2S_CH_ST_SH_0 HDMI_I2S_BASE(0x03c) 425#define HDMI_I2S_CH_ST_SH_0 HDMI_I2S_BASE(0x03c)
428#define HDMI_I2S_CH_ST_SH_1 HDMI_I2S_BASE(0x040) 426#define HDMI_I2S_CH_ST_SH_1 HDMI_I2S_BASE(0x040)
429#define HDMI_I2S_CH_ST_SH_2 HDMI_I2S_BASE(0x044) 427#define HDMI_I2S_CH_ST_SH_2 HDMI_I2S_BASE(0x044)
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
index 58e9e0601a61..faf17b83b910 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
@@ -210,7 +210,6 @@ static int fsl_dcu_drm_pm_suspend(struct device *dev)
210 return PTR_ERR(fsl_dev->state); 210 return PTR_ERR(fsl_dev->state);
211 } 211 }
212 212
213 clk_disable_unprepare(fsl_dev->pix_clk);
214 clk_disable_unprepare(fsl_dev->clk); 213 clk_disable_unprepare(fsl_dev->clk);
215 214
216 return 0; 215 return 0;
@@ -233,6 +232,7 @@ static int fsl_dcu_drm_pm_resume(struct device *dev)
233 if (fsl_dev->tcon) 232 if (fsl_dev->tcon)
234 fsl_tcon_bypass_enable(fsl_dev->tcon); 233 fsl_tcon_bypass_enable(fsl_dev->tcon);
235 fsl_dcu_drm_init_planes(fsl_dev->drm); 234 fsl_dcu_drm_init_planes(fsl_dev->drm);
235 enable_irq(fsl_dev->irq);
236 drm_atomic_helper_resume(fsl_dev->drm, fsl_dev->state); 236 drm_atomic_helper_resume(fsl_dev->drm, fsl_dev->state);
237 237
238 console_lock(); 238 console_lock();
@@ -240,7 +240,6 @@ static int fsl_dcu_drm_pm_resume(struct device *dev)
240 console_unlock(); 240 console_unlock();
241 241
242 drm_kms_helper_poll_enable(fsl_dev->drm); 242 drm_kms_helper_poll_enable(fsl_dev->drm);
243 enable_irq(fsl_dev->irq);
244 243
245 return 0; 244 return 0;
246} 245}
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
index edd7d8127d19..c54806d08dd7 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
@@ -102,7 +102,6 @@ static int fsl_dcu_attach_panel(struct fsl_dcu_drm_device *fsl_dev,
102{ 102{
103 struct drm_encoder *encoder = &fsl_dev->encoder; 103 struct drm_encoder *encoder = &fsl_dev->encoder;
104 struct drm_connector *connector = &fsl_dev->connector.base; 104 struct drm_connector *connector = &fsl_dev->connector.base;
105 struct drm_mode_config *mode_config = &fsl_dev->drm->mode_config;
106 int ret; 105 int ret;
107 106
108 fsl_dev->connector.encoder = encoder; 107 fsl_dev->connector.encoder = encoder;
@@ -122,10 +121,6 @@ static int fsl_dcu_attach_panel(struct fsl_dcu_drm_device *fsl_dev,
122 if (ret < 0) 121 if (ret < 0)
123 goto err_sysfs; 122 goto err_sysfs;
124 123
125 drm_object_property_set_value(&connector->base,
126 mode_config->dpms_property,
127 DRM_MODE_DPMS_OFF);
128
129 ret = drm_panel_attach(panel, connector); 124 ret = drm_panel_attach(panel, connector);
130 if (ret) { 125 if (ret) {
131 dev_err(fsl_dev->dev, "failed to attach panel\n"); 126 dev_err(fsl_dev->dev, "failed to attach panel\n");
diff --git a/drivers/gpu/drm/imx/ipuv3-crtc.c b/drivers/gpu/drm/imx/ipuv3-crtc.c
index 53e0b24beda6..9a9961802f5c 100644
--- a/drivers/gpu/drm/imx/ipuv3-crtc.c
+++ b/drivers/gpu/drm/imx/ipuv3-crtc.c
@@ -115,7 +115,7 @@ static void imx_drm_crtc_reset(struct drm_crtc *crtc)
115 115
116 if (crtc->state) { 116 if (crtc->state) {
117 if (crtc->state->mode_blob) 117 if (crtc->state->mode_blob)
118 drm_property_unreference_blob(crtc->state->mode_blob); 118 drm_property_blob_put(crtc->state->mode_blob);
119 119
120 state = to_imx_crtc_state(crtc->state); 120 state = to_imx_crtc_state(crtc->state);
121 memset(state, 0, sizeof(*state)); 121 memset(state, 0, sizeof(*state));
diff --git a/drivers/gpu/drm/imx/parallel-display.c b/drivers/gpu/drm/imx/parallel-display.c
index 8def97d75030..aedecda9728a 100644
--- a/drivers/gpu/drm/imx/parallel-display.c
+++ b/drivers/gpu/drm/imx/parallel-display.c
@@ -183,7 +183,7 @@ static int imx_pd_register(struct drm_device *drm,
183 &imx_pd_connector_helper_funcs); 183 &imx_pd_connector_helper_funcs);
184 drm_connector_init(drm, &imxpd->connector, 184 drm_connector_init(drm, &imxpd->connector,
185 &imx_pd_connector_funcs, 185 &imx_pd_connector_funcs,
186 DRM_MODE_CONNECTOR_VGA); 186 DRM_MODE_CONNECTOR_DPI);
187 } 187 }
188 188
189 if (imxpd->panel) 189 if (imxpd->panel)
diff --git a/drivers/gpu/drm/qxl/qxl_cmd.c b/drivers/gpu/drm/qxl/qxl_cmd.c
index 74fc9362ecf9..c0fb52c6d4ca 100644
--- a/drivers/gpu/drm/qxl/qxl_cmd.c
+++ b/drivers/gpu/drm/qxl/qxl_cmd.c
@@ -219,7 +219,7 @@ int qxl_garbage_collect(struct qxl_device *qdev)
219 union qxl_release_info *info; 219 union qxl_release_info *info;
220 220
221 while (qxl_ring_pop(qdev->release_ring, &id)) { 221 while (qxl_ring_pop(qdev->release_ring, &id)) {
222 QXL_INFO(qdev, "popped %lld\n", id); 222 DRM_DEBUG_DRIVER("popped %lld\n", id);
223 while (id) { 223 while (id) {
224 release = qxl_release_from_id_locked(qdev, id); 224 release = qxl_release_from_id_locked(qdev, id);
225 if (release == NULL) 225 if (release == NULL)
@@ -229,8 +229,8 @@ int qxl_garbage_collect(struct qxl_device *qdev)
229 next_id = info->next; 229 next_id = info->next;
230 qxl_release_unmap(qdev, release, info); 230 qxl_release_unmap(qdev, release, info);
231 231
232 QXL_INFO(qdev, "popped %lld, next %lld\n", id, 232 DRM_DEBUG_DRIVER("popped %lld, next %lld\n", id,
233 next_id); 233 next_id);
234 234
235 switch (release->type) { 235 switch (release->type) {
236 case QXL_RELEASE_DRAWABLE: 236 case QXL_RELEASE_DRAWABLE:
@@ -248,7 +248,7 @@ int qxl_garbage_collect(struct qxl_device *qdev)
248 } 248 }
249 } 249 }
250 250
251 QXL_INFO(qdev, "%s: %d\n", __func__, i); 251 DRM_DEBUG_DRIVER("%d\n", i);
252 252
253 return i; 253 return i;
254} 254}
@@ -381,17 +381,19 @@ void qxl_io_create_primary(struct qxl_device *qdev,
381{ 381{
382 struct qxl_surface_create *create; 382 struct qxl_surface_create *create;
383 383
384 QXL_INFO(qdev, "%s: qdev %p, ram_header %p\n", __func__, qdev, 384 DRM_DEBUG_DRIVER("qdev %p, ram_header %p\n", qdev, qdev->ram_header);
385 qdev->ram_header);
386 create = &qdev->ram_header->create_surface; 385 create = &qdev->ram_header->create_surface;
387 create->format = bo->surf.format; 386 create->format = bo->surf.format;
388 create->width = bo->surf.width; 387 create->width = bo->surf.width;
389 create->height = bo->surf.height; 388 create->height = bo->surf.height;
390 create->stride = bo->surf.stride; 389 create->stride = bo->surf.stride;
391 create->mem = qxl_bo_physical_address(qdev, bo, offset); 390 if (bo->shadow) {
391 create->mem = qxl_bo_physical_address(qdev, bo->shadow, offset);
392 } else {
393 create->mem = qxl_bo_physical_address(qdev, bo, offset);
394 }
392 395
393 QXL_INFO(qdev, "%s: mem = %llx, from %p\n", __func__, create->mem, 396 DRM_DEBUG_DRIVER("mem = %llx, from %p\n", create->mem, bo->kptr);
394 bo->kptr);
395 397
396 create->flags = QXL_SURF_FLAG_KEEP_DATA; 398 create->flags = QXL_SURF_FLAG_KEEP_DATA;
397 create->type = QXL_SURF_TYPE_PRIMARY; 399 create->type = QXL_SURF_TYPE_PRIMARY;
@@ -401,7 +403,7 @@ void qxl_io_create_primary(struct qxl_device *qdev,
401 403
402void qxl_io_memslot_add(struct qxl_device *qdev, uint8_t id) 404void qxl_io_memslot_add(struct qxl_device *qdev, uint8_t id)
403{ 405{
404 QXL_INFO(qdev, "qxl_memslot_add %d\n", id); 406 DRM_DEBUG_DRIVER("qxl_memslot_add %d\n", id);
405 wait_for_io_cmd(qdev, id, QXL_IO_MEMSLOT_ADD_ASYNC); 407 wait_for_io_cmd(qdev, id, QXL_IO_MEMSLOT_ADD_ASYNC);
406} 408}
407 409
diff --git a/drivers/gpu/drm/qxl/qxl_display.c b/drivers/gpu/drm/qxl/qxl_display.c
index afbf50d0c08f..4756b3c9bf2c 100644
--- a/drivers/gpu/drm/qxl/qxl_display.c
+++ b/drivers/gpu/drm/qxl/qxl_display.c
@@ -305,7 +305,9 @@ static const struct drm_crtc_funcs qxl_crtc_funcs = {
305void qxl_user_framebuffer_destroy(struct drm_framebuffer *fb) 305void qxl_user_framebuffer_destroy(struct drm_framebuffer *fb)
306{ 306{
307 struct qxl_framebuffer *qxl_fb = to_qxl_framebuffer(fb); 307 struct qxl_framebuffer *qxl_fb = to_qxl_framebuffer(fb);
308 struct qxl_bo *bo = gem_to_qxl_bo(qxl_fb->obj);
308 309
310 WARN_ON(bo->shadow);
309 drm_gem_object_unreference_unlocked(qxl_fb->obj); 311 drm_gem_object_unreference_unlocked(qxl_fb->obj);
310 drm_framebuffer_cleanup(fb); 312 drm_framebuffer_cleanup(fb);
311 kfree(qxl_fb); 313 kfree(qxl_fb);
@@ -508,6 +510,7 @@ static void qxl_primary_atomic_update(struct drm_plane *plane,
508 .x2 = qfb->base.width, 510 .x2 = qfb->base.width,
509 .y2 = qfb->base.height 511 .y2 = qfb->base.height
510 }; 512 };
513 bool same_shadow = false;
511 514
512 if (old_state->fb) { 515 if (old_state->fb) {
513 qfb_old = to_qxl_framebuffer(old_state->fb); 516 qfb_old = to_qxl_framebuffer(old_state->fb);
@@ -519,15 +522,23 @@ static void qxl_primary_atomic_update(struct drm_plane *plane,
519 if (bo == bo_old) 522 if (bo == bo_old)
520 return; 523 return;
521 524
525 if (bo_old && bo_old->shadow && bo->shadow &&
526 bo_old->shadow == bo->shadow) {
527 same_shadow = true;
528 }
529
522 if (bo_old && bo_old->is_primary) { 530 if (bo_old && bo_old->is_primary) {
523 qxl_io_destroy_primary(qdev); 531 if (!same_shadow)
532 qxl_io_destroy_primary(qdev);
524 bo_old->is_primary = false; 533 bo_old->is_primary = false;
525 } 534 }
526 535
527 if (!bo->is_primary) { 536 if (!bo->is_primary) {
528 qxl_io_create_primary(qdev, 0, bo); 537 if (!same_shadow)
538 qxl_io_create_primary(qdev, 0, bo);
529 bo->is_primary = true; 539 bo->is_primary = true;
530 } 540 }
541
531 qxl_draw_dirty_fb(qdev, qfb, bo, 0, 0, &norect, 1, 1); 542 qxl_draw_dirty_fb(qdev, qfb, bo, 0, 0, &norect, 1, 1);
532} 543}
533 544
@@ -679,8 +690,9 @@ static void qxl_cursor_atomic_disable(struct drm_plane *plane,
679static int qxl_plane_prepare_fb(struct drm_plane *plane, 690static int qxl_plane_prepare_fb(struct drm_plane *plane,
680 struct drm_plane_state *new_state) 691 struct drm_plane_state *new_state)
681{ 692{
693 struct qxl_device *qdev = plane->dev->dev_private;
682 struct drm_gem_object *obj; 694 struct drm_gem_object *obj;
683 struct qxl_bo *user_bo; 695 struct qxl_bo *user_bo, *old_bo = NULL;
684 int ret; 696 int ret;
685 697
686 if (!new_state->fb) 698 if (!new_state->fb)
@@ -689,6 +701,32 @@ static int qxl_plane_prepare_fb(struct drm_plane *plane,
689 obj = to_qxl_framebuffer(new_state->fb)->obj; 701 obj = to_qxl_framebuffer(new_state->fb)->obj;
690 user_bo = gem_to_qxl_bo(obj); 702 user_bo = gem_to_qxl_bo(obj);
691 703
704 if (plane->type == DRM_PLANE_TYPE_PRIMARY &&
705 user_bo->is_dumb && !user_bo->shadow) {
706 if (plane->state->fb) {
707 obj = to_qxl_framebuffer(plane->state->fb)->obj;
708 old_bo = gem_to_qxl_bo(obj);
709 }
710 if (old_bo && old_bo->shadow &&
711 user_bo->gem_base.size == old_bo->gem_base.size &&
712 plane->state->crtc == new_state->crtc &&
713 plane->state->crtc_w == new_state->crtc_w &&
714 plane->state->crtc_h == new_state->crtc_h &&
715 plane->state->src_x == new_state->src_x &&
716 plane->state->src_y == new_state->src_y &&
717 plane->state->src_w == new_state->src_w &&
718 plane->state->src_h == new_state->src_h &&
719 plane->state->rotation == new_state->rotation &&
720 plane->state->zpos == new_state->zpos) {
721 drm_gem_object_get(&old_bo->shadow->gem_base);
722 user_bo->shadow = old_bo->shadow;
723 } else {
724 qxl_bo_create(qdev, user_bo->gem_base.size,
725 true, true, QXL_GEM_DOMAIN_VRAM, NULL,
726 &user_bo->shadow);
727 }
728 }
729
692 ret = qxl_bo_pin(user_bo, QXL_GEM_DOMAIN_CPU, NULL); 730 ret = qxl_bo_pin(user_bo, QXL_GEM_DOMAIN_CPU, NULL);
693 if (ret) 731 if (ret)
694 return ret; 732 return ret;
@@ -713,6 +751,11 @@ static void qxl_plane_cleanup_fb(struct drm_plane *plane,
713 obj = to_qxl_framebuffer(old_state->fb)->obj; 751 obj = to_qxl_framebuffer(old_state->fb)->obj;
714 user_bo = gem_to_qxl_bo(obj); 752 user_bo = gem_to_qxl_bo(obj);
715 qxl_bo_unpin(user_bo); 753 qxl_bo_unpin(user_bo);
754
755 if (user_bo->shadow && !user_bo->is_primary) {
756 drm_gem_object_put_unlocked(&user_bo->shadow->gem_base);
757 user_bo->shadow = NULL;
758 }
716} 759}
717 760
718static const uint32_t qxl_cursor_plane_formats[] = { 761static const uint32_t qxl_cursor_plane_formats[] = {
diff --git a/drivers/gpu/drm/qxl/qxl_drv.h b/drivers/gpu/drm/qxl/qxl_drv.h
index 3397a1907336..08752c0ffb35 100644
--- a/drivers/gpu/drm/qxl/qxl_drv.h
+++ b/drivers/gpu/drm/qxl/qxl_drv.h
@@ -62,33 +62,9 @@
62 62
63#define QXL_DEBUGFS_MAX_COMPONENTS 32 63#define QXL_DEBUGFS_MAX_COMPONENTS 32
64 64
65extern int qxl_log_level;
66extern int qxl_num_crtc; 65extern int qxl_num_crtc;
67extern int qxl_max_ioctls; 66extern int qxl_max_ioctls;
68 67
69enum {
70 QXL_INFO_LEVEL = 1,
71 QXL_DEBUG_LEVEL = 2,
72};
73
74#define QXL_INFO(qdev, fmt, ...) do { \
75 if (qxl_log_level >= QXL_INFO_LEVEL) { \
76 qxl_io_log(qdev, fmt, __VA_ARGS__); \
77 } \
78 } while (0)
79#define QXL_DEBUG(qdev, fmt, ...) do { \
80 if (qxl_log_level >= QXL_DEBUG_LEVEL) { \
81 qxl_io_log(qdev, fmt, __VA_ARGS__); \
82 } \
83 } while (0)
84#define QXL_INFO_ONCE(qdev, fmt, ...) do { \
85 static int done; \
86 if (!done) { \
87 done = 1; \
88 QXL_INFO(qdev, fmt, __VA_ARGS__); \
89 } \
90 } while (0)
91
92#define DRM_FILE_OFFSET 0x100000000ULL 68#define DRM_FILE_OFFSET 0x100000000ULL
93#define DRM_FILE_PAGE_OFFSET (DRM_FILE_OFFSET >> PAGE_SHIFT) 69#define DRM_FILE_PAGE_OFFSET (DRM_FILE_OFFSET >> PAGE_SHIFT)
94 70
@@ -113,6 +89,8 @@ struct qxl_bo {
113 /* Constant after initialization */ 89 /* Constant after initialization */
114 struct drm_gem_object gem_base; 90 struct drm_gem_object gem_base;
115 bool is_primary; /* is this now a primary surface */ 91 bool is_primary; /* is this now a primary surface */
92 bool is_dumb;
93 struct qxl_bo *shadow;
116 bool hw_surf_alloc; 94 bool hw_surf_alloc;
117 struct qxl_surface surf; 95 struct qxl_surface surf;
118 uint32_t surface_id; 96 uint32_t surface_id;
@@ -351,7 +329,7 @@ int qxl_check_idle(struct qxl_ring *ring);
351static inline void * 329static inline void *
352qxl_fb_virtual_address(struct qxl_device *qdev, unsigned long physical) 330qxl_fb_virtual_address(struct qxl_device *qdev, unsigned long physical)
353{ 331{
354 QXL_INFO(qdev, "not implemented (%lu)\n", physical); 332 DRM_DEBUG_DRIVER("not implemented (%lu)\n", physical);
355 return 0; 333 return 0;
356} 334}
357 335
diff --git a/drivers/gpu/drm/qxl/qxl_dumb.c b/drivers/gpu/drm/qxl/qxl_dumb.c
index 5e65d5d2d937..11085ab01374 100644
--- a/drivers/gpu/drm/qxl/qxl_dumb.c
+++ b/drivers/gpu/drm/qxl/qxl_dumb.c
@@ -63,6 +63,7 @@ int qxl_mode_dumb_create(struct drm_file *file_priv,
63 &handle); 63 &handle);
64 if (r) 64 if (r)
65 return r; 65 return r;
66 qobj->is_dumb = true;
66 args->pitch = pitch; 67 args->pitch = pitch;
67 args->handle = handle; 68 args->handle = handle;
68 return 0; 69 return 0;
diff --git a/drivers/gpu/drm/qxl/qxl_fb.c b/drivers/gpu/drm/qxl/qxl_fb.c
index 844c4a31ca13..23af3e352673 100644
--- a/drivers/gpu/drm/qxl/qxl_fb.c
+++ b/drivers/gpu/drm/qxl/qxl_fb.c
@@ -240,18 +240,15 @@ static int qxlfb_create(struct qxl_fbdev *qfbdev,
240 return ret; 240 return ret;
241 241
242 qbo = gem_to_qxl_bo(gobj); 242 qbo = gem_to_qxl_bo(gobj);
243 QXL_INFO(qdev, "%s: %dx%d %d\n", __func__, mode_cmd.width, 243 DRM_DEBUG_DRIVER("%dx%d %d\n", mode_cmd.width,
244 mode_cmd.height, mode_cmd.pitches[0]); 244 mode_cmd.height, mode_cmd.pitches[0]);
245 245
246 shadow = vmalloc(mode_cmd.pitches[0] * mode_cmd.height); 246 shadow = vmalloc(mode_cmd.pitches[0] * mode_cmd.height);
247 /* TODO: what's the usual response to memory allocation errors? */ 247 /* TODO: what's the usual response to memory allocation errors? */
248 BUG_ON(!shadow); 248 BUG_ON(!shadow);
249 QXL_INFO(qdev, 249 DRM_DEBUG_DRIVER("surface0 at gpu offset %lld, mmap_offset %lld (virt %p, shadow %p)\n",
250 "surface0 at gpu offset %lld, mmap_offset %lld (virt %p, shadow %p)\n", 250 qxl_bo_gpu_offset(qbo), qxl_bo_mmap_offset(qbo),
251 qxl_bo_gpu_offset(qbo), 251 qbo->kptr, shadow);
252 qxl_bo_mmap_offset(qbo),
253 qbo->kptr,
254 shadow);
255 size = mode_cmd.pitches[0] * mode_cmd.height; 252 size = mode_cmd.pitches[0] * mode_cmd.height;
256 253
257 info = drm_fb_helper_alloc_fbi(&qfbdev->helper); 254 info = drm_fb_helper_alloc_fbi(&qfbdev->helper);
diff --git a/drivers/gpu/drm/qxl/qxl_release.c b/drivers/gpu/drm/qxl/qxl_release.c
index e6ec845b5be0..a6da6fa6ad58 100644
--- a/drivers/gpu/drm/qxl/qxl_release.c
+++ b/drivers/gpu/drm/qxl/qxl_release.c
@@ -154,7 +154,7 @@ qxl_release_alloc(struct qxl_device *qdev, int type,
154 return handle; 154 return handle;
155 } 155 }
156 *ret = release; 156 *ret = release;
157 QXL_INFO(qdev, "allocated release %d\n", handle); 157 DRM_DEBUG_DRIVER("allocated release %d\n", handle);
158 release->id = handle; 158 release->id = handle;
159 return handle; 159 return handle;
160} 160}
@@ -179,8 +179,7 @@ void
179qxl_release_free(struct qxl_device *qdev, 179qxl_release_free(struct qxl_device *qdev,
180 struct qxl_release *release) 180 struct qxl_release *release)
181{ 181{
182 QXL_INFO(qdev, "release %d, type %d\n", release->id, 182 DRM_DEBUG_DRIVER("release %d, type %d\n", release->id, release->type);
183 release->type);
184 183
185 if (release->surface_release_id) 184 if (release->surface_release_id)
186 qxl_surface_id_dealloc(qdev, release->surface_release_id); 185 qxl_surface_id_dealloc(qdev, release->surface_release_id);
diff --git a/drivers/gpu/drm/qxl/qxl_ttm.c b/drivers/gpu/drm/qxl/qxl_ttm.c
index 7ecf8a4b9fe6..ab4823875311 100644
--- a/drivers/gpu/drm/qxl/qxl_ttm.c
+++ b/drivers/gpu/drm/qxl/qxl_ttm.c
@@ -136,8 +136,8 @@ int qxl_mmap(struct file *filp, struct vm_area_struct *vma)
136 "filp->private_data->minor->dev->dev_private == NULL\n"); 136 "filp->private_data->minor->dev->dev_private == NULL\n");
137 return -EINVAL; 137 return -EINVAL;
138 } 138 }
139 QXL_INFO(qdev, "%s: filp->private_data = 0x%p, vma->vm_pgoff = %lx\n", 139 DRM_DEBUG_DRIVER("filp->private_data = 0x%p, vma->vm_pgoff = %lx\n",
140 __func__, filp->private_data, vma->vm_pgoff); 140 filp->private_data, vma->vm_pgoff);
141 141
142 r = ttm_bo_mmap(filp, vma, &qdev->mman.bdev); 142 r = ttm_bo_mmap(filp, vma, &qdev->mman.bdev);
143 if (unlikely(r != 0)) 143 if (unlikely(r != 0))
diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c
index 2fcf805d3a16..33b821d6d018 100644
--- a/drivers/gpu/drm/radeon/radeon_fb.c
+++ b/drivers/gpu/drm/radeon/radeon_fb.c
@@ -245,7 +245,6 @@ static int radeonfb_create(struct drm_fb_helper *helper,
245 } 245 }
246 246
247 info->par = rfbdev; 247 info->par = rfbdev;
248 info->skip_vt_switch = true;
249 248
250 ret = radeon_framebuffer_init(rdev->ddev, &rfbdev->rfb, &mode_cmd, gobj); 249 ret = radeon_framebuffer_init(rdev->ddev, &rfbdev->rfb, &mode_cmd, gobj);
251 if (ret) { 250 if (ret) {
diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index 3c70c6224bd2..0ccc76217ee4 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -60,7 +60,7 @@ config ROCKCHIP_INNO_HDMI
60config ROCKCHIP_LVDS 60config ROCKCHIP_LVDS
61 bool "Rockchip LVDS support" 61 bool "Rockchip LVDS support"
62 depends on DRM_ROCKCHIP 62 depends on DRM_ROCKCHIP
63 depends on PINCTRL 63 depends on PINCTRL && OF
64 help 64 help
65 Choose this option to enable support for Rockchip LVDS controllers. 65 Choose this option to enable support for Rockchip LVDS controllers.
66 Rockchip rk3288 SoC has LVDS TX Controller can be used, and it 66 Rockchip rk3288 SoC has LVDS TX Controller can be used, and it
diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
index 4d3f6ad0abdd..93b7102dd008 100644
--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -72,7 +72,7 @@ struct rockchip_dp_device {
72 struct reset_control *rst; 72 struct reset_control *rst;
73 73
74 struct work_struct psr_work; 74 struct work_struct psr_work;
75 spinlock_t psr_lock; 75 struct mutex psr_lock;
76 unsigned int psr_state; 76 unsigned int psr_state;
77 77
78 const struct rockchip_dp_chip_data *data; 78 const struct rockchip_dp_chip_data *data;
@@ -83,21 +83,20 @@ struct rockchip_dp_device {
83static void analogix_dp_psr_set(struct drm_encoder *encoder, bool enabled) 83static void analogix_dp_psr_set(struct drm_encoder *encoder, bool enabled)
84{ 84{
85 struct rockchip_dp_device *dp = to_dp(encoder); 85 struct rockchip_dp_device *dp = to_dp(encoder);
86 unsigned long flags;
87 86
88 if (!analogix_dp_psr_supported(dp->dev)) 87 if (!analogix_dp_psr_supported(dp->dev))
89 return; 88 return;
90 89
91 DRM_DEV_DEBUG(dp->dev, "%s PSR...\n", enabled ? "Entry" : "Exit"); 90 DRM_DEV_DEBUG(dp->dev, "%s PSR...\n", enabled ? "Entry" : "Exit");
92 91
93 spin_lock_irqsave(&dp->psr_lock, flags); 92 mutex_lock(&dp->psr_lock);
94 if (enabled) 93 if (enabled)
95 dp->psr_state = EDP_VSC_PSR_STATE_ACTIVE; 94 dp->psr_state = EDP_VSC_PSR_STATE_ACTIVE;
96 else 95 else
97 dp->psr_state = ~EDP_VSC_PSR_STATE_ACTIVE; 96 dp->psr_state = ~EDP_VSC_PSR_STATE_ACTIVE;
98 97
99 schedule_work(&dp->psr_work); 98 schedule_work(&dp->psr_work);
100 spin_unlock_irqrestore(&dp->psr_lock, flags); 99 mutex_unlock(&dp->psr_lock);
101} 100}
102 101
103static void analogix_dp_psr_work(struct work_struct *work) 102static void analogix_dp_psr_work(struct work_struct *work)
@@ -105,7 +104,6 @@ static void analogix_dp_psr_work(struct work_struct *work)
105 struct rockchip_dp_device *dp = 104 struct rockchip_dp_device *dp =
106 container_of(work, typeof(*dp), psr_work); 105 container_of(work, typeof(*dp), psr_work);
107 int ret; 106 int ret;
108 unsigned long flags;
109 107
110 ret = rockchip_drm_wait_vact_end(dp->encoder.crtc, 108 ret = rockchip_drm_wait_vact_end(dp->encoder.crtc,
111 PSR_WAIT_LINE_FLAG_TIMEOUT_MS); 109 PSR_WAIT_LINE_FLAG_TIMEOUT_MS);
@@ -114,12 +112,12 @@ static void analogix_dp_psr_work(struct work_struct *work)
114 return; 112 return;
115 } 113 }
116 114
117 spin_lock_irqsave(&dp->psr_lock, flags); 115 mutex_lock(&dp->psr_lock);
118 if (dp->psr_state == EDP_VSC_PSR_STATE_ACTIVE) 116 if (dp->psr_state == EDP_VSC_PSR_STATE_ACTIVE)
119 analogix_dp_enable_psr(dp->dev); 117 analogix_dp_enable_psr(dp->dev);
120 else 118 else
121 analogix_dp_disable_psr(dp->dev); 119 analogix_dp_disable_psr(dp->dev);
122 spin_unlock_irqrestore(&dp->psr_lock, flags); 120 mutex_unlock(&dp->psr_lock);
123} 121}
124 122
125static int rockchip_dp_pre_init(struct rockchip_dp_device *dp) 123static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
@@ -381,7 +379,7 @@ static int rockchip_dp_bind(struct device *dev, struct device *master,
381 dp->plat_data.power_off = rockchip_dp_powerdown; 379 dp->plat_data.power_off = rockchip_dp_powerdown;
382 dp->plat_data.get_modes = rockchip_dp_get_modes; 380 dp->plat_data.get_modes = rockchip_dp_get_modes;
383 381
384 spin_lock_init(&dp->psr_lock); 382 mutex_init(&dp->psr_lock);
385 dp->psr_state = ~EDP_VSC_PSR_STATE_ACTIVE; 383 dp->psr_state = ~EDP_VSC_PSR_STATE_ACTIVE;
386 INIT_WORK(&dp->psr_work, analogix_dp_psr_work); 384 INIT_WORK(&dp->psr_work, analogix_dp_psr_work);
387 385
diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c
index 4bcacd3f4861..b0a1dedac802 100644
--- a/drivers/gpu/drm/tegra/sor.c
+++ b/drivers/gpu/drm/tegra/sor.c
@@ -174,9 +174,9 @@ struct tegra_sor {
174 174
175 struct reset_control *rst; 175 struct reset_control *rst;
176 struct clk *clk_parent; 176 struct clk *clk_parent;
177 struct clk *clk_brick;
178 struct clk *clk_safe; 177 struct clk *clk_safe;
179 struct clk *clk_src; 178 struct clk *clk_out;
179 struct clk *clk_pad;
180 struct clk *clk_dp; 180 struct clk *clk_dp;
181 struct clk *clk; 181 struct clk *clk;
182 182
@@ -255,7 +255,7 @@ static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent)
255 255
256 clk_disable_unprepare(sor->clk); 256 clk_disable_unprepare(sor->clk);
257 257
258 err = clk_set_parent(sor->clk, parent); 258 err = clk_set_parent(sor->clk_out, parent);
259 if (err < 0) 259 if (err < 0)
260 return err; 260 return err;
261 261
@@ -266,24 +266,24 @@ static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent)
266 return 0; 266 return 0;
267} 267}
268 268
269struct tegra_clk_sor_brick { 269struct tegra_clk_sor_pad {
270 struct clk_hw hw; 270 struct clk_hw hw;
271 struct tegra_sor *sor; 271 struct tegra_sor *sor;
272}; 272};
273 273
274static inline struct tegra_clk_sor_brick *to_brick(struct clk_hw *hw) 274static inline struct tegra_clk_sor_pad *to_pad(struct clk_hw *hw)
275{ 275{
276 return container_of(hw, struct tegra_clk_sor_brick, hw); 276 return container_of(hw, struct tegra_clk_sor_pad, hw);
277} 277}
278 278
279static const char * const tegra_clk_sor_brick_parents[] = { 279static const char * const tegra_clk_sor_pad_parents[] = {
280 "pll_d2_out0", "pll_dp" 280 "pll_d2_out0", "pll_dp"
281}; 281};
282 282
283static int tegra_clk_sor_brick_set_parent(struct clk_hw *hw, u8 index) 283static int tegra_clk_sor_pad_set_parent(struct clk_hw *hw, u8 index)
284{ 284{
285 struct tegra_clk_sor_brick *brick = to_brick(hw); 285 struct tegra_clk_sor_pad *pad = to_pad(hw);
286 struct tegra_sor *sor = brick->sor; 286 struct tegra_sor *sor = pad->sor;
287 u32 value; 287 u32 value;
288 288
289 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 289 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
@@ -304,10 +304,10 @@ static int tegra_clk_sor_brick_set_parent(struct clk_hw *hw, u8 index)
304 return 0; 304 return 0;
305} 305}
306 306
307static u8 tegra_clk_sor_brick_get_parent(struct clk_hw *hw) 307static u8 tegra_clk_sor_pad_get_parent(struct clk_hw *hw)
308{ 308{
309 struct tegra_clk_sor_brick *brick = to_brick(hw); 309 struct tegra_clk_sor_pad *pad = to_pad(hw);
310 struct tegra_sor *sor = brick->sor; 310 struct tegra_sor *sor = pad->sor;
311 u8 parent = U8_MAX; 311 u8 parent = U8_MAX;
312 u32 value; 312 u32 value;
313 313
@@ -328,33 +328,33 @@ static u8 tegra_clk_sor_brick_get_parent(struct clk_hw *hw)
328 return parent; 328 return parent;
329} 329}
330 330
331static const struct clk_ops tegra_clk_sor_brick_ops = { 331static const struct clk_ops tegra_clk_sor_pad_ops = {
332 .set_parent = tegra_clk_sor_brick_set_parent, 332 .set_parent = tegra_clk_sor_pad_set_parent,
333 .get_parent = tegra_clk_sor_brick_get_parent, 333 .get_parent = tegra_clk_sor_pad_get_parent,
334}; 334};
335 335
336static struct clk *tegra_clk_sor_brick_register(struct tegra_sor *sor, 336static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor,
337 const char *name) 337 const char *name)
338{ 338{
339 struct tegra_clk_sor_brick *brick; 339 struct tegra_clk_sor_pad *pad;
340 struct clk_init_data init; 340 struct clk_init_data init;
341 struct clk *clk; 341 struct clk *clk;
342 342
343 brick = devm_kzalloc(sor->dev, sizeof(*brick), GFP_KERNEL); 343 pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL);
344 if (!brick) 344 if (!pad)
345 return ERR_PTR(-ENOMEM); 345 return ERR_PTR(-ENOMEM);
346 346
347 brick->sor = sor; 347 pad->sor = sor;
348 348
349 init.name = name; 349 init.name = name;
350 init.flags = 0; 350 init.flags = 0;
351 init.parent_names = tegra_clk_sor_brick_parents; 351 init.parent_names = tegra_clk_sor_pad_parents;
352 init.num_parents = ARRAY_SIZE(tegra_clk_sor_brick_parents); 352 init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents);
353 init.ops = &tegra_clk_sor_brick_ops; 353 init.ops = &tegra_clk_sor_pad_ops;
354 354
355 brick->hw.init = &init; 355 pad->hw.init = &init;
356 356
357 clk = devm_clk_register(sor->dev, &brick->hw); 357 clk = devm_clk_register(sor->dev, &pad->hw);
358 358
359 return clk; 359 return clk;
360} 360}
@@ -998,8 +998,10 @@ static int tegra_sor_power_down(struct tegra_sor *sor)
998 998
999 /* switch to safe parent clock */ 999 /* switch to safe parent clock */
1000 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); 1000 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1001 if (err < 0) 1001 if (err < 0) {
1002 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); 1002 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1003 return err;
1004 }
1003 1005
1004 value = tegra_sor_readl(sor, SOR_DP_PADCTL0); 1006 value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
1005 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | 1007 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
@@ -2007,8 +2009,10 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
2007 2009
2008 /* switch to safe parent clock */ 2010 /* switch to safe parent clock */
2009 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); 2011 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2010 if (err < 0) 2012 if (err < 0) {
2011 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); 2013 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
2014 return;
2015 }
2012 2016
2013 div = clk_get_rate(sor->clk) / 1000000 * 4; 2017 div = clk_get_rate(sor->clk) / 1000000 * 4;
2014 2018
@@ -2111,13 +2115,17 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
2111 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); 2115 tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2112 2116
2113 /* switch to parent clock */ 2117 /* switch to parent clock */
2114 err = clk_set_parent(sor->clk_src, sor->clk_parent); 2118 err = clk_set_parent(sor->clk, sor->clk_parent);
2115 if (err < 0) 2119 if (err < 0) {
2116 dev_err(sor->dev, "failed to set source clock: %d\n", err);
2117
2118 err = tegra_sor_set_parent_clock(sor, sor->clk_src);
2119 if (err < 0)
2120 dev_err(sor->dev, "failed to set parent clock: %d\n", err); 2120 dev_err(sor->dev, "failed to set parent clock: %d\n", err);
2121 return;
2122 }
2123
2124 err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
2125 if (err < 0) {
2126 dev_err(sor->dev, "failed to set pad clock: %d\n", err);
2127 return;
2128 }
2121 2129
2122 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe); 2130 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe);
2123 2131
@@ -2628,11 +2636,24 @@ static int tegra_sor_probe(struct platform_device *pdev)
2628 } 2636 }
2629 2637
2630 if (sor->soc->supports_hdmi || sor->soc->supports_dp) { 2638 if (sor->soc->supports_hdmi || sor->soc->supports_dp) {
2631 sor->clk_src = devm_clk_get(&pdev->dev, "source"); 2639 struct device_node *np = pdev->dev.of_node;
2632 if (IS_ERR(sor->clk_src)) { 2640 const char *name;
2633 err = PTR_ERR(sor->clk_src); 2641
2634 dev_err(sor->dev, "failed to get source clock: %d\n", 2642 /*
2635 err); 2643 * For backwards compatibility with Tegra210 device trees,
2644 * fall back to the old clock name "source" if the new "out"
2645 * clock is not available.
2646 */
2647 if (of_property_match_string(np, "clock-names", "out") < 0)
2648 name = "source";
2649 else
2650 name = "out";
2651
2652 sor->clk_out = devm_clk_get(&pdev->dev, name);
2653 if (IS_ERR(sor->clk_out)) {
2654 err = PTR_ERR(sor->clk_out);
2655 dev_err(sor->dev, "failed to get %s clock: %d\n",
2656 name, err);
2636 goto remove; 2657 goto remove;
2637 } 2658 }
2638 } 2659 }
@@ -2658,16 +2679,60 @@ static int tegra_sor_probe(struct platform_device *pdev)
2658 goto remove; 2679 goto remove;
2659 } 2680 }
2660 2681
2682 /*
2683 * Starting with Tegra186, the BPMP provides an implementation for
2684 * the pad output clock, so we have to look it up from device tree.
2685 */
2686 sor->clk_pad = devm_clk_get(&pdev->dev, "pad");
2687 if (IS_ERR(sor->clk_pad)) {
2688 if (sor->clk_pad != ERR_PTR(-ENOENT)) {
2689 err = PTR_ERR(sor->clk_pad);
2690 goto remove;
2691 }
2692
2693 /*
2694 * If the pad output clock is not available, then we assume
2695 * we're on Tegra210 or earlier and have to provide our own
2696 * implementation.
2697 */
2698 sor->clk_pad = NULL;
2699 }
2700
2701 /*
2702 * The bootloader may have set up the SOR such that it's module clock
2703 * is sourced by one of the display PLLs. However, that doesn't work
2704 * without properly having set up other bits of the SOR.
2705 */
2706 err = clk_set_parent(sor->clk_out, sor->clk_safe);
2707 if (err < 0) {
2708 dev_err(&pdev->dev, "failed to use safe clock: %d\n", err);
2709 goto remove;
2710 }
2711
2661 platform_set_drvdata(pdev, sor); 2712 platform_set_drvdata(pdev, sor);
2662 pm_runtime_enable(&pdev->dev); 2713 pm_runtime_enable(&pdev->dev);
2663 2714
2664 pm_runtime_get_sync(&pdev->dev); 2715 /*
2665 sor->clk_brick = tegra_clk_sor_brick_register(sor, "sor1_brick"); 2716 * On Tegra210 and earlier, provide our own implementation for the
2666 pm_runtime_put(&pdev->dev); 2717 * pad output clock.
2718 */
2719 if (!sor->clk_pad) {
2720 err = pm_runtime_get_sync(&pdev->dev);
2721 if (err < 0) {
2722 dev_err(&pdev->dev, "failed to get runtime PM: %d\n",
2723 err);
2724 goto remove;
2725 }
2726
2727 sor->clk_pad = tegra_clk_sor_pad_register(sor,
2728 "sor1_pad_clkout");
2729 pm_runtime_put(&pdev->dev);
2730 }
2667 2731
2668 if (IS_ERR(sor->clk_brick)) { 2732 if (IS_ERR(sor->clk_pad)) {
2669 err = PTR_ERR(sor->clk_brick); 2733 err = PTR_ERR(sor->clk_pad);
2670 dev_err(&pdev->dev, "failed to register SOR clock: %d\n", err); 2734 dev_err(&pdev->dev, "failed to register SOR pad clock: %d\n",
2735 err);
2671 goto remove; 2736 goto remove;
2672 } 2737 }
2673 2738
diff --git a/drivers/gpu/drm/tilcdc/Kconfig b/drivers/gpu/drm/tilcdc/Kconfig
index 28fed7e206d0..81ac82455ce4 100644
--- a/drivers/gpu/drm/tilcdc/Kconfig
+++ b/drivers/gpu/drm/tilcdc/Kconfig
@@ -12,14 +12,3 @@ config DRM_TILCDC
12 controller, for example AM33xx in beagle-bone, DA8xx, or 12 controller, for example AM33xx in beagle-bone, DA8xx, or
13 OMAP-L1xx. This driver replaces the FB_DA8XX fbdev driver. 13 OMAP-L1xx. This driver replaces the FB_DA8XX fbdev driver.
14 14
15config DRM_TILCDC_SLAVE_COMPAT
16 bool "Support device tree blobs using TI LCDC Slave binding"
17 depends on DRM_TILCDC
18 default y
19 select OF_RESOLVE
20 select OF_OVERLAY
21 help
22 Choose this option if you need a kernel that is compatible
23 with device tree blobs using the obsolete "ti,tilcdc,slave"
24 binding. If you find "ti,tilcdc,slave"-string from your DTB,
25 you probably need this. Otherwise you do not.
diff --git a/drivers/gpu/drm/tilcdc/Makefile b/drivers/gpu/drm/tilcdc/Makefile
index 55ebd516728f..efc2c4f00daa 100644
--- a/drivers/gpu/drm/tilcdc/Makefile
+++ b/drivers/gpu/drm/tilcdc/Makefile
@@ -2,9 +2,6 @@ ifeq (, $(findstring -W,$(EXTRA_CFLAGS)))
2 ccflags-y += -Werror 2 ccflags-y += -Werror
3endif 3endif
4 4
5obj-$(CONFIG_DRM_TILCDC_SLAVE_COMPAT) += tilcdc_slave_compat.o \
6 tilcdc_slave_compat.dtb.o
7
8tilcdc-y := \ 5tilcdc-y := \
9 tilcdc_plane.o \ 6 tilcdc_plane.o \
10 tilcdc_crtc.o \ 7 tilcdc_crtc.o \
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c b/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c
deleted file mode 100644
index 482299a6f3b0..000000000000
--- a/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c
+++ /dev/null
@@ -1,269 +0,0 @@
1/*
2 * Copyright (C) 2015 Texas Instruments
3 * Author: Jyri Sarha <jsarha@ti.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 */
10
11/*
12 * To support the old "ti,tilcdc,slave" binding the binding has to be
13 * transformed to the new external encoder binding.
14 */
15
16#include <linux/kernel.h>
17#include <linux/of.h>
18#include <linux/of_graph.h>
19#include <linux/of_fdt.h>
20#include <linux/slab.h>
21#include <linux/list.h>
22
23#include "tilcdc_slave_compat.h"
24
25struct kfree_table {
26 int total;
27 int num;
28 void **table;
29};
30
31static int __init kfree_table_init(struct kfree_table *kft)
32{
33 kft->total = 32;
34 kft->num = 0;
35 kft->table = kmalloc(kft->total * sizeof(*kft->table),
36 GFP_KERNEL);
37 if (!kft->table)
38 return -ENOMEM;
39
40 return 0;
41}
42
43static int __init kfree_table_add(struct kfree_table *kft, void *p)
44{
45 if (kft->num == kft->total) {
46 void **old = kft->table;
47
48 kft->total *= 2;
49 kft->table = krealloc(old, kft->total * sizeof(*kft->table),
50 GFP_KERNEL);
51 if (!kft->table) {
52 kft->table = old;
53 kfree(p);
54 return -ENOMEM;
55 }
56 }
57 kft->table[kft->num++] = p;
58 return 0;
59}
60
61static void __init kfree_table_free(struct kfree_table *kft)
62{
63 int i;
64
65 for (i = 0; i < kft->num; i++)
66 kfree(kft->table[i]);
67
68 kfree(kft->table);
69}
70
71static
72struct property * __init tilcdc_prop_dup(const struct property *prop,
73 struct kfree_table *kft)
74{
75 struct property *nprop;
76
77 nprop = kzalloc(sizeof(*nprop), GFP_KERNEL);
78 if (!nprop || kfree_table_add(kft, nprop))
79 return NULL;
80
81 nprop->name = kstrdup(prop->name, GFP_KERNEL);
82 if (!nprop->name || kfree_table_add(kft, nprop->name))
83 return NULL;
84
85 nprop->value = kmemdup(prop->value, prop->length, GFP_KERNEL);
86 if (!nprop->value || kfree_table_add(kft, nprop->value))
87 return NULL;
88
89 nprop->length = prop->length;
90
91 return nprop;
92}
93
94static void __init tilcdc_copy_props(struct device_node *from,
95 struct device_node *to,
96 const char * const props[],
97 struct kfree_table *kft)
98{
99 struct property *prop;
100 int i;
101
102 for (i = 0; props[i]; i++) {
103 prop = of_find_property(from, props[i], NULL);
104 if (!prop)
105 continue;
106
107 prop = tilcdc_prop_dup(prop, kft);
108 if (!prop)
109 continue;
110
111 prop->next = to->properties;
112 to->properties = prop;
113 }
114}
115
116static int __init tilcdc_prop_str_update(struct property *prop,
117 const char *str,
118 struct kfree_table *kft)
119{
120 prop->value = kstrdup(str, GFP_KERNEL);
121 if (kfree_table_add(kft, prop->value) || !prop->value)
122 return -ENOMEM;
123 prop->length = strlen(str)+1;
124 return 0;
125}
126
127static void __init tilcdc_node_disable(struct device_node *node)
128{
129 struct property *prop;
130
131 prop = kzalloc(sizeof(*prop), GFP_KERNEL);
132 if (!prop)
133 return;
134
135 prop->name = "status";
136 prop->value = "disabled";
137 prop->length = strlen((char *)prop->value)+1;
138
139 of_update_property(node, prop);
140}
141
142static struct device_node * __init tilcdc_get_overlay(struct kfree_table *kft)
143{
144 const int size = __dtb_tilcdc_slave_compat_end -
145 __dtb_tilcdc_slave_compat_begin;
146 static void *overlay_data;
147 struct device_node *overlay;
148 int ret;
149
150 if (!size) {
151 pr_warn("%s: No overlay data\n", __func__);
152 return NULL;
153 }
154
155 overlay_data = kmemdup(__dtb_tilcdc_slave_compat_begin,
156 size, GFP_KERNEL);
157 if (!overlay_data || kfree_table_add(kft, overlay_data))
158 return NULL;
159
160 of_fdt_unflatten_tree(overlay_data, NULL, &overlay);
161 if (!overlay) {
162 pr_warn("%s: Unfattening overlay tree failed\n", __func__);
163 return NULL;
164 }
165
166 ret = of_resolve_phandles(overlay);
167 if (ret) {
168 pr_err("%s: Failed to resolve phandles: %d\n", __func__, ret);
169 return NULL;
170 }
171
172 return overlay;
173}
174
175static const struct of_device_id tilcdc_slave_of_match[] __initconst = {
176 { .compatible = "ti,tilcdc,slave", },
177 {},
178};
179
180static const struct of_device_id tilcdc_of_match[] __initconst = {
181 { .compatible = "ti,am33xx-tilcdc", },
182 {},
183};
184
185static const struct of_device_id tilcdc_tda998x_of_match[] __initconst = {
186 { .compatible = "nxp,tda998x", },
187 {},
188};
189
190static const char * const tilcdc_slave_props[] __initconst = {
191 "pinctrl-names",
192 "pinctrl-0",
193 "pinctrl-1",
194 NULL
195};
196
197static void __init tilcdc_convert_slave_node(void)
198{
199 struct device_node *slave = NULL, *lcdc = NULL;
200 struct device_node *i2c = NULL, *fragment = NULL;
201 struct device_node *overlay, *encoder;
202 struct property *prop;
203 /* For all memory needed for the overlay tree. This memory can
204 be freed after the overlay has been applied. */
205 struct kfree_table kft;
206 int ret;
207
208 if (kfree_table_init(&kft))
209 return;
210
211 lcdc = of_find_matching_node(NULL, tilcdc_of_match);
212 slave = of_find_matching_node(NULL, tilcdc_slave_of_match);
213
214 if (!slave || !of_device_is_available(lcdc))
215 goto out;
216
217 i2c = of_parse_phandle(slave, "i2c", 0);
218 if (!i2c) {
219 pr_err("%s: Can't find i2c node trough phandle\n", __func__);
220 goto out;
221 }
222
223 overlay = tilcdc_get_overlay(&kft);
224 if (!overlay)
225 goto out;
226
227 encoder = of_find_matching_node(overlay, tilcdc_tda998x_of_match);
228 if (!encoder) {
229 pr_err("%s: Failed to find tda998x node\n", __func__);
230 goto out;
231 }
232
233 tilcdc_copy_props(slave, encoder, tilcdc_slave_props, &kft);
234
235 for_each_child_of_node(overlay, fragment) {
236 prop = of_find_property(fragment, "target-path", NULL);
237 if (!prop)
238 continue;
239 if (!strncmp("i2c", (char *)prop->value, prop->length))
240 if (tilcdc_prop_str_update(prop, i2c->full_name, &kft))
241 goto out;
242 if (!strncmp("lcdc", (char *)prop->value, prop->length))
243 if (tilcdc_prop_str_update(prop, lcdc->full_name, &kft))
244 goto out;
245 }
246
247 tilcdc_node_disable(slave);
248
249 ret = of_overlay_create(overlay);
250 if (ret)
251 pr_err("%s: Creating overlay failed: %d\n", __func__, ret);
252 else
253 pr_info("%s: ti,tilcdc,slave node successfully converted\n",
254 __func__);
255out:
256 kfree_table_free(&kft);
257 of_node_put(i2c);
258 of_node_put(slave);
259 of_node_put(lcdc);
260 of_node_put(fragment);
261}
262
263static int __init tilcdc_slave_compat_init(void)
264{
265 tilcdc_convert_slave_node();
266 return 0;
267}
268
269subsys_initcall(tilcdc_slave_compat_init);
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.dts b/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.dts
deleted file mode 100644
index 693f8b0aea2d..000000000000
--- a/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.dts
+++ /dev/null
@@ -1,72 +0,0 @@
1/*
2 * DTS overlay for converting ti,tilcdc,slave binding to new binding.
3 *
4 * Copyright (C) 2015 Texas Instruments Inc.
5 * Author: Jyri Sarha <jsarha@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 */
11
12/*
13 * target-path property values are simple tags that are replaced with
14 * correct values in tildcdc_slave_compat.c. Some properties are also
15 * copied over from the ti,tilcdc,slave node.
16 */
17
18/dts-v1/;
19/ {
20 fragment@0 {
21 target-path = "i2c";
22 __overlay__ {
23 #address-cells = <1>;
24 #size-cells = <0>;
25 tda19988 {
26 compatible = "nxp,tda998x";
27 reg = <0x70>;
28 status = "okay";
29
30 port {
31 hdmi_0: endpoint@0 {
32 remote-endpoint = <&lcd_0>;
33 };
34 };
35 };
36 };
37 };
38
39 fragment@1 {
40 target-path = "lcdc";
41 __overlay__ {
42 port {
43 lcd_0: endpoint@0 {
44 remote-endpoint = <&hdmi_0>;
45 };
46 };
47 };
48 };
49
50 __local_fixups__ {
51 fragment@0 {
52 __overlay__ {
53 tda19988 {
54 port {
55 endpoint@0 {
56 remote-endpoint = <0>;
57 };
58 };
59 };
60 };
61 };
62 fragment@1 {
63 __overlay__ {
64 port {
65 endpoint@0 {
66 remote-endpoint = <0>;
67 };
68 };
69 };
70 };
71 };
72};
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.h b/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.h
deleted file mode 100644
index 403d35d87d0b..000000000000
--- a/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * Copyright (C) 2015 Texas Instruments
3 * Author: Jyri Sarha <jsarha@ti.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17/* This header declares the symbols defined in tilcdc_slave_compat.dts */
18
19#ifndef __TILCDC_SLAVE_COMPAT_H__
20#define __TILCDC_SLAVE_COMPAT_H__
21
22extern uint8_t __dtb_tilcdc_slave_compat_begin[];
23extern uint8_t __dtb_tilcdc_slave_compat_end[];
24
25#endif /* __TILCDC_SLAVE_COMPAT_H__ */
diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c
index 316f831ad5f0..b0551aa677b8 100644
--- a/drivers/gpu/drm/ttm/ttm_page_alloc.c
+++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c
@@ -744,12 +744,14 @@ static void ttm_put_pages(struct page **pages, unsigned npages, int flags,
744 } 744 }
745 745
746#ifdef CONFIG_TRANSPARENT_HUGEPAGE 746#ifdef CONFIG_TRANSPARENT_HUGEPAGE
747 for (j = 0; j < HPAGE_PMD_NR; ++j) 747 if (!(flags & TTM_PAGE_FLAG_DMA32)) {
748 if (p++ != pages[i + j]) 748 for (j = 0; j < HPAGE_PMD_NR; ++j)
749 break; 749 if (p++ != pages[i + j])
750 break;
750 751
751 if (j == HPAGE_PMD_NR) 752 if (j == HPAGE_PMD_NR)
752 order = HPAGE_PMD_ORDER; 753 order = HPAGE_PMD_ORDER;
754 }
753#endif 755#endif
754 756
755 if (page_count(pages[i]) != 1) 757 if (page_count(pages[i]) != 1)
@@ -865,20 +867,22 @@ static int ttm_get_pages(struct page **pages, unsigned npages, int flags,
865 867
866 i = 0; 868 i = 0;
867#ifdef CONFIG_TRANSPARENT_HUGEPAGE 869#ifdef CONFIG_TRANSPARENT_HUGEPAGE
868 while (npages >= HPAGE_PMD_NR) { 870 if (!(gfp_flags & GFP_DMA32)) {
869 gfp_t huge_flags = gfp_flags; 871 while (npages >= HPAGE_PMD_NR) {
872 gfp_t huge_flags = gfp_flags;
870 873
871 huge_flags |= GFP_TRANSHUGE; 874 huge_flags |= GFP_TRANSHUGE;
872 huge_flags &= ~__GFP_MOVABLE; 875 huge_flags &= ~__GFP_MOVABLE;
873 huge_flags &= ~__GFP_COMP; 876 huge_flags &= ~__GFP_COMP;
874 p = alloc_pages(huge_flags, HPAGE_PMD_ORDER); 877 p = alloc_pages(huge_flags, HPAGE_PMD_ORDER);
875 if (!p) 878 if (!p)
876 break; 879 break;
877 880
878 for (j = 0; j < HPAGE_PMD_NR; ++j) 881 for (j = 0; j < HPAGE_PMD_NR; ++j)
879 pages[i++] = p++; 882 pages[i++] = p++;
880 883
881 npages -= HPAGE_PMD_NR; 884 npages -= HPAGE_PMD_NR;
885 }
882 } 886 }
883#endif 887#endif
884 888
diff --git a/drivers/gpu/drm/vc4/vc4_bo.c b/drivers/gpu/drm/vc4/vc4_bo.c
index 01a53ba304f8..98a6cb9f44fc 100644
--- a/drivers/gpu/drm/vc4/vc4_bo.c
+++ b/drivers/gpu/drm/vc4/vc4_bo.c
@@ -88,11 +88,11 @@ int vc4_bo_stats_debugfs(struct seq_file *m, void *unused)
88 88
89 mutex_lock(&vc4->purgeable.lock); 89 mutex_lock(&vc4->purgeable.lock);
90 if (vc4->purgeable.num) 90 if (vc4->purgeable.num)
91 seq_printf(m, "%30s: %6dkb BOs (%d)\n", "userspace BO cache", 91 seq_printf(m, "%30s: %6zdkb BOs (%d)\n", "userspace BO cache",
92 vc4->purgeable.size / 1024, vc4->purgeable.num); 92 vc4->purgeable.size / 1024, vc4->purgeable.num);
93 93
94 if (vc4->purgeable.purged_num) 94 if (vc4->purgeable.purged_num)
95 seq_printf(m, "%30s: %6dkb BOs (%d)\n", "total purged BO", 95 seq_printf(m, "%30s: %6zdkb BOs (%d)\n", "total purged BO",
96 vc4->purgeable.purged_size / 1024, 96 vc4->purgeable.purged_size / 1024,
97 vc4->purgeable.purged_num); 97 vc4->purgeable.purged_num);
98 mutex_unlock(&vc4->purgeable.lock); 98 mutex_unlock(&vc4->purgeable.lock);
diff --git a/drivers/gpu/ipu-v3/ipu-dc.c b/drivers/gpu/ipu-v3/ipu-dc.c
index 7a4b8362dda8..49bfe6e7d005 100644
--- a/drivers/gpu/ipu-v3/ipu-dc.c
+++ b/drivers/gpu/ipu-v3/ipu-dc.c
@@ -249,11 +249,8 @@ EXPORT_SYMBOL_GPL(ipu_dc_enable);
249 249
250void ipu_dc_enable_channel(struct ipu_dc *dc) 250void ipu_dc_enable_channel(struct ipu_dc *dc)
251{ 251{
252 int di;
253 u32 reg; 252 u32 reg;
254 253
255 di = dc->di;
256
257 reg = readl(dc->base + DC_WR_CH_CONF); 254 reg = readl(dc->base + DC_WR_CH_CONF);
258 reg |= DC_WR_CH_CONF_PROG_TYPE_NORMAL; 255 reg |= DC_WR_CH_CONF_PROG_TYPE_NORMAL;
259 writel(reg, dc->base + DC_WR_CH_CONF); 256 writel(reg, dc->base + DC_WR_CH_CONF);
diff --git a/include/drm/amd_asic_type.h b/include/drm/amd_asic_type.h
new file mode 100644
index 000000000000..599028f66585
--- /dev/null
+++ b/include/drm/amd_asic_type.h
@@ -0,0 +1,52 @@
1/*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef __AMD_ASIC_TYPE_H__
24#define __AMD_ASIC_TYPE_H__
25/*
26 * Supported ASIC types
27 */
28enum amd_asic_type {
29 CHIP_TAHITI = 0,
30 CHIP_PITCAIRN,
31 CHIP_VERDE,
32 CHIP_OLAND,
33 CHIP_HAINAN,
34 CHIP_BONAIRE,
35 CHIP_KAVERI,
36 CHIP_KABINI,
37 CHIP_HAWAII,
38 CHIP_MULLINS,
39 CHIP_TOPAZ,
40 CHIP_TONGA,
41 CHIP_FIJI,
42 CHIP_CARRIZO,
43 CHIP_STONEY,
44 CHIP_POLARIS10,
45 CHIP_POLARIS11,
46 CHIP_POLARIS12,
47 CHIP_VEGA10,
48 CHIP_RAVEN,
49 CHIP_LAST,
50};
51
52#endif /*__AMD_ASIC_TYPE_H__ */
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index b4285c40e1e4..df9807a3caae 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -284,6 +284,11 @@ struct drm_display_info {
284 * @hdmi: advance features of a HDMI sink. 284 * @hdmi: advance features of a HDMI sink.
285 */ 285 */
286 struct drm_hdmi_info hdmi; 286 struct drm_hdmi_info hdmi;
287
288 /**
289 * @non_desktop: Non desktop display (HMD).
290 */
291 bool non_desktop;
287}; 292};
288 293
289int drm_display_info_set_bus_formats(struct drm_display_info *info, 294int drm_display_info_set_bus_formats(struct drm_display_info *info,
@@ -933,6 +938,7 @@ static inline unsigned drm_connector_index(struct drm_connector *connector)
933/** 938/**
934 * drm_connector_lookup - lookup connector object 939 * drm_connector_lookup - lookup connector object
935 * @dev: DRM device 940 * @dev: DRM device
941 * @file_priv: drm file to check for lease against.
936 * @id: connector object id 942 * @id: connector object id
937 * 943 *
938 * This function looks up the connector object specified by id 944 * This function looks up the connector object specified by id
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index f7fcceef46d9..a2d81d2907a9 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -952,6 +952,7 @@ struct drm_crtc *drm_crtc_from_index(struct drm_device *dev, int idx);
952/** 952/**
953 * drm_crtc_find - look up a CRTC object from its ID 953 * drm_crtc_find - look up a CRTC object from its ID
954 * @dev: DRM device 954 * @dev: DRM device
955 * @file_priv: drm file to check for lease against.
955 * @id: &drm_mode_object ID 956 * @id: &drm_mode_object ID
956 * 957 *
957 * This can be used to look up a CRTC from its userspace ID. Only used by 958 * This can be used to look up a CRTC from its userspace ID. Only used by
diff --git a/include/drm/drm_encoder.h b/include/drm/drm_encoder.h
index 86db0da8bdcb..ee4cfbe63c52 100644
--- a/include/drm/drm_encoder.h
+++ b/include/drm/drm_encoder.h
@@ -208,6 +208,7 @@ static inline bool drm_encoder_crtc_ok(struct drm_encoder *encoder,
208/** 208/**
209 * drm_encoder_find - find a &drm_encoder 209 * drm_encoder_find - find a &drm_encoder
210 * @dev: DRM device 210 * @dev: DRM device
211 * @file_priv: drm file to check for lease against.
211 * @id: encoder id 212 * @id: encoder id
212 * 213 *
213 * Returns the encoder with @id, NULL if it doesn't exist. Simple wrapper around 214 * Returns the encoder with @id, NULL if it doesn't exist. Simple wrapper around
diff --git a/include/drm/drm_mode_config.h b/include/drm/drm_mode_config.h
index 0b4ac2ebc610..b21e827c5c78 100644
--- a/include/drm/drm_mode_config.h
+++ b/include/drm/drm_mode_config.h
@@ -728,6 +728,13 @@ struct drm_mode_config {
728 */ 728 */
729 struct drm_property *suggested_y_property; 729 struct drm_property *suggested_y_property;
730 730
731 /**
732 * @non_desktop_property: Optional connector property with a hint
733 * that device isn't a standard display, and the console/desktop,
734 * should not be displayed on it.
735 */
736 struct drm_property *non_desktop_property;
737
731 /* dumb ioctl parameters */ 738 /* dumb ioctl parameters */
732 uint32_t preferred_depth, prefer_shadow; 739 uint32_t preferred_depth, prefer_shadow;
733 740
diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h
index 069c4c8ce360..571615079230 100644
--- a/include/drm/drm_plane.h
+++ b/include/drm/drm_plane.h
@@ -591,6 +591,7 @@ int drm_mode_plane_set_obj_prop(struct drm_plane *plane,
591/** 591/**
592 * drm_plane_find - find a &drm_plane 592 * drm_plane_find - find a &drm_plane
593 * @dev: DRM device 593 * @dev: DRM device
594 * @file_priv: drm file to check for lease against.
594 * @id: plane id 595 * @id: plane id
595 * 596 *
596 * Returns the plane with @id, NULL if it doesn't exist. Simple wrapper around 597 * Returns the plane with @id, NULL if it doesn't exist. Simple wrapper around
diff --git a/include/drm/drm_property.h b/include/drm/drm_property.h
index 429d8218f740..8a522b4bed40 100644
--- a/include/drm/drm_property.h
+++ b/include/drm/drm_property.h
@@ -305,8 +305,9 @@ drm_property_unreference_blob(struct drm_property_blob *blob)
305} 305}
306 306
307/** 307/**
308 * drm_connector_find - find property object 308 * drm_property_find - find property object
309 * @dev: DRM device 309 * @dev: DRM device
310 * @file_priv: drm file to check for lease against.
310 * @id: property object id 311 * @id: property object id
311 * 312 *
312 * This function looks up the property object specified by id and returns it. 313 * This function looks up the property object specified by id and returns it.
diff --git a/include/dt-bindings/msm/msm-bus-ids.h b/include/dt-bindings/msm/msm-bus-ids.h
deleted file mode 100644
index a75d304473d5..000000000000
--- a/include/dt-bindings/msm/msm-bus-ids.h
+++ /dev/null
@@ -1,887 +0,0 @@
1/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#ifndef __MSM_BUS_IDS_H
14#define __MSM_BUS_IDS_H
15
16/* Aggregation types */
17#define AGG_SCHEME_NONE 0
18#define AGG_SCHEME_LEG 1
19#define AGG_SCHEME_1 2
20
21/* Topology related enums */
22#define MSM_BUS_FAB_DEFAULT 0
23#define MSM_BUS_FAB_APPSS 0
24#define MSM_BUS_FAB_SYSTEM 1024
25#define MSM_BUS_FAB_MMSS 2048
26#define MSM_BUS_FAB_SYSTEM_FPB 3072
27#define MSM_BUS_FAB_CPSS_FPB 4096
28
29#define MSM_BUS_FAB_BIMC 0
30#define MSM_BUS_FAB_SYS_NOC 1024
31#define MSM_BUS_FAB_MMSS_NOC 2048
32#define MSM_BUS_FAB_OCMEM_NOC 3072
33#define MSM_BUS_FAB_PERIPH_NOC 4096
34#define MSM_BUS_FAB_CONFIG_NOC 5120
35#define MSM_BUS_FAB_OCMEM_VNOC 6144
36#define MSM_BUS_FAB_MMSS_AHB 2049
37#define MSM_BUS_FAB_A0_NOC 6145
38#define MSM_BUS_FAB_A1_NOC 6146
39#define MSM_BUS_FAB_A2_NOC 6147
40#define MSM_BUS_FAB_GNOC 6148
41#define MSM_BUS_FAB_CR_VIRT 6149
42
43#define MSM_BUS_MASTER_FIRST 1
44#define MSM_BUS_MASTER_AMPSS_M0 1
45#define MSM_BUS_MASTER_AMPSS_M1 2
46#define MSM_BUS_APPSS_MASTER_FAB_MMSS 3
47#define MSM_BUS_APPSS_MASTER_FAB_SYSTEM 4
48#define MSM_BUS_SYSTEM_MASTER_FAB_APPSS 5
49#define MSM_BUS_MASTER_SPS 6
50#define MSM_BUS_MASTER_ADM_PORT0 7
51#define MSM_BUS_MASTER_ADM_PORT1 8
52#define MSM_BUS_SYSTEM_MASTER_ADM1_PORT0 9
53#define MSM_BUS_MASTER_ADM1_PORT1 10
54#define MSM_BUS_MASTER_LPASS_PROC 11
55#define MSM_BUS_MASTER_MSS_PROCI 12
56#define MSM_BUS_MASTER_MSS_PROCD 13
57#define MSM_BUS_MASTER_MSS_MDM_PORT0 14
58#define MSM_BUS_MASTER_LPASS 15
59#define MSM_BUS_SYSTEM_MASTER_CPSS_FPB 16
60#define MSM_BUS_SYSTEM_MASTER_SYSTEM_FPB 17
61#define MSM_BUS_SYSTEM_MASTER_MMSS_FPB 18
62#define MSM_BUS_MASTER_ADM1_CI 19
63#define MSM_BUS_MASTER_ADM0_CI 20
64#define MSM_BUS_MASTER_MSS_MDM_PORT1 21
65#define MSM_BUS_MASTER_MDP_PORT0 22
66#define MSM_BUS_MASTER_MDP_PORT1 23
67#define MSM_BUS_MMSS_MASTER_ADM1_PORT0 24
68#define MSM_BUS_MASTER_ROTATOR 25
69#define MSM_BUS_MASTER_GRAPHICS_3D 26
70#define MSM_BUS_MASTER_JPEG_DEC 27
71#define MSM_BUS_MASTER_GRAPHICS_2D_CORE0 28
72#define MSM_BUS_MASTER_VFE 29
73#define MSM_BUS_MASTER_VFE0 MSM_BUS_MASTER_VFE
74#define MSM_BUS_MASTER_VPE 30
75#define MSM_BUS_MASTER_JPEG_ENC 31
76#define MSM_BUS_MASTER_GRAPHICS_2D_CORE1 32
77#define MSM_BUS_MMSS_MASTER_APPS_FAB 33
78#define MSM_BUS_MASTER_HD_CODEC_PORT0 34
79#define MSM_BUS_MASTER_HD_CODEC_PORT1 35
80#define MSM_BUS_MASTER_SPDM 36
81#define MSM_BUS_MASTER_RPM 37
82#define MSM_BUS_MASTER_MSS 38
83#define MSM_BUS_MASTER_RIVA 39
84#define MSM_BUS_MASTER_SNOC_VMEM 40
85#define MSM_BUS_MASTER_MSS_SW_PROC 41
86#define MSM_BUS_MASTER_MSS_FW_PROC 42
87#define MSM_BUS_MASTER_HMSS 43
88#define MSM_BUS_MASTER_GSS_NAV 44
89#define MSM_BUS_MASTER_PCIE 45
90#define MSM_BUS_MASTER_SATA 46
91#define MSM_BUS_MASTER_CRYPTO 47
92#define MSM_BUS_MASTER_VIDEO_CAP 48
93#define MSM_BUS_MASTER_GRAPHICS_3D_PORT1 49
94#define MSM_BUS_MASTER_VIDEO_ENC 50
95#define MSM_BUS_MASTER_VIDEO_DEC 51
96#define MSM_BUS_MASTER_LPASS_AHB 52
97#define MSM_BUS_MASTER_QDSS_BAM 53
98#define MSM_BUS_MASTER_SNOC_CFG 54
99#define MSM_BUS_MASTER_CRYPTO_CORE0 55
100#define MSM_BUS_MASTER_CRYPTO_CORE1 56
101#define MSM_BUS_MASTER_MSS_NAV 57
102#define MSM_BUS_MASTER_OCMEM_DMA 58
103#define MSM_BUS_MASTER_WCSS 59
104#define MSM_BUS_MASTER_QDSS_ETR 60
105#define MSM_BUS_MASTER_USB3 61
106#define MSM_BUS_MASTER_JPEG 62
107#define MSM_BUS_MASTER_VIDEO_P0 63
108#define MSM_BUS_MASTER_VIDEO_P1 64
109#define MSM_BUS_MASTER_MSS_PROC 65
110#define MSM_BUS_MASTER_JPEG_OCMEM 66
111#define MSM_BUS_MASTER_MDP_OCMEM 67
112#define MSM_BUS_MASTER_VIDEO_P0_OCMEM 68
113#define MSM_BUS_MASTER_VIDEO_P1_OCMEM 69
114#define MSM_BUS_MASTER_VFE_OCMEM 70
115#define MSM_BUS_MASTER_CNOC_ONOC_CFG 71
116#define MSM_BUS_MASTER_RPM_INST 72
117#define MSM_BUS_MASTER_RPM_DATA 73
118#define MSM_BUS_MASTER_RPM_SYS 74
119#define MSM_BUS_MASTER_DEHR 75
120#define MSM_BUS_MASTER_QDSS_DAP 76
121#define MSM_BUS_MASTER_TIC 77
122#define MSM_BUS_MASTER_SDCC_1 78
123#define MSM_BUS_MASTER_SDCC_3 79
124#define MSM_BUS_MASTER_SDCC_4 80
125#define MSM_BUS_MASTER_SDCC_2 81
126#define MSM_BUS_MASTER_TSIF 82
127#define MSM_BUS_MASTER_BAM_DMA 83
128#define MSM_BUS_MASTER_BLSP_2 84
129#define MSM_BUS_MASTER_USB_HSIC 85
130#define MSM_BUS_MASTER_BLSP_1 86
131#define MSM_BUS_MASTER_USB_HS 87
132#define MSM_BUS_MASTER_PNOC_CFG 88
133#define MSM_BUS_MASTER_V_OCMEM_GFX3D 89
134#define MSM_BUS_MASTER_IPA 90
135#define MSM_BUS_MASTER_QPIC 91
136#define MSM_BUS_MASTER_MDPE 92
137#define MSM_BUS_MASTER_USB_HS2 93
138#define MSM_BUS_MASTER_VPU 94
139#define MSM_BUS_MASTER_UFS 95
140#define MSM_BUS_MASTER_BCAST 96
141#define MSM_BUS_MASTER_CRYPTO_CORE2 97
142#define MSM_BUS_MASTER_EMAC 98
143#define MSM_BUS_MASTER_VPU_1 99
144#define MSM_BUS_MASTER_PCIE_1 100
145#define MSM_BUS_MASTER_USB3_1 101
146#define MSM_BUS_MASTER_CNOC_MNOC_MMSS_CFG 102
147#define MSM_BUS_MASTER_CNOC_MNOC_CFG 103
148#define MSM_BUS_MASTER_TCU_0 104
149#define MSM_BUS_MASTER_TCU_1 105
150#define MSM_BUS_MASTER_CPP 106
151#define MSM_BUS_MASTER_AUDIO 107
152#define MSM_BUS_MASTER_PCIE_2 108
153#define MSM_BUS_MASTER_VFE1 109
154#define MSM_BUS_MASTER_XM_USB_HS1 110
155#define MSM_BUS_MASTER_PCNOC_BIMC_1 111
156#define MSM_BUS_MASTER_BIMC_PCNOC 112
157#define MSM_BUS_MASTER_XI_USB_HSIC 113
158#define MSM_BUS_MASTER_SGMII 114
159#define MSM_BUS_SPMI_FETCHER 115
160#define MSM_BUS_MASTER_GNOC_BIMC 116
161#define MSM_BUS_MASTER_CRVIRT_A2NOC 117
162#define MSM_BUS_MASTER_CNOC_A2NOC 118
163#define MSM_BUS_MASTER_WLAN 119
164#define MSM_BUS_MASTER_MSS_CE 120
165#define MSM_BUS_MASTER_CDSP_PROC 121
166#define MSM_BUS_MASTER_GNOC_SNOC 122
167#define MSM_BUS_MASTER_PIMEM 123
168#define MSM_BUS_MASTER_MASTER_LAST 124
169
170#define MSM_BUS_SYSTEM_FPB_MASTER_SYSTEM MSM_BUS_SYSTEM_MASTER_SYSTEM_FPB
171#define MSM_BUS_CPSS_FPB_MASTER_SYSTEM MSM_BUS_SYSTEM_MASTER_CPSS_FPB
172
173#define MSM_BUS_SNOC_MM_INT_0 10000
174#define MSM_BUS_SNOC_MM_INT_1 10001
175#define MSM_BUS_SNOC_MM_INT_2 10002
176#define MSM_BUS_SNOC_MM_INT_BIMC 10003
177#define MSM_BUS_SNOC_INT_0 10004
178#define MSM_BUS_SNOC_INT_1 10005
179#define MSM_BUS_SNOC_INT_BIMC 10006
180#define MSM_BUS_SNOC_BIMC_0_MAS 10007
181#define MSM_BUS_SNOC_BIMC_1_MAS 10008
182#define MSM_BUS_SNOC_QDSS_INT 10009
183#define MSM_BUS_PNOC_SNOC_MAS 10010
184#define MSM_BUS_PNOC_SNOC_SLV 10011
185#define MSM_BUS_PNOC_INT_0 10012
186#define MSM_BUS_PNOC_INT_1 10013
187#define MSM_BUS_PNOC_M_0 10014
188#define MSM_BUS_PNOC_M_1 10015
189#define MSM_BUS_BIMC_SNOC_MAS 10016
190#define MSM_BUS_BIMC_SNOC_SLV 10017
191#define MSM_BUS_PNOC_SLV_0 10018
192#define MSM_BUS_PNOC_SLV_1 10019
193#define MSM_BUS_PNOC_SLV_2 10020
194#define MSM_BUS_PNOC_SLV_3 10021
195#define MSM_BUS_PNOC_SLV_4 10022
196#define MSM_BUS_PNOC_SLV_8 10023
197#define MSM_BUS_PNOC_SLV_9 10024
198#define MSM_BUS_SNOC_BIMC_0_SLV 10025
199#define MSM_BUS_SNOC_BIMC_1_SLV 10026
200#define MSM_BUS_MNOC_BIMC_MAS 10027
201#define MSM_BUS_MNOC_BIMC_SLV 10028
202#define MSM_BUS_BIMC_MNOC_MAS 10029
203#define MSM_BUS_BIMC_MNOC_SLV 10030
204#define MSM_BUS_SNOC_BIMC_MAS 10031
205#define MSM_BUS_SNOC_BIMC_SLV 10032
206#define MSM_BUS_CNOC_SNOC_MAS 10033
207#define MSM_BUS_CNOC_SNOC_SLV 10034
208#define MSM_BUS_SNOC_CNOC_MAS 10035
209#define MSM_BUS_SNOC_CNOC_SLV 10036
210#define MSM_BUS_OVNOC_SNOC_MAS 10037
211#define MSM_BUS_OVNOC_SNOC_SLV 10038
212#define MSM_BUS_SNOC_OVNOC_MAS 10039
213#define MSM_BUS_SNOC_OVNOC_SLV 10040
214#define MSM_BUS_SNOC_PNOC_MAS 10041
215#define MSM_BUS_SNOC_PNOC_SLV 10042
216#define MSM_BUS_BIMC_INT_APPS_EBI 10043
217#define MSM_BUS_BIMC_INT_APPS_SNOC 10044
218#define MSM_BUS_SNOC_BIMC_2_MAS 10045
219#define MSM_BUS_SNOC_BIMC_2_SLV 10046
220#define MSM_BUS_PNOC_SLV_5 10047
221#define MSM_BUS_PNOC_SLV_7 10048
222#define MSM_BUS_PNOC_INT_2 10049
223#define MSM_BUS_PNOC_INT_3 10050
224#define MSM_BUS_PNOC_INT_4 10051
225#define MSM_BUS_PNOC_INT_5 10052
226#define MSM_BUS_PNOC_INT_6 10053
227#define MSM_BUS_PNOC_INT_7 10054
228#define MSM_BUS_BIMC_SNOC_1_MAS 10055
229#define MSM_BUS_BIMC_SNOC_1_SLV 10056
230#define MSM_BUS_PNOC_A1NOC_MAS 10057
231#define MSM_BUS_PNOC_A1NOC_SLV 10058
232#define MSM_BUS_CNOC_A1NOC_MAS 10059
233#define MSM_BUS_A0NOC_SNOC_MAS 10060
234#define MSM_BUS_A0NOC_SNOC_SLV 10061
235#define MSM_BUS_A1NOC_SNOC_SLV 10062
236#define MSM_BUS_A1NOC_SNOC_MAS 10063
237#define MSM_BUS_A2NOC_SNOC_MAS 10064
238#define MSM_BUS_A2NOC_SNOC_SLV 10065
239#define MSM_BUS_SNOC_INT_2 10066
240#define MSM_BUS_A0NOC_QDSS_INT 10067
241#define MSM_BUS_INT_LAST 10068
242
243#define MSM_BUS_INT_TEST_ID 20000
244#define MSM_BUS_INT_TEST_LAST 20050
245
246#define MSM_BUS_SLAVE_FIRST 512
247#define MSM_BUS_SLAVE_EBI_CH0 512
248#define MSM_BUS_SLAVE_EBI_CH1 513
249#define MSM_BUS_SLAVE_AMPSS_L2 514
250#define MSM_BUS_APPSS_SLAVE_FAB_MMSS 515
251#define MSM_BUS_APPSS_SLAVE_FAB_SYSTEM 516
252#define MSM_BUS_SYSTEM_SLAVE_FAB_APPS 517
253#define MSM_BUS_SLAVE_SPS 518
254#define MSM_BUS_SLAVE_SYSTEM_IMEM 519
255#define MSM_BUS_SLAVE_AMPSS 520
256#define MSM_BUS_SLAVE_MSS 521
257#define MSM_BUS_SLAVE_LPASS 522
258#define MSM_BUS_SYSTEM_SLAVE_CPSS_FPB 523
259#define MSM_BUS_SYSTEM_SLAVE_SYSTEM_FPB 524
260#define MSM_BUS_SYSTEM_SLAVE_MMSS_FPB 525
261#define MSM_BUS_SLAVE_CORESIGHT 526
262#define MSM_BUS_SLAVE_RIVA 527
263#define MSM_BUS_SLAVE_SMI 528
264#define MSM_BUS_MMSS_SLAVE_FAB_APPS 529
265#define MSM_BUS_MMSS_SLAVE_FAB_APPS_1 530
266#define MSM_BUS_SLAVE_MM_IMEM 531
267#define MSM_BUS_SLAVE_CRYPTO 532
268#define MSM_BUS_SLAVE_SPDM 533
269#define MSM_BUS_SLAVE_RPM 534
270#define MSM_BUS_SLAVE_RPM_MSG_RAM 535
271#define MSM_BUS_SLAVE_MPM 536
272#define MSM_BUS_SLAVE_PMIC1_SSBI1_A 537
273#define MSM_BUS_SLAVE_PMIC1_SSBI1_B 538
274#define MSM_BUS_SLAVE_PMIC1_SSBI1_C 539
275#define MSM_BUS_SLAVE_PMIC2_SSBI2_A 540
276#define MSM_BUS_SLAVE_PMIC2_SSBI2_B 541
277#define MSM_BUS_SLAVE_GSBI1_UART 542
278#define MSM_BUS_SLAVE_GSBI2_UART 543
279#define MSM_BUS_SLAVE_GSBI3_UART 544
280#define MSM_BUS_SLAVE_GSBI4_UART 545
281#define MSM_BUS_SLAVE_GSBI5_UART 546
282#define MSM_BUS_SLAVE_GSBI6_UART 547
283#define MSM_BUS_SLAVE_GSBI7_UART 548
284#define MSM_BUS_SLAVE_GSBI8_UART 549
285#define MSM_BUS_SLAVE_GSBI9_UART 550
286#define MSM_BUS_SLAVE_GSBI10_UART 551
287#define MSM_BUS_SLAVE_GSBI11_UART 552
288#define MSM_BUS_SLAVE_GSBI12_UART 553
289#define MSM_BUS_SLAVE_GSBI1_QUP 554
290#define MSM_BUS_SLAVE_GSBI2_QUP 555
291#define MSM_BUS_SLAVE_GSBI3_QUP 556
292#define MSM_BUS_SLAVE_GSBI4_QUP 557
293#define MSM_BUS_SLAVE_GSBI5_QUP 558
294#define MSM_BUS_SLAVE_GSBI6_QUP 559
295#define MSM_BUS_SLAVE_GSBI7_QUP 560
296#define MSM_BUS_SLAVE_GSBI8_QUP 561
297#define MSM_BUS_SLAVE_GSBI9_QUP 562
298#define MSM_BUS_SLAVE_GSBI10_QUP 563
299#define MSM_BUS_SLAVE_GSBI11_QUP 564
300#define MSM_BUS_SLAVE_GSBI12_QUP 565
301#define MSM_BUS_SLAVE_EBI2_NAND 566
302#define MSM_BUS_SLAVE_EBI2_CS0 567
303#define MSM_BUS_SLAVE_EBI2_CS1 568
304#define MSM_BUS_SLAVE_EBI2_CS2 569
305#define MSM_BUS_SLAVE_EBI2_CS3 570
306#define MSM_BUS_SLAVE_EBI2_CS4 571
307#define MSM_BUS_SLAVE_EBI2_CS5 572
308#define MSM_BUS_SLAVE_USB_FS1 573
309#define MSM_BUS_SLAVE_USB_FS2 574
310#define MSM_BUS_SLAVE_TSIF 575
311#define MSM_BUS_SLAVE_MSM_TSSC 576
312#define MSM_BUS_SLAVE_MSM_PDM 577
313#define MSM_BUS_SLAVE_MSM_DIMEM 578
314#define MSM_BUS_SLAVE_MSM_TCSR 579
315#define MSM_BUS_SLAVE_MSM_PRNG 580
316#define MSM_BUS_SLAVE_GSS 581
317#define MSM_BUS_SLAVE_SATA 582
318#define MSM_BUS_SLAVE_USB3 583
319#define MSM_BUS_SLAVE_WCSS 584
320#define MSM_BUS_SLAVE_OCIMEM 585
321#define MSM_BUS_SLAVE_SNOC_OCMEM 586
322#define MSM_BUS_SLAVE_SERVICE_SNOC 587
323#define MSM_BUS_SLAVE_QDSS_STM 588
324#define MSM_BUS_SLAVE_CAMERA_CFG 589
325#define MSM_BUS_SLAVE_DISPLAY_CFG 590
326#define MSM_BUS_SLAVE_OCMEM_CFG 591
327#define MSM_BUS_SLAVE_CPR_CFG 592
328#define MSM_BUS_SLAVE_CPR_XPU_CFG 593
329#define MSM_BUS_SLAVE_MISC_CFG 594
330#define MSM_BUS_SLAVE_MISC_XPU_CFG 595
331#define MSM_BUS_SLAVE_VENUS_CFG 596
332#define MSM_BUS_SLAVE_MISC_VENUS_CFG 597
333#define MSM_BUS_SLAVE_GRAPHICS_3D_CFG 598
334#define MSM_BUS_SLAVE_MMSS_CLK_CFG 599
335#define MSM_BUS_SLAVE_MMSS_CLK_XPU_CFG 600
336#define MSM_BUS_SLAVE_MNOC_MPU_CFG 601
337#define MSM_BUS_SLAVE_ONOC_MPU_CFG 602
338#define MSM_BUS_SLAVE_SERVICE_MNOC 603
339#define MSM_BUS_SLAVE_OCMEM 604
340#define MSM_BUS_SLAVE_SERVICE_ONOC 605
341#define MSM_BUS_SLAVE_SDCC_1 606
342#define MSM_BUS_SLAVE_SDCC_3 607
343#define MSM_BUS_SLAVE_SDCC_2 608
344#define MSM_BUS_SLAVE_SDCC_4 609
345#define MSM_BUS_SLAVE_BAM_DMA 610
346#define MSM_BUS_SLAVE_BLSP_2 611
347#define MSM_BUS_SLAVE_USB_HSIC 612
348#define MSM_BUS_SLAVE_BLSP_1 613
349#define MSM_BUS_SLAVE_USB_HS 614
350#define MSM_BUS_SLAVE_PDM 615
351#define MSM_BUS_SLAVE_PERIPH_APU_CFG 616
352#define MSM_BUS_SLAVE_PNOC_MPU_CFG 617
353#define MSM_BUS_SLAVE_PRNG 618
354#define MSM_BUS_SLAVE_SERVICE_PNOC 619
355#define MSM_BUS_SLAVE_CLK_CTL 620
356#define MSM_BUS_SLAVE_CNOC_MSS 621
357#define MSM_BUS_SLAVE_SECURITY 622
358#define MSM_BUS_SLAVE_TCSR 623
359#define MSM_BUS_SLAVE_TLMM 624
360#define MSM_BUS_SLAVE_CRYPTO_0_CFG 625
361#define MSM_BUS_SLAVE_CRYPTO_1_CFG 626
362#define MSM_BUS_SLAVE_IMEM_CFG 627
363#define MSM_BUS_SLAVE_MESSAGE_RAM 628
364#define MSM_BUS_SLAVE_BIMC_CFG 629
365#define MSM_BUS_SLAVE_BOOT_ROM 630
366#define MSM_BUS_SLAVE_CNOC_MNOC_MMSS_CFG 631
367#define MSM_BUS_SLAVE_PMIC_ARB 632
368#define MSM_BUS_SLAVE_SPDM_WRAPPER 633
369#define MSM_BUS_SLAVE_DEHR_CFG 634
370#define MSM_BUS_SLAVE_QDSS_CFG 635
371#define MSM_BUS_SLAVE_RBCPR_CFG 636
372#define MSM_BUS_SLAVE_RBCPR_QDSS_APU_CFG 637
373#define MSM_BUS_SLAVE_SNOC_MPU_CFG 638
374#define MSM_BUS_SLAVE_CNOC_ONOC_CFG 639
375#define MSM_BUS_SLAVE_CNOC_MNOC_CFG 640
376#define MSM_BUS_SLAVE_PNOC_CFG 641
377#define MSM_BUS_SLAVE_SNOC_CFG 642
378#define MSM_BUS_SLAVE_EBI1_DLL_CFG 643
379#define MSM_BUS_SLAVE_PHY_APU_CFG 644
380#define MSM_BUS_SLAVE_EBI1_PHY_CFG 645
381#define MSM_BUS_SLAVE_SERVICE_CNOC 646
382#define MSM_BUS_SLAVE_IPS_CFG 647
383#define MSM_BUS_SLAVE_QPIC 648
384#define MSM_BUS_SLAVE_DSI_CFG 649
385#define MSM_BUS_SLAVE_UFS_CFG 650
386#define MSM_BUS_SLAVE_RBCPR_CX_CFG 651
387#define MSM_BUS_SLAVE_RBCPR_MX_CFG 652
388#define MSM_BUS_SLAVE_PCIE_CFG 653
389#define MSM_BUS_SLAVE_USB_PHYS_CFG 654
390#define MSM_BUS_SLAVE_VIDEO_CAP_CFG 655
391#define MSM_BUS_SLAVE_AVSYNC_CFG 656
392#define MSM_BUS_SLAVE_CRYPTO_2_CFG 657
393#define MSM_BUS_SLAVE_VPU_CFG 658
394#define MSM_BUS_SLAVE_BCAST_CFG 659
395#define MSM_BUS_SLAVE_KLM_CFG 660
396#define MSM_BUS_SLAVE_GENI_IR_CFG 661
397#define MSM_BUS_SLAVE_OCMEM_GFX 662
398#define MSM_BUS_SLAVE_CATS_128 663
399#define MSM_BUS_SLAVE_OCMEM_64 664
400#define MSM_BUS_SLAVE_PCIE_0 665
401#define MSM_BUS_SLAVE_PCIE_1 666
402#define MSM_BUS_SLAVE_PCIE_0_CFG 667
403#define MSM_BUS_SLAVE_PCIE_1_CFG 668
404#define MSM_BUS_SLAVE_SRVC_MNOC 669
405#define MSM_BUS_SLAVE_USB_HS2 670
406#define MSM_BUS_SLAVE_AUDIO 671
407#define MSM_BUS_SLAVE_TCU 672
408#define MSM_BUS_SLAVE_APPSS 673
409#define MSM_BUS_SLAVE_PCIE_PARF 674
410#define MSM_BUS_SLAVE_USB3_PHY_CFG 675
411#define MSM_BUS_SLAVE_IPA_CFG 676
412#define MSM_BUS_SLAVE_A0NOC_SNOC 677
413#define MSM_BUS_SLAVE_A1NOC_SNOC 678
414#define MSM_BUS_SLAVE_A2NOC_SNOC 679
415#define MSM_BUS_SLAVE_HMSS_L3 680
416#define MSM_BUS_SLAVE_PIMEM_CFG 681
417#define MSM_BUS_SLAVE_DCC_CFG 682
418#define MSM_BUS_SLAVE_QDSS_RBCPR_APU_CFG 683
419#define MSM_BUS_SLAVE_PCIE_2_CFG 684
420#define MSM_BUS_SLAVE_PCIE20_AHB2PHY 685
421#define MSM_BUS_SLAVE_A0NOC_CFG 686
422#define MSM_BUS_SLAVE_A1NOC_CFG 687
423#define MSM_BUS_SLAVE_A2NOC_CFG 688
424#define MSM_BUS_SLAVE_A1NOC_MPU_CFG 689
425#define MSM_BUS_SLAVE_A2NOC_MPU_CFG 690
426#define MSM_BUS_SLAVE_A0NOC_SMMU_CFG 691
427#define MSM_BUS_SLAVE_A1NOC_SMMU_CFG 692
428#define MSM_BUS_SLAVE_A2NOC_SMMU_CFG 693
429#define MSM_BUS_SLAVE_LPASS_SMMU_CFG 694
430#define MSM_BUS_SLAVE_MMAGIC_CFG 695
431#define MSM_BUS_SLAVE_VENUS_THROTTLE_CFG 696
432#define MSM_BUS_SLAVE_SSC_CFG 697
433#define MSM_BUS_SLAVE_DSA_CFG 698
434#define MSM_BUS_SLAVE_DSA_MPU_CFG 699
435#define MSM_BUS_SLAVE_DISPLAY_THROTTLE_CFG 700
436#define MSM_BUS_SLAVE_SMMU_CPP_CFG 701
437#define MSM_BUS_SLAVE_SMMU_JPEG_CFG 702
438#define MSM_BUS_SLAVE_SMMU_MDP_CFG 703
439#define MSM_BUS_SLAVE_SMMU_ROTATOR_CFG 704
440#define MSM_BUS_SLAVE_SMMU_VENUS_CFG 705
441#define MSM_BUS_SLAVE_SMMU_VFE_CFG 706
442#define MSM_BUS_SLAVE_A0NOC_MPU_CFG 707
443#define MSM_BUS_SLAVE_VMEM_CFG 708
444#define MSM_BUS_SLAVE_CAMERA_THROTTLE_CFG 709
445#define MSM_BUS_SLAVE_VMEM 710
446#define MSM_BUS_SLAVE_AHB2PHY 711
447#define MSM_BUS_SLAVE_PIMEM 712
448#define MSM_BUS_SLAVE_SNOC_VMEM 713
449#define MSM_BUS_SLAVE_PCIE_2 714
450#define MSM_BUS_SLAVE_RBCPR_MX 715
451#define MSM_BUS_SLAVE_RBCPR_CX 716
452#define MSM_BUS_SLAVE_BIMC_PCNOC 717
453#define MSM_BUS_SLAVE_PCNOC_BIMC_1 718
454#define MSM_BUS_SLAVE_SGMII 719
455#define MSM_BUS_SLAVE_SPMI_FETCHER 720
456#define MSM_BUS_PNOC_SLV_6 721
457#define MSM_BUS_SLAVE_MMSS_SMMU_CFG 722
458#define MSM_BUS_SLAVE_WLAN 723
459#define MSM_BUS_SLAVE_CRVIRT_A2NOC 724
460#define MSM_BUS_SLAVE_CNOC_A2NOC 725
461#define MSM_BUS_SLAVE_GLM 726
462#define MSM_BUS_SLAVE_GNOC_BIMC 727
463#define MSM_BUS_SLAVE_GNOC_SNOC 728
464#define MSM_BUS_SLAVE_QM_CFG 729
465#define MSM_BUS_SLAVE_TLMM_EAST 730
466#define MSM_BUS_SLAVE_TLMM_NORTH 731
467#define MSM_BUS_SLAVE_TLMM_WEST 732
468#define MSM_BUS_SLAVE_SKL 733
469#define MSM_BUS_SLAVE_LPASS_TCM 734
470#define MSM_BUS_SLAVE_TLMM_SOUTH 735
471#define MSM_BUS_SLAVE_TLMM_CENTER 736
472#define MSM_BUS_MSS_NAV_CE_MPU_CFG 737
473#define MSM_BUS_SLAVE_A2NOC_THROTTLE_CFG 738
474#define MSM_BUS_SLAVE_CDSP 739
475#define MSM_BUS_SLAVE_CDSP_SMMU_CFG 740
476#define MSM_BUS_SLAVE_LPASS_MPU_CFG 741
477#define MSM_BUS_SLAVE_CSI_PHY_CFG 742
478#define MSM_BUS_SLAVE_LAST 743
479
480#define MSM_BUS_SYSTEM_FPB_SLAVE_SYSTEM MSM_BUS_SYSTEM_SLAVE_SYSTEM_FPB
481#define MSM_BUS_CPSS_FPB_SLAVE_SYSTEM MSM_BUS_SYSTEM_SLAVE_CPSS_FPB
482
483/*
484 * ID's used in RPM messages
485 */
486#define ICBID_MASTER_APPSS_PROC 0
487#define ICBID_MASTER_MSS_PROC 1
488#define ICBID_MASTER_MNOC_BIMC 2
489#define ICBID_MASTER_SNOC_BIMC 3
490#define ICBID_MASTER_SNOC_BIMC_0 ICBID_MASTER_SNOC_BIMC
491#define ICBID_MASTER_CNOC_MNOC_MMSS_CFG 4
492#define ICBID_MASTER_CNOC_MNOC_CFG 5
493#define ICBID_MASTER_GFX3D 6
494#define ICBID_MASTER_JPEG 7
495#define ICBID_MASTER_MDP 8
496#define ICBID_MASTER_MDP0 ICBID_MASTER_MDP
497#define ICBID_MASTER_MDPS ICBID_MASTER_MDP
498#define ICBID_MASTER_VIDEO 9
499#define ICBID_MASTER_VIDEO_P0 ICBID_MASTER_VIDEO
500#define ICBID_MASTER_VIDEO_P1 10
501#define ICBID_MASTER_VFE 11
502#define ICBID_MASTER_VFE0 ICBID_MASTER_VFE
503#define ICBID_MASTER_CNOC_ONOC_CFG 12
504#define ICBID_MASTER_JPEG_OCMEM 13
505#define ICBID_MASTER_MDP_OCMEM 14
506#define ICBID_MASTER_VIDEO_P0_OCMEM 15
507#define ICBID_MASTER_VIDEO_P1_OCMEM 16
508#define ICBID_MASTER_VFE_OCMEM 17
509#define ICBID_MASTER_LPASS_AHB 18
510#define ICBID_MASTER_QDSS_BAM 19
511#define ICBID_MASTER_SNOC_CFG 20
512#define ICBID_MASTER_BIMC_SNOC 21
513#define ICBID_MASTER_BIMC_SNOC_0 ICBID_MASTER_BIMC_SNOC
514#define ICBID_MASTER_CNOC_SNOC 22
515#define ICBID_MASTER_CRYPTO 23
516#define ICBID_MASTER_CRYPTO_CORE0 ICBID_MASTER_CRYPTO
517#define ICBID_MASTER_CRYPTO_CORE1 24
518#define ICBID_MASTER_LPASS_PROC 25
519#define ICBID_MASTER_MSS 26
520#define ICBID_MASTER_MSS_NAV 27
521#define ICBID_MASTER_OCMEM_DMA 28
522#define ICBID_MASTER_PNOC_SNOC 29
523#define ICBID_MASTER_WCSS 30
524#define ICBID_MASTER_QDSS_ETR 31
525#define ICBID_MASTER_USB3 32
526#define ICBID_MASTER_USB3_0 ICBID_MASTER_USB3
527#define ICBID_MASTER_SDCC_1 33
528#define ICBID_MASTER_SDCC_3 34
529#define ICBID_MASTER_SDCC_2 35
530#define ICBID_MASTER_SDCC_4 36
531#define ICBID_MASTER_TSIF 37
532#define ICBID_MASTER_BAM_DMA 38
533#define ICBID_MASTER_BLSP_2 39
534#define ICBID_MASTER_USB_HSIC 40
535#define ICBID_MASTER_BLSP_1 41
536#define ICBID_MASTER_USB_HS 42
537#define ICBID_MASTER_USB_HS1 ICBID_MASTER_USB_HS
538#define ICBID_MASTER_PNOC_CFG 43
539#define ICBID_MASTER_SNOC_PNOC 44
540#define ICBID_MASTER_RPM_INST 45
541#define ICBID_MASTER_RPM_DATA 46
542#define ICBID_MASTER_RPM_SYS 47
543#define ICBID_MASTER_DEHR 48
544#define ICBID_MASTER_QDSS_DAP 49
545#define ICBID_MASTER_SPDM 50
546#define ICBID_MASTER_TIC 51
547#define ICBID_MASTER_SNOC_CNOC 52
548#define ICBID_MASTER_GFX3D_OCMEM 53
549#define ICBID_MASTER_GFX3D_GMEM ICBID_MASTER_GFX3D_OCMEM
550#define ICBID_MASTER_OVIRT_SNOC 54
551#define ICBID_MASTER_SNOC_OVIRT 55
552#define ICBID_MASTER_SNOC_GVIRT ICBID_MASTER_SNOC_OVIRT
553#define ICBID_MASTER_ONOC_OVIRT 56
554#define ICBID_MASTER_USB_HS2 57
555#define ICBID_MASTER_QPIC 58
556#define ICBID_MASTER_IPA 59
557#define ICBID_MASTER_DSI 60
558#define ICBID_MASTER_MDP1 61
559#define ICBID_MASTER_MDPE ICBID_MASTER_MDP1
560#define ICBID_MASTER_VPU_PROC 62
561#define ICBID_MASTER_VPU 63
562#define ICBID_MASTER_VPU0 ICBID_MASTER_VPU
563#define ICBID_MASTER_CRYPTO_CORE2 64
564#define ICBID_MASTER_PCIE_0 65
565#define ICBID_MASTER_PCIE_1 66
566#define ICBID_MASTER_SATA 67
567#define ICBID_MASTER_UFS 68
568#define ICBID_MASTER_USB3_1 69
569#define ICBID_MASTER_VIDEO_OCMEM 70
570#define ICBID_MASTER_VPU1 71
571#define ICBID_MASTER_VCAP 72
572#define ICBID_MASTER_EMAC 73
573#define ICBID_MASTER_BCAST 74
574#define ICBID_MASTER_MMSS_PROC 75
575#define ICBID_MASTER_SNOC_BIMC_1 76
576#define ICBID_MASTER_SNOC_PCNOC 77
577#define ICBID_MASTER_AUDIO 78
578#define ICBID_MASTER_MM_INT_0 79
579#define ICBID_MASTER_MM_INT_1 80
580#define ICBID_MASTER_MM_INT_2 81
581#define ICBID_MASTER_MM_INT_BIMC 82
582#define ICBID_MASTER_MSS_INT 83
583#define ICBID_MASTER_PCNOC_CFG 84
584#define ICBID_MASTER_PCNOC_INT_0 85
585#define ICBID_MASTER_PCNOC_INT_1 86
586#define ICBID_MASTER_PCNOC_M_0 87
587#define ICBID_MASTER_PCNOC_M_1 88
588#define ICBID_MASTER_PCNOC_S_0 89
589#define ICBID_MASTER_PCNOC_S_1 90
590#define ICBID_MASTER_PCNOC_S_2 91
591#define ICBID_MASTER_PCNOC_S_3 92
592#define ICBID_MASTER_PCNOC_S_4 93
593#define ICBID_MASTER_PCNOC_S_6 94
594#define ICBID_MASTER_PCNOC_S_7 95
595#define ICBID_MASTER_PCNOC_S_8 96
596#define ICBID_MASTER_PCNOC_S_9 97
597#define ICBID_MASTER_QDSS_INT 98
598#define ICBID_MASTER_SNOC_INT_0 99
599#define ICBID_MASTER_SNOC_INT_1 100
600#define ICBID_MASTER_SNOC_INT_BIMC 101
601#define ICBID_MASTER_TCU_0 102
602#define ICBID_MASTER_TCU_1 103
603#define ICBID_MASTER_BIMC_INT_0 104
604#define ICBID_MASTER_BIMC_INT_1 105
605#define ICBID_MASTER_CAMERA 106
606#define ICBID_MASTER_RICA 107
607#define ICBID_MASTER_SNOC_BIMC_2 108
608#define ICBID_MASTER_BIMC_SNOC_1 109
609#define ICBID_MASTER_A0NOC_SNOC 110
610#define ICBID_MASTER_A1NOC_SNOC 111
611#define ICBID_MASTER_A2NOC_SNOC 112
612#define ICBID_MASTER_PIMEM 113
613#define ICBID_MASTER_SNOC_VMEM 114
614#define ICBID_MASTER_CPP 115
615#define ICBID_MASTER_CNOC_A1NOC 116
616#define ICBID_MASTER_PNOC_A1NOC 117
617#define ICBID_MASTER_HMSS 118
618#define ICBID_MASTER_PCIE_2 119
619#define ICBID_MASTER_ROTATOR 120
620#define ICBID_MASTER_VENUS_VMEM 121
621#define ICBID_MASTER_DCC 122
622#define ICBID_MASTER_MCDMA 123
623#define ICBID_MASTER_PCNOC_INT_2 124
624#define ICBID_MASTER_PCNOC_INT_3 125
625#define ICBID_MASTER_PCNOC_INT_4 126
626#define ICBID_MASTER_PCNOC_INT_5 127
627#define ICBID_MASTER_PCNOC_INT_6 128
628#define ICBID_MASTER_PCNOC_S_5 129
629#define ICBID_MASTER_SENSORS_AHB 130
630#define ICBID_MASTER_SENSORS_PROC 131
631#define ICBID_MASTER_QSPI 132
632#define ICBID_MASTER_VFE1 133
633#define ICBID_MASTER_SNOC_INT_2 134
634#define ICBID_MASTER_SMMNOC_BIMC 135
635#define ICBID_MASTER_CRVIRT_A1NOC 136
636#define ICBID_MASTER_XM_USB_HS1 137
637#define ICBID_MASTER_XI_USB_HS1 138
638#define ICBID_MASTER_PCNOC_BIMC_1 139
639#define ICBID_MASTER_BIMC_PCNOC 140
640#define ICBID_MASTER_XI_HSIC 141
641#define ICBID_MASTER_SGMII 142
642#define ICBID_MASTER_SPMI_FETCHER 143
643#define ICBID_MASTER_GNOC_BIMC 144
644#define ICBID_MASTER_CRVIRT_A2NOC 145
645#define ICBID_MASTER_CNOC_A2NOC 146
646#define ICBID_MASTER_WLAN 147
647#define ICBID_MASTER_MSS_CE 148
648#define ICBID_MASTER_CDSP_PROC 149
649#define ICBID_MASTER_GNOC_SNOC 150
650
651#define ICBID_SLAVE_EBI1 0
652#define ICBID_SLAVE_APPSS_L2 1
653#define ICBID_SLAVE_BIMC_SNOC 2
654#define ICBID_SLAVE_BIMC_SNOC_0 ICBID_SLAVE_BIMC_SNOC
655#define ICBID_SLAVE_CAMERA_CFG 3
656#define ICBID_SLAVE_DISPLAY_CFG 4
657#define ICBID_SLAVE_OCMEM_CFG 5
658#define ICBID_SLAVE_CPR_CFG 6
659#define ICBID_SLAVE_CPR_XPU_CFG 7
660#define ICBID_SLAVE_MISC_CFG 8
661#define ICBID_SLAVE_MISC_XPU_CFG 9
662#define ICBID_SLAVE_VENUS_CFG 10
663#define ICBID_SLAVE_GFX3D_CFG 11
664#define ICBID_SLAVE_MMSS_CLK_CFG 12
665#define ICBID_SLAVE_MMSS_CLK_XPU_CFG 13
666#define ICBID_SLAVE_MNOC_MPU_CFG 14
667#define ICBID_SLAVE_ONOC_MPU_CFG 15
668#define ICBID_SLAVE_MNOC_BIMC 16
669#define ICBID_SLAVE_SERVICE_MNOC 17
670#define ICBID_SLAVE_OCMEM 18
671#define ICBID_SLAVE_GMEM ICBID_SLAVE_OCMEM
672#define ICBID_SLAVE_SERVICE_ONOC 19
673#define ICBID_SLAVE_APPSS 20
674#define ICBID_SLAVE_LPASS 21
675#define ICBID_SLAVE_USB3 22
676#define ICBID_SLAVE_USB3_0 ICBID_SLAVE_USB3
677#define ICBID_SLAVE_WCSS 23
678#define ICBID_SLAVE_SNOC_BIMC 24
679#define ICBID_SLAVE_SNOC_BIMC_0 ICBID_SLAVE_SNOC_BIMC
680#define ICBID_SLAVE_SNOC_CNOC 25
681#define ICBID_SLAVE_IMEM 26
682#define ICBID_SLAVE_OCIMEM ICBID_SLAVE_IMEM
683#define ICBID_SLAVE_SNOC_OVIRT 27
684#define ICBID_SLAVE_SNOC_GVIRT ICBID_SLAVE_SNOC_OVIRT
685#define ICBID_SLAVE_SNOC_PNOC 28
686#define ICBID_SLAVE_SNOC_PCNOC ICBID_SLAVE_SNOC_PNOC
687#define ICBID_SLAVE_SERVICE_SNOC 29
688#define ICBID_SLAVE_QDSS_STM 30
689#define ICBID_SLAVE_SDCC_1 31
690#define ICBID_SLAVE_SDCC_3 32
691#define ICBID_SLAVE_SDCC_2 33
692#define ICBID_SLAVE_SDCC_4 34
693#define ICBID_SLAVE_TSIF 35
694#define ICBID_SLAVE_BAM_DMA 36
695#define ICBID_SLAVE_BLSP_2 37
696#define ICBID_SLAVE_USB_HSIC 38
697#define ICBID_SLAVE_BLSP_1 39
698#define ICBID_SLAVE_USB_HS 40
699#define ICBID_SLAVE_USB_HS1 ICBID_SLAVE_USB_HS
700#define ICBID_SLAVE_PDM 41
701#define ICBID_SLAVE_PERIPH_APU_CFG 42
702#define ICBID_SLAVE_PNOC_MPU_CFG 43
703#define ICBID_SLAVE_PRNG 44
704#define ICBID_SLAVE_PNOC_SNOC 45
705#define ICBID_SLAVE_PCNOC_SNOC ICBID_SLAVE_PNOC_SNOC
706#define ICBID_SLAVE_SERVICE_PNOC 46
707#define ICBID_SLAVE_CLK_CTL 47
708#define ICBID_SLAVE_CNOC_MSS 48
709#define ICBID_SLAVE_PCNOC_MSS ICBID_SLAVE_CNOC_MSS
710#define ICBID_SLAVE_SECURITY 49
711#define ICBID_SLAVE_TCSR 50
712#define ICBID_SLAVE_TLMM 51
713#define ICBID_SLAVE_CRYPTO_0_CFG 52
714#define ICBID_SLAVE_CRYPTO_1_CFG 53
715#define ICBID_SLAVE_IMEM_CFG 54
716#define ICBID_SLAVE_MESSAGE_RAM 55
717#define ICBID_SLAVE_BIMC_CFG 56
718#define ICBID_SLAVE_BOOT_ROM 57
719#define ICBID_SLAVE_CNOC_MNOC_MMSS_CFG 58
720#define ICBID_SLAVE_PMIC_ARB 59
721#define ICBID_SLAVE_SPDM_WRAPPER 60
722#define ICBID_SLAVE_DEHR_CFG 61
723#define ICBID_SLAVE_MPM 62
724#define ICBID_SLAVE_QDSS_CFG 63
725#define ICBID_SLAVE_RBCPR_CFG 64
726#define ICBID_SLAVE_RBCPR_CX_CFG ICBID_SLAVE_RBCPR_CFG
727#define ICBID_SLAVE_RBCPR_QDSS_APU_CFG 65
728#define ICBID_SLAVE_CNOC_MNOC_CFG 66
729#define ICBID_SLAVE_SNOC_MPU_CFG 67
730#define ICBID_SLAVE_CNOC_ONOC_CFG 68
731#define ICBID_SLAVE_PNOC_CFG 69
732#define ICBID_SLAVE_SNOC_CFG 70
733#define ICBID_SLAVE_EBI1_DLL_CFG 71
734#define ICBID_SLAVE_PHY_APU_CFG 72
735#define ICBID_SLAVE_EBI1_PHY_CFG 73
736#define ICBID_SLAVE_RPM 74
737#define ICBID_SLAVE_CNOC_SNOC 75
738#define ICBID_SLAVE_SERVICE_CNOC 76
739#define ICBID_SLAVE_OVIRT_SNOC 77
740#define ICBID_SLAVE_OVIRT_OCMEM 78
741#define ICBID_SLAVE_USB_HS2 79
742#define ICBID_SLAVE_QPIC 80
743#define ICBID_SLAVE_IPS_CFG 81
744#define ICBID_SLAVE_DSI_CFG 82
745#define ICBID_SLAVE_USB3_1 83
746#define ICBID_SLAVE_PCIE_0 84
747#define ICBID_SLAVE_PCIE_1 85
748#define ICBID_SLAVE_PSS_SMMU_CFG 86
749#define ICBID_SLAVE_CRYPTO_2_CFG 87
750#define ICBID_SLAVE_PCIE_0_CFG 88
751#define ICBID_SLAVE_PCIE_1_CFG 89
752#define ICBID_SLAVE_SATA_CFG 90
753#define ICBID_SLAVE_SPSS_GENI_IR 91
754#define ICBID_SLAVE_UFS_CFG 92
755#define ICBID_SLAVE_AVSYNC_CFG 93
756#define ICBID_SLAVE_VPU_CFG 94
757#define ICBID_SLAVE_USB_PHY_CFG 95
758#define ICBID_SLAVE_RBCPR_MX_CFG 96
759#define ICBID_SLAVE_PCIE_PARF 97
760#define ICBID_SLAVE_VCAP_CFG 98
761#define ICBID_SLAVE_EMAC_CFG 99
762#define ICBID_SLAVE_BCAST_CFG 100
763#define ICBID_SLAVE_KLM_CFG 101
764#define ICBID_SLAVE_DISPLAY_PWM 102
765#define ICBID_SLAVE_GENI 103
766#define ICBID_SLAVE_SNOC_BIMC_1 104
767#define ICBID_SLAVE_AUDIO 105
768#define ICBID_SLAVE_CATS_0 106
769#define ICBID_SLAVE_CATS_1 107
770#define ICBID_SLAVE_MM_INT_0 108
771#define ICBID_SLAVE_MM_INT_1 109
772#define ICBID_SLAVE_MM_INT_2 110
773#define ICBID_SLAVE_MM_INT_BIMC 111
774#define ICBID_SLAVE_MMU_MODEM_XPU_CFG 112
775#define ICBID_SLAVE_MSS_INT 113
776#define ICBID_SLAVE_PCNOC_INT_0 114
777#define ICBID_SLAVE_PCNOC_INT_1 115
778#define ICBID_SLAVE_PCNOC_M_0 116
779#define ICBID_SLAVE_PCNOC_M_1 117
780#define ICBID_SLAVE_PCNOC_S_0 118
781#define ICBID_SLAVE_PCNOC_S_1 119
782#define ICBID_SLAVE_PCNOC_S_2 120
783#define ICBID_SLAVE_PCNOC_S_3 121
784#define ICBID_SLAVE_PCNOC_S_4 122
785#define ICBID_SLAVE_PCNOC_S_6 123
786#define ICBID_SLAVE_PCNOC_S_7 124
787#define ICBID_SLAVE_PCNOC_S_8 125
788#define ICBID_SLAVE_PCNOC_S_9 126
789#define ICBID_SLAVE_PRNG_XPU_CFG 127
790#define ICBID_SLAVE_QDSS_INT 128
791#define ICBID_SLAVE_RPM_XPU_CFG 129
792#define ICBID_SLAVE_SNOC_INT_0 130
793#define ICBID_SLAVE_SNOC_INT_1 131
794#define ICBID_SLAVE_SNOC_INT_BIMC 132
795#define ICBID_SLAVE_TCU 133
796#define ICBID_SLAVE_BIMC_INT_0 134
797#define ICBID_SLAVE_BIMC_INT_1 135
798#define ICBID_SLAVE_RICA_CFG 136
799#define ICBID_SLAVE_SNOC_BIMC_2 137
800#define ICBID_SLAVE_BIMC_SNOC_1 138
801#define ICBID_SLAVE_PNOC_A1NOC 139
802#define ICBID_SLAVE_SNOC_VMEM 140
803#define ICBID_SLAVE_A0NOC_SNOC 141
804#define ICBID_SLAVE_A1NOC_SNOC 142
805#define ICBID_SLAVE_A2NOC_SNOC 143
806#define ICBID_SLAVE_A0NOC_CFG 144
807#define ICBID_SLAVE_A0NOC_MPU_CFG 145
808#define ICBID_SLAVE_A0NOC_SMMU_CFG 146
809#define ICBID_SLAVE_A1NOC_CFG 147
810#define ICBID_SLAVE_A1NOC_MPU_CFG 148
811#define ICBID_SLAVE_A1NOC_SMMU_CFG 149
812#define ICBID_SLAVE_A2NOC_CFG 150
813#define ICBID_SLAVE_A2NOC_MPU_CFG 151
814#define ICBID_SLAVE_A2NOC_SMMU_CFG 152
815#define ICBID_SLAVE_AHB2PHY 153
816#define ICBID_SLAVE_CAMERA_THROTTLE_CFG 154
817#define ICBID_SLAVE_DCC_CFG 155
818#define ICBID_SLAVE_DISPLAY_THROTTLE_CFG 156
819#define ICBID_SLAVE_DSA_CFG 157
820#define ICBID_SLAVE_DSA_MPU_CFG 158
821#define ICBID_SLAVE_SSC_MPU_CFG 159
822#define ICBID_SLAVE_HMSS_L3 160
823#define ICBID_SLAVE_LPASS_SMMU_CFG 161
824#define ICBID_SLAVE_MMAGIC_CFG 162
825#define ICBID_SLAVE_PCIE20_AHB2PHY 163
826#define ICBID_SLAVE_PCIE_2 164
827#define ICBID_SLAVE_PCIE_2_CFG 165
828#define ICBID_SLAVE_PIMEM 166
829#define ICBID_SLAVE_PIMEM_CFG 167
830#define ICBID_SLAVE_QDSS_RBCPR_APU_CFG 168
831#define ICBID_SLAVE_RBCPR_CX 169
832#define ICBID_SLAVE_RBCPR_MX 170
833#define ICBID_SLAVE_SMMU_CPP_CFG 171
834#define ICBID_SLAVE_SMMU_JPEG_CFG 172
835#define ICBID_SLAVE_SMMU_MDP_CFG 173
836#define ICBID_SLAVE_SMMU_ROTATOR_CFG 174
837#define ICBID_SLAVE_SMMU_VENUS_CFG 175
838#define ICBID_SLAVE_SMMU_VFE_CFG 176
839#define ICBID_SLAVE_SSC_CFG 177
840#define ICBID_SLAVE_VENUS_THROTTLE_CFG 178
841#define ICBID_SLAVE_VMEM 179
842#define ICBID_SLAVE_VMEM_CFG 180
843#define ICBID_SLAVE_QDSS_MPU_CFG 181
844#define ICBID_SLAVE_USB3_PHY_CFG 182
845#define ICBID_SLAVE_IPA_CFG 183
846#define ICBID_SLAVE_PCNOC_INT_2 184
847#define ICBID_SLAVE_PCNOC_INT_3 185
848#define ICBID_SLAVE_PCNOC_INT_4 186
849#define ICBID_SLAVE_PCNOC_INT_5 187
850#define ICBID_SLAVE_PCNOC_INT_6 188
851#define ICBID_SLAVE_PCNOC_S_5 189
852#define ICBID_SLAVE_QSPI 190
853#define ICBID_SLAVE_A1NOC_MS_MPU_CFG 191
854#define ICBID_SLAVE_A2NOC_MS_MPU_CFG 192
855#define ICBID_SLAVE_MODEM_Q6_SMMU_CFG 193
856#define ICBID_SLAVE_MSS_MPU_CFG 194
857#define ICBID_SLAVE_MSS_PROC_MS_MPU_CFG 195
858#define ICBID_SLAVE_SKL 196
859#define ICBID_SLAVE_SNOC_INT_2 197
860#define ICBID_SLAVE_SMMNOC_BIMC 198
861#define ICBID_SLAVE_CRVIRT_A1NOC 199
862#define ICBID_SLAVE_SGMII 200
863#define ICBID_SLAVE_QHS4_APPS 201
864#define ICBID_SLAVE_BIMC_PCNOC 202
865#define ICBID_SLAVE_PCNOC_BIMC_1 203
866#define ICBID_SLAVE_SPMI_FETCHER 204
867#define ICBID_SLAVE_MMSS_SMMU_CFG 205
868#define ICBID_SLAVE_WLAN 206
869#define ICBID_SLAVE_CRVIRT_A2NOC 207
870#define ICBID_SLAVE_CNOC_A2NOC 208
871#define ICBID_SLAVE_GLM 209
872#define ICBID_SLAVE_GNOC_BIMC 210
873#define ICBID_SLAVE_GNOC_SNOC 211
874#define ICBID_SLAVE_QM_CFG 212
875#define ICBID_SLAVE_TLMM_EAST 213
876#define ICBID_SLAVE_TLMM_NORTH 214
877#define ICBID_SLAVE_TLMM_WEST 215
878#define ICBID_SLAVE_LPASS_TCM 216
879#define ICBID_SLAVE_TLMM_SOUTH 217
880#define ICBID_SLAVE_TLMM_CENTER 218
881#define ICBID_SLAVE_MSS_NAV_CE_MPU_CFG 219
882#define ICBID_SLAVE_A2NOC_THROTTLE_CFG 220
883#define ICBID_SLAVE_CDSP 221
884#define ICBID_SLAVE_CDSP_SMMU_CFG 222
885#define ICBID_SLAVE_LPASS_MPU_CFG 223
886#define ICBID_SLAVE_CSI_PHY_CFG 224
887#endif
diff --git a/sound/soc/amd/acp-pcm-dma.c b/sound/soc/amd/acp-pcm-dma.c
index 08b1399d1da2..dcbf9973884d 100644
--- a/sound/soc/amd/acp-pcm-dma.c
+++ b/sound/soc/amd/acp-pcm-dma.c
@@ -73,12 +73,6 @@ static const struct snd_pcm_hardware acp_pcm_hardware_capture = {
73 .periods_max = CAPTURE_MAX_NUM_PERIODS, 73 .periods_max = CAPTURE_MAX_NUM_PERIODS,
74}; 74};
75 75
76struct audio_drv_data {
77 struct snd_pcm_substream *play_stream;
78 struct snd_pcm_substream *capture_stream;
79 void __iomem *acp_mmio;
80};
81
82static u32 acp_reg_read(void __iomem *acp_mmio, u32 reg) 76static u32 acp_reg_read(void __iomem *acp_mmio, u32 reg)
83{ 77{
84 return readl(acp_mmio + (reg * 4)); 78 return readl(acp_mmio + (reg * 4));
@@ -916,6 +910,7 @@ static int acp_audio_probe(struct platform_device *pdev)
916 int status; 910 int status;
917 struct audio_drv_data *audio_drv_data; 911 struct audio_drv_data *audio_drv_data;
918 struct resource *res; 912 struct resource *res;
913 const u32 *pdata = pdev->dev.platform_data;
919 914
920 audio_drv_data = devm_kzalloc(&pdev->dev, sizeof(struct audio_drv_data), 915 audio_drv_data = devm_kzalloc(&pdev->dev, sizeof(struct audio_drv_data),
921 GFP_KERNEL); 916 GFP_KERNEL);
@@ -932,6 +927,7 @@ static int acp_audio_probe(struct platform_device *pdev)
932 927
933 audio_drv_data->play_stream = NULL; 928 audio_drv_data->play_stream = NULL;
934 audio_drv_data->capture_stream = NULL; 929 audio_drv_data->capture_stream = NULL;
930 audio_drv_data->asic_type = *pdata;
935 931
936 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 932 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
937 if (!res) { 933 if (!res) {
diff --git a/sound/soc/amd/acp.h b/sound/soc/amd/acp.h
index 330832ef4e5e..28cf9140f49c 100644
--- a/sound/soc/amd/acp.h
+++ b/sound/soc/amd/acp.h
@@ -84,6 +84,13 @@ struct audio_substream_data {
84 void __iomem *acp_mmio; 84 void __iomem *acp_mmio;
85}; 85};
86 86
87struct audio_drv_data {
88 struct snd_pcm_substream *play_stream;
89 struct snd_pcm_substream *capture_stream;
90 void __iomem *acp_mmio;
91 u32 asic_type;
92};
93
87enum { 94enum {
88 ACP_TILE_P1 = 0, 95 ACP_TILE_P1 = 0,
89 ACP_TILE_P2, 96 ACP_TILE_P2,
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-15 15:37:46 -0400