2 files changed, 24 insertions, 6 deletions

diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index 15114febfd92..790306e921c8 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -53,12 +53,18 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable)
         if (gate->lock)
                 spin_lock_irqsave(gate->lock, flags);
 
-        reg = readl(gate->reg);
-
-        if (set)
-                reg |= BIT(gate->bit_idx);
-        else
-                reg &= ~BIT(gate->bit_idx);
+        if (gate->flags & CLK_GATE_HIWORD_MASK) {
+                reg = BIT(gate->bit_idx + 16);
+                if (set)
+                        reg |= BIT(gate->bit_idx);
+        } else {
+                reg = readl(gate->reg);
+
+                if (set)
+                        reg |= BIT(gate->bit_idx);
+                else
+                        reg &= ~BIT(gate->bit_idx);
+        }
 
         writel(reg, gate->reg);
 
@@ -121,6 +127,13 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
         struct clk *clk;
         struct clk_init_data init;
 
+        if (clk_gate_flags & CLK_GATE_HIWORD_MASK) {
+                if (bit_idx > 16) {
+                        pr_err("gate bit exceeds LOWORD field\n");
+                        return ERR_PTR(-EINVAL);
+                }
+        }
+
         /* allocate the gate */
         gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
         if (!gate) {
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index d77f1267f419..1ec14a732176 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -210,6 +210,10 @@ void of_fixed_clk_setup(struct device_node *np);
  * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
  *      enable the clock.  Setting this flag does the opposite: setting the bit
  *      disable the clock and clearing it enables the clock
+ * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
+ *   of this register, and mask of gate bits are in higher 16-bit of this
+ *   register.  While setting the gate bits, higher 16-bit should also be
+ *   updated to indicate changing gate bits.
  */
 struct clk_gate {
         struct clk_hw hw;
@@ -220,6 +224,7 @@ struct clk_gate {
 };
 
 #define CLK_GATE_SET_TO_DISABLE         BIT(0)
+#define CLK_GATE_HIWORD_MASK            BIT(1)
 
 extern const struct clk_ops clk_gate_ops;
 struct clk *clk_register_gate(struct device *dev, const char *name,