7 files changed, 39 insertions, 1 deletions

diff --git a/Documentation/devicetree/bindings/dma/snps-dma.txt b/Documentation/devicetree/bindings/dma/snps-dma.txt
index 39e2b26be344..db757df7057d 100644
--- a/Documentation/devicetree/bindings/dma/snps-dma.txt
+++ b/Documentation/devicetree/bindings/dma/snps-dma.txt
@@ -27,6 +27,10 @@ Optional properties:
   general purpose DMA channel allocator. False if not passed.
 - multi-block: Multi block transfers supported by hardware. Array property with
   one cell per channel. 0: not supported, 1 (default): supported.
+- snps,dma-protection-control: AHB HPROT[3:1] protection setting.
+  The default value is 0 (for non-cacheable, non-buffered,
+  unprivileged data access).
+  Refer to include/dt-bindings/dma/dw-dmac.h for possible values.
 
 Example:
 
diff --git a/MAINTAINERS b/MAINTAINERS
index f4855974f325..dc041fe9b3af 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14363,9 +14363,11 @@ SYNOPSYS DESIGNWARE DMAC DRIVER
 M:      Viresh Kumar <vireshk@kernel.org>
 R:      Andy Shevchenko <andriy.shevchenko@linux.intel.com>
 S:      Maintained
+F:      Documentation/devicetree/bindings/dma/snps-dma.txt
+F:      drivers/dma/dw/
+F:      include/dt-bindings/dma/dw-dmac.h
 F:      include/linux/dma/dw.h
 F:      include/linux/platform_data/dma-dw.h
-F:      drivers/dma/dw/
 
 SYNOPSYS DESIGNWARE ENTERPRISE ETHERNET DRIVER
 M:      Jose Abreu <Jose.Abreu@synopsys.com>
diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
index d0c3e50b39fb..2c5ca1961256 100644
--- a/drivers/dma/dw/core.c
+++ b/drivers/dma/dw/core.c
@@ -160,12 +160,14 @@ static void dwc_initialize_chan_idma32(struct dw_dma_chan *dwc)
 
 static void dwc_initialize_chan_dw(struct dw_dma_chan *dwc)
 {
+        struct dw_dma *dw = to_dw_dma(dwc->chan.device);
         u32 cfghi = DWC_CFGH_FIFO_MODE;
         u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
         bool hs_polarity = dwc->dws.hs_polarity;
 
         cfghi |= DWC_CFGH_DST_PER(dwc->dws.dst_id);
         cfghi |= DWC_CFGH_SRC_PER(dwc->dws.src_id);
+        cfghi |= DWC_CFGH_PROTCTL(dw->pdata->protctl);
 
         /* Set polarity of handshake interface */
         cfglo |= hs_polarity ? DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL : 0;
diff --git a/drivers/dma/dw/platform.c b/drivers/dma/dw/platform.c
index f01b2c173fa6..31ff8113c3de 100644
--- a/drivers/dma/dw/platform.c
+++ b/drivers/dma/dw/platform.c
@@ -162,6 +162,12 @@ dw_dma_parse_dt(struct platform_device *pdev)
                         pdata->multi_block[tmp] = 1;
         }
 
+        if (!of_property_read_u32(np, "snps,dma-protection-control", &tmp)) {
+                if (tmp > CHAN_PROTCTL_MASK)
+                        return NULL;
+                pdata->protctl = tmp;
+        }
+
         return pdata;
 }
 #else
diff --git a/drivers/dma/dw/regs.h b/drivers/dma/dw/regs.h
index 09e7dfdbb790..646c9c960c07 100644
--- a/drivers/dma/dw/regs.h
+++ b/drivers/dma/dw/regs.h
@@ -200,6 +200,10 @@ enum dw_dma_msize {
 #define DWC_CFGH_FCMODE         (1 << 0)
 #define DWC_CFGH_FIFO_MODE      (1 << 1)
 #define DWC_CFGH_PROTCTL(x)     ((x) << 2)
+#define DWC_CFGH_PROTCTL_DATA   (0 << 2)        /* data access - always set */
+#define DWC_CFGH_PROTCTL_PRIV   (1 << 2)        /* privileged -> AHB HPROT[1] */
+#define DWC_CFGH_PROTCTL_BUFFER (2 << 2)        /* bufferable -> AHB HPROT[2] */
+#define DWC_CFGH_PROTCTL_CACHE  (4 << 2)        /* cacheable  -> AHB HPROT[3] */
 #define DWC_CFGH_DS_UPD_EN      (1 << 5)
 #define DWC_CFGH_SS_UPD_EN      (1 << 6)
 #define DWC_CFGH_SRC_PER(x)     ((x) << 7)
diff --git a/include/dt-bindings/dma/dw-dmac.h b/include/dt-bindings/dma/dw-dmac.h
new file mode 100644
index 000000000000..d1ca705c95b3
--- /dev/null
+++ b/include/dt-bindings/dma/dw-dmac.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+
+#ifndef __DT_BINDINGS_DMA_DW_DMAC_H__
+#define __DT_BINDINGS_DMA_DW_DMAC_H__
+
+/*
+ * Protection Control bits provide protection against illegal transactions.
+ * The protection bits[0:2] are one-to-one mapped to AHB HPROT[3:1] signals.
+ */
+#define DW_DMAC_HPROT1_PRIVILEGED_MODE  (1 << 0)        /* Privileged Mode */
+#define DW_DMAC_HPROT2_BUFFERABLE       (1 << 1)        /* DMA is bufferable */
+#define DW_DMAC_HPROT3_CACHEABLE        (1 << 2)        /* DMA is cacheable */
+
+#endif /* __DT_BINDINGS_DMA_DW_DMAC_H__ */
diff --git a/include/linux/platform_data/dma-dw.h b/include/linux/platform_data/dma-dw.h
index 896cb71a382c..1a1d58ebffbf 100644
--- a/include/linux/platform_data/dma-dw.h
+++ b/include/linux/platform_data/dma-dw.h
@@ -49,6 +49,7 @@ struct dw_dma_slave {
  * @data_width: Maximum data width supported by hardware per AHB master
  *              (in bytes, power of 2)
  * @multi_block: Multi block transfers supported by hardware per channel.
+ * @protctl: Protection control signals setting per channel.
  */
 struct dw_dma_platform_data {
         unsigned int    nr_channels;
@@ -65,6 +66,11 @@ struct dw_dma_platform_data {
         unsigned char   nr_masters;
         unsigned char   data_width[DW_DMA_MAX_NR_MASTERS];
         unsigned char   multi_block[DW_DMA_MAX_NR_CHANNELS];
+#define CHAN_PROTCTL_PRIVILEGED         BIT(0)
+#define CHAN_PROTCTL_BUFFERABLE         BIT(1)
+#define CHAN_PROTCTL_CACHEABLE          BIT(2)
+#define CHAN_PROTCTL_MASK               GENMASK(2, 0)
+        unsigned char   protctl;
 };
 
 #endif /* _PLATFORM_DATA_DMA_DW_H */