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-rw-r--r--arch/m68k/Kconfig.cpu8
-rw-r--r--arch/m68k/Makefile1
-rw-r--r--arch/m68k/include/asm/gpio.h10
-rw-r--r--arch/m68k/include/asm/m5441xsim.h270
-rw-r--r--arch/m68k/include/asm/m54xxacr.h4
-rw-r--r--arch/m68k/include/asm/mcfclk.h43
-rw-r--r--arch/m68k/include/asm/mcfgpio.h30
-rw-r--r--arch/m68k/include/asm/mcfsim.h2
-rw-r--r--arch/m68k/include/asm/mcftimer.h2
-rw-r--r--arch/m68k/platform/coldfire/Makefile1
-rw-r--r--arch/m68k/platform/coldfire/clk.c105
-rw-r--r--arch/m68k/platform/coldfire/device.c57
-rw-r--r--arch/m68k/platform/coldfire/intc-simr.c26
-rw-r--r--arch/m68k/platform/coldfire/m5441x.c224
-rw-r--r--arch/m68k/platform/coldfire/timers.c2
15 files changed, 761 insertions, 24 deletions
diff --git a/arch/m68k/Kconfig.cpu b/arch/m68k/Kconfig.cpu
index 8d9afb09f569..43a9f8f1b8eb 100644
--- a/arch/m68k/Kconfig.cpu
+++ b/arch/m68k/Kconfig.cpu
@@ -261,6 +261,14 @@ config M548x
261 help 261 help
262 Freescale ColdFire 5480/5481/5482/5483/5484/5485 processor support. 262 Freescale ColdFire 5480/5481/5482/5483/5484/5485 processor support.
263 263
264config M5441x
265 bool "MCF5441x"
266 depends on !MMU
267 select GENERIC_CLOCKEVENTS
268 select HAVE_CACHE_CB
269 help
270 Freescale Coldfire 54410/54415/54416/54417/54418 processor support.
271
264endif # COLDFIRE 272endif # COLDFIRE
265 273
266 274
diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile
index 8daf9697e5e2..7636751f2f87 100644
--- a/arch/m68k/Makefile
+++ b/arch/m68k/Makefile
@@ -41,6 +41,7 @@ cpuflags-$(CONFIG_M68030) :=
41cpuflags-$(CONFIG_M68020) := 41cpuflags-$(CONFIG_M68020) :=
42cpuflags-$(CONFIG_M68360) := -m68332 42cpuflags-$(CONFIG_M68360) := -m68332
43cpuflags-$(CONFIG_M68000) := -m68000 43cpuflags-$(CONFIG_M68000) := -m68000
44cpuflags-$(CONFIG_M5441x) := $(call cc-option,-mcpu=54455,-mcfv4e)
44cpuflags-$(CONFIG_M54xx) := $(call cc-option,-mcpu=5475,-m5200) 45cpuflags-$(CONFIG_M54xx) := $(call cc-option,-mcpu=5475,-m5200)
45cpuflags-$(CONFIG_M5407) := $(call cc-option,-mcpu=5407,-m5200) 46cpuflags-$(CONFIG_M5407) := $(call cc-option,-mcpu=5407,-m5200)
46cpuflags-$(CONFIG_M532x) := $(call cc-option,-mcpu=532x,-m5307) 47cpuflags-$(CONFIG_M532x) := $(call cc-option,-mcpu=532x,-m5307)
diff --git a/arch/m68k/include/asm/gpio.h b/arch/m68k/include/asm/gpio.h
index 530862207ecf..4395ffc51fdb 100644
--- a/arch/m68k/include/asm/gpio.h
+++ b/arch/m68k/include/asm/gpio.h
@@ -64,8 +64,14 @@ static inline void gpio_set_value(unsigned gpio, int value)
64 64
65static inline int gpio_to_irq(unsigned gpio) 65static inline int gpio_to_irq(unsigned gpio)
66{ 66{
67 return (gpio < MCFGPIO_IRQ_MAX) ? gpio + MCFGPIO_IRQ_VECBASE 67#if defined(MCFGPIO_IRQ_MIN)
68 : __gpio_to_irq(gpio); 68 if ((gpio >= MCFGPIO_IRQ_MIN) && (gpio < MCFGPIO_IRQ_MAX))
69#else
70 if (gpio < MCFGPIO_IRQ_MAX)
71#endif
72 return gpio + MCFGPIO_IRQ_VECBASE;
73 else
74 return __gpio_to_irq(gpio);
69} 75}
70 76
71static inline int irq_to_gpio(unsigned irq) 77static inline int irq_to_gpio(unsigned irq)
diff --git a/arch/m68k/include/asm/m5441xsim.h b/arch/m68k/include/asm/m5441xsim.h
new file mode 100644
index 000000000000..86315a96604d
--- /dev/null
+++ b/arch/m68k/include/asm/m5441xsim.h
@@ -0,0 +1,270 @@
1/*
2 * m5441xsim.h -- Coldfire 5441x register definitions
3 *
4 * (C) Copyright 2012, Steven King <sfking@fdwdc.com>
5*/
6
7#ifndef m5441xsim_h
8#define m5441xsim_h
9
10#define CPU_NAME "COLDFIRE(m5441x)"
11#define CPU_INSTR_PER_JIFFY 2
12#define MCF_BUSCLK (MCF_CLK / 2)
13
14#include <asm/m54xxacr.h>
15
16/*
17 * Reset Controller Module.
18 */
19
20#define MCF_RCR 0xec090000
21#define MCF_RSR 0xec090001
22
23#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
24#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
25
26/*
27 * Interrupt Controller Modules.
28 */
29/* the 5441x have 3 interrupt controllers, each control 64 interrupts */
30#define MCFINT_VECBASE 64
31#define MCFINT0_VECBASE MCFINT_VECBASE
32#define MCFINT1_VECBASE (MCFINT0_VECBASE + 64)
33#define MCFINT2_VECBASE (MCFINT1_VECBASE + 64)
34
35/* interrupt controller 0 */
36#define MCFINTC0_SIMR 0xfc04801c
37#define MCFINTC0_CIMR 0xfc04801d
38#define MCFINTC0_ICR0 0xfc048040
39/* interrupt controller 1 */
40#define MCFINTC1_SIMR 0xfc04c01c
41#define MCFINTC1_CIMR 0xfc04c01d
42#define MCFINTC1_ICR0 0xfc04c040
43/* interrupt controller 2 */
44#define MCFINTC2_SIMR 0xfc05001c
45#define MCFINTC2_CIMR 0xfc05001d
46#define MCFINTC2_ICR0 0xfc050040
47
48/* on interrupt controller 0 */
49#define MCFINT0_EPORT0 1
50#define MCFINT0_UART0 26
51#define MCFINT0_UART1 27
52#define MCFINT0_UART2 28
53#define MCFINT0_UART3 29
54#define MCFINT0_I2C0 30
55#define MCFINT0_DSPI0 31
56
57#define MCFINT0_TIMER0 32
58#define MCFINT0_TIMER1 33
59#define MCFINT0_TIMER2 34
60#define MCFINT0_TIMER3 35
61
62#define MCFINT0_FECRX0 36
63#define MCFINT0_FECTX0 40
64#define MCFINT0_FECENTC0 42
65
66#define MCFINT0_FECRX1 49
67#define MCFINT0_FECTX1 53
68#define MCFINT0_FECENTC1 55
69
70/* on interrupt controller 1 */
71#define MCFINT1_UART4 48
72#define MCFINT1_UART5 49
73#define MCFINT1_UART6 50
74#define MCFINT1_UART7 51
75#define MCFINT1_UART8 52
76#define MCFINT1_UART9 53
77#define MCFINT1_DSPI1 54
78#define MCFINT1_DSPI2 55
79#define MCFINT1_DSPI3 56
80#define MCFINT1_I2C1 57
81#define MCFINT1_I2C2 58
82#define MCFINT1_I2C3 59
83#define MCFINT1_I2C4 60
84#define MCFINT1_I2C5 61
85
86/* on interrupt controller 2 */
87#define MCFINT2_PIT0 13
88#define MCFINT2_PIT1 14
89#define MCFINT2_PIT2 15
90#define MCFINT2_PIT3 16
91#define MCFINT2_RTC 26
92
93/*
94 * PIT timer module.
95 */
96#define MCFPIT_BASE0 0xFC080000 /* Base address of TIMER0 */
97#define MCFPIT_BASE1 0xFC084000 /* Base address of TIMER1 */
98#define MCFPIT_BASE2 0xFC088000 /* Base address of TIMER2 */
99#define MCFPIT_BASE3 0xFC08C000 /* Base address of TIMER3 */
100
101
102#define MCF_IRQ_PIT1 (MCFINT2_VECBASE + MCFINT2_PIT1)
103
104/*
105 * Power Management
106 */
107#define MCFPM_WCR 0xfc040013
108#define MCFPM_PPMSR0 0xfc04002c
109#define MCFPM_PPMCR0 0xfc04002d
110#define MCFPM_PPMSR1 0xfc04002e
111#define MCFPM_PPMCR1 0xfc04002f
112#define MCFPM_PPMHR0 0xfc040030
113#define MCFPM_PPMLR0 0xfc040034
114#define MCFPM_PPMHR1 0xfc040038
115#define MCFPM_PPMLR1 0xfc04003c
116#define MCFPM_LPCR 0xec090007
117/*
118 * UART module.
119 */
120#define MCFUART_BASE0 0xfc060000 /* Base address of UART0 */
121#define MCFUART_BASE1 0xfc064000 /* Base address of UART1 */
122#define MCFUART_BASE2 0xfc068000 /* Base address of UART2 */
123#define MCFUART_BASE3 0xfc06c000 /* Base address of UART3 */
124#define MCFUART_BASE4 0xec060000 /* Base address of UART4 */
125#define MCFUART_BASE5 0xec064000 /* Base address of UART5 */
126#define MCFUART_BASE6 0xec068000 /* Base address of UART6 */
127#define MCFUART_BASE7 0xec06c000 /* Base address of UART7 */
128#define MCFUART_BASE8 0xec070000 /* Base address of UART8 */
129#define MCFUART_BASE9 0xec074000 /* Base address of UART9 */
130
131#define MCF_IRQ_UART0 (MCFINT0_VECBASE + MCFINT0_UART0)
132#define MCF_IRQ_UART1 (MCFINT0_VECBASE + MCFINT0_UART1)
133#define MCF_IRQ_UART2 (MCFINT0_VECBASE + MCFINT0_UART2)
134#define MCF_IRQ_UART3 (MCFINT0_VECBASE + MCFINT0_UART3)
135#define MCF_IRQ_UART4 (MCFINT1_VECBASE + MCFINT1_UART4)
136#define MCF_IRQ_UART5 (MCFINT1_VECBASE + MCFINT1_UART5)
137#define MCF_IRQ_UART6 (MCFINT1_VECBASE + MCFINT1_UART6)
138#define MCF_IRQ_UART7 (MCFINT1_VECBASE + MCFINT1_UART7)
139#define MCF_IRQ_UART8 (MCFINT1_VECBASE + MCFINT1_UART8)
140#define MCF_IRQ_UART9 (MCFINT1_VECBASE + MCFINT1_UART9)
141/*
142 * FEC modules.
143 */
144#define MCFFEC_BASE0 0xfc0d4000
145#define MCFFEC_SIZE0 0x800
146#define MCF_IRQ_FECRX0 (MCFINT0_VECBASE + MCFINT0_FECRX0)
147#define MCF_IRQ_FECTX0 (MCFINT0_VECBASE + MCFINT0_FECTX0)
148#define MCF_IRQ_FECENTC0 (MCFINT0_VECBASE + MCFINT0_FECENTC0)
149
150#define MCFFEC_BASE1 0xfc0d8000
151#define MCFFEC_SIZE1 0x800
152#define MCF_IRQ_FECRX1 (MCFINT0_VECBASE + MCFINT0_FECRX1)
153#define MCF_IRQ_FECTX1 (MCFINT0_VECBASE + MCFINT0_FECTX1)
154#define MCF_IRQ_FECENTC1 (MCFINT0_VECBASE + MCFINT0_FECENTC1)
155/*
156 * I2C modules.
157 */
158#define MCFI2C_BASE0 0xfc058000
159#define MCFI2C_SIZE0 0x20
160#define MCFI2C_BASE1 0xfc038000
161#define MCFI2C_SIZE1 0x20
162#define MCFI2C_BASE2 0xec010000
163#define MCFI2C_SIZE2 0x20
164#define MCFI2C_BASE3 0xec014000
165#define MCFI2C_SIZE3 0x20
166#define MCFI2C_BASE4 0xec018000
167#define MCFI2C_SIZE4 0x20
168#define MCFI2C_BASE5 0xec01c000
169#define MCFI2C_SIZE5 0x20
170
171#define MCF_IRQ_I2C0 (MCFINT0_VECBASE + MCFINT0_I2C0)
172#define MCF_IRQ_I2C1 (MCFINT1_VECBASE + MCFINT1_I2C1)
173#define MCF_IRQ_I2C2 (MCFINT1_VECBASE + MCFINT1_I2C2)
174#define MCF_IRQ_I2C3 (MCFINT1_VECBASE + MCFINT1_I2C3)
175#define MCF_IRQ_I2C4 (MCFINT1_VECBASE + MCFINT1_I2C4)
176#define MCF_IRQ_I2C5 (MCFINT1_VECBASE + MCFINT1_I2C5)
177/*
178 * EPORT Module.
179 */
180#define MCFEPORT_EPPAR 0xfc090000
181#define MCFEPORT_EPIER 0xfc090003
182#define MCFEPORT_EPFR 0xfc090006
183
184/*
185 * GPIO Module.
186 */
187#define MCFGPIO_PODR_A 0xec094000
188#define MCFGPIO_PODR_B 0xec094001
189#define MCFGPIO_PODR_C 0xec094002
190#define MCFGPIO_PODR_D 0xec094003
191#define MCFGPIO_PODR_E 0xec094004
192#define MCFGPIO_PODR_F 0xec094005
193#define MCFGPIO_PODR_G 0xec094006
194#define MCFGPIO_PODR_H 0xec094007
195#define MCFGPIO_PODR_I 0xec094008
196#define MCFGPIO_PODR_J 0xec094009
197#define MCFGPIO_PODR_K 0xec09400a
198
199#define MCFGPIO_PDDR_A 0xec09400c
200#define MCFGPIO_PDDR_B 0xec09400d
201#define MCFGPIO_PDDR_C 0xec09400e
202#define MCFGPIO_PDDR_D 0xec09400f
203#define MCFGPIO_PDDR_E 0xec094010
204#define MCFGPIO_PDDR_F 0xec094011
205#define MCFGPIO_PDDR_G 0xec094012
206#define MCFGPIO_PDDR_H 0xec094013
207#define MCFGPIO_PDDR_I 0xec094014
208#define MCFGPIO_PDDR_J 0xec094015
209#define MCFGPIO_PDDR_K 0xec094016
210
211#define MCFGPIO_PPDSDR_A 0xec094018
212#define MCFGPIO_PPDSDR_B 0xec094019
213#define MCFGPIO_PPDSDR_C 0xec09401a
214#define MCFGPIO_PPDSDR_D 0xec09401b
215#define MCFGPIO_PPDSDR_E 0xec09401c
216#define MCFGPIO_PPDSDR_F 0xec09401d
217#define MCFGPIO_PPDSDR_G 0xec09401e
218#define MCFGPIO_PPDSDR_H 0xec09401f
219#define MCFGPIO_PPDSDR_I 0xec094020
220#define MCFGPIO_PPDSDR_J 0xec094021
221#define MCFGPIO_PPDSDR_K 0xec094022
222
223#define MCFGPIO_PCLRR_A 0xec094024
224#define MCFGPIO_PCLRR_B 0xec094025
225#define MCFGPIO_PCLRR_C 0xec094026
226#define MCFGPIO_PCLRR_D 0xec094027
227#define MCFGPIO_PCLRR_E 0xec094028
228#define MCFGPIO_PCLRR_F 0xec094029
229#define MCFGPIO_PCLRR_G 0xec09402a
230#define MCFGPIO_PCLRR_H 0xec09402b
231#define MCFGPIO_PCLRR_I 0xec09402c
232#define MCFGPIO_PCLRR_J 0xec09402d
233#define MCFGPIO_PCLRR_K 0xec09402e
234
235#define MCFGPIO_PAR_FBCTL 0xec094048
236#define MCFGPIO_PAR_BE 0xec094049
237#define MCFGPIO_PAR_CS 0xec09404a
238#define MCFGPIO_PAR_CANI2C 0xec09404b
239#define MCFGPIO_PAR_IRQ0H 0xec09404c
240#define MCFGPIO_PAR_IRQ0L 0xec09404d
241#define MCFGPIO_PAR_DSPIOWH 0xec09404e
242#define MCFGPIO_PAR_DSPIOWL 0xec09404f
243#define MCFGPIO_PAR_TIMER 0xec094050
244#define MCFGPIO_PAR_UART2 0xec094051
245#define MCFGPIO_PAR_UART1 0xec094052
246#define MCFGPIO_PAR_UART0 0xec094053
247#define MCFGPIO_PAR_SDHCH 0xec094054
248#define MCFGPIO_PAR_SDHCL 0xec094055
249#define MCFGPIO_PAR_SIMP0H 0xec094056
250#define MCFGPIO_PAR_SIMP0L 0xec094057
251#define MCFGPIO_PAR_SSI0H 0xec094058
252#define MCFGPIO_PAR_SSI0L 0xec094059
253#define MCFGPIO_PAR_DEBUGH1 0xec09405a
254#define MCFGPIO_PAR_DEBUGH0 0xec09405b
255#define MCFGPIO_PAR_DEBUGl 0xec09405c
256#define MCFGPIO_PAR_FEC 0xec09405e
257
258/* generalization for generic gpio support */
259#define MCFGPIO_PODR MCFGPIO_PODR_A
260#define MCFGPIO_PDDR MCFGPIO_PDDR_A
261#define MCFGPIO_PPDR MCFGPIO_PPDSDR_A
262#define MCFGPIO_SETR MCFGPIO_PPDSDR_A
263#define MCFGPIO_CLRR MCFGPIO_PCLRR_A
264
265#define MCFGPIO_IRQ_MIN 17
266#define MCFGPIO_IRQ_MAX 24
267#define MCFGPIO_IRQ_VECBASE (MCFINT_VECBASE - MCFGPIO_IRQ_MIN)
268#define MCFGPIO_PIN_MAX 87
269
270#endif /* m5441xsim_h */
diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h
index 47906aafbf67..192bbfeabf70 100644
--- a/arch/m68k/include/asm/m54xxacr.h
+++ b/arch/m68k/include/asm/m54xxacr.h
@@ -55,6 +55,10 @@
55#define ICACHE_SIZE 0x8000 /* instruction - 32k */ 55#define ICACHE_SIZE 0x8000 /* instruction - 32k */
56#define DCACHE_SIZE 0x8000 /* data - 32k */ 56#define DCACHE_SIZE 0x8000 /* data - 32k */
57 57
58#elif defined(CONFIG_M5441x)
59
60#define ICACHE_SIZE 0x2000 /* instruction - 8k */
61#define DCACHE_SIZE 0x2000 /* data - 8k */
58#endif 62#endif
59 63
60#define CACHE_LINE_SIZE 0x0010 /* 16 bytes */ 64#define CACHE_LINE_SIZE 0x0010 /* 16 bytes */
diff --git a/arch/m68k/include/asm/mcfclk.h b/arch/m68k/include/asm/mcfclk.h
new file mode 100644
index 000000000000..b676a02bb392
--- /dev/null
+++ b/arch/m68k/include/asm/mcfclk.h
@@ -0,0 +1,43 @@
1/*
2 * mcfclk.h -- coldfire specific clock structure
3 */
4
5
6#ifndef mcfclk_h
7#define mcfclk_h
8
9struct clk;
10
11#ifdef MCFPM_PPMCR0
12struct clk_ops {
13 void (*enable)(struct clk *);
14 void (*disable)(struct clk *);
15};
16
17struct clk {
18 const char *name;
19 struct clk_ops *clk_ops;
20 unsigned long rate;
21 unsigned long enabled;
22 u8 slot;
23};
24
25extern struct clk *mcf_clks[];
26extern struct clk_ops clk_ops0;
27#ifdef MCFPM_PPMCR1
28extern struct clk_ops clk_ops1;
29#endif /* MCFPM_PPMCR1 */
30
31#define DEFINE_CLK(clk_bank, clk_name, clk_slot, clk_rate) \
32static struct clk __clk_##clk_bank##_##clk_slot = { \
33 .name = clk_name, \
34 .clk_ops = &clk_ops##clk_bank, \
35 .rate = clk_rate, \
36 .slot = clk_slot, \
37}
38
39void __clk_init_enabled(struct clk *);
40void __clk_init_disabled(struct clk *);
41#endif /* MCFPM_PPMCR0 */
42
43#endif /* mcfclk_h */
diff --git a/arch/m68k/include/asm/mcfgpio.h b/arch/m68k/include/asm/mcfgpio.h
index b2471a5f02eb..fa1059f50dfc 100644
--- a/arch/m68k/include/asm/mcfgpio.h
+++ b/arch/m68k/include/asm/mcfgpio.h
@@ -104,7 +104,8 @@ static inline void gpio_free(unsigned gpio)
104#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ 104#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
105 defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ 105 defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
106 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 106 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
107 defined(CONFIG_M532x) || defined(CONFIG_M54xx) 107 defined(CONFIG_M532x) || defined(CONFIG_M54xx) || \
108 defined(CONFIG_M5441x)
108 109
109/* These parts have GPIO organized by 8 bit ports */ 110/* These parts have GPIO organized by 8 bit ports */
110 111
@@ -137,7 +138,8 @@ static inline void gpio_free(unsigned gpio)
137#define mcfgpio_port(gpio) ((gpio) / MCFGPIO_PORTSIZE) 138#define mcfgpio_port(gpio) ((gpio) / MCFGPIO_PORTSIZE)
138 139
139#if defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ 140#if defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
140 defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x) 141 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
142 defined(CONFIG_M532x) || defined(CONFIG_M5441x)
141/* 143/*
142 * These parts have an 'Edge' Port module (external interrupt/GPIO) which uses 144 * These parts have an 'Edge' Port module (external interrupt/GPIO) which uses
143 * read-modify-write to change an output and a GPIO module which has separate 145 * read-modify-write to change an output and a GPIO module which has separate
@@ -149,6 +151,9 @@ static inline void gpio_free(unsigned gpio)
149 * read-modify-write as well as those controlled by the EPORT and GPIO modules. 151 * read-modify-write as well as those controlled by the EPORT and GPIO modules.
150 */ 152 */
151#define MCFGPIO_SCR_START 40 153#define MCFGPIO_SCR_START 40
154#elif defined(CONFIGM5441x)
155/* The m5441x EPORT doesn't have its own GPIO port, uses PORT C */
156#define MCFGPIO_SCR_START 0
152#else 157#else
153#define MCFGPIO_SCR_START 8 158#define MCFGPIO_SCR_START 8
154#endif 159#endif
@@ -189,7 +194,9 @@ static inline u32 __mcfgpio_ppdr(unsigned gpio)
189 else 194 else
190 return MCFSIM2_GPIO1READ; 195 return MCFSIM2_GPIO1READ;
191#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ 196#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
192 defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x) 197 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
198 defined(CONFIG_M532x) || defined(CONFIG_M5441x)
199#if !defined(CONFIG_M5441x)
193 if (gpio < 8) 200 if (gpio < 8)
194 return MCFEPORT_EPPDR; 201 return MCFEPORT_EPPDR;
195#if defined(CONFIG_M528x) 202#if defined(CONFIG_M528x)
@@ -201,8 +208,9 @@ static inline u32 __mcfgpio_ppdr(unsigned gpio)
201 return MCFQADC_PORTQA; 208 return MCFQADC_PORTQA;
202 else if (gpio < 40) 209 else if (gpio < 40)
203 return MCFQADC_PORTQB; 210 return MCFQADC_PORTQB;
204#endif 211#endif /* defined(CONFIG_M528x) */
205 else 212 else
213#endif /* !defined(CONFIG_M5441x) */
206 return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START); 214 return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
207#else 215#else
208 return 0; 216 return 0;
@@ -228,7 +236,9 @@ static inline u32 __mcfgpio_podr(unsigned gpio)
228 else 236 else
229 return MCFSIM2_GPIO1WRITE; 237 return MCFSIM2_GPIO1WRITE;
230#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ 238#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
231 defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x) 239 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
240 defined(CONFIG_M532x) || defined(CONFIG_M5441x)
241#if !defined(CONFIG_M5441x)
232 if (gpio < 8) 242 if (gpio < 8)
233 return MCFEPORT_EPDR; 243 return MCFEPORT_EPDR;
234#if defined(CONFIG_M528x) 244#if defined(CONFIG_M528x)
@@ -240,8 +250,9 @@ static inline u32 __mcfgpio_podr(unsigned gpio)
240 return MCFQADC_PORTQA; 250 return MCFQADC_PORTQA;
241 else if (gpio < 40) 251 else if (gpio < 40)
242 return MCFQADC_PORTQB; 252 return MCFQADC_PORTQB;
243#endif 253#endif /* defined(CONFIG_M528x) */
244 else 254 else
255#endif /* !defined(CONFIG_M5441x) */
245 return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START); 256 return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
246#else 257#else
247 return 0; 258 return 0;
@@ -267,7 +278,9 @@ static inline u32 __mcfgpio_pddr(unsigned gpio)
267 else 278 else
268 return MCFSIM2_GPIO1ENABLE; 279 return MCFSIM2_GPIO1ENABLE;
269#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ 280#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
270 defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x) 281 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
282 defined(CONFIG_M532x) || defined(CONFIG_M5441x)
283#if !defined(CONFIG_M5441x)
271 if (gpio < 8) 284 if (gpio < 8)
272 return MCFEPORT_EPDDR; 285 return MCFEPORT_EPDDR;
273#if defined(CONFIG_M528x) 286#if defined(CONFIG_M528x)
@@ -279,8 +292,9 @@ static inline u32 __mcfgpio_pddr(unsigned gpio)
279 return MCFQADC_DDRQA; 292 return MCFQADC_DDRQA;
280 else if (gpio < 40) 293 else if (gpio < 40)
281 return MCFQADC_DDRQB; 294 return MCFQADC_DDRQB;
282#endif 295#endif /* defined(CONFIG_M528x) */
283 else 296 else
297#endif /* !defined(CONFIG_M5441x) */
284 return MCFGPIO_PDDR + mcfgpio_port(gpio - MCFGPIO_SCR_START); 298 return MCFGPIO_PDDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
285#else 299#else
286 return 0; 300 return 0;
diff --git a/arch/m68k/include/asm/mcfsim.h b/arch/m68k/include/asm/mcfsim.h
index 6871f62b11b1..7a83e619e73b 100644
--- a/arch/m68k/include/asm/mcfsim.h
+++ b/arch/m68k/include/asm/mcfsim.h
@@ -46,6 +46,8 @@
46#include <asm/mcfintc.h> 46#include <asm/mcfintc.h>
47#elif defined(CONFIG_M54xx) 47#elif defined(CONFIG_M54xx)
48#include <asm/m54xxsim.h> 48#include <asm/m54xxsim.h>
49#elif defined(CONFIG_M5441x)
50#include <asm/m5441xsim.h>
49#endif 51#endif
50 52
51/****************************************************************************/ 53/****************************************************************************/
diff --git a/arch/m68k/include/asm/mcftimer.h b/arch/m68k/include/asm/mcftimer.h
index 351c27237874..da2fa43c2e45 100644
--- a/arch/m68k/include/asm/mcftimer.h
+++ b/arch/m68k/include/asm/mcftimer.h
@@ -19,7 +19,7 @@
19#define MCFTIMER_TRR 0x04 /* Timer Reference (r/w) */ 19#define MCFTIMER_TRR 0x04 /* Timer Reference (r/w) */
20#define MCFTIMER_TCR 0x08 /* Timer Capture reg (r/w) */ 20#define MCFTIMER_TCR 0x08 /* Timer Capture reg (r/w) */
21#define MCFTIMER_TCN 0x0C /* Timer Counter reg (r/w) */ 21#define MCFTIMER_TCN 0x0C /* Timer Counter reg (r/w) */
22#if defined(CONFIG_M532x) 22#if defined(CONFIG_M532x) || defined(CONFIG_M5441x)
23#define MCFTIMER_TER 0x03 /* Timer Event reg (r/w) */ 23#define MCFTIMER_TER 0x03 /* Timer Event reg (r/w) */
24#else 24#else
25#define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */ 25#define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */
diff --git a/arch/m68k/platform/coldfire/Makefile b/arch/m68k/platform/coldfire/Makefile
index a7329b4fbef8..b3f8bfda52e2 100644
--- a/arch/m68k/platform/coldfire/Makefile
+++ b/arch/m68k/platform/coldfire/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_M5307) += m5307.o timers.o intc.o reset.o
28obj-$(CONFIG_M532x) += m532x.o timers.o intc-simr.o reset.o 28obj-$(CONFIG_M532x) += m532x.o timers.o intc-simr.o reset.o
29obj-$(CONFIG_M5407) += m5407.o timers.o intc.o reset.o 29obj-$(CONFIG_M5407) += m5407.o timers.o intc.o reset.o
30obj-$(CONFIG_M54xx) += m54xx.o sltimers.o intc-2.o 30obj-$(CONFIG_M54xx) += m54xx.o sltimers.o intc-2.o
31obj-$(CONFIG_M5441x) += m5441x.o pit.o intc-simr.o reset.o
31 32
32obj-$(CONFIG_NETtel) += nettel.o 33obj-$(CONFIG_NETtel) += nettel.o
33obj-$(CONFIG_CLEOPATRA) += nettel.o 34obj-$(CONFIG_CLEOPATRA) += nettel.o
diff --git a/arch/m68k/platform/coldfire/clk.c b/arch/m68k/platform/coldfire/clk.c
index 44da406897e5..c06c0f4a0ffc 100644
--- a/arch/m68k/platform/coldfire/clk.c
+++ b/arch/m68k/platform/coldfire/clk.c
@@ -10,11 +10,17 @@
10 10
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/module.h> 12#include <linux/module.h>
13#include <linux/platform_device.h>
14#include <linux/mutex.h>
13#include <linux/clk.h> 15#include <linux/clk.h>
16#include <linux/io.h>
17#include <linux/err.h>
14#include <asm/coldfire.h> 18#include <asm/coldfire.h>
19#include <asm/mcfsim.h>
20#include <asm/mcfclk.h>
15 21
16/***************************************************************************/ 22/***************************************************************************/
17 23#ifndef MCFPM_PPMCR0
18struct clk *clk_get(struct device *dev, const char *id) 24struct clk *clk_get(struct device *dev, const char *id)
19{ 25{
20 return NULL; 26 return NULL;
@@ -49,4 +55,101 @@ struct clk *devm_clk_get(struct device *dev, const char *id)
49} 55}
50EXPORT_SYMBOL(devm_clk_get); 56EXPORT_SYMBOL(devm_clk_get);
51 57
58#else
59static DEFINE_SPINLOCK(clk_lock);
60
61struct clk *clk_get(struct device *dev, const char *id)
62{
63 const char *clk_name = dev ? dev_name(dev) : id ? id : NULL;
64 struct clk *clk;
65 unsigned i;
66
67 for (i = 0; (clk = mcf_clks[i]) != NULL; ++i)
68 if (!strcmp(clk->name, clk_name))
69 return clk;
70 pr_warn("clk_get: didn't find clock %s\n", clk_name);
71 return ERR_PTR(-ENOENT);
72}
73EXPORT_SYMBOL(clk_get);
74
75int clk_enable(struct clk *clk)
76{
77 unsigned long flags;
78 spin_lock_irqsave(&clk_lock, flags);
79 if ((clk->enabled++ == 0) && clk->clk_ops)
80 clk->clk_ops->enable(clk);
81 spin_unlock_irqrestore(&clk_lock, flags);
82
83 return 0;
84}
85EXPORT_SYMBOL(clk_enable);
86
87void clk_disable(struct clk *clk)
88{
89 unsigned long flags;
90 spin_lock_irqsave(&clk_lock, flags);
91 if ((--clk->enabled == 0) && clk->clk_ops)
92 clk->clk_ops->disable(clk);
93 spin_unlock_irqrestore(&clk_lock, flags);
94}
95EXPORT_SYMBOL(clk_disable);
96
97void clk_put(struct clk *clk)
98{
99 if (clk->enabled != 0)
100 pr_warn("clk_put %s still enabled\n", clk->name);
101}
102EXPORT_SYMBOL(clk_put);
103
104unsigned long clk_get_rate(struct clk *clk)
105{
106 return clk->rate;
107}
108EXPORT_SYMBOL(clk_get_rate);
109
52/***************************************************************************/ 110/***************************************************************************/
111
112void __clk_init_enabled(struct clk *clk)
113{
114 clk->enabled = 1;
115 clk->clk_ops->enable(clk);
116}
117
118void __clk_init_disabled(struct clk *clk)
119{
120 clk->enabled = 0;
121 clk->clk_ops->disable(clk);
122}
123
124static void __clk_enable0(struct clk *clk)
125{
126 __raw_writeb(clk->slot, MCFPM_PPMCR0);
127}
128
129static void __clk_disable0(struct clk *clk)
130{
131 __raw_writeb(clk->slot, MCFPM_PPMSR0);
132}
133
134struct clk_ops clk_ops0 = {
135 .enable = __clk_enable0,
136 .disable = __clk_disable0,
137};
138
139#ifdef MCFPM_PPMCR1
140static void __clk_enable1(struct clk *clk)
141{
142 __raw_writeb(clk->slot, MCFPM_PPMCR1);
143}
144
145static void __clk_disable1(struct clk *clk)
146{
147 __raw_writeb(clk->slot, MCFPM_PPMSR1);
148}
149
150struct clk_ops clk_ops1 = {
151 .enable = __clk_enable1,
152 .disable = __clk_disable1,
153};
154#endif /* MCFPM_PPMCR1 */
155#endif /* MCFPM_PPMCR0 */
diff --git a/arch/m68k/platform/coldfire/device.c b/arch/m68k/platform/coldfire/device.c
index 3aa77ddea89d..81f0fb5e51cf 100644
--- a/arch/m68k/platform/coldfire/device.c
+++ b/arch/m68k/platform/coldfire/device.c
@@ -13,6 +13,7 @@
13#include <linux/io.h> 13#include <linux/io.h>
14#include <linux/spi/spi.h> 14#include <linux/spi/spi.h>
15#include <linux/gpio.h> 15#include <linux/gpio.h>
16#include <linux/fec.h>
16#include <asm/traps.h> 17#include <asm/traps.h>
17#include <asm/coldfire.h> 18#include <asm/coldfire.h>
18#include <asm/mcfsim.h> 19#include <asm/mcfsim.h>
@@ -20,7 +21,7 @@
20#include <asm/mcfqspi.h> 21#include <asm/mcfqspi.h>
21 22
22/* 23/*
23 * All current ColdFire parts contain from 2, 3 or 4 UARTS. 24 * All current ColdFire parts contain from 2, 3, 4 or 10 UARTS.
24 */ 25 */
25static struct mcf_platform_uart mcf_uart_platform_data[] = { 26static struct mcf_platform_uart mcf_uart_platform_data[] = {
26 { 27 {
@@ -43,6 +44,42 @@ static struct mcf_platform_uart mcf_uart_platform_data[] = {
43 .irq = MCF_IRQ_UART3, 44 .irq = MCF_IRQ_UART3,
44 }, 45 },
45#endif 46#endif
47#ifdef MCFUART_BASE4
48 {
49 .mapbase = MCFUART_BASE4,
50 .irq = MCF_IRQ_UART4,
51 },
52#endif
53#ifdef MCFUART_BASE5
54 {
55 .mapbase = MCFUART_BASE5,
56 .irq = MCF_IRQ_UART5,
57 },
58#endif
59#ifdef MCFUART_BASE6
60 {
61 .mapbase = MCFUART_BASE6,
62 .irq = MCF_IRQ_UART6,
63 },
64#endif
65#ifdef MCFUART_BASE7
66 {
67 .mapbase = MCFUART_BASE7,
68 .irq = MCF_IRQ_UART7,
69 },
70#endif
71#ifdef MCFUART_BASE8
72 {
73 .mapbase = MCFUART_BASE8,
74 .irq = MCF_IRQ_UART8,
75 },
76#endif
77#ifdef MCFUART_BASE9
78 {
79 .mapbase = MCFUART_BASE9,
80 .irq = MCF_IRQ_UART9,
81 },
82#endif
46 { }, 83 { },
47}; 84};
48 85
@@ -53,6 +90,18 @@ static struct platform_device mcf_uart = {
53}; 90};
54 91
55#ifdef CONFIG_FEC 92#ifdef CONFIG_FEC
93
94#ifdef CONFIG_M5441x
95#define FEC_NAME "enet-fec"
96static struct fec_platform_data fec_pdata = {
97 .phy = PHY_INTERFACE_MODE_RMII,
98};
99#define FEC_PDATA (&fec_pdata)
100#else
101#define FEC_NAME "fec"
102#define FEC_PDATA NULL
103#endif
104
56/* 105/*
57 * Some ColdFire cores contain the Fast Ethernet Controller (FEC) 106 * Some ColdFire cores contain the Fast Ethernet Controller (FEC)
58 * block. It is Freescale's own hardware block. Some ColdFires 107 * block. It is Freescale's own hardware block. Some ColdFires
@@ -82,10 +131,11 @@ static struct resource mcf_fec0_resources[] = {
82}; 131};
83 132
84static struct platform_device mcf_fec0 = { 133static struct platform_device mcf_fec0 = {
85 .name = "fec", 134 .name = FEC_NAME,
86 .id = 0, 135 .id = 0,
87 .num_resources = ARRAY_SIZE(mcf_fec0_resources), 136 .num_resources = ARRAY_SIZE(mcf_fec0_resources),
88 .resource = mcf_fec0_resources, 137 .resource = mcf_fec0_resources,
138 .dev.platform_data = FEC_PDATA,
89}; 139};
90 140
91#ifdef MCFFEC_BASE1 141#ifdef MCFFEC_BASE1
@@ -113,10 +163,11 @@ static struct resource mcf_fec1_resources[] = {
113}; 163};
114 164
115static struct platform_device mcf_fec1 = { 165static struct platform_device mcf_fec1 = {
116 .name = "fec", 166 .name = FEC_NAME,
117 .id = 1, 167 .id = 1,
118 .num_resources = ARRAY_SIZE(mcf_fec1_resources), 168 .num_resources = ARRAY_SIZE(mcf_fec1_resources),
119 .resource = mcf_fec1_resources, 169 .resource = mcf_fec1_resources,
170 .dev.platform_data = FEC_PDATA,
120}; 171};
121#endif /* MCFFEC_BASE1 */ 172#endif /* MCFFEC_BASE1 */
122#endif /* CONFIG_FEC */ 173#endif /* CONFIG_FEC */
diff --git a/arch/m68k/platform/coldfire/intc-simr.c b/arch/m68k/platform/coldfire/intc-simr.c
index 650d52e2927e..7cf2c156f72d 100644
--- a/arch/m68k/platform/coldfire/intc-simr.c
+++ b/arch/m68k/platform/coldfire/intc-simr.c
@@ -59,16 +59,18 @@ static unsigned int inline irq2ebit(unsigned int irq)
59#endif 59#endif
60 60
61/* 61/*
62 * There maybe one or two interrupt control units, each has 64 62 * There maybe one, two or three interrupt control units, each has 64
63 * interrupts. If there is no second unit then MCFINTC1_* defines 63 * interrupts. If there is no second or third unit then MCFINTC1_* or
64 * will be 0 (and code for them optimized away). 64 * MCFINTC2_* defines will be 0 (and code for them optimized away).
65 */ 65 */
66 66
67static void intc_irq_mask(struct irq_data *d) 67static void intc_irq_mask(struct irq_data *d)
68{ 68{
69 unsigned int irq = d->irq - MCFINT_VECBASE; 69 unsigned int irq = d->irq - MCFINT_VECBASE;
70 70
71 if (MCFINTC1_SIMR && (irq > 64)) 71 if (MCFINTC2_SIMR && (irq > 128))
72 __raw_writeb(irq - 128, MCFINTC2_SIMR);
73 else if (MCFINTC1_SIMR && (irq > 64))
72 __raw_writeb(irq - 64, MCFINTC1_SIMR); 74 __raw_writeb(irq - 64, MCFINTC1_SIMR);
73 else 75 else
74 __raw_writeb(irq, MCFINTC0_SIMR); 76 __raw_writeb(irq, MCFINTC0_SIMR);
@@ -78,7 +80,9 @@ static void intc_irq_unmask(struct irq_data *d)
78{ 80{
79 unsigned int irq = d->irq - MCFINT_VECBASE; 81 unsigned int irq = d->irq - MCFINT_VECBASE;
80 82
81 if (MCFINTC1_CIMR && (irq > 64)) 83 if (MCFINTC2_CIMR && (irq > 128))
84 __raw_writeb(irq - 128, MCFINTC2_CIMR);
85 else if (MCFINTC1_CIMR && (irq > 64))
82 __raw_writeb(irq - 64, MCFINTC1_CIMR); 86 __raw_writeb(irq - 64, MCFINTC1_CIMR);
83 else 87 else
84 __raw_writeb(irq, MCFINTC0_CIMR); 88 __raw_writeb(irq, MCFINTC0_CIMR);
@@ -99,9 +103,11 @@ static unsigned int intc_irq_startup(struct irq_data *d)
99 unsigned int ebit = irq2ebit(irq); 103 unsigned int ebit = irq2ebit(irq);
100 u8 v; 104 u8 v;
101 105
106#if defined(MCFEPORT_EPDDR)
102 /* Set EPORT line as input */ 107 /* Set EPORT line as input */
103 v = __raw_readb(MCFEPORT_EPDDR); 108 v = __raw_readb(MCFEPORT_EPDDR);
104 __raw_writeb(v & ~(0x1 << ebit), MCFEPORT_EPDDR); 109 __raw_writeb(v & ~(0x1 << ebit), MCFEPORT_EPDDR);
110#endif
105 111
106 /* Set EPORT line as interrupt source */ 112 /* Set EPORT line as interrupt source */
107 v = __raw_readb(MCFEPORT_EPIER); 113 v = __raw_readb(MCFEPORT_EPIER);
@@ -109,12 +115,13 @@ static unsigned int intc_irq_startup(struct irq_data *d)
109 } 115 }
110 116
111 irq -= MCFINT_VECBASE; 117 irq -= MCFINT_VECBASE;
112 if (MCFINTC1_ICR0 && (irq > 64)) 118 if (MCFINTC2_ICR0 && (irq > 128))
119 __raw_writeb(5, MCFINTC2_ICR0 + irq - 128);
120 else if (MCFINTC1_ICR0 && (irq > 64))
113 __raw_writeb(5, MCFINTC1_ICR0 + irq - 64); 121 __raw_writeb(5, MCFINTC1_ICR0 + irq - 64);
114 else 122 else
115 __raw_writeb(5, MCFINTC0_ICR0 + irq); 123 __raw_writeb(5, MCFINTC0_ICR0 + irq);
116 124
117
118 intc_irq_unmask(d); 125 intc_irq_unmask(d);
119 return 0; 126 return 0;
120} 127}
@@ -175,8 +182,11 @@ void __init init_IRQ(void)
175 __raw_writeb(0xff, MCFINTC0_SIMR); 182 __raw_writeb(0xff, MCFINTC0_SIMR);
176 if (MCFINTC1_SIMR) 183 if (MCFINTC1_SIMR)
177 __raw_writeb(0xff, MCFINTC1_SIMR); 184 __raw_writeb(0xff, MCFINTC1_SIMR);
185 if (MCFINTC2_SIMR)
186 __raw_writeb(0xff, MCFINTC2_SIMR);
178 187
179 eirq = MCFINT_VECBASE + 64 + (MCFINTC1_ICR0 ? 64 : 0); 188 eirq = MCFINT_VECBASE + 64 + (MCFINTC1_ICR0 ? 64 : 0) +
189 (MCFINTC2_ICR0 ? 64 : 0);
180 for (irq = MCFINT_VECBASE; (irq < eirq); irq++) { 190 for (irq = MCFINT_VECBASE; (irq < eirq); irq++) {
181 if ((irq >= EINT1) && (irq <= EINT7)) 191 if ((irq >= EINT1) && (irq <= EINT7))
182 irq_set_chip(irq, &intc_irq_chip_edge_port); 192 irq_set_chip(irq, &intc_irq_chip_edge_port);
diff --git a/arch/m68k/platform/coldfire/m5441x.c b/arch/m68k/platform/coldfire/m5441x.c
new file mode 100644
index 000000000000..3020ceaba629
--- /dev/null
+++ b/arch/m68k/platform/coldfire/m5441x.c
@@ -0,0 +1,224 @@
1/*
2 * m5441x.c -- support for Coldfire m5441x processors
3 *
4 * (C) Copyright Steven King <sfking@fdwdc.com>
5 */
6
7#include <linux/kernel.h>
8#include <linux/param.h>
9#include <linux/init.h>
10#include <linux/io.h>
11#include <linux/clk.h>
12#include <asm/machdep.h>
13#include <asm/coldfire.h>
14#include <asm/mcfsim.h>
15#include <asm/mcfuart.h>
16#include <asm/mcfdma.h>
17#include <asm/mcfclk.h>
18
19DEFINE_CLK(0, "flexbus", 2, MCF_CLK);
20DEFINE_CLK(0, "mcfcan.0", 8, MCF_CLK);
21DEFINE_CLK(0, "mcfcan.1", 9, MCF_CLK);
22DEFINE_CLK(0, "mcfi2c.1", 14, MCF_CLK);
23DEFINE_CLK(0, "mcfdspi.1", 15, MCF_CLK);
24DEFINE_CLK(0, "edma", 17, MCF_CLK);
25DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
26DEFINE_CLK(0, "intc.1", 19, MCF_CLK);
27DEFINE_CLK(0, "intc.2", 20, MCF_CLK);
28DEFINE_CLK(0, "mcfi2c.0", 22, MCF_CLK);
29DEFINE_CLK(0, "mcfdspi.0", 23, MCF_CLK);
30DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
31DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK);
32DEFINE_CLK(0, "mcfuart.2", 26, MCF_BUSCLK);
33DEFINE_CLK(0, "mcfuart.3", 27, MCF_BUSCLK);
34DEFINE_CLK(0, "mcftmr.0", 28, MCF_CLK);
35DEFINE_CLK(0, "mcftmr.1", 29, MCF_CLK);
36DEFINE_CLK(0, "mcftmr.2", 30, MCF_CLK);
37DEFINE_CLK(0, "mcftmr.3", 31, MCF_CLK);
38DEFINE_CLK(0, "mcfpit.0", 32, MCF_CLK);
39DEFINE_CLK(0, "mcfpit.1", 33, MCF_CLK);
40DEFINE_CLK(0, "mcfpit.2", 34, MCF_CLK);
41DEFINE_CLK(0, "mcfpit.3", 35, MCF_CLK);
42DEFINE_CLK(0, "mcfeport.0", 37, MCF_CLK);
43DEFINE_CLK(0, "mcfadc.0", 38, MCF_CLK);
44DEFINE_CLK(0, "mcfdac.0", 39, MCF_CLK);
45DEFINE_CLK(0, "mcfrtc.0", 42, MCF_CLK);
46DEFINE_CLK(0, "mcfsim.0", 43, MCF_CLK);
47DEFINE_CLK(0, "mcfusb-otg.0", 44, MCF_CLK);
48DEFINE_CLK(0, "mcfusb-host.0", 45, MCF_CLK);
49DEFINE_CLK(0, "mcfddr-sram.0", 46, MCF_CLK);
50DEFINE_CLK(0, "mcfssi.0", 47, MCF_CLK);
51DEFINE_CLK(0, "pll.0", 48, MCF_CLK);
52DEFINE_CLK(0, "mcfrng.0", 49, MCF_CLK);
53DEFINE_CLK(0, "mcfssi.1", 50, MCF_CLK);
54DEFINE_CLK(0, "mcfsdhc.0", 51, MCF_CLK);
55DEFINE_CLK(0, "enet-fec.0", 53, MCF_CLK);
56DEFINE_CLK(0, "enet-fec.1", 54, MCF_CLK);
57DEFINE_CLK(0, "switch.0", 55, MCF_CLK);
58DEFINE_CLK(0, "switch.1", 56, MCF_CLK);
59DEFINE_CLK(0, "nand.0", 63, MCF_CLK);
60
61DEFINE_CLK(1, "mcfow.0", 2, MCF_CLK);
62DEFINE_CLK(1, "mcfi2c.2", 4, MCF_CLK);
63DEFINE_CLK(1, "mcfi2c.3", 5, MCF_CLK);
64DEFINE_CLK(1, "mcfi2c.4", 6, MCF_CLK);
65DEFINE_CLK(1, "mcfi2c.5", 7, MCF_CLK);
66DEFINE_CLK(1, "mcfuart.4", 24, MCF_BUSCLK);
67DEFINE_CLK(1, "mcfuart.5", 25, MCF_BUSCLK);
68DEFINE_CLK(1, "mcfuart.6", 26, MCF_BUSCLK);
69DEFINE_CLK(1, "mcfuart.7", 27, MCF_BUSCLK);
70DEFINE_CLK(1, "mcfuart.8", 28, MCF_BUSCLK);
71DEFINE_CLK(1, "mcfuart.9", 29, MCF_BUSCLK);
72DEFINE_CLK(1, "mcfpwm.0", 34, MCF_BUSCLK);
73DEFINE_CLK(1, "sys.0", 36, MCF_BUSCLK);
74DEFINE_CLK(1, "gpio.0", 37, MCF_BUSCLK);
75
76struct clk *mcf_clks[] = {
77 &__clk_0_2,
78 &__clk_0_8,
79 &__clk_0_9,
80 &__clk_0_14,
81 &__clk_0_15,
82 &__clk_0_17,
83 &__clk_0_18,
84 &__clk_0_19,
85 &__clk_0_20,
86 &__clk_0_22,
87 &__clk_0_23,
88 &__clk_0_24,
89 &__clk_0_25,
90 &__clk_0_26,
91 &__clk_0_27,
92 &__clk_0_28,
93 &__clk_0_29,
94 &__clk_0_30,
95 &__clk_0_31,
96 &__clk_0_32,
97 &__clk_0_33,
98 &__clk_0_34,
99 &__clk_0_35,
100 &__clk_0_37,
101 &__clk_0_38,
102 &__clk_0_39,
103 &__clk_0_42,
104 &__clk_0_43,
105 &__clk_0_44,
106 &__clk_0_45,
107 &__clk_0_46,
108 &__clk_0_47,
109 &__clk_0_48,
110 &__clk_0_49,
111 &__clk_0_50,
112 &__clk_0_51,
113 &__clk_0_53,
114 &__clk_0_54,
115 &__clk_0_55,
116 &__clk_0_56,
117 &__clk_0_63,
118
119 &__clk_1_2,
120 &__clk_1_4,
121 &__clk_1_5,
122 &__clk_1_6,
123 &__clk_1_7,
124 &__clk_1_24,
125 &__clk_1_25,
126 &__clk_1_26,
127 &__clk_1_27,
128 &__clk_1_28,
129 &__clk_1_29,
130 &__clk_1_34,
131 &__clk_1_36,
132 &__clk_1_37,
133 NULL,
134};
135
136
137static struct clk * const enable_clks[] __initconst = {
138 /* make sure these clocks are enabled */
139 &__clk_0_18, /* intc0 */
140 &__clk_0_19, /* intc0 */
141 &__clk_0_20, /* intc0 */
142 &__clk_0_24, /* uart0 */
143 &__clk_0_25, /* uart1 */
144 &__clk_0_26, /* uart2 */
145 &__clk_0_27, /* uart3 */
146
147 &__clk_0_33, /* pit.1 */
148 &__clk_0_37, /* eport */
149 &__clk_0_48, /* pll */
150
151 &__clk_1_36, /* CCM/reset module/Power management */
152 &__clk_1_37, /* gpio */
153};
154static struct clk * const disable_clks[] __initconst = {
155 &__clk_0_8, /* can.0 */
156 &__clk_0_9, /* can.1 */
157 &__clk_0_14, /* i2c.1 */
158 &__clk_0_15, /* dspi.1 */
159 &__clk_0_17, /* eDMA */
160 &__clk_0_22, /* i2c.0 */
161 &__clk_0_23, /* dspi.0 */
162 &__clk_0_28, /* tmr.1 */
163 &__clk_0_29, /* tmr.2 */
164 &__clk_0_30, /* tmr.2 */
165 &__clk_0_31, /* tmr.3 */
166 &__clk_0_32, /* pit.0 */
167 &__clk_0_34, /* pit.2 */
168 &__clk_0_35, /* pit.3 */
169 &__clk_0_38, /* adc */
170 &__clk_0_39, /* dac */
171 &__clk_0_44, /* usb otg */
172 &__clk_0_45, /* usb host */
173 &__clk_0_47, /* ssi.0 */
174 &__clk_0_49, /* rng */
175 &__clk_0_50, /* ssi.1 */
176 &__clk_0_51, /* eSDHC */
177 &__clk_0_53, /* enet-fec */
178 &__clk_0_54, /* enet-fec */
179 &__clk_0_55, /* switch.0 */
180 &__clk_0_56, /* switch.1 */
181
182 &__clk_1_2, /* 1-wire */
183 &__clk_1_4, /* i2c.2 */
184 &__clk_1_5, /* i2c.3 */
185 &__clk_1_6, /* i2c.4 */
186 &__clk_1_7, /* i2c.5 */
187 &__clk_1_24, /* uart 4 */
188 &__clk_1_25, /* uart 5 */
189 &__clk_1_26, /* uart 6 */
190 &__clk_1_27, /* uart 7 */
191 &__clk_1_28, /* uart 8 */
192 &__clk_1_29, /* uart 9 */
193};
194
195static void __init m5441x_clk_init(void)
196{
197 unsigned i;
198
199 for (i = 0; i < ARRAY_SIZE(enable_clks); ++i)
200 __clk_init_enabled(enable_clks[i]);
201 /* make sure these clocks are disabled */
202 for (i = 0; i < ARRAY_SIZE(disable_clks); ++i)
203 __clk_init_disabled(disable_clks[i]);
204}
205
206static void __init m5441x_uarts_init(void)
207{
208 __raw_writeb(0x0f, MCFGPIO_PAR_UART0);
209 __raw_writeb(0x00, MCFGPIO_PAR_UART1);
210 __raw_writeb(0x00, MCFGPIO_PAR_UART2);
211}
212
213static void __init m5441x_fec_init(void)
214{
215 __raw_writeb(0x03, MCFGPIO_PAR_FEC);
216}
217
218void __init config_BSP(char *commandp, int size)
219{
220 m5441x_clk_init();
221 mach_sched_init = hw_timer_init;
222 m5441x_uarts_init();
223 m5441x_fec_init();
224}
diff --git a/arch/m68k/platform/coldfire/timers.c b/arch/m68k/platform/coldfire/timers.c
index ed96ce50d79f..0a273e75408c 100644
--- a/arch/m68k/platform/coldfire/timers.c
+++ b/arch/m68k/platform/coldfire/timers.c
@@ -36,7 +36,7 @@
36 */ 36 */
37void coldfire_profile_init(void); 37void coldfire_profile_init(void);
38 38
39#if defined(CONFIG_M532x) 39#if defined(CONFIG_M532x) || defined(CONFIG_M5441x)
40#define __raw_readtrr __raw_readl 40#define __raw_readtrr __raw_readl
41#define __raw_writetrr __raw_writel 41#define __raw_writetrr __raw_writel
42#else 42#else
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-25 05:26:07 -0400