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-rw-r--r--arch/m68k/68360/Makefile12
-rw-r--r--arch/m68k/68360/commproc.c309
-rw-r--r--arch/m68k/68360/config.c169
-rw-r--r--arch/m68k/68360/entry.S164
-rw-r--r--arch/m68k/68360/head-ram.S402
-rw-r--r--arch/m68k/68360/head-rom.S413
-rw-r--r--arch/m68k/68360/ints.c138
-rw-r--r--arch/m68k/Kconfig.cpu7
-rw-r--r--arch/m68k/Kconfig.debug2
-rw-r--r--arch/m68k/Kconfig.machine6
-rw-r--r--arch/m68k/Makefile3
-rw-r--r--arch/m68k/include/asm/commproc.h664
-rw-r--r--arch/m68k/include/asm/m68360.h13
-rw-r--r--arch/m68k/include/asm/m68360_enet.h177
-rw-r--r--arch/m68k/include/asm/m68360_pram.h431
-rw-r--r--arch/m68k/include/asm/m68360_quicc.h362
-rw-r--r--arch/m68k/include/asm/m68360_regs.h408
-rw-r--r--arch/m68k/kernel/early_printk.c8
-rw-r--r--arch/m68k/kernel/setup_no.c7
19 files changed, 5 insertions, 3690 deletions
diff --git a/arch/m68k/68360/Makefile b/arch/m68k/68360/Makefile
deleted file mode 100644
index 591ce42df3de..000000000000
--- a/arch/m68k/68360/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
1#
2# Makefile for 68360 machines.
3#
4model-y := ram
5model-$(CONFIG_ROMKERNEL) := rom
6
7obj-y := config.o commproc.o entry.o ints.o
8
9extra-y := head.o
10
11$(obj)/head.o: $(obj)/head-$(model-y).o
12 ln -sf head-$(model-y).o $(obj)/head.o
diff --git a/arch/m68k/68360/commproc.c b/arch/m68k/68360/commproc.c
deleted file mode 100644
index 14d7f35cd37b..000000000000
--- a/arch/m68k/68360/commproc.c
+++ /dev/null
@@ -1,309 +0,0 @@
1/*
2 * General Purpose functions for the global management of the
3 * Communication Processor Module.
4 *
5 * Copyright (c) 2000 Michael Leslie <mleslie@lineo.com>
6 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
7 *
8 * In addition to the individual control of the communication
9 * channels, there are a few functions that globally affect the
10 * communication processor.
11 *
12 * Buffer descriptors must be allocated from the dual ported memory
13 * space. The allocator for that is here. When the communication
14 * process is reset, we reclaim the memory available. There is
15 * currently no deallocator for this memory.
16 * The amount of space available is platform dependent. On the
17 * MBX, the EPPC software loads additional microcode into the
18 * communication processor, and uses some of the DP ram for this
19 * purpose. Current, the first 512 bytes and the last 256 bytes of
20 * memory are used. Right now I am conservative and only use the
21 * memory that can never be used for microcode. If there are
22 * applications that require more DP ram, we can expand the boundaries
23 * but then we have to be careful of any downloaded microcode.
24 *
25 */
26
27/*
28 * Michael Leslie <mleslie@lineo.com>
29 * adapted Dan Malek's ppc8xx drivers to M68360
30 *
31 */
32
33#include <linux/errno.h>
34#include <linux/init.h>
35#include <linux/sched.h>
36#include <linux/kernel.h>
37#include <linux/param.h>
38#include <linux/string.h>
39#include <linux/mm.h>
40#include <linux/interrupt.h>
41#include <asm/irq.h>
42#include <asm/m68360.h>
43#include <asm/commproc.h>
44
45/* #include <asm/page.h> */
46/* #include <asm/pgtable.h> */
47extern void *_quicc_base;
48extern unsigned int system_clock;
49
50
51static uint dp_alloc_base; /* Starting offset in DP ram */
52static uint dp_alloc_top; /* Max offset + 1 */
53
54#if 0
55static void *host_buffer; /* One page of host buffer */
56static void *host_end; /* end + 1 */
57#endif
58
59/* struct cpm360_t *cpmp; */ /* Pointer to comm processor space */
60
61QUICC *pquicc;
62/* QUICC *quicc_dpram; */ /* mleslie - temporary; use extern pquicc elsewhere instead */
63
64
65/* CPM interrupt vector functions. */
66struct cpm_action {
67 irq_handler_t handler;
68 void *dev_id;
69};
70static struct cpm_action cpm_vecs[CPMVEC_NR];
71static void cpm_interrupt(int irq, void * dev, struct pt_regs * regs);
72static void cpm_error_interrupt(void *);
73
74/* prototypes: */
75void cpm_install_handler(int vec, irq_handler_t handler, void *dev_id);
76void m360_cpm_reset(void);
77
78
79
80
81void __init m360_cpm_reset()
82{
83/* pte_t *pte; */
84
85 pquicc = (struct quicc *)(_quicc_base); /* initialized in crt0_rXm.S */
86
87 /* Perform a CPM reset. */
88 pquicc->cp_cr = (SOFTWARE_RESET | CMD_FLAG);
89
90 /* Wait for CPM to become ready (should be 2 clocks). */
91 while (pquicc->cp_cr & CMD_FLAG);
92
93 /* On the recommendation of the 68360 manual, p. 7-60
94 * - Set sdma interrupt service mask to 7
95 * - Set sdma arbitration ID to 4
96 */
97 pquicc->sdma_sdcr = 0x0740;
98
99
100 /* Claim the DP memory for our use.
101 */
102 dp_alloc_base = CPM_DATAONLY_BASE;
103 dp_alloc_top = dp_alloc_base + CPM_DATAONLY_SIZE;
104
105
106 /* Set the host page for allocation.
107 */
108 /* host_buffer = host_page_addr; */
109 /* host_end = host_page_addr + PAGE_SIZE; */
110
111 /* pte = find_pte(&init_mm, host_page_addr); */
112 /* pte_val(*pte) |= _PAGE_NO_CACHE; */
113 /* flush_tlb_page(current->mm->mmap, host_buffer); */
114
115 /* Tell everyone where the comm processor resides.
116 */
117/* cpmp = (cpm360_t *)commproc; */
118}
119
120
121/* This is called during init_IRQ. We used to do it above, but this
122 * was too early since init_IRQ was not yet called.
123 */
124void
125cpm_interrupt_init(void)
126{
127 /* Initialize the CPM interrupt controller.
128 * NOTE THAT pquicc had better have been initialized!
129 * reference: MC68360UM p. 7-377
130 */
131 pquicc->intr_cicr =
132 (CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) |
133 (CPM_INTERRUPT << 13) |
134 CICR_HP_MASK |
135 (CPM_VECTOR_BASE << 5) |
136 CICR_SPS;
137
138 /* mask all CPM interrupts from reaching the cpu32 core: */
139 pquicc->intr_cimr = 0;
140
141
142 /* mles - If I understand correctly, the 360 just pops over to the CPM
143 * specific vector, obviating the necessity to vector through the IRQ
144 * whose priority the CPM is set to. This needs a closer look, though.
145 */
146
147 /* Set our interrupt handler with the core CPU. */
148/* if (request_irq(CPM_INTERRUPT, cpm_interrupt, 0, "cpm", NULL) != 0) */
149/* panic("Could not allocate CPM IRQ!"); */
150
151 /* Install our own error handler.
152 */
153 /* I think we want to hold off on this one for the moment - mles */
154 /* cpm_install_handler(CPMVEC_ERROR, cpm_error_interrupt, NULL); */
155
156 /* master CPM interrupt enable */
157 /* pquicc->intr_cicr |= CICR_IEN; */ /* no such animal for 360 */
158}
159
160
161
162/* CPM interrupt controller interrupt.
163*/
164static void
165cpm_interrupt(int irq, void * dev, struct pt_regs * regs)
166{
167 /* uint vec; */
168
169 /* mles: Note that this stuff is currently being performed by
170 * M68360_do_irq(int vec, struct pt_regs *fp), in ../ints.c */
171
172 /* figure out the vector */
173 /* call that vector's handler */
174 /* clear the irq's bit in the service register */
175
176#if 0 /* old 860 stuff: */
177 /* Get the vector by setting the ACK bit and then reading
178 * the register.
179 */
180 ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_civr = 1;
181 vec = ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_civr;
182 vec >>= 11;
183
184
185 if (cpm_vecs[vec].handler != 0)
186 (*cpm_vecs[vec].handler)(cpm_vecs[vec].dev_id);
187 else
188 ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr &= ~(1 << vec);
189
190 /* After servicing the interrupt, we have to remove the status
191 * indicator.
192 */
193 ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cisr |= (1 << vec);
194#endif
195
196}
197
198/* The CPM can generate the error interrupt when there is a race condition
199 * between generating and masking interrupts. All we have to do is ACK it
200 * and return. This is a no-op function so we don't need any special
201 * tests in the interrupt handler.
202 */
203static void
204cpm_error_interrupt(void *dev)
205{
206}
207
208/* Install a CPM interrupt handler.
209*/
210void
211cpm_install_handler(int vec, irq_handler_t handler, void *dev_id)
212{
213
214 request_irq(vec, handler, 0, "timer", dev_id);
215
216/* if (cpm_vecs[vec].handler != 0) */
217/* printk(KERN_INFO "CPM interrupt %x replacing %x\n", */
218/* (uint)handler, (uint)cpm_vecs[vec].handler); */
219/* cpm_vecs[vec].handler = handler; */
220/* cpm_vecs[vec].dev_id = dev_id; */
221
222 /* ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr |= (1 << vec); */
223/* pquicc->intr_cimr |= (1 << vec); */
224
225}
226
227/* Free a CPM interrupt handler.
228*/
229void
230cpm_free_handler(int vec)
231{
232 cpm_vecs[vec].handler = NULL;
233 cpm_vecs[vec].dev_id = NULL;
234 /* ((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr &= ~(1 << vec); */
235 pquicc->intr_cimr &= ~(1 << vec);
236}
237
238
239
240
241/* Allocate some memory from the dual ported ram. We may want to
242 * enforce alignment restrictions, but right now everyone is a good
243 * citizen.
244 */
245uint
246m360_cpm_dpalloc(uint size)
247{
248 uint retloc;
249
250 if ((dp_alloc_base + size) >= dp_alloc_top)
251 return(CPM_DP_NOSPACE);
252
253 retloc = dp_alloc_base;
254 dp_alloc_base += size;
255
256 return(retloc);
257}
258
259
260#if 0 /* mleslie - for now these are simply kmalloc'd */
261/* We also own one page of host buffer space for the allocation of
262 * UART "fifos" and the like.
263 */
264uint
265m360_cpm_hostalloc(uint size)
266{
267 uint retloc;
268
269 if ((host_buffer + size) >= host_end)
270 return(0);
271
272 retloc = host_buffer;
273 host_buffer += size;
274
275 return(retloc);
276}
277#endif
278
279
280/* Set a baud rate generator. This needs lots of work. There are
281 * four BRGs, any of which can be wired to any channel.
282 * The internal baud rate clock is the system clock divided by 16.
283 * This assumes the baudrate is 16x oversampled by the uart.
284 */
285/* #define BRG_INT_CLK (((bd_t *)__res)->bi_intfreq * 1000000) */
286#define BRG_INT_CLK system_clock
287#define BRG_UART_CLK (BRG_INT_CLK/16)
288
289void
290m360_cpm_setbrg(uint brg, uint rate)
291{
292 volatile uint *bp;
293
294 /* This is good enough to get SMCs running.....
295 */
296 /* bp = (uint *)&cpmp->cp_brgc1; */
297 bp = (volatile uint *)(&pquicc->brgc[0].l);
298 bp += brg;
299 *bp = ((BRG_UART_CLK / rate - 1) << 1) | CPM_BRG_EN;
300}
301
302
303/*
304 * Local variables:
305 * c-indent-level: 4
306 * c-basic-offset: 4
307 * tab-width: 4
308 * End:
309 */
diff --git a/arch/m68k/68360/config.c b/arch/m68k/68360/config.c
deleted file mode 100644
index b65fe4eed38e..000000000000
--- a/arch/m68k/68360/config.c
+++ /dev/null
@@ -1,169 +0,0 @@
1/*
2 * config.c - non-mmu 68360 platform initialization code
3 *
4 * Copyright (c) 2000 Michael Leslie <mleslie@lineo.com>
5 * Copyright (C) 1993 Hamish Macdonald
6 * Copyright (C) 1999 D. Jeff Dionne <jeff@uclinux.org>
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file COPYING in the main directory of this archive
10 * for more details.
11 */
12
13#include <stdarg.h>
14#include <linux/init.h>
15#include <linux/types.h>
16#include <linux/kernel.h>
17#include <linux/mm.h>
18#include <linux/interrupt.h>
19#include <linux/irq.h>
20
21#include <asm/setup.h>
22#include <asm/pgtable.h>
23#include <asm/machdep.h>
24#include <asm/m68360.h>
25
26#ifdef CONFIG_UCQUICC
27#include <asm/bootstd.h>
28#endif
29
30extern void m360_cpm_reset(void);
31
32// Mask to select if the PLL prescaler is enabled.
33#define MCU_PREEN ((unsigned short)(0x0001 << 13))
34
35#if defined(CONFIG_UCQUICC)
36#define OSCILLATOR (unsigned long int)33000000
37#endif
38
39static irq_handler_t timer_interrupt;
40unsigned long int system_clock;
41
42extern QUICC *pquicc;
43
44/* TODO DON"T Hard Code this */
45/* calculate properly using the right PLL and prescaller */
46// unsigned int system_clock = 33000000l;
47extern unsigned long int system_clock; //In kernel setup.c
48
49
50static irqreturn_t hw_tick(int irq, void *dummy)
51{
52 /* Reset Timer1 */
53 /* TSTAT &= 0; */
54
55 pquicc->timer_ter1 = 0x0002; /* clear timer event */
56
57 return timer_interrupt(irq, dummy);
58}
59
60static struct irqaction m68360_timer_irq = {
61 .name = "timer",
62 .flags = IRQF_TIMER,
63 .handler = hw_tick,
64};
65
66void hw_timer_init(irq_handler_t handler)
67{
68 unsigned char prescaler;
69 unsigned short tgcr_save;
70
71#if 0
72 /* Restart mode, Enable int, 32KHz, Enable timer */
73 TCTL = TCTL_OM | TCTL_IRQEN | TCTL_CLKSOURCE_32KHZ | TCTL_TEN;
74 /* Set prescaler (Divide 32KHz by 32)*/
75 TPRER = 31;
76 /* Set compare register 32Khz / 32 / 10 = 100 */
77 TCMP = 10;
78
79 request_irq(IRQ_MACHSPEC | 1, timer_routine, 0, "timer", NULL);
80#endif
81
82 /* General purpose quicc timers: MC68360UM p7-20 */
83
84 /* Set up timer 1 (in [1..4]) to do 100Hz */
85 tgcr_save = pquicc->timer_tgcr & 0xfff0;
86 pquicc->timer_tgcr = tgcr_save; /* stop and reset timer 1 */
87 /* pquicc->timer_tgcr |= 0x4444; */ /* halt timers when FREEZE (ie bdm freeze) */
88
89 prescaler = 8;
90 pquicc->timer_tmr1 = 0x001a | /* or=1, frr=1, iclk=01b */
91 (unsigned short)((prescaler - 1) << 8);
92
93 pquicc->timer_tcn1 = 0x0000; /* initial count */
94 /* calculate interval for 100Hz based on the _system_clock: */
95 pquicc->timer_trr1 = (system_clock/ prescaler) / HZ; /* reference count */
96
97 pquicc->timer_ter1 = 0x0003; /* clear timer events */
98
99 timer_interrupt = handler;
100
101 /* enable timer 1 interrupt in CIMR */
102 setup_irq(CPMVEC_TIMER1, &m68360_timer_irq);
103
104 /* Start timer 1: */
105 tgcr_save = (pquicc->timer_tgcr & 0xfff0) | 0x0001;
106 pquicc->timer_tgcr = tgcr_save;
107}
108
109void BSP_reset (void)
110{
111 local_irq_disable();
112 asm volatile (
113 "moveal #_start, %a0;\n"
114 "moveb #0, 0xFFFFF300;\n"
115 "moveal 0(%a0), %sp;\n"
116 "moveal 4(%a0), %a0;\n"
117 "jmp (%a0);\n"
118 );
119}
120
121unsigned char *scc1_hwaddr;
122static int errno;
123
124#if defined (CONFIG_UCQUICC)
125_bsc0(char *, getserialnum)
126_bsc1(unsigned char *, gethwaddr, int, a)
127_bsc1(char *, getbenv, char *, a)
128#endif
129
130
131void __init config_BSP(char *command, int len)
132{
133 unsigned char *p;
134
135 m360_cpm_reset();
136
137 /* Calculate the real system clock value. */
138 {
139 unsigned int local_pllcr = (unsigned int)(pquicc->sim_pllcr);
140 if( local_pllcr & MCU_PREEN ) // If the prescaler is dividing by 128
141 {
142 int mf = (int)(pquicc->sim_pllcr & 0x0fff);
143 system_clock = (OSCILLATOR / 128) * (mf + 1);
144 }
145 else
146 {
147 int mf = (int)(pquicc->sim_pllcr & 0x0fff);
148 system_clock = (OSCILLATOR) * (mf + 1);
149 }
150 }
151
152 printk(KERN_INFO "\n68360 QUICC support (C) 2000 Lineo Inc.\n");
153
154#if defined(CONFIG_UCQUICC) && 0
155 printk(KERN_INFO "uCquicc serial string [%s]\n",getserialnum());
156 p = scc1_hwaddr = gethwaddr(0);
157 printk(KERN_INFO "uCquicc hwaddr %pM\n", p);
158
159 p = getbenv("APPEND");
160 if (p)
161 strcpy(p,command);
162 else
163 command[0] = 0;
164#else
165 scc1_hwaddr = "\00\01\02\03\04\05";
166#endif
167
168 mach_reset = BSP_reset;
169}
diff --git a/arch/m68k/68360/entry.S b/arch/m68k/68360/entry.S
deleted file mode 100644
index 22eb3022f9ee..000000000000
--- a/arch/m68k/68360/entry.S
+++ /dev/null
@@ -1,164 +0,0 @@
1/*
2 * entry.S - non-mmu 68360 interrupt and exceptions entry points
3 *
4 * Copyright (C) 1991, 1992 Linus Torvalds
5 * Copyright (C) 2001 SED Systems, a Division of Calian Ltd.
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file README.legal in the main directory of this archive
9 * for more details.
10 *
11 * Linux/m68k support by Hamish Macdonald
12 * M68360 Port by SED Systems, and Lineo.
13 */
14
15#include <linux/linkage.h>
16#include <asm/thread_info.h>
17#include <asm/unistd.h>
18#include <asm/errno.h>
19#include <asm/setup.h>
20#include <asm/segment.h>
21#include <asm/traps.h>
22#include <asm/asm-offsets.h>
23#include <asm/entry.h>
24
25.text
26
27.globl system_call
28.globl resume
29.globl ret_from_exception
30.globl ret_from_signal
31.globl sys_call_table
32.globl bad_interrupt
33.globl inthandler
34
35badsys:
36 movel #-ENOSYS,%sp@(PT_OFF_D0)
37 jra ret_from_exception
38
39do_trace:
40 movel #-ENOSYS,%sp@(PT_OFF_D0) /* needed for strace*/
41 subql #4,%sp
42 SAVE_SWITCH_STACK
43 jbsr syscall_trace_enter
44 RESTORE_SWITCH_STACK
45 addql #4,%sp
46 movel %sp@(PT_OFF_ORIG_D0),%d1
47 movel #-ENOSYS,%d0
48 cmpl #NR_syscalls,%d1
49 jcc 1f
50 lsl #2,%d1
51 lea sys_call_table, %a0
52 jbsr %a0@(%d1)
53
541: movel %d0,%sp@(PT_OFF_D0) /* save the return value */
55 subql #4,%sp /* dummy return address */
56 SAVE_SWITCH_STACK
57 jbsr syscall_trace_leave
58
59ret_from_signal:
60 RESTORE_SWITCH_STACK
61 addql #4,%sp
62 jra ret_from_exception
63
64ENTRY(system_call)
65 SAVE_ALL_SYS
66
67 /* save top of frame*/
68 pea %sp@
69 jbsr set_esp0
70 addql #4,%sp
71
72 movel %sp@(PT_OFF_ORIG_D0),%d0
73
74 movel %sp,%d1 /* get thread_info pointer */
75 andl #-THREAD_SIZE,%d1
76 movel %d1,%a2
77 btst #(TIF_SYSCALL_TRACE%8),%a2@(TINFO_FLAGS+(31-TIF_SYSCALL_TRACE)/8)
78 jne do_trace
79 cmpl #NR_syscalls,%d0
80 jcc badsys
81 lsl #2,%d0
82 lea sys_call_table,%a0
83 movel %a0@(%d0), %a0
84 jbsr %a0@
85 movel %d0,%sp@(PT_OFF_D0) /* save the return value*/
86
87ret_from_exception:
88 btst #5,%sp@(PT_OFF_SR) /* check if returning to kernel*/
89 jeq Luser_return /* if so, skip resched, signals*/
90
91Lkernel_return:
92 RESTORE_ALL
93
94Luser_return:
95 /* only allow interrupts when we are really the last one on the*/
96 /* kernel stack, otherwise stack overflow can occur during*/
97 /* heavy interrupt load*/
98 andw #ALLOWINT,%sr
99
100 movel %sp,%d1 /* get thread_info pointer */
101 andl #-THREAD_SIZE,%d1
102 movel %d1,%a2
1031:
104 move %a2@(TINFO_FLAGS),%d1 /* thread_info->flags */
105 jne Lwork_to_do
106 RESTORE_ALL
107
108Lwork_to_do:
109 movel %a2@(TINFO_FLAGS),%d1 /* thread_info->flags */
110 btst #TIF_NEED_RESCHED,%d1
111 jne reschedule
112
113Lsignal_return:
114 subql #4,%sp /* dummy return address*/
115 SAVE_SWITCH_STACK
116 pea %sp@(SWITCH_STACK_SIZE)
117 bsrw do_notify_resume
118 addql #4,%sp
119 RESTORE_SWITCH_STACK
120 addql #4,%sp
121 jra 1b
122
123/*
124 * This is the main interrupt handler, responsible for calling do_IRQ()
125 */
126inthandler:
127 SAVE_ALL_INT
128 movew %sp@(PT_OFF_FORMATVEC), %d0
129 and.l #0x3ff, %d0
130 lsr.l #0x02, %d0
131
132 movel %sp,%sp@-
133 movel %d0,%sp@- /* put vector # on stack*/
134 jbsr do_IRQ /* process the IRQ */
135 addql #8,%sp /* pop parameters off stack*/
136 jra ret_from_exception
137
138/*
139 * Handler for uninitialized and spurious interrupts.
140 */
141bad_interrupt:
142 addql #1,irq_err_count
143 rte
144
145/*
146 * Beware - when entering resume, prev (the current task) is
147 * in a0, next (the new task) is in a1, so don't change these
148 * registers until their contents are no longer needed.
149 */
150ENTRY(resume)
151 movel %a0,%d1 /* save prev thread in d1 */
152 movew %sr,%a0@(TASK_THREAD+THREAD_SR) /* save sr */
153 SAVE_SWITCH_STACK
154 movel %sp,%a0@(TASK_THREAD+THREAD_KSP) /* save kernel stack */
155 movel %usp,%a3 /* save usp */
156 movel %a3,%a0@(TASK_THREAD+THREAD_USP)
157
158 movel %a1@(TASK_THREAD+THREAD_USP),%a3 /* restore user stack */
159 movel %a3,%usp
160 movel %a1@(TASK_THREAD+THREAD_KSP),%sp /* restore new thread stack */
161 RESTORE_SWITCH_STACK
162 movew %a1@(TASK_THREAD+THREAD_SR),%sr /* restore thread status reg */
163 rts
164
diff --git a/arch/m68k/68360/head-ram.S b/arch/m68k/68360/head-ram.S
deleted file mode 100644
index 62bc56f41d57..000000000000
--- a/arch/m68k/68360/head-ram.S
+++ /dev/null
@@ -1,402 +0,0 @@
1/*
2 * head-ram.S - startup code for Motorola 68360
3 *
4 * Copyright 2001 (C) SED Systems, a Division of Calian Ltd.
5 * Based on: arch/m68knommu/platform/68328/pilot/crt0_rom.S
6 * Based on: arch/m68knommu/platform/68360/uCquicc/crt0_rom.S, 2.0.38.1.pre7
7 * uClinux Kernel
8 * Copyright (C) Michael Leslie <mleslie@lineo.com>
9 * Based on: arch/m68knommu/platform/68EZ328/ucsimm/crt0_rom.S
10 * Copyright (C) 1998 D. Jeff Dionne <jeff@uclinux.org>,
11 *
12 */
13#define ASSEMBLY
14
15.global _stext
16.global _start
17
18.global _rambase
19.global _ramvec
20.global _ramstart
21.global _ramend
22
23.global _quicc_base
24.global _periph_base
25
26#define RAMEND (CONFIG_RAMBASE + CONFIG_RAMSIZE)
27#define ROMEND (CONFIG_ROMBASE + CONFIG_ROMSIZE)
28
29#define REGB 0x1000
30#define PEPAR (_dprbase + REGB + 0x0016)
31#define GMR (_dprbase + REGB + 0x0040)
32#define OR0 (_dprbase + REGB + 0x0054)
33#define BR0 (_dprbase + REGB + 0x0050)
34#define OR1 (_dprbase + REGB + 0x0064)
35#define BR1 (_dprbase + REGB + 0x0060)
36#define OR4 (_dprbase + REGB + 0x0094)
37#define BR4 (_dprbase + REGB + 0x0090)
38#define OR6 (_dprbase + REGB + 0x00b4)
39#define BR6 (_dprbase + REGB + 0x00b0)
40#define OR7 (_dprbase + REGB + 0x00c4)
41#define BR7 (_dprbase + REGB + 0x00c0)
42
43#define MCR (_dprbase + REGB + 0x0000)
44#define AVR (_dprbase + REGB + 0x0008)
45
46#define SYPCR (_dprbase + REGB + 0x0022)
47
48#define PLLCR (_dprbase + REGB + 0x0010)
49#define CLKOCR (_dprbase + REGB + 0x000C)
50#define CDVCR (_dprbase + REGB + 0x0014)
51
52#define BKAR (_dprbase + REGB + 0x0030)
53#define BKCR (_dprbase + REGB + 0x0034)
54#define SWIV (_dprbase + REGB + 0x0023)
55#define PICR (_dprbase + REGB + 0x0026)
56#define PITR (_dprbase + REGB + 0x002A)
57
58/* Define for all memory configuration */
59#define MCU_SIM_GMR 0x00000000
60#define SIM_OR_MASK 0x0fffffff
61
62/* Defines for chip select zero - the flash */
63#define SIM_OR0_MASK 0x20000002
64#define SIM_BR0_MASK 0x00000001
65
66
67/* Defines for chip select one - the RAM */
68#define SIM_OR1_MASK 0x10000000
69#define SIM_BR1_MASK 0x00000001
70
71#define MCU_SIM_MBAR_ADRS 0x0003ff00
72#define MCU_SIM_MBAR_BA_MASK 0xfffff000
73#define MCU_SIM_MBAR_AS_MASK 0x00000001
74
75#define MCU_SIM_PEPAR 0x00B4
76
77#define MCU_DISABLE_INTRPTS 0x2700
78#define MCU_SIM_AVR 0x00
79
80#define MCU_SIM_MCR 0x00005cff
81
82#define MCU_SIM_CLKOCR 0x00
83#define MCU_SIM_PLLCR 0x8000
84#define MCU_SIM_CDVCR 0x0000
85
86#define MCU_SIM_SYPCR 0x0000
87#define MCU_SIM_SWIV 0x00
88#define MCU_SIM_PICR 0x0000
89#define MCU_SIM_PITR 0x0000
90
91
92#include <asm/m68360_regs.h>
93
94
95/*
96 * By the time this RAM specific code begins to execute, DPRAM
97 * and DRAM should already be mapped and accessible.
98 */
99
100 .text
101_start:
102_stext:
103 nop
104 ori.w #MCU_DISABLE_INTRPTS, %sr /* disable interrupts: */
105 /* We should not need to setup the boot stack the reset should do it. */
106 movea.l #RAMEND, %sp /*set up stack at the end of DRAM:*/
107
108set_mbar_register:
109 moveq.l #0x07, %d1 /* Setup MBAR */
110 movec %d1, %dfc
111
112 lea.l MCU_SIM_MBAR_ADRS, %a0
113 move.l #_dprbase, %d0
114 andi.l #MCU_SIM_MBAR_BA_MASK, %d0
115 ori.l #MCU_SIM_MBAR_AS_MASK, %d0
116 moves.l %d0, %a0@
117
118 moveq.l #0x05, %d1
119 movec.l %d1, %dfc
120
121 /* Now we can begin to access registers in DPRAM */
122
123set_sim_mcr:
124 /* Set Module Configuration Register */
125 move.l #MCU_SIM_MCR, MCR
126
127 /* to do: Determine cause of reset */
128
129 /*
130 * configure system clock MC68360 p. 6-40
131 * (value +1)*osc/128 = system clock
132 */
133set_sim_clock:
134 move.w #MCU_SIM_PLLCR, PLLCR
135 move.b #MCU_SIM_CLKOCR, CLKOCR
136 move.w #MCU_SIM_CDVCR, CDVCR
137
138 /* Wait for the PLL to settle */
139 move.w #16384, %d0
140pll_settle_wait:
141 subi.w #1, %d0
142 bne pll_settle_wait
143
144 /* Setup the system protection register, and watchdog timer register */
145 move.b #MCU_SIM_SWIV, SWIV
146 move.w #MCU_SIM_PICR, PICR
147 move.w #MCU_SIM_PITR, PITR
148 move.w #MCU_SIM_SYPCR, SYPCR
149
150 /* Clear DPRAM - system + parameter */
151 movea.l #_dprbase, %a0
152 movea.l #_dprbase+0x2000, %a1
153
154 /* Copy 0 to %a0 until %a0 == %a1 */
155clear_dpram:
156 movel #0, %a0@+
157 cmpal %a0, %a1
158 bhi clear_dpram
159
160configure_memory_controller:
161 /* Set up Global Memory Register (GMR) */
162 move.l #MCU_SIM_GMR, %d0
163 move.l %d0, GMR
164
165configure_chip_select_0:
166 move.l #RAMEND, %d0
167 subi.l #__ramstart, %d0
168 subq.l #0x01, %d0
169 eori.l #SIM_OR_MASK, %d0
170 ori.l #SIM_OR0_MASK, %d0
171 move.l %d0, OR0
172
173 move.l #__ramstart, %d0
174 ori.l #SIM_BR0_MASK, %d0
175 move.l %d0, BR0
176
177configure_chip_select_1:
178 move.l #ROMEND, %d0
179 subi.l #__rom_start, %d0
180 subq.l #0x01, %d0
181 eori.l #SIM_OR_MASK, %d0
182 ori.l #SIM_OR1_MASK, %d0
183 move.l %d0, OR1
184
185 move.l #__rom_start, %d0
186 ori.l #SIM_BR1_MASK, %d0
187 move.l %d0, BR1
188
189 move.w #MCU_SIM_PEPAR, PEPAR
190
191 /* point to vector table: */
192 move.l #_romvec, %a0
193 move.l #_ramvec, %a1
194copy_vectors:
195 move.l %a0@, %d0
196 move.l %d0, %a1@
197 move.l %a0@, %a1@
198 addq.l #0x04, %a0
199 addq.l #0x04, %a1
200 cmp.l #_start, %a0
201 blt copy_vectors
202
203 move.l #_ramvec, %a1
204 movec %a1, %vbr
205
206
207 /* Copy data segment from ROM to RAM */
208 moveal #_stext, %a0
209 moveal #_sdata, %a1
210 moveal #_edata, %a2
211
212 /* Copy %a0 to %a1 until %a1 == %a2 */
213LD1:
214 move.l %a0@, %d0
215 addq.l #0x04, %a0
216 move.l %d0, %a1@
217 addq.l #0x04, %a1
218 cmp.l #_edata, %a1
219 blt LD1
220
221 moveal #__bss_start, %a0
222 moveal #__bss_stop, %a1
223
224 /* Copy 0 to %a0 until %a0 == %a1 */
225L1:
226 movel #0, %a0@+
227 cmpal %a0, %a1
228 bhi L1
229
230load_quicc:
231 move.l #_dprbase, _quicc_base
232
233store_ram_size:
234 /* Set ram size information */
235 move.l #_sdata, _rambase
236 move.l #__bss_stop, _ramstart
237 move.l #RAMEND, %d0
238 sub.l #0x1000, %d0 /* Reserve 4K for stack space.*/
239 move.l %d0, _ramend /* Different from RAMEND.*/
240
241 pea 0
242 pea env
243 pea %sp@(4)
244 pea 0
245
246 lea init_thread_union, %a2
247 lea 0x2000(%a2), %sp
248
249lp:
250 jsr start_kernel
251
252_exit:
253 jmp _exit
254
255
256 .data
257 .align 4
258env:
259 .long 0
260_quicc_base:
261 .long 0
262_periph_base:
263 .long 0
264_ramvec:
265 .long 0
266_rambase:
267 .long 0
268_ramstart:
269 .long 0
270_ramend:
271 .long 0
272_dprbase:
273 .long 0xffffe000
274
275 .text
276
277 /*
278 * These are the exception vectors at boot up, they are copied into RAM
279 * and then overwritten as needed.
280 */
281
282.section ".data..initvect","awx"
283 .long RAMEND /* Reset: Initial Stack Pointer - 0. */
284 .long _start /* Reset: Initial Program Counter - 1. */
285 .long buserr /* Bus Error - 2. */
286 .long trap /* Address Error - 3. */
287 .long trap /* Illegal Instruction - 4. */
288 .long trap /* Divide by zero - 5. */
289 .long trap /* CHK, CHK2 Instructions - 6. */
290 .long trap /* TRAPcc, TRAPV Instructions - 7. */
291 .long trap /* Privilege Violation - 8. */
292 .long trap /* Trace - 9. */
293 .long trap /* Line 1010 Emulator - 10. */
294 .long trap /* Line 1111 Emualtor - 11. */
295 .long trap /* Harware Breakpoint - 12. */
296 .long trap /* (Reserved for Coprocessor Protocol Violation)- 13. */
297 .long trap /* Format Error - 14. */
298 .long trap /* Uninitialized Interrupt - 15. */
299 .long trap /* (Unassigned, Reserver) - 16. */
300 .long trap /* (Unassigned, Reserver) - 17. */
301 .long trap /* (Unassigned, Reserver) - 18. */
302 .long trap /* (Unassigned, Reserver) - 19. */
303 .long trap /* (Unassigned, Reserver) - 20. */
304 .long trap /* (Unassigned, Reserver) - 21. */
305 .long trap /* (Unassigned, Reserver) - 22. */
306 .long trap /* (Unassigned, Reserver) - 23. */
307 .long trap /* Spurious Interrupt - 24. */
308 .long trap /* Level 1 Interrupt Autovector - 25. */
309 .long trap /* Level 2 Interrupt Autovector - 26. */
310 .long trap /* Level 3 Interrupt Autovector - 27. */
311 .long trap /* Level 4 Interrupt Autovector - 28. */
312 .long trap /* Level 5 Interrupt Autovector - 29. */
313 .long trap /* Level 6 Interrupt Autovector - 30. */
314 .long trap /* Level 7 Interrupt Autovector - 31. */
315 .long system_call /* Trap Instruction Vectors 0 - 32. */
316 .long trap /* Trap Instruction Vectors 1 - 33. */
317 .long trap /* Trap Instruction Vectors 2 - 34. */
318 .long trap /* Trap Instruction Vectors 3 - 35. */
319 .long trap /* Trap Instruction Vectors 4 - 36. */
320 .long trap /* Trap Instruction Vectors 5 - 37. */
321 .long trap /* Trap Instruction Vectors 6 - 38. */
322 .long trap /* Trap Instruction Vectors 7 - 39. */
323 .long trap /* Trap Instruction Vectors 8 - 40. */
324 .long trap /* Trap Instruction Vectors 9 - 41. */
325 .long trap /* Trap Instruction Vectors 10 - 42. */
326 .long trap /* Trap Instruction Vectors 11 - 43. */
327 .long trap /* Trap Instruction Vectors 12 - 44. */
328 .long trap /* Trap Instruction Vectors 13 - 45. */
329 .long trap /* Trap Instruction Vectors 14 - 46. */
330 .long trap /* Trap Instruction Vectors 15 - 47. */
331 .long 0 /* (Reserved for Coprocessor) - 48. */
332 .long 0 /* (Reserved for Coprocessor) - 49. */
333 .long 0 /* (Reserved for Coprocessor) - 50. */
334 .long 0 /* (Reserved for Coprocessor) - 51. */
335 .long 0 /* (Reserved for Coprocessor) - 52. */
336 .long 0 /* (Reserved for Coprocessor) - 53. */
337 .long 0 /* (Reserved for Coprocessor) - 54. */
338 .long 0 /* (Reserved for Coprocessor) - 55. */
339 .long 0 /* (Reserved for Coprocessor) - 56. */
340 .long 0 /* (Reserved for Coprocessor) - 57. */
341 .long 0 /* (Reserved for Coprocessor) - 58. */
342 .long 0 /* (Unassigned, Reserved) - 59. */
343 .long 0 /* (Unassigned, Reserved) - 60. */
344 .long 0 /* (Unassigned, Reserved) - 61. */
345 .long 0 /* (Unassigned, Reserved) - 62. */
346 .long 0 /* (Unassigned, Reserved) - 63. */
347 /* The assignment of these vectors to the CPM is */
348 /* dependent on the configuration of the CPM vba */
349 /* fields. */
350 .long 0 /* (User-Defined Vectors 1) CPM Error - 64. */
351 .long 0 /* (User-Defined Vectors 2) CPM Parallel IO PC11- 65. */
352 .long 0 /* (User-Defined Vectors 3) CPM Parallel IO PC10- 66. */
353 .long 0 /* (User-Defined Vectors 4) CPM SMC2 / PIP - 67. */
354 .long 0 /* (User-Defined Vectors 5) CPM SMC1 - 68. */
355 .long 0 /* (User-Defined Vectors 6) CPM SPI - 69. */
356 .long 0 /* (User-Defined Vectors 7) CPM Parallel IO PC9 - 70. */
357 .long 0 /* (User-Defined Vectors 8) CPM Timer 4 - 71. */
358 .long 0 /* (User-Defined Vectors 9) CPM Reserved - 72. */
359 .long 0 /* (User-Defined Vectors 10) CPM Parallel IO PC8- 73. */
360 .long 0 /* (User-Defined Vectors 11) CPM Parallel IO PC7- 74. */
361 .long 0 /* (User-Defined Vectors 12) CPM Parallel IO PC6- 75. */
362 .long 0 /* (User-Defined Vectors 13) CPM Timer 3 - 76. */
363 .long 0 /* (User-Defined Vectors 14) CPM Reserved - 77. */
364 .long 0 /* (User-Defined Vectors 15) CPM Parallel IO PC5- 78. */
365 .long 0 /* (User-Defined Vectors 16) CPM Parallel IO PC4- 79. */
366 .long 0 /* (User-Defined Vectors 17) CPM Reserved - 80. */
367 .long 0 /* (User-Defined Vectors 18) CPM RISC Timer Tbl - 81. */
368 .long 0 /* (User-Defined Vectors 19) CPM Timer 2 - 82. */
369 .long 0 /* (User-Defined Vectors 21) CPM Reserved - 83. */
370 .long 0 /* (User-Defined Vectors 22) CPM IDMA2 - 84. */
371 .long 0 /* (User-Defined Vectors 23) CPM IDMA1 - 85. */
372 .long 0 /* (User-Defined Vectors 24) CPM SDMA Bus Err - 86. */
373 .long 0 /* (User-Defined Vectors 25) CPM Parallel IO PC3- 87. */
374 .long 0 /* (User-Defined Vectors 26) CPM Parallel IO PC2- 88. */
375 .long 0 /* (User-Defined Vectors 27) CPM Timer 1 - 89. */
376 .long 0 /* (User-Defined Vectors 28) CPM Parallel IO PC1- 90. */
377 .long 0 /* (User-Defined Vectors 29) CPM SCC 4 - 91. */
378 .long 0 /* (User-Defined Vectors 30) CPM SCC 3 - 92. */
379 .long 0 /* (User-Defined Vectors 31) CPM SCC 2 - 93. */
380 .long 0 /* (User-Defined Vectors 32) CPM SCC 1 - 94. */
381 .long 0 /* (User-Defined Vectors 33) CPM Parallel IO PC0- 95. */
382 /* I don't think anything uses the vectors after here. */
383 .long 0 /* (User-Defined Vectors 34) - 96. */
384 .long 0,0,0,0,0 /* (User-Defined Vectors 35 - 39). */
385 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 40 - 49). */
386 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 50 - 59). */
387 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 60 - 69). */
388 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 70 - 79). */
389 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 80 - 89). */
390 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 90 - 99). */
391 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 100 - 109). */
392 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 110 - 119). */
393 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 120 - 129). */
394 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 130 - 139). */
395 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 140 - 149). */
396 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 150 - 159). */
397 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 160 - 169). */
398 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 170 - 179). */
399 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 180 - 189). */
400 .long 0,0,0 /* (User-Defined Vectors 190 - 192). */
401.text
402ignore: rte
diff --git a/arch/m68k/68360/head-rom.S b/arch/m68k/68360/head-rom.S
deleted file mode 100644
index b3a7e40f35e1..000000000000
--- a/arch/m68k/68360/head-rom.S
+++ /dev/null
@@ -1,413 +0,0 @@
1/*
2 * head-rom.S - startup code for Motorola 68360
3 *
4 * Copyright (C) SED Systems, a Division of Calian Ltd.
5 * Based on: arch/m68knommu/platform/68328/pilot/crt0_rom.S
6 * Based on: arch/m68knommu/platform/68360/uCquicc/crt0_rom.S, 2.0.38.1.pre7
7 * uClinux Kernel
8 * Copyright (C) Michael Leslie <mleslie@lineo.com>
9 * Based on: arch/m68knommu/platform/68EZ328/ucsimm/crt0_rom.S
10 * Copyright (C) 1998 D. Jeff Dionne <jeff@uclinux.org>,
11 *
12 */
13
14.global _stext
15.global __bss_start
16.global _start
17
18.global _rambase
19.global _ramvec
20.global _ramstart
21.global _ramend
22
23.global _quicc_base
24.global _periph_base
25
26#define RAMEND (CONFIG_RAMBASE + CONFIG_RAMSIZE)
27
28#define REGB 0x1000
29#define PEPAR (_dprbase + REGB + 0x0016)
30#define GMR (_dprbase + REGB + 0x0040)
31#define OR0 (_dprbase + REGB + 0x0054)
32#define BR0 (_dprbase + REGB + 0x0050)
33
34#define OR1 (_dprbase + REGB + 0x0064)
35#define BR1 (_dprbase + REGB + 0x0060)
36
37#define OR2 (_dprbase + REGB + 0x0074)
38#define BR2 (_dprbase + REGB + 0x0070)
39
40#define OR3 (_dprbase + REGB + 0x0084)
41#define BR3 (_dprbase + REGB + 0x0080)
42
43#define OR4 (_dprbase + REGB + 0x0094)
44#define BR4 (_dprbase + REGB + 0x0090)
45
46#define OR5 (_dprbase + REGB + 0x00A4)
47#define BR5 (_dprbase + REGB + 0x00A0)
48
49#define OR6 (_dprbase + REGB + 0x00b4)
50#define BR6 (_dprbase + REGB + 0x00b0)
51
52#define OR7 (_dprbase + REGB + 0x00c4)
53#define BR7 (_dprbase + REGB + 0x00c0)
54
55#define MCR (_dprbase + REGB + 0x0000)
56#define AVR (_dprbase + REGB + 0x0008)
57
58#define SYPCR (_dprbase + REGB + 0x0022)
59
60#define PLLCR (_dprbase + REGB + 0x0010)
61#define CLKOCR (_dprbase + REGB + 0x000C)
62#define CDVCR (_dprbase + REGB + 0x0014)
63
64#define BKAR (_dprbase + REGB + 0x0030)
65#define BKCR (_dprbase + REGB + 0x0034)
66#define SWIV (_dprbase + REGB + 0x0023)
67#define PICR (_dprbase + REGB + 0x0026)
68#define PITR (_dprbase + REGB + 0x002A)
69
70/* Define for all memory configuration */
71#define MCU_SIM_GMR 0x00000000
72#define SIM_OR_MASK 0x0fffffff
73
74/* Defines for chip select zero - the flash */
75#define SIM_OR0_MASK 0x20000000
76#define SIM_BR0_MASK 0x00000001
77
78/* Defines for chip select one - the RAM */
79#define SIM_OR1_MASK 0x10000000
80#define SIM_BR1_MASK 0x00000001
81
82#define MCU_SIM_MBAR_ADRS 0x0003ff00
83#define MCU_SIM_MBAR_BA_MASK 0xfffff000
84#define MCU_SIM_MBAR_AS_MASK 0x00000001
85
86#define MCU_SIM_PEPAR 0x00B4
87
88#define MCU_DISABLE_INTRPTS 0x2700
89#define MCU_SIM_AVR 0x00
90
91#define MCU_SIM_MCR 0x00005cff
92
93#define MCU_SIM_CLKOCR 0x00
94#define MCU_SIM_PLLCR 0x8000
95#define MCU_SIM_CDVCR 0x0000
96
97#define MCU_SIM_SYPCR 0x0000
98#define MCU_SIM_SWIV 0x00
99#define MCU_SIM_PICR 0x0000
100#define MCU_SIM_PITR 0x0000
101
102
103#include <asm/m68360_regs.h>
104
105
106/*
107 * By the time this RAM specific code begins to execute, DPRAM
108 * and DRAM should already be mapped and accessible.
109 */
110
111 .text
112_start:
113_stext:
114 nop
115 ori.w #MCU_DISABLE_INTRPTS, %sr /* disable interrupts: */
116 /* We should not need to setup the boot stack the reset should do it. */
117 movea.l #RAMEND, %sp /* set up stack at the end of DRAM:*/
118
119
120set_mbar_register:
121 moveq.l #0x07, %d1 /* Setup MBAR */
122 movec %d1, %dfc
123
124 lea.l MCU_SIM_MBAR_ADRS, %a0
125 move.l #_dprbase, %d0
126 andi.l #MCU_SIM_MBAR_BA_MASK, %d0
127 ori.l #MCU_SIM_MBAR_AS_MASK, %d0
128 moves.l %d0, %a0@
129
130 moveq.l #0x05, %d1
131 movec.l %d1, %dfc
132
133 /* Now we can begin to access registers in DPRAM */
134
135set_sim_mcr:
136 /* Set Module Configuration Register */
137 move.l #MCU_SIM_MCR, MCR
138
139 /* to do: Determine cause of reset */
140
141 /*
142 * configure system clock MC68360 p. 6-40
143 * (value +1)*osc/128 = system clock
144 * or
145 * (value + 1)*osc = system clock
146 * You do not need to divide the oscillator by 128 unless you want to.
147 */
148set_sim_clock:
149 move.w #MCU_SIM_PLLCR, PLLCR
150 move.b #MCU_SIM_CLKOCR, CLKOCR
151 move.w #MCU_SIM_CDVCR, CDVCR
152
153 /* Wait for the PLL to settle */
154 move.w #16384, %d0
155pll_settle_wait:
156 subi.w #1, %d0
157 bne pll_settle_wait
158
159 /* Setup the system protection register, and watchdog timer register */
160 move.b #MCU_SIM_SWIV, SWIV
161 move.w #MCU_SIM_PICR, PICR
162 move.w #MCU_SIM_PITR, PITR
163 move.w #MCU_SIM_SYPCR, SYPCR
164
165 /* Clear DPRAM - system + parameter */
166 movea.l #_dprbase, %a0
167 movea.l #_dprbase+0x2000, %a1
168
169 /* Copy 0 to %a0 until %a0 == %a1 */
170clear_dpram:
171 movel #0, %a0@+
172 cmpal %a0, %a1
173 bhi clear_dpram
174
175configure_memory_controller:
176 /* Set up Global Memory Register (GMR) */
177 move.l #MCU_SIM_GMR, %d0
178 move.l %d0, GMR
179
180configure_chip_select_0:
181 move.l #0x00400000, %d0
182 subq.l #0x01, %d0
183 eori.l #SIM_OR_MASK, %d0
184 ori.l #SIM_OR0_MASK, %d0
185 move.l %d0, OR0
186
187 move.l #__rom_start, %d0
188 ori.l #SIM_BR0_MASK, %d0
189 move.l %d0, BR0
190
191 move.l #0x0, BR1
192 move.l #0x0, BR2
193 move.l #0x0, BR3
194 move.l #0x0, BR4
195 move.l #0x0, BR5
196 move.l #0x0, BR6
197 move.l #0x0, BR7
198
199 move.w #MCU_SIM_PEPAR, PEPAR
200
201 /* point to vector table: */
202 move.l #_romvec, %a0
203 move.l #_ramvec, %a1
204copy_vectors:
205 move.l %a0@, %d0
206 move.l %d0, %a1@
207 move.l %a0@, %a1@
208 addq.l #0x04, %a0
209 addq.l #0x04, %a1
210 cmp.l #_start, %a0
211 blt copy_vectors
212
213 move.l #_ramvec, %a1
214 movec %a1, %vbr
215
216
217 /* Copy data segment from ROM to RAM */
218 moveal #_etext, %a0
219 moveal #_sdata, %a1
220 moveal #_edata, %a2
221
222 /* Copy %a0 to %a1 until %a1 == %a2 */
223LD1:
224 move.l %a0@, %d0
225 addq.l #0x04, %a0
226 move.l %d0, %a1@
227 addq.l #0x04, %a1
228 cmp.l #_edata, %a1
229 blt LD1
230
231 moveal #__bss_start, %a0
232 moveal #__bss_stop, %a1
233
234 /* Copy 0 to %a0 until %a0 == %a1 */
235L1:
236 movel #0, %a0@+
237 cmpal %a0, %a1
238 bhi L1
239
240load_quicc:
241 move.l #_dprbase, _quicc_base
242
243store_ram_size:
244 /* Set ram size information */
245 move.l #_sdata, _rambase
246 move.l #__bss_stop, _ramstart
247 move.l #RAMEND, %d0
248 sub.l #0x1000, %d0 /* Reserve 4K for stack space.*/
249 move.l %d0, _ramend /* Different from RAMEND.*/
250
251 pea 0
252 pea env
253 pea %sp@(4)
254 pea 0
255
256 lea init_thread_union, %a2
257 lea 0x2000(%a2), %sp
258
259lp:
260 jsr start_kernel
261
262_exit:
263 jmp _exit
264
265
266 .data
267 .align 4
268env:
269 .long 0
270_quicc_base:
271 .long 0
272_periph_base:
273 .long 0
274_ramvec:
275 .long 0
276_rambase:
277 .long 0
278_ramstart:
279 .long 0
280_ramend:
281 .long 0
282_dprbase:
283 .long 0xffffe000
284
285
286 .text
287
288 /*
289 * These are the exception vectors at boot up, they are copied into RAM
290 * and then overwritten as needed.
291 */
292
293.section ".data..initvect","awx"
294 .long RAMEND /* Reset: Initial Stack Pointer - 0. */
295 .long _start /* Reset: Initial Program Counter - 1. */
296 .long buserr /* Bus Error - 2. */
297 .long trap /* Address Error - 3. */
298 .long trap /* Illegal Instruction - 4. */
299 .long trap /* Divide by zero - 5. */
300 .long trap /* CHK, CHK2 Instructions - 6. */
301 .long trap /* TRAPcc, TRAPV Instructions - 7. */
302 .long trap /* Privilege Violation - 8. */
303 .long trap /* Trace - 9. */
304 .long trap /* Line 1010 Emulator - 10. */
305 .long trap /* Line 1111 Emualtor - 11. */
306 .long trap /* Harware Breakpoint - 12. */
307 .long trap /* (Reserved for Coprocessor Protocol Violation)- 13. */
308 .long trap /* Format Error - 14. */
309 .long trap /* Uninitialized Interrupt - 15. */
310 .long trap /* (Unassigned, Reserver) - 16. */
311 .long trap /* (Unassigned, Reserver) - 17. */
312 .long trap /* (Unassigned, Reserver) - 18. */
313 .long trap /* (Unassigned, Reserver) - 19. */
314 .long trap /* (Unassigned, Reserver) - 20. */
315 .long trap /* (Unassigned, Reserver) - 21. */
316 .long trap /* (Unassigned, Reserver) - 22. */
317 .long trap /* (Unassigned, Reserver) - 23. */
318 .long trap /* Spurious Interrupt - 24. */
319 .long trap /* Level 1 Interrupt Autovector - 25. */
320 .long trap /* Level 2 Interrupt Autovector - 26. */
321 .long trap /* Level 3 Interrupt Autovector - 27. */
322 .long trap /* Level 4 Interrupt Autovector - 28. */
323 .long trap /* Level 5 Interrupt Autovector - 29. */
324 .long trap /* Level 6 Interrupt Autovector - 30. */
325 .long trap /* Level 7 Interrupt Autovector - 31. */
326 .long system_call /* Trap Instruction Vectors 0 - 32. */
327 .long trap /* Trap Instruction Vectors 1 - 33. */
328 .long trap /* Trap Instruction Vectors 2 - 34. */
329 .long trap /* Trap Instruction Vectors 3 - 35. */
330 .long trap /* Trap Instruction Vectors 4 - 36. */
331 .long trap /* Trap Instruction Vectors 5 - 37. */
332 .long trap /* Trap Instruction Vectors 6 - 38. */
333 .long trap /* Trap Instruction Vectors 7 - 39. */
334 .long trap /* Trap Instruction Vectors 8 - 40. */
335 .long trap /* Trap Instruction Vectors 9 - 41. */
336 .long trap /* Trap Instruction Vectors 10 - 42. */
337 .long trap /* Trap Instruction Vectors 11 - 43. */
338 .long trap /* Trap Instruction Vectors 12 - 44. */
339 .long trap /* Trap Instruction Vectors 13 - 45. */
340 .long trap /* Trap Instruction Vectors 14 - 46. */
341 .long trap /* Trap Instruction Vectors 15 - 47. */
342 .long 0 /* (Reserved for Coprocessor) - 48. */
343 .long 0 /* (Reserved for Coprocessor) - 49. */
344 .long 0 /* (Reserved for Coprocessor) - 50. */
345 .long 0 /* (Reserved for Coprocessor) - 51. */
346 .long 0 /* (Reserved for Coprocessor) - 52. */
347 .long 0 /* (Reserved for Coprocessor) - 53. */
348 .long 0 /* (Reserved for Coprocessor) - 54. */
349 .long 0 /* (Reserved for Coprocessor) - 55. */
350 .long 0 /* (Reserved for Coprocessor) - 56. */
351 .long 0 /* (Reserved for Coprocessor) - 57. */
352 .long 0 /* (Reserved for Coprocessor) - 58. */
353 .long 0 /* (Unassigned, Reserved) - 59. */
354 .long 0 /* (Unassigned, Reserved) - 60. */
355 .long 0 /* (Unassigned, Reserved) - 61. */
356 .long 0 /* (Unassigned, Reserved) - 62. */
357 .long 0 /* (Unassigned, Reserved) - 63. */
358 /* The assignment of these vectors to the CPM is */
359 /* dependent on the configuration of the CPM vba */
360 /* fields. */
361 .long 0 /* (User-Defined Vectors 1) CPM Error - 64. */
362 .long 0 /* (User-Defined Vectors 2) CPM Parallel IO PC11- 65. */
363 .long 0 /* (User-Defined Vectors 3) CPM Parallel IO PC10- 66. */
364 .long 0 /* (User-Defined Vectors 4) CPM SMC2 / PIP - 67. */
365 .long 0 /* (User-Defined Vectors 5) CPM SMC1 - 68. */
366 .long 0 /* (User-Defined Vectors 6) CPM SPI - 69. */
367 .long 0 /* (User-Defined Vectors 7) CPM Parallel IO PC9 - 70. */
368 .long 0 /* (User-Defined Vectors 8) CPM Timer 4 - 71. */
369 .long 0 /* (User-Defined Vectors 9) CPM Reserved - 72. */
370 .long 0 /* (User-Defined Vectors 10) CPM Parallel IO PC8- 73. */
371 .long 0 /* (User-Defined Vectors 11) CPM Parallel IO PC7- 74. */
372 .long 0 /* (User-Defined Vectors 12) CPM Parallel IO PC6- 75. */
373 .long 0 /* (User-Defined Vectors 13) CPM Timer 3 - 76. */
374 .long 0 /* (User-Defined Vectors 14) CPM Reserved - 77. */
375 .long 0 /* (User-Defined Vectors 15) CPM Parallel IO PC5- 78. */
376 .long 0 /* (User-Defined Vectors 16) CPM Parallel IO PC4- 79. */
377 .long 0 /* (User-Defined Vectors 17) CPM Reserved - 80. */
378 .long 0 /* (User-Defined Vectors 18) CPM RISC Timer Tbl - 81. */
379 .long 0 /* (User-Defined Vectors 19) CPM Timer 2 - 82. */
380 .long 0 /* (User-Defined Vectors 21) CPM Reserved - 83. */
381 .long 0 /* (User-Defined Vectors 22) CPM IDMA2 - 84. */
382 .long 0 /* (User-Defined Vectors 23) CPM IDMA1 - 85. */
383 .long 0 /* (User-Defined Vectors 24) CPM SDMA Bus Err - 86. */
384 .long 0 /* (User-Defined Vectors 25) CPM Parallel IO PC3- 87. */
385 .long 0 /* (User-Defined Vectors 26) CPM Parallel IO PC2- 88. */
386 .long 0 /* (User-Defined Vectors 27) CPM Timer 1 - 89. */
387 .long 0 /* (User-Defined Vectors 28) CPM Parallel IO PC1- 90. */
388 .long 0 /* (User-Defined Vectors 29) CPM SCC 4 - 91. */
389 .long 0 /* (User-Defined Vectors 30) CPM SCC 3 - 92. */
390 .long 0 /* (User-Defined Vectors 31) CPM SCC 2 - 93. */
391 .long 0 /* (User-Defined Vectors 32) CPM SCC 1 - 94. */
392 .long 0 /* (User-Defined Vectors 33) CPM Parallel IO PC0- 95. */
393 /* I don't think anything uses the vectors after here. */
394 .long 0 /* (User-Defined Vectors 34) - 96. */
395 .long 0,0,0,0,0 /* (User-Defined Vectors 35 - 39). */
396 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 40 - 49). */
397 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 50 - 59). */
398 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 60 - 69). */
399 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 70 - 79). */
400 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 80 - 89). */
401 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 90 - 99). */
402 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 100 - 109). */
403 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 110 - 119). */
404 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 120 - 129). */
405 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 130 - 139). */
406 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 140 - 149). */
407 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 150 - 159). */
408 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 160 - 169). */
409 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 170 - 179). */
410 .long 0,0,0,0,0,0,0,0,0,0 /* (User-Defined Vectors 180 - 189). */
411 .long 0,0,0 /* (User-Defined Vectors 190 - 192). */
412.text
413ignore: rte
diff --git a/arch/m68k/68360/ints.c b/arch/m68k/68360/ints.c
deleted file mode 100644
index 2360fc046681..000000000000
--- a/arch/m68k/68360/ints.c
+++ /dev/null
@@ -1,138 +0,0 @@
1/*
2 * ints.c - first level interrupt handlers
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file COPYING in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (c) 2000 Michael Leslie <mleslie@lineo.com>
9 * Copyright (c) 1996 Roman Zippel
10 * Copyright (c) 1999 D. Jeff Dionne <jeff@uclinux.org>
11 */
12
13#include <linux/types.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/irq.h>
18#include <asm/traps.h>
19#include <asm/machdep.h>
20#include <asm/m68360.h>
21
22/* from quicc/commproc.c: */
23extern QUICC *pquicc;
24extern void cpm_interrupt_init(void);
25
26#define INTERNAL_IRQS (96)
27
28/* assembler routines */
29asmlinkage void system_call(void);
30asmlinkage void buserr(void);
31asmlinkage void trap(void);
32asmlinkage void bad_interrupt(void);
33asmlinkage void inthandler(void);
34
35static void intc_irq_unmask(struct irq_data *d)
36{
37 pquicc->intr_cimr |= (1 << d->irq);
38}
39
40static void intc_irq_mask(struct irq_data *d)
41{
42 pquicc->intr_cimr &= ~(1 << d->irq);
43}
44
45static void intc_irq_ack(struct irq_data *d)
46{
47 pquicc->intr_cisr = (1 << d->irq);
48}
49
50static struct irq_chip intc_irq_chip = {
51 .name = "M68K-INTC",
52 .irq_mask = intc_irq_mask,
53 .irq_unmask = intc_irq_unmask,
54 .irq_ack = intc_irq_ack,
55};
56
57/*
58 * This function should be called during kernel startup to initialize
59 * the vector table.
60 */
61void __init trap_init(void)
62{
63 int vba = (CPM_VECTOR_BASE<<4);
64
65 /* set up the vectors */
66 _ramvec[2] = buserr;
67 _ramvec[3] = trap;
68 _ramvec[4] = trap;
69 _ramvec[5] = trap;
70 _ramvec[6] = trap;
71 _ramvec[7] = trap;
72 _ramvec[8] = trap;
73 _ramvec[9] = trap;
74 _ramvec[10] = trap;
75 _ramvec[11] = trap;
76 _ramvec[12] = trap;
77 _ramvec[13] = trap;
78 _ramvec[14] = trap;
79 _ramvec[15] = trap;
80
81 _ramvec[32] = system_call;
82 _ramvec[33] = trap;
83
84 cpm_interrupt_init();
85
86 /* set up CICR for vector base address and irq level */
87 /* irl = 4, hp = 1f - see MC68360UM p 7-377 */
88 pquicc->intr_cicr = 0x00e49f00 | vba;
89
90 /* CPM interrupt vectors: (p 7-376) */
91 _ramvec[vba+CPMVEC_ERROR] = bad_interrupt; /* Error */
92 _ramvec[vba+CPMVEC_PIO_PC11] = inthandler; /* pio - pc11 */
93 _ramvec[vba+CPMVEC_PIO_PC10] = inthandler; /* pio - pc10 */
94 _ramvec[vba+CPMVEC_SMC2] = inthandler; /* smc2/pip */
95 _ramvec[vba+CPMVEC_SMC1] = inthandler; /* smc1 */
96 _ramvec[vba+CPMVEC_SPI] = inthandler; /* spi */
97 _ramvec[vba+CPMVEC_PIO_PC9] = inthandler; /* pio - pc9 */
98 _ramvec[vba+CPMVEC_TIMER4] = inthandler; /* timer 4 */
99 _ramvec[vba+CPMVEC_RESERVED1] = inthandler; /* reserved */
100 _ramvec[vba+CPMVEC_PIO_PC8] = inthandler; /* pio - pc8 */
101 _ramvec[vba+CPMVEC_PIO_PC7] = inthandler; /* pio - pc7 */
102 _ramvec[vba+CPMVEC_PIO_PC6] = inthandler; /* pio - pc6 */
103 _ramvec[vba+CPMVEC_TIMER3] = inthandler; /* timer 3 */
104 _ramvec[vba+CPMVEC_PIO_PC5] = inthandler; /* pio - pc5 */
105 _ramvec[vba+CPMVEC_PIO_PC4] = inthandler; /* pio - pc4 */
106 _ramvec[vba+CPMVEC_RESERVED2] = inthandler; /* reserved */
107 _ramvec[vba+CPMVEC_RISCTIMER] = inthandler; /* timer table */
108 _ramvec[vba+CPMVEC_TIMER2] = inthandler; /* timer 2 */
109 _ramvec[vba+CPMVEC_RESERVED3] = inthandler; /* reserved */
110 _ramvec[vba+CPMVEC_IDMA2] = inthandler; /* idma 2 */
111 _ramvec[vba+CPMVEC_IDMA1] = inthandler; /* idma 1 */
112 _ramvec[vba+CPMVEC_SDMA_CB_ERR] = inthandler; /* sdma channel bus error */
113 _ramvec[vba+CPMVEC_PIO_PC3] = inthandler; /* pio - pc3 */
114 _ramvec[vba+CPMVEC_PIO_PC2] = inthandler; /* pio - pc2 */
115 /* _ramvec[vba+CPMVEC_TIMER1] = cpm_isr_timer1; */ /* timer 1 */
116 _ramvec[vba+CPMVEC_TIMER1] = inthandler; /* timer 1 */
117 _ramvec[vba+CPMVEC_PIO_PC1] = inthandler; /* pio - pc1 */
118 _ramvec[vba+CPMVEC_SCC4] = inthandler; /* scc 4 */
119 _ramvec[vba+CPMVEC_SCC3] = inthandler; /* scc 3 */
120 _ramvec[vba+CPMVEC_SCC2] = inthandler; /* scc 2 */
121 _ramvec[vba+CPMVEC_SCC1] = inthandler; /* scc 1 */
122 _ramvec[vba+CPMVEC_PIO_PC0] = inthandler; /* pio - pc0 */
123
124
125 /* turn off all CPM interrupts */
126 pquicc->intr_cimr = 0x00000000;
127}
128
129void init_IRQ(void)
130{
131 int i;
132
133 for (i = 0; (i < NR_IRQS); i++) {
134 irq_set_chip(i, &intc_irq_chip);
135 irq_set_handler(i, handle_level_irq);
136 }
137}
138
diff --git a/arch/m68k/Kconfig.cpu b/arch/m68k/Kconfig.cpu
index c496d48a8c8d..0dfcf1281e9c 100644
--- a/arch/m68k/Kconfig.cpu
+++ b/arch/m68k/Kconfig.cpu
@@ -114,13 +114,6 @@ config M68VZ328
114 help 114 help
115 Motorola 68VZ328 processor support. 115 Motorola 68VZ328 processor support.
116 116
117config M68360
118 bool "MC68360"
119 depends on !MMU
120 select MCPU32
121 help
122 Motorola 68360 processor support.
123
124endif # M68KCLASSIC 117endif # M68KCLASSIC
125 118
126if COLDFIRE 119if COLDFIRE
diff --git a/arch/m68k/Kconfig.debug b/arch/m68k/Kconfig.debug
index 64776d7ac199..50a67d08aec4 100644
--- a/arch/m68k/Kconfig.debug
+++ b/arch/m68k/Kconfig.debug
@@ -12,7 +12,7 @@ config BOOTPARAM_STRING
12 12
13config EARLY_PRINTK 13config EARLY_PRINTK
14 bool "Early printk" 14 bool "Early printk"
15 depends on !(SUN3 || M68360 || M68000 || COLDFIRE) 15 depends on !(SUN3 || M68000 || COLDFIRE)
16 help 16 help
17 Write kernel log output directly to a serial port. 17 Write kernel log output directly to a serial port.
18 Where implemented, output goes to the framebuffer as well. 18 Where implemented, output goes to the framebuffer as well.
diff --git a/arch/m68k/Kconfig.machine b/arch/m68k/Kconfig.machine
index 61dc643c0b05..2a5c7abb2896 100644
--- a/arch/m68k/Kconfig.machine
+++ b/arch/m68k/Kconfig.machine
@@ -187,12 +187,6 @@ config MEMORY_RESERVE
187 help 187 help
188 Reserve certain memory regions on 68x328 based boards. 188 Reserve certain memory regions on 68x328 based boards.
189 189
190config UCQUICC
191 bool "Lineo uCquicc board support"
192 depends on M68360
193 help
194 Support for the Lineo uCquicc board.
195
196config ARN5206 190config ARN5206
197 bool "Arnewsh 5206 board support" 191 bool "Arnewsh 5206 board support"
198 depends on M5206 192 depends on M5206
diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile
index 0b29dcfef69f..f0dd9fc84002 100644
--- a/arch/m68k/Makefile
+++ b/arch/m68k/Makefile
@@ -39,7 +39,6 @@ cpuflags-$(CONFIG_M68040) := -m68040
39endif 39endif
40cpuflags-$(CONFIG_M68030) := 40cpuflags-$(CONFIG_M68030) :=
41cpuflags-$(CONFIG_M68020) := 41cpuflags-$(CONFIG_M68020) :=
42cpuflags-$(CONFIG_M68360) := -m68332
43cpuflags-$(CONFIG_M68000) := -m68000 42cpuflags-$(CONFIG_M68000) := -m68000
44cpuflags-$(CONFIG_M5441x) := $(call cc-option,-mcpu=54455,-mcfv4e) 43cpuflags-$(CONFIG_M5441x) := $(call cc-option,-mcpu=54455,-mcfv4e)
45cpuflags-$(CONFIG_M54xx) := $(call cc-option,-mcpu=5475,-m5200) 44cpuflags-$(CONFIG_M54xx) := $(call cc-option,-mcpu=5475,-m5200)
@@ -92,7 +91,6 @@ endif
92# 91#
93head-y := arch/m68k/kernel/head.o 92head-y := arch/m68k/kernel/head.o
94head-$(CONFIG_SUN3) := arch/m68k/kernel/sun3-head.o 93head-$(CONFIG_SUN3) := arch/m68k/kernel/sun3-head.o
95head-$(CONFIG_M68360) := arch/m68k/68360/head.o
96head-$(CONFIG_M68000) := arch/m68k/68000/head.o 94head-$(CONFIG_M68000) := arch/m68k/68000/head.o
97head-$(CONFIG_COLDFIRE) := arch/m68k/coldfire/head.o 95head-$(CONFIG_COLDFIRE) := arch/m68k/coldfire/head.o
98 96
@@ -114,7 +112,6 @@ core-$(CONFIG_NATFEAT) += arch/m68k/emu/
114core-$(CONFIG_M68040) += arch/m68k/fpsp040/ 112core-$(CONFIG_M68040) += arch/m68k/fpsp040/
115core-$(CONFIG_M68060) += arch/m68k/ifpsp060/ 113core-$(CONFIG_M68060) += arch/m68k/ifpsp060/
116core-$(CONFIG_M68KFPU_EMU) += arch/m68k/math-emu/ 114core-$(CONFIG_M68KFPU_EMU) += arch/m68k/math-emu/
117core-$(CONFIG_M68360) += arch/m68k/68360/
118core-$(CONFIG_M68000) += arch/m68k/68000/ 115core-$(CONFIG_M68000) += arch/m68k/68000/
119core-$(CONFIG_COLDFIRE) += arch/m68k/coldfire/ 116core-$(CONFIG_COLDFIRE) += arch/m68k/coldfire/
120 117
diff --git a/arch/m68k/include/asm/commproc.h b/arch/m68k/include/asm/commproc.h
deleted file mode 100644
index f41c96863e98..000000000000
--- a/arch/m68k/include/asm/commproc.h
+++ /dev/null
@@ -1,664 +0,0 @@
1
2/*
3 * 68360 Communication Processor Module.
4 * Copyright (c) 2000 Michael Leslie <mleslie@lineo.com> (mc68360) after:
5 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net> (mpc8xx)
6 *
7 * This file contains structures and information for the communication
8 * processor channels. Some CPM control and status is available
9 * through the 68360 internal memory map. See include/asm/360_immap.h for details.
10 * This file is not a complete map of all of the 360 QUICC's capabilities
11 *
12 * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
13 * bytes of the DP RAM and relocates the I2C parameter area to the
14 * IDMA1 space. The remaining DP RAM is available for buffer descriptors
15 * or other use.
16 */
17#ifndef __CPM_360__
18#define __CPM_360__
19
20
21/* CPM Command register masks: */
22#define CPM_CR_RST ((ushort)0x8000)
23#define CPM_CR_OPCODE ((ushort)0x0f00)
24#define CPM_CR_CHAN ((ushort)0x00f0)
25#define CPM_CR_FLG ((ushort)0x0001)
26
27/* CPM Command set (opcodes): */
28#define CPM_CR_INIT_TRX ((ushort)0x0000)
29#define CPM_CR_INIT_RX ((ushort)0x0001)
30#define CPM_CR_INIT_TX ((ushort)0x0002)
31#define CPM_CR_HUNT_MODE ((ushort)0x0003)
32#define CPM_CR_STOP_TX ((ushort)0x0004)
33#define CPM_CR_GRSTOP_TX ((ushort)0x0005)
34#define CPM_CR_RESTART_TX ((ushort)0x0006)
35#define CPM_CR_CLOSE_RXBD ((ushort)0x0007)
36#define CPM_CR_SET_GADDR ((ushort)0x0008)
37#define CPM_CR_GCI_TIMEOUT ((ushort)0x0009)
38#define CPM_CR_GCI_ABORT ((ushort)0x000a)
39#define CPM_CR_RESET_BCS ((ushort)0x000a)
40
41/* CPM Channel numbers. */
42#define CPM_CR_CH_SCC1 ((ushort)0x0000)
43#define CPM_CR_CH_SCC2 ((ushort)0x0004)
44#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / Timers */
45#define CPM_CR_CH_TMR ((ushort)0x0005)
46#define CPM_CR_CH_SCC3 ((ushort)0x0008)
47#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / IDMA1 */
48#define CPM_CR_CH_IDMA1 ((ushort)0x0009)
49#define CPM_CR_CH_SCC4 ((ushort)0x000c)
50#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / IDMA2 */
51#define CPM_CR_CH_IDMA2 ((ushort)0x000d)
52
53
54#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4))
55
56#if 1 /* mleslie: I dinna think we have any such restrictions on
57 * DP RAM aboard the 360 board - see the MC68360UM p.3-3 */
58
59/* The dual ported RAM is multi-functional. Some areas can be (and are
60 * being) used for microcode. There is an area that can only be used
61 * as data ram for buffer descriptors, which is all we use right now.
62 * Currently the first 512 and last 256 bytes are used for microcode.
63 */
64/* mleslie: The uCquicc board is using no extra microcode in DPRAM */
65#define CPM_DATAONLY_BASE ((uint)0x0000)
66#define CPM_DATAONLY_SIZE ((uint)0x0800)
67#define CPM_DP_NOSPACE ((uint)0x7fffffff)
68
69#endif
70
71
72/* Export the base address of the communication processor registers
73 * and dual port ram. */
74/* extern cpm360_t *cpmp; */ /* Pointer to comm processor */
75extern QUICC *pquicc;
76uint m360_cpm_dpalloc(uint size);
77/* void *m360_cpm_hostalloc(uint size); */
78void m360_cpm_setbrg(uint brg, uint rate);
79
80#if 0 /* use QUICC_BD declared in include/asm/m68360_quicc.h */
81/* Buffer descriptors used by many of the CPM protocols. */
82typedef struct cpm_buf_desc {
83 ushort cbd_sc; /* Status and Control */
84 ushort cbd_datlen; /* Data length in buffer */
85 uint cbd_bufaddr; /* Buffer address in host memory */
86} cbd_t;
87#endif
88
89
90/* rx bd status/control bits */
91#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
92#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor in table */
93#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
94#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame OR control char */
95
96#define BD_SC_FIRST ((ushort)0x0400) /* 1st buffer in an HDLC frame */
97#define BD_SC_ADDR ((ushort)0x0400) /* 1st byte is a multidrop address */
98
99#define BD_SC_CM ((ushort)0x0200) /* Continuous mode */
100#define BD_SC_ID ((ushort)0x0100) /* Received too many idles */
101
102#define BD_SC_AM ((ushort)0x0080) /* Multidrop address match */
103#define BD_SC_DE ((ushort)0x0080) /* DPLL Error (HDLC) */
104
105#define BD_SC_BR ((ushort)0x0020) /* Break received */
106#define BD_SC_LG ((ushort)0x0020) /* Frame length violation (HDLC) */
107
108#define BD_SC_FR ((ushort)0x0010) /* Framing error */
109#define BD_SC_NO ((ushort)0x0010) /* Nonoctet aligned frame (HDLC) */
110
111#define BD_SC_PR ((ushort)0x0008) /* Parity error */
112#define BD_SC_AB ((ushort)0x0008) /* Received abort Sequence (HDLC) */
113
114#define BD_SC_OV ((ushort)0x0002) /* Overrun */
115#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */
116
117/* tx bd status/control bits (as differ from rx bd) */
118#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
119#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
120#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
121#define BD_SC_UN ((ushort)0x0002) /* Underrun */
122
123
124
125
126/* Parameter RAM offsets. */
127
128
129
130/* In 2.4 ppc, the PROFF_S?C? are used as byte offsets into DPRAM.
131 * In 2.0, we use a more structured C struct map of DPRAM, and so
132 * instead, we need only a parameter ram `slot' */
133
134#define PRSLOT_SCC1 0
135#define PRSLOT_SCC2 1
136#define PRSLOT_SCC3 2
137#define PRSLOT_SMC1 2
138#define PRSLOT_SCC4 3
139#define PRSLOT_SMC2 3
140
141
142/* #define PROFF_SCC1 ((uint)0x0000) */
143/* #define PROFF_SCC2 ((uint)0x0100) */
144/* #define PROFF_SCC3 ((uint)0x0200) */
145/* #define PROFF_SMC1 ((uint)0x0280) */
146/* #define PROFF_SCC4 ((uint)0x0300) */
147/* #define PROFF_SMC2 ((uint)0x0380) */
148
149
150/* Define enough so I can at least use the serial port as a UART.
151 * The MBX uses SMC1 as the host serial port.
152 */
153typedef struct smc_uart {
154 ushort smc_rbase; /* Rx Buffer descriptor base address */
155 ushort smc_tbase; /* Tx Buffer descriptor base address */
156 u_char smc_rfcr; /* Rx function code */
157 u_char smc_tfcr; /* Tx function code */
158 ushort smc_mrblr; /* Max receive buffer length */
159 uint smc_rstate; /* Internal */
160 uint smc_idp; /* Internal */
161 ushort smc_rbptr; /* Internal */
162 ushort smc_ibc; /* Internal */
163 uint smc_rxtmp; /* Internal */
164 uint smc_tstate; /* Internal */
165 uint smc_tdp; /* Internal */
166 ushort smc_tbptr; /* Internal */
167 ushort smc_tbc; /* Internal */
168 uint smc_txtmp; /* Internal */
169 ushort smc_maxidl; /* Maximum idle characters */
170 ushort smc_tmpidl; /* Temporary idle counter */
171 ushort smc_brklen; /* Last received break length */
172 ushort smc_brkec; /* rcv'd break condition counter */
173 ushort smc_brkcr; /* xmt break count register */
174 ushort smc_rmask; /* Temporary bit mask */
175} smc_uart_t;
176
177/* Function code bits.
178*/
179#define SMC_EB ((u_char)0x10) /* Set big endian byte order */
180
181/* SMC uart mode register.
182*/
183#define SMCMR_REN ((ushort)0x0001)
184#define SMCMR_TEN ((ushort)0x0002)
185#define SMCMR_DM ((ushort)0x000c)
186#define SMCMR_SM_GCI ((ushort)0x0000)
187#define SMCMR_SM_UART ((ushort)0x0020)
188#define SMCMR_SM_TRANS ((ushort)0x0030)
189#define SMCMR_SM_MASK ((ushort)0x0030)
190#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
191#define SMCMR_REVD SMCMR_PM_EVEN
192#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
193#define SMCMR_BS SMCMR_PEN
194#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
195#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
196#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
197
198/* SMC2 as Centronics parallel printer. It is half duplex, in that
199 * it can only receive or transmit. The parameter ram values for
200 * each direction are either unique or properly overlap, so we can
201 * include them in one structure.
202 */
203typedef struct smc_centronics {
204 ushort scent_rbase;
205 ushort scent_tbase;
206 u_char scent_cfcr;
207 u_char scent_smask;
208 ushort scent_mrblr;
209 uint scent_rstate;
210 uint scent_r_ptr;
211 ushort scent_rbptr;
212 ushort scent_r_cnt;
213 uint scent_rtemp;
214 uint scent_tstate;
215 uint scent_t_ptr;
216 ushort scent_tbptr;
217 ushort scent_t_cnt;
218 uint scent_ttemp;
219 ushort scent_max_sl;
220 ushort scent_sl_cnt;
221 ushort scent_character1;
222 ushort scent_character2;
223 ushort scent_character3;
224 ushort scent_character4;
225 ushort scent_character5;
226 ushort scent_character6;
227 ushort scent_character7;
228 ushort scent_character8;
229 ushort scent_rccm;
230 ushort scent_rccr;
231} smc_cent_t;
232
233/* Centronics Status Mask Register.
234*/
235#define SMC_CENT_F ((u_char)0x08)
236#define SMC_CENT_PE ((u_char)0x04)
237#define SMC_CENT_S ((u_char)0x02)
238
239/* SMC Event and Mask register.
240*/
241#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
242#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
243#define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */
244#define SMCM_BSY ((unsigned char)0x04)
245#define SMCM_TX ((unsigned char)0x02)
246#define SMCM_RX ((unsigned char)0x01)
247
248/* Baud rate generators.
249*/
250#define CPM_BRG_RST ((uint)0x00020000)
251#define CPM_BRG_EN ((uint)0x00010000)
252#define CPM_BRG_EXTC_INT ((uint)0x00000000)
253#define CPM_BRG_EXTC_CLK2 ((uint)0x00004000)
254#define CPM_BRG_EXTC_CLK6 ((uint)0x00008000)
255#define CPM_BRG_ATB ((uint)0x00002000)
256#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
257#define CPM_BRG_DIV16 ((uint)0x00000001)
258
259/* SCCs.
260*/
261#define SCC_GSMRH_IRP ((uint)0x00040000)
262#define SCC_GSMRH_GDE ((uint)0x00010000)
263#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
264#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
265#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
266#define SCC_GSMRH_REVD ((uint)0x00002000)
267#define SCC_GSMRH_TRX ((uint)0x00001000)
268#define SCC_GSMRH_TTX ((uint)0x00000800)
269#define SCC_GSMRH_CDP ((uint)0x00000400)
270#define SCC_GSMRH_CTSP ((uint)0x00000200)
271#define SCC_GSMRH_CDS ((uint)0x00000100)
272#define SCC_GSMRH_CTSS ((uint)0x00000080)
273#define SCC_GSMRH_TFL ((uint)0x00000040)
274#define SCC_GSMRH_RFW ((uint)0x00000020)
275#define SCC_GSMRH_TXSY ((uint)0x00000010)
276#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
277#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
278#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
279#define SCC_GSMRH_RTSM ((uint)0x00000002)
280#define SCC_GSMRH_RSYN ((uint)0x00000001)
281
282#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
283#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
284#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
285#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
286#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
287#define SCC_GSMRL_TCI ((uint)0x10000000)
288#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
289#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
290#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
291#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
292#define SCC_GSMRL_RINV ((uint)0x02000000)
293#define SCC_GSMRL_TINV ((uint)0x01000000)
294#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
295#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
296#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
297#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
298#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
299#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
300#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
301#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
302#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
303#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
304#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
305#define SCC_GSMRL_TEND ((uint)0x00040000)
306#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
307#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
308#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
309#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
310#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
311#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
312#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
313#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
314#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
315#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
316#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
317#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
318#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
319#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
320#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
321#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
322#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
323#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
324#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
325#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
326#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
327#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
328#define SCC_GSMRL_ENR ((uint)0x00000020)
329#define SCC_GSMRL_ENT ((uint)0x00000010)
330#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
331#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
332#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
333#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
334#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
335#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
336#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
337#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
338#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
339#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
340
341#define SCC_TODR_TOD ((ushort)0x8000)
342
343/* SCC Event and Mask register.
344*/
345#define SCCM_TXE ((unsigned char)0x10)
346#define SCCM_BSY ((unsigned char)0x04)
347#define SCCM_TX ((unsigned char)0x02)
348#define SCCM_RX ((unsigned char)0x01)
349
350typedef struct scc_param {
351 ushort scc_rbase; /* Rx Buffer descriptor base address */
352 ushort scc_tbase; /* Tx Buffer descriptor base address */
353 u_char scc_rfcr; /* Rx function code */
354 u_char scc_tfcr; /* Tx function code */
355 ushort scc_mrblr; /* Max receive buffer length */
356 uint scc_rstate; /* Internal */
357 uint scc_idp; /* Internal */
358 ushort scc_rbptr; /* Internal */
359 ushort scc_ibc; /* Internal */
360 uint scc_rxtmp; /* Internal */
361 uint scc_tstate; /* Internal */
362 uint scc_tdp; /* Internal */
363 ushort scc_tbptr; /* Internal */
364 ushort scc_tbc; /* Internal */
365 uint scc_txtmp; /* Internal */
366 uint scc_rcrc; /* Internal */
367 uint scc_tcrc; /* Internal */
368} sccp_t;
369
370
371/* Function code bits.
372 */
373#define SCC_EB ((u_char)0x10) /* Set big endian byte order */
374#define SCC_FC_DMA ((u_char)0x08) /* Set SDMA */
375
376/* CPM Ethernet through SCC1.
377 */
378typedef struct scc_enet {
379 sccp_t sen_genscc;
380 uint sen_cpres; /* Preset CRC */
381 uint sen_cmask; /* Constant mask for CRC */
382 uint sen_crcec; /* CRC Error counter */
383 uint sen_alec; /* alignment error counter */
384 uint sen_disfc; /* discard frame counter */
385 ushort sen_pads; /* Tx short frame pad character */
386 ushort sen_retlim; /* Retry limit threshold */
387 ushort sen_retcnt; /* Retry limit counter */
388 ushort sen_maxflr; /* maximum frame length register */
389 ushort sen_minflr; /* minimum frame length register */
390 ushort sen_maxd1; /* maximum DMA1 length */
391 ushort sen_maxd2; /* maximum DMA2 length */
392 ushort sen_maxd; /* Rx max DMA */
393 ushort sen_dmacnt; /* Rx DMA counter */
394 ushort sen_maxb; /* Max BD byte count */
395 ushort sen_gaddr1; /* Group address filter */
396 ushort sen_gaddr2;
397 ushort sen_gaddr3;
398 ushort sen_gaddr4;
399 uint sen_tbuf0data0; /* Save area 0 - current frame */
400 uint sen_tbuf0data1; /* Save area 1 - current frame */
401 uint sen_tbuf0rba; /* Internal */
402 uint sen_tbuf0crc; /* Internal */
403 ushort sen_tbuf0bcnt; /* Internal */
404 ushort sen_paddrh; /* physical address (MSB) */
405 ushort sen_paddrm;
406 ushort sen_paddrl; /* physical address (LSB) */
407 ushort sen_pper; /* persistence */
408 ushort sen_rfbdptr; /* Rx first BD pointer */
409 ushort sen_tfbdptr; /* Tx first BD pointer */
410 ushort sen_tlbdptr; /* Tx last BD pointer */
411 uint sen_tbuf1data0; /* Save area 0 - current frame */
412 uint sen_tbuf1data1; /* Save area 1 - current frame */
413 uint sen_tbuf1rba; /* Internal */
414 uint sen_tbuf1crc; /* Internal */
415 ushort sen_tbuf1bcnt; /* Internal */
416 ushort sen_txlen; /* Tx Frame length counter */
417 ushort sen_iaddr1; /* Individual address filter */
418 ushort sen_iaddr2;
419 ushort sen_iaddr3;
420 ushort sen_iaddr4;
421 ushort sen_boffcnt; /* Backoff counter */
422
423 /* NOTE: Some versions of the manual have the following items
424 * incorrectly documented. Below is the proper order.
425 */
426 ushort sen_taddrh; /* temp address (MSB) */
427 ushort sen_taddrm;
428 ushort sen_taddrl; /* temp address (LSB) */
429} scc_enet_t;
430
431
432
433#if defined (CONFIG_UCQUICC)
434/* uCquicc has the following signals connected to Ethernet:
435 * 68360 - lxt905
436 * PA0/RXD1 - rxd
437 * PA1/TXD1 - txd
438 * PA8/CLK1 - tclk
439 * PA9/CLK2 - rclk
440 * PC0/!RTS1 - t_en
441 * PC1/!CTS1 - col
442 * PC5/!CD1 - cd
443 */
444#define PA_ENET_RXD PA_RXD1
445#define PA_ENET_TXD PA_TXD1
446#define PA_ENET_TCLK PA_CLK1
447#define PA_ENET_RCLK PA_CLK2
448#define PC_ENET_TENA PC_RTS1
449#define PC_ENET_CLSN PC_CTS1
450#define PC_ENET_RENA PC_CD1
451
452/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
453 * SCC1.
454 */
455#define SICR_ENET_MASK ((uint)0x000000ff)
456#define SICR_ENET_CLKRT ((uint)0x0000002c)
457
458#endif /* config_ucquicc */
459
460
461#ifdef MBX
462/* Bits in parallel I/O port registers that have to be set/cleared
463 * to configure the pins for SCC1 use. The TCLK and RCLK seem unique
464 * to the MBX860 board. Any two of the four available clocks could be
465 * used, and the MPC860 cookbook manual has an example using different
466 * clock pins.
467 */
468#define PA_ENET_RXD ((ushort)0x0001)
469#define PA_ENET_TXD ((ushort)0x0002)
470#define PA_ENET_TCLK ((ushort)0x0200)
471#define PA_ENET_RCLK ((ushort)0x0800)
472#define PC_ENET_TENA ((ushort)0x0001)
473#define PC_ENET_CLSN ((ushort)0x0010)
474#define PC_ENET_RENA ((ushort)0x0020)
475
476/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
477 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
478 */
479#define SICR_ENET_MASK ((uint)0x000000ff)
480#define SICR_ENET_CLKRT ((uint)0x0000003d)
481#endif
482
483/* SCC Event register as used by Ethernet.
484*/
485#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
486#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
487#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
488#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
489#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
490#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
491
492/* SCC Mode Register (PMSR) as used by Ethernet.
493*/
494#define SCC_PMSR_HBC ((ushort)0x8000) /* Enable heartbeat */
495#define SCC_PMSR_FC ((ushort)0x4000) /* Force collision */
496#define SCC_PMSR_RSH ((ushort)0x2000) /* Receive short frames */
497#define SCC_PMSR_IAM ((ushort)0x1000) /* Check individual hash */
498#define SCC_PMSR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
499#define SCC_PMSR_PRO ((ushort)0x0200) /* Promiscuous mode */
500#define SCC_PMSR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
501#define SCC_PMSR_SBT ((ushort)0x0080) /* Special backoff timer */
502#define SCC_PMSR_LPB ((ushort)0x0040) /* Set Loopback mode */
503#define SCC_PMSR_SIP ((ushort)0x0020) /* Sample Input Pins */
504#define SCC_PMSR_LCW ((ushort)0x0010) /* Late collision window */
505#define SCC_PMSR_NIB22 ((ushort)0x000a) /* Start frame search */
506#define SCC_PMSR_FDE ((ushort)0x0001) /* Full duplex enable */
507
508/* Buffer descriptor control/status used by Ethernet receive.
509*/
510#define BD_ENET_RX_EMPTY ((ushort)0x8000)
511#define BD_ENET_RX_WRAP ((ushort)0x2000)
512#define BD_ENET_RX_INTR ((ushort)0x1000)
513#define BD_ENET_RX_LAST ((ushort)0x0800)
514#define BD_ENET_RX_FIRST ((ushort)0x0400)
515#define BD_ENET_RX_MISS ((ushort)0x0100)
516#define BD_ENET_RX_LG ((ushort)0x0020)
517#define BD_ENET_RX_NO ((ushort)0x0010)
518#define BD_ENET_RX_SH ((ushort)0x0008)
519#define BD_ENET_RX_CR ((ushort)0x0004)
520#define BD_ENET_RX_OV ((ushort)0x0002)
521#define BD_ENET_RX_CL ((ushort)0x0001)
522#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
523
524/* Buffer descriptor control/status used by Ethernet transmit.
525*/
526#define BD_ENET_TX_READY ((ushort)0x8000)
527#define BD_ENET_TX_PAD ((ushort)0x4000)
528#define BD_ENET_TX_WRAP ((ushort)0x2000)
529#define BD_ENET_TX_INTR ((ushort)0x1000)
530#define BD_ENET_TX_LAST ((ushort)0x0800)
531#define BD_ENET_TX_TC ((ushort)0x0400)
532#define BD_ENET_TX_DEF ((ushort)0x0200)
533#define BD_ENET_TX_HB ((ushort)0x0100)
534#define BD_ENET_TX_LC ((ushort)0x0080)
535#define BD_ENET_TX_RL ((ushort)0x0040)
536#define BD_ENET_TX_RCMASK ((ushort)0x003c)
537#define BD_ENET_TX_UN ((ushort)0x0002)
538#define BD_ENET_TX_CSL ((ushort)0x0001)
539#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
540
541/* SCC as UART
542*/
543typedef struct scc_uart {
544 sccp_t scc_genscc;
545 uint scc_res1; /* Reserved */
546 uint scc_res2; /* Reserved */
547 ushort scc_maxidl; /* Maximum idle chars */
548 ushort scc_idlc; /* temp idle counter */
549 ushort scc_brkcr; /* Break count register */
550 ushort scc_parec; /* receive parity error counter */
551 ushort scc_frmec; /* receive framing error counter */
552 ushort scc_nosec; /* receive noise counter */
553 ushort scc_brkec; /* receive break condition counter */
554 ushort scc_brkln; /* last received break length */
555 ushort scc_uaddr1; /* UART address character 1 */
556 ushort scc_uaddr2; /* UART address character 2 */
557 ushort scc_rtemp; /* Temp storage */
558 ushort scc_toseq; /* Transmit out of sequence char */
559 ushort scc_char1; /* control character 1 */
560 ushort scc_char2; /* control character 2 */
561 ushort scc_char3; /* control character 3 */
562 ushort scc_char4; /* control character 4 */
563 ushort scc_char5; /* control character 5 */
564 ushort scc_char6; /* control character 6 */
565 ushort scc_char7; /* control character 7 */
566 ushort scc_char8; /* control character 8 */
567 ushort scc_rccm; /* receive control character mask */
568 ushort scc_rccr; /* receive control character register */
569 ushort scc_rlbc; /* receive last break character */
570} scc_uart_t;
571
572/* SCC Event and Mask registers when it is used as a UART.
573*/
574#define UART_SCCM_GLR ((ushort)0x1000)
575#define UART_SCCM_GLT ((ushort)0x0800)
576#define UART_SCCM_AB ((ushort)0x0200)
577#define UART_SCCM_IDL ((ushort)0x0100)
578#define UART_SCCM_GRA ((ushort)0x0080)
579#define UART_SCCM_BRKE ((ushort)0x0040)
580#define UART_SCCM_BRKS ((ushort)0x0020)
581#define UART_SCCM_CCR ((ushort)0x0008)
582#define UART_SCCM_BSY ((ushort)0x0004)
583#define UART_SCCM_TX ((ushort)0x0002)
584#define UART_SCCM_RX ((ushort)0x0001)
585
586/* The SCC PMSR when used as a UART.
587*/
588#define SCU_PMSR_FLC ((ushort)0x8000)
589#define SCU_PMSR_SL ((ushort)0x4000)
590#define SCU_PMSR_CL ((ushort)0x3000)
591#define SCU_PMSR_UM ((ushort)0x0c00)
592#define SCU_PMSR_FRZ ((ushort)0x0200)
593#define SCU_PMSR_RZS ((ushort)0x0100)
594#define SCU_PMSR_SYN ((ushort)0x0080)
595#define SCU_PMSR_DRT ((ushort)0x0040)
596#define SCU_PMSR_PEN ((ushort)0x0010)
597#define SCU_PMSR_RPM ((ushort)0x000c)
598#define SCU_PMSR_REVP ((ushort)0x0008)
599#define SCU_PMSR_TPM ((ushort)0x0003)
600#define SCU_PMSR_TEVP ((ushort)0x0003)
601
602/* CPM Transparent mode SCC.
603 */
604typedef struct scc_trans {
605 sccp_t st_genscc;
606 uint st_cpres; /* Preset CRC */
607 uint st_cmask; /* Constant mask for CRC */
608} scc_trans_t;
609
610#define BD_SCC_TX_LAST ((ushort)0x0800)
611
612
613
614/* CPM interrupts. There are nearly 32 interrupts generated by CPM
615 * channels or devices. All of these are presented to the PPC core
616 * as a single interrupt. The CPM interrupt handler dispatches its
617 * own handlers, in a similar fashion to the PPC core handler. We
618 * use the table as defined in the manuals (i.e. no special high
619 * priority and SCC1 == SCCa, etc...).
620 */
621/* #define CPMVEC_NR 32 */
622/* #define CPMVEC_PIO_PC15 ((ushort)0x1f) */
623/* #define CPMVEC_SCC1 ((ushort)0x1e) */
624/* #define CPMVEC_SCC2 ((ushort)0x1d) */
625/* #define CPMVEC_SCC3 ((ushort)0x1c) */
626/* #define CPMVEC_SCC4 ((ushort)0x1b) */
627/* #define CPMVEC_PIO_PC14 ((ushort)0x1a) */
628/* #define CPMVEC_TIMER1 ((ushort)0x19) */
629/* #define CPMVEC_PIO_PC13 ((ushort)0x18) */
630/* #define CPMVEC_PIO_PC12 ((ushort)0x17) */
631/* #define CPMVEC_SDMA_CB_ERR ((ushort)0x16) */
632/* #define CPMVEC_IDMA1 ((ushort)0x15) */
633/* #define CPMVEC_IDMA2 ((ushort)0x14) */
634/* #define CPMVEC_TIMER2 ((ushort)0x12) */
635/* #define CPMVEC_RISCTIMER ((ushort)0x11) */
636/* #define CPMVEC_I2C ((ushort)0x10) */
637/* #define CPMVEC_PIO_PC11 ((ushort)0x0f) */
638/* #define CPMVEC_PIO_PC10 ((ushort)0x0e) */
639/* #define CPMVEC_TIMER3 ((ushort)0x0c) */
640/* #define CPMVEC_PIO_PC9 ((ushort)0x0b) */
641/* #define CPMVEC_PIO_PC8 ((ushort)0x0a) */
642/* #define CPMVEC_PIO_PC7 ((ushort)0x09) */
643/* #define CPMVEC_TIMER4 ((ushort)0x07) */
644/* #define CPMVEC_PIO_PC6 ((ushort)0x06) */
645/* #define CPMVEC_SPI ((ushort)0x05) */
646/* #define CPMVEC_SMC1 ((ushort)0x04) */
647/* #define CPMVEC_SMC2 ((ushort)0x03) */
648/* #define CPMVEC_PIO_PC5 ((ushort)0x02) */
649/* #define CPMVEC_PIO_PC4 ((ushort)0x01) */
650/* #define CPMVEC_ERROR ((ushort)0x00) */
651
652extern void cpm_install_handler(int vec, irq_handler_t handler, void *dev_id);
653
654/* CPM interrupt configuration vector.
655*/
656#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */
657#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
658#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
659#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
660#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */
661#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
662#define CICR_IEN ((uint)0x00000080) /* Int. enable */
663#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
664#endif /* __CPM_360__ */
diff --git a/arch/m68k/include/asm/m68360.h b/arch/m68k/include/asm/m68360.h
deleted file mode 100644
index 4664180a3ab3..000000000000
--- a/arch/m68k/include/asm/m68360.h
+++ /dev/null
@@ -1,13 +0,0 @@
1#include <asm/m68360_regs.h>
2#include <asm/m68360_pram.h>
3#include <asm/m68360_quicc.h>
4#include <asm/m68360_enet.h>
5
6#ifdef CONFIG_M68360
7
8#define CPM_INTERRUPT 4
9
10/* see MC68360 User's Manual, p. 7-377 */
11#define CPM_VECTOR_BASE 0x04 /* 3 MSbits of CPM vector */
12
13#endif /* CONFIG_M68360 */
diff --git a/arch/m68k/include/asm/m68360_enet.h b/arch/m68k/include/asm/m68360_enet.h
deleted file mode 100644
index 4d04037c78a2..000000000000
--- a/arch/m68k/include/asm/m68360_enet.h
+++ /dev/null
@@ -1,177 +0,0 @@
1/***********************************
2 * $Id: m68360_enet.h,v 1.1 2002/03/02 15:01:07 gerg Exp $
3 ***********************************
4 *
5 ***************************************
6 * Definitions for the ETHERNET controllers
7 ***************************************
8 */
9
10#ifndef __ETHER_H
11#define __ETHER_H
12
13#include <asm/quicc_simple.h>
14
15/*
16 * transmit BD's
17 */
18#define T_R 0x8000 /* ready bit */
19#define E_T_PAD 0x4000 /* short frame padding */
20#define T_W 0x2000 /* wrap bit */
21#define T_I 0x1000 /* interrupt on completion */
22#define T_L 0x0800 /* last in frame */
23#define T_TC 0x0400 /* transmit CRC (when last) */
24
25#define T_DEF 0x0200 /* defer indication */
26#define T_HB 0x0100 /* heartbeat */
27#define T_LC 0x0080 /* error: late collision */
28#define T_RL 0x0040 /* error: retransmission limit */
29#define T_RC 0x003c /* retry count */
30#define T_UN 0x0002 /* error: underrun */
31#define T_CSL 0x0001 /* carier sense lost */
32#define T_ERROR (T_HB | T_LC | T_RL | T_UN | T_CSL)
33
34/*
35 * receive BD's
36 */
37#define R_E 0x8000 /* buffer empty */
38#define R_W 0x2000 /* wrap bit */
39#define R_I 0x1000 /* interrupt on reception */
40#define R_L 0x0800 /* last BD in frame */
41#define R_F 0x0400 /* first BD in frame */
42#define R_M 0x0100 /* received because of promisc. mode */
43
44#define R_LG 0x0020 /* frame too long */
45#define R_NO 0x0010 /* non-octet aligned */
46#define R_SH 0x0008 /* short frame */
47#define R_CR 0x0004 /* receive CRC error */
48#define R_OV 0x0002 /* receive overrun */
49#define R_CL 0x0001 /* collision */
50#define ETHER_R_ERROR (R_LG | R_NO | R_SH | R_CR | R_OV | R_CL)
51
52
53/*
54 * ethernet interrupts
55 */
56#define ETHERNET_GRA 0x0080 /* graceful stop complete */
57#define ETHERNET_TXE 0x0010 /* transmit error */
58#define ETHERNET_RXF 0x0008 /* receive frame */
59#define ETHERNET_BSY 0x0004 /* busy condition */
60#define ETHERNET_TXB 0x0002 /* transmit buffer */
61#define ETHERNET_RXB 0x0001 /* receive buffer */
62
63/*
64 * ethernet protocol specific mode register (PSMR)
65 */
66#define ETHER_HBC 0x8000 /* heartbeat checking */
67#define ETHER_FC 0x4000 /* force collision */
68#define ETHER_RSH 0x2000 /* receive short frames */
69#define ETHER_IAM 0x1000 /* individual address mode */
70#define ETHER_CRC_32 (0x2<<10) /* Enable CRC */
71#define ETHER_PRO 0x0200 /* promiscuous */
72#define ETHER_BRO 0x0100 /* broadcast address */
73#define ETHER_SBT 0x0080 /* stop backoff timer */
74#define ETHER_LPB 0x0040 /* Loop Back Mode */
75#define ETHER_SIP 0x0020 /* sample input pins */
76#define ETHER_LCW 0x0010 /* late collision window */
77#define ETHER_NIB_13 (0x0<<1) /* # of ignored bits 13 */
78#define ETHER_NIB_14 (0x1<<1) /* # of ignored bits 14 */
79#define ETHER_NIB_15 (0x2<<1) /* # of ignored bits 15 */
80#define ETHER_NIB_16 (0x3<<1) /* # of ignored bits 16 */
81#define ETHER_NIB_21 (0x4<<1) /* # of ignored bits 21 */
82#define ETHER_NIB_22 (0x5<<1) /* # of ignored bits 22 */
83#define ETHER_NIB_23 (0x6<<1) /* # of ignored bits 23 */
84#define ETHER_NIB_24 (0x7<<1) /* # of ignored bits 24 */
85
86/*
87 * ethernet specific parameters
88 */
89#define CRC_WORD 4 /* Length in bytes of CRC */
90#define C_PRES 0xffffffff /* preform 32 bit CRC */
91#define C_MASK 0xdebb20e3 /* comply with 32 bit CRC */
92#define CRCEC 0x00000000
93#define ALEC 0x00000000
94#define DISFC 0x00000000
95#define PADS 0x00000000
96#define RET_LIM 0x000f /* retry 15 times to send a frame before interrupt */
97#define ETH_MFLR 0x05ee /* 1518 max frame size */
98#define MINFLR 0x0040 /* Minimum frame size 64 */
99#define MAXD1 0x05ee /* Max dma count 1518 */
100#define MAXD2 0x05ee
101#define GADDR1 0x00000000 /* Clear group address */
102#define GADDR2 0x00000000
103#define GADDR3 0x00000000
104#define GADDR4 0x00000000
105#define P_PER 0x00000000 /*not used */
106#define IADDR1 0x00000000 /* Individual hash table not used */
107#define IADDR2 0x00000000
108#define IADDR3 0x00000000
109#define IADDR4 0x00000000
110#define TADDR_H 0x00000000 /* clear this regs */
111#define TADDR_M 0x00000000
112#define TADDR_L 0x00000000
113
114/* SCC Parameter Ram */
115#define RFCR 0x18 /* normal operation */
116#define TFCR 0x18 /* normal operation */
117#define E_MRBLR 1518 /* Max ethernet frame length */
118
119/*
120 * ethernet specific structure
121 */
122typedef union {
123 unsigned char b[6];
124 struct {
125 unsigned short high;
126 unsigned short middl;
127 unsigned short low;
128 } w;
129} ETHER_ADDR;
130
131typedef struct {
132 int max_frame_length;
133 int promisc_mode;
134 int reject_broadcast;
135 ETHER_ADDR phys_adr;
136} ETHER_SPECIFIC;
137
138typedef struct {
139 ETHER_ADDR dst_addr;
140 ETHER_ADDR src_addr;
141 unsigned short type_or_len;
142 unsigned char data[1];
143} ETHER_FRAME;
144
145#define MAX_DATALEN 1500
146typedef struct {
147 ETHER_ADDR dst_addr;
148 ETHER_ADDR src_addr;
149 unsigned short type_or_len;
150 unsigned char data[MAX_DATALEN];
151 unsigned char fcs[CRC_WORD];
152} ETHER_MAX_FRAME;
153
154
155/*
156 * Internal ethernet function prototypes
157 */
158void ether_interrupt(int scc_num);
159/* mleslie: debug */
160/* static void ethernet_rx_internal(int scc_num); */
161/* static void ethernet_tx_internal(int scc_num); */
162
163/*
164 * User callable routines prototypes (ethernet specific)
165 */
166void ethernet_init(int scc_number,
167 alloc_routine *alloc_buffer,
168 free_routine *free_buffer,
169 store_rx_buffer_routine *store_rx_buffer,
170 handle_tx_error_routine *handle_tx_error,
171 handle_rx_error_routine *handle_rx_error,
172 handle_lost_error_routine *handle_lost_error,
173 ETHER_SPECIFIC *ether_spec);
174int ethernet_tx(int scc_number, void *buf, int length);
175
176#endif
177
diff --git a/arch/m68k/include/asm/m68360_pram.h b/arch/m68k/include/asm/m68360_pram.h
deleted file mode 100644
index c0cbd96f09bc..000000000000
--- a/arch/m68k/include/asm/m68360_pram.h
+++ /dev/null
@@ -1,431 +0,0 @@
1/***********************************
2 * $Id: m68360_pram.h,v 1.1 2002/03/02 15:01:07 gerg Exp $
3 ***********************************
4 *
5 ***************************************
6 * Definitions of the parameter area RAM.
7 * Note that different structures are overlaid
8 * at the same offsets for the different modes
9 * of operation.
10 ***************************************
11 */
12
13#ifndef __PRAM_H
14#define __PRAM_H
15
16/* Time slot assignment table */
17#define VALID_SLOT 0x8000
18#define WRAP_SLOT 0x4000
19
20/*****************************************************************
21 Global Multichannel parameter RAM
22*****************************************************************/
23struct global_multi_pram {
24 /*
25 * Global Multichannel parameter RAM
26 */
27 unsigned long mcbase; /* Multichannel Base pointer */
28 unsigned short qmcstate; /* Multichannel Controller state */
29 unsigned short mrblr; /* Maximum Receive Buffer Length */
30 unsigned short tx_s_ptr; /* TSTATx Pointer */
31 unsigned short rxptr; /* Current Time slot entry in TSATRx */
32 unsigned short grfthr; /* Global Receive frame threshold */
33 unsigned short grfcnt; /* Global Receive Frame Count */
34 unsigned long intbase; /* Multichannel Base address */
35 unsigned long iintptr; /* Pointer to interrupt queue */
36 unsigned short rx_s_ptr; /* TSTARx Pointer */
37
38 unsigned short txptr; /* Current Time slot entry in TSATTx */
39 unsigned long c_mask32; /* CRC Constant (debb20e3) */
40 unsigned short tsatrx[32]; /* Time Slot Assignment Table Rx */
41 unsigned short tsattx[32]; /* Time Slot Assignment Table Tx */
42 unsigned short c_mask16; /* CRC Constant (f0b8) */
43};
44
45/*****************************************************************
46 Quicc32 HDLC parameter RAM
47*****************************************************************/
48struct quicc32_pram {
49
50 unsigned short tbase; /* Tx Buffer Descriptors Base Address */
51 unsigned short chamr; /* Channel Mode Register */
52 unsigned long tstate; /* Tx Internal State */
53 unsigned long txintr; /* Tx Internal Data Pointer */
54 unsigned short tbptr; /* Tx Buffer Descriptor Pointer */
55 unsigned short txcntr; /* Tx Internal Byte Count */
56 unsigned long tupack; /* (Tx Temp) */
57 unsigned long zistate; /* Zero Insertion machine state */
58 unsigned long tcrc; /* Temp Transmit CRC */
59 unsigned short intmask; /* Channel's interrupt mask flags */
60 unsigned short bdflags;
61 unsigned short rbase; /* Rx Buffer Descriptors Base Address */
62 unsigned short mflr; /* Max Frame Length Register */
63 unsigned long rstate; /* Rx Internal State */
64 unsigned long rxintr; /* Rx Internal Data Pointer */
65 unsigned short rbptr; /* Rx Buffer Descriptor Pointer */
66 unsigned short rxbyc; /* Rx Internal Byte Count */
67 unsigned long rpack; /* (Rx Temp) */
68 unsigned long zdstate; /* Zero Deletion machine state */
69 unsigned long rcrc; /* Temp Transmit CRC */
70 unsigned short maxc; /* Max_length counter */
71 unsigned short tmp_mb; /* Temp */
72};
73
74
75/*****************************************************************
76 HDLC parameter RAM
77*****************************************************************/
78
79struct hdlc_pram {
80 /*
81 * SCC parameter RAM
82 */
83 unsigned short rbase; /* RX BD base address */
84 unsigned short tbase; /* TX BD base address */
85 unsigned char rfcr; /* Rx function code */
86 unsigned char tfcr; /* Tx function code */
87 unsigned short mrblr; /* Rx buffer length */
88 unsigned long rstate; /* Rx internal state */
89 unsigned long rptr; /* Rx internal data pointer */
90 unsigned short rbptr; /* rb BD Pointer */
91 unsigned short rcount; /* Rx internal byte count */
92 unsigned long rtemp; /* Rx temp */
93 unsigned long tstate; /* Tx internal state */
94 unsigned long tptr; /* Tx internal data pointer */
95 unsigned short tbptr; /* Tx BD pointer */
96 unsigned short tcount; /* Tx byte count */
97 unsigned long ttemp; /* Tx temp */
98 unsigned long rcrc; /* temp receive CRC */
99 unsigned long tcrc; /* temp transmit CRC */
100
101 /*
102 * HDLC specific parameter RAM
103 */
104 unsigned char RESERVED1[4]; /* Reserved area */
105 unsigned long c_mask; /* CRC constant */
106 unsigned long c_pres; /* CRC preset */
107 unsigned short disfc; /* discarded frame counter */
108 unsigned short crcec; /* CRC error counter */
109 unsigned short abtsc; /* abort sequence counter */
110 unsigned short nmarc; /* nonmatching address rx cnt */
111 unsigned short retrc; /* frame retransmission cnt */
112 unsigned short mflr; /* maximum frame length reg */
113 unsigned short max_cnt; /* maximum length counter */
114 unsigned short rfthr; /* received frames threshold */
115 unsigned short rfcnt; /* received frames count */
116 unsigned short hmask; /* user defined frm addr mask */
117 unsigned short haddr1; /* user defined frm address 1 */
118 unsigned short haddr2; /* user defined frm address 2 */
119 unsigned short haddr3; /* user defined frm address 3 */
120 unsigned short haddr4; /* user defined frm address 4 */
121 unsigned short tmp; /* temp */
122 unsigned short tmp_mb; /* temp */
123};
124
125
126
127/*****************************************************************
128 UART parameter RAM
129*****************************************************************/
130
131/*
132 * bits in uart control characters table
133 */
134#define CC_INVALID 0x8000 /* control character is valid */
135#define CC_REJ 0x4000 /* don't store char in buffer */
136#define CC_CHAR 0x00ff /* control character */
137
138/* UART */
139struct uart_pram {
140 /*
141 * SCC parameter RAM
142 */
143 unsigned short rbase; /* RX BD base address */
144 unsigned short tbase; /* TX BD base address */
145 unsigned char rfcr; /* Rx function code */
146 unsigned char tfcr; /* Tx function code */
147 unsigned short mrblr; /* Rx buffer length */
148 unsigned long rstate; /* Rx internal state */
149 unsigned long rptr; /* Rx internal data pointer */
150 unsigned short rbptr; /* rb BD Pointer */
151 unsigned short rcount; /* Rx internal byte count */
152 unsigned long rx_temp; /* Rx temp */
153 unsigned long tstate; /* Tx internal state */
154 unsigned long tptr; /* Tx internal data pointer */
155 unsigned short tbptr; /* Tx BD pointer */
156 unsigned short tcount; /* Tx byte count */
157 unsigned long ttemp; /* Tx temp */
158 unsigned long rcrc; /* temp receive CRC */
159 unsigned long tcrc; /* temp transmit CRC */
160
161 /*
162 * UART specific parameter RAM
163 */
164 unsigned char RESERVED1[8]; /* Reserved area */
165 unsigned short max_idl; /* maximum idle characters */
166 unsigned short idlc; /* rx idle counter (internal) */
167 unsigned short brkcr; /* break count register */
168
169 unsigned short parec; /* Rx parity error counter */
170 unsigned short frmer; /* Rx framing error counter */
171 unsigned short nosec; /* Rx noise counter */
172 unsigned short brkec; /* Rx break character counter */
173 unsigned short brkln; /* Receive break length */
174
175 unsigned short uaddr1; /* address character 1 */
176 unsigned short uaddr2; /* address character 2 */
177 unsigned short rtemp; /* temp storage */
178 unsigned short toseq; /* Tx out of sequence char */
179 unsigned short cc[8]; /* Rx control characters */
180 unsigned short rccm; /* Rx control char mask */
181 unsigned short rccr; /* Rx control char register */
182 unsigned short rlbc; /* Receive last break char */
183};
184
185
186
187/*****************************************************************
188 BISYNC parameter RAM
189*****************************************************************/
190
191struct bisync_pram {
192 /*
193 * SCC parameter RAM
194 */
195 unsigned short rbase; /* RX BD base address */
196 unsigned short tbase; /* TX BD base address */
197 unsigned char rfcr; /* Rx function code */
198 unsigned char tfcr; /* Tx function code */
199 unsigned short mrblr; /* Rx buffer length */
200 unsigned long rstate; /* Rx internal state */
201 unsigned long rptr; /* Rx internal data pointer */
202 unsigned short rbptr; /* rb BD Pointer */
203 unsigned short rcount; /* Rx internal byte count */
204 unsigned long rtemp; /* Rx temp */
205 unsigned long tstate; /* Tx internal state */
206 unsigned long tptr; /* Tx internal data pointer */
207 unsigned short tbptr; /* Tx BD pointer */
208 unsigned short tcount; /* Tx byte count */
209 unsigned long ttemp; /* Tx temp */
210 unsigned long rcrc; /* temp receive CRC */
211 unsigned long tcrc; /* temp transmit CRC */
212
213 /*
214 * BISYNC specific parameter RAM
215 */
216 unsigned char RESERVED1[4]; /* Reserved area */
217 unsigned long crcc; /* CRC Constant Temp Value */
218 unsigned short prcrc; /* Preset Receiver CRC-16/LRC */
219 unsigned short ptcrc; /* Preset Transmitter CRC-16/LRC */
220 unsigned short parec; /* Receive Parity Error Counter */
221 unsigned short bsync; /* BISYNC SYNC Character */
222 unsigned short bdle; /* BISYNC DLE Character */
223 unsigned short cc[8]; /* Rx control characters */
224 unsigned short rccm; /* Receive Control Character Mask */
225};
226
227/*****************************************************************
228 IOM2 parameter RAM
229 (overlaid on tx bd[5] of SCC channel[2])
230*****************************************************************/
231struct iom2_pram {
232 unsigned short ci_data; /* ci data */
233 unsigned short monitor_data; /* monitor data */
234 unsigned short tstate; /* transmitter state */
235 unsigned short rstate; /* receiver state */
236};
237
238/*****************************************************************
239 SPI/SMC parameter RAM
240 (overlaid on tx bd[6,7] of SCC channel[2])
241*****************************************************************/
242
243#define SPI_R 0x8000 /* Ready bit in BD */
244
245struct spi_pram {
246 unsigned short rbase; /* Rx BD Base Address */
247 unsigned short tbase; /* Tx BD Base Address */
248 unsigned char rfcr; /* Rx function code */
249 unsigned char tfcr; /* Tx function code */
250 unsigned short mrblr; /* Rx buffer length */
251 unsigned long rstate; /* Rx internal state */
252 unsigned long rptr; /* Rx internal data pointer */
253 unsigned short rbptr; /* rb BD Pointer */
254 unsigned short rcount; /* Rx internal byte count */
255 unsigned long rtemp; /* Rx temp */
256 unsigned long tstate; /* Tx internal state */
257 unsigned long tptr; /* Tx internal data pointer */
258 unsigned short tbptr; /* Tx BD pointer */
259 unsigned short tcount; /* Tx byte count */
260 unsigned long ttemp; /* Tx temp */
261};
262
263struct smc_uart_pram {
264 unsigned short rbase; /* Rx BD Base Address */
265 unsigned short tbase; /* Tx BD Base Address */
266 unsigned char rfcr; /* Rx function code */
267 unsigned char tfcr; /* Tx function code */
268 unsigned short mrblr; /* Rx buffer length */
269 unsigned long rstate; /* Rx internal state */
270 unsigned long rptr; /* Rx internal data pointer */
271 unsigned short rbptr; /* rb BD Pointer */
272 unsigned short rcount; /* Rx internal byte count */
273 unsigned long rtemp; /* Rx temp */
274 unsigned long tstate; /* Tx internal state */
275 unsigned long tptr; /* Tx internal data pointer */
276 unsigned short tbptr; /* Tx BD pointer */
277 unsigned short tcount; /* Tx byte count */
278 unsigned long ttemp; /* Tx temp */
279 unsigned short max_idl; /* Maximum IDLE Characters */
280 unsigned short idlc; /* Temporary IDLE Counter */
281 unsigned short brkln; /* Last Rx Break Length */
282 unsigned short brkec; /* Rx Break Condition Counter */
283 unsigned short brkcr; /* Break Count Register (Tx) */
284 unsigned short r_mask; /* Temporary bit mask */
285};
286
287struct smc_trnsp_pram {
288 unsigned short rbase; /* rx BD Base Address */
289 unsigned short tbase; /* Tx BD Base Address */
290 unsigned char rfcr; /* Rx function code */
291 unsigned char tfcr; /* Tx function code */
292 unsigned short mrblr; /* Rx buffer length */
293 unsigned long rstate; /* Rx internal state */
294 unsigned long rptr; /* Rx internal data pointer */
295 unsigned short rbptr; /* rb BD Pointer */
296 unsigned short rcount; /* Rx internal byte count */
297 unsigned long rtemp; /* Rx temp */
298 unsigned long tstate; /* Tx internal state */
299 unsigned long tptr; /* Tx internal data pointer */
300 unsigned short tbptr; /* Tx BD pointer */
301 unsigned short tcount; /* Tx byte count */
302 unsigned long ttemp; /* Tx temp */
303 unsigned short reserved[5]; /* Reserved */
304};
305
306struct idma_pram {
307 unsigned short ibase; /* IDMA BD Base Address */
308 unsigned short ibptr; /* IDMA buffer descriptor pointer */
309 unsigned long istate; /* IDMA internal state */
310 unsigned long itemp; /* IDMA temp */
311};
312
313struct ethernet_pram {
314 /*
315 * SCC parameter RAM
316 */
317 unsigned short rbase; /* RX BD base address */
318 unsigned short tbase; /* TX BD base address */
319 unsigned char rfcr; /* Rx function code */
320 unsigned char tfcr; /* Tx function code */
321 unsigned short mrblr; /* Rx buffer length */
322 unsigned long rstate; /* Rx internal state */
323 unsigned long rptr; /* Rx internal data pointer */
324 unsigned short rbptr; /* rb BD Pointer */
325 unsigned short rcount; /* Rx internal byte count */
326 unsigned long rtemp; /* Rx temp */
327 unsigned long tstate; /* Tx internal state */
328 unsigned long tptr; /* Tx internal data pointer */
329 unsigned short tbptr; /* Tx BD pointer */
330 unsigned short tcount; /* Tx byte count */
331 unsigned long ttemp; /* Tx temp */
332 unsigned long rcrc; /* temp receive CRC */
333 unsigned long tcrc; /* temp transmit CRC */
334
335 /*
336 * ETHERNET specific parameter RAM
337 */
338 unsigned long c_pres; /* preset CRC */
339 unsigned long c_mask; /* constant mask for CRC */
340 unsigned long crcec; /* CRC error counter */
341 unsigned long alec; /* alignment error counter */
342 unsigned long disfc; /* discard frame counter */
343 unsigned short pads; /* short frame PAD characters */
344 unsigned short ret_lim; /* retry limit threshold */
345 unsigned short ret_cnt; /* retry limit counter */
346 unsigned short mflr; /* maximum frame length reg */
347 unsigned short minflr; /* minimum frame length reg */
348 unsigned short maxd1; /* maximum DMA1 length reg */
349 unsigned short maxd2; /* maximum DMA2 length reg */
350 unsigned short maxd; /* rx max DMA */
351 unsigned short dma_cnt; /* rx dma counter */
352 unsigned short max_b; /* max bd byte count */
353 unsigned short gaddr1; /* group address filter 1 */
354 unsigned short gaddr2; /* group address filter 2 */
355 unsigned short gaddr3; /* group address filter 3 */
356 unsigned short gaddr4; /* group address filter 4 */
357 unsigned long tbuf0_data0; /* save area 0 - current frm */
358 unsigned long tbuf0_data1; /* save area 1 - current frm */
359 unsigned long tbuf0_rba0;
360 unsigned long tbuf0_crc;
361 unsigned short tbuf0_bcnt;
362 union {
363 unsigned char b[6];
364 struct {
365 unsigned short high;
366 unsigned short middl;
367 unsigned short low;
368 } w;
369 } paddr;
370 unsigned short p_per; /* persistence */
371 unsigned short rfbd_ptr; /* rx first bd pointer */
372 unsigned short tfbd_ptr; /* tx first bd pointer */
373 unsigned short tlbd_ptr; /* tx last bd pointer */
374 unsigned long tbuf1_data0; /* save area 0 - next frame */
375 unsigned long tbuf1_data1; /* save area 1 - next frame */
376 unsigned long tbuf1_rba0;
377 unsigned long tbuf1_crc;
378 unsigned short tbuf1_bcnt;
379 unsigned short tx_len; /* tx frame length counter */
380 unsigned short iaddr1; /* individual address filter 1*/
381 unsigned short iaddr2; /* individual address filter 2*/
382 unsigned short iaddr3; /* individual address filter 3*/
383 unsigned short iaddr4; /* individual address filter 4*/
384 unsigned short boff_cnt; /* back-off counter */
385 unsigned short taddr_h; /* temp address (MSB) */
386 unsigned short taddr_m; /* temp address */
387 unsigned short taddr_l; /* temp address (LSB) */
388};
389
390struct transparent_pram {
391 /*
392 * SCC parameter RAM
393 */
394 unsigned short rbase; /* RX BD base address */
395 unsigned short tbase; /* TX BD base address */
396 unsigned char rfcr; /* Rx function code */
397 unsigned char tfcr; /* Tx function code */
398 unsigned short mrblr; /* Rx buffer length */
399 unsigned long rstate; /* Rx internal state */
400 unsigned long rptr; /* Rx internal data pointer */
401 unsigned short rbptr; /* rb BD Pointer */
402 unsigned short rcount; /* Rx internal byte count */
403 unsigned long rtemp; /* Rx temp */
404 unsigned long tstate; /* Tx internal state */
405 unsigned long tptr; /* Tx internal data pointer */
406 unsigned short tbptr; /* Tx BD pointer */
407 unsigned short tcount; /* Tx byte count */
408 unsigned long ttemp; /* Tx temp */
409 unsigned long rcrc; /* temp receive CRC */
410 unsigned long tcrc; /* temp transmit CRC */
411
412 /*
413 * TRANSPARENT specific parameter RAM
414 */
415 unsigned long crc_p; /* CRC Preset */
416 unsigned long crc_c; /* CRC constant */
417};
418
419struct timer_pram {
420 /*
421 * RISC timers parameter RAM
422 */
423 unsigned short tm_base; /* RISC timer table base adr */
424 unsigned short tm_ptr; /* RISC timer table pointer */
425 unsigned short r_tmr; /* RISC timer mode register */
426 unsigned short r_tmv; /* RISC timer valid register */
427 unsigned long tm_cmd; /* RISC timer cmd register */
428 unsigned long tm_cnt; /* RISC timer internal cnt */
429};
430
431#endif
diff --git a/arch/m68k/include/asm/m68360_quicc.h b/arch/m68k/include/asm/m68360_quicc.h
deleted file mode 100644
index 59414cc108d3..000000000000
--- a/arch/m68k/include/asm/m68360_quicc.h
+++ /dev/null
@@ -1,362 +0,0 @@
1/***********************************
2 * $Id: m68360_quicc.h,v 1.1 2002/03/02 15:01:07 gerg Exp $
3 ***********************************
4 *
5 ***************************************
6 * Definitions of QUICC memory structures
7 ***************************************
8 */
9
10#ifndef __M68360_QUICC_H
11#define __M68360_QUICC_H
12
13/*
14 * include registers and
15 * parameter ram definitions files
16 */
17#include <asm/m68360_regs.h>
18#include <asm/m68360_pram.h>
19
20
21
22/* Buffer Descriptors */
23typedef struct quicc_bd {
24 volatile unsigned short status;
25 volatile unsigned short length;
26 volatile unsigned char *buf; /* WARNING: This is only true if *char is 32 bits */
27} QUICC_BD;
28
29
30#ifdef MOTOROLA_ORIGINAL
31struct user_data {
32 /* BASE + 0x000: user data memory */
33 volatile unsigned char udata_bd_ucode[0x400]; /*user data bd's Ucode*/
34 volatile unsigned char udata_bd[0x200]; /*user data Ucode */
35 volatile unsigned char ucode_ext[0x100]; /*Ucode Extension ram */
36 volatile unsigned char RESERVED1[0x500]; /* Reserved area */
37};
38#else
39struct user_data {
40 /* BASE + 0x000: user data memory */
41 volatile unsigned char udata_bd_ucode[0x400]; /* user data, bds, Ucode*/
42 volatile unsigned char udata_bd1[0x200]; /* user, bds */
43 volatile unsigned char ucode_bd_scratch[0x100]; /* user, bds, ucode scratch */
44 volatile unsigned char udata_bd2[0x100]; /* user, bds */
45 volatile unsigned char RESERVED1[0x400]; /* Reserved area */
46};
47#endif
48
49
50/*
51 * internal ram
52 */
53typedef struct quicc {
54 union {
55 struct quicc32_pram ch_pram_tbl[32]; /* 32*64(bytes) per channel */
56 struct user_data u;
57 }ch_or_u; /* multipul or user space */
58
59 /* BASE + 0xc00: PARAMETER RAM */
60 union {
61 struct scc_pram {
62 union {
63 struct hdlc_pram h;
64 struct uart_pram u;
65 struct bisync_pram b;
66 struct transparent_pram t;
67 unsigned char RESERVED66[0x70];
68 } pscc; /* scc parameter area (protocol dependent) */
69 union {
70 struct {
71 unsigned char RESERVED70[0x10];
72 struct spi_pram spi;
73 unsigned char RESERVED72[0x8];
74 struct timer_pram timer;
75 } timer_spi;
76 struct {
77 struct idma_pram idma;
78 unsigned char RESERVED67[0x4];
79 union {
80 struct smc_uart_pram u;
81 struct smc_trnsp_pram t;
82 } psmc;
83 } idma_smc;
84 } pothers;
85 } scc;
86 struct ethernet_pram enet_scc;
87 struct global_multi_pram m;
88 unsigned char pr[0x100];
89 } pram[4];
90
91 /* reserved */
92
93 /* BASE + 0x1000: INTERNAL REGISTERS */
94 /* SIM */
95 volatile unsigned long sim_mcr; /* module configuration reg */
96 volatile unsigned short sim_simtr; /* module test register */
97 volatile unsigned char RESERVED2[0x2]; /* Reserved area */
98 volatile unsigned char sim_avr; /* auto vector reg */
99 volatile unsigned char sim_rsr; /* reset status reg */
100 volatile unsigned char RESERVED3[0x2]; /* Reserved area */
101 volatile unsigned char sim_clkocr; /* CLCO control register */
102 volatile unsigned char RESERVED62[0x3]; /* Reserved area */
103 volatile unsigned short sim_pllcr; /* PLL control register */
104 volatile unsigned char RESERVED63[0x2]; /* Reserved area */
105 volatile unsigned short sim_cdvcr; /* Clock devider control register */
106 volatile unsigned short sim_pepar; /* Port E pin assignment register */
107 volatile unsigned char RESERVED64[0xa]; /* Reserved area */
108 volatile unsigned char sim_sypcr; /* system protection control*/
109 volatile unsigned char sim_swiv; /* software interrupt vector*/
110 volatile unsigned char RESERVED6[0x2]; /* Reserved area */
111 volatile unsigned short sim_picr; /* periodic interrupt control reg */
112 volatile unsigned char RESERVED7[0x2]; /* Reserved area */
113 volatile unsigned short sim_pitr; /* periodic interrupt timing reg */
114 volatile unsigned char RESERVED8[0x3]; /* Reserved area */
115 volatile unsigned char sim_swsr; /* software service */
116 volatile unsigned long sim_bkar; /* breakpoint address register*/
117 volatile unsigned long sim_bkcr; /* breakpoint control register*/
118 volatile unsigned char RESERVED10[0x8]; /* Reserved area */
119 /* MEMC */
120 volatile unsigned long memc_gmr; /* Global memory register */
121 volatile unsigned short memc_mstat; /* MEMC status register */
122 volatile unsigned char RESERVED11[0xa]; /* Reserved area */
123 volatile unsigned long memc_br0; /* base register 0 */
124 volatile unsigned long memc_or0; /* option register 0 */
125 volatile unsigned char RESERVED12[0x8]; /* Reserved area */
126 volatile unsigned long memc_br1; /* base register 1 */
127 volatile unsigned long memc_or1; /* option register 1 */
128 volatile unsigned char RESERVED13[0x8]; /* Reserved area */
129 volatile unsigned long memc_br2; /* base register 2 */
130 volatile unsigned long memc_or2; /* option register 2 */
131 volatile unsigned char RESERVED14[0x8]; /* Reserved area */
132 volatile unsigned long memc_br3; /* base register 3 */
133 volatile unsigned long memc_or3; /* option register 3 */
134 volatile unsigned char RESERVED15[0x8]; /* Reserved area */
135 volatile unsigned long memc_br4; /* base register 3 */
136 volatile unsigned long memc_or4; /* option register 3 */
137 volatile unsigned char RESERVED16[0x8]; /* Reserved area */
138 volatile unsigned long memc_br5; /* base register 3 */
139 volatile unsigned long memc_or5; /* option register 3 */
140 volatile unsigned char RESERVED17[0x8]; /* Reserved area */
141 volatile unsigned long memc_br6; /* base register 3 */
142 volatile unsigned long memc_or6; /* option register 3 */
143 volatile unsigned char RESERVED18[0x8]; /* Reserved area */
144 volatile unsigned long memc_br7; /* base register 3 */
145 volatile unsigned long memc_or7; /* option register 3 */
146 volatile unsigned char RESERVED9[0x28]; /* Reserved area */
147 /* TEST */
148 volatile unsigned short test_tstmra; /* master shift a */
149 volatile unsigned short test_tstmrb; /* master shift b */
150 volatile unsigned short test_tstsc; /* shift count */
151 volatile unsigned short test_tstrc; /* repetition counter */
152 volatile unsigned short test_creg; /* control */
153 volatile unsigned short test_dreg; /* destributed register */
154 volatile unsigned char RESERVED58[0x404]; /* Reserved area */
155 /* IDMA1 */
156 volatile unsigned short idma_iccr; /* channel configuration reg*/
157 volatile unsigned char RESERVED19[0x2]; /* Reserved area */
158 volatile unsigned short idma1_cmr; /* dma mode reg */
159 volatile unsigned char RESERVED68[0x2]; /* Reserved area */
160 volatile unsigned long idma1_sapr; /* dma source addr ptr */
161 volatile unsigned long idma1_dapr; /* dma destination addr ptr */
162 volatile unsigned long idma1_bcr; /* dma byte count reg */
163 volatile unsigned char idma1_fcr; /* function code reg */
164 volatile unsigned char RESERVED20; /* Reserved area */
165 volatile unsigned char idma1_cmar; /* channel mask reg */
166 volatile unsigned char RESERVED21; /* Reserved area */
167 volatile unsigned char idma1_csr; /* channel status reg */
168 volatile unsigned char RESERVED22[0x3]; /* Reserved area */
169 /* SDMA */
170 volatile unsigned char sdma_sdsr; /* status reg */
171 volatile unsigned char RESERVED23; /* Reserved area */
172 volatile unsigned short sdma_sdcr; /* configuration reg */
173 volatile unsigned long sdma_sdar; /* address reg */
174 /* IDMA2 */
175 volatile unsigned char RESERVED69[0x2]; /* Reserved area */
176 volatile unsigned short idma2_cmr; /* dma mode reg */
177 volatile unsigned long idma2_sapr; /* dma source addr ptr */
178 volatile unsigned long idma2_dapr; /* dma destination addr ptr */
179 volatile unsigned long idma2_bcr; /* dma byte count reg */
180 volatile unsigned char idma2_fcr; /* function code reg */
181 volatile unsigned char RESERVED24; /* Reserved area */
182 volatile unsigned char idma2_cmar; /* channel mask reg */
183 volatile unsigned char RESERVED25; /* Reserved area */
184 volatile unsigned char idma2_csr; /* channel status reg */
185 volatile unsigned char RESERVED26[0x7]; /* Reserved area */
186 /* Interrupt Controller */
187 volatile unsigned long intr_cicr; /* CP interrupt configuration reg*/
188 volatile unsigned long intr_cipr; /* CP interrupt pending reg */
189 volatile unsigned long intr_cimr; /* CP interrupt mask reg */
190 volatile unsigned long intr_cisr; /* CP interrupt in service reg*/
191 /* Parallel I/O */
192 volatile unsigned short pio_padir; /* port A data direction reg */
193 volatile unsigned short pio_papar; /* port A pin assignment reg */
194 volatile unsigned short pio_paodr; /* port A open drain reg */
195 volatile unsigned short pio_padat; /* port A data register */
196 volatile unsigned char RESERVED28[0x8]; /* Reserved area */
197 volatile unsigned short pio_pcdir; /* port C data direction reg*/
198 volatile unsigned short pio_pcpar; /* port C pin assignment reg*/
199 volatile unsigned short pio_pcso; /* port C special options */
200 volatile unsigned short pio_pcdat; /* port C data register */
201 volatile unsigned short pio_pcint; /* port C interrupt cntrl reg */
202 volatile unsigned char RESERVED29[0x16]; /* Reserved area */
203 /* Timer */
204 volatile unsigned short timer_tgcr; /* timer global configuration reg */
205 volatile unsigned char RESERVED30[0xe]; /* Reserved area */
206 volatile unsigned short timer_tmr1; /* timer 1 mode reg */
207 volatile unsigned short timer_tmr2; /* timer 2 mode reg */
208 volatile unsigned short timer_trr1; /* timer 1 referance reg */
209 volatile unsigned short timer_trr2; /* timer 2 referance reg */
210 volatile unsigned short timer_tcr1; /* timer 1 capture reg */
211 volatile unsigned short timer_tcr2; /* timer 2 capture reg */
212 volatile unsigned short timer_tcn1; /* timer 1 counter reg */
213 volatile unsigned short timer_tcn2; /* timer 2 counter reg */
214 volatile unsigned short timer_tmr3; /* timer 3 mode reg */
215 volatile unsigned short timer_tmr4; /* timer 4 mode reg */
216 volatile unsigned short timer_trr3; /* timer 3 referance reg */
217 volatile unsigned short timer_trr4; /* timer 4 referance reg */
218 volatile unsigned short timer_tcr3; /* timer 3 capture reg */
219 volatile unsigned short timer_tcr4; /* timer 4 capture reg */
220 volatile unsigned short timer_tcn3; /* timer 3 counter reg */
221 volatile unsigned short timer_tcn4; /* timer 4 counter reg */
222 volatile unsigned short timer_ter1; /* timer 1 event reg */
223 volatile unsigned short timer_ter2; /* timer 2 event reg */
224 volatile unsigned short timer_ter3; /* timer 3 event reg */
225 volatile unsigned short timer_ter4; /* timer 4 event reg */
226 volatile unsigned char RESERVED34[0x8]; /* Reserved area */
227 /* CP */
228 volatile unsigned short cp_cr; /* command register */
229 volatile unsigned char RESERVED35[0x2]; /* Reserved area */
230 volatile unsigned short cp_rccr; /* main configuration reg */
231 volatile unsigned char RESERVED37; /* Reserved area */
232 volatile unsigned char cp_rmds; /* development support status reg */
233 volatile unsigned long cp_rmdr; /* development support control reg */
234 volatile unsigned short cp_rctr1; /* ram break register 1 */
235 volatile unsigned short cp_rctr2; /* ram break register 2 */
236 volatile unsigned short cp_rctr3; /* ram break register 3 */
237 volatile unsigned short cp_rctr4; /* ram break register 4 */
238 volatile unsigned char RESERVED59[0x2]; /* Reserved area */
239 volatile unsigned short cp_rter; /* RISC timers event reg */
240 volatile unsigned char RESERVED38[0x2]; /* Reserved area */
241 volatile unsigned short cp_rtmr; /* RISC timers mask reg */
242 volatile unsigned char RESERVED39[0x14]; /* Reserved area */
243 /* BRG */
244 union {
245 volatile unsigned long l;
246 struct {
247 volatile unsigned short BRGC_RESERV:14;
248 volatile unsigned short rst:1;
249 volatile unsigned short en:1;
250 volatile unsigned short extc:2;
251 volatile unsigned short atb:1;
252 volatile unsigned short cd:12;
253 volatile unsigned short div16:1;
254 } b;
255 } brgc[4]; /* BRG1-BRG4 configuration regs*/
256 /* SCC registers */
257 struct scc_regs {
258 union {
259 struct {
260 /* Low word. */
261 volatile unsigned short GSMR_RESERV2:1;
262 volatile unsigned short edge:2;
263 volatile unsigned short tci:1;
264 volatile unsigned short tsnc:2;
265 volatile unsigned short rinv:1;
266 volatile unsigned short tinv:1;
267 volatile unsigned short tpl:3;
268 volatile unsigned short tpp:2;
269 volatile unsigned short tend:1;
270 volatile unsigned short tdcr:2;
271 volatile unsigned short rdcr:2;
272 volatile unsigned short renc:3;
273 volatile unsigned short tenc:3;
274 volatile unsigned short diag:2;
275 volatile unsigned short enr:1;
276 volatile unsigned short ent:1;
277 volatile unsigned short mode:4;
278 /* High word. */
279 volatile unsigned short GSMR_RESERV1:14;
280 volatile unsigned short pri:1;
281 volatile unsigned short gde:1;
282 volatile unsigned short tcrc:2;
283 volatile unsigned short revd:1;
284 volatile unsigned short trx:1;
285 volatile unsigned short ttx:1;
286 volatile unsigned short cdp:1;
287 volatile unsigned short ctsp:1;
288 volatile unsigned short cds:1;
289 volatile unsigned short ctss:1;
290 volatile unsigned short tfl:1;
291 volatile unsigned short rfw:1;
292 volatile unsigned short txsy:1;
293 volatile unsigned short synl:2;
294 volatile unsigned short rtsm:1;
295 volatile unsigned short rsyn:1;
296 } b;
297 struct {
298 volatile unsigned long low;
299 volatile unsigned long high;
300 } w;
301 } scc_gsmr; /* SCC general mode reg */
302 volatile unsigned short scc_psmr; /* protocol specific mode reg */
303 volatile unsigned char RESERVED42[0x2]; /* Reserved area */
304 volatile unsigned short scc_todr; /* SCC transmit on demand */
305 volatile unsigned short scc_dsr; /* SCC data sync reg */
306 volatile unsigned short scc_scce; /* SCC event reg */
307 volatile unsigned char RESERVED43[0x2];/* Reserved area */
308 volatile unsigned short scc_sccm; /* SCC mask reg */
309 volatile unsigned char RESERVED44[0x1];/* Reserved area */
310 volatile unsigned char scc_sccs; /* SCC status reg */
311 volatile unsigned char RESERVED45[0x8]; /* Reserved area */
312 } scc_regs[4];
313 /* SMC */
314 struct smc_regs {
315 volatile unsigned char RESERVED46[0x2]; /* Reserved area */
316 volatile unsigned short smc_smcmr; /* SMC mode reg */
317 volatile unsigned char RESERVED60[0x2]; /* Reserved area */
318 volatile unsigned char smc_smce; /* SMC event reg */
319 volatile unsigned char RESERVED47[0x3]; /* Reserved area */
320 volatile unsigned char smc_smcm; /* SMC mask reg */
321 volatile unsigned char RESERVED48[0x5]; /* Reserved area */
322 } smc_regs[2];
323 /* SPI */
324 volatile unsigned short spi_spmode; /* SPI mode reg */
325 volatile unsigned char RESERVED51[0x4]; /* Reserved area */
326 volatile unsigned char spi_spie; /* SPI event reg */
327 volatile unsigned char RESERVED52[0x3]; /* Reserved area */
328 volatile unsigned char spi_spim; /* SPI mask reg */
329 volatile unsigned char RESERVED53[0x2]; /* Reserved area */
330 volatile unsigned char spi_spcom; /* SPI command reg */
331 volatile unsigned char RESERVED54[0x4]; /* Reserved area */
332 /* PIP */
333 volatile unsigned short pip_pipc; /* pip configuration reg */
334 volatile unsigned char RESERVED65[0x2]; /* Reserved area */
335 volatile unsigned short pip_ptpr; /* pip timing parameters reg */
336 volatile unsigned long pip_pbdir; /* port b data direction reg */
337 volatile unsigned long pip_pbpar; /* port b pin assignment reg */
338 volatile unsigned long pip_pbodr; /* port b open drain reg */
339 volatile unsigned long pip_pbdat; /* port b data reg */
340 volatile unsigned char RESERVED71[0x18]; /* Reserved area */
341 /* Serial Interface */
342 volatile unsigned long si_simode; /* SI mode register */
343 volatile unsigned char si_sigmr; /* SI global mode register */
344 volatile unsigned char RESERVED55; /* Reserved area */
345 volatile unsigned char si_sistr; /* SI status register */
346 volatile unsigned char si_sicmr; /* SI command register */
347 volatile unsigned char RESERVED56[0x4]; /* Reserved area */
348 volatile unsigned long si_sicr; /* SI clock routing */
349 volatile unsigned long si_sirp; /* SI ram pointers */
350 volatile unsigned char RESERVED57[0xc]; /* Reserved area */
351 volatile unsigned short si_siram[0x80]; /* SI routing ram */
352} QUICC;
353
354#endif
355
356/*
357 * Local variables:
358 * c-indent-level: 4
359 * c-basic-offset: 4
360 * tab-width: 4
361 * End:
362 */
diff --git a/arch/m68k/include/asm/m68360_regs.h b/arch/m68k/include/asm/m68360_regs.h
deleted file mode 100644
index d57217ca4f27..000000000000
--- a/arch/m68k/include/asm/m68360_regs.h
+++ /dev/null
@@ -1,408 +0,0 @@
1/***********************************
2 * $Id: m68360_regs.h,v 1.2 2002/10/26 15:03:55 gerg Exp $
3 ***********************************
4 *
5 ***************************************
6 * Definitions of the QUICC registers
7 ***************************************
8 */
9
10#ifndef __REGISTERS_H
11#define __REGISTERS_H
12
13#define CLEAR_BIT(x, bit) x =bit
14
15/*****************************************************************
16 Command Register
17*****************************************************************/
18
19/* bit fields within command register */
20#define SOFTWARE_RESET 0x8000
21#define CMD_OPCODE 0x0f00
22#define CMD_CHANNEL 0x00f0
23#define CMD_FLAG 0x0001
24
25/* general command opcodes */
26#define INIT_RXTX_PARAMS 0x0000
27#define INIT_RX_PARAMS 0x0100
28#define INIT_TX_PARAMS 0x0200
29#define ENTER_HUNT_MODE 0x0300
30#define STOP_TX 0x0400
31#define GR_STOP_TX 0x0500
32#define RESTART_TX 0x0600
33#define CLOSE_RX_BD 0x0700
34#define SET_ENET_GROUP 0x0800
35#define RESET_ENET_GROUP 0x0900
36
37/* quicc32 CP commands */
38#define STOP_TX_32 0x0e00 /*add chan# bits 2-6 */
39#define ENTER_HUNT_MODE_32 0x1e00
40
41/* quicc32 mask/event SCC register */
42#define GOV 0x01
43#define GUN 0x02
44#define GINT 0x04
45#define IQOV 0x08
46
47
48/* Timer commands */
49#define SET_TIMER 0x0800
50
51/* Multi channel Interrupt structure */
52#define INTR_VALID 0x8000 /* Valid interrupt entry */
53#define INTR_WRAP 0x4000 /* Wrap bit in the interrupt entry table */
54#define INTR_CH_NU 0x07c0 /* Channel Num in interrupt table */
55#define INTR_MASK_BITS 0x383f
56
57/*
58 * General SCC mode register (GSMR)
59 */
60
61#define MODE_HDLC 0x0
62#define MODE_APPLE_TALK 0x2
63#define MODE_SS7 0x3
64#define MODE_UART 0x4
65#define MODE_PROFIBUS 0x5
66#define MODE_ASYNC_HDLC 0x6
67#define MODE_V14 0x7
68#define MODE_BISYNC 0x8
69#define MODE_DDCMP 0x9
70#define MODE_MULTI_CHANNEL 0xa
71#define MODE_ETHERNET 0xc
72
73#define DIAG_NORMAL 0x0
74#define DIAG_LOCAL_LPB 0x1
75#define DIAG_AUTO_ECHO 0x2
76#define DIAG_LBP_ECHO 0x3
77
78/* For RENC and TENC fields in GSMR */
79#define ENC_NRZ 0x0
80#define ENC_NRZI 0x1
81#define ENC_FM0 0x2
82#define ENC_MANCH 0x4
83#define ENC_DIFF_MANC 0x6
84
85/* For TDCR and RDCR fields in GSMR */
86#define CLOCK_RATE_1 0x0
87#define CLOCK_RATE_8 0x1
88#define CLOCK_RATE_16 0x2
89#define CLOCK_RATE_32 0x3
90
91#define TPP_00 0x0
92#define TPP_10 0x1
93#define TPP_01 0x2
94#define TPP_11 0x3
95
96#define TPL_NO 0x0
97#define TPL_8 0x1
98#define TPL_16 0x2
99#define TPL_32 0x3
100#define TPL_48 0x4
101#define TPL_64 0x5
102#define TPL_128 0x6
103
104#define TSNC_INFINITE 0x0
105#define TSNC_14_65 0x1
106#define TSNC_4_15 0x2
107#define TSNC_3_1 0x3
108
109#define EDGE_BOTH 0x0
110#define EDGE_POS 0x1
111#define EDGE_NEG 0x2
112#define EDGE_NO 0x3
113
114#define SYNL_NO 0x0
115#define SYNL_4 0x1
116#define SYNL_8 0x2
117#define SYNL_16 0x3
118
119#define TCRC_CCITT16 0x0
120#define TCRC_CRC16 0x1
121#define TCRC_CCITT32 0x2
122
123
124/*****************************************************************
125 TODR (Transmit on demand) Register
126*****************************************************************/
127#define TODR_TOD 0x8000 /* Transmit on demand */
128
129
130/*****************************************************************
131 CICR register settings
132*****************************************************************/
133
134/* note that relative irq priorities of the SCCs can be reordered
135 * if desired - see p. 7-377 of the MC68360UM */
136#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
137#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
138#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
139#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */
140
141#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */
142#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
143#define CICR_VBA_MASK ((uint)0x000000e0) /* Vector Base Address */
144#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
145
146
147/*****************************************************************
148 Interrupt bits for CIPR and CIMR (MC68360UM p. 7-379)
149*****************************************************************/
150
151#define INTR_PIO_PC0 0x80000000 /* parallel I/O C bit 0 */
152#define INTR_SCC1 0x40000000 /* SCC port 1 */
153#define INTR_SCC2 0x20000000 /* SCC port 2 */
154#define INTR_SCC3 0x10000000 /* SCC port 3 */
155#define INTR_SCC4 0x08000000 /* SCC port 4 */
156#define INTR_PIO_PC1 0x04000000 /* parallel i/o C bit 1 */
157#define INTR_TIMER1 0x02000000 /* timer 1 */
158#define INTR_PIO_PC2 0x01000000 /* parallel i/o C bit 2 */
159#define INTR_PIO_PC3 0x00800000 /* parallel i/o C bit 3 */
160#define INTR_SDMA_BERR 0x00400000 /* SDMA channel bus error */
161#define INTR_DMA1 0x00200000 /* idma 1 */
162#define INTR_DMA2 0x00100000 /* idma 2 */
163#define INTR_TIMER2 0x00040000 /* timer 2 */
164#define INTR_CP_TIMER 0x00020000 /* CP timer */
165#define INTR_PIP_STATUS 0x00010000 /* PIP status */
166#define INTR_PIO_PC4 0x00008000 /* parallel i/o C bit 4 */
167#define INTR_PIO_PC5 0x00004000 /* parallel i/o C bit 5 */
168#define INTR_TIMER3 0x00001000 /* timer 3 */
169#define INTR_PIO_PC6 0x00000800 /* parallel i/o C bit 6 */
170#define INTR_PIO_PC7 0x00000400 /* parallel i/o C bit 7 */
171#define INTR_PIO_PC8 0x00000200 /* parallel i/o C bit 8 */
172#define INTR_TIMER4 0x00000080 /* timer 4 */
173#define INTR_PIO_PC9 0x00000040 /* parallel i/o C bit 9 */
174#define INTR_SCP 0x00000020 /* SCP */
175#define INTR_SMC1 0x00000010 /* SMC 1 */
176#define INTR_SMC2 0x00000008 /* SMC 2 */
177#define INTR_PIO_PC10 0x00000004 /* parallel i/o C bit 10 */
178#define INTR_PIO_PC11 0x00000002 /* parallel i/o C bit 11 */
179#define INTR_ERR 0x00000001 /* error */
180
181
182/*****************************************************************
183 CPM Interrupt vector encodings (MC68360UM p. 7-376)
184*****************************************************************/
185
186#define CPMVEC_NR 32
187#define CPMVEC_PIO_PC0 0x1f
188#define CPMVEC_SCC1 0x1e
189#define CPMVEC_SCC2 0x1d
190#define CPMVEC_SCC3 0x1c
191#define CPMVEC_SCC4 0x1b
192#define CPMVEC_PIO_PC1 0x1a
193#define CPMVEC_TIMER1 0x19
194#define CPMVEC_PIO_PC2 0x18
195#define CPMVEC_PIO_PC3 0x17
196#define CPMVEC_SDMA_CB_ERR 0x16
197#define CPMVEC_IDMA1 0x15
198#define CPMVEC_IDMA2 0x14
199#define CPMVEC_RESERVED3 0x13
200#define CPMVEC_TIMER2 0x12
201#define CPMVEC_RISCTIMER 0x11
202#define CPMVEC_RESERVED2 0x10
203#define CPMVEC_PIO_PC4 0x0f
204#define CPMVEC_PIO_PC5 0x0e
205#define CPMVEC_TIMER3 0x0c
206#define CPMVEC_PIO_PC6 0x0b
207#define CPMVEC_PIO_PC7 0x0a
208#define CPMVEC_PIO_PC8 0x09
209#define CPMVEC_RESERVED1 0x08
210#define CPMVEC_TIMER4 0x07
211#define CPMVEC_PIO_PC9 0x06
212#define CPMVEC_SPI 0x05
213#define CPMVEC_SMC1 0x04
214#define CPMVEC_SMC2 0x03
215#define CPMVEC_PIO_PC10 0x02
216#define CPMVEC_PIO_PC11 0x01
217#define CPMVEC_ERROR 0x00
218
219/* #define CPMVEC_PIO_PC0 ((ushort)0x1f) */
220/* #define CPMVEC_SCC1 ((ushort)0x1e) */
221/* #define CPMVEC_SCC2 ((ushort)0x1d) */
222/* #define CPMVEC_SCC3 ((ushort)0x1c) */
223/* #define CPMVEC_SCC4 ((ushort)0x1b) */
224/* #define CPMVEC_PIO_PC1 ((ushort)0x1a) */
225/* #define CPMVEC_TIMER1 ((ushort)0x19) */
226/* #define CPMVEC_PIO_PC2 ((ushort)0x18) */
227/* #define CPMVEC_PIO_PC3 ((ushort)0x17) */
228/* #define CPMVEC_SDMA_CB_ERR ((ushort)0x16) */
229/* #define CPMVEC_IDMA1 ((ushort)0x15) */
230/* #define CPMVEC_IDMA2 ((ushort)0x14) */
231/* #define CPMVEC_RESERVED3 ((ushort)0x13) */
232/* #define CPMVEC_TIMER2 ((ushort)0x12) */
233/* #define CPMVEC_RISCTIMER ((ushort)0x11) */
234/* #define CPMVEC_RESERVED2 ((ushort)0x10) */
235/* #define CPMVEC_PIO_PC4 ((ushort)0x0f) */
236/* #define CPMVEC_PIO_PC5 ((ushort)0x0e) */
237/* #define CPMVEC_TIMER3 ((ushort)0x0c) */
238/* #define CPMVEC_PIO_PC6 ((ushort)0x0b) */
239/* #define CPMVEC_PIO_PC7 ((ushort)0x0a) */
240/* #define CPMVEC_PIO_PC8 ((ushort)0x09) */
241/* #define CPMVEC_RESERVED1 ((ushort)0x08) */
242/* #define CPMVEC_TIMER4 ((ushort)0x07) */
243/* #define CPMVEC_PIO_PC9 ((ushort)0x06) */
244/* #define CPMVEC_SPI ((ushort)0x05) */
245/* #define CPMVEC_SMC1 ((ushort)0x04) */
246/* #define CPMVEC_SMC2 ((ushort)0x03) */
247/* #define CPMVEC_PIO_PC10 ((ushort)0x02) */
248/* #define CPMVEC_PIO_PC11 ((ushort)0x01) */
249/* #define CPMVEC_ERROR ((ushort)0x00) */
250
251
252/*****************************************************************
253 * PIO control registers
254 *****************************************************************/
255
256/* Port A - See 360UM p. 7-358
257 *
258 * Note that most of these pins have alternate functions
259 */
260
261
262/* The macros are nice, but there are all sorts of references to 1-indexed
263 * facilities on the 68360... */
264/* #define PA_RXD(n) ((ushort)(0x01<<(2*n))) */
265/* #define PA_TXD(n) ((ushort)(0x02<<(2*n))) */
266
267#define PA_RXD1 ((ushort)0x0001)
268#define PA_TXD1 ((ushort)0x0002)
269#define PA_RXD2 ((ushort)0x0004)
270#define PA_TXD2 ((ushort)0x0008)
271#define PA_RXD3 ((ushort)0x0010)
272#define PA_TXD3 ((ushort)0x0020)
273#define PA_RXD4 ((ushort)0x0040)
274#define PA_TXD4 ((ushort)0x0080)
275
276#define PA_CLK1 ((ushort)0x0100)
277#define PA_CLK2 ((ushort)0x0200)
278#define PA_CLK3 ((ushort)0x0400)
279#define PA_CLK4 ((ushort)0x0800)
280#define PA_CLK5 ((ushort)0x1000)
281#define PA_CLK6 ((ushort)0x2000)
282#define PA_CLK7 ((ushort)0x4000)
283#define PA_CLK8 ((ushort)0x8000)
284
285
286/* Port B - See 360UM p. 7-362
287 */
288
289
290/* Port C - See 360UM p. 7-365
291 */
292
293#define PC_RTS1 ((ushort)0x0001)
294#define PC_RTS2 ((ushort)0x0002)
295#define PC__RTS3 ((ushort)0x0004) /* !RTS3 */
296#define PC__RTS4 ((ushort)0x0008) /* !RTS4 */
297
298#define PC_CTS1 ((ushort)0x0010)
299#define PC_CD1 ((ushort)0x0020)
300#define PC_CTS2 ((ushort)0x0040)
301#define PC_CD2 ((ushort)0x0080)
302#define PC_CTS3 ((ushort)0x0100)
303#define PC_CD3 ((ushort)0x0200)
304#define PC_CTS4 ((ushort)0x0400)
305#define PC_CD4 ((ushort)0x0800)
306
307
308
309/*****************************************************************
310 chip select option register
311*****************************************************************/
312#define DTACK 0xe000
313#define ADR_MASK 0x1ffc
314#define RDWR_MASK 0x0002
315#define FC_MASK 0x0001
316
317/*****************************************************************
318 tbase and rbase registers
319*****************************************************************/
320#define TBD_ADDR(quicc,pram) ((struct quicc_bd *) \
321 (quicc->ch_or_u.u.udata_bd_ucode + pram->tbase))
322#define RBD_ADDR(quicc,pram) ((struct quicc_bd *) \
323 (quicc->ch_or_u.u.udata_bd_ucode + pram->rbase))
324#define TBD_CUR_ADDR(quicc,pram) ((struct quicc_bd *) \
325 (quicc->ch_or_u.u.udata_bd_ucode + pram->tbptr))
326#define RBD_CUR_ADDR(quicc,pram) ((struct quicc_bd *) \
327 (quicc->ch_or_u.u.udata_bd_ucode + pram->rbptr))
328#define TBD_SET_CUR_ADDR(bd,quicc,pram) pram->tbptr = \
329 ((unsigned short)((char *)(bd) - (char *)(quicc->ch_or_u.u.udata_bd_ucode)))
330#define RBD_SET_CUR_ADDR(bd,quicc,pram) pram->rbptr = \
331 ((unsigned short)((char *)(bd) - (char *)(quicc->ch_or_u.u.udata_bd_ucode)))
332#define INCREASE_TBD(bd,quicc,pram) { \
333 if((bd)->status & T_W) \
334 (bd) = TBD_ADDR(quicc,pram); \
335 else \
336 (bd)++; \
337}
338#define DECREASE_TBD(bd,quicc,pram) { \
339 if ((bd) == TBD_ADDR(quicc, pram)) \
340 while (!((bd)->status & T_W)) \
341 (bd)++; \
342 else \
343 (bd)--; \
344}
345#define INCREASE_RBD(bd,quicc,pram) { \
346 if((bd)->status & R_W) \
347 (bd) = RBD_ADDR(quicc,pram); \
348 else \
349 (bd)++; \
350}
351#define DECREASE_RBD(bd,quicc,pram) { \
352 if ((bd) == RBD_ADDR(quicc, pram)) \
353 while (!((bd)->status & T_W)) \
354 (bd)++; \
355 else \
356 (bd)--; \
357}
358
359/*****************************************************************
360 Macros for Multi channel
361*****************************************************************/
362#define QMC_BASE(quicc,page) (struct global_multi_pram *)(&quicc->pram[page])
363#define MCBASE(quicc,page) (unsigned long)(quicc->pram[page].m.mcbase)
364#define CHANNEL_PRAM_BASE(quicc,channel) ((struct quicc32_pram *) \
365 (&(quicc->ch_or_u.ch_pram_tbl[channel])))
366#define TBD_32_ADDR(quicc,page,channel) ((struct quicc_bd *) \
367 (MCBASE(quicc,page) + (CHANNEL_PRAM_BASE(quicc,channel)->tbase)))
368#define RBD_32_ADDR(quicc,page,channel) ((struct quicc_bd *) \
369 (MCBASE(quicc,page) + (CHANNEL_PRAM_BASE(quicc,channel)->rbase)))
370#define TBD_32_CUR_ADDR(quicc,page,channel) ((struct quicc_bd *) \
371 (MCBASE(quicc,page) + (CHANNEL_PRAM_BASE(quicc,channel)->tbptr)))
372#define RBD_32_CUR_ADDR(quicc,page,channel) ((struct quicc_bd *) \
373 (MCBASE(quicc,page) + (CHANNEL_PRAM_BASE(quicc,channel)->rbptr)))
374#define TBD_32_SET_CUR_ADDR(bd,quicc,page,channel) \
375 CHANNEL_PRAM_BASE(quicc,channel)->tbptr = \
376 ((unsigned short)((char *)(bd) - (char *)(MCBASE(quicc,page))))
377#define RBD_32_SET_CUR_ADDR(bd,quicc,page,channel) \
378 CHANNEL_PRAM_BASE(quicc,channel)->rbptr = \
379 ((unsigned short)((char *)(bd) - (char *)(MCBASE(quicc,page))))
380
381#define INCREASE_TBD_32(bd,quicc,page,channel) { \
382 if((bd)->status & T_W) \
383 (bd) = TBD_32_ADDR(quicc,page,channel); \
384 else \
385 (bd)++; \
386}
387#define DECREASE_TBD_32(bd,quicc,page,channel) { \
388 if ((bd) == TBD_32_ADDR(quicc, page,channel)) \
389 while (!((bd)->status & T_W)) \
390 (bd)++; \
391 else \
392 (bd)--; \
393}
394#define INCREASE_RBD_32(bd,quicc,page,channel) { \
395 if((bd)->status & R_W) \
396 (bd) = RBD_32_ADDR(quicc,page,channel); \
397 else \
398 (bd)++; \
399}
400#define DECREASE_RBD_32(bd,quicc,page,channel) { \
401 if ((bd) == RBD_32_ADDR(quicc, page,channel)) \
402 while (!((bd)->status & T_W)) \
403 (bd)++; \
404 else \
405 (bd)--; \
406}
407
408#endif
diff --git a/arch/m68k/kernel/early_printk.c b/arch/m68k/kernel/early_printk.c
index ff9708d71921..7d3fe08a48eb 100644
--- a/arch/m68k/kernel/early_printk.c
+++ b/arch/m68k/kernel/early_printk.c
@@ -20,8 +20,8 @@ asmlinkage void __init debug_cons_nputs(const char *s, unsigned n);
20static void __ref debug_cons_write(struct console *c, 20static void __ref debug_cons_write(struct console *c,
21 const char *s, unsigned n) 21 const char *s, unsigned n)
22{ 22{
23#if !(defined(CONFIG_SUN3) || defined(CONFIG_M68360) || \ 23#if !(defined(CONFIG_SUN3) || defined(CONFIG_M68000) || \
24 defined(CONFIG_M68000) || defined(CONFIG_COLDFIRE)) 24 defined(CONFIG_COLDFIRE))
25 if (MACH_IS_MVME16x) 25 if (MACH_IS_MVME16x)
26 mvme16x_cons_write(c, s, n); 26 mvme16x_cons_write(c, s, n);
27 else 27 else
@@ -52,8 +52,8 @@ early_param("earlyprintk", setup_early_printk);
52 * debug_cons_nputs() defined in arch/m68k/kernel/head.S cannot be called 52 * debug_cons_nputs() defined in arch/m68k/kernel/head.S cannot be called
53 * after init sections are discarded (for platforms that use it). 53 * after init sections are discarded (for platforms that use it).
54 */ 54 */
55#if !(defined(CONFIG_SUN3) || defined(CONFIG_M68360) || \ 55#if !(defined(CONFIG_SUN3) || defined(CONFIG_M68000) || \
56 defined(CONFIG_M68000) || defined(CONFIG_COLDFIRE)) 56 defined(CONFIG_COLDFIRE))
57 57
58static int __init unregister_early_console(void) 58static int __init unregister_early_console(void)
59{ 59{
diff --git a/arch/m68k/kernel/setup_no.c b/arch/m68k/kernel/setup_no.c
index 76b9113f3092..9309789215a8 100644
--- a/arch/m68k/kernel/setup_no.c
+++ b/arch/m68k/kernel/setup_no.c
@@ -68,9 +68,6 @@ void (*mach_power_off)(void);
68#define CPU_NAME "MC68000" 68#define CPU_NAME "MC68000"
69#endif 69#endif
70#endif /* CONFIG_M68000 */ 70#endif /* CONFIG_M68000 */
71#ifdef CONFIG_M68360
72#define CPU_NAME "MC68360"
73#endif
74#ifndef CPU_NAME 71#ifndef CPU_NAME
75#define CPU_NAME "UNKNOWN" 72#define CPU_NAME "UNKNOWN"
76#endif 73#endif
@@ -209,10 +206,6 @@ void __init setup_arch(char **cmdline_p)
209#if defined( CONFIG_PILOT ) && defined( CONFIG_M68EZ328 ) 206#if defined( CONFIG_PILOT ) && defined( CONFIG_M68EZ328 )
210 printk(KERN_INFO "PalmV support by Lineo Inc. <jeff@uclinux.com>\n"); 207 printk(KERN_INFO "PalmV support by Lineo Inc. <jeff@uclinux.com>\n");
211#endif 208#endif
212#if defined (CONFIG_M68360)
213 printk(KERN_INFO "QUICC port done by SED Systems <hamilton@sedsystems.ca>,\n");
214 printk(KERN_INFO "based on 2.0.38 port by Lineo Inc. <mleslie@lineo.com>.\n");
215#endif
216#ifdef CONFIG_DRAGEN2 209#ifdef CONFIG_DRAGEN2
217 printk(KERN_INFO "DragonEngine II board support by Georges Menie\n"); 210 printk(KERN_INFO "DragonEngine II board support by Georges Menie\n");
218#endif 211#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-25 05:29:59 -0400