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-rw-r--r--arch/sh/include/uapi/asm/cpu-features.h1
-rw-r--r--arch/sh/kernel/cpu/sh2/probe.c2
2 files changed, 3 insertions, 0 deletions
diff --git a/arch/sh/include/uapi/asm/cpu-features.h b/arch/sh/include/uapi/asm/cpu-features.h
index 694abe490edb..2f1bc851042a 100644
--- a/arch/sh/include/uapi/asm/cpu-features.h
+++ b/arch/sh/include/uapi/asm/cpu-features.h
@@ -22,5 +22,6 @@
22#define CPU_HAS_L2_CACHE 0x0080 /* Secondary cache / URAM */ 22#define CPU_HAS_L2_CACHE 0x0080 /* Secondary cache / URAM */
23#define CPU_HAS_OP32 0x0100 /* 32-bit instruction support */ 23#define CPU_HAS_OP32 0x0100 /* 32-bit instruction support */
24#define CPU_HAS_PTEAEX 0x0200 /* PTE ASID Extension support */ 24#define CPU_HAS_PTEAEX 0x0200 /* PTE ASID Extension support */
25#define CPU_HAS_CAS_L 0x0400 /* cas.l atomic compare-and-swap */
25 26
26#endif /* __ASM_SH_CPU_FEATURES_H */ 27#endif /* __ASM_SH_CPU_FEATURES_H */
diff --git a/arch/sh/kernel/cpu/sh2/probe.c b/arch/sh/kernel/cpu/sh2/probe.c
index 152184007964..4205f6d42b69 100644
--- a/arch/sh/kernel/cpu/sh2/probe.c
+++ b/arch/sh/kernel/cpu/sh2/probe.c
@@ -57,6 +57,8 @@ void __ref cpu_probe(void)
57 boot_cpu_data.dcache.entry_shift = 5; 57 boot_cpu_data.dcache.entry_shift = 5;
58 boot_cpu_data.dcache.linesz = 32; 58 boot_cpu_data.dcache.linesz = 32;
59 boot_cpu_data.dcache.flags = 0; 59 boot_cpu_data.dcache.flags = 0;
60
61 boot_cpu_data.flags |= CPU_HAS_CAS_L;
60#else 62#else
61 /* 63 /*
62 * SH-2 doesn't have separate caches 64 * SH-2 doesn't have separate caches