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authorKrzysztof Kozlowski <krzk@kernel.org>2017-12-26 08:07:18 -0500
committerInki Dae <inki.dae@samsung.com>2018-01-01 18:38:00 -0500
commit4f52e55081fb81d6348ecca1f5e2cd45480ca559 (patch)
tree3b589a689199af57108581da46c8533dff51af03 /include/video
parentcb30701b7482cfe2e03ca6186b7c89043faa1f25 (diff)
drm/exynos/decon: Move headers from global to local place
The DECON headers contain only defines for registers. There are no other drivers using them so this should be put locally to the Exynos DRM driver. Keeping headers local helps managing the code. Suggested-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Inki Dae <inki.dae@samsung.com>
Diffstat (limited to 'include/video')
-rw-r--r--include/video/exynos5433_decon.h209
-rw-r--r--include/video/exynos7_decon.h349
2 files changed, 0 insertions, 558 deletions
diff --git a/include/video/exynos5433_decon.h b/include/video/exynos5433_decon.h
deleted file mode 100644
index 78957c9626f5..000000000000
--- a/include/video/exynos5433_decon.h
+++ /dev/null
@@ -1,209 +0,0 @@
1/*
2 * Copyright (C) 2014 Samsung Electronics Co.Ltd
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundationr
7 */
8
9#ifndef EXYNOS_REGS_DECON_H
10#define EXYNOS_REGS_DECON_H
11
12/* Exynos543X DECON */
13#define DECON_VIDCON0 0x0000
14#define DECON_VIDOUTCON0 0x0010
15#define DECON_WINCONx(n) (0x0020 + ((n) * 4))
16#define DECON_VIDOSDxH(n) (0x0080 + ((n) * 4))
17#define DECON_SHADOWCON 0x00A0
18#define DECON_VIDOSDxA(n) (0x00B0 + ((n) * 0x20))
19#define DECON_VIDOSDxB(n) (0x00B4 + ((n) * 0x20))
20#define DECON_VIDOSDxC(n) (0x00B8 + ((n) * 0x20))
21#define DECON_VIDOSDxD(n) (0x00BC + ((n) * 0x20))
22#define DECON_VIDOSDxE(n) (0x00C0 + ((n) * 0x20))
23#define DECON_VIDW0xADD0B0(n) (0x0150 + ((n) * 0x10))
24#define DECON_VIDW0xADD0B1(n) (0x0154 + ((n) * 0x10))
25#define DECON_VIDW0xADD0B2(n) (0x0158 + ((n) * 0x10))
26#define DECON_VIDW0xADD1B0(n) (0x01A0 + ((n) * 0x10))
27#define DECON_VIDW0xADD1B1(n) (0x01A4 + ((n) * 0x10))
28#define DECON_VIDW0xADD1B2(n) (0x01A8 + ((n) * 0x10))
29#define DECON_VIDW0xADD2(n) (0x0200 + ((n) * 4))
30#define DECON_LOCALxSIZE(n) (0x0214 + ((n) * 4))
31#define DECON_VIDINTCON0 0x0220
32#define DECON_VIDINTCON1 0x0224
33#define DECON_WxKEYCON0(n) (0x0230 + ((n - 1) * 8))
34#define DECON_WxKEYCON1(n) (0x0234 + ((n - 1) * 8))
35#define DECON_WxKEYALPHA(n) (0x0250 + ((n - 1) * 4))
36#define DECON_WINxMAP(n) (0x0270 + ((n) * 4))
37#define DECON_QOSLUT07_00 0x02C0
38#define DECON_QOSLUT15_08 0x02C4
39#define DECON_QOSCTRL 0x02C8
40#define DECON_BLENDERQx(n) (0x0300 + ((n - 1) * 4))
41#define DECON_BLENDCON 0x0310
42#define DECON_OPE_VIDW0xADD0(n) (0x0400 + ((n) * 4))
43#define DECON_OPE_VIDW0xADD1(n) (0x0414 + ((n) * 4))
44#define DECON_FRAMEFIFO_REG7 0x051C
45#define DECON_FRAMEFIFO_REG8 0x0520
46#define DECON_FRAMEFIFO_STATUS 0x0524
47#define DECON_CMU 0x1404
48#define DECON_UPDATE 0x1410
49#define DECON_CRFMID 0x1414
50#define DECON_UPDATE_SCHEME 0x1438
51#define DECON_VIDCON1 0x2000
52#define DECON_VIDCON2 0x2004
53#define DECON_VIDCON3 0x2008
54#define DECON_VIDCON4 0x200C
55#define DECON_VIDTCON2 0x2028
56#define DECON_FRAME_SIZE 0x2038
57#define DECON_LINECNT_OP_THRESHOLD 0x203C
58#define DECON_TRIGCON 0x2040
59#define DECON_TRIGSKIP 0x2050
60#define DECON_CRCRDATA 0x20B0
61#define DECON_CRCCTRL 0x20B4
62
63/* Exynos5430 DECON */
64#define DECON_VIDTCON0 0x2020
65#define DECON_VIDTCON1 0x2024
66
67/* Exynos5433 DECON */
68#define DECON_VIDTCON00 0x2010
69#define DECON_VIDTCON01 0x2014
70#define DECON_VIDTCON10 0x2018
71#define DECON_VIDTCON11 0x201C
72
73/* Exynos543X DECON Internal */
74#define DECON_W013DSTREOCON 0x0320
75#define DECON_W233DSTREOCON 0x0324
76#define DECON_FRAMEFIFO_REG0 0x0500
77#define DECON_ENHANCER_CTRL 0x2100
78
79/* Exynos543X DECON TV */
80#define DECON_VCLKCON0 0x0014
81#define DECON_VIDINTCON2 0x0228
82#define DECON_VIDINTCON3 0x022C
83
84/* VIDCON0 */
85#define VIDCON0_SWRESET (1 << 28)
86#define VIDCON0_CLKVALUP (1 << 14)
87#define VIDCON0_VLCKFREE (1 << 5)
88#define VIDCON0_STOP_STATUS (1 << 2)
89#define VIDCON0_ENVID (1 << 1)
90#define VIDCON0_ENVID_F (1 << 0)
91
92/* VIDOUTCON0 */
93#define VIDOUT_INTERLACE_FIELD_F (1 << 29)
94#define VIDOUT_INTERLACE_EN_F (1 << 28)
95#define VIDOUT_LCD_ON (1 << 24)
96#define VIDOUT_IF_F_MASK (0x3 << 20)
97#define VIDOUT_RGB_IF (0x0 << 20)
98#define VIDOUT_COMMAND_IF (0x2 << 20)
99
100/* WINCONx */
101#define WINCONx_HAWSWP_F (1 << 16)
102#define WINCONx_WSWP_F (1 << 15)
103#define WINCONx_BURSTLEN_MASK (0x3 << 10)
104#define WINCONx_BURSTLEN_16WORD (0x0 << 10)
105#define WINCONx_BURSTLEN_8WORD (0x1 << 10)
106#define WINCONx_BURSTLEN_4WORD (0x2 << 10)
107#define WINCONx_BLD_PIX_F (1 << 6)
108#define WINCONx_BPPMODE_MASK (0xf << 2)
109#define WINCONx_BPPMODE_16BPP_565 (0x5 << 2)
110#define WINCONx_BPPMODE_16BPP_A1555 (0x6 << 2)
111#define WINCONx_BPPMODE_16BPP_I1555 (0x7 << 2)
112#define WINCONx_BPPMODE_24BPP_888 (0xb << 2)
113#define WINCONx_BPPMODE_24BPP_A1887 (0xc << 2)
114#define WINCONx_BPPMODE_25BPP_A1888 (0xd << 2)
115#define WINCONx_BPPMODE_32BPP_A8888 (0xd << 2)
116#define WINCONx_BPPMODE_16BPP_A4444 (0xe << 2)
117#define WINCONx_ALPHA_SEL_F (1 << 1)
118#define WINCONx_ENWIN_F (1 << 0)
119
120/* SHADOWCON */
121#define SHADOWCON_PROTECT_MASK GENMASK(14, 10)
122#define SHADOWCON_Wx_PROTECT(n) (1 << (10 + (n)))
123
124/* VIDOSDxD */
125#define VIDOSD_Wx_ALPHA_R_F(n) (((n) & 0xff) << 16)
126#define VIDOSD_Wx_ALPHA_G_F(n) (((n) & 0xff) << 8)
127#define VIDOSD_Wx_ALPHA_B_F(n) (((n) & 0xff) << 0)
128
129/* VIDINTCON0 */
130#define VIDINTCON0_FRAMEDONE (1 << 17)
131#define VIDINTCON0_FRAMESEL_BP (0 << 15)
132#define VIDINTCON0_FRAMESEL_VS (1 << 15)
133#define VIDINTCON0_FRAMESEL_AC (2 << 15)
134#define VIDINTCON0_FRAMESEL_FP (3 << 15)
135#define VIDINTCON0_INTFRMEN (1 << 12)
136#define VIDINTCON0_INTEN (1 << 0)
137
138/* VIDINTCON1 */
139#define VIDINTCON1_INTFRMDONEPEND (1 << 2)
140#define VIDINTCON1_INTFRMPEND (1 << 1)
141#define VIDINTCON1_INTFIFOPEND (1 << 0)
142
143/* DECON_CMU */
144#define CMU_CLKGAGE_MODE_SFR_F (1 << 1)
145#define CMU_CLKGAGE_MODE_MEM_F (1 << 0)
146
147/* DECON_UPDATE */
148#define STANDALONE_UPDATE_F (1 << 0)
149
150/* DECON_VIDCON1 */
151#define VIDCON1_LINECNT_MASK (0x0fff << 16)
152#define VIDCON1_I80_ACTIVE (1 << 15)
153#define VIDCON1_VSTATUS_MASK (0x3 << 13)
154#define VIDCON1_VSTATUS_VS (0 << 13)
155#define VIDCON1_VSTATUS_BP (1 << 13)
156#define VIDCON1_VSTATUS_AC (2 << 13)
157#define VIDCON1_VSTATUS_FP (3 << 13)
158#define VIDCON1_VCLK_MASK (0x3 << 9)
159#define VIDCON1_VCLK_RUN_VDEN_DISABLE (0x3 << 9)
160#define VIDCON1_VCLK_HOLD (0x0 << 9)
161#define VIDCON1_VCLK_RUN (0x1 << 9)
162
163
164/* DECON_VIDTCON00 */
165#define VIDTCON00_VBPD_F(x) (((x) & 0xfff) << 16)
166#define VIDTCON00_VFPD_F(x) ((x) & 0xfff)
167
168/* DECON_VIDTCON01 */
169#define VIDTCON01_VSPW_F(x) (((x) & 0xfff) << 16)
170
171/* DECON_VIDTCON10 */
172#define VIDTCON10_HBPD_F(x) (((x) & 0xfff) << 16)
173#define VIDTCON10_HFPD_F(x) ((x) & 0xfff)
174
175/* DECON_VIDTCON11 */
176#define VIDTCON11_HSPW_F(x) (((x) & 0xfff) << 16)
177
178/* DECON_VIDTCON2 */
179#define VIDTCON2_LINEVAL(x) (((x) & 0xfff) << 16)
180#define VIDTCON2_HOZVAL(x) ((x) & 0xfff)
181
182/* TRIGCON */
183#define TRIGCON_TRIGEN_PER_F (1 << 31)
184#define TRIGCON_TRIGEN_F (1 << 30)
185#define TRIGCON_TE_AUTO_MASK (1 << 29)
186#define TRIGCON_WB_SWTRIGCMD (1 << 28)
187#define TRIGCON_SWTRIGCMD_W4BUF (1 << 26)
188#define TRIGCON_TRIGMODE_W4BUF (1 << 25)
189#define TRIGCON_SWTRIGCMD_W3BUF (1 << 21)
190#define TRIGCON_TRIGMODE_W3BUF (1 << 20)
191#define TRIGCON_SWTRIGCMD_W2BUF (1 << 16)
192#define TRIGCON_TRIGMODE_W2BUF (1 << 15)
193#define TRIGCON_SWTRIGCMD_W1BUF (1 << 11)
194#define TRIGCON_TRIGMODE_W1BUF (1 << 10)
195#define TRIGCON_SWTRIGCMD_W0BUF (1 << 6)
196#define TRIGCON_TRIGMODE_W0BUF (1 << 5)
197#define TRIGCON_HWTRIGMASK (1 << 4)
198#define TRIGCON_HWTRIGEN (1 << 3)
199#define TRIGCON_HWTRIG_INV (1 << 2)
200#define TRIGCON_SWTRIGCMD (1 << 1)
201#define TRIGCON_SWTRIGEN (1 << 0)
202
203/* DECON_CRCCTRL */
204#define CRCCTRL_CRCCLKEN (0x1 << 2)
205#define CRCCTRL_CRCSTART_F (0x1 << 1)
206#define CRCCTRL_CRCEN (0x1 << 0)
207#define CRCCTRL_MASK (0x7)
208
209#endif /* EXYNOS_REGS_DECON_H */
diff --git a/include/video/exynos7_decon.h b/include/video/exynos7_decon.h
deleted file mode 100644
index a62b11b613f6..000000000000
--- a/include/video/exynos7_decon.h
+++ /dev/null
@@ -1,349 +0,0 @@
1/* include/video/exynos7_decon.h
2 *
3 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
4 * Author: Ajay Kumar <ajaykumar.rs@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/* VIDCON0 */
13#define VIDCON0 0x00
14
15#define VIDCON0_SWRESET (1 << 28)
16#define VIDCON0_DECON_STOP_STATUS (1 << 2)
17#define VIDCON0_ENVID (1 << 1)
18#define VIDCON0_ENVID_F (1 << 0)
19
20/* VIDOUTCON0 */
21#define VIDOUTCON0 0x4
22
23#define VIDOUTCON0_DUAL_MASK (0x3 << 24)
24#define VIDOUTCON0_DUAL_ON (0x3 << 24)
25#define VIDOUTCON0_DISP_IF_1_ON (0x2 << 24)
26#define VIDOUTCON0_DISP_IF_0_ON (0x1 << 24)
27#define VIDOUTCON0_DUAL_OFF (0x0 << 24)
28#define VIDOUTCON0_IF_SHIFT 23
29#define VIDOUTCON0_IF_MASK (0x1 << 23)
30#define VIDOUTCON0_RGBIF (0x0 << 23)
31#define VIDOUTCON0_I80IF (0x1 << 23)
32
33/* VIDCON3 */
34#define VIDCON3 0x8
35
36/* VIDCON4 */
37#define VIDCON4 0xC
38#define VIDCON4_FIFOCNT_START_EN (1 << 0)
39
40/* VCLKCON0 */
41#define VCLKCON0 0x10
42#define VCLKCON0_CLKVALUP (1 << 8)
43#define VCLKCON0_VCLKFREE (1 << 0)
44
45/* VCLKCON */
46#define VCLKCON1 0x14
47#define VCLKCON1_CLKVAL_NUM_VCLK(val) (((val) & 0xff) << 0)
48#define VCLKCON2 0x18
49
50/* SHADOWCON */
51#define SHADOWCON 0x30
52
53#define SHADOWCON_WINx_PROTECT(_win) (1 << (10 + (_win)))
54
55/* WINCONx */
56#define WINCON(_win) (0x50 + ((_win) * 4))
57
58#define WINCONx_BUFSTATUS (0x3 << 30)
59#define WINCONx_BUFSEL_MASK (0x3 << 28)
60#define WINCONx_BUFSEL_SHIFT 28
61#define WINCONx_TRIPLE_BUF_MODE (0x1 << 18)
62#define WINCONx_DOUBLE_BUF_MODE (0x0 << 18)
63#define WINCONx_BURSTLEN_16WORD (0x0 << 11)
64#define WINCONx_BURSTLEN_8WORD (0x1 << 11)
65#define WINCONx_BURSTLEN_MASK (0x1 << 11)
66#define WINCONx_BURSTLEN_SHIFT 11
67#define WINCONx_BLD_PLANE (0 << 8)
68#define WINCONx_BLD_PIX (1 << 8)
69#define WINCONx_ALPHA_MUL (1 << 7)
70
71#define WINCONx_BPPMODE_MASK (0xf << 2)
72#define WINCONx_BPPMODE_SHIFT 2
73#define WINCONx_BPPMODE_16BPP_565 (0x8 << 2)
74#define WINCONx_BPPMODE_24BPP_BGRx (0x7 << 2)
75#define WINCONx_BPPMODE_24BPP_RGBx (0x6 << 2)
76#define WINCONx_BPPMODE_24BPP_xBGR (0x5 << 2)
77#define WINCONx_BPPMODE_24BPP_xRGB (0x4 << 2)
78#define WINCONx_BPPMODE_32BPP_BGRA (0x3 << 2)
79#define WINCONx_BPPMODE_32BPP_RGBA (0x2 << 2)
80#define WINCONx_BPPMODE_32BPP_ABGR (0x1 << 2)
81#define WINCONx_BPPMODE_32BPP_ARGB (0x0 << 2)
82#define WINCONx_ALPHA_SEL (1 << 1)
83#define WINCONx_ENWIN (1 << 0)
84
85#define WINCON1_ALPHA_MUL_F (1 << 7)
86#define WINCON2_ALPHA_MUL_F (1 << 7)
87#define WINCON3_ALPHA_MUL_F (1 << 7)
88#define WINCON4_ALPHA_MUL_F (1 << 7)
89
90/* VIDOSDxH: The height for the OSD image(READ ONLY)*/
91#define VIDOSD_H(_x) (0x80 + ((_x) * 4))
92
93/* Frame buffer start addresses: VIDWxxADD0n */
94#define VIDW_BUF_START(_win) (0x80 + ((_win) * 0x10))
95#define VIDW_BUF_START1(_win) (0x84 + ((_win) * 0x10))
96#define VIDW_BUF_START2(_win) (0x88 + ((_win) * 0x10))
97
98#define VIDW_WHOLE_X(_win) (0x0130 + ((_win) * 8))
99#define VIDW_WHOLE_Y(_win) (0x0134 + ((_win) * 8))
100#define VIDW_OFFSET_X(_win) (0x0170 + ((_win) * 8))
101#define VIDW_OFFSET_Y(_win) (0x0174 + ((_win) * 8))
102#define VIDW_BLKOFFSET(_win) (0x01B0 + ((_win) * 4))
103#define VIDW_BLKSIZE(win) (0x0200 + ((_win) * 4))
104
105/* Interrupt controls register */
106#define VIDINTCON2 0x228
107
108#define VIDINTCON1_INTEXTRA1_EN (1 << 1)
109#define VIDINTCON1_INTEXTRA0_EN (1 << 0)
110
111/* Interrupt controls and status register */
112#define VIDINTCON3 0x22C
113
114#define VIDINTCON1_INTEXTRA1_PEND (1 << 1)
115#define VIDINTCON1_INTEXTRA0_PEND (1 << 0)
116
117/* VIDOSDxA ~ VIDOSDxE */
118#define VIDOSD_BASE 0x230
119
120#define OSD_STRIDE 0x20
121
122#define VIDOSD_A(_win) (VIDOSD_BASE + \
123 ((_win) * OSD_STRIDE) + 0x00)
124#define VIDOSD_B(_win) (VIDOSD_BASE + \
125 ((_win) * OSD_STRIDE) + 0x04)
126#define VIDOSD_C(_win) (VIDOSD_BASE + \
127 ((_win) * OSD_STRIDE) + 0x08)
128#define VIDOSD_D(_win) (VIDOSD_BASE + \
129 ((_win) * OSD_STRIDE) + 0x0C)
130#define VIDOSD_E(_win) (VIDOSD_BASE + \
131 ((_win) * OSD_STRIDE) + 0x10)
132
133#define VIDOSDxA_TOPLEFT_X_MASK (0x1fff << 13)
134#define VIDOSDxA_TOPLEFT_X_SHIFT 13
135#define VIDOSDxA_TOPLEFT_X_LIMIT 0x1fff
136#define VIDOSDxA_TOPLEFT_X(_x) (((_x) & 0x1fff) << 13)
137
138#define VIDOSDxA_TOPLEFT_Y_MASK (0x1fff << 0)
139#define VIDOSDxA_TOPLEFT_Y_SHIFT 0
140#define VIDOSDxA_TOPLEFT_Y_LIMIT 0x1fff
141#define VIDOSDxA_TOPLEFT_Y(_x) (((_x) & 0x1fff) << 0)
142
143#define VIDOSDxB_BOTRIGHT_X_MASK (0x1fff << 13)
144#define VIDOSDxB_BOTRIGHT_X_SHIFT 13
145#define VIDOSDxB_BOTRIGHT_X_LIMIT 0x1fff
146#define VIDOSDxB_BOTRIGHT_X(_x) (((_x) & 0x1fff) << 13)
147
148#define VIDOSDxB_BOTRIGHT_Y_MASK (0x1fff << 0)
149#define VIDOSDxB_BOTRIGHT_Y_SHIFT 0
150#define VIDOSDxB_BOTRIGHT_Y_LIMIT 0x1fff
151#define VIDOSDxB_BOTRIGHT_Y(_x) (((_x) & 0x1fff) << 0)
152
153#define VIDOSDxC_ALPHA0_R_F(_x) (((_x) & 0xFF) << 16)
154#define VIDOSDxC_ALPHA0_G_F(_x) (((_x) & 0xFF) << 8)
155#define VIDOSDxC_ALPHA0_B_F(_x) (((_x) & 0xFF) << 0)
156
157#define VIDOSDxD_ALPHA1_R_F(_x) (((_x) & 0xFF) << 16)
158#define VIDOSDxD_ALPHA1_G_F(_x) (((_x) & 0xFF) << 8)
159#define VIDOSDxD_ALPHA1_B_F(_x) (((_x) & 0xFF) >> 0)
160
161/* Window MAP (Color map) */
162#define WINxMAP(_win) (0x340 + ((_win) * 4))
163
164#define WINxMAP_MAP (1 << 24)
165#define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0)
166#define WINxMAP_MAP_COLOUR_SHIFT 0
167#define WINxMAP_MAP_COLOUR_LIMIT 0xffffff
168#define WINxMAP_MAP_COLOUR(_x) ((_x) << 0)
169
170/* Window colour-key control registers */
171#define WKEYCON 0x370
172
173#define WKEYCON0 0x00
174#define WKEYCON1 0x04
175#define WxKEYCON0_KEYBL_EN (1 << 26)
176#define WxKEYCON0_KEYEN_F (1 << 25)
177#define WxKEYCON0_DIRCON (1 << 24)
178#define WxKEYCON0_COMPKEY_MASK (0xffffff << 0)
179#define WxKEYCON0_COMPKEY_SHIFT 0
180#define WxKEYCON0_COMPKEY_LIMIT 0xffffff
181#define WxKEYCON0_COMPKEY(_x) ((_x) << 0)
182#define WxKEYCON1_COLVAL_MASK (0xffffff << 0)
183#define WxKEYCON1_COLVAL_SHIFT 0
184#define WxKEYCON1_COLVAL_LIMIT 0xffffff
185#define WxKEYCON1_COLVAL(_x) ((_x) << 0)
186
187/* color key control register for hardware window 1 ~ 4. */
188#define WKEYCON0_BASE(x) ((WKEYCON + WKEYCON0) + ((x - 1) * 8))
189/* color key value register for hardware window 1 ~ 4. */
190#define WKEYCON1_BASE(x) ((WKEYCON + WKEYCON1) + ((x - 1) * 8))
191
192/* Window KEY Alpha value */
193#define WxKEYALPHA(_win) (0x3A0 + (((_win) - 1) * 0x4))
194
195#define Wx_KEYALPHA_R_F_SHIFT 16
196#define Wx_KEYALPHA_G_F_SHIFT 8
197#define Wx_KEYALPHA_B_F_SHIFT 0
198
199/* Blending equation */
200#define BLENDE(_win) (0x03C0 + ((_win) * 4))
201#define BLENDE_COEF_ZERO 0x0
202#define BLENDE_COEF_ONE 0x1
203#define BLENDE_COEF_ALPHA_A 0x2
204#define BLENDE_COEF_ONE_MINUS_ALPHA_A 0x3
205#define BLENDE_COEF_ALPHA_B 0x4
206#define BLENDE_COEF_ONE_MINUS_ALPHA_B 0x5
207#define BLENDE_COEF_ALPHA0 0x6
208#define BLENDE_COEF_A 0xA
209#define BLENDE_COEF_ONE_MINUS_A 0xB
210#define BLENDE_COEF_B 0xC
211#define BLENDE_COEF_ONE_MINUS_B 0xD
212#define BLENDE_Q_FUNC(_v) ((_v) << 18)
213#define BLENDE_P_FUNC(_v) ((_v) << 12)
214#define BLENDE_B_FUNC(_v) ((_v) << 6)
215#define BLENDE_A_FUNC(_v) ((_v) << 0)
216
217/* Blending equation control */
218#define BLENDCON 0x3D8
219#define BLENDCON_NEW_MASK (1 << 0)
220#define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
221#define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
222
223/* Interrupt control register */
224#define VIDINTCON0 0x500
225
226#define VIDINTCON0_WAKEUP_MASK (0x3f << 26)
227#define VIDINTCON0_INTEXTRAEN (1 << 21)
228
229#define VIDINTCON0_FRAMESEL0_SHIFT 15
230#define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15)
231#define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15)
232#define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15)
233#define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15)
234#define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15)
235
236#define VIDINTCON0_INT_FRAME (1 << 11)
237
238#define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 3)
239#define VIDINTCON0_FIFOLEVEL_SHIFT 3
240#define VIDINTCON0_FIFOLEVEL_EMPTY (0x0 << 3)
241#define VIDINTCON0_FIFOLEVEL_TO25PC (0x1 << 3)
242#define VIDINTCON0_FIFOLEVEL_TO50PC (0x2 << 3)
243#define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 3)
244
245#define VIDINTCON0_FIFOSEL_MAIN_EN (1 << 1)
246#define VIDINTCON0_INT_FIFO (1 << 1)
247
248#define VIDINTCON0_INT_ENABLE (1 << 0)
249
250/* Interrupt controls and status register */
251#define VIDINTCON1 0x504
252
253#define VIDINTCON1_INT_EXTRA (1 << 3)
254#define VIDINTCON1_INT_I80 (1 << 2)
255#define VIDINTCON1_INT_FRAME (1 << 1)
256#define VIDINTCON1_INT_FIFO (1 << 0)
257
258/* VIDCON1 */
259#define VIDCON1(_x) (0x0600 + ((_x) * 0x50))
260#define VIDCON1_LINECNT_GET(_v) (((_v) >> 17) & 0x1fff)
261#define VIDCON1_VCLK_MASK (0x3 << 9)
262#define VIDCON1_VCLK_HOLD (0x0 << 9)
263#define VIDCON1_VCLK_RUN (0x1 << 9)
264#define VIDCON1_VCLK_RUN_VDEN_DISABLE (0x3 << 9)
265#define VIDCON1_RGB_ORDER_O_MASK (0x7 << 4)
266#define VIDCON1_RGB_ORDER_O_RGB (0x0 << 4)
267#define VIDCON1_RGB_ORDER_O_GBR (0x1 << 4)
268#define VIDCON1_RGB_ORDER_O_BRG (0x2 << 4)
269#define VIDCON1_RGB_ORDER_O_BGR (0x4 << 4)
270#define VIDCON1_RGB_ORDER_O_RBG (0x5 << 4)
271#define VIDCON1_RGB_ORDER_O_GRB (0x6 << 4)
272
273/* VIDTCON0 */
274#define VIDTCON0 0x610
275
276#define VIDTCON0_VBPD_MASK (0xffff << 16)
277#define VIDTCON0_VBPD_SHIFT 16
278#define VIDTCON0_VBPD_LIMIT 0xffff
279#define VIDTCON0_VBPD(_x) ((_x) << 16)
280
281#define VIDTCON0_VFPD_MASK (0xffff << 0)
282#define VIDTCON0_VFPD_SHIFT 0
283#define VIDTCON0_VFPD_LIMIT 0xffff
284#define VIDTCON0_VFPD(_x) ((_x) << 0)
285
286/* VIDTCON1 */
287#define VIDTCON1 0x614
288
289#define VIDTCON1_VSPW_MASK (0xffff << 16)
290#define VIDTCON1_VSPW_SHIFT 16
291#define VIDTCON1_VSPW_LIMIT 0xffff
292#define VIDTCON1_VSPW(_x) ((_x) << 16)
293
294/* VIDTCON2 */
295#define VIDTCON2 0x618
296
297#define VIDTCON2_HBPD_MASK (0xffff << 16)
298#define VIDTCON2_HBPD_SHIFT 16
299#define VIDTCON2_HBPD_LIMIT 0xffff
300#define VIDTCON2_HBPD(_x) ((_x) << 16)
301
302#define VIDTCON2_HFPD_MASK (0xffff << 0)
303#define VIDTCON2_HFPD_SHIFT 0
304#define VIDTCON2_HFPD_LIMIT 0xffff
305#define VIDTCON2_HFPD(_x) ((_x) << 0)
306
307/* VIDTCON3 */
308#define VIDTCON3 0x61C
309
310#define VIDTCON3_HSPW_MASK (0xffff << 16)
311#define VIDTCON3_HSPW_SHIFT 16
312#define VIDTCON3_HSPW_LIMIT 0xffff
313#define VIDTCON3_HSPW(_x) ((_x) << 16)
314
315/* VIDTCON4 */
316#define VIDTCON4 0x620
317
318#define VIDTCON4_LINEVAL_MASK (0xfff << 16)
319#define VIDTCON4_LINEVAL_SHIFT 16
320#define VIDTCON4_LINEVAL_LIMIT 0xfff
321#define VIDTCON4_LINEVAL(_x) (((_x) & 0xfff) << 16)
322
323#define VIDTCON4_HOZVAL_MASK (0xfff << 0)
324#define VIDTCON4_HOZVAL_SHIFT 0
325#define VIDTCON4_HOZVAL_LIMIT 0xfff
326#define VIDTCON4_HOZVAL(_x) (((_x) & 0xfff) << 0)
327
328/* LINECNT OP THRSHOLD*/
329#define LINECNT_OP_THRESHOLD 0x630
330
331/* CRCCTRL */
332#define CRCCTRL 0x6C8
333#define CRCCTRL_CRCCLKEN (0x1 << 2)
334#define CRCCTRL_CRCSTART_F (0x1 << 1)
335#define CRCCTRL_CRCEN (0x1 << 0)
336
337/* DECON_CMU */
338#define DECON_CMU 0x704
339
340#define DECON_CMU_ALL_CLKGATE_ENABLE 0x3
341#define DECON_CMU_SE_CLKGATE_ENABLE (0x1 << 2)
342#define DECON_CMU_SFR_CLKGATE_ENABLE (0x1 << 1)
343#define DECON_CMU_MEM_CLKGATE_ENABLE (0x1 << 0)
344
345/* DECON_UPDATE */
346#define DECON_UPDATE 0x710
347
348#define DECON_UPDATE_SLAVE_SYNC (1 << 4)
349#define DECON_UPDATE_STANDALONE_F (1 << 0)
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-03 01:09:55 -0400