Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC-related driver updates from Olof Johansson:
 "Various driver updates for platforms and a couple of the small driver
  subsystems we merge through our tree:

   - A driver for SCU (system control) on NXP i.MX8QXP

   - Qualcomm Always-on Subsystem messaging driver (AOSS QMP)

   - Qualcomm PM support for MSM8998

   - Support for a newer version of DRAM PHY driver for Broadcom (DPFE)

   - Reset controller support for Bitmain BM1880

   - TI SCI (System Control Interface) support for CPU control on AM654
     processors

   - More TI sysc refactoring and rework"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (84 commits)
  reset: remove redundant null check on pointer dev
  soc: rockchip: work around clang warning
  dt-bindings: reset: imx7: Fix the spelling of 'indices'
  soc: imx: Add i.MX8MN SoC driver support
  soc: aspeed: lpc-ctrl: Fix probe error handling
  soc: qcom: geni: Add support for ACPI
  firmware: ti_sci: Fix gcc unused-but-set-variable warning
  firmware: ti_sci: Use the correct style for SPDX License Identifier
  soc: imx8: Use existing of_root directly
  soc: imx8: Fix potential kernel dump in error path
  firmware/psci: psci_checker: Park kthreads before stopping them
  memory: move jedec_ddr.h from include/memory to drivers/memory/
  memory: move jedec_ddr_data.c from lib/ to drivers/memory/
  MAINTAINERS: Remove myself as qcom maintainer
  soc: aspeed: lpc-ctrl: make parameter optional
  soc: qcom: apr: Don't use reg for domain id
  soc: qcom: fix QCOM_AOSS_QMP dependency and build errors
  memory: tegra: Fix -Wunused-const-variable
  firmware: tegra: Early resume BPMP
  soc/tegra: Select pinctrl for Tegra194
  ...

1 files changed, 246 insertions, 0 deletions

diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h
index 406e6717d252..6c610e188a44 100644
--- a/include/linux/soc/ti/ti_sci_protocol.h
+++ b/include/linux/soc/ti/ti_sci_protocol.h
@@ -241,12 +241,254 @@ struct ti_sci_rm_irq_ops {
                               u16 global_event, u8 vint_status_bit);
 };
 
+/* RA config.addr_lo parameter is valid for RM ring configure TI_SCI message */
+#define TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID  BIT(0)
+/* RA config.addr_hi parameter is valid for RM ring configure TI_SCI message */
+#define TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID  BIT(1)
+ /* RA config.count parameter is valid for RM ring configure TI_SCI message */
+#define TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID    BIT(2)
+/* RA config.mode parameter is valid for RM ring configure TI_SCI message */
+#define TI_SCI_MSG_VALUE_RM_RING_MODE_VALID     BIT(3)
+/* RA config.size parameter is valid for RM ring configure TI_SCI message */
+#define TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID     BIT(4)
+/* RA config.order_id parameter is valid for RM ring configure TISCI message */
+#define TI_SCI_MSG_VALUE_RM_RING_ORDER_ID_VALID BIT(5)
+
+#define TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER \
+        (TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID | \
+        TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID | \
+        TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID | \
+        TI_SCI_MSG_VALUE_RM_RING_MODE_VALID | \
+        TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID)
+
+/**
+ * struct ti_sci_rm_ringacc_ops - Ring Accelerator Management operations
+ * @config: configure the SoC Navigator Subsystem Ring Accelerator ring
+ * @get_config: get the SoC Navigator Subsystem Ring Accelerator ring
+ *              configuration
+ */
+struct ti_sci_rm_ringacc_ops {
+        int (*config)(const struct ti_sci_handle *handle,
+                      u32 valid_params, u16 nav_id, u16 index,
+                      u32 addr_lo, u32 addr_hi, u32 count, u8 mode,
+                      u8 size, u8 order_id
+        );
+        int (*get_config)(const struct ti_sci_handle *handle,
+                          u32 nav_id, u32 index, u8 *mode,
+                          u32 *addr_lo, u32 *addr_hi, u32 *count,
+                          u8 *size, u8 *order_id);
+};
+
+/**
+ * struct ti_sci_rm_psil_ops - PSI-L thread operations
+ * @pair: pair PSI-L source thread to a destination thread.
+ *      If the src_thread is mapped to UDMA tchan, the corresponding channel's
+ *      TCHAN_THRD_ID register is updated.
+ *      If the dst_thread is mapped to UDMA rchan, the corresponding channel's
+ *      RCHAN_THRD_ID register is updated.
+ * @unpair: unpair PSI-L source thread from a destination thread.
+ *      If the src_thread is mapped to UDMA tchan, the corresponding channel's
+ *      TCHAN_THRD_ID register is cleared.
+ *      If the dst_thread is mapped to UDMA rchan, the corresponding channel's
+ *      RCHAN_THRD_ID register is cleared.
+ */
+struct ti_sci_rm_psil_ops {
+        int (*pair)(const struct ti_sci_handle *handle, u32 nav_id,
+                    u32 src_thread, u32 dst_thread);
+        int (*unpair)(const struct ti_sci_handle *handle, u32 nav_id,
+                      u32 src_thread, u32 dst_thread);
+};
+
+/* UDMAP channel types */
+#define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR              2
+#define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR_SB           3       /* RX only */
+#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBRR             10
+#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBVR             11
+#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBRR       12
+#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBVR       13
+
+#define TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST               0
+#define TI_SCI_RM_UDMAP_RX_FLOW_DESC_MONO               2
+
+#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES        1
+#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_128_BYTES       2
+#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_256_BYTES       3
+
+/* UDMAP TX/RX channel valid_params common declarations */
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID         BIT(0)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID                BIT(1)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID            BIT(2)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID           BIT(3)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID              BIT(4)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PRIORITY_VALID             BIT(5)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_QOS_VALID                  BIT(6)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_VALID             BIT(7)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIORITY_VALID       BIT(8)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_VALID           BIT(14)
+
+/**
+ * Configures a Navigator Subsystem UDMAP transmit channel
+ *
+ * Configures a Navigator Subsystem UDMAP transmit channel registers.
+ * See @ti_sci_msg_rm_udmap_tx_ch_cfg_req
+ */
+struct ti_sci_msg_rm_udmap_tx_ch_cfg {
+        u32 valid_params;
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_EINFO_VALID        BIT(9)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_PSWORDS_VALID      BIT(10)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID        BIT(11)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID      BIT(12)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALID            BIT(13)
+        u16 nav_id;
+        u16 index;
+        u8 tx_pause_on_err;
+        u8 tx_filt_einfo;
+        u8 tx_filt_pswords;
+        u8 tx_atype;
+        u8 tx_chan_type;
+        u8 tx_supr_tdpkt;
+        u16 tx_fetch_size;
+        u8 tx_credit_count;
+        u16 txcq_qnum;
+        u8 tx_priority;
+        u8 tx_qos;
+        u8 tx_orderid;
+        u16 fdepth;
+        u8 tx_sched_priority;
+        u8 tx_burst_size;
+};
+
+/**
+ * Configures a Navigator Subsystem UDMAP receive channel
+ *
+ * Configures a Navigator Subsystem UDMAP receive channel registers.
+ * See @ti_sci_msg_rm_udmap_rx_ch_cfg_req
+ */
+struct ti_sci_msg_rm_udmap_rx_ch_cfg {
+        u32 valid_params;
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID      BIT(9)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID        BIT(10)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_SHORT_VALID      BIT(11)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_LONG_VALID       BIT(12)
+        u16 nav_id;
+        u16 index;
+        u16 rx_fetch_size;
+        u16 rxcq_qnum;
+        u8 rx_priority;
+        u8 rx_qos;
+        u8 rx_orderid;
+        u8 rx_sched_priority;
+        u16 flowid_start;
+        u16 flowid_cnt;
+        u8 rx_pause_on_err;
+        u8 rx_atype;
+        u8 rx_chan_type;
+        u8 rx_ignore_short;
+        u8 rx_ignore_long;
+        u8 rx_burst_size;
+};
+
+/**
+ * Configures a Navigator Subsystem UDMAP receive flow
+ *
+ * Configures a Navigator Subsystem UDMAP receive flow's registers.
+ * See @tis_ci_msg_rm_udmap_flow_cfg_req
+ */
+struct ti_sci_msg_rm_udmap_flow_cfg {
+        u32 valid_params;
+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID      BIT(0)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID     BIT(1)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID     BIT(2)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DESC_TYPE_VALID          BIT(3)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SOP_OFFSET_VALID         BIT(4)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID          BIT(5)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_VALID         BIT(6)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_VALID         BIT(7)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_VALID        BIT(8)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_VALID        BIT(9)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_SEL_VALID     BIT(10)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_SEL_VALID     BIT(11)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_SEL_VALID    BIT(12)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_SEL_VALID    BIT(13)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ0_QNUM_VALID      BIT(14)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ1_QNUM_VALID          BIT(15)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ2_QNUM_VALID          BIT(16)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID          BIT(17)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PS_LOCATION_VALID        BIT(18)
+        u16 nav_id;
+        u16 flow_index;
+        u8 rx_einfo_present;
+        u8 rx_psinfo_present;
+        u8 rx_error_handling;
+        u8 rx_desc_type;
+        u16 rx_sop_offset;
+        u16 rx_dest_qnum;
+        u8 rx_src_tag_hi;
+        u8 rx_src_tag_lo;
+        u8 rx_dest_tag_hi;
+        u8 rx_dest_tag_lo;
+        u8 rx_src_tag_hi_sel;
+        u8 rx_src_tag_lo_sel;
+        u8 rx_dest_tag_hi_sel;
+        u8 rx_dest_tag_lo_sel;
+        u16 rx_fdq0_sz0_qnum;
+        u16 rx_fdq1_qnum;
+        u16 rx_fdq2_qnum;
+        u16 rx_fdq3_qnum;
+        u8 rx_ps_location;
+};
+
+/**
+ * struct ti_sci_rm_udmap_ops - UDMA Management operations
+ * @tx_ch_cfg: configure SoC Navigator Subsystem UDMA transmit channel.
+ * @rx_ch_cfg: configure SoC Navigator Subsystem UDMA receive channel.
+ * @rx_flow_cfg1: configure SoC Navigator Subsystem UDMA receive flow.
+ */
+struct ti_sci_rm_udmap_ops {
+        int (*tx_ch_cfg)(const struct ti_sci_handle *handle,
+                         const struct ti_sci_msg_rm_udmap_tx_ch_cfg *params);
+        int (*rx_ch_cfg)(const struct ti_sci_handle *handle,
+                         const struct ti_sci_msg_rm_udmap_rx_ch_cfg *params);
+        int (*rx_flow_cfg)(const struct ti_sci_handle *handle,
+                           const struct ti_sci_msg_rm_udmap_flow_cfg *params);
+};
+
+/**
+ * struct ti_sci_proc_ops - Processor Control operations
+ * @request:    Request to control a physical processor. The requesting host
+ *              should be in the processor access list
+ * @release:    Relinquish a physical processor control
+ * @handover:   Handover a physical processor control to another host
+ *              in the permitted list
+ * @set_config: Set base configuration of a processor
+ * @set_control: Setup limited control flags in specific cases
+ * @get_status: Get the state of physical processor
+ *
+ * NOTE: The following paramteres are generic in nature for all these ops,
+ * -handle:     Pointer to TI SCI handle as retrieved by *ti_sci_get_handle
+ * -pid:        Processor ID
+ * -hid:        Host ID
+ */
+struct ti_sci_proc_ops {
+        int (*request)(const struct ti_sci_handle *handle, u8 pid);
+        int (*release)(const struct ti_sci_handle *handle, u8 pid);
+        int (*handover)(const struct ti_sci_handle *handle, u8 pid, u8 hid);
+        int (*set_config)(const struct ti_sci_handle *handle, u8 pid,
+                          u64 boot_vector, u32 cfg_set, u32 cfg_clr);
+        int (*set_control)(const struct ti_sci_handle *handle, u8 pid,
+                           u32 ctrl_set, u32 ctrl_clr);
+        int (*get_status)(const struct ti_sci_handle *handle, u8 pid,
+                          u64 *boot_vector, u32 *cfg_flags, u32 *ctrl_flags,
+                          u32 *status_flags);
+};
+
 /**
  * struct ti_sci_ops - Function support for TI SCI
  * @dev_ops:    Device specific operations
  * @clk_ops:    Clock specific operations
  * @rm_core_ops:        Resource management core operations.
  * @rm_irq_ops:         IRQ management specific operations
+ * @proc_ops:   Processor Control specific operations
  */
 struct ti_sci_ops {
         struct ti_sci_core_ops core_ops;
@@ -254,6 +496,10 @@ struct ti_sci_ops {
         struct ti_sci_clk_ops clk_ops;
         struct ti_sci_rm_core_ops rm_core_ops;
         struct ti_sci_rm_irq_ops rm_irq_ops;
+        struct ti_sci_rm_ringacc_ops rm_ring_ops;
+        struct ti_sci_rm_psil_ops rm_psil_ops;
+        struct ti_sci_rm_udmap_ops rm_udmap_ops;
+        struct ti_sci_proc_ops proc_ops;
 };
 
 /**