Merge tag 'reset-for-5.1' of git://git.pengutronix.de/git/pza/linux into arm/drivers

Reset controller changes for v5.1

This adds the include/linux/reset directory to MAINTAINERS for reset
specific headers and adds headers for sunxi and socfpga in there to
get rid of a few extern function declarations.
There is a new reset driver for the Broadcom STB reset controller and
the i.MX7 system reset controller driver is extended to support i.MX8MQ
as well. Finally, there is a new header with reset id constants for
the Meson G12A SoC, which has a reset controller identical to Meson AXG
and thus can reuse its driver and DT bindings.

* tag 'reset-for-5.1' of git://git.pengutronix.de/git/pza/linux:
  dt-bindings: reset: meson: add g12a bindings
  reset: imx7: Add support for i.MX8MQ IP block variant
  reset: imx7: Add plubming to support multiple IP variants
  reset: Add Broadcom STB SW_INIT reset controller driver
  dt-bindings: reset: Add document for Broadcom STB reset controller
  reset: socfpga: declare socfpga_reset_init in a header file
  reset: sunxi: declare sun6i_reset_init in a header file
  MAINTAINERS: use include/linux/reset for reset controller related headers
  dt-bindings: reset: imx7: Document usage on i.MX8MQ SoCs

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

6 files changed, 303 insertions, 17 deletions

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 2e01bd833ffd..2c8c23db92fb 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -40,6 +40,14 @@ config RESET_BERLIN
         help
           This enables the reset controller driver for Marvell Berlin SoCs.
 
+config RESET_BRCMSTB
+        tristate "Broadcom STB reset controller"
+        depends on ARCH_BRCMSTB || COMPILE_TEST
+        default ARCH_BRCMSTB
+        help
+          This enables the reset controller driver for Broadcom STB SoCs using
+          a SUN_TOP_CTRL_SW_INIT style controller.
+
 config RESET_HSDK
         bool "Synopsys HSDK Reset Driver"
         depends on HAS_IOMEM
@@ -48,9 +56,9 @@ config RESET_HSDK
           This enables the reset controller driver for HSDK board.
 
 config RESET_IMX7
-        bool "i.MX7 Reset Driver" if COMPILE_TEST
+        bool "i.MX7/8 Reset Driver" if COMPILE_TEST
         depends on HAS_IOMEM
-        default SOC_IMX7D
+        default SOC_IMX7D || (ARM64 && ARCH_MXC)
         select MFD_SYSCON
         help
           This enables the reset controller driver for i.MX7 SoCs.
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 573b8386d901..61456b8f659c 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
 obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
 obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o
 obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
+obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o
 obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
 obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
 obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
diff --git a/drivers/reset/reset-brcmstb.c b/drivers/reset/reset-brcmstb.c
new file mode 100644
index 000000000000..a608f445dad6
--- /dev/null
+++ b/drivers/reset/reset-brcmstb.c
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Broadcom STB generic reset controller for SW_INIT style reset controller
+ *
+ * Author: Florian Fainelli <f.fainelli@gmail.com>
+ * Copyright (C) 2018 Broadcom
+ */
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/types.h>
+
+struct brcmstb_reset {
+        void __iomem *base;
+        struct reset_controller_dev rcdev;
+};
+
+#define SW_INIT_SET             0x00
+#define SW_INIT_CLEAR           0x04
+#define SW_INIT_STATUS          0x08
+
+#define SW_INIT_BIT(id)         BIT((id) & 0x1f)
+#define SW_INIT_BANK(id)        ((id) >> 5)
+
+/* A full bank contains extra registers that we are not utilizing but still
+ * qualify as a single bank.
+ */
+#define SW_INIT_BANK_SIZE       0x18
+
+static inline
+struct brcmstb_reset *to_brcmstb(struct reset_controller_dev *rcdev)
+{
+        return container_of(rcdev, struct brcmstb_reset, rcdev);
+}
+
+static int brcmstb_reset_assert(struct reset_controller_dev *rcdev,
+                                unsigned long id)
+{
+        unsigned int off = SW_INIT_BANK(id) * SW_INIT_BANK_SIZE;
+        struct brcmstb_reset *priv = to_brcmstb(rcdev);
+
+        writel_relaxed(SW_INIT_BIT(id), priv->base + off + SW_INIT_SET);
+
+        return 0;
+}
+
+static int brcmstb_reset_deassert(struct reset_controller_dev *rcdev,
+                                  unsigned long id)
+{
+        unsigned int off = SW_INIT_BANK(id) * SW_INIT_BANK_SIZE;
+        struct brcmstb_reset *priv = to_brcmstb(rcdev);
+
+        writel_relaxed(SW_INIT_BIT(id), priv->base + off + SW_INIT_CLEAR);
+        /* Maximum reset delay after de-asserting a line and seeing block
+         * operation is typically 14us for the worst case, build some slack
+         * here.
+         */
+        usleep_range(100, 200);
+
+        return 0;
+}
+
+static int brcmstb_reset_status(struct reset_controller_dev *rcdev,
+                                unsigned long id)
+{
+        unsigned int off = SW_INIT_BANK(id) * SW_INIT_BANK_SIZE;
+        struct brcmstb_reset *priv = to_brcmstb(rcdev);
+
+        return readl_relaxed(priv->base + off + SW_INIT_STATUS) &
+                             SW_INIT_BIT(id);
+}
+
+static const struct reset_control_ops brcmstb_reset_ops = {
+        .assert = brcmstb_reset_assert,
+        .deassert = brcmstb_reset_deassert,
+        .status = brcmstb_reset_status,
+};
+
+static int brcmstb_reset_probe(struct platform_device *pdev)
+{
+        struct device *kdev = &pdev->dev;
+        struct brcmstb_reset *priv;
+        struct resource *res;
+
+        priv = devm_kzalloc(kdev, sizeof(*priv), GFP_KERNEL);
+        if (!priv)
+                return -ENOMEM;
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!IS_ALIGNED(res->start, SW_INIT_BANK_SIZE) ||
+            !IS_ALIGNED(resource_size(res), SW_INIT_BANK_SIZE)) {
+                dev_err(kdev, "incorrect register range\n");
+                return -EINVAL;
+        }
+
+        priv->base = devm_ioremap_resource(kdev, res);
+        if (IS_ERR(priv->base))
+                return PTR_ERR(priv->base);
+
+        dev_set_drvdata(kdev, priv);
+
+        priv->rcdev.owner = THIS_MODULE;
+        priv->rcdev.nr_resets = DIV_ROUND_DOWN_ULL(resource_size(res),
+                                                   SW_INIT_BANK_SIZE) * 32;
+        priv->rcdev.ops = &brcmstb_reset_ops;
+        priv->rcdev.of_node = kdev->of_node;
+        /* Use defaults: 1 cell and simple xlate function */
+
+        return devm_reset_controller_register(kdev, &priv->rcdev);
+}
+
+static const struct of_device_id brcmstb_reset_of_match[] = {
+        { .compatible = "brcm,brcmstb-reset" },
+        { /* sentinel */ }
+};
+
+static struct platform_driver brcmstb_reset_driver = {
+        .probe  = brcmstb_reset_probe,
+        .driver = {
+                .name = "brcmstb-reset",
+                .of_match_table = brcmstb_reset_of_match,
+        },
+};
+module_platform_driver(brcmstb_reset_driver);
+
+MODULE_AUTHOR("Broadcom");
+MODULE_DESCRIPTION("Broadcom STB reset controller");
+MODULE_LICENSE("GPL");
diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c
index 77911fa8f31d..aed76e33a0a9 100644
--- a/drivers/reset/reset-imx7.c
+++ b/drivers/reset/reset-imx7.c
@@ -17,14 +17,27 @@
 
 #include <linux/mfd/syscon.h>
 #include <linux/mod_devicetable.h>
+#include <linux/of_device.h>
 #include <linux/platform_device.h>
 #include <linux/reset-controller.h>
 #include <linux/regmap.h>
 #include <dt-bindings/reset/imx7-reset.h>
+#include <dt-bindings/reset/imx8mq-reset.h>
+
+struct imx7_src_signal {
+        unsigned int offset, bit;
+};
+
+struct imx7_src_variant {
+        const struct imx7_src_signal *signals;
+        unsigned int signals_num;
+        struct reset_control_ops ops;
+};
 
 struct imx7_src {
         struct reset_controller_dev rcdev;
         struct regmap *regmap;
+        const struct imx7_src_signal *signals;
 };
 
 enum imx7_src_registers {
@@ -39,9 +52,14 @@ enum imx7_src_registers {
         SRC_DDRC_RCR            = 0x1000,
 };
 
-struct imx7_src_signal {
-        unsigned int offset, bit;
-};
+static int imx7_reset_update(struct imx7_src *imx7src,
+                             unsigned long id, unsigned int value)
+{
+        const struct imx7_src_signal *signal = &imx7src->signals[id];
+
+        return regmap_update_bits(imx7src->regmap,
+                                  signal->offset, signal->bit, value);
+}
 
 static const struct imx7_src_signal imx7_src_signals[IMX7_RESET_NUM] = {
         [IMX7_RESET_A7_CORE_POR_RESET0] = { SRC_A7RCR0, BIT(0) },
@@ -81,8 +99,8 @@ static int imx7_reset_set(struct reset_controller_dev *rcdev,
                           unsigned long id, bool assert)
 {
         struct imx7_src *imx7src = to_imx7_src(rcdev);
-        const struct imx7_src_signal *signal = &imx7_src_signals[id];
-        unsigned int value = assert ? signal->bit : 0;
+        const unsigned int bit = imx7src->signals[id].bit;
+        unsigned int value = assert ? bit : 0;
 
         switch (id) {
         case IMX7_RESET_PCIEPHY:
@@ -95,12 +113,11 @@ static int imx7_reset_set(struct reset_controller_dev *rcdev,
                 break;
 
         case IMX7_RESET_PCIE_CTRL_APPS_EN:
-                value = (assert) ? 0 : signal->bit;
+                value = assert ? 0 : bit;
                 break;
         }
 
-        return regmap_update_bits(imx7src->regmap,
-                                  signal->offset, signal->bit, value);
+        return imx7_reset_update(imx7src, id, value);
 }
 
 static int imx7_reset_assert(struct reset_controller_dev *rcdev,
@@ -115,9 +132,133 @@ static int imx7_reset_deassert(struct reset_controller_dev *rcdev,
         return imx7_reset_set(rcdev, id, false);
 }
 
-static const struct reset_control_ops imx7_reset_ops = {
-        .assert         = imx7_reset_assert,
-        .deassert       = imx7_reset_deassert,
+static const struct imx7_src_variant variant_imx7 = {
+        .signals = imx7_src_signals,
+        .signals_num = ARRAY_SIZE(imx7_src_signals),
+        .ops = {
+                .assert   = imx7_reset_assert,
+                .deassert = imx7_reset_deassert,
+        },
+};
+
+enum imx8mq_src_registers {
+        SRC_A53RCR0             = 0x0004,
+        SRC_HDMI_RCR            = 0x0030,
+        SRC_DISP_RCR            = 0x0034,
+        SRC_GPU_RCR             = 0x0040,
+        SRC_VPU_RCR             = 0x0044,
+        SRC_PCIE2_RCR           = 0x0048,
+        SRC_MIPIPHY1_RCR        = 0x004c,
+        SRC_MIPIPHY2_RCR        = 0x0050,
+        SRC_DDRC2_RCR           = 0x1004,
+};
+
+static const struct imx7_src_signal imx8mq_src_signals[IMX8MQ_RESET_NUM] = {
+        [IMX8MQ_RESET_A53_CORE_POR_RESET0]      = { SRC_A53RCR0, BIT(0) },
+        [IMX8MQ_RESET_A53_CORE_POR_RESET1]      = { SRC_A53RCR0, BIT(1) },
+        [IMX8MQ_RESET_A53_CORE_POR_RESET2]      = { SRC_A53RCR0, BIT(2) },
+        [IMX8MQ_RESET_A53_CORE_POR_RESET3]      = { SRC_A53RCR0, BIT(3) },
+        [IMX8MQ_RESET_A53_CORE_RESET0]          = { SRC_A53RCR0, BIT(4) },
+        [IMX8MQ_RESET_A53_CORE_RESET1]          = { SRC_A53RCR0, BIT(5) },
+        [IMX8MQ_RESET_A53_CORE_RESET2]          = { SRC_A53RCR0, BIT(6) },
+        [IMX8MQ_RESET_A53_CORE_RESET3]          = { SRC_A53RCR0, BIT(7) },
+        [IMX8MQ_RESET_A53_DBG_RESET0]           = { SRC_A53RCR0, BIT(8) },
+        [IMX8MQ_RESET_A53_DBG_RESET1]           = { SRC_A53RCR0, BIT(9) },
+        [IMX8MQ_RESET_A53_DBG_RESET2]           = { SRC_A53RCR0, BIT(10) },
+        [IMX8MQ_RESET_A53_DBG_RESET3]           = { SRC_A53RCR0, BIT(11) },
+        [IMX8MQ_RESET_A53_ETM_RESET0]           = { SRC_A53RCR0, BIT(12) },
+        [IMX8MQ_RESET_A53_ETM_RESET1]           = { SRC_A53RCR0, BIT(13) },
+        [IMX8MQ_RESET_A53_ETM_RESET2]           = { SRC_A53RCR0, BIT(14) },
+        [IMX8MQ_RESET_A53_ETM_RESET3]           = { SRC_A53RCR0, BIT(15) },
+        [IMX8MQ_RESET_A53_SOC_DBG_RESET]        = { SRC_A53RCR0, BIT(20) },
+        [IMX8MQ_RESET_A53_L2RESET]              = { SRC_A53RCR0, BIT(21) },
+        [IMX8MQ_RESET_SW_NON_SCLR_M4C_RST]      = { SRC_M4RCR, BIT(0) },
+        [IMX8MQ_RESET_OTG1_PHY_RESET]           = { SRC_USBOPHY1_RCR, BIT(0) },
+        [IMX8MQ_RESET_OTG2_PHY_RESET]           = { SRC_USBOPHY2_RCR, BIT(0) },
+        [IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N]    = { SRC_MIPIPHY_RCR, BIT(1) },
+        [IMX8MQ_RESET_MIPI_DSI_RESET_N]         = { SRC_MIPIPHY_RCR, BIT(2) },
+        [IMX8MQ_RESET_MIPI_DIS_DPI_RESET_N]     = { SRC_MIPIPHY_RCR, BIT(3) },
+        [IMX8MQ_RESET_MIPI_DIS_ESC_RESET_N]     = { SRC_MIPIPHY_RCR, BIT(4) },
+        [IMX8MQ_RESET_MIPI_DIS_PCLK_RESET_N]    = { SRC_MIPIPHY_RCR, BIT(5) },
+        [IMX8MQ_RESET_PCIEPHY]                  = { SRC_PCIEPHY_RCR,
+                                                    BIT(2) | BIT(1) },
+        [IMX8MQ_RESET_PCIEPHY_PERST]            = { SRC_PCIEPHY_RCR, BIT(3) },
+        [IMX8MQ_RESET_PCIE_CTRL_APPS_EN]        = { SRC_PCIEPHY_RCR, BIT(6) },
+        [IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF]   = { SRC_PCIEPHY_RCR, BIT(11) },
+        [IMX8MQ_RESET_HDMI_PHY_APB_RESET]       = { SRC_HDMI_RCR, BIT(0) },
+        [IMX8MQ_RESET_DISP_RESET]               = { SRC_DISP_RCR, BIT(0) },
+        [IMX8MQ_RESET_GPU_RESET]                = { SRC_GPU_RCR, BIT(0) },
+        [IMX8MQ_RESET_VPU_RESET]                = { SRC_VPU_RCR, BIT(0) },
+        [IMX8MQ_RESET_PCIEPHY2]                 = { SRC_PCIE2_RCR,
+                                                    BIT(2) | BIT(1) },
+        [IMX8MQ_RESET_PCIEPHY2_PERST]           = { SRC_PCIE2_RCR, BIT(3) },
+        [IMX8MQ_RESET_PCIE2_CTRL_APPS_EN]       = { SRC_PCIE2_RCR, BIT(6) },
+        [IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF]  = { SRC_PCIE2_RCR, BIT(11) },
+        [IMX8MQ_RESET_MIPI_CSI1_CORE_RESET]     = { SRC_MIPIPHY1_RCR, BIT(0) },
+        [IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET]  = { SRC_MIPIPHY1_RCR, BIT(1) },
+        [IMX8MQ_RESET_MIPI_CSI1_ESC_RESET]      = { SRC_MIPIPHY1_RCR, BIT(2) },
+        [IMX8MQ_RESET_MIPI_CSI2_CORE_RESET]     = { SRC_MIPIPHY2_RCR, BIT(0) },
+        [IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET]  = { SRC_MIPIPHY2_RCR, BIT(1) },
+        [IMX8MQ_RESET_MIPI_CSI2_ESC_RESET]      = { SRC_MIPIPHY2_RCR, BIT(2) },
+        [IMX8MQ_RESET_DDRC1_PRST]               = { SRC_DDRC_RCR, BIT(0) },
+        [IMX8MQ_RESET_DDRC1_CORE_RESET]         = { SRC_DDRC_RCR, BIT(1) },
+        [IMX8MQ_RESET_DDRC1_PHY_RESET]          = { SRC_DDRC_RCR, BIT(2) },
+        [IMX8MQ_RESET_DDRC2_PHY_RESET]          = { SRC_DDRC2_RCR, BIT(0) },
+        [IMX8MQ_RESET_DDRC2_CORE_RESET]         = { SRC_DDRC2_RCR, BIT(1) },
+        [IMX8MQ_RESET_DDRC2_PRST]               = { SRC_DDRC2_RCR, BIT(2) },
+};
+
+static int imx8mq_reset_set(struct reset_controller_dev *rcdev,
+                            unsigned long id, bool assert)
+{
+        struct imx7_src *imx7src = to_imx7_src(rcdev);
+        const unsigned int bit = imx7src->signals[id].bit;
+        unsigned int value = assert ? bit : 0;
+
+        switch (id) {
+        case IMX8MQ_RESET_PCIEPHY:
+        case IMX8MQ_RESET_PCIEPHY2: /* fallthrough */
+                /*
+                 * wait for more than 10us to release phy g_rst and
+                 * btnrst
+                 */
+                if (!assert)
+                        udelay(10);
+                break;
+
+        case IMX8MQ_RESET_PCIE_CTRL_APPS_EN:
+        case IMX8MQ_RESET_PCIE2_CTRL_APPS_EN:   /* fallthrough */
+        case IMX8MQ_RESET_MIPI_DIS_PCLK_RESET_N:        /* fallthrough */
+        case IMX8MQ_RESET_MIPI_DIS_ESC_RESET_N: /* fallthrough */
+        case IMX8MQ_RESET_MIPI_DIS_DPI_RESET_N: /* fallthrough */
+        case IMX8MQ_RESET_MIPI_DSI_RESET_N:     /* fallthrough */
+        case IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N:        /* fallthrough */
+                value = assert ? 0 : bit;
+                break;
+        }
+
+        return imx7_reset_update(imx7src, id, value);
+}
+
+static int imx8mq_reset_assert(struct reset_controller_dev *rcdev,
+                               unsigned long id)
+{
+        return imx8mq_reset_set(rcdev, id, true);
+}
+
+static int imx8mq_reset_deassert(struct reset_controller_dev *rcdev,
+                                 unsigned long id)
+{
+        return imx8mq_reset_set(rcdev, id, false);
+}
+
+static const struct imx7_src_variant variant_imx8mq = {
+        .signals = imx8mq_src_signals,
+        .signals_num = ARRAY_SIZE(imx8mq_src_signals),
+        .ops = {
+                .assert   = imx8mq_reset_assert,
+                .deassert = imx8mq_reset_deassert,
+        },
 };
 
 static int imx7_reset_probe(struct platform_device *pdev)
@@ -125,11 +266,13 @@ static int imx7_reset_probe(struct platform_device *pdev)
         struct imx7_src *imx7src;
         struct device *dev = &pdev->dev;
         struct regmap_config config = { .name = "src" };
+        const struct imx7_src_variant *variant = of_device_get_match_data(dev);
 
         imx7src = devm_kzalloc(dev, sizeof(*imx7src), GFP_KERNEL);
         if (!imx7src)
                 return -ENOMEM;
 
+        imx7src->signals = variant->signals;
         imx7src->regmap = syscon_node_to_regmap(dev->of_node);
         if (IS_ERR(imx7src->regmap)) {
                 dev_err(dev, "Unable to get imx7-src regmap");
@@ -138,15 +281,16 @@ static int imx7_reset_probe(struct platform_device *pdev)
         regmap_attach_dev(dev, imx7src->regmap, &config);
 
         imx7src->rcdev.owner     = THIS_MODULE;
-        imx7src->rcdev.nr_resets = IMX7_RESET_NUM;
-        imx7src->rcdev.ops       = &imx7_reset_ops;
+        imx7src->rcdev.nr_resets = variant->signals_num;
+        imx7src->rcdev.ops       = &variant->ops;
         imx7src->rcdev.of_node   = dev->of_node;
 
         return devm_reset_controller_register(dev, &imx7src->rcdev);
 }
 
 static const struct of_device_id imx7_reset_dt_ids[] = {
-        { .compatible = "fsl,imx7d-src", },
+        { .compatible = "fsl,imx7d-src", .data = &variant_imx7 },
+        { .compatible = "fsl,imx8mq-src", .data = &variant_imx8mq },
         { /* sentinel */ },
 };
 
diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
index 318cfc51c441..96953992c2bb 100644
--- a/drivers/reset/reset-socfpga.c
+++ b/drivers/reset/reset-socfpga.c
@@ -11,6 +11,7 @@
 #include <linux/of_address.h>
 #include <linux/platform_device.h>
 #include <linux/reset-controller.h>
+#include <linux/reset/socfpga.h>
 #include <linux/slab.h>
 #include <linux/spinlock.h>
 #include <linux/types.h>
@@ -18,7 +19,6 @@
 #include "reset-simple.h"
 
 #define SOCFPGA_NR_BANKS        8
-void __init socfpga_reset_init(void);
 
 static int a10_reset_init(struct device_node *np)
 {
diff --git a/drivers/reset/reset-sunxi.c b/drivers/reset/reset-sunxi.c
index db9a1a75523f..b06d724d8f21 100644
--- a/drivers/reset/reset-sunxi.c
+++ b/drivers/reset/reset-sunxi.c
@@ -18,6 +18,7 @@
 #include <linux/of_address.h>
 #include <linux/platform_device.h>
 #include <linux/reset-controller.h>
+#include <linux/reset/sunxi.h>
 #include <linux/slab.h>
 #include <linux/spinlock.h>
 #include <linux/types.h>