diff options
author | Bjorn Helgaas <bhelgaas@google.com> | 2018-08-15 15:59:06 -0400 |
---|---|---|
committer | Bjorn Helgaas <bhelgaas@google.com> | 2018-08-15 15:59:06 -0400 |
commit | 3a48dc6fc260c9cac302a9ffaeab95359431c485 (patch) | |
tree | 7dc85ea850ef81c756b55e2bdec5b7b6146f535e /drivers/pci/pcie/aer.c | |
parent | e7aaf90f9d9dbbba54f67c653a1c56c2bf117268 (diff) | |
parent | 7695e73f3db4576ef3ce05063c28e9a673425763 (diff) |
Merge branch 'pci/virtualization'
- To avoid bus errors, enable PASID only if entire path supports End-End
TLP prefixes (Sinan Kaya)
- Unify slot and bus reset functions and remove hotplug knowledge from
callers (Sinan Kaya)
- Add Function-Level Reset quirks for Intel and Samsung NVMe devices to
fix guest reboot issues (Alex Williamson)
- Add function 1 DMA alias quirk for Marvell 88SS9183 PCIe SSD Controller
(Bjorn Helgaas)
* pci/virtualization:
PCI: Add function 1 DMA alias quirk for Marvell 88SS9183
PCI: Delay after FLR of Intel DC P3700 NVMe
PCI: Disable Samsung SM961/PM961 NVMe before FLR
PCI: Export pcie_has_flr()
PCI: Rename pci_try_reset_bus() to pci_reset_bus()
PCI: Deprecate pci_reset_bus() and pci_reset_slot() functions
PCI: Unify try slot and bus reset API
PCI: Hide pci_reset_bridge_secondary_bus() from drivers
IB/hfi1: Use pci_try_reset_bus() for initiating PCI Secondary Bus Reset
PCI: Handle error return from pci_reset_bridge_secondary_bus()
PCI/IOV: Tidy pci_sriov_set_totalvfs()
PCI: Enable PASID only if entire path supports End-End TLP prefixes
# Conflicts:
# drivers/pci/hotplug/pciehp_hpc.c
Diffstat (limited to 'drivers/pci/pcie/aer.c')
-rw-r--r-- | drivers/pci/pcie/aer.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 4e823ae051a7..83180edd6ed4 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c | |||
@@ -1517,6 +1517,7 @@ static pci_ers_result_t aer_root_reset(struct pci_dev *dev) | |||
1517 | { | 1517 | { |
1518 | u32 reg32; | 1518 | u32 reg32; |
1519 | int pos; | 1519 | int pos; |
1520 | int rc; | ||
1520 | 1521 | ||
1521 | pos = dev->aer_cap; | 1522 | pos = dev->aer_cap; |
1522 | 1523 | ||
@@ -1525,7 +1526,7 @@ static pci_ers_result_t aer_root_reset(struct pci_dev *dev) | |||
1525 | reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK; | 1526 | reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK; |
1526 | pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, reg32); | 1527 | pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, reg32); |
1527 | 1528 | ||
1528 | pci_reset_bridge_secondary_bus(dev); | 1529 | rc = pci_bridge_secondary_bus_reset(dev); |
1529 | pci_printk(KERN_DEBUG, dev, "Root Port link has been reset\n"); | 1530 | pci_printk(KERN_DEBUG, dev, "Root Port link has been reset\n"); |
1530 | 1531 | ||
1531 | /* Clear Root Error Status */ | 1532 | /* Clear Root Error Status */ |
@@ -1537,7 +1538,7 @@ static pci_ers_result_t aer_root_reset(struct pci_dev *dev) | |||
1537 | reg32 |= ROOT_PORT_INTR_ON_MESG_MASK; | 1538 | reg32 |= ROOT_PORT_INTR_ON_MESG_MASK; |
1538 | pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, reg32); | 1539 | pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, reg32); |
1539 | 1540 | ||
1540 | return PCI_ERS_RESULT_RECOVERED; | 1541 | return rc ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; |
1541 | } | 1542 | } |
1542 | 1543 | ||
1543 | /** | 1544 | /** |